arch/arm64/include/asm/kvm_arm.h
296
#define __HCRX_EL2_MASK (BIT_ULL(6))
arch/arm64/include/asm/sysreg.h
1059
#define GICV5_GIC_CDAFF_IRM_MASK BIT_ULL(28)
arch/arm64/include/asm/sysreg.h
1077
#define GICV5_GIC_CDHM_HM_MASK BIT_ULL(32)
arch/arm64/include/asm/sysreg.h
1082
#define GICV5_GIC_CDPEND_PENDING_MASK BIT_ULL(32)
arch/arm64/include/asm/sysreg.h
1096
#define GICV5_GIC_CDIA_VALID_MASK BIT_ULL(32)
arch/arm64/include/asm/virt.h
62
#define BOOT_CPU_FLAG_E2H BIT_ULL(32)
arch/arm64/kvm/arm.c
848
nr_entries = BIT_ULL(hweight_long(mask));
arch/arm64/kvm/hyp/nvhe/pkvm.c
345
hyp_vm->kvm.arch.flags &= ~BIT_ULL(KVM_ARCH_FLAG_ID_REGS_INITIALIZED);
arch/arm64/kvm/mmu.c
2078
if (fault_ipa >= BIT_ULL(get_kvm_ipa_limit())) {
arch/arm64/kvm/mmu.c
2084
if (fault_ipa >= BIT_ULL(VTCR_EL2_IPA(vcpu->arch.hw_mmu->vtcr))) {
arch/arm64/kvm/pmu-emul.c
873
val &= ~(BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT - 32) |
arch/arm64/kvm/pmu-emul.c
874
BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND - 32) |
arch/arm64/kvm/pmu-emul.c
875
BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND - 32));
arch/arm64/kvm/sys_regs.c
3942
limit = BIT_ULL(kvm_get_pa_bits(vcpu->kvm));
arch/arm64/kvm/vgic/vgic-debug.c
463
dev->device_id, BIT_ULL(dev->num_eventid_bits) - 1);
arch/arm64/kvm/vgic/vgic-its.c
2156
if (event_id + offset >= BIT_ULL(dev->num_eventid_bits))
arch/arm64/kvm/vgic/vgic-its.c
2238
size_t max_size = BIT_ULL(dev->num_eventid_bits) * ite_esz;
arch/arm64/kvm/vgic/vgic-its.c
771
return (le64_to_cpu(its_cmd[word]) >> shift) & (BIT_ULL(size) - 1);
arch/arm64/kvm/vgic/vgic-its.c
883
if (id >= BIT_ULL(16))
arch/arm64/kvm/vgic/vgic-its.c
918
if (!(indirect_ptr & BIT_ULL(63)))
arch/arm64/kvm/vgic/vgic-its.c
946
if (event_id >= BIT_ULL(device->num_eventid_bits))
arch/arm64/kvm/vgic/vgic-mmio-v3.c
1113
if (unlikely(reg & BIT_ULL(ICC_SGI1R_IRQ_ROUTING_MODE_BIT))) {
arch/arm64/kvm/vgic/vgic-mmio-v3.c
443
(BIT_ULL(63) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) | \
arch/arm64/kvm/vgic/vgic.h
104
#define KVM_ITS_L1E_VALID_MASK BIT_ULL(63)
arch/arm64/kvm/vgic/vgic.h
90
#define KVM_ITS_CTE_VALID_MASK BIT_ULL(63)
arch/arm64/kvm/vgic/vgic.h
98
#define KVM_ITS_DTE_VALID_MASK BIT_ULL(63)
arch/csky/kernel/perf_event.c
1308
csky_pmu.max_period = BIT_ULL(csky_pmu.count_width) - 1;
arch/loongarch/include/asm/cpu-features.h
16
#define cpu_has(feat) (cpu_data[0].options & BIT_ULL(feat))
arch/loongarch/include/asm/cpu.h
130
#define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG)
arch/loongarch/include/asm/cpu.h
131
#define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM)
arch/loongarch/include/asm/cpu.h
132
#define LOONGARCH_CPU_SCQ BIT_ULL(CPU_FEATURE_SCQ)
arch/loongarch/include/asm/cpu.h
133
#define LOONGARCH_CPU_UAL BIT_ULL(CPU_FEATURE_UAL)
arch/loongarch/include/asm/cpu.h
134
#define LOONGARCH_CPU_FPU BIT_ULL(CPU_FEATURE_FPU)
arch/loongarch/include/asm/cpu.h
135
#define LOONGARCH_CPU_LSX BIT_ULL(CPU_FEATURE_LSX)
arch/loongarch/include/asm/cpu.h
136
#define LOONGARCH_CPU_LASX BIT_ULL(CPU_FEATURE_LASX)
arch/loongarch/include/asm/cpu.h
137
#define LOONGARCH_CPU_CRC32 BIT_ULL(CPU_FEATURE_CRC32)
arch/loongarch/include/asm/cpu.h
138
#define LOONGARCH_CPU_COMPLEX BIT_ULL(CPU_FEATURE_COMPLEX)
arch/loongarch/include/asm/cpu.h
139
#define LOONGARCH_CPU_CRYPTO BIT_ULL(CPU_FEATURE_CRYPTO)
arch/loongarch/include/asm/cpu.h
140
#define LOONGARCH_CPU_LVZ BIT_ULL(CPU_FEATURE_LVZ)
arch/loongarch/include/asm/cpu.h
141
#define LOONGARCH_CPU_LBT_X86 BIT_ULL(CPU_FEATURE_LBT_X86)
arch/loongarch/include/asm/cpu.h
142
#define LOONGARCH_CPU_LBT_ARM BIT_ULL(CPU_FEATURE_LBT_ARM)
arch/loongarch/include/asm/cpu.h
143
#define LOONGARCH_CPU_LBT_MIPS BIT_ULL(CPU_FEATURE_LBT_MIPS)
arch/loongarch/include/asm/cpu.h
144
#define LOONGARCH_CPU_TLB BIT_ULL(CPU_FEATURE_TLB)
arch/loongarch/include/asm/cpu.h
145
#define LOONGARCH_CPU_IOCSR BIT_ULL(CPU_FEATURE_IOCSR)
arch/loongarch/include/asm/cpu.h
146
#define LOONGARCH_CPU_CSR BIT_ULL(CPU_FEATURE_CSR)
arch/loongarch/include/asm/cpu.h
147
#define LOONGARCH_CPU_WATCH BIT_ULL(CPU_FEATURE_WATCH)
arch/loongarch/include/asm/cpu.h
148
#define LOONGARCH_CPU_VINT BIT_ULL(CPU_FEATURE_VINT)
arch/loongarch/include/asm/cpu.h
149
#define LOONGARCH_CPU_CSRIPI BIT_ULL(CPU_FEATURE_CSRIPI)
arch/loongarch/include/asm/cpu.h
150
#define LOONGARCH_CPU_EXTIOI BIT_ULL(CPU_FEATURE_EXTIOI)
arch/loongarch/include/asm/cpu.h
151
#define LOONGARCH_CPU_PREFETCH BIT_ULL(CPU_FEATURE_PREFETCH)
arch/loongarch/include/asm/cpu.h
152
#define LOONGARCH_CPU_PMP BIT_ULL(CPU_FEATURE_PMP)
arch/loongarch/include/asm/cpu.h
153
#define LOONGARCH_CPU_SCALEFREQ BIT_ULL(CPU_FEATURE_SCALEFREQ)
arch/loongarch/include/asm/cpu.h
154
#define LOONGARCH_CPU_FLATMODE BIT_ULL(CPU_FEATURE_FLATMODE)
arch/loongarch/include/asm/cpu.h
155
#define LOONGARCH_CPU_EIODECODE BIT_ULL(CPU_FEATURE_EIODECODE)
arch/loongarch/include/asm/cpu.h
156
#define LOONGARCH_CPU_GUESTID BIT_ULL(CPU_FEATURE_GUESTID)
arch/loongarch/include/asm/cpu.h
157
#define LOONGARCH_CPU_HYPERVISOR BIT_ULL(CPU_FEATURE_HYPERVISOR)
arch/loongarch/include/asm/cpu.h
158
#define LOONGARCH_CPU_PTW BIT_ULL(CPU_FEATURE_PTW)
arch/loongarch/include/asm/cpu.h
159
#define LOONGARCH_CPU_LSPW BIT_ULL(CPU_FEATURE_LSPW)
arch/loongarch/include/asm/cpu.h
160
#define LOONGARCH_CPU_MSGINT BIT_ULL(CPU_FEATURE_MSGINT)
arch/loongarch/include/asm/cpu.h
161
#define LOONGARCH_CPU_AVECINT BIT_ULL(CPU_FEATURE_AVECINT)
arch/loongarch/include/asm/cpu.h
162
#define LOONGARCH_CPU_REDIRECTINT BIT_ULL(CPU_FEATURE_REDIRECTINT)
arch/loongarch/include/asm/kvm_host.h
166
#define LOONGARCH_PV_FEAT_UPDATED BIT_ULL(63)
arch/loongarch/include/asm/kvm_host.h
310
return !!(arch->kvm_features & BIT_ULL(feature));
arch/loongarch/include/asm/kvm_para.h
33
#define KVM_STEAL_PHYS_VALID BIT_ULL(0)
arch/loongarch/include/asm/loongarch.h
1171
#define IOCSRF_TEMP BIT_ULL(0)
arch/loongarch/include/asm/loongarch.h
1172
#define IOCSRF_NODECNT BIT_ULL(1)
arch/loongarch/include/asm/loongarch.h
1173
#define IOCSRF_MSI BIT_ULL(2)
arch/loongarch/include/asm/loongarch.h
1174
#define IOCSRF_EXTIOI BIT_ULL(3)
arch/loongarch/include/asm/loongarch.h
1175
#define IOCSRF_CSRIPI BIT_ULL(4)
arch/loongarch/include/asm/loongarch.h
1176
#define IOCSRF_FREQCSR BIT_ULL(5)
arch/loongarch/include/asm/loongarch.h
1177
#define IOCSRF_FREQSCALE BIT_ULL(6)
arch/loongarch/include/asm/loongarch.h
1178
#define IOCSRF_DVFSV1 BIT_ULL(7)
arch/loongarch/include/asm/loongarch.h
1179
#define IOCSRF_EIODECODE BIT_ULL(9)
arch/loongarch/include/asm/loongarch.h
1180
#define IOCSRF_FLATMODE BIT_ULL(10)
arch/loongarch/include/asm/loongarch.h
1181
#define IOCSRF_VM BIT_ULL(11)
arch/loongarch/include/asm/loongarch.h
1182
#define IOCSRF_AVEC BIT_ULL(15)
arch/loongarch/include/asm/loongarch.h
1183
#define IOCSRF_REDIRECT BIT_ULL(16)
arch/loongarch/include/asm/loongarch.h
1192
#define IOCSR_MISC_FUNC_SOFT_INT BIT_ULL(10)
arch/loongarch/include/asm/loongarch.h
1193
#define IOCSR_MISC_FUNC_TIMER_RESET BIT_ULL(21)
arch/loongarch/include/asm/loongarch.h
1194
#define IOCSR_MISC_FUNC_EXT_IOI_EN BIT_ULL(48)
arch/loongarch/include/asm/loongarch.h
1195
#define IOCSR_MISC_FUNC_AVEC_EN BIT_ULL(51)
arch/loongarch/include/asm/loongarch.h
1217
#define IOCSR_MBUF_SEND_BLOCKING BIT_ULL(31)
arch/loongarch/include/asm/loongarch.h
1226
#define IOCSR_ANY_SEND_BLOCKING BIT_ULL(31)
arch/loongarch/kvm/intc/eiointc.c
245
data &= ~BIT_ULL(irq);
arch/loongarch/kvm/intc/eiointc.c
255
data &= ~BIT_ULL(irq);
arch/loongarch/kvm/intc/eiointc.c
275
data &= ~BIT_ULL(irq);
arch/mips/include/asm/cpu.h
359
#define MIPS_CPU_TLB BIT_ULL( 0) /* CPU has TLB */
arch/mips/include/asm/cpu.h
360
#define MIPS_CPU_4KEX BIT_ULL( 1) /* "R4K" exception model */
arch/mips/include/asm/cpu.h
361
#define MIPS_CPU_3K_CACHE BIT_ULL( 2) /* R3000-style caches */
arch/mips/include/asm/cpu.h
362
#define MIPS_CPU_4K_CACHE BIT_ULL( 3) /* R4000-style caches */
arch/mips/include/asm/cpu.h
363
#define MIPS_CPU_FPU BIT_ULL( 5) /* CPU has FPU */
arch/mips/include/asm/cpu.h
364
#define MIPS_CPU_32FPR BIT_ULL( 6) /* 32 dbl. prec. FP registers */
arch/mips/include/asm/cpu.h
365
#define MIPS_CPU_COUNTER BIT_ULL( 7) /* Cycle count/compare */
arch/mips/include/asm/cpu.h
366
#define MIPS_CPU_WATCH BIT_ULL( 8) /* watchpoint registers */
arch/mips/include/asm/cpu.h
367
#define MIPS_CPU_DIVEC BIT_ULL( 9) /* dedicated interrupt vector */
arch/mips/include/asm/cpu.h
368
#define MIPS_CPU_VCE BIT_ULL(10) /* virt. coherence conflict possible */
arch/mips/include/asm/cpu.h
369
#define MIPS_CPU_CACHE_CDEX_P BIT_ULL(11) /* Create_Dirty_Exclusive CACHE op */
arch/mips/include/asm/cpu.h
370
#define MIPS_CPU_CACHE_CDEX_S BIT_ULL(12) /* ... same for seconary cache ... */
arch/mips/include/asm/cpu.h
371
#define MIPS_CPU_MCHECK BIT_ULL(13) /* Machine check exception */
arch/mips/include/asm/cpu.h
372
#define MIPS_CPU_EJTAG BIT_ULL(14) /* EJTAG exception */
arch/mips/include/asm/cpu.h
373
#define MIPS_CPU_NOFPUEX BIT_ULL(15) /* no FPU exception */
arch/mips/include/asm/cpu.h
374
#define MIPS_CPU_LLSC BIT_ULL(16) /* CPU has ll/sc instructions */
arch/mips/include/asm/cpu.h
375
#define MIPS_CPU_INCLUSIVE_CACHES BIT_ULL(17) /* P-cache subset enforced */
arch/mips/include/asm/cpu.h
376
#define MIPS_CPU_PREFETCH BIT_ULL(18) /* CPU has usable prefetch */
arch/mips/include/asm/cpu.h
377
#define MIPS_CPU_VINT BIT_ULL(19) /* CPU supports MIPSR2 vectored interrupts */
arch/mips/include/asm/cpu.h
378
#define MIPS_CPU_VEIC BIT_ULL(20) /* CPU supports MIPSR2 external interrupt controller mode */
arch/mips/include/asm/cpu.h
379
#define MIPS_CPU_ULRI BIT_ULL(21) /* CPU has ULRI feature */
arch/mips/include/asm/cpu.h
380
#define MIPS_CPU_PCI BIT_ULL(22) /* CPU has Perf Ctr Int indicator */
arch/mips/include/asm/cpu.h
381
#define MIPS_CPU_RIXI BIT_ULL(23) /* CPU has TLB Read/eXec Inhibit */
arch/mips/include/asm/cpu.h
382
#define MIPS_CPU_MICROMIPS BIT_ULL(24) /* CPU has microMIPS capability */
arch/mips/include/asm/cpu.h
383
#define MIPS_CPU_TLBINV BIT_ULL(25) /* CPU supports TLBINV/F */
arch/mips/include/asm/cpu.h
384
#define MIPS_CPU_SEGMENTS BIT_ULL(26) /* CPU supports Segmentation Control registers */
arch/mips/include/asm/cpu.h
385
#define MIPS_CPU_EVA BIT_ULL(27) /* CPU supports Enhanced Virtual Addressing */
arch/mips/include/asm/cpu.h
386
#define MIPS_CPU_HTW BIT_ULL(28) /* CPU support Hardware Page Table Walker */
arch/mips/include/asm/cpu.h
387
#define MIPS_CPU_RIXIEX BIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
arch/mips/include/asm/cpu.h
388
#define MIPS_CPU_MAAR BIT_ULL(30) /* MAAR(I) registers are present */
arch/mips/include/asm/cpu.h
389
#define MIPS_CPU_FRE BIT_ULL(31) /* FRE & UFE bits implemented */
arch/mips/include/asm/cpu.h
390
#define MIPS_CPU_RW_LLB BIT_ULL(32) /* LLADDR/LLB writes are allowed */
arch/mips/include/asm/cpu.h
391
#define MIPS_CPU_LPA BIT_ULL(33) /* CPU supports Large Physical Addressing */
arch/mips/include/asm/cpu.h
392
#define MIPS_CPU_CDMM BIT_ULL(34) /* CPU has Common Device Memory Map */
arch/mips/include/asm/cpu.h
393
#define MIPS_CPU_SP BIT_ULL(36) /* Small (1KB) page support */
arch/mips/include/asm/cpu.h
394
#define MIPS_CPU_FTLB BIT_ULL(37) /* CPU has Fixed-page-size TLB */
arch/mips/include/asm/cpu.h
395
#define MIPS_CPU_NAN_LEGACY BIT_ULL(38) /* Legacy NaN implemented */
arch/mips/include/asm/cpu.h
396
#define MIPS_CPU_NAN_2008 BIT_ULL(39) /* 2008 NaN implemented */
arch/mips/include/asm/cpu.h
397
#define MIPS_CPU_VP BIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */
arch/mips/include/asm/cpu.h
398
#define MIPS_CPU_LDPTE BIT_ULL(41) /* CPU has ldpte/lddir instructions */
arch/mips/include/asm/cpu.h
399
#define MIPS_CPU_MVH BIT_ULL(42) /* CPU supports MFHC0/MTHC0 */
arch/mips/include/asm/cpu.h
400
#define MIPS_CPU_EBASE_WG BIT_ULL(43) /* CPU has EBase.WG */
arch/mips/include/asm/cpu.h
401
#define MIPS_CPU_BADINSTR BIT_ULL(44) /* CPU has BadInstr register */
arch/mips/include/asm/cpu.h
402
#define MIPS_CPU_BADINSTRP BIT_ULL(45) /* CPU has BadInstrP register */
arch/mips/include/asm/cpu.h
403
#define MIPS_CPU_CTXTC BIT_ULL(46) /* CPU has [X]ConfigContext registers */
arch/mips/include/asm/cpu.h
404
#define MIPS_CPU_PERF BIT_ULL(47) /* CPU has MIPS performance counters */
arch/mips/include/asm/cpu.h
405
#define MIPS_CPU_GUESTCTL0EXT BIT_ULL(48) /* CPU has VZ GuestCtl0Ext register */
arch/mips/include/asm/cpu.h
406
#define MIPS_CPU_GUESTCTL1 BIT_ULL(49) /* CPU has VZ GuestCtl1 register */
arch/mips/include/asm/cpu.h
407
#define MIPS_CPU_GUESTCTL2 BIT_ULL(50) /* CPU has VZ GuestCtl2 register */
arch/mips/include/asm/cpu.h
408
#define MIPS_CPU_GUESTID BIT_ULL(51) /* CPU uses VZ ASE GuestID feature */
arch/mips/include/asm/cpu.h
409
#define MIPS_CPU_DRG BIT_ULL(52) /* CPU has VZ Direct Root to Guest (DRG) */
arch/mips/include/asm/cpu.h
410
#define MIPS_CPU_UFR BIT_ULL(53) /* CPU supports User mode FR switching */
arch/mips/include/asm/cpu.h
412
BIT_ULL(54) /* CPU shares FTLB RAM with another */
arch/mips/include/asm/cpu.h
414
BIT_ULL(55) /* CPU shares FTLB entries with another */
arch/mips/include/asm/cpu.h
416
BIT_ULL(56) /* CPU has perf counters implemented per TC (MIPSMT ASE) */
arch/mips/include/asm/cpu.h
417
#define MIPS_CPU_MMID BIT_ULL(57) /* CPU supports MemoryMapIDs */
arch/mips/include/asm/cpu.h
418
#define MIPS_CPU_MM_SYSAD BIT_ULL(58) /* CPU supports write-through SysAD Valid merge */
arch/mips/include/asm/cpu.h
419
#define MIPS_CPU_MM_FULL BIT_ULL(59) /* CPU supports write-through full merge */
arch/mips/include/asm/cpu.h
420
#define MIPS_CPU_MAC_2008_ONLY BIT_ULL(60) /* CPU Only support MAC2008 Fused multiply-add instruction */
arch/mips/include/asm/cpu.h
421
#define MIPS_CPU_FTLBPAREX BIT_ULL(61) /* CPU has FTLB parity exception */
arch/mips/include/asm/cpu.h
422
#define MIPS_CPU_GSEXCEX BIT_ULL(62) /* CPU has GSExc exception */
arch/mips/include/asm/mach-loongson64/loongson_regs.h
242
#define CSR_MAIL_SEND_BLOCK BIT_ULL(31)
arch/mips/include/asm/mips-cm.h
166
#define CM_GCR_CONFIG_CLUSTER_COH_CAPABLE BIT_ULL(43)
arch/mips/include/asm/mips-gic.h
145
_val &= ~BIT_ULL(intr % 64); \
arch/mips/sgi-ip27/ip27-memory.c
49
region_mask |= BIT_ULL(nasid >> region_shift);
arch/mips/sgi-ip27/ip27-xtalk.c
85
bd->intr_addr = BIT_ULL(47) + 0x01800000 + PI_INT_PEND_MOD;
arch/mips/sgi-ip30/ip30-irq.c
113
if (pend & BIT_ULL(HEART_L2_INT_RESCHED_CPU_0)) {
arch/mips/sgi-ip30/ip30-irq.c
114
heart_write(BIT_ULL(HEART_L2_INT_RESCHED_CPU_0),
arch/mips/sgi-ip30/ip30-irq.c
117
} else if (pend & BIT_ULL(HEART_L2_INT_RESCHED_CPU_1)) {
arch/mips/sgi-ip30/ip30-irq.c
118
heart_write(BIT_ULL(HEART_L2_INT_RESCHED_CPU_1),
arch/mips/sgi-ip30/ip30-irq.c
121
} else if (pend & BIT_ULL(HEART_L2_INT_CALL_CPU_0)) {
arch/mips/sgi-ip30/ip30-irq.c
122
heart_write(BIT_ULL(HEART_L2_INT_CALL_CPU_0),
arch/mips/sgi-ip30/ip30-irq.c
125
} else if (pend & BIT_ULL(HEART_L2_INT_CALL_CPU_1)) {
arch/mips/sgi-ip30/ip30-irq.c
126
heart_write(BIT_ULL(HEART_L2_INT_CALL_CPU_1),
arch/mips/sgi-ip30/ip30-irq.c
141
heart_write(BIT_ULL(d->hwirq), &heart_regs->clear_isr);
arch/mips/sgi-ip30/ip30-irq.c
160
heart_write(BIT_ULL(d->hwirq), &heart_regs->clear_isr);
arch/mips/sgi-ip30/ip30-irq.c
253
heart_write(BIT_ULL(HEART_L2_INT_RESCHED_CPU_0 + cpu),
arch/mips/sgi-ip30/ip30-irq.c
256
heart_write(BIT_ULL(HEART_L2_INT_CALL_CPU_0 + cpu),
arch/mips/sgi-ip30/ip30-smp.c
64
heart_write(BIT_ULL(irq), &heart_regs->set_isr);
arch/powerpc/platforms/powernv/opal-irqchip.c
52
e &= ~BIT_ULL(hwirq);
arch/powerpc/platforms/pseries/plpks.c
30
BIT_ULL(63 - (be_bit))
arch/riscv/kvm/vcpu_sbi_fwft.c
17
#define MIS_DELEG (BIT_ULL(EXC_LOAD_MISALIGNED) | BIT_ULL(EXC_STORE_MISALIGNED))
arch/um/drivers/vhost_user.h
25
#define VHOST_USER_SUPPORTED_F BIT_ULL(VHOST_USER_F_PROTOCOL_FEATURES)
arch/um/drivers/vhost_user.h
27
#define VHOST_USER_SUPPORTED_PROTOCOL_F (BIT_ULL(VHOST_USER_PROTOCOL_F_MQ) | \
arch/um/drivers/vhost_user.h
28
BIT_ULL(VHOST_USER_PROTOCOL_F_REPLY_ACK) | \
arch/um/drivers/vhost_user.h
29
BIT_ULL(VHOST_USER_PROTOCOL_F_SLAVE_REQ) | \
arch/um/drivers/vhost_user.h
30
BIT_ULL(VHOST_USER_PROTOCOL_F_CONFIG) | \
arch/um/drivers/vhost_user.h
31
BIT_ULL(VHOST_USER_PROTOCOL_F_INBAND_NOTIFICATIONS))
arch/um/drivers/virtio_uml.c
245
BIT_ULL(VHOST_USER_PROTOCOL_F_REPLY_ACK)))
arch/um/drivers/virtio_uml.c
408
vu_dev->vq_irq_vq_map |= BIT_ULL(vq->index);
arch/um/drivers/virtio_uml.c
448
if (vu_dev->vq_irq_vq_map & BIT_ULL(vq->index))
arch/um/drivers/virtio_uml.c
512
if (vu_dev->features & BIT_ULL(VHOST_USER_F_PROTOCOL_FEATURES)) {
arch/um/drivers/virtio_uml.c
525
BIT_ULL(VHOST_USER_PROTOCOL_F_SLAVE_REQ)) {
arch/um/drivers/virtio_uml.c
532
BIT_ULL(VHOST_USER_PROTOCOL_F_MQ)) {
arch/um/drivers/virtio_uml.c
553
BIT_ULL(VHOST_USER_PROTOCOL_F_CONFIG)))
arch/um/drivers/virtio_uml.c
603
BIT_ULL(VHOST_USER_PROTOCOL_F_CONFIG)))
arch/um/drivers/virtio_uml.c
781
if (!(vu_dev->features & BIT_ULL(VHOST_USER_F_PROTOCOL_FEATURES)))
arch/um/drivers/virtio_uml.c
918
BIT_ULL(VHOST_USER_PROTOCOL_F_INBAND_NOTIFICATIONS) &&
arch/um/drivers/virtio_uml.c
920
BIT_ULL(VHOST_USER_PROTOCOL_F_SLAVE_REQ)) {
arch/um/drivers/virtio_uml.c
987
BIT_ULL(VHOST_USER_PROTOCOL_F_INBAND_NOTIFICATIONS)) {
arch/x86/boot/compressed/sev.c
435
sme_me_mask = BIT_ULL(bitpos);
arch/x86/boot/startup/sev-shared.c
237
if (!(xfeatures_en & (BIT_ULL(e->ecx_in))))
arch/x86/boot/startup/sev-shared.c
239
if (xfeatures_found & (BIT_ULL(e->ecx_in)))
arch/x86/boot/startup/sev-shared.c
242
xfeatures_found |= (BIT_ULL(e->ecx_in));
arch/x86/coco/sev/core.c
1421
if (sev_status & BIT_ULL(i)) {
arch/x86/coco/sev/svsm.c
361
return call.rcx_out & BIT_ULL(8);
arch/x86/coco/tdx/tdx.c
352
*cc_mask = BIT_ULL(gpa_width - 1);
arch/x86/events/amd/core.c
1471
even_ctr_mask |= BIT_ULL(i);
arch/x86/events/amd/core.c
686
return !(counter & BIT_ULL(x86_pmu.cntval_bits - 1));
arch/x86/events/amd/core.c
691
return amd_pmu_get_global_status() & BIT_ULL(idx);
arch/x86/events/amd/core.c
998
mask = BIT_ULL(idx);
arch/x86/events/amd/iommu.c
169
if (piommu->cntr_assign_mask & BIT_ULL(shift)) {
arch/x86/events/amd/iommu.c
172
piommu->cntr_assign_mask |= BIT_ULL(shift);
arch/x86/events/amd/lbr.c
293
if (!(br_type & BIT_ULL(i)))
arch/x86/events/amd/uncore.c
977
if (new & BIT_ULL(63 - COUNTER_SHIFT)) {
arch/x86/events/core.c
1066
mask = BIT_ULL(hwc->idx);
arch/x86/events/core.c
878
sched->state.used &= ~BIT_ULL(sched->state.counter);
arch/x86/events/core.c
906
u64 mask = BIT_ULL(idx);
arch/x86/events/core.c
919
u64 mask = BIT_ULL(idx);
arch/x86/events/intel/core.c
1221
#define HSW_DEMAND_DATA_RD BIT_ULL(0)
arch/x86/events/intel/core.c
1222
#define HSW_DEMAND_RFO BIT_ULL(1)
arch/x86/events/intel/core.c
1223
#define HSW_ANY_RESPONSE BIT_ULL(16)
arch/x86/events/intel/core.c
1224
#define HSW_SUPPLIER_NONE BIT_ULL(17)
arch/x86/events/intel/core.c
1225
#define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
arch/x86/events/intel/core.c
1226
#define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
arch/x86/events/intel/core.c
1227
#define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
arch/x86/events/intel/core.c
1228
#define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
arch/x86/events/intel/core.c
1232
#define HSW_SNOOP_NONE BIT_ULL(31)
arch/x86/events/intel/core.c
1233
#define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
arch/x86/events/intel/core.c
1234
#define HSW_SNOOP_MISS BIT_ULL(33)
arch/x86/events/intel/core.c
1235
#define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
arch/x86/events/intel/core.c
1236
#define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
arch/x86/events/intel/core.c
1237
#define HSW_SNOOP_HITM BIT_ULL(36)
arch/x86/events/intel/core.c
1238
#define HSW_SNOOP_NON_DRAM BIT_ULL(37)
arch/x86/events/intel/core.c
2072
#define GLM_DEMAND_DATA_RD BIT_ULL(0)
arch/x86/events/intel/core.c
2073
#define GLM_DEMAND_RFO BIT_ULL(1)
arch/x86/events/intel/core.c
2074
#define GLM_ANY_RESPONSE BIT_ULL(16)
arch/x86/events/intel/core.c
2075
#define GLM_SNP_NONE_OR_MISS BIT_ULL(33)
arch/x86/events/intel/core.c
2313
#define TNT_LOCAL_DRAM BIT_ULL(26)
arch/x86/events/intel/core.c
2451
#define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
arch/x86/events/intel/core.c
2452
#define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
arch/x86/events/intel/core.c
2453
#define KNL_MCDRAM_LOCAL BIT_ULL(21)
arch/x86/events/intel/core.c
2454
#define KNL_MCDRAM_FAR BIT_ULL(22)
arch/x86/events/intel/core.c
2455
#define KNL_DDR_LOCAL BIT_ULL(23)
arch/x86/events/intel/core.c
2456
#define KNL_DDR_FAR BIT_ULL(24)
arch/x86/events/intel/core.c
5235
if (c->idxmsk64 & BIT_ULL(0))
arch/x86/events/intel/core.c
837
#define SKL_DEMAND_DATA_RD BIT_ULL(0)
arch/x86/events/intel/core.c
838
#define SKL_DEMAND_RFO BIT_ULL(1)
arch/x86/events/intel/core.c
839
#define SKL_ANY_RESPONSE BIT_ULL(16)
arch/x86/events/intel/core.c
840
#define SKL_SUPPLIER_NONE BIT_ULL(17)
arch/x86/events/intel/core.c
841
#define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
arch/x86/events/intel/core.c
842
#define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
arch/x86/events/intel/core.c
843
#define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
arch/x86/events/intel/core.c
844
#define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
arch/x86/events/intel/core.c
849
#define SKL_SPL_HIT BIT_ULL(30)
arch/x86/events/intel/core.c
850
#define SKL_SNOOP_NONE BIT_ULL(31)
arch/x86/events/intel/core.c
851
#define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
arch/x86/events/intel/core.c
852
#define SKL_SNOOP_MISS BIT_ULL(33)
arch/x86/events/intel/core.c
853
#define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
arch/x86/events/intel/core.c
854
#define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
arch/x86/events/intel/core.c
855
#define SKL_SNOOP_HITM BIT_ULL(36)
arch/x86/events/intel/core.c
856
#define SKL_SNOOP_NON_DRAM BIT_ULL(37)
arch/x86/events/intel/lbr.c
63
#define LBR_FROM_FLAG_MISPRED BIT_ULL(63)
arch/x86/events/intel/lbr.c
64
#define LBR_FROM_FLAG_IN_TX BIT_ULL(62)
arch/x86/events/intel/lbr.c
65
#define LBR_FROM_FLAG_ABORT BIT_ULL(61)
arch/x86/events/intel/lbr.c
67
#define LBR_FROM_SIGNEXT_2MSB (BIT_ULL(60) | BIT_ULL(59))
arch/x86/events/intel/pt.c
1416
-BIT_ULL(vaddr_bits - 1);
arch/x86/events/intel/pt.c
1424
BIT_ULL(vaddr_bits - 1) - 1;
arch/x86/events/perf_event.h
148
#define PEBS_PMI_AFTER_EACH_RECORD BIT_ULL(60)
arch/x86/hyperv/hv_apic.c
260
status = hv_do_fast_hypercall16(HVCALL_SEND_IPI, vector, BIT_ULL(vp));
arch/x86/include/asm/fpu/types.h
423
#define FPU_GUEST_PERM_LOCKED BIT_ULL(63)
arch/x86/include/asm/kvm_host.h
280
#define PFERR_GUEST_RMP_MASK BIT_ULL(31)
arch/x86/include/asm/kvm_host.h
281
#define PFERR_GUEST_FINAL_MASK BIT_ULL(32)
arch/x86/include/asm/kvm_host.h
282
#define PFERR_GUEST_PAGE_MASK BIT_ULL(33)
arch/x86/include/asm/kvm_host.h
283
#define PFERR_GUEST_ENC_MASK BIT_ULL(34)
arch/x86/include/asm/kvm_host.h
284
#define PFERR_GUEST_SIZEM_MASK BIT_ULL(35)
arch/x86/include/asm/kvm_host.h
285
#define PFERR_GUEST_VMPL_MASK BIT_ULL(36)
arch/x86/include/asm/kvm_host.h
291
#define PFERR_IMPLICIT_ACCESS BIT_ULL(48)
arch/x86/include/asm/kvm_host.h
296
#define PFERR_PRIVATE_ACCESS BIT_ULL(49)
arch/x86/include/asm/mce.h
100
#define MCI_CTL2_CMCI_EN BIT_ULL(30)
arch/x86/include/asm/mce.h
13
#define MCG_CTL_P BIT_ULL(8) /* MCG_CTL register available */
arch/x86/include/asm/mce.h
14
#define MCG_EXT_P BIT_ULL(9) /* Extended registers available */
arch/x86/include/asm/mce.h
147
#define MCE_HANDLED_CEC BIT_ULL(0)
arch/x86/include/asm/mce.h
148
#define MCE_HANDLED_UC BIT_ULL(1)
arch/x86/include/asm/mce.h
149
#define MCE_HANDLED_EXTLOG BIT_ULL(2)
arch/x86/include/asm/mce.h
15
#define MCG_CMCI_P BIT_ULL(10) /* CMCI supported */
arch/x86/include/asm/mce.h
150
#define MCE_HANDLED_NFIT BIT_ULL(3)
arch/x86/include/asm/mce.h
151
#define MCE_HANDLED_EDAC BIT_ULL(4)
arch/x86/include/asm/mce.h
152
#define MCE_HANDLED_MCELOG BIT_ULL(5)
arch/x86/include/asm/mce.h
16
#define MCG_SEAM_NR BIT_ULL(12) /* MCG_STATUS_SEAM_NR supported */
arch/x86/include/asm/mce.h
160
#define MCE_IN_KERNEL_RECOV BIT_ULL(6)
arch/x86/include/asm/mce.h
168
#define MCE_IN_KERNEL_COPYIN BIT_ULL(7)
arch/x86/include/asm/mce.h
174
#define MCE_CHECK_DFR_REGS BIT_ULL(8)
arch/x86/include/asm/mce.h
20
#define MCG_SER_P BIT_ULL(24) /* MCA recovery/new status bits */
arch/x86/include/asm/mce.h
21
#define MCG_ELOG_P BIT_ULL(26) /* Extended error log supported */
arch/x86/include/asm/mce.h
22
#define MCG_LMCE_P BIT_ULL(27) /* Local machine check supported */
arch/x86/include/asm/mce.h
25
#define MCG_STATUS_RIPV BIT_ULL(0) /* restart ip valid */
arch/x86/include/asm/mce.h
26
#define MCG_STATUS_EIPV BIT_ULL(1) /* ip points to correct instruction */
arch/x86/include/asm/mce.h
27
#define MCG_STATUS_MCIP BIT_ULL(2) /* machine check in progress */
arch/x86/include/asm/mce.h
28
#define MCG_STATUS_LMCES BIT_ULL(3) /* LMCE signaled */
arch/x86/include/asm/mce.h
29
#define MCG_STATUS_SEAM_NR BIT_ULL(12) /* Machine check inside SEAM non-root mode */
arch/x86/include/asm/mce.h
32
#define MCG_EXT_CTL_LMCE_EN BIT_ULL(0) /* Enable LMCE */
arch/x86/include/asm/mce.h
35
#define MCI_STATUS_VAL BIT_ULL(63) /* valid error */
arch/x86/include/asm/mce.h
36
#define MCI_STATUS_OVER BIT_ULL(62) /* previous errors lost */
arch/x86/include/asm/mce.h
37
#define MCI_STATUS_UC BIT_ULL(61) /* uncorrected error */
arch/x86/include/asm/mce.h
38
#define MCI_STATUS_EN BIT_ULL(60) /* error enabled */
arch/x86/include/asm/mce.h
39
#define MCI_STATUS_MISCV BIT_ULL(59) /* misc error reg. valid */
arch/x86/include/asm/mce.h
40
#define MCI_STATUS_ADDRV BIT_ULL(58) /* addr reg. valid */
arch/x86/include/asm/mce.h
41
#define MCI_STATUS_PCC BIT_ULL(57) /* processor context corrupt */
arch/x86/include/asm/mce.h
42
#define MCI_STATUS_S BIT_ULL(56) /* Signaled machine check */
arch/x86/include/asm/mce.h
43
#define MCI_STATUS_AR BIT_ULL(55) /* Action required */
arch/x86/include/asm/mce.h
50
#define MCI_STATUS_TCC BIT_ULL(55) /* Task context corrupt */
arch/x86/include/asm/mce.h
51
#define MCI_STATUS_PADDRV BIT_ULL(54) /* Valid System Physical Address */
arch/x86/include/asm/mce.h
52
#define MCI_STATUS_SYNDV BIT_ULL(53) /* synd reg. valid */
arch/x86/include/asm/mce.h
53
#define MCI_STATUS_DEFERRED BIT_ULL(44) /* uncorrected error, deferred exception */
arch/x86/include/asm/mce.h
54
#define MCI_STATUS_POISON BIT_ULL(43) /* access poisonous data */
arch/x86/include/asm/mce.h
55
#define MCI_STATUS_SCRUB BIT_ULL(40) /* Error detected during scrub operation */
arch/x86/include/asm/mce.h
65
#define MCI_CONFIG_FRUTEXT BIT_ULL(9)
arch/x86/include/asm/mce.h
66
#define MCI_CONFIG_PADDRV BIT_ULL(11)
arch/x86/include/asm/msr-index.h
100
#define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
arch/x86/include/asm/msr-index.h
1106
#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT)
arch/x86/include/asm/msr-index.h
1115
#define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT)
arch/x86/include/asm/msr-index.h
1117
#define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT)
arch/x86/include/asm/msr-index.h
1119
#define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT)
arch/x86/include/asm/msr-index.h
218
#define ARCH_CAP_ITS_NO BIT_ULL(62) /*
arch/x86/include/asm/msr-index.h
293
#define LBR_INFO_MISPRED BIT_ULL(63)
arch/x86/include/asm/msr-index.h
294
#define LBR_INFO_IN_TX BIT_ULL(62)
arch/x86/include/asm/msr-index.h
295
#define LBR_INFO_ABORT BIT_ULL(61)
arch/x86/include/asm/msr-index.h
296
#define LBR_INFO_CYC_CNT_VALID BIT_ULL(60)
arch/x86/include/asm/msr-index.h
329
#define PERF_CAP_PEBS_TRAP BIT_ULL(6)
arch/x86/include/asm/msr-index.h
330
#define PERF_CAP_ARCH_REG BIT_ULL(7)
arch/x86/include/asm/msr-index.h
332
#define PERF_CAP_FW_WRITES BIT_ULL(13)
arch/x86/include/asm/msr-index.h
333
#define PERF_CAP_PEBS_BASELINE BIT_ULL(14)
arch/x86/include/asm/msr-index.h
334
#define PERF_CAP_PEBS_TIMING_INFO BIT_ULL(17)
arch/x86/include/asm/msr-index.h
346
#define ARCH_PEBS_CNTR_ALLOW BIT_ULL(35)
arch/x86/include/asm/msr-index.h
347
#define ARCH_PEBS_CNTR_GP BIT_ULL(36)
arch/x86/include/asm/msr-index.h
348
#define ARCH_PEBS_CNTR_FIXED BIT_ULL(37)
arch/x86/include/asm/msr-index.h
349
#define ARCH_PEBS_CNTR_METRICS BIT_ULL(38)
arch/x86/include/asm/msr-index.h
352
#define ARCH_PEBS_VECR_XMM BIT_ULL(49)
arch/x86/include/asm/msr-index.h
353
#define ARCH_PEBS_GPR BIT_ULL(61)
arch/x86/include/asm/msr-index.h
354
#define ARCH_PEBS_AUX BIT_ULL(62)
arch/x86/include/asm/msr-index.h
355
#define ARCH_PEBS_EN BIT_ULL(63)
arch/x86/include/asm/msr-index.h
375
#define RTIT_CTL_NOTNT BIT_ULL(55)
arch/x86/include/asm/msr-index.h
439
#define MSR_IA32_PASID_VALID BIT_ULL(31)
arch/x86/include/asm/msr-index.h
548
#define CET_SHSTK_EN BIT_ULL(0)
arch/x86/include/asm/msr-index.h
549
#define CET_WRSS_EN BIT_ULL(1)
arch/x86/include/asm/msr-index.h
550
#define CET_ENDBR_EN BIT_ULL(2)
arch/x86/include/asm/msr-index.h
551
#define CET_LEG_IW_EN BIT_ULL(3)
arch/x86/include/asm/msr-index.h
552
#define CET_NO_TRACK_EN BIT_ULL(4)
arch/x86/include/asm/msr-index.h
553
#define CET_SUPPRESS_DISABLE BIT_ULL(5)
arch/x86/include/asm/msr-index.h
554
#define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9))
arch/x86/include/asm/msr-index.h
555
#define CET_SUPPRESS BIT_ULL(10)
arch/x86/include/asm/msr-index.h
556
#define CET_WAIT_ENDBR BIT_ULL(11)
arch/x86/include/asm/msr-index.h
671
#define MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT BIT_ULL(MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT_BIT)
arch/x86/include/asm/msr-index.h
679
#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
arch/x86/include/asm/msr-index.h
708
#define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT)
arch/x86/include/asm/msr-index.h
710
#define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT)
arch/x86/include/asm/msr-index.h
712
#define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT)
arch/x86/include/asm/msr-index.h
714
#define MSR_AMD64_SNP_VTOM BIT_ULL(MSR_AMD64_SNP_VTOM_BIT)
arch/x86/include/asm/msr-index.h
716
#define MSR_AMD64_SNP_REFLECT_VC BIT_ULL(MSR_AMD64_SNP_REFLECT_VC_BIT)
arch/x86/include/asm/msr-index.h
718
#define MSR_AMD64_SNP_RESTRICTED_INJ BIT_ULL(MSR_AMD64_SNP_RESTRICTED_INJ_BIT)
arch/x86/include/asm/msr-index.h
720
#define MSR_AMD64_SNP_ALT_INJ BIT_ULL(MSR_AMD64_SNP_ALT_INJ_BIT)
arch/x86/include/asm/msr-index.h
722
#define MSR_AMD64_SNP_DEBUG_SWAP BIT_ULL(MSR_AMD64_SNP_DEBUG_SWAP_BIT)
arch/x86/include/asm/msr-index.h
724
#define MSR_AMD64_SNP_PREVENT_HOST_IBS BIT_ULL(MSR_AMD64_SNP_PREVENT_HOST_IBS_BIT)
arch/x86/include/asm/msr-index.h
726
#define MSR_AMD64_SNP_BTB_ISOLATION BIT_ULL(MSR_AMD64_SNP_BTB_ISOLATION_BIT)
arch/x86/include/asm/msr-index.h
728
#define MSR_AMD64_SNP_VMPL_SSS BIT_ULL(MSR_AMD64_SNP_VMPL_SSS_BIT)
arch/x86/include/asm/msr-index.h
730
#define MSR_AMD64_SNP_SECURE_TSC BIT_ULL(MSR_AMD64_SNP_SECURE_TSC_BIT)
arch/x86/include/asm/msr-index.h
732
#define MSR_AMD64_SNP_VMGEXIT_PARAM BIT_ULL(MSR_AMD64_SNP_VMGEXIT_PARAM_BIT)
arch/x86/include/asm/msr-index.h
733
#define MSR_AMD64_SNP_RESERVED_BIT13 BIT_ULL(13)
arch/x86/include/asm/msr-index.h
735
#define MSR_AMD64_SNP_IBS_VIRT BIT_ULL(MSR_AMD64_SNP_IBS_VIRT_BIT)
arch/x86/include/asm/msr-index.h
736
#define MSR_AMD64_SNP_RESERVED_BIT15 BIT_ULL(15)
arch/x86/include/asm/msr-index.h
738
#define MSR_AMD64_SNP_VMSA_REG_PROT BIT_ULL(MSR_AMD64_SNP_VMSA_REG_PROT_BIT)
arch/x86/include/asm/msr-index.h
740
#define MSR_AMD64_SNP_SMT_PROT BIT_ULL(MSR_AMD64_SNP_SMT_PROT_BIT)
arch/x86/include/asm/msr-index.h
742
#define MSR_AMD64_SNP_SECURE_AVIC BIT_ULL(MSR_AMD64_SNP_SECURE_AVIC_BIT)
arch/x86/include/asm/msr-index.h
745
#define MSR_AMD64_SNP_IBPB_ON_ENTRY BIT_ULL(MSR_AMD64_SNP_IBPB_ON_ENTRY_BIT)
arch/x86/include/asm/msr-index.h
750
#define MSR_AMD64_SAVIC_EN BIT_ULL(MSR_AMD64_SAVIC_EN_BIT)
arch/x86/include/asm/msr-index.h
752
#define MSR_AMD64_SAVIC_ALLOWEDNMI BIT_ULL(MSR_AMD64_SAVIC_ALLOWEDNMI_BIT)
arch/x86/include/asm/msr-index.h
757
#define MSR_AMD64_SEG_RMP_ENABLED BIT_ULL(MSR_AMD64_SEG_RMP_ENABLED_BIT)
arch/x86/include/asm/msr-index.h
858
#define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT)
arch/x86/include/asm/msr-index.h
860
#define MSR_AMD64_SYSCFG_SNP_EN BIT_ULL(MSR_AMD64_SYSCFG_SNP_EN_BIT)
arch/x86/include/asm/msr-index.h
862
#define MSR_AMD64_SYSCFG_SNP_VMPL_EN BIT_ULL(MSR_AMD64_SYSCFG_SNP_VMPL_EN_BIT)
arch/x86/include/asm/msr-index.h
864
#define MSR_AMD64_SYSCFG_MFDM BIT_ULL(MSR_AMD64_SYSCFG_MFDM_BIT)
arch/x86/include/asm/msr-index.h
887
#define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT)
arch/x86/include/asm/msr-index.h
889
#define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT)
arch/x86/include/asm/msr-index.h
894
#define MSR_K7_HWCR_CPB_DIS BIT_ULL(MSR_K7_HWCR_CPB_DIS_BIT)
arch/x86/include/asm/msr-index.h
987
#define DBG_EXTN_CFG_LBRV2EN BIT_ULL(6)
arch/x86/include/asm/perf_event.h
125
#define AMD64_PERFMON_V2_ENABLE_UMC BIT_ULL(31)
arch/x86/include/asm/perf_event.h
145
#define PEBS_DATACFG_MEMINFO BIT_ULL(0)
arch/x86/include/asm/perf_event.h
146
#define PEBS_DATACFG_GP BIT_ULL(1)
arch/x86/include/asm/perf_event.h
147
#define PEBS_DATACFG_XMMS BIT_ULL(2)
arch/x86/include/asm/perf_event.h
148
#define PEBS_DATACFG_LBRS BIT_ULL(3)
arch/x86/include/asm/perf_event.h
149
#define PEBS_DATACFG_CNTR BIT_ULL(4)
arch/x86/include/asm/perf_event.h
150
#define PEBS_DATACFG_METRICS BIT_ULL(5)
arch/x86/include/asm/perf_event.h
158
#define PEBS_UPDATE_DS_SW BIT_ULL(63)
arch/x86/include/asm/perf_event.h
420
#define INTEL_TD_CFG_METRIC_CLEAR BIT_ULL(INTEL_TD_CFG_METRIC_CLEAR_BIT)
arch/x86/include/asm/perf_event.h
435
#define GLOBAL_STATUS_COND_CHG BIT_ULL(63)
arch/x86/include/asm/perf_event.h
437
#define GLOBAL_STATUS_BUFFER_OVF BIT_ULL(GLOBAL_STATUS_BUFFER_OVF_BIT)
arch/x86/include/asm/perf_event.h
438
#define GLOBAL_STATUS_UNC_OVF BIT_ULL(61)
arch/x86/include/asm/perf_event.h
439
#define GLOBAL_STATUS_ASIF BIT_ULL(60)
arch/x86/include/asm/perf_event.h
440
#define GLOBAL_STATUS_COUNTERS_FROZEN BIT_ULL(59)
arch/x86/include/asm/perf_event.h
442
#define GLOBAL_STATUS_LBRS_FROZEN BIT_ULL(GLOBAL_STATUS_LBRS_FROZEN_BIT)
arch/x86/include/asm/perf_event.h
444
#define GLOBAL_STATUS_TRACE_TOPAPMI BIT_ULL(GLOBAL_STATUS_TRACE_TOPAPMI_BIT)
arch/x86/include/asm/perf_event.h
446
#define GLOBAL_STATUS_ARCH_PEBS_THRESHOLD BIT_ULL(GLOBAL_STATUS_ARCH_PEBS_THRESHOLD_BIT)
arch/x86/include/asm/perf_event.h
449
#define GLOBAL_CTRL_EN_PERF_METRICS BIT_ULL(48)
arch/x86/include/asm/perf_event.h
85
#define AMD64_L3_EN_ALL_CORES BIT_ULL(47)
arch/x86/include/asm/perf_event.h
86
#define AMD64_L3_EN_ALL_SLICES BIT_ULL(46)
arch/x86/include/asm/processor-flags.h
42
#define CR3_NOFLUSH BIT_ULL(63)
arch/x86/include/asm/processor.h
226
return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT);
arch/x86/include/asm/sev-common.h
113
#define GHCB_MSR_PSC_RESP_ERROR (BIT_ULL(63) | GHCB_MSR_PSC_RESP)
arch/x86/include/asm/sev-common.h
13
#define GHCB_MSR_INFO_MASK (BIT_ULL(GHCB_DATA_LOW) - 1)
arch/x86/include/asm/sev-common.h
137
#define GHCB_HV_FT_SNP BIT_ULL(0)
arch/x86/include/asm/sev-common.h
138
#define GHCB_HV_FT_SNP_AP_CREATION BIT_ULL(1)
arch/x86/include/asm/sev-common.h
139
#define GHCB_HV_FT_SNP_MULTI_VMPL BIT_ULL(5)
arch/x86/include/asm/sgx.h
142
#define SGX_ATTR_RESERVED_MASK (BIT_ULL(3) | \
arch/x86/include/asm/sgx.h
143
BIT_ULL(6) | \
arch/x86/include/asm/sgx.h
144
BIT_ULL(8) | \
arch/x86/include/asm/sgx.h
145
BIT_ULL(9) | \
arch/x86/include/asm/shared/tdx.h
25
#define TDX_ATTR_DEBUG BIT_ULL(TDX_ATTR_DEBUG_BIT)
arch/x86/include/asm/shared/tdx.h
27
#define TDX_ATTR_HGS_PLUS_PROF BIT_ULL(TDX_ATTR_HGS_PLUS_PROF_BIT)
arch/x86/include/asm/shared/tdx.h
29
#define TDX_ATTR_PERF_PROF BIT_ULL(TDX_ATTR_PERF_PROF_BIT)
arch/x86/include/asm/shared/tdx.h
31
#define TDX_ATTR_PMT_PROF BIT_ULL(TDX_ATTR_PMT_PROF_BIT)
arch/x86/include/asm/shared/tdx.h
33
#define TDX_ATTR_ICSSD BIT_ULL(TDX_ATTR_ICSSD_BIT)
arch/x86/include/asm/shared/tdx.h
35
#define TDX_ATTR_LASS BIT_ULL(TDX_ATTR_LASS_BIT)
arch/x86/include/asm/shared/tdx.h
37
#define TDX_ATTR_SEPT_VE_DISABLE BIT_ULL(TDX_ATTR_SEPT_VE_DISABLE_BIT)
arch/x86/include/asm/shared/tdx.h
39
#define TDX_ATTR_MIGRTABLE BIT_ULL(TDX_ATTR_MIGRTABLE_BIT)
arch/x86/include/asm/shared/tdx.h
41
#define TDX_ATTR_PKS BIT_ULL(TDX_ATTR_PKS_BIT)
arch/x86/include/asm/shared/tdx.h
43
#define TDX_ATTR_KL BIT_ULL(TDX_ATTR_KL_BIT)
arch/x86/include/asm/shared/tdx.h
45
#define TDX_ATTR_TPA BIT_ULL(TDX_ATTR_TPA_BIT)
arch/x86/include/asm/shared/tdx.h
47
#define TDX_ATTR_PERFMON BIT_ULL(TDX_ATTR_PERFMON_BIT)
arch/x86/include/asm/shared/tdx.h
56
#define TDCS_CONFIG_FLEXIBLE_PENDING_VE BIT_ULL(1)
arch/x86/include/asm/shared/tdx.h
60
#define TD_CTLS_PENDING_VE_DISABLE BIT_ULL(TD_CTLS_PENDING_VE_DISABLE_BIT)
arch/x86/include/asm/shared/tdx.h
62
#define TD_CTLS_ENUM_TOPOLOGY BIT_ULL(TD_CTLS_ENUM_TOPOLOGY_BIT)
arch/x86/include/asm/shared/tdx.h
64
#define TD_CTLS_VIRT_CPUID2 BIT_ULL(TD_CTLS_VIRT_CPUID2_BIT)
arch/x86/include/asm/shared/tdx.h
66
#define TD_CTLS_REDUCE_VE BIT_ULL(TD_CTLS_REDUCE_VE_BIT)
arch/x86/include/asm/shared/tdx.h
68
#define TD_CTLS_LOCK BIT_ULL(TD_CTLS_LOCK_BIT)
arch/x86/include/asm/svm.h
225
#define LBR_CTL_ENABLE_MASK BIT_ULL(0)
arch/x86/include/asm/svm.h
226
#define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
arch/x86/include/asm/svm.h
228
#define SVM_INTERRUPT_SHADOW_MASK BIT_ULL(0)
arch/x86/include/asm/svm.h
229
#define SVM_GUEST_INTERRUPT_MASK BIT_ULL(1)
arch/x86/include/asm/svm.h
263
#define AVIC_PHYSICAL_ID_ENTRY_GA_LOG_INTR BIT_ULL(61)
arch/x86/include/asm/svm.h
310
#define VMCB_ALLOWED_SEV_FEATURES_VALID BIT_ULL(63)
arch/x86/include/asm/vmx.h
134
#define VMX_BASIC_32BIT_PHYS_ADDR_ONLY BIT_ULL(48)
arch/x86/include/asm/vmx.h
135
#define VMX_BASIC_DUAL_MONITOR_TREATMENT BIT_ULL(49)
arch/x86/include/asm/vmx.h
136
#define VMX_BASIC_INOUT BIT_ULL(54)
arch/x86/include/asm/vmx.h
137
#define VMX_BASIC_TRUE_CTLS BIT_ULL(55)
arch/x86/include/asm/vmx.h
138
#define VMX_BASIC_NO_HW_ERROR_CODE_CC BIT_ULL(56)
arch/x86/include/asm/vmx.h
160
#define VMX_MISC_SAVE_EFER_LMA BIT_ULL(5)
arch/x86/include/asm/vmx.h
161
#define VMX_MISC_ACTIVITY_HLT BIT_ULL(6)
arch/x86/include/asm/vmx.h
162
#define VMX_MISC_ACTIVITY_SHUTDOWN BIT_ULL(7)
arch/x86/include/asm/vmx.h
163
#define VMX_MISC_ACTIVITY_WAIT_SIPI BIT_ULL(8)
arch/x86/include/asm/vmx.h
164
#define VMX_MISC_INTEL_PT BIT_ULL(14)
arch/x86/include/asm/vmx.h
165
#define VMX_MISC_RDMSR_IN_SMM BIT_ULL(15)
arch/x86/include/asm/vmx.h
166
#define VMX_MISC_VMXOFF_BLOCK_SMI BIT_ULL(28)
arch/x86/include/asm/vmx.h
167
#define VMX_MISC_VMWRITE_SHADOW_RO_FIELDS BIT_ULL(29)
arch/x86/include/asm/vmx.h
168
#define VMX_MISC_ZERO_LEN_INS BIT_ULL(30)
arch/x86/kernel/cpu/mce/amd.c
1263
if (!(this_cpu_read(bank_map) & BIT_ULL(bank)))
arch/x86/kernel/cpu/mce/amd.c
573
per_cpu(bank_map, cpu) |= BIT_ULL(bank);
arch/x86/kernel/cpu/mshyperv.c
573
BIT_ULL(ms_hyperv.shared_gpa_boundary_bits);
arch/x86/kernel/cpu/mtrr/generic.c
317
add_map_entry(BIT_ULL(32), mtrr_tom2, MTRR_TYPE_WRBACK);
arch/x86/kernel/cpu/resctrl/intel_aet.c
340
#define DATA_VALID BIT_ULL(63)
arch/x86/kernel/cpu/resctrl/internal.h
20
#define RMID_VAL_ERROR BIT_ULL(63)
arch/x86/kernel/cpu/resctrl/internal.h
22
#define RMID_VAL_UNAVAIL BIT_ULL(62)
arch/x86/kernel/fpu/xstate.c
1006
if (WARN_ON_ONCE(!(xcomp_bv & BIT_ULL(xfeature_nr))))
arch/x86/kernel/fpu/xstate.c
1057
if (!(xsave->header.xfeatures & BIT_ULL(xfeature_nr)))
arch/x86/kernel/fpu/xstate.c
108
if (mask & BIT_ULL(xfeature_uncompact_order[i]))
arch/x86/kernel/fpu/xstate.c
1355
mask = BIT_ULL(i);
arch/x86/kernel/fpu/xstate.c
240
return fpu_kernel_cfg.max_features & BIT_ULL(xfeature);
arch/x86/kernel/fpu/xstate.c
304
u64 mask = BIT_ULL(i);
arch/x86/kernel/fpu/xstate.c
869
fpu_kernel_cfg.max_features &= ~BIT_ULL(i);
arch/x86/kernel/kvm.c
966
.mask_hi = (BIT_ULL(boot_cpu_data.x86_phys_bits) - 1) >> 32,
arch/x86/kvm/cpuid.c
1566
if (permitted_xcr0 & BIT_ULL(i))
arch/x86/kvm/cpuid.c
1568
else if (permitted_xss & BIT_ULL(i))
arch/x86/kvm/cpuid.c
1591
entry->ecx &= ~BIT_ULL(2);
arch/x86/kvm/cpuid.c
72
if (!(xstate_bv & BIT_ULL(i)))
arch/x86/kvm/cpuid.c
81
xstate_bv &= ~BIT_ULL(i);
arch/x86/kvm/hyperv.c
2067
valid_bank_mask = BIT_ULL(0);
arch/x86/kvm/hyperv.c
2252
valid_bank_mask = BIT_ULL(0);
arch/x86/kvm/mmu/spte.c
571
mask = BIT_ULL(51) | PT_PRESENT_MASK;
arch/x86/kvm/mmu/spte.h
139
#define SPTE_MMIO_ALLOWED_MASK (BIT_ULL(63) | GENMASK_ULL(51, 12) | GENMASK_ULL(2, 0))
arch/x86/kvm/mmu/spte.h
164
#define SHADOW_NONPRESENT_VALUE BIT_ULL(63)
arch/x86/kvm/mmu/spte.h
18
#define SPTE_MMU_PRESENT_MASK BIT_ULL(11)
arch/x86/kvm/mmu/spte.h
390
return rsvd_check->bad_mt_xwr & BIT_ULL(pte & 0x3f);
arch/x86/kvm/mmu/spte.h
82
#define DEFAULT_SPTE_HOST_WRITABLE BIT_ULL(9)
arch/x86/kvm/mmu/spte.h
83
#define DEFAULT_SPTE_MMU_WRITABLE BIT_ULL(10)
arch/x86/kvm/mmu/spte.h
90
#define EPT_SPTE_HOST_WRITABLE BIT_ULL(57)
arch/x86/kvm/mmu/spte.h
91
#define EPT_SPTE_MMU_WRITABLE BIT_ULL(58)
arch/x86/kvm/pmu.c
1069
pmc_to_pmu(pmc)->global_status |= BIT_ULL(pmc->idx);
arch/x86/kvm/pmu.c
784
pmu->counter_bitmask[KVM_PMC_GP] != (BIT_ULL(kvm_host_pmu.bit_width_gp) - 1) ||
arch/x86/kvm/pmu.c
785
pmu->counter_bitmask[KVM_PMC_FIXED] != (BIT_ULL(kvm_host_pmu.bit_width_fixed) - 1);
arch/x86/kvm/svm/pmu.c
205
pmu->global_ctrl_rsvd = ~(BIT_ULL(pmu->nr_arch_gp_counters) - 1);
arch/x86/kvm/svm/pmu.c
209
pmu->counter_bitmask[KVM_PMC_GP] = BIT_ULL(48) - 1;
arch/x86/kvm/vmx/nested.c
1298
BIT_ULL(31);
arch/x86/kvm/vmx/nested.c
1396
const u64 reserved_bits = BIT_ULL(31) | GENMASK_ULL(13, 9);
arch/x86/kvm/vmx/nested.c
6194
if (!(vmcs12->vm_function_control & BIT_ULL(function)))
arch/x86/kvm/vmx/nested.c
6407
return vmcs12->encls_exiting_bitmap & BIT_ULL(encls_leaf);
arch/x86/kvm/vmx/pmu_intel.c
528
pmu->counter_bitmask[KVM_PMC_GP] = BIT_ULL(eax.split.bit_width) - 1;
arch/x86/kvm/vmx/pmu_intel.c
531
pmu->available_event_types = ~entry->ebx & (BIT_ULL(eax.split.mask_length) - 1);
arch/x86/kvm/vmx/pmu_intel.c
558
pmu->counter_bitmask[KVM_PMC_FIXED] = BIT_ULL(edx.split.bit_width_fixed) - 1;
arch/x86/kvm/vmx/pmu_intel.c
564
counter_rsvd = ~((BIT_ULL(pmu->nr_arch_gp_counters) - 1) |
arch/x86/kvm/vmx/pmu_intel.c
565
((BIT_ULL(pmu->nr_arch_fixed_counters) - 1) << KVM_FIXED_PMC_BASE_IDX));
arch/x86/kvm/vmx/pmu_intel.c
587
pmu->pebs_enable_rsvd = ~(BIT_ULL(pmu->nr_arch_gp_counters) - 1);
arch/x86/kvm/vmx/pmu_intel.c
755
pmu->host_cross_mapped_mask |= BIT_ULL(hw_idx);
arch/x86/kvm/vmx/sgx.c
194
if (size >= BIT_ULL(max_size_log2)) {
arch/x86/kvm/vmx/tdx.c
1020
#define TDX_REGS_AVAIL_SET (BIT_ULL(VCPU_EXREG_EXIT_INFO_1) | \
arch/x86/kvm/vmx/tdx.c
1021
BIT_ULL(VCPU_EXREG_EXIT_INFO_2) | \
arch/x86/kvm/vmx/tdx.c
1022
BIT_ULL(VCPU_REGS_RAX) | \
arch/x86/kvm/vmx/tdx.c
1023
BIT_ULL(VCPU_REGS_RBX) | \
arch/x86/kvm/vmx/tdx.c
1024
BIT_ULL(VCPU_REGS_RCX) | \
arch/x86/kvm/vmx/tdx.c
1025
BIT_ULL(VCPU_REGS_RDX) | \
arch/x86/kvm/vmx/tdx.c
1026
BIT_ULL(VCPU_REGS_RBP) | \
arch/x86/kvm/vmx/tdx.c
1027
BIT_ULL(VCPU_REGS_RSI) | \
arch/x86/kvm/vmx/tdx.c
1028
BIT_ULL(VCPU_REGS_RDI) | \
arch/x86/kvm/vmx/tdx.c
1029
BIT_ULL(VCPU_REGS_R8) | \
arch/x86/kvm/vmx/tdx.c
1030
BIT_ULL(VCPU_REGS_R9) | \
arch/x86/kvm/vmx/tdx.c
1031
BIT_ULL(VCPU_REGS_R10) | \
arch/x86/kvm/vmx/tdx.c
1032
BIT_ULL(VCPU_REGS_R11) | \
arch/x86/kvm/vmx/tdx.c
1033
BIT_ULL(VCPU_REGS_R12) | \
arch/x86/kvm/vmx/tdx.c
1034
BIT_ULL(VCPU_REGS_R13) | \
arch/x86/kvm/vmx/tdx.c
1035
BIT_ULL(VCPU_REGS_R14) | \
arch/x86/kvm/vmx/tdx.c
1036
BIT_ULL(VCPU_REGS_R15))
arch/x86/kvm/vmx/tdx.c
58
#define TDX_SHARED_BIT_PWL_5 gpa_to_gfn(BIT_ULL(51))
arch/x86/kvm/vmx/tdx.c
59
#define TDX_SHARED_BIT_PWL_4 gpa_to_gfn(BIT_ULL(47))
arch/x86/kvm/vmx/tdx_arch.h
10
#define TDX_NON_ARCH BIT_ULL(63)
arch/x86/kvm/vmx/tdx_arch.h
116
#define TDX_CONFIG_FLAGS_MAX_GPAW BIT_ULL(0)
arch/x86/kvm/vmx/tdx_arch.h
123
#define TDX_CONFIG_FLAGS_NO_RBP_MOD BIT_ULL(2)
arch/x86/kvm/vmx/tdx_arch.h
160
#define MD_FIELD_ID_FEATURES0_TOPOLOGY_ENUM BIT_ULL(20)
arch/x86/kvm/vmx/tdx_arch.h
44
#define TDX_VCPU_STATE_DETAILS_INTR_PENDING BIT_ULL(0)
arch/x86/kvm/vmx/tdx_arch.h
78
#define TDX_TD_ATTR_DEBUG BIT_ULL(0)
arch/x86/kvm/vmx/tdx_arch.h
79
#define TDX_TD_ATTR_SEPT_VE_DISABLE BIT_ULL(28)
arch/x86/kvm/vmx/tdx_arch.h
80
#define TDX_TD_ATTR_PKS BIT_ULL(30)
arch/x86/kvm/vmx/tdx_arch.h
81
#define TDX_TD_ATTR_KL BIT_ULL(31)
arch/x86/kvm/vmx/tdx_arch.h
82
#define TDX_TD_ATTR_PERFMON BIT_ULL(63)
arch/x86/kvm/vmx/vmx.c
2430
if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
arch/x86/kvm/vmx/vmx.c
8605
if (!(gva & BIT_ULL(63))) {
arch/x86/kvm/vmx/vmx.c
8624
return (sign_extend64(gva, lam_bit) & ~BIT_ULL(63)) | (gva & BIT_ULL(63));
arch/x86/kvm/x86.c
3552
return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
arch/x86/kvm/x86.c
4013
if (data & ~(BIT_ULL(18) | BIT_ULL(24))) {
arch/x86/platform/efi/efi_64.c
485
____s ^= (____s & BIT(31)) | (____s & BIT_ULL(31)) << 32; \
drivers/accel/habanalabs/common/habanalabs.h
2721
__elem_bitmask = BIT_ULL(arr_size) - 1; \
drivers/accel/habanalabs/common/habanalabs.h
2726
if (!(__elem_bitmask & BIT_ULL(__arr_idx))) \
drivers/accel/habanalabs/common/habanalabs.h
2736
__elem_bitmask &= ~BIT_ULL(__arr_idx); \
drivers/accel/habanalabs/common/security.c
328
if (!(mask & BIT_ULL(seq)))
drivers/accel/habanalabs/common/security.c
410
if (!(mask & BIT_ULL(seq)))
drivers/accel/habanalabs/common/security.c
566
if (!(mask & BIT_ULL(seq)))
drivers/accel/habanalabs/gaudi/gaudiP.h
211
(addr) |= BIT_ULL(39); \
drivers/accel/habanalabs/gaudi2/gaudi2.c
11003
if (!(cfg_ctx->enabled_mask & BIT_ULL(seq)))
drivers/accel/habanalabs/gaudi2/gaudi2.c
3581
!(hdev->nic_ports_mask & BIT_ULL(arc_id - CPU_ID_NIC_QMAN_ARC0)))
drivers/accel/habanalabs/gaudi2/gaudi2.c
3585
BIT_ULL(arc_id - CPU_ID_TPC_QMAN_ARC0)))
drivers/accel/habanalabs/gaudi2/gaudi2.c
4278
if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_EDMA_SHIFT + seq)))
drivers/accel/habanalabs/gaudi2/gaudi2.c
4298
if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_MME_SHIFT + i)))
drivers/accel/habanalabs/gaudi2/gaudi2.c
4315
if (!(gaudi2->tpc_hw_cap_initialized & BIT_ULL(HW_CAP_TPC_SHIFT + i)))
drivers/accel/habanalabs/gaudi2/gaudi2.c
4333
if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_ROT_SHIFT + i)))
drivers/accel/habanalabs/gaudi2/gaudi2.c
4389
if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_EDMA_SHIFT + seq)))
drivers/accel/habanalabs/gaudi2/gaudi2.c
4409
if (gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_MME_SHIFT + i))
drivers/accel/habanalabs/gaudi2/gaudi2.c
4423
if (!(gaudi2->tpc_hw_cap_initialized & BIT_ULL(HW_CAP_TPC_SHIFT + i)))
drivers/accel/habanalabs/gaudi2/gaudi2.c
4445
if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_ROT_SHIFT + i)))
drivers/accel/habanalabs/gaudi2/gaudi2.c
4477
if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_EDMA_SHIFT + seq)))
drivers/accel/habanalabs/gaudi2/gaudi2.c
4497
if (gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_MME_SHIFT + i))
drivers/accel/habanalabs/gaudi2/gaudi2.c
4511
if (!(gaudi2->tpc_hw_cap_initialized & BIT_ULL(HW_CAP_TPC_SHIFT + i)))
drivers/accel/habanalabs/gaudi2/gaudi2.c
4529
if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_ROT_SHIFT + i)))
drivers/accel/habanalabs/gaudi2/gaudi2.c
5060
if (!(gaudi2->tpc_hw_cap_initialized & BIT_ULL(HW_CAP_TPC_SHIFT + tpc_id)))
drivers/accel/habanalabs/gaudi2/gaudi2.c
5084
if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_MME_SHIFT + mme_id)))
drivers/accel/habanalabs/gaudi2/gaudi2.c
5105
if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_EDMA_SHIFT + edma_id)))
drivers/accel/habanalabs/gaudi2/gaudi2.c
5646
gaudi2->hw_cap_initialized |= BIT_ULL(HW_CAP_EDMA_SHIFT + seq);
drivers/accel/habanalabs/gaudi2/gaudi2.c
5862
gaudi2->hw_cap_initialized |= BIT_ULL(HW_CAP_MME_SHIFT + i);
drivers/accel/habanalabs/gaudi2/gaudi2.c
5899
gaudi2->tpc_hw_cap_initialized |= BIT_ULL(HW_CAP_TPC_SHIFT + seq);
drivers/accel/habanalabs/gaudi2/gaudi2.c
5934
gaudi2->hw_cap_initialized |= BIT_ULL(HW_CAP_ROT_SHIFT + i);
drivers/accel/habanalabs/gaudi2/gaudi2.c
5981
gaudi2->dec_hw_cap_initialized |= BIT_ULL(HW_CAP_DEC_SHIFT + dec_bit);
drivers/accel/habanalabs/gaudi2/gaudi2.c
5994
gaudi2->dec_hw_cap_initialized |= BIT_ULL(HW_CAP_DEC_SHIFT + dec_bit);
drivers/accel/habanalabs/gaudi2/gaudi2.c
6919
return !!(gaudi2->tpc_hw_cap_initialized & BIT_ULL(0));
drivers/accel/habanalabs/gaudi2/gaudi2.c
6950
return !!(gaudi2->nic_hw_cap_initialized & BIT_ULL(0));
drivers/accel/habanalabs/gaudi2/gaudi2.c
6961
return !!(gaudi2->tpc_hw_cap_initialized & BIT_ULL(hw_tpc_cap_bit));
drivers/accel/habanalabs/gaudi2/gaudi2.c
6964
return !!(gaudi2->nic_hw_cap_initialized & BIT_ULL(hw_nic_cap_bit));
drivers/accel/habanalabs/gaudi2/gaudi2.c
6967
hw_cap_mask = BIT_ULL(hw_test_cap_bit);
drivers/accel/habanalabs/gaudi2/gaudi2.c
6979
return !!(gaudi2->active_hw_arc & BIT_ULL(arc_id));
drivers/accel/habanalabs/gaudi2/gaudi2.c
6982
return !!(gaudi2->active_tpc_arc & BIT_ULL(arc_id - CPU_ID_TPC_QMAN_ARC0));
drivers/accel/habanalabs/gaudi2/gaudi2.c
6985
return !!(gaudi2->active_nic_arc & BIT_ULL(arc_id - CPU_ID_NIC_QMAN_ARC0));
drivers/accel/habanalabs/gaudi2/gaudi2.c
6999
gaudi2->active_hw_arc &= ~(BIT_ULL(arc_id));
drivers/accel/habanalabs/gaudi2/gaudi2.c
7003
gaudi2->active_tpc_arc &= ~(BIT_ULL(arc_id - CPU_ID_TPC_QMAN_ARC0));
drivers/accel/habanalabs/gaudi2/gaudi2.c
7007
gaudi2->active_nic_arc &= ~(BIT_ULL(arc_id - CPU_ID_NIC_QMAN_ARC0));
drivers/accel/habanalabs/gaudi2/gaudi2.c
7022
gaudi2->active_hw_arc |= BIT_ULL(arc_id);
drivers/accel/habanalabs/gaudi2/gaudi2.c
7026
gaudi2->active_tpc_arc |= BIT_ULL(arc_id - CPU_ID_TPC_QMAN_ARC0);
drivers/accel/habanalabs/gaudi2/gaudi2.c
7030
gaudi2->active_nic_arc |= BIT_ULL(arc_id - CPU_ID_NIC_QMAN_ARC0);
drivers/accel/habanalabs/gaudi2/gaudi2.c
9305
if (!(intr_cause_data & BIT_ULL(i)))
drivers/accel/habanalabs/gaudi2/gaudi2.c
9312
switch (intr_cause_data & BIT_ULL(i)) {
drivers/accel/habanalabs/gaudi2/gaudi2.c
9333
if (intr_cause_data & BIT_ULL(i)) {
drivers/accel/habanalabs/gaudi2/gaudi2.c
9349
if (intr_cause_data & BIT_ULL(i)) {
drivers/accel/habanalabs/gaudi2/gaudi2.c
9912
if (cause & BIT_ULL(0)) {
drivers/accel/habanalabs/gaudi2/gaudi2.c
9917
if (cause & BIT_ULL(1)) {
drivers/accel/habanalabs/gaudi2/gaudi2.c
9931
if (intr_cause_data & BIT_ULL(i)) {
drivers/accel/habanalabs/gaudi2/gaudi2P.h
157
#define HW_CAP_PLL BIT_ULL(0)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
158
#define HW_CAP_DRAM BIT_ULL(1)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
159
#define HW_CAP_PMMU BIT_ULL(2)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
160
#define HW_CAP_CPU BIT_ULL(3)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
161
#define HW_CAP_MSIX BIT_ULL(4)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
163
#define HW_CAP_CPU_Q BIT_ULL(5)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
166
#define HW_CAP_CLK_GATE BIT_ULL(6)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
167
#define HW_CAP_KDMA BIT_ULL(7)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
168
#define HW_CAP_SRAM_SCRAMBLER BIT_ULL(8)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
170
#define HW_CAP_DCORE0_DMMU0 BIT_ULL(9)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
171
#define HW_CAP_DCORE0_DMMU1 BIT_ULL(10)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
172
#define HW_CAP_DCORE0_DMMU2 BIT_ULL(11)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
173
#define HW_CAP_DCORE0_DMMU3 BIT_ULL(12)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
174
#define HW_CAP_DCORE1_DMMU0 BIT_ULL(13)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
175
#define HW_CAP_DCORE1_DMMU1 BIT_ULL(14)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
176
#define HW_CAP_DCORE1_DMMU2 BIT_ULL(15)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
177
#define HW_CAP_DCORE1_DMMU3 BIT_ULL(16)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
178
#define HW_CAP_DCORE2_DMMU0 BIT_ULL(17)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
179
#define HW_CAP_DCORE2_DMMU1 BIT_ULL(18)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
180
#define HW_CAP_DCORE2_DMMU2 BIT_ULL(19)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
181
#define HW_CAP_DCORE2_DMMU3 BIT_ULL(20)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
182
#define HW_CAP_DCORE3_DMMU0 BIT_ULL(21)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
183
#define HW_CAP_DCORE3_DMMU1 BIT_ULL(22)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
184
#define HW_CAP_DCORE3_DMMU2 BIT_ULL(23)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
185
#define HW_CAP_DCORE3_DMMU3 BIT_ULL(24)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
188
#define HW_CAP_PDMA_MASK BIT_ULL(26)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
195
#define HW_CAP_HBM_SCRAMBLER_HW_RESET BIT_ULL(41)
drivers/accel/habanalabs/gaudi2/gaudi2P.h
196
#define HW_CAP_HBM_SCRAMBLER_SW_RESET BIT_ULL(42)
drivers/accel/ivpu/ivpu_mmu.c
170
#define IVPU_MMU_CD_0_TCR_EPD0 BIT_ULL(14)
drivers/accel/ivpu/ivpu_mmu.c
171
#define IVPU_MMU_CD_0_TCR_EPD1 BIT_ULL(30)
drivers/accel/ivpu/ivpu_mmu.c
175
#define IVPU_MMU_CD_0_TCR_TBI0 BIT_ULL(38)
drivers/acpi/riscv/cpuidle.c
20
#define RISCV_FFH_LPI_TYPE_SBI BIT_ULL(60)
drivers/ata/libata-core.c
2600
if (!(val & BIT_ULL(63)) || !(val & BIT_ULL(0)))
drivers/ata/libata-core.c
2604
if (!(val & BIT_ULL(1)))
drivers/ata/libata-core.c
2613
if (!(val & BIT_ULL(63)) || !(val & BIT_ULL(47))) {
drivers/ata/libata-core.c
2637
cdl_enabled = val & BIT_ULL(63) && val & BIT_ULL(21);
drivers/ata/libata-core.c
2666
if (!(val & BIT_ULL(63)) || !(val & BIT_ULL(18))) {
drivers/cache/sifive_ccache.c
113
BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_SETS_MASK, cfg)),
drivers/cache/sifive_ccache.c
114
BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_BLKS_MASK, cfg)));
drivers/char/hw_random/cavium-rng-vf.c
94
if (status & BIT_ULL(0)) {
drivers/char/hw_random/cn10k-rng.c
88
if (status & BIT_ULL(20)) {
drivers/clk/clk-si5341.c
388
while (!(n_num & BIT_ULL(43)) && !(n_den & BIT(31))) {
drivers/clk/clk-versaclock7.c
786
denom = BIT_ULL(VC7_FOD_DENOMINATOR_BITS);
drivers/crypto/cavium/nitrox/nitrox_hal.c
433
nitrox_write_csr(ndev, POM_PERF_CTL, BIT_ULL(i));
drivers/crypto/cavium/nitrox/nitrox_mbx.c
151
nitrox_write_csr(ndev, reg_addr, BIT_ULL(i));
drivers/crypto/cavium/nitrox/nitrox_mbx.c
175
nitrox_write_csr(ndev, reg_addr, BIT_ULL(i));
drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c
108
val = accel_dev->pf.vf_info ? 0 : BIT_ULL(GET_MAX_BANKS(accel_dev)) - 1;
drivers/crypto/intel/qat/qat_common/adf_sriov.c
78
adf_enable_vf2pf_interrupts(accel_dev, BIT_ULL(totalvfs) - 1);
drivers/crypto/marvell/octeontx2/cn10k_cpt.c
150
cptr_dma = er_ctx->cptr_dma & ~(BIT_ULL(60));
drivers/crypto/marvell/octeontx2/cn10k_cpt.c
191
er_ctx->cptr_dma = cptr_dma | BIT_ULL(60);
drivers/crypto/marvell/octeontx2/cn10k_cpt.c
205
reg = reg | BIT_ULL(46);
drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h
110
#define OTX2_CPT_LMT_LFBASE BIT_ULL(OTX2_CPT_RVU_FUNC_BLKADDR_SHIFT)
drivers/crypto/marvell/octeontx2/otx2_cptlf.h
244
inprog |= BIT_ULL(16);
drivers/crypto/marvell/octeontx2/otx2_cptlf.h
331
val |= BIT_ULL(0);
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
170
RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
172
RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf));
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
193
if (!(intr & BIT_ULL(vf)))
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
199
RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf));
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
203
BIT_ULL(vf));
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
224
if (!(intr & BIT_ULL(vf)))
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
227
RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
230
RVU_PF_VFME_INTX(reg), BIT_ULL(vf));
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
603
if ((cpt_feature_sgv2(pdev) && (reg_val & BIT_ULL(18))) ||
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
616
if (cfg & BIT_ULL(11))
drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c
365
BIT_ULL(vf->intr_idx));
drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c
1248
reg_val |= OTX2_CPT_ALL_ENG_GRPS_MASK << 3 | BIT_ULL(16);
drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c
1269
reg_val | BIT_ULL(24), BLKADDR_CPT0);
drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c
417
if (cptvf->eng_caps[OTX2_CPT_SE_TYPES] & BIT_ULL(35))
drivers/dma/xgene-dma.c
111
#define XGENE_DMA_DESC_NV_BIT BIT_ULL(50)
drivers/dma/xgene-dma.c
112
#define XGENE_DMA_DESC_IN_BIT BIT_ULL(55)
drivers/dma/xgene-dma.c
113
#define XGENE_DMA_DESC_C_BIT BIT_ULL(63)
drivers/dma/xgene-dma.c
114
#define XGENE_DMA_DESC_DR_BIT BIT_ULL(61)
drivers/edac/ie31200_edac.c
669
.reg_mchbar_window_size = BIT_ULL(15),
drivers/edac/ie31200_edac.c
672
.reg_eccerrlog_ce_mask = BIT_ULL(0),
drivers/edac/ie31200_edac.c
673
.reg_eccerrlog_ue_mask = BIT_ULL(1),
drivers/edac/ie31200_edac.c
676
.reg_mad_dimm_size_granularity = BIT_ULL(28),
drivers/edac/ie31200_edac.c
691
.reg_mchbar_window_size = BIT_ULL(15),
drivers/edac/ie31200_edac.c
694
.reg_eccerrlog_ce_mask = BIT_ULL(0),
drivers/edac/ie31200_edac.c
695
.reg_eccerrlog_ue_mask = BIT_ULL(1),
drivers/edac/ie31200_edac.c
698
.reg_mad_dimm_size_granularity = BIT_ULL(30),
drivers/edac/ie31200_edac.c
714
.reg_mchbar_window_size = BIT_ULL(16),
drivers/edac/ie31200_edac.c
717
.reg_eccerrlog_ce_mask = BIT_ULL(0),
drivers/edac/ie31200_edac.c
718
.reg_eccerrlog_ce_ovfl_mask = BIT_ULL(1),
drivers/edac/ie31200_edac.c
719
.reg_eccerrlog_ue_mask = BIT_ULL(2),
drivers/edac/ie31200_edac.c
720
.reg_eccerrlog_ue_ovfl_mask = BIT_ULL(3),
drivers/edac/ie31200_edac.c
726
.reg_mad_dimm_size_granularity = BIT_ULL(29),
drivers/edac/igen6_edac.c
49
#define _4GB BIT_ULL(32)
drivers/edac/igen6_edac.c
66
#define ERRSTS_CE BIT_ULL(6)
drivers/edac/igen6_edac.c
67
#define ERRSTS_UE BIT_ULL(7)
drivers/edac/igen6_edac.c
71
#define ERRCMD_CE BIT_ULL(6)
drivers/edac/igen6_edac.c
72
#define ERRCMD_UE BIT_ULL(7)
drivers/edac/igen6_edac.c
81
#define ECC_ERROR_LOG_CE BIT_ULL(62)
drivers/edac/igen6_edac.c
82
#define ECC_ERROR_LOG_UE BIT_ULL(63)
drivers/edac/igen6_edac.c
87
#define MCHBAR_EN BIT_ULL(0)
drivers/edac/pnd2_edac.c
575
slice_hash_mask |= BIT_ULL(slice_selector);
drivers/edac/pnd2_edac.c
582
chan_hash_mask |= BIT_ULL(chan_selector);
drivers/edac/pnd2_edac.c
602
mask = BIT_ULL(bitidx) - 1;
drivers/edac/skx_base.c
279
if (addr >= skx_tohm || (addr >= skx_tolm && addr < BIT_ULL(32))) {
drivers/edac/skx_common.c
169
res->addr < BIT_ULL(32))) {
drivers/edac/skx_common.c
867
m.status |= BIT_ULL(MCI_STATUS_CEC_SHIFT);
drivers/edac/skx_common.h
219
#define BIT_NM_MEMCTRL BIT_ULL(INDEX_NM_MEMCTRL)
drivers/edac/skx_common.h
220
#define BIT_NM_CHANNEL BIT_ULL(INDEX_NM_CHANNEL)
drivers/edac/skx_common.h
221
#define BIT_NM_DIMM BIT_ULL(INDEX_NM_DIMM)
drivers/edac/skx_common.h
222
#define BIT_NM_CS BIT_ULL(INDEX_NM_CS)
drivers/extcon/extcon-fsa9480.c
127
[DEV_USB_OTG] = BIT_ULL(EXTCON_USB_HOST),
drivers/extcon/extcon-fsa9480.c
128
[DEV_DEDICATED_CHG] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_CHG_USB_DCP),
drivers/extcon/extcon-fsa9480.c
129
[DEV_USB_CHG] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_CHG_USB_SDP),
drivers/extcon/extcon-fsa9480.c
130
[DEV_CAR_KIT] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_CHG_USB_SDP)
drivers/extcon/extcon-fsa9480.c
131
| BIT_ULL(EXTCON_JACK_LINE_OUT),
drivers/extcon/extcon-fsa9480.c
132
[DEV_UART] = BIT_ULL(EXTCON_JIG),
drivers/extcon/extcon-fsa9480.c
133
[DEV_USB] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_CHG_USB_SDP),
drivers/extcon/extcon-fsa9480.c
134
[DEV_AUDIO_2] = BIT_ULL(EXTCON_JACK_LINE_OUT),
drivers/extcon/extcon-fsa9480.c
135
[DEV_AUDIO_1] = BIT_ULL(EXTCON_JACK_LINE_OUT),
drivers/extcon/extcon-fsa9480.c
136
[DEV_AV] = BIT_ULL(EXTCON_JACK_LINE_OUT)
drivers/extcon/extcon-fsa9480.c
137
| BIT_ULL(EXTCON_JACK_VIDEO_OUT),
drivers/extcon/extcon-fsa9480.c
138
[DEV_TTY] = BIT_ULL(EXTCON_JIG),
drivers/extcon/extcon-fsa9480.c
139
[DEV_PPD] = BIT_ULL(EXTCON_JACK_LINE_OUT) | BIT_ULL(EXTCON_CHG_USB_ACA),
drivers/extcon/extcon-fsa9480.c
140
[DEV_JIG_UART_OFF] = BIT_ULL(EXTCON_JIG),
drivers/extcon/extcon-fsa9480.c
141
[DEV_JIG_UART_ON] = BIT_ULL(EXTCON_JIG),
drivers/extcon/extcon-fsa9480.c
142
[DEV_JIG_USB_OFF] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_JIG),
drivers/extcon/extcon-fsa9480.c
143
[DEV_JIG_USB_ON] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_JIG),
drivers/extcon/extcon-fsa9480.c
213
cables &= ~BIT_ULL(cable);
drivers/extcon/extcon-fsa9480.c
216
mask &= ~BIT_ULL(dev);
drivers/firmware/efi/cper-x86.c
11
#define VALID_LAPIC_ID BIT_ULL(0)
drivers/firmware/efi/cper-x86.c
12
#define VALID_CPUID_INFO BIT_ULL(1)
drivers/firmware/efi/cper-x86.c
29
#define INFO_VALID_CHECK_INFO BIT_ULL(0)
drivers/firmware/efi/cper-x86.c
30
#define INFO_VALID_TARGET_ID BIT_ULL(1)
drivers/firmware/efi/cper-x86.c
31
#define INFO_VALID_REQUESTOR_ID BIT_ULL(2)
drivers/firmware/efi/cper-x86.c
32
#define INFO_VALID_RESPONDER_ID BIT_ULL(3)
drivers/firmware/efi/cper-x86.c
33
#define INFO_VALID_IP BIT_ULL(4)
drivers/firmware/efi/cper-x86.c
35
#define CHECK_VALID_TRANS_TYPE BIT_ULL(0)
drivers/firmware/efi/cper-x86.c
36
#define CHECK_VALID_OPERATION BIT_ULL(1)
drivers/firmware/efi/cper-x86.c
37
#define CHECK_VALID_LEVEL BIT_ULL(2)
drivers/firmware/efi/cper-x86.c
38
#define CHECK_VALID_PCC BIT_ULL(3)
drivers/firmware/efi/cper-x86.c
39
#define CHECK_VALID_UNCORRECTED BIT_ULL(4)
drivers/firmware/efi/cper-x86.c
40
#define CHECK_VALID_PRECISE_IP BIT_ULL(5)
drivers/firmware/efi/cper-x86.c
41
#define CHECK_VALID_RESTARTABLE_IP BIT_ULL(6)
drivers/firmware/efi/cper-x86.c
42
#define CHECK_VALID_OVERFLOW BIT_ULL(7)
drivers/firmware/efi/cper-x86.c
44
#define CHECK_VALID_BUS_PART_TYPE BIT_ULL(8)
drivers/firmware/efi/cper-x86.c
45
#define CHECK_VALID_BUS_TIME_OUT BIT_ULL(9)
drivers/firmware/efi/cper-x86.c
46
#define CHECK_VALID_BUS_ADDR_SPACE BIT_ULL(10)
drivers/firmware/efi/cper-x86.c
52
#define CHECK_PCC BIT_ULL(25)
drivers/firmware/efi/cper-x86.c
53
#define CHECK_UNCORRECTED BIT_ULL(26)
drivers/firmware/efi/cper-x86.c
54
#define CHECK_PRECISE_IP BIT_ULL(27)
drivers/firmware/efi/cper-x86.c
55
#define CHECK_RESTARTABLE_IP BIT_ULL(28)
drivers/firmware/efi/cper-x86.c
56
#define CHECK_OVERFLOW BIT_ULL(29)
drivers/firmware/efi/cper-x86.c
59
#define CHECK_BUS_TIME_OUT BIT_ULL(32)
drivers/firmware/efi/cper-x86.c
62
#define CHECK_VALID_MS_ERR_TYPE BIT_ULL(0)
drivers/firmware/efi/cper-x86.c
63
#define CHECK_VALID_MS_PCC BIT_ULL(1)
drivers/firmware/efi/cper-x86.c
64
#define CHECK_VALID_MS_UNCORRECTED BIT_ULL(2)
drivers/firmware/efi/cper-x86.c
65
#define CHECK_VALID_MS_PRECISE_IP BIT_ULL(3)
drivers/firmware/efi/cper-x86.c
66
#define CHECK_VALID_MS_RESTARTABLE_IP BIT_ULL(4)
drivers/firmware/efi/cper-x86.c
67
#define CHECK_VALID_MS_OVERFLOW BIT_ULL(5)
drivers/firmware/efi/cper-x86.c
70
#define CHECK_MS_PCC BIT_ULL(19)
drivers/firmware/efi/cper-x86.c
71
#define CHECK_MS_UNCORRECTED BIT_ULL(20)
drivers/firmware/efi/cper-x86.c
72
#define CHECK_MS_PRECISE_IP BIT_ULL(21)
drivers/firmware/efi/cper-x86.c
73
#define CHECK_MS_RESTARTABLE_IP BIT_ULL(22)
drivers/firmware/efi/cper-x86.c
74
#define CHECK_MS_OVERFLOW BIT_ULL(23)
drivers/firmware/efi/cper.c
149
if (!(bits & BIT_ULL(i)))
drivers/fpga/dfl-fme-error.c
26
#define MBP_ERROR BIT_ULL(6)
drivers/fpga/dfl-fme-main.c
195
#define TEMP_THRESHOLD1_EN BIT_ULL(7)
drivers/fpga/dfl-fme-main.c
197
#define TEMP_THRESHOLD2_EN BIT_ULL(15)
drivers/fpga/dfl-fme-main.c
199
#define TEMP_THRESHOLD1_STATUS BIT_ULL(32) /* threshold1 reached */
drivers/fpga/dfl-fme-main.c
200
#define TEMP_THRESHOLD2_STATUS BIT_ULL(33) /* threshold2 reached */
drivers/fpga/dfl-fme-main.c
202
#define TEMP_THRESHOLD1_POLICY BIT_ULL(44)
drivers/fpga/dfl-fme-main.c
208
#define THERM_NO_THROTTLE BIT_ULL(0)
drivers/fpga/dfl-fme-main.c
366
#define FME_LATENCY_TOLERANCE BIT_ULL(18)
drivers/fpga/dfl-fme-main.c
373
#define PWR_THRESHOLD1_STATUS BIT_ULL(16)
drivers/fpga/dfl-fme-main.c
374
#define PWR_THRESHOLD2_STATUS BIT_ULL(17)
drivers/fpga/dfl-fme-main.c
378
#define XEON_PWR_EN BIT_ULL(15)
drivers/fpga/dfl-fme-main.c
381
#define FPGA_PWR_EN BIT_ULL(15)
drivers/fpga/dfl-fme-mgr.c
37
#define FME_PR_CTRL_PR_RST BIT_ULL(0) /* Reset PR engine */
drivers/fpga/dfl-fme-mgr.c
38
#define FME_PR_CTRL_PR_RSTACK BIT_ULL(4) /* Ack for PR engine reset */
drivers/fpga/dfl-fme-mgr.c
40
#define FME_PR_CTRL_PR_START BIT_ULL(12) /* Start to request PR service */
drivers/fpga/dfl-fme-mgr.c
41
#define FME_PR_CTRL_PR_COMPLETE BIT_ULL(13) /* PR data push completion */
drivers/fpga/dfl-fme-mgr.c
46
#define FME_PR_STS_PR_STS BIT_ULL(16) /* PR operation status */
drivers/fpga/dfl-fme-mgr.c
57
#define FME_PR_ERR_OPERATION_ERR BIT_ULL(0)
drivers/fpga/dfl-fme-mgr.c
59
#define FME_PR_ERR_CRC_ERR BIT_ULL(1)
drivers/fpga/dfl-fme-mgr.c
61
#define FME_PR_ERR_INCOMPATIBLE_BS BIT_ULL(2)
drivers/fpga/dfl-fme-mgr.c
63
#define FME_PR_ERR_PROTOCOL_ERR BIT_ULL(3)
drivers/fpga/dfl-fme-mgr.c
65
#define FME_PR_ERR_FIFO_OVERFLOW BIT_ULL(4)
drivers/fpga/dfl-fme-perf.c
109
#define VTD_SIP_RESET_CNTR BIT_ULL(0)
drivers/fpga/dfl-fme-perf.c
110
#define VTD_SIP_FREEZE_CNTR BIT_ULL(8)
drivers/fpga/dfl-fme-perf.c
29
#define CACHE_RESET_CNTR BIT_ULL(0)
drivers/fpga/dfl-fme-perf.c
30
#define CACHE_FREEZE_CNTR BIT_ULL(8)
drivers/fpga/dfl-fme-perf.c
44
#define CACHE_CHANNEL_SEL BIT_ULL(20)
drivers/fpga/dfl-fme-perf.c
58
#define FAB_RESET_CNTR BIT_ULL(0)
drivers/fpga/dfl-fme-perf.c
59
#define FAB_FREEZE_CNTR BIT_ULL(8)
drivers/fpga/dfl-fme-perf.c
71
#define FAB_PORT_FILTER BIT_ULL(23)
drivers/fpga/dfl-fme-perf.c
93
#define VTD_RESET_CNTR BIT_ULL(0)
drivers/fpga/dfl-fme-perf.c
94
#define VTD_FREEZE_CNTR BIT_ULL(8)
drivers/fpga/dfl-n3000-nios.c
31
#define N3000_NS_PARAM_SHIFT_MODE_MSK BIT_ULL(1)
drivers/fpga/dfl-n3000-nios.c
36
#define N3000_NS_PARAM_CLK_POL BIT_ULL(14)
drivers/fpga/dfl-n3000-nios.c
37
#define N3000_NS_PARAM_CLK_PHASE BIT_ULL(15)
drivers/fpga/dfl-n3000-nios.c
50
#define N3000_NS_STAT_RW_VAL BIT_ULL(32)
drivers/fpga/dfl.h
105
#define DFHv1_CSR_SIZE_GRP_HAS_PARAMS BIT_ULL(31) /* Presence of Parameters */
drivers/fpga/dfl.h
112
#define DFHv1_PARAM_HDR_NEXT_EOP BIT_ULL(32)
drivers/fpga/dfl.h
135
#define FME_CAP_SOCKET_ID BIT_ULL(8) /* Socket ID */
drivers/fpga/dfl.h
136
#define FME_CAP_PCIE0_LINK_AVL BIT_ULL(12) /* PCIE0 Link */
drivers/fpga/dfl.h
137
#define FME_CAP_PCIE1_LINK_AVL BIT_ULL(13) /* PCIE1 Link */
drivers/fpga/dfl.h
138
#define FME_CAP_COHR_LINK_AVL BIT_ULL(14) /* Coherent Link */
drivers/fpga/dfl.h
139
#define FME_CAP_IOMMU_AVL BIT_ULL(16) /* IOMMU available */
drivers/fpga/dfl.h
151
#define FME_PORT_OFST_ACC_CTRL BIT_ULL(55)
drivers/fpga/dfl.h
154
#define FME_PORT_OFST_IMP BIT_ULL(60)
drivers/fpga/dfl.h
160
#define FME_ERROR_CAP_SUPP_INT BIT_ULL(0) /* Interrupt Support */
drivers/fpga/dfl.h
182
#define PORT_CTRL_SFTRST BIT_ULL(0) /* Port soft reset */
drivers/fpga/dfl.h
184
#define PORT_CTRL_LATENCY BIT_ULL(2)
drivers/fpga/dfl.h
185
#define PORT_CTRL_SFTRST_ACK BIT_ULL(4) /* HW ack for reset */
drivers/fpga/dfl.h
188
#define PORT_STS_AP2_EVT BIT_ULL(13) /* AP2 event detected */
drivers/fpga/dfl.h
189
#define PORT_STS_AP1_EVT BIT_ULL(12) /* AP1 event detected */
drivers/fpga/dfl.h
200
#define PORT_ERROR_CAP_SUPP_INT BIT_ULL(0) /* Interrupt Support */
drivers/fpga/dfl.h
77
#define DFH_EOL BIT_ULL(40) /* End of list */
drivers/fpga/dfl.h
97
#define DFHv1_CSR_ADDR_REL BIT_ULL(0)
drivers/fsi/fsi-master-i2cr.c
20
#define I2CR_STATUS_ERR BIT_ULL(61)
drivers/fsi/fsi-scom.c
48
#define XSCOM_ADDR_IND_FLAG BIT_ULL(63)
drivers/fsi/fsi-scom.c
49
#define XSCOM_ADDR_INF_FORM1 BIT_ULL(60)
drivers/fsi/fsi-scom.c
54
#define XSCOM_DATA_IND_READ BIT_ULL(63)
drivers/fsi/fsi-scom.c
55
#define XSCOM_DATA_IND_COMPLETE BIT_ULL(31)
drivers/gpio/gpio-thunderx.c
129
writeq(BIT_ULL(bank_bit), reg);
drivers/gpio/gpio-thunderx.c
266
u64 masked_bits = read_bits & BIT_ULL(bank_bit);
drivers/gpio/gpiolib-acpi-core.c
1171
gpiod_set_raw_value_cansleep(desc, value[word] & BIT_ULL(shift));
drivers/gpio/gpiolib-acpi-core.c
1174
value[word] |= BIT_ULL(shift);
drivers/gpio/gpiolib-acpi-core.c
1176
value[word] &= ~BIT_ULL(shift);
drivers/gpio/gpiolib-cdev.c
1101
u64 mask = BIT_ULL(line_idx);
drivers/gpio/gpiolib-cdev.c
1115
u64 mask = BIT_ULL(line_idx);
drivers/gpio/gpiolib-cdev.c
1271
if (lv.mask & BIT_ULL(i)) {
drivers/gpio/gpiolib-cdev.c
1287
if (lv.mask & BIT_ULL(i)) {
drivers/gpio/gpiolib-cdev.c
1304
if (lv.mask & BIT_ULL(i)) {
drivers/gpio/gpiolib-cdev.c
1310
lv.bits |= BIT_ULL(i);
drivers/gpio/gpiolib-cdev.c
1344
if (lv.mask & BIT_ULL(i)) {
drivers/gpio/gpiolib-cdev.c
1346
if (lv.bits & BIT_ULL(i))
drivers/gpio/gpiolib-cdev.c
1362
if (lv.mask & BIT_ULL(i)) {
drivers/gpio/gpiolib-cdev.c
951
u64 mask = BIT_ULL(line_idx);
drivers/gpio/gpiolib-cdev.c
965
u64 mask = BIT_ULL(line_idx);
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
374
if (val & (BIT_ULL((i * adev->jpeg.num_jpeg_rings) + j)))
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
524
RAS_SMU_FEATURE_BIT__RAS_EEPROM = BIT_ULL(0),
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
72
#define RAS_EVENT_INVALID_ID (BIT_ULL(63))
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
73
#define RAS_EVENT_ID_IS_VALID(x) (!((x) & BIT_ULL(63)))
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
371
mask = BIT_ULL(adev->sdma.num_instances * num_ring) - 1;
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
380
if (val & BIT_ULL(i * num_ring))
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
386
if (val & BIT_ULL(i * num_ring + 1))
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
421
mask |= BIT_ULL(i * num_ring);
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
423
mask &= ~BIT_ULL(i * num_ring);
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
427
mask |= BIT_ULL(i * num_ring + 1);
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
429
mask &= ~BIT_ULL(i * num_ring + 1);
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
72
#define UMC_CHANNEL_IDX_V2 BIT_ULL(47)
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
279
soc_pa &= ~BIT_ULL(flip_bits[i]);
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
286
row_lower &= ~BIT_ULL(adev->umc.flip_bits.flip_row_bit);
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
583
ecc_err->pa_pfn = BIT_ULL(shift_bit) >> AMDGPU_GPU_PAGE_SHIFT;
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
276
dpm_context->caps |= BIT_ULL(cap);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
284
dpm_context->caps &= ~BIT_ULL(cap);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
292
return !!(dpm_context->caps & BIT_ULL(cap));
drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c
127
row_pa &= ~BIT_ULL(flip_bits.flip_bits_in_pa[i]);
drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c
130
row_pa |= BIT_ULL(flip_bits.flip_bits_in_pa[2]);
drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c
156
row_lower &= ~BIT_ULL(flip_bits.flip_row_bit);
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
16
#define KOMEDA_EVENT_VSYNC BIT_ULL(0)
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
17
#define KOMEDA_EVENT_FLIP BIT_ULL(1)
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
18
#define KOMEDA_EVENT_URUN BIT_ULL(2)
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
19
#define KOMEDA_EVENT_IBSY BIT_ULL(3)
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
20
#define KOMEDA_EVENT_OVR BIT_ULL(4)
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
21
#define KOMEDA_EVENT_EOW BIT_ULL(5)
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
22
#define KOMEDA_EVENT_MODE BIT_ULL(6)
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
23
#define KOMEDA_EVENT_FULL BIT_ULL(7)
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
24
#define KOMEDA_EVENT_EMPTY BIT_ULL(8)
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
26
#define KOMEDA_ERR_TETO BIT_ULL(14)
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
27
#define KOMEDA_ERR_TEMR BIT_ULL(15)
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
28
#define KOMEDA_ERR_TITR BIT_ULL(16)
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
29
#define KOMEDA_ERR_CPE BIT_ULL(17)
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
30
#define KOMEDA_ERR_CFGE BIT_ULL(18)
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
31
#define KOMEDA_ERR_AXIE BIT_ULL(19)
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
32
#define KOMEDA_ERR_ACE0 BIT_ULL(20)
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
33
#define KOMEDA_ERR_ACE1 BIT_ULL(21)
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
34
#define KOMEDA_ERR_ACE2 BIT_ULL(22)
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
35
#define KOMEDA_ERR_ACE3 BIT_ULL(23)
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
36
#define KOMEDA_ERR_DRIFTTO BIT_ULL(24)
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
37
#define KOMEDA_ERR_FRAMETO BIT_ULL(25)
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
38
#define KOMEDA_ERR_CSCE BIT_ULL(26)
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
39
#define KOMEDA_ERR_ZME BIT_ULL(27)
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
40
#define KOMEDA_ERR_MERR BIT_ULL(28)
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
41
#define KOMEDA_ERR_TCF BIT_ULL(29)
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
42
#define KOMEDA_ERR_TTNG BIT_ULL(30)
drivers/gpu/drm/arm/display/komeda/komeda_dev.h
43
#define KOMEDA_ERR_TTF BIT_ULL(31)
drivers/gpu/drm/arm/malidp_crtc.c
226
u32 mag = ((((u64)val) & ~BIT_ULL(63)) >> 20) &
drivers/gpu/drm/arm/malidp_crtc.c
236
if (val & BIT_ULL(63))
drivers/gpu/drm/arm/malidp_crtc.c
238
if (!!(val & BIT_ULL(63)) != !!(mag & BIT(14)))
drivers/gpu/drm/drm_client_modeset.c
423
const u64 mask = BIT_ULL(connector_count) - 1;
drivers/gpu/drm/drm_client_modeset.c
441
if (conn_configured & BIT_ULL(i))
drivers/gpu/drm/drm_client_modeset.c
445
conn_configured |= BIT_ULL(i);
drivers/gpu/drm/drm_client_modeset.c
521
conn_configured |= BIT_ULL(i);
drivers/gpu/drm/drm_color_mgmt.c
138
u64 mag = (user_input & ~BIT_ULL(63)) >> (32 - n);
drivers/gpu/drm/drm_color_mgmt.c
139
bool negative = !!(user_input & BIT_ULL(63));
drivers/gpu/drm/drm_color_mgmt.c
145
BIT_ULL(n + m - 1) : BIT_ULL(n + m - 1) - 1);
drivers/gpu/drm/drm_edid.c
6058
if (vic && y420cmdb_map & BIT_ULL(i))
drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h
13
#define MASK(x) (BIT_ULL(x) - 1)
drivers/gpu/drm/i915/display/intel_display_power_map.c
1848
drm_WARN_ON(display->drm, power_well_ids & BIT_ULL(id));
drivers/gpu/drm/i915/display/intel_display_power_map.c
1849
power_well_ids |= BIT_ULL(id);
drivers/gpu/drm/i915/display/intel_fbc.c
805
return BIT_ULL(28);
drivers/gpu/drm/i915/display/intel_fbc.c
807
return BIT_ULL(32);
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
1680
min_t(u64, BIT_ULL(31), size - copied);
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
348
return (offset & BIT_ULL(bit)) >> (bit - 6);
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
43
return (offset & BIT_ULL(bit)) >> (bit - 6);
drivers/gpu/drm/i915/gt/gen8_ppgtt.c
310
GEM_BUG_ON(!IS_ALIGNED(start, BIT_ULL(GEN8_PTE_SHIFT)));
drivers/gpu/drm/i915/gt/gen8_ppgtt.c
311
GEM_BUG_ON(!IS_ALIGNED(length, BIT_ULL(GEN8_PTE_SHIFT)));
drivers/gpu/drm/i915/gt/gen8_ppgtt.c
394
GEM_BUG_ON(!IS_ALIGNED(start, BIT_ULL(GEN8_PTE_SHIFT)));
drivers/gpu/drm/i915/gt/gen8_ppgtt.c
395
GEM_BUG_ON(!IS_ALIGNED(length, BIT_ULL(GEN8_PTE_SHIFT)));
drivers/gpu/drm/i915/gt/intel_gtt.h
152
#define GEN8_PAGE_PRESENT BIT_ULL(0)
drivers/gpu/drm/i915/gt/intel_gtt.h
153
#define GEN8_PAGE_RW BIT_ULL(1)
drivers/gpu/drm/i915/gt/intel_gtt.h
45
#define I915_GTT_PAGE_SIZE_4K BIT_ULL(12)
drivers/gpu/drm/i915/gt/intel_gtt.h
46
#define I915_GTT_PAGE_SIZE_64K BIT_ULL(16)
drivers/gpu/drm/i915/gt/intel_gtt.h
47
#define I915_GTT_PAGE_SIZE_2M BIT_ULL(21)
drivers/gpu/drm/i915/gt/intel_gtt.h
91
#define MTL_PPGTT_PTE_PAT3 BIT_ULL(62)
drivers/gpu/drm/i915/gt/intel_gtt.h
92
#define GEN12_PPGTT_PTE_LM BIT_ULL(11)
drivers/gpu/drm/i915/gt/intel_gtt.h
93
#define GEN12_PPGTT_PTE_PAT2 BIT_ULL(7)
drivers/gpu/drm/i915/gt/intel_gtt.h
94
#define GEN12_PPGTT_PTE_PAT1 BIT_ULL(4)
drivers/gpu/drm/i915/gt/intel_gtt.h
95
#define GEN12_PPGTT_PTE_PAT0 BIT_ULL(3)
drivers/gpu/drm/i915/gt/intel_gtt.h
97
#define GEN12_GGTT_PTE_LM BIT_ULL(1)
drivers/gpu/drm/i915/gt/intel_gtt.h
98
#define MTL_GGTT_PTE_PAT0 BIT_ULL(52)
drivers/gpu/drm/i915/gt/intel_gtt.h
99
#define MTL_GGTT_PTE_PAT1 BIT_ULL(53)
drivers/gpu/drm/i915/gt/intel_lrc_reg.h
11
#define CTX_DESC_FORCE_RESTORE BIT_ULL(2)
drivers/gpu/drm/i915/gt/intel_ppgtt.c
220
return (size + 2 * (BIT_ULL(shift) - 1)) >> shift;
drivers/gpu/drm/i915/gt/intel_ppgtt.c
315
ppgtt->vm.total = BIT_ULL(RUNTIME_INFO(i915)->ppgtt_size);
drivers/gpu/drm/i915/gt/intel_rc6.c
809
overflow_hw = BIT_ULL(40);
drivers/gpu/drm/i915/gt/intel_rc6.c
821
overflow_hw = BIT_ULL(32);
drivers/gpu/drm/i915/gt/selftest_timeline.c
254
u64 ctx = BIT_ULL(order) + offset;
drivers/gpu/drm/i915/gt/selftest_timeline.c
267
u64 ctx = BIT_ULL(order) + offset;
drivers/gpu/drm/i915/gt/selftest_tlb.c
320
if (BIT_ULL(bit) < i915_vm_obj_min_alignment(va->vm, va->obj))
drivers/gpu/drm/i915/gt/selftest_tlb.c
325
BIT_ULL(bit),
drivers/gpu/drm/i915/gt/selftest_tlb.c
333
BIT_ULL(bit),
drivers/gpu/drm/i915/gt/selftest_tlb.c
335
BIT_ULL(len),
drivers/gpu/drm/i915/gt/selftest_tlb.c
67
addr = igt_random_offset(prng, addr, min(ce->vm->total, BIT_ULL(48)),
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
46
#define HOST_SESSION_PXP_SINGLE BIT_ULL(60)
drivers/gpu/drm/i915/i915_gem_gtt.h
41
#define PIN_NOEVICT BIT_ULL(0)
drivers/gpu/drm/i915/i915_gem_gtt.h
42
#define PIN_NOSEARCH BIT_ULL(1)
drivers/gpu/drm/i915/i915_gem_gtt.h
43
#define PIN_NONBLOCK BIT_ULL(2)
drivers/gpu/drm/i915/i915_gem_gtt.h
44
#define PIN_MAPPABLE BIT_ULL(3)
drivers/gpu/drm/i915/i915_gem_gtt.h
45
#define PIN_ZONE_4G BIT_ULL(4)
drivers/gpu/drm/i915/i915_gem_gtt.h
46
#define PIN_HIGH BIT_ULL(5)
drivers/gpu/drm/i915/i915_gem_gtt.h
47
#define PIN_OFFSET_BIAS BIT_ULL(6)
drivers/gpu/drm/i915/i915_gem_gtt.h
48
#define PIN_OFFSET_FIXED BIT_ULL(7)
drivers/gpu/drm/i915/i915_gem_gtt.h
49
#define PIN_OFFSET_GUARD BIT_ULL(8)
drivers/gpu/drm/i915/i915_gem_gtt.h
50
#define PIN_VALIDATE BIT_ULL(9) /* validate placement only, no need to call unpin() */
drivers/gpu/drm/i915/i915_gem_gtt.h
52
#define PIN_GLOBAL BIT_ULL(10) /* I915_VMA_GLOBAL_BIND */
drivers/gpu/drm/i915/i915_gem_gtt.h
53
#define PIN_USER BIT_ULL(11) /* I915_VMA_LOCAL_BIND */
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
287
GEM_BUG_ON(count * BIT_ULL(aligned_size) > vm->total);
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
288
GEM_BUG_ON(hole_start + count * BIT_ULL(aligned_size) > hole_end);
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
297
obj = fake_dma_object(vm->i915, BIT_ULL(size));
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
303
GEM_BUG_ON(obj->base.size != BIT_ULL(size));
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
312
u64 addr = hole_start + order[n] * BIT_ULL(aligned_size);
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
315
GEM_BUG_ON(addr + BIT_ULL(aligned_size) > vm->total);
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
337
BIT_ULL(size)))
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
343
addr, BIT_ULL(size));
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
358
mock_vma_res->node_size = BIT_ULL(aligned_size);
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
371
u64 addr = hole_start + order[n] * BIT_ULL(aligned_size);
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
374
GEM_BUG_ON(addr + BIT_ULL(size) > vm->total);
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
376
vm->clear_range(vm, addr, BIT_ULL(size));
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
749
u64 step = BIT_ULL(pot);
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
843
obj = fake_dma_object(vm->i915, BIT_ULL(size));
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
855
GEM_BUG_ON(vma->size != BIT_ULL(size));
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
858
u64 addr = hole_start + order[n] * BIT_ULL(aligned_size);
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
864
addr, BIT_ULL(size),
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
873
__func__, addr, BIT_ULL(size));
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
921
u64 size = BIT_ULL(order++);
drivers/gpu/drm/i915/selftests/i915_syncmap.c
297
u64 context = BIT_ULL(order);
drivers/gpu/drm/i915/selftests/i915_syncmap.c
346
u64 context = step * BIT_ULL(order);
drivers/gpu/drm/i915/selftests/i915_syncmap.c
363
u64 context = step * BIT_ULL(order);
drivers/gpu/drm/i915/selftests/i915_syncmap.c
385
u64 context = step * BIT_ULL(order);
drivers/gpu/drm/i915/selftests/i915_syncmap.c
469
u64 context = idx * BIT_ULL(order) + idx;
drivers/gpu/drm/i915/selftests/intel_memory_region.c
441
#define SZ_8G BIT_ULL(33)
drivers/gpu/drm/imagination/pvr_device_info.c
240
if (features[i >> 6] & BIT_ULL(i & 63)) {
drivers/gpu/drm/imagination/pvr_device_info.c
79
if (bitmask[i >> 6] & BIT_ULL(i & 63))
drivers/gpu/drm/imagination/pvr_gem.h
56
#define PVR_BO_CPU_CACHED BIT_ULL(63)
drivers/gpu/drm/imagination/pvr_gem.h
58
#define PVR_BO_FW_NO_CLEAR_ON_RESET BIT_ULL(62)
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
45
(((((u64)val) & ~BIT_ULL(63)) >> 17) & GENMASK_ULL(17, 0))
drivers/gpu/drm/msm/msm_iommu.c
685
if (iova & BIT_ULL(48))
drivers/gpu/drm/msm/msm_iommu.c
698
if (iova & BIT_ULL(48))
drivers/gpu/drm/nouveau/dispnv50/base907c.c
122
bool sign = in & BIT_ULL(63);
drivers/gpu/drm/nouveau/nvif/fifo.c
81
runm |= BIT_ULL(i);
drivers/gpu/drm/nouveau/nvkm/engine/sec2/ga102.c
115
.bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_FECS) |
drivers/gpu/drm/nouveau/nvkm/engine/sec2/ga102.c
116
BIT_ULL(NVKM_ACR_LSF_GPCCS) |
drivers/gpu/drm/nouveau/nvkm/engine/sec2/ga102.c
117
BIT_ULL(NVKM_ACR_LSF_SEC2),
drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c
115
.bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_FECS) |
drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c
116
BIT_ULL(NVKM_ACR_LSF_GPCCS) |
drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c
117
BIT_ULL(NVKM_ACR_LSF_SEC2),
drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c
276
.bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_FECS) |
drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c
277
BIT_ULL(NVKM_ACR_LSF_GPCCS) |
drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c
278
BIT_ULL(NVKM_ACR_LSF_SEC2),
drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c
177
if (acr->managed_falcons & BIT_ULL(id))
drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c
260
acr->managed_falcons |= BIT_ULL(lsf->id);
drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c
276
if (!(falcons & BIT_ULL(lsfw->id))) {
drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c
338
.bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_FECS) |
drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c
339
BIT_ULL(NVKM_ACR_LSF_GPCCS),
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c
729
if (!acpi_check_dsm(handle, &NVOP_DSM_GUID, NVOP_DSM_REV, BIT_ULL(0x1a)))
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/vmm.c
124
ctrl->levels[i].size = BIT_ULL(desc->bits) * desc->size;
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/vmm.c
79
const u64 page_size = BIT_ULL(page_shift);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c
117
data |= BIT_ULL(35); /* VOL */
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c
131
data |= BIT_ULL(34); /* VOL */
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c
349
base |= BIT_ULL(2) /* VOL. */;
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c
42
data |= BIT_ULL(60);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk104.c
29
VMM_FO064(pt, vmm, ptei * 8, BIT_ULL(1) /* PRIV. */, ptes);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.c
32
VMM_FO064(pt, vmm, ptei * 8, BIT_ULL(32) /* VOL. */, ptes);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.c
57
VMM_FO064(pt, vmm, pdei * 8, BIT_ULL(35) /* VOL_BIG. */, pdes);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.c
99
base |= BIT_ULL(11);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
100
data |= BIT_ULL(0); /* VALID. */
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
104
data |= BIT_ULL(0); /* VALID. */
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
183
VMM_FO064(pt, vmm, ptei * 8, BIT_ULL(3) /* VOL. */, ptes);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
203
VMM_FO064(pt, vmm, ptei * 8, BIT_ULL(5) /* PRIV. */, ptes);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
242
*data |= BIT_ULL(3); /* VOL. */
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
275
VMM_FO128(pt, vmm, pdei * 0x10, BIT_ULL(3) /* VOL_BIG. */, 0ULL, pdes);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
319
if ((data & BIT_ULL(0)) && (data & (3ULL << 1)) != 0) {
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
320
VMM_WO064(pt, vmm, ptei * 16, data & ~BIT_ULL(0));
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
344
data |= BIT_ULL(6); /* RO. */
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
347
data |= BIT_ULL(7); /* Atomic disable. */
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
356
data |= BIT_ULL(3); /* VOL. */
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
357
data |= BIT_ULL(0); /* VALID. */
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
361
data |= BIT_ULL(0); /* VALID. */
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
585
u64 base = BIT_ULL(10) /* VER2 */ | BIT_ULL(11) /* 64KiB */;
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
587
base |= BIT_ULL(4); /* FAULT_REPLAY_TEX */
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
588
base |= BIT_ULL(5); /* FAULT_REPLAY_GCC */
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
62
if ((data & BIT_ULL(0)) && (data & (3ULL << 1)) != 0) {
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
63
VMM_WO064(pt, vmm, ptei * 8, data & ~BIT_ULL(0));
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
87
data |= BIT_ULL(6); /* RO. */
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
90
data |= BIT_ULL(7); /* Atomic disable. */
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
99
data |= BIT_ULL(3); /* VOL. */
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.c
41
mask = BIT_ULL(0);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.c
46
if (mask & BIT_ULL(i)) {
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c
118
.bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_PMU) |
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c
119
BIT_ULL(NVKM_ACR_LSF_FECS) |
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c
120
BIT_ULL(NVKM_ACR_LSF_GPCCS),
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c
71
.bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_PMU) |
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c
72
BIT_ULL(NVKM_ACR_LSF_FECS) |
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c
73
BIT_ULL(NVKM_ACR_LSF_GPCCS),
drivers/gpu/drm/panfrost/panfrost_features.h
100
BIT_ULL(HW_FEATURE_JOBCHAIN_DISAMBIGUATION) | \
drivers/gpu/drm/panfrost/panfrost_features.h
101
BIT_ULL(HW_FEATURE_PWRON_DURING_PWROFF_TRANS) | \
drivers/gpu/drm/panfrost/panfrost_features.h
102
BIT_ULL(HW_FEATURE_XAFFINITY) | \
drivers/gpu/drm/panfrost/panfrost_features.h
103
BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT) | \
drivers/gpu/drm/panfrost/panfrost_features.h
104
BIT_ULL(HW_FEATURE_FLUSH_REDUCTION) | \
drivers/gpu/drm/panfrost/panfrost_features.h
105
BIT_ULL(HW_FEATURE_PROTECTED_MODE) | \
drivers/gpu/drm/panfrost/panfrost_features.h
106
BIT_ULL(HW_FEATURE_PROTECTED_DEBUG_MODE) | \
drivers/gpu/drm/panfrost/panfrost_features.h
107
BIT_ULL(HW_FEATURE_COHERENCY_REG) | \
drivers/gpu/drm/panfrost/panfrost_features.h
108
BIT_ULL(HW_FEATURE_AARCH64_MMU) | \
drivers/gpu/drm/panfrost/panfrost_features.h
109
BIT_ULL(HW_FEATURE_TLS_HASHING) | \
drivers/gpu/drm/panfrost/panfrost_features.h
110
BIT_ULL(HW_FEATURE_3BIT_EXT_RW_L2_MMU_CONFIG))
drivers/gpu/drm/panfrost/panfrost_features.h
113
BIT_ULL(HW_FEATURE_JOBCHAIN_DISAMBIGUATION) | \
drivers/gpu/drm/panfrost/panfrost_features.h
114
BIT_ULL(HW_FEATURE_PWRON_DURING_PWROFF_TRANS) | \
drivers/gpu/drm/panfrost/panfrost_features.h
115
BIT_ULL(HW_FEATURE_XAFFINITY) | \
drivers/gpu/drm/panfrost/panfrost_features.h
116
BIT_ULL(HW_FEATURE_FLUSH_REDUCTION) | \
drivers/gpu/drm/panfrost/panfrost_features.h
117
BIT_ULL(HW_FEATURE_PROTECTED_MODE) | \
drivers/gpu/drm/panfrost/panfrost_features.h
118
BIT_ULL(HW_FEATURE_PROTECTED_DEBUG_MODE) | \
drivers/gpu/drm/panfrost/panfrost_features.h
119
BIT_ULL(HW_FEATURE_COHERENCY_REG) | \
drivers/gpu/drm/panfrost/panfrost_features.h
120
BIT_ULL(HW_FEATURE_AARCH64_MMU) | \
drivers/gpu/drm/panfrost/panfrost_features.h
121
BIT_ULL(HW_FEATURE_IDVS_GROUP_SIZE) | \
drivers/gpu/drm/panfrost/panfrost_features.h
122
BIT_ULL(HW_FEATURE_CLEAN_ONLY_SAFE))
drivers/gpu/drm/panfrost/panfrost_features.h
29
BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT) | \
drivers/gpu/drm/panfrost/panfrost_features.h
30
BIT_ULL(HW_FEATURE_V4))
drivers/gpu/drm/panfrost/panfrost_features.h
37
BIT_ULL(HW_FEATURE_JOBCHAIN_DISAMBIGUATION) | \
drivers/gpu/drm/panfrost/panfrost_features.h
38
BIT_ULL(HW_FEATURE_PWRON_DURING_PWROFF_TRANS) | \
drivers/gpu/drm/panfrost/panfrost_features.h
39
BIT_ULL(HW_FEATURE_XAFFINITY) | \
drivers/gpu/drm/panfrost/panfrost_features.h
40
BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT))
drivers/gpu/drm/panfrost/panfrost_features.h
51
BIT_ULL(HW_FEATURE_JOBCHAIN_DISAMBIGUATION) | \
drivers/gpu/drm/panfrost/panfrost_features.h
52
BIT_ULL(HW_FEATURE_PWRON_DURING_PWROFF_TRANS) | \
drivers/gpu/drm/panfrost/panfrost_features.h
53
BIT_ULL(HW_FEATURE_XAFFINITY) | \
drivers/gpu/drm/panfrost/panfrost_features.h
54
BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT) | \
drivers/gpu/drm/panfrost/panfrost_features.h
55
BIT_ULL(HW_FEATURE_FLUSH_REDUCTION) | \
drivers/gpu/drm/panfrost/panfrost_features.h
56
BIT_ULL(HW_FEATURE_PROTECTED_MODE) | \
drivers/gpu/drm/panfrost/panfrost_features.h
57
BIT_ULL(HW_FEATURE_AARCH64_MMU) | \
drivers/gpu/drm/panfrost/panfrost_features.h
58
BIT_ULL(HW_FEATURE_COHERENCY_REG))
drivers/gpu/drm/panfrost/panfrost_features.h
61
BIT_ULL(HW_FEATURE_JOBCHAIN_DISAMBIGUATION) | \
drivers/gpu/drm/panfrost/panfrost_features.h
62
BIT_ULL(HW_FEATURE_PWRON_DURING_PWROFF_TRANS) | \
drivers/gpu/drm/panfrost/panfrost_features.h
63
BIT_ULL(HW_FEATURE_XAFFINITY) | \
drivers/gpu/drm/panfrost/panfrost_features.h
64
BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT) | \
drivers/gpu/drm/panfrost/panfrost_features.h
65
BIT_ULL(HW_FEATURE_FLUSH_REDUCTION) | \
drivers/gpu/drm/panfrost/panfrost_features.h
66
BIT_ULL(HW_FEATURE_PROTECTED_MODE) | \
drivers/gpu/drm/panfrost/panfrost_features.h
67
BIT_ULL(HW_FEATURE_PROTECTED_DEBUG_MODE) | \
drivers/gpu/drm/panfrost/panfrost_features.h
68
BIT_ULL(HW_FEATURE_AARCH64_MMU) | \
drivers/gpu/drm/panfrost/panfrost_features.h
69
BIT_ULL(HW_FEATURE_COHERENCY_REG))
drivers/gpu/drm/panfrost/panfrost_features.h
74
BIT_ULL(HW_FEATURE_JOBCHAIN_DISAMBIGUATION) | \
drivers/gpu/drm/panfrost/panfrost_features.h
75
BIT_ULL(HW_FEATURE_PWRON_DURING_PWROFF_TRANS) | \
drivers/gpu/drm/panfrost/panfrost_features.h
76
BIT_ULL(HW_FEATURE_XAFFINITY) | \
drivers/gpu/drm/panfrost/panfrost_features.h
77
BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT) | \
drivers/gpu/drm/panfrost/panfrost_features.h
78
BIT_ULL(HW_FEATURE_FLUSH_REDUCTION) | \
drivers/gpu/drm/panfrost/panfrost_features.h
79
BIT_ULL(HW_FEATURE_PROTECTED_MODE) | \
drivers/gpu/drm/panfrost/panfrost_features.h
80
BIT_ULL(HW_FEATURE_PROTECTED_DEBUG_MODE) | \
drivers/gpu/drm/panfrost/panfrost_features.h
81
BIT_ULL(HW_FEATURE_IDVS_GROUP_SIZE) | \
drivers/gpu/drm/panfrost/panfrost_features.h
82
BIT_ULL(HW_FEATURE_AARCH64_MMU) | \
drivers/gpu/drm/panfrost/panfrost_features.h
83
BIT_ULL(HW_FEATURE_COHERENCY_REG))
drivers/gpu/drm/panfrost/panfrost_features.h
86
BIT_ULL(HW_FEATURE_JOBCHAIN_DISAMBIGUATION) | \
drivers/gpu/drm/panfrost/panfrost_features.h
87
BIT_ULL(HW_FEATURE_PWRON_DURING_PWROFF_TRANS) | \
drivers/gpu/drm/panfrost/panfrost_features.h
88
BIT_ULL(HW_FEATURE_XAFFINITY) | \
drivers/gpu/drm/panfrost/panfrost_features.h
89
BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT) | \
drivers/gpu/drm/panfrost/panfrost_features.h
90
BIT_ULL(HW_FEATURE_FLUSH_REDUCTION) | \
drivers/gpu/drm/panfrost/panfrost_features.h
91
BIT_ULL(HW_FEATURE_PROTECTED_MODE) | \
drivers/gpu/drm/panfrost/panfrost_features.h
92
BIT_ULL(HW_FEATURE_PROTECTED_DEBUG_MODE) | \
drivers/gpu/drm/panfrost/panfrost_features.h
93
BIT_ULL(HW_FEATURE_COHERENCY_REG) | \
drivers/gpu/drm/panfrost/panfrost_features.h
94
BIT_ULL(HW_FEATURE_AARCH64_MMU) | \
drivers/gpu/drm/panfrost/panfrost_features.h
95
BIT_ULL(HW_FEATURE_TLS_HASHING) | \
drivers/gpu/drm/panfrost/panfrost_features.h
96
BIT_ULL(HW_FEATURE_IDVS_GROUP_SIZE) | \
drivers/gpu/drm/panfrost/panfrost_features.h
97
BIT_ULL(HW_FEATURE_3BIT_EXT_RW_L2_MMU_CONFIG))
drivers/gpu/drm/panfrost/panfrost_issues.h
142
BIT_ULL(HW_ISSUE_9435))
drivers/gpu/drm/panfrost/panfrost_issues.h
145
BIT_ULL(HW_ISSUE_6367) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
146
BIT_ULL(HW_ISSUE_6787) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
147
BIT_ULL(HW_ISSUE_8408) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
148
BIT_ULL(HW_ISSUE_9510) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
149
BIT_ULL(HW_ISSUE_10649) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
150
BIT_ULL(HW_ISSUE_10676) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
151
BIT_ULL(HW_ISSUE_10883) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
152
BIT_ULL(HW_ISSUE_11020) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
153
BIT_ULL(HW_ISSUE_11035) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
154
BIT_ULL(HW_ISSUE_11056) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
155
BIT_ULL(HW_ISSUE_TMIX_8438))
drivers/gpu/drm/panfrost/panfrost_issues.h
158
BIT_ULL(HW_ISSUE_8186) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
159
BIT_ULL(HW_ISSUE_8245) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
160
BIT_ULL(HW_ISSUE_8316) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
161
BIT_ULL(HW_ISSUE_8394) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
162
BIT_ULL(HW_ISSUE_8401) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
163
BIT_ULL(HW_ISSUE_8443) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
164
BIT_ULL(HW_ISSUE_8987) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
165
BIT_ULL(HW_ISSUE_9630) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
166
BIT_ULL(HW_ISSUE_10969) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
167
BIT_ULL(GPUCORE_1619))
drivers/gpu/drm/panfrost/panfrost_issues.h
170
BIT_ULL(HW_ISSUE_10649) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
171
BIT_ULL(HW_ISSUE_10883) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
172
BIT_ULL(HW_ISSUE_10959) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
173
BIT_ULL(HW_ISSUE_11056) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
174
BIT_ULL(HW_ISSUE_TMIX_8438))
drivers/gpu/drm/panfrost/panfrost_issues.h
177
BIT_ULL(HW_ISSUE_10327) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
178
BIT_ULL(HW_ISSUE_10676) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
179
BIT_ULL(HW_ISSUE_10817) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
180
BIT_ULL(HW_ISSUE_11020) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
181
BIT_ULL(HW_ISSUE_11024) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
182
BIT_ULL(HW_ISSUE_11035))
drivers/gpu/drm/panfrost/panfrost_issues.h
185
BIT_ULL(HW_ISSUE_11020) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
186
BIT_ULL(HW_ISSUE_11024))
drivers/gpu/drm/panfrost/panfrost_issues.h
189
BIT_ULL(HW_ISSUE_10649) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
190
BIT_ULL(HW_ISSUE_10797) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
191
BIT_ULL(HW_ISSUE_10883) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
192
BIT_ULL(HW_ISSUE_11056) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
193
BIT_ULL(HW_ISSUE_TMIX_8438))
drivers/gpu/drm/panfrost/panfrost_issues.h
196
BIT_ULL(HW_ISSUE_10883) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
197
BIT_ULL(HW_ISSUE_T76X_3953) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
198
BIT_ULL(HW_ISSUE_TMIX_8438))
drivers/gpu/drm/panfrost/panfrost_issues.h
201
BIT_ULL(HW_ISSUE_11020) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
202
BIT_ULL(HW_ISSUE_11024) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
203
BIT_ULL(HW_ISSUE_T76X_3542))
drivers/gpu/drm/panfrost/panfrost_issues.h
206
BIT_ULL(HW_ISSUE_11020) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
207
BIT_ULL(HW_ISSUE_11024) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
208
BIT_ULL(HW_ISSUE_T76X_3542))
drivers/gpu/drm/panfrost/panfrost_issues.h
211
BIT_ULL(HW_ISSUE_T76X_3542))
drivers/gpu/drm/panfrost/panfrost_issues.h
214
BIT_ULL(HW_ISSUE_11020) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
215
BIT_ULL(HW_ISSUE_11024) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
216
BIT_ULL(HW_ISSUE_T76X_3542))
drivers/gpu/drm/panfrost/panfrost_issues.h
219
BIT_ULL(HW_ISSUE_T76X_3542))
drivers/gpu/drm/panfrost/panfrost_issues.h
222
BIT_ULL(HW_ISSUE_10883) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
223
BIT_ULL(HW_ISSUE_T76X_3953) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
224
BIT_ULL(HW_ISSUE_TMIX_8438))
drivers/gpu/drm/panfrost/panfrost_issues.h
227
BIT_ULL(HW_ISSUE_10883) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
228
BIT_ULL(HW_ISSUE_T76X_3953) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
229
BIT_ULL(HW_ISSUE_TMIX_8438))
drivers/gpu/drm/panfrost/panfrost_issues.h
232
BIT_ULL(HW_ISSUE_10883) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
233
BIT_ULL(HW_ISSUE_T76X_3953) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
234
BIT_ULL(HW_ISSUE_TMIX_8438))
drivers/gpu/drm/panfrost/panfrost_issues.h
237
BIT_ULL(HW_ISSUE_10883) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
238
BIT_ULL(HW_ISSUE_T76X_3953) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
239
BIT_ULL(HW_ISSUE_TMIX_8438))
drivers/gpu/drm/panfrost/panfrost_issues.h
244
BIT_ULL(HW_ISSUE_TGOX_R1_1234))
drivers/gpu/drm/panfrost/panfrost_issues.h
251
BIT_ULL(HW_ISSUE_TMIX_8463) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
252
BIT_ULL(HW_ISSUE_TMIX_8438))
drivers/gpu/drm/panfrost/panfrost_issues.h
255
BIT_ULL(HW_ISSUE_T76X_3953))
drivers/gpu/drm/panfrost/panfrost_issues.h
262
BIT_ULL(HW_ISSUE_TTRX_2968_TTRX_3162) | \
drivers/gpu/drm/panfrost/panfrost_issues.h
263
BIT_ULL(HW_ISSUE_TTRX_3076))
drivers/gpu/drm/panfrost/panfrost_issues.h
266
BIT_ULL(HW_ISSUE_TTRX_3485))
drivers/gpu/drm/tegra/drm.h
26
#define DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT BIT_ULL(22)
drivers/gpu/drm/tegra/hub.c
638
addr_flag = BIT_ULL(39);
drivers/gpu/drm/tegra/submit.c
237
iova |= BIT_ULL(39);
drivers/gpu/drm/tests/drm_buddy_test.c
851
BIT_ULL(mm.max_order) * mm.chunk_size,
drivers/gpu/drm/tests/drm_buddy_test.c
854
BIT_ULL(mm.max_order) * mm.chunk_size);
drivers/gpu/drm/tests/drm_mm_test.c
261
align = BIT_ULL(bit);
drivers/gpu/drm/tests/drm_mm_test.c
262
size = BIT_ULL(bit - 1) + 1;
drivers/gpu/drm/vc4/vc4_kms.c
122
r = in & BIT_ULL(63) ? BIT(9) : 0;
drivers/gpu/drm/vc4/vc4_kms.c
634
val &= ~BIT_ULL(63);
drivers/gpu/drm/vc4/vc4_kms.c
635
if (val > BIT_ULL(32))
drivers/gpu/drm/virtio/virtgpu_submit.c
382
(vfpriv->ring_idx_mask & BIT_ULL(ring_idx)))
drivers/gpu/drm/xe/regs/xe_gtt_defs.h
10
#define XELPG_GGTT_PTE_PAT1 BIT_ULL(53)
drivers/gpu/drm/xe/regs/xe_gtt_defs.h
17
#define XELPG_PPGTT_PTE_PAT3 BIT_ULL(62)
drivers/gpu/drm/xe/regs/xe_gtt_defs.h
18
#define XE2_PPGTT_PTE_PAT4 BIT_ULL(61)
drivers/gpu/drm/xe/regs/xe_gtt_defs.h
19
#define XE_PPGTT_PDE_PDPE_PAT2 BIT_ULL(12)
drivers/gpu/drm/xe/regs/xe_gtt_defs.h
20
#define XE_PPGTT_PTE_PAT2 BIT_ULL(7)
drivers/gpu/drm/xe/regs/xe_gtt_defs.h
21
#define XE_PPGTT_PTE_PAT1 BIT_ULL(4)
drivers/gpu/drm/xe/regs/xe_gtt_defs.h
22
#define XE_PPGTT_PTE_PAT0 BIT_ULL(3)
drivers/gpu/drm/xe/regs/xe_gtt_defs.h
24
#define XE_PDE_PS_2M BIT_ULL(7)
drivers/gpu/drm/xe/regs/xe_gtt_defs.h
25
#define XE_PDPE_PS_1G BIT_ULL(7)
drivers/gpu/drm/xe/regs/xe_gtt_defs.h
26
#define XE_PDE_IPS_64K BIT_ULL(11)
drivers/gpu/drm/xe/regs/xe_gtt_defs.h
28
#define XE_GGTT_PTE_DM BIT_ULL(1)
drivers/gpu/drm/xe/regs/xe_gtt_defs.h
29
#define XE_USM_PPGTT_PTE_AE BIT_ULL(10)
drivers/gpu/drm/xe/regs/xe_gtt_defs.h
30
#define XE_PPGTT_PTE_DM BIT_ULL(11)
drivers/gpu/drm/xe/regs/xe_gtt_defs.h
31
#define XE_PDE_64K BIT_ULL(6)
drivers/gpu/drm/xe/regs/xe_gtt_defs.h
32
#define XE_PTE_PS64 BIT_ULL(8)
drivers/gpu/drm/xe/regs/xe_gtt_defs.h
33
#define XE_PTE_NULL BIT_ULL(9)
drivers/gpu/drm/xe/regs/xe_gtt_defs.h
35
#define XE_PAGE_PRESENT BIT_ULL(0)
drivers/gpu/drm/xe/regs/xe_gtt_defs.h
36
#define XE_PAGE_RW BIT_ULL(1)
drivers/gpu/drm/xe/regs/xe_gtt_defs.h
9
#define XELPG_GGTT_PTE_PAT0 BIT_ULL(52)
drivers/gpu/drm/xe/tests/xe_lmtt_test.c
48
u64 addr = BIT_ULL(ops->lmtt_pte_shift(n));
drivers/gpu/drm/xe/xe_bo.h
416
size_t max = BIT_ULL(sizeof(sg.length) * 8) - 1;
drivers/gpu/drm/xe/xe_configfs.c
1137
return get_gt_types_allowed(pdev) & BIT_ULL(XE_GT_TYPE_MAIN);
drivers/gpu/drm/xe/xe_configfs.c
1149
return get_gt_types_allowed(pdev) & BIT_ULL(XE_GT_TYPE_MEDIA);
drivers/gpu/drm/xe/xe_configfs.c
389
if (dev->gt_types_allowed & BIT_ULL(gt_types[i].type))
drivers/gpu/drm/xe/xe_configfs.c
494
*mask = BIT_ULL(bit);
drivers/gpu/drm/xe/xe_exec_queue.c
899
u64 secondary_queue_valid_props = BIT_ULL(DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP) |
drivers/gpu/drm/xe/xe_exec_queue.c
900
BIT_ULL(DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY);
drivers/gpu/drm/xe/xe_exec_queue.c
916
if ((properties & BIT_ULL(DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY)) &&
drivers/gpu/drm/xe/xe_exec_queue.c
917
!(properties & BIT_ULL(DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP)))
drivers/gpu/drm/xe/xe_exec_queue.c
951
*properties |= BIT_ULL(idx);
drivers/gpu/drm/xe/xe_gt.c
760
gt->user_engines.mask |= BIT_ULL(id);
drivers/gpu/drm/xe/xe_gt_idle.c
75
overflow_residency = BIT_ULL(32);
drivers/gpu/drm/xe/xe_lmtt.c
363
u64 pte_addr_shift = BIT_ULL(lmtt->ops->lmtt_pte_shift(pd->level));
drivers/gpu/drm/xe/xe_lmtt.c
57
return BIT_ULL(lmtt->ops->lmtt_pte_shift(0));
drivers/gpu/drm/xe/xe_lmtt_ml.c
109
BUILD_BUG_ON(BIT_ULL(LMTT_ML_PDE_L2_SHIFT) != SZ_32G);
drivers/gpu/drm/xe/xe_lmtt_ml.c
65
#define LMTT_ML_PDE_L2_MAX_NUM BIT_ULL(LMTT_ML_HAW - 35)
drivers/gpu/drm/xe/xe_lrc.c
35
#define LRC_VALID BIT_ULL(0)
drivers/gpu/drm/xe/xe_lrc.c
36
#define LRC_PRIVILEGE BIT_ULL(8)
drivers/gpu/drm/xe/xe_page_reclaim.h
28
#define XE_PAGE_RECLAIM_VALID BIT_ULL(0)
drivers/gpu/drm/xe/xe_pmu.c
170
pmu->supported_events & BIT_ULL(id);
drivers/gpu/drm/xe/xe_pmu.c
508
pmu->supported_events |= BIT_ULL(XE_PMU_EVENT_GT_C6_RESIDENCY);
drivers/gpu/drm/xe/xe_pmu.c
509
pmu->supported_events |= BIT_ULL(XE_PMU_EVENT_GT_ACTUAL_FREQUENCY);
drivers/gpu/drm/xe/xe_pmu.c
510
pmu->supported_events |= BIT_ULL(XE_PMU_EVENT_GT_REQUESTED_FREQUENCY);
drivers/gpu/drm/xe/xe_pmu.c
518
pmu->supported_events |= BIT_ULL(XE_PMU_EVENT_ENGINE_ACTIVE_TICKS);
drivers/gpu/drm/xe/xe_pmu.c
519
pmu->supported_events |= BIT_ULL(XE_PMU_EVENT_ENGINE_TOTAL_TICKS);
drivers/hid/hid-logitech-dj.c
91
#define HIDPP BIT_ULL(63)
drivers/hv/mshv_root_main.c
1898
if (args.pt_flags & BIT_ULL(MSHV_PT_BIT_CPU_AND_XSAVE_FEATURES)) {
drivers/hv/mshv_root_main.c
1951
if (args.pt_flags & BIT_ULL(MSHV_PT_BIT_LAPIC))
drivers/hv/mshv_root_main.c
1953
if (args.pt_flags & BIT_ULL(MSHV_PT_BIT_X2APIC))
drivers/hv/mshv_root_main.c
1955
if (args.pt_flags & BIT_ULL(MSHV_PT_BIT_GPA_SUPER_PAGES))
drivers/hv/mshv_vtl_main.c
43
#define MSHV_PG_OFF_CPU_MASK (BIT_ULL(MSHV_REAL_OFF_SHIFT) - 1)
drivers/hwmon/ltc4282.c
526
temp = power * 40 * DECA * st->vfs_out * BIT_ULL(8);
drivers/i2c/busses/i2c-octeon-core.h
14
#define SW_TWSI_V BIT_ULL(63) /* Valid bit */
drivers/i2c/busses/i2c-octeon-core.h
15
#define SW_TWSI_EIA BIT_ULL(61) /* Extended internal address */
drivers/i2c/busses/i2c-octeon-core.h
16
#define SW_TWSI_R BIT_ULL(56) /* Result or read bit */
drivers/i2c/busses/i2c-octeon-core.h
17
#define SW_TWSI_SOVR BIT_ULL(55) /* Size override */
drivers/i2c/busses/i2c-octeon-core.h
80
#define TWSI_INT_ST_INT BIT_ULL(0)
drivers/i2c/busses/i2c-octeon-core.h
81
#define TWSI_INT_TS_INT BIT_ULL(1)
drivers/i2c/busses/i2c-octeon-core.h
82
#define TWSI_INT_CORE_INT BIT_ULL(2)
drivers/i2c/busses/i2c-octeon-core.h
83
#define TWSI_INT_ST_EN BIT_ULL(4)
drivers/i2c/busses/i2c-octeon-core.h
84
#define TWSI_INT_TS_EN BIT_ULL(5)
drivers/i2c/busses/i2c-octeon-core.h
85
#define TWSI_INT_CORE_EN BIT_ULL(6)
drivers/i2c/busses/i2c-octeon-core.h
86
#define TWSI_INT_SDA_OVR BIT_ULL(8)
drivers/i2c/busses/i2c-octeon-core.h
87
#define TWSI_INT_SCL_OVR BIT_ULL(9)
drivers/i2c/busses/i2c-octeon-core.h
88
#define TWSI_INT_SDA BIT_ULL(10)
drivers/i2c/busses/i2c-octeon-core.h
89
#define TWSI_INT_SCL BIT_ULL(11)
drivers/iio/adc/xilinx-ams.c
449
scan_mask |= BIT_ULL(chan->scan_index);
drivers/infiniband/core/device.c
618
BIT_ULL(IB_USER_VERBS_CMD_ALLOC_MW) |
drivers/infiniband/core/device.c
619
BIT_ULL(IB_USER_VERBS_CMD_ALLOC_PD) |
drivers/infiniband/core/device.c
620
BIT_ULL(IB_USER_VERBS_CMD_ATTACH_MCAST) |
drivers/infiniband/core/device.c
621
BIT_ULL(IB_USER_VERBS_CMD_CLOSE_XRCD) |
drivers/infiniband/core/device.c
622
BIT_ULL(IB_USER_VERBS_CMD_CREATE_AH) |
drivers/infiniband/core/device.c
623
BIT_ULL(IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
drivers/infiniband/core/device.c
624
BIT_ULL(IB_USER_VERBS_CMD_CREATE_CQ) |
drivers/infiniband/core/device.c
625
BIT_ULL(IB_USER_VERBS_CMD_CREATE_QP) |
drivers/infiniband/core/device.c
626
BIT_ULL(IB_USER_VERBS_CMD_CREATE_SRQ) |
drivers/infiniband/core/device.c
627
BIT_ULL(IB_USER_VERBS_CMD_CREATE_XSRQ) |
drivers/infiniband/core/device.c
628
BIT_ULL(IB_USER_VERBS_CMD_DEALLOC_MW) |
drivers/infiniband/core/device.c
629
BIT_ULL(IB_USER_VERBS_CMD_DEALLOC_PD) |
drivers/infiniband/core/device.c
630
BIT_ULL(IB_USER_VERBS_CMD_DEREG_MR) |
drivers/infiniband/core/device.c
631
BIT_ULL(IB_USER_VERBS_CMD_DESTROY_AH) |
drivers/infiniband/core/device.c
632
BIT_ULL(IB_USER_VERBS_CMD_DESTROY_CQ) |
drivers/infiniband/core/device.c
633
BIT_ULL(IB_USER_VERBS_CMD_DESTROY_QP) |
drivers/infiniband/core/device.c
634
BIT_ULL(IB_USER_VERBS_CMD_DESTROY_SRQ) |
drivers/infiniband/core/device.c
635
BIT_ULL(IB_USER_VERBS_CMD_DETACH_MCAST) |
drivers/infiniband/core/device.c
636
BIT_ULL(IB_USER_VERBS_CMD_GET_CONTEXT) |
drivers/infiniband/core/device.c
637
BIT_ULL(IB_USER_VERBS_CMD_MODIFY_QP) |
drivers/infiniband/core/device.c
638
BIT_ULL(IB_USER_VERBS_CMD_MODIFY_SRQ) |
drivers/infiniband/core/device.c
639
BIT_ULL(IB_USER_VERBS_CMD_OPEN_QP) |
drivers/infiniband/core/device.c
640
BIT_ULL(IB_USER_VERBS_CMD_OPEN_XRCD) |
drivers/infiniband/core/device.c
641
BIT_ULL(IB_USER_VERBS_CMD_QUERY_DEVICE) |
drivers/infiniband/core/device.c
642
BIT_ULL(IB_USER_VERBS_CMD_QUERY_PORT) |
drivers/infiniband/core/device.c
643
BIT_ULL(IB_USER_VERBS_CMD_QUERY_QP) |
drivers/infiniband/core/device.c
644
BIT_ULL(IB_USER_VERBS_CMD_QUERY_SRQ) |
drivers/infiniband/core/device.c
645
BIT_ULL(IB_USER_VERBS_CMD_REG_MR) |
drivers/infiniband/core/device.c
646
BIT_ULL(IB_USER_VERBS_CMD_REREG_MR) |
drivers/infiniband/core/device.c
647
BIT_ULL(IB_USER_VERBS_CMD_RESIZE_CQ);
drivers/infiniband/core/uverbs_uapi.c
84
BIT_ULL(def->write.command_num));
drivers/infiniband/core/verbs.c
3179
block_offset = biter->__dma_addr & (BIT_ULL(biter->__pg_bit) - 1);
drivers/infiniband/core/verbs.c
3180
delta = BIT_ULL(biter->__pg_bit) - block_offset;
drivers/infiniband/hw/bnxt_re/bnxt_re.h
52
#define BNXT_RE_MAX_MR_SIZE_LOW BIT_ULL(BNXT_RE_PAGE_SHIFT_1G)
drivers/infiniband/hw/bnxt_re/bnxt_re.h
53
#define BNXT_RE_MAX_MR_SIZE_HIGH BIT_ULL(39)
drivers/infiniband/hw/bnxt_re/main.c
1423
ibdev->uverbs_cmd_mask |= BIT_ULL(IB_USER_VERBS_CMD_POLL_CQ);
drivers/infiniband/hw/erdma/erdma_hw.h
104
#define ERDMA_CQDB_ARM_MASK BIT_ULL(31)
drivers/infiniband/hw/erdma/erdma_hw.h
105
#define ERDMA_CQDB_SOL_MASK BIT_ULL(30)
drivers/infiniband/hw/erdma/erdma_hw.h
582
#define ERDMA_SQE_HDR_DWQE_MASK BIT_ULL(26)
drivers/infiniband/hw/erdma/erdma_hw.h
583
#define ERDMA_SQE_HDR_INLINE_MASK BIT_ULL(25)
drivers/infiniband/hw/erdma/erdma_hw.h
584
#define ERDMA_SQE_HDR_FENCE_MASK BIT_ULL(24)
drivers/infiniband/hw/erdma/erdma_hw.h
585
#define ERDMA_SQE_HDR_SE_MASK BIT_ULL(23)
drivers/infiniband/hw/erdma/erdma_hw.h
586
#define ERDMA_SQE_HDR_CE_MASK BIT_ULL(22)
drivers/infiniband/hw/erdma/erdma_hw.h
663
#define ERDMA_CEQE_HDR_DB_MASK BIT_ULL(63)
drivers/infiniband/hw/erdma/erdma_hw.h
665
#define ERDMA_CEQE_HDR_O_MASK BIT_ULL(31)
drivers/infiniband/hw/hfi1/chip.c
13210
bits |= BIT_ULL(bit);
drivers/infiniband/hw/hfi1/chip.c
5229
return !(mask & BIT_ULL(bit));
drivers/infiniband/hw/hfi1/chip.h
51
#define PBC_INTR BIT_ULL(31)
drivers/infiniband/hw/hfi1/chip.h
53
#define PBC_DC_INFO BIT_ULL(PBC_DC_INFO_SHIFT)
drivers/infiniband/hw/hfi1/chip.h
54
#define PBC_TEST_EBP BIT_ULL(29)
drivers/infiniband/hw/hfi1/chip.h
55
#define PBC_PACKET_BYPASS BIT_ULL(28)
drivers/infiniband/hw/hfi1/chip.h
56
#define PBC_CREDIT_RETURN BIT_ULL(25)
drivers/infiniband/hw/hfi1/chip.h
57
#define PBC_INSERT_BYPASS_ICRC BIT_ULL(24)
drivers/infiniband/hw/hfi1/chip.h
58
#define PBC_TEST_BAD_ICRC BIT_ULL(23)
drivers/infiniband/hw/hfi1/chip.h
59
#define PBC_FECN BIT_ULL(22)
drivers/infiniband/hw/hfi1/chip_registers.h
58
#define DCC_CFG_RESET_RESET_LCB BIT_ULL(0)
drivers/infiniband/hw/hfi1/chip_registers.h
59
#define DCC_CFG_RESET_RESET_TX_FPE BIT_ULL(1)
drivers/infiniband/hw/hfi1/chip_registers.h
60
#define DCC_CFG_RESET_RESET_RX_FPE BIT_ULL(2)
drivers/infiniband/hw/hfi1/chip_registers.h
61
#define DCC_CFG_RESET_RESET_8051 BIT_ULL(3)
drivers/infiniband/hw/hfi1/chip_registers.h
62
#define DCC_CFG_RESET_ENABLE_CCLK_BCC BIT_ULL(4)
drivers/infiniband/hw/hfi1/debugfs.c
995
#define EXPROM_WRITE_ENABLE BIT_ULL(14)
drivers/infiniband/hw/hfi1/pio.c
52
mask |= BIT_ULL(i);
drivers/infiniband/hw/hfi1/sdma.h
101
#define SDMA_DESC1_INT_REQ_FLAG BIT_ULL(1)
drivers/infiniband/hw/hfi1/sdma.h
102
#define SDMA_DESC1_HEAD_TO_HOST_FLAG BIT_ULL(0)
drivers/infiniband/hw/hfi1/sdma.h
56
#define SDMA_DESC0_FIRST_DESC_FLAG BIT_ULL(63)
drivers/infiniband/hw/hfi1/sdma.h
57
#define SDMA_DESC0_LAST_DESC_FLAG BIT_ULL(62)
drivers/infiniband/hw/hfi1/tid_rdma.c
30
#define RCV_TID_FLOW_TABLE_CTRL_FLOW_VALID_SMASK BIT_ULL(32)
drivers/infiniband/hw/hfi1/tid_rdma.c
31
#define RCV_TID_FLOW_TABLE_CTRL_HDR_SUPP_EN_SMASK BIT_ULL(33)
drivers/infiniband/hw/hfi1/tid_rdma.c
32
#define RCV_TID_FLOW_TABLE_CTRL_KEEP_AFTER_SEQ_ERR_SMASK BIT_ULL(34)
drivers/infiniband/hw/hfi1/tid_rdma.c
33
#define RCV_TID_FLOW_TABLE_CTRL_KEEP_ON_GEN_ERR_SMASK BIT_ULL(35)
drivers/infiniband/hw/hfi1/tid_rdma.c
34
#define RCV_TID_FLOW_TABLE_STATUS_SEQ_MISMATCH_SMASK BIT_ULL(37)
drivers/infiniband/hw/hfi1/tid_rdma.c
35
#define RCV_TID_FLOW_TABLE_STATUS_GEN_MISMATCH_SMASK BIT_ULL(38)
drivers/infiniband/hw/ionic/ionic_controlpath.c
29
if (q->size < BIT_ULL(q->depth_log2 + q->stride_log2))
drivers/infiniband/hw/ionic/ionic_pgtbl.c
12
u64 pg_mask = BIT_ULL(buf->page_size_log2) - 1;
drivers/infiniband/hw/ionic/ionic_pgtbl.c
32
u64 pg_mask = BIT_ULL(buf->page_size_log2) - 1;
drivers/infiniband/hw/ionic/ionic_pgtbl.c
82
rdma_umem_for_each_dma_block(umem, &biter, BIT_ULL(buf->page_size_log2)) {
drivers/infiniband/hw/ionic/ionic_queue.c
29
q->size = BIT_ULL(q->depth_log2 + q->stride_log2);
drivers/infiniband/hw/irdma/ctrl.c
3435
obj_info[rsrc_idx].size = BIT_ULL(size);
drivers/infiniband/hw/irdma/ctrl.c
3483
obj_info[IRDMA_HMC_IW_QP].size = BIT_ULL(size);
drivers/infiniband/hw/irdma/ctrl.c
3488
obj_info[IRDMA_HMC_IW_CQ].size = BIT_ULL(size);
drivers/infiniband/hw/irdma/ctrl.c
5031
u64 loc_mem_en = BIT_ULL(ENABLE_LOC_MEM);
drivers/infiniband/hw/irdma/defs.h
173
#define IRDMA_FEATURE_RTS_AE BIT_ULL(0)
drivers/infiniband/hw/irdma/defs.h
174
#define IRDMA_FEATURE_CQ_RESIZE BIT_ULL(1)
drivers/infiniband/hw/irdma/defs.h
175
#define IRDMA_FEATURE_64_BYTE_CQE BIT_ULL(5)
drivers/infiniband/hw/irdma/defs.h
176
#define IRDMA_FEATURE_ATOMIC_OPS BIT_ULL(6)
drivers/infiniband/hw/irdma/defs.h
177
#define IRDMA_FEATURE_SRQ BIT_ULL(7)
drivers/infiniband/hw/irdma/defs.h
178
#define IRDMA_FEATURE_CQE_TIMESTAMPING BIT_ULL(8)
drivers/infiniband/hw/irdma/defs.h
329
#define IRDMA_CQPSQ_QHASH_WQEVALID BIT_ULL(63)
drivers/infiniband/hw/irdma/defs.h
332
#define IRDMA_CQPSQ_QHASH_IPV4VALID BIT_ULL(60)
drivers/infiniband/hw/irdma/defs.h
333
#define IRDMA_CQPSQ_QHASH_VLANVALID BIT_ULL(59)
drivers/infiniband/hw/irdma/defs.h
335
#define IRDMA_CQPSQ_STATS_WQEVALID BIT_ULL(63)
drivers/infiniband/hw/irdma/defs.h
336
#define IRDMA_CQPSQ_STATS_ALLOC_INST BIT_ULL(62)
drivers/infiniband/hw/irdma/defs.h
337
#define IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX BIT_ULL(60)
drivers/infiniband/hw/irdma/defs.h
338
#define IRDMA_CQPSQ_STATS_USE_INST BIT_ULL(61)
drivers/infiniband/hw/irdma/defs.h
342
#define IRDMA_CQPSQ_WS_WQEVALID BIT_ULL(63)
drivers/infiniband/hw/irdma/defs.h
349
#define IRDMA_CQPSQ_WS_ENABLENODE BIT_ULL(62)
drivers/infiniband/hw/irdma/defs.h
350
#define IRDMA_CQPSQ_WS_NODETYPE BIT_ULL(61)
drivers/infiniband/hw/irdma/defs.h
361
#define IRDMA_CQPSQ_UP_WQEVALID BIT_ULL(63)
drivers/infiniband/hw/irdma/defs.h
362
#define IRDMA_CQPSQ_UP_USEVLAN BIT_ULL(62)
drivers/infiniband/hw/irdma/defs.h
363
#define IRDMA_CQPSQ_UP_USEOVERRIDE BIT_ULL(61)
drivers/infiniband/hw/irdma/defs.h
367
#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID BIT_ULL(63)
drivers/infiniband/hw/irdma/defs.h
374
#define IRDMA_CQPHC_DISABLE_PFPDUS BIT_ULL(1)
drivers/infiniband/hw/irdma/defs.h
375
#define IRDMA_CQPHC_ROCEV2_RTO_POLICY BIT_ULL(2)
drivers/infiniband/hw/irdma/defs.h
384
#define IRDMA_CQPHC_CC_CFG_VALID BIT_ULL(31)
drivers/infiniband/hw/irdma/defs.h
400
#define IRDMA_CQPHC_TIMESTAMP_OVERRIDE BIT_ULL(5)
drivers/infiniband/hw/irdma/defs.h
402
#define IRDMA_CQPHC_EN_FINE_GRAINED_TIMERS BIT_ULL(0)
drivers/infiniband/hw/irdma/defs.h
408
#define IRDMA_CQPHC_BLKSIZES_VALID BIT_ULL(4)
drivers/infiniband/hw/irdma/defs.h
414
#define IRDMA_CQ_DBSA_ARM_NEXT BIT_ULL(14)
drivers/infiniband/hw/irdma/defs.h
415
#define IRDMA_CQ_DBSA_ARM_NEXT_SE BIT_ULL(15)
drivers/infiniband/hw/irdma/defs.h
428
#define IRDMA_CQ_EXTCQE BIT_ULL(50)
drivers/infiniband/hw/irdma/defs.h
429
#define IRDMA_OOO_CMPL BIT_ULL(54)
drivers/infiniband/hw/irdma/defs.h
430
#define IRDMA_CQ_ERROR BIT_ULL(55)
drivers/infiniband/hw/irdma/defs.h
431
#define IRDMA_CQ_SQ BIT_ULL(62)
drivers/infiniband/hw/irdma/defs.h
433
#define IRDMA_CQ_SRQ BIT_ULL(52)
drivers/infiniband/hw/irdma/defs.h
434
#define IRDMA_CQ_VALID BIT_ULL(63)
drivers/infiniband/hw/irdma/defs.h
435
#define IRDMA_CQ_IMMVALID BIT_ULL(62)
drivers/infiniband/hw/irdma/defs.h
436
#define IRDMA_CQ_UDSMACVALID BIT_ULL(61)
drivers/infiniband/hw/irdma/defs.h
437
#define IRDMA_CQ_UDVLANVALID BIT_ULL(60)
drivers/infiniband/hw/irdma/defs.h
449
#define IRDMACQ_PSHDROP BIT_ULL(51)
drivers/infiniband/hw/irdma/defs.h
450
#define IRDMACQ_STAG BIT_ULL(53)
drivers/infiniband/hw/irdma/defs.h
451
#define IRDMACQ_IPV4 BIT_ULL(53)
drivers/infiniband/hw/irdma/defs.h
452
#define IRDMACQ_SOEVENT BIT_ULL(54)
drivers/infiniband/hw/irdma/defs.h
456
#define IRDMA_CEQE_VALID BIT_ULL(63)
drivers/infiniband/hw/irdma/defs.h
461
#define IRDMA_AEQE_QPCQID_HI BIT_ULL(46)
drivers/infiniband/hw/irdma/defs.h
463
#define IRDMA_AEQE_OVERFLOW BIT_ULL(33)
drivers/infiniband/hw/irdma/defs.h
469
#define IRDMA_AEQE_VALID BIT_ULL(63)
drivers/infiniband/hw/irdma/defs.h
475
#define IRDMA_AEQE_OVERFLOW_GEN_3 BIT_ULL(62)
drivers/infiniband/hw/irdma/defs.h
487
#define IRDMA_UDA_QPSQ_VALID BIT_ULL(63)
drivers/infiniband/hw/irdma/defs.h
488
#define IRDMA_UDA_QPSQ_SIGCOMPL BIT_ULL(62)
drivers/infiniband/hw/irdma/defs.h
495
#define IRDMA_VLAN_TAG_VALID BIT_ULL(50)
drivers/infiniband/hw/irdma/defs.h
498
#define IRDMA_UDA_QPSQ_DOLOOPBACK BIT_ULL(44)
drivers/infiniband/hw/irdma/defs.h
501
#define IRDMA_CQPSQ_WQEVALID BIT_ULL(63)
drivers/infiniband/hw/irdma/defs.h
505
#define IRDMA_CQPSQ_TPHEN BIT_ULL(60)
drivers/infiniband/hw/irdma/defs.h
510
#define IRDMA_CQPSQ_PASID_VALID BIT_ULL(62)
drivers/infiniband/hw/irdma/defs.h
524
#define IRDMA_CQPSQ_QP_ORDVALID BIT_ULL(42)
drivers/infiniband/hw/irdma/defs.h
525
#define IRDMA_CQPSQ_QP_TOECTXVALID BIT_ULL(43)
drivers/infiniband/hw/irdma/defs.h
526
#define IRDMA_CQPSQ_QP_CACHEDVARVALID BIT_ULL(44)
drivers/infiniband/hw/irdma/defs.h
527
#define IRDMA_CQPSQ_QP_VQ BIT_ULL(45)
drivers/infiniband/hw/irdma/defs.h
528
#define IRDMA_CQPSQ_QP_FORCELOOPBACK BIT_ULL(46)
drivers/infiniband/hw/irdma/defs.h
529
#define IRDMA_CQPSQ_QP_CQNUMVALID BIT_ULL(47)
drivers/infiniband/hw/irdma/defs.h
531
#define IRDMA_CQPSQ_QP_MACVALID BIT_ULL(51)
drivers/infiniband/hw/irdma/defs.h
532
#define IRDMA_CQPSQ_QP_MSSCHANGE BIT_ULL(52)
drivers/infiniband/hw/irdma/defs.h
534
#define IRDMA_CQPSQ_QP_IGNOREMWBOUND BIT_ULL(54)
drivers/infiniband/hw/irdma/defs.h
535
#define IRDMA_CQPSQ_QP_REMOVEHASHENTRY BIT_ULL(55)
drivers/infiniband/hw/irdma/defs.h
537
#define IRDMA_CQPSQ_QP_RESETCON BIT_ULL(58)
drivers/infiniband/hw/irdma/defs.h
538
#define IRDMA_CQPSQ_QP_ARPTABIDXVALID BIT_ULL(59)
drivers/infiniband/hw/irdma/defs.h
551
#define IRDMA_CQPSQ_SRQ_VIRTMAP BIT_ULL(47)
drivers/infiniband/hw/irdma/defs.h
552
#define IRDMA_CQPSQ_SRQ_TPH_EN BIT_ULL(60)
drivers/infiniband/hw/irdma/defs.h
553
#define IRDMA_CQPSQ_SRQ_ARM_LIMIT_EVENT BIT_ULL(61)
drivers/infiniband/hw/irdma/defs.h
568
#define IRDMA_CQPSQ_CQ_CQRESIZE BIT_ULL(43)
drivers/infiniband/hw/irdma/defs.h
570
#define IRDMA_CQPSQ_CQ_CHKOVERFLOW BIT_ULL(46)
drivers/infiniband/hw/irdma/defs.h
571
#define IRDMA_CQPSQ_CQ_VIRTMAP BIT_ULL(47)
drivers/infiniband/hw/irdma/defs.h
572
#define IRDMA_CQPSQ_CQ_ENCEQEMASK BIT_ULL(48)
drivers/infiniband/hw/irdma/defs.h
573
#define IRDMA_CQPSQ_CQ_CEQIDVALID BIT_ULL(49)
drivers/infiniband/hw/irdma/defs.h
574
#define IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT BIT_ULL(61)
drivers/infiniband/hw/irdma/defs.h
584
#define IRDMA_CQPSQ_STAG_MR BIT_ULL(43)
drivers/infiniband/hw/irdma/defs.h
585
#define IRDMA_CQPSQ_STAG_MWTYPE BIT_ULL(42)
drivers/infiniband/hw/irdma/defs.h
586
#define IRDMA_CQPSQ_STAG_MW1_BIND_DONT_VLDT_KEY BIT_ULL(58)
drivers/infiniband/hw/irdma/defs.h
592
#define IRDMA_CQPSQ_STAG_REMACCENABLED BIT_ULL(53)
drivers/infiniband/hw/irdma/defs.h
593
#define IRDMA_CQPSQ_STAG_VABASEDTO BIT_ULL(59)
drivers/infiniband/hw/irdma/defs.h
594
#define IRDMA_CQPSQ_STAG_USEHMCFNIDX BIT_ULL(60)
drivers/infiniband/hw/irdma/defs.h
595
#define IRDMA_CQPSQ_STAG_USEPFRID BIT_ULL(61)
drivers/infiniband/hw/irdma/defs.h
599
#define IRDMA_CQPSQ_STAG_REMOTE_ATOMIC_EN BIT_ULL(61)
drivers/infiniband/hw/irdma/defs.h
604
#define IRDMA_CQPSQ_MLM_FREEENTRY BIT_ULL(62)
drivers/infiniband/hw/irdma/defs.h
605
#define IRDMA_CQPSQ_MLM_IGNORE_REF_CNT BIT_ULL(61)
drivers/infiniband/hw/irdma/defs.h
615
#define IRDMA_CQPSQ_MAT_ENTRYVALID BIT_ULL(42)
drivers/infiniband/hw/irdma/defs.h
616
#define IRDMA_CQPSQ_MAT_PERMANENT BIT_ULL(43)
drivers/infiniband/hw/irdma/defs.h
617
#define IRDMA_CQPSQ_MAT_QUERY BIT_ULL(44)
drivers/infiniband/hw/irdma/defs.h
621
#define IRDMA_CQPSQ_MVPBP_INV_PD_ENT BIT_ULL(62)
drivers/infiniband/hw/irdma/defs.h
629
#define IRDMA_CQPSQ_MPP_FREE_PAGE BIT_ULL(62)
drivers/infiniband/hw/irdma/defs.h
636
#define IRDMA_CQPSQ_UCTX_RAWFORMAT BIT_ULL(61)
drivers/infiniband/hw/irdma/defs.h
637
#define IRDMA_CQPSQ_UCTX_FREEZEQP BIT_ULL(62)
drivers/infiniband/hw/irdma/defs.h
640
#define IRDMA_CQPSQ_MHMC_FREEPMFN BIT_ULL(62)
drivers/infiniband/hw/irdma/defs.h
650
#define IRDMA_CQPSQ_CEQ_VMAP BIT_ULL(47)
drivers/infiniband/hw/irdma/defs.h
651
#define IRDMA_CQPSQ_CEQ_ITRNOEXPIRE BIT_ULL(46)
drivers/infiniband/hw/irdma/defs.h
655
#define IRDMA_CQPSQ_AEQ_VMAP BIT_ULL(47)
drivers/infiniband/hw/irdma/defs.h
669
#define IRDMA_CQPSQ_FWQE_GENERATE_AE BIT_ULL(59)
drivers/infiniband/hw/irdma/defs.h
670
#define IRDMA_CQPSQ_FWQE_USERFLCODE BIT_ULL(60)
drivers/infiniband/hw/irdma/defs.h
671
#define IRDMA_CQPSQ_FWQE_FLUSHSQ BIT_ULL(61)
drivers/infiniband/hw/irdma/defs.h
672
#define IRDMA_CQPSQ_FWQE_FLUSHRQ BIT_ULL(62)
drivers/infiniband/hw/irdma/defs.h
673
#define IRDMA_CQPSQ_FWQE_ERR_SQ_IDX_VALID BIT_ULL(42)
drivers/infiniband/hw/irdma/defs.h
675
#define IRDMA_CQPSQ_FWQE_ERR_RQ_IDX_VALID BIT_ULL(43)
drivers/infiniband/hw/irdma/defs.h
678
#define IRDMA_CQPSQ_MAPT_ADDPORT BIT_ULL(62)
drivers/infiniband/hw/irdma/defs.h
683
#define IRDMA_CQPSQ_UPESD_ENTRY_VALID BIT_ULL(63)
drivers/infiniband/hw/irdma/defs.h
691
#define IRDMA_CQPSQ_UPESD_SKIP_ENTRY BIT_ULL(7)
drivers/infiniband/hw/irdma/defs.h
695
#define IRDMA_MANAGE_RSRC_VER2 BIT_ULL(2)
drivers/infiniband/hw/irdma/defs.h
707
#define IRDMAQPC_IBRDENABLE BIT_ULL(2)
drivers/infiniband/hw/irdma/defs.h
708
#define IRDMAQPC_IPV4 BIT_ULL(3)
drivers/infiniband/hw/irdma/defs.h
709
#define IRDMAQPC_NONAGLE BIT_ULL(4)
drivers/infiniband/hw/irdma/defs.h
710
#define IRDMAQPC_INSERTVLANTAG BIT_ULL(5)
drivers/infiniband/hw/irdma/defs.h
711
#define IRDMAQPC_ISQP1 BIT_ULL(6)
drivers/infiniband/hw/irdma/defs.h
712
#define IRDMAQPC_TIMESTAMP BIT_ULL(7)
drivers/infiniband/hw/irdma/defs.h
714
#define IRDMAQPC_INSERTL2TAG2 BIT_ULL(11)
drivers/infiniband/hw/irdma/defs.h
717
#define IRDMAQPC_USE_SRQ BIT_ULL(10)
drivers/infiniband/hw/irdma/defs.h
720
#define IRDMAQPC_PASID_VALID BIT_ULL(11)
drivers/infiniband/hw/irdma/defs.h
722
#define IRDMAQPC_ECN_EN BIT_ULL(14)
drivers/infiniband/hw/irdma/defs.h
723
#define IRDMAQPC_DROPOOOSEG BIT_ULL(15)
drivers/infiniband/hw/irdma/defs.h
725
#define IRDMAQPC_ERR_RQ_IDX_VALID BIT_ULL(19)
drivers/infiniband/hw/irdma/defs.h
727
#define IRDMAQPC_DC_TCP_EN BIT_ULL(25)
drivers/infiniband/hw/irdma/defs.h
728
#define IRDMAQPC_RCVTPHEN BIT_ULL(28)
drivers/infiniband/hw/irdma/defs.h
729
#define IRDMAQPC_XMITTPHEN BIT_ULL(29)
drivers/infiniband/hw/irdma/defs.h
730
#define IRDMAQPC_RQTPHEN BIT_ULL(30)
drivers/infiniband/hw/irdma/defs.h
731
#define IRDMAQPC_SQTPHEN BIT_ULL(31)
drivers/infiniband/hw/irdma/defs.h
733
#define IRDMAQPC_PMENA BIT_ULL(47)
drivers/infiniband/hw/irdma/defs.h
743
#define IRDMAQPC_AVOIDSTRETCHACK BIT_ULL(23)
drivers/infiniband/hw/irdma/defs.h
756
#define IRDMAQPC_WSCALE BIT_ULL(20)
drivers/infiniband/hw/irdma/defs.h
757
#define IRDMAQPC_KEEPALIVE BIT_ULL(21)
drivers/infiniband/hw/irdma/defs.h
758
#define IRDMAQPC_IGNORE_TCP_OPT BIT_ULL(22)
drivers/infiniband/hw/irdma/defs.h
759
#define IRDMAQPC_IGNORE_TCP_UNS_OPT BIT_ULL(23)
drivers/infiniband/hw/irdma/defs.h
809
#define IRDMAQPC_REMOTE_ATOMIC_EN BIT_ULL(18)
drivers/infiniband/hw/irdma/defs.h
817
#define IRDMAQPC_UDPRIVCQENABLE BIT_ULL(19)
drivers/infiniband/hw/irdma/defs.h
818
#define IRDMAQPC_WRRDRSPOK BIT_ULL(20)
drivers/infiniband/hw/irdma/defs.h
819
#define IRDMAQPC_RDOK BIT_ULL(21)
drivers/infiniband/hw/irdma/defs.h
820
#define IRDMAQPC_SNDMARKERS BIT_ULL(22)
drivers/infiniband/hw/irdma/defs.h
821
#define IRDMAQPC_DCQCNENABLE BIT_ULL(22)
drivers/infiniband/hw/irdma/defs.h
822
#define IRDMAQPC_FW_CC_ENABLE BIT_ULL(28)
drivers/infiniband/hw/irdma/defs.h
823
#define IRDMAQPC_RCVNOICRC BIT_ULL(31)
drivers/infiniband/hw/irdma/defs.h
824
#define IRDMAQPC_BINDEN BIT_ULL(23)
drivers/infiniband/hw/irdma/defs.h
825
#define IRDMAQPC_FASTREGEN BIT_ULL(24)
drivers/infiniband/hw/irdma/defs.h
826
#define IRDMAQPC_PRIVEN BIT_ULL(25)
drivers/infiniband/hw/irdma/defs.h
827
#define IRDMAQPC_TIMELYENABLE BIT_ULL(27)
drivers/infiniband/hw/irdma/defs.h
831
#define IRDMAQPC_USESTATSINSTANCE BIT_ULL(26)
drivers/infiniband/hw/irdma/defs.h
832
#define IRDMAQPC_IWARPMODE BIT_ULL(28)
drivers/infiniband/hw/irdma/defs.h
833
#define IRDMAQPC_RCVMARKERS BIT_ULL(29)
drivers/infiniband/hw/irdma/defs.h
834
#define IRDMAQPC_ALIGNHDRS BIT_ULL(30)
drivers/infiniband/hw/irdma/defs.h
835
#define IRDMAQPC_RCVNOMPACRC BIT_ULL(31)
drivers/infiniband/hw/irdma/defs.h
856
#define IRDMAQPSQ_COPY_HOST_PBL BIT_ULL(43)
drivers/infiniband/hw/irdma/defs.h
858
#define IRDMAQPSQ_PUSHWQE BIT_ULL(56)
drivers/infiniband/hw/irdma/defs.h
859
#define IRDMAQPSQ_STREAMMODE BIT_ULL(58)
drivers/infiniband/hw/irdma/defs.h
860
#define IRDMAQPSQ_WAITFORRCVPDU BIT_ULL(59)
drivers/infiniband/hw/irdma/defs.h
861
#define IRDMAQPSQ_READFENCE BIT_ULL(60)
drivers/infiniband/hw/irdma/defs.h
862
#define IRDMAQPSQ_LOCALFENCE BIT_ULL(61)
drivers/infiniband/hw/irdma/defs.h
863
#define IRDMAQPSQ_UDPHEADER BIT_ULL(61)
drivers/infiniband/hw/irdma/defs.h
865
#define IRDMAQPSQ_SIGCOMPL BIT_ULL(62)
drivers/infiniband/hw/irdma/defs.h
866
#define IRDMAQPSQ_VALID BIT_ULL(63)
drivers/infiniband/hw/irdma/defs.h
869
#define IRDMAQPSQ_FRAG_VALID BIT_ULL(63)
drivers/infiniband/hw/irdma/defs.h
878
#define IRDMAQPSQ_INLINEDATAFLAG BIT_ULL(57)
drivers/infiniband/hw/irdma/defs.h
882
#define IRDMAQPSQ_IMMDATAFLAG BIT_ULL(47)
drivers/infiniband/hw/irdma/defs.h
883
#define IRDMAQPSQ_REPORTRTT BIT_ULL(46)
drivers/infiniband/hw/irdma/defs.h
894
#define IRDMAQPSQ_VABASEDTO BIT_ULL(53)
drivers/infiniband/hw/irdma/defs.h
895
#define IRDMAQPSQ_MEMWINDOWTYPE BIT_ULL(54)
drivers/infiniband/hw/irdma/defs.h
903
#define IRDMAQPSQ_REMOTE_ATOMICS_EN BIT_ULL(55)
drivers/infiniband/hw/irdma/defs.h
909
#define IRDMAQPSQ_COPYHOSTPBLS BIT_ULL(43)
drivers/infiniband/hw/irdma/i40iw_hw.h
113
#define I40E_PFPE_CCQPSTATUS_CCQP_DONE BIT_ULL(0)
drivers/infiniband/hw/irdma/i40iw_hw.h
115
#define I40E_PFPE_CCQPSTATUS_CCQP_ERR BIT_ULL(31)
drivers/infiniband/hw/irdma/icrdma_hw.h
50
#define ICRDMA_CCQPSTATUS_CCQP_DONE BIT_ULL(0)
drivers/infiniband/hw/irdma/icrdma_hw.h
52
#define ICRDMA_CCQPSTATUS_CCQP_ERR BIT_ULL(31)
drivers/infiniband/hw/irdma/uda_d.h
101
#define IRDMA_UDA_MGCTX_VALIDENT BIT_ULL(31)
drivers/infiniband/hw/irdma/uda_d.h
103
#define IRDMA_UDA_MGCTX_FLAGIGNOREDPORT BIT_ULL(30)
drivers/infiniband/hw/irdma/uda_d.h
105
#define IRDMA_UDA_CQPSQ_MG_WQEVALID BIT_ULL(63)
drivers/infiniband/hw/irdma/uda_d.h
108
#define IRDMA_UDA_CQPSQ_MG_IPV4VALID BIT_ULL(60)
drivers/infiniband/hw/irdma/uda_d.h
109
#define IRDMA_UDA_CQPSQ_MG_VLANVALID BIT_ULL(59)
drivers/infiniband/hw/irdma/uda_d.h
114
#define IRDMA_UDA_CQPSQ_QHASH_ BIT_ULL(0)
drivers/infiniband/hw/irdma/uda_d.h
121
#define IRDMA_UDA_CQPSQ_QHASH_WQEVALID BIT_ULL(63)
drivers/infiniband/hw/irdma/uda_d.h
17
#define IRDMA_UDA_QPSQ_PUSHWQE BIT_ULL(56)
drivers/infiniband/hw/irdma/uda_d.h
18
#define IRDMA_UDA_QPSQ_INLINEDATAFLAG BIT_ULL(57)
drivers/infiniband/hw/irdma/uda_d.h
22
#define IRDMA_UDA_QPSQ_NOCHECKSUM BIT_ULL(45)
drivers/infiniband/hw/irdma/uda_d.h
23
#define IRDMA_UDA_QPSQ_AHIDXVALID BIT_ULL(46)
drivers/infiniband/hw/irdma/uda_d.h
24
#define IRDMA_UDA_QPSQ_LOCAL_FENCE BIT_ULL(61)
drivers/infiniband/hw/irdma/uda_d.h
28
#define IRDMA_UDA_QPSQ_MULTICAST BIT_ULL(63)
drivers/infiniband/hw/irdma/uda_d.h
39
#define IRDMA_UDA_QPSQ_FWD_PROG_CONFIRM BIT_ULL(45)
drivers/infiniband/hw/irdma/uda_d.h
44
#define IRDMA_UDAQPC_IPV4_M BIT_ULL(3)
drivers/infiniband/hw/irdma/uda_d.h
45
#define IRDMA_UDAQPC_INSERTVLANTAG BIT_ULL(5)
drivers/infiniband/hw/irdma/uda_d.h
46
#define IRDMA_UDAQPC_ISQP1 BIT_ULL(6)
drivers/infiniband/hw/irdma/uda_d.h
48
#define IRDMA_UDAQPC_ECNENABLE BIT_ULL(14)
drivers/infiniband/hw/irdma/uda_d.h
50
#define IRDMA_UDAQPC_DCTCPENABLE BIT_ULL(25)
drivers/infiniband/hw/irdma/uda_d.h
58
#define IRDMA_UDAQPC_INSERTTAG2 BIT_ULL(11)
drivers/infiniband/hw/irdma/uda_d.h
59
#define IRDMA_UDAQPC_INSERTTAG3 BIT_ULL(14)
drivers/infiniband/hw/irdma/uda_d.h
71
#define IRDMA_UDAQPC_PRIVILEGEENABLE BIT_ULL(25)
drivers/infiniband/hw/irdma/uda_d.h
72
#define IRDMA_UDAQPC_USE_STATISTICS_INSTANCE BIT_ULL(26)
drivers/infiniband/hw/irdma/uda_d.h
74
#define IRDMA_UDAQPC_PRIVHDRGENENABLE BIT_ULL(0)
drivers/infiniband/hw/irdma/uda_d.h
75
#define IRDMA_UDAQPC_RQHDRSPLITENABLE BIT_ULL(3)
drivers/infiniband/hw/irdma/uda_d.h
76
#define IRDMA_UDAQPC_RQHDRRINGBUFENABLE BIT_ULL(2)
drivers/infiniband/hw/irdma/uda_d.h
77
#define IRDMA_UDAQPC_SQHDRRINGBUFENABLE BIT_ULL(1)
drivers/infiniband/hw/irdma/uda_d.h
92
#define IRDMA_UDA_CQPSQ_MAV_WQEVALID BIT_ULL(63)
drivers/infiniband/hw/irdma/uda_d.h
94
#define IRDMA_UDA_CQPSQ_MAV_DOLOOPBACKK BIT_ULL(62)
drivers/infiniband/hw/irdma/uda_d.h
95
#define IRDMA_UDA_CQPSQ_MAV_IPV4VALID BIT_ULL(59)
drivers/infiniband/hw/irdma/uda_d.h
97
#define IRDMA_UDA_CQPSQ_MAV_INSERTVLANTAG BIT_ULL(60)
drivers/infiniband/hw/irdma/uda_d.h
98
#define IRDMA_UDA_MGCTX_VFFLAG BIT_ULL(29)
drivers/infiniband/hw/irdma/utils.c
2142
bits_needed = DIV_ROUND_UP_ULL(mem_size, BIT_ULL(pprm->pble_shift));
drivers/infiniband/hw/mlx5/odp.c
1936
mlx5_imr_mtt_size = BIT_ULL(mlx5_imr_mtt_shift);
drivers/infiniband/hw/mlx5/odp.c
1938
mlx5_imr_mtt_entries = BIT_ULL(mlx5_imr_mtt_bits);
drivers/infiniband/hw/mlx5/odp.c
1939
mlx5_imr_ksm_entries = BIT_ULL(get_order(TASK_SIZE) -
drivers/infiniband/hw/mlx5/odp.c
375
dev->odp_max_size = BIT_ULL(MLX5_MAX_UMR_SHIFT + PAGE_SHIFT);
drivers/infiniband/sw/rxe/rxe_verbs.c
1548
dev->uverbs_cmd_mask |= BIT_ULL(IB_USER_VERBS_CMD_POST_SEND) |
drivers/infiniband/sw/rxe/rxe_verbs.c
1549
BIT_ULL(IB_USER_VERBS_CMD_REQ_NOTIFY_CQ);
drivers/infiniband/sw/siw/siw_main.c
302
base_dev->uverbs_cmd_mask |= BIT_ULL(IB_USER_VERBS_CMD_POST_SEND);
drivers/iommu/amd/amd_iommu_types.h
103
#define FEATURE_GAM_VAPIC BIT_ULL(21)
drivers/iommu/amd/amd_iommu_types.h
105
#define FEATURE_GIOSUP BIT_ULL(48)
drivers/iommu/amd/amd_iommu_types.h
106
#define FEATURE_HASUP BIT_ULL(49)
drivers/iommu/amd/amd_iommu_types.h
107
#define FEATURE_EPHSUP BIT_ULL(50)
drivers/iommu/amd/amd_iommu_types.h
108
#define FEATURE_HDSUP BIT_ULL(52)
drivers/iommu/amd/amd_iommu_types.h
109
#define FEATURE_SNP BIT_ULL(63)
drivers/iommu/amd/amd_iommu_types.h
113
#define FEATURE_SEVSNPIO_SUP BIT_ULL(1)
drivers/iommu/amd/amd_iommu_types.h
114
#define FEATURE_GCR3TRPMODE BIT_ULL(3)
drivers/iommu/amd/amd_iommu_types.h
118
#define FEATURE_HT_RANGE_IGNORE BIT_ULL(11)
drivers/iommu/amd/amd_iommu_types.h
355
#define DTE_FLAG_V BIT_ULL(0)
drivers/iommu/amd/amd_iommu_types.h
356
#define DTE_FLAG_TV BIT_ULL(1)
drivers/iommu/amd/amd_iommu_types.h
360
#define DTE_FLAG_PPR BIT_ULL(52)
drivers/iommu/amd/amd_iommu_types.h
361
#define DTE_FLAG_GIOV BIT_ULL(54)
drivers/iommu/amd/amd_iommu_types.h
362
#define DTE_FLAG_GV BIT_ULL(55)
drivers/iommu/amd/amd_iommu_types.h
364
#define DTE_FLAG_IR BIT_ULL(61)
drivers/iommu/amd/amd_iommu_types.h
365
#define DTE_FLAG_IW BIT_ULL(62)
drivers/iommu/amd/amd_iommu_types.h
367
#define DTE_FLAG_IOTLB BIT_ULL(32)
drivers/iommu/amd/amd_iommu_types.h
91
#define FEATURE_PREFETCH BIT_ULL(0)
drivers/iommu/amd/amd_iommu_types.h
92
#define FEATURE_PPR BIT_ULL(1)
drivers/iommu/amd/amd_iommu_types.h
93
#define FEATURE_X2APIC BIT_ULL(2)
drivers/iommu/amd/amd_iommu_types.h
94
#define FEATURE_NX BIT_ULL(3)
drivers/iommu/amd/amd_iommu_types.h
95
#define FEATURE_GT BIT_ULL(4)
drivers/iommu/amd/amd_iommu_types.h
96
#define FEATURE_IA BIT_ULL(6)
drivers/iommu/amd/amd_iommu_types.h
97
#define FEATURE_GA BIT_ULL(7)
drivers/iommu/amd/amd_iommu_types.h
98
#define FEATURE_HE BIT_ULL(8)
drivers/iommu/amd/amd_iommu_types.h
99
#define FEATURE_PC BIT_ULL(9)
drivers/iommu/amd/init.c
932
(BIT_ULL(52)-1)) & ~7ULL;
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
326
map &= ~BIT_ULL(lidx);
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
352
if (vintf_map & BIT_ULL(0)) {
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
354
vintf_map &= ~BIT_ULL(0);
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
362
vintf_map &= ~BIT_ULL(idx);
drivers/iommu/generic_pt/fmt/amdv1.h
58
AMDV1PT_FMT_FC = BIT_ULL(60),
drivers/iommu/generic_pt/fmt/amdv1.h
59
AMDV1PT_FMT_IR = BIT_ULL(61),
drivers/iommu/generic_pt/fmt/amdv1.h
60
AMDV1PT_FMT_IW = BIT_ULL(62),
drivers/iommu/generic_pt/fmt/vtdss.h
185
return BIT_ULL((bitnr - 1) + 52);
drivers/iommu/generic_pt/fmt/vtdss.h
187
return BIT_ULL(63);
drivers/iommu/generic_pt/fmt/x86_64.h
188
return BIT_ULL((bitnr - 2) + 52);
drivers/iommu/generic_pt/fmt/x86_64.h
68
X86_64_FMT_XD = BIT_ULL(63),
drivers/iommu/generic_pt/kunit_generic_pt.h
168
KUNIT_ASSERT_EQ(test, ffs_t(u64, BIT_ULL(63)), 63);
drivers/iommu/generic_pt/kunit_generic_pt.h
171
KUNIT_ASSERT_EQ(test, ffz_t(u64, BIT_ULL(i) - 1), i);
drivers/iommu/generic_pt/kunit_generic_pt.h
174
KUNIT_ASSERT_EQ(test, ffz_t(u64, BIT_ULL(i) - 1), i);
drivers/iommu/intel/debugfs.c
305
return BIT_ULL(VTD_PAGE_SHIFT + VTD_STRIDE_SHIFT * (level - 1));
drivers/iommu/intel/debugfs.c
330
for (i = 0; i < BIT_ULL(VTD_STRIDE_SHIFT);
drivers/iommu/intel/dmar.c
1657
val |= BIT_ULL(11) | BIT_ULL(0);
drivers/iommu/intel/iommu.c
1549
iommu->copied_tables = bitmap_zalloc(BIT_ULL(16), GFP_KERNEL);
drivers/iommu/intel/iommu.c
659
level = pte->val[2] & BIT_ULL(2) ? 5 : 4;
drivers/iommu/intel/iommu.h
1011
context->lo |= BIT_ULL(2);
drivers/iommu/intel/iommu.h
1020
context->lo |= BIT_ULL(4);
drivers/iommu/intel/iommu.h
1029
context->lo &= ~BIT_ULL(4);
drivers/iommu/intel/iommu.h
1381
dw1 & BIT_ULL(0) ? 'r' : '-',
drivers/iommu/intel/iommu.h
1382
dw1 & BIT_ULL(1) ? 'w' : '-',
drivers/iommu/intel/iommu.h
1383
dw0 & BIT_ULL(52) ? 'x' : '-',
drivers/iommu/intel/iommu.h
1384
dw0 & BIT_ULL(53) ? 'p' : '-',
drivers/iommu/intel/iommu.h
1385
dw1 & BIT_ULL(2) ? 'l' : '-',
drivers/iommu/intel/iommu.h
1390
if (dw0 & BIT_ULL(9)) {
drivers/iommu/intel/iommu.h
323
#define DMA_ECMD_ECCAP3_ECNTS BIT_ULL(48)
drivers/iommu/intel/iommu.h
324
#define DMA_ECMD_ECCAP3_DCNTS BIT_ULL(49)
drivers/iommu/intel/iommu.h
325
#define DMA_ECMD_ECCAP3_FCNTS BIT_ULL(52)
drivers/iommu/intel/iommu.h
326
#define DMA_ECMD_ECCAP3_UFCNTS BIT_ULL(53)
drivers/iommu/intel/iommu.h
44
#define DMA_PTE_READ BIT_ULL(0)
drivers/iommu/intel/iommu.h
45
#define DMA_PTE_WRITE BIT_ULL(1)
drivers/iommu/intel/iommu.h
46
#define DMA_PTE_LARGE_PAGE BIT_ULL(7)
drivers/iommu/intel/iommu.h
47
#define DMA_PTE_SNP BIT_ULL(11)
drivers/iommu/intel/iommu.h
49
#define DMA_FL_PTE_PRESENT BIT_ULL(0)
drivers/iommu/intel/iommu.h
50
#define DMA_FL_PTE_US BIT_ULL(2)
drivers/iommu/intel/iommu.h
51
#define DMA_FL_PTE_ACCESS BIT_ULL(5)
drivers/iommu/intel/iommu.h
52
#define DMA_FL_PTE_DIRTY BIT_ULL(6)
drivers/iommu/intel/iommu.h
55
#define DMA_SL_PTE_DIRTY BIT_ULL(DMA_SL_PTE_DIRTY_BIT)
drivers/iommu/intel/iommu.h
63
#define CONTEXT_PASIDE BIT_ULL(3)
drivers/iommu/intel/perfmon.h
33
#define IOMMU_EVENT_CFG_INT BIT_ULL(1)
drivers/iommu/io-pgtable-arm-v7s.c
186
if (paddr & BIT_ULL(32))
drivers/iommu/io-pgtable-arm-v7s.c
188
if (paddr & BIT_ULL(33))
drivers/iommu/io-pgtable-arm-v7s.c
190
if (paddr & BIT_ULL(34))
drivers/iommu/io-pgtable-arm-v7s.c
224
paddr |= BIT_ULL(32);
drivers/iommu/io-pgtable-arm-v7s.c
226
paddr |= BIT_ULL(33);
drivers/iommu/io-pgtable-arm-v7s.c
228
paddr |= BIT_ULL(34);
drivers/iommu/mtk_iommu.c
819
paddr |= BIT_ULL(32);
drivers/iommu/mtk_iommu.c
871
pa &= ~BIT_ULL(32);
drivers/iommu/riscv/iommu-bits.h
205
#define RISCV_IOMMU_IOHPMCYCLES_OF BIT_ULL(63)
drivers/iommu/riscv/iommu-bits.h
215
#define RISCV_IOMMU_IOHPMEVT_DMASK BIT_ULL(15)
drivers/iommu/riscv/iommu-bits.h
218
#define RISCV_IOMMU_IOHPMEVT_PV_PSCV BIT_ULL(60)
drivers/iommu/riscv/iommu-bits.h
219
#define RISCV_IOMMU_IOHPMEVT_DV_GSCV BIT_ULL(61)
drivers/iommu/riscv/iommu-bits.h
220
#define RISCV_IOMMU_IOHPMEVT_IDT BIT_ULL(62)
drivers/iommu/riscv/iommu-bits.h
221
#define RISCV_IOMMU_IOHPMEVT_OF BIT_ULL(63)
drivers/iommu/riscv/iommu-bits.h
259
#define RISCV_IOMMU_TR_REQ_CTL_GO_BUSY BIT_ULL(0)
drivers/iommu/riscv/iommu-bits.h
260
#define RISCV_IOMMU_TR_REQ_CTL_PRIV BIT_ULL(1)
drivers/iommu/riscv/iommu-bits.h
261
#define RISCV_IOMMU_TR_REQ_CTL_EXE BIT_ULL(2)
drivers/iommu/riscv/iommu-bits.h
262
#define RISCV_IOMMU_TR_REQ_CTL_NW BIT_ULL(3)
drivers/iommu/riscv/iommu-bits.h
264
#define RISCV_IOMMU_TR_REQ_CTL_PV BIT_ULL(32)
drivers/iommu/riscv/iommu-bits.h
269
#define RISCV_IOMMU_TR_RESPONSE_FAULT BIT_ULL(0)
drivers/iommu/riscv/iommu-bits.h
271
#define RISCV_IOMMU_TR_RESPONSE_SZ BIT_ULL(9)
drivers/iommu/riscv/iommu-bits.h
291
#define RISCV_IOMMU_MSI_CFG_TBL_CTRL_M BIT_ULL(0)
drivers/iommu/riscv/iommu-bits.h
302
#define RISCV_IOMMU_DDTE_V BIT_ULL(0)
drivers/iommu/riscv/iommu-bits.h
335
#define RISCV_IOMMU_DC_TC_V BIT_ULL(0)
drivers/iommu/riscv/iommu-bits.h
336
#define RISCV_IOMMU_DC_TC_EN_ATS BIT_ULL(1)
drivers/iommu/riscv/iommu-bits.h
337
#define RISCV_IOMMU_DC_TC_EN_PRI BIT_ULL(2)
drivers/iommu/riscv/iommu-bits.h
338
#define RISCV_IOMMU_DC_TC_T2GPA BIT_ULL(3)
drivers/iommu/riscv/iommu-bits.h
339
#define RISCV_IOMMU_DC_TC_DTF BIT_ULL(4)
drivers/iommu/riscv/iommu-bits.h
340
#define RISCV_IOMMU_DC_TC_PDTV BIT_ULL(5)
drivers/iommu/riscv/iommu-bits.h
341
#define RISCV_IOMMU_DC_TC_PRPR BIT_ULL(6)
drivers/iommu/riscv/iommu-bits.h
342
#define RISCV_IOMMU_DC_TC_GADE BIT_ULL(7)
drivers/iommu/riscv/iommu-bits.h
343
#define RISCV_IOMMU_DC_TC_SADE BIT_ULL(8)
drivers/iommu/riscv/iommu-bits.h
344
#define RISCV_IOMMU_DC_TC_DPE BIT_ULL(9)
drivers/iommu/riscv/iommu-bits.h
345
#define RISCV_IOMMU_DC_TC_SBE BIT_ULL(10)
drivers/iommu/riscv/iommu-bits.h
346
#define RISCV_IOMMU_DC_TC_SXL BIT_ULL(11)
drivers/iommu/riscv/iommu-bits.h
42
#define RISCV_IOMMU_CAPABILITIES_SV32 BIT_ULL(8)
drivers/iommu/riscv/iommu-bits.h
43
#define RISCV_IOMMU_CAPABILITIES_SV39 BIT_ULL(9)
drivers/iommu/riscv/iommu-bits.h
430
#define RISCV_IOMMU_PC_TA_V BIT_ULL(0)
drivers/iommu/riscv/iommu-bits.h
431
#define RISCV_IOMMU_PC_TA_ENS BIT_ULL(1)
drivers/iommu/riscv/iommu-bits.h
432
#define RISCV_IOMMU_PC_TA_SUM BIT_ULL(2)
drivers/iommu/riscv/iommu-bits.h
44
#define RISCV_IOMMU_CAPABILITIES_SV48 BIT_ULL(10)
drivers/iommu/riscv/iommu-bits.h
45
#define RISCV_IOMMU_CAPABILITIES_SV57 BIT_ULL(11)
drivers/iommu/riscv/iommu-bits.h
46
#define RISCV_IOMMU_CAPABILITIES_SVPBMT BIT_ULL(15)
drivers/iommu/riscv/iommu-bits.h
47
#define RISCV_IOMMU_CAPABILITIES_SV32X4 BIT_ULL(16)
drivers/iommu/riscv/iommu-bits.h
470
#define RISCV_IOMMU_CMD_IOTINVAL_AV BIT_ULL(10)
drivers/iommu/riscv/iommu-bits.h
472
#define RISCV_IOMMU_CMD_IOTINVAL_PSCV BIT_ULL(32)
drivers/iommu/riscv/iommu-bits.h
473
#define RISCV_IOMMU_CMD_IOTINVAL_GV BIT_ULL(33)
drivers/iommu/riscv/iommu-bits.h
48
#define RISCV_IOMMU_CAPABILITIES_SV39X4 BIT_ULL(17)
drivers/iommu/riscv/iommu-bits.h
482
#define RISCV_IOMMU_CMD_IOFENCE_AV BIT_ULL(10)
drivers/iommu/riscv/iommu-bits.h
483
#define RISCV_IOMMU_CMD_IOFENCE_WSI BIT_ULL(11)
drivers/iommu/riscv/iommu-bits.h
484
#define RISCV_IOMMU_CMD_IOFENCE_PR BIT_ULL(12)
drivers/iommu/riscv/iommu-bits.h
485
#define RISCV_IOMMU_CMD_IOFENCE_PW BIT_ULL(13)
drivers/iommu/riscv/iommu-bits.h
49
#define RISCV_IOMMU_CAPABILITIES_SV48X4 BIT_ULL(18)
drivers/iommu/riscv/iommu-bits.h
495
#define RISCV_IOMMU_CMD_IODIR_DV BIT_ULL(33)
drivers/iommu/riscv/iommu-bits.h
50
#define RISCV_IOMMU_CAPABILITIES_SV57X4 BIT_ULL(19)
drivers/iommu/riscv/iommu-bits.h
505
#define RISCV_IOMMU_CMD_ATS_PV BIT_ULL(32)
drivers/iommu/riscv/iommu-bits.h
506
#define RISCV_IOMMU_CMD_ATS_DSV BIT_ULL(33)
drivers/iommu/riscv/iommu-bits.h
51
#define RISCV_IOMMU_CAPABILITIES_AMO_MRIF BIT_ULL(21)
drivers/iommu/riscv/iommu-bits.h
512
#define RISCV_IOMMU_CMD_ATS_INVAL_G BIT_ULL(0)
drivers/iommu/riscv/iommu-bits.h
514
#define RISCV_IOMMU_CMD_ATS_INVAL_S BIT_ULL(11)
drivers/iommu/riscv/iommu-bits.h
52
#define RISCV_IOMMU_CAPABILITIES_MSI_FLAT BIT_ULL(22)
drivers/iommu/riscv/iommu-bits.h
53
#define RISCV_IOMMU_CAPABILITIES_MSI_MRIF BIT_ULL(23)
drivers/iommu/riscv/iommu-bits.h
54
#define RISCV_IOMMU_CAPABILITIES_AMO_HWAD BIT_ULL(24)
drivers/iommu/riscv/iommu-bits.h
548
#define RISCV_IOMMU_FQ_HDR_PV BIT_ULL(32)
drivers/iommu/riscv/iommu-bits.h
549
#define RISCV_IOMMU_FQ_HDR_PRIV BIT_ULL(33)
drivers/iommu/riscv/iommu-bits.h
55
#define RISCV_IOMMU_CAPABILITIES_ATS BIT_ULL(25)
drivers/iommu/riscv/iommu-bits.h
56
#define RISCV_IOMMU_CAPABILITIES_T2GPA BIT_ULL(26)
drivers/iommu/riscv/iommu-bits.h
57
#define RISCV_IOMMU_CAPABILITIES_END BIT_ULL(27)
drivers/iommu/riscv/iommu-bits.h
59
#define RISCV_IOMMU_CAPABILITIES_HPM BIT_ULL(30)
drivers/iommu/riscv/iommu-bits.h
60
#define RISCV_IOMMU_CAPABILITIES_DBG BIT_ULL(31)
drivers/iommu/riscv/iommu-bits.h
62
#define RISCV_IOMMU_CAPABILITIES_PD8 BIT_ULL(38)
drivers/iommu/riscv/iommu-bits.h
63
#define RISCV_IOMMU_CAPABILITIES_PD17 BIT_ULL(39)
drivers/iommu/riscv/iommu-bits.h
64
#define RISCV_IOMMU_CAPABILITIES_PD20 BIT_ULL(40)
drivers/iommu/riscv/iommu-bits.h
663
#define RISCV_IOMMU_PQ_HDR_PV BIT_ULL(32)
drivers/iommu/riscv/iommu-bits.h
664
#define RISCV_IOMMU_PQ_HDR_PRIV BIT_ULL(33)
drivers/iommu/riscv/iommu-bits.h
665
#define RISCV_IOMMU_PQ_HDR_EXEC BIT_ULL(34)
drivers/iommu/riscv/iommu-bits.h
669
#define RISCV_IOMMU_PQ_PAYLOAD_R BIT_ULL(0)
drivers/iommu/riscv/iommu-bits.h
670
#define RISCV_IOMMU_PQ_PAYLOAD_W BIT_ULL(1)
drivers/iommu/riscv/iommu-bits.h
671
#define RISCV_IOMMU_PQ_PAYLOAD_L BIT_ULL(2)
drivers/iommu/riscv/iommu-bits.h
698
#define RISCV_IOMMU_MSIPTE_V BIT_ULL(0)
drivers/iommu/riscv/iommu-bits.h
702
#define RISCV_IOMMU_MSIPTE_C BIT_ULL(63)
drivers/iommu/riscv/iommu-bits.h
707
#define RISCV_IOMMU_MSIPTE_MRIF_NID_MSB BIT_ULL(60)
drivers/iommu/riscv/iommu-bits.h
89
#define RISCV_IOMMU_DDTP_BUSY BIT_ULL(4)
drivers/irqchip/irq-gic-v5-its.c
587
sz = BIT_ULL(device_id_bits) * sizeof(*devtab);
drivers/irqchip/irq-gic-v5.c
124
u64 hwirq_id_bit = BIT_ULL(d->hwirq % 64);
drivers/irqchip/irq-gic-v5.c
173
u64 hwirq_id_bit = BIT_ULL(d->hwirq % 64);
drivers/irqchip/irq-gic-v5.c
316
u64 bit = BIT_ULL(irq % 64);
drivers/irqchip/irq-gic-v5.c
354
u64 hwirq_id_bit = BIT_ULL(d->hwirq % 64);
drivers/irqchip/irq-gic-v5.c
509
u64 bit = BIT_ULL(hwirq % 64);
drivers/media/i2c/ds90ub960.c
3707
if (!(source_streams_mask & BIT_ULL(route->source_stream)))
drivers/media/i2c/ds90ub960.c
3712
sink_streams[nport] |= BIT_ULL(route->sink_stream);
drivers/media/i2c/ds90ub960.c
3804
if (!(source_streams_mask & BIT_ULL(route->source_stream)))
drivers/media/i2c/ds90ub960.c
3809
sink_streams[nport] |= BIT_ULL(route->sink_stream);
drivers/media/pci/ddbridge/ddbridge-regs.h
134
#define LNB_BUSY BIT_ULL(4)
drivers/media/pci/ddbridge/ddbridge-regs.h
135
#define LNB_TONE BIT_ULL(15)
drivers/media/pci/intel/ipu6/ipu6-isys-video.c
979
stream_mask |= BIT_ULL(av->source_stream);
drivers/media/platform/raspberrypi/rp1-cfe/cfe.c
1232
cfe->streams_mask |= BIT_ULL(route->sink_stream);
drivers/media/platform/renesas/rcar-csi2.c
1818
BIT_ULL(0));
drivers/media/platform/renesas/rcar-csi2.c
1830
v4l2_subdev_disable_streams(priv->remote, priv->remote_pad, BIT_ULL(0));
drivers/media/platform/renesas/rcar-isp/csisp.c
275
BIT_ULL(0));
drivers/media/platform/renesas/rcar-isp/csisp.c
284
v4l2_subdev_disable_streams(isp->remote, isp->remote_pad, BIT_ULL(0));
drivers/media/platform/renesas/rcar-vin/rcar-dma.c
1305
return v4l2_subdev_disable_streams(sd, pad->index, BIT_ULL(0));
drivers/media/platform/renesas/rcar-vin/rcar-dma.c
1316
ret = v4l2_subdev_enable_streams(sd, pad->index, BIT_ULL(0));
drivers/media/platform/rockchip/rkcif/rkcif-stream.c
284
mask = BIT_ULL(stream->id);
drivers/media/platform/rockchip/rkcif/rkcif-stream.c
311
mask = BIT_ULL(stream->id);
drivers/media/platform/st/stm32/stm32-csi.c
670
csidev->s_subdev_pad_nb, BIT_ULL(0));
drivers/media/platform/st/stm32/stm32-csi.c
703
csidev->s_subdev_pad_nb, BIT_ULL(0));
drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-bytecap.c
425
vcap->s_subdev_pad_nb, BIT_ULL(0));
drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-bytecap.c
493
vcap->s_subdev_pad_nb, BIT_ULL(0));
drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-byteproc.c
498
ret = v4l2_subdev_enable_streams(s_subdev, s_pad->index, BIT_ULL(0));
drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-byteproc.c
523
ret = v4l2_subdev_disable_streams(s_subdev, s_pad->index, BIT_ULL(0));
drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-input.c
437
ret = v4l2_subdev_enable_streams(s_subdev, s_pad->index, BIT_ULL(0));
drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-input.c
463
ret = v4l2_subdev_disable_streams(s_subdev, s_pad->index, BIT_ULL(0));
drivers/media/rc/imon_raw.c
61
bit = fls64(data & (BIT_ULL(offset) - 1));
drivers/media/rc/rc-ir-raw.c
324
i = BIT_ULL(n - 1);
drivers/media/rc/rc-ir-raw.c
595
u64 mask = BIT_ULL(protocol);
drivers/media/rc/rc-main.c
1803
rc_proto = BIT_ULL(rc_map->rc_proto);
drivers/media/v4l2-core/v4l2-ctrls-api.c
1233
if (i < BITS_PER_LONG_LONG && (ctrl->menu_skip_mask & BIT_ULL(i)))
drivers/media/v4l2-core/v4l2-ctrls-core.c
1403
(ctrl->menu_skip_mask & BIT_ULL(ptr.p_s32[idx])))
drivers/media/v4l2-core/v4l2-ctrls-core.c
1697
if (def < BITS_PER_LONG_LONG && (step & BIT_ULL(def)))
drivers/media/v4l2-core/v4l2-subdev.c
1386
*streams_mask |= BIT_ULL(route_stream);
drivers/media/v4l2-core/v4l2-subdev.c
1403
*streams_mask = BIT_ULL(0);
drivers/media/v4l2-core/v4l2-subdev.c
1451
if (!(sink_streams_mask & BIT_ULL(stream)))
drivers/media/v4l2-core/v4l2-subdev.c
2091
(*streams & BIT_ULL(route->sink_stream))) {
drivers/media/v4l2-core/v4l2-subdev.c
2092
streams0 |= BIT_ULL(route->sink_stream);
drivers/media/v4l2-core/v4l2-subdev.c
2093
streams1 |= BIT_ULL(route->source_stream);
drivers/media/v4l2-core/v4l2-subdev.c
2096
(*streams & BIT_ULL(route->source_stream))) {
drivers/media/v4l2-core/v4l2-subdev.c
2097
streams0 |= BIT_ULL(route->source_stream);
drivers/media/v4l2-core/v4l2-subdev.c
2098
streams1 |= BIT_ULL(route->sink_stream);
drivers/media/v4l2-core/v4l2-subdev.c
2253
*found_streams = BIT_ULL(0);
drivers/media/v4l2-core/v4l2-subdev.c
2255
(sd->enabled_pads & BIT_ULL(pad)) ? BIT_ULL(0) : 0;
drivers/media/v4l2-core/v4l2-subdev.c
2269
if (cfg->pad != pad || !(streams_mask & BIT_ULL(cfg->stream)))
drivers/media/v4l2-core/v4l2-subdev.c
2272
*found_streams |= BIT_ULL(cfg->stream);
drivers/media/v4l2-core/v4l2-subdev.c
2274
*enabled_streams |= BIT_ULL(cfg->stream);
drivers/media/v4l2-core/v4l2-subdev.c
2289
sd->enabled_pads |= BIT_ULL(pad);
drivers/media/v4l2-core/v4l2-subdev.c
2291
sd->enabled_pads &= ~BIT_ULL(pad);
drivers/media/v4l2-core/v4l2-subdev.c
2299
if (cfg->pad == pad && (streams_mask & BIT_ULL(cfg->stream)))
drivers/media/v4l2-core/v4l2-subdev.c
2473
if (!(sd->enabled_pads & ~BIT_ULL(pad)))
drivers/media/v4l2-core/v4l2-subdev.c
2530
source_mask |= BIT_ULL(route->source_stream);
drivers/media/v4l2-core/v4l2-subdev.c
2538
source_mask = BIT_ULL(0);
drivers/memory/dfl-emif.c
208
return (val & BIT_ULL(eattr->index)) ? attr->mode : 0;
drivers/memory/dfl-emif.c
70
!!(val & BIT_ULL(eattr->shift + eattr->index)));
drivers/memory/dfl-emif.c
85
clear_busy_msk = BIT_ULL(EMIF_STAT_CLEAR_BUSY_SFT + eattr->index);
drivers/memory/dfl-emif.c
86
clear_en_msk = BIT_ULL(EMIF_CTRL_CLEAR_EN_SFT + eattr->index);
drivers/misc/mrvl_cn10k_dpi.c
274
if (reg & BIT_ULL(vf))
drivers/misc/mrvl_cn10k_dpi.c
52
#define DPI_DMA_CONTROL_O_MODE BIT_ULL(14)
drivers/misc/mrvl_cn10k_dpi.c
53
#define DPI_DMA_CONTROL_LDWB BIT_ULL(32)
drivers/misc/mrvl_cn10k_dpi.c
54
#define DPI_DMA_CONTROL_WQECSMODE1 BIT_ULL(37)
drivers/misc/mrvl_cn10k_dpi.c
55
#define DPI_DMA_CONTROL_ZBWCSEN BIT_ULL(39)
drivers/misc/mrvl_cn10k_dpi.c
57
#define DPI_DMA_CONTROL_WQECSDIS BIT_ULL(47)
drivers/misc/mrvl_cn10k_dpi.c
58
#define DPI_DMA_CONTROL_PKT_EN BIT_ULL(56)
drivers/misc/mrvl_cn10k_dpi.c
61
#define DPI_CTL_EN BIT_ULL(0)
drivers/misc/mrvl_cn10k_dpi.c
62
#define DPI_DMA_CC_INT BIT_ULL(0)
drivers/misc/mrvl_cn10k_dpi.c
63
#define DPI_DMA_QRST BIT_ULL(0)
drivers/misc/mrvl_cn10k_dpi.c
65
#define DPI_REQQ_INT_INSTRFLT BIT_ULL(0)
drivers/misc/mrvl_cn10k_dpi.c
66
#define DPI_REQQ_INT_RDFLT BIT_ULL(1)
drivers/misc/mrvl_cn10k_dpi.c
67
#define DPI_REQQ_INT_WRFLT BIT_ULL(2)
drivers/misc/mrvl_cn10k_dpi.c
68
#define DPI_REQQ_INT_CSFLT BIT_ULL(3)
drivers/misc/mrvl_cn10k_dpi.c
69
#define DPI_REQQ_INT_INST_DBO BIT_ULL(4)
drivers/misc/mrvl_cn10k_dpi.c
70
#define DPI_REQQ_INT_INST_ADDR_NULL BIT_ULL(5)
drivers/misc/mrvl_cn10k_dpi.c
71
#define DPI_REQQ_INT_INST_FILL_INVAL BIT_ULL(6)
drivers/misc/mrvl_cn10k_dpi.c
72
#define DPI_REQQ_INT_INSTR_PSN BIT_ULL(7)
drivers/misc/mrvl_cn10k_dpi.c
84
#define DPI_PF_RAS_EBI_DAT_PSN BIT_ULL(0)
drivers/misc/mrvl_cn10k_dpi.c
85
#define DPI_PF_RAS_NCB_DAT_PSN BIT_ULL(1)
drivers/misc/mrvl_cn10k_dpi.c
86
#define DPI_PF_RAS_NCB_CMD_PSN BIT_ULL(2)
drivers/mmc/host/cavium-thunderx.c
126
writeq(BIT_ULL(16), host->base + MIO_EMM_DMA_FIFO_CFG(host));
drivers/mmc/host/cavium.c
396
writeq(BIT_ULL(16), host->dma_base + MIO_EMM_DMA_FIFO_CFG(host));
drivers/mmc/host/cavium.c
613
writeq(BIT_ULL(16), host->dma_base + MIO_EMM_DMA_FIFO_CFG(host));
drivers/mmc/host/cavium.h
120
#define MIO_EMM_DMA_FIFO_CFG_CLR BIT_ULL(16)
drivers/mmc/host/cavium.h
124
#define MIO_EMM_DMA_FIFO_CMD_RW BIT_ULL(62)
drivers/mmc/host/cavium.h
125
#define MIO_EMM_DMA_FIFO_CMD_INTDIS BIT_ULL(60)
drivers/mmc/host/cavium.h
126
#define MIO_EMM_DMA_FIFO_CMD_SWAP32 BIT_ULL(59)
drivers/mmc/host/cavium.h
127
#define MIO_EMM_DMA_FIFO_CMD_SWAP16 BIT_ULL(58)
drivers/mmc/host/cavium.h
128
#define MIO_EMM_DMA_FIFO_CMD_SWAP8 BIT_ULL(57)
drivers/mmc/host/cavium.h
129
#define MIO_EMM_DMA_FIFO_CMD_ENDIAN BIT_ULL(56)
drivers/mmc/host/cavium.h
132
#define MIO_EMM_CMD_SKIP_BUSY BIT_ULL(62)
drivers/mmc/host/cavium.h
134
#define MIO_EMM_CMD_VAL BIT_ULL(59)
drivers/mmc/host/cavium.h
135
#define MIO_EMM_CMD_DBUF BIT_ULL(55)
drivers/mmc/host/cavium.h
142
#define MIO_EMM_DMA_SKIP_BUSY BIT_ULL(62)
drivers/mmc/host/cavium.h
144
#define MIO_EMM_DMA_VAL BIT_ULL(59)
drivers/mmc/host/cavium.h
145
#define MIO_EMM_DMA_SECTOR BIT_ULL(58)
drivers/mmc/host/cavium.h
146
#define MIO_EMM_DMA_DAT_NULL BIT_ULL(57)
drivers/mmc/host/cavium.h
148
#define MIO_EMM_DMA_REL_WR BIT_ULL(50)
drivers/mmc/host/cavium.h
149
#define MIO_EMM_DMA_RW BIT_ULL(49)
drivers/mmc/host/cavium.h
150
#define MIO_EMM_DMA_MULTI BIT_ULL(48)
drivers/mmc/host/cavium.h
154
#define MIO_EMM_DMA_CFG_EN BIT_ULL(63)
drivers/mmc/host/cavium.h
155
#define MIO_EMM_DMA_CFG_RW BIT_ULL(62)
drivers/mmc/host/cavium.h
156
#define MIO_EMM_DMA_CFG_CLR BIT_ULL(61)
drivers/mmc/host/cavium.h
157
#define MIO_EMM_DMA_CFG_SWAP32 BIT_ULL(59)
drivers/mmc/host/cavium.h
158
#define MIO_EMM_DMA_CFG_SWAP16 BIT_ULL(58)
drivers/mmc/host/cavium.h
159
#define MIO_EMM_DMA_CFG_SWAP8 BIT_ULL(57)
drivers/mmc/host/cavium.h
160
#define MIO_EMM_DMA_CFG_ENDIAN BIT_ULL(56)
drivers/mmc/host/cavium.h
164
#define MIO_EMM_INT_SWITCH_ERR BIT_ULL(6)
drivers/mmc/host/cavium.h
165
#define MIO_EMM_INT_SWITCH_DONE BIT_ULL(5)
drivers/mmc/host/cavium.h
166
#define MIO_EMM_INT_DMA_ERR BIT_ULL(4)
drivers/mmc/host/cavium.h
167
#define MIO_EMM_INT_CMD_ERR BIT_ULL(3)
drivers/mmc/host/cavium.h
168
#define MIO_EMM_INT_DMA_DONE BIT_ULL(2)
drivers/mmc/host/cavium.h
169
#define MIO_EMM_INT_CMD_DONE BIT_ULL(1)
drivers/mmc/host/cavium.h
170
#define MIO_EMM_INT_BUF_DONE BIT_ULL(0)
drivers/mmc/host/cavium.h
173
#define MIO_EMM_RSP_STS_CMD_VAL BIT_ULL(59)
drivers/mmc/host/cavium.h
174
#define MIO_EMM_RSP_STS_SWITCH_VAL BIT_ULL(58)
drivers/mmc/host/cavium.h
175
#define MIO_EMM_RSP_STS_DMA_VAL BIT_ULL(57)
drivers/mmc/host/cavium.h
176
#define MIO_EMM_RSP_STS_DMA_PEND BIT_ULL(56)
drivers/mmc/host/cavium.h
177
#define MIO_EMM_RSP_STS_DBUF_ERR BIT_ULL(28)
drivers/mmc/host/cavium.h
178
#define MIO_EMM_RSP_STS_DBUF BIT_ULL(23)
drivers/mmc/host/cavium.h
179
#define MIO_EMM_RSP_STS_BLK_TIMEOUT BIT_ULL(22)
drivers/mmc/host/cavium.h
180
#define MIO_EMM_RSP_STS_BLK_CRC_ERR BIT_ULL(21)
drivers/mmc/host/cavium.h
181
#define MIO_EMM_RSP_STS_RSP_BUSYBIT BIT_ULL(20)
drivers/mmc/host/cavium.h
182
#define MIO_EMM_RSP_STS_STP_TIMEOUT BIT_ULL(19)
drivers/mmc/host/cavium.h
183
#define MIO_EMM_RSP_STS_STP_CRC_ERR BIT_ULL(18)
drivers/mmc/host/cavium.h
184
#define MIO_EMM_RSP_STS_STP_BAD_STS BIT_ULL(17)
drivers/mmc/host/cavium.h
185
#define MIO_EMM_RSP_STS_STP_VAL BIT_ULL(16)
drivers/mmc/host/cavium.h
186
#define MIO_EMM_RSP_STS_RSP_TIMEOUT BIT_ULL(15)
drivers/mmc/host/cavium.h
187
#define MIO_EMM_RSP_STS_RSP_CRC_ERR BIT_ULL(14)
drivers/mmc/host/cavium.h
188
#define MIO_EMM_RSP_STS_RSP_BAD_STS BIT_ULL(13)
drivers/mmc/host/cavium.h
189
#define MIO_EMM_RSP_STS_RSP_VAL BIT_ULL(12)
drivers/mmc/host/cavium.h
193
#define MIO_EMM_RSP_STS_CMD_DONE BIT_ULL(0)
drivers/mmc/host/cavium.h
199
#define MIO_EMM_SWITCH_EXE BIT_ULL(59)
drivers/mmc/host/cavium.h
200
#define MIO_EMM_SWITCH_ERR0 BIT_ULL(58)
drivers/mmc/host/cavium.h
201
#define MIO_EMM_SWITCH_ERR1 BIT_ULL(57)
drivers/mmc/host/cavium.h
202
#define MIO_EMM_SWITCH_ERR2 BIT_ULL(56)
drivers/mmc/host/cavium.h
203
#define MIO_EMM_SWITCH_HS_TIMING BIT_ULL(48)
drivers/mmc/host/mtk-sd.c
2168
return delay & BIT_ULL(bit);
drivers/mmc/host/mtk-sd.c
2323
rise_delay |= BIT_ULL(i);
drivers/mmc/host/mtk-sd.c
2325
rise_delay &= ~BIT_ULL(i);
drivers/mmc/host/mtk-sd.c
2347
fall_delay |= BIT_ULL(i);
drivers/mmc/host/mtk-sd.c
2349
fall_delay &= ~BIT_ULL(i);
drivers/mmc/host/mtk-sd.c
2377
internal_delay |= BIT_ULL(i);
drivers/mmc/host/mtk-sd.c
2454
rise_delay |= BIT_ULL(i);
drivers/mmc/host/mtk-sd.c
2467
fall_delay |= BIT_ULL(i);
drivers/mmc/host/mtk-sd.c
2508
rise_delay |= BIT_ULL(i);
drivers/mmc/host/mtk-sd.c
2523
fall_delay |= BIT_ULL(i);
drivers/mtd/nand/raw/cadence-nand-controller.c
305
#define GCMD_LAY_TWB BIT_ULL(6)
drivers/mtd/nand/raw/cadence-nand-controller.c
325
#define GCMD_DIR BIT_ULL(11)
drivers/mtd/nand/raw/cadence-nand-controller.c
332
#define GCMD_ECC_EN BIT_ULL(12)
drivers/mtd/nand/raw/meson_nand.c
573
*correct_bitmap |= BIT_ULL(i);
drivers/mtd/nand/raw/meson_nand.c
910
if (correct_bitmap & BIT_ULL(i))
drivers/net/can/dev/rx-offload.c
186
if (!(pending & BIT_ULL(i)))
drivers/net/can/flexcan/flexcan-core.c
180
#define FLEXCAN_IFLAG_MB(x) BIT_ULL(x)
drivers/net/can/usb/peak_usb/pcan_usb_core.c
186
delta_ts = BIT_ULL(time_ref->adapter->ts_used_bits);
drivers/net/can/usb/peak_usb/pcan_usb_core.c
198
delta_ts = -BIT_ULL(time_ref->adapter->ts_used_bits);
drivers/net/dsa/b53/b53_regs.h
335
#define ARLTBL_AGE_25 BIT_ULL(61)
drivers/net/dsa/b53/b53_regs.h
336
#define ARLTBL_STATIC_25 BIT_ULL(62)
drivers/net/dsa/b53/b53_regs.h
337
#define ARLTBL_VALID_25 BIT_ULL(63)
drivers/net/dsa/microchip/ksz9477_tc_flower.c
119
~(BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
drivers/net/dsa/microchip/ksz9477_tc_flower.c
120
BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
drivers/net/dsa/microchip/ksz9477_tc_flower.c
121
BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL))) {
drivers/net/dsa/ocelot/felix_vsc9959.c
1764
~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
drivers/net/dsa/ocelot/felix_vsc9959.c
1765
BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
drivers/net/dsa/ocelot/felix_vsc9959.c
1766
BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) |
drivers/net/dsa/ocelot/felix_vsc9959.c
1767
BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS)))
drivers/net/dsa/sja1105/sja1105_flower.c
208
~(BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
drivers/net/dsa/sja1105/sja1105_flower.c
209
BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
drivers/net/dsa/sja1105/sja1105_flower.c
210
BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) |
drivers/net/dsa/sja1105/sja1105_flower.c
211
BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS))) {
drivers/net/dsa/yt921x.h
434
#define YT921X_VLAN_CTRL_UNTAG_PORTn(port) BIT_ULL((port) + 40)
drivers/net/dsa/yt921x.h
437
#define YT921X_VLAN_CTRL_SVLAN_EN BIT_ULL(35)
drivers/net/dsa/yt921x.h
440
#define YT921X_VLAN_CTRL_LEARN_DIS BIT_ULL(22)
drivers/net/dsa/yt921x.h
441
#define YT921X_VLAN_CTRL_PRIO_EN BIT_ULL(21)
drivers/net/dsa/yt921x.h
446
#define YT921X_VLAN_CTRL_PORTn(port) BIT_ULL((port) + 7)
drivers/net/dsa/yt921x.h
447
#define YT921X_VLAN_CTRL_BYPASS_1X_AC BIT_ULL(6)
drivers/net/dsa/yt921x.h
448
#define YT921X_VLAN_CTRL_METER_EN BIT_ULL(5)
drivers/net/ethernet/amd/pds_core/adminq.c
63
if (pdsc->state & BIT_ULL(PDSC_S_STOPPING_DRIVER) ||
drivers/net/ethernet/amd/pds_core/adminq.c
64
pdsc->state & BIT_ULL(PDSC_S_FW_DEAD))
drivers/net/ethernet/amd/pds_core/auxbus.c
213
mask = BIT_ULL(PDSC_S_FW_DEAD) |
drivers/net/ethernet/amd/pds_core/auxbus.c
214
BIT_ULL(PDSC_S_STOPPING_DRIVER);
drivers/net/ethernet/amd/pds_core/core.c
637
mask = BIT_ULL(PDSC_S_INITING_DRIVER) |
drivers/net/ethernet/amd/pds_core/core.c
638
BIT_ULL(PDSC_S_STOPPING_DRIVER);
drivers/net/ethernet/aquantia/atlantic/aq_ptp.c
724
BIT_ULL(aq_ptp->ptp_ring_param.vec_idx));
drivers/net/ethernet/broadcom/asp2/bcmasp.h
189
#define DESC_CHKSUM BIT_ULL(40)
drivers/net/ethernet/broadcom/asp2/bcmasp.h
190
#define DESC_CRC_ERR BIT_ULL(41)
drivers/net/ethernet/broadcom/asp2/bcmasp.h
191
#define DESC_RX_SYM_ERR BIT_ULL(42)
drivers/net/ethernet/broadcom/asp2/bcmasp.h
192
#define DESC_NO_OCT_ALN BIT_ULL(43)
drivers/net/ethernet/broadcom/asp2/bcmasp.h
193
#define DESC_PKT_TRUC BIT_ULL(44)
drivers/net/ethernet/broadcom/bnge/bnge.h
41
BNGE_FW_CAP_SHORT_CMD = BIT_ULL(0),
drivers/net/ethernet/broadcom/bnge/bnge.h
42
BNGE_FW_CAP_LLDP_AGENT = BIT_ULL(1),
drivers/net/ethernet/broadcom/bnge/bnge.h
43
BNGE_FW_CAP_DCBX_AGENT = BIT_ULL(2),
drivers/net/ethernet/broadcom/bnge/bnge.h
44
BNGE_FW_CAP_IF_CHANGE = BIT_ULL(3),
drivers/net/ethernet/broadcom/bnge/bnge.h
45
BNGE_FW_CAP_KONG_MB_CHNL = BIT_ULL(4),
drivers/net/ethernet/broadcom/bnge/bnge.h
46
BNGE_FW_CAP_ERROR_RECOVERY = BIT_ULL(5),
drivers/net/ethernet/broadcom/bnge/bnge.h
47
BNGE_FW_CAP_PKG_VER = BIT_ULL(6),
drivers/net/ethernet/broadcom/bnge/bnge.h
48
BNGE_FW_CAP_CFA_ADV_FLOW = BIT_ULL(7),
drivers/net/ethernet/broadcom/bnge/bnge.h
49
BNGE_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 = BIT_ULL(8),
drivers/net/ethernet/broadcom/bnge/bnge.h
50
BNGE_FW_CAP_PCIE_STATS_SUPPORTED = BIT_ULL(9),
drivers/net/ethernet/broadcom/bnge/bnge.h
51
BNGE_FW_CAP_EXT_STATS_SUPPORTED = BIT_ULL(10),
drivers/net/ethernet/broadcom/bnge/bnge.h
52
BNGE_FW_CAP_ERR_RECOVER_RELOAD = BIT_ULL(11),
drivers/net/ethernet/broadcom/bnge/bnge.h
53
BNGE_FW_CAP_HOT_RESET = BIT_ULL(12),
drivers/net/ethernet/broadcom/bnge/bnge.h
54
BNGE_FW_CAP_RX_ALL_PKT_TS = BIT_ULL(13),
drivers/net/ethernet/broadcom/bnge/bnge.h
55
BNGE_FW_CAP_VLAN_RX_STRIP = BIT_ULL(14),
drivers/net/ethernet/broadcom/bnge/bnge.h
56
BNGE_FW_CAP_VLAN_TX_INSERT = BIT_ULL(15),
drivers/net/ethernet/broadcom/bnge/bnge.h
57
BNGE_FW_CAP_EXT_HW_STATS_SUPPORTED = BIT_ULL(16),
drivers/net/ethernet/broadcom/bnge/bnge.h
58
BNGE_FW_CAP_LIVEPATCH = BIT_ULL(17),
drivers/net/ethernet/broadcom/bnge/bnge.h
59
BNGE_FW_CAP_HOT_RESET_IF = BIT_ULL(18),
drivers/net/ethernet/broadcom/bnge/bnge.h
60
BNGE_FW_CAP_RING_MONITOR = BIT_ULL(19),
drivers/net/ethernet/broadcom/bnge/bnge.h
61
BNGE_FW_CAP_DBG_QCAPS = BIT_ULL(20),
drivers/net/ethernet/broadcom/bnge/bnge.h
62
BNGE_FW_CAP_THRESHOLD_TEMP_SUPPORTED = BIT_ULL(21),
drivers/net/ethernet/broadcom/bnge/bnge.h
63
BNGE_FW_CAP_DFLT_VLAN_TPID_PCP = BIT_ULL(22),
drivers/net/ethernet/broadcom/bnge/bnge.h
64
BNGE_FW_CAP_VNIC_TUNNEL_TPA = BIT_ULL(23),
drivers/net/ethernet/broadcom/bnge/bnge.h
65
BNGE_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO = BIT_ULL(24),
drivers/net/ethernet/broadcom/bnge/bnge.h
66
BNGE_FW_CAP_CFA_RFS_RING_TBL_IDX_V3 = BIT_ULL(25),
drivers/net/ethernet/broadcom/bnge/bnge.h
67
BNGE_FW_CAP_VNIC_RE_FLUSH = BIT_ULL(26),
drivers/net/ethernet/broadcom/bnge/bnge.h
71
BNGE_EN_ROCE_V1 = BIT_ULL(0),
drivers/net/ethernet/broadcom/bnge/bnge.h
72
BNGE_EN_ROCE_V2 = BIT_ULL(1),
drivers/net/ethernet/broadcom/bnge/bnge.h
73
BNGE_EN_STRIP_VLAN = BIT_ULL(2),
drivers/net/ethernet/broadcom/bnge/bnge.h
74
BNGE_EN_SHARED_CHNL = BIT_ULL(3),
drivers/net/ethernet/broadcom/bnge/bnge.h
75
BNGE_EN_UDP_GSO_SUPP = BIT_ULL(4),
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2488
#define BNXT_FW_CAP_SHORT_CMD BIT_ULL(0)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2489
#define BNXT_FW_CAP_LLDP_AGENT BIT_ULL(1)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2490
#define BNXT_FW_CAP_DCBX_AGENT BIT_ULL(2)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2491
#define BNXT_FW_CAP_NEW_RM BIT_ULL(3)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2492
#define BNXT_FW_CAP_IF_CHANGE BIT_ULL(4)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2493
#define BNXT_FW_CAP_ENABLE_RDMA_SRIOV BIT_ULL(5)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2494
#define BNXT_FW_CAP_ROCE_VF_RESC_MGMT_SUPPORTED BIT_ULL(6)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2495
#define BNXT_FW_CAP_KONG_MB_CHNL BIT_ULL(7)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2496
#define BNXT_FW_CAP_ROCE_VF_DYN_ALLOC_SUPPORT BIT_ULL(8)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2497
#define BNXT_FW_CAP_LINK_ADMIN BIT_ULL(9)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2498
#define BNXT_FW_CAP_OVS_64BIT_HANDLE BIT_ULL(10)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2499
#define BNXT_FW_CAP_TRUSTED_VF BIT_ULL(11)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2500
#define BNXT_FW_CAP_ERROR_RECOVERY BIT_ULL(13)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2501
#define BNXT_FW_CAP_PKG_VER BIT_ULL(14)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2502
#define BNXT_FW_CAP_CFA_ADV_FLOW BIT_ULL(15)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2503
#define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 BIT_ULL(16)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2504
#define BNXT_FW_CAP_PCIE_STATS_SUPPORTED BIT_ULL(17)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2505
#define BNXT_FW_CAP_EXT_STATS_SUPPORTED BIT_ULL(18)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2506
#define BNXT_FW_CAP_TX_TS_CMP BIT_ULL(19)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2507
#define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT_ULL(20)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2508
#define BNXT_FW_CAP_HOT_RESET BIT_ULL(21)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2509
#define BNXT_FW_CAP_PTP_RTC BIT_ULL(22)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2510
#define BNXT_FW_CAP_RX_ALL_PKT_TS BIT_ULL(23)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2511
#define BNXT_FW_CAP_VLAN_RX_STRIP BIT_ULL(24)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2512
#define BNXT_FW_CAP_VLAN_TX_INSERT BIT_ULL(25)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2513
#define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED BIT_ULL(26)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2514
#define BNXT_FW_CAP_LIVEPATCH BIT_ULL(27)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2515
#define BNXT_FW_CAP_PTP_PPS BIT_ULL(28)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2516
#define BNXT_FW_CAP_HOT_RESET_IF BIT_ULL(29)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2517
#define BNXT_FW_CAP_RING_MONITOR BIT_ULL(30)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2518
#define BNXT_FW_CAP_DBG_QCAPS BIT_ULL(31)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2519
#define BNXT_FW_CAP_PTP BIT_ULL(32)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2520
#define BNXT_FW_CAP_THRESHOLD_TEMP_SUPPORTED BIT_ULL(33)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2521
#define BNXT_FW_CAP_DFLT_VLAN_TPID_PCP BIT_ULL(34)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2522
#define BNXT_FW_CAP_PRE_RESV_VNICS BIT_ULL(35)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2523
#define BNXT_FW_CAP_BACKING_STORE_V2 BIT_ULL(36)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2524
#define BNXT_FW_CAP_VNIC_TUNNEL_TPA BIT_ULL(37)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2525
#define BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO BIT_ULL(38)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2526
#define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V3 BIT_ULL(39)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2527
#define BNXT_FW_CAP_VNIC_RE_FLUSH BIT_ULL(40)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2528
#define BNXT_FW_CAP_SW_MAX_RESOURCE_LIMITS BIT_ULL(41)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2529
#define BNXT_FW_CAP_NPAR_1_2 BIT_ULL(42)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2530
#define BNXT_FW_CAP_MIRROR_ON_ROCE BIT_ULL(43)
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2531
#define BNXT_FW_CAP_PTP_PTM BIT_ULL(44)
drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c
377
if ((dissector->used_keys & BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL)) == 0 ||
drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c
378
(dissector->used_keys & BIT_ULL(FLOW_DISSECTOR_KEY_BASIC)) == 0) {
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c
1234
if (oct->sriov_info.vf_drv_loaded_mask & BIT_ULL(vfidx)) {
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c
630
if (oct->io_qmask.iq64B & BIT_ULL(q_no - srn)) {
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c
639
if (oct->io_qmask.iq & BIT_ULL(q_no - srn)) {
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c
685
if (oct->io_qmask.oq & BIT_ULL(q_no - srn)) {
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c
724
while (!(READ_ONCE(d64) & BIT_ULL(q_no)) && loop--) {
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c
748
while (!(READ_ONCE(d64) & BIT_ULL(q_no)) && loop--) {
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c
824
if (mbox_int_val & BIT_ULL(q_no)) {
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c
825
writeq(BIT_ULL(q_no),
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h
137
#define CN23XX_PKT_MAC_CTL_RINFO_TRS BIT_ULL(16)
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h
186
#define CN23XX_PKT_INPUT_CTL_VF_NUM BIT_ULL(32)
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h
233
#define CN23XX_IN_DONE_CNTS_PI_INT BIT_ULL(62)
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h
234
#define CN23XX_IN_DONE_CNTS_CINT_ENB BIT_ULL(48)
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h
389
#define CN23XX_MSIX_ENTRY_VECTOR_CTL BIT_ULL(32)
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h
425
#define CN23XX_INTR_PO_INT BIT_ULL(63)
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h
426
#define CN23XX_INTR_PI_INT BIT_ULL(62)
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h
427
#define CN23XX_INTR_MBOX_INT BIT_ULL(61)
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h
428
#define CN23XX_INTR_RESEND BIT_ULL(60)
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h
430
#define CN23XX_INTR_CINT_ENB BIT_ULL(48)
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h
451
#define CN23XX_INTR_DMA0_FORCE BIT_ULL(32)
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h
452
#define CN23XX_INTR_DMA1_FORCE BIT_ULL(33)
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h
454
#define CN23XX_INTR_DMA0_COUNT BIT_ULL(34)
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h
455
#define CN23XX_INTR_DMA1_COUNT BIT_ULL(35)
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h
457
#define CN23XX_INTR_DMA0_TIME BIT_ULL(36)
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h
458
#define CN23XX_INTR_DMA1_TIME BIT_ULL(37)
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h
462
#define CN23XX_INTR_VF_MBOX BIT_ULL(57)
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h
463
#define CN23XX_INTR_DMAVF_ERR BIT_ULL(58)
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h
464
#define CN23XX_INTR_DMAPF_ERR BIT_ULL(59)
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h
466
#define CN23XX_INTR_PKTVF_ERR BIT_ULL(60)
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h
467
#define CN23XX_INTR_PKTPF_ERR BIT_ULL(61)
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h
468
#define CN23XX_INTR_PPVF_ERR BIT_ULL(62)
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h
469
#define CN23XX_INTR_PPPF_ERR BIT_ULL(63)
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h
574
#define CN23XX_DPI_DMA_COMMIT_MODE BIT_ULL(58)
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_regs.h
575
#define CN23XX_DPI_DMA_PKT_EN BIT_ULL(56)
drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c
324
if (oct->io_qmask.iq64B & BIT_ULL(q_no)) {
drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c
333
if (oct->io_qmask.iq & BIT_ULL(q_no)) {
drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c
345
if (oct->io_qmask.oq & BIT_ULL(q_no)) {
drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h
133
#define CN23XX_IN_DONE_CNTS_PI_INT BIT_ULL(62)
drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h
134
#define CN23XX_IN_DONE_CNTS_CINT_ENB BIT_ULL(48)
drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h
231
#define CN23XX_INTR_PO_INT BIT_ULL(63)
drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h
232
#define CN23XX_INTR_PI_INT BIT_ULL(62)
drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h
233
#define CN23XX_INTR_MBOX_INT BIT_ULL(61)
drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h
234
#define CN23XX_INTR_RESEND BIT_ULL(60)
drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h
236
#define CN23XX_INTR_CINT_ENB BIT_ULL(48)
drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h
266
#define CN23XX_MSIX_ENTRY_VECTOR_CTL BIT_ULL(32)
drivers/net/ethernet/cavium/liquidio/cn23xx_vf_regs.h
86
#define CN23XX_PKT_INPUT_CTL_VF_NUM BIT_ULL(32)
drivers/net/ethernet/cavium/liquidio/cn66xx_device.c
370
if (!(oct->io_qmask.iq & BIT_ULL(i)))
drivers/net/ethernet/cavium/liquidio/cn66xx_device.c
393
if (!(oct->io_qmask.oq & BIT_ULL(i)))
drivers/net/ethernet/cavium/liquidio/cn66xx_device.c
526
if (!(droq_mask & BIT_ULL(oq_no)))
drivers/net/ethernet/cavium/liquidio/cn66xx_device.c
532
oct->droq_intr |= BIT_ULL(oq_no);
drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h
367
#define CN6XXX_INTR_DMA0_FORCE BIT_ULL(32)
drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h
368
#define CN6XXX_INTR_DMA1_FORCE BIT_ULL(33)
drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h
369
#define CN6XXX_INTR_DMA0_COUNT BIT_ULL(34)
drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h
370
#define CN6XXX_INTR_DMA1_COUNT BIT_ULL(35)
drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h
371
#define CN6XXX_INTR_DMA0_TIME BIT_ULL(36)
drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h
372
#define CN6XXX_INTR_DMA1_TIME BIT_ULL(37)
drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h
373
#define CN6XXX_INTR_INSTR_DB_OF_ERR BIT_ULL(48)
drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h
374
#define CN6XXX_INTR_SLIST_DB_OF_ERR BIT_ULL(49)
drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h
375
#define CN6XXX_INTR_POUT_ERR BIT_ULL(50)
drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h
376
#define CN6XXX_INTR_PIN_BP_ERR BIT_ULL(51)
drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h
377
#define CN6XXX_INTR_PGL_ERR BIT_ULL(52)
drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h
378
#define CN6XXX_INTR_PDI_ERR BIT_ULL(53)
drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h
379
#define CN6XXX_INTR_POP_ERR BIT_ULL(54)
drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h
380
#define CN6XXX_INTR_PINS_ERR BIT_ULL(55)
drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h
381
#define CN6XXX_INTR_SPRT0_ERR BIT_ULL(56)
drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h
382
#define CN6XXX_INTR_SPRT1_ERR BIT_ULL(57)
drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h
383
#define CN6XXX_INTR_ILL_PAD_ERR BIT_ULL(60)
drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h
486
#define CN6XXX_DPI_DMA_COMMIT_MODE BIT_ULL(58)
drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h
487
#define CN6XXX_DPI_DMA_PKT_HP BIT_ULL(57)
drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h
488
#define CN6XXX_DPI_DMA_PKT_EN BIT_ULL(56)
drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h
489
#define CN6XXX_DPI_DMA_O_ES BIT_ULL(15)
drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h
490
#define CN6XXX_DPI_DMA_O_MODE BIT_ULL(14)
drivers/net/ethernet/cavium/liquidio/cn68xx_regs.h
43
#define CN68XX_INTR_PIPE_ERR BIT_ULL(61)
drivers/net/ethernet/cavium/liquidio/lio_core.c
1279
if (!(oct->io_qmask.oq & BIT_ULL(idx)))
drivers/net/ethernet/cavium/liquidio/lio_core.c
967
if (!(oct->droq_intr & BIT_ULL(oq_no)))
drivers/net/ethernet/cavium/liquidio/lio_core.c
974
oct_priv->napi_mask |= BIT_ULL(oq_no);
drivers/net/ethernet/cavium/liquidio/lio_ethtool.c
1154
if (!(oct->io_qmask.oq & BIT_ULL(i)))
drivers/net/ethernet/cavium/liquidio/lio_ethtool.c
1160
if (!(oct->io_qmask.iq & BIT_ULL(i)))
drivers/net/ethernet/cavium/liquidio/lio_ethtool.c
1640
if (!(oct_dev->io_qmask.iq & BIT_ULL(j)))
drivers/net/ethernet/cavium/liquidio/lio_ethtool.c
1683
if (!(oct_dev->io_qmask.oq & BIT_ULL(j)))
drivers/net/ethernet/cavium/liquidio/lio_ethtool.c
1871
if (!(oct_dev->io_qmask.iq & BIT_ULL(i)))
drivers/net/ethernet/cavium/liquidio/lio_ethtool.c
1882
if (!(oct_dev->io_qmask.oq & BIT_ULL(i)))
drivers/net/ethernet/cavium/liquidio/lio_ethtool.c
1919
if (!(oct_dev->io_qmask.iq & BIT_ULL(i)))
drivers/net/ethernet/cavium/liquidio/lio_ethtool.c
1930
if (!(oct_dev->io_qmask.oq & BIT_ULL(i)))
drivers/net/ethernet/cavium/liquidio/lio_main.c
1065
if (!(oct->io_qmask.oq & BIT_ULL(i)))
drivers/net/ethernet/cavium/liquidio/lio_main.c
1089
if (!(oct->io_qmask.iq & BIT_ULL(i)))
drivers/net/ethernet/cavium/liquidio/lio_main.c
162
if (!(oct->io_qmask.oq & BIT_ULL(q_no)))
drivers/net/ethernet/cavium/liquidio/lio_main.c
196
if (!(oct->io_qmask.oq & BIT_ULL(i)))
drivers/net/ethernet/cavium/liquidio/lio_main.c
252
if (!(oct->io_qmask.iq & BIT_ULL(i)))
drivers/net/ethernet/cavium/liquidio/lio_main.c
4001
if (!(oct->sriov_info.vf_drv_loaded_mask & BIT_ULL(vf_idx))) {
drivers/net/ethernet/cavium/liquidio/lio_main.c
4002
oct->sriov_info.vf_drv_loaded_mask |= BIT_ULL(vf_idx);
drivers/net/ethernet/cavium/liquidio/lio_main.c
4009
if (oct->sriov_info.vf_drv_loaded_mask & BIT_ULL(vf_idx)) {
drivers/net/ethernet/cavium/liquidio/lio_main.c
4010
oct->sriov_info.vf_drv_loaded_mask &= ~BIT_ULL(vf_idx);
drivers/net/ethernet/cavium/liquidio/lio_main.c
995
if (!(oct->io_qmask.iq & BIT_ULL(i)))
drivers/net/ethernet/cavium/liquidio/lio_vf_main.c
123
if (!(oct->io_qmask.iq & BIT_ULL(i)))
drivers/net/ethernet/cavium/liquidio/lio_vf_main.c
485
if (!(oct->io_qmask.iq & BIT_ULL(i)))
drivers/net/ethernet/cavium/liquidio/lio_vf_main.c
546
if (!(oct->io_qmask.oq & BIT_ULL(i)))
drivers/net/ethernet/cavium/liquidio/lio_vf_main.c
558
if (!(oct->io_qmask.iq & BIT_ULL(i)))
drivers/net/ethernet/cavium/liquidio/lio_vf_main.c
84
if (!(oct->io_qmask.oq & BIT_ULL(i)))
drivers/net/ethernet/cavium/liquidio/octeon_device.c
1286
(oct->io_qmask.iq & BIT_ULL(q_no)))
drivers/net/ethernet/cavium/liquidio/octeon_device.c
1296
(oct->io_qmask.oq & BIT_ULL(q_no)))
drivers/net/ethernet/cavium/liquidio/octeon_device.c
651
if (oct->io_qmask.oq & BIT_ULL(i))
drivers/net/ethernet/cavium/liquidio/octeon_device.c
656
if (oct->io_qmask.iq & BIT_ULL(i))
drivers/net/ethernet/cavium/liquidio/octeon_droq.c
303
oct->io_qmask.oq |= BIT_ULL(q_no);
drivers/net/ethernet/cavium/liquidio/request_manager.c
126
oct->io_qmask.iq |= BIT_ULL(iq_no);
drivers/net/ethernet/cavium/liquidio/request_manager.c
244
if (!(oct->io_qmask.iq & BIT_ULL(i)))
drivers/net/ethernet/cavium/thunder/nic_main.c
103
#define INTR_MASK(vfs) ((vfs < 64) ? (BIT_ULL(vfs) - 1) : (~0ull))
drivers/net/ethernet/cavium/thunder/nic_main.c
121
nic_reg_write(nic, NIC_PF_MAILBOX_INT + (mbx_reg << 3), BIT_ULL(vf));
drivers/net/ethernet/cavium/thunder/nic_main.c
777
(BIT_ULL(20) | 0x2ull << 14 | 0x1));
drivers/net/ethernet/cavium/thunder/nic_main.c
779
(BIT_ULL(20) | 0x3ull << 14 | 0x1));
drivers/net/ethernet/cavium/thunder/nicvf_queues.c
786
mbx.rq.cfg = BIT_ULL(63) | BIT_ULL(62) |
drivers/net/ethernet/cavium/thunder/nicvf_queues.c
795
mbx.rq.cfg = BIT_ULL(63) | BIT_ULL(62) |
drivers/net/ethernet/cavium/thunder/nicvf_queues.h
129
#define NICVF_SQ_EN BIT_ULL(19)
drivers/net/ethernet/cavium/thunder/nicvf_queues.h
132
#define NICVF_CQ_RESET BIT_ULL(41)
drivers/net/ethernet/cavium/thunder/nicvf_queues.h
133
#define NICVF_SQ_RESET BIT_ULL(17)
drivers/net/ethernet/cavium/thunder/nicvf_queues.h
134
#define NICVF_RBDR_RESET BIT_ULL(43)
drivers/net/ethernet/cavium/thunder/thunder_bgx.c
271
lmac->dmacs[i].vf_map &= ~BIT_ULL(vf_id);
drivers/net/ethernet/cavium/thunder/thunder_bgx.c
296
lmac->dmacs[i].vf_map |= BIT_ULL(vf_id);
drivers/net/ethernet/cavium/thunder/thunder_bgx.c
306
lmac->dmacs[lmac->dmacs_cfg].vf_map = BIT_ULL(vf_id);
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
100
#define SPU_PMD_CRTL_TRAIN_EN BIT_ULL(1)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
105
#define SPU_FEC_CTL_FEC_EN BIT_ULL(0)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
106
#define SPU_FEC_CTL_ERR_EN BIT_ULL(1)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
108
#define SPU_AN_CTL_AN_EN BIT_ULL(12)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
109
#define SPU_AN_CTL_XNP_EN BIT_ULL(13)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
112
#define SPU_MISC_CTL_INTLV_RDISP BIT_ULL(10)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
113
#define SPU_MISC_CTL_RX_DIS BIT_ULL(12)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
119
#define SPU_DBG_CTL_AN_ARB_LINK_CHK_EN BIT_ULL(18)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
120
#define SPU_DBG_CTL_AN_NONCE_MCT_DIS BIT_ULL(29)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
124
#define BGX_PKT_RX_PTP_EN BIT_ULL(12)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
129
#define SMU_TX_APPEND_FCS_D BIT_ULL(2)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
136
#define SMU_TX_CTL_DIC_EN BIT_ULL(0)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
137
#define SMU_TX_CTL_UNI_EN BIT_ULL(1)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
141
#define SMU_CTL_RX_IDLE BIT_ULL(0)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
142
#define SMU_CTL_TX_IDLE BIT_ULL(1)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
144
#define RX_EN BIT_ULL(0)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
145
#define TX_EN BIT_ULL(1)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
146
#define BCK_EN BIT_ULL(2)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
147
#define DRP_EN BIT_ULL(3)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
150
#define PCS_MRX_CTL_RST_AN BIT_ULL(9)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
151
#define PCS_MRX_CTL_PWR_DN BIT_ULL(11)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
152
#define PCS_MRX_CTL_AN_EN BIT_ULL(12)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
153
#define PCS_MRX_CTL_LOOPBACK1 BIT_ULL(14)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
154
#define PCS_MRX_CTL_RESET BIT_ULL(15)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
156
#define PCS_MRX_STATUS_LINK BIT_ULL(2)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
157
#define PCS_MRX_STATUS_AN_CPT BIT_ULL(5)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
164
#define PCS_MISC_CTL_MODE BIT_ULL(8)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
165
#define PCS_MISC_CTL_DISP_EN BIT_ULL(13)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
166
#define PCS_MISC_CTL_GMX_ENO BIT_ULL(11)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
169
#define GMI_PORT_CFG_SPEED BIT_ULL(1)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
170
#define GMI_PORT_CFG_DUPLEX BIT_ULL(2)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
171
#define GMI_PORT_CFG_SLOT_TIME BIT_ULL(3)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
172
#define GMI_PORT_CFG_SPEED_MSB BIT_ULL(8)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
173
#define GMI_PORT_CFG_RX_IDLE BIT_ULL(12)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
174
#define GMI_PORT_CFG_TX_IDLE BIT_ULL(13)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
187
#define GMI_TXX_INT_PTP_LOST BIT_ULL(4)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
188
#define GMI_TXX_INT_LATE_COL BIT_ULL(3)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
189
#define GMI_TXX_INT_XSDEF BIT_ULL(2)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
190
#define GMI_TXX_INT_XSCOL BIT_ULL(1)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
191
#define GMI_TXX_INT_UNDFLW BIT_ULL(0)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
36
#define CMR_PKT_TX_EN BIT_ULL(13)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
37
#define CMR_PKT_RX_EN BIT_ULL(14)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
38
#define CMR_EN BIT_ULL(15)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
40
#define CMR_GLOBAL_CFG_FCS_STRIP BIT_ULL(6)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
57
#define RX_DMACX_CAM_EN BIT_ULL(48)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
87
#define SPU_CTL_LOW_POWER BIT_ULL(11)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
88
#define SPU_CTL_LOOPBACK BIT_ULL(14)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
89
#define SPU_CTL_RESET BIT_ULL(15)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
91
#define SPU_STATUS1_RCV_LNK BIT_ULL(2)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
93
#define SPU_STATUS2_RCVFLT BIT_ULL(10)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
95
#define SPU_BX_STATUS_RX_ALIGN BIT_ULL(12)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
97
#define SPU_BR_STATUS_BLK_LOCK BIT_ULL(0)
drivers/net/ethernet/cavium/thunder/thunder_bgx.h
98
#define SPU_BR_STATUS_RCV_LNK BIT_ULL(12)
drivers/net/ethernet/cavium/thunder/thunder_xcv.c
25
#define PORT_EN BIT_ULL(63)
drivers/net/ethernet/cavium/thunder/thunder_xcv.c
26
#define CLK_RESET BIT_ULL(15)
drivers/net/ethernet/cavium/thunder/thunder_xcv.c
27
#define DLL_RESET BIT_ULL(11)
drivers/net/ethernet/cavium/thunder/thunder_xcv.c
28
#define COMP_EN BIT_ULL(7)
drivers/net/ethernet/cavium/thunder/thunder_xcv.c
29
#define TX_PKT_RESET BIT_ULL(3)
drivers/net/ethernet/cavium/thunder/thunder_xcv.c
30
#define TX_DATA_RESET BIT_ULL(2)
drivers/net/ethernet/cavium/thunder/thunder_xcv.c
31
#define RX_PKT_RESET BIT_ULL(1)
drivers/net/ethernet/cavium/thunder/thunder_xcv.c
32
#define RX_DATA_RESET BIT_ULL(0)
drivers/net/ethernet/cavium/thunder/thunder_xcv.c
34
#define CLKRX_BYP BIT_ULL(23)
drivers/net/ethernet/cavium/thunder/thunder_xcv.c
35
#define CLKTX_BYP BIT_ULL(15)
drivers/net/ethernet/cavium/thunder/thunder_xcv.c
37
#define DRV_BYP BIT_ULL(63)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c
305
~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c
306
BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c
307
BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c
308
BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c
309
BIT_ULL(FLOW_DISSECTOR_KEY_PORTS) |
drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c
310
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_KEYID) |
drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c
311
BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) |
drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c
312
BIT_ULL(FLOW_DISSECTOR_KEY_IP))) {
drivers/net/ethernet/cisco/enic/enic_main.c
2887
patch_level &= BIT_ULL(0) | BIT_ULL(2);
drivers/net/ethernet/faraday/ftmac100.c
160
maht |= BIT_ULL(hash);
drivers/net/ethernet/freescale/dpaa2/dpaa2-switch-flower.c
20
~(BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
drivers/net/ethernet/freescale/dpaa2/dpaa2-switch-flower.c
21
BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
drivers/net/ethernet/freescale/dpaa2/dpaa2-switch-flower.c
22
BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
drivers/net/ethernet/freescale/dpaa2/dpaa2-switch-flower.c
23
BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) |
drivers/net/ethernet/freescale/dpaa2/dpaa2-switch-flower.c
24
BIT_ULL(FLOW_DISSECTOR_KEY_PORTS) |
drivers/net/ethernet/freescale/dpaa2/dpaa2-switch-flower.c
25
BIT_ULL(FLOW_DISSECTOR_KEY_IP) |
drivers/net/ethernet/freescale/dpaa2/dpaa2-switch-flower.c
26
BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
drivers/net/ethernet/freescale/dpaa2/dpaa2-switch-flower.c
27
BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS))) {
drivers/net/ethernet/freescale/dpaa2/dpaa2-switch-flower.c
546
~(BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
drivers/net/ethernet/freescale/dpaa2/dpaa2-switch-flower.c
547
BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
drivers/net/ethernet/freescale/dpaa2/dpaa2-switch-flower.c
548
BIT_ULL(FLOW_DISSECTOR_KEY_VLAN))) {
drivers/net/ethernet/freescale/dpaa2/dpmac.h
101
#define DPMAC_ADVERTISED_AUTONEG BIT_ULL(3)
drivers/net/ethernet/freescale/dpaa2/dpmac.h
88
#define DPMAC_LINK_OPT_AUTONEG BIT_ULL(0)
drivers/net/ethernet/freescale/dpaa2/dpmac.h
89
#define DPMAC_LINK_OPT_HALF_DUPLEX BIT_ULL(1)
drivers/net/ethernet/freescale/dpaa2/dpmac.h
90
#define DPMAC_LINK_OPT_PAUSE BIT_ULL(2)
drivers/net/ethernet/freescale/dpaa2/dpmac.h
91
#define DPMAC_LINK_OPT_ASYM_PAUSE BIT_ULL(3)
drivers/net/ethernet/freescale/dpaa2/dpmac.h
94
#define DPMAC_ADVERTISED_10BASET_FULL BIT_ULL(0)
drivers/net/ethernet/freescale/dpaa2/dpmac.h
95
#define DPMAC_ADVERTISED_100BASET_FULL BIT_ULL(1)
drivers/net/ethernet/freescale/dpaa2/dpmac.h
96
#define DPMAC_ADVERTISED_1000BASET_FULL BIT_ULL(2)
drivers/net/ethernet/freescale/dpaa2/dpmac.h
97
#define DPMAC_ADVERTISED_10000BASET_FULL BIT_ULL(4)
drivers/net/ethernet/freescale/dpaa2/dpmac.h
98
#define DPMAC_ADVERTISED_2500BASEX_FULL BIT_ULL(5)
drivers/net/ethernet/freescale/enetc/enetc.c
56
mask |= BIT_ULL(i * 6);
drivers/net/ethernet/freescale/enetc/enetc_qos.c
486
BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS),
drivers/net/ethernet/freescale/enetc/enetc_qos.c
492
BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS),
drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
188
#define HNS3_VECTOR_TX_IRQ BIT_ULL(0)
drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
189
#define HNS3_VECTOR_RX_IRQ BIT_ULL(1)
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
7341
~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
7342
BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
7343
BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
7344
BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) |
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
7345
BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
7346
BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
7347
BIT_ULL(FLOW_DISSECTOR_KEY_PORTS))) {
drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c
21
#define CMDQ_CTXT_CEQ_ARM_MASK BIT_ULL(61)
drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c
22
#define CMDQ_CTXT_CEQ_EN_MASK BIT_ULL(62)
drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c
23
#define CMDQ_CTXT_HW_BUSY_BIT_MASK BIT_ULL(63)
drivers/net/ethernet/huawei/hinic3/hinic3_mbox.h
14
#define MBOX_MSG_HEADER_STATUS_MASK BIT_ULL(13)
drivers/net/ethernet/huawei/hinic3/hinic3_mbox.h
15
#define MBOX_MSG_HEADER_SOURCE_MASK BIT_ULL(15)
drivers/net/ethernet/huawei/hinic3/hinic3_mbox.h
22
#define MBOX_MSG_HEADER_NO_ACK_MASK BIT_ULL(54)
drivers/net/ethernet/huawei/hinic3/hinic3_mbox.h
23
#define MBOX_MSG_HEADER_DATA_TYPE_MASK BIT_ULL(55)
drivers/net/ethernet/huawei/hinic3/hinic3_mbox.h
25
#define MBOX_MSG_HEADER_LAST_MASK BIT_ULL(62)
drivers/net/ethernet/huawei/hinic3/hinic3_mbox.h
26
#define MBOX_MSG_HEADER_DIRECTION_MASK BIT_ULL(63)
drivers/net/ethernet/intel/i40e/i40e.h
127
#define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED)
drivers/net/ethernet/intel/i40e/i40e.h
129
BIT_ULL(__I40E_PF_RESET_AND_REBUILD_REQUESTED)
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1431
#define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1432
BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1433
BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1434
BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1435
BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1436
BIT_ULL(I40E_PHY_TYPE_XAUI) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1437
BIT_ULL(I40E_PHY_TYPE_XFI) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1438
BIT_ULL(I40E_PHY_TYPE_SFI) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1439
BIT_ULL(I40E_PHY_TYPE_XLAUI) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1440
BIT_ULL(I40E_PHY_TYPE_XLPPI) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1441
BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1442
BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1443
BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1444
BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1445
BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1446
BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1447
BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1448
BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1449
BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1450
BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1451
BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1452
BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1453
BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1454
BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1455
BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1456
BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1457
BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1458
BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1459
BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1460
BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1461
BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1462
BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1463
BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1464
BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1465
BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1466
BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1467
BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
1468
BIT_ULL(I40E_PHY_TYPE_5GBASE_T))
drivers/net/ethernet/intel/i40e/i40e_ethtool.c
3667
hena |= BIT_ULL(LIBIE_FILTER_PCTYPE_FRAG_IPV4);
drivers/net/ethernet/intel/i40e/i40e_ethtool.c
3678
hena |= BIT_ULL(LIBIE_FILTER_PCTYPE_FRAG_IPV6);
drivers/net/ethernet/intel/i40e/i40e_ethtool.c
3687
hena |= BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_OTHER);
drivers/net/ethernet/intel/i40e/i40e_ethtool.c
3696
hena |= BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_OTHER);
drivers/net/ethernet/intel/i40e/i40e_ethtool.c
3699
hena |= BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_OTHER) |
drivers/net/ethernet/intel/i40e/i40e_ethtool.c
3700
BIT_ULL(LIBIE_FILTER_PCTYPE_FRAG_IPV4);
drivers/net/ethernet/intel/i40e/i40e_ethtool.c
3703
hena |= BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_OTHER) |
drivers/net/ethernet/intel/i40e/i40e_ethtool.c
3704
BIT_ULL(LIBIE_FILTER_PCTYPE_FRAG_IPV6);
drivers/net/ethernet/intel/i40e/i40e_ethtool.c
3722
hena |= BIT_ULL(flow_id);
drivers/net/ethernet/intel/i40e/i40e_hmc.h
111
val3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
drivers/net/ethernet/intel/i40e/i40e_hmc.h
130
val3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c
107
obj->size = BIT_ULL(size_exp);
drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c
130
obj->size = BIT_ULL(size_exp);
drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c
153
obj->size = BIT_ULL(size_exp);
drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c
176
obj->size = BIT_ULL(size_exp);
drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c
883
mask = BIT_ULL(ce_info->width) - 1;
drivers/net/ethernet/intel/i40e/i40e_main.c
2127
while (num_qps && (BIT_ULL(pow) < qcount)) {
drivers/net/ethernet/intel/i40e/i40e_main.c
3625
BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT));
drivers/net/ethernet/intel/i40e/i40e_main.c
3787
if (!(vsi->tc_config.enabled_tc & BIT_ULL(n)))
drivers/net/ethernet/intel/i40e/i40e_main.c
653
*stat = (new_data + BIT_ULL(48)) - *offset;
drivers/net/ethernet/intel/i40e/i40e_main.c
676
*stat = (u32)((new_data + BIT_ULL(32)) - *offset);
drivers/net/ethernet/intel/i40e/i40e_main.c
8575
~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
drivers/net/ethernet/intel/i40e/i40e_main.c
8576
BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
drivers/net/ethernet/intel/i40e/i40e_main.c
8577
BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
drivers/net/ethernet/intel/i40e/i40e_main.c
8578
BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) |
drivers/net/ethernet/intel/i40e/i40e_main.c
8579
BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
drivers/net/ethernet/intel/i40e/i40e_main.c
8580
BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
drivers/net/ethernet/intel/i40e/i40e_main.c
8581
BIT_ULL(FLOW_DISSECTOR_KEY_PORTS) |
drivers/net/ethernet/intel/i40e/i40e_main.c
8582
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_KEYID))) {
drivers/net/ethernet/intel/i40e/i40e_main.c
9288
if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {
drivers/net/ethernet/intel/i40e/i40e_main.c
9303
} else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {
drivers/net/ethernet/intel/i40e/i40e_main.c
9340
} else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
drivers/net/ethernet/intel/i40e/i40e_main.c
9349
} else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {
drivers/net/ethernet/intel/i40e/i40e_txrx.h
76
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_UDP) | \
drivers/net/ethernet/intel/i40e/i40e_txrx.h
77
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
drivers/net/ethernet/intel/i40e/i40e_txrx.h
78
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_TCP) | \
drivers/net/ethernet/intel/i40e/i40e_txrx.h
79
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
drivers/net/ethernet/intel/i40e/i40e_txrx.h
80
BIT_ULL(LIBIE_FILTER_PCTYPE_FRAG_IPV4) | \
drivers/net/ethernet/intel/i40e/i40e_txrx.h
81
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_UDP) | \
drivers/net/ethernet/intel/i40e/i40e_txrx.h
82
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_TCP) | \
drivers/net/ethernet/intel/i40e/i40e_txrx.h
83
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
drivers/net/ethernet/intel/i40e/i40e_txrx.h
84
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
drivers/net/ethernet/intel/i40e/i40e_txrx.h
85
BIT_ULL(LIBIE_FILTER_PCTYPE_FRAG_IPV6) | \
drivers/net/ethernet/intel/i40e/i40e_txrx.h
86
BIT_ULL(LIBIE_FILTER_PCTYPE_L2_PAYLOAD))
drivers/net/ethernet/intel/i40e/i40e_txrx.h
89
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
drivers/net/ethernet/intel/i40e/i40e_txrx.h
90
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
drivers/net/ethernet/intel/i40e/i40e_txrx.h
91
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
drivers/net/ethernet/intel/i40e/i40e_txrx.h
92
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
drivers/net/ethernet/intel/i40e/i40e_txrx.h
93
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
drivers/net/ethernet/intel/i40e/i40e_txrx.h
94
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
drivers/net/ethernet/intel/i40e/i40e_type.h
150
#define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
drivers/net/ethernet/intel/i40e/i40e_type.h
151
#define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
drivers/net/ethernet/intel/i40e/i40e_type.h
152
#define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
drivers/net/ethernet/intel/i40e/i40e_type.h
153
#define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
drivers/net/ethernet/intel/i40e/i40e_type.h
154
#define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
drivers/net/ethernet/intel/i40e/i40e_type.h
155
#define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
drivers/net/ethernet/intel/i40e/i40e_type.h
156
#define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
drivers/net/ethernet/intel/i40e/i40e_type.h
157
#define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
drivers/net/ethernet/intel/i40e/i40e_type.h
158
#define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
drivers/net/ethernet/intel/i40e/i40e_type.h
159
#define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
drivers/net/ethernet/intel/i40e/i40e_type.h
160
#define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
drivers/net/ethernet/intel/i40e/i40e_type.h
161
#define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
drivers/net/ethernet/intel/i40e/i40e_type.h
162
#define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
drivers/net/ethernet/intel/i40e/i40e_type.h
163
#define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
drivers/net/ethernet/intel/i40e/i40e_type.h
164
#define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
drivers/net/ethernet/intel/i40e/i40e_type.h
165
#define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
drivers/net/ethernet/intel/i40e/i40e_type.h
166
#define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
drivers/net/ethernet/intel/i40e/i40e_type.h
167
#define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
drivers/net/ethernet/intel/i40e/i40e_type.h
168
#define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
drivers/net/ethernet/intel/i40e/i40e_type.h
169
#define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
drivers/net/ethernet/intel/i40e/i40e_type.h
170
#define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
drivers/net/ethernet/intel/i40e/i40e_type.h
171
#define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
drivers/net/ethernet/intel/i40e/i40e_type.h
172
#define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
drivers/net/ethernet/intel/i40e/i40e_type.h
173
#define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
drivers/net/ethernet/intel/i40e/i40e_type.h
174
#define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
drivers/net/ethernet/intel/i40e/i40e_type.h
175
#define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
drivers/net/ethernet/intel/i40e/i40e_type.h
177
BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
drivers/net/ethernet/intel/i40e/i40e_type.h
178
#define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
drivers/net/ethernet/intel/i40e/i40e_type.h
186
#define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
drivers/net/ethernet/intel/i40e/i40e_type.h
188
#define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
drivers/net/ethernet/intel/i40e/i40e_type.h
190
#define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
drivers/net/ethernet/intel/i40e/i40e_type.h
192
#define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
drivers/net/ethernet/intel/i40e/i40e_type.h
194
#define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \
drivers/net/ethernet/intel/i40e/i40e_type.h
196
#define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
drivers/net/ethernet/intel/i40e/i40e_type.h
199
#define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T)
drivers/net/ethernet/intel/i40e/i40e_type.h
200
#define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T)
drivers/net/ethernet/intel/i40e/i40e_type.h
712
BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
drivers/net/ethernet/intel/i40e/i40e_type.h
754
#define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
drivers/net/ethernet/intel/i40e/i40e_type.h
906
#define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
drivers/net/ethernet/intel/i40e/i40e_type.h
915
#define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
drivers/net/ethernet/intel/i40e/i40e_type.h
962
#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
drivers/net/ethernet/intel/i40e/i40e_type.h
971
#define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
drivers/net/ethernet/intel/i40e/i40e_type.h
975
#define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
drivers/net/ethernet/intel/iavf/iavf.h
303
#define IAVF_FLAG_AQ_ENABLE_QUEUES BIT_ULL(0)
drivers/net/ethernet/intel/iavf/iavf.h
304
#define IAVF_FLAG_AQ_DISABLE_QUEUES BIT_ULL(1)
drivers/net/ethernet/intel/iavf/iavf.h
305
#define IAVF_FLAG_AQ_ADD_MAC_FILTER BIT_ULL(2)
drivers/net/ethernet/intel/iavf/iavf.h
306
#define IAVF_FLAG_AQ_ADD_VLAN_FILTER BIT_ULL(3)
drivers/net/ethernet/intel/iavf/iavf.h
307
#define IAVF_FLAG_AQ_DEL_MAC_FILTER BIT_ULL(4)
drivers/net/ethernet/intel/iavf/iavf.h
308
#define IAVF_FLAG_AQ_DEL_VLAN_FILTER BIT_ULL(5)
drivers/net/ethernet/intel/iavf/iavf.h
309
#define IAVF_FLAG_AQ_CONFIGURE_QUEUES BIT_ULL(6)
drivers/net/ethernet/intel/iavf/iavf.h
310
#define IAVF_FLAG_AQ_MAP_VECTORS BIT_ULL(7)
drivers/net/ethernet/intel/iavf/iavf.h
311
#define IAVF_FLAG_AQ_HANDLE_RESET BIT_ULL(8)
drivers/net/ethernet/intel/iavf/iavf.h
312
#define IAVF_FLAG_AQ_CONFIGURE_RSS BIT_ULL(9) /* direct AQ config */
drivers/net/ethernet/intel/iavf/iavf.h
313
#define IAVF_FLAG_AQ_GET_CONFIG BIT_ULL(10)
drivers/net/ethernet/intel/iavf/iavf.h
315
#define IAVF_FLAG_AQ_GET_RSS_HASHCFG BIT_ULL(11)
drivers/net/ethernet/intel/iavf/iavf.h
316
#define IAVF_FLAG_AQ_SET_RSS_HASHCFG BIT_ULL(12)
drivers/net/ethernet/intel/iavf/iavf.h
317
#define IAVF_FLAG_AQ_SET_RSS_KEY BIT_ULL(13)
drivers/net/ethernet/intel/iavf/iavf.h
318
#define IAVF_FLAG_AQ_SET_RSS_LUT BIT_ULL(14)
drivers/net/ethernet/intel/iavf/iavf.h
319
#define IAVF_FLAG_AQ_SET_RSS_HFUNC BIT_ULL(15)
drivers/net/ethernet/intel/iavf/iavf.h
320
#define IAVF_FLAG_AQ_CONFIGURE_PROMISC_MODE BIT_ULL(16)
drivers/net/ethernet/intel/iavf/iavf.h
321
#define IAVF_FLAG_AQ_ENABLE_VLAN_STRIPPING BIT_ULL(19)
drivers/net/ethernet/intel/iavf/iavf.h
322
#define IAVF_FLAG_AQ_DISABLE_VLAN_STRIPPING BIT_ULL(20)
drivers/net/ethernet/intel/iavf/iavf.h
323
#define IAVF_FLAG_AQ_ENABLE_CHANNELS BIT_ULL(21)
drivers/net/ethernet/intel/iavf/iavf.h
324
#define IAVF_FLAG_AQ_DISABLE_CHANNELS BIT_ULL(22)
drivers/net/ethernet/intel/iavf/iavf.h
325
#define IAVF_FLAG_AQ_ADD_CLOUD_FILTER BIT_ULL(23)
drivers/net/ethernet/intel/iavf/iavf.h
326
#define IAVF_FLAG_AQ_DEL_CLOUD_FILTER BIT_ULL(24)
drivers/net/ethernet/intel/iavf/iavf.h
327
#define IAVF_FLAG_AQ_ADD_FDIR_FILTER BIT_ULL(25)
drivers/net/ethernet/intel/iavf/iavf.h
328
#define IAVF_FLAG_AQ_DEL_FDIR_FILTER BIT_ULL(26)
drivers/net/ethernet/intel/iavf/iavf.h
329
#define IAVF_FLAG_AQ_ADD_ADV_RSS_CFG BIT_ULL(27)
drivers/net/ethernet/intel/iavf/iavf.h
330
#define IAVF_FLAG_AQ_DEL_ADV_RSS_CFG BIT_ULL(28)
drivers/net/ethernet/intel/iavf/iavf.h
331
#define IAVF_FLAG_AQ_REQUEST_STATS BIT_ULL(29)
drivers/net/ethernet/intel/iavf/iavf.h
332
#define IAVF_FLAG_AQ_GET_OFFLOAD_VLAN_V2_CAPS BIT_ULL(30)
drivers/net/ethernet/intel/iavf/iavf.h
333
#define IAVF_FLAG_AQ_ENABLE_CTAG_VLAN_STRIPPING BIT_ULL(31)
drivers/net/ethernet/intel/iavf/iavf.h
334
#define IAVF_FLAG_AQ_DISABLE_CTAG_VLAN_STRIPPING BIT_ULL(32)
drivers/net/ethernet/intel/iavf/iavf.h
335
#define IAVF_FLAG_AQ_ENABLE_STAG_VLAN_STRIPPING BIT_ULL(33)
drivers/net/ethernet/intel/iavf/iavf.h
336
#define IAVF_FLAG_AQ_DISABLE_STAG_VLAN_STRIPPING BIT_ULL(34)
drivers/net/ethernet/intel/iavf/iavf.h
337
#define IAVF_FLAG_AQ_ENABLE_CTAG_VLAN_INSERTION BIT_ULL(35)
drivers/net/ethernet/intel/iavf/iavf.h
338
#define IAVF_FLAG_AQ_DISABLE_CTAG_VLAN_INSERTION BIT_ULL(36)
drivers/net/ethernet/intel/iavf/iavf.h
339
#define IAVF_FLAG_AQ_ENABLE_STAG_VLAN_INSERTION BIT_ULL(37)
drivers/net/ethernet/intel/iavf/iavf.h
340
#define IAVF_FLAG_AQ_DISABLE_STAG_VLAN_INSERTION BIT_ULL(38)
drivers/net/ethernet/intel/iavf/iavf.h
341
#define IAVF_FLAG_AQ_CONFIGURE_QUEUES_BW BIT_ULL(39)
drivers/net/ethernet/intel/iavf/iavf.h
342
#define IAVF_FLAG_AQ_CFG_QUEUES_QUANTA_SIZE BIT_ULL(40)
drivers/net/ethernet/intel/iavf/iavf.h
343
#define IAVF_FLAG_AQ_GET_QOS_CAPS BIT_ULL(41)
drivers/net/ethernet/intel/iavf/iavf.h
344
#define IAVF_FLAG_AQ_GET_SUPPORTED_RXDIDS BIT_ULL(42)
drivers/net/ethernet/intel/iavf/iavf.h
345
#define IAVF_FLAG_AQ_GET_PTP_CAPS BIT_ULL(43)
drivers/net/ethernet/intel/iavf/iavf.h
346
#define IAVF_FLAG_AQ_SEND_PTP_CMD BIT_ULL(44)
drivers/net/ethernet/intel/iavf/iavf.h
364
#define IAVF_EXTENDED_CAP_SEND_VLAN_V2 BIT_ULL(0)
drivers/net/ethernet/intel/iavf/iavf.h
365
#define IAVF_EXTENDED_CAP_RECV_VLAN_V2 BIT_ULL(1)
drivers/net/ethernet/intel/iavf/iavf.h
366
#define IAVF_EXTENDED_CAP_SEND_RXDID BIT_ULL(2)
drivers/net/ethernet/intel/iavf/iavf.h
367
#define IAVF_EXTENDED_CAP_RECV_RXDID BIT_ULL(3)
drivers/net/ethernet/intel/iavf/iavf.h
368
#define IAVF_EXTENDED_CAP_SEND_PTP BIT_ULL(4)
drivers/net/ethernet/intel/iavf/iavf.h
369
#define IAVF_EXTENDED_CAP_RECV_PTP BIT_ULL(5)
drivers/net/ethernet/intel/iavf/iavf_adv_rss.h
100
#define IAVF_ADV_RSS_HASH_FLD_GTPC_TEID BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_GTPC_TEID)
drivers/net/ethernet/intel/iavf/iavf_adv_rss.h
101
#define IAVF_ADV_RSS_HASH_FLD_GTPU_IP_TEID BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_GTPU_IP_TEID)
drivers/net/ethernet/intel/iavf/iavf_adv_rss.h
102
#define IAVF_ADV_RSS_HASH_FLD_GTPU_EH_TEID BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_GTPU_EH_TEID)
drivers/net/ethernet/intel/iavf/iavf_adv_rss.h
103
#define IAVF_ADV_RSS_HASH_FLD_GTPU_UP_TEID BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_GTPU_UP_TEID)
drivers/net/ethernet/intel/iavf/iavf_adv_rss.h
105
BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_GTPU_DWN_TEID)
drivers/net/ethernet/intel/iavf/iavf_adv_rss.h
81
BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_IPV4_SA)
drivers/net/ethernet/intel/iavf/iavf_adv_rss.h
83
BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_IPV6_SA)
drivers/net/ethernet/intel/iavf/iavf_adv_rss.h
85
BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_IPV4_DA)
drivers/net/ethernet/intel/iavf/iavf_adv_rss.h
87
BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_IPV6_DA)
drivers/net/ethernet/intel/iavf/iavf_adv_rss.h
89
BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_TCP_SRC_PORT)
drivers/net/ethernet/intel/iavf/iavf_adv_rss.h
91
BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_TCP_DST_PORT)
drivers/net/ethernet/intel/iavf/iavf_adv_rss.h
93
BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_UDP_SRC_PORT)
drivers/net/ethernet/intel/iavf/iavf_adv_rss.h
95
BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_UDP_DST_PORT)
drivers/net/ethernet/intel/iavf/iavf_adv_rss.h
97
BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_SCTP_SRC_PORT)
drivers/net/ethernet/intel/iavf/iavf_adv_rss.h
99
BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_SCTP_DST_PORT)
drivers/net/ethernet/intel/iavf/iavf_main.c
3824
~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
drivers/net/ethernet/intel/iavf/iavf_main.c
3825
BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
drivers/net/ethernet/intel/iavf/iavf_main.c
3826
BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
drivers/net/ethernet/intel/iavf/iavf_main.c
3827
BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) |
drivers/net/ethernet/intel/iavf/iavf_main.c
3828
BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
drivers/net/ethernet/intel/iavf/iavf_main.c
3829
BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
drivers/net/ethernet/intel/iavf/iavf_main.c
3830
BIT_ULL(FLOW_DISSECTOR_KEY_PORTS) |
drivers/net/ethernet/intel/iavf/iavf_main.c
3831
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_KEYID))) {
drivers/net/ethernet/intel/iavf/iavf_txrx.h
65
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_UDP) | \
drivers/net/ethernet/intel/iavf/iavf_txrx.h
66
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
drivers/net/ethernet/intel/iavf/iavf_txrx.h
67
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_TCP) | \
drivers/net/ethernet/intel/iavf/iavf_txrx.h
68
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
drivers/net/ethernet/intel/iavf/iavf_txrx.h
69
BIT_ULL(LIBIE_FILTER_PCTYPE_FRAG_IPV4) | \
drivers/net/ethernet/intel/iavf/iavf_txrx.h
70
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_UDP) | \
drivers/net/ethernet/intel/iavf/iavf_txrx.h
71
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_TCP) | \
drivers/net/ethernet/intel/iavf/iavf_txrx.h
72
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
drivers/net/ethernet/intel/iavf/iavf_txrx.h
73
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
drivers/net/ethernet/intel/iavf/iavf_txrx.h
74
BIT_ULL(LIBIE_FILTER_PCTYPE_FRAG_IPV6) | \
drivers/net/ethernet/intel/iavf/iavf_txrx.h
75
BIT_ULL(LIBIE_FILTER_PCTYPE_L2_PAYLOAD))
drivers/net/ethernet/intel/iavf/iavf_txrx.h
78
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
drivers/net/ethernet/intel/iavf/iavf_txrx.h
79
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
drivers/net/ethernet/intel/iavf/iavf_txrx.h
80
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
drivers/net/ethernet/intel/iavf/iavf_txrx.h
81
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
drivers/net/ethernet/intel/iavf/iavf_txrx.h
82
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
drivers/net/ethernet/intel/iavf/iavf_txrx.h
83
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
drivers/net/ethernet/intel/iavf/iavf_type.h
298
BIT_ULL(IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT)
drivers/net/ethernet/intel/iavf/iavf_type.h
320
#define IAVF_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(IAVF_RXD_QW1_LENGTH_SPH_SHIFT)
drivers/net/ethernet/intel/iavf/iavf_type.h
495
#define IAVF_TXD_CTX_UDP_TUNNELING BIT_ULL(IAVF_TXD_CTX_QW0_NATT_SHIFT)
drivers/net/ethernet/intel/iavf/iavf_type.h
500
BIT_ULL(IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT)
drivers/net/ethernet/intel/iavf/iavf_type.h
513
#define IAVF_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(IAVF_TXD_CTX_QW0_L4T_CS_SHIFT)
drivers/net/ethernet/intel/ice/ice_adapter.c
16
#define ICE_ADAPTER_FIXED_INDEX BIT_ULL(63)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1000
#define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1001
#define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1002
#define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1003
#define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1004
#define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1005
#define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1006
#define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1007
#define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1008
#define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1009
#define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1010
#define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1011
#define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1012
#define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1013
#define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1014
#define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1015
#define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1016
#define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1017
#define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1018
#define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1019
#define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1020
#define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1021
#define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1022
#define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1023
#define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1024
#define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1025
#define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1026
#define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1027
#define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1028
#define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1029
#define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1030
#define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1031
#define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1034
#define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1035
#define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1036
#define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1037
#define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1038
#define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1039
#define ICE_PHY_TYPE_HIGH_200G_CR4_PAM4 BIT_ULL(5)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1040
#define ICE_PHY_TYPE_HIGH_200G_SR4 BIT_ULL(6)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1041
#define ICE_PHY_TYPE_HIGH_200G_FR4 BIT_ULL(7)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1042
#define ICE_PHY_TYPE_HIGH_200G_LR4 BIT_ULL(8)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1043
#define ICE_PHY_TYPE_HIGH_200G_DR4 BIT_ULL(9)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1044
#define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4 BIT_ULL(10)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1045
#define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC BIT_ULL(11)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1046
#define ICE_PHY_TYPE_HIGH_200G_AUI4 BIT_ULL(12)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
968
#define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
969
#define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
970
#define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
971
#define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
972
#define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
973
#define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
974
#define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
975
#define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
976
#define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
977
#define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
978
#define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
979
#define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
980
#define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
981
#define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
982
#define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
983
#define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
984
#define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
985
#define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
986
#define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
987
#define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
988
#define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
989
#define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
990
#define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
991
#define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
992
#define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
993
#define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
994
#define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
995
#define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
996
#define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
997
#define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
998
#define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30)
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
999
#define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31)
drivers/net/ethernet/intel/ice/ice_base.c
502
BIT_ULL(ICE_RLAN_CTX_DBUF_S));
drivers/net/ethernet/intel/ice/ice_common.c
102
if (low & BIT_ULL(i))
drivers/net/ethernet/intel/ice/ice_common.c
110
if (high & BIT_ULL(i))
drivers/net/ethernet/intel/ice/ice_common.c
3542
pt_low = BIT_ULL(index);
drivers/net/ethernet/intel/ice/ice_common.c
3546
*phy_type_low |= BIT_ULL(index);
drivers/net/ethernet/intel/ice/ice_common.c
3551
pt_high = BIT_ULL(index);
drivers/net/ethernet/intel/ice/ice_common.c
3555
*phy_type_high |= BIT_ULL(index);
drivers/net/ethernet/intel/ice/ice_common.c
5843
u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
drivers/net/ethernet/intel/ice/ice_common.c
5862
*cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
drivers/net/ethernet/intel/ice/ice_common.c
5901
*cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
drivers/net/ethernet/intel/ice/ice_ethtool.c
2191
if (phy_types_low & BIT_ULL(i))
drivers/net/ethernet/intel/ice/ice_ethtool.c
2198
if (phy_types_high & BIT_ULL(i))
drivers/net/ethernet/intel/ice/ice_flow.c
1632
#define FLAG_GTP_EH_PDU_LINK BIT_ULL(13)
drivers/net/ethernet/intel/ice/ice_flow.c
1633
#define FLAG_GTP_EH_PDU BIT_ULL(14)
drivers/net/ethernet/intel/ice/ice_flow.c
1917
u64 bit = BIT_ULL(fld);
drivers/net/ethernet/intel/ice/ice_flow.c
2783
(BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
drivers/net/ethernet/intel/ice/ice_flow.c
2784
BIT_ULL(LIBIE_FILTER_PCTYPE_FRAG_IPV4))
drivers/net/ethernet/intel/ice/ice_flow.c
2786
(BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
drivers/net/ethernet/intel/ice/ice_flow.c
2787
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_TCP))
drivers/net/ethernet/intel/ice/ice_flow.c
2789
(BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
drivers/net/ethernet/intel/ice/ice_flow.c
2790
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
drivers/net/ethernet/intel/ice/ice_flow.c
2791
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_UDP))
drivers/net/ethernet/intel/ice/ice_flow.c
2794
ICE_FLOW_AVF_RSS_IPV4_MASKS | BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_SCTP))
drivers/net/ethernet/intel/ice/ice_flow.c
2797
(BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
drivers/net/ethernet/intel/ice/ice_flow.c
2798
BIT_ULL(LIBIE_FILTER_PCTYPE_FRAG_IPV6))
drivers/net/ethernet/intel/ice/ice_flow.c
2800
(BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
drivers/net/ethernet/intel/ice/ice_flow.c
2801
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
drivers/net/ethernet/intel/ice/ice_flow.c
2802
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_UDP))
drivers/net/ethernet/intel/ice/ice_flow.c
2804
(BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
drivers/net/ethernet/intel/ice/ice_flow.c
2805
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_TCP))
drivers/net/ethernet/intel/ice/ice_flow.c
2808
ICE_FLOW_AVF_RSS_IPV6_MASKS | BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_SCTP))
drivers/net/ethernet/intel/ice/ice_flow.c
2867
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_SCTP)) {
drivers/net/ethernet/intel/ice/ice_flow.c
2871
~BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_SCTP);
drivers/net/ethernet/intel/ice/ice_flow.c
2888
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_SCTP)) {
drivers/net/ethernet/intel/ice/ice_flow.c
2892
~BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_SCTP);
drivers/net/ethernet/intel/ice/ice_flow.h
109
(BIT_ULL(ICE_FLOW_FIELD_IDX_GTPU_UP_TEID))
drivers/net/ethernet/intel/ice/ice_flow.h
111
(BIT_ULL(ICE_FLOW_FIELD_IDX_GTPU_DWN_TEID))
drivers/net/ethernet/intel/ice/ice_flow.h
123
(BIT_ULL(ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID))
drivers/net/ethernet/intel/ice/ice_flow.h
133
(BIT_ULL(ICE_FLOW_FIELD_IDX_PFCP_SEID))
drivers/net/ethernet/intel/ice/ice_flow.h
140
(BIT_ULL(ICE_FLOW_FIELD_IDX_L2TPV3_SESS_ID))
drivers/net/ethernet/intel/ice/ice_flow.h
147
(BIT_ULL(ICE_FLOW_FIELD_IDX_ESP_SPI))
drivers/net/ethernet/intel/ice/ice_flow.h
154
(BIT_ULL(ICE_FLOW_FIELD_IDX_AH_SPI))
drivers/net/ethernet/intel/ice/ice_flow.h
161
(BIT_ULL(ICE_FLOW_FIELD_IDX_NAT_T_ESP_SPI))
drivers/net/ethernet/intel/ice/ice_flow.h
168
(BIT_ULL(ICE_FLOW_FIELD_IDX_L2TPV2_SESS_ID))
drivers/net/ethernet/intel/ice/ice_flow.h
17
(BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_DA) | \
drivers/net/ethernet/intel/ice/ice_flow.h
173
(BIT_ULL(ICE_FLOW_FIELD_IDX_L2TPV2_LEN_SESS_ID))
drivers/net/ethernet/intel/ice/ice_flow.h
18
BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_SA))
drivers/net/ethernet/intel/ice/ice_flow.h
20
(BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) | \
drivers/net/ethernet/intel/ice/ice_flow.h
21
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA))
drivers/net/ethernet/intel/ice/ice_flow.h
23
(BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_SA) | \
drivers/net/ethernet/intel/ice/ice_flow.h
24
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_DA))
drivers/net/ethernet/intel/ice/ice_flow.h
26
(BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_PRE32_SA) | \
drivers/net/ethernet/intel/ice/ice_flow.h
27
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_PRE32_DA))
drivers/net/ethernet/intel/ice/ice_flow.h
29
(BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_PRE48_SA) | \
drivers/net/ethernet/intel/ice/ice_flow.h
30
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_PRE48_DA))
drivers/net/ethernet/intel/ice/ice_flow.h
32
(BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_PRE64_SA) | \
drivers/net/ethernet/intel/ice/ice_flow.h
323
#define ICE_FLOW_HASH_FLD_IPV4_SA BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA)
drivers/net/ethernet/intel/ice/ice_flow.h
324
#define ICE_FLOW_HASH_FLD_IPV6_SA BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_SA)
drivers/net/ethernet/intel/ice/ice_flow.h
325
#define ICE_FLOW_HASH_FLD_IPV4_DA BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA)
drivers/net/ethernet/intel/ice/ice_flow.h
326
#define ICE_FLOW_HASH_FLD_IPV6_DA BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_DA)
drivers/net/ethernet/intel/ice/ice_flow.h
327
#define ICE_FLOW_HASH_FLD_TCP_SRC_PORT BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_SRC_PORT)
drivers/net/ethernet/intel/ice/ice_flow.h
328
#define ICE_FLOW_HASH_FLD_TCP_DST_PORT BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_DST_PORT)
drivers/net/ethernet/intel/ice/ice_flow.h
329
#define ICE_FLOW_HASH_FLD_UDP_SRC_PORT BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_SRC_PORT)
drivers/net/ethernet/intel/ice/ice_flow.h
33
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_PRE64_DA))
drivers/net/ethernet/intel/ice/ice_flow.h
330
#define ICE_FLOW_HASH_FLD_UDP_DST_PORT BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_DST_PORT)
drivers/net/ethernet/intel/ice/ice_flow.h
332
BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT)
drivers/net/ethernet/intel/ice/ice_flow.h
334
BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_DST_PORT)
drivers/net/ethernet/intel/ice/ice_flow.h
336
#define ICE_FLOW_HASH_FLD_GTPC_TEID BIT_ULL(ICE_FLOW_FIELD_IDX_GTPC_TEID)
drivers/net/ethernet/intel/ice/ice_flow.h
337
#define ICE_FLOW_HASH_FLD_GTPU_IP_TEID BIT_ULL(ICE_FLOW_FIELD_IDX_GTPU_IP_TEID)
drivers/net/ethernet/intel/ice/ice_flow.h
338
#define ICE_FLOW_HASH_FLD_GTPU_EH_TEID BIT_ULL(ICE_FLOW_FIELD_IDX_GTPU_EH_TEID)
drivers/net/ethernet/intel/ice/ice_flow.h
339
#define ICE_FLOW_HASH_FLD_GTPU_UP_TEID BIT_ULL(ICE_FLOW_FIELD_IDX_GTPU_UP_TEID)
drivers/net/ethernet/intel/ice/ice_flow.h
341
BIT_ULL(ICE_FLOW_FIELD_IDX_GTPU_DWN_TEID)
drivers/net/ethernet/intel/ice/ice_flow.h
348
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_UDP) | \
drivers/net/ethernet/intel/ice/ice_flow.h
349
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
drivers/net/ethernet/intel/ice/ice_flow.h
35
(BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_SRC_PORT) | \
drivers/net/ethernet/intel/ice/ice_flow.h
350
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_TCP) | \
drivers/net/ethernet/intel/ice/ice_flow.h
351
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
drivers/net/ethernet/intel/ice/ice_flow.h
352
BIT_ULL(LIBIE_FILTER_PCTYPE_FRAG_IPV4) | \
drivers/net/ethernet/intel/ice/ice_flow.h
353
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_UDP) | \
drivers/net/ethernet/intel/ice/ice_flow.h
354
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_TCP) | \
drivers/net/ethernet/intel/ice/ice_flow.h
355
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
drivers/net/ethernet/intel/ice/ice_flow.h
356
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
drivers/net/ethernet/intel/ice/ice_flow.h
357
BIT_ULL(LIBIE_FILTER_PCTYPE_FRAG_IPV6) | \
drivers/net/ethernet/intel/ice/ice_flow.h
358
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
drivers/net/ethernet/intel/ice/ice_flow.h
359
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
drivers/net/ethernet/intel/ice/ice_flow.h
36
BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_DST_PORT))
drivers/net/ethernet/intel/ice/ice_flow.h
360
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
drivers/net/ethernet/intel/ice/ice_flow.h
361
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
drivers/net/ethernet/intel/ice/ice_flow.h
362
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
drivers/net/ethernet/intel/ice/ice_flow.h
363
BIT_ULL(LIBIE_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
drivers/net/ethernet/intel/ice/ice_flow.h
38
(BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_SRC_PORT) | \
drivers/net/ethernet/intel/ice/ice_flow.h
39
BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_DST_PORT))
drivers/net/ethernet/intel/ice/ice_flow.h
41
(BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT) | \
drivers/net/ethernet/intel/ice/ice_flow.h
42
BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_DST_PORT))
drivers/net/ethernet/intel/ice/ice_flow.h
72
(BIT_ULL(ICE_FLOW_FIELD_IDX_GTPC_TEID))
drivers/net/ethernet/intel/ice/ice_flow.h
80
(BIT_ULL(ICE_FLOW_FIELD_IDX_GTPC_TEID))
drivers/net/ethernet/intel/ice/ice_flow.h
88
(BIT_ULL(ICE_FLOW_FIELD_IDX_GTPU_IP_TEID))
drivers/net/ethernet/intel/ice/ice_flow.h
96
(BIT_ULL(ICE_FLOW_FIELD_IDX_GTPU_EH_TEID))
drivers/net/ethernet/intel/ice/ice_flow.h
99
(BIT_ULL(ICE_FLOW_FIELD_IDX_GTPU_EH_QFI))
drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h
110
#define ICE_FXD_FLTR_QW1_PCMD_M BIT_ULL(ICE_FXD_FLTR_QW1_PCMD_S)
drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h
125
#define ICE_FXD_FLTR_QW1_SWAP_M BIT_ULL(ICE_FXD_FLTR_QW1_SWAP_S)
drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h
51
#define ICE_FXD_FLTR_QW0_COMP_Q_M BIT_ULL(ICE_FXD_FLTR_QW0_COMP_Q_S)
drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h
529
#define ICE_TXD_CTX_UDP_TUNNELING BIT_ULL(ICE_TXD_CTX_QW0_L4TUNT_S)
drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h
535
#define ICE_TXD_CTX_QW0_L4T_CS_M BIT_ULL(ICE_TXD_CTX_QW0_L4T_CS_S)
drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h
72
#define ICE_FXD_FLTR_QW0_EVICT_ENA_M BIT_ULL(ICE_FXD_FLTR_QW0_EVICT_ENA_S)
drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h
90
#define ICE_FXD_FLTR_QW0_DROP_M BIT_ULL(ICE_FXD_FLTR_QW0_DROP_S)
drivers/net/ethernet/intel/ice/ice_parser.c
1187
#define ICE_BST_ALU_SXS BIT_ULL(19)
drivers/net/ethernet/intel/ice/ice_parser.c
1191
#define ICE_BST_ALU_INC0 BIT_ULL(38)
drivers/net/ethernet/intel/ice/ice_parser.c
1192
#define ICE_BST_ALU_INC1 BIT_ULL(39)
drivers/net/ethernet/intel/ice/ice_parser.c
1200
#define ICE_BST_ALU_DFE BIT_ULL(74 - ICE_BST_ALU_BA_S)
drivers/net/ethernet/intel/ice/ice_parser.c
1205
#define ICE_BST_ALU_FEI BIT_ULL(87 - ICE_BST_ALU_BA_S)
drivers/net/ethernet/intel/ice/ice_parser.c
1247
#define ICE_BST_PGKB_F0_ENA BIT_ULL(0)
drivers/net/ethernet/intel/ice/ice_parser.c
1249
#define ICE_BST_PGKB_F1_ENA BIT_ULL(7)
drivers/net/ethernet/intel/ice/ice_parser.c
1251
#define ICE_BST_PGKB_F2_ENA BIT_ULL(14)
drivers/net/ethernet/intel/ice/ice_parser.c
1253
#define ICE_BST_PGKB_F3_ENA BIT_ULL(21)
drivers/net/ethernet/intel/ice/ice_parser.c
274
#define ICE_IM_PGKB_F0_ENA BIT_ULL(0)
drivers/net/ethernet/intel/ice/ice_parser.c
276
#define ICE_IM_PGKB_F1_ENA BIT_ULL(7)
drivers/net/ethernet/intel/ice/ice_parser.c
278
#define ICE_IM_PGKB_F2_ENA BIT_ULL(14)
drivers/net/ethernet/intel/ice/ice_parser.c
280
#define ICE_IM_PGKB_F3_ENA BIT_ULL(21)
drivers/net/ethernet/intel/ice/ice_parser.c
305
#define ICE_IM_ALU_SXS BIT_ULL(19)
drivers/net/ethernet/intel/ice/ice_parser.c
309
#define ICE_IM_ALU_INC0 BIT_ULL(38)
drivers/net/ethernet/intel/ice/ice_parser.c
310
#define ICE_IM_ALU_INC1 BIT_ULL(39)
drivers/net/ethernet/intel/ice/ice_parser.c
318
#define ICE_IM_ALU_DFE BIT_ULL(74 - ICE_IM_ALU_BA_S)
drivers/net/ethernet/intel/ice/ice_parser.c
323
#define ICE_IM_ALU_FEI BIT_ULL(87 - ICE_IM_ALU_BA_S)
drivers/net/ethernet/intel/ice/ice_parser.c
494
#define ICE_MI_GAC BIT_ULL(39)
drivers/net/ethernet/intel/ice/ice_parser.c
499
#define ICE_MI_GBC BIT_ULL(60)
drivers/net/ethernet/intel/ice/ice_parser.c
510
#define ICE_MI_GCC BIT_ULL(81 - ICE_MI_GBDM_S)
drivers/net/ethernet/intel/ice/ice_parser.c
515
#define ICE_MI_GDC BIT_ULL(102 - ICE_MI_GBDM_S)
drivers/net/ethernet/intel/ice/ice_parser.c
705
#define ICE_PGCA_IPG BIT_ULL(19)
drivers/net/ethernet/intel/ice/ice_parser.c
707
#define ICE_PGCA_IMG BIT_ULL(31)
drivers/net/ethernet/intel/ice/ice_parser.c
709
#define ICE_PGCA_ILR BIT_ULL(40)
drivers/net/ethernet/intel/ice/ice_parser.c
710
#define ICE_PGCA_HOP BIT_ULL(41)
drivers/net/ethernet/intel/ice/ice_parser.c
731
#define ICE_PGNCK_VLD BIT_ULL(0)
drivers/net/ethernet/intel/ice/ice_parser.c
733
#define ICE_PGNCK_F0 BIT_ULL(12)
drivers/net/ethernet/intel/ice/ice_parser.c
734
#define ICE_PGNCK_F1 BIT_ULL(13)
drivers/net/ethernet/intel/ice/ice_parser.c
735
#define ICE_PGNCK_F2 BIT_ULL(14)
drivers/net/ethernet/intel/ice/ice_parser.c
736
#define ICE_PGNCK_F3 BIT_ULL(15)
drivers/net/ethernet/intel/ice/ice_parser.c
737
#define ICE_PGNCK_BH BIT_ULL(16)
drivers/net/ethernet/intel/ice/ice_parser.c
763
#define ICE_PGCK_VLD BIT_ULL(0)
drivers/net/ethernet/intel/ice/ice_parser.c
765
#define ICE_PGCK_F0 BIT_ULL(12)
drivers/net/ethernet/intel/ice/ice_parser.c
766
#define ICE_PGCK_F1 BIT_ULL(13)
drivers/net/ethernet/intel/ice/ice_parser.c
767
#define ICE_PGCK_F2 BIT_ULL(14)
drivers/net/ethernet/intel/ice/ice_parser.c
768
#define ICE_PGCK_F3 BIT_ULL(15)
drivers/net/ethernet/intel/ice/ice_parser.c
769
#define ICE_PGCK_BH BIT_ULL(16)
drivers/net/ethernet/intel/ice/ice_parser_rt.c
378
rt->pu.flg_msk |= BIT_ULL(idx);
drivers/net/ethernet/intel/ice/ice_parser_rt.c
380
rt->pu.flg_val |= BIT_ULL(idx);
drivers/net/ethernet/intel/ice/ice_parser_rt.c
382
rt->pu.flg_val &= ~BIT_ULL(idx);
drivers/net/ethernet/intel/ice/ice_parser_rt.c
443
rt->pu.flg_val |= (u64)BIT_ULL(idx);
drivers/net/ethernet/intel/ice/ice_parser_rt.c
445
rt->pu.flg_val &= ~(u64)BIT_ULL(idx);
drivers/net/ethernet/intel/ice/ice_ptp.c
613
!(tstamp_ready & BIT_ULL(phy_idx))) {
drivers/net/ethernet/intel/ice/ice_ptp.c
764
if (!hw->reset_ongoing && (tstamp_ready & BIT_ULL(phy_idx)))
drivers/net/ethernet/intel/ice/ice_sched.c
3256
u64 pow_result = BIT_ULL(i);
drivers/net/ethernet/intel/ice/ice_tc_lib.c
1650
~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
drivers/net/ethernet/intel/ice/ice_tc_lib.c
1651
BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
drivers/net/ethernet/intel/ice/ice_tc_lib.c
1652
BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
drivers/net/ethernet/intel/ice/ice_tc_lib.c
1653
BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) |
drivers/net/ethernet/intel/ice/ice_tc_lib.c
1654
BIT_ULL(FLOW_DISSECTOR_KEY_CVLAN) |
drivers/net/ethernet/intel/ice/ice_tc_lib.c
1655
BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
drivers/net/ethernet/intel/ice/ice_tc_lib.c
1656
BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
drivers/net/ethernet/intel/ice/ice_tc_lib.c
1657
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
drivers/net/ethernet/intel/ice/ice_tc_lib.c
1658
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_KEYID) |
drivers/net/ethernet/intel/ice/ice_tc_lib.c
1659
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
drivers/net/ethernet/intel/ice/ice_tc_lib.c
1660
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
drivers/net/ethernet/intel/ice/ice_tc_lib.c
1661
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_PORTS) |
drivers/net/ethernet/intel/ice/ice_tc_lib.c
1662
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_OPTS) |
drivers/net/ethernet/intel/ice/ice_tc_lib.c
1663
BIT_ULL(FLOW_DISSECTOR_KEY_IP) |
drivers/net/ethernet/intel/ice/ice_tc_lib.c
1664
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IP) |
drivers/net/ethernet/intel/ice/ice_tc_lib.c
1665
BIT_ULL(FLOW_DISSECTOR_KEY_PORTS) |
drivers/net/ethernet/intel/ice/ice_tc_lib.c
1666
BIT_ULL(FLOW_DISSECTOR_KEY_PPPOE) |
drivers/net/ethernet/intel/ice/ice_tc_lib.c
1667
BIT_ULL(FLOW_DISSECTOR_KEY_L2TPV3))) {
drivers/net/ethernet/intel/ice/ice_tc_lib.c
1693
(BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
drivers/net/ethernet/intel/ice/ice_tc_lib.c
1694
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
drivers/net/ethernet/intel/ice/ice_tc_lib.c
1695
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_KEYID) |
drivers/net/ethernet/intel/ice/ice_tc_lib.c
1696
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_PORTS) |
drivers/net/ethernet/intel/ice/ice_tc_lib.c
1697
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IP) |
drivers/net/ethernet/intel/ice/ice_tc_lib.c
1698
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_OPTS) |
drivers/net/ethernet/intel/ice/ice_tc_lib.c
1699
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_CONTROL))) {
drivers/net/ethernet/intel/ice/ice_type.h
44
#define ICE_DBG_INIT BIT_ULL(1)
drivers/net/ethernet/intel/ice/ice_type.h
45
#define ICE_DBG_FW_LOG BIT_ULL(3)
drivers/net/ethernet/intel/ice/ice_type.h
46
#define ICE_DBG_LINK BIT_ULL(4)
drivers/net/ethernet/intel/ice/ice_type.h
47
#define ICE_DBG_PHY BIT_ULL(5)
drivers/net/ethernet/intel/ice/ice_type.h
48
#define ICE_DBG_QCTX BIT_ULL(6)
drivers/net/ethernet/intel/ice/ice_type.h
49
#define ICE_DBG_NVM BIT_ULL(7)
drivers/net/ethernet/intel/ice/ice_type.h
50
#define ICE_DBG_LAN BIT_ULL(8)
drivers/net/ethernet/intel/ice/ice_type.h
51
#define ICE_DBG_FLOW BIT_ULL(9)
drivers/net/ethernet/intel/ice/ice_type.h
52
#define ICE_DBG_SW BIT_ULL(13)
drivers/net/ethernet/intel/ice/ice_type.h
53
#define ICE_DBG_SCHED BIT_ULL(14)
drivers/net/ethernet/intel/ice/ice_type.h
54
#define ICE_DBG_RDMA BIT_ULL(15)
drivers/net/ethernet/intel/ice/ice_type.h
55
#define ICE_DBG_PKG BIT_ULL(16)
drivers/net/ethernet/intel/ice/ice_type.h
56
#define ICE_DBG_RES BIT_ULL(17)
drivers/net/ethernet/intel/ice/ice_type.h
57
#define ICE_DBG_PTP BIT_ULL(19)
drivers/net/ethernet/intel/ice/ice_type.h
58
#define ICE_DBG_AQ_MSG BIT_ULL(24)
drivers/net/ethernet/intel/ice/ice_type.h
59
#define ICE_DBG_AQ_DESC BIT_ULL(25)
drivers/net/ethernet/intel/ice/ice_type.h
60
#define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
drivers/net/ethernet/intel/ice/ice_type.h
61
#define ICE_DBG_AQ_CMD BIT_ULL(27)
drivers/net/ethernet/intel/ice/ice_type.h
66
#define ICE_DBG_PARSER BIT_ULL(28)
drivers/net/ethernet/intel/ice/ice_type.h
68
#define ICE_DBG_USER BIT_ULL(31)
drivers/net/ethernet/intel/ice/virt/fdir.c
21
#define FDIR_INSET_FLAG_ESP_M BIT_ULL(FDIR_INSET_FLAG_ESP_S)
drivers/net/ethernet/intel/ice/virt/fdir.c
22
#define FDIR_INSET_FLAG_ESP_UDP BIT_ULL(FDIR_INSET_FLAG_ESP_S)
drivers/net/ethernet/intel/ice/virt/rss.c
100
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
103
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) |
drivers/net/ethernet/intel/ice/virt/rss.c
104
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
107
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA) |
drivers/net/ethernet/intel/ice/virt/rss.c
108
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
112
ICE_FLOW_HASH_IPV4 | BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
116
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) |
drivers/net/ethernet/intel/ice/virt/rss.c
117
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_PROT) |
drivers/net/ethernet/intel/ice/virt/rss.c
118
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
122
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA) |
drivers/net/ethernet/intel/ice/virt/rss.c
123
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_PROT) |
drivers/net/ethernet/intel/ice/virt/rss.c
124
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
129
ICE_FLOW_HASH_IPV4 | BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_PROT) |
drivers/net/ethernet/intel/ice/virt/rss.c
130
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
134
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_PROT) |
drivers/net/ethernet/intel/ice/virt/rss.c
135
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
138
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_PROT)},
drivers/net/ethernet/intel/ice/virt/rss.c
141
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA)},
drivers/net/ethernet/intel/ice/virt/rss.c
144
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA)},
drivers/net/ethernet/intel/ice/virt/rss.c
152
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) |
drivers/net/ethernet/intel/ice/virt/rss.c
153
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_PROT)},
drivers/net/ethernet/intel/ice/virt/rss.c
157
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA) |
drivers/net/ethernet/intel/ice/virt/rss.c
158
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_PROT)},
drivers/net/ethernet/intel/ice/virt/rss.c
163
ICE_FLOW_HASH_IPV4 | BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_PROT)},
drivers/net/ethernet/intel/ice/virt/rss.c
166
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_PROT)},
drivers/net/ethernet/intel/ice/virt/rss.c
169
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_ID)},
drivers/net/ethernet/intel/ice/virt/rss.c
172
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
176
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) |
drivers/net/ethernet/intel/ice/virt/rss.c
177
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
181
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA) |
drivers/net/ethernet/intel/ice/virt/rss.c
182
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
187
ICE_FLOW_HASH_IPV4 | BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
192
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) |
drivers/net/ethernet/intel/ice/virt/rss.c
193
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_PROT) |
drivers/net/ethernet/intel/ice/virt/rss.c
194
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
199
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA) |
drivers/net/ethernet/intel/ice/virt/rss.c
200
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_PROT) |
drivers/net/ethernet/intel/ice/virt/rss.c
201
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
207
ICE_FLOW_HASH_IPV4 | BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_PROT) |
drivers/net/ethernet/intel/ice/virt/rss.c
208
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
212
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_PROT) |
drivers/net/ethernet/intel/ice/virt/rss.c
213
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
215
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_SA)},
drivers/net/ethernet/intel/ice/virt/rss.c
217
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_DA)},
drivers/net/ethernet/intel/ice/virt/rss.c
223
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_SA) |
drivers/net/ethernet/intel/ice/virt/rss.c
224
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_PROT)},
drivers/net/ethernet/intel/ice/virt/rss.c
227
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_DA) |
drivers/net/ethernet/intel/ice/virt/rss.c
228
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_PROT)},
drivers/net/ethernet/intel/ice/virt/rss.c
232
ICE_FLOW_HASH_IPV6 | BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_PROT)},
drivers/net/ethernet/intel/ice/virt/rss.c
234
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_PROT)},
drivers/net/ethernet/intel/ice/virt/rss.c
237
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_ID)},
drivers/net/ethernet/intel/ice/virt/rss.c
244
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_PRE64_SA)},
drivers/net/ethernet/intel/ice/virt/rss.c
247
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_PRE64_DA)},
drivers/net/ethernet/intel/ice/virt/rss.c
253
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_PROT)},
drivers/net/ethernet/intel/ice/virt/rss.c
257
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_PRE64_SA) |
drivers/net/ethernet/intel/ice/virt/rss.c
258
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_PROT)},
drivers/net/ethernet/intel/ice/virt/rss.c
262
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_PRE64_DA) |
drivers/net/ethernet/intel/ice/virt/rss.c
263
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_PROT)},
drivers/net/ethernet/intel/ice/virt/rss.c
266
BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_SRC_PORT)},
drivers/net/ethernet/intel/ice/virt/rss.c
269
BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_DST_PORT)},
drivers/net/ethernet/intel/ice/virt/rss.c
276
BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
280
BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_SRC_PORT) |
drivers/net/ethernet/intel/ice/virt/rss.c
281
BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
285
BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_DST_PORT) |
drivers/net/ethernet/intel/ice/virt/rss.c
286
BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
292
BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
295
BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_SRC_PORT)},
drivers/net/ethernet/intel/ice/virt/rss.c
298
BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_DST_PORT)},
drivers/net/ethernet/intel/ice/virt/rss.c
305
BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
309
BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_SRC_PORT) |
drivers/net/ethernet/intel/ice/virt/rss.c
310
BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
314
BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_DST_PORT) |
drivers/net/ethernet/intel/ice/virt/rss.c
315
BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
321
BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
324
BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT)},
drivers/net/ethernet/intel/ice/virt/rss.c
327
BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_DST_PORT)},
drivers/net/ethernet/intel/ice/virt/rss.c
334
BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
338
BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT) |
drivers/net/ethernet/intel/ice/virt/rss.c
339
BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
343
BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_DST_PORT) |
drivers/net/ethernet/intel/ice/virt/rss.c
344
BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
350
BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_CHKSUM)},
drivers/net/ethernet/intel/ice/virt/rss.c
353
BIT_ULL(ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID)},
drivers/net/ethernet/intel/ice/virt/rss.c
356
BIT_ULL(ICE_FLOW_FIELD_IDX_GTPU_IP_TEID)},
drivers/net/ethernet/intel/ice/virt/rss.c
359
BIT_ULL(ICE_FLOW_FIELD_IDX_L2TPV3_SESS_ID)},
drivers/net/ethernet/intel/ice/virt/rss.c
361
BIT_ULL(ICE_FLOW_FIELD_IDX_ESP_SPI)},
drivers/net/ethernet/intel/ice/virt/rss.c
363
BIT_ULL(ICE_FLOW_FIELD_IDX_AH_SPI)},
drivers/net/ethernet/intel/ice/virt/rss.c
365
BIT_ULL(ICE_FLOW_FIELD_IDX_PFCP_SEID)},
drivers/net/ethernet/intel/ice/virt/rss.c
368
BIT_ULL(ICE_FLOW_FIELD_IDX_GTPC_TEID)},
drivers/net/ethernet/intel/ice/virt/rss.c
371
BIT_ULL(ICE_FLOW_FIELD_IDX_L2TPV2_SESS_ID)},
drivers/net/ethernet/intel/ice/virt/rss.c
374
BIT_ULL(ICE_FLOW_FIELD_IDX_L2TPV2_LEN_SESS_ID)},
drivers/net/ethernet/intel/ice/virt/rss.c
61
BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_SA)},
drivers/net/ethernet/intel/ice/virt/rss.c
63
BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_DA)},
drivers/net/ethernet/intel/ice/virt/rss.c
633
*hash_flds |= BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_ID);
drivers/net/ethernet/intel/ice/virt/rss.c
642
*hash_flds |= BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_ID);
drivers/net/ethernet/intel/ice/virt/rss.c
662
*hash_flds &= ~(BIT_ULL(ICE_FLOW_FIELD_IDX_ESP_SPI));
drivers/net/ethernet/intel/ice/virt/rss.c
663
*hash_flds |= BIT_ULL(ICE_FLOW_FIELD_IDX_NAT_T_ESP_SPI);
drivers/net/ethernet/intel/ice/virt/rss.c
69
BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_TYPE)},
drivers/net/ethernet/intel/ice/virt/rss.c
72
BIT_ULL(ICE_FLOW_FIELD_IDX_S_VLAN)},
drivers/net/ethernet/intel/ice/virt/rss.c
75
BIT_ULL(ICE_FLOW_FIELD_IDX_C_VLAN)},
drivers/net/ethernet/intel/ice/virt/rss.c
77
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA)},
drivers/net/ethernet/intel/ice/virt/rss.c
79
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA)},
drivers/net/ethernet/intel/ice/virt/rss.c
85
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) |
drivers/net/ethernet/intel/ice/virt/rss.c
86
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_PROT)},
drivers/net/ethernet/intel/ice/virt/rss.c
89
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA) |
drivers/net/ethernet/intel/ice/virt/rss.c
90
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_PROT)},
drivers/net/ethernet/intel/ice/virt/rss.c
94
ICE_FLOW_HASH_IPV4 | BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_PROT)},
drivers/net/ethernet/intel/ice/virt/rss.c
97
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_ID)},
drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h
41
(BIT_ULL(IDPF_HASH_NONF_IPV4_UDP) | \
drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h
42
BIT_ULL(IDPF_HASH_NONF_IPV4_SCTP) | \
drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h
43
BIT_ULL(IDPF_HASH_NONF_IPV4_TCP) | \
drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h
44
BIT_ULL(IDPF_HASH_NONF_IPV4_OTHER) | \
drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h
45
BIT_ULL(IDPF_HASH_FRAG_IPV4) | \
drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h
46
BIT_ULL(IDPF_HASH_NONF_IPV6_UDP) | \
drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h
47
BIT_ULL(IDPF_HASH_NONF_IPV6_TCP) | \
drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h
48
BIT_ULL(IDPF_HASH_NONF_IPV6_SCTP) | \
drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h
49
BIT_ULL(IDPF_HASH_NONF_IPV6_OTHER) | \
drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h
50
BIT_ULL(IDPF_HASH_FRAG_IPV6) | \
drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h
51
BIT_ULL(IDPF_HASH_L2_PAYLOAD))
drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h
54
BIT_ULL(IDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK) | \
drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h
55
BIT_ULL(IDPF_HASH_NONF_UNICAST_IPV4_UDP) | \
drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h
56
BIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV4_UDP) | \
drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h
57
BIT_ULL(IDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK) | \
drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h
58
BIT_ULL(IDPF_HASH_NONF_UNICAST_IPV6_UDP) | \
drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h
59
BIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV6_UDP))
drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h
63
#define IDPF_TXD_COMPLQ_GEN_M BIT_ULL(IDPF_TXD_COMPLQ_GEN_S)
drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h
72
#define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_M BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S)
drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h
81
BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_S)
drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h
86
#define IDPF_TXD_CTX_UDP_TUNNELING BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_NATT_S)
drivers/net/ethernet/intel/idpf/virtchnl2.h
198
VIRTCHNL2_CAP_RDMA = BIT_ULL(0),
drivers/net/ethernet/intel/idpf/virtchnl2.h
199
VIRTCHNL2_CAP_SRIOV = BIT_ULL(1),
drivers/net/ethernet/intel/idpf/virtchnl2.h
200
VIRTCHNL2_CAP_MACFILTER = BIT_ULL(2),
drivers/net/ethernet/intel/idpf/virtchnl2.h
204
VIRTCHNL2_CAP_SPLITQ_QSCHED = BIT_ULL(4),
drivers/net/ethernet/intel/idpf/virtchnl2.h
205
VIRTCHNL2_CAP_CRC = BIT_ULL(5),
drivers/net/ethernet/intel/idpf/virtchnl2.h
206
VIRTCHNL2_CAP_ADQ = BIT_ULL(6),
drivers/net/ethernet/intel/idpf/virtchnl2.h
207
VIRTCHNL2_CAP_WB_ON_ITR = BIT_ULL(7),
drivers/net/ethernet/intel/idpf/virtchnl2.h
208
VIRTCHNL2_CAP_PROMISC = BIT_ULL(8),
drivers/net/ethernet/intel/idpf/virtchnl2.h
209
VIRTCHNL2_CAP_LINK_SPEED = BIT_ULL(9),
drivers/net/ethernet/intel/idpf/virtchnl2.h
210
VIRTCHNL2_CAP_INLINE_IPSEC = BIT_ULL(10),
drivers/net/ethernet/intel/idpf/virtchnl2.h
211
VIRTCHNL2_CAP_LARGE_NUM_QUEUES = BIT_ULL(11),
drivers/net/ethernet/intel/idpf/virtchnl2.h
212
VIRTCHNL2_CAP_VLAN = BIT_ULL(12),
drivers/net/ethernet/intel/idpf/virtchnl2.h
213
VIRTCHNL2_CAP_PTP = BIT_ULL(13),
drivers/net/ethernet/intel/idpf/virtchnl2.h
215
VIRTCHNL2_CAP_EDT = BIT_ULL(14),
drivers/net/ethernet/intel/idpf/virtchnl2.h
216
VIRTCHNL2_CAP_ADV_RSS = BIT_ULL(15),
drivers/net/ethernet/intel/idpf/virtchnl2.h
218
VIRTCHNL2_CAP_RX_FLEX_DESC = BIT_ULL(17),
drivers/net/ethernet/intel/idpf/virtchnl2.h
219
VIRTCHNL2_CAP_PTYPE = BIT_ULL(18),
drivers/net/ethernet/intel/idpf/virtchnl2.h
220
VIRTCHNL2_CAP_LOOPBACK = BIT_ULL(19),
drivers/net/ethernet/intel/idpf/virtchnl2.h
222
VIRTCHNL2_CAP_FLOW_STEER = BIT_ULL(21),
drivers/net/ethernet/intel/idpf/virtchnl2.h
223
VIRTCHNL2_CAP_LAN_MEMORY_REGIONS = BIT_ULL(22),
drivers/net/ethernet/intel/idpf/virtchnl2.h
226
VIRTCHNL2_CAP_OEM = BIT_ULL(63),
drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h
50
#define VIRTCHNL2_RXDID_M(bit) BIT_ULL(VIRTCHNL2_RXDID_##bit)
drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h
65
BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_RAW_CSUM_INV_S)
drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h
70
BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_S)
drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h
73
BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_BUFQ_ID_S)
drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h
77
BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_S)
drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h
80
BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_SPH_S)
drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h
85
BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_MISS_S)
drivers/net/ethernet/intel/idpf/xdp.h
107
#define IDPF_XDP_RX_BUFQ BIT_ULL(47)
drivers/net/ethernet/intel/idpf/xdp.h
108
#define IDPF_XDP_RX_GEN BIT_ULL(46)
drivers/net/ethernet/intel/idpf/xdp.h
114
#define IDPF_XDP_RX_EOP BIT_ULL(1)
drivers/net/ethernet/intel/igb/igb_main.c
2625
~(BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
drivers/net/ethernet/intel/igb/igb_main.c
2626
BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
drivers/net/ethernet/intel/igb/igb_main.c
2627
BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
drivers/net/ethernet/intel/igb/igb_main.c
2628
BIT_ULL(FLOW_DISSECTOR_KEY_VLAN))) {
drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c
1557
BIT_ULL(highest_bit - 1);
drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c
1563
BIT_ULL(highest_bit - 1);
drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
11185
u64 qmask = BIT_ULL(ring);
drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
11282
ixgbe_irq_enable_queues(adapter, BIT_ULL(ring));
drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
3633
BIT_ULL(q_vector->v_idx));
drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
7998
eics |= BIT_ULL(i);
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
262
#define IXGBE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
263
#define IXGBE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
264
#define IXGBE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
265
#define IXGBE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
266
#define IXGBE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
267
#define IXGBE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
268
#define IXGBE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
269
#define IXGBE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
270
#define IXGBE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
271
#define IXGBE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
272
#define IXGBE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
273
#define IXGBE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
274
#define IXGBE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
275
#define IXGBE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
276
#define IXGBE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
277
#define IXGBE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
278
#define IXGBE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
279
#define IXGBE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
280
#define IXGBE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
281
#define IXGBE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
282
#define IXGBE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
283
#define IXGBE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
284
#define IXGBE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
285
#define IXGBE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
286
#define IXGBE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
287
#define IXGBE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
288
#define IXGBE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
289
#define IXGBE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
290
#define IXGBE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
291
#define IXGBE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
294
#define IXGBE_PHY_TYPE_HIGH_10BASE_T BIT_ULL(1)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
295
#define IXGBE_PHY_TYPE_HIGH_10M_SGMII BIT_ULL(2)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
296
#define IXGBE_PHY_TYPE_HIGH_2500M_SGMII BIT_ULL(56)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
297
#define IXGBE_PHY_TYPE_HIGH_100M_USXGMII BIT_ULL(57)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
298
#define IXGBE_PHY_TYPE_HIGH_1G_USXGMII BIT_ULL(58)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
299
#define IXGBE_PHY_TYPE_HIGH_2500M_USXGMII BIT_ULL(59)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
300
#define IXGBE_PHY_TYPE_HIGH_5G_USXGMII BIT_ULL(60)
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
301
#define IXGBE_PHY_TYPE_HIGH_10G_USXGMII BIT_ULL(61)
drivers/net/ethernet/intel/ixgbe/ixgbe_xsk.c
534
u64 eics = BIT_ULL(ring->q_vector->v_idx);
drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
720
intr_mask |= BIT_ULL(srn + i);
drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c
760
intr_mask |= BIT_ULL(srn + i);
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
159
#define CN93_R_OUT_INT_LEVELS_BMODE BIT_ULL(63)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
162
#define CN93_R_OUT_CTL_IDLE BIT_ULL(40)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
163
#define CN93_R_OUT_CTL_ES_I BIT_ULL(34)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
164
#define CN93_R_OUT_CTL_NSR_I BIT_ULL(33)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
165
#define CN93_R_OUT_CTL_ROR_I BIT_ULL(32)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
166
#define CN93_R_OUT_CTL_ES_D BIT_ULL(30)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
167
#define CN93_R_OUT_CTL_NSR_D BIT_ULL(29)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
168
#define CN93_R_OUT_CTL_ROR_D BIT_ULL(28)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
169
#define CN93_R_OUT_CTL_ES_P BIT_ULL(26)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
170
#define CN93_R_OUT_CTL_NSR_P BIT_ULL(25)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
171
#define CN93_R_OUT_CTL_ROR_P BIT_ULL(24)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
172
#define CN93_R_OUT_CTL_IMODE BIT_ULL(23)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
350
#define CN93_INTR_R_SEND_ISM BIT_ULL(63)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
351
#define CN93_INTR_R_OUT_INT BIT_ULL(62)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
352
#define CN93_INTR_R_IN_INT BIT_ULL(61)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
353
#define CN93_INTR_R_MBOX_INT BIT_ULL(60)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
354
#define CN93_INTR_R_RESEND BIT_ULL(59)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
355
#define CN93_INTR_R_CLR_TIM BIT_ULL(58)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
384
#define CN93_SDP_EPF_OEI_RINT_DATA_BIT_MBOX BIT_ULL(0)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
386
#define CN93_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT BIT_ULL(1)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
391
#define CN9K_PEM_GENMASK BIT_ULL(36)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
393
#define CN9K_PFX_CSX_PFCFGX_SHADOW_BIT BIT_ULL(16)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
395
#define CN9K_4BYTE_ALIGNED_ADDRESS_OFFSET(offset) ((offset) & BIT_ULL(2))
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
419
#define CN93_INT_ENA_BIT BIT_ULL(62)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
162
#define CNXK_R_OUT_INT_LEVELS_BMODE BIT_ULL(63)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
165
#define CNXK_R_OUT_CTL_IDLE BIT_ULL(40)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
166
#define CNXK_R_OUT_CTL_ES_I BIT_ULL(34)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
167
#define CNXK_R_OUT_CTL_NSR_I BIT_ULL(33)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
168
#define CNXK_R_OUT_CTL_ROR_I BIT_ULL(32)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
169
#define CNXK_R_OUT_CTL_ES_D BIT_ULL(30)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
170
#define CNXK_R_OUT_CTL_NSR_D BIT_ULL(29)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
171
#define CNXK_R_OUT_CTL_ROR_D BIT_ULL(28)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
172
#define CNXK_R_OUT_CTL_ES_P BIT_ULL(26)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
173
#define CNXK_R_OUT_CTL_NSR_P BIT_ULL(25)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
174
#define CNXK_R_OUT_CTL_ROR_P BIT_ULL(24)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
175
#define CNXK_R_OUT_CTL_IMODE BIT_ULL(23)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
366
#define CNXK_INTR_R_SEND_ISM BIT_ULL(63)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
367
#define CNXK_INTR_R_OUT_INT BIT_ULL(62)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
368
#define CNXK_INTR_R_IN_INT BIT_ULL(61)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
369
#define CNXK_INTR_R_MBOX_INT BIT_ULL(60)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
370
#define CNXK_INTR_R_RESEND BIT_ULL(59)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
371
#define CNXK_INTR_R_CLR_TIM BIT_ULL(58)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
396
#define CNXK_SDP_EPF_OEI_RINT_DATA_BIT_MBOX BIT_ULL(0)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
398
#define CNXK_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT BIT_ULL(1)
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
416
#define CNXK_INT_ENA_BIT BIT_ULL(62)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cn9k.h
120
#define CN93_VF_R_OUT_INT_LEVELS_BMODE BIT_ULL(63)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cn9k.h
123
#define CN93_VF_R_OUT_CTL_IDLE BIT_ULL(40)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cn9k.h
124
#define CN93_VF_R_OUT_CTL_ES_I BIT_ULL(34)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cn9k.h
125
#define CN93_VF_R_OUT_CTL_NSR_I BIT_ULL(33)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cn9k.h
126
#define CN93_VF_R_OUT_CTL_ROR_I BIT_ULL(32)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cn9k.h
127
#define CN93_VF_R_OUT_CTL_ES_D BIT_ULL(30)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cn9k.h
128
#define CN93_VF_R_OUT_CTL_NSR_D BIT_ULL(29)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cn9k.h
129
#define CN93_VF_R_OUT_CTL_ROR_D BIT_ULL(28)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cn9k.h
130
#define CN93_VF_R_OUT_CTL_ES_P BIT_ULL(26)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cn9k.h
131
#define CN93_VF_R_OUT_CTL_NSR_P BIT_ULL(25)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cn9k.h
132
#define CN93_VF_R_OUT_CTL_ROR_P BIT_ULL(24)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cn9k.h
133
#define CN93_VF_R_OUT_CTL_IMODE BIT_ULL(23)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cn9k.h
143
#define CN93_VF_SDP_R_MBOX_PF_VF_INT_ENAB BIT_ULL(1)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cn9k.h
144
#define CN93_VF_SDP_R_MBOX_PF_VF_INT_STATUS BIT_ULL(0)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cn9k.h
20
#define CN93_VF_RING_OFFSET BIT_ULL(17)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cn9k.h
69
#define CN93_VF_R_IN_CTL_IDLE BIT_ULL(28)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cn9k.h
71
#define CN93_VF_R_IN_CTL_IS_64B BIT_ULL(24)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cn9k.h
72
#define CN93_VF_R_IN_CTL_D_NSR BIT_ULL(8)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cn9k.h
73
#define CN93_VF_R_IN_CTL_D_ESR BIT_ULL(6)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cn9k.h
74
#define CN93_VF_R_IN_CTL_D_ROR BIT_ULL(5)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cn9k.h
75
#define CN93_VF_R_IN_CTL_NSR BIT_ULL(3)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cn9k.h
76
#define CN93_VF_R_IN_CTL_ESR BIT_ULL(1)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cn9k.h
77
#define CN93_VF_R_IN_CTL_ROR BIT_ULL(0)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cnxk.h
128
#define CNXK_VF_R_OUT_INT_LEVELS_BMODE BIT_ULL(63)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cnxk.h
131
#define CNXK_VF_R_OUT_CTL_IDLE BIT_ULL(40)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cnxk.h
132
#define CNXK_VF_R_OUT_CTL_ES_I BIT_ULL(34)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cnxk.h
133
#define CNXK_VF_R_OUT_CTL_NSR_I BIT_ULL(33)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cnxk.h
134
#define CNXK_VF_R_OUT_CTL_ROR_I BIT_ULL(32)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cnxk.h
135
#define CNXK_VF_R_OUT_CTL_ES_D BIT_ULL(30)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cnxk.h
136
#define CNXK_VF_R_OUT_CTL_NSR_D BIT_ULL(29)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cnxk.h
137
#define CNXK_VF_R_OUT_CTL_ROR_D BIT_ULL(28)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cnxk.h
138
#define CNXK_VF_R_OUT_CTL_ES_P BIT_ULL(26)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cnxk.h
139
#define CNXK_VF_R_OUT_CTL_NSR_P BIT_ULL(25)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cnxk.h
140
#define CNXK_VF_R_OUT_CTL_ROR_P BIT_ULL(24)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cnxk.h
141
#define CNXK_VF_R_OUT_CTL_IMODE BIT_ULL(23)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cnxk.h
151
#define CNXK_VF_SDP_R_MBOX_PF_VF_INT_ENAB BIT_ULL(1)
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cnxk.h
152
#define CNXK_VF_SDP_R_MBOX_PF_VF_INT_STATUS BIT_ULL(0)
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1201
args->mode = BIT_ULL(mode_baseidx);
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1210
set_mod_args(args, 10, 1, 1, BIT_ULL(CGX_MODE_SGMII_10M_BIT));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1213
set_mod_args(args, 10, 0, 1, BIT_ULL(CGX_MODE_SGMII_10M_BIT));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1216
set_mod_args(args, 100, 1, 1, BIT_ULL(CGX_MODE_SGMII_100M_BIT));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1219
set_mod_args(args, 100, 0, 1, BIT_ULL(CGX_MODE_SGMII_100M_BIT));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1222
set_mod_args(args, 1000, 1, 1, BIT_ULL(CGX_MODE_SGMII));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1225
set_mod_args(args, 1000, 0, 1, BIT_ULL(CGX_MODE_SGMII));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1228
set_mod_args(args, 1000, 0, 0, BIT_ULL(CGX_MODE_1000_BASEX));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1231
set_mod_args(args, 1000, 0, 1, BIT_ULL(CGX_MODE_QSGMII));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1234
set_mod_args(args, 10000, 0, 0, BIT_ULL(CGX_MODE_10G_C2C));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1237
set_mod_args(args, 10000, 0, 0, BIT_ULL(CGX_MODE_10G_C2M));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1240
set_mod_args(args, 10000, 0, 1, BIT_ULL(CGX_MODE_10G_KR));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1243
set_mod_args(args, 25000, 0, 0, BIT_ULL(CGX_MODE_25G_C2C));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1246
set_mod_args(args, 25000, 0, 1, BIT_ULL(CGX_MODE_25G_CR));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1249
set_mod_args(args, 25000, 0, 1, BIT_ULL(CGX_MODE_25G_KR));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1252
set_mod_args(args, 40000, 0, 0, BIT_ULL(CGX_MODE_40G_C2C));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1255
set_mod_args(args, 40000, 0, 0, BIT_ULL(CGX_MODE_40G_C2M));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1258
set_mod_args(args, 40000, 0, 1, BIT_ULL(CGX_MODE_40G_CR4));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1261
set_mod_args(args, 40000, 0, 1, BIT_ULL(CGX_MODE_40G_KR4));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1264
set_mod_args(args, 50000, 0, 0, BIT_ULL(CGX_MODE_50G_C2C));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1267
set_mod_args(args, 50000, 0, 0, BIT_ULL(CGX_MODE_50G_C2M));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1270
set_mod_args(args, 50000, 0, 1, BIT_ULL(CGX_MODE_50G_CR));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1273
set_mod_args(args, 50000, 0, 1, BIT_ULL(CGX_MODE_50G_KR));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1276
set_mod_args(args, 100000, 0, 0, BIT_ULL(CGX_MODE_100G_C2C));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1279
set_mod_args(args, 100000, 0, 0, BIT_ULL(CGX_MODE_100G_C2M));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1282
set_mod_args(args, 100000, 0, 1, BIT_ULL(CGX_MODE_100G_CR4));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1285
set_mod_args(args, 100000, 0, 1, BIT_ULL(CGX_MODE_100G_KR4));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1288
set_mod_args(args, 0, 1, 0, BIT_ULL(CGX_MODE_MAX));
drivers/net/ethernet/marvell/octeontx2/af/cgx.c
1739
lmac_list &= ~BIT_ULL(lmac->lmac_id);
drivers/net/ethernet/marvell/octeontx2/af/cgx.h
29
#define DATA_PKT_TX_EN BIT_ULL(53)
drivers/net/ethernet/marvell/octeontx2/af/cgx.h
30
#define DATA_PKT_RX_EN BIT_ULL(54)
drivers/net/ethernet/marvell/octeontx2/af/cgx.h
34
#define FW_CGX_INT BIT_ULL(1)
drivers/net/ethernet/marvell/octeontx2/af/cgx.h
36
#define CGX_NIX0_RESET BIT_ULL(2)
drivers/net/ethernet/marvell/octeontx2/af/cgx.h
37
#define CGX_NIX1_RESET BIT_ULL(3)
drivers/net/ethernet/marvell/octeontx2/af/cgx.h
38
#define CGX_NSCI_DROP BIT_ULL(9)
drivers/net/ethernet/marvell/octeontx2/af/cgx.h
45
#define CGX_DMAC_CTL0_CAM_ENABLE BIT_ULL(3)
drivers/net/ethernet/marvell/octeontx2/af/cgx.h
46
#define CGX_DMAC_CAM_ACCEPT BIT_ULL(3)
drivers/net/ethernet/marvell/octeontx2/af/cgx.h
47
#define CGX_DMAC_MCAST_MODE_CAM BIT_ULL(2)
drivers/net/ethernet/marvell/octeontx2/af/cgx.h
48
#define CGX_DMAC_MCAST_MODE BIT_ULL(1)
drivers/net/ethernet/marvell/octeontx2/af/cgx.h
49
#define CGX_DMAC_BCAST_MODE BIT_ULL(0)
drivers/net/ethernet/marvell/octeontx2/af/cgx.h
51
#define CGX_DMAC_CAM_ADDR_ENABLE BIT_ULL(48)
drivers/net/ethernet/marvell/octeontx2/af/cgx.h
67
#define CGXX_SPUX_CONTROL1_LBK BIT_ULL(14)
drivers/net/ethernet/marvell/octeontx2/af/cgx.h
69
#define CGXX_GMP_PCS_MRX_CTL_LBK BIT_ULL(14)
drivers/net/ethernet/marvell/octeontx2/af/cgx.h
72
#define CGX_SMUX_RX_FRM_CTL_CTL_BCK BIT_ULL(3)
drivers/net/ethernet/marvell/octeontx2/af/cgx.h
73
#define CGX_SMUX_RX_FRM_CTL_PTP_MODE BIT_ULL(12)
drivers/net/ethernet/marvell/octeontx2/af/cgx.h
75
#define CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK BIT_ULL(3)
drivers/net/ethernet/marvell/octeontx2/af/cgx.h
76
#define CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE BIT_ULL(12)
drivers/net/ethernet/marvell/octeontx2/af/cgx.h
82
#define CGXX_SMUX_CBFC_CTL_RX_EN BIT_ULL(0)
drivers/net/ethernet/marvell/octeontx2/af/cgx.h
83
#define CGXX_SMUX_CBFC_CTL_TX_EN BIT_ULL(1)
drivers/net/ethernet/marvell/octeontx2/af/cgx.h
84
#define CGXX_SMUX_CBFC_CTL_DRP_EN BIT_ULL(2)
drivers/net/ethernet/marvell/octeontx2/af/cgx.h
85
#define CGXX_SMUX_CBFC_CTL_BCK_EN BIT_ULL(3)
drivers/net/ethernet/marvell/octeontx2/af/cgx.h
89
#define CGX_SMUX_TX_CTL_L2P_BP_CONV BIT_ULL(7)
drivers/net/ethernet/marvell/octeontx2/af/cgx.h
91
#define CGX_CMR_RX_OVR_BP_EN(X) BIT_ULL(((X) + 8))
drivers/net/ethernet/marvell/octeontx2/af/cgx.h
92
#define CGX_CMR_RX_OVR_BP_BP(X) BIT_ULL(((X) + 4))
drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h
191
#define EVTREG_ACK BIT_ULL(0)
drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h
192
#define EVTREG_EVT_TYPE BIT_ULL(1)
drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h
193
#define EVTREG_STAT BIT_ULL(2)
drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h
263
#define CMDREG_OWN BIT_ULL(0)
drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h
270
#define CMDREG_ENABLE BIT_ULL(8)
drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h
276
#define CMDLINKCHANGE_LINKUP BIT_ULL(8)
drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h
277
#define CMDLINKCHANGE_FULLDPLX BIT_ULL(9)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
1114
#define TXSCHQ_FREE_ALL BIT_ULL(0)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
1127
#define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
1658
#define PTP_CAP_HW_ATOMIC_UPDATE BIT_ULL(0)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
1688
#define RVU_EVENT_PORT_STATE BIT_ULL(0)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
1689
#define RVU_EVENT_PFVF_STATE BIT_ULL(1)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
1690
#define RVU_EVENT_MTU_CHANGE BIT_ULL(2)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
1691
#define RVU_EVENT_RX_MODE_CHANGE BIT_ULL(3)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
1692
#define RVU_EVENT_MAC_ADDR_CHANGE BIT_ULL(4)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
1873
#define RESET_VF_PERM BIT_ULL(0)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
1874
#define VF_TRUSTED BIT_ULL(1)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
2452
#define MCS_CPM_RX_SECTAG_V_EQ1_INT BIT_ULL(0)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
2453
#define MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT BIT_ULL(1)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
2454
#define MCS_CPM_RX_SECTAG_SL_GTE48_INT BIT_ULL(2)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
2455
#define MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT BIT_ULL(3)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
2456
#define MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
2457
#define MCS_CPM_RX_PACKET_XPN_EQ0_INT BIT_ULL(5)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
2458
#define MCS_CPM_RX_PN_THRESH_REACHED_INT BIT_ULL(6)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
2459
#define MCS_CPM_TX_PACKET_XPN_EQ0_INT BIT_ULL(7)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
2460
#define MCS_CPM_TX_PN_THRESH_REACHED_INT BIT_ULL(8)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
2461
#define MCS_CPM_TX_SA_NOT_VALID_INT BIT_ULL(9)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
2462
#define MCS_BBE_RX_DFIFO_OVERFLOW_INT BIT_ULL(10)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
2463
#define MCS_BBE_RX_PLFIFO_OVERFLOW_INT BIT_ULL(11)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
2464
#define MCS_BBE_TX_DFIFO_OVERFLOW_INT BIT_ULL(12)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
2465
#define MCS_BBE_TX_PLFIFO_OVERFLOW_INT BIT_ULL(13)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
2466
#define MCS_PAB_RX_CHAN_OVERFLOW_INT BIT_ULL(14)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
2467
#define MCS_PAB_TX_CHAN_OVERFLOW_INT BIT_ULL(15)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
39
#define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
540
#define HW_CAP_MACSEC BIT_ULL(1)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
721
#define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
722
#define RVU_LMAC_FEAT_HIGIG2 BIT_ULL(1)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
724
#define RVU_LMAC_FEAT_PTP BIT_ULL(2) /* precison time protocol */
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
725
#define RVU_LMAC_FEAT_DMACF BIT_ULL(3) /* DMAC FILTER */
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
726
#define RVU_MAC_VERSION BIT_ULL(4)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
727
#define RVU_MAC_CGX BIT_ULL(5)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
728
#define RVU_MAC_RPM BIT_ULL(6)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
760
#define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
761
#define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
763
#define PKIND_TX BIT_ULL(0)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
764
#define PKIND_RX BIT_ULL(1)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
948
#define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
949
#define NIX_LF_LBK_BLK_SEL BIT_ULL(1)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
975
#define NIX_LF_DISABLE_FLOWS BIT_ULL(0)
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
976
#define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1)
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
1069
mcs_reg_write(mcs, MCSX_IP_INT, BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
1070
mcs_reg_write(mcs, MCSX_IP_INT_ENA_W1S, BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
1159
mcs_reg_write(mcs, MCSX_IP_INT_ENA_W1S, BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
1252
val |= BIT_ULL(req->port_id);
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
1254
val &= ~BIT_ULL(req->port_id);
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
1277
if (mcs_reg_read(mcs, MCSX_PEX_RX_SLAVE_PEX_CONFIGURATION) & BIT_ULL(req->port_id))
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
1356
val = BIT_ULL(0) | (0x8100ull & 0xFFFF) << 1 | BIT_ULL(17);
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
1366
val = BIT_ULL(0) | (0x88a8ull & 0xFFFF) << 1 | BIT_ULL(18);
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
1422
val |= BIT_ULL(5);
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
1426
while (!(mcs_reg_read(mcs, MCSX_MIL_RX_GBL_STATUS) & BIT_ULL(0))) {
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
1439
if (val & BIT_ULL(1 + i))
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
1445
mcs_reg_write(mcs, MCSX_MIL_GLOBAL, mcs_reg_read(mcs, MCSX_MIL_GLOBAL) & ~BIT_ULL(5));
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
1457
val |= BIT_ULL(6);
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
1459
val &= ~BIT_ULL(6);
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
1475
mcs_reg_write(mcs, MCSX_IP_MODE, BIT_ULL(3));
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
266
mcs_reg_write(mcs, reg, BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
399
val = mcs_reg_read(mcs, reg) | BIT_ULL(sc_id);
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
401
val = mcs_reg_read(mcs, reg) & ~BIT_ULL(sc_id);
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
460
val = mcs_reg_read(mcs, reg) | BIT_ULL(flow_id);
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
462
val = mcs_reg_read(mcs, reg) & ~BIT_ULL(flow_id);
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
520
plcy = BIT_ULL(0) | 0x3ull << 4;
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
524
plcy = BIT_ULL(0) | GENMASK_ULL(43, 28);
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
526
plcy = BIT_ULL(0) | GENMASK_ULL(63, 48);
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
598
dis &= ~BIT_ULL(id);
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
606
dis &= ~BIT_ULL(req->rule_idx);
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
630
if (!(req->data0 & BIT_ULL(40)))
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
640
if (!(req->data0 & BIT_ULL(40)) || !(req->data1 & BIT_ULL(40)))
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
658
if (req->data2 != ETH_P_PAE || !(req->data0 & BIT_ULL(40)) ||
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
659
!(req->data1 & BIT_ULL(40)))
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
680
if (!(req->data0 & BIT_ULL(40)))
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
694
enb |= BIT_ULL(req->rule_idx);
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
889
if (!(intr & BIT_ULL(sa)))
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
948
if (intr & BIT_ULL(1))
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
958
if (!(val & BIT_ULL(lmac)))
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
973
if (intr & BIT_ULL(lmac))
drivers/net/ethernet/marvell/octeontx2/af/mcs.c
984
mcs_reg_write(mcs, MCSX_IP_INT_ENA_W1C, BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/af/mcs.h
56
#define MCS_BBE_RX_INT_ENA BIT_ULL(0)
drivers/net/ethernet/marvell/octeontx2/af/mcs.h
57
#define MCS_BBE_TX_INT_ENA BIT_ULL(1)
drivers/net/ethernet/marvell/octeontx2/af/mcs.h
58
#define MCS_CPM_RX_INT_ENA BIT_ULL(2)
drivers/net/ethernet/marvell/octeontx2/af/mcs.h
59
#define MCS_CPM_TX_INT_ENA BIT_ULL(3)
drivers/net/ethernet/marvell/octeontx2/af/mcs.h
60
#define MCS_PAB_RX_INT_ENA BIT_ULL(4)
drivers/net/ethernet/marvell/octeontx2/af/mcs.h
61
#define MCS_PAB_TX_INT_ENA BIT_ULL(5)
drivers/net/ethernet/marvell/octeontx2/af/mcs.h
63
#define MCS_CPM_TX_INT_PACKET_XPN_EQ0 BIT_ULL(0)
drivers/net/ethernet/marvell/octeontx2/af/mcs.h
64
#define MCS_CPM_TX_INT_PN_THRESH_REACHED BIT_ULL(1)
drivers/net/ethernet/marvell/octeontx2/af/mcs.h
65
#define MCS_CPM_TX_INT_SA_NOT_VALID BIT_ULL(2)
drivers/net/ethernet/marvell/octeontx2/af/mcs.h
67
#define MCS_CPM_RX_INT_SECTAG_V_EQ1 BIT_ULL(0)
drivers/net/ethernet/marvell/octeontx2/af/mcs.h
68
#define MCS_CPM_RX_INT_SECTAG_E_EQ0_C_EQ1 BIT_ULL(1)
drivers/net/ethernet/marvell/octeontx2/af/mcs.h
69
#define MCS_CPM_RX_INT_SL_GTE48 BIT_ULL(2)
drivers/net/ethernet/marvell/octeontx2/af/mcs.h
70
#define MCS_CPM_RX_INT_ES_EQ1_SC_EQ1 BIT_ULL(3)
drivers/net/ethernet/marvell/octeontx2/af/mcs.h
71
#define MCS_CPM_RX_INT_SC_EQ1_SCB_EQ1 BIT_ULL(4)
drivers/net/ethernet/marvell/octeontx2/af/mcs.h
72
#define MCS_CPM_RX_INT_PACKET_XPN_EQ0 BIT_ULL(5)
drivers/net/ethernet/marvell/octeontx2/af/mcs.h
73
#define MCS_CPM_RX_INT_PN_THRESH_REACHED BIT_ULL(6)
drivers/net/ethernet/marvell/octeontx2/af/mcs_cnf10kb.c
103
val |= BIT_ULL(map->sc_id);
drivers/net/ethernet/marvell/octeontx2/af/mcs_cnf10kb.c
105
val &= ~BIT_ULL(map->sc_id);
drivers/net/ethernet/marvell/octeontx2/af/mcs_cnf10kb.c
133
val |= BIT_ULL(4);
drivers/net/ethernet/marvell/octeontx2/af/mcs_cnf10kb.c
137
while (!(mcs_reg_read(mcs, MCSX_MIL_IP_GBL_STATUS) & BIT_ULL(0))) {
drivers/net/ethernet/marvell/octeontx2/af/mcs_cnf10kb.c
144
val &= ~BIT_ULL(4);
drivers/net/ethernet/marvell/octeontx2/af/mcs_cnf10kb.c
232
if (!(intr & BIT_ULL(i)))
drivers/net/ethernet/marvell/octeontx2/af/mcs_cnf10kb.c
266
if (!(intr & BIT_ULL(i)))
drivers/net/ethernet/marvell/octeontx2/af/mcs_cnf10kb.c
44
val = (0x8100ull & 0xFFFF) | BIT_ULL(20) | BIT_ULL(22);
drivers/net/ethernet/marvell/octeontx2/af/mcs_cnf10kb.c
53
val = (0x88a8ull & 0xFFFF) | BIT_ULL(20) | BIT_ULL(23);
drivers/net/ethernet/marvell/octeontx2/af/mcs_cnf10kb.c
64
val = BIT_ULL(0) | BIT_ULL(1) | BIT_ULL(12);
drivers/net/ethernet/marvell/octeontx2/af/mcs_rvu_if.c
419
if (mcs->hw->lmac_cnt <= req->port_id || !(mcs->hw->lmac_bmap & BIT_ULL(req->port_id)))
drivers/net/ethernet/marvell/octeontx2/af/mcs_rvu_if.c
437
if (mcs->hw->lmac_cnt <= req->port_id || !(mcs->hw->lmac_bmap & BIT_ULL(req->port_id)))
drivers/net/ethernet/marvell/octeontx2/af/mcs_rvu_if.c
55
cfg |= BIT_ULL(lmac_id);
drivers/net/ethernet/marvell/octeontx2/af/mcs_rvu_if.c
57
cfg &= ~BIT_ULL(lmac_id);
drivers/net/ethernet/marvell/octeontx2/af/mcs_rvu_if.c
66
cfg |= BIT_ULL(0);
drivers/net/ethernet/marvell/octeontx2/af/mcs_rvu_if.c
68
cfg &= ~BIT_ULL(0);
drivers/net/ethernet/marvell/octeontx2/af/mcs_rvu_if.c
83
if (BIT_ULL(req->lmac_id) & mcs->hw->lmac_bmap)
drivers/net/ethernet/marvell/octeontx2/af/npc.h
420
#define NPC_EXACT_NIBBLE_HIT BIT_ULL(40)
drivers/net/ethernet/marvell/octeontx2/af/npc.h
421
#define NPC_EXACT_NIBBLE_OPC BIT_ULL(40)
drivers/net/ethernet/marvell/octeontx2/af/npc.h
422
#define NPC_EXACT_NIBBLE_WAY BIT_ULL(40)
drivers/net/ethernet/marvell/octeontx2/af/npc.h
425
#define NPC_EXACT_RESULT_HIT BIT_ULL(0)
drivers/net/ethernet/marvell/octeontx2/af/npc.h
435
#define NPC_PARSE_NIBBLE_ERRLEV BIT_ULL(3)
drivers/net/ethernet/marvell/octeontx2/af/npc.h
437
#define NPC_PARSE_NIBBLE_L2L3_BCAST BIT_ULL(6)
drivers/net/ethernet/marvell/octeontx2/af/npc.h
439
#define NPC_PARSE_NIBBLE_LA_LTYPE BIT_ULL(9)
drivers/net/ethernet/marvell/octeontx2/af/npc.h
441
#define NPC_PARSE_NIBBLE_LB_LTYPE BIT_ULL(12)
drivers/net/ethernet/marvell/octeontx2/af/npc.h
443
#define NPC_PARSE_NIBBLE_LC_LTYPE BIT_ULL(15)
drivers/net/ethernet/marvell/octeontx2/af/npc.h
445
#define NPC_PARSE_NIBBLE_LD_LTYPE BIT_ULL(18)
drivers/net/ethernet/marvell/octeontx2/af/npc.h
447
#define NPC_PARSE_NIBBLE_LE_LTYPE BIT_ULL(21)
drivers/net/ethernet/marvell/octeontx2/af/npc.h
449
#define NPC_PARSE_NIBBLE_LF_LTYPE BIT_ULL(24)
drivers/net/ethernet/marvell/octeontx2/af/npc.h
451
#define NPC_PARSE_NIBBLE_LG_LTYPE BIT_ULL(27)
drivers/net/ethernet/marvell/octeontx2/af/npc.h
453
#define NPC_PARSE_NIBBLE_LH_LTYPE BIT_ULL(30)
drivers/net/ethernet/marvell/octeontx2/af/npc.h
472
#define RX_VTAG0_VALID_BIT BIT_ULL(15)
drivers/net/ethernet/marvell/octeontx2/af/npc.h
476
#define RX_VTAG1_VALID_BIT BIT_ULL(47)
drivers/net/ethernet/marvell/octeontx2/af/ptp.c
37
#define PTP_CLOCK_CFG_PTP_EN BIT_ULL(0)
drivers/net/ethernet/marvell/octeontx2/af/ptp.c
38
#define PTP_CLOCK_CFG_EXT_CLK_EN BIT_ULL(1)
drivers/net/ethernet/marvell/octeontx2/af/ptp.c
40
#define PTP_CLOCK_CFG_TSTMP_EDGE BIT_ULL(9)
drivers/net/ethernet/marvell/octeontx2/af/ptp.c
41
#define PTP_CLOCK_CFG_TSTMP_EN BIT_ULL(8)
drivers/net/ethernet/marvell/octeontx2/af/ptp.c
44
#define PTP_CLOCK_CFG_PPS_EN BIT_ULL(30)
drivers/net/ethernet/marvell/octeontx2/af/ptp.c
45
#define PTP_CLOCK_CFG_PPS_INV BIT_ULL(31)
drivers/net/ethernet/marvell/octeontx2/af/rpm.c
18
.int_ena_bit = BIT_ULL(0),
drivers/net/ethernet/marvell/octeontx2/af/rpm.c
461
cfg |= RPMX_CMD_CLEAR_TX | RPMX_CMD_CLEAR_RX | BIT_ULL(lmac_id);
drivers/net/ethernet/marvell/octeontx2/af/rpm.c
53
.int_ena_bit = BIT_ULL(0),
drivers/net/ethernet/marvell/octeontx2/af/rpm.h
107
#define RPM2_CMR_RX_OVR_BP_EN BIT_ULL(2)
drivers/net/ethernet/marvell/octeontx2/af/rpm.h
108
#define RPM2_CMR_RX_OVR_BP_BP BIT_ULL(1)
drivers/net/ethernet/marvell/octeontx2/af/rpm.h
116
#define RPM2_USX_PCS_LBK BIT_ULL(14)
drivers/net/ethernet/marvell/octeontx2/af/rpm.h
21
#define RPM_NIX0_RESET BIT_ULL(3)
drivers/net/ethernet/marvell/octeontx2/af/rpm.h
22
#define RPMX_RX_TS_PREPEND BIT_ULL(22)
drivers/net/ethernet/marvell/octeontx2/af/rpm.h
23
#define RPMX_TX_PTP_1S_SUPPORT BIT_ULL(17)
drivers/net/ethernet/marvell/octeontx2/af/rpm.h
30
#define RPMX_MTI_PCS_LBK BIT_ULL(14)
drivers/net/ethernet/marvell/octeontx2/af/rpm.h
36
#define RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE BIT_ULL(29)
drivers/net/ethernet/marvell/octeontx2/af/rpm.h
37
#define RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE BIT_ULL(28)
drivers/net/ethernet/marvell/octeontx2/af/rpm.h
38
#define RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE BIT_ULL(8)
drivers/net/ethernet/marvell/octeontx2/af/rpm.h
39
#define RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE BIT_ULL(19)
drivers/net/ethernet/marvell/octeontx2/af/rpm.h
57
#define RPMX_CMR_RX_OVR_BP_EN(x) BIT_ULL((x) + 8)
drivers/net/ethernet/marvell/octeontx2/af/rpm.h
58
#define RPMX_CMR_RX_OVR_BP_BP(x) BIT_ULL((x) + 4)
drivers/net/ethernet/marvell/octeontx2/af/rpm.h
65
#define RPM_TX_EN BIT_ULL(0)
drivers/net/ethernet/marvell/octeontx2/af/rpm.h
66
#define RPM_RX_EN BIT_ULL(1)
drivers/net/ethernet/marvell/octeontx2/af/rpm.h
73
#define RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_PAD_EN BIT_ULL(11)
drivers/net/ethernet/marvell/octeontx2/af/rpm.h
74
#define RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE BIT_ULL(8)
drivers/net/ethernet/marvell/octeontx2/af/rpm.h
75
#define RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_FWD BIT_ULL(7)
drivers/net/ethernet/marvell/octeontx2/af/rpm.h
82
#define RPMX_ONESTEP_ENABLE BIT_ULL(5)
drivers/net/ethernet/marvell/octeontx2/af/rpm.h
83
#define RPMX_TS_BINARY_MODE BIT_ULL(11)
drivers/net/ethernet/marvell/octeontx2/af/rpm.h
89
#define RPMX_RSFEC_RX_CAPTURE BIT_ULL(28)
drivers/net/ethernet/marvell/octeontx2/af/rpm.h
90
#define RPMX_CMD_CLEAR_RX BIT_ULL(30)
drivers/net/ethernet/marvell/octeontx2/af/rpm.h
91
#define RPMX_CMD_CLEAR_TX BIT_ULL(31)
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2068
rvu_write64(rvu, lfblkaddr, lfoffset, BIT_ULL(12) | lfidx);
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2069
return rvu_poll_reg(rvu, lfblkaddr, lfoffset, BIT_ULL(12), true);
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2533
if (cfg & BIT_ULL(20))
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2675
if (!(intr & BIT_ULL(i - first)))
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2859
rvupf_write64(rvu, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2860
rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2887
rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, BIT_ULL(pf));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2890
rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, BIT_ULL(pf));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2906
if (!(intr & BIT_ULL(vf)))
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2909
rvupf_write64(rvu, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2910
rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(reg), BIT_ULL(vf));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2931
BIT_ULL(pf));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2934
BIT_ULL(pf));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2958
rvupf_write64(rvu, RVU_PF_VFTRPENDX(idx), BIT_ULL(vf));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2960
rvupf_write64(rvu, RVU_PF_VFME_INTX(idx), BIT_ULL(vf));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2999
BIT_ULL(pf));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
3002
BIT_ULL(pf));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
3279
cfg | BIT_ULL(22));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
482
if (cfg & BIT_ULL(11))
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
507
rvu_write64(rvu, block->addr, block->lfreset_reg, lf | BIT_ULL(12));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
508
err = rvu_poll_reg(rvu, block->addr, block->lfreset_reg, BIT_ULL(12),
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
521
rvu_write64(rvu, blkaddr, rst_reg, BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
522
err = rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true);
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
525
while (rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true) == -EBUSY)
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
557
if (!(cfg & BIT_ULL(63)))
drivers/net/ethernet/marvell/octeontx2/af/rvu.h
335
#define NIX_TXSCHQ_FREE BIT_ULL(1)
drivers/net/ethernet/marvell/octeontx2/af/rvu.h
336
#define NIX_TXSCHQ_CFG_DONE BIT_ULL(0)
drivers/net/ethernet/marvell/octeontx2/af/rvu.h
815
if (!(npc_const3 & BIT_ULL(62)))
drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
19
#define LMT_MAP_ENTRY_ENA BIT_ULL(20)
drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
323
if (!(nix_const & BIT_ULL(60)))
drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
57
rvu_write64(rvu, BLKADDR_APR, APR_AF_LMT_CTL, BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
573
cfg |= BIT_ULL(1) | BIT_ULL(2);
drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
87
val = BIT_ULL(63) | BIT_ULL(14) | BIT_ULL(13) | pf << 8 |
drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
91
err = rvu_poll_reg(rvu, BLKADDR_RVUM, RVU_AF_SMMU_ADDR_RSP_STS, BIT_ULL(0), false);
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
1081
inprog |= BIT_ULL(16);
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
1130
reg = BIT_ULL(16) | pcifunc;
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
116
block->cpt_flt_eng_map[vec] |= BIT_ULL(i);
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
120
block->cpt_rcvrd_eng_map[vec] |= BIT_ULL(i);
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
1200
BIT_ULL(22) - 1);
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
1270
reg = BIT_ULL(16) | pcifunc;
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
1278
reg = BIT_ULL(46) | FIELD_GET(CTX_CAM_CPTR, cam_data);
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
568
if (req->enable && (val & BIT_ULL(16))) {
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
582
val |= BIT_ULL(9);
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
584
val &= ~BIT_ULL(9);
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
623
if (req->enable && (val & BIT_ULL(9))) {
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
637
val |= BIT_ULL(16);
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
639
val &= ~BIT_ULL(16);
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
285
if (intr_val & BIT_ULL(0))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
294
if (intr_val & BIT_ULL(0))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
296
if (intr_val & BIT_ULL(1))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
298
if (intr_val & BIT_ULL(4))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
307
if (intr_val & BIT_ULL(14))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
309
if (intr_val & BIT_ULL(13))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
311
if (intr_val & BIT_ULL(12))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
313
if (intr_val & BIT_ULL(6))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
315
if (intr_val & BIT_ULL(5))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
317
if (intr_val & BIT_ULL(4))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
319
if (intr_val & BIT_ULL(3))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
321
if (intr_val & BIT_ULL(2))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
323
if (intr_val & BIT_ULL(1))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
325
if (intr_val & BIT_ULL(0))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
335
if (intr_val & BIT_ULL(34))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
337
if (intr_val & BIT_ULL(33))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
339
if (intr_val & BIT_ULL(32))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
341
if (intr_val & BIT_ULL(4))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
343
if (intr_val & BIT_ULL(3))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
345
if (intr_val & BIT_ULL(2))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
347
if (intr_val & BIT_ULL(1))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
349
if (intr_val & BIT_ULL(0))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
834
if (intr_val & BIT_ULL(32))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
879
if (npa_event_context->npa_af_rvu_err & BIT_ULL(14))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
881
if (npa_event_context->npa_af_rvu_err & BIT_ULL(13))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
883
if (npa_event_context->npa_af_rvu_err & BIT_ULL(12))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
891
if (npa_event_context->npa_af_rvu_ras & BIT_ULL(34))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
893
if (npa_event_context->npa_af_rvu_ras & BIT_ULL(33))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
895
if (npa_event_context->npa_af_rvu_ras & BIT_ULL(32))
drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c
903
if (npa_event_context->npa_af_rvu_int & BIT_ULL(0))
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
1091
if (!(cfg & BIT_ULL(4)) || !pfvf->rss_ctx ||
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
1581
cfg = BIT_ULL(36) | (req->rq_cnt - 1) | req->way_mask << 20;
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
1597
cfg = BIT_ULL(36) | (req->sq_cnt - 1) | req->way_mask << 20;
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
1613
cfg = BIT_ULL(36) | (req->cq_cnt - 1) | req->way_mask << 20;
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
1636
BIT_ULL(36) | req->way_mask << 20);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
1649
BIT_ULL(36) | req->way_mask << 20);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
1659
rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_CFG2(nixlf), BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
1900
} while (!(dbgval & BIT_ULL(32)) && (dbgval & BIT_ULL(48)));
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
1991
rvu_write64(rvu, blkaddr, cir_reg, cfg & ~BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
1996
rvu_write64(rvu, blkaddr, pir_reg, cfg & ~BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
244
return BIT_ULL(dwrr_mtu);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
2477
cfg |= BIT_ULL(50);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
2484
if (!(cfg & BIT_ULL(12)))
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
2486
bmap |= BIT_ULL(i);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
2487
cfg &= ~BIT_ULL(12);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
2494
cfg |= BIT_ULL(50) | BIT_ULL(49);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
2499
NIX_AF_SMQX_CFG(smq), BIT_ULL(49), true);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
2507
if (!(bmap & BIT_ULL(i)))
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
2511
cfg |= BIT_ULL(12);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
256
if (bytes > BIT_ULL(16))
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
276
rvu_write64(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
277
err = rvu_poll_reg(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0), true);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
2838
cfg = enable ? (BIT_ULL(12) | RVU_SWITCH_LBK_CHAN) : 0;
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
287
rvu_write64(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
288
err = rvu_poll_reg(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0), true);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
2933
regval &= ~BIT_ULL(13);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
2950
(regval & BIT_ULL(49))) {
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
2953
regval &= ~BIT_ULL(49);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
2975
regval |= BIT_ULL(5);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
2977
regval |= BIT_ULL(4);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
3673
size = BIT_ULL(size);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
3703
BIT_ULL(36) | (hw->max_vfs_per_pf << 4) | MC_TBL_SIZE);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
3722
BIT_ULL(63) | (mcast->replay_pkind << 24) |
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
3723
BIT_ULL(20) | MC_BUF_CNT);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
4690
cfg |= BIT_ULL(41);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
4692
cfg &= ~BIT_ULL(41);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
4695
cfg |= BIT_ULL(40);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
4697
cfg &= ~BIT_ULL(40);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
4700
cfg |= BIT_ULL(32);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
4702
cfg &= ~BIT_ULL(32);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
4705
cfg |= BIT_ULL(37);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
4707
cfg &= ~BIT_ULL(37);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
4785
cfg = (tx_credits << 12) | (0x1FF << 2) | BIT_ULL(1);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
4801
tx_credits = (tx_credits << 12) | (0x1FF << 2) | BIT_ULL(1);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
4814
rvu_read64(rvu, blkaddr, NIX_AF_CFG) | BIT_ULL(9));
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
4817
NIX_AF_STATUS, BIT_ULL(10), false);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
4828
(status & (BIT_ULL(16 + idx))))
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
4836
if (!(status & BIT_ULL(19))) {
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
4844
rvu_read64(rvu, blkaddr, NIX_AF_CFG) & ~BIT_ULL(9));
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
4861
cfg |= BIT_ULL(8);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
4864
cfg &= ~BIT_ULL(8);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
4911
if ((((hw_const >> 56) & 0x10) == 0x10) && !(hw_const & BIT_ULL(61)))
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
4914
if (hw_const & BIT_ULL(61))
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
4948
cfg &= ~(BIT_ULL(15) | BIT_ULL(14) | BIT_ULL(23));
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
4952
cfg |= BIT_ULL(21);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
5097
rvu_write64(rvu, blkaddr, NIX_AF_RX_CFG, BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
5394
#define NIX_AF_LFX_TX_CFG_PTP_EN BIT_ULL(32)
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
5516
val |= BIT_ULL(51);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
5621
val |= BIT_ULL(46);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
5725
if (!(cfg & BIT_ULL(61))) {
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
616
cfg & ~BIT_ULL(16));
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
771
cfg | (bpid & GENMASK_ULL(8, 0)) | BIT_ULL(16));
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
870
rvu_write64(rvu, blkaddr, NIX_AF_LSO_CFG, cfg | BIT_ULL(63));
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
952
val = BIT_ULL(36) | BIT_ULL(4) | way_mask << 20 |
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
956
val |= BIT_ULL(5);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
400
cfg &= ~(BIT_ULL(34) - 1);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
402
cfg |= (req->aura_sz << 16) | BIT_ULL(34) | req->way_mask;
drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
412
BIT_ULL(36) | req->way_mask << 20);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
492
cfg |= BIT_ULL(1);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
495
cfg &= ~BIT_ULL(1);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
505
cfg |= BIT_ULL(6) | BIT_ULL(2) | BIT_ULL(1);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
605
if (!(reg & BIT_ULL(63)) && (reg & BIT_ULL(60))) {
drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
608
reg & ~BIT_ULL(60));
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
1124
if (npc_is_feature_supported(rvu, BIT_ULL(NPC_DMAC),
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
1482
return (((count) < 64) ? ~(BIT_ULL(count) - 1) : (0x00ULL));
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
1848
mcam->total_entries = (mcam->banks / BIT_ULL(cfg)) * mcam->banksize;
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
1980
if (npc_const1 & BIT_ULL(63))
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
1992
hw->npc_stat_ena = BIT_ULL(9);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
2007
hw->npc_stat_ena = BIT_ULL(63);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
2146
BIT_ULL(7) | BIT_ULL(6) | BIT_ULL(2) | BIT_ULL(1));
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
240
#define CAM_MASK(n) (BIT_ULL(n) - 1)
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
3271
rsp->stat &= BIT_ULL(48) - 1;
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
3576
rsp->stat &= BIT_ULL(48) - 1;
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
623
if (!npc_is_feature_supported(rvu, BIT_ULL(NPC_DMAC), pfvf->nix_rx_intf))
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
643
req.features = BIT_ULL(NPC_DMAC);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
794
if (!npc_is_feature_supported(rvu, BIT_ULL(NPC_DMAC), pfvf->nix_rx_intf) &&
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
795
!npc_is_feature_supported(rvu, BIT_ULL(NPC_LXMB), pfvf->nix_rx_intf))
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
814
req.features = BIT_ULL(NPC_DMAC);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
855
if (!npc_is_feature_supported(rvu, BIT_ULL(NPC_DMAC), pfvf->nix_rx_intf) &&
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
856
!npc_is_feature_supported(rvu, BIT_ULL(NPC_LXMB), pfvf->nix_rx_intf))
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
888
req.features = BIT_ULL(NPC_DMAC);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
1426
req->features & BIT_ULL(NPC_DMAC)) {
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
1442
req->features &= ~BIT_ULL(NPC_DMAC);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
1443
req->features |= BIT_ULL(NPC_LXMB);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
1462
(req->features & BIT_ULL(NPC_DMAC));
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
1488
if ((req->features & BIT_ULL(NPC_DMAC)) && is_npc_intf_rx(req->intf) &&
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
418
*features |= BIT_ULL(NPC_ETYPE);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
448
*features |= BIT_ULL(NPC_OUTER_VID);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
453
*features |= BIT_ULL(NPC_INNER_VID);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
572
*features |= BIT_ULL(hdr);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
575
proto_flags = BIT_ULL(NPC_SPORT_TCP) | BIT_ULL(NPC_SPORT_UDP) |
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
576
BIT_ULL(NPC_DPORT_TCP) | BIT_ULL(NPC_DPORT_UDP) |
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
577
BIT_ULL(NPC_SPORT_SCTP) | BIT_ULL(NPC_DPORT_SCTP) |
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
578
BIT_ULL(NPC_SPORT_SCTP) | BIT_ULL(NPC_DPORT_SCTP) |
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
579
BIT_ULL(NPC_TYPE_ICMP) | BIT_ULL(NPC_CODE_ICMP) |
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
580
BIT_ULL(NPC_TCP_FLAGS);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
587
*features |= BIT_ULL(NPC_IPPROTO_TCP) |
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
588
BIT_ULL(NPC_IPPROTO_UDP) |
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
589
BIT_ULL(NPC_IPPROTO_SCTP) |
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
590
BIT_ULL(NPC_IPPROTO_ICMP);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
595
*features |= BIT_ULL(NPC_IPPROTO_AH);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
596
*features |= BIT_ULL(NPC_IPPROTO_ICMP);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
597
*features |= BIT_ULL(NPC_IPPROTO_ICMP6);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
602
*features |= BIT_ULL(NPC_IPPROTO_ESP);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
605
if (*features & BIT_ULL(NPC_OUTER_VID))
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
607
*features &= ~BIT_ULL(NPC_OUTER_VID);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
611
(*features & (BIT_ULL(NPC_IPPROTO_ESP) | BIT_ULL(NPC_IPPROTO_AH))))
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
612
*features |= BIT_ULL(NPC_IPSEC_SPI);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
616
*features |= BIT_ULL(NPC_VLAN_ETYPE_CTAG) |
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
617
BIT_ULL(NPC_VLAN_ETYPE_STAG);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
621
*features |= BIT_ULL(NPC_LXMB);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
625
*features |= BIT_ULL(hdr);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
851
if (features & BIT_ULL(NPC_SIP_IPV6)) {
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
865
if (features & BIT_ULL(NPC_DIP_IPV6)) {
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
884
bool ctag = !!(features & BIT_ULL(NPC_VLAN_ETYPE_CTAG));
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
885
bool stag = !!(features & BIT_ULL(NPC_VLAN_ETYPE_STAG));
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
886
bool vid = !!(features & BIT_ULL(NPC_OUTER_VID));
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
920
if (features & BIT_ULL(NPC_IPPROTO_TCP))
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
923
if (features & BIT_ULL(NPC_IPPROTO_UDP))
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
926
if (features & BIT_ULL(NPC_IPPROTO_SCTP))
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
929
if (features & BIT_ULL(NPC_IPPROTO_ICMP))
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
932
if (features & BIT_ULL(NPC_IPPROTO_ICMP6))
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
937
if (features & BIT_ULL(NPC_IPPROTO_AH))
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
941
if (features & BIT_ULL(NPC_IPPROTO_ESP))
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
945
if (features & BIT_ULL(NPC_LXMB)) {
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
952
if (features & BIT_ULL((field))) { \
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.h
15
#define NPC_LDATA_EN BIT_ULL(7)
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c
1888
if (!(npc_const3 & BIT_ULL(62)))
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c
301
if ((cfg & BIT_ULL(11)) && (cfg & BIT_ULL(12))) {
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c
316
if ((features & BIT_ULL(NPC_SIP_IPV6)) && !hash_idx) {
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c
333
} else if ((features & BIT_ULL(NPC_DIP_IPV6)) && hash_idx) {
drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
272
#define NIX_PTP_1STEP_EN BIT_ULL(2)
drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c
247
vlan_tci = rep_id | BIT_ULL(8);
drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c
260
req.features = BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_VLAN_ETYPE_CTAG);
drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c
288
vlan_tci |= BIT_ULL(8);
drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h
850
#define VTAG_STRIP BIT_ULL(4)
drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h
851
#define VTAG_CAPTURE BIT_ULL(5)
drivers/net/ethernet/marvell/octeontx2/af/rvu_switch.c
41
req.features = BIT_ULL(NPC_DMAC);
drivers/net/ethernet/marvell/octeontx2/af/rvu_switch.c
74
req.features = BIT_ULL(NPC_DMAC);
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
147
reg_val |= BIT_ULL(16);
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
152
reg_val |= BIT_ULL(0);
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
186
reg_val &= ~BIT_ULL(16);
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
193
if (reg_val & BIT_ULL(31))
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_macsec.c
17
#define MCS_SA_MAP_MEM_SA_USE BIT_ULL(9)
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_macsec.c
20
#define MCS_RX_SECY_PLCY_RP BIT_ULL(17)
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_macsec.c
21
#define MCS_RX_SECY_PLCY_AUTH_ENA BIT_ULL(16)
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_macsec.c
24
#define MCS_RX_SECY_PLCY_ENA BIT_ULL(0)
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_macsec.c
29
#define MCS_TX_SECY_PLCY_INS_MODE BIT_ULL(14)
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_macsec.c
30
#define MCS_TX_SECY_PLCY_AUTH_ENA BIT_ULL(13)
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_macsec.c
32
#define MCS_TX_SECY_PLCY_PROTECT BIT_ULL(1)
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_macsec.c
33
#define MCS_TX_SECY_PLCY_ENA BIT_ULL(0)
drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c
28
if (pf_trig_val & BIT_ULL(0)) {
drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c
38
BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c
41
if (pf_trig_val & BIT_ULL(1)) {
drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c
50
BIT_ULL(1));
drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c
71
if (vf_trig_val & BIT_ULL(1)) {
drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c
82
BIT_ULL(1));
drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c
85
if (vf_trig_val & BIT_ULL(0)) {
drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c
96
BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
1247
nixlf->rx_cfg = BIT_ULL(33) | BIT_ULL(35) | BIT_ULL(37);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
674
req->regval[2] = BIT_ULL(12) | BIT_ULL(13) |
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
691
req->regval[2] = BIT_ULL(13) | BIT_ULL(12) | prio;
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
709
req->regval[2] = BIT_ULL(13) | BIT_ULL(12) | prio;
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
751
req->regval[0] |= BIT_ULL(49);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
469
#define OTX2_FLAG_RX_TSTAMP_ENABLED BIT_ULL(0)
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
470
#define OTX2_FLAG_TX_TSTAMP_ENABLED BIT_ULL(1)
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
471
#define OTX2_FLAG_INTF_DOWN BIT_ULL(2)
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
472
#define OTX2_FLAG_MCAM_ENTRIES_ALLOC BIT_ULL(3)
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
473
#define OTX2_FLAG_NTUPLE_SUPPORT BIT_ULL(4)
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
474
#define OTX2_FLAG_UCAST_FLTR_SUPPORT BIT_ULL(5)
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
475
#define OTX2_FLAG_RX_VLAN_SUPPORT BIT_ULL(6)
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
476
#define OTX2_FLAG_VF_VLAN_SUPPORT BIT_ULL(7)
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
477
#define OTX2_FLAG_PF_SHUTDOWN BIT_ULL(8)
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
478
#define OTX2_FLAG_RX_PAUSE_ENABLED BIT_ULL(9)
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
479
#define OTX2_FLAG_TX_PAUSE_ENABLED BIT_ULL(10)
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
480
#define OTX2_FLAG_TC_FLOWER_SUPPORT BIT_ULL(11)
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
481
#define OTX2_FLAG_TC_MATCHALL_EGRESS_ENABLED BIT_ULL(12)
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
482
#define OTX2_FLAG_TC_MATCHALL_INGRESS_ENABLED BIT_ULL(13)
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
483
#define OTX2_FLAG_DMACFLTR_SUPPORT BIT_ULL(14)
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
484
#define OTX2_FLAG_PTP_ONESTEP_SYNC BIT_ULL(15)
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
485
#define OTX2_FLAG_ADPTV_INT_COAL_ENABLED BIT_ULL(16)
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
486
#define OTX2_FLAG_TC_MARK_ENABLED BIT_ULL(17)
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
487
#define OTX2_FLAG_REP_MODE_ENABLED BIT_ULL(18)
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
488
#define OTX2_FLAG_PORT_UP BIT_ULL(19)
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
489
#define OTX2_FLAG_IPSEC_OFFLOAD_ENABLED BIT_ULL(20)
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
791
val = (lmt_info->lmt_id & 0x7FF) | BIT_ULL(63);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
836
u64 incr = (u64)aura | BIT_ULL(63);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
847
otx2_write128(buf, (u64)aura | BIT_ULL(63), addr);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
1024
if (!vf && (req->features & BIT_ULL(NPC_OUTER_VID)) &&
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
1429
req->features = BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_DMAC);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
390
req->features = BIT_ULL(NPC_DMAC);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
556
req->features |= BIT_ULL(NPC_SIP_IPV4);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
563
req->features |= BIT_ULL(NPC_DIP_IPV4);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
568
req->features |= BIT_ULL(NPC_TOS);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
573
req->features |= BIT_ULL(NPC_IPPROTO_ICMP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
576
req->features |= BIT_ULL(NPC_IPPROTO_TCP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
579
req->features |= BIT_ULL(NPC_IPPROTO_UDP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
582
req->features |= BIT_ULL(NPC_IPPROTO_SCTP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
585
req->features |= BIT_ULL(NPC_IPPROTO_AH);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
588
req->features |= BIT_ULL(NPC_IPPROTO_ESP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
596
req->features |= BIT_ULL(NPC_ETYPE);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
603
req->features |= BIT_ULL(NPC_ETYPE);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
609
req->features |= BIT_ULL(NPC_SIP_IPV4);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
616
req->features |= BIT_ULL(NPC_DIP_IPV4);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
621
req->features |= BIT_ULL(NPC_TOS);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
629
req->features |= BIT_ULL(NPC_SPORT_UDP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
631
req->features |= BIT_ULL(NPC_SPORT_TCP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
633
req->features |= BIT_ULL(NPC_SPORT_SCTP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
641
req->features |= BIT_ULL(NPC_DPORT_UDP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
643
req->features |= BIT_ULL(NPC_DPORT_TCP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
645
req->features |= BIT_ULL(NPC_DPORT_SCTP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
648
req->features |= BIT_ULL(NPC_IPPROTO_UDP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
650
req->features |= BIT_ULL(NPC_IPPROTO_TCP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
652
req->features |= BIT_ULL(NPC_IPPROTO_SCTP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
658
req->features |= BIT_ULL(NPC_ETYPE);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
664
req->features |= BIT_ULL(NPC_SIP_IPV4);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
671
req->features |= BIT_ULL(NPC_DIP_IPV4);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
676
req->features |= BIT_ULL(NPC_TOS);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
684
req->features |= BIT_ULL(NPC_IPPROTO_AH);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
686
req->features |= BIT_ULL(NPC_IPPROTO_ESP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
715
req->features |= BIT_ULL(NPC_SIP_IPV6);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
722
req->features |= BIT_ULL(NPC_DIP_IPV6);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
727
req->features |= BIT_ULL(NPC_IPFRAG_IPV6);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
731
req->features |= BIT_ULL(NPC_ETYPE);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
738
req->features |= BIT_ULL(NPC_ETYPE);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
744
req->features |= BIT_ULL(NPC_SIP_IPV6);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
751
req->features |= BIT_ULL(NPC_DIP_IPV6);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
759
req->features |= BIT_ULL(NPC_SPORT_UDP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
761
req->features |= BIT_ULL(NPC_SPORT_TCP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
763
req->features |= BIT_ULL(NPC_SPORT_SCTP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
771
req->features |= BIT_ULL(NPC_DPORT_UDP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
773
req->features |= BIT_ULL(NPC_DPORT_TCP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
775
req->features |= BIT_ULL(NPC_DPORT_SCTP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
778
req->features |= BIT_ULL(NPC_IPPROTO_UDP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
780
req->features |= BIT_ULL(NPC_IPPROTO_TCP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
782
req->features |= BIT_ULL(NPC_IPPROTO_SCTP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
788
req->features |= BIT_ULL(NPC_ETYPE);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
794
req->features |= BIT_ULL(NPC_SIP_IPV6);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
801
req->features |= BIT_ULL(NPC_DIP_IPV6);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
810
req->features |= BIT_ULL(NPC_IPPROTO_AH);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
812
req->features |= BIT_ULL(NPC_IPPROTO_ESP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
838
req->features |= BIT_ULL(NPC_SMAC);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
843
req->features |= BIT_ULL(NPC_DMAC);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
850
req->features |= BIT_ULL(NPC_ETYPE);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
904
req->features |= BIT_ULL(NPC_VLAN_ETYPE_CTAG);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
906
req->features |= BIT_ULL(NPC_VLAN_ETYPE_STAG);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
914
req->features |= BIT_ULL(NPC_OUTER_VID);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
924
req->features |= BIT_ULL(NPC_IPFRAG_IPV4);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c
939
req->features |= BIT_ULL(NPC_DMAC);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
1054
otx2_write64(pf, RVU_PF_INT, BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
1072
BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
1091
BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
1107
otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
1112
BIT_ULL(0) | BIT_ULL(1));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
1154
otx2_write64(pf, RVU_PF_INT, BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
1155
otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
1157
otx2_write64(pf, RVU_PF_INT, BIT_ULL(0) | BIT_ULL(1));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
1158
otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0) |
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
1159
BIT_ULL(1));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
140
otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
1407
if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42))))
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
141
otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
1410
if (val & BIT_ULL(42)) {
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
1415
if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR))
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
1418
if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT))
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
1446
if (val & BIT_ULL(42)) {
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
1464
otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG, BIT_ULL(44));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
1483
otx2_write64(pf, NIX_LF_MNQ_ERR_DBG, BIT_ULL(44));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
1494
otx2_write64(pf, NIX_LF_SEND_ERR_DBG, BIT_ULL(44));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
1499
if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL))
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
1520
otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
162
if (!(intr & BIT_ULL(vf)))
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
167
otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
170
BIT_ULL(vf));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
190
if (!(intr & BIT_ULL(vf)))
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
193
otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
195
otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
2049
otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
2081
otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
2082
otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
2143
otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
2181
otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
2188
otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
2535
req->features = BIT_ULL(NPC_DMAC);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
2652
req->features = BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_DMAC);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
2699
req->features = BIT_ULL(NPC_DMAC);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
309
if (!(intr & BIT_ULL(i - first)))
drivers/net/ethernet/marvell/octeontx2/nic/otx2_reg.h
158
#define LMT_LFBASE BIT_ULL(RVU_FUNC_BLKADDR_SHIFT)
drivers/net/ethernet/marvell/octeontx2/nic/otx2_struct.h
262
#define NIX_CQERRINT_BITS (BIT_ULL(NIX_CQERRINT_DOOR_ERR) | \
drivers/net/ethernet/marvell/octeontx2/nic/otx2_struct.h
263
BIT_ULL(NIX_CQERRINT_CQE_FAULT))
drivers/net/ethernet/marvell/octeontx2/nic/otx2_struct.h
270
#define NIX_RQINT_BITS (BIT_ULL(NIX_RQINT_DROP) | BIT_ULL(NIX_RQINT_RED))
drivers/net/ethernet/marvell/octeontx2/nic/otx2_struct.h
279
#define NIX_SQINT_BITS (BIT_ULL(NIX_SQINT_LMT_ERR) | \
drivers/net/ethernet/marvell/octeontx2/nic/otx2_struct.h
280
BIT_ULL(NIX_SQINT_MNQ_ERR) | \
drivers/net/ethernet/marvell/octeontx2/nic/otx2_struct.h
281
BIT_ULL(NIX_SQINT_SEND_ERR) | \
drivers/net/ethernet/marvell/octeontx2/nic/otx2_struct.h
282
BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL))
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
138
FIELD_PREP(TLX_RATE_MANTISSA, mantissa) | BIT_ULL(0);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
144
FIELD_PREP(TLX_RATE_MANTISSA, mantissa) | BIT_ULL(0);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
618
req->features |= BIT_ULL(NPC_INNER_VID);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
622
req->features |= BIT_ULL(NPC_OUTER_VID);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
644
~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
645
BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
646
BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
647
BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) |
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
649
BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
650
BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
651
BIT_ULL(FLOW_DISSECTOR_KEY_PORTS) |
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
653
BIT_ULL(FLOW_DISSECTOR_KEY_MPLS) |
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
654
BIT_ULL(FLOW_DISSECTOR_KEY_ICMP) |
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
655
BIT_ULL(FLOW_DISSECTOR_KEY_TCP) |
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
656
BIT_ULL(FLOW_DISSECTOR_KEY_IP)))) {
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
670
req->features |= BIT_ULL(NPC_ETYPE);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
689
req->features |= BIT_ULL(NPC_IPPROTO_UDP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
691
req->features |= BIT_ULL(NPC_IPPROTO_TCP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
693
req->features |= BIT_ULL(NPC_IPPROTO_SCTP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
695
req->features |= BIT_ULL(NPC_IPPROTO_ICMP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
697
req->features |= BIT_ULL(NPC_IPPROTO_ICMP6);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
699
req->features |= BIT_ULL(NPC_IPPROTO_ESP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
701
req->features |= BIT_ULL(NPC_IPPROTO_AH);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
715
req->features |= BIT_ULL(NPC_IPFRAG_IPV4);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
720
req->features |= BIT_ULL(NPC_IPFRAG_IPV6);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
745
req->features |= BIT_ULL(NPC_DMAC);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
766
req->features |= BIT_ULL(NPC_IPSEC_SPI);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
784
req->features |= BIT_ULL(NPC_TOS);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
810
req->features |= BIT_ULL(NPC_DIP_IPV4);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
814
req->features |= BIT_ULL(NPC_SIP_IPV4);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
834
req->features |= BIT_ULL(NPC_DIP_IPV6);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
844
req->features |= BIT_ULL(NPC_SIP_IPV6);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
858
req->features |= BIT_ULL(NPC_DPORT_UDP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
860
req->features |= BIT_ULL(NPC_DPORT_TCP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
862
req->features |= BIT_ULL(NPC_DPORT_SCTP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
870
req->features |= BIT_ULL(NPC_SPORT_UDP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
872
req->features |= BIT_ULL(NPC_SPORT_TCP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
874
req->features |= BIT_ULL(NPC_SPORT_SCTP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
885
req->features |= BIT_ULL(NPC_TCP_FLAGS);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
911
req->features |= BIT_ULL(NPC_MPLS1_LBTCBOS +
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
931
req->features |= BIT_ULL(NPC_MPLS1_TTL +
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
950
req->features |= BIT_ULL(NPC_TYPE_ICMP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c
954
req->features |= BIT_ULL(NPC_CODE_ICMP);
drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c
598
otx2_write64(pfvf, NIX_LF_CINTX_INT(cq_poll->cint_idx), BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c
637
BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c
65
if (unlikely(status & BIT_ULL(CQ_OP_STAT_OP_ERR) ||
drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c
66
status & BIT_ULL(CQ_OP_STAT_CQ_ERR))) {
drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c
193
otx2_write64(vf, RVU_VF_INT, BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c
214
BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c
231
BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c
242
otx2_write64(vf, RVU_VF_INT_ENA_W1C, BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c
245
otx2_write64(vf, RVU_VF_INT_ENA_W1C, BIT_ULL(0) | BIT_ULL(1));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c
281
otx2_write64(vf, RVU_VF_INT, BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c
282
otx2_write64(vf, RVU_VF_INT_ENA_W1S, BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c
284
otx2_write64(vf, RVU_VF_INT, BIT_ULL(0) | BIT_ULL(1) |
drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c
285
BIT_ULL(2) | BIT_ULL(3));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c
286
otx2_write64(vf, RVU_VF_INT_ENA_W1S, BIT_ULL(0) |
drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c
287
BIT_ULL(1) | BIT_ULL(2) | BIT_ULL(3));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_xsk.c
187
otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(cq_poll->cint_idx), BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_xsk.c
188
otx2_write64(pf, NIX_LF_CINTX_INT_W1S(cq_poll->cint_idx), BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/qos.c
162
cfg->regval[num_regs] = BIT_ULL(13) | BIT_ULL(12);
drivers/net/ethernet/marvell/octeontx2/nic/qos.c
176
cfg->regval[num_regs] = BIT_ULL(13) | BIT_ULL(12);
drivers/net/ethernet/marvell/octeontx2/nic/rep.c
547
otx2_write64(priv, NIX_LF_CINTX_INT(qidx), BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/rep.c
548
otx2_write64(priv, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/rep.c
569
otx2_write64(priv, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0));
drivers/net/ethernet/marvell/octeontx2/nic/rep.h
40
#define RVU_REP_VF_INITIALIZED BIT_ULL(0)
drivers/net/ethernet/marvell/prestera/prestera_flower.c
205
~(BIT_ULL(FLOW_DISSECTOR_KEY_META) |
drivers/net/ethernet/marvell/prestera/prestera_flower.c
206
BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
drivers/net/ethernet/marvell/prestera/prestera_flower.c
207
BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
drivers/net/ethernet/marvell/prestera/prestera_flower.c
208
BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
drivers/net/ethernet/marvell/prestera/prestera_flower.c
209
BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
drivers/net/ethernet/marvell/prestera/prestera_flower.c
210
BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
drivers/net/ethernet/marvell/prestera/prestera_flower.c
211
BIT_ULL(FLOW_DISSECTOR_KEY_ICMP) |
drivers/net/ethernet/marvell/prestera/prestera_flower.c
212
BIT_ULL(FLOW_DISSECTOR_KEY_PORTS) |
drivers/net/ethernet/marvell/prestera/prestera_flower.c
213
BIT_ULL(FLOW_DISSECTOR_KEY_PORTS_RANGE) |
drivers/net/ethernet/marvell/prestera/prestera_flower.c
214
BIT_ULL(FLOW_DISSECTOR_KEY_VLAN))) {
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1018
#define MTK_RGMII BIT_ULL(MTK_RGMII_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1019
#define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1020
#define MTK_SGMII BIT_ULL(MTK_SGMII_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1021
#define MTK_2P5GPHY BIT_ULL(MTK_2P5GPHY_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1022
#define MTK_ESW BIT_ULL(MTK_ESW_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1023
#define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1024
#define MTK_MUX BIT_ULL(MTK_MUX_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1025
#define MTK_INFRA BIT_ULL(MTK_INFRA_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1026
#define MTK_SHARED_SGMII BIT_ULL(MTK_SHARED_SGMII_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1027
#define MTK_HWLRO BIT_ULL(MTK_HWLRO_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1028
#define MTK_SHARED_INT BIT_ULL(MTK_SHARED_INT_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1029
#define MTK_TRGMII_MT7621_CLK BIT_ULL(MTK_TRGMII_MT7621_CLK_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1030
#define MTK_QDMA BIT_ULL(MTK_QDMA_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1031
#define MTK_SOC_MT7628 BIT_ULL(MTK_SOC_MT7628_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1032
#define MTK_RSTCTRL_PPE1 BIT_ULL(MTK_RSTCTRL_PPE1_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1033
#define MTK_RSTCTRL_PPE2 BIT_ULL(MTK_RSTCTRL_PPE2_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1034
#define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1035
#define MTK_SRAM BIT_ULL(MTK_SRAM_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1036
#define MTK_36BIT_DMA BIT_ULL(MTK_36BIT_DMA_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1039
BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1041
BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1043
BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1045
BIT_ULL(MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1047
BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1049
BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1052
#define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1053
#define MTK_ETH_PATH_GMAC1_TRGMII BIT_ULL(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1054
#define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1055
#define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1056
#define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1057
#define MTK_ETH_PATH_GMAC2_2P5GPHY BIT_ULL(MTK_ETH_PATH_GMAC2_2P5GPHY_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1058
#define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
1059
#define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT)
drivers/net/ethernet/mediatek/mtk_eth_soc.h
790
#define MT7623_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
791
BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
792
BIT_ULL(MTK_CLK_TRGPLL))
drivers/net/ethernet/mediatek/mtk_eth_soc.h
793
#define MT7622_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
794
BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
795
BIT_ULL(MTK_CLK_GP2) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
796
BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
797
BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
798
BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
799
BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
800
BIT_ULL(MTK_CLK_SGMII_CK) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
801
BIT_ULL(MTK_CLK_ETH2PLL))
drivers/net/ethernet/mediatek/mtk_eth_soc.h
804
#define MT7629_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
805
BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
806
BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
807
BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
808
BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
809
BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
810
BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
811
BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
812
BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
813
BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
814
BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
815
BIT_ULL(MTK_CLK_SGMII_CK) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
816
BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP))
drivers/net/ethernet/mediatek/mtk_eth_soc.h
817
#define MT7981_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
818
BIT_ULL(MTK_CLK_GP1) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
819
BIT_ULL(MTK_CLK_WOCPU0) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
820
BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
821
BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
822
BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
823
BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
824
BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
825
BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
826
BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
827
BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
828
BIT_ULL(MTK_CLK_SGMII_CK))
drivers/net/ethernet/mediatek/mtk_eth_soc.h
829
#define MT7986_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
830
BIT_ULL(MTK_CLK_GP1) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
831
BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
832
BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
833
BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
834
BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
835
BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
836
BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
837
BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
838
BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
839
BIT_ULL(MTK_CLK_SGMII2_CDR_FB))
drivers/net/ethernet/mediatek/mtk_eth_soc.h
840
#define MT7988_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
841
BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
842
BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
843
BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
844
BIT_ULL(MTK_CLK_CRYPTO) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
845
BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
846
BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
847
BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
848
BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
849
BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
850
BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
851
BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
852
BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
853
BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
854
BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
855
BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
856
BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
857
BIT_ULL(MTK_CLK_TOP_NETSYS_SYNC_250M_SEL) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
858
BIT_ULL(MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL) | \
drivers/net/ethernet/mediatek/mtk_eth_soc.h
859
BIT_ULL(MTK_CLK_TOP_NETSYS_WARP_SEL))
drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c
2471
#define DISS_BIT(name) BIT_ULL(FLOW_DISSECTOR_KEY_ ## name)
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c
187
n = attrs->lft.hard_packet_limit / BIT_ULL(31);
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c
188
start_value = attrs->lft.hard_packet_limit - n * BIT_ULL(31);
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c
195
start_value = attrs->lft.hard_packet_limit - n * BIT_ULL(31);
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c
225
n = (x->lft.soft_packet_limit - attrs->lft.hard_packet_limit) / BIT_ULL(31);
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c
226
start_value = attrs->lft.hard_packet_limit + n * BIT_ULL(31) -
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c
232
else if (start_value >= BIT_ULL(32))
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c
238
start_value = attrs->lft.hard_packet_limit + n * BIT_ULL(31) - start_value;
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c
239
if (n != attrs->lft.numb_rounds_hard && start_value < BIT_ULL(30))
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c
247
start_value = attrs->lft.hard_packet_limit + n * BIT_ULL(31) - start_value;
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c
331
data.bitwise_data = cpu_to_be64(BIT_ULL(54));
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c
343
data.bitwise_data = cpu_to_be64(BIT_ULL(57) + BIT_ULL(31));
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c
400
if (attrs->lft.soft_packet_limit > BIT_ULL(31)) {
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c
413
BIT_ULL(31) - BIT_ULL(30));
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c
435
mlx5e_ipsec_aso_update_soft(sa_entry, BIT_ULL(31) - 1);
drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c
1366
param.bitwise_data = BIT_ULL(54);
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
2729
~(BIT_ULL(FLOW_DISSECTOR_KEY_META) |
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
2730
BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
2731
BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
2732
BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
2733
BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) |
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
2734
BIT_ULL(FLOW_DISSECTOR_KEY_CVLAN) |
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
2735
BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
2736
BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
2737
BIT_ULL(FLOW_DISSECTOR_KEY_PORTS) |
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
2738
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_KEYID) |
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
2739
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
2740
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
2741
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_PORTS) |
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
2742
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
2743
BIT_ULL(FLOW_DISSECTOR_KEY_TCP) |
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
2744
BIT_ULL(FLOW_DISSECTOR_KEY_IP) |
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
2745
BIT_ULL(FLOW_DISSECTOR_KEY_CT) |
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
2746
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IP) |
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
2747
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_OPTS) |
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
2748
BIT_ULL(FLOW_DISSECTOR_KEY_ICMP) |
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
2749
BIT_ULL(FLOW_DISSECTOR_KEY_MPLS))) {
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c
18
#define MLX5_FLOW_ITEM_FLEX_TUNNEL BIT_ULL(39)
drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c
581
~(BIT_ULL(FLOW_DISSECTOR_KEY_META) |
drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c
582
BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c
583
BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c
584
BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c
585
BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c
586
BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c
587
BIT_ULL(FLOW_DISSECTOR_KEY_PORTS) |
drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c
588
BIT_ULL(FLOW_DISSECTOR_KEY_PORTS_RANGE) |
drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c
589
BIT_ULL(FLOW_DISSECTOR_KEY_TCP) |
drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c
590
BIT_ULL(FLOW_DISSECTOR_KEY_IP) |
drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c
591
BIT_ULL(FLOW_DISSECTOR_KEY_VLAN))) {
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
1745
if (burst != (BIT_ULL(bs))) {
drivers/net/ethernet/meta/fbnic/fbnic_csr.h
12
#define DESC_BIT(nr) BIT_ULL(nr)
drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c
636
lan966x_ifh_set_port(ifh, BIT_ULL(port->chip_port));
drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c
655
lan966x_ifh_set_port(ifh, BIT_ULL(port->chip_port));
drivers/net/ethernet/microchip/lan966x/lan966x_main.c
377
lan966x_ifh_set_port(ifh, BIT_ULL(port->chip_port));
drivers/net/ethernet/microchip/lan966x/lan966x_tc_flower.c
181
st->used_keys |= BIT_ULL(FLOW_DISSECTOR_KEY_BASIC);
drivers/net/ethernet/microchip/lan966x/lan966x_tc_flower.c
84
st->used_keys |= BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL);
drivers/net/ethernet/microchip/sparx5/sparx5_mirror.c
67
return (sparx5_mirror_port_get(sparx5, idx) & BIT_ULL(portno)) != 0;
drivers/net/ethernet/microchip/sparx5/sparx5_tc_flower.c
150
st->used_keys |= BIT_ULL(FLOW_DISSECTOR_KEY_BASIC);
drivers/net/ethernet/microchip/sparx5/sparx5_tc_flower.c
205
st->used_keys |= BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL);
drivers/net/ethernet/microchip/vcap/vcap_tc.c
127
st->used_keys |= BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS);
drivers/net/ethernet/microchip/vcap/vcap_tc.c
161
st->used_keys |= BIT_ULL(FLOW_DISSECTOR_KEY_PORTS);
drivers/net/ethernet/microchip/vcap/vcap_tc.c
204
st->used_keys |= BIT_ULL(FLOW_DISSECTOR_KEY_CVLAN);
drivers/net/ethernet/microchip/vcap/vcap_tc.c
241
st->used_keys |= BIT_ULL(FLOW_DISSECTOR_KEY_VLAN);
drivers/net/ethernet/microchip/vcap/vcap_tc.c
316
st->used_keys |= BIT_ULL(FLOW_DISSECTOR_KEY_TCP);
drivers/net/ethernet/microchip/vcap/vcap_tc.c
379
st->used_keys |= BIT_ULL(FLOW_DISSECTOR_KEY_ARP);
drivers/net/ethernet/microchip/vcap/vcap_tc.c
404
st->used_keys |= BIT_ULL(FLOW_DISSECTOR_KEY_IP);
drivers/net/ethernet/microchip/vcap/vcap_tc.c
53
st->used_keys |= BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS);
drivers/net/ethernet/microchip/vcap/vcap_tc.c
89
st->used_keys |= BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS);
drivers/net/ethernet/mscc/ocelot.c
1442
ocelot_ifh_set_dest(ifh, BIT_ULL(port));
drivers/net/ethernet/mscc/ocelot_flower.c
614
~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
drivers/net/ethernet/mscc/ocelot_flower.c
615
BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
drivers/net/ethernet/mscc/ocelot_flower.c
616
BIT_ULL(FLOW_DISSECTOR_KEY_META) |
drivers/net/ethernet/mscc/ocelot_flower.c
617
BIT_ULL(FLOW_DISSECTOR_KEY_PORTS) |
drivers/net/ethernet/mscc/ocelot_flower.c
618
BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) |
drivers/net/ethernet/mscc/ocelot_flower.c
619
BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
drivers/net/ethernet/mscc/ocelot_flower.c
620
BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
drivers/net/ethernet/mscc/ocelot_flower.c
621
BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS))) {
drivers/net/ethernet/mscc/ocelot_flower.c
671
(BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
drivers/net/ethernet/mscc/ocelot_flower.c
672
BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
drivers/net/ethernet/mscc/ocelot_flower.c
673
BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL))) !=
drivers/net/ethernet/mscc/ocelot_flower.c
674
(BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
drivers/net/ethernet/mscc/ocelot_flower.c
675
BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
drivers/net/ethernet/mscc/ocelot_flower.c
676
BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL)))
drivers/net/ethernet/netronome/nfp/flower/conntrack.c
261
if (ovlp_keys & BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL)) {
drivers/net/ethernet/netronome/nfp/flower/conntrack.c
271
if (ovlp_keys & BIT_ULL(FLOW_DISSECTOR_KEY_BASIC)) {
drivers/net/ethernet/netronome/nfp/flower/conntrack.c
293
if ((ovlp_keys & BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS)) &&
drivers/net/ethernet/netronome/nfp/flower/conntrack.c
315
if ((ovlp_keys & BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS)) &&
drivers/net/ethernet/netronome/nfp/flower/conntrack.c
337
if ((ovlp_keys & BIT_ULL(FLOW_DISSECTOR_KEY_PORTS)) &&
drivers/net/ethernet/netronome/nfp/flower/conntrack.c
359
if (ovlp_keys & BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
drivers/net/ethernet/netronome/nfp/flower/conntrack.c
375
if (ovlp_keys & BIT_ULL(FLOW_DISSECTOR_KEY_VLAN)) {
drivers/net/ethernet/netronome/nfp/flower/conntrack.c
385
if (ovlp_keys & BIT_ULL(FLOW_DISSECTOR_KEY_MPLS)) {
drivers/net/ethernet/netronome/nfp/flower/conntrack.c
395
if (ovlp_keys & BIT_ULL(FLOW_DISSECTOR_KEY_TCP)) {
drivers/net/ethernet/netronome/nfp/flower/conntrack.c
405
if (ovlp_keys & BIT_ULL(FLOW_DISSECTOR_KEY_IP)) {
drivers/net/ethernet/netronome/nfp/flower/conntrack.c
417
if (ovlp_keys & BIT_ULL(FLOW_DISSECTOR_KEY_ENC_KEYID)) {
drivers/net/ethernet/netronome/nfp/flower/conntrack.c
427
if (ovlp_keys & BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS)) {
drivers/net/ethernet/netronome/nfp/flower/conntrack.c
437
if (ovlp_keys & BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS)) {
drivers/net/ethernet/netronome/nfp/flower/conntrack.c
447
if (ovlp_keys & BIT_ULL(FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
drivers/net/ethernet/netronome/nfp/flower/conntrack.c
457
if (ovlp_keys & BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IP)) {
drivers/net/ethernet/netronome/nfp/flower/conntrack.c
467
if (ovlp_keys & BIT_ULL(FLOW_DISSECTOR_KEY_ENC_OPTS)) {
drivers/net/ethernet/netronome/nfp/flower/conntrack.c
593
if (ct_met && (dissector->used_keys & BIT_ULL(FLOW_DISSECTOR_KEY_CT))) {
drivers/net/ethernet/netronome/nfp/flower/conntrack.c
64
if (dissector->used_keys & BIT_ULL(FLOW_DISSECTOR_KEY_CT)) {
drivers/net/ethernet/netronome/nfp/flower/conntrack.c
97
if (dissector->used_keys & BIT_ULL(FLOW_DISSECTOR_KEY_CT)) {
drivers/net/ethernet/netronome/nfp/flower/offload.c
1308
if (dissector->used_keys & BIT_ULL(FLOW_DISSECTOR_KEY_CT)) {
drivers/net/ethernet/netronome/nfp/flower/offload.c
27
(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
28
BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
29
BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
30
BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
31
BIT_ULL(FLOW_DISSECTOR_KEY_TCP) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
32
BIT_ULL(FLOW_DISSECTOR_KEY_PORTS) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
33
BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
34
BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
35
BIT_ULL(FLOW_DISSECTOR_KEY_CVLAN) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
36
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_KEYID) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
37
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
38
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
39
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_CONTROL) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
40
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_PORTS) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
41
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_OPTS) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
42
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IP) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
43
BIT_ULL(FLOW_DISSECTOR_KEY_MPLS) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
44
BIT_ULL(FLOW_DISSECTOR_KEY_CT) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
45
BIT_ULL(FLOW_DISSECTOR_KEY_META) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
46
BIT_ULL(FLOW_DISSECTOR_KEY_IP))
drivers/net/ethernet/netronome/nfp/flower/offload.c
49
(BIT_ULL(FLOW_DISSECTOR_KEY_ENC_CONTROL) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
50
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_KEYID) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
51
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
52
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
53
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_OPTS) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
54
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_PORTS) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
55
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IP))
drivers/net/ethernet/netronome/nfp/flower/offload.c
58
(BIT_ULL(FLOW_DISSECTOR_KEY_ENC_CONTROL) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
59
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS))
drivers/net/ethernet/netronome/nfp/flower/offload.c
62
(BIT_ULL(FLOW_DISSECTOR_KEY_ENC_CONTROL) | \
drivers/net/ethernet/netronome/nfp/flower/offload.c
63
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS))
drivers/net/ethernet/netronome/nfp/nfp_net_ctrl.h
18
#define NFP_NET_APP_CAP_SP_INDIFF BIT_ULL(0) /* indifferent to port speed */
drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c
443
if (eth_port->link_modes_supp[0] & BIT_ULL(i)) {
drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c
450
if (eth_port->link_modes_ad[0] & BIT_ULL(i))
drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c
454
if (eth_port->link_modes_supp[1] & BIT_ULL(i - 64)) {
drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c
461
if (eth_port->link_modes_ad[1] & BIT_ULL(i - 64))
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c
36
#define NSP_STATUS_BUSY BIT_ULL(0)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c
41
#define NSP_COMMAND_DMA_BUF BIT_ULL(1)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c
42
#define NSP_COMMAND_START BIT_ULL(0)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c
513
chunk_size = BIT_ULL(chunk_order);
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c
514
dma_size = BIT_ULL(dma_order);
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c
640
sg_ok = reg & BIT_ULL(arg->arg.code - 1);
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c
28
#define NSP_ETH_PORT_FEC_SUPP_BASER BIT_ULL(60)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c
29
#define NSP_ETH_PORT_FEC_SUPP_RS BIT_ULL(61)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c
30
#define NSP_ETH_PORT_SUPP_ANEG BIT_ULL(63)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c
34
#define NSP_ETH_STATE_CONFIGURED BIT_ULL(0)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c
35
#define NSP_ETH_STATE_ENABLED BIT_ULL(1)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c
36
#define NSP_ETH_STATE_TX_ENABLED BIT_ULL(2)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c
37
#define NSP_ETH_STATE_RX_ENABLED BIT_ULL(3)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c
41
#define NSP_ETH_STATE_OVRD_CHNG BIT_ULL(22)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c
45
#define NSP_ETH_STATE_TX_PAUSE BIT_ULL(31)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c
46
#define NSP_ETH_STATE_RX_PAUSE BIT_ULL(32)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c
48
#define NSP_ETH_CTRL_CONFIGURED BIT_ULL(0)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c
49
#define NSP_ETH_CTRL_ENABLED BIT_ULL(1)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c
50
#define NSP_ETH_CTRL_TX_ENABLED BIT_ULL(2)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c
51
#define NSP_ETH_CTRL_RX_ENABLED BIT_ULL(3)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c
52
#define NSP_ETH_CTRL_SET_RATE BIT_ULL(4)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c
53
#define NSP_ETH_CTRL_SET_LANES BIT_ULL(5)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c
54
#define NSP_ETH_CTRL_SET_ANEG BIT_ULL(6)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c
55
#define NSP_ETH_CTRL_SET_FEC BIT_ULL(7)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c
56
#define NSP_ETH_CTRL_SET_IDMODE BIT_ULL(8)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c
57
#define NSP_ETH_CTRL_SET_TX_PAUSE BIT_ULL(10)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c
58
#define NSP_ETH_CTRL_SET_RX_PAUSE BIT_ULL(11)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c
375
if (addr & BIT_ULL(idx_lsb))
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c
398
if (addr & BIT_ULL(idx_lsb))
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c
420
if (addr & BIT_ULL(idx_lsb))
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c
513
*addr &= ~BIT_ULL(idx_lsb);
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c
519
*addr |= BIT_ULL(idx_lsb);
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c
605
*addr &= ~BIT_ULL(idx_lsb);
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c
610
*addr |= BIT_ULL(idx_lsb);
drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
1028
mask = cpu_to_le64(BIT_ULL(IONIC_TXSTAMP_ONESTEP_SYNC));
drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
1032
mask = cpu_to_le64(BIT_ULL(IONIC_TXSTAMP_ONESTEP_P2P));
drivers/net/ethernet/pensando/ionic/ionic_if.h
406
IONIC_QIDENT_F_CQ = BIT_ULL(0),
drivers/net/ethernet/pensando/ionic/ionic_if.h
407
IONIC_QIDENT_F_SG = BIT_ULL(1),
drivers/net/ethernet/pensando/ionic/ionic_if.h
408
IONIC_QIDENT_F_EQ = BIT_ULL(2),
drivers/net/ethernet/pensando/ionic/ionic_if.h
409
IONIC_QIDENT_F_CMB = BIT_ULL(3),
drivers/net/ethernet/pensando/ionic/ionic_if.h
410
IONIC_Q_F_2X_DESC = BIT_ULL(4),
drivers/net/ethernet/pensando/ionic/ionic_if.h
411
IONIC_Q_F_2X_CQ_DESC = BIT_ULL(5),
drivers/net/ethernet/pensando/ionic/ionic_if.h
412
IONIC_Q_F_2X_SG_DESC = BIT_ULL(6),
drivers/net/ethernet/pensando/ionic/ionic_if.h
413
IONIC_Q_F_4X_DESC = BIT_ULL(7),
drivers/net/ethernet/pensando/ionic/ionic_if.h
414
IONIC_Q_F_4X_CQ_DESC = BIT_ULL(8),
drivers/net/ethernet/pensando/ionic/ionic_if.h
415
IONIC_Q_F_4X_SG_DESC = BIT_ULL(9),
drivers/net/ethernet/pensando/ionic/ionic_if.h
416
IONIC_QIDENT_F_EXPDB = BIT_ULL(10),
drivers/net/ethernet/pensando/ionic/ionic_if.h
427
IONIC_RXQ_F_HWSTAMP = BIT_ULL(16),
drivers/net/ethernet/pensando/ionic/ionic_if.h
784
#define IONIC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1)
drivers/net/ethernet/pensando/ionic/ionic_if.h
915
#define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1)
drivers/net/ethernet/pensando/ionic/ionic_phc.c
109
mask = cpu_to_le64(BIT_ULL(tx_mode));
drivers/net/ethernet/qlogic/qede/qede_filter.c
1838
~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
drivers/net/ethernet/qlogic/qede/qede_filter.c
1839
BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
drivers/net/ethernet/qlogic/qede/qede_filter.c
1840
BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
drivers/net/ethernet/qlogic/qede/qede_filter.c
1841
BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
drivers/net/ethernet/qlogic/qede/qede_filter.c
1842
BIT_ULL(FLOW_DISSECTOR_KEY_PORTS))) {
drivers/net/ethernet/sfc/ef10.c
4018
return nic_data->datapath_caps & BIT_ULL(flag);
drivers/net/ethernet/sfc/ef10.c
4020
return nic_data->datapath_caps2 & BIT_ULL(flag);
drivers/net/ethernet/sfc/ef100_nic.c
728
return nic_data->datapath_caps & BIT_ULL(flag);
drivers/net/ethernet/sfc/ef100_nic.c
730
return nic_data->datapath_caps2 & BIT_ULL(flag);
drivers/net/ethernet/sfc/ef100_nic.c
732
return nic_data->datapath_caps3 & BIT_ULL(flag);
drivers/net/ethernet/sfc/ef100_nic.h
89
(!!((caps) & BIT_ULL(MC_CMD_GET_CAPABILITIES_V4_OUT_ ## flag ## _LBN)))
drivers/net/ethernet/sfc/tc.c
282
~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
drivers/net/ethernet/sfc/tc.c
283
BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
drivers/net/ethernet/sfc/tc.c
284
BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
drivers/net/ethernet/sfc/tc.c
285
BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) |
drivers/net/ethernet/sfc/tc.c
286
BIT_ULL(FLOW_DISSECTOR_KEY_CVLAN) |
drivers/net/ethernet/sfc/tc.c
287
BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
drivers/net/ethernet/sfc/tc.c
288
BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
drivers/net/ethernet/sfc/tc.c
289
BIT_ULL(FLOW_DISSECTOR_KEY_PORTS) |
drivers/net/ethernet/sfc/tc.c
290
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_KEYID) |
drivers/net/ethernet/sfc/tc.c
291
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
drivers/net/ethernet/sfc/tc.c
292
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
drivers/net/ethernet/sfc/tc.c
293
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IP) |
drivers/net/ethernet/sfc/tc.c
294
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_PORTS) |
drivers/net/ethernet/sfc/tc.c
295
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
drivers/net/ethernet/sfc/tc.c
296
BIT_ULL(FLOW_DISSECTOR_KEY_CT) |
drivers/net/ethernet/sfc/tc.c
297
BIT_ULL(FLOW_DISSECTOR_KEY_TCP) |
drivers/net/ethernet/sfc/tc.c
298
BIT_ULL(FLOW_DISSECTOR_KEY_IP))) {
drivers/net/ethernet/sfc/tc.c
310
(BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
drivers/net/ethernet/sfc/tc.c
311
BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
drivers/net/ethernet/sfc/tc.c
312
BIT_ULL(FLOW_DISSECTOR_KEY_PORTS) |
drivers/net/ethernet/sfc/tc.c
313
BIT_ULL(FLOW_DISSECTOR_KEY_IP) |
drivers/net/ethernet/sfc/tc.c
314
BIT_ULL(FLOW_DISSECTOR_KEY_TCP))) {
drivers/net/ethernet/sfc/tc.c
364
(BIT_ULL(FLOW_DISSECTOR_KEY_PORTS) |
drivers/net/ethernet/sfc/tc.c
365
BIT_ULL(FLOW_DISSECTOR_KEY_TCP))) {
drivers/net/ethernet/sfc/tc.c
425
(BIT_ULL(FLOW_DISSECTOR_KEY_ENC_KEYID) |
drivers/net/ethernet/sfc/tc.c
426
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
drivers/net/ethernet/sfc/tc.c
427
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
drivers/net/ethernet/sfc/tc.c
428
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IP) |
drivers/net/ethernet/sfc/tc.c
429
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_PORTS))) {
drivers/net/ethernet/sfc/tc_conntrack.c
124
~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
drivers/net/ethernet/sfc/tc_conntrack.c
125
BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
drivers/net/ethernet/sfc/tc_conntrack.c
126
BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
drivers/net/ethernet/sfc/tc_conntrack.c
127
BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
drivers/net/ethernet/sfc/tc_conntrack.c
128
BIT_ULL(FLOW_DISSECTOR_KEY_PORTS) |
drivers/net/ethernet/sfc/tc_conntrack.c
129
BIT_ULL(FLOW_DISSECTOR_KEY_TCP) |
drivers/net/ethernet/sfc/tc_conntrack.c
130
BIT_ULL(FLOW_DISSECTOR_KEY_META))) {
drivers/net/ethernet/ti/am65-cpsw-qos.c
1036
~(BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
drivers/net/ethernet/ti/am65-cpsw-qos.c
1037
BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
drivers/net/ethernet/ti/am65-cpsw-qos.c
1038
BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS))) {
drivers/net/ethernet/ti/cpsw_priv.c
1379
~(BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
drivers/net/ethernet/ti/cpsw_priv.c
1380
BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
drivers/net/ethernet/ti/cpsw_priv.c
1381
BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS))) {
drivers/net/thunderbolt/main.c
437
route &= ~BIT_ULL(63);
drivers/net/wireless/ath/ath10k/mac.c
9344
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_BITRATE);
drivers/net/wireless/ath/ath10k/mac.c
9354
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
drivers/net/wireless/ath/ath10k/mac.c
9376
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_DURATION);
drivers/net/wireless/ath/ath10k/mac.c
9387
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
drivers/net/wireless/ath/ath10k/mac.c
9392
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_FAILED);
drivers/net/wireless/ath/ath10k/mac.c
9396
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_RETRIES);
drivers/net/wireless/ath/ath11k/mac.c
9402
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL);
drivers/net/wireless/ath/ath11k/mac.c
9419
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_DURATION);
drivers/net/wireless/ath/ath11k/mac.c
9422
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_DURATION);
drivers/net/wireless/ath/ath11k/mac.c
9436
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
drivers/net/wireless/ath/ath11k/mac.c
9442
if (!(sinfo->filled & BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL)) &&
drivers/net/wireless/ath/ath11k/mac.c
9465
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL);
drivers/net/wireless/ath/ath11k/mac.c
9473
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL_AVG);
drivers/net/wireless/ath/ath12k/mac.c
13396
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL);
drivers/net/wireless/ath/ath12k/mac.c
13430
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_DURATION);
drivers/net/wireless/ath/ath12k/mac.c
13433
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_DURATION);
drivers/net/wireless/ath/ath12k/mac.c
13449
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
drivers/net/wireless/ath/ath12k/mac.c
13467
if (!(sinfo->filled & BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL)) &&
drivers/net/wireless/ath/ath12k/mac.c
13480
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL);
drivers/net/wireless/ath/ath12k/mac.c
13488
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL_AVG);
drivers/net/wireless/ath/ath12k/mac.c
13499
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_RETRIES);
drivers/net/wireless/ath/ath12k/mac.c
13500
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_FAILED);
drivers/net/wireless/ath/ath12k/mac.c
13541
link_sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_DURATION);
drivers/net/wireless/ath/ath12k/mac.c
13544
link_sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_DURATION);
drivers/net/wireless/ath/ath12k/mac.c
13562
link_sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
drivers/net/wireless/ath/ath12k/mac.c
13570
link_sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL_AVG);
drivers/net/wireless/ath/ath12k/mac.c
13574
link_sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_RETRIES);
drivers/net/wireless/ath/ath12k/mac.c
13575
link_sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_FAILED);
drivers/net/wireless/ath/ath12k/mac.c
13596
link_sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL);
drivers/net/wireless/ath/ath6kl/cfg80211.c
1818
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_BYTES64);
drivers/net/wireless/ath/ath6kl/cfg80211.c
1820
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_PACKETS);
drivers/net/wireless/ath/ath6kl/cfg80211.c
1825
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BYTES64);
drivers/net/wireless/ath/ath6kl/cfg80211.c
1827
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_PACKETS);
drivers/net/wireless/ath/ath6kl/cfg80211.c
1831
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL);
drivers/net/wireless/ath/ath6kl/cfg80211.c
1864
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
drivers/net/wireless/ath/ath6kl/cfg80211.c
1869
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_BSS_PARAM);
drivers/net/wireless/ath/wcn36xx/smd.c
2579
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
drivers/net/wireless/ath/wil6210/cfg80211.c
479
sinfo->filled = BIT_ULL(NL80211_STA_INFO_RX_BYTES) |
drivers/net/wireless/ath/wil6210/cfg80211.c
480
BIT_ULL(NL80211_STA_INFO_TX_BYTES) |
drivers/net/wireless/ath/wil6210/cfg80211.c
481
BIT_ULL(NL80211_STA_INFO_RX_PACKETS) |
drivers/net/wireless/ath/wil6210/cfg80211.c
482
BIT_ULL(NL80211_STA_INFO_TX_PACKETS) |
drivers/net/wireless/ath/wil6210/cfg80211.c
483
BIT_ULL(NL80211_STA_INFO_RX_BITRATE) |
drivers/net/wireless/ath/wil6210/cfg80211.c
484
BIT_ULL(NL80211_STA_INFO_TX_BITRATE) |
drivers/net/wireless/ath/wil6210/cfg80211.c
485
BIT_ULL(NL80211_STA_INFO_RX_DROP_MISC) |
drivers/net/wireless/ath/wil6210/cfg80211.c
486
BIT_ULL(NL80211_STA_INFO_TX_FAILED);
drivers/net/wireless/ath/wil6210/cfg80211.c
524
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL);
drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
3033
si->filled |= BIT_ULL(NL80211_STA_INFO_STA_FLAGS);
drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
3070
si->filled |= BIT_ULL(NL80211_STA_INFO_BSS_PARAM);
drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
3102
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
3113
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL);
drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
3122
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_PACKETS) |
drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
3123
BIT_ULL(NL80211_STA_INFO_RX_DROP_MISC) |
drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
3124
BIT_ULL(NL80211_STA_INFO_TX_PACKETS) |
drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
3125
BIT_ULL(NL80211_STA_INFO_TX_FAILED);
drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
3175
sinfo->filled = BIT_ULL(NL80211_STA_INFO_INACTIVE_TIME);
drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
3185
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_CONNECTED_TIME);
drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
3190
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_FAILED);
drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
3192
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_PACKETS);
drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
3195
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_PACKETS);
drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
3199
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
3204
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_BITRATE);
drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
3209
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BYTES);
drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
3211
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_BYTES);
drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
3228
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL);
drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
3229
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL_AVG);
drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
3230
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL);
drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
3232
BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL_AVG);
drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
3246
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL);
drivers/net/wireless/intel/iwlwifi/fw/dbg.c
2626
if (!(BIT_ULL(i) & regions_mask))
drivers/net/wireless/intel/iwlwifi/mld/stats.c
174
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
drivers/net/wireless/intel/iwlwifi/mld/stats.c
68
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL_AVG);
drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c
6027
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL_AVG);
drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c
6034
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c
6057
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_BEACON_RX);
drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c
6062
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_BEACON_SIGNAL_AVG);
drivers/net/wireless/marvell/libertas/cfg.c
1618
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BYTES) |
drivers/net/wireless/marvell/libertas/cfg.c
1619
BIT_ULL(NL80211_STA_INFO_TX_PACKETS) |
drivers/net/wireless/marvell/libertas/cfg.c
1620
BIT_ULL(NL80211_STA_INFO_RX_BYTES) |
drivers/net/wireless/marvell/libertas/cfg.c
1621
BIT_ULL(NL80211_STA_INFO_RX_PACKETS);
drivers/net/wireless/marvell/libertas/cfg.c
1631
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL);
drivers/net/wireless/marvell/libertas/cfg.c
1638
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
drivers/net/wireless/marvell/mwifiex/cfg80211.c
1466
sinfo->filled = BIT_ULL(NL80211_STA_INFO_RX_BYTES) | BIT_ULL(NL80211_STA_INFO_TX_BYTES) |
drivers/net/wireless/marvell/mwifiex/cfg80211.c
1467
BIT_ULL(NL80211_STA_INFO_RX_PACKETS) | BIT_ULL(NL80211_STA_INFO_TX_PACKETS) |
drivers/net/wireless/marvell/mwifiex/cfg80211.c
1468
BIT_ULL(NL80211_STA_INFO_TX_BITRATE) |
drivers/net/wireless/marvell/mwifiex/cfg80211.c
1469
BIT_ULL(NL80211_STA_INFO_SIGNAL) | BIT_ULL(NL80211_STA_INFO_SIGNAL_AVG);
drivers/net/wireless/marvell/mwifiex/cfg80211.c
1475
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_INACTIVE_TIME) |
drivers/net/wireless/marvell/mwifiex/cfg80211.c
1476
BIT_ULL(NL80211_STA_INFO_TX_FAILED);
drivers/net/wireless/marvell/mwifiex/cfg80211.c
1532
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_BSS_PARAM);
drivers/net/wireless/marvell/mwifiex/main.c
967
mac_addr |= BIT_ULL(MWIFIEX_MAC_LOCAL_ADMIN_BIT);
drivers/net/wireless/marvell/mwifiex/main.c
971
mac_addr ^= BIT_ULL(priv->bss_type + 8);
drivers/net/wireless/mediatek/mt76/mt7603/main.c
108
dev->mt76.vif_mask &= ~BIT_ULL(mvif->idx);
drivers/net/wireless/mediatek/mt76/mt7603/main.c
68
dev->mt76.vif_mask |= BIT_ULL(mvif->idx);
drivers/net/wireless/mediatek/mt76/mt7615/main.c
216
dev->mt76.vif_mask |= BIT_ULL(mvif->mt76.idx);
drivers/net/wireless/mediatek/mt76/mt7615/main.c
217
dev->omac_mask |= BIT_ULL(mvif->mt76.omac_idx);
drivers/net/wireless/mediatek/mt76/mt7615/main.c
218
phy->omac_mask |= BIT_ULL(mvif->mt76.omac_idx);
drivers/net/wireless/mediatek/mt76/mt7615/main.c
270
dev->mt76.vif_mask &= ~BIT_ULL(mvif->mt76.idx);
drivers/net/wireless/mediatek/mt76/mt7615/main.c
271
dev->omac_mask &= ~BIT_ULL(mvif->mt76.omac_idx);
drivers/net/wireless/mediatek/mt76/mt7615/main.c
272
phy->omac_mask &= ~BIT_ULL(mvif->mt76.omac_idx);
drivers/net/wireless/mediatek/mt76/mt7615/mcu.c
1856
bool band = !!(ext_phy->omac_mask & BIT_ULL(i));
drivers/net/wireless/mediatek/mt76/mt7615/mcu.c
1862
bool band = !!(ext_phy->omac_mask & BIT_ULL(0x11 + i));
drivers/net/wireless/mediatek/mt76/mt7615/mcu.c
371
if (ext_phy && ext_phy->omac_mask & BIT_ULL(c->omac_idx))
drivers/net/wireless/mediatek/mt76/mt76x02_util.c
329
if (dev->mt76.vif_mask & BIT_ULL(idx) ||
drivers/net/wireless/mediatek/mt76/mt76x02_util.c
333
dev->mt76.vif_mask |= BIT_ULL(idx);
drivers/net/wireless/mediatek/mt76/mt76x02_util.c
346
dev->mt76.vif_mask &= ~BIT_ULL(mvif->idx);
drivers/net/wireless/mediatek/mt76/mt7915/main.c
1163
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_BITRATE);
drivers/net/wireless/mediatek/mt76/mt7915/main.c
1178
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
drivers/net/wireless/mediatek/mt76/mt7915/main.c
1186
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BYTES64);
drivers/net/wireless/mediatek/mt76/mt7915/main.c
1190
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_PACKETS);
drivers/net/wireless/mediatek/mt76/mt7915/main.c
1195
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_BYTES64);
drivers/net/wireless/mediatek/mt76/mt7915/main.c
1198
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_PACKETS);
drivers/net/wireless/mediatek/mt76/mt7915/main.c
1203
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_FAILED);
drivers/net/wireless/mediatek/mt76/mt7915/main.c
1206
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_RETRIES);
drivers/net/wireless/mediatek/mt76/mt7915/main.c
1209
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_ACK_SIGNAL);
drivers/net/wireless/mediatek/mt76/mt7915/main.c
1212
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_ACK_SIGNAL_AVG);
drivers/net/wireless/mediatek/mt76/mt7915/main.c
246
dev->mt76.vif_mask |= BIT_ULL(mvif->mt76.idx);
drivers/net/wireless/mediatek/mt76/mt7915/main.c
247
phy->omac_mask |= BIT_ULL(mvif->mt76.omac_idx);
drivers/net/wireless/mediatek/mt76/mt7915/main.c
311
dev->mt76.vif_mask &= ~BIT_ULL(mvif->mt76.idx);
drivers/net/wireless/mediatek/mt76/mt7915/main.c
312
phy->omac_mask &= ~BIT_ULL(mvif->mt76.omac_idx);
drivers/net/wireless/mediatek/mt76/mt7921/main.c
328
dev->mt76.vif_mask |= BIT_ULL(mvif->bss_conf.mt76.idx);
drivers/net/wireless/mediatek/mt76/mt7921/main.c
329
phy->omac_mask |= BIT_ULL(mvif->bss_conf.mt76.omac_idx);
drivers/net/wireless/mediatek/mt76/mt7925/main.c
387
dev->mt76.vif_mask |= BIT_ULL(mconf->mt76.idx);
drivers/net/wireless/mediatek/mt76/mt7925/main.c
388
mvif->phy->omac_mask |= BIT_ULL(mconf->mt76.omac_idx);
drivers/net/wireless/mediatek/mt76/mt792x_core.c
181
dev->mt76.vif_mask &= ~BIT_ULL(mconf->mt76.idx);
drivers/net/wireless/mediatek/mt76/mt792x_core.c
182
mconf->vif->phy->omac_mask &= ~BIT_ULL(mconf->mt76.omac_idx);
drivers/net/wireless/mediatek/mt76/mt792x_core.c
588
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_FAILED);
drivers/net/wireless/mediatek/mt76/mt792x_core.c
591
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_RETRIES);
drivers/net/wireless/mediatek/mt76/mt792x_core.c
594
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
drivers/net/wireless/mediatek/mt76/mt792x_core.c
597
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_ACK_SIGNAL);
drivers/net/wireless/mediatek/mt76/mt792x_core.c
600
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_ACK_SIGNAL_AVG);
drivers/net/wireless/mediatek/mt76/mt7996/main.c
1679
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
drivers/net/wireless/mediatek/mt76/mt7996/main.c
1682
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
drivers/net/wireless/mediatek/mt76/mt7996/main.c
1685
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_FAILED);
drivers/net/wireless/mediatek/mt76/mt7996/main.c
1688
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_RETRIES);
drivers/net/wireless/mediatek/mt76/mt7996/main.c
1691
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_ACK_SIGNAL);
drivers/net/wireless/mediatek/mt76/mt7996/main.c
1695
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_ACK_SIGNAL_AVG);
drivers/net/wireless/mediatek/mt76/mt7996/main.c
1699
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BYTES64);
drivers/net/wireless/mediatek/mt76/mt7996/main.c
1702
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_BYTES64);
drivers/net/wireless/mediatek/mt76/mt7996/main.c
1705
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_PACKETS);
drivers/net/wireless/mediatek/mt76/mt7996/main.c
1708
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_PACKETS);
drivers/net/wireless/mediatek/mt76/mt7996/main.c
2242
dev->mld_idx_mask |= BIT_ULL(mvif->mld_group_idx);
drivers/net/wireless/mediatek/mt76/mt7996/main.c
2250
dev->mld_remap_idx_mask |= BIT_ULL(mvif->mld_remap_idx);
drivers/net/wireless/mediatek/mt76/mt7996/main.c
2256
dev->mld_idx_mask &= ~BIT_ULL(mvif->mld_group_idx);
drivers/net/wireless/mediatek/mt76/mt7996/main.c
2257
dev->mld_remap_idx_mask &= ~BIT_ULL(mvif->mld_remap_idx);
drivers/net/wireless/mediatek/mt76/mt7996/main.c
330
dev->mt76.vif_mask |= BIT_ULL(mlink->idx);
drivers/net/wireless/mediatek/mt76/mt7996/main.c
331
dev->mld_idx_mask |= BIT_ULL(link->mld_idx);
drivers/net/wireless/mediatek/mt76/mt7996/main.c
332
phy->omac_mask |= BIT_ULL(mlink->omac_idx);
drivers/net/wireless/mediatek/mt76/mt7996/main.c
420
dev->mt76.vif_mask &= ~BIT_ULL(mlink->idx);
drivers/net/wireless/mediatek/mt76/mt7996/main.c
421
dev->mld_idx_mask &= ~BIT_ULL(link->mld_idx);
drivers/net/wireless/mediatek/mt76/mt7996/main.c
422
phy->omac_mask &= ~BIT_ULL(mlink->omac_idx);
drivers/net/wireless/microchip/wilc1000/cfg80211.c
1328
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL);
drivers/net/wireless/microchip/wilc1000/cfg80211.c
761
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_INACTIVE_TIME);
drivers/net/wireless/microchip/wilc1000/cfg80211.c
773
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL) |
drivers/net/wireless/microchip/wilc1000/cfg80211.c
774
BIT_ULL(NL80211_STA_INFO_RX_PACKETS) |
drivers/net/wireless/microchip/wilc1000/cfg80211.c
775
BIT_ULL(NL80211_STA_INFO_TX_PACKETS) |
drivers/net/wireless/microchip/wilc1000/cfg80211.c
776
BIT_ULL(NL80211_STA_INFO_TX_FAILED) |
drivers/net/wireless/microchip/wilc1000/cfg80211.c
777
BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
drivers/net/wireless/quantenna/qtnfmac/commands.c
619
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_INACTIVE_TIME);
drivers/net/wireless/quantenna/qtnfmac/commands.c
625
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_CONNECTED_TIME);
drivers/net/wireless/quantenna/qtnfmac/commands.c
630
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL);
drivers/net/wireless/quantenna/qtnfmac/commands.c
635
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL_AVG);
drivers/net/wireless/quantenna/qtnfmac/commands.c
640
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_BITRATE);
drivers/net/wireless/quantenna/qtnfmac/commands.c
645
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
drivers/net/wireless/quantenna/qtnfmac/commands.c
650
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_STA_FLAGS);
drivers/net/wireless/quantenna/qtnfmac/commands.c
655
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_BYTES);
drivers/net/wireless/quantenna/qtnfmac/commands.c
660
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BYTES);
drivers/net/wireless/quantenna/qtnfmac/commands.c
665
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_BYTES64);
drivers/net/wireless/quantenna/qtnfmac/commands.c
670
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BYTES64);
drivers/net/wireless/quantenna/qtnfmac/commands.c
675
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_PACKETS);
drivers/net/wireless/quantenna/qtnfmac/commands.c
680
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_PACKETS);
drivers/net/wireless/quantenna/qtnfmac/commands.c
685
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_BEACON_RX);
drivers/net/wireless/quantenna/qtnfmac/commands.c
690
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_DROP_MISC);
drivers/net/wireless/quantenna/qtnfmac/commands.c
695
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_FAILED);
drivers/net/wireless/realtek/rtl8xxxu/core.c
7067
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
drivers/net/wireless/realtek/rtlwifi/debug.h
87
#define COMP_TX_REPORT BIT_ULL(32)
drivers/net/wireless/realtek/rtw88/mac80211.c
731
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
drivers/net/wireless/realtek/rtw89/mac80211.c
1056
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
drivers/net/wireless/ti/wlcore/main.c
5811
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL);
drivers/net/wireless/virtual/virt_wifi.c
333
sinfo->filled = BIT_ULL(NL80211_STA_INFO_TX_PACKETS) |
drivers/net/wireless/virtual/virt_wifi.c
334
BIT_ULL(NL80211_STA_INFO_TX_FAILED) |
drivers/net/wireless/virtual/virt_wifi.c
335
BIT_ULL(NL80211_STA_INFO_SIGNAL) |
drivers/net/wireless/virtual/virt_wifi.c
336
BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
drivers/ntb/hw/amd/ntb_hw_amd.c
1137
ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1;
drivers/ntb/hw/amd/ntb_hw_amd.c
1152
ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1;
drivers/ntb/hw/amd/ntb_hw_amd.c
1284
ntb_peer_db_set(&ndev->ntb, BIT_ULL(ndev->db_last_bit));
drivers/ntb/hw/amd/ntb_hw_amd.c
1300
ntb_peer_db_set(&ndev->ntb, BIT_ULL(ndev->db_last_bit));
drivers/ntb/hw/epf/ntb_hw_epf.c
563
ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1;
drivers/ntb/hw/intel/ntb_hw_gen1.c
1125
db_bits = BIT_ULL(db_bit);
drivers/ntb/hw/intel/ntb_hw_gen1.c
1635
ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1;
drivers/ntb/hw/intel/ntb_hw_gen1.c
272
mask = BIT_ULL(shift) - 1;
drivers/ntb/hw/intel/ntb_hw_gen1.h
121
#define XEON_DB_LINK_BIT BIT_ULL(XEON_DB_LINK)
drivers/ntb/hw/intel/ntb_hw_gen1.h
139
#define NTB_HWERR_SDOORBELL_LOCKUP BIT_ULL(0)
drivers/ntb/hw/intel/ntb_hw_gen1.h
140
#define NTB_HWERR_SB01BASE_LOCKUP BIT_ULL(1)
drivers/ntb/hw/intel/ntb_hw_gen1.h
141
#define NTB_HWERR_B2BDOORBELL_BIT14 BIT_ULL(2)
drivers/ntb/hw/intel/ntb_hw_gen1.h
142
#define NTB_HWERR_MSIX_VECTOR32_BAD BIT_ULL(3)
drivers/ntb/hw/intel/ntb_hw_gen1.h
143
#define NTB_HWERR_BAR_ALIGN BIT_ULL(4)
drivers/ntb/hw/intel/ntb_hw_gen1.h
144
#define NTB_HWERR_LTR_BAD BIT_ULL(5)
drivers/ntb/hw/intel/ntb_hw_gen3.c
185
ndev->db_link_mask |= BIT_ULL(31);
drivers/ntb/hw/intel/ntb_hw_gen3.c
217
ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1;
drivers/ntb/hw/intel/ntb_hw_gen3.c
547
if (unlikely(BIT_ULL(db_bit) & ~ntb_ndev(ntb)->db_valid_mask))
drivers/ntb/hw/intel/ntb_hw_gen3.h
88
#define GEN3_DB_LINK_BIT BIT_ULL(GEN3_DB_LINK)
drivers/ntb/hw/intel/ntb_hw_gen4.c
160
ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1;
drivers/ntb/hw/intel/ntb_hw_gen4.h
75
#define GEN4_DB_LINK_BIT BIT_ULL(GEN4_DB_LINK)
drivers/ntb/hw/intel/ntb_hw_intel.h
94
#define NTB_UNSAFE_DB BIT_ULL(0)
drivers/ntb/hw/intel/ntb_hw_intel.h
95
#define NTB_UNSAFE_SPAD BIT_ULL(1)
drivers/ntb/hw/mscc/ntb_hw_switchtec.c
291
if (xlate_pos >= 0 && !IS_ALIGNED(addr, BIT_ULL(xlate_pos))) {
drivers/ntb/hw/mscc/ntb_hw_switchtec.c
709
*db_data = BIT_ULL(db_bit) << sndev->db_peer_shift;
drivers/ntb/ntb_transport.c
1327
nt->msi_db_mask = BIT_ULL(qp_count);
drivers/ntb/ntb_transport.c
1336
qp_bitmap &= BIT_ULL(qp_count) - 1;
drivers/ntb/ntb_transport.c
1411
if (qp_bitmap_alloc & BIT_ULL(i))
drivers/ntb/ntb_transport.c
1702
} else if (ntb_db_read(qp->ndev) & BIT_ULL(qp->qp_num)) {
drivers/ntb/ntb_transport.c
1704
ntb_db_clear(qp->ndev, BIT_ULL(qp->qp_num));
drivers/ntb/ntb_transport.c
1763
ntb_peer_db_set(qp->ndev, BIT_ULL(qp->qp_num));
drivers/ntb/ntb_transport.c
2048
qp_bit = BIT_ULL(qp->qp_num);
drivers/ntb/ntb_transport.c
2218
qp_bit = BIT_ULL(qp->qp_num);
drivers/ntb/ntb_transport.c
2516
db_bits &= ~BIT_ULL(qp_num);
drivers/ntb/ntb_transport.c
966
if (qp_bitmap_alloc & BIT_ULL(i)) {
drivers/ntb/test/ntb_perf.c
223
(BIT_ULL(_gidx))
drivers/ntb/test/ntb_perf.c
715
incmd_bit = BIT_ULL(__ffs64(inbits));
drivers/ntb/test/ntb_pingpong.c
131
out_db = BIT_ULL(ntb_peer_port_number(pp->ntb, pidx));
drivers/ntb/test/ntb_pingpong.c
304
pp->in_db = BIT_ULL(lport);
drivers/pci/endpoint/functions/pci-epf-vntb.c
1264
return BIT_ULL(ntb_ndev(ntb)->db_count) - 1;
drivers/pci/endpoint/pci-epf-core.c
392
if ((limit ^ bar_addr) & BIT_ULL(pos))
drivers/pci/endpoint/pci-epf-core.c
398
bar_size = BIT_ULL(pos + 1);
drivers/perf/arm-cmn.c
166
#define CMN_CONFIG_BYNODEID BIT_ULL(31)
drivers/perf/arm-cmn.c
179
#define CMN_CONFIG_WP_EXCLUSIVE BIT_ULL(58)
drivers/perf/arm-cmn.c
49
#define CMN_INFO_MULTIPLE_DTM_EN BIT_ULL(63)
drivers/perf/arm-cmn.c
52
#define CMN_INFO_DEVICE_ISO_ENABLE BIT_ULL(44)
drivers/perf/cxl_pmu.c
35
#define CXL_PMU_CAP_WRITEABLE_WHEN_FROZEN BIT_ULL(48)
drivers/perf/cxl_pmu.c
36
#define CXL_PMU_CAP_FREEZE BIT_ULL(49)
drivers/perf/cxl_pmu.c
37
#define CXL_PMU_CAP_INT BIT_ULL(50)
drivers/perf/cxl_pmu.c
52
#define CXL_PMU_COUNTER_CFG_ENABLE BIT_ULL(8)
drivers/perf/cxl_pmu.c
53
#define CXL_PMU_COUNTER_CFG_INT_ON_OVRFLW BIT_ULL(9)
drivers/perf/cxl_pmu.c
54
#define CXL_PMU_COUNTER_CFG_FREEZE_ON_OVRFLW BIT_ULL(10)
drivers/perf/cxl_pmu.c
55
#define CXL_PMU_COUNTER_CFG_EDGE BIT_ULL(11)
drivers/perf/cxl_pmu.c
56
#define CXL_PMU_COUNTER_CFG_INVERT BIT_ULL(12)
drivers/perf/hisilicon/hisi_pcie_pmu.c
39
#define HISI_PCIE_EVENT_EN BIT_ULL(20)
drivers/perf/hisilicon/hisi_pcie_pmu.c
40
#define HISI_PCIE_RESET_CNT BIT_ULL(22)
drivers/perf/hisilicon/hisi_pcie_pmu.c
41
#define HISI_PCIE_INIT_SET BIT_ULL(34)
drivers/perf/hisilicon/hisi_pcie_pmu.c
42
#define HISI_PCIE_THR_EN BIT_ULL(26)
drivers/perf/hisilicon/hisi_pcie_pmu.c
43
#define HISI_PCIE_TARGET_EN BIT_ULL(32)
drivers/perf/hisilicon/hisi_pcie_pmu.c
44
#define HISI_PCIE_TRIG_EN BIT_ULL(52)
drivers/perf/hisilicon/hisi_pcie_pmu.c
63
#define HISI_PCIE_INIT_VAL BIT_ULL(63)
drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c
34
#define CPA_PERF_CTRL_EN BIT_ULL(0)
drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c
36
#define CPA_PM_CTRL BIT_ULL(9)
drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
178
val |= BIT_ULL(hwc->idx);
drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
189
val &= ~BIT_ULL(hwc->idx);
drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
200
val &= ~BIT_ULL(hwc->idx);
drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
211
val |= BIT_ULL(hwc->idx);
drivers/perf/hisilicon/hisi_uncore_pmu.c
307
u64 val = BIT_ULL(hisi_pmu->counter_bits - 1);
drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c
279
val |= BIT_ULL(hwc->idx);
drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c
290
val &= ~BIT_ULL(hwc->idx);
drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c
301
val &= ~BIT_ULL(hwc->idx);
drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c
312
val |= BIT_ULL(hwc->idx);
drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c
327
writel(BIT_ULL(idx), sllc_pmu->base + regs->int_clear);
drivers/perf/marvell_cn10k_ddr_pmu.c
138
#define DDRC_PERF_CNT_VALUE_OVERFLOW BIT_ULL(48)
drivers/perf/marvell_cn10k_ddr_pmu.c
52
#define EVENT_ENABLE BIT_ULL(63)
drivers/perf/marvell_cn10k_ddr_pmu.c
942
.counter_overflow_val = BIT_ULL(48),
drivers/perf/qcom_l2_pmu.c
67
#define L2PMRESR_EN BIT_ULL(63)
drivers/perf/qcom_l2_pmu.c
80
#define L2_COUNTER_RELOAD BIT_ULL(31)
drivers/perf/qcom_l2_pmu.c
81
#define L2_CYCLE_COUNTER_RELOAD BIT_ULL(63)
drivers/perf/qcom_l3_pmu.c
143
return !!(event->attr.config & BIT_ULL(L3_EVENT_LC_BIT));
drivers/perf/starfive_starlink_pmu.c
203
val |= BIT_ULL(idx);
drivers/perf/starfive_starlink_pmu.c
227
val &= ~BIT_ULL(idx);
drivers/perf/starfive_starlink_pmu.c
35
#define STARLINK_PMU_GLOBAL_ENABLE BIT_ULL(0)
drivers/perf/starfive_starlink_pmu.c
39
#define STARLINK_PMU_CYCLE_OVERFLOW_MASK BIT_ULL(63)
drivers/perf/starfive_starlink_pmu.c
414
if (!(overflow_status & BIT_ULL(idx)))
drivers/perf/starfive_starlink_pmu.c
417
writeq(BIT_ULL(idx), starlink_pmu->pmu_base +
drivers/pinctrl/renesas/pinctrl-rzg2l.c
67
#define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */
drivers/pinctrl/renesas/pinctrl-rzg2l.c
68
#define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */
drivers/platform/mellanox/mlxbf-tmfifo.c
240
(BIT_ULL(VIRTIO_NET_F_MTU) | BIT_ULL(VIRTIO_NET_F_STATUS) | \
drivers/platform/mellanox/mlxbf-tmfifo.c
241
BIT_ULL(VIRTIO_NET_F_MAC))
drivers/platform/raspberrypi/vchiq-mmal/mmal-common.h
23
#define MMAL_TIME_UNKNOWN BIT_ULL(63)
drivers/platform/surface/aggregator/controller.c
1068
if (!(funcs & BIT_ULL(func)))
drivers/platform/surface/surface_acpi_notify.c
192
if (!acpi_check_dsm(san, &SAN_DSM_UUID, SAN_DSM_REVISION, BIT_ULL(func)))
drivers/platform/x86/intel/plr_tpmi.c
37
#define PLR_RUN_BUSY BIT_ULL(63)
drivers/platform/x86/intel/speed_select_if/isst_if_mbox_msr.c
44
if (data & BIT_ULL(MSR_OS_MAILBOX_BUSY_BIT)) {
drivers/platform/x86/intel/speed_select_if/isst_if_mbox_msr.c
59
data = BIT_ULL(MSR_OS_MAILBOX_BUSY_BIT) |
drivers/platform/x86/intel/speed_select_if/isst_if_mbox_msr.c
69
if (data & BIT_ULL(MSR_OS_MAILBOX_BUSY_BIT)) {
drivers/platform/x86/intel/speed_select_if/isst_if_mbox_pci.c
55
if (data & BIT_ULL(PUNIT_MAILBOX_BUSY_BIT)) {
drivers/platform/x86/intel/speed_select_if/isst_if_mbox_pci.c
76
data = BIT_ULL(PUNIT_MAILBOX_BUSY_BIT) |
drivers/platform/x86/intel/speed_select_if/isst_if_mbox_pci.c
94
if (data & BIT_ULL(PUNIT_MAILBOX_BUSY_BIT)) {
drivers/platform/x86/intel/turbo_max_3.c
44
value |= BIT_ULL(MSR_OC_MAILBOX_BUSY_BIT);
drivers/platform/x86/intel/turbo_max_3.c
58
if (value & BIT_ULL(MSR_OC_MAILBOX_BUSY_BIT)) {
drivers/platform/x86/intel/vsec_tpmi.c
238
#define TPMI_CONTROL_STATUS_RB BIT_ULL(0)
drivers/platform/x86/intel/vsec_tpmi.c
244
#define TPMI_CONTROL_STATUS_CPL BIT_ULL(6)
drivers/powercap/intel_rapl_common.c
41
#define POWER_LIMIT2_ENABLE BIT_ULL(47)
drivers/powercap/intel_rapl_common.c
42
#define POWER_LIMIT2_CLAMP BIT_ULL(48)
drivers/powercap/intel_rapl_common.c
43
#define POWER_HIGH_LOCK BIT_ULL(63)
drivers/powercap/intel_rapl_common.c
77
#define PSYS_POWER_LIMIT2_ENABLE BIT_ULL(49)
drivers/powercap/intel_rapl_common.c
84
#define TPMI_POWER_LIMIT_ENABLE BIT_ULL(62)
drivers/ptp/ptp_dte.c
132
ns += (s64)(BIT_ULL(DTE_WRAP_AROUND_NSEC_SHIFT) * ptp_dte->ts_wrap_cnt);
drivers/pwm/pwm-xilinx.c
257
priv->max = BIT_ULL(width) - 1;
drivers/ras/amd/atl/core.c
58
addr += (BIT_ULL(32) - df_cfg.dram_hole_base);
drivers/ras/amd/atl/core.c
69
addr -= (BIT_ULL(32) - df_cfg.dram_hole_base);
drivers/ras/amd/atl/dehash.c
102
intlv_bit = !!(BIT_ULL(intlv_bit_pos) & ctx->ret_addr);
drivers/ras/amd/atl/dehash.c
105
hashed_bit ^= !!(BIT_ULL(intlv_bit_pos + num_intlv_bits) & ctx->ret_addr);
drivers/ras/amd/atl/dehash.c
106
hashed_bit ^= FIELD_GET(BIT_ULL(23), ctx->ret_addr) & hash_ctl_2M;
drivers/ras/amd/atl/dehash.c
107
hashed_bit ^= FIELD_GET(BIT_ULL(32), ctx->ret_addr) & hash_ctl_1G;
drivers/ras/amd/atl/dehash.c
110
ctx->ret_addr ^= BIT_ULL(intlv_bit_pos);
drivers/ras/amd/atl/dehash.c
113
intlv_bit = !!(BIT_ULL(intlv_bit_pos) & ctx->ret_addr);
drivers/ras/amd/atl/dehash.c
116
hashed_bit ^= FIELD_GET(BIT_ULL(21), ctx->ret_addr) & hash_ctl_2M;
drivers/ras/amd/atl/dehash.c
117
hashed_bit ^= FIELD_GET(BIT_ULL(30), ctx->ret_addr) & hash_ctl_1G;
drivers/ras/amd/atl/dehash.c
120
ctx->ret_addr ^= BIT_ULL(intlv_bit_pos);
drivers/ras/amd/atl/dehash.c
123
intlv_bit = !!(BIT_ULL(intlv_bit_pos) & ctx->ret_addr);
drivers/ras/amd/atl/dehash.c
126
hashed_bit ^= FIELD_GET(BIT_ULL(22), ctx->ret_addr) & hash_ctl_2M;
drivers/ras/amd/atl/dehash.c
127
hashed_bit ^= FIELD_GET(BIT_ULL(31), ctx->ret_addr) & hash_ctl_1G;
drivers/ras/amd/atl/dehash.c
130
ctx->ret_addr ^= BIT_ULL(intlv_bit_pos);
drivers/ras/amd/atl/dehash.c
144
intlv_bit = FIELD_GET(BIT_ULL(8), ctx->ret_addr);
drivers/ras/amd/atl/dehash.c
147
hashed_bit ^= FIELD_GET(BIT_ULL(16), ctx->ret_addr) & hash_ctl_64k;
drivers/ras/amd/atl/dehash.c
148
hashed_bit ^= FIELD_GET(BIT_ULL(21), ctx->ret_addr) & hash_ctl_2M;
drivers/ras/amd/atl/dehash.c
149
hashed_bit ^= FIELD_GET(BIT_ULL(30), ctx->ret_addr) & hash_ctl_1G;
drivers/ras/amd/atl/dehash.c
152
hashed_bit ^= FIELD_GET(BIT_ULL(14), ctx->ret_addr);
drivers/ras/amd/atl/dehash.c
155
ctx->ret_addr ^= BIT_ULL(8);
drivers/ras/amd/atl/dehash.c
166
intlv_bit = FIELD_GET(BIT_ULL(12), ctx->ret_addr);
drivers/ras/amd/atl/dehash.c
169
hashed_bit ^= FIELD_GET(BIT_ULL(17), ctx->ret_addr) & hash_ctl_64k;
drivers/ras/amd/atl/dehash.c
170
hashed_bit ^= FIELD_GET(BIT_ULL(22), ctx->ret_addr) & hash_ctl_2M;
drivers/ras/amd/atl/dehash.c
171
hashed_bit ^= FIELD_GET(BIT_ULL(31), ctx->ret_addr) & hash_ctl_1G;
drivers/ras/amd/atl/dehash.c
174
ctx->ret_addr ^= BIT_ULL(12);
drivers/ras/amd/atl/dehash.c
180
intlv_bit = FIELD_GET(BIT_ULL(13), ctx->ret_addr);
drivers/ras/amd/atl/dehash.c
183
hashed_bit ^= FIELD_GET(BIT_ULL(18), ctx->ret_addr) & hash_ctl_64k;
drivers/ras/amd/atl/dehash.c
184
hashed_bit ^= FIELD_GET(BIT_ULL(23), ctx->ret_addr) & hash_ctl_2M;
drivers/ras/amd/atl/dehash.c
185
hashed_bit ^= FIELD_GET(BIT_ULL(32), ctx->ret_addr) & hash_ctl_1G;
drivers/ras/amd/atl/dehash.c
188
ctx->ret_addr ^= BIT_ULL(13);
drivers/ras/amd/atl/dehash.c
194
intlv_bit = FIELD_GET(BIT_ULL(14), ctx->ret_addr);
drivers/ras/amd/atl/dehash.c
197
hashed_bit ^= FIELD_GET(BIT_ULL(19), ctx->ret_addr) & hash_ctl_64k;
drivers/ras/amd/atl/dehash.c
198
hashed_bit ^= FIELD_GET(BIT_ULL(24), ctx->ret_addr) & hash_ctl_2M;
drivers/ras/amd/atl/dehash.c
199
hashed_bit ^= FIELD_GET(BIT_ULL(33), ctx->ret_addr) & hash_ctl_1G;
drivers/ras/amd/atl/dehash.c
20
intlv_bit = !!(BIT_ULL(intlv_bit_pos) & ctx->ret_addr);
drivers/ras/amd/atl/dehash.c
202
ctx->ret_addr ^= BIT_ULL(14);
drivers/ras/amd/atl/dehash.c
23
hashed_bit ^= FIELD_GET(BIT_ULL(12), ctx->ret_addr);
drivers/ras/amd/atl/dehash.c
238
if (rehash_vector & BIT_ULL(8)) {
drivers/ras/amd/atl/dehash.c
239
intlv_bit = FIELD_GET(BIT_ULL(8), ctx->ret_addr);
drivers/ras/amd/atl/dehash.c
24
hashed_bit ^= FIELD_GET(BIT_ULL(18), ctx->ret_addr);
drivers/ras/amd/atl/dehash.c
242
hashed_bit ^= FIELD_GET(BIT_ULL(16), ctx->ret_addr) & hash_ctl_64k;
drivers/ras/amd/atl/dehash.c
243
hashed_bit ^= FIELD_GET(BIT_ULL(21), ctx->ret_addr) & hash_ctl_2M;
drivers/ras/amd/atl/dehash.c
244
hashed_bit ^= FIELD_GET(BIT_ULL(30), ctx->ret_addr) & hash_ctl_1G;
drivers/ras/amd/atl/dehash.c
245
hashed_bit ^= FIELD_GET(BIT_ULL(40), ctx->ret_addr) & hash_ctl_1T;
drivers/ras/amd/atl/dehash.c
248
ctx->ret_addr ^= BIT_ULL(8);
drivers/ras/amd/atl/dehash.c
25
hashed_bit ^= FIELD_GET(BIT_ULL(21), ctx->ret_addr);
drivers/ras/amd/atl/dehash.c
251
if (rehash_vector & BIT_ULL(9)) {
drivers/ras/amd/atl/dehash.c
252
intlv_bit = FIELD_GET(BIT_ULL(9), ctx->ret_addr);
drivers/ras/amd/atl/dehash.c
255
hashed_bit ^= FIELD_GET(BIT_ULL(17), ctx->ret_addr) & hash_ctl_64k;
drivers/ras/amd/atl/dehash.c
256
hashed_bit ^= FIELD_GET(BIT_ULL(22), ctx->ret_addr) & hash_ctl_2M;
drivers/ras/amd/atl/dehash.c
257
hashed_bit ^= FIELD_GET(BIT_ULL(31), ctx->ret_addr) & hash_ctl_1G;
drivers/ras/amd/atl/dehash.c
258
hashed_bit ^= FIELD_GET(BIT_ULL(41), ctx->ret_addr) & hash_ctl_1T;
drivers/ras/amd/atl/dehash.c
26
hashed_bit ^= FIELD_GET(BIT_ULL(30), ctx->ret_addr);
drivers/ras/amd/atl/dehash.c
261
ctx->ret_addr ^= BIT_ULL(9);
drivers/ras/amd/atl/dehash.c
264
if (rehash_vector & BIT_ULL(12)) {
drivers/ras/amd/atl/dehash.c
265
intlv_bit = FIELD_GET(BIT_ULL(12), ctx->ret_addr);
drivers/ras/amd/atl/dehash.c
268
hashed_bit ^= FIELD_GET(BIT_ULL(18), ctx->ret_addr) & hash_ctl_64k;
drivers/ras/amd/atl/dehash.c
269
hashed_bit ^= FIELD_GET(BIT_ULL(23), ctx->ret_addr) & hash_ctl_2M;
drivers/ras/amd/atl/dehash.c
270
hashed_bit ^= FIELD_GET(BIT_ULL(32), ctx->ret_addr) & hash_ctl_1G;
drivers/ras/amd/atl/dehash.c
271
hashed_bit ^= FIELD_GET(BIT_ULL(42), ctx->ret_addr) & hash_ctl_1T;
drivers/ras/amd/atl/dehash.c
274
ctx->ret_addr ^= BIT_ULL(12);
drivers/ras/amd/atl/dehash.c
277
if (rehash_vector & BIT_ULL(13)) {
drivers/ras/amd/atl/dehash.c
278
intlv_bit = FIELD_GET(BIT_ULL(13), ctx->ret_addr);
drivers/ras/amd/atl/dehash.c
281
hashed_bit ^= FIELD_GET(BIT_ULL(19), ctx->ret_addr) & hash_ctl_64k;
drivers/ras/amd/atl/dehash.c
282
hashed_bit ^= FIELD_GET(BIT_ULL(24), ctx->ret_addr) & hash_ctl_2M;
drivers/ras/amd/atl/dehash.c
283
hashed_bit ^= FIELD_GET(BIT_ULL(33), ctx->ret_addr) & hash_ctl_1G;
drivers/ras/amd/atl/dehash.c
284
hashed_bit ^= FIELD_GET(BIT_ULL(43), ctx->ret_addr) & hash_ctl_1T;
drivers/ras/amd/atl/dehash.c
287
ctx->ret_addr ^= BIT_ULL(13);
drivers/ras/amd/atl/dehash.c
29
ctx->ret_addr ^= BIT_ULL(intlv_bit_pos);
drivers/ras/amd/atl/dehash.c
290
if (rehash_vector & BIT_ULL(14)) {
drivers/ras/amd/atl/dehash.c
291
intlv_bit = FIELD_GET(BIT_ULL(14), ctx->ret_addr);
drivers/ras/amd/atl/dehash.c
294
hashed_bit ^= FIELD_GET(BIT_ULL(20), ctx->ret_addr) & hash_ctl_64k;
drivers/ras/amd/atl/dehash.c
295
hashed_bit ^= FIELD_GET(BIT_ULL(25), ctx->ret_addr) & hash_ctl_2M;
drivers/ras/amd/atl/dehash.c
296
hashed_bit ^= FIELD_GET(BIT_ULL(34), ctx->ret_addr) & hash_ctl_1G;
drivers/ras/amd/atl/dehash.c
297
hashed_bit ^= FIELD_GET(BIT_ULL(44), ctx->ret_addr) & hash_ctl_1T;
drivers/ras/amd/atl/dehash.c
300
ctx->ret_addr ^= BIT_ULL(14);
drivers/ras/amd/atl/dehash.c
339
intlv_bit = BIT_ULL(base_bit) & ctx->ret_addr;
drivers/ras/amd/atl/dehash.c
345
test_bit = BIT_ULL(12 + i) & ctx->ret_addr;
drivers/ras/amd/atl/dehash.c
350
test_bit = BIT_ULL(15 + i) & ctx->ret_addr;
drivers/ras/amd/atl/dehash.c
352
test_bit = BIT_ULL(22 + i) & ctx->ret_addr;
drivers/ras/amd/atl/dehash.c
354
test_bit = BIT_ULL(29 + i) & ctx->ret_addr;
drivers/ras/amd/atl/dehash.c
356
test_bit = BIT_ULL(36 + i) & ctx->ret_addr;
drivers/ras/amd/atl/dehash.c
358
test_bit = BIT_ULL(43 + i) & ctx->ret_addr;
drivers/ras/amd/atl/dehash.c
362
ctx->ret_addr ^= BIT_ULL(base_bit);
drivers/ras/amd/atl/dehash.c
371
intlv_bit = BIT_ULL(base_bit) & ctx->ret_addr;
drivers/ras/amd/atl/dehash.c
375
test_bit = BIT_ULL(20 + i) & ctx->ret_addr;
drivers/ras/amd/atl/dehash.c
377
test_bit = BIT_ULL(27 + i) & ctx->ret_addr;
drivers/ras/amd/atl/dehash.c
379
test_bit = BIT_ULL(34 + i) & ctx->ret_addr;
drivers/ras/amd/atl/dehash.c
381
test_bit = BIT_ULL(41 + i) & ctx->ret_addr;
drivers/ras/amd/atl/dehash.c
385
ctx->ret_addr ^= BIT_ULL(base_bit);
drivers/ras/amd/atl/dehash.c
44
intlv_bit = !!(BIT_ULL(intlv_bit_pos) & ctx->ret_addr);
drivers/ras/amd/atl/dehash.c
47
hashed_bit ^= FIELD_GET(BIT_ULL(14), ctx->ret_addr);
drivers/ras/amd/atl/dehash.c
48
hashed_bit ^= FIELD_GET(BIT_ULL(18), ctx->ret_addr) & hash_ctl_64k;
drivers/ras/amd/atl/dehash.c
49
hashed_bit ^= FIELD_GET(BIT_ULL(23), ctx->ret_addr) & hash_ctl_2M;
drivers/ras/amd/atl/dehash.c
50
hashed_bit ^= FIELD_GET(BIT_ULL(32), ctx->ret_addr) & hash_ctl_1G;
drivers/ras/amd/atl/dehash.c
53
ctx->ret_addr ^= BIT_ULL(intlv_bit_pos);
drivers/ras/amd/atl/dehash.c
59
intlv_bit = FIELD_GET(BIT_ULL(12), ctx->ret_addr);
drivers/ras/amd/atl/dehash.c
62
hashed_bit ^= FIELD_GET(BIT_ULL(16), ctx->ret_addr) & hash_ctl_64k;
drivers/ras/amd/atl/dehash.c
63
hashed_bit ^= FIELD_GET(BIT_ULL(21), ctx->ret_addr) & hash_ctl_2M;
drivers/ras/amd/atl/dehash.c
64
hashed_bit ^= FIELD_GET(BIT_ULL(30), ctx->ret_addr) & hash_ctl_1G;
drivers/ras/amd/atl/dehash.c
67
ctx->ret_addr ^= BIT_ULL(12);
drivers/ras/amd/atl/dehash.c
73
intlv_bit = FIELD_GET(BIT_ULL(13), ctx->ret_addr);
drivers/ras/amd/atl/dehash.c
76
hashed_bit ^= FIELD_GET(BIT_ULL(17), ctx->ret_addr) & hash_ctl_64k;
drivers/ras/amd/atl/dehash.c
77
hashed_bit ^= FIELD_GET(BIT_ULL(22), ctx->ret_addr) & hash_ctl_2M;
drivers/ras/amd/atl/dehash.c
78
hashed_bit ^= FIELD_GET(BIT_ULL(31), ctx->ret_addr) & hash_ctl_1G;
drivers/ras/amd/atl/dehash.c
81
ctx->ret_addr ^= BIT_ULL(13);
drivers/ras/amd/atl/denormalize.c
1033
denorm_addr |= FIELD_GET(BIT_ULL(0), temp_addr) << 9;
drivers/ras/amd/atl/denormalize.c
1045
denorm_addr |= FIELD_GET(BIT_ULL(0), temp_addr) << 8;
drivers/ras/amd/atl/denormalize.c
1056
denorm_addr |= FIELD_GET(BIT_ULL(0), test_perm) << 8;
drivers/ras/amd/atl/denormalize.c
1057
denorm_addr |= FIELD_GET(BIT_ULL(1), test_perm) << 9;
drivers/ras/amd/atl/denormalize.c
1058
denorm_addr |= FIELD_GET(BIT_ULL(2), test_perm) << 12;
drivers/ras/amd/atl/denormalize.c
1062
denorm_addr |= FIELD_GET(BIT_ULL(0), test_perm) << 8;
drivers/ras/amd/atl/denormalize.c
1063
denorm_addr |= FIELD_GET(BIT_ULL(1), test_perm) << 12;
drivers/ras/amd/atl/denormalize.c
1064
denorm_addr |= FIELD_GET(BIT_ULL(2), test_perm) << 13;
drivers/ras/amd/atl/denormalize.c
1068
denorm_addr |= FIELD_GET(BIT_ULL(0), test_perm) << 8;
drivers/ras/amd/atl/denormalize.c
1069
denorm_addr |= FIELD_GET(BIT_ULL(1), test_perm) << 12;
drivers/ras/amd/atl/denormalize.c
1075
denorm_addr |= FIELD_GET(BIT_ULL(0), test_perm) << 8;
drivers/ras/amd/atl/denormalize.c
1076
denorm_addr |= FIELD_GET(BIT_ULL(1), test_perm) << 9;
drivers/ras/amd/atl/denormalize.c
1085
denorm_addr |= FIELD_GET(BIT_ULL(0), test_perm) << 8;
drivers/ras/amd/atl/denormalize.c
463
hash_pa8 = FIELD_GET(BIT_ULL(8), denorm_ctx->current_spa);
drivers/ras/amd/atl/denormalize.c
464
hash_pa8 ^= FIELD_GET(BIT_ULL(14), denorm_ctx->current_spa);
drivers/ras/amd/atl/denormalize.c
465
hash_pa8 ^= FIELD_GET(BIT_ULL(16), denorm_ctx->current_spa) & hash_ctl_64k;
drivers/ras/amd/atl/denormalize.c
466
hash_pa8 ^= FIELD_GET(BIT_ULL(21), denorm_ctx->current_spa) & hash_ctl_2M;
drivers/ras/amd/atl/denormalize.c
467
hash_pa8 ^= FIELD_GET(BIT_ULL(30), denorm_ctx->current_spa) & hash_ctl_1G;
drivers/ras/amd/atl/denormalize.c
468
hash_pa8 ^= FIELD_GET(BIT_ULL(40), denorm_ctx->current_spa) & hash_ctl_1T;
drivers/ras/amd/atl/denormalize.c
470
hash_pa9 = FIELD_GET(BIT_ULL(9), denorm_ctx->current_spa);
drivers/ras/amd/atl/denormalize.c
471
hash_pa9 ^= FIELD_GET(BIT_ULL(17), denorm_ctx->current_spa) & hash_ctl_64k;
drivers/ras/amd/atl/denormalize.c
472
hash_pa9 ^= FIELD_GET(BIT_ULL(22), denorm_ctx->current_spa) & hash_ctl_2M;
drivers/ras/amd/atl/denormalize.c
473
hash_pa9 ^= FIELD_GET(BIT_ULL(31), denorm_ctx->current_spa) & hash_ctl_1G;
drivers/ras/amd/atl/denormalize.c
474
hash_pa9 ^= FIELD_GET(BIT_ULL(41), denorm_ctx->current_spa) & hash_ctl_1T;
drivers/ras/amd/atl/denormalize.c
476
hash_pa12 = FIELD_GET(BIT_ULL(12), denorm_ctx->current_spa);
drivers/ras/amd/atl/denormalize.c
477
hash_pa12 ^= FIELD_GET(BIT_ULL(18), denorm_ctx->current_spa) & hash_ctl_64k;
drivers/ras/amd/atl/denormalize.c
478
hash_pa12 ^= FIELD_GET(BIT_ULL(23), denorm_ctx->current_spa) & hash_ctl_2M;
drivers/ras/amd/atl/denormalize.c
479
hash_pa12 ^= FIELD_GET(BIT_ULL(32), denorm_ctx->current_spa) & hash_ctl_1G;
drivers/ras/amd/atl/denormalize.c
480
hash_pa12 ^= FIELD_GET(BIT_ULL(42), denorm_ctx->current_spa) & hash_ctl_1T;
drivers/ras/amd/atl/denormalize.c
482
hash_pa13 = FIELD_GET(BIT_ULL(13), denorm_ctx->current_spa);
drivers/ras/amd/atl/denormalize.c
483
hash_pa13 ^= FIELD_GET(BIT_ULL(19), denorm_ctx->current_spa) & hash_ctl_64k;
drivers/ras/amd/atl/denormalize.c
484
hash_pa13 ^= FIELD_GET(BIT_ULL(24), denorm_ctx->current_spa) & hash_ctl_2M;
drivers/ras/amd/atl/denormalize.c
485
hash_pa13 ^= FIELD_GET(BIT_ULL(33), denorm_ctx->current_spa) & hash_ctl_1G;
drivers/ras/amd/atl/denormalize.c
486
hash_pa13 ^= FIELD_GET(BIT_ULL(43), denorm_ctx->current_spa) & hash_ctl_1T;
drivers/ras/amd/atl/denormalize.c
522
cs_id |= (FIELD_GET(BIT_ULL(9), denorm_ctx->current_spa) << 1);
drivers/ras/amd/atl/denormalize.c
546
cs_id |= FIELD_GET(BIT_ULL(8), denorm_ctx->current_spa) << 1;
drivers/ras/amd/atl/denormalize.c
689
hash_pa8 = BIT_ULL(shift_value) & ctx->ret_addr;
drivers/ras/amd/atl/denormalize.c
777
hashed_bit ^= FIELD_GET(BIT_ULL(14), ctx->ret_addr);
drivers/ras/amd/atl/denormalize.c
778
hashed_bit ^= FIELD_GET(BIT_ULL(16), ctx->ret_addr) & hash_ctl_64k;
drivers/ras/amd/atl/denormalize.c
779
hashed_bit ^= FIELD_GET(BIT_ULL(21), ctx->ret_addr) & hash_ctl_2M;
drivers/ras/amd/atl/denormalize.c
780
hashed_bit ^= FIELD_GET(BIT_ULL(30), ctx->ret_addr) & hash_ctl_1G;
drivers/ras/amd/atl/denormalize.c
795
hashed_bit ^= FIELD_GET(BIT_ULL(18), ctx->ret_addr) & hash_ctl_64k;
drivers/ras/amd/atl/denormalize.c
796
hashed_bit ^= FIELD_GET(BIT_ULL(23), ctx->ret_addr) & hash_ctl_2M;
drivers/ras/amd/atl/denormalize.c
797
hashed_bit ^= FIELD_GET(BIT_ULL(32), ctx->ret_addr) & hash_ctl_1G;
drivers/ras/amd/atl/denormalize.c
806
hashed_bit ^= FIELD_GET(BIT_ULL(17), ctx->ret_addr) & hash_ctl_64k;
drivers/ras/amd/atl/denormalize.c
807
hashed_bit ^= FIELD_GET(BIT_ULL(22), ctx->ret_addr) & hash_ctl_2M;
drivers/ras/amd/atl/denormalize.c
808
hashed_bit ^= FIELD_GET(BIT_ULL(31), ctx->ret_addr) & hash_ctl_1G;
drivers/ras/amd/atl/denormalize.c
867
temp_addr_b |= FIELD_GET(BIT_ULL(9), addr);
drivers/ras/amd/atl/denormalize.c
889
temp_addr_b |= FIELD_GET(BIT_ULL(8), addr);
drivers/ras/amd/atl/denormalize.c
915
if (denorm_ctx->rehash_vector & BIT_ULL(8)) {
drivers/ras/amd/atl/denormalize.c
916
hashed_bit = FIELD_GET(BIT_ULL(8), denorm_ctx->current_spa);
drivers/ras/amd/atl/denormalize.c
917
hashed_bit ^= FIELD_GET(BIT_ULL(14), denorm_ctx->current_spa);
drivers/ras/amd/atl/denormalize.c
918
hashed_bit ^= FIELD_GET(BIT_ULL(16), denorm_ctx->current_spa) & hash_ctl_64k;
drivers/ras/amd/atl/denormalize.c
919
hashed_bit ^= FIELD_GET(BIT_ULL(21), denorm_ctx->current_spa) & hash_ctl_2M;
drivers/ras/amd/atl/denormalize.c
920
hashed_bit ^= FIELD_GET(BIT_ULL(30), denorm_ctx->current_spa) & hash_ctl_1G;
drivers/ras/amd/atl/denormalize.c
921
hashed_bit ^= FIELD_GET(BIT_ULL(40), denorm_ctx->current_spa) & hash_ctl_1T;
drivers/ras/amd/atl/denormalize.c
923
if (FIELD_GET(BIT_ULL(8), denorm_ctx->current_spa) != hashed_bit)
drivers/ras/amd/atl/denormalize.c
924
denorm_ctx->current_spa ^= BIT_ULL(8);
drivers/ras/amd/atl/denormalize.c
927
if (denorm_ctx->rehash_vector & BIT_ULL(9)) {
drivers/ras/amd/atl/denormalize.c
928
hashed_bit = FIELD_GET(BIT_ULL(9), denorm_ctx->current_spa);
drivers/ras/amd/atl/denormalize.c
929
hashed_bit ^= FIELD_GET(BIT_ULL(17), denorm_ctx->current_spa) & hash_ctl_64k;
drivers/ras/amd/atl/denormalize.c
930
hashed_bit ^= FIELD_GET(BIT_ULL(22), denorm_ctx->current_spa) & hash_ctl_2M;
drivers/ras/amd/atl/denormalize.c
931
hashed_bit ^= FIELD_GET(BIT_ULL(31), denorm_ctx->current_spa) & hash_ctl_1G;
drivers/ras/amd/atl/denormalize.c
932
hashed_bit ^= FIELD_GET(BIT_ULL(41), denorm_ctx->current_spa) & hash_ctl_1T;
drivers/ras/amd/atl/denormalize.c
934
if (FIELD_GET(BIT_ULL(9), denorm_ctx->current_spa) != hashed_bit)
drivers/ras/amd/atl/denormalize.c
935
denorm_ctx->current_spa ^= BIT_ULL(9);
drivers/ras/amd/atl/denormalize.c
938
if (denorm_ctx->rehash_vector & BIT_ULL(12)) {
drivers/ras/amd/atl/denormalize.c
939
hashed_bit = FIELD_GET(BIT_ULL(12), denorm_ctx->current_spa);
drivers/ras/amd/atl/denormalize.c
940
hashed_bit ^= FIELD_GET(BIT_ULL(18), denorm_ctx->current_spa) & hash_ctl_64k;
drivers/ras/amd/atl/denormalize.c
941
hashed_bit ^= FIELD_GET(BIT_ULL(23), denorm_ctx->current_spa) & hash_ctl_2M;
drivers/ras/amd/atl/denormalize.c
942
hashed_bit ^= FIELD_GET(BIT_ULL(32), denorm_ctx->current_spa) & hash_ctl_1G;
drivers/ras/amd/atl/denormalize.c
943
hashed_bit ^= FIELD_GET(BIT_ULL(42), denorm_ctx->current_spa) & hash_ctl_1T;
drivers/ras/amd/atl/denormalize.c
945
if (FIELD_GET(BIT_ULL(12), denorm_ctx->current_spa) != hashed_bit)
drivers/ras/amd/atl/denormalize.c
946
denorm_ctx->current_spa ^= BIT_ULL(12);
drivers/ras/amd/atl/denormalize.c
949
if (denorm_ctx->rehash_vector & BIT_ULL(13)) {
drivers/ras/amd/atl/denormalize.c
950
hashed_bit = FIELD_GET(BIT_ULL(13), denorm_ctx->current_spa);
drivers/ras/amd/atl/denormalize.c
951
hashed_bit ^= FIELD_GET(BIT_ULL(19), denorm_ctx->current_spa) & hash_ctl_64k;
drivers/ras/amd/atl/denormalize.c
952
hashed_bit ^= FIELD_GET(BIT_ULL(24), denorm_ctx->current_spa) & hash_ctl_2M;
drivers/ras/amd/atl/denormalize.c
953
hashed_bit ^= FIELD_GET(BIT_ULL(33), denorm_ctx->current_spa) & hash_ctl_1G;
drivers/ras/amd/atl/denormalize.c
954
hashed_bit ^= FIELD_GET(BIT_ULL(43), denorm_ctx->current_spa) & hash_ctl_1T;
drivers/ras/amd/atl/denormalize.c
956
if (FIELD_GET(BIT_ULL(13), denorm_ctx->current_spa) != hashed_bit)
drivers/ras/amd/atl/denormalize.c
957
denorm_ctx->current_spa ^= BIT_ULL(13);
drivers/ras/amd/fmpm.c
64
#define FMP_VALID_ARCH_TYPE BIT_ULL(0)
drivers/ras/amd/fmpm.c
65
#define FMP_VALID_ARCH BIT_ULL(1)
drivers/ras/amd/fmpm.c
66
#define FMP_VALID_ID_TYPE BIT_ULL(2)
drivers/ras/amd/fmpm.c
67
#define FMP_VALID_ID BIT_ULL(3)
drivers/ras/amd/fmpm.c
68
#define FMP_VALID_LIST_ENTRIES BIT_ULL(4)
drivers/ras/amd/fmpm.c
69
#define FMP_VALID_LIST BIT_ULL(5)
drivers/resctrl/mpam_devices.c
1060
return BIT_ULL(hweight_long(MSMON___LWD_VALUE));
drivers/resctrl/mpam_devices.c
1062
return BIT_ULL(hweight_long(MSMON___L_VALUE));
drivers/resctrl/mpam_devices.c
1064
return BIT_ULL(hweight_long(MSMON___VALUE));
drivers/soc/apple/rtkit.c
44
#define APPLE_RTKIT_MGMT_EPMAP_LAST BIT_ULL(51)
drivers/soc/apple/rtkit.c
48
#define APPLE_RTKIT_MGMT_EPMAP_REPLY_MORE BIT_ULL(0)
drivers/soc/apple/rtkit.c
51
#define APPLE_RTKIT_MGMT_STARTEP_FLAG BIT_ULL(1)
drivers/soc/hisilicon/kunpeng_hccs.h
81
#define HCCS_CAPS_HCCS_V2_PM BIT_ULL(0)
drivers/soc/tegra/ari-tegra186.c
17
#define SERR_STATUS_VAL BIT_ULL(63)
drivers/spi/spi-altera-dfl.c
29
#define SHIFT_MODE BIT_ULL(1)
drivers/spi/spi-altera-dfl.c
34
#define CLK_POLARITY BIT_ULL(14)
drivers/spi/spi-altera-dfl.c
35
#define CLK_PHASE BIT_ULL(15)
drivers/spi/spi-altera-dfl.c
41
#define INDIRECT_WR BIT_ULL(8)
drivers/spi/spi-altera-dfl.c
42
#define INDIRECT_RD BIT_ULL(9)
drivers/spi/spi-altera-dfl.c
45
#define INDIRECT_DEBUG BIT_ULL(32)
drivers/spi/spi-fsi.c
35
#define SPI_FSI_CLOCK_CFG_MM_ENABLE BIT_ULL(32)
drivers/spi/spi-fsi.c
36
#define SPI_FSI_CLOCK_CFG_ECC_DISABLE (BIT_ULL(35) | BIT_ULL(33))
drivers/spi/spi-fsi.c
37
#define SPI_FSI_CLOCK_CFG_RESET1 (BIT_ULL(36) | BIT_ULL(38))
drivers/spi/spi-fsi.c
38
#define SPI_FSI_CLOCK_CFG_RESET2 (BIT_ULL(37) | BIT_ULL(39))
drivers/spi/spi-fsi.c
39
#define SPI_FSI_CLOCK_CFG_MODE (BIT_ULL(41) | BIT_ULL(42))
drivers/spi/spi-fsi.c
41
#define SPI_FSI_CLOCK_CFG_SCK_NO_DEL BIT_ULL(51)
drivers/spi/spi-fsi.c
57
#define SPI_FSI_STATUS_SEQ_STATE_IDLE BIT_ULL(48)
drivers/spi/spi-fsi.c
58
#define SPI_FSI_STATUS_TDR_UNDERRUN BIT_ULL(57)
drivers/spi/spi-fsi.c
59
#define SPI_FSI_STATUS_TDR_OVERRUN BIT_ULL(58)
drivers/spi/spi-fsi.c
60
#define SPI_FSI_STATUS_TDR_FULL BIT_ULL(59)
drivers/spi/spi-fsi.c
61
#define SPI_FSI_STATUS_RDR_UNDERRUN BIT_ULL(61)
drivers/spi/spi-fsi.c
62
#define SPI_FSI_STATUS_RDR_OVERRUN BIT_ULL(62)
drivers/spi/spi-fsi.c
63
#define SPI_FSI_STATUS_RDR_FULL BIT_ULL(63)
drivers/staging/media/ipu7/ipu7-isys-csi2.c
309
if (streams_mask & BIT_ULL(i))
drivers/staging/media/ipu7/ipu7-isys-csi2.c
322
BIT_ULL(sink_stream));
drivers/staging/media/ipu7/ipu7-isys-csi2.c
346
if (streams_mask & BIT_ULL(i))
drivers/staging/media/ipu7/ipu7-isys-csi2.c
358
v4l2_subdev_disable_streams(r_sd, rp->index, BIT_ULL(sink_stream));
drivers/staging/media/ipu7/ipu7-isys-video.c
799
sd->name, r_pad->index, BIT_ULL(r_stream));
drivers/staging/media/ipu7/ipu7-isys-video.c
801
BIT_ULL(r_stream));
drivers/staging/media/ipu7/ipu7-isys-video.c
818
sd->name, r_pad->index, BIT_ULL(r_stream));
drivers/staging/media/ipu7/ipu7-isys-video.c
820
BIT_ULL(r_stream));
drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c
1002
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_PACKETS);
drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c
1005
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_PACKETS);
drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c
1007
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_FAILED);
drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c
2436
sinfo->filled = BIT_ULL(NL80211_STA_INFO_SIGNAL);
drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c
996
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL);
drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c
999
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
drivers/thermal/intel/int340x_thermal/processor_thermal_mbox.c
30
if (data & BIT_ULL(MBOX_BUSY_BIT)) {
drivers/thermal/intel/int340x_thermal/processor_thermal_mbox.c
54
reg_data = BIT_ULL(MBOX_BUSY_BIT) | id;
drivers/thermal/intel/int340x_thermal/processor_thermal_mbox.c
72
reg_data = BIT_ULL(MBOX_BUSY_BIT) | id;
drivers/thunderbolt/ctl.c
859
u64 route = tb_cfg_get_route(pkg->buffer) & ~BIT_ULL(63);
drivers/thunderbolt/dma_port.c
68
u64 route = tb_cfg_get_route(pkg->buffer) & ~BIT_ULL(63);
drivers/thunderbolt/xdomain.c
742
route = ((u64)xhdr->route_hi << 32 | xhdr->route_lo) & ~BIT_ULL(63);
drivers/usb/dwc3/dwc3-octeon.c
100
# define USBDRD_UCTL_CTL_USB2_PORT_PERM_ATTACH BIT_ULL(20)
drivers/usb/dwc3/dwc3-octeon.c
102
# define USBDRD_UCTL_CTL_USB3_PORT_DISABLE BIT_ULL(18)
drivers/usb/dwc3/dwc3-octeon.c
104
# define USBDRD_UCTL_CTL_USB2_PORT_DISABLE BIT_ULL(16)
drivers/usb/dwc3/dwc3-octeon.c
106
# define USBDRD_UCTL_CTL_SS_POWER_EN BIT_ULL(14)
drivers/usb/dwc3/dwc3-octeon.c
108
# define USBDRD_UCTL_CTL_HS_POWER_EN BIT_ULL(12)
drivers/usb/dwc3/dwc3-octeon.c
110
# define USBDRD_UCTL_CTL_CSCLK_EN BIT_ULL(4)
drivers/usb/dwc3/dwc3-octeon.c
112
# define USBDRD_UCTL_CTL_DRD_MODE BIT_ULL(3)
drivers/usb/dwc3/dwc3-octeon.c
114
# define USBDRD_UCTL_CTL_UPHY_RST BIT_ULL(2)
drivers/usb/dwc3/dwc3-octeon.c
116
# define USBDRD_UCTL_CTL_UAHC_RST BIT_ULL(1)
drivers/usb/dwc3/dwc3-octeon.c
118
# define USBDRD_UCTL_CTL_UCTL_RST BIT_ULL(0)
drivers/usb/dwc3/dwc3-octeon.c
137
# define USBDRD_UCTL_HOST_CFG_BME BIT_ULL(28)
drivers/usb/dwc3/dwc3-octeon.c
139
# define USBDRD_UCTL_HOST_OCI_EN BIT_ULL(27)
drivers/usb/dwc3/dwc3-octeon.c
144
# define USBDRD_UCTL_HOST_OCI_ACTIVE_HIGH_EN BIT_ULL(26)
drivers/usb/dwc3/dwc3-octeon.c
146
# define USBDRD_UCTL_HOST_PPC_EN BIT_ULL(25)
drivers/usb/dwc3/dwc3-octeon.c
151
# define USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN BIT_ULL(24)
drivers/usb/dwc3/dwc3-octeon.c
158
# define USBDRD_UCTL_SHIM_CFG_XS_NCB_OOB_WRN BIT_ULL(63)
drivers/usb/dwc3/dwc3-octeon.c
167
# define USBDRD_UCTL_SHIM_CFG_XM_BAD_DMA_WRN BIT_ULL(47)
drivers/usb/dwc3/dwc3-octeon.c
171
# define USBDRD_UCTL_SHIM_CFG_DMA_READ_CMD BIT_ULL(12)
drivers/usb/dwc3/dwc3-octeon.c
27
# define USBDRD_UCTL_CTL_CLEAR_BIST BIT_ULL(63)
drivers/usb/dwc3/dwc3-octeon.c
29
# define USBDRD_UCTL_CTL_START_BIST BIT_ULL(62)
drivers/usb/dwc3/dwc3-octeon.c
40
# define USBDRD_UCTL_CTL_SSC_EN BIT_ULL(59)
drivers/usb/dwc3/dwc3-octeon.c
63
# define USBDRD_UCTL_CTL_REF_SSP_EN BIT_ULL(39)
drivers/usb/dwc3/dwc3-octeon.c
71
# define USBDRD_UCTL_CTL_REF_CLK_DIV2 BIT_ULL(38)
drivers/usb/dwc3/dwc3-octeon.c
78
# define USBDRD_UCTL_CTL_H_CLK_EN BIT_ULL(30)
drivers/usb/dwc3/dwc3-octeon.c
83
# define USBDRD_UCTL_CTL_H_CLK_BYP_SEL BIT_ULL(29)
drivers/usb/dwc3/dwc3-octeon.c
85
# define USBDRD_UCTL_CTL_H_CLKDIV_RST BIT_ULL(28)
drivers/usb/dwc3/dwc3-octeon.c
98
# define USBDRD_UCTL_CTL_USB3_PORT_PERM_ATTACH BIT_ULL(21)
drivers/usb/host/xhci.h
1585
#define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
drivers/usb/host/xhci.h
1586
#define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */
drivers/usb/host/xhci.h
1587
#define XHCI_NEC_HOST BIT_ULL(2)
drivers/usb/host/xhci.h
1588
#define XHCI_AMD_PLL_FIX BIT_ULL(3)
drivers/usb/host/xhci.h
1589
#define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
drivers/usb/host/xhci.h
1599
#define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
drivers/usb/host/xhci.h
1600
#define XHCI_BROKEN_MSI BIT_ULL(6)
drivers/usb/host/xhci.h
1601
#define XHCI_RESET_ON_RESUME BIT_ULL(7)
drivers/usb/host/xhci.h
1602
#define XHCI_SW_BW_CHECKING BIT_ULL(8)
drivers/usb/host/xhci.h
1603
#define XHCI_AMD_0x96_HOST BIT_ULL(9)
drivers/usb/host/xhci.h
1604
#define XHCI_TRUST_TX_LENGTH BIT_ULL(10) /* Deprecated */
drivers/usb/host/xhci.h
1605
#define XHCI_LPM_SUPPORT BIT_ULL(11)
drivers/usb/host/xhci.h
1606
#define XHCI_INTEL_HOST BIT_ULL(12)
drivers/usb/host/xhci.h
1607
#define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
drivers/usb/host/xhci.h
1608
#define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
drivers/usb/host/xhci.h
1609
#define XHCI_AVOID_BEI BIT_ULL(15)
drivers/usb/host/xhci.h
1610
#define XHCI_PLAT BIT_ULL(16) /* Deprecated */
drivers/usb/host/xhci.h
1611
#define XHCI_SLOW_SUSPEND BIT_ULL(17)
drivers/usb/host/xhci.h
1612
#define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
drivers/usb/host/xhci.h
1614
#define XHCI_BROKEN_STREAMS BIT_ULL(19)
drivers/usb/host/xhci.h
1615
#define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
drivers/usb/host/xhci.h
1616
#define XHCI_MTK_HOST BIT_ULL(21)
drivers/usb/host/xhci.h
1617
#define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
drivers/usb/host/xhci.h
1618
#define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
drivers/usb/host/xhci.h
1619
#define XHCI_MISSING_CAS BIT_ULL(24)
drivers/usb/host/xhci.h
1621
#define XHCI_BROKEN_PORT_PED BIT_ULL(25)
drivers/usb/host/xhci.h
1622
#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
drivers/usb/host/xhci.h
1623
#define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
drivers/usb/host/xhci.h
1624
#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
drivers/usb/host/xhci.h
1625
#define XHCI_HW_LPM_DISABLE BIT_ULL(29)
drivers/usb/host/xhci.h
1626
#define XHCI_SUSPEND_DELAY BIT_ULL(30)
drivers/usb/host/xhci.h
1627
#define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
drivers/usb/host/xhci.h
1628
#define XHCI_ZERO_64B_REGS BIT_ULL(32)
drivers/usb/host/xhci.h
1629
#define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
drivers/usb/host/xhci.h
1630
#define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
drivers/usb/host/xhci.h
1631
#define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
drivers/usb/host/xhci.h
1633
#define XHCI_SKIP_PHY_INIT BIT_ULL(37)
drivers/usb/host/xhci.h
1634
#define XHCI_DISABLE_SPARSE BIT_ULL(38)
drivers/usb/host/xhci.h
1635
#define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39)
drivers/usb/host/xhci.h
1636
#define XHCI_NO_SOFT_RETRY BIT_ULL(40)
drivers/usb/host/xhci.h
1637
#define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41)
drivers/usb/host/xhci.h
1638
#define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42)
drivers/usb/host/xhci.h
1639
#define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43)
drivers/usb/host/xhci.h
1640
#define XHCI_RESET_TO_DEFAULT BIT_ULL(44)
drivers/usb/host/xhci.h
1641
#define XHCI_TRB_OVERFETCH BIT_ULL(45)
drivers/usb/host/xhci.h
1642
#define XHCI_ZHAOXIN_HOST BIT_ULL(46)
drivers/usb/host/xhci.h
1643
#define XHCI_WRITE_64_HI_LO BIT_ULL(47)
drivers/usb/host/xhci.h
1644
#define XHCI_CDNS_SCTX_QUIRK BIT_ULL(48)
drivers/usb/host/xhci.h
1645
#define XHCI_ETRON_HOST BIT_ULL(49)
drivers/usb/host/xhci.h
1646
#define XHCI_LIMIT_ENDPOINT_INTERVAL_9 BIT_ULL(50)
drivers/usb/typec/tipd/tps6598x.h
100
#define TPS_REG_INT_ERROR_POWER_EVENT_OCCURRED BIT_ULL(3+32)
drivers/usb/typec/tipd/tps6598x.h
101
#define TPS_REG_INT_ERROR_CAN_PROVIDE_PWR_LATER BIT_ULL(2+32)
drivers/usb/typec/tipd/tps6598x.h
102
#define TPS_REG_INT_ERROR_CANNOT_PROVIDE_PWR BIT_ULL(1+32)
drivers/usb/typec/tipd/tps6598x.h
103
#define TPS_REG_INT_ERROR_DEVICE_INCOMPATIBLE BIT_ULL(0+32)
drivers/usb/typec/tipd/tps6598x.h
86
#define TPS_REG_INT_USER_VID_ALT_MODE_OTHER_VDM BIT_ULL(27+32)
drivers/usb/typec/tipd/tps6598x.h
87
#define TPS_REG_INT_USER_VID_ALT_MODE_ATTN_VDM BIT_ULL(26+32)
drivers/usb/typec/tipd/tps6598x.h
88
#define TPS_REG_INT_USER_VID_ALT_MODE_EXIT BIT_ULL(25+32)
drivers/usb/typec/tipd/tps6598x.h
89
#define TPS_REG_INT_USER_VID_ALT_MODE_ENTERED BIT_ULL(24+32)
drivers/usb/typec/tipd/tps6598x.h
90
#define TPS_REG_INT_EXIT_MODES_COMPLETE BIT_ULL(20+32)
drivers/usb/typec/tipd/tps6598x.h
91
#define TPS_REG_INT_DISCOVER_MODES_COMPLETE BIT_ULL(19+32)
drivers/usb/typec/tipd/tps6598x.h
92
#define TPS_REG_INT_VDM_MSG_SENT BIT_ULL(18+32)
drivers/usb/typec/tipd/tps6598x.h
93
#define TPS_REG_INT_VDM_ENTERED_MODE BIT_ULL(17+32)
drivers/usb/typec/tipd/tps6598x.h
94
#define TPS_REG_INT_ERROR_UNABLE_TO_SOURCE BIT_ULL(14+32)
drivers/usb/typec/tipd/tps6598x.h
95
#define TPS_REG_INT_SRC_TRANSITION BIT_ULL(10+32)
drivers/usb/typec/tipd/tps6598x.h
96
#define TPS_REG_INT_ERROR_DISCHARGE_FAILED BIT_ULL(9+32)
drivers/usb/typec/tipd/tps6598x.h
97
#define TPS_REG_INT_ERROR_MESSAGE_DATA BIT_ULL(7+32)
drivers/usb/typec/tipd/tps6598x.h
98
#define TPS_REG_INT_ERROR_PROTOCOL_ERROR BIT_ULL(6+32)
drivers/usb/typec/tipd/tps6598x.h
99
#define TPS_REG_INT_ERROR_MISSING_GET_CAP_MESSAGE BIT_ULL(4+32)
drivers/usb/typec/ucsi/ucsi.h
158
#define UCSI_ENABLE_NTFY_CMD_COMPLETE BIT_ULL(16)
drivers/usb/typec/ucsi/ucsi.h
159
#define UCSI_ENABLE_NTFY_EXT_PWR_SRC_CHANGE BIT_ULL(17)
drivers/usb/typec/ucsi/ucsi.h
160
#define UCSI_ENABLE_NTFY_PWR_OPMODE_CHANGE BIT_ULL(18)
drivers/usb/typec/ucsi/ucsi.h
161
#define UCSI_ENABLE_NTFY_ATTENTION BIT_ULL(19)
drivers/usb/typec/ucsi/ucsi.h
162
#define UCSI_ENABLE_NTFY_LPM_FW_UPDATE_REQ BIT_ULL(20)
drivers/usb/typec/ucsi/ucsi.h
163
#define UCSI_ENABLE_NTFY_CAP_CHANGE BIT_ULL(21)
drivers/usb/typec/ucsi/ucsi.h
164
#define UCSI_ENABLE_NTFY_PWR_LEVEL_CHANGE BIT_ULL(22)
drivers/usb/typec/ucsi/ucsi.h
165
#define UCSI_ENABLE_NTFY_PD_RESET_COMPLETE BIT_ULL(23)
drivers/usb/typec/ucsi/ucsi.h
166
#define UCSI_ENABLE_NTFY_CAM_CHANGE BIT_ULL(24)
drivers/usb/typec/ucsi/ucsi.h
167
#define UCSI_ENABLE_NTFY_BAT_STATUS_CHANGE BIT_ULL(25)
drivers/usb/typec/ucsi/ucsi.h
168
#define UCSI_ENABLE_NTFY_SECURITY_REQ_PARTNER BIT_ULL(26)
drivers/usb/typec/ucsi/ucsi.h
169
#define UCSI_ENABLE_NTFY_PARTNER_CHANGE BIT_ULL(27)
drivers/usb/typec/ucsi/ucsi.h
170
#define UCSI_ENABLE_NTFY_PWR_DIR_CHANGE BIT_ULL(28)
drivers/usb/typec/ucsi/ucsi.h
171
#define UCSI_ENABLE_NTFY_SET_RETIMER_MODE BIT_ULL(29)
drivers/usb/typec/ucsi/ucsi.h
172
#define UCSI_ENABLE_NTFY_CONNECTOR_CHANGE BIT_ULL(30)
drivers/usb/typec/ucsi/ucsi.h
173
#define UCSI_ENABLE_NTFY_ERROR BIT_ULL(31)
drivers/usb/typec/ucsi/ucsi.h
174
#define UCSI_ENABLE_NTFY_SINK_PATH_STS_CHANGE BIT_ULL(32)
drivers/vdpa/alibaba/eni_vdpa.c
452
if (features & BIT_ULL(VIRTIO_NET_F_MQ)) {
drivers/vdpa/alibaba/eni_vdpa.c
463
if (features & BIT_ULL(VIRTIO_NET_F_CTRL_VQ))
drivers/vdpa/alibaba/eni_vdpa.c
66
features |= BIT_ULL(VIRTIO_F_ACCESS_PLATFORM);
drivers/vdpa/alibaba/eni_vdpa.c
67
features |= BIT_ULL(VIRTIO_F_ORDER_PLATFORM);
drivers/vdpa/alibaba/eni_vdpa.c
76
if (!(features & BIT_ULL(VIRTIO_NET_F_MRG_RXBUF)) && features) {
drivers/vdpa/ifcvf/ifcvf_base.c
253
if (!(features & BIT_ULL(VIRTIO_F_ACCESS_PLATFORM)) && features) {
drivers/vdpa/ifcvf/ifcvf_main.c
723
if (config->mask & BIT_ULL(VDPA_ATTR_DEV_FEATURES)) {
drivers/vdpa/mlx5/net/mlx5_vnet.c
1343
!!(ndev->mvdev.actual_features & BIT_ULL(VIRTIO_F_VERSION_1)));
drivers/vdpa/mlx5/net/mlx5_vnet.c
149
if (!(mvdev->actual_features & BIT_ULL(VIRTIO_NET_F_MQ))) {
drivers/vdpa/mlx5/net/mlx5_vnet.c
150
if (!(mvdev->actual_features & BIT_ULL(VIRTIO_NET_F_CTRL_VQ)))
drivers/vdpa/mlx5/net/mlx5_vnet.c
169
if (features & BIT_ULL(_feature)) \
drivers/vdpa/mlx5/net/mlx5_vnet.c
183
(mvdev->actual_features & BIT_ULL(VIRTIO_F_VERSION_1));
drivers/vdpa/mlx5/net/mlx5_vnet.c
1937
if (ndev->mvdev.actual_features & BIT_ULL(VIRTIO_NET_F_CTRL_VLAN)) {
drivers/vdpa/mlx5/net/mlx5_vnet.c
198
if (!(mvdev->actual_features & BIT_ULL(VIRTIO_NET_F_MQ)))
drivers/vdpa/mlx5/net/mlx5_vnet.c
2334
if (!(ndev->mvdev.actual_features & BIT_ULL(VIRTIO_NET_F_CTRL_VLAN)))
drivers/vdpa/mlx5/net/mlx5_vnet.c
2386
if (!(ndev->mvdev.actual_features & BIT_ULL(VIRTIO_NET_F_CTRL_VQ)))
drivers/vdpa/mlx5/net/mlx5_vnet.c
2676
if (dev_features & BIT_ULL(MLX5_VIRTIO_NET_F_MRG_RXBUF))
drivers/vdpa/mlx5/net/mlx5_vnet.c
2677
result |= BIT_ULL(VIRTIO_NET_F_MRG_RXBUF);
drivers/vdpa/mlx5/net/mlx5_vnet.c
2678
if (dev_features & BIT_ULL(MLX5_VIRTIO_NET_F_HOST_ECN))
drivers/vdpa/mlx5/net/mlx5_vnet.c
2679
result |= BIT_ULL(VIRTIO_NET_F_HOST_ECN);
drivers/vdpa/mlx5/net/mlx5_vnet.c
2680
if (dev_features & BIT_ULL(MLX5_VIRTIO_NET_F_GUEST_ECN))
drivers/vdpa/mlx5/net/mlx5_vnet.c
2681
result |= BIT_ULL(VIRTIO_NET_F_GUEST_ECN);
drivers/vdpa/mlx5/net/mlx5_vnet.c
2682
if (dev_features & BIT_ULL(MLX5_VIRTIO_NET_F_GUEST_TSO6))
drivers/vdpa/mlx5/net/mlx5_vnet.c
2683
result |= BIT_ULL(VIRTIO_NET_F_GUEST_TSO6);
drivers/vdpa/mlx5/net/mlx5_vnet.c
2684
if (dev_features & BIT_ULL(MLX5_VIRTIO_NET_F_GUEST_TSO4))
drivers/vdpa/mlx5/net/mlx5_vnet.c
2685
result |= BIT_ULL(VIRTIO_NET_F_GUEST_TSO4);
drivers/vdpa/mlx5/net/mlx5_vnet.c
2686
if (dev_features & BIT_ULL(MLX5_VIRTIO_NET_F_GUEST_CSUM))
drivers/vdpa/mlx5/net/mlx5_vnet.c
2687
result |= BIT_ULL(VIRTIO_NET_F_GUEST_CSUM);
drivers/vdpa/mlx5/net/mlx5_vnet.c
2688
if (dev_features & BIT_ULL(MLX5_VIRTIO_NET_F_CSUM))
drivers/vdpa/mlx5/net/mlx5_vnet.c
2689
result |= BIT_ULL(VIRTIO_NET_F_CSUM);
drivers/vdpa/mlx5/net/mlx5_vnet.c
2690
if (dev_features & BIT_ULL(MLX5_VIRTIO_NET_F_HOST_TSO6))
drivers/vdpa/mlx5/net/mlx5_vnet.c
2691
result |= BIT_ULL(VIRTIO_NET_F_HOST_TSO6);
drivers/vdpa/mlx5/net/mlx5_vnet.c
2692
if (dev_features & BIT_ULL(MLX5_VIRTIO_NET_F_HOST_TSO4))
drivers/vdpa/mlx5/net/mlx5_vnet.c
2693
result |= BIT_ULL(VIRTIO_NET_F_HOST_TSO4);
drivers/vdpa/mlx5/net/mlx5_vnet.c
2706
mlx_vdpa_features |= BIT_ULL(VIRTIO_F_VERSION_1);
drivers/vdpa/mlx5/net/mlx5_vnet.c
2707
mlx_vdpa_features |= BIT_ULL(VIRTIO_F_ACCESS_PLATFORM);
drivers/vdpa/mlx5/net/mlx5_vnet.c
2708
mlx_vdpa_features |= BIT_ULL(VIRTIO_NET_F_CTRL_VQ);
drivers/vdpa/mlx5/net/mlx5_vnet.c
2709
mlx_vdpa_features |= BIT_ULL(VIRTIO_NET_F_CTRL_MAC_ADDR);
drivers/vdpa/mlx5/net/mlx5_vnet.c
2710
mlx_vdpa_features |= BIT_ULL(VIRTIO_NET_F_MQ);
drivers/vdpa/mlx5/net/mlx5_vnet.c
2711
mlx_vdpa_features |= BIT_ULL(VIRTIO_NET_F_STATUS);
drivers/vdpa/mlx5/net/mlx5_vnet.c
2712
mlx_vdpa_features |= BIT_ULL(VIRTIO_NET_F_MTU);
drivers/vdpa/mlx5/net/mlx5_vnet.c
2713
mlx_vdpa_features |= BIT_ULL(VIRTIO_NET_F_CTRL_VLAN);
drivers/vdpa/mlx5/net/mlx5_vnet.c
2714
mlx_vdpa_features |= BIT_ULL(VIRTIO_NET_F_MAC);
drivers/vdpa/mlx5/net/mlx5_vnet.c
2731
if (!(features & BIT_ULL(VIRTIO_F_ACCESS_PLATFORM)))
drivers/vdpa/mlx5/net/mlx5_vnet.c
2743
if ((features & (BIT_ULL(VIRTIO_NET_F_MQ) | BIT_ULL(VIRTIO_NET_F_CTRL_VQ))) ==
drivers/vdpa/mlx5/net/mlx5_vnet.c
2744
BIT_ULL(VIRTIO_NET_F_MQ))
drivers/vdpa/mlx5/net/mlx5_vnet.c
2887
if (!(ndev->mvdev.actual_features & BIT_ULL(VIRTIO_NET_F_STATUS)))
drivers/vdpa/mlx5/net/mlx5_vnet.c
29
(BIT_ULL(VIRTIO_NET_F_CSUM) | BIT_ULL(VIRTIO_NET_F_GUEST_CSUM) | \
drivers/vdpa/mlx5/net/mlx5_vnet.c
2909
return BIT_ULL(VHOST_BACKEND_F_ENABLE_AFTER_DRIVER_OK);
drivers/vdpa/mlx5/net/mlx5_vnet.c
2941
#define NEEDS_TEARDOWN_MASK (BIT_ULL(VIRTIO_NET_F_MRG_RXBUF) | \
drivers/vdpa/mlx5/net/mlx5_vnet.c
2942
BIT_ULL(VIRTIO_NET_F_CSUM) | \
drivers/vdpa/mlx5/net/mlx5_vnet.c
2943
BIT_ULL(VIRTIO_F_VERSION_1))
drivers/vdpa/mlx5/net/mlx5_vnet.c
30
BIT_ULL(VIRTIO_NET_F_CTRL_GUEST_OFFLOADS) | BIT_ULL(VIRTIO_NET_F_MTU) | BIT_ULL(VIRTIO_NET_F_MAC) | \
drivers/vdpa/mlx5/net/mlx5_vnet.c
31
BIT_ULL(VIRTIO_NET_F_GUEST_TSO4) | BIT_ULL(VIRTIO_NET_F_GUEST_TSO6) | \
drivers/vdpa/mlx5/net/mlx5_vnet.c
3172
if (mvdev->actual_features & BIT_ULL(VIRTIO_NET_F_CTRL_VQ)) {
drivers/vdpa/mlx5/net/mlx5_vnet.c
32
BIT_ULL(VIRTIO_NET_F_GUEST_ECN) | BIT_ULL(VIRTIO_NET_F_GUEST_UFO) | BIT_ULL(VIRTIO_NET_F_HOST_TSO4) | \
drivers/vdpa/mlx5/net/mlx5_vnet.c
33
BIT_ULL(VIRTIO_NET_F_HOST_TSO6) | BIT_ULL(VIRTIO_NET_F_HOST_ECN) | BIT_ULL(VIRTIO_NET_F_HOST_UFO) | \
drivers/vdpa/mlx5/net/mlx5_vnet.c
34
BIT_ULL(VIRTIO_NET_F_MRG_RXBUF) | BIT_ULL(VIRTIO_NET_F_STATUS) | BIT_ULL(VIRTIO_NET_F_CTRL_VQ) | \
drivers/vdpa/mlx5/net/mlx5_vnet.c
35
BIT_ULL(VIRTIO_NET_F_CTRL_RX) | BIT_ULL(VIRTIO_NET_F_CTRL_VLAN) | \
drivers/vdpa/mlx5/net/mlx5_vnet.c
36
BIT_ULL(VIRTIO_NET_F_CTRL_RX_EXTRA) | BIT_ULL(VIRTIO_NET_F_GUEST_ANNOUNCE) | \
drivers/vdpa/mlx5/net/mlx5_vnet.c
3605
if (!(mvdev->actual_features & BIT_ULL(VIRTIO_NET_F_CTRL_VQ)))
drivers/vdpa/mlx5/net/mlx5_vnet.c
37
BIT_ULL(VIRTIO_NET_F_MQ) | BIT_ULL(VIRTIO_NET_F_CTRL_MAC_ADDR) | BIT_ULL(VIRTIO_NET_F_HASH_REPORT) | \
drivers/vdpa/mlx5/net/mlx5_vnet.c
38
BIT_ULL(VIRTIO_NET_F_RSS) | BIT_ULL(VIRTIO_NET_F_RSC_EXT) | BIT_ULL(VIRTIO_NET_F_STANDBY) | \
drivers/vdpa/mlx5/net/mlx5_vnet.c
3849
if (add_config->mask & BIT_ULL(VDPA_ATTR_DEV_FEATURES)) {
drivers/vdpa/mlx5/net/mlx5_vnet.c
3858
device_features &= ~BIT_ULL(VIRTIO_NET_F_MRG_RXBUF);
drivers/vdpa/mlx5/net/mlx5_vnet.c
3860
if (!(device_features & BIT_ULL(VIRTIO_F_VERSION_1) &&
drivers/vdpa/mlx5/net/mlx5_vnet.c
3861
device_features & BIT_ULL(VIRTIO_F_ACCESS_PLATFORM))) {
drivers/vdpa/mlx5/net/mlx5_vnet.c
3864
BIT_ULL(VIRTIO_F_VERSION_1) | BIT_ULL(VIRTIO_F_ACCESS_PLATFORM));
drivers/vdpa/mlx5/net/mlx5_vnet.c
3883
if (add_config->mask & BIT_ULL(VDPA_ATTR_DEV_NET_CFG_MAX_VQP)) {
drivers/vdpa/mlx5/net/mlx5_vnet.c
39
BIT_ULL(VIRTIO_NET_F_SPEED_DUPLEX) | BIT_ULL(VIRTIO_F_NOTIFY_ON_EMPTY) | \
drivers/vdpa/mlx5/net/mlx5_vnet.c
3901
(device_features & BIT_ULL(VIRTIO_F_VERSION_1));
drivers/vdpa/mlx5/net/mlx5_vnet.c
3918
if (add_config->mask & BIT_ULL(VDPA_ATTR_DEV_NET_CFG_MTU)) {
drivers/vdpa/mlx5/net/mlx5_vnet.c
3924
if (device_features & BIT_ULL(VIRTIO_NET_F_MTU)) {
drivers/vdpa/mlx5/net/mlx5_vnet.c
3932
if (device_features & BIT_ULL(VIRTIO_NET_F_STATUS)) {
drivers/vdpa/mlx5/net/mlx5_vnet.c
3942
} else if ((add_config->mask & BIT_ULL(VDPA_ATTR_DEV_FEATURES)) == 0 ||
drivers/vdpa/mlx5/net/mlx5_vnet.c
3943
device_features & BIT_ULL(VIRTIO_NET_F_MAC)) {
drivers/vdpa/mlx5/net/mlx5_vnet.c
3954
} else if ((add_config->mask & BIT_ULL(VDPA_ATTR_DEV_FEATURES)) == 0) {
drivers/vdpa/mlx5/net/mlx5_vnet.c
3961
device_features &= ~BIT_ULL(VIRTIO_NET_F_MAC);
drivers/vdpa/mlx5/net/mlx5_vnet.c
3962
} else if (device_features & BIT_ULL(VIRTIO_NET_F_MAC)) {
drivers/vdpa/mlx5/net/mlx5_vnet.c
3970
if (device_features & BIT_ULL(VIRTIO_NET_F_MQ)) {
drivers/vdpa/mlx5/net/mlx5_vnet.c
40
BIT_ULL(VIRTIO_F_ANY_LAYOUT) | BIT_ULL(VIRTIO_F_VERSION_1) | BIT_ULL(VIRTIO_F_ACCESS_PLATFORM) | \
drivers/vdpa/mlx5/net/mlx5_vnet.c
4068
if (add_config->mask & BIT_ULL(VDPA_ATTR_DEV_NET_CFG_MACADDR)) {
drivers/vdpa/mlx5/net/mlx5_vnet.c
4070
ndev->mvdev.mlx_features |= BIT_ULL(VIRTIO_NET_F_MAC);
drivers/vdpa/mlx5/net/mlx5_vnet.c
41
BIT_ULL(VIRTIO_F_RING_PACKED) | BIT_ULL(VIRTIO_F_ORDER_PLATFORM) | BIT_ULL(VIRTIO_F_SR_IOV))
drivers/vdpa/mlx5/net/mlx5_vnet.c
4113
mgtdev->mgtdev.config_attr_mask = BIT_ULL(VDPA_ATTR_DEV_NET_CFG_MACADDR) |
drivers/vdpa/mlx5/net/mlx5_vnet.c
4114
BIT_ULL(VDPA_ATTR_DEV_NET_CFG_MAX_VQP) |
drivers/vdpa/mlx5/net/mlx5_vnet.c
4115
BIT_ULL(VDPA_ATTR_DEV_NET_CFG_MTU) |
drivers/vdpa/mlx5/net/mlx5_vnet.c
4116
BIT_ULL(VDPA_ATTR_DEV_FEATURES);
drivers/vdpa/mlx5/net/mlx5_vnet.c
47
#define MLX5_FEATURE(_mvdev, _feature) (!!((_mvdev)->actual_features & BIT_ULL(_feature)))
drivers/vdpa/mlx5/net/mlx5_vnet.c
853
return (!!(features & BIT_ULL(VIRTIO_NET_F_MRG_RXBUF)) << MLX5_VIRTIO_NET_F_MRG_RXBUF) |
drivers/vdpa/mlx5/net/mlx5_vnet.c
854
(!!(features & BIT_ULL(VIRTIO_NET_F_HOST_ECN)) << MLX5_VIRTIO_NET_F_HOST_ECN) |
drivers/vdpa/mlx5/net/mlx5_vnet.c
855
(!!(features & BIT_ULL(VIRTIO_NET_F_GUEST_ECN)) << MLX5_VIRTIO_NET_F_GUEST_ECN) |
drivers/vdpa/mlx5/net/mlx5_vnet.c
856
(!!(features & BIT_ULL(VIRTIO_NET_F_GUEST_TSO6)) << MLX5_VIRTIO_NET_F_GUEST_TSO6) |
drivers/vdpa/mlx5/net/mlx5_vnet.c
857
(!!(features & BIT_ULL(VIRTIO_NET_F_GUEST_TSO4)) << MLX5_VIRTIO_NET_F_GUEST_TSO4) |
drivers/vdpa/mlx5/net/mlx5_vnet.c
858
(!!(features & BIT_ULL(VIRTIO_NET_F_CSUM)) << MLX5_VIRTIO_NET_F_CSUM) |
drivers/vdpa/mlx5/net/mlx5_vnet.c
859
(!!(features & BIT_ULL(VIRTIO_NET_F_HOST_TSO6)) << MLX5_VIRTIO_NET_F_HOST_TSO6) |
drivers/vdpa/mlx5/net/mlx5_vnet.c
860
(!!(features & BIT_ULL(VIRTIO_NET_F_HOST_TSO4)) << MLX5_VIRTIO_NET_F_HOST_TSO4);
drivers/vdpa/mlx5/net/mlx5_vnet.c
866
BIT_ULL(MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS);
drivers/vdpa/mlx5/net/mlx5_vnet.c
932
!!(features & BIT_ULL(VIRTIO_F_VERSION_1)));
drivers/vdpa/octeon_ep/octep_vdpa_hw.c
169
if (!(features & BIT_ULL(VIRTIO_F_VERSION_1)))
drivers/vdpa/octeon_ep/octep_vdpa_hw.c
172
if (!(features & BIT_ULL(VIRTIO_F_NOTIFICATION_DATA)))
drivers/vdpa/octeon_ep/octep_vdpa_hw.c
175
if (!(features & BIT_ULL(VIRTIO_F_RING_PACKED)))
drivers/vdpa/octeon_ep/octep_vdpa_hw.c
255
iowrite32(features & (BIT_ULL(32) - 1), &oct_hw->common_cfg->guest_feature);
drivers/vdpa/octeon_ep/octep_vdpa_main.c
156
BIT_ULL(VIRTIO_F_VERSION_1) | BIT_ULL(VIRTIO_F_NOTIFICATION_DATA) |
drivers/vdpa/octeon_ep/octep_vdpa_main.c
157
BIT_ULL(VIRTIO_F_RING_PACKED));
drivers/vdpa/octeon_ep/octep_vdpa_main.c
525
if (config->mask & BIT_ULL(VDPA_ATTR_DEV_FEATURES)) {
drivers/vdpa/octeon_ep/octep_vdpa_main.c
542
BIT_ULL(VIRTIO_F_VERSION_1) | BIT_ULL(VIRTIO_F_ACCESS_PLATFORM) |
drivers/vdpa/octeon_ep/octep_vdpa_main.c
543
BIT_ULL(VIRTIO_F_NOTIFICATION_DATA) | BIT_ULL(VIRTIO_F_RING_PACKED));
drivers/vdpa/pds/debugfs.c
102
case BIT_ULL(VIRTIO_NET_F_CTRL_VQ):
drivers/vdpa/pds/debugfs.c
105
case BIT_ULL(VIRTIO_NET_F_CTRL_RX):
drivers/vdpa/pds/debugfs.c
108
case BIT_ULL(VIRTIO_NET_F_CTRL_VLAN):
drivers/vdpa/pds/debugfs.c
111
case BIT_ULL(VIRTIO_NET_F_CTRL_RX_EXTRA):
drivers/vdpa/pds/debugfs.c
114
case BIT_ULL(VIRTIO_NET_F_GUEST_ANNOUNCE):
drivers/vdpa/pds/debugfs.c
117
case BIT_ULL(VIRTIO_NET_F_MQ):
drivers/vdpa/pds/debugfs.c
120
case BIT_ULL(VIRTIO_NET_F_CTRL_MAC_ADDR):
drivers/vdpa/pds/debugfs.c
123
case BIT_ULL(VIRTIO_NET_F_HASH_REPORT):
drivers/vdpa/pds/debugfs.c
126
case BIT_ULL(VIRTIO_NET_F_RSS):
drivers/vdpa/pds/debugfs.c
129
case BIT_ULL(VIRTIO_NET_F_RSC_EXT):
drivers/vdpa/pds/debugfs.c
132
case BIT_ULL(VIRTIO_NET_F_STANDBY):
drivers/vdpa/pds/debugfs.c
135
case BIT_ULL(VIRTIO_NET_F_SPEED_DUPLEX):
drivers/vdpa/pds/debugfs.c
138
case BIT_ULL(VIRTIO_F_NOTIFY_ON_EMPTY):
drivers/vdpa/pds/debugfs.c
141
case BIT_ULL(VIRTIO_F_ANY_LAYOUT):
drivers/vdpa/pds/debugfs.c
144
case BIT_ULL(VIRTIO_F_VERSION_1):
drivers/vdpa/pds/debugfs.c
147
case BIT_ULL(VIRTIO_F_ACCESS_PLATFORM):
drivers/vdpa/pds/debugfs.c
150
case BIT_ULL(VIRTIO_F_RING_PACKED):
drivers/vdpa/pds/debugfs.c
153
case BIT_ULL(VIRTIO_F_ORDER_PLATFORM):
drivers/vdpa/pds/debugfs.c
156
case BIT_ULL(VIRTIO_F_SR_IOV):
drivers/vdpa/pds/debugfs.c
54
u64 mask = BIT_ULL(i);
drivers/vdpa/pds/debugfs.c
57
case BIT_ULL(VIRTIO_NET_F_CSUM):
drivers/vdpa/pds/debugfs.c
60
case BIT_ULL(VIRTIO_NET_F_GUEST_CSUM):
drivers/vdpa/pds/debugfs.c
63
case BIT_ULL(VIRTIO_NET_F_CTRL_GUEST_OFFLOADS):
drivers/vdpa/pds/debugfs.c
66
case BIT_ULL(VIRTIO_NET_F_MTU):
drivers/vdpa/pds/debugfs.c
69
case BIT_ULL(VIRTIO_NET_F_MAC):
drivers/vdpa/pds/debugfs.c
72
case BIT_ULL(VIRTIO_NET_F_GUEST_TSO4):
drivers/vdpa/pds/debugfs.c
75
case BIT_ULL(VIRTIO_NET_F_GUEST_TSO6):
drivers/vdpa/pds/debugfs.c
78
case BIT_ULL(VIRTIO_NET_F_GUEST_ECN):
drivers/vdpa/pds/debugfs.c
81
case BIT_ULL(VIRTIO_NET_F_GUEST_UFO):
drivers/vdpa/pds/debugfs.c
84
case BIT_ULL(VIRTIO_NET_F_HOST_TSO4):
drivers/vdpa/pds/debugfs.c
87
case BIT_ULL(VIRTIO_NET_F_HOST_TSO6):
drivers/vdpa/pds/debugfs.c
90
case BIT_ULL(VIRTIO_NET_F_HOST_ECN):
drivers/vdpa/pds/debugfs.c
93
case BIT_ULL(VIRTIO_NET_F_HOST_UFO):
drivers/vdpa/pds/debugfs.c
96
case BIT_ULL(VIRTIO_NET_F_MRG_RXBUF):
drivers/vdpa/pds/debugfs.c
99
case BIT_ULL(VIRTIO_NET_F_STATUS):
drivers/vdpa/pds/vdpa_dev.c
140
if (driver_features & BIT_ULL(VIRTIO_F_RING_PACKED))
drivers/vdpa/pds/vdpa_dev.c
187
if (driver_features & BIT_ULL(VIRTIO_F_RING_PACKED)) {
drivers/vdpa/pds/vdpa_dev.c
240
if (driver_features & BIT_ULL(VIRTIO_F_RING_PACKED)) {
drivers/vdpa/pds/vdpa_dev.c
307
if (!(features & BIT_ULL(VIRTIO_F_ACCESS_PLATFORM)) && features) {
drivers/vdpa/pds/vdpa_dev.c
328
if (!(hw_features & BIT_ULL(VIRTIO_NET_F_MAC)))
drivers/vdpa/pds/vdpa_dev.c
329
nego_features &= ~BIT_ULL(VIRTIO_NET_F_MAC);
drivers/vdpa/pds/vdpa_dev.c
658
if (add_config->mask & BIT_ULL(VDPA_ATTR_DEV_FEATURES)) {
drivers/vdpa/pds/vdpa_dev.c
691
if (pdsv->supported_features & BIT_ULL(VIRTIO_NET_F_CTRL_VQ))
drivers/vdpa/pds/vdpa_dev.c
714
if (add_config->mask & BIT_ULL(VDPA_ATTR_DEV_NET_CFG_MACADDR)) {
drivers/vdpa/pds/vdpa_dev.c
722
(pdsv->supported_features & BIT_ULL(VIRTIO_NET_F_MAC))) {
drivers/vdpa/pds/vdpa_dev.c
852
mgmt->supported_features |= BIT_ULL(VIRTIO_NET_F_MAC);
drivers/vdpa/pds/vdpa_dev.c
854
mgmt->config_attr_mask = BIT_ULL(VDPA_ATTR_DEV_NET_CFG_MACADDR);
drivers/vdpa/pds/vdpa_dev.c
855
mgmt->config_attr_mask |= BIT_ULL(VDPA_ATTR_DEV_NET_CFG_MAX_VQP);
drivers/vdpa/pds/vdpa_dev.c
856
mgmt->config_attr_mask |= BIT_ULL(VDPA_ATTR_DEV_FEATURES);
drivers/vdpa/solidrun/snet_vdpa.h
22
#define SNET_HAS_FEATURE(s, f) ((s)->negotiated_features & BIT_ULL(f))
drivers/vdpa/vdpa.c
1010
if ((features & BIT_ULL(VIRTIO_BLK_F_MQ)) == 0)
drivers/vdpa/vdpa.c
1024
if ((features & BIT_ULL(VIRTIO_BLK_F_TOPOLOGY)) == 0)
drivers/vdpa/vdpa.c
1052
if ((features & BIT_ULL(VIRTIO_BLK_F_DISCARD)) == 0)
drivers/vdpa/vdpa.c
1076
if ((features & BIT_ULL(VIRTIO_BLK_F_WRITE_ZEROES)) == 0)
drivers/vdpa/vdpa.c
1094
ro = ((features & BIT_ULL(VIRTIO_BLK_F_RO)) == 0) ? 0 : 1;
drivers/vdpa/vdpa.c
1105
flush = ((features & BIT_ULL(VIRTIO_BLK_F_FLUSH)) == 0) ? 0 : 1;
drivers/vdpa/vdpa.c
1378
set_config.mask |= BIT_ULL(VDPA_ATTR_DEV_NET_CFG_MACADDR);
drivers/vdpa/vdpa.c
1427
if (classes & BIT_ULL(VIRTIO_ID_NET)) {
drivers/vdpa/vdpa.c
480
supported_classes |= BIT_ULL(mdev->id_table[i].device);
drivers/vdpa/vdpa.c
584
#define VDPA_DEV_NET_ATTRS_MASK (BIT_ULL(VDPA_ATTR_DEV_NET_CFG_MACADDR) | \
drivers/vdpa/vdpa.c
585
BIT_ULL(VDPA_ATTR_DEV_NET_CFG_MTU) | \
drivers/vdpa/vdpa.c
586
BIT_ULL(VDPA_ATTR_DEV_NET_CFG_MAX_VQP))
drivers/vdpa/vdpa.c
617
config.mask |= BIT_ULL(VDPA_ATTR_DEV_NET_CFG_MACADDR);
drivers/vdpa/vdpa.c
622
config.mask |= BIT_ULL(VDPA_ATTR_DEV_NET_CFG_MTU);
drivers/vdpa/vdpa.c
632
config.mask |= BIT_ULL(VDPA_ATTR_DEV_NET_CFG_MAX_VQP);
drivers/vdpa/vdpa.c
640
!(config.device_features & BIT_ULL(VIRTIO_NET_F_MAC)))
drivers/vdpa/vdpa.c
641
missing |= BIT_ULL(VIRTIO_NET_F_MAC);
drivers/vdpa/vdpa.c
643
!(config.device_features & BIT_ULL(VIRTIO_NET_F_MTU)))
drivers/vdpa/vdpa.c
644
missing |= BIT_ULL(VIRTIO_NET_F_MTU);
drivers/vdpa/vdpa.c
647
!(config.device_features & BIT_ULL(VIRTIO_NET_F_MQ)))
drivers/vdpa/vdpa.c
648
missing |= BIT_ULL(VIRTIO_NET_F_MQ);
drivers/vdpa/vdpa.c
655
config.mask |= BIT_ULL(VDPA_ATTR_DEV_FEATURES);
drivers/vdpa/vdpa.c
685
!(classes & BIT_ULL(VIRTIO_ID_NET))) {
drivers/vdpa/vdpa.c
692
config.mask & BIT_ULL(VDPA_ATTR_DEV_FEATURES) &&
drivers/vdpa/vdpa.c
693
classes & BIT_ULL(VIRTIO_ID_NET) && ncls > 1 &&
drivers/vdpa/vdpa.c
881
if ((features & BIT_ULL(VIRTIO_NET_F_MQ)) == 0 &&
drivers/vdpa/vdpa.c
882
(features & BIT_ULL(VIRTIO_NET_F_RSS)) == 0)
drivers/vdpa/vdpa.c
895
if ((features & BIT_ULL(VIRTIO_NET_F_MTU)) == 0)
drivers/vdpa/vdpa.c
906
if ((features & BIT_ULL(VIRTIO_NET_F_MAC)) == 0)
drivers/vdpa/vdpa.c
918
if ((features & BIT_ULL(VIRTIO_NET_F_STATUS)) == 0)
drivers/vdpa/vdpa.c
968
if ((features & BIT_ULL(VIRTIO_BLK_F_SIZE_MAX)) == 0)
drivers/vdpa/vdpa.c
983
if ((features & BIT_ULL(VIRTIO_BLK_F_BLK_SIZE)) == 0)
drivers/vdpa/vdpa.c
997
if ((features & BIT_ULL(VIRTIO_BLK_F_SEG_MAX)) == 0)
drivers/vdpa/vdpa_sim/vdpa_sim.c
205
if (config->mask & BIT_ULL(VDPA_ATTR_DEV_FEATURES)) {
drivers/vdpa/vdpa_sim/vdpa_sim.c
431
return BIT_ULL(VHOST_BACKEND_F_ENABLE_AFTER_DRIVER_OK);
drivers/vdpa/vdpa_user/vduse_dev.c
1478
if (dev->driver_features & BIT_ULL(VIRTIO_F_RING_PACKED)) {
drivers/vdpa/vdpa_user/vduse_dev.c
1924
if (!(config->features & BIT_ULL(VIRTIO_F_ACCESS_PLATFORM)))
drivers/vdpa/vdpa_user/vduse_dev.c
1929
(config->features & BIT_ULL(VIRTIO_BLK_F_CONFIG_WCE)))
drivers/vdpa/vdpa_user/vduse_dev.c
1932
(config->features & BIT_ULL(VIRTIO_NET_F_CTRL_VQ)))
drivers/vdpa/vdpa_user/vduse_dev.c
1936
!(config->features & BIT_ULL(VIRTIO_F_VERSION_1)))
drivers/vdpa/vdpa_user/vduse_dev.c
618
if (dev->driver_features & BIT_ULL(VIRTIO_F_RING_PACKED)) {
drivers/vdpa/vdpa_user/vduse_dev.c
694
if (dev->driver_features & BIT_ULL(VIRTIO_F_RING_PACKED))
drivers/vdpa/virtio_pci/vp_vdpa.c
304
BIT_ULL(VIRTIO_F_RING_PACKED))
drivers/vdpa/virtio_pci/vp_vdpa.c
529
if (add_config->mask & BIT_ULL(VDPA_ATTR_DEV_FEATURES)) {
drivers/vfio/pci/mlx5/main.c
25
#define MAX_LOAD_SIZE (BIT_ULL(__mlx5_bit_sz(load_vhca_state_in, size)) - 1)
drivers/vfio/pci/mlx5/main.c
406
(BIT_ULL(__mlx5_bit_sz(save_vhca_state_in, size)) - PAGE_SIZE));
drivers/vfio/pci/virtio/migrate.c
23
#define MAX_LOAD_SIZE (BIT_ULL(BITS_PER_TYPE \
drivers/vhost/vdpa.c
460
vhost_vdpa_get_backend_features(v) & BIT_ULL(VHOST_BACKEND_F_IOTLB_PERSIST);
drivers/vhost/vdpa.c
790
BIT_ULL(VHOST_BACKEND_F_DESC_ASID) |
drivers/vhost/vdpa.c
791
BIT_ULL(VHOST_BACKEND_F_IOTLB_PERSIST) |
drivers/vhost/vdpa.c
792
BIT_ULL(VHOST_BACKEND_F_SUSPEND) |
drivers/vhost/vdpa.c
793
BIT_ULL(VHOST_BACKEND_F_RESUME) |
drivers/vhost/vdpa.c
794
BIT_ULL(VHOST_BACKEND_F_ENABLE_AFTER_DRIVER_OK)))
drivers/vhost/vdpa.c
796
if ((features & BIT_ULL(VHOST_BACKEND_F_SUSPEND)) &&
drivers/vhost/vdpa.c
799
if ((features & BIT_ULL(VHOST_BACKEND_F_RESUME)) &&
drivers/vhost/vdpa.c
802
if ((features & BIT_ULL(VHOST_BACKEND_F_DESC_ASID)) &&
drivers/vhost/vdpa.c
803
!(features & BIT_ULL(VHOST_BACKEND_F_IOTLB_ASID)))
drivers/vhost/vdpa.c
805
if ((features & BIT_ULL(VHOST_BACKEND_F_DESC_ASID)) &&
drivers/vhost/vdpa.c
808
if ((features & BIT_ULL(VHOST_BACKEND_F_IOTLB_PERSIST)) &&
drivers/vhost/vdpa.c
861
features |= BIT_ULL(VHOST_BACKEND_F_SUSPEND);
drivers/vhost/vdpa.c
863
features |= BIT_ULL(VHOST_BACKEND_F_RESUME);
drivers/vhost/vdpa.c
865
features |= BIT_ULL(VHOST_BACKEND_F_DESC_ASID);
drivers/vhost/vdpa.c
867
features |= BIT_ULL(VHOST_BACKEND_F_IOTLB_PERSIST);
drivers/virtio/virtio_pci_common.h
167
(BIT_ULL(VIRTIO_ADMIN_CMD_LEGACY_COMMON_CFG_WRITE) | \
drivers/virtio/virtio_pci_common.h
168
BIT_ULL(VIRTIO_ADMIN_CMD_LEGACY_COMMON_CFG_READ) | \
drivers/virtio/virtio_pci_common.h
169
BIT_ULL(VIRTIO_ADMIN_CMD_LEGACY_DEV_CFG_WRITE) | \
drivers/virtio/virtio_pci_common.h
170
BIT_ULL(VIRTIO_ADMIN_CMD_LEGACY_DEV_CFG_READ) | \
drivers/virtio/virtio_pci_common.h
171
BIT_ULL(VIRTIO_ADMIN_CMD_LEGACY_NOTIFY_INFO))
drivers/virtio/virtio_pci_common.h
174
(BIT_ULL(VIRTIO_ADMIN_CMD_CAP_ID_LIST_QUERY) | \
drivers/virtio/virtio_pci_common.h
175
BIT_ULL(VIRTIO_ADMIN_CMD_DRIVER_CAP_SET) | \
drivers/virtio/virtio_pci_common.h
176
BIT_ULL(VIRTIO_ADMIN_CMD_DEVICE_CAP_GET) | \
drivers/virtio/virtio_pci_common.h
177
BIT_ULL(VIRTIO_ADMIN_CMD_RESOURCE_OBJ_CREATE) | \
drivers/virtio/virtio_pci_common.h
178
BIT_ULL(VIRTIO_ADMIN_CMD_RESOURCE_OBJ_DESTROY) | \
drivers/virtio/virtio_pci_common.h
179
BIT_ULL(VIRTIO_ADMIN_CMD_DEV_PARTS_METADATA_GET) | \
drivers/virtio/virtio_pci_common.h
180
BIT_ULL(VIRTIO_ADMIN_CMD_DEV_PARTS_GET) | \
drivers/virtio/virtio_pci_common.h
181
BIT_ULL(VIRTIO_ADMIN_CMD_DEV_PARTS_SET) | \
drivers/virtio/virtio_pci_common.h
182
BIT_ULL(VIRTIO_ADMIN_CMD_DEV_MODE_SET))
drivers/virtio/virtio_pci_modern.c
372
if ((features & BIT_ULL(VIRTIO_F_SR_IOV)) &&
drivers/virtio/virtio_pci_modern.c
376
if (features & BIT_ULL(VIRTIO_F_RING_RESET))
drivers/virtio/virtio_pci_modern.c
379
if (features & BIT_ULL(VIRTIO_F_ADMIN_VQ))
drivers/watchdog/marvell_gti_wdt.c
48
#define GTI_CWD_INT_PENDING_STATUS(bit) BIT_ULL(bit)
drivers/watchdog/marvell_gti_wdt.c
52
#define GTI_CWD_INT_ENA_CLR_VAL(bit) BIT_ULL(bit)
drivers/watchdog/marvell_gti_wdt.c
56
#define GTI_CWD_INT_ENA_SET_VAL(bit) BIT_ULL(bit)
fs/erofs/data.c
144
BIT_ULL(48) - 1 : BIT_ULL(32) - 1;
fs/erofs/erofs_fs.h
278
#define EROFS_DIRENT_NID_MASK (BIT_ULL(EROFS_DIRENT_NID_METABOX_BIT) - 1)
fs/erofs/inode.c
129
addrmask = BIT_ULL(32) - 1;
fs/erofs/inode.c
44
erofs_blk_t addrmask = BIT_ULL(48) - 1;
fs/erofs/internal.h
330
return EROFS_I(inode)->nid & BIT_ULL(EROFS_DIRENT_NID_METABOX_BIT);
fs/erofs/super.c
336
if (sbi->metabox_nid & BIT_ULL(EROFS_DIRENT_NID_METABOX_BIT))
fs/erofs/zmap.c
735
(pend >> sbi->blkszbits) >= BIT_ULL(48)))
fs/proc/task_mmu.c
1864
#define PM_SOFT_DIRTY BIT_ULL(55)
fs/proc/task_mmu.c
1865
#define PM_MMAP_EXCLUSIVE BIT_ULL(56)
fs/proc/task_mmu.c
1866
#define PM_UFFD_WP BIT_ULL(57)
fs/proc/task_mmu.c
1867
#define PM_GUARD_REGION BIT_ULL(58)
fs/proc/task_mmu.c
1868
#define PM_FILE BIT_ULL(61)
fs/proc/task_mmu.c
1869
#define PM_SWAP BIT_ULL(62)
fs/proc/task_mmu.c
1870
#define PM_PRESENT BIT_ULL(63)
include/cxl/event.h
202
#define PROT_ERR_VALID_AGENT_TYPE BIT_ULL(0)
include/cxl/event.h
203
#define PROT_ERR_VALID_AGENT_ADDRESS BIT_ULL(1)
include/cxl/event.h
204
#define PROT_ERR_VALID_DEVICE_ID BIT_ULL(2)
include/cxl/event.h
205
#define PROT_ERR_VALID_SERIAL_NUMBER BIT_ULL(3)
include/cxl/event.h
206
#define PROT_ERR_VALID_CAPABILITY BIT_ULL(4)
include/cxl/event.h
207
#define PROT_ERR_VALID_DVSEC BIT_ULL(5)
include/cxl/event.h
208
#define PROT_ERR_VALID_ERROR_LOG BIT_ULL(6)
include/hyperv/hvgdk_mini.h
185
#define HV_EXPOSE_INVARIANT_TSC BIT_ULL(0)
include/hyperv/hvgdk_mini.h
194
#define HV_CRASH_CTL_CRASH_NOTIFY_MSG BIT_ULL(62)
include/hyperv/hvgdk_mini.h
195
#define HV_CRASH_CTL_CRASH_NOTIFY BIT_ULL(63)
include/hyperv/hvgdk_mini.h
512
#define HV_HYPERCALL_NESTED BIT_ULL(31)
include/hyperv/hvgdk_mini.h
514
#define HV_HYPERCALL_REP_COMP_1 BIT_ULL(32)
include/linux/avf/virtchnl.h
336
#define VIRTCHNL_RXDID_BIT(x) BIT_ULL(VIRTCHNL_RXDID_##x)
include/linux/bits.h
71
#define BIT_TYPE(type, nr) ((type)(BIT_INPUT_CHECK(type, nr) + BIT_ULL(nr)))
include/linux/capability.h
57
# define CAP_FS_MASK (BIT_ULL(CAP_CHOWN) \
include/linux/capability.h
58
| BIT_ULL(CAP_MKNOD) \
include/linux/capability.h
59
| BIT_ULL(CAP_DAC_OVERRIDE) \
include/linux/capability.h
60
| BIT_ULL(CAP_DAC_READ_SEARCH) \
include/linux/capability.h
61
| BIT_ULL(CAP_FOWNER) \
include/linux/capability.h
62
| BIT_ULL(CAP_FSETID) \
include/linux/capability.h
63
| BIT_ULL(CAP_MAC_OVERRIDE))
include/linux/capability.h
64
#define CAP_VALID_MASK (BIT_ULL(CAP_LAST_CAP+1)-1)
include/linux/capability.h
68
# define CAP_FS_SET ((kernel_cap_t) { CAP_FS_MASK | BIT_ULL(CAP_LINUX_IMMUTABLE) })
include/linux/capability.h
69
# define CAP_NFSD_SET ((kernel_cap_t) { CAP_FS_MASK | BIT_ULL(CAP_SYS_RESOURCE) })
include/linux/capability.h
73
#define cap_raise(c, flag) ((c).val |= BIT_ULL(flag))
include/linux/capability.h
74
#define cap_lower(c, flag) ((c).val &= ~BIT_ULL(flag))
include/linux/capability.h
75
#define cap_raised(c, flag) (((c).val & BIT_ULL(flag)) != 0)
include/linux/dim.h
39
#define BIT_GAP(bits, end, start) ((((end) - (start)) + BIT_ULL(bits)) \
include/linux/dim.h
40
& (BIT_ULL(bits) - 1))
include/linux/efi.h
117
#define EFI_MEMORY_UC BIT_ULL(0) /* uncached */
include/linux/efi.h
118
#define EFI_MEMORY_WC BIT_ULL(1) /* write-coalescing */
include/linux/efi.h
119
#define EFI_MEMORY_WT BIT_ULL(2) /* write-through */
include/linux/efi.h
120
#define EFI_MEMORY_WB BIT_ULL(3) /* write-back */
include/linux/efi.h
121
#define EFI_MEMORY_UCE BIT_ULL(4) /* uncached, exported */
include/linux/efi.h
122
#define EFI_MEMORY_WP BIT_ULL(12) /* write-protect */
include/linux/efi.h
123
#define EFI_MEMORY_RP BIT_ULL(13) /* read-protect */
include/linux/efi.h
124
#define EFI_MEMORY_XP BIT_ULL(14) /* execute-protect */
include/linux/efi.h
125
#define EFI_MEMORY_NV BIT_ULL(15) /* non-volatile */
include/linux/efi.h
126
#define EFI_MEMORY_MORE_RELIABLE BIT_ULL(16) /* higher reliability */
include/linux/efi.h
127
#define EFI_MEMORY_RO BIT_ULL(17) /* read-only */
include/linux/efi.h
128
#define EFI_MEMORY_SP BIT_ULL(18) /* soft reserved */
include/linux/efi.h
129
#define EFI_MEMORY_CPU_CRYPTO BIT_ULL(19) /* supports encryption */
include/linux/efi.h
130
#define EFI_MEMORY_HOT_PLUGGABLE BIT_ULL(20) /* supports unplugging at runtime */
include/linux/efi.h
131
#define EFI_MEMORY_RUNTIME BIT_ULL(63) /* range requires runtime mapping */
include/linux/i3c/device.h
91
#define I3C_PID_RND_LOWER_32BITS(pid) (!!((pid) & BIT_ULL(32)))
include/linux/io_uring_types.h
554
#define IO_REQ_FLAG(bitno) ((__force io_req_flags_t) BIT_ULL((bitno)))
include/linux/irqchip/arm-gic-v3.h
225
#define GICR_PENDBASER_PTZ BIT_ULL(62)
include/linux/irqchip/arm-gic-v5.h
148
#define GICV5_IRS_IST_BASER_VALID BIT_ULL(0)
include/linux/irqchip/arm-gic-v5.h
152
#define GICV5_ISTL1E_VALID BIT_ULL(0)
include/linux/irqchip/arm-gic-v5.h
214
#define GICV5_ITS_SYNCR_SYNC BIT_ULL(63)
include/linux/irqchip/arm-gic-v5.h
215
#define GICV5_ITS_SYNCR_SYNCALL BIT_ULL(32)
include/linux/irqchip/arm-gic-v5.h
220
#define GICV5_DTL1E_VALID BIT_ULL(0)
include/linux/irqchip/arm-gic-v5.h
225
#define GICV5_DTL2E_VALID BIT_ULL(0)
include/linux/irqchip/arm-gic-v5.h
229
#define GICV5_DTL2E_ITT_DSWE BIT_ULL(57)
include/linux/irqchip/arm-gic-v5.h
230
#define GICV5_DTL2E_ITT_STRUCTURE BIT_ULL(58)
include/linux/irqchip/arm-gic-v5.h
233
#define GICV5_ITTL1E_VALID BIT_ULL(0)
include/linux/irqchip/arm-gic-v5.h
240
#define GICV5_ITTL2E_VIRTUAL BIT_ULL(30)
include/linux/irqchip/arm-gic-v5.h
241
#define GICV5_ITTL2E_VALID BIT_ULL(31)
include/linux/kvm_host.h
79
#define KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS BIT_ULL(63)
include/linux/libata.h
100
ATA_QUIRK_BRIDGE_OK = BIT_ULL(__ATA_QUIRK_BRIDGE_OK),
include/linux/libata.h
101
ATA_QUIRK_ATAPI_MOD16_DMA = BIT_ULL(__ATA_QUIRK_ATAPI_MOD16_DMA),
include/linux/libata.h
102
ATA_QUIRK_FIRMWARE_WARN = BIT_ULL(__ATA_QUIRK_FIRMWARE_WARN),
include/linux/libata.h
103
ATA_QUIRK_1_5_GBPS = BIT_ULL(__ATA_QUIRK_1_5_GBPS),
include/linux/libata.h
104
ATA_QUIRK_NOSETXFER = BIT_ULL(__ATA_QUIRK_NOSETXFER),
include/linux/libata.h
105
ATA_QUIRK_BROKEN_FPDMA_AA = BIT_ULL(__ATA_QUIRK_BROKEN_FPDMA_AA),
include/linux/libata.h
106
ATA_QUIRK_DUMP_ID = BIT_ULL(__ATA_QUIRK_DUMP_ID),
include/linux/libata.h
107
ATA_QUIRK_MAX_SEC_LBA48 = BIT_ULL(__ATA_QUIRK_MAX_SEC_LBA48),
include/linux/libata.h
108
ATA_QUIRK_ATAPI_DMADIR = BIT_ULL(__ATA_QUIRK_ATAPI_DMADIR),
include/linux/libata.h
109
ATA_QUIRK_NO_NCQ_TRIM = BIT_ULL(__ATA_QUIRK_NO_NCQ_TRIM),
include/linux/libata.h
110
ATA_QUIRK_NOLPM = BIT_ULL(__ATA_QUIRK_NOLPM),
include/linux/libata.h
111
ATA_QUIRK_WD_BROKEN_LPM = BIT_ULL(__ATA_QUIRK_WD_BROKEN_LPM),
include/linux/libata.h
112
ATA_QUIRK_ZERO_AFTER_TRIM = BIT_ULL(__ATA_QUIRK_ZERO_AFTER_TRIM),
include/linux/libata.h
113
ATA_QUIRK_NO_DMA_LOG = BIT_ULL(__ATA_QUIRK_NO_DMA_LOG),
include/linux/libata.h
114
ATA_QUIRK_NOTRIM = BIT_ULL(__ATA_QUIRK_NOTRIM),
include/linux/libata.h
115
ATA_QUIRK_MAX_SEC = BIT_ULL(__ATA_QUIRK_MAX_SEC),
include/linux/libata.h
116
ATA_QUIRK_MAX_TRIM_128M = BIT_ULL(__ATA_QUIRK_MAX_TRIM_128M),
include/linux/libata.h
117
ATA_QUIRK_NO_NCQ_ON_ATI = BIT_ULL(__ATA_QUIRK_NO_NCQ_ON_ATI),
include/linux/libata.h
118
ATA_QUIRK_NO_LPM_ON_ATI = BIT_ULL(__ATA_QUIRK_NO_LPM_ON_ATI),
include/linux/libata.h
119
ATA_QUIRK_NO_ID_DEV_LOG = BIT_ULL(__ATA_QUIRK_NO_ID_DEV_LOG),
include/linux/libata.h
120
ATA_QUIRK_NO_LOG_DIR = BIT_ULL(__ATA_QUIRK_NO_LOG_DIR),
include/linux/libata.h
121
ATA_QUIRK_NO_FUA = BIT_ULL(__ATA_QUIRK_NO_FUA),
include/linux/libata.h
92
ATA_QUIRK_DIAGNOSTIC = BIT_ULL(__ATA_QUIRK_DIAGNOSTIC),
include/linux/libata.h
93
ATA_QUIRK_NODMA = BIT_ULL(__ATA_QUIRK_NODMA),
include/linux/libata.h
94
ATA_QUIRK_NONCQ = BIT_ULL(__ATA_QUIRK_NONCQ),
include/linux/libata.h
95
ATA_QUIRK_BROKEN_HPA = BIT_ULL(__ATA_QUIRK_BROKEN_HPA),
include/linux/libata.h
96
ATA_QUIRK_DISABLE = BIT_ULL(__ATA_QUIRK_DISABLE),
include/linux/libata.h
97
ATA_QUIRK_HPA_SIZE = BIT_ULL(__ATA_QUIRK_HPA_SIZE),
include/linux/libata.h
98
ATA_QUIRK_IVB = BIT_ULL(__ATA_QUIRK_IVB),
include/linux/libata.h
99
ATA_QUIRK_STUCK_ERR = BIT_ULL(__ATA_QUIRK_STUCK_ERR),
include/linux/mlx5/mlx5_ifc.h
12779
BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY),
include/linux/mlx5/mlx5_ifc.h
12781
BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_IPSEC),
include/linux/mlx5/mlx5_ifc.h
12783
BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_SAMPLER),
include/linux/mlx5/mlx5_ifc.h
12785
BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO),
include/linux/mlx5/mlx5_ifc.h
12790
BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL - 0x40),
include/linux/mlx5/mlx5_ifc.h
12792
BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT - 0x40),
include/linux/netdevice.h
1762
IFF_NO_ADDRCONF = BIT_ULL(30),
include/linux/netdevice.h
1763
IFF_TX_SKB_NO_LINEAR = BIT_ULL(31),
include/linux/nfs_xdr.h
100
#define NFS_ATTR_FATTR_PRECTIME BIT_ULL(16)
include/linux/nfs_xdr.h
101
#define NFS_ATTR_FATTR_CHANGE BIT_ULL(17)
include/linux/nfs_xdr.h
102
#define NFS_ATTR_FATTR_PRECHANGE BIT_ULL(18)
include/linux/nfs_xdr.h
103
#define NFS_ATTR_FATTR_V4_LOCATIONS BIT_ULL(19)
include/linux/nfs_xdr.h
104
#define NFS_ATTR_FATTR_V4_REFERRAL BIT_ULL(20)
include/linux/nfs_xdr.h
105
#define NFS_ATTR_FATTR_MOUNTPOINT BIT_ULL(21)
include/linux/nfs_xdr.h
106
#define NFS_ATTR_FATTR_MOUNTED_ON_FILEID BIT_ULL(22)
include/linux/nfs_xdr.h
107
#define NFS_ATTR_FATTR_OWNER_NAME BIT_ULL(23)
include/linux/nfs_xdr.h
108
#define NFS_ATTR_FATTR_GROUP_NAME BIT_ULL(24)
include/linux/nfs_xdr.h
109
#define NFS_ATTR_FATTR_V4_SECURITY_LABEL BIT_ULL(25)
include/linux/nfs_xdr.h
110
#define NFS_ATTR_FATTR_BTIME BIT_ULL(26)
include/linux/nfs_xdr.h
84
#define NFS_ATTR_FATTR_TYPE BIT_ULL(0)
include/linux/nfs_xdr.h
85
#define NFS_ATTR_FATTR_MODE BIT_ULL(1)
include/linux/nfs_xdr.h
86
#define NFS_ATTR_FATTR_NLINK BIT_ULL(2)
include/linux/nfs_xdr.h
87
#define NFS_ATTR_FATTR_OWNER BIT_ULL(3)
include/linux/nfs_xdr.h
88
#define NFS_ATTR_FATTR_GROUP BIT_ULL(4)
include/linux/nfs_xdr.h
89
#define NFS_ATTR_FATTR_RDEV BIT_ULL(5)
include/linux/nfs_xdr.h
90
#define NFS_ATTR_FATTR_SIZE BIT_ULL(6)
include/linux/nfs_xdr.h
91
#define NFS_ATTR_FATTR_PRESIZE BIT_ULL(7)
include/linux/nfs_xdr.h
92
#define NFS_ATTR_FATTR_BLOCKS_USED BIT_ULL(8)
include/linux/nfs_xdr.h
93
#define NFS_ATTR_FATTR_SPACE_USED BIT_ULL(9)
include/linux/nfs_xdr.h
94
#define NFS_ATTR_FATTR_FSID BIT_ULL(10)
include/linux/nfs_xdr.h
95
#define NFS_ATTR_FATTR_FILEID BIT_ULL(11)
include/linux/nfs_xdr.h
96
#define NFS_ATTR_FATTR_ATIME BIT_ULL(12)
include/linux/nfs_xdr.h
97
#define NFS_ATTR_FATTR_MTIME BIT_ULL(13)
include/linux/nfs_xdr.h
98
#define NFS_ATTR_FATTR_CTIME BIT_ULL(14)
include/linux/nfs_xdr.h
99
#define NFS_ATTR_FATTR_PREMTIME BIT_ULL(15)
include/linux/ntb.h
828
if (!(ntb_link_is_up(ntb, NULL, NULL) & BIT_ULL(pidx)))
include/linux/pds/pds_common.h
13
#define PDS_CORE_ADDR_MASK (BIT_ULL(PDS_ADDR_LEN) - 1)
include/linux/perf/arm_pmuv3.h
231
#define ARMV8_PMU_OVSR_F BIT_ULL(32) /* arm64 only */
include/linux/platform_data/cros_ec_commands.h
576
#define EC_HOST_EVENT_MASK(event_code) BIT_ULL((event_code) - 1)
include/linux/psp-sev.h
30
#define SNP_POLICY_MASK_SMT BIT_ULL(16)
include/linux/psp-sev.h
31
#define SNP_POLICY_MASK_RSVD_MBO BIT_ULL(17)
include/linux/psp-sev.h
32
#define SNP_POLICY_MASK_MIGRATE_MA BIT_ULL(18)
include/linux/psp-sev.h
33
#define SNP_POLICY_MASK_DEBUG BIT_ULL(19)
include/linux/psp-sev.h
34
#define SNP_POLICY_MASK_SINGLE_SOCKET BIT_ULL(20)
include/linux/psp-sev.h
35
#define SNP_POLICY_MASK_CXL_ALLOW BIT_ULL(21)
include/linux/psp-sev.h
36
#define SNP_POLICY_MASK_MEM_AES_256_XTS BIT_ULL(22)
include/linux/psp-sev.h
37
#define SNP_POLICY_MASK_RAPL_DIS BIT_ULL(23)
include/linux/psp-sev.h
38
#define SNP_POLICY_MASK_CIPHERTEXT_HIDING_DRAM BIT_ULL(24)
include/linux/psp-sev.h
39
#define SNP_POLICY_MASK_PAGE_SWAP_DISABLE BIT_ULL(25)
include/linux/serial_core.h
529
#define UPF_NO_THRE_TEST ((__force upf_t) BIT_ULL(19))
include/linux/serial_core.h
531
#define UPF_AUTO_CTS ((__force upf_t) BIT_ULL(20))
include/linux/serial_core.h
532
#define UPF_AUTO_RTS ((__force upf_t) BIT_ULL(21))
include/linux/serial_core.h
535
#define UPF_SOFT_FLOW ((__force upf_t) BIT_ULL(22))
include/linux/serial_core.h
536
#define UPF_CONS_FLOW ((__force upf_t) BIT_ULL(23))
include/linux/serial_core.h
537
#define UPF_SHARE_IRQ ((__force upf_t) BIT_ULL(24))
include/linux/serial_core.h
538
#define UPF_EXAR_EFR ((__force upf_t) BIT_ULL(25))
include/linux/serial_core.h
539
#define UPF_BUG_THRE ((__force upf_t) BIT_ULL(26))
include/linux/serial_core.h
541
#define UPF_FIXED_TYPE ((__force upf_t) BIT_ULL(27))
include/linux/serial_core.h
542
#define UPF_BOOT_AUTOCONF ((__force upf_t) BIT_ULL(28))
include/linux/serial_core.h
543
#define UPF_FIXED_PORT ((__force upf_t) BIT_ULL(29))
include/linux/serial_core.h
544
#define UPF_DEAD ((__force upf_t) BIT_ULL(30))
include/linux/serial_core.h
545
#define UPF_IOREMAP ((__force upf_t) BIT_ULL(31))
include/linux/serial_core.h
546
#define UPF_FULL_PROBE ((__force upf_t) BIT_ULL(32))
include/linux/switchtec.h
371
#define NTB_DBMSG_IMSG_STATUS BIT_ULL(32)
include/linux/switchtec.h
372
#define NTB_DBMSG_IMSG_MASK BIT_ULL(40)
include/linux/virtio_features.h
12
#define VIRTIO_BIT(b) BIT_ULL((b) & 0x3f)
include/media/rc-map.h
15
#define RC_PROTO_BIT_UNKNOWN BIT_ULL(RC_PROTO_UNKNOWN)
include/media/rc-map.h
16
#define RC_PROTO_BIT_OTHER BIT_ULL(RC_PROTO_OTHER)
include/media/rc-map.h
17
#define RC_PROTO_BIT_RC5 BIT_ULL(RC_PROTO_RC5)
include/media/rc-map.h
18
#define RC_PROTO_BIT_RC5X_20 BIT_ULL(RC_PROTO_RC5X_20)
include/media/rc-map.h
19
#define RC_PROTO_BIT_RC5_SZ BIT_ULL(RC_PROTO_RC5_SZ)
include/media/rc-map.h
20
#define RC_PROTO_BIT_JVC BIT_ULL(RC_PROTO_JVC)
include/media/rc-map.h
21
#define RC_PROTO_BIT_SONY12 BIT_ULL(RC_PROTO_SONY12)
include/media/rc-map.h
22
#define RC_PROTO_BIT_SONY15 BIT_ULL(RC_PROTO_SONY15)
include/media/rc-map.h
23
#define RC_PROTO_BIT_SONY20 BIT_ULL(RC_PROTO_SONY20)
include/media/rc-map.h
24
#define RC_PROTO_BIT_NEC BIT_ULL(RC_PROTO_NEC)
include/media/rc-map.h
25
#define RC_PROTO_BIT_NECX BIT_ULL(RC_PROTO_NECX)
include/media/rc-map.h
26
#define RC_PROTO_BIT_NEC32 BIT_ULL(RC_PROTO_NEC32)
include/media/rc-map.h
27
#define RC_PROTO_BIT_SANYO BIT_ULL(RC_PROTO_SANYO)
include/media/rc-map.h
28
#define RC_PROTO_BIT_MCIR2_KBD BIT_ULL(RC_PROTO_MCIR2_KBD)
include/media/rc-map.h
29
#define RC_PROTO_BIT_MCIR2_MSE BIT_ULL(RC_PROTO_MCIR2_MSE)
include/media/rc-map.h
30
#define RC_PROTO_BIT_RC6_0 BIT_ULL(RC_PROTO_RC6_0)
include/media/rc-map.h
31
#define RC_PROTO_BIT_RC6_6A_20 BIT_ULL(RC_PROTO_RC6_6A_20)
include/media/rc-map.h
32
#define RC_PROTO_BIT_RC6_6A_24 BIT_ULL(RC_PROTO_RC6_6A_24)
include/media/rc-map.h
33
#define RC_PROTO_BIT_RC6_6A_32 BIT_ULL(RC_PROTO_RC6_6A_32)
include/media/rc-map.h
34
#define RC_PROTO_BIT_RC6_MCE BIT_ULL(RC_PROTO_RC6_MCE)
include/media/rc-map.h
35
#define RC_PROTO_BIT_SHARP BIT_ULL(RC_PROTO_SHARP)
include/media/rc-map.h
36
#define RC_PROTO_BIT_XMP BIT_ULL(RC_PROTO_XMP)
include/media/rc-map.h
37
#define RC_PROTO_BIT_CEC BIT_ULL(RC_PROTO_CEC)
include/media/rc-map.h
38
#define RC_PROTO_BIT_IMON BIT_ULL(RC_PROTO_IMON)
include/media/rc-map.h
39
#define RC_PROTO_BIT_RCMM12 BIT_ULL(RC_PROTO_RCMM12)
include/media/rc-map.h
40
#define RC_PROTO_BIT_RCMM24 BIT_ULL(RC_PROTO_RCMM24)
include/media/rc-map.h
41
#define RC_PROTO_BIT_RCMM32 BIT_ULL(RC_PROTO_RCMM32)
include/media/rc-map.h
42
#define RC_PROTO_BIT_XBOX_DVD BIT_ULL(RC_PROTO_XBOX_DVD)
include/net/mac80211.h
401
BSS_CHANGED_UNSOL_BCAST_PROBE_RESP = BIT_ULL(31),
include/net/mac80211.h
402
BSS_CHANGED_MLD_VALID_LINKS = BIT_ULL(33),
include/net/mac80211.h
403
BSS_CHANGED_MLD_TTLM = BIT_ULL(34),
include/net/mac80211.h
404
BSS_CHANGED_TPE = BIT_ULL(35),
include/net/mana/gdma.h
776
GDMA_ACCESS_FLAG_LOCAL_READ = BIT_ULL(0),
include/net/mana/gdma.h
777
GDMA_ACCESS_FLAG_LOCAL_WRITE = BIT_ULL(1),
include/net/mana/gdma.h
778
GDMA_ACCESS_FLAG_REMOTE_READ = BIT_ULL(2),
include/net/mana/gdma.h
779
GDMA_ACCESS_FLAG_REMOTE_WRITE = BIT_ULL(3),
include/net/mana/gdma.h
780
GDMA_ACCESS_FLAG_REMOTE_ATOMIC = BIT_ULL(4),
include/net/xsk_buff_pool.h
101
#define XSK_NEXT_PG_CONTIG_MASK BIT_ULL(XSK_NEXT_PG_CONTIG_SHIFT)
include/net/xsk_buff_pool.h
182
#define XSK_NEXT_PG_CONTIG_MASK BIT_ULL(XSK_NEXT_PG_CONTIG_SHIFT)
include/rdma/ib_verbs.h
162
IB_SA_WELL_KNOWN_GUID = BIT_ULL(57) | 2,
include/rdma/ib_verbs.h
3020
return biter->__dma_addr & ~(BIT_ULL(biter->__pg_bit) - 1);
kernel/bpf/btf.c
7771
ARG_TAG_CTX = BIT_ULL(0),
kernel/bpf/btf.c
7772
ARG_TAG_NONNULL = BIT_ULL(1),
kernel/bpf/btf.c
7773
ARG_TAG_TRUSTED = BIT_ULL(2),
kernel/bpf/btf.c
7774
ARG_TAG_UNTRUSTED = BIT_ULL(3),
kernel/bpf/btf.c
7775
ARG_TAG_NULLABLE = BIT_ULL(4),
kernel/bpf/btf.c
7776
ARG_TAG_ARENA = BIT_ULL(5),
kernel/bpf/token.c
240
if (!(token->allowed_cmds & BIT_ULL(cmd)))
kernel/bpf/token.c
250
return token->allowed_maps & BIT_ULL(type);
kernel/bpf/token.c
260
return (token->allowed_progs & BIT_ULL(prog_type)) &&
kernel/bpf/token.c
261
(token->allowed_attachs & BIT_ULL(attach_type));
kernel/bpf/token.c
75
mask = BIT_ULL(__MAX_BPF_CMD) - 1;
kernel/bpf/token.c
82
mask = BIT_ULL(__MAX_BPF_MAP_TYPE) - 1;
kernel/bpf/token.c
89
mask = BIT_ULL(__MAX_BPF_PROG_TYPE) - 1;
kernel/bpf/token.c
96
mask = BIT_ULL(__MAX_BPF_ATTACH_TYPE) - 1;
net/ethtool/ioctl.c
3692
BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS);
net/ethtool/ioctl.c
3707
BIT_ULL(FLOW_DISSECTOR_KEY_PORTS);
net/ethtool/ioctl.c
3744
BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS);
net/ethtool/ioctl.c
3759
BIT_ULL(FLOW_DISSECTOR_KEY_PORTS);
net/ethtool/ioctl.c
3767
BIT_ULL(FLOW_DISSECTOR_KEY_IP);
net/ethtool/ioctl.c
3791
match->dissector.used_keys |= BIT_ULL(FLOW_DISSECTOR_KEY_BASIC);
net/ethtool/ioctl.c
3824
BIT_ULL(FLOW_DISSECTOR_KEY_VLAN);
net/ethtool/ioctl.c
3839
BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS);
net/mac80211/ethtool.c
127
if (sinfo.filled & BIT_ULL(NL80211_STA_INFO_TX_BITRATE))
net/mac80211/ethtool.c
131
if (sinfo.filled & BIT_ULL(NL80211_STA_INFO_RX_BITRATE))
net/mac80211/ethtool.c
136
if (sinfo.filled & BIT_ULL(NL80211_STA_INFO_SIGNAL_AVG))
net/mac80211/rx.c
1196
tid_agg_rx->reorder_buf_filtered & BIT_ULL(index))
net/mac80211/rx.c
1238
tid_agg_rx->reorder_buf_filtered &= ~BIT_ULL(index);
net/mac80211/rx.c
3492
BIT_ULL(color),
net/mac80211/rx.c
4451
tid_agg_rx->reorder_buf_filtered &= ~BIT_ULL(index);
net/mac80211/rx.c
4452
if (filtered & BIT_ULL(i))
net/mac80211/rx.c
4453
tid_agg_rx->reorder_buf_filtered |= BIT_ULL(index);
net/mac80211/sta_info.c
2692
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_LLID) |
net/mac80211/sta_info.c
2693
BIT_ULL(NL80211_STA_INFO_PLID) |
net/mac80211/sta_info.c
2694
BIT_ULL(NL80211_STA_INFO_PLINK_STATE) |
net/mac80211/sta_info.c
2695
BIT_ULL(NL80211_STA_INFO_LOCAL_PM) |
net/mac80211/sta_info.c
2696
BIT_ULL(NL80211_STA_INFO_PEER_PM) |
net/mac80211/sta_info.c
2697
BIT_ULL(NL80211_STA_INFO_NONPEER_PM) |
net/mac80211/sta_info.c
2698
BIT_ULL(NL80211_STA_INFO_CONNECTED_TO_GATE) |
net/mac80211/sta_info.c
2699
BIT_ULL(NL80211_STA_INFO_CONNECTED_TO_AS);
net/mac80211/sta_info.c
2705
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_T_OFFSET);
net/mac80211/sta_info.c
2714
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_AIRTIME_LINK_METRIC);
net/mac80211/sta_info.c
2774
link_sinfo->filled |= BIT_ULL(NL80211_STA_INFO_INACTIVE_TIME) |
net/mac80211/sta_info.c
2775
BIT_ULL(NL80211_STA_INFO_BSS_PARAM) |
net/mac80211/sta_info.c
2776
BIT_ULL(NL80211_STA_INFO_RX_DROP_MISC);
net/mac80211/sta_info.c
2781
link_sinfo->filled |= BIT_ULL(NL80211_STA_INFO_BEACON_LOSS);
net/mac80211/sta_info.c
2789
if (!(link_sinfo->filled & (BIT_ULL(NL80211_STA_INFO_TX_BYTES64) |
net/mac80211/sta_info.c
2790
BIT_ULL(NL80211_STA_INFO_TX_BYTES)))) {
net/mac80211/sta_info.c
2795
link_sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BYTES64);
net/mac80211/sta_info.c
2798
if (!(link_sinfo->filled & BIT_ULL(NL80211_STA_INFO_TX_PACKETS))) {
net/mac80211/sta_info.c
2803
link_sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_PACKETS);
net/mac80211/sta_info.c
2806
if (!(link_sinfo->filled & (BIT_ULL(NL80211_STA_INFO_RX_BYTES64) |
net/mac80211/sta_info.c
2807
BIT_ULL(NL80211_STA_INFO_RX_BYTES)))) {
net/mac80211/sta_info.c
2822
link_sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_BYTES64);
net/mac80211/sta_info.c
2825
if (!(link_sinfo->filled & BIT_ULL(NL80211_STA_INFO_RX_PACKETS))) {
net/mac80211/sta_info.c
2836
link_sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_PACKETS);
net/mac80211/sta_info.c
2839
if (!(link_sinfo->filled & BIT_ULL(NL80211_STA_INFO_TX_RETRIES))) {
net/mac80211/sta_info.c
2842
link_sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_RETRIES);
net/mac80211/sta_info.c
2845
if (!(link_sinfo->filled & BIT_ULL(NL80211_STA_INFO_TX_FAILED))) {
net/mac80211/sta_info.c
2848
link_sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_FAILED);
net/mac80211/sta_info.c
2851
if (!(link_sinfo->filled & BIT_ULL(NL80211_STA_INFO_RX_DURATION))) {
net/mac80211/sta_info.c
2854
link_sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_DURATION);
net/mac80211/sta_info.c
2857
if (!(link_sinfo->filled & BIT_ULL(NL80211_STA_INFO_TX_DURATION))) {
net/mac80211/sta_info.c
2860
link_sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_DURATION);
net/mac80211/sta_info.c
2863
if (!(link_sinfo->filled & BIT_ULL(NL80211_STA_INFO_AIRTIME_WEIGHT))) {
net/mac80211/sta_info.c
2865
link_sinfo->filled |= BIT_ULL(NL80211_STA_INFO_AIRTIME_WEIGHT);
net/mac80211/sta_info.c
2881
link_sinfo->filled |= BIT_ULL(NL80211_STA_INFO_BEACON_RX) |
net/mac80211/sta_info.c
2882
BIT_ULL(NL80211_STA_INFO_BEACON_SIGNAL_AVG);
net/mac80211/sta_info.c
2889
if (!(link_sinfo->filled & BIT_ULL(NL80211_STA_INFO_SIGNAL))) {
net/mac80211/sta_info.c
2891
link_sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL);
net/mac80211/sta_info.c
2896
BIT_ULL(NL80211_STA_INFO_SIGNAL_AVG))) {
net/mac80211/sta_info.c
2900
BIT_ULL(NL80211_STA_INFO_SIGNAL_AVG);
net/mac80211/sta_info.c
2909
!(link_sinfo->filled & (BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL) |
net/mac80211/sta_info.c
2910
BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL_AVG)))) {
net/mac80211/sta_info.c
2911
link_sinfo->filled |= BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL);
net/mac80211/sta_info.c
2914
BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL_AVG);
net/mac80211/sta_info.c
2927
if (!(link_sinfo->filled & BIT_ULL(NL80211_STA_INFO_TX_BITRATE)) &&
net/mac80211/sta_info.c
2931
link_sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
net/mac80211/sta_info.c
2934
if (!(link_sinfo->filled & BIT_ULL(NL80211_STA_INFO_RX_BITRATE))) {
net/mac80211/sta_info.c
2938
BIT_ULL(NL80211_STA_INFO_RX_BITRATE);
net/mac80211/sta_info.c
2962
BIT_ULL(NL80211_STA_INFO_EXPECTED_THROUGHPUT);
net/mac80211/sta_info.c
2966
if (!(link_sinfo->filled & BIT_ULL(NL80211_STA_INFO_ACK_SIGNAL)) &&
net/mac80211/sta_info.c
2970
link_sinfo->filled |= BIT_ULL(NL80211_STA_INFO_ACK_SIGNAL);
net/mac80211/sta_info.c
2973
if (!(link_sinfo->filled & BIT_ULL(NL80211_STA_INFO_ACK_SIGNAL_AVG)) &&
net/mac80211/sta_info.c
2979
BIT_ULL(NL80211_STA_INFO_ACK_SIGNAL_AVG);
net/mac80211/sta_info.c
3004
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_INACTIVE_TIME) |
net/mac80211/sta_info.c
3005
BIT_ULL(NL80211_STA_INFO_STA_FLAGS) |
net/mac80211/sta_info.c
3006
BIT_ULL(NL80211_STA_INFO_BSS_PARAM) |
net/mac80211/sta_info.c
3007
BIT_ULL(NL80211_STA_INFO_CONNECTED_TIME) |
net/mac80211/sta_info.c
3008
BIT_ULL(NL80211_STA_INFO_ASSOC_AT_BOOTTIME) |
net/mac80211/sta_info.c
3009
BIT_ULL(NL80211_STA_INFO_RX_DROP_MISC);
net/mac80211/sta_info.c
3014
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_BEACON_LOSS);
net/mac80211/sta_info.c
3023
if (!(sinfo->filled & (BIT_ULL(NL80211_STA_INFO_TX_BYTES64) |
net/mac80211/sta_info.c
3024
BIT_ULL(NL80211_STA_INFO_TX_BYTES)))) {
net/mac80211/sta_info.c
3028
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BYTES64);
net/mac80211/sta_info.c
3031
if (!(sinfo->filled & BIT_ULL(NL80211_STA_INFO_TX_PACKETS))) {
net/mac80211/sta_info.c
3035
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_PACKETS);
net/mac80211/sta_info.c
3038
if (!(sinfo->filled & (BIT_ULL(NL80211_STA_INFO_RX_BYTES64) |
net/mac80211/sta_info.c
3039
BIT_ULL(NL80211_STA_INFO_RX_BYTES)))) {
net/mac80211/sta_info.c
3052
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_BYTES64);
net/mac80211/sta_info.c
3055
if (!(sinfo->filled & BIT_ULL(NL80211_STA_INFO_RX_PACKETS))) {
net/mac80211/sta_info.c
3066
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_PACKETS);
net/mac80211/sta_info.c
3069
if (!(sinfo->filled & BIT_ULL(NL80211_STA_INFO_TX_RETRIES))) {
net/mac80211/sta_info.c
3071
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_RETRIES);
net/mac80211/sta_info.c
3074
if (!(sinfo->filled & BIT_ULL(NL80211_STA_INFO_TX_FAILED))) {
net/mac80211/sta_info.c
3076
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_FAILED);
net/mac80211/sta_info.c
3079
if (!(sinfo->filled & BIT_ULL(NL80211_STA_INFO_RX_DURATION))) {
net/mac80211/sta_info.c
3082
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_DURATION);
net/mac80211/sta_info.c
3085
if (!(sinfo->filled & BIT_ULL(NL80211_STA_INFO_TX_DURATION))) {
net/mac80211/sta_info.c
3088
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_DURATION);
net/mac80211/sta_info.c
3091
if (!(sinfo->filled & BIT_ULL(NL80211_STA_INFO_AIRTIME_WEIGHT))) {
net/mac80211/sta_info.c
3093
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_AIRTIME_WEIGHT);
net/mac80211/sta_info.c
3108
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_BEACON_RX) |
net/mac80211/sta_info.c
3109
BIT_ULL(NL80211_STA_INFO_BEACON_SIGNAL_AVG);
net/mac80211/sta_info.c
3116
if (!(sinfo->filled & BIT_ULL(NL80211_STA_INFO_SIGNAL))) {
net/mac80211/sta_info.c
3118
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL);
net/mac80211/sta_info.c
3122
!(sinfo->filled & BIT_ULL(NL80211_STA_INFO_SIGNAL_AVG))) {
net/mac80211/sta_info.c
3125
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL_AVG);
net/mac80211/sta_info.c
3134
!(sinfo->filled & (BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL) |
net/mac80211/sta_info.c
3135
BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL_AVG)))) {
net/mac80211/sta_info.c
3136
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL);
net/mac80211/sta_info.c
3138
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL_AVG);
net/mac80211/sta_info.c
3150
if (!(sinfo->filled & BIT_ULL(NL80211_STA_INFO_TX_BITRATE)) &&
net/mac80211/sta_info.c
3155
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
net/mac80211/sta_info.c
3158
if (!(sinfo->filled & BIT_ULL(NL80211_STA_INFO_RX_BITRATE)) &&
net/mac80211/sta_info.c
3161
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_BITRATE);
net/mac80211/sta_info.c
3210
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_EXPECTED_THROUGHPUT);
net/mac80211/sta_info.c
3214
if (!(sinfo->filled & BIT_ULL(NL80211_STA_INFO_ACK_SIGNAL)) &&
net/mac80211/sta_info.c
3217
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_ACK_SIGNAL);
net/mac80211/sta_info.c
3220
if (!(sinfo->filled & BIT_ULL(NL80211_STA_INFO_ACK_SIGNAL_AVG)) &&
net/mac80211/sta_info.c
3226
BIT_ULL(NL80211_STA_INFO_ACK_SIGNAL_AVG);
net/netfilter/nf_flow_table_offload.c
169
match->dissector.used_keys |= BIT_ULL(key->control.addr_type);
net/netfilter/nf_flow_table_offload.c
176
match->dissector.used_keys |= BIT_ULL(FLOW_DISSECTOR_KEY_TCP);
net/netfilter/nf_flow_table_offload.c
188
match->dissector.used_keys |= BIT_ULL(FLOW_DISSECTOR_KEY_META) |
net/netfilter/nf_flow_table_offload.c
189
BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
net/netfilter/nf_flow_table_offload.c
190
BIT_ULL(FLOW_DISSECTOR_KEY_BASIC);
net/netfilter/nf_flow_table_offload.c
200
match->dissector.used_keys |= BIT_ULL(FLOW_DISSECTOR_KEY_PORTS);
net/netfilter/nf_flow_table_offload.c
49
enc_keys = BIT_ULL(FLOW_DISSECTOR_KEY_ENC_KEYID) |
net/netfilter/nf_flow_table_offload.c
50
BIT_ULL(FLOW_DISSECTOR_KEY_ENC_CONTROL);
net/netfilter/nf_flow_table_offload.c
61
enc_keys |= BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS);
net/netfilter/nf_flow_table_offload.c
76
enc_keys |= BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS);
net/netfilter/nf_tables_offload.c
38
if (match->dissector.used_keys & BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL))
net/netfilter/nf_tables_offload.c
43
match->dissector.used_keys |= BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL);
net/netfilter/nf_tables_offload.c
62
if (match->dissector.used_keys & BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) &&
net/netfilter/nf_tables_offload.c
73
match->dissector.used_keys |= BIT_ULL(FLOW_DISSECTOR_KEY_CVLAN);
net/netfilter/nf_tables_offload.c
75
BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) &&
net/netfilter/nf_tables_offload.c
84
match->dissector.used_keys |= BIT_ULL(FLOW_DISSECTOR_KEY_VLAN);
net/netfilter/nft_cmp.c
165
flow->match.dissector.used_keys |= BIT_ULL(reg->key);
net/openvswitch/meter.h
21
#define DP_METER_ARRAY_SIZE_MIN BIT_ULL(10)
net/wireless/nl80211.c
14235
if (sinfo.filled & BIT_ULL(NL80211_STA_INFO_BEACON_SIGNAL_AVG))
net/wireless/nl80211.c
7326
if (link_sinfo->filled & BIT_ULL(NL80211_STA_INFO_ ## attr) && \
net/wireless/nl80211.c
7332
if (link_sinfo->filled & BIT_ULL(NL80211_STA_INFO_ ## attr) && \
net/wireless/nl80211.c
7344
if (link_sinfo->filled & (BIT_ULL(NL80211_STA_INFO_RX_BYTES) |
net/wireless/nl80211.c
7345
BIT_ULL(NL80211_STA_INFO_RX_BYTES64)) &&
net/wireless/nl80211.c
7350
if (link_sinfo->filled & (BIT_ULL(NL80211_STA_INFO_TX_BYTES) |
net/wireless/nl80211.c
7351
BIT_ULL(NL80211_STA_INFO_TX_BYTES64)) &&
net/wireless/nl80211.c
7373
if (link_sinfo->filled & BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL)) {
net/wireless/nl80211.c
7379
if (link_sinfo->filled & BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL_AVG)) {
net/wireless/nl80211.c
7385
if (link_sinfo->filled & BIT_ULL(NL80211_STA_INFO_TX_BITRATE)) {
net/wireless/nl80211.c
7390
if (link_sinfo->filled & BIT_ULL(NL80211_STA_INFO_RX_BITRATE)) {
net/wireless/nl80211.c
7403
if (link_sinfo->filled & BIT_ULL(NL80211_STA_INFO_BSS_PARAM)) {
net/wireless/nl80211.c
7527
if (sinfo->filled & BIT_ULL(NL80211_STA_INFO_ ## attr) && \
net/wireless/nl80211.c
7533
if (sinfo->filled & BIT_ULL(NL80211_STA_INFO_ ## attr) && \
net/wireless/nl80211.c
7543
if (sinfo->filled & (BIT_ULL(NL80211_STA_INFO_RX_BYTES) |
net/wireless/nl80211.c
7544
BIT_ULL(NL80211_STA_INFO_RX_BYTES64)) &&
net/wireless/nl80211.c
7549
if (sinfo->filled & (BIT_ULL(NL80211_STA_INFO_TX_BYTES) |
net/wireless/nl80211.c
7550
BIT_ULL(NL80211_STA_INFO_TX_BYTES64)) &&
net/wireless/nl80211.c
7572
if (sinfo->filled & BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL)) {
net/wireless/nl80211.c
7578
if (sinfo->filled & BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL_AVG)) {
net/wireless/nl80211.c
7584
if (sinfo->filled & BIT_ULL(NL80211_STA_INFO_TX_BITRATE)) {
net/wireless/nl80211.c
7589
if (sinfo->filled & BIT_ULL(NL80211_STA_INFO_RX_BITRATE)) {
net/wireless/nl80211.c
7613
if (sinfo->filled & BIT_ULL(NL80211_STA_INFO_BSS_PARAM)) {
net/wireless/nl80211.c
7633
if ((sinfo->filled & BIT_ULL(NL80211_STA_INFO_STA_FLAGS)) &&
net/wireless/nl80211.c
7781
BIT_ULL(NL80211_STA_INFO_TX_PACKETS))) {
net/wireless/nl80211.c
7783
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_PACKETS);
net/wireless/nl80211.c
7787
BIT_ULL(NL80211_STA_INFO_RX_PACKETS))) {
net/wireless/nl80211.c
7789
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_PACKETS);
net/wireless/nl80211.c
7793
(BIT_ULL(NL80211_STA_INFO_TX_BYTES) |
net/wireless/nl80211.c
7794
BIT_ULL(NL80211_STA_INFO_TX_BYTES64))) {
net/wireless/nl80211.c
7796
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BYTES);
net/wireless/nl80211.c
7800
(BIT_ULL(NL80211_STA_INFO_RX_BYTES) |
net/wireless/nl80211.c
7801
BIT_ULL(NL80211_STA_INFO_TX_BYTES64))) {
net/wireless/nl80211.c
7803
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_BYTES);
net/wireless/nl80211.c
7807
BIT_ULL(NL80211_STA_INFO_TX_RETRIES)) {
net/wireless/nl80211.c
7809
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_RETRIES);
net/wireless/nl80211.c
7812
if (link_sinfo->filled & BIT_ULL(NL80211_STA_INFO_TX_FAILED)) {
net/wireless/nl80211.c
7814
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_FAILED);
net/wireless/nl80211.c
7818
BIT_ULL(NL80211_STA_INFO_RX_DROP_MISC)) {
net/wireless/nl80211.c
7821
BIT_ULL(NL80211_STA_INFO_RX_DROP_MISC);
net/wireless/nl80211.c
7825
BIT_ULL(NL80211_STA_INFO_BEACON_LOSS)) {
net/wireless/nl80211.c
7828
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_BEACON_LOSS);
net/wireless/nl80211.c
7832
BIT_ULL(NL80211_STA_INFO_EXPECTED_THROUGHPUT)) {
net/wireless/nl80211.c
7836
BIT_ULL(NL80211_STA_INFO_EXPECTED_THROUGHPUT);
net/wireless/nl80211.c
7839
if (link_sinfo->filled & BIT_ULL(NL80211_STA_INFO_RX_MPDUS)) {
net/wireless/nl80211.c
7841
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_MPDUS);
net/wireless/nl80211.c
7845
BIT_ULL(NL80211_STA_INFO_FCS_ERROR_COUNT)) {
net/wireless/nl80211.c
7848
BIT_ULL(NL80211_STA_INFO_FCS_ERROR_COUNT);
net/wireless/nl80211.c
7852
BIT_ULL(NL80211_STA_INFO_BEACON_RX)) {
net/wireless/nl80211.c
7854
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_BEACON_RX);
net/wireless/nl80211.c
7858
if ((link_sinfo->filled & BIT_ULL(NL80211_STA_INFO_SIGNAL)) &&
net/wireless/nl80211.c
7861
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL);
net/wireless/nl80211.c
7865
BIT_ULL(NL80211_STA_INFO_SIGNAL_AVG)) &&
net/wireless/nl80211.c
7868
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL_AVG);
net/wireless/nl80211.c
7875
BIT_ULL(NL80211_STA_INFO_INACTIVE_TIME)) &&
net/wireless/nl80211.c
7883
if (link_sinfo->filled & BIT_ULL(NL80211_STA_INFO_BSS_PARAM) &&
net/wireless/nl80211.c
7897
BIT_ULL(NL80211_STA_INFO_TX_BITRATE)) &&
net/wireless/nl80211.c
7901
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
net/wireless/nl80211.c
7904
BIT_ULL(NL80211_STA_INFO_RX_BITRATE)) &&
net/wireless/nl80211.c
7908
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_BITRATE);
net/wireless/nl80211.c
7912
BIT_ULL(NL80211_STA_INFO_TX_DURATION) &&
net/wireless/nl80211.c
7917
BIT_ULL(NL80211_STA_INFO_TX_DURATION);
net/wireless/nl80211.c
7920
BIT_ULL(NL80211_STA_INFO_RX_DURATION) &&
net/wireless/nl80211.c
7925
BIT_ULL(NL80211_STA_INFO_RX_DURATION);
net/wireless/nl80211.c
7951
sinfo->filled &= ~BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL);
net/wireless/nl80211.c
7952
sinfo->filled &= ~BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL_AVG);
net/wireless/scan.c
2556
if (seen_indices & BIT_ULL(mbssid_index_ie[2]))
net/wireless/scan.c
2561
seen_indices |= BIT_ULL(mbssid_index_ie[2]);
net/wireless/wext-compat.c
1269
if (!(sinfo.filled & BIT_ULL(NL80211_STA_INFO_TX_BITRATE))) {
net/wireless/wext-compat.c
1318
if (sinfo.filled & BIT_ULL(NL80211_STA_INFO_SIGNAL)) {
net/wireless/wext-compat.c
1333
if (sinfo.filled & BIT_ULL(NL80211_STA_INFO_SIGNAL)) {
net/wireless/wext-compat.c
1347
if (sinfo.filled & BIT_ULL(NL80211_STA_INFO_RX_DROP_MISC))
net/wireless/wext-compat.c
1349
if (sinfo.filled & BIT_ULL(NL80211_STA_INFO_TX_FAILED))
net/xdp/xsk.h
12
#define XSK_NEXT_PG_CONTIG_MASK BIT_ULL(XSK_NEXT_PG_CONTIG_SHIFT)
security/landlock/id.c
29
init = BIT_ULL(32);
sound/soc/intel/avs/avs.h
73
#define AVS_PLATATTR_CLDMA BIT_ULL(0)
sound/soc/intel/avs/avs.h
74
#define AVS_PLATATTR_IMR BIT_ULL(1)
sound/soc/intel/avs/avs.h
75
#define AVS_PLATATTR_ACE BIT_ULL(2)
sound/soc/intel/avs/avs.h
76
#define AVS_PLATATTR_ALTHDA BIT_ULL(3)
sound/soc/sof/intel/shim.h
103
#define SHIM_BYT_IPCX_DONE BIT_ULL(62)
sound/soc/sof/intel/shim.h
104
#define SHIM_BYT_IPCX_BUSY BIT_ULL(63)
sound/soc/sof/intel/shim.h
109
#define SHIM_BYT_IPCD_DONE BIT_ULL(62)
sound/soc/sof/intel/shim.h
110
#define SHIM_BYT_IPCD_BUSY BIT_ULL(63)
sound/xen/xen_snd_front_alsa.c
194
mask |= BIT_ULL(ALSA_SNDIF_FORMATS[i].sndif);
sound/xen/xen_snd_front_alsa.c
206
if (BIT_ULL(ALSA_SNDIF_FORMATS[i].sndif) & sndif_formats)
tools/arch/arm64/include/asm/sysreg.h
355
BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
tools/arch/arm64/include/asm/sysreg.h
357
(PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
tools/arch/arm64/include/asm/sysreg.h
359
(PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6))
tools/arch/x86/include/asm/msr-index.h
100
#define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
tools/arch/x86/include/asm/msr-index.h
1106
#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT)
tools/arch/x86/include/asm/msr-index.h
1115
#define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT)
tools/arch/x86/include/asm/msr-index.h
1117
#define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT)
tools/arch/x86/include/asm/msr-index.h
1119
#define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT)
tools/arch/x86/include/asm/msr-index.h
218
#define ARCH_CAP_ITS_NO BIT_ULL(62) /*
tools/arch/x86/include/asm/msr-index.h
293
#define LBR_INFO_MISPRED BIT_ULL(63)
tools/arch/x86/include/asm/msr-index.h
294
#define LBR_INFO_IN_TX BIT_ULL(62)
tools/arch/x86/include/asm/msr-index.h
295
#define LBR_INFO_ABORT BIT_ULL(61)
tools/arch/x86/include/asm/msr-index.h
296
#define LBR_INFO_CYC_CNT_VALID BIT_ULL(60)
tools/arch/x86/include/asm/msr-index.h
329
#define PERF_CAP_PEBS_TRAP BIT_ULL(6)
tools/arch/x86/include/asm/msr-index.h
330
#define PERF_CAP_ARCH_REG BIT_ULL(7)
tools/arch/x86/include/asm/msr-index.h
332
#define PERF_CAP_FW_WRITES BIT_ULL(13)
tools/arch/x86/include/asm/msr-index.h
333
#define PERF_CAP_PEBS_BASELINE BIT_ULL(14)
tools/arch/x86/include/asm/msr-index.h
334
#define PERF_CAP_PEBS_TIMING_INFO BIT_ULL(17)
tools/arch/x86/include/asm/msr-index.h
346
#define ARCH_PEBS_CNTR_ALLOW BIT_ULL(35)
tools/arch/x86/include/asm/msr-index.h
347
#define ARCH_PEBS_CNTR_GP BIT_ULL(36)
tools/arch/x86/include/asm/msr-index.h
348
#define ARCH_PEBS_CNTR_FIXED BIT_ULL(37)
tools/arch/x86/include/asm/msr-index.h
349
#define ARCH_PEBS_CNTR_METRICS BIT_ULL(38)
tools/arch/x86/include/asm/msr-index.h
352
#define ARCH_PEBS_VECR_XMM BIT_ULL(49)
tools/arch/x86/include/asm/msr-index.h
353
#define ARCH_PEBS_GPR BIT_ULL(61)
tools/arch/x86/include/asm/msr-index.h
354
#define ARCH_PEBS_AUX BIT_ULL(62)
tools/arch/x86/include/asm/msr-index.h
355
#define ARCH_PEBS_EN BIT_ULL(63)
tools/arch/x86/include/asm/msr-index.h
375
#define RTIT_CTL_NOTNT BIT_ULL(55)
tools/arch/x86/include/asm/msr-index.h
439
#define MSR_IA32_PASID_VALID BIT_ULL(31)
tools/arch/x86/include/asm/msr-index.h
548
#define CET_SHSTK_EN BIT_ULL(0)
tools/arch/x86/include/asm/msr-index.h
549
#define CET_WRSS_EN BIT_ULL(1)
tools/arch/x86/include/asm/msr-index.h
550
#define CET_ENDBR_EN BIT_ULL(2)
tools/arch/x86/include/asm/msr-index.h
551
#define CET_LEG_IW_EN BIT_ULL(3)
tools/arch/x86/include/asm/msr-index.h
552
#define CET_NO_TRACK_EN BIT_ULL(4)
tools/arch/x86/include/asm/msr-index.h
553
#define CET_SUPPRESS_DISABLE BIT_ULL(5)
tools/arch/x86/include/asm/msr-index.h
554
#define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9))
tools/arch/x86/include/asm/msr-index.h
555
#define CET_SUPPRESS BIT_ULL(10)
tools/arch/x86/include/asm/msr-index.h
556
#define CET_WAIT_ENDBR BIT_ULL(11)
tools/arch/x86/include/asm/msr-index.h
671
#define MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT BIT_ULL(MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT_BIT)
tools/arch/x86/include/asm/msr-index.h
679
#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
tools/arch/x86/include/asm/msr-index.h
708
#define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT)
tools/arch/x86/include/asm/msr-index.h
710
#define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT)
tools/arch/x86/include/asm/msr-index.h
712
#define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT)
tools/arch/x86/include/asm/msr-index.h
714
#define MSR_AMD64_SNP_VTOM BIT_ULL(MSR_AMD64_SNP_VTOM_BIT)
tools/arch/x86/include/asm/msr-index.h
716
#define MSR_AMD64_SNP_REFLECT_VC BIT_ULL(MSR_AMD64_SNP_REFLECT_VC_BIT)
tools/arch/x86/include/asm/msr-index.h
718
#define MSR_AMD64_SNP_RESTRICTED_INJ BIT_ULL(MSR_AMD64_SNP_RESTRICTED_INJ_BIT)
tools/arch/x86/include/asm/msr-index.h
720
#define MSR_AMD64_SNP_ALT_INJ BIT_ULL(MSR_AMD64_SNP_ALT_INJ_BIT)
tools/arch/x86/include/asm/msr-index.h
722
#define MSR_AMD64_SNP_DEBUG_SWAP BIT_ULL(MSR_AMD64_SNP_DEBUG_SWAP_BIT)
tools/arch/x86/include/asm/msr-index.h
724
#define MSR_AMD64_SNP_PREVENT_HOST_IBS BIT_ULL(MSR_AMD64_SNP_PREVENT_HOST_IBS_BIT)
tools/arch/x86/include/asm/msr-index.h
726
#define MSR_AMD64_SNP_BTB_ISOLATION BIT_ULL(MSR_AMD64_SNP_BTB_ISOLATION_BIT)
tools/arch/x86/include/asm/msr-index.h
728
#define MSR_AMD64_SNP_VMPL_SSS BIT_ULL(MSR_AMD64_SNP_VMPL_SSS_BIT)
tools/arch/x86/include/asm/msr-index.h
730
#define MSR_AMD64_SNP_SECURE_TSC BIT_ULL(MSR_AMD64_SNP_SECURE_TSC_BIT)
tools/arch/x86/include/asm/msr-index.h
732
#define MSR_AMD64_SNP_VMGEXIT_PARAM BIT_ULL(MSR_AMD64_SNP_VMGEXIT_PARAM_BIT)
tools/arch/x86/include/asm/msr-index.h
733
#define MSR_AMD64_SNP_RESERVED_BIT13 BIT_ULL(13)
tools/arch/x86/include/asm/msr-index.h
735
#define MSR_AMD64_SNP_IBS_VIRT BIT_ULL(MSR_AMD64_SNP_IBS_VIRT_BIT)
tools/arch/x86/include/asm/msr-index.h
736
#define MSR_AMD64_SNP_RESERVED_BIT15 BIT_ULL(15)
tools/arch/x86/include/asm/msr-index.h
738
#define MSR_AMD64_SNP_VMSA_REG_PROT BIT_ULL(MSR_AMD64_SNP_VMSA_REG_PROT_BIT)
tools/arch/x86/include/asm/msr-index.h
740
#define MSR_AMD64_SNP_SMT_PROT BIT_ULL(MSR_AMD64_SNP_SMT_PROT_BIT)
tools/arch/x86/include/asm/msr-index.h
742
#define MSR_AMD64_SNP_SECURE_AVIC BIT_ULL(MSR_AMD64_SNP_SECURE_AVIC_BIT)
tools/arch/x86/include/asm/msr-index.h
745
#define MSR_AMD64_SNP_IBPB_ON_ENTRY BIT_ULL(MSR_AMD64_SNP_IBPB_ON_ENTRY_BIT)
tools/arch/x86/include/asm/msr-index.h
750
#define MSR_AMD64_SAVIC_EN BIT_ULL(MSR_AMD64_SAVIC_EN_BIT)
tools/arch/x86/include/asm/msr-index.h
752
#define MSR_AMD64_SAVIC_ALLOWEDNMI BIT_ULL(MSR_AMD64_SAVIC_ALLOWEDNMI_BIT)
tools/arch/x86/include/asm/msr-index.h
757
#define MSR_AMD64_SEG_RMP_ENABLED BIT_ULL(MSR_AMD64_SEG_RMP_ENABLED_BIT)
tools/arch/x86/include/asm/msr-index.h
858
#define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT)
tools/arch/x86/include/asm/msr-index.h
860
#define MSR_AMD64_SYSCFG_SNP_EN BIT_ULL(MSR_AMD64_SYSCFG_SNP_EN_BIT)
tools/arch/x86/include/asm/msr-index.h
862
#define MSR_AMD64_SYSCFG_SNP_VMPL_EN BIT_ULL(MSR_AMD64_SYSCFG_SNP_VMPL_EN_BIT)
tools/arch/x86/include/asm/msr-index.h
864
#define MSR_AMD64_SYSCFG_MFDM BIT_ULL(MSR_AMD64_SYSCFG_MFDM_BIT)
tools/arch/x86/include/asm/msr-index.h
887
#define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT)
tools/arch/x86/include/asm/msr-index.h
889
#define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT)
tools/arch/x86/include/asm/msr-index.h
894
#define MSR_K7_HWCR_CPB_DIS BIT_ULL(MSR_K7_HWCR_CPB_DIS_BIT)
tools/arch/x86/include/asm/msr-index.h
987
#define DBG_EXTN_CFG_LBRV2EN BIT_ULL(6)
tools/include/linux/bits.h
71
#define BIT_TYPE(type, nr) ((type)(BIT_INPUT_CHECK(type, nr) + BIT_ULL(nr)))
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
76
#define SPE_ADDR_PKT_GET_NS(v) (((v) & BIT_ULL(63)) >> 63)
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
78
#define SPE_ADDR_PKT_GET_CH(v) (((v) & BIT_ULL(62)) >> 62)
tools/perf/util/intel-pt.c
50
#define INTEL_PT_CFG_PASS_THRU BIT_ULL(0)
tools/perf/util/intel-pt.c
51
#define INTEL_PT_CFG_PWR_EVT_EN BIT_ULL(4)
tools/perf/util/intel-pt.c
52
#define INTEL_PT_CFG_BRANCH_EN BIT_ULL(13)
tools/perf/util/intel-pt.c
53
#define INTEL_PT_CFG_EVT_EN BIT_ULL(31)
tools/perf/util/intel-pt.c
54
#define INTEL_PT_CFG_TNT_DIS BIT_ULL(55)
tools/perf/util/pmu.c
1355
res |= BIT_ULL(val_bit);
tools/power/x86/intel-speed-select/isst-config.c
880
if (core_mask & BIT_ULL(i)) {
tools/testing/selftests/kvm/include/arm64/gic_v3.h
225
#define GICR_PENDBASER_PTZ BIT_ULL(62)
tools/testing/selftests/kvm/include/loongarch/processor.h
116
#define CSR_TCFG_VAL (BIT_ULL(48) - BIT_ULL(2))
tools/testing/selftests/kvm/include/loongarch/processor.h
59
#define _PAGE_VALID BIT_ULL(_PAGE_VALID_SHIFT)
tools/testing/selftests/kvm/include/loongarch/processor.h
60
#define _PAGE_PRESENT BIT_ULL(_PAGE_PRESENT_SHIFT)
tools/testing/selftests/kvm/include/loongarch/processor.h
61
#define _PAGE_WRITE BIT_ULL(_PAGE_WRITE_SHIFT)
tools/testing/selftests/kvm/include/loongarch/processor.h
62
#define _PAGE_DIRTY BIT_ULL(_PAGE_DIRTY_SHIFT)
tools/testing/selftests/kvm/include/loongarch/processor.h
67
#define _CACHE_CC BIT_ULL(_CACHE_SHIFT)
tools/testing/selftests/kvm/include/loongarch/processor.h
76
#define CSR_CRMD_PG BIT_ULL(CSR_CRMD_PG_SHIFT)
tools/testing/selftests/kvm/include/loongarch/processor.h
78
#define CSR_CRMD_IE BIT_ULL(CSR_CRMD_IE_SHIFT)
tools/testing/selftests/kvm/include/loongarch/processor.h
87
#define ECFGF_TIMER (BIT_ULL(ECFGB_TIMER))
tools/testing/selftests/kvm/include/s390/processor.h
26
#define PAGE_SIZE BIT_ULL(PAGE_SHIFT)
tools/testing/selftests/kvm/include/x86/hyperv.h
353
#define HV_INVARIANT_TSC_EXPOSED BIT_ULL(0)
tools/testing/selftests/kvm/include/x86/mce.h
10
#define MCG_SER_P BIT_ULL(24) /* MCA recovery/new status bits */
tools/testing/selftests/kvm/include/x86/mce.h
11
#define MCG_LMCE_P BIT_ULL(27) /* Local machine check supported */
tools/testing/selftests/kvm/include/x86/mce.h
12
#define MCG_CMCI_P BIT_ULL(10) /* CMCI supported */
tools/testing/selftests/kvm/include/x86/mce.h
21
#define MCI_CTL2_CMCI_EN BIT_ULL(30)
tools/testing/selftests/kvm/include/x86/mce.h
9
#define MCG_CTL_P BIT_ULL(8) /* MCG_CTL register available */
tools/testing/selftests/kvm/include/x86/pmu.h
120
return pmu_errata_mask & BIT_ULL(errata);
tools/testing/selftests/kvm/include/x86/pmu.h
31
#define ARCH_PERFMON_EVENTSEL_USR BIT_ULL(16)
tools/testing/selftests/kvm/include/x86/pmu.h
32
#define ARCH_PERFMON_EVENTSEL_OS BIT_ULL(17)
tools/testing/selftests/kvm/include/x86/pmu.h
33
#define ARCH_PERFMON_EVENTSEL_EDGE BIT_ULL(18)
tools/testing/selftests/kvm/include/x86/pmu.h
34
#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL BIT_ULL(19)
tools/testing/selftests/kvm/include/x86/pmu.h
35
#define ARCH_PERFMON_EVENTSEL_INT BIT_ULL(20)
tools/testing/selftests/kvm/include/x86/pmu.h
36
#define ARCH_PERFMON_EVENTSEL_ANY BIT_ULL(21)
tools/testing/selftests/kvm/include/x86/pmu.h
37
#define ARCH_PERFMON_EVENTSEL_ENABLE BIT_ULL(22)
tools/testing/selftests/kvm/include/x86/pmu.h
38
#define ARCH_PERFMON_EVENTSEL_INV BIT_ULL(23)
tools/testing/selftests/kvm/include/x86/pmu.h
42
#define INTEL_RDPMC_METRICS BIT_ULL(29)
tools/testing/selftests/kvm/include/x86/pmu.h
43
#define INTEL_RDPMC_FIXED BIT_ULL(30)
tools/testing/selftests/kvm/include/x86/pmu.h
44
#define INTEL_RDPMC_FAST BIT_ULL(31)
tools/testing/selftests/kvm/include/x86/pmu.h
47
#define FIXED_PMC_GLOBAL_CTRL_ENABLE(_idx) BIT_ULL((32 + (_idx)))
tools/testing/selftests/kvm/include/x86/pmu.h
49
#define FIXED_PMC_KERNEL BIT_ULL(0)
tools/testing/selftests/kvm/include/x86/pmu.h
50
#define FIXED_PMC_USER BIT_ULL(1)
tools/testing/selftests/kvm/include/x86/pmu.h
51
#define FIXED_PMC_ANYTHREAD BIT_ULL(2)
tools/testing/selftests/kvm/include/x86/pmu.h
52
#define FIXED_PMC_ENABLE_PMI BIT_ULL(3)
tools/testing/selftests/kvm/include/x86/pmu.h
56
#define PMU_CAP_FW_WRITES BIT_ULL(13)
tools/testing/selftests/kvm/include/x86/processor.h
1547
#define PFERR_GUEST_FINAL_MASK BIT_ULL(PFERR_GUEST_FINAL_BIT)
tools/testing/selftests/kvm/include/x86/processor.h
1548
#define PFERR_GUEST_PAGE_MASK BIT_ULL(PFERR_GUEST_PAGE_BIT)
tools/testing/selftests/kvm/include/x86/processor.h
1549
#define PFERR_IMPLICIT_ACCESS BIT_ULL(PFERR_IMPLICIT_ACCESS_BIT)
tools/testing/selftests/kvm/include/x86/processor.h
75
#define XFEATURE_MASK_FP BIT_ULL(0)
tools/testing/selftests/kvm/include/x86/processor.h
76
#define XFEATURE_MASK_SSE BIT_ULL(1)
tools/testing/selftests/kvm/include/x86/processor.h
77
#define XFEATURE_MASK_YMM BIT_ULL(2)
tools/testing/selftests/kvm/include/x86/processor.h
78
#define XFEATURE_MASK_BNDREGS BIT_ULL(3)
tools/testing/selftests/kvm/include/x86/processor.h
79
#define XFEATURE_MASK_BNDCSR BIT_ULL(4)
tools/testing/selftests/kvm/include/x86/processor.h
80
#define XFEATURE_MASK_OPMASK BIT_ULL(5)
tools/testing/selftests/kvm/include/x86/processor.h
81
#define XFEATURE_MASK_ZMM_Hi256 BIT_ULL(6)
tools/testing/selftests/kvm/include/x86/processor.h
82
#define XFEATURE_MASK_Hi16_ZMM BIT_ULL(7)
tools/testing/selftests/kvm/include/x86/processor.h
83
#define XFEATURE_MASK_PT BIT_ULL(8)
tools/testing/selftests/kvm/include/x86/processor.h
84
#define XFEATURE_MASK_PKRU BIT_ULL(9)
tools/testing/selftests/kvm/include/x86/processor.h
85
#define XFEATURE_MASK_PASID BIT_ULL(10)
tools/testing/selftests/kvm/include/x86/processor.h
86
#define XFEATURE_MASK_CET_USER BIT_ULL(11)
tools/testing/selftests/kvm/include/x86/processor.h
87
#define XFEATURE_MASK_CET_KERNEL BIT_ULL(12)
tools/testing/selftests/kvm/include/x86/processor.h
88
#define XFEATURE_MASK_LBR BIT_ULL(15)
tools/testing/selftests/kvm/include/x86/processor.h
89
#define XFEATURE_MASK_XTILE_CFG BIT_ULL(17)
tools/testing/selftests/kvm/include/x86/processor.h
90
#define XFEATURE_MASK_XTILE_DATA BIT_ULL(18)
tools/testing/selftests/kvm/include/x86/svm.h
158
#define LBR_CTL_ENABLE_MASK BIT_ULL(0)
tools/testing/selftests/kvm/include/x86/svm.h
159
#define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
tools/testing/selftests/kvm/lib/x86/pmu.c
63
return BIT_ULL(INSTRUCTIONS_RETIRED_OVERCOUNT);
tools/testing/selftests/kvm/lib/x86/pmu.c
68
return BIT_ULL(INSTRUCTIONS_RETIRED_OVERCOUNT) |
tools/testing/selftests/kvm/lib/x86/pmu.c
69
BIT_ULL(BRANCHES_RETIRED_OVERCOUNT);
tools/testing/selftests/kvm/lib/x86/processor.c
1318
vm->arch.c_bit = BIT_ULL(this_cpu_property(X86_PROPERTY_SEV_C_BIT));
tools/testing/selftests/kvm/lib/x86/processor.c
183
.present = BIT_ULL(0),
tools/testing/selftests/kvm/lib/x86/processor.c
184
.writable = BIT_ULL(1),
tools/testing/selftests/kvm/lib/x86/processor.c
185
.user = BIT_ULL(2),
tools/testing/selftests/kvm/lib/x86/processor.c
186
.accessed = BIT_ULL(5),
tools/testing/selftests/kvm/lib/x86/processor.c
187
.dirty = BIT_ULL(6),
tools/testing/selftests/kvm/lib/x86/processor.c
188
.huge = BIT_ULL(7),
tools/testing/selftests/kvm/lib/x86/processor.c
189
.nx = BIT_ULL(63),
tools/testing/selftests/kvm/lib/x86/vmx.c
57
.readable = BIT_ULL(0),
tools/testing/selftests/kvm/lib/x86/vmx.c
58
.writable = BIT_ULL(1),
tools/testing/selftests/kvm/lib/x86/vmx.c
59
.executable = BIT_ULL(2),
tools/testing/selftests/kvm/lib/x86/vmx.c
60
.huge = BIT_ULL(7),
tools/testing/selftests/kvm/lib/x86/vmx.c
61
.accessed = BIT_ULL(8),
tools/testing/selftests/kvm/lib/x86/vmx.c
62
.dirty = BIT_ULL(9),
tools/testing/selftests/kvm/steal_time.c
308
#define KVM_STEAL_PHYS_VALID BIT_ULL(0)
tools/testing/selftests/kvm/x86/hwcr_msr_test.c
13
const uint64_t ignored = BIT_ULL(3) | BIT_ULL(6) | BIT_ULL(8);
tools/testing/selftests/kvm/x86/hwcr_msr_test.c
14
const uint64_t valid = BIT_ULL(18) | BIT_ULL(24);
tools/testing/selftests/kvm/x86/hwcr_msr_test.c
16
uint64_t val = BIT_ULL(bit);
tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
273
flush_ex->hv_vp_set.valid_bank_mask = BIT_ULL(WORKER_VCPU_ID_2 / 64);
tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
274
flush_ex->hv_vp_set.bank_contents[0] = BIT_ULL(WORKER_VCPU_ID_2 % 64);
tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
288
flush_ex->hv_vp_set.valid_bank_mask = BIT_ULL(WORKER_VCPU_ID_2 / 64);
tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
289
flush_ex->hv_vp_set.bank_contents[0] = BIT_ULL(WORKER_VCPU_ID_2 % 64);
tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
306
flush_ex->hv_vp_set.valid_bank_mask = BIT_ULL(WORKER_VCPU_ID_2 / 64) |
tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
307
BIT_ULL(WORKER_VCPU_ID_1 / 64);
tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
308
flush_ex->hv_vp_set.bank_contents[0] = BIT_ULL(WORKER_VCPU_ID_1 % 64);
tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
309
flush_ex->hv_vp_set.bank_contents[1] = BIT_ULL(WORKER_VCPU_ID_2 % 64);
tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
324
flush_ex->hv_vp_set.valid_bank_mask = BIT_ULL(WORKER_VCPU_ID_1 / 64) |
tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
325
BIT_ULL(WORKER_VCPU_ID_2 / 64);
tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
326
flush_ex->hv_vp_set.bank_contents[0] = BIT_ULL(WORKER_VCPU_ID_1 % 64);
tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
327
flush_ex->hv_vp_set.bank_contents[1] = BIT_ULL(WORKER_VCPU_ID_2 % 64);
tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
432
flush_ex->hv_vp_set.valid_bank_mask = BIT_ULL(WORKER_VCPU_ID_2 / 64);
tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
433
flush_ex->hv_vp_set.bank_contents[0] = BIT_ULL(WORKER_VCPU_ID_2 % 64);
tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
448
flush_ex->hv_vp_set.valid_bank_mask = BIT_ULL(WORKER_VCPU_ID_2 / 64);
tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
449
flush_ex->hv_vp_set.bank_contents[0] = BIT_ULL(WORKER_VCPU_ID_2 % 64);
tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
467
flush_ex->hv_vp_set.valid_bank_mask = BIT_ULL(WORKER_VCPU_ID_2 / 64) |
tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
468
BIT_ULL(WORKER_VCPU_ID_1 / 64);
tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
469
flush_ex->hv_vp_set.bank_contents[0] = BIT_ULL(WORKER_VCPU_ID_1 % 64);
tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
470
flush_ex->hv_vp_set.bank_contents[1] = BIT_ULL(WORKER_VCPU_ID_2 % 64);
tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
486
flush_ex->hv_vp_set.valid_bank_mask = BIT_ULL(WORKER_VCPU_ID_1 / 64) |
tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
487
BIT_ULL(WORKER_VCPU_ID_2 / 64);
tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
488
flush_ex->hv_vp_set.bank_contents[0] = BIT_ULL(WORKER_VCPU_ID_1 % 64);
tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
489
flush_ex->hv_vp_set.bank_contents[1] = BIT_ULL(WORKER_VCPU_ID_2 % 64);
tools/testing/selftests/kvm/x86/nested_emulation_test.c
64
vmcb->control.intercept |= BIT_ULL(INTERCEPT_SHUTDOWN) |
tools/testing/selftests/kvm/x86/nested_emulation_test.c
65
BIT_ULL(INTERCEPT_PAUSE) |
tools/testing/selftests/kvm/x86/nested_emulation_test.c
66
BIT_ULL(INTERCEPT_HLT);
tools/testing/selftests/kvm/x86/nested_exceptions_test.c
50
#define INTERCEPT_SS (BIT_ULL(SS_VECTOR))
tools/testing/selftests/kvm/x86/nested_exceptions_test.c
51
#define INTERCEPT_SS_DF (INTERCEPT_SS | BIT_ULL(DF_VECTOR))
tools/testing/selftests/kvm/x86/nested_exceptions_test.c
52
#define INTERCEPT_SS_GP_DF (INTERCEPT_SS_DF | BIT_ULL(GP_VECTOR))
tools/testing/selftests/kvm/x86/nested_exceptions_test.c
98
ctrl->intercept |= BIT_ULL(INTERCEPT_SHUTDOWN);
tools/testing/selftests/kvm/x86/nested_vmsave_vmload_test.c
105
svm->vmcb->control.intercept &= ~(BIT_ULL(INTERCEPT_VMSAVE) |
tools/testing/selftests/kvm/x86/nested_vmsave_vmload_test.c
106
BIT_ULL(INTERCEPT_VMLOAD));
tools/testing/selftests/kvm/x86/nested_vmsave_vmload_test.c
79
svm->vmcb->control.intercept |= (BIT_ULL(INTERCEPT_VMSAVE) |
tools/testing/selftests/kvm/x86/nested_vmsave_vmload_test.c
80
BIT_ULL(INTERCEPT_VMLOAD));
tools/testing/selftests/kvm/x86/pmu_counters_test.c
298
wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, BIT_ULL(i));
tools/testing/selftests/kvm/x86/pmu_counters_test.c
539
if (i >= nr_fixed_counters && !(supported_bitmask & BIT_ULL(i))) {
tools/testing/selftests/kvm/x86/sev_init2_tests.c
112
if (!(supported_features & BIT_ULL(i)))
tools/testing/selftests/kvm/x86/sev_init2_tests.c
114
&(struct kvm_sev_init){ .vmsa_features = BIT_ULL(i) },
tools/testing/selftests/kvm/x86/sev_init2_tests.c
116
else if (KNOWN_FEATURES & BIT_ULL(i))
tools/testing/selftests/kvm/x86/sev_init2_tests.c
118
&(struct kvm_sev_init){ .vmsa_features = BIT_ULL(i) });
tools/testing/selftests/kvm/x86/smaller_maxphyaddr_emulation_test.c
75
*vm_get_pte(vm, MEM_REGION_GVA) |= BIT_ULL(MAXPHYADDR);
tools/testing/selftests/kvm/x86/state_test.c
192
wrmsr(MSR_IA32_BNDCFGS, BIT_ULL(0));
tools/testing/selftests/kvm/x86/ucna_injection_test.c
46
#define MCI_CTL2_RESERVED_BIT BIT_ULL(29)
tools/testing/selftests/kvm/x86/userspace_msr_exit_test.c
719
cap.args[0] = BIT_ULL(i);
tools/testing/selftests/kvm/x86/userspace_msr_exit_test.c
721
BIT_ULL(i), KVM_MSR_EXIT_REASON_VALID_MASK);
tools/testing/selftests/kvm/x86/userspace_msr_exit_test.c
748
filter.flags = BIT_ULL(i);
tools/testing/selftests/kvm/x86/userspace_msr_exit_test.c
750
BIT_ULL(i), KVM_MSR_FILTER_VALID_MASK);
tools/testing/selftests/kvm/x86/userspace_msr_exit_test.c
756
filter.ranges[0].flags = BIT_ULL(i);
tools/testing/selftests/kvm/x86/userspace_msr_exit_test.c
758
BIT_ULL(i), KVM_MSR_FILTER_RANGE_VALID_MASK);
tools/testing/selftests/kvm/x86/vmx_msrs_test.c
24
vcpu_set_msr(vcpu, msr_index, val & ~BIT_ULL(bit));
tools/testing/selftests/kvm/x86/vmx_msrs_test.c
38
vcpu_set_msr(vcpu, msr_index, val | BIT_ULL(bit));
tools/testing/selftests/kvm/x86/vmx_msrs_test.c
55
BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55));
tools/testing/selftests/kvm/x86/vmx_msrs_test.c
58
BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) |
tools/testing/selftests/kvm/x86/vmx_msrs_test.c
59
BIT_ULL(15) | BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30));
tools/testing/selftests/kvm/x86/vmx_pmu_caps_test.c
114
host_cap.capabilities ^ BIT_ULL(i));
tools/testing/selftests/kvm/x86/vmx_pmu_caps_test.c
116
host_cap.capabilities ^ BIT_ULL(i));
tools/testing/selftests/kvm/x86/vmx_pmu_caps_test.c
136
vcpu_set_msr(vcpu, MSR_IA32_PERF_CAPABILITIES, BIT_ULL(bit));
tools/testing/selftests/kvm/x86/vmx_pmu_caps_test.c
138
host_cap.capabilities & ~BIT_ULL(bit));
tools/testing/selftests/kvm/x86/vmx_pmu_caps_test.c
159
host_cap.capabilities ^ BIT_ULL(bit));
tools/testing/selftests/kvm/x86/vmx_pmu_caps_test.c
161
host_cap.capabilities & BIT_ULL(bit) ? "Setting" : "Clearing",
tools/testing/selftests/kvm/x86/vmx_pmu_caps_test.c
162
BIT_ULL(bit), bit);
tools/testing/selftests/kvm/x86/vmx_pmu_caps_test.c
228
r = _vcpu_set_msr(vcpu, MSR_IA32_PERF_CAPABILITIES, BIT_ULL(i));
tools/testing/selftests/kvm/x86/vmx_pmu_caps_test.c
230
i, BIT_ULL(i));
tools/testing/selftests/kvm/x86/vmx_pmu_caps_test.c
72
guest_test_perf_capabilities_gp(current_val ^ BIT_ULL(i));
tools/testing/selftests/kvm/x86/xcr0_cpuid_test.c
93
if (supported_xcr0 & BIT_ULL(i))
tools/testing/selftests/kvm/x86/xcr0_cpuid_test.c
96
vector = xsetbv_safe(0, supported_xcr0 | BIT_ULL(i));
tools/testing/selftests/kvm/x86/xcr0_cpuid_test.c
99
BIT_ULL(i), supported_xcr0, ex_str(vector));
tools/testing/selftests/mm/uffd-unit-tests.c
1469
uint64_t ioctls = 0, expected = BIT_ULL(_UFFDIO_WAKE);
tools/testing/selftests/mm/uffd-unit-tests.c
1493
expected |= BIT_ULL(_UFFDIO_COPY);
tools/testing/selftests/mm/uffd-unit-tests.c
1495
expected |= BIT_ULL(_UFFDIO_WRITEPROTECT);
tools/testing/selftests/mm/uffd-unit-tests.c
1497
expected |= BIT_ULL(_UFFDIO_CONTINUE);
tools/testing/selftests/mm/uffd-unit-tests.c
156
uffdio_api.features = BIT_ULL(63);
tools/testing/selftests/mm/uffd-unit-tests.c
17
#define MEM_ANON BIT_ULL(0)
tools/testing/selftests/mm/uffd-unit-tests.c
171
uffdio_api.features = BIT_ULL(0);
tools/testing/selftests/mm/uffd-unit-tests.c
18
#define MEM_SHMEM BIT_ULL(1)
tools/testing/selftests/mm/uffd-unit-tests.c
19
#define MEM_SHMEM_PRIVATE BIT_ULL(2)
tools/testing/selftests/mm/uffd-unit-tests.c
20
#define MEM_HUGETLB BIT_ULL(3)
tools/testing/selftests/mm/uffd-unit-tests.c
21
#define MEM_HUGETLB_PRIVATE BIT_ULL(4)
tools/testing/selftests/mm/vm_util.h
13
#define PM_SOFT_DIRTY BIT_ULL(55)
tools/testing/selftests/mm/vm_util.h
14
#define PM_MMAP_EXCLUSIVE BIT_ULL(56)
tools/testing/selftests/mm/vm_util.h
15
#define PM_UFFD_WP BIT_ULL(57)
tools/testing/selftests/mm/vm_util.h
16
#define PM_GUARD_REGION BIT_ULL(58)
tools/testing/selftests/mm/vm_util.h
17
#define PM_FILE BIT_ULL(61)
tools/testing/selftests/mm/vm_util.h
18
#define PM_SWAP BIT_ULL(62)
tools/testing/selftests/mm/vm_util.h
19
#define PM_PRESENT BIT_ULL(63)
tools/testing/selftests/mm/vm_util.h
21
#define KPF_COMPOUND_HEAD BIT_ULL(15)
tools/testing/selftests/mm/vm_util.h
22
#define KPF_COMPOUND_TAIL BIT_ULL(16)
tools/testing/selftests/mm/vm_util.h
23
#define KPF_HWPOISON BIT_ULL(19)
tools/testing/selftests/mm/vm_util.h
24
#define KPF_THP BIT_ULL(22)
