bin/csh/dir.c
340
char *tmp;
bin/csh/dir.c
343
if (chdir(tmp = short2str(dp->di_name)) == -1)
bin/csh/dir.c
344
stderror(ERR_SYSTEM, tmp, strerror(errno));
bin/csh/dir.c
473
char *tmp;
bin/csh/dir.c
479
if (chdir(tmp = short2str(dp->di_name)) == -1)
bin/csh/dir.c
480
stderror(ERR_SYSTEM, tmp, strerror(errno));
bin/csh/dir.c
494
char *tmp;
bin/csh/dir.c
496
if (chdir(tmp = short2str(dp->di_name)) == -1)
bin/csh/dir.c
497
stderror(ERR_SYSTEM, tmp, strerror(errno));
bin/csh/dir.c
565
char *tmp;
bin/csh/dir.c
569
if (chdir(tmp = short2str(p->di_name)) == -1)
bin/csh/dir.c
570
stderror(ERR_SYSTEM, tmp, strerror(errno));
bin/csh/dol.c
822
char tmp[] = "/tmp/sh.XXXXXXXX";
bin/csh/dol.c
824
if (mkstemp(tmp) == -1)
bin/csh/dol.c
825
stderror(ERR_SYSTEM, tmp, strerror(errno));
bin/csh/dol.c
826
(void) unlink(tmp); /* 0 0 inode! */
bin/csh/sem.c
524
char tmp[PATH_MAX];
bin/csh/sem.c
533
strlcpy(tmp, short2str(cp), sizeof tmp);
bin/csh/sem.c
535
if ((fd = open(tmp, O_RDONLY)) == -1)
bin/csh/sem.c
536
stderror(ERR_SYSTEM, tmp, strerror(errno));
bin/csh/sem.c
553
char tmp[PATH_MAX];
bin/csh/sem.c
556
strlcpy(tmp, short2str(cp), sizeof tmp);
bin/csh/sem.c
564
(fd = open(tmp, O_WRONLY | O_APPEND)) >= 0);
bin/csh/sem.c
568
stderror(ERR_SYSTEM, tmp, strerror(errno));
bin/csh/sem.c
569
chkclob(tmp);
bin/csh/sem.c
571
if ((fd = open(tmp, O_WRONLY | O_CREAT | O_TRUNC, 0666)) == -1)
bin/csh/sem.c
572
stderror(ERR_SYSTEM, tmp, strerror(errno));
bin/dd/args.c
106
tmp.name = oper;
bin/dd/args.c
107
if (!(ap = (struct arg *)bsearch(&tmp, args,
bin/dd/args.c
110
errx(1, "unknown operand %s", tmp.name);
bin/dd/args.c
113
tmp.name);
bin/dd/args.c
93
struct arg *ap, tmp;
bin/expr/expr.c
147
char *tmp;
bin/expr/expr.c
152
if (asprintf(&tmp, "%lld", vp->u.i) == -1)
bin/expr/expr.c
156
vp->u.s = tmp;
bin/ksh/emacs.c
1103
char tmp;
bin/ksh/emacs.c
1133
tmp = xcp[-1];
bin/ksh/emacs.c
1135
xcp[-2] = tmp;
bin/ksh/emacs.c
1143
tmp = xcp[-1];
bin/ksh/emacs.c
1145
xcp[0] = tmp;
bin/ksh/emacs.c
1638
char *tmp;
bin/ksh/emacs.c
1644
tmp = xmp;
bin/ksh/emacs.c
1646
x_goto( tmp );
bin/ksh/history.c
555
char **tmp;
bin/ksh/history.c
568
tmp = reallocarray(histbase, n + 1, sizeof(char *));
bin/ksh/history.c
569
if (tmp != NULL) {
bin/ksh/history.c
570
histbase = tmp;
bin/ksh/jobs.c
1564
Proc *p, *tmp;
bin/ksh/jobs.c
1579
tmp = p;
bin/ksh/jobs.c
1581
tmp->next = free_procs;
bin/ksh/jobs.c
1582
free_procs = tmp;
bin/ksh/jobs.c
838
Job *j, *tmp;
bin/ksh/jobs.c
871
for (j = job_list; j; j = tmp) {
bin/ksh/jobs.c
872
tmp = j->next;
bin/ksh/jobs.c
884
Job *j, *tmp;
bin/ksh/jobs.c
897
for (j = job_list; j; j = tmp) {
bin/ksh/jobs.c
898
tmp = j->next;
bin/ksh/lex.c
1199
char *tmp = special_prompt_expand(ps1);
bin/ksh/lex.c
1200
prompt = str_save(substitute(tmp, 0), saved_atemp);
bin/ksh/lex.c
1552
char *tmp, *p;
bin/ksh/lex.c
1554
if (!arraysub(&tmp))
bin/ksh/lex.c
1557
for (p = tmp; *p; ) {
bin/ksh/lex.c
1561
afree(tmp, ATEMP);
bin/ksh/lex.c
264
char *p, *tmp;
bin/ksh/lex.c
266
if (arraysub(&tmp)) {
bin/ksh/lex.c
269
for (p = tmp; *p; ) {
bin/ksh/lex.c
274
afree(tmp, ATEMP);
bin/ksh/lex.c
282
= s->u.freeme = tmp;
bin/ksh/misc.c
1027
int tmp = rows;
bin/ksh/misc.c
1030
cols = tmp;
bin/ksh/shf.c
738
int tmp = 0;
bin/ksh/shf.c
794
tmp = va_arg(args, int);
bin/ksh/shf.c
796
precision = tmp;
bin/ksh/shf.c
797
else if ((field = tmp) < 0) {
bin/ksh/shf.c
816
tmp = c - '0';
bin/ksh/shf.c
818
tmp = tmp * 10 + c - '0';
bin/ksh/shf.c
820
if (tmp < 0) /* overflow? */
bin/ksh/shf.c
821
tmp = 0;
bin/ksh/shf.c
823
precision = tmp;
bin/ksh/shf.c
825
field = tmp;
bin/ksh/shf.c
871
llnum = - (long long) llnum, tmp = 1;
bin/ksh/shf.c
873
tmp = 0;
bin/ksh/shf.c
883
if (tmp)
bin/ksh/var.c
146
char *sub, *tmp;
bin/ksh/var.c
151
tmp = str_nsave(p+1, len-2, ATEMP);
bin/ksh/var.c
152
sub = substitute(tmp, 0);
bin/ksh/var.c
153
afree(tmp, ATEMP);
bin/ksh/var.c
756
struct tbl *a, *tmp;
bin/ksh/var.c
760
tmp = a;
bin/ksh/var.c
762
if (tmp->flag & ALLOC)
bin/ksh/var.c
763
afree(tmp->val.s, tmp->areap);
bin/ksh/var.c
764
afree(tmp, tmp->areap);
bin/stty/cchar.c
100
c_cchar)) && !(cp = (struct cchar *)bsearch(&tmp, cchars2,
bin/stty/cchar.c
91
struct cchar *cp, tmp;
bin/stty/cchar.c
97
tmp.name = name;
bin/stty/cchar.c
98
if (!(cp = (struct cchar *)bsearch(&tmp, cchars1,
bin/stty/gfmt.c
101
tp->c_oflag = tmp;
bin/stty/gfmt.c
105
(void)sscanf(ep, "%ld", &tmp);
bin/stty/gfmt.c
106
tp->c_ospeed = tmp;
bin/stty/gfmt.c
111
tp->c_cc[cp->sub] = tmp;
bin/stty/gfmt.c
69
long tmp;
bin/stty/gfmt.c
80
(void)sscanf(ep, "%lx", &tmp);
bin/stty/gfmt.c
84
tp->c_cflag = tmp;
bin/stty/gfmt.c
88
tp->c_iflag = tmp;
bin/stty/gfmt.c
92
(void)sscanf(ep, "%ld", &tmp);
bin/stty/gfmt.c
93
tp->c_ispeed = tmp;
bin/stty/gfmt.c
97
tp->c_lflag = tmp;
bin/stty/key.c
112
struct key *kp, tmp;
bin/stty/key.c
121
tmp.name = name;
bin/stty/key.c
122
if (!(kp = (struct key *)bsearch(&tmp, keys,
bin/stty/key.c
203
int tmp = 0;
bin/stty/key.c
204
(void)ioctl(ip->fd, TIOCEXT, &tmp);
bin/stty/key.c
206
int tmp = 1;
bin/stty/key.c
207
(void)ioctl(ip->fd, TIOCEXT, &tmp);
bin/stty/key.c
323
int tmp;
bin/stty/key.c
325
tmp = TTYDISC;
bin/stty/key.c
326
if (ioctl(ip->fd, TIOCSETD, &tmp) == -1)
bin/stty/print.c
114
tmp = tp->c_iflag;
bin/stty/print.c
132
tmp = tp->c_oflag;
bin/stty/print.c
144
tmp = tp->c_cflag;
bin/stty/print.c
147
switch(tmp&CSIZE) {
bin/stty/print.c
51
long tmp;
bin/stty/print.c
86
#define on(f) ((tmp&f) != 0)
bin/stty/print.c
92
tmp = tp->c_lflag;
games/battlestar/save.c
107
tmp = location == dayfile;
games/battlestar/save.c
108
fwrite(&tmp, sizeof tmp, 1, fp);
games/battlestar/save.c
44
int tmp;
games/battlestar/save.c
54
fread(&tmp, sizeof tmp, 1, fp);
games/battlestar/save.c
55
location = tmp ? dayfile : nightfile;
games/battlestar/save.c
95
int tmp;
games/bcd/bcd.c
254
char tmp[1024];
games/bcd/bcd.c
257
if (fgets(tmp, sizeof(tmp), stdin) == NULL)
games/bcd/bcd.c
260
if (fgets(tmp, sizeof(tmp), stdin) == NULL)
games/bcd/bcd.c
267
if (fgets(tmp, sizeof(tmp), stdin) == NULL)
games/boggle/boggle/bog.c
588
char *tmp, **cubes;
games/boggle/boggle/bog.c
611
tmp = cubes[p];
games/boggle/boggle/bog.c
613
cubes[q] = tmp;
games/cribbage/io.c
304
int sum, tmp;
games/cribbage/io.c
320
tmp = 10 * sum + (*p - '0');
games/cribbage/io.c
322
if (tmp < sum) {
games/cribbage/io.c
328
sum = tmp;
games/fortune/strfile/strfile.c
432
int32_t tmp;
games/fortune/strfile/strfile.c
444
tmp = sp[0];
games/fortune/strfile/strfile.c
446
sp[i] = tmp;
games/hack/hack.apply.c
157
int tmp = dist(mtmp->mx,mtmp->my);
games/hack/hack.apply.c
162
if(tmp < 9 && !mtmp->isshk && rn2(4)) {
games/hack/hack.apply.c
166
if(tmp < 3) mtmp->mcansee = mtmp->mblinded = 0;
games/hack/hack.apply.c
169
tmp2 += rnd(1 + 50/tmp);
games/hack/hack.do.c
326
int tmp;
games/hack/hack.do.c
403
tmp = -1+u.ulevel+mon->data->ac+abon();
games/hack/hack.do.c
407
tmp -= 4;
games/hack/hack.do.c
409
tmp += uwep->spe;
games/hack/hack.do.c
412
if(obj->otyp == BOOMERANG) tmp += 4;
games/hack/hack.do.c
413
tmp += obj->spe;
games/hack/hack.do.c
414
if(u.uswallow || tmp >= rnd(20)) {
games/hack/hack.do.c
429
tmp = -1+u.ulevel+mon->data->ac+abon();
games/hack/hack.do.c
430
if(!Punished || obj != uball) tmp += 2;
games/hack/hack.do.c
431
if(u.utrap) tmp -= 2;
games/hack/hack.do.c
432
if(u.uswallow || tmp >= rnd(20)) {
games/hack/hack.dog.c
292
int tmp = rooms[(int)dogroom].fdoor;
games/hack/hack.dog.c
298
dist(doors[tmp].x, doors[tmp].y)){
games/hack/hack.dog.c
299
gx = doors[tmp].x;
games/hack/hack.dog.c
300
gy = doors[tmp].y;
games/hack/hack.dog.c
302
tmp++;
games/hack/hack.eat.c
168
int tmp;
games/hack/hack.eat.c
196
tmp = 1;
games/hack/hack.eat.c
200
tmp = 3;
games/hack/hack.eat.c
204
tmp = 6;
games/hack/hack.eat.c
225
tmp = 10 + rn2(1 + 500/((int)(u.ulevel + u.ustr)));
games/hack/hack.eat.c
227
tin.reqtime = tmp;
games/hack/hack.end.c
209
{ long int tmp;
games/hack/hack.end.c
210
tmp = u.ugold - u.ugold0;
games/hack/hack.end.c
211
if(tmp < 0)
games/hack/hack.end.c
212
tmp = 0;
games/hack/hack.end.c
214
tmp -= tmp/10;
games/hack/hack.end.c
215
u.urexp += tmp;
games/hack/hack.fight.c
206
int tmp;
games/hack/hack.fight.c
210
tmp = rnd(2); /* attack with bare hands */
games/hack/hack.fight.c
218
tmp = rnd(2);
games/hack/hack.fight.c
221
tmp = rnd(objects[obj->otyp].wldam);
games/hack/hack.fight.c
222
if(obj->otyp == TWO_HANDED_SWORD) tmp += d(2,6);
games/hack/hack.fight.c
223
else if(obj->otyp == FLAIL) tmp += rnd(4);
games/hack/hack.fight.c
225
tmp = rnd(objects[obj->otyp].wsdam);
games/hack/hack.fight.c
227
tmp += obj->spe;
games/hack/hack.fight.c
235
tmp++;
games/hack/hack.fight.c
240
tmp += rnd(10);
games/hack/hack.fight.c
243
tmp = rnd(25); break;
games/hack/hack.fight.c
255
tmp = 1;
games/hack/hack.fight.c
265
tmp = 1;
games/hack/hack.fight.c
270
tmp = obj->owt/10;
games/hack/hack.fight.c
271
if(tmp < 1) tmp = 1;
games/hack/hack.fight.c
272
else tmp = rnd(tmp);
games/hack/hack.fight.c
273
if(tmp > 6) tmp = 6;
games/hack/hack.fight.c
278
tmp += u.udaminc + dbon();
games/hack/hack.fight.c
280
if((tmp -= u.uswldtim) <= 0) {
games/hack/hack.fight.c
285
if(tmp < 1) tmp = 1;
games/hack/hack.fight.c
286
mon->mhp -= tmp;
games/hack/hack.fight.c
293
mon->mfleetim += 10*rnd(tmp);
games/hack/hack.fight.c
300
mon, exclam(tmp) );
games/hack/hack.fight.c
304
pline("You hit %s%s", monnam(mon), exclam(tmp));
games/hack/hack.fight.c
324
schar tmp;
games/hack/hack.fight.c
365
tmp = u.uluck + u.ulevel + mdat->ac + abon();
games/hack/hack.fight.c
368
tmp += uwep->spe;
games/hack/hack.fight.c
369
if(uwep->otyp == TWO_HANDED_SWORD) tmp -= 1;
games/hack/hack.fight.c
370
else if(uwep->otyp == DAGGER) tmp += 2;
games/hack/hack.fight.c
371
else if(uwep->otyp == CRYSKNIFE) tmp += 3;
games/hack/hack.fight.c
373
strchr("XDne", mdat->mlet)) tmp += 2;
games/hack/hack.fight.c
377
tmp += 2;
games/hack/hack.fight.c
380
tmp += 4;
games/hack/hack.fight.c
383
if(mtmp->mflee) tmp += 2;
games/hack/hack.fight.c
384
if(u.utrap) tmp -= 3;
games/hack/hack.fight.c
387
tmp -= (inv_weight() + 40)/20;
games/hack/hack.fight.c
389
if(tmp <= rnd(20) && !u.uswallow){
games/hack/hack.fight.c
81
schar tmp;
games/hack/hack.fight.c
86
tmp = pd->ac + pa->mlevel;
games/hack/hack.fight.c
88
tmp += 4;
games/hack/hack.fight.c
91
hit = (tmp > rnd(20));
games/hack/hack.lev.c
120
for(tmp=1; tmp<32; tmp++){
games/hack/hack.lev.c
121
for(wtmp = wsegs[tmp]; wtmp; wtmp = wtmp2){
games/hack/hack.lev.c
125
wsegs[tmp] = 0;
games/hack/hack.lev.c
212
int tmp;
games/hack/hack.lev.c
294
for(tmp = 1; tmp < 32; tmp++) if(wsegs[tmp]){
games/hack/hack.lev.c
295
wheads[tmp] = wsegs[tmp] = wtmp = newseg();
games/hack/hack.lev.c
299
wheads[tmp]->nseg = wtmp = newseg();
games/hack/hack.lev.c
300
wheads[tmp] = wtmp;
games/hack/hack.lev.c
87
int tmp;
games/hack/hack.makemon.c
100
if(!tmp--) goto gotmon;
games/hack/hack.makemon.c
81
int tmp, ct;
games/hack/hack.makemon.c
93
tmp = rn2(ct*dlevel/24 + 7);
games/hack/hack.makemon.c
94
if(tmp < dlevel - 4) tmp = rn2(ct*dlevel/24 + 12);
games/hack/hack.makemon.c
95
if(tmp >= ct) tmp = rn1(ct - ct/2, ct/2);
games/hack/hack.mhitu.c
123
tmp = hitu(mtmp,d(mdat->damn,mdat->damd));
games/hack/hack.mhitu.c
125
tmp = 0;
games/hack/hack.mhitu.c
127
tmp += hitu(mtmp,d(mdat->damn,mdat->damd));
games/hack/hack.mhitu.c
129
ctmp = tmp && !mtmp->mcan &&
games/hack/hack.mhitu.c
147
if(tmp) justswld(mtmp,"The trapper");
games/hack/hack.mhitu.c
150
if(tmp) justswld(mtmp, "The lurker above");
games/hack/hack.mhitu.c
236
tmp = hitu(mtmp,rnd(3));
games/hack/hack.mhitu.c
237
tmp &= hitu(mtmp,rnd(3));
games/hack/hack.mhitu.c
238
if(tmp){
games/hack/hack.mhitu.c
249
if(tmp) stealgold(mtmp);
games/hack/hack.mhitu.c
276
tmp = hitu(mtmp,rnd(6));
games/hack/hack.mhitu.c
277
if(hitu(mtmp,rnd(6)) && tmp && /* hits with both paws */
games/hack/hack.mhitu.c
298
if(tmp && uarmh && !uarmh->rustfree &&
games/hack/hack.mhitu.c
316
if(tmp && !rn2(8)) {
games/hack/hack.mhitu.c
340
if(tmp) u.uhp -= 4;
games/hack/hack.mhitu.c
348
if(tmp) wormhit(mtmp);
games/hack/hack.mhitu.c
384
int tmp, res;
games/hack/hack.mhitu.c
399
tmp = u.uac;
games/hack/hack.mhitu.c
401
if(tmp < 0) {
games/hack/hack.mhitu.c
402
dam += tmp; /* decrease damage */
games/hack/hack.mhitu.c
404
tmp = -rn2(-tmp);
games/hack/hack.mhitu.c
406
tmp += mtmp->data->mlevel;
games/hack/hack.mhitu.c
407
if(multi < 0) tmp += 4;
games/hack/hack.mhitu.c
408
if((Invis && mtmp->data->mlet != 'I') || !mtmp->mcansee) tmp -= 2;
games/hack/hack.mhitu.c
409
if(mtmp->mtrapped) tmp -= 2;
games/hack/hack.mhitu.c
410
if(tmp <= rnd(20)) {
games/hack/hack.mhitu.c
76
int tmp, ctmp;
games/hack/hack.mklev.c
415
int tmp;
games/hack/hack.mklev.c
424
if(broom->hx < 0) tmp = doorindex; else
games/hack/hack.mklev.c
425
for(tmp = doorindex; tmp > broom->fdoor; tmp--)
games/hack/hack.mklev.c
426
doors[tmp] = doors[tmp-1];
games/hack/hack.mklev.c
428
doors[tmp].x = x;
games/hack/hack.mklev.c
429
doors[tmp].y = y;
games/hack/hack.mon.c
220
int tmp, nearby, scared;
games/hack/hack.mon.c
283
tmp = m_move(mtmp,0); /* 2: monster died moving */
games/hack/hack.mon.c
284
if(tmp == 2 || (tmp && mdat->mmove <= 12))
games/hack/hack.mon.c
285
return(tmp == 2);
games/hack/hack.mon.c
294
if(mdat->mmove-12 > rnd(12)) tmp = m_move(mtmp,1);
games/hack/hack.mon.c
295
return(tmp == 2);
games/hack/hack.mon.c
730
int tmp, nk, x, y;
games/hack/hack.mon.c
748
tmp = mdat - mons; /* index in mons array (if not 'd', '@', ...) */
games/hack/hack.mon.c
749
if(tmp >= 0 && tmp < CMNUM+2) {
games/hack/hack.mon.c
751
u.nr_killed[tmp]++;
games/hack/hack.mon.c
752
if((nk = u.nr_killed[tmp]) > MAXMONNO &&
games/hack/hack.mon.c
764
tmp = 1 + mdat->mlevel * mdat->mlevel;
games/hack/hack.mon.c
765
if(mdat->ac < 3) tmp += 2*(7 - mdat->ac);
games/hack/hack.mon.c
767
tmp += 2*mdat->mlevel;
games/hack/hack.mon.c
768
if(strchr("DeV&P",mdat->mlet)) tmp += (7*mdat->mlevel);
games/hack/hack.mon.c
769
if(mdat->mlevel > 6) tmp += 50;
games/hack/hack.mon.c
770
if(mdat->mlet == ';') tmp += 1000;
games/hack/hack.mon.c
781
if(u.uexp + 1 + (tmp + ((tmp2 <= 0) ? 0 : 4<<(tmp2-1)))/nk
games/hack/hack.mon.c
786
tmp = (tmp + ((tmp2 < 0) ? 0 : 4<<tmp2))/nk;
games/hack/hack.mon.c
787
if(!tmp) tmp = 1;
games/hack/hack.mon.c
793
more_experienced(tmp,0);
games/hack/hack.mon.c
797
tmp = rnd(10);
games/hack/hack.mon.c
798
if(tmp < 3) tmp = rnd(10);
games/hack/hack.mon.c
799
u.uhpmax += tmp;
games/hack/hack.mon.c
800
u.uhp += tmp;
games/hack/hack.mon.c
807
tmp = mdat->mlet;
games/hack/hack.mon.c
808
if(tmp == 'm') { /* he killed a minotaur, give him a wand of digging */
games/hack/hack.mon.c
815
if(tmp == 'w') {
games/hack/hack.mon.c
820
if(!letter(tmp) || (!strchr("mw", tmp) && !rn2(3))) tmp = 0;
games/hack/hack.mon.c
825
struct obj *obj2 = mkobj_at(tmp,x,y);
games/hack/hack.o_init.c
124
tmp = objects[j].oc_descr;
games/hack/hack.o_init.c
126
objects[i].oc_descr = tmp;
games/hack/hack.o_init.c
87
char let, *tmp;
games/hack/hack.pri.c
421
char tmp;
games/hack/hack.pri.c
424
if(!room->seen) tmp = ' ';
games/hack/hack.pri.c
425
else if(room->typ == POOL) tmp = POOL_SYM;
games/hack/hack.pri.c
426
else if(!Blind && (otmp = o_at(x,y))) tmp = otmp->olet;
games/hack/hack.pri.c
427
else if(!Blind && g_at(x,y)) tmp = '$';
games/hack/hack.pri.c
428
else if(x == xupstair && y == yupstair) tmp = '<';
games/hack/hack.pri.c
429
else if(x == xdnstair && y == ydnstair) tmp = '>';
games/hack/hack.pri.c
430
else if((ttmp = t_at(x,y)) && ttmp->tseen) tmp = '^';
games/hack/hack.pri.c
434
tmp = room->scrsym; /* %% wrong after killing mimic ! */
games/hack/hack.pri.c
437
tmp = '-';
games/hack/hack.pri.c
440
tmp = '|';
games/hack/hack.pri.c
444
tmp = '+';
games/hack/hack.pri.c
447
tmp = CORR_SYM;
games/hack/hack.pri.c
450
if(room->lit || cansee(x,y) || Blind) tmp = '.';
games/hack/hack.pri.c
451
else tmp = ' ';
games/hack/hack.pri.c
459
tmp = ERRCHAR;
games/hack/hack.pri.c
461
return(tmp);
games/hack/hack.save.c
100
int tmp; /* not register ! */
games/hack/hack.save.c
115
tmp = getuid();
games/hack/hack.save.c
116
bwrite(fd, &tmp, sizeof tmp);
games/hack/hack.save.c
128
for(tmp = 1; tmp <= maxdlevel; tmp++) {
games/hack/hack.save.c
132
if(tmp == dlevel || !level_exists[tmp]) continue;
games/hack/hack.save.c
133
glo(tmp);
games/hack/hack.save.c
141
getlev(ofd, hackpid, tmp);
games/hack/hack.save.c
143
bwrite(fd, &tmp, sizeof tmp); /* level number */
games/hack/hack.save.c
144
savelev(fd,tmp); /* actual level */
games/hack/hack.save.c
159
int tmp; /* not a register ! */
games/hack/hack.save.c
172
mread(fd, (char *) &tmp, sizeof tmp);
games/hack/hack.save.c
173
if(tmp != getuid()) { /* strange ... */
games/hack/hack.save.c
192
if(read(fd, (char *) &tmp, sizeof tmp) != sizeof tmp)
games/hack/hack.save.c
194
getlev(fd, 0, tmp);
games/hack/hack.save.c
195
glo(tmp);
games/hack/hack.save.c
198
savelev(nfd,tmp);
games/hack/hack.shk.c
430
pay(long tmp, struct monst *shkp)
games/hack/hack.shk.c
434
u.ugold -= tmp;
games/hack/hack.shk.c
435
shkp->mgold += tmp;
games/hack/hack.shk.c
438
robbed -= tmp;
games/hack/hack.shk.c
450
int pass, tmp;
games/hack/hack.shk.c
541
tmp = 0;
games/hack/hack.shk.c
542
while(tmp < ESHK(shopkeeper)->billct) {
games/hack/hack.shk.c
543
bp = &bill[tmp];
games/hack/hack.shk.c
545
tmp++;
games/hack/hack.shk.c
549
bill[tmp] = bill[--ESHK(shopkeeper)->billct];
games/hack/hack.shk.c
680
int tmp;
games/hack/hack.shk.c
697
tmp = bp->price;
games/hack/hack.shk.c
702
bp->price = tmp;
games/hack/hack.shk.c
711
int tmp;
games/hack/hack.shk.c
746
((tmp = shtypes[rooms[ESHK(shopkeeper)->shoproom].rtype-8]) && tmp != obj->olet)
games/hack/hack.shk.c
841
int tmp, ac;
games/hack/hack.shk.c
845
tmp = 10*rnd(500);
games/hack/hack.shk.c
848
tmp = 10*rnd((obj->otyp == EXPENSIVE_CAMERA) ? 150 : 30);
games/hack/hack.shk.c
851
tmp = 10*rnd(100);
games/hack/hack.shk.c
854
tmp = 10*rnd(100);
games/hack/hack.shk.c
857
tmp = 10*rnd(50);
games/hack/hack.shk.c
860
tmp = rnd(5);
games/hack/hack.shk.c
864
tmp = 10*rnd(50);
games/hack/hack.shk.c
867
tmp = 10*rnd(5 + (2000/realhunger()));
games/hack/hack.shk.c
870
tmp = 10*rnd(20);
games/hack/hack.shk.c
876
tmp = 100 + ac*ac*rnd(10+ac);
games/hack/hack.shk.c
880
tmp = 5*rnd(10);
games/hack/hack.shk.c
883
tmp = 10*rnd(150);
games/hack/hack.shk.c
884
else tmp = 10*rnd(75);
games/hack/hack.shk.c
889
tmp = 10;
games/hack/hack.shk.c
892
tmp = 10000;
games/hack/hack.shk.c
894
return(tmp);
games/hack/hack.shk.c
901
int tmp = u.uhunger;
games/hack/hack.shk.c
906
tmp += objects[otmp->otyp].nutrition;
games/hack/hack.shk.c
909
return((tmp <= 0) ? 1 : tmp);
games/hack/hack.steal.c
139
int tmp;
games/hack/hack.steal.c
150
tmp = 0;
games/hack/hack.steal.c
152
tmp += ((otmp->owornmask & (W_ARMOR | W_RING)) ? 5 : 1);
games/hack/hack.steal.c
153
tmp = rn2(tmp);
games/hack/hack.steal.c
155
if((tmp -= ((otmp->owornmask & (W_ARMOR | W_RING)) ? 5 : 1))
games/hack/hack.steal.c
259
long tmp;
games/hack/hack.steal.c
261
tmp = (mtmp->mgold > 10000) ? 10000 : mtmp->mgold;
games/hack/hack.steal.c
262
mkgold((long)(tmp + d(dlevel,30)), mtmp->mx, mtmp->my);
games/hack/hack.steal.c
82
long tmp;
games/hack/hack.steal.c
95
u.ugold -= (tmp = somegold());
games/hack/hack.steal.c
97
mtmp->mgold += tmp;
games/hack/hack.unix.c
373
int tmp = rooms[uroom].fdoor;
games/hack/hack.unix.c
377
if(dist(fx,fy) < dist(doors[tmp].x, doors[tmp].y)){
games/hack/hack.unix.c
378
fx = doors[tmp].x;
games/hack/hack.unix.c
379
fy = doors[tmp].y;
games/hack/hack.unix.c
381
tmp++;
games/hack/hack.unix.c
386
tmp = fx; fx = md->mx; md->mx = tmp;
games/hack/hack.unix.c
387
tmp = fy; fy = md->my; md->my = tmp;
games/hack/hack.vault.c
166
int tmp = inroom(u.ux, u.uy);
games/hack/hack.vault.c
168
if(tmp < 0 || rooms[tmp].rtype != VAULT) {
games/hack/hack.worm.c
107
int tmp = mtmp->wormno;
games/hack/hack.worm.c
114
(whd = wheads[tmp])->nseg = wtmp;
games/hack/hack.worm.c
115
wheads[tmp] = wtmp;
games/hack/hack.worm.c
121
if(wgrowtime[tmp] <= moves) {
games/hack/hack.worm.c
122
if(!wgrowtime[tmp]) wgrowtime[tmp] = moves + rnd(5);
games/hack/hack.worm.c
123
else wgrowtime[tmp] += 2+rnd(15);
games/hack/hack.worm.c
128
whd = wsegs[tmp];
games/hack/hack.worm.c
129
wsegs[tmp] = whd->nseg;
games/hack/hack.worm.c
136
int tmp;
games/hack/hack.worm.c
139
tmp = mtmp->wormno;
games/hack/hack.worm.c
140
wtmp = wsegs[tmp];
games/hack/hack.worm.c
141
if(wtmp == wheads[tmp]) return;
games/hack/hack.worm.c
143
wsegs[tmp] = wtmp->nseg;
games/hack/hack.worm.c
151
int tmp = mtmp->wormno;
games/hack/hack.worm.c
154
if(!tmp) return;
games/hack/hack.worm.c
156
for(wtmp = wsegs[tmp]; wtmp; wtmp = wtmp2){
games/hack/hack.worm.c
160
wsegs[tmp] = 0;
games/hack/hack.worm.c
166
int tmp = mtmp->wormno;
games/hack/hack.worm.c
169
if(!tmp) return; /* worm without tail */
games/hack/hack.worm.c
170
for(wtmp = wsegs[tmp]; wtmp; wtmp = wtmp->nseg)
games/hack/hack.worm.c
175
wormsee(unsigned tmp)
games/hack/hack.worm.c
177
struct wseg *wtmp = wsegs[tmp];
games/hack/hack.worm.c
202
int tmp,tmp2;
games/hack/hack.worm.c
206
tmp = rnd(20);
games/hack/hack.worm.c
208
weptyp == AXE) tmp += 5;
games/hack/hack.worm.c
209
if(tmp < 12) return;
games/hack/hack.worm.c
212
tmp = mtmp->wormno;
games/hack/hack.worm.c
213
wtmp = wsegs[tmp];
games/hack/hack.worm.c
215
wsegs[tmp] = wtmp->nseg;
games/hack/hack.worm.c
231
wsegs[tmp2] = wsegs[tmp];
games/hack/hack.worm.c
237
wsegs[tmp] = wtmp->nseg->nseg;
games/hack/hack.worm.c
78
int tmp;
games/hack/hack.worm.c
80
for(tmp=1; tmp<32; tmp++) if(!wsegs[tmp]) {
games/hack/hack.worm.c
81
mtmp->wormno = tmp;
games/hack/hack.worm.c
92
int tmp = mtmp->wormno;
games/hack/hack.worm.c
94
if(!tmp) return;
games/hack/hack.worm.c
95
wheads[tmp] = wsegs[tmp] = wtmp = newseg();
games/hack/hack.worm.c
96
wgrowtime[tmp] = 0;
games/hack/hack.zap.c
478
int tmp;
games/hack/hack.zap.c
481
tmp = zhit(u.ustuck, type);
games/hack/hack.zap.c
483
fltxt, monnam(u.ustuck), exclam(tmp));
games/hack/hack.zap.c
534
int tmp = zhit(mon,abstype);
games/hack/hack.zap.c
544
hit(fltxt, mon, exclam(tmp));
games/hack/hack.zap.c
619
int tmp = 0;
games/hack/hack.zap.c
623
tmp = d(2,6);
games/hack/hack.zap.c
628
tmp = d(6,6);
games/hack/hack.zap.c
629
if(strchr("YF", mon->data->mlet)) tmp += 7;
games/hack/hack.zap.c
636
tmp = d(6,6);
games/hack/hack.zap.c
637
if(mon->data->mlet == 'D') tmp += 7;
games/hack/hack.zap.c
641
tmp = mon->mhp+1;
games/hack/hack.zap.c
644
mon->mhp -= tmp;
games/hack/hack.zap.c
645
return(tmp);
games/hack/hack.zap.c
93
int tmp = d(2,12);
games/hack/hack.zap.c
94
hit("wand", mtmp, exclam(tmp));
games/hack/hack.zap.c
95
mtmp->mhp -= tmp;
games/hack/rnd.c
89
int tmp = n;
games/hack/rnd.c
91
while(n--) tmp += RND(x);
games/hack/rnd.c
92
return(tmp);
games/number/number.c
198
char tmp[2];
games/number/number.c
222
j = strlen(part2); tmp[1] = '\0';
games/number/number.c
224
tmp[0] = part2[i];
games/number/number.c
225
convert(tmp);
games/sail/sync.c
140
struct stat tmp;
games/sail/sync.c
147
if (stat(sync_file, &tmp) == -1) {
games/snake/snake.c
504
struct highscore tmp;
games/snake/snake.c
533
memcpy(&tmp, &scores[rank], sizeof(struct highscore));
games/snake/snake.c
536
memcpy(&scores[rank + 1], &tmp, sizeof(struct highscore));
games/snake/snake.c
801
struct point tmp;
games/snake/snake.c
813
tmp.col = snake[5].col;
games/snake/snake.c
814
tmp.line = snake[5].line;
games/snake/snake.c
821
if ((same(&snake[i], &you)) || (same(&tmp, &you))) {
games/tetris/tetris.c
140
const struct shape *tmp;
games/tetris/tetris.c
143
tmp = &shapes[arc4random_uniform(7)];
games/tetris/tetris.c
146
tmp = &shapes[classic? tmp->rotc : tmp->rot];
games/tetris/tetris.c
147
return (tmp);
games/worm/worm.c
378
struct body *tmp;
games/worm/worm.c
380
if ((tmp = malloc(sizeof (struct body))) == NULL) {
games/worm/worm.c
384
return (tmp);
lib/libagentx/agentx.c
3960
char *tmp;
lib/libagentx/agentx.c
3971
tmp = recallocarray(*dst, buflen, nbuflen, sizeof(*tmp));
lib/libagentx/agentx.c
3972
if (tmp == NULL)
lib/libagentx/agentx.c
3974
*dst = tmp;
lib/libc/arch/powerpc/gen/flt_rounds.c
53
double tmp;
lib/libc/arch/powerpc/gen/flt_rounds.c
56
__asm__ volatile("mffs %0; stfiwx %0,0,%1" : "=f"(tmp): "b"(&x));
lib/libc/arch/powerpc64/gen/flt_rounds.c
53
double tmp;
lib/libc/arch/powerpc64/gen/flt_rounds.c
56
__asm__ volatile("mffs %0; stfiwx %0,0,%1" : "=f"(tmp): "b"(&x));
lib/libc/asr/asr_debug.c
104
print_dname(rr->rr.soa.mname, tmp, sizeof tmp),
lib/libc/asr/asr_debug.c
116
&rr->rr.in_a.addr, tmp, sizeof tmp));
lib/libc/asr/asr_debug.c
122
&rr->rr.in_aaaa.addr6, tmp, sizeof tmp));
lib/libc/asr/asr_debug.c
65
char tmp[256];
lib/libc/asr/asr_debug.c
72
print_dname(rr->rr_dname, tmp, sizeof tmp),
lib/libc/asr/asr_debug.c
94
print_dname(rr->rr.mx.exchange, tmp, sizeof tmp));
lib/libc/asr/getnameinfo.c
50
char tmp[sizeof("ffff:ffff:ffff:ffff:ffff:ffff:255.255.255.255")];
lib/libc/asr/getnameinfo.c
67
if (inet_ntop(sa->sa_family, addr, tmp, sizeof(tmp)) == NULL)
lib/libc/asr/getnameinfo.c
70
s = strlcpy(buf, tmp, buflen);
lib/libc/crypt/chacha_private.h
118
for (i = 0;i < bytes;++i) tmp[i] = m[i];
lib/libc/crypt/chacha_private.h
119
m = tmp;
lib/libc/crypt/chacha_private.h
121
c = tmp;
lib/libc/crypt/chacha_private.h
94
u8 tmp[64];
lib/libc/db/btree/bt_open.c
211
if ((t->bt_fd = tmp()) == -1)
lib/libc/db/btree/bt_open.c
64
static int tmp(void);
lib/libc/gen/fts.c
257
FTSENT *p, *tmp;
lib/libc/gen/fts.c
352
next: tmp = p;
lib/libc/gen/fts.c
354
free(tmp);
lib/libc/gen/fts.c
396
p = tmp->fts_parent;
lib/libc/gen/fts.c
397
free(tmp);
lib/libc/gen/getcap.c
1089
char *cp, tmp;
lib/libc/gen/getcap.c
1095
tmp = *(cp + 1);
lib/libc/gen/getcap.c
1098
*(cp + 1) = tmp;
lib/libc/gen/tree.c
102
struct rb_entry *tmp;
lib/libc/gen/tree.c
104
tmp = RBE_RIGHT(rbe);
lib/libc/gen/tree.c
105
RBE_RIGHT(rbe) = RBE_LEFT(tmp);
lib/libc/gen/tree.c
107
RBE_PARENT(RBE_LEFT(tmp)) = rbe;
lib/libc/gen/tree.c
110
RBE_PARENT(tmp) = parent;
lib/libc/gen/tree.c
113
RBE_LEFT(parent) = tmp;
lib/libc/gen/tree.c
115
RBE_RIGHT(parent) = tmp;
lib/libc/gen/tree.c
117
RBH_ROOT(rbt) = tmp;
lib/libc/gen/tree.c
119
RBE_LEFT(tmp) = rbe;
lib/libc/gen/tree.c
120
RBE_PARENT(rbe) = tmp;
lib/libc/gen/tree.c
124
rbe_augment(t, tmp);
lib/libc/gen/tree.c
125
parent = RBE_PARENT(tmp);
lib/libc/gen/tree.c
136
struct rb_entry *tmp;
lib/libc/gen/tree.c
138
tmp = RBE_LEFT(rbe);
lib/libc/gen/tree.c
139
RBE_LEFT(rbe) = RBE_RIGHT(tmp);
lib/libc/gen/tree.c
141
RBE_PARENT(RBE_RIGHT(tmp)) = rbe;
lib/libc/gen/tree.c
144
RBE_PARENT(tmp) = parent;
lib/libc/gen/tree.c
147
RBE_LEFT(parent) = tmp;
lib/libc/gen/tree.c
149
RBE_RIGHT(parent) = tmp;
lib/libc/gen/tree.c
151
RBH_ROOT(rbt) = tmp;
lib/libc/gen/tree.c
153
RBE_RIGHT(tmp) = rbe;
lib/libc/gen/tree.c
154
RBE_PARENT(rbe) = tmp;
lib/libc/gen/tree.c
158
rbe_augment(t, tmp);
lib/libc/gen/tree.c
159
parent = RBE_PARENT(tmp);
lib/libc/gen/tree.c
169
struct rb_entry *parent, *gparent, *tmp;
lib/libc/gen/tree.c
176
tmp = RBE_RIGHT(gparent);
lib/libc/gen/tree.c
177
if (tmp != NULL && RBE_COLOR(tmp) == RB_RED) {
lib/libc/gen/tree.c
178
RBE_COLOR(tmp) = RB_BLACK;
lib/libc/gen/tree.c
186
tmp = parent;
lib/libc/gen/tree.c
188
rbe = tmp;
lib/libc/gen/tree.c
194
tmp = RBE_LEFT(gparent);
lib/libc/gen/tree.c
195
if (tmp != NULL && RBE_COLOR(tmp) == RB_RED) {
lib/libc/gen/tree.c
196
RBE_COLOR(tmp) = RB_BLACK;
lib/libc/gen/tree.c
204
tmp = parent;
lib/libc/gen/tree.c
206
rbe = tmp;
lib/libc/gen/tree.c
221
struct rb_entry *tmp;
lib/libc/gen/tree.c
226
tmp = RBE_RIGHT(parent);
lib/libc/gen/tree.c
227
if (RBE_COLOR(tmp) == RB_RED) {
lib/libc/gen/tree.c
228
rbe_set_blackred(tmp, parent);
lib/libc/gen/tree.c
230
tmp = RBE_RIGHT(parent);
lib/libc/gen/tree.c
232
if ((RBE_LEFT(tmp) == NULL ||
lib/libc/gen/tree.c
233
RBE_COLOR(RBE_LEFT(tmp)) == RB_BLACK) &&
lib/libc/gen/tree.c
234
(RBE_RIGHT(tmp) == NULL ||
lib/libc/gen/tree.c
235
RBE_COLOR(RBE_RIGHT(tmp)) == RB_BLACK)) {
lib/libc/gen/tree.c
236
RBE_COLOR(tmp) = RB_RED;
lib/libc/gen/tree.c
240
if (RBE_RIGHT(tmp) == NULL ||
lib/libc/gen/tree.c
241
RBE_COLOR(RBE_RIGHT(tmp)) == RB_BLACK) {
lib/libc/gen/tree.c
244
oleft = RBE_LEFT(tmp);
lib/libc/gen/tree.c
248
RBE_COLOR(tmp) = RB_RED;
lib/libc/gen/tree.c
249
rbe_rotate_right(t, rbt, tmp);
lib/libc/gen/tree.c
250
tmp = RBE_RIGHT(parent);
lib/libc/gen/tree.c
253
RBE_COLOR(tmp) = RBE_COLOR(parent);
lib/libc/gen/tree.c
255
if (RBE_RIGHT(tmp))
lib/libc/gen/tree.c
256
RBE_COLOR(RBE_RIGHT(tmp)) = RB_BLACK;
lib/libc/gen/tree.c
263
tmp = RBE_LEFT(parent);
lib/libc/gen/tree.c
264
if (RBE_COLOR(tmp) == RB_RED) {
lib/libc/gen/tree.c
265
rbe_set_blackred(tmp, parent);
lib/libc/gen/tree.c
267
tmp = RBE_LEFT(parent);
lib/libc/gen/tree.c
270
if ((RBE_LEFT(tmp) == NULL ||
lib/libc/gen/tree.c
271
RBE_COLOR(RBE_LEFT(tmp)) == RB_BLACK) &&
lib/libc/gen/tree.c
272
(RBE_RIGHT(tmp) == NULL ||
lib/libc/gen/tree.c
273
RBE_COLOR(RBE_RIGHT(tmp)) == RB_BLACK)) {
lib/libc/gen/tree.c
274
RBE_COLOR(tmp) = RB_RED;
lib/libc/gen/tree.c
278
if (RBE_LEFT(tmp) == NULL ||
lib/libc/gen/tree.c
279
RBE_COLOR(RBE_LEFT(tmp)) == RB_BLACK) {
lib/libc/gen/tree.c
282
oright = RBE_RIGHT(tmp);
lib/libc/gen/tree.c
286
RBE_COLOR(tmp) = RB_RED;
lib/libc/gen/tree.c
287
rbe_rotate_left(t, rbt, tmp);
lib/libc/gen/tree.c
288
tmp = RBE_LEFT(parent);
lib/libc/gen/tree.c
291
RBE_COLOR(tmp) = RBE_COLOR(parent);
lib/libc/gen/tree.c
293
if (RBE_LEFT(tmp) != NULL)
lib/libc/gen/tree.c
294
RBE_COLOR(RBE_LEFT(tmp)) = RB_BLACK;
lib/libc/gen/tree.c
318
struct rb_entry *tmp;
lib/libc/gen/tree.c
321
while ((tmp = RBE_LEFT(rbe)) != NULL)
lib/libc/gen/tree.c
322
rbe = tmp;
lib/libc/gen/tree.c
342
tmp = RBE_PARENT(old);
lib/libc/gen/tree.c
343
if (tmp != NULL) {
lib/libc/gen/tree.c
344
if (RBE_LEFT(tmp) == old)
lib/libc/gen/tree.c
345
RBE_LEFT(tmp) = rbe;
lib/libc/gen/tree.c
347
RBE_RIGHT(tmp) = rbe;
lib/libc/gen/tree.c
349
rbe_if_augment(t, tmp);
lib/libc/gen/tree.c
358
tmp = parent;
lib/libc/gen/tree.c
360
rbe_augment(t, tmp);
lib/libc/gen/tree.c
361
tmp = RBE_PARENT(tmp);
lib/libc/gen/tree.c
362
} while (tmp != NULL);
lib/libc/gen/tree.c
405
struct rb_entry *tmp;
lib/libc/gen/tree.c
410
tmp = RBH_ROOT(rbt);
lib/libc/gen/tree.c
411
while (tmp != NULL) {
lib/libc/gen/tree.c
412
parent = tmp;
lib/libc/gen/tree.c
414
node = rb_e2n(t, tmp);
lib/libc/gen/tree.c
417
tmp = RBE_LEFT(tmp);
lib/libc/gen/tree.c
419
tmp = RBE_RIGHT(tmp);
lib/libc/gen/tree.c
446
struct rb_entry *tmp = RBH_ROOT(rbt);
lib/libc/gen/tree.c
450
while (tmp != NULL) {
lib/libc/gen/tree.c
451
node = rb_e2n(t, tmp);
lib/libc/gen/tree.c
454
tmp = RBE_LEFT(tmp);
lib/libc/gen/tree.c
456
tmp = RBE_RIGHT(tmp);
lib/libc/gen/tree.c
469
struct rb_entry *tmp = RBH_ROOT(rbt);
lib/libc/gen/tree.c
474
while (tmp != NULL) {
lib/libc/gen/tree.c
475
node = rb_e2n(t, tmp);
lib/libc/gen/tree.c
479
tmp = RBE_LEFT(tmp);
lib/libc/gen/tree.c
481
tmp = RBE_RIGHT(tmp);
lib/libc/net/inet_net_pton.c
103
tmp = n;
lib/libc/net/inet_net_pton.c
105
tmp = (tmp << 4) | n;
lib/libc/net/inet_net_pton.c
109
*dst++ = (u_char) tmp;
lib/libc/net/inet_net_pton.c
116
*dst++ = (u_char) (tmp << 4);
lib/libc/net/inet_net_pton.c
121
tmp = 0;
lib/libc/net/inet_net_pton.c
125
tmp *= 10;
lib/libc/net/inet_net_pton.c
126
tmp += n;
lib/libc/net/inet_net_pton.c
127
if (tmp > 255)
lib/libc/net/inet_net_pton.c
133
*dst++ = (u_char) tmp;
lib/libc/net/inet_net_pton.c
85
int n, ch, tmp, dirty, bits;
lib/libc/net/inet_net_pton.c
94
tmp = 0, dirty = 0;
lib/libc/net/inet_ntop.c
103
char tmp[sizeof "ffff:ffff:ffff:ffff:ffff:ffff:255.255.255.255"];
lib/libc/net/inet_ntop.c
144
tp = tmp;
lib/libc/net/inet_ntop.c
145
ep = tmp + sizeof(tmp);
lib/libc/net/inet_ntop.c
199
if ((size_t)(tp - tmp) > size) {
lib/libc/net/inet_ntop.c
203
strlcpy(dst, tmp, size);
lib/libc/net/inet_ntop.c
74
char tmp[sizeof "255.255.255.255"];
lib/libc/net/inet_ntop.c
77
l = snprintf(tmp, sizeof(tmp), "%u.%u.%u.%u",
lib/libc/net/inet_ntop.c
83
strlcpy(dst, tmp, size);
lib/libc/net/inet_pton.c
107
memcpy(dst, tmp, INADDRSZ);
lib/libc/net/inet_pton.c
128
u_char tmp[IN6ADDRSZ], *tp, *endp, *colonp;
lib/libc/net/inet_pton.c
133
memset((tp = tmp), '\0', IN6ADDRSZ);
lib/libc/net/inet_pton.c
211
memcpy(dst, tmp, IN6ADDRSZ);
lib/libc/net/inet_pton.c
77
u_char tmp[INADDRSZ], *tp;
lib/libc/net/inet_pton.c
81
*(tp = tmp) = 0;
lib/libc/net/res_random.c
138
u_int left, right, tmp;
lib/libc/net/res_random.c
153
tmp = ru_prf->prf8[(i << (8 - 1)) | right] & 0x7f;
lib/libc/net/res_random.c
155
tmp = ru_prf->prf7[((i - 1) << (7 - 1)) | right];
lib/libc/net/res_random.c
156
tmp ^= left;
lib/libc/net/res_random.c
158
right = tmp;
lib/libc/net/res_random.c
176
u_int32_t tmp;
lib/libc/net/res_random.c
183
tmp = arc4random();
lib/libc/net/res_random.c
184
ru_seed = (tmp >> 16) & 0x7FFF;
lib/libc/net/res_random.c
185
ru_seed2 = tmp & 0x7FFF;
lib/libc/net/res_random.c
188
tmp = arc4random();
lib/libc/net/res_random.c
189
ru_b = (tmp & 0xfffe) | 1;
lib/libc/net/res_random.c
190
ru_a = pmod(RU_AGEN, (tmp >> 16) & 0xfffe, RU_M);
lib/libc/quad/fixunsdfdi.c
50
unsigned int tmp;
lib/libc/quad/fixunsdfdi.c
68
tmp = x / ONE;
lib/libc/quad/fixunsdfdi.c
69
t.ul[L] = (unsigned int) (x - tmp * ONE);
lib/libc/quad/fixunsdfdi.c
70
t.ul[H] = tmp;
lib/libc/quad/qdivrem.c
108
tmp.uq = uq;
lib/libc/quad/qdivrem.c
110
u[1] = (digit)HHALF(tmp.ul[H]);
lib/libc/quad/qdivrem.c
111
u[2] = (digit)LHALF(tmp.ul[H]);
lib/libc/quad/qdivrem.c
112
u[3] = (digit)HHALF(tmp.ul[L]);
lib/libc/quad/qdivrem.c
113
u[4] = (digit)LHALF(tmp.ul[L]);
lib/libc/quad/qdivrem.c
114
tmp.uq = vq;
lib/libc/quad/qdivrem.c
115
v[1] = (digit)HHALF(tmp.ul[H]);
lib/libc/quad/qdivrem.c
116
v[2] = (digit)LHALF(tmp.ul[H]);
lib/libc/quad/qdivrem.c
117
v[3] = (digit)HHALF(tmp.ul[L]);
lib/libc/quad/qdivrem.c
118
v[4] = (digit)LHALF(tmp.ul[L]);
lib/libc/quad/qdivrem.c
142
tmp.ul[H] = COMBINE(q1, q2);
lib/libc/quad/qdivrem.c
143
tmp.ul[L] = COMBINE(q3, q4);
lib/libc/quad/qdivrem.c
144
return (tmp.q);
lib/libc/quad/qdivrem.c
250
tmp.ul[H] = COMBINE(uspace[1], uspace[2]);
lib/libc/quad/qdivrem.c
251
tmp.ul[L] = COMBINE(uspace[3], uspace[4]);
lib/libc/quad/qdivrem.c
252
*arq = tmp.q;
lib/libc/quad/qdivrem.c
255
tmp.ul[H] = COMBINE(qspace[1], qspace[2]);
lib/libc/quad/qdivrem.c
256
tmp.ul[L] = COMBINE(qspace[3], qspace[4]);
lib/libc/quad/qdivrem.c
257
return (tmp.q);
lib/libc/quad/qdivrem.c
67
union uu tmp;
lib/libc/quad/qdivrem.c
81
tmp.ul[H] = tmp.ul[L] = 1 / zero;
lib/libc/quad/qdivrem.c
84
return (tmp.q);
lib/libc/regex/engine.c
181
SETUP(m->tmp);
lib/libc/regex/engine.c
679
states tmp = m->tmp;
lib/libc/regex/engine.c
742
ASSIGN(tmp, st);
lib/libc/regex/engine.c
745
st = step(m->g, startst, stopst, tmp, c, st);
lib/libc/regex/engine.c
768
states tmp = m->tmp;
lib/libc/regex/engine.c
83
states tmp; /* temporary */
lib/libc/regex/engine.c
831
ASSIGN(tmp, st);
lib/libc/regex/engine.c
834
st = step(m->g, startst, stopst, tmp, c, st);
lib/libc/stdio/fdopen.c
46
int flags, oflags, fdflags, tmp;
lib/libc/stdio/fdopen.c
54
tmp = fdflags & O_ACCMODE;
lib/libc/stdio/fdopen.c
55
if (tmp != O_RDWR && (tmp != (oflags & O_ACCMODE))) {
lib/libc/stdio/fdopen.c
75
if ((oflags & O_CLOEXEC) && !((tmp = fcntl(fd, F_GETFD)) & FD_CLOEXEC))
lib/libc/stdio/fdopen.c
76
fcntl(fd, F_SETFD, tmp | FD_CLOEXEC);
lib/libc/stdlib/heapsort.c
138
char tmp, *tmp1, *tmp2;
lib/libc/stdlib/heapsort.c
159
CREATE(l, nmemb, i, j, t, p, size, cnt, tmp);
lib/libc/stdlib/heapsort.c
45
#define SWAP(a, b, count, size, tmp) { \
lib/libc/stdlib/heapsort.c
48
tmp = *a; \
lib/libc/stdlib/heapsort.c
50
*b++ = tmp; \
lib/libc/stdlib/heapsort.c
71
#define CREATE(initval, nmemb, par_i, child_i, par, child, size, count, tmp) { \
lib/libc/stdlib/heapsort.c
82
SWAP(par, child, count, size, tmp); \
lib/libc/stdlib/malloc.c
1652
void *tmp;
lib/libc/stdlib/malloc.c
1663
tmp = pool->delayed_chunks[i];
lib/libc/stdlib/malloc.c
1664
if (tmp == p)
lib/libc/stdlib/malloc.c
1667
if (tmp != NULL) {
lib/libc/stdlib/malloc.c
1670
r = find(pool, tmp);
lib/libc/stdlib/malloc.c
1674
"double free?) %p", tmp);
lib/libc/stdlib/malloc.c
1676
validate_junk(pool, tmp, tmpsz);
lib/libc/stdlib/malloc.c
1686
tmp = p;
lib/libc/stdlib/malloc.c
1688
if (tmp == p)
lib/libc/stdlib/malloc.c
1690
pool->delayed_chunks[i] = tmp;
lib/libc/stdlib/malloc.c
825
size_t tmp;
lib/libc/stdlib/malloc.c
829
tmp = d->bigcache[i].psize << MALLOC_PAGESHIFT;
lib/libc/stdlib/malloc.c
831
validate_junk(d, r, tmp);
lib/libc/stdlib/malloc.c
832
if (munmap(r, tmp))
lib/libc/stdlib/malloc.c
834
STATS_SUB(d->malloc_used, tmp);
lib/libc/stdlib/merge.c
229
tmp = *a; *a++ = *s; *s++ = tmp; \
lib/libc/stdlib/merge.c
238
tmp = *bot; *bot++ = *s; *s++ = tmp; \
lib/libc/stdlib/merge.c
255
u_char tmp, *f1, *f2, *s, *l2, *last, *p2;
lib/libc/stdlib/merge.c
326
u_char *ai, *s, *t, *u, tmp;
lib/libc/time/localtime.c
1235
localsub(const time_t *timep, int_fast32_t offset, struct tm *tmp)
lib/libc/time/localtime.c
1245
return gmtsub(timep, offset, tmp);
lib/libc/time/localtime.c
1266
result = localsub(&newt, offset, tmp);
lib/libc/time/localtime.c
1267
if (result == tmp) {
lib/libc/time/localtime.c
1270
newy = tmp->tm_year;
lib/libc/time/localtime.c
1275
tmp->tm_year = newy;
lib/libc/time/localtime.c
1276
if (tmp->tm_year != newy)
lib/libc/time/localtime.c
1310
result = timesub(&t, ttisp->tt_gmtoff, sp, tmp);
lib/libc/time/localtime.c
1311
tmp->tm_isdst = ttisp->tt_isdst;
lib/libc/time/localtime.c
1312
tzname[tmp->tm_isdst] = &sp->chars[ttisp->tt_abbrind];
lib/libc/time/localtime.c
1313
tmp->tm_zone = &sp->chars[ttisp->tt_abbrind];
lib/libc/time/localtime.c
1349
gmtsub(const time_t *timep, int_fast32_t offset, struct tm *tmp)
lib/libc/time/localtime.c
1361
result = timesub(timep, offset, gmtptr, tmp);
lib/libc/time/localtime.c
1368
tmp->tm_zone = wildabbr;
lib/libc/time/localtime.c
1371
tmp->tm_zone = gmt;
lib/libc/time/localtime.c
1373
tmp->tm_zone = gmtptr->chars;
lib/libc/time/localtime.c
1426
struct tm *tmp)
lib/libc/time/localtime.c
144
struct tm * tmp);
lib/libc/time/localtime.c
146
struct tm * tmp);
lib/libc/time/localtime.c
1515
tmp->tm_year = y;
lib/libc/time/localtime.c
1516
if (increment_overflow(&tmp->tm_year, -TM_YEAR_BASE))
lib/libc/time/localtime.c
1518
tmp->tm_yday = idays;
lib/libc/time/localtime.c
1522
tmp->tm_wday = EPOCH_WDAY +
lib/libc/time/localtime.c
1528
tmp->tm_wday %= DAYSPERWEEK;
lib/libc/time/localtime.c
1529
if (tmp->tm_wday < 0)
lib/libc/time/localtime.c
1530
tmp->tm_wday += DAYSPERWEEK;
lib/libc/time/localtime.c
1531
tmp->tm_hour = (int) (rem / SECSPERHOUR);
lib/libc/time/localtime.c
1533
tmp->tm_min = (int) (rem / SECSPERMIN);
lib/libc/time/localtime.c
1538
tmp->tm_sec = (int) (rem % SECSPERMIN) + hit;
lib/libc/time/localtime.c
1540
for (tmp->tm_mon = 0; idays >= ip[tmp->tm_mon]; ++(tmp->tm_mon))
lib/libc/time/localtime.c
1541
idays -= ip[tmp->tm_mon];
lib/libc/time/localtime.c
1542
tmp->tm_mday = (int) (idays + 1);
lib/libc/time/localtime.c
1543
tmp->tm_isdst = 0;
lib/libc/time/localtime.c
1544
tmp->tm_gmtoff = offset;
lib/libc/time/localtime.c
1545
return tmp;
lib/libc/time/localtime.c
155
static time_t time1(struct tm * tmp,
lib/libc/time/localtime.c
159
static time_t time2(struct tm *tmp,
lib/libc/time/localtime.c
163
static time_t time2sub(struct tm *tmp,
lib/libc/time/localtime.c
1652
time2sub(struct tm *tmp,
lib/libc/time/localtime.c
1669
yourtm = *tmp;
lib/libc/time/localtime.c
168
const struct state * sp, struct tm * tmp);
lib/libc/time/localtime.c
1817
if ((*funcp)(&t, offset, tmp))
lib/libc/time/localtime.c
1823
time2(struct tm *tmp,
lib/libc/time/localtime.c
1834
t = time2sub(tmp, funcp, offset, okayp, FALSE);
lib/libc/time/localtime.c
1835
return *okayp ? t : time2sub(tmp, funcp, offset, okayp, TRUE);
lib/libc/time/localtime.c
1839
time1(struct tm *tmp,
lib/libc/time/localtime.c
1853
if (tmp == NULL) {
lib/libc/time/localtime.c
1857
if (tmp->tm_isdst > 1)
lib/libc/time/localtime.c
1858
tmp->tm_isdst = 1;
lib/libc/time/localtime.c
1859
t = time2(tmp, funcp, offset, &okay);
lib/libc/time/localtime.c
1866
if (tmp->tm_isdst < 0)
lib/libc/time/localtime.c
1867
tmp->tm_isdst = 0; /* reset to std and try again */
lib/libc/time/localtime.c
1870
if (okay || tmp->tm_isdst < 0)
lib/libc/time/localtime.c
1893
if (sp->ttis[samei].tt_isdst != tmp->tm_isdst)
lib/libc/time/localtime.c
1897
if (sp->ttis[otheri].tt_isdst == tmp->tm_isdst)
lib/libc/time/localtime.c
1899
tmp->tm_sec += sp->ttis[otheri].tt_gmtoff -
lib/libc/time/localtime.c
1901
tmp->tm_isdst = !tmp->tm_isdst;
lib/libc/time/localtime.c
1902
t = time2(tmp, funcp, offset, &okay);
lib/libc/time/localtime.c
1905
tmp->tm_sec -= sp->ttis[otheri].tt_gmtoff -
lib/libc/time/localtime.c
1907
tmp->tm_isdst = !tmp->tm_isdst;
lib/libc/time/localtime.c
1914
mktime(struct tm *tmp)
lib/libc/time/localtime.c
1920
ret = time1(tmp, localsub, 0L);
lib/libc/time/localtime.c
1929
timelocal(struct tm *tmp)
lib/libc/time/localtime.c
1931
if (tmp != NULL)
lib/libc/time/localtime.c
1932
tmp->tm_isdst = -1; /* in case it wasn't initialized */
lib/libc/time/localtime.c
1933
return mktime(tmp);
lib/libc/time/localtime.c
1937
timegm(struct tm *tmp)
lib/libc/time/localtime.c
1939
if (tmp != NULL)
lib/libc/time/localtime.c
1940
tmp->tm_isdst = 0;
lib/libc/time/localtime.c
1941
return time1(tmp, gmtsub, 0L);
lib/libc/time/localtime.c
1945
timeoff(struct tm *tmp, long offset)
lib/libc/time/localtime.c
1947
if (tmp != NULL)
lib/libc/time/localtime.c
1948
tmp->tm_isdst = 0;
lib/libc/time/localtime.c
1949
return time1(tmp, gmtsub, offset);
lib/libcrypto/aes/aes.c
365
aes_block_t tmp, tmp2;
lib/libcrypto/aes/aes.c
382
memcpy(tmp.data, in, AES_BLOCK_SIZE);
lib/libcrypto/aes/aes.c
384
tmp2.data[n] = tmp.data[n] ^ iv.data[n];
lib/libcrypto/aes/aes.c
391
iv2 = tmp;
lib/libcrypto/aes/aes.c
398
memcpy(tmp.data, in, AES_BLOCK_SIZE);
lib/libcrypto/aes/aes.c
399
tmp2 = tmp;
lib/libcrypto/aes/aes.c
401
tmp.data[n] ^= iv2.data[n];
lib/libcrypto/aes/aes.c
402
AES_decrypt((unsigned char *)tmp.data,
lib/libcrypto/aes/aes.c
403
(unsigned char *)tmp.data, key);
lib/libcrypto/aes/aes.c
405
tmp.data[n] ^= iv.data[n];
lib/libcrypto/aes/aes.c
406
memcpy(out, tmp.data, AES_BLOCK_SIZE);
lib/libcrypto/aes/aes.c
408
iv2 = tmp;
lib/libcrypto/bn/bn_bpsw.c
104
if (!BN_add(V, V, tmp))
lib/libcrypto/bn/bn_bpsw.c
66
BIGNUM *tmp;
lib/libcrypto/bn/bn_bpsw.c
71
if ((tmp = BN_CTX_get(ctx)) == NULL)
lib/libcrypto/bn/bn_bpsw.c
75
if (!BN_sqr(tmp, U, ctx))
lib/libcrypto/bn/bn_bpsw.c
77
if (!BN_mul(tmp, D, tmp, ctx))
lib/libcrypto/bn/bn_bpsw.c
87
if (!BN_add(V, V, tmp))
lib/libcrypto/bn/bn_bpsw.c
94
if (!BN_mul(tmp, D, U, ctx))
lib/libcrypto/bn/bn_convert.c
305
BIGNUM *tmp = NULL;
lib/libcrypto/bn/bn_convert.c
319
if ((tmp = BN_dup(bn)) == NULL)
lib/libcrypto/bn/bn_convert.c
327
while (!BN_is_zero(tmp)) {
lib/libcrypto/bn/bn_convert.c
328
if ((w = BN_div_word(tmp, BN_DEC_CONV)) == -1)
lib/libcrypto/bn/bn_convert.c
372
BN_free(tmp);
lib/libcrypto/bn/bn_div.c
230
BIGNUM *tmp, wnum, *snum, *sdiv, *res;
lib/libcrypto/bn/bn_div.c
266
if ((tmp = BN_CTX_get(ctx)) == NULL)
lib/libcrypto/bn/bn_div.c
337
if (!bn_wexpand(tmp, (div_n + 1)))
lib/libcrypto/bn/bn_div.c
367
l0 = bn_mulw_words(tmp->d, sdiv->d, div_n, q);
lib/libcrypto/bn/bn_div.c
368
tmp->d[div_n] = l0;
lib/libcrypto/bn/bn_div.c
375
if (bn_sub_words(wnum.d, wnum.d, tmp->d, div_n + 1)) {
lib/libcrypto/bn/bn_exp.c
404
BIGNUM tmp, am;
lib/libcrypto/bn/bn_exp.c
451
tmp.d = (BN_ULONG *)(powerbuf + sizeof(m->d[0]) * top * numPowers);
lib/libcrypto/bn/bn_exp.c
452
am.d = tmp.d + top;
lib/libcrypto/bn/bn_exp.c
453
tmp.top = am.top = 0;
lib/libcrypto/bn/bn_exp.c
454
tmp.dmax = am.dmax = top;
lib/libcrypto/bn/bn_exp.c
455
tmp.neg = am.neg = 0;
lib/libcrypto/bn/bn_exp.c
456
tmp.flags = am.flags = BN_FLG_STATIC_DATA;
lib/libcrypto/bn/bn_exp.c
460
if (!BN_to_montgomery(&tmp, BN_value_one(), mont, ctx))
lib/libcrypto/bn/bn_exp.c
463
tmp.d[0] = (0 - m - >d[0]) & BN_MASK2; /* 2^(top*BN_BITS2) - m */
lib/libcrypto/bn/bn_exp.c
465
tmp.d[i] = (~m->d[i]) & BN_MASK2;
lib/libcrypto/bn/bn_exp.c
466
tmp.top = top;
lib/libcrypto/bn/bn_exp.c
497
for (i = tmp.top; i < top; i++)
lib/libcrypto/bn/bn_exp.c
498
tmp.d[i] = 0;
lib/libcrypto/bn/bn_exp.c
500
bn_scatter5(tmp.d, top, powerbuf, 0);
lib/libcrypto/bn/bn_exp.c
502
bn_mul_mont(tmp.d, am.d, am.d, np, n0, top);
lib/libcrypto/bn/bn_exp.c
503
bn_scatter5(tmp.d, top, powerbuf, 2);
lib/libcrypto/bn/bn_exp.c
508
bn_mul_mont_gather5(tmp.d, am.d, powerbuf, np,
lib/libcrypto/bn/bn_exp.c
510
bn_scatter5(tmp.d, top, powerbuf, i);
lib/libcrypto/bn/bn_exp.c
515
bn_mul_mont(tmp.d, tmp.d, tmp.d, np, n0, top);
lib/libcrypto/bn/bn_exp.c
516
bn_scatter5(tmp.d, top, powerbuf, i);
lib/libcrypto/bn/bn_exp.c
520
bn_mul_mont_gather5(tmp.d, am.d, powerbuf, np,
lib/libcrypto/bn/bn_exp.c
522
bn_scatter5(tmp.d, top, powerbuf, i);
lib/libcrypto/bn/bn_exp.c
524
bn_mul_mont(tmp.d, tmp.d, tmp.d, np, n0, top);
lib/libcrypto/bn/bn_exp.c
525
bn_scatter5(tmp.d, top, powerbuf, j);
lib/libcrypto/bn/bn_exp.c
529
bn_mul_mont_gather5(tmp.d, am.d, powerbuf, np,
lib/libcrypto/bn/bn_exp.c
531
bn_scatter5(tmp.d, top, powerbuf, i);
lib/libcrypto/bn/bn_exp.c
532
bn_mul_mont(tmp.d, tmp.d, tmp.d, np, n0, top);
lib/libcrypto/bn/bn_exp.c
533
bn_scatter5(tmp.d, top, powerbuf, 2*i);
lib/libcrypto/bn/bn_exp.c
536
bn_mul_mont_gather5(tmp.d, am.d, powerbuf, np,
lib/libcrypto/bn/bn_exp.c
538
bn_scatter5(tmp.d, top, powerbuf, i);
lib/libcrypto/bn/bn_exp.c
544
bn_gather5(tmp.d, top, powerbuf, wvalue);
lib/libcrypto/bn/bn_exp.c
553
bn_mul_mont(tmp.d, tmp.d, tmp.d, np, n0, top);
lib/libcrypto/bn/bn_exp.c
554
bn_mul_mont(tmp.d, tmp.d, tmp.d, np, n0, top);
lib/libcrypto/bn/bn_exp.c
555
bn_mul_mont(tmp.d, tmp.d, tmp.d, np, n0, top);
lib/libcrypto/bn/bn_exp.c
556
bn_mul_mont(tmp.d, tmp.d, tmp.d, np, n0, top);
lib/libcrypto/bn/bn_exp.c
557
bn_mul_mont(tmp.d, tmp.d, tmp.d, np, n0, top);
lib/libcrypto/bn/bn_exp.c
558
bn_mul_mont_gather5(tmp.d, tmp.d, powerbuf, np, n0, top, wvalue);
lib/libcrypto/bn/bn_exp.c
561
tmp.top = top;
lib/libcrypto/bn/bn_exp.c
562
bn_correct_top(&tmp);
lib/libcrypto/bn/bn_exp.c
566
if (!MOD_EXP_CTIME_COPY_TO_PREBUF(&tmp, top, powerbuf, 0,
lib/libcrypto/bn/bn_exp.c
579
if (!BN_mod_mul_montgomery(&tmp, &am, &am, mont, ctx))
lib/libcrypto/bn/bn_exp.c
581
if (!MOD_EXP_CTIME_COPY_TO_PREBUF(&tmp, top, powerbuf,
lib/libcrypto/bn/bn_exp.c
586
if (!BN_mod_mul_montgomery(&tmp, &am, &tmp,
lib/libcrypto/bn/bn_exp.c
589
if (!MOD_EXP_CTIME_COPY_TO_PREBUF(&tmp, top,
lib/libcrypto/bn/bn_exp.c
598
if (!MOD_EXP_CTIME_COPY_FROM_PREBUF(&tmp, top, powerbuf,
lib/libcrypto/bn/bn_exp.c
610
if (!BN_mod_mul_montgomery(&tmp, &tmp, &tmp,
lib/libcrypto/bn/bn_exp.c
622
if (!BN_mod_mul_montgomery(&tmp, &tmp, &am, mont, ctx))
lib/libcrypto/bn/bn_exp.c
628
if (!BN_from_montgomery(rr, &tmp, mont, ctx))
lib/libcrypto/bn/bn_gcd.c
265
BIGNUM *tmp;
lib/libcrypto/bn/bn_gcd.c
290
tmp = A; /* keep the BIGNUM object, the value does not matter */
lib/libcrypto/bn/bn_gcd.c
316
if (!BN_mul(tmp, D, X, ctx))
lib/libcrypto/bn/bn_gcd.c
318
if (!BN_add(tmp, tmp, Y))
lib/libcrypto/bn/bn_gcd.c
323
X = tmp;
lib/libcrypto/bn/bn_gcd.c
418
BIGNUM *tmp;
lib/libcrypto/bn/bn_gcd.c
443
tmp = A; /* keep the BIGNUM object, the value does not matter */
lib/libcrypto/bn/bn_gcd.c
469
if (!BN_mul(tmp, D, X, ctx))
lib/libcrypto/bn/bn_gcd.c
471
if (!BN_add(tmp, tmp, Y))
lib/libcrypto/bn/bn_gcd.c
476
X = tmp;
lib/libcrypto/bn/bn_gcd.c
655
BIGNUM *tmp;
lib/libcrypto/bn/bn_gcd.c
710
tmp = A; /* keep the BIGNUM object, the value does not matter */
lib/libcrypto/bn/bn_gcd.c
738
if (!BN_add(tmp, X, Y))
lib/libcrypto/bn/bn_gcd.c
742
if (!BN_lshift1(tmp, X))
lib/libcrypto/bn/bn_gcd.c
745
if (!BN_lshift(tmp, X, 2))
lib/libcrypto/bn/bn_gcd.c
748
if (!bn_copy(tmp, X))
lib/libcrypto/bn/bn_gcd.c
750
if (!BN_mul_word(tmp, D->d[0]))
lib/libcrypto/bn/bn_gcd.c
753
if (!BN_mul(tmp, D,X, ctx))
lib/libcrypto/bn/bn_gcd.c
756
if (!BN_add(tmp, tmp, Y))
lib/libcrypto/bn/bn_gcd.c
762
X = tmp;
lib/libcrypto/bn/bn_kron.c
183
tmp = a;
lib/libcrypto/bn/bn_kron.c
185
b = tmp;
lib/libcrypto/bn/bn_kron.c
70
BIGNUM *a, *b, *tmp;
lib/libcrypto/bn/bn_mod_sqrt.c
149
BIGNUM *b, *i, *n, *tmp;
lib/libcrypto/bn/bn_mod_sqrt.c
160
if ((tmp = BN_CTX_get(ctx)) == NULL)
lib/libcrypto/bn/bn_mod_sqrt.c
169
if (!BN_mod_lshift1(tmp, a, p, ctx))
lib/libcrypto/bn/bn_mod_sqrt.c
173
if (!BN_mod_exp_ct(b, tmp, n, p, ctx))
lib/libcrypto/bn/bn_mod_sqrt.c
179
if (!BN_mod_mul(i, tmp, i, p, ctx))
lib/libcrypto/bn/bn_mont.c
407
BIGNUM *tmp;
lib/libcrypto/bn/bn_mont.c
412
if ((tmp = BN_CTX_get(ctx)) == NULL)
lib/libcrypto/bn/bn_mont.c
416
if (!BN_sqr(tmp, a, ctx))
lib/libcrypto/bn/bn_mont.c
419
if (!BN_mul(tmp, a, b, ctx))
lib/libcrypto/bn/bn_mont.c
424
if (!bn_montgomery_reduce(r, tmp, mctx))
lib/libcrypto/bn/bn_mont.c
617
BIGNUM *tmp;
lib/libcrypto/bn/bn_mont.c
622
if ((tmp = BN_CTX_get(ctx)) == NULL)
lib/libcrypto/bn/bn_mont.c
624
if (!bn_copy(tmp, a))
lib/libcrypto/bn/bn_mont.c
626
if (!bn_montgomery_reduce(r, tmp, mctx))
lib/libcrypto/bn/bn_word.c
80
BIGNUM *tmp = BN_dup(a);
lib/libcrypto/bn/bn_word.c
81
if (tmp == NULL) {
lib/libcrypto/bn/bn_word.c
84
ret = BN_div_word(tmp, w);
lib/libcrypto/bn/bn_word.c
85
BN_free(tmp);
lib/libcrypto/chacha/chacha-merged.c
126
u8 tmp[64];
lib/libcrypto/chacha/chacha-merged.c
152
tmp[i] = m[i];
lib/libcrypto/chacha/chacha-merged.c
153
m = tmp;
lib/libcrypto/chacha/chacha-merged.c
155
c = tmp;
lib/libcrypto/cms/cms_pwri.c
232
unsigned char *tmp;
lib/libcrypto/cms/cms_pwri.c
243
if ((tmp = malloc(inlen)) == NULL) {
lib/libcrypto/cms/cms_pwri.c
249
if (!EVP_DecryptUpdate(ctx, tmp + inlen - 2 * blocklen, &outl,
lib/libcrypto/cms/cms_pwri.c
256
|| !EVP_DecryptUpdate(ctx, tmp, &outl, tmp + inlen - blocklen, blocklen)
lib/libcrypto/cms/cms_pwri.c
258
|| !EVP_DecryptUpdate(ctx, tmp, &outl, in, inlen - blocklen)
lib/libcrypto/cms/cms_pwri.c
263
|| !EVP_DecryptUpdate(ctx, tmp, &outl, tmp, inlen))
lib/libcrypto/cms/cms_pwri.c
266
if (((tmp[1] ^ tmp[4]) & (tmp[2] ^ tmp[5]) & (tmp[3] ^ tmp[6])) != 0xff) {
lib/libcrypto/cms/cms_pwri.c
270
if (inlen < 4 + (size_t)tmp[0]) {
lib/libcrypto/cms/cms_pwri.c
274
*outlen = (size_t)tmp[0];
lib/libcrypto/cms/cms_pwri.c
275
memcpy(out, tmp + 4, *outlen);
lib/libcrypto/cms/cms_pwri.c
279
freezero(tmp, inlen);
lib/libcrypto/ct/ct_log.c
221
char *tmp;
lib/libcrypto/ct/ct_log.c
228
tmp = strndup(log_name, log_name_len);
lib/libcrypto/ct/ct_log.c
229
if (tmp == NULL)
lib/libcrypto/ct/ct_log.c
232
ret = ctlog_new_from_conf(&ct_log, load_ctx->conf, tmp);
lib/libcrypto/ct/ct_log.c
233
free(tmp);
lib/libcrypto/des/des_local.h
130
{ DES_LONG tmp; LOAD_DATA(R,S,u,t,E0,E1,tmp); }
lib/libcrypto/des/des_local.h
132
#define LOAD_DATA(R,S,u,t,E0,E1,tmp) \
lib/libcrypto/des/des_local.h
135
tmp=(u<<16); u^=R^s[S ]; u^=tmp; \
lib/libcrypto/des/des_local.h
136
tmp=(t<<16); t^=R^s[S+1]; t^=tmp
lib/libcrypto/des/des_local.h
139
#define LOAD_DATA(R,S,u,t,E0,E1,tmp) \
lib/libcrypto/dh/dh_key.c
140
BIGNUM *tmp;
lib/libcrypto/dh/dh_key.c
153
if ((tmp = BN_CTX_get(ctx)) == NULL)
lib/libcrypto/dh/dh_key.c
176
if (!dh->meth->bn_mod_exp(dh, tmp, pub_key, dh->priv_key, dh->p, ctx,
lib/libcrypto/dh/dh_key.c
182
ret = BN_bn2bin(tmp, key);
lib/libcrypto/ec/ec_field.c
70
BIGNUM *tmp;
lib/libcrypto/ec/ec_field.c
76
if ((tmp = BN_CTX_get(ctx)) == NULL)
lib/libcrypto/ec/ec_field.c
85
if (!BN_nnmod(tmp, bn, group->p, ctx))
lib/libcrypto/ec/ec_field.c
88
if (BN_num_bits(tmp) > EC_FIELD_ELEMENT_MAX_BITS)
lib/libcrypto/ec/ec_field.c
93
for (i = 0; i < tmp->top; i++)
lib/libcrypto/ec/ec_field.c
94
fe->w[i] = tmp->d[i];
lib/libcrypto/ec/ecp_hp_methods.c
698
BIGNUM *tmp, *tmp_Z;
lib/libcrypto/ec/ecp_hp_methods.c
707
if ((tmp = BN_CTX_get(ctx)) == NULL)
lib/libcrypto/ec/ecp_hp_methods.c
738
if (!BN_mod_inverse_nonct(tmp, prod_Z[num - 1], group->p, ctx)) {
lib/libcrypto/ec/ecp_hp_methods.c
747
if (!BN_mod_mul(tmp_Z, prod_Z[i - 1], tmp, group->p, ctx))
lib/libcrypto/ec/ecp_hp_methods.c
749
if (!BN_mod_mul(tmp, tmp, points[i]->Z, group->p, ctx))
lib/libcrypto/ec/ecp_methods.c
1002
if (!ec_field_sqr(group, tmp, lambda, ctx))
lib/libcrypto/ec/ecp_methods.c
1006
if (!ec_field_mul(group, p->X, tmp, p->X, ctx))
lib/libcrypto/ec/ecp_methods.c
1010
if (!ec_field_mul(group, tmp, tmp, lambda, ctx))
lib/libcrypto/ec/ecp_methods.c
1014
if (!ec_field_mul(group, p->Y, tmp, p->Y, ctx))
lib/libcrypto/ec/ecp_methods.c
200
BIGNUM *rh, *tmp, *Z4, *Z6;
lib/libcrypto/ec/ecp_methods.c
210
if ((tmp = BN_CTX_get(ctx)) == NULL)
lib/libcrypto/ec/ecp_methods.c
229
if (!ec_field_sqr(group, tmp, point->Z, ctx))
lib/libcrypto/ec/ecp_methods.c
231
if (!ec_field_sqr(group, Z4, tmp, ctx))
lib/libcrypto/ec/ecp_methods.c
233
if (!ec_field_mul(group, Z6, Z4, tmp, ctx))
lib/libcrypto/ec/ecp_methods.c
238
if (!BN_mod_lshift1_quick(tmp, Z4, group->p))
lib/libcrypto/ec/ecp_methods.c
240
if (!BN_mod_add_quick(tmp, tmp, Z4, group->p))
lib/libcrypto/ec/ecp_methods.c
242
if (!BN_mod_sub_quick(rh, rh, tmp, group->p))
lib/libcrypto/ec/ecp_methods.c
247
if (!ec_field_mul(group, tmp, Z4, group->a, ctx))
lib/libcrypto/ec/ecp_methods.c
249
if (!BN_mod_add_quick(rh, rh, tmp, group->p))
lib/libcrypto/ec/ecp_methods.c
256
if (!ec_field_mul(group, tmp, group->b, Z6, ctx))
lib/libcrypto/ec/ecp_methods.c
258
if (!BN_mod_add_quick(rh, rh, tmp, group->p))
lib/libcrypto/ec/ecp_methods.c
274
if (!ec_field_sqr(group, tmp, point->Y, ctx))
lib/libcrypto/ec/ecp_methods.c
277
ret = (0 == BN_ucmp(tmp, rh));
lib/libcrypto/ec/ecp_methods.c
295
const EC_POINT *tmp;
lib/libcrypto/ec/ecp_methods.c
306
tmp = a;
lib/libcrypto/ec/ecp_methods.c
308
b = tmp;
lib/libcrypto/ec/ecp_methods.c
527
BIGNUM *one, *tmp, *tmp_Z;
lib/libcrypto/ec/ecp_methods.c
538
if ((tmp = BN_CTX_get(ctx)) == NULL)
lib/libcrypto/ec/ecp_methods.c
581
if (!BN_mod_inverse_nonct(tmp, prod_Z[num - 1], group->p, ctx)) {
lib/libcrypto/ec/ecp_methods.c
592
if (!group->meth->field_encode(group, tmp, tmp, ctx))
lib/libcrypto/ec/ecp_methods.c
594
if (!group->meth->field_encode(group, tmp, tmp, ctx))
lib/libcrypto/ec/ecp_methods.c
607
if (!ec_field_mul(group, tmp_Z, prod_Z[i - 1], tmp, ctx))
lib/libcrypto/ec/ecp_methods.c
610
if (!ec_field_mul(group, tmp, tmp, points[i]->Z, ctx))
lib/libcrypto/ec/ecp_methods.c
619
if (!bn_copy(points[0]->Z, tmp))
lib/libcrypto/ec/ecp_methods.c
632
if (!ec_field_sqr(group, tmp, p->Z, ctx))
lib/libcrypto/ec/ecp_methods.c
634
if (!ec_field_mul(group, p->X, p->X, tmp, ctx))
lib/libcrypto/ec/ecp_methods.c
637
if (!ec_field_mul(group, tmp, tmp, p->Z, ctx))
lib/libcrypto/ec/ecp_methods.c
639
if (!ec_field_mul(group, p->Y, p->Y, tmp, ctx))
lib/libcrypto/ec/ecp_methods.c
980
BIGNUM *tmp = NULL;
lib/libcrypto/ec/ecp_methods.c
986
if ((tmp = BN_CTX_get(ctx)) == NULL)
lib/libcrypto/err/err.c
550
ERR_STATE *ret, tmp, *tmpp = NULL;
lib/libcrypto/err/err.c
553
tmp.tid = pthread_self();
lib/libcrypto/err/err.c
554
ret = err_thread_get_item(&tmp);
lib/libcrypto/err/err.c
748
ERR_STATE tmp;
lib/libcrypto/err/err.c
751
tmp.tid = pthread_self();
lib/libcrypto/err/err.c
757
err_thread_del_item(&tmp);
lib/libcrypto/evp/bio_b64.c
202
i = BIO_read(b->next_bio, &(ctx->tmp[ctx->tmp_len]),
lib/libcrypto/evp/bio_b64.c
231
q = p =(unsigned char *)ctx->tmp;
lib/libcrypto/evp/bio_b64.c
254
&(ctx->tmp[0])) {
lib/libcrypto/evp/bio_b64.c
256
&(ctx->tmp[0]));
lib/libcrypto/evp/bio_b64.c
258
ctx->tmp[x] = p[x];
lib/libcrypto/evp/bio_b64.c
271
if (p == (unsigned char *)&(ctx->tmp[0])) {
lib/libcrypto/evp/bio_b64.c
282
ctx->tmp[ii] = p[ii];
lib/libcrypto/evp/bio_b64.c
302
(unsigned char *)ctx->tmp, jj);
lib/libcrypto/evp/bio_b64.c
304
if (ctx->tmp[jj-1] == '=') {
lib/libcrypto/evp/bio_b64.c
306
if (ctx->tmp[jj-2] == '=')
lib/libcrypto/evp/bio_b64.c
313
memmove(ctx->tmp, &ctx->tmp[jj], i - jj);
lib/libcrypto/evp/bio_b64.c
324
(unsigned char *)ctx->tmp, i);
lib/libcrypto/evp/bio_b64.c
406
memcpy(&(ctx->tmp[ctx->tmp_len]), in, n);
lib/libcrypto/evp/bio_b64.c
413
(unsigned char *)ctx->tmp, ctx->tmp_len);
lib/libcrypto/evp/bio_b64.c
422
memcpy(ctx->tmp, in, n);
lib/libcrypto/evp/bio_b64.c
517
(unsigned char *)ctx->tmp,
lib/libcrypto/evp/bio_b64.c
94
char tmp[B64_BLOCK_SIZE];
lib/libcrypto/evp/e_idea.c
90
IDEA_KEY_SCHEDULE tmp;
lib/libcrypto/evp/e_idea.c
92
idea_set_encrypt_key(key, &tmp);
lib/libcrypto/evp/e_idea.c
93
idea_set_decrypt_key(&tmp, ctx->cipher_data);
lib/libcrypto/evp/e_idea.c
94
explicit_bzero((unsigned char *)&tmp,
lib/libcrypto/evp/evp_encode.c
262
int seof = 0, eof = 0, rv = -1, ret = 0, i, v, tmp, n, decoded_len;
lib/libcrypto/evp/evp_encode.c
281
tmp = *(in++);
lib/libcrypto/evp/evp_encode.c
282
v = conv_ascii2bin(tmp);
lib/libcrypto/evp/evp_encode.c
288
if (tmp == '=') {
lib/libcrypto/evp/evp_encode.c
320
d[n++] = tmp;
lib/libcrypto/kdf/tls1_prf.c
261
unsigned char *tmp = NULL;
lib/libcrypto/kdf/tls1_prf.c
275
if ((tmp = calloc(1, out_len)) == NULL) {
lib/libcrypto/kdf/tls1_prf.c
281
tmp, out_len))
lib/libcrypto/kdf/tls1_prf.c
284
out[i] ^= tmp[i];
lib/libcrypto/kdf/tls1_prf.c
289
freezero(tmp, out_len);
lib/libcrypto/modes/cbc128.c
122
} tmp;
lib/libcrypto/modes/cbc128.c
160
(*block)(in, tmp.c, key);
lib/libcrypto/modes/cbc128.c
163
out[n] = tmp.c[n] ^ ivec[n];
lib/libcrypto/modes/cbc128.c
176
(*block)(in, tmp.c, key);
lib/libcrypto/modes/cbc128.c
179
out_t[n] = tmp.t[n] ^ ivec_t[n];
lib/libcrypto/modes/cbc128.c
190
(*block)(in, tmp.c, key);
lib/libcrypto/modes/cbc128.c
193
out[n] = tmp.c[n] ^ ivec[n];
lib/libcrypto/ocsp/ocsp_lib.c
194
char *host, *path, *port, *tmp;
lib/libcrypto/ocsp/ocsp_lib.c
213
if ((tmp = strchr(host, '/')) != NULL) {
lib/libcrypto/ocsp/ocsp_lib.c
214
path = strdup(tmp);
lib/libcrypto/ocsp/ocsp_lib.c
215
*tmp = '\0';
lib/libcrypto/ocsp/ocsp_lib.c
219
if ((tmp = strchr(host, ':')) != NULL ) {
lib/libcrypto/ocsp/ocsp_lib.c
220
port = strdup(tmp + 1);
lib/libcrypto/ocsp/ocsp_lib.c
221
*tmp = '\0';
lib/libcrypto/pem/pvkfmt.c
537
unsigned char *tmp = NULL;
lib/libcrypto/pem/pvkfmt.c
540
outlen = do_i2b(&tmp, pk, ispub);
lib/libcrypto/pem/pvkfmt.c
543
wrlen = BIO_write(out, tmp, outlen);
lib/libcrypto/pem/pvkfmt.c
544
free(tmp);
lib/libcrypto/pem/pvkfmt.c
926
unsigned char *tmp = NULL;
lib/libcrypto/pem/pvkfmt.c
929
outlen = i2b_PVK(&tmp, pk, enclevel, cb, u);
lib/libcrypto/pem/pvkfmt.c
932
wrlen = BIO_write(out, tmp, outlen);
lib/libcrypto/pem/pvkfmt.c
933
free(tmp);
lib/libcrypto/rc4/rc4.c
156
RC4_INT *d, tmp;
lib/libcrypto/rc4/rc4.c
169
tmp = d[i + j];
lib/libcrypto/rc4/rc4.c
170
idx2 = (data[idx1] + tmp + idx2) & 0xff;
lib/libcrypto/rc4/rc4.c
172
d[idx2] = tmp;
lib/libcrypto/rsa/rsa_gen.c
186
tmp = rsa->p;
lib/libcrypto/rsa/rsa_gen.c
188
rsa->q = tmp;
lib/libcrypto/rsa/rsa_gen.c
83
BIGNUM *r0 = NULL, *r1 = NULL, *r2 = NULL, *r3 = NULL, *tmp;
lib/libcrypto/sm2/sm2_sign.c
143
if ((tmp = BN_CTX_get(ctx)) == NULL) {
lib/libcrypto/sm2/sm2_sign.c
202
if (!BN_mod_mul(tmp, dA, r, order, ctx)) {
lib/libcrypto/sm2/sm2_sign.c
207
if (!BN_sub(tmp, k, tmp)) {
lib/libcrypto/sm2/sm2_sign.c
212
if (!BN_mod_mul(s, s, tmp, order, ctx)) {
lib/libcrypto/sm2/sm2_sign.c
97
BIGNUM *k, *rk, *tmp, *x1;
lib/libcrypto/x509/by_dir.c
271
X509_OBJECT stmp, *tmp;
lib/libcrypto/x509/by_dir.c
358
tmp = sk_X509_OBJECT_value(xl->store_ctx->objs, j);
lib/libcrypto/x509/by_dir.c
397
if (tmp != NULL) {
lib/libcrypto/x509/by_dir.c
399
ret->type = tmp->type;
lib/libcrypto/x509/by_dir.c
400
memcpy(&ret->data, &tmp->data, sizeof(ret->data));
lib/libcrypto/x509/x509_constraints.c
151
struct x509_constraints_name **tmp;
lib/libcrypto/x509/x509_constraints.c
152
if ((tmp = recallocarray(names->names, names->names_len,
lib/libcrypto/x509/x509_constraints.c
153
names->names_len + 32, sizeof(*tmp))) == NULL)
lib/libcrypto/x509/x509_constraints.c
156
names->names = tmp;
lib/libcrypto/x509/x509_cpols.c
757
char *tmp;
lib/libcrypto/x509/x509_cpols.c
761
tmp = i2s_ASN1_INTEGER(NULL, num);
lib/libcrypto/x509/x509_cpols.c
762
BIO_puts(out, tmp);
lib/libcrypto/x509/x509_cpols.c
763
free(tmp);
lib/libcrypto/x509/x509_ia5.c
236
char *tmp;
lib/libcrypto/x509/x509_ia5.c
240
if (!(tmp = malloc(ia5->length + 1))) {
lib/libcrypto/x509/x509_ia5.c
244
memcpy(tmp, ia5->data, ia5->length);
lib/libcrypto/x509/x509_ia5.c
245
tmp[ia5->length] = 0;
lib/libcrypto/x509/x509_ia5.c
246
return tmp;
lib/libcrypto/x509/x509_lu.c
301
X509_OBJECT stmp, *tmp;
lib/libcrypto/x509/x509_lu.c
310
tmp = X509_OBJECT_retrieve_by_subject(ctx->objs, type, name);
lib/libcrypto/x509/x509_lu.c
313
if (tmp == NULL || type == X509_LU_CRL) {
lib/libcrypto/x509/x509_lu.c
317
tmp = &stmp;
lib/libcrypto/x509/x509_lu.c
321
if (tmp == NULL)
lib/libcrypto/x509/x509_lu.c
325
if (!X509_OBJECT_up_ref_count(tmp))
lib/libcrypto/x509/x509_lu.c
328
*ret = *tmp;
lib/libcrypto/x509/x509_utl.c
1312
unsigned char tmp[16];
lib/libcrypto/x509/x509_utl.c
1375
memcpy(v6, v6stat.tmp, v6stat.zero_pos);
lib/libcrypto/x509/x509_utl.c
1381
v6stat.tmp + v6stat.zero_pos,
lib/libcrypto/x509/x509_utl.c
1384
memcpy(v6, v6stat.tmp, 16);
lib/libcrypto/x509/x509_utl.c
1414
if (!ipv4_from_asc(s->tmp + s->total, elem))
lib/libcrypto/x509/x509_utl.c
1418
if (!ipv6_hex(s->tmp + s->total, elem, len))
lib/libcrypto/x509/x509_vpm.c
345
char *tmp;
lib/libcrypto/x509/x509_vpm.c
354
if ((tmp = strdup(src)) == NULL)
lib/libcrypto/x509/x509_vpm.c
359
if ((tmp = malloc(srclen)) == NULL)
lib/libcrypto/x509/x509_vpm.c
361
memcpy(tmp, src, srclen);
lib/libcrypto/x509/x509_vpm.c
366
*pdest = tmp;
lib/libcurses/base/lib_bkgd.c
91
int tmp;
lib/libcurses/base/lib_bkgd.c
95
tmp = _nc_to_char((wint_t) CharOf(wch));
lib/libcurses/base/lib_bkgd.c
97
win->_bkgd = (((tmp == EOF) ? ' ' : (chtype) tmp)
lib/libcurses/base/lib_instr.c
101
wcstombs(tmp, wch, n3);
lib/libcurses/base/lib_instr.c
103
str[i++] = tmp[i3];
lib/libcurses/base/lib_instr.c
104
free(tmp);
lib/libcurses/base/lib_instr.c
71
char *tmp;
lib/libcurses/base/lib_instr.c
95
} else if ((tmp = typeCalloc(char, need)) == 0) {
lib/libcurses/base/lib_screen.c
505
WINDOW tmp, *nwin;
lib/libcurses/base/lib_screen.c
518
if (read_block(&tmp, (size_t) 4, filep) < 0) {
lib/libcurses/base/lib_screen.c
524
if (!memcmp(&tmp, my_magic, (size_t) 4)) {
lib/libcurses/base/lib_screen.c
526
if (read_win(&tmp, filep) < 0)
lib/libcurses/base/lib_screen.c
529
} else if (read_block(((char *) &tmp) + 4, sizeof(WINDOW) - 4, filep) < 0) {
lib/libcurses/base/lib_screen.c
538
if (tmp._maxy == 0 ||
lib/libcurses/base/lib_screen.c
539
tmp._maxy > MAX_SIZE ||
lib/libcurses/base/lib_screen.c
540
tmp._maxx == 0 ||
lib/libcurses/base/lib_screen.c
541
tmp._maxx > MAX_SIZE) {
lib/libcurses/base/lib_screen.c
545
if (IS_PAD(&tmp)) {
lib/libcurses/base/lib_screen.c
547
tmp._maxy + 1,
lib/libcurses/base/lib_screen.c
548
tmp._maxx + 1);
lib/libcurses/base/lib_screen.c
551
tmp._maxy + 1,
lib/libcurses/base/lib_screen.c
552
tmp._maxx + 1, 0, 0);
lib/libcurses/base/lib_screen.c
562
size_t linesize = sizeof(NCURSES_CH_T) * (size_t) (tmp._maxx + 1);
lib/libcurses/base/lib_screen.c
564
nwin->_curx = tmp._curx;
lib/libcurses/base/lib_screen.c
565
nwin->_cury = tmp._cury;
lib/libcurses/base/lib_screen.c
566
nwin->_maxy = tmp._maxy;
lib/libcurses/base/lib_screen.c
567
nwin->_maxx = tmp._maxx;
lib/libcurses/base/lib_screen.c
568
nwin->_begy = tmp._begy;
lib/libcurses/base/lib_screen.c
569
nwin->_begx = tmp._begx;
lib/libcurses/base/lib_screen.c
570
nwin->_yoffset = tmp._yoffset;
lib/libcurses/base/lib_screen.c
571
nwin->_flags = tmp._flags & ~(_SUBWIN);
lib/libcurses/base/lib_screen.c
573
WINDOW_ATTRS(nwin) = WINDOW_ATTRS(&tmp);
lib/libcurses/base/lib_screen.c
574
nwin->_nc_bkgd = tmp._nc_bkgd;
lib/libcurses/base/lib_screen.c
576
nwin->_notimeout = tmp._notimeout;
lib/libcurses/base/lib_screen.c
577
nwin->_clear = tmp._clear;
lib/libcurses/base/lib_screen.c
578
nwin->_leaveok = tmp._leaveok;
lib/libcurses/base/lib_screen.c
579
nwin->_idlok = tmp._idlok;
lib/libcurses/base/lib_screen.c
580
nwin->_idcok = tmp._idcok;
lib/libcurses/base/lib_screen.c
581
nwin->_immed = tmp._immed;
lib/libcurses/base/lib_screen.c
582
nwin->_scroll = tmp._scroll;
lib/libcurses/base/lib_screen.c
583
nwin->_sync = tmp._sync;
lib/libcurses/base/lib_screen.c
584
nwin->_use_keypad = tmp._use_keypad;
lib/libcurses/base/lib_screen.c
585
nwin->_delay = tmp._delay;
lib/libcurses/base/lib_screen.c
587
nwin->_regtop = tmp._regtop;
lib/libcurses/base/lib_screen.c
588
nwin->_regbottom = tmp._regbottom;
lib/libcurses/base/lib_screen.c
590
if (IS_PAD(&tmp))
lib/libcurses/base/lib_screen.c
591
nwin->_pad = tmp._pad;
lib/libcurses/base/lib_screen.c
625
if (read_row(++next, &prior, nwin->_line[n].text, tmp._maxx
lib/libcurses/base/lib_set_term.c
292
char *tmp = 0;
lib/libcurses/base/lib_set_term.c
293
long value = strtol(src, &tmp, 0);
lib/libcurses/base/lib_set_term.c
295
if ((dst = tmp) == 0) {
lib/libcurses/tinfo/lib_setup.c
528
char *tmp;
lib/libcurses/tinfo/lib_setup.c
535
if ((tmp = getenv("CC")) != 0 && strlen(tmp) == 1) {
lib/libcurses/tinfo/lib_setup.c
537
char CC = *tmp;
lib/libcurses/tinfo/lib_setup.c
540
for (tmp = termp->type.Strings[i]; tmp && *tmp; tmp++) {
lib/libcurses/tinfo/lib_setup.c
541
if (UChar(*tmp) == proto)
lib/libcurses/tinfo/lib_setup.c
542
*tmp = CC;
lib/libcurses/tinfo/lib_tputs.c
186
char tmp = (char) ch;
lib/libcurses/tinfo/lib_tputs.c
191
if (write(fileno(NC_OUTPUT(SP_PARM)), &tmp, (size_t) 1) == -1)
lib/libcurses/tinfo/lib_tputs.c
195
char tmp = (char) ch;
lib/libcurses/tinfo/lib_tputs.c
196
if (write(fileno(stdout), &tmp, (size_t) 1) == -1)
lib/libcurses/tinfo/read_termcap.c
653
char *cp, tmp;
lib/libcurses/tinfo/read_termcap.c
658
tmp = *(cp + 1);
lib/libcurses/tinfo/read_termcap.c
661
*(cp + 1) = tmp;
lib/libcurses/tinfo/trim_sgr0.c
250
char *tmp;
lib/libcurses/tinfo/trim_sgr0.c
293
tmp = skip_zero(off + i);
lib/libcurses/tinfo/trim_sgr0.c
294
if (tmp[0] == '1'
lib/libcurses/tinfo/trim_sgr0.c
295
&& skip_zero(tmp + 1) != tmp + 1) {
lib/libcurses/tinfo/trim_sgr0.c
296
i = (size_t) (tmp - off);
lib/libcurses/tinfo/trim_sgr0.c
299
j = (size_t) (skip_zero(tmp + 1) - off);
lib/libcurses/tinfo/trim_sgr0.c
306
&& (tmp = strstr(end, off)) != 0
lib/libcurses/tinfo/trim_sgr0.c
308
i = (size_t) (tmp - end);
lib/libcurses/tinfo/trim_sgr0.c
310
tmp = strdup(end);
lib/libcurses/tinfo/trim_sgr0.c
311
chop_out(tmp, (unsigned) i, (unsigned) j);
lib/libcurses/tinfo/trim_sgr0.c
313
result = tmp;
lib/libcurses/widechar/lib_get_wstr.c
50
cchar_t tmp;
lib/libcurses/widechar/lib_get_wstr.c
55
setcchar(&tmp, wch, A_NORMAL, (short) 0, NULL);
lib/libcurses/widechar/lib_get_wstr.c
56
return wadd_wch(win, &tmp);
lib/libedit/eln.c
71
const wchar_t *tmp;
lib/libedit/eln.c
74
if ((tmp = el_wgets(el, nread)) == NULL)
lib/libedit/eln.c
81
wr = (wchar_t *)tmp;
lib/libedit/eln.c
89
*nread = wr - tmp;
lib/libedit/eln.c
91
return ct_encode_string(tmp, &el->el_lgcyconv);
lib/libedit/readline.c
640
char *tmp, *search = NULL, *aptr;
lib/libedit/readline.c
699
tmp = strdup(last_search_match? last_search_match:"");
lib/libedit/readline.c
731
tmp = history_arg_extract(start, end, aptr? aptr:ptr);
lib/libedit/readline.c
732
if (tmp == NULL) {
lib/libedit/readline.c
740
tmp = strdup(aptr? aptr:ptr);
lib/libedit/readline.c
746
*result = tmp;
lib/libedit/readline.c
754
if ((aptr = strrchr(tmp, '/')) != NULL)
lib/libedit/readline.c
757
if ((aptr = strrchr(tmp, '/')) != NULL) {
lib/libedit/readline.c
759
free(tmp);
lib/libedit/readline.c
760
tmp = aptr;
lib/libedit/readline.c
763
if ((aptr = strrchr(tmp, '.')) != NULL)
lib/libedit/readline.c
766
if ((aptr = strrchr(tmp, '.')) != NULL) {
lib/libedit/readline.c
768
free(tmp);
lib/libedit/readline.c
769
tmp = aptr;
lib/libedit/readline.c
788
free(tmp);
lib/libedit/readline.c
801
free(tmp);
lib/libedit/readline.c
816
free(tmp);
lib/libedit/readline.c
821
free(tmp);
lib/libedit/readline.c
833
free(tmp);
lib/libedit/readline.c
845
free(tmp);
lib/libedit/readline.c
867
aptr = _rl_compat_sub(tmp, from, to, g_on);
lib/libedit/readline.c
869
free(tmp);
lib/libedit/readline.c
870
tmp = aptr;
lib/libedit/readline.c
875
*result = tmp;
lib/libedit/readline.c
888
char *tmp, *result;
lib/libedit/readline.c
923
free(tmp); \
lib/libedit/readline.c
935
tmp = NULL;
lib/libedit/readline.c
985
ret = _history_expand_command (str, i, (j - i), &tmp);
lib/libedit/readline.c
986
if (ret > 0 && tmp) {
lib/libedit/readline.c
987
len = strlen(tmp);
lib/libedit/readline.c
988
ADD_STRING(tmp, len, 1);
lib/libedit/readline.c
990
if (tmp) {
lib/libedit/readline.c
991
free(tmp);
lib/libedit/readline.c
992
tmp = NULL;
lib/libedit/terminal.c
331
char **tmp, **str = &tlist[t - tstr];
lib/libedit/terminal.c
364
for (tmp = tlist; tmp < &tlist[T_str]; tmp++)
lib/libedit/terminal.c
365
if (*tmp != NULL && **tmp != '\0' && *tmp != *str) {
lib/libedit/terminal.c
368
for (ptr = *tmp; *ptr != '\0'; termbuf[tlen++] = *ptr++)
lib/libevent/buffer.c
83
struct evbuffer tmp;
lib/libevent/buffer.c
87
SWAP(&tmp, outbuf);
lib/libevent/buffer.c
89
SWAP(inbuf, &tmp);
lib/libevent/event_tagging.c
251
struct evbuffer tmp;
lib/libevent/event_tagging.c
258
tmp = *evbuf;
lib/libevent/event_tagging.c
259
tmp.buffer += len;
lib/libevent/event_tagging.c
260
tmp.off -= len;
lib/libevent/event_tagging.c
262
res = decode_int_internal(plength, &tmp, 0);
lib/libevent/event_tagging.c
274
struct evbuffer tmp;
lib/libevent/event_tagging.c
281
tmp = *evbuf;
lib/libevent/event_tagging.c
282
tmp.buffer += len;
lib/libevent/event_tagging.c
283
tmp.off -= len;
lib/libevent/event_tagging.c
285
res = decode_int_internal(plength, &tmp, 0);
lib/libexpat/lib/xmlparse.c
1023
XML_Char tmp[2] = {nsSep, 0};
lib/libexpat/lib/xmlparse.c
1024
return XML_ParserCreate_MM(encodingName, NULL, tmp);
lib/libexpat/lib/xmlparse.c
1842
XML_Char tmp[2] = {parser->m_namespaceSeparator, 0};
lib/libexpat/lib/xmlparse.c
1843
parser = parserCreate(encodingName, &parser->m_mem, tmp, newDtd, oldParser);
lib/libfido2/src/blob.c
47
u_char *tmp;
lib/libfido2/src/blob.c
58
if ((tmp = realloc(b->ptr, b->len + len)) == NULL) {
lib/libfido2/src/blob.c
62
b->ptr = tmp;
lib/libfido2/src/cred.c
217
fido_cred_ext_t tmp;
lib/libfido2/src/cred.c
220
memcpy(&tmp, ext, sizeof(tmp));
lib/libfido2/src/cred.c
221
tmp.mask &= ~FIDO_EXT_LARGEBLOB_KEY;
lib/libfido2/src/cred.c
223
return (timingsafe_bcmp(authdata_ext, &tmp, sizeof(*authdata_ext)));
lib/libfuse/fuse_subr.c
173
char *tmp = NULL;
lib/libfuse/fuse_subr.c
188
ret = asprintf(&tmp, "/%s%s", vn->path, name);
lib/libfuse/fuse_subr.c
190
ret = asprintf(&tmp, "/%s", vn->path);
lib/libfuse/fuse_subr.c
198
name = tmp;
lib/libfuse/fuse_subr.c
199
tmp = NULL;
lib/libkvm/kvm_file2.c
361
char *tmp = reallocarray(filebuf,
lib/libkvm/kvm_file2.c
365
if (tmp == NULL) {
lib/libkvm/kvm_file2.c
369
filebuf = tmp;
lib/libm/src/e_jn.c
152
double q0,q1,h,tmp; int32_t k,m;
lib/libm/src/e_jn.c
157
tmp = z*q1 - q0;
lib/libm/src/e_jn.c
159
q1 = tmp;
lib/libm/src/e_jn.c
173
tmp = n;
lib/libm/src/e_jn.c
175
tmp = tmp*log(fabs(v*tmp));
lib/libm/src/e_jn.c
176
if(tmp<7.09782712893383973096e+02) {
lib/libm/src/e_jnf.c
105
float q0,q1,h,tmp; int32_t k,m;
lib/libm/src/e_jnf.c
110
tmp = z*q1 - q0;
lib/libm/src/e_jnf.c
112
q1 = tmp;
lib/libm/src/e_jnf.c
126
tmp = n;
lib/libm/src/e_jnf.c
128
tmp = tmp*logf(fabsf(v*tmp));
lib/libm/src/e_jnf.c
129
if(tmp<(float)8.8721679688e+01) {
lib/libpcap/gencode.c
1150
struct block *b0, *b1, *b2, *tmp;
lib/libpcap/gencode.c
1187
tmp = gen_mcmp_nl(base_off + 2, BPF_H,
lib/libpcap/gencode.c
1191
gen_and(tmp, b1);
lib/libpcap/gencode.c
1193
tmp = gen_mcmp_nl(base_off + 2, BPF_B, (bpf_int32)0x06, (bpf_int32)0x7);
lib/libpcap/gencode.c
1195
gen_and(tmp, b2);
lib/libpcap/gencode.c
1198
tmp = gen_mcmp_nl(base_off + 2, BPF_H,
lib/libpcap/gencode.c
1202
gen_and(tmp, b2);
lib/libpcap/gencode.c
1205
tmp = gen_mcmp_nl(base_off + 2, BPF_B, (bpf_int32)0x02, (bpf_int32)0x7);
lib/libpcap/gencode.c
1207
gen_and(tmp, b2);
lib/libpcap/gencode.c
1383
struct block *b0, *b1, *tmp;
lib/libpcap/gencode.c
1403
tmp = gen_host(**alist++, 0xffffffff, proto, Q_OR);
lib/libpcap/gencode.c
1404
gen_or(b1, tmp);
lib/libpcap/gencode.c
1405
b1 = tmp;
lib/libpcap/gencode.c
1557
struct slist *s, *tmp;
lib/libpcap/gencode.c
1563
tmp = new_stmt(BPF_LD|BPF_H|BPF_IND);
lib/libpcap/gencode.c
1564
tmp->s.k = 6;
lib/libpcap/gencode.c
1565
sappend(s, tmp);
lib/libpcap/gencode.c
1585
struct slist *s, *tmp;
lib/libpcap/gencode.c
1594
tmp = new_stmt(BPF_LD|BPF_B|BPF_IND);
lib/libpcap/gencode.c
1595
tmp->s.k = 0;
lib/libpcap/gencode.c
1596
sappend(s, tmp);
lib/libpcap/gencode.c
1599
tmp = new_stmt(BPF_ALU|BPF_AND|BPF_K);
lib/libpcap/gencode.c
1600
tmp->s.k = 0x0f;
lib/libpcap/gencode.c
1601
sappend(s, tmp);
lib/libpcap/gencode.c
1604
tmp = new_stmt(BPF_ALU|BPF_LSH|BPF_K);
lib/libpcap/gencode.c
1605
tmp->s.k = 2;
lib/libpcap/gencode.c
1606
sappend(s, tmp);
lib/libpcap/gencode.c
1613
tmp = new_stmt(BPF_ST);
lib/libpcap/gencode.c
1614
tmp->s.k = iphl_reg;
lib/libpcap/gencode.c
1615
sappend(s, tmp);
lib/libpcap/gencode.c
1633
struct slist *s, *tmp;
lib/libpcap/gencode.c
1638
tmp = new_stmt(BPF_LD|BPF_IND|BPF_H);
lib/libpcap/gencode.c
1639
tmp->s.k = off_nl + off; /* off_nl == 0 if variable_nl */
lib/libpcap/gencode.c
1640
sappend(s, tmp);
lib/libpcap/gencode.c
1660
struct block *b0, *b1, *tmp;
lib/libpcap/gencode.c
1663
tmp = gen_cmp_nl(9, BPF_B, (bpf_int32)proto);
lib/libpcap/gencode.c
1665
gen_and(tmp, b0);
lib/libpcap/gencode.c
1678
tmp = gen_portatom(0, (bpf_int32)port);
lib/libpcap/gencode.c
1680
gen_or(tmp, b1);
lib/libpcap/gencode.c
1684
tmp = gen_portatom(0, (bpf_int32)port);
lib/libpcap/gencode.c
1686
gen_and(tmp, b1);
lib/libpcap/gencode.c
1700
struct block *b0, *b1, *tmp;
lib/libpcap/gencode.c
1712
tmp = gen_portop(port, IPPROTO_TCP, dir);
lib/libpcap/gencode.c
1714
gen_or(tmp, b1);
lib/libpcap/gencode.c
1728
struct block *b0, *b1, *tmp;
lib/libpcap/gencode.c
1744
tmp = gen_portatom6(0, (bpf_int32)port);
lib/libpcap/gencode.c
1746
gen_or(tmp, b1);
lib/libpcap/gencode.c
1750
tmp = gen_portatom6(0, (bpf_int32)port);
lib/libpcap/gencode.c
1752
gen_and(tmp, b1);
lib/libpcap/gencode.c
1766
struct block *b0, *b1, *tmp;
lib/libpcap/gencode.c
1778
tmp = gen_portop6(port, IPPROTO_TCP, dir);
lib/libpcap/gencode.c
1780
gen_or(tmp, b1);
lib/libpcap/gencode.c
2252
struct block *b, *tmp;
lib/libpcap/gencode.c
2319
tmp = gen_host(**alist++, 0xffffffff,
lib/libpcap/gencode.c
2321
gen_or(b, tmp);
lib/libpcap/gencode.c
2322
b = tmp;
lib/libpcap/gencode.c
2330
b = tmp = NULL;
lib/libpcap/gencode.c
2344
tmp = gen_host(ntohl(sin->sin_addr.s_addr),
lib/libpcap/gencode.c
2353
tmp = gen_host6(&sin6->sin6_addr,
lib/libpcap/gencode.c
2358
gen_or(b, tmp);
lib/libpcap/gencode.c
2359
b = tmp;
lib/libpcap/gencode.c
2666
struct slist *s, *tmp;
lib/libpcap/gencode.c
2694
tmp = new_stmt(BPF_LD|BPF_IND|size);
lib/libpcap/gencode.c
2695
sappend(s, tmp);
lib/libpcap/gencode.c
2720
tmp = new_stmt(BPF_LD|BPF_IND|size);
lib/libpcap/gencode.c
2721
tmp->s.k = off_nl; /* off_nl == 0 for variable_nl */
lib/libpcap/gencode.c
2722
sappend(s, tmp);
lib/libpcap/gencode.c
2741
sappend(s, tmp = new_stmt(BPF_LD|BPF_IND|size));
lib/libpcap/gencode.c
2742
tmp->s.k = off_nl; /* off_nl is 0 if variable_nl */
lib/libpcap/gencode.c
2771
struct block *b, *tmp;
lib/libpcap/gencode.c
2797
gen_and(a0->b, tmp = a1->b);
lib/libpcap/gencode.c
2800
tmp = a0->b;
lib/libpcap/gencode.c
2802
tmp = a1->b;
lib/libpcap/gencode.c
2804
if (tmp)
lib/libpcap/gencode.c
2805
gen_and(tmp, b);
lib/libpcap/gencode.c
533
struct block *b, *tmp;
lib/libpcap/gencode.c
541
tmp = gen_cmp(offset + size - 4, BPF_W, w);
lib/libpcap/gencode.c
543
gen_and(b, tmp);
lib/libpcap/gencode.c
544
b = tmp;
lib/libpcap/gencode.c
551
tmp = gen_cmp(offset + size - 2, BPF_H, w);
lib/libpcap/gencode.c
553
gen_and(b, tmp);
lib/libpcap/gencode.c
554
b = tmp;
lib/libpcap/gencode.c
558
tmp = gen_cmp(offset, BPF_B, (bpf_int32)v[0]);
lib/libpcap/gencode.c
560
gen_and(b, tmp);
lib/libpcap/gencode.c
561
b = tmp;
lib/libpcap/gencode.c
581
struct slist *s, *tmp;
lib/libpcap/gencode.c
592
tmp = new_stmt(BPF_ALU|BPF_ADD|BPF_K);
lib/libpcap/gencode.c
593
tmp->s.k = 3;
lib/libpcap/gencode.c
594
sappend(s, tmp);
lib/libpcap/gencode.c
596
tmp = new_stmt(BPF_ALU|BPF_AND|BPF_K);
lib/libpcap/gencode.c
597
tmp->s.k = 0xfc;
lib/libpcap/gencode.c
598
sappend(s, tmp);
lib/libpcap/gencode.c
601
tmp = new_stmt(BPF_ST);
lib/libpcap/gencode.c
602
tmp->s.k = nl_reg;
lib/libpcap/gencode.c
603
sappend(s, tmp);
lib/libpcap/gencode.c
627
struct slist *s, *tmp;
lib/libpcap/gencode.c
632
tmp = new_stmt(BPF_LD|BPF_IND|size);
lib/libpcap/gencode.c
633
tmp->s.k = offset;
lib/libpcap/gencode.c
634
sappend(s, tmp);
lib/libpcap/optimize.c
1503
struct slist *tmp, *s;
lib/libpcap/optimize.c
1510
tmp = (*b)->stmts;
lib/libpcap/optimize.c
1511
if (tmp != 0)
lib/libpcap/optimize.c
1512
sappend(s, tmp);
lib/libpcap/optimize.c
628
struct block *tmp = JT(b);
lib/libpcap/optimize.c
631
JF(b) = tmp;
lib/libsndio/aucat.c
208
char *home, *dir = NULL, *path = NULL, *tmp = NULL;
lib/libsndio/aucat.c
262
if (asprintf(&tmp, "%s.XXXXXXXX", path) == -1)
lib/libsndio/aucat.c
264
fd = mkstemp(tmp);
lib/libsndio/aucat.c
266
DPERROR(tmp);
lib/libsndio/aucat.c
270
DPERROR(tmp);
lib/libsndio/aucat.c
271
unlink(tmp);
lib/libsndio/aucat.c
276
if (rename(tmp, path) == -1) {
lib/libsndio/aucat.c
277
DPERROR(tmp);
lib/libsndio/aucat.c
278
unlink(tmp);
lib/libsndio/aucat.c
281
free(tmp);
lib/libssl/ssl_lib.c
961
SSL_CERT *tmp;
lib/libssl/ssl_lib.c
975
tmp = t->cert;
lib/libssl/ssl_lib.c
981
ssl_cert_free(tmp);
lib/libssl/ssl_sess.c
435
unsigned int tmp;
lib/libssl/ssl_sess.c
486
tmp = ss->session_id_length;
lib/libssl/ssl_sess.c
487
if (!cb(s, ss->session_id, &tmp)) {
lib/libssl/ssl_sess.c
498
if (tmp == 0 || tmp > ss->session_id_length) {
lib/libssl/ssl_sess.c
504
ss->session_id_length = tmp;
lib/libtls/tls_conninfo.c
254
const char *tmp;
lib/libtls/tls_conninfo.c
266
if ((tmp = SSL_get_cipher(ctx->ssl_conn)) == NULL)
lib/libtls/tls_conninfo.c
268
if ((ctx->conninfo->cipher = strdup(tmp)) == NULL)
lib/libtls/tls_conninfo.c
278
if ((tmp = SSL_get_version(ctx->ssl_conn)) == NULL)
lib/libtls/tls_conninfo.c
280
if ((ctx->conninfo->version = strdup(tmp)) == NULL)
lib/libz/adler32.c
25
unsigned long tmp = a >> 16; \
lib/libz/adler32.c
27
a += (tmp << 4) - tmp; \
lib/libz/adler32.c
41
z_off64_t tmp = a >> 32; \
lib/libz/adler32.c
43
a += (tmp << 8) - (tmp << 5) + tmp; \
lib/libz/adler32.c
44
tmp = a >> 16; \
lib/libz/adler32.c
46
a += (tmp << 4) - tmp; \
lib/libz/adler32.c
47
tmp = a >> 16; \
lib/libz/adler32.c
49
a += (tmp << 4) - tmp; \
libexec/ftpd/ftpd.c
1862
union sockunion tmp = *su;
libexec/ftpd/ftpd.c
1864
if (tmp.su_family == AF_INET6)
libexec/ftpd/ftpd.c
1865
tmp.su_sin6.sin6_scope_id = 0;
libexec/ftpd/ftpd.c
1866
if (getnameinfo((struct sockaddr *)&tmp, tmp.su_len,
libexec/ftpd/ftpd.c
2410
char *tmp = NULL;
libexec/ftpd/ftpd.c
2430
tmp = strdup(arg);
libexec/ftpd/ftpd.c
2431
if (!tmp) {
libexec/ftpd/ftpd.c
2435
p = tmp;
libexec/ftpd/ftpd.c
2483
free(tmp);
libexec/ftpd/ftpd.c
2491
free(tmp);
libexec/ftpd/ftpd.c
2499
free(tmp);
libexec/ld.so/alpha/rtld_machine.c
121
Elf_Addr tmp;
libexec/ld.so/alpha/rtld_machine.c
126
_dl_bcopy(r_addr, &tmp, sizeof(Elf_Addr));
libexec/ld.so/alpha/rtld_machine.c
127
tmp += loff;
libexec/ld.so/alpha/rtld_machine.c
128
_dl_bcopy(&tmp, r_addr, sizeof(Elf_Addr));
libexec/ld.so/alpha/rtld_machine.c
82
Elf_Addr tmp;
libexec/ld.so/alpha/rtld_machine.c
83
_dl_bcopy(r_addr, &tmp, sizeof(Elf_Addr));
libexec/ld.so/alpha/rtld_machine.c
84
tmp += loff;
libexec/ld.so/alpha/rtld_machine.c
85
_dl_bcopy(&tmp, r_addr, sizeof(Elf_Addr));
libexec/ld.so/chacha_private.h
118
for (i = 0;i < bytes;++i) tmp[i] = m[i];
libexec/ld.so/chacha_private.h
119
m = tmp;
libexec/ld.so/chacha_private.h
121
c = tmp;
libexec/ld.so/chacha_private.h
94
u8 tmp[64];
libexec/ld.so/malloc.c
206
size_t d_avail, regioninfo_size, tmp;
libexec/ld.so/malloc.c
226
_dl_arc4randombuf(&tmp, sizeof(tmp));
libexec/ld.so/malloc.c
228
((tmp % d_avail) << MALLOC_MINSHIFT)); /* not uniform */
libexec/ld.so/malloc.c
946
void *tmp;
libexec/ld.so/malloc.c
960
tmp = p;
libexec/ld.so/malloc.c
962
g_pool->delayed_chunks[i] = tmp;
libexec/ld.so/sparc64/rtld_machine.c
315
Elf_Addr tmp = 0;
libexec/ld.so/sparc64/rtld_machine.c
321
tmp = (tmp << 8) | ptr[i];
libexec/ld.so/sparc64/rtld_machine.c
323
tmp &= ~mask;
libexec/ld.so/sparc64/rtld_machine.c
324
tmp |= value;
libexec/ld.so/sparc64/rtld_machine.c
328
ptr[i] = ((tmp >> (8*i)) & 0xff);
libexec/login_ldap/login_ldap.c
192
char *tmp;
libexec/login_ldap/login_ldap.c
233
tmp = ctx.gfilter;
libexec/login_ldap/login_ldap.c
236
free(tmp);
libexec/login_ldap/login_ldap.c
237
tmp = ctx.gbasedn;
libexec/login_ldap/login_ldap.c
240
free(tmp);
libexec/login_ldap/util.c
463
char tmp[PATH_MAX];
libexec/login_ldap/util.c
475
for (p = str, q = tmp; p[0] != '\0' &&
libexec/login_ldap/util.c
476
((size_t)(q - tmp) < sizeof(tmp)); p++) {
libexec/login_ldap/util.c
489
q = tmp + strlcat(tmp, ctx->user, sizeof(tmp));
libexec/login_ldap/util.c
498
q = tmp + strlcat(tmp, hostname, sizeof(tmp));
libexec/login_ldap/util.c
505
q = tmp + strlcat(tmp, ctx->userdn,
libexec/login_ldap/util.c
506
sizeof(tmp));
libexec/login_ldap/util.c
522
if ((size_t) (q - tmp) >= sizeof(tmp)) {
libexec/login_ldap/util.c
528
q = strdup(tmp);
libexec/login_token/token.c
165
TOKEN_CBlock tmp;
libexec/login_token/token.c
179
tmp.ul[0] = strtoul(state, NULL, 10);
libexec/login_token/token.c
180
snprintf(tokennumber.ct, sizeof(tokennumber.ct), "%8.8u",tmp.ul[0]);
libexec/snmpd/snmpd_metrics/kroute.c
448
struct kroute_node *kn, *tmp;
libexec/snmpd/snmpd_metrics/kroute.c
456
tmp = RB_PREV(kroute_tree, &kt->krt, kn);
libexec/snmpd/snmpd_metrics/kroute.c
457
while (tmp) {
libexec/snmpd/snmpd_metrics/kroute.c
458
if (kroute_compare(&s, tmp) == 0)
libexec/snmpd/snmpd_metrics/kroute.c
459
kn = tmp;
libexec/snmpd/snmpd_metrics/kroute.c
462
tmp = RB_PREV(kroute_tree, &kt->krt, kn);
libexec/snmpd/snmpd_metrics/kroute.c
562
struct kroute6_node *kn6, *tmp;
libexec/snmpd/snmpd_metrics/kroute.c
570
tmp = RB_PREV(kroute6_tree, &kt->krt6, kn6);
libexec/snmpd/snmpd_metrics/kroute.c
571
while (tmp) {
libexec/snmpd/snmpd_metrics/kroute.c
572
if (kroute6_compare(&s, tmp) == 0)
libexec/snmpd/snmpd_metrics/kroute.c
573
kn6 = tmp;
libexec/snmpd/snmpd_metrics/kroute.c
576
tmp = RB_PREV(kroute6_tree, &kt->krt6, kn6);
libexec/spamd-setup/spamd-setup.c
143
struct cidr *tmp;
libexec/spamd-setup/spamd-setup.c
151
tmp = reallocarray(list, *cls + 32,
libexec/spamd-setup/spamd-setup.c
153
if (tmp == NULL)
libexec/spamd-setup/spamd-setup.c
155
list = tmp;
libexec/spamd-setup/spamd-setup.c
399
char *buf = NULL, last, *tmp;
libexec/spamd-setup/spamd-setup.c
419
tmp = realloc(buf, bs + 8192);
libexec/spamd-setup/spamd-setup.c
420
if (tmp == NULL)
libexec/spamd-setup/spamd-setup.c
423
buf = tmp;
libexec/spamd-setup/spamd-setup.c
471
char *buf = NULL, *tmp;
libexec/spamd-setup/spamd-setup.c
477
tmp = realloc(buf, bs + (1024 * 1024) + 1);
libexec/spamd-setup/spamd-setup.c
478
if (tmp == NULL) {
libexec/spamd-setup/spamd-setup.c
486
buf = tmp;
libexec/spamd-setup/spamd-setup.c
878
struct blacklist *tmp;
libexec/spamd-setup/spamd-setup.c
881
tmp = reallocarray(blists, bls,
libexec/spamd-setup/spamd-setup.c
883
if (tmp == NULL)
libexec/spamd-setup/spamd-setup.c
885
blists = tmp;
libexec/spamd/grey.c
353
char **tmp;
libexec/spamd/grey.c
355
tmp = reallocarray(whitelist,
libexec/spamd/grey.c
357
if (tmp == NULL) {
libexec/spamd/grey.c
361
whitelist = tmp;
libexec/spamd/grey.c
388
char **tmp;
libexec/spamd/grey.c
390
tmp = reallocarray(traplist,
libexec/spamd/grey.c
392
if (tmp == NULL) {
libexec/spamd/grey.c
396
traplist = tmp;
libexec/spamd/grey.c
548
char *tmp;
libexec/spamd/grey.c
550
tmp = reallocarray(a, dbk.size, 2);
libexec/spamd/grey.c
551
if (tmp == NULL)
libexec/spamd/grey.c
553
a = tmp;
libexec/spamd/sdl.c
132
struct sdlist *tmp;
libexec/spamd/sdl.c
134
tmp = reallocarray(blacklists, blc + 128,
libexec/spamd/sdl.c
136
if (tmp == NULL)
libexec/spamd/sdl.c
138
blacklists = tmp;
libexec/spamd/sdl.c
358
struct sdlist **tmp; \
libexec/spamd/sdl.c
360
tmp = reallocarray(sd, l + 128, sizeof(struct sdlist *)); \
libexec/spamd/sdl.c
361
if (tmp == NULL) { \
libexec/spamd/sdl.c
367
sd = tmp; \
libexec/spamd/spamd.c
191
char *tmp;
libexec/spamd/spamd.c
193
tmp = realloc(cp->obuf, cp->osize + 8192);
libexec/spamd/spamd.c
194
if (tmp == NULL) {
libexec/spamd/spamd.c
201
cp->obuf = tmp;
libexec/spamd/spamd.c
209
char *cp, prev, *name, *msg, *tmp;
libexec/spamd/spamd.c
262
while ((tmp = strsep(&cp, ";")) != NULL) {
libexec/spamd/spamd.c
266
if (*tmp == '\0')
libexec/spamd/spamd.c
269
if (strncmp(tmp, "inet", 4) != 0)
libexec/spamd/spamd.c
271
switch (tmp[4]) {
libexec/spamd/spamd.c
276
if (tmp[5] == '\0') {
libexec/spamd/spamd.c
283
printf("unsupported address family: %s\n", tmp);
libexec/spamd/spamd.c
287
tmp = strsep(&cp, ";");
libexec/spamd/spamd.c
288
if (tmp == NULL) {
libexec/spamd/spamd.c
293
ac = strtonum(tmp, 0, UINT_MAX, &errstr);
libexec/spamd/spamd.c
296
printf("count \"%s\" is %s\n", tmp, errstr);
libexec/spamd/spamd.c
302
tmp = strsep(&cp, ";");
libexec/spamd/spamd.c
303
if (tmp == NULL) {
libexec/spamd/spamd.c
310
if (*tmp == '\0')
libexec/spamd/spamd.c
312
av[au] = tmp;
libexec/spamd/spamd.c
384
char *tmp;
libexec/spamd/spamd.c
386
tmp = realloc(cb, cbs + (1024 * 1024));
libexec/spamd/spamd.c
387
if (tmp == NULL) {
libexec/spamd/spamd.c
393
cb = tmp;
libexec/tradcpp/eval.c
655
char tmp;
libexec/tradcpp/eval.c
661
tmp = expr[pos + len];
libexec/tradcpp/eval.c
664
expr[pos + len] = tmp;
libexec/tradcpp/files.c
181
size_t bufend, bufmax, linestart, lineend, nextlinestart, tmp;
libexec/tradcpp/files.c
281
tmp = nextlinestart - lineend;
libexec/tradcpp/files.c
286
bufend -= tmp;
libexec/tradcpp/files.c
287
nextlinestart -= tmp;
regress/lib/libc/asr/bin/res_mkquery.c
198
char tmp[256];
regress/lib/libc/asr/bin/res_mkquery.c
205
print_dname(rr->rr_dname, tmp, sizeof tmp),
regress/lib/libc/asr/bin/res_mkquery.c
227
print_dname(rr->rr.mx.exchange, tmp, sizeof tmp));
regress/lib/libc/asr/bin/res_mkquery.c
238
print_dname(rr->rr.soa.rname, tmp, sizeof tmp),
regress/lib/libc/asr/bin/res_query.c
234
char tmp[256];
regress/lib/libc/asr/bin/res_query.c
241
print_dname(rr->rr_dname, tmp, sizeof tmp),
regress/lib/libc/asr/bin/res_query.c
263
print_dname(rr->rr.mx.exchange, tmp, sizeof tmp));
regress/lib/libc/asr/bin/res_query.c
274
print_dname(rr->rr.soa.rname, tmp, sizeof tmp),
regress/lib/libc/strtod/strtodtest.c
16
char *tmp="0.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002";
regress/lib/libc/strtod/strtodtest.c
19
d = strtod(tmp, NULL);
regress/lib/libc/sys/t_revoke.c
58
char tmp[10];
regress/lib/libc/sys/t_revoke.c
83
ATF_REQUIRE(read(buf[i], tmp, sizeof(tmp)) == -1);
regress/lib/libcrypto/ec/ectest.c
186
EC_GROUP *tmp;
regress/lib/libcrypto/ec/ectest.c
188
if ((tmp = EC_GROUP_dup(group)) == NULL)
regress/lib/libcrypto/ec/ectest.c
191
group = tmp;
regress/lib/libevent/event_regress.c
1562
struct evbuffer *tmp = evbuffer_new();
regress/lib/libevent/event_regress.c
1571
oldlen = EVBUFFER_LENGTH(tmp);
regress/lib/libevent/event_regress.c
1572
encode_int(tmp, integers[i]);
regress/lib/libevent/event_regress.c
1573
newlen = EVBUFFER_LENGTH(tmp);
regress/lib/libevent/event_regress.c
1579
if (evtag_decode_int(&integer, tmp) == -1) {
regress/lib/libevent/event_regress.c
1590
if (EVBUFFER_LENGTH(tmp) != 0) {
regress/lib/libevent/event_regress.c
1594
evbuffer_free(tmp);
regress/lib/libevent/event_regress.c
1603
struct evbuffer *tmp = evbuffer_new();
regress/lib/libevent/event_regress.c
1611
evbuffer_drain(tmp, -1);
regress/lib/libevent/event_regress.c
1612
evbuffer_add(tmp, buffer, sizeof(buffer));
regress/lib/libevent/event_regress.c
1614
if (evtag_unmarshal_timeval(tmp, 0, &tv) != -1)
regress/lib/libevent/event_regress.c
1625
evbuffer_drain(tmp, -1);
regress/lib/libevent/event_regress.c
1628
evtag_marshal_timeval(tmp, 0, &tv);
regress/lib/libevent/event_regress.c
1629
evbuffer_add(tmp, buffer, sizeof(buffer));
regress/lib/libevent/event_regress.c
1631
EVBUFFER_DATA(tmp)[1] = 0xff;
regress/lib/libevent/event_regress.c
1632
if (evtag_unmarshal_timeval(tmp, 0, &tv) != -1) {
regress/lib/libevent/event_regress.c
1637
evbuffer_free(tmp);
regress/lib/libevent/event_regress.c
1645
struct evbuffer *tmp = evbuffer_new();
regress/lib/libevent/event_regress.c
1654
oldlen = EVBUFFER_LENGTH(tmp);
regress/lib/libevent/event_regress.c
1655
evtag_encode_tag(tmp, integers[i]);
regress/lib/libevent/event_regress.c
1656
newlen = EVBUFFER_LENGTH(tmp);
regress/lib/libevent/event_regress.c
1662
if (evtag_decode_tag(&integer, tmp) == -1) {
regress/lib/libevent/event_regress.c
1673
if (EVBUFFER_LENGTH(tmp) != 0) {
regress/lib/libevent/event_regress.c
1677
evbuffer_free(tmp);
regress/lib/libevent/event_regress.c
1704
struct evbuffer *tmp = evbuffer_new();
regress/lib/libevent/event_regress.c
1740
evtag_marshal_msg(tmp, 0xdeaf, msg);
regress/lib/libevent/event_regress.c
1742
if (evtag_peek(tmp, &tag) == -1) {
regress/lib/libevent/event_regress.c
1753
if (evtag_unmarshal_msg(tmp, 0xdeaf, msg2) == -1) {
regress/lib/libevent/event_regress.c
1779
evbuffer_free(tmp);
regress/lib/libpthread/sigsuspend/sigsuspend.c
101
sigset_t tmp;
regress/lib/libpthread/sigsuspend/sigsuspend.c
124
tmp = suspender_mask;
regress/lib/libpthread/sigsuspend/sigsuspend.c
125
sigaddset(&tmp, signo);
regress/lib/libpthread/sigsuspend/sigsuspend.c
126
sigdelset(&tmp, SIGTHR);
regress/lib/libpthread/sigsuspend/sigsuspend.c
128
ASSERT(set == tmp);
regress/lib/libssl/bytestring/bytestringtest.c
880
uint8_t *tmp = NULL;
regress/lib/libssl/bytestring/bytestringtest.c
882
CHECK_GOTO((tmp = malloc(sizeof(input))) != NULL);
regress/lib/libssl/bytestring/bytestringtest.c
883
memset(tmp, 100, sizeof(input));
regress/lib/libssl/bytestring/bytestringtest.c
892
CHECK_GOTO(CBS_write_bytes(&data, tmp, sizeof(input), &len));
regress/lib/libssl/bytestring/bytestringtest.c
894
CHECK_GOTO(memcmp(input + 2, tmp, len) == 0);
regress/lib/libssl/bytestring/bytestringtest.c
895
CHECK_GOTO(tmp[4] == 100 && tmp[5] == 100);
regress/lib/libssl/bytestring/bytestringtest.c
900
free(tmp);
regress/sbin/iked/test_helper/test_helper.c
299
char tmp[64];
regress/sbin/iked/test_helper/test_helper.c
307
snprintf(tmp, sizeof(tmp), "(%s)[%zu]", a1, where);
regress/sbin/iked/test_helper/test_helper.c
308
fprintf(stderr, "%20s = 0x%02x (expected 0x%02x)\n", tmp,
regress/sys/crypto/aes/aestest.c
176
u_int keylen, textlen, tmp;
regress/sys/crypto/aes/aestest.c
182
keylen = textlen = tmp = 0;
regress/sys/crypto/aes/aestest.c
214
parsehex(cp, &plaintext, &tmp);
regress/sys/crypto/aes/aestest.c
215
if (tmp * 8 != (u_int)blocksize)
regress/sys/crypto/aes/aestest.c
217
"blocklen %d", lnum, tmp, blocksize);
regress/sys/crypto/aes/aestest.c
219
if (textlen != tmp)
regress/sys/crypto/aes/aestest.c
221
"ciphertext len %d", lnum, tmp,
regress/sys/crypto/aes/aestest.c
224
textlen = tmp;
regress/sys/crypto/aes/aestest.c
228
parsehex(cp, &ciphertext, &tmp);
regress/sys/crypto/aes/aestest.c
229
if (tmp * 8 != (u_int)blocksize)
regress/sys/crypto/aes/aestest.c
231
"blocklen %d", lnum, tmp, blocksize);
regress/sys/crypto/aes/aestest.c
233
if (textlen != tmp)
regress/sys/crypto/aes/aestest.c
235
"plaintext len %d", lnum, tmp,
regress/sys/crypto/aes/aestest.c
238
textlen = tmp;
regress/sys/crypto/aes/aestest.c
245
"blocklen %d", lnum, tmp, textlen);
regress/sys/net/pf_print/pf_print_test.c
111
char *tmp;
regress/sys/net/pf_print/pf_print_test.c
113
if ((tmp = malloc(len + 1)) == NULL)
regress/sys/net/pf_print/pf_print_test.c
115
memcpy(tmp, out, len);
regress/sys/net/pf_print/pf_print_test.c
116
tmp[len] = '\0';
regress/sys/net/pf_print/pf_print_test.c
117
out = tmp;
regress/sys/sys/tree/rb-linux/rb-linux.c
102
tmp = malloc(sizeof(struct keynode));
regress/sys/sys/tree/rb-linux/rb-linux.c
103
if (tmp == NULL)
regress/sys/sys/tree/rb-linux/rb-linux.c
106
tmp->key = arc4random_uniform(MAX - MIN);
regress/sys/sys/tree/rb-linux/rb-linux.c
107
tmp->key += MIN;
regress/sys/sys/tree/rb-linux/rb-linux.c
108
} while (rb_find(&root, tmp) != NULL);
regress/sys/sys/tree/rb-linux/rb-linux.c
110
max = min = tmp->key;
regress/sys/sys/tree/rb-linux/rb-linux.c
112
if (tmp->key > max)
regress/sys/sys/tree/rb-linux/rb-linux.c
113
max = tmp->key;
regress/sys/sys/tree/rb-linux/rb-linux.c
114
if (tmp->key < min)
regress/sys/sys/tree/rb-linux/rb-linux.c
115
min = tmp->key;
regress/sys/sys/tree/rb-linux/rb-linux.c
117
if (rb_insert(&root, tmp) != NULL)
regress/sys/sys/tree/rb-linux/rb-linux.c
125
tmp = ins;
regress/sys/sys/tree/rb-linux/rb-linux.c
131
rb_erase(&tmp->node, &root);
regress/sys/sys/tree/rb-linux/rb-linux.c
137
tmp = container_of(rb_node, struct keynode, node);
regress/sys/sys/tree/rb-linux/rb-linux.c
138
rb_erase(&tmp->node, &root);
regress/sys/sys/tree/rb-linux/rb-linux.c
139
free(tmp);
regress/sys/sys/tree/rb-linux/rb-linux.c
48
struct rb_node *tmp = head->rb_node;
regress/sys/sys/tree/rb-linux/rb-linux.c
50
while (tmp) {
regress/sys/sys/tree/rb-linux/rb-linux.c
51
struct keynode *n = container_of(tmp, struct keynode, node);
regress/sys/sys/tree/rb-linux/rb-linux.c
53
tmp = tmp->rb_left;
regress/sys/sys/tree/rb-linux/rb-linux.c
55
tmp = tmp->rb_right;
regress/sys/sys/tree/rb-linux/rb-linux.c
65
struct rb_node **tmp;
regress/sys/sys/tree/rb-linux/rb-linux.c
67
tmp = &(head->rb_node);
regress/sys/sys/tree/rb-linux/rb-linux.c
69
while (*tmp) {
regress/sys/sys/tree/rb-linux/rb-linux.c
70
struct keynode *n = container_of(*tmp, struct keynode, node);
regress/sys/sys/tree/rb-linux/rb-linux.c
71
parent = *tmp;
regress/sys/sys/tree/rb-linux/rb-linux.c
73
tmp = &((*tmp)->rb_left);
regress/sys/sys/tree/rb-linux/rb-linux.c
75
tmp = &((*tmp)->rb_right);
regress/sys/sys/tree/rb-linux/rb-linux.c
80
rb_link_node(&elm->node, parent, tmp);
regress/sys/sys/tree/rb-linux/rb-linux.c
94
struct keynode *tmp, *ins;
regress/sys/sys/tree/rb/rb-test.c
135
struct node *tmp, *ins, *nodes;
regress/sys/sys/tree/rb/rb-test.c
239
tmp = RB_ROOT(&root);
regress/sys/sys/tree/rb/rb-test.c
240
assert(NULL != tmp);
regress/sys/sys/tree/rb/rb-test.c
241
assert(RB_REMOVE(tree, &root, tmp) == tmp);
regress/sys/sys/tree/rb/rb-test.c
278
tmp = RB_ROOT(&root);
regress/sys/sys/tree/rb/rb-test.c
279
assert(NULL != tmp);
regress/sys/sys/tree/rb/rb-test.c
280
assert(RB_REMOVE(tree, &root, tmp) == tmp);
regress/sys/sys/tree/rb/rb-test.c
311
tmp = malloc(sizeof(struct node));
regress/sys/sys/tree/rb/rb-test.c
313
tmp->key = i;
regress/sys/sys/tree/rb/rb-test.c
314
ins = RB_FIND(tree, &root, tmp);
regress/sys/sys/tree/rb/rb-test.c
315
assert(NULL != tmp);
regress/sys/sys/tree/rb/rb-test.c
325
free(tmp);
regress/sys/sys/tree/rb/rb-test.c
355
tmp = malloc(sizeof(struct node));
regress/sys/sys/tree/rb/rb-test.c
357
tmp->key = perm[i];
regress/sys/sys/tree/rb/rb-test.c
358
ins = RB_FIND(tree, &root, tmp);
regress/sys/sys/tree/rb/rb-test.c
372
free(tmp);
regress/sys/sys/tree/rb/rb-test.c
401
tmp = malloc(sizeof(struct node));
regress/sys/sys/tree/rb/rb-test.c
403
tmp->key = i;
regress/sys/sys/tree/rb/rb-test.c
404
ins = RB_NFIND(tree, &root, tmp);
regress/sys/sys/tree/rb/rb-test.c
417
free(tmp);
regress/sys/sys/tree/rb/rb-test.c
441
tmp = malloc(sizeof(struct node));
regress/sys/sys/tree/rb/rb-test.c
443
tmp->key = ITER + 6;
regress/sys/sys/tree/rb/rb-test.c
444
ins = RB_PFIND(tree, &root, tmp);
regress/sys/sys/tree/rb/rb-test.c
457
free(tmp);
regress/sys/sys/tree/rb/rb-test.c
480
tmp = RB_MIN(tree, &root);
regress/sys/sys/tree/rb/rb-test.c
481
assert(tmp != NULL);
regress/sys/sys/tree/rb/rb-test.c
482
assert(tmp->key == 0);
regress/sys/sys/tree/rb/rb-test.c
484
tmp = RB_NEXT(tree, &root, tmp);
regress/sys/sys/tree/rb/rb-test.c
485
assert(tmp != NULL);
regress/sys/sys/tree/rb/rb-test.c
486
assert(tmp->key == i);
regress/sys/sys/tree/rb/rb-test.c
495
tmp = RB_MAX(tree, &root);
regress/sys/sys/tree/rb/rb-test.c
496
assert(tmp != NULL);
regress/sys/sys/tree/rb/rb-test.c
497
assert(tmp->key == ITER + 5);
regress/sys/sys/tree/rb/rb-test.c
499
tmp = RB_PREV(tree, &root, tmp);
regress/sys/sys/tree/rb/rb-test.c
500
assert(tmp != NULL);
regress/sys/sys/tree/rb/rb-test.c
501
assert(tmp->key == ITER - 1 - i);
regress/sys/sys/tree/rb/rb-test.c
511
tmp = RB_ROOT(&root);
regress/sys/sys/tree/rb/rb-test.c
512
assert(NULL != tmp);
regress/sys/sys/tree/rb/rb-test.c
513
assert(RB_REMOVE(tree, &root, tmp) == tmp);
regress/sys/sys/tree/rb/rb-test.c
579
tmp = RB_ROOT(&root);
regress/sys/sys/tree/rb/rb-test.c
580
assert(NULL != tmp);
regress/sys/sys/tree/rb/rb-test.c
581
assert(RB_REMOVE(tree, &root, tmp) == tmp);
regress/sys/sys/tree/rb/rb-test.c
607
RB_FOREACH_SAFE(ins, tree, &root, tmp) {
regress/sys/sys/tree/rb/rb-test.c
633
RB_FOREACH_REVERSE_SAFE(ins, tree, &root, tmp) {
regress/sys/sys/tree/rb/rb-test.c
657
tmp = &(nodes[0]);
regress/sys/sys/tree/rb/rb-test.c
658
tmp->size = 1;
regress/sys/sys/tree/rb/rb-test.c
659
tmp->height = 1;
regress/sys/sys/tree/rb/rb-test.c
660
tmp->key = 0;
regress/sys/sys/tree/rb/rb-test.c
661
if (RB_INSERT(tree, &root, tmp) != NULL)
regress/sys/sys/tree/rb/rb-test.c
663
ins = tmp;
regress/sys/sys/tree/rb/rb-test.c
665
tmp = &(nodes[i]);
regress/sys/sys/tree/rb/rb-test.c
666
tmp->size = 1;
regress/sys/sys/tree/rb/rb-test.c
667
tmp->height = 1;
regress/sys/sys/tree/rb/rb-test.c
668
tmp->key = i;
regress/sys/sys/tree/rb/rb-test.c
669
if (RB_INSERT_NEXT(tree, &root, ins, tmp) != NULL)
regress/sys/sys/tree/rb/rb-test.c
671
ins = tmp;
regress/sys/sys/tree/rb/rb-test.c
687
RB_FOREACH_REVERSE_SAFE(ins, tree, &root, tmp) {
regress/sys/sys/tree/rb/rb-test.c
706
tmp = &(nodes[ITER]);
regress/sys/sys/tree/rb/rb-test.c
707
tmp->size = 1;
regress/sys/sys/tree/rb/rb-test.c
708
tmp->height = 1;
regress/sys/sys/tree/rb/rb-test.c
709
tmp->key = ITER;
regress/sys/sys/tree/rb/rb-test.c
710
if (RB_INSERT(tree, &root, tmp) != NULL)
regress/sys/sys/tree/rb/rb-test.c
712
ins = tmp;
regress/sys/sys/tree/rb/rb-test.c
714
tmp = &(nodes[i]);
regress/sys/sys/tree/rb/rb-test.c
715
tmp->size = 1;
regress/sys/sys/tree/rb/rb-test.c
716
tmp->height = 1;
regress/sys/sys/tree/rb/rb-test.c
717
tmp->key = i;
regress/sys/sys/tree/rb/rb-test.c
718
if (RB_INSERT_PREV(tree, &root, ins, tmp) != NULL)
regress/sys/sys/tree/rb/rb-test.c
720
ins = tmp;
regress/sys/sys/tree/rb/rb-test.c
736
RB_FOREACH_REVERSE_SAFE(ins, tree, &root, tmp) {
regress/sys/sys/tree/rb/rb-test.c
760
tmp = RB_ROOT(&root);
regress/sys/sys/tree/rb/rb-test.c
761
if (tmp == NULL)
regress/sys/sys/tree/rb/rb-test.c
763
if (RB_REMOVE(tree, &root, tmp) != tmp)
regress/sys/sys/tree/rb/rb-test.c
782
tmp = RB_ROOT(&root);
regress/sys/sys/tree/rb/rb-test.c
783
if (tmp == NULL)
regress/sys/sys/tree/rb/rb-test.c
785
if (RB_REMOVE(tree, &root, tmp) != tmp)
regress/sys/sys/tree/rb/rb-test.c
804
tmp = RB_ROOT(&root);
regress/sys/sys/tree/rb/rb-test.c
805
if (tmp == NULL)
regress/sys/sys/tree/rb/rb-test.c
807
if (RB_REMOVE(tree, &root, tmp) != tmp)
regress/sys/sys/tree/rb/rb-test.c
828
tmp = RB_ROOT(&root);
regress/sys/sys/tree/rb/rb-test.c
829
if (tmp == NULL)
regress/sys/sys/tree/rb/rb-test.c
831
if (RB_REMOVE(tree, &root, tmp) != tmp)
regress/sys/sys/tree/rb/rb-test.c
852
tmp = RB_ROOT(&root);
regress/sys/sys/tree/rb/rb-test.c
853
if (tmp == NULL)
regress/sys/sys/tree/rb/rb-test.c
855
if (RB_REMOVE(tree, &root, tmp) != tmp)
regress/sys/sys/tree/rb/rb-test.c
928
struct node *tmp, *ins;
regress/sys/sys/tree/rb/rb-test.c
935
tmp = &(nodes[i]);
regress/sys/sys/tree/rb/rb-test.c
936
if (tmp == NULL) err(1, "malloc");
regress/sys/sys/tree/rb/rb-test.c
937
tmp->size = 1;
regress/sys/sys/tree/rb/rb-test.c
938
tmp->height = 1;
regress/sys/sys/tree/rb/rb-test.c
939
tmp->key = perm[i];
regress/sys/sys/tree/rb/rb-test.c
941
if (RB_INSERT(tree, &root, tmp) != NULL)
regress/sys/sys/tree/rb/rb-test.c
957
tmp = &(nodes[insertions]);
regress/sys/sys/tree/rb/rb-test.c
958
tmp->key = ITER + 5;
regress/sys/sys/tree/rb/rb-test.c
959
tmp->size = 1;
regress/sys/sys/tree/rb/rb-test.c
960
tmp->height = 1;
regress/sys/sys/tree/rb/rb-test.c
961
RB_INSERT(tree, &root, tmp);
regress/sys/sys/tree/rb/rbt-test.c
134
struct node *tmp, *ins, *nodes;
regress/sys/sys/tree/rb/rbt-test.c
238
tmp = RBT_ROOT(tree, &root);
regress/sys/sys/tree/rb/rbt-test.c
239
assert(NULL != tmp);
regress/sys/sys/tree/rb/rbt-test.c
240
assert(RBT_REMOVE(tree, &root, tmp) == tmp);
regress/sys/sys/tree/rb/rbt-test.c
277
tmp = RBT_ROOT(tree, &root);
regress/sys/sys/tree/rb/rbt-test.c
278
assert(NULL != tmp);
regress/sys/sys/tree/rb/rbt-test.c
279
assert(RBT_REMOVE(tree, &root, tmp) == tmp);
regress/sys/sys/tree/rb/rbt-test.c
310
tmp = malloc(sizeof(struct node));
regress/sys/sys/tree/rb/rbt-test.c
312
tmp->key = i;
regress/sys/sys/tree/rb/rbt-test.c
313
ins = RBT_FIND(tree, &root, tmp);
regress/sys/sys/tree/rb/rbt-test.c
314
assert(NULL != tmp);
regress/sys/sys/tree/rb/rbt-test.c
324
free(tmp);
regress/sys/sys/tree/rb/rbt-test.c
354
tmp = malloc(sizeof(struct node));
regress/sys/sys/tree/rb/rbt-test.c
356
tmp->key = perm[i];
regress/sys/sys/tree/rb/rbt-test.c
357
ins = RBT_FIND(tree, &root, tmp);
regress/sys/sys/tree/rb/rbt-test.c
371
free(tmp);
regress/sys/sys/tree/rb/rbt-test.c
400
tmp = malloc(sizeof(struct node));
regress/sys/sys/tree/rb/rbt-test.c
402
tmp->key = i;
regress/sys/sys/tree/rb/rbt-test.c
403
ins = RBT_NFIND(tree, &root, tmp);
regress/sys/sys/tree/rb/rbt-test.c
416
free(tmp);
regress/sys/sys/tree/rb/rbt-test.c
440
tmp = malloc(sizeof(struct node));
regress/sys/sys/tree/rb/rbt-test.c
442
tmp->key = ITER + 6;
regress/sys/sys/tree/rb/rbt-test.c
443
ins = RBT_PFIND(tree, &root, tmp);
regress/sys/sys/tree/rb/rbt-test.c
456
free(tmp);
regress/sys/sys/tree/rb/rbt-test.c
479
tmp = RBT_MIN(tree, &root);
regress/sys/sys/tree/rb/rbt-test.c
480
assert(tmp != NULL);
regress/sys/sys/tree/rb/rbt-test.c
481
assert(tmp->key == 0);
regress/sys/sys/tree/rb/rbt-test.c
483
tmp = RBT_NEXT(tree, tmp);
regress/sys/sys/tree/rb/rbt-test.c
484
assert(tmp != NULL);
regress/sys/sys/tree/rb/rbt-test.c
485
assert(tmp->key == i);
regress/sys/sys/tree/rb/rbt-test.c
494
tmp = RBT_MAX(tree, &root);
regress/sys/sys/tree/rb/rbt-test.c
495
assert(tmp != NULL);
regress/sys/sys/tree/rb/rbt-test.c
496
assert(tmp->key == ITER + 5);
regress/sys/sys/tree/rb/rbt-test.c
498
tmp = RBT_PREV(tree, tmp);
regress/sys/sys/tree/rb/rbt-test.c
499
assert(tmp != NULL);
regress/sys/sys/tree/rb/rbt-test.c
500
assert(tmp->key == ITER - 1 - i);
regress/sys/sys/tree/rb/rbt-test.c
510
tmp = RBT_ROOT(tree, &root);
regress/sys/sys/tree/rb/rbt-test.c
511
assert(NULL != tmp);
regress/sys/sys/tree/rb/rbt-test.c
512
assert(RBT_REMOVE(tree, &root, tmp) == tmp);
regress/sys/sys/tree/rb/rbt-test.c
578
tmp = RBT_ROOT(tree, &root);
regress/sys/sys/tree/rb/rbt-test.c
579
assert(NULL != tmp);
regress/sys/sys/tree/rb/rbt-test.c
580
assert(RBT_REMOVE(tree, &root, tmp) == tmp);
regress/sys/sys/tree/rb/rbt-test.c
606
RBT_FOREACH_SAFE(ins, tree, &root, tmp) {
regress/sys/sys/tree/rb/rbt-test.c
632
RBT_FOREACH_REVERSE_SAFE(ins, tree, &root, tmp) {
regress/sys/sys/tree/rb/rbt-test.c
656
tmp = &(nodes[0]);
regress/sys/sys/tree/rb/rbt-test.c
657
tmp->size = 1;
regress/sys/sys/tree/rb/rbt-test.c
658
tmp->height = 1;
regress/sys/sys/tree/rb/rbt-test.c
659
tmp->key = 0;
regress/sys/sys/tree/rb/rbt-test.c
660
if (RBT_INSERT(tree, &root, tmp) != NULL)
regress/sys/sys/tree/rb/rbt-test.c
662
ins = tmp;
regress/sys/sys/tree/rb/rbt-test.c
664
tmp = &(nodes[i]);
regress/sys/sys/tree/rb/rbt-test.c
665
tmp->size = 1;
regress/sys/sys/tree/rb/rbt-test.c
666
tmp->height = 1;
regress/sys/sys/tree/rb/rbt-test.c
667
tmp->key = i;
regress/sys/sys/tree/rb/rbt-test.c
668
if (RBT_INSERT_NEXT(tree, &root, ins, tmp) != NULL)
regress/sys/sys/tree/rb/rbt-test.c
670
ins = tmp;
regress/sys/sys/tree/rb/rbt-test.c
686
RBT_FOREACH_REVERSE_SAFE(ins, tree, &root, tmp) {
regress/sys/sys/tree/rb/rbt-test.c
705
tmp = &(nodes[ITER]);
regress/sys/sys/tree/rb/rbt-test.c
706
tmp->size = 1;
regress/sys/sys/tree/rb/rbt-test.c
707
tmp->height = 1;
regress/sys/sys/tree/rb/rbt-test.c
708
tmp->key = ITER;
regress/sys/sys/tree/rb/rbt-test.c
709
if (RBT_INSERT(tree, &root, tmp) != NULL)
regress/sys/sys/tree/rb/rbt-test.c
711
ins = tmp;
regress/sys/sys/tree/rb/rbt-test.c
713
tmp = &(nodes[i]);
regress/sys/sys/tree/rb/rbt-test.c
714
tmp->size = 1;
regress/sys/sys/tree/rb/rbt-test.c
715
tmp->height = 1;
regress/sys/sys/tree/rb/rbt-test.c
716
tmp->key = i;
regress/sys/sys/tree/rb/rbt-test.c
717
if (RBT_INSERT_PREV(tree, &root, ins, tmp) != NULL)
regress/sys/sys/tree/rb/rbt-test.c
719
ins = tmp;
regress/sys/sys/tree/rb/rbt-test.c
735
RBT_FOREACH_REVERSE_SAFE(ins, tree, &root, tmp) {
regress/sys/sys/tree/rb/rbt-test.c
759
tmp = RBT_ROOT(tree, &root);
regress/sys/sys/tree/rb/rbt-test.c
760
if (tmp == NULL)
regress/sys/sys/tree/rb/rbt-test.c
762
if (RBT_REMOVE(tree, &root, tmp) != tmp)
regress/sys/sys/tree/rb/rbt-test.c
781
tmp = RBT_ROOT(tree, &root);
regress/sys/sys/tree/rb/rbt-test.c
782
if (tmp == NULL)
regress/sys/sys/tree/rb/rbt-test.c
784
if (RBT_REMOVE(tree, &root, tmp) != tmp)
regress/sys/sys/tree/rb/rbt-test.c
803
tmp = RBT_ROOT(tree, &root);
regress/sys/sys/tree/rb/rbt-test.c
804
if (tmp == NULL)
regress/sys/sys/tree/rb/rbt-test.c
806
if (RBT_REMOVE(tree, &root, tmp) != tmp)
regress/sys/sys/tree/rb/rbt-test.c
827
tmp = RBT_ROOT(tree, &root);
regress/sys/sys/tree/rb/rbt-test.c
828
if (tmp == NULL)
regress/sys/sys/tree/rb/rbt-test.c
830
if (RBT_REMOVE(tree, &root, tmp) != tmp)
regress/sys/sys/tree/rb/rbt-test.c
851
tmp = RBT_ROOT(tree, &root);
regress/sys/sys/tree/rb/rbt-test.c
852
if (tmp == NULL)
regress/sys/sys/tree/rb/rbt-test.c
854
if (RBT_REMOVE(tree, &root, tmp) != tmp)
regress/sys/sys/tree/rb/rbt-test.c
927
struct node *tmp, *ins;
regress/sys/sys/tree/rb/rbt-test.c
934
tmp = &(nodes[i]);
regress/sys/sys/tree/rb/rbt-test.c
935
if (tmp == NULL) err(1, "malloc");
regress/sys/sys/tree/rb/rbt-test.c
936
tmp->size = 1;
regress/sys/sys/tree/rb/rbt-test.c
937
tmp->height = 1;
regress/sys/sys/tree/rb/rbt-test.c
938
tmp->key = perm[i];
regress/sys/sys/tree/rb/rbt-test.c
940
if (RBT_INSERT(tree, &root, tmp) != NULL)
regress/sys/sys/tree/rb/rbt-test.c
956
tmp = &(nodes[insertions]);
regress/sys/sys/tree/rb/rbt-test.c
957
tmp->key = ITER + 5;
regress/sys/sys/tree/rb/rbt-test.c
958
tmp->size = 1;
regress/sys/sys/tree/rb/rbt-test.c
959
tmp->height = 1;
regress/sys/sys/tree/rb/rbt-test.c
960
RBT_INSERT(tree, &root, tmp);
regress/sys/sys/tree/splay/splay-test.c
100
if (SPLAY_REMOVE(tree, &root, tmp) != tmp)
regress/sys/sys/tree/splay/splay-test.c
102
free(tmp);
regress/sys/sys/tree/splay/splay-test.c
61
struct node *tmp, *ins;
regress/sys/sys/tree/splay/splay-test.c
67
tmp = malloc(sizeof(struct node));
regress/sys/sys/tree/splay/splay-test.c
68
if (tmp == NULL) err(1, "malloc");
regress/sys/sys/tree/splay/splay-test.c
70
tmp->key = arc4random_uniform(MAX-MIN);
regress/sys/sys/tree/splay/splay-test.c
71
tmp->key += MIN;
regress/sys/sys/tree/splay/splay-test.c
72
} while (SPLAY_FIND(tree, &root, tmp) != NULL);
regress/sys/sys/tree/splay/splay-test.c
74
max = min = tmp->key;
regress/sys/sys/tree/splay/splay-test.c
76
if (tmp->key > max)
regress/sys/sys/tree/splay/splay-test.c
77
max = tmp->key;
regress/sys/sys/tree/splay/splay-test.c
78
if (tmp->key < min)
regress/sys/sys/tree/splay/splay-test.c
79
min = tmp->key;
regress/sys/sys/tree/splay/splay-test.c
81
if (SPLAY_INSERT(tree, &root, tmp) != NULL)
regress/sys/sys/tree/splay/splay-test.c
88
tmp = ins;
regress/sys/sys/tree/splay/splay-test.c
93
if (SPLAY_REMOVE(tree, &root, tmp) != tmp)
regress/sys/sys/tree/splay/splay-test.c
97
tmp = SPLAY_ROOT(&root);
regress/sys/sys/tree/splay/splay-test.c
98
if (tmp == NULL)
regress/usr.bin/ssh/unittests/sshbuf/test_sshbuf_misc.c
25
char tmp[512];
regress/usr.bin/ssh/unittests/sshbuf/test_sshbuf_misc.c
38
sz = fread(tmp, 1, sizeof(tmp), out);
regress/usr.bin/ssh/unittests/sshbuf/test_sshbuf_misc.c
42
tmp[sz] = '\0';
regress/usr.bin/ssh/unittests/sshbuf/test_sshbuf_misc.c
43
ASSERT_PTR_NE(strstr(tmp, "12 34 56 78"), NULL);
regress/usr.bin/ssh/unittests/test_helper/test_helper.c
434
char tmp[64];
regress/usr.bin/ssh/unittests/test_helper/test_helper.c
449
snprintf(tmp, sizeof(tmp), "(%s)[%zu]", a1, where);
regress/usr.bin/ssh/unittests/test_helper/test_helper.c
450
fprintf(stderr, "%20s = 0x%02x (expected 0x%02x)\n", tmp,
regress/usr.sbin/bgpd/unittests/rde_community_test.c
64
uint8_t tmp;
regress/usr.sbin/bgpd/unittests/rde_community_test.c
65
if (ibuf_get_n8(in, &tmp) == -1)
regress/usr.sbin/bgpd/unittests/rde_community_test.c
67
attr_len = tmp;
sbin/ifconfig/ifconfig.c
2003
char *tmp = NULL;
sbin/ifconfig/ifconfig.c
2009
j = asprintf(&tmp, "0x%s", val);
sbin/ifconfig/ifconfig.c
2014
val = tmp;
sbin/ifconfig/ifconfig.c
2028
free(tmp);
sbin/iked/crypto.c
1038
uint8_t *tmp = NULL;
sbin/iked/crypto.c
1055
if ((tmp = calloc(1, tmplen)) == NULL)
sbin/iked/crypto.c
1057
if (EVP_DigestSignFinal(dsa->dsa_ctx, tmp, &tmplen) != 1)
sbin/iked/crypto.c
1059
p = tmp;
sbin/iked/crypto.c
1072
free(tmp);
sbin/iked/ikev2_msg.c
512
struct ibuf *integr, *tmp = NULL;
sbin/iked/ikev2_msg.c
532
if ((tmp = ibuf_new(NULL, hash_keylength(sa->sa_integr))) == NULL)
sbin/iked/ikev2_msg.c
546
hash_final(sa->sa_integr, ibuf_data(tmp), &tmplen);
sbin/iked/ikev2_msg.c
554
if (cipher_gettag(sa->sa_encr, ibuf_data(tmp), ibuf_size(tmp)))
sbin/iked/ikev2_msg.c
561
memcpy(ptr, ibuf_data(tmp), integrlen);
sbin/iked/ikev2_msg.c
563
print_hexbuf(tmp);
sbin/iked/ikev2_msg.c
567
ibuf_free(tmp);
sbin/iked/ikev2_msg.c
579
struct ibuf *integr, *encr, *tmp = NULL, *out = NULL;
sbin/iked/ikev2_msg.c
622
if ((tmp = ibuf_new(NULL, hash_keylength(sa->sa_integr))) == NULL)
sbin/iked/ikev2_msg.c
630
hash_final(sa->sa_integr, ibuf_data(tmp), &tmplen);
sbin/iked/ikev2_msg.c
635
if (memcmp(ibuf_data(tmp), integrdata, integrlen) != 0) {
sbin/iked/ikev2_msg.c
641
print_hex(ibuf_data(tmp), 0, tmplen);
sbin/iked/ikev2_msg.c
643
ibuf_free(tmp);
sbin/iked/ikev2_msg.c
644
tmp = NULL;
sbin/iked/ikev2_msg.c
715
ibuf_free(tmp);
sbin/iked/imsg_util.c
83
struct ibuf tmp;
sbin/iked/imsg_util.c
85
if (ibuf_get_ibuf(buf, len, &tmp) == -1)
sbin/iked/imsg_util.c
88
return (ibuf_new(ibuf_data(&tmp), ibuf_size(&tmp)));
sbin/iked/policy.c
373
struct iked_sa *tmp;
sbin/iked/policy.c
376
TAILQ_FOREACH(tmp, &pol->pol_sapeers, sa_peer_entry)
sbin/iked/util.c
720
char *tmp;
sbin/iked/util.c
723
if ((tmp = calloc(1, len)) == NULL) {
sbin/iked/util.c
730
if ((strlcat(tmp, p, len) >= len) ||
sbin/iked/util.c
731
(strlcat(tmp, repl, len) >= len)) {
sbin/iked/util.c
733
free(tmp);
sbin/iked/util.c
739
if (strlcat(tmp, p, len) >= len) {
sbin/iked/util.c
741
free(tmp);
sbin/iked/util.c
744
strlcpy(label, tmp, len); /* always fits */
sbin/iked/util.c
745
free(tmp);
sbin/ipsecctl/ipsecctl.c
929
u_int32_t tmp;
sbin/ipsecctl/ipsecctl.c
936
tmp = ntohl(ipa->addr32[j]);
sbin/ipsecctl/ipsecctl.c
937
for (i = 31; tmp & (1 << i); --i)
sbin/isakmpd/conf.c
384
char sect[CONF_SECT_MAX], tmp[CONF_SECT_MAX];
sbin/isakmpd/conf.c
410
snprintf(tmp, sizeof tmp, "QM-%s%s%s%s%s%s", PROTO(proto),
sbin/isakmpd/conf.c
413
strlcpy(sect, tmp, CONF_SECT_MAX);
sbin/isakmpd/conf.c
418
conf_set(tr, sect, "Protocols", tmp, 0, 1);
sbin/isakmpd/conf.c
420
conf_set(tr, tmp, "PROTOCOL_ID", sect, 0, 1);
sbin/isakmpd/conf.c
421
strlcpy(sect, tmp, CONF_SECT_MAX);
sbin/isakmpd/conf.c
423
conf_set(tr, tmp, "Transforms", sect, 0, 1);
sbin/isakmpd/constants.c
73
static char tmp[32];/* XXX Ugly, I know. */
sbin/isakmpd/constants.c
77
snprintf(tmp, sizeof tmp, "<Unknown %d>", value);
sbin/isakmpd/constants.c
78
return tmp;
sbin/isakmpd/constants.c
86
static char tmp[32];/* XXX Ugly, I know. */
sbin/isakmpd/constants.c
95
snprintf(tmp, sizeof tmp, "<Unknown %d>", value);
sbin/isakmpd/constants.c
96
return tmp;
sbin/isakmpd/crypto.c
266
u_int8_t *tmp;
sbin/isakmpd/crypto.c
268
tmp = ks->riv;
sbin/isakmpd/crypto.c
270
ks->liv = tmp;
sbin/isakmpd/policy.c
101
strlcpy(dst, tmp, size);
sbin/isakmpd/policy.c
110
char tmp[sizeof "ffff:ffff:ffff:ffff:ffff:ffff:ffff:ffff"];
sbin/isakmpd/policy.c
113
len = snprintf(tmp, sizeof tmp, fmt, src[0], src[1], src[2], src[3],
sbin/isakmpd/policy.c
120
strlcpy(dst, tmp, size);
sbin/isakmpd/policy.c
85
char tmp[sizeof "255.255.255.255"];
sbin/isakmpd/policy.c
94
len = snprintf(tmp, sizeof tmp, fmt, ((u_int8_t *)&src2)[0],
sbin/isakmpd/ui.c
224
char subcmd[201], section[201], tag[201], value[201], tmp[201];
sbin/isakmpd/ui.c
249
section, tag, value, tmp);
sbin/isakmpd/ui.c
259
section, tag, value, tmp);
sbin/isakmpd/ui.c
298
section, tag, value, tmp);
sbin/isakmpd/util.c
123
int tmp;
sbin/isakmpd/util.c
130
tmp = hex2nibble(*p--);
sbin/isakmpd/util.c
131
if (tmp == -1)
sbin/isakmpd/util.c
133
*bp = tmp;
sbin/isakmpd/util.c
136
tmp = hex2nibble(*p--);
sbin/isakmpd/util.c
137
if (tmp == -1)
sbin/isakmpd/util.c
139
*bp |= tmp << 4;
sbin/isakmpd/util.c
570
char *tmp;
sbin/isakmpd/util.c
573
if ((tmp = calloc(1, len)) == NULL) {
sbin/isakmpd/util.c
580
if ((strlcat(tmp, p, len) >= len) ||
sbin/isakmpd/util.c
581
(strlcat(tmp, repl, len) >= len)) {
sbin/isakmpd/util.c
588
if (strlcat(tmp, p, len) >= len) {
sbin/isakmpd/util.c
592
strlcpy(label, tmp, len); /* always fits */
sbin/isakmpd/util.c
593
free(tmp);
sbin/isakmpd/x509.c
1005
tmp = asn_decompose("aca.RelativeDistinguishedName."
sbin/isakmpd/x509.c
1007
if (!tmp)
sbin/isakmpd/x509.c
1009
x509_get_attribval(tmp, &naca.name1);
sbin/isakmpd/x509.c
1011
tmp = asn_decompose("aca.RelativeDistinguishedName[1]"
sbin/isakmpd/x509.c
1013
if (tmp)
sbin/isakmpd/x509.c
1014
x509_get_attribval(tmp, &naca.name2);
sbin/isakmpd/x509.c
994
struct norm_type *tmp;
sbin/newfs/newfs.c
792
const char *tmp = _PATH_TMP;
sbin/newfs/newfs.c
797
if (statfs(tmp, &fs) != 0)
sbin/newfs/newfs.c
798
err(1, "statfs %s", tmp);
sbin/newfs/newfs.c
808
n = strlcpy(mountpoint, tmp, len);
sbin/pfctl/parse.y
4610
char *tmp;
sbin/pfctl/parse.y
4613
if ((tmp = calloc(1, len)) == NULL)
sbin/pfctl/parse.y
4618
if ((strlcat(tmp, p, len) >= len) ||
sbin/pfctl/parse.y
4619
(strlcat(tmp, repl, len) >= len))
sbin/pfctl/parse.y
4624
if (strlcat(tmp, p, len) >= len)
sbin/pfctl/parse.y
4626
strlcpy(label, tmp, len); /* always fits */
sbin/pfctl/parse.y
4627
free(tmp);
sbin/pfctl/parse.y
4645
char tmp[64], tmp_not[66];
sbin/pfctl/parse.y
4650
snprintf(tmp, sizeof(tmp), "(%s)", h->addr.v.ifname);
sbin/pfctl/parse.y
4653
snprintf(tmp, sizeof(tmp), "<%s>", h->addr.v.tblname);
sbin/pfctl/parse.y
4656
snprintf(tmp, sizeof(tmp), "no-route");
sbin/pfctl/parse.y
4659
snprintf(tmp, sizeof(tmp), "urpf-failed");
sbin/pfctl/parse.y
4664
snprintf(tmp, sizeof(tmp), "any");
sbin/pfctl/parse.y
4671
snprintf(tmp, sizeof(tmp), "?");
sbin/pfctl/parse.y
4676
snprintf(tmp, sizeof(tmp),
sbin/pfctl/parse.y
4679
snprintf(tmp, sizeof(tmp),
sbin/pfctl/parse.y
4685
snprintf(tmp, sizeof(tmp), "?");
sbin/pfctl/parse.y
4690
snprintf(tmp_not, sizeof(tmp_not), "! %s", tmp);
sbin/pfctl/parse.y
4693
expand_label_str(label, len, name, tmp);
sbin/pfctl/pf_print_state.c
366
u_int32_t tmp;
sbin/pfctl/pf_print_state.c
373
tmp = ntohl(m->addr32[j]);
sbin/pfctl/pf_print_state.c
374
for (i = 31; tmp & (1 << i); --i)
sbin/pfctl/pfctl_osfp.c
1000
char tmp[32];
sbin/pfctl/pfctl_osfp.c
1013
snprintf(tmp, sizeof(tmp), "%d", fp->fp_wsize);
sbin/pfctl/pfctl_osfp.c
1014
strlcat(buf, tmp, sizeof(buf));
sbin/pfctl/pfctl_osfp.c
1018
snprintf(tmp, sizeof(tmp), "%d", fp->fp_ttl);
sbin/pfctl/pfctl_osfp.c
1019
strlcat(buf, tmp, sizeof(buf));
sbin/pfctl/pfctl_osfp.c
1033
snprintf(tmp, sizeof(tmp), "%d", fp->fp_psize);
sbin/pfctl/pfctl_osfp.c
1034
strlcat(buf, tmp, sizeof(buf));
sbin/pfctl/pfctl_osfp.c
1062
snprintf(tmp, sizeof(tmp), "%d", fp->fp_mss);
sbin/pfctl/pfctl_osfp.c
1063
strlcat(buf, tmp, sizeof(buf));
sbin/pfctl/pfctl_osfp.c
1073
snprintf(tmp, sizeof(tmp), "%d", fp->fp_wscale);
sbin/pfctl/pfctl_osfp.c
1074
strlcat(buf, tmp, sizeof(buf));
sbin/pfctl/pfctl_osfp.c
1091
snprintf(tmp, sizeof(tmp), "TcpOpts %d 0x%llx", fp->fp_optcnt,
sbin/pfctl/pfctl_osfp.c
1093
strlcat(buf, tmp, sizeof(buf));
sbin/quotacheck/quotacheck.c
501
char *tmp, *targetdev, *argvdev;
sbin/quotacheck/quotacheck.c
503
fd = opendev(target, O_RDONLY, 0, &tmp);
sbin/quotacheck/quotacheck.c
507
targetdev = strdup(tmp);
sbin/savecore/zopen.c
216
u_char tmp;
sbin/savecore/zopen.c
234
tmp = (u_char)(zs->zs_maxbits | zs->zs_block_compress);
sbin/savecore/zopen.c
235
if (write(zs->zs_fd, &tmp, sizeof(tmp)) != sizeof(tmp))
sbin/slaacd/engine.c
1944
struct address_proposal *tmp;
sbin/slaacd/engine.c
1950
entries, tmp) {
sbin/sysctl/sysctl.c
1150
int64_t tmp;
sbin/sysctl/sysctl.c
1152
memcpy(&tmp, buf, sizeof tmp);
sbin/sysctl/sysctl.c
1155
(void)printf("%lld\n", tmp);
sbin/sysctl/sysctl.c
1157
int64_t tmp;
sbin/sysctl/sysctl.c
1159
memcpy(&tmp, buf, sizeof tmp);
sbin/sysctl/sysctl.c
1163
string, tmp);
sbin/sysctl/sysctl.c
1164
memcpy(&tmp, newval, sizeof tmp);
sbin/sysctl/sysctl.c
1165
(void)printf("%lld\n", tmp);
sbin/unwind/frontend.c
1227
struct sldns_buffer *tmp;
sbin/unwind/frontend.c
1229
tmp = sldns_buffer_new(sldns_buffer_limit(pq->abuf) + 2);
sbin/unwind/frontend.c
1231
if (!tmp) {
sbin/unwind/frontend.c
1236
sldns_buffer_write_u16(tmp, sldns_buffer_limit(pq->abuf));
sbin/unwind/frontend.c
1237
sldns_buffer_write(tmp, sldns_buffer_current(pq->abuf),
sbin/unwind/frontend.c
1239
sldns_buffer_flip(tmp);
sbin/unwind/frontend.c
1241
pq->abuf = tmp;
sbin/unwind/frontend.c
1733
struct sldns_buffer *tmp;
sbin/unwind/frontend.c
1739
tmp = sldns_buffer_new(len);
sbin/unwind/frontend.c
1740
if (tmp == NULL)
sbin/unwind/frontend.c
1744
sldns_buffer_free(tmp);
sbin/unwind/frontend.c
1749
sldns_buffer_write(tmp, sldns_buffer_current(pq->qbuf),
sbin/unwind/frontend.c
1752
pq->qbuf = tmp;
sbin/unwind/libunbound/services/outside_network.c
1024
sldns_buffer tmp;
sbin/unwind/libunbound/services/outside_network.c
1025
sldns_buffer_init_frm_data(&tmp, w->pkt, w->pkt_len);
sbin/unwind/libunbound/services/outside_network.c
1028
w->sq->zonelen, &tmp);
sbin/unwind/libunbound/services/outside_network.c
2543
sldns_buffer tmp;
sbin/unwind/libunbound/services/outside_network.c
2544
sldns_buffer_init_frm_data(&tmp, w->pkt, w->pkt_len);
sbin/unwind/libunbound/services/outside_network.c
2547
sq->zonelen, &tmp);
sbin/unwind/resolver.c
2034
struct uw_forwarder *uw_forwarder, *tmp;
sbin/unwind/resolver.c
2107
TAILQ_FOREACH(tmp, &autoconf_forwarder_list, entry) {
sbin/unwind/resolver.c
2113
tmp->src) && (rdns_proposal->if_index == 0 ||
sbin/unwind/resolver.c
2114
rdns_proposal->if_index == tmp->if_index))
sbin/unwind/resolver.c
2119
if (strlcpy(uw_forwarder->ip, tmp->ip,
sbin/unwind/resolver.c
2122
uw_forwarder->port = tmp->port;
sbin/unwind/resolver.c
2123
uw_forwarder->src = tmp->src;
sbin/unwind/resolver.c
2124
uw_forwarder->if_index = tmp->if_index;
sbin/unwind/resolver.c
2138
while ((tmp = TAILQ_FIRST(&new_forwarder_list)) != NULL) {
sbin/unwind/resolver.c
2139
TAILQ_REMOVE(&new_forwarder_list, tmp, entry);
sbin/unwind/resolver.c
2140
free(tmp);
sbin/unwind/resolver.c
2283
char *resolv_conf = NULL, *tmp = NULL;
sbin/unwind/resolver.c
2286
tmp = resolv_conf;
sbin/unwind/resolver.c
2287
if (asprintf(&resolv_conf, "%snameserver %s\n", tmp ==
sbin/unwind/resolver.c
2288
NULL ? "" : tmp, uw_forwarder->ip) == -1) {
sbin/unwind/resolver.c
2289
free(tmp);
sbin/unwind/resolver.c
2292
free(tmp);
sbin/unwind/resolver.c
2487
struct in6_addr tmp;
sbin/unwind/resolver.c
2490
tmp = *in6;
sbin/unwind/resolver.c
2493
tmp.s6_addr[i] = 0;
sbin/unwind/resolver.c
2497
prefixes[i].in6 = tmp;
sbin/unwind/resolver.c
2502
memcmp(&prefixes[i].in6, &tmp, sizeof(tmp)) == 0) {
sbin/wsconsctl/keysym.c
122
static char tmp[20];
sbin/wsconsctl/keysym.c
143
snprintf(tmp, sizeof(tmp), "unknown_%d", k);
sbin/wsconsctl/keysym.c
144
return(tmp);
sbin/wsconsctl/util.c
221
static char tmp[20];
sbin/wsconsctl/util.c
229
snprintf(tmp, sizeof(tmp), "unknown_%d", val);
sbin/wsconsctl/util.c
230
return(tmp);
sys/arch/alpha/pci/sio_pic.c
560
int i, tmp, bestirq, count;
sys/arch/alpha/pci/sio_pic.c
606
for (p = &TAILQ_FIRST(&sio_intr[i].intr_q), tmp = 0;
sys/arch/alpha/pci/sio_pic.c
607
(q = *p) != NULL; p = &TAILQ_NEXT(q, ih_q), tmp++)
sys/arch/alpha/pci/sio_pic.c
609
if ((bestirq == -1) || (count > tmp)) {
sys/arch/alpha/pci/sio_pic.c
611
count = tmp;
sys/arch/amd64/amd64/lapic.c
537
u_int64_t dtick, dapic, tmp;
sys/arch/amd64/amd64/lapic.c
576
tmp = (TIMER_FREQ * dapic) / dtick;
sys/arch/amd64/amd64/lapic.c
578
lapic_per_second = tmp;
sys/arch/amd64/amd64/nvram.c
112
for (tmp = buf; count-- > 0 && pos < NVRAM_SIZE; ++pos, ++tmp)
sys/arch/amd64/amd64/nvram.c
113
*tmp = nvram_get_byte(pos);
sys/arch/amd64/amd64/nvram.c
116
printf("nvramread read %td bytes (%s)\n", (tmp - buf), tmp);
sys/arch/amd64/amd64/nvram.c
119
ret = uiomove(buf, (tmp - buf), uio);
sys/arch/amd64/amd64/nvram.c
95
u_char *tmp;
sys/arch/amd64/isa/isa_machdep.c
154
int tmp;
sys/arch/amd64/isa/isa_machdep.c
197
for (p = &intrhand[i], tmp = 0; (q = *p) != NULL;
sys/arch/amd64/isa/isa_machdep.c
198
p = &q->ih_next, tmp++)
sys/arch/amd64/isa/isa_machdep.c
200
if ((bestirq == -1) || (count > tmp)) {
sys/arch/amd64/isa/isa_machdep.c
202
count = tmp;
sys/arch/arm/include/atomic.h
259
unsigned int modified, tmp;
sys/arch/arm/include/atomic.h
267
: "=&r" (tmp), "=&r" (modified)
sys/arch/arm/include/atomic.h
280
unsigned int modified, tmp;
sys/arch/arm/include/atomic.h
288
: "=&r" (tmp), "=&r" (modified)
sys/arch/arm/include/cpufunc.h
272
u_int32_t tmp, ret;
sys/arch/arm/include/cpufunc.h
279
: "=&r" (ret), "=&r" (tmp)
sys/arch/arm64/dev/aplintc.c
616
struct intrhand *tmp;
sys/arch/arm64/dev/aplintc.c
627
TAILQ_FOREACH(tmp, &sc->sc_irq_list[ih->ih_ipl], ih_list) {
sys/arch/arm64/dev/aplintc.c
628
if (tmp == ih) {
sys/arch/arm64/dev/aplsmc.c
563
uint32_t tmp = (sc->sc_data >> 32);
sys/arch/arm64/dev/aplsmc.c
564
memcpy(data, &tmp, len);
sys/arch/arm64/include/atomic.h
30
unsigned int modified, tmp;
sys/arch/arm64/include/atomic.h
37
: "=&r" (tmp), "=&r" (modified)
sys/arch/arm64/include/atomic.h
50
unsigned int modified, tmp;
sys/arch/arm64/include/atomic.h
57
: "=&r" (tmp), "=&r" (modified)
sys/arch/arm64/stand/efiboot/fdt.c
208
char *tmp;
sys/arch/arm64/stand/efiboot/fdt.c
222
tmp = fdt_get_str(nameid);
sys/arch/arm64/stand/efiboot/fdt.c
223
if (!strcmp(name, tmp)) {
sys/arch/arm64/stand/efiboot/fdt.c
240
char *tmp;
sys/arch/arm64/stand/efiboot/fdt.c
254
tmp = fdt_get_str(nameid);
sys/arch/arm64/stand/efiboot/fdt.c
256
if (!strcmp(name, tmp)) {
sys/arch/arm64/stand/efiboot/fdt.c
525
void *tmp;
sys/arch/arm64/stand/efiboot/fdt.c
528
if ((tmp = fdt_parent_node_recurse(node, child)))
sys/arch/arm64/stand/efiboot/fdt.c
529
return tmp;
sys/arch/arm64/stand/efiboot/fdt.c
574
char *tmp, *value;
sys/arch/arm64/stand/efiboot/fdt.c
593
tmp = fdt_get_str(nameid);
sys/arch/arm64/stand/efiboot/fdt.c
594
printf("\t%s : ", tmp ? tmp : "NO_NAME");
sys/arch/arm64/stand/efiboot/fdt.c
599
if (!strcmp(tmp, "device_type") || !strcmp(tmp, "compatible") ||
sys/arch/arm64/stand/efiboot/fdt.c
600
!strcmp(tmp, "model") || !strcmp(tmp, "bootargs") ||
sys/arch/arm64/stand/efiboot/fdt.c
601
!strcmp(tmp, "linux,stdout-path")) {
sys/arch/arm64/stand/efiboot/fdt.c
603
} else if (!strcmp(tmp, "clock-frequency") ||
sys/arch/arm64/stand/efiboot/fdt.c
604
!strcmp(tmp, "timebase-frequency")) {
sys/arch/armv7/stand/efiboot/fdt.c
208
char *tmp;
sys/arch/armv7/stand/efiboot/fdt.c
222
tmp = fdt_get_str(nameid);
sys/arch/armv7/stand/efiboot/fdt.c
223
if (!strcmp(name, tmp)) {
sys/arch/armv7/stand/efiboot/fdt.c
240
char *tmp;
sys/arch/armv7/stand/efiboot/fdt.c
254
tmp = fdt_get_str(nameid);
sys/arch/armv7/stand/efiboot/fdt.c
256
if (!strcmp(name, tmp)) {
sys/arch/armv7/stand/efiboot/fdt.c
525
void *tmp;
sys/arch/armv7/stand/efiboot/fdt.c
528
if ((tmp = fdt_parent_node_recurse(node, child)))
sys/arch/armv7/stand/efiboot/fdt.c
529
return tmp;
sys/arch/armv7/stand/efiboot/fdt.c
574
char *tmp, *value;
sys/arch/armv7/stand/efiboot/fdt.c
593
tmp = fdt_get_str(nameid);
sys/arch/armv7/stand/efiboot/fdt.c
594
printf("\t%s : ", tmp ? tmp : "NO_NAME");
sys/arch/armv7/stand/efiboot/fdt.c
599
if (!strcmp(tmp, "device_type") || !strcmp(tmp, "compatible") ||
sys/arch/armv7/stand/efiboot/fdt.c
600
!strcmp(tmp, "model") || !strcmp(tmp, "bootargs") ||
sys/arch/armv7/stand/efiboot/fdt.c
601
!strcmp(tmp, "linux,stdout-path")) {
sys/arch/armv7/stand/efiboot/fdt.c
603
} else if (!strcmp(tmp, "clock-frequency") ||
sys/arch/armv7/stand/efiboot/fdt.c
604
!strcmp(tmp, "timebase-frequency")) {
sys/arch/i386/i386/lapic.c
364
u_int64_t dtick, dapic, tmp;
sys/arch/i386/i386/lapic.c
400
tmp = (TIMER_FREQ * dapic) / dtick;
sys/arch/i386/i386/lapic.c
402
lapic_per_second = tmp;
sys/arch/i386/i386/nvram.c
112
for (tmp = buf; count-- > 0 && pos < NVRAM_SIZE; ++pos, ++tmp)
sys/arch/i386/i386/nvram.c
113
*tmp = nvram_get_byte(pos);
sys/arch/i386/i386/nvram.c
116
printf("nvramread read %td bytes (%s)\n", (tmp - buf), tmp);
sys/arch/i386/i386/nvram.c
119
ret = uiomove(buf, (tmp - buf), uio);
sys/arch/i386/i386/nvram.c
95
u_char *tmp;
sys/arch/i386/isa/isa_machdep.c
348
int tmp;
sys/arch/i386/isa/isa_machdep.c
391
for (p = &intrhand[i], tmp = 0; (q = *p) != NULL;
sys/arch/i386/isa/isa_machdep.c
392
p = &q->ih_next, tmp++)
sys/arch/i386/isa/isa_machdep.c
394
if ((bestirq == -1) || (count > tmp)) {
sys/arch/i386/isa/isa_machdep.c
396
count = tmp;
sys/arch/i386/stand/libsa/smpprobe.c
77
mp_float_t *tmp = (mp_float_t*)(ptr + i);
sys/arch/i386/stand/libsa/smpprobe.c
79
if (tmp->signature == MP_FLOAT_SIG) {
sys/arch/i386/stand/libsa/smpprobe.c
82
mpp = tmp;
sys/arch/i386/stand/libsa/smpprobe.c
85
if ((tmp->signature == MP_FLOAT_SIG) &&
sys/arch/i386/stand/libsa/smpprobe.c
86
mp_checksum((u_int8_t *)tmp, tmp->length*16)) {
sys/arch/i386/stand/libsa/smpprobe.c
92
mpp = tmp;
sys/arch/loongson/dev/sisfb.c
389
uint tmp;
sys/arch/loongson/dev/sisfb.c
402
tmp = sisfb_crtc_read(fb, CRTC_OVERFLL);
sys/arch/loongson/dev/sisfb.c
403
if (ISSET(tmp, 1 << 1))
sys/arch/loongson/dev/sisfb.c
405
if (ISSET(tmp, 1 << 6))
sys/arch/loongson/dev/sisfb.c
407
tmp = sisfb_seq_read(fb, 0x0a);
sys/arch/loongson/dev/sisfb.c
408
if (ISSET(tmp, 1 << 1))
sys/arch/loongson/dev/sisfb.c
413
tmp = sisfb_seq_read(fb, 0x0b);
sys/arch/loongson/dev/sisfb.c
414
if (ISSET(tmp, 1 << 2))
sys/arch/loongson/dev/sisfb.c
416
if (ISSET(tmp, 1 << 3))
sys/arch/loongson/dev/sisfb.c
430
tmp = sisfb_seq_read(fb, 0x06);
sys/arch/loongson/dev/sisfb.c
431
switch (tmp & 0x1c) {
sys/arch/loongson/include/asm.h
5
#define HW_GET_CPU_INFO(ci, tmp) \
sys/arch/loongson/loongson/loongson3_intr.c
58
uint64_t tmp = *isr;
sys/arch/loongson/loongson/loongson3_intr.c
61
if (tmp == 0)
sys/arch/loongson/loongson/loongson3_intr.c
69
: "=r" (tmp) : "0" (tmp));
sys/arch/loongson/loongson/loongson3_intr.c
71
irq = 63u - tmp;
sys/arch/loongson/stand/boot/machdep.c
122
tmp = strchr(bootpath, '@');
sys/arch/loongson/stand/boot/machdep.c
123
if (tmp == NULL) {
sys/arch/loongson/stand/boot/machdep.c
126
bootpath = tmp + 1;
sys/arch/loongson/stand/boot/machdep.c
127
tmp = strchr(bootpath, '/');
sys/arch/loongson/stand/boot/machdep.c
128
if (tmp == NULL) {
sys/arch/loongson/stand/boot/machdep.c
131
bootpathlen = tmp - bootpath;
sys/arch/loongson/stand/boot/machdep.c
69
const char *tmp;
sys/arch/loongson/stand/boot/machdep.c
93
tmp = (const char *)pmon_getarg(0);
sys/arch/loongson/stand/boot/machdep.c
94
if (tmp[0] != 'g') {
sys/arch/loongson/stand/boot/machdep.c
97
tmp = (const char *)pmon_getarg(i);
sys/arch/loongson/stand/boot/machdep.c
98
if (tmp[0] != '-') {
sys/arch/loongson/stand/boot/machdep.c
99
bootpath = tmp;
sys/arch/m88k/m88k/fpu.c
100
frame->tf_r[regno] = tmp;
sys/arch/m88k/m88k/fpu.c
105
tmp = src->sng;
sys/arch/m88k/m88k/fpu.c
108
tmp = float64_to_float32(src->dbl);
sys/arch/m88k/m88k/fpu.c
112
frame->tf_r[regno] = tmp;
sys/arch/m88k/m88k/fpu.c
117
tmp = (u_int32_t)(src->dbl >> 32);
sys/arch/m88k/m88k/fpu.c
119
frame->tf_r[regno] = tmp;
sys/arch/m88k/m88k/fpu.c
120
tmp = (u_int32_t)src->dbl;
sys/arch/m88k/m88k/fpu.c
122
frame->tf_r[regno + 1] = tmp;
sys/arch/m88k/m88k/fpu.c
79
u_int32_t tmp;
sys/arch/m88k/m88k/fpu.c
88
tmp = float32_to_int32_round_to_zero(src->sng);
sys/arch/m88k/m88k/fpu.c
90
tmp = float32_to_int32(src->sng);
sys/arch/m88k/m88k/fpu.c
94
tmp = float64_to_int32_round_to_zero(src->dbl);
sys/arch/m88k/m88k/fpu.c
96
tmp = float64_to_int32(src->dbl);
sys/arch/m88k/m88k/m88100_fp.c
110
u_int32_t tmp;
sys/arch/m88k/m88k/m88100_fp.c
114
tmp = operandno == 1 ? frame->tf_fpls1 : frame->tf_fpls2;
sys/arch/m88k/m88k/m88100_fp.c
117
dest->sng = int32_to_float32(tmp);
sys/arch/m88k/m88k/m88100_fp.c
120
dest->dbl = int32_to_float64(tmp);
sys/arch/m88k/m88k/m88100_fp.c
125
tmp = operandno == 1 ?
sys/arch/m88k/m88k/m88100_fp.c
130
dest->sng = tmp;
sys/arch/m88k/m88k/m88100_fp.c
133
dest->dbl = float32_to_float64(tmp);
sys/arch/m88k/m88k/m88100_fp.c
138
tmp = operandno == 1 ? frame->tf_fphs1 : frame->tf_fphs2;
sys/arch/m88k/m88k/m88100_fp.c
139
dest->dbl = ((float64)tmp) << 32;
sys/arch/m88k/m88k/m88100_fp.c
140
tmp = operandno == 1 ? frame->tf_fpls1 : frame->tf_fpls2;
sys/arch/m88k/m88k/m88100_fp.c
141
dest->dbl |= (float64)tmp;
sys/arch/m88k/m88k/m88110_fp.c
184
u_int32_t tmp;
sys/arch/m88k/m88k/m88110_fp.c
188
tmp = regno == 0 ? 0 : frame->tf_r[regno];
sys/arch/m88k/m88k/m88110_fp.c
191
dest->sng = int32_to_float32(tmp);
sys/arch/m88k/m88k/m88110_fp.c
194
dest->dbl = int32_to_float64(tmp);
sys/arch/m88k/m88k/m88110_fp.c
199
tmp = regno == 0 ? 0 : frame->tf_r[regno];
sys/arch/m88k/m88k/m88110_fp.c
202
dest->sng = tmp;
sys/arch/m88k/m88k/m88110_fp.c
205
dest->dbl = float32_to_float64(tmp);
sys/arch/m88k/m88k/m88110_fp.c
210
tmp = regno == 0 ? 0 : frame->tf_r[regno];
sys/arch/m88k/m88k/m88110_fp.c
211
dest->dbl = ((float64)tmp) << 32;
sys/arch/m88k/m88k/m88110_fp.c
212
tmp = regno == 31 ? 0 : frame->tf_r[regno + 1];
sys/arch/m88k/m88k/m88110_fp.c
213
dest->dbl |= (float64)tmp;
sys/arch/mips64/include/asm.h
312
#define GET_CPU_INFO(ci, tmp) HW_GET_CPU_INFO(ci, tmp)
sys/arch/mips64/include/asm.h
314
#define GET_CPU_INFO(ci, tmp) \
sys/arch/mips64/include/atomic.h
31
unsigned int tmp;
sys/arch/mips64/include/atomic.h
39
"=&r"(tmp) :
sys/arch/mips64/include/atomic.h
46
unsigned int tmp;
sys/arch/mips64/include/atomic.h
54
"=&r"(tmp) :
sys/arch/mips64/include/loongson3.h
42
uint32_t tmp;
sys/arch/mips64/include/loongson3.h
49
: "=r" (tmp));
sys/arch/mips64/include/loongson3.h
51
return tmp & 0xf;
sys/arch/mips64/mips64/fp_emulate.c
720
uint64_t tmp, tmp2;
sys/arch/mips64/mips64/fp_emulate.c
722
tmp = ((uint64_t *)p->p_md.md_regs)[FPBASE + regno];
sys/arch/mips64/mips64/fp_emulate.c
730
tmp &= 0xffffffff;
sys/arch/mips64/mips64/fp_emulate.c
734
tmp &= 0xffffffff;
sys/arch/mips64/mips64/fp_emulate.c
741
tmp |= tmp2 << 32;
sys/arch/mips64/mips64/fp_emulate.c
749
return tmp;
sys/arch/octeon/dev/cn30xxgmx.c
605
uint64_t tmp;
sys/arch/octeon/dev/cn30xxgmx.c
607
tmp = _GMX_PORT_RD8(sc, GMX0_RX0_FRM_CTL);
sys/arch/octeon/dev/cn30xxgmx.c
609
SET(tmp, rx_frm_ctl);
sys/arch/octeon/dev/cn30xxgmx.c
611
CLR(tmp, rx_frm_ctl);
sys/arch/octeon/dev/cn30xxgmx.c
612
_GMX_PORT_WR8(sc, GMX0_RX0_FRM_CTL, tmp);
sys/arch/octeon/dev/cn30xxpip.c
143
uint64_t tmp;
sys/arch/octeon/dev/cn30xxpip.c
145
tmp = _PIP_RD8(sc, PIP_PRT_CFG0_OFFSET + (8 * sc->sc_port));
sys/arch/octeon/dev/cn30xxpip.c
147
tmp |= prt_cfg;
sys/arch/octeon/dev/cn30xxpip.c
149
tmp &= ~prt_cfg;
sys/arch/octeon/dev/cn30xxpip.c
150
_PIP_WR8(sc, PIP_PRT_CFG0_OFFSET + (8 * sc->sc_port), tmp);
sys/arch/octeon/dev/octcib.c
231
struct octcib_intrhand *tmp;
sys/arch/octeon/dev/octcib.c
239
LIST_FOREACH(tmp, &sc->sc_bits[bit], cih_list) {
sys/arch/octeon/dev/octcib.c
240
if (tmp == cih) {
sys/arch/octeon/dev/octcit.c
205
int tmp;
sys/arch/octeon/dev/octcit.c
207
tmp = intsn * 0xffb;
sys/arch/octeon/dev/octcit.c
208
return ((tmp >> 14) ^ tmp) & (HASH_SIZE - 1);
sys/arch/octeon/dev/octcit.c
337
struct octcit_intrhand *tmp;
sys/arch/octeon/dev/octcit.c
345
SLIST_FOREACH(tmp, &sc->sc_handlers[hash], ih_list) {
sys/arch/octeon/dev/octcit.c
346
if (tmp->ih_intsn == ih->ih_intsn)
sys/arch/octeon/dev/octcit.c
348
if (tmp == ih)
sys/arch/octeon/dev/octcit.c
369
SLIST_FOREACH(tmp, &sc->sc_handlers[i], ih_list) {
sys/arch/octeon/dev/octcit.c
371
tmp->ih_level)
sys/arch/octeon/dev/octcit.c
373
tmp->ih_level;
sys/arch/octeon/dev/octciu.c
243
struct octciu_intrhand *ih, *last, *tmp;
sys/arch/octeon/dev/octciu.c
283
SLIST_FOREACH(tmp, &sc->sc_intrhand[irq], ih_list)
sys/arch/octeon/dev/octciu.c
284
last = tmp;
sys/arch/octeon/dev/octciu.c
325
struct octciu_intrhand *tmp;
sys/arch/octeon/dev/octciu.c
337
SLIST_FOREACH(tmp, &sc->sc_intrhand[irq], ih_list) {
sys/arch/octeon/dev/octciu.c
338
if (tmp == ih) {
sys/arch/octeon/dev/octciu.c
442
uint64_t irq, tmp = *isr;
sys/arch/octeon/dev/octciu.c
444
if (tmp == 0)
sys/arch/octeon/dev/octciu.c
452
: "=r" (tmp) : "0" (tmp));
sys/arch/octeon/dev/octciu.c
454
irq = 63u - tmp;
sys/arch/octeon/dev/octeon_intr.c
55
struct intr_controller *tmp;
sys/arch/octeon/dev/octeon_intr.c
65
LIST_FOREACH(tmp, &octeon_ic_list, ic_list) {
sys/arch/octeon/dev/octeon_intr.c
66
if (tmp->ic_phandle == ic->ic_phandle) {
sys/arch/octeon/include/asm.h
5
#define HW_GET_CPU_INFO(ci, tmp) \
sys/arch/octeon/include/octeon_model.h
69
uint32_t tmp;
sys/arch/octeon/include/octeon_model.h
77
: "=&r"(tmp) : );
sys/arch/octeon/include/octeon_model.h
79
return(tmp);
sys/arch/octeon/include/octeonvar.h
416
uint64_t tmp;
sys/arch/octeon/include/octeonvar.h
422
: [tmp]"=&r"(tmp));
sys/arch/octeon/include/octeonvar.h
423
return tmp;
sys/arch/octeon/include/octeonvar.h
429
uint64_t tmp;
sys/arch/octeon/include/octeonvar.h
435
: [tmp]"=r"(tmp));
sys/arch/octeon/include/octeonvar.h
436
return tmp;
sys/arch/octeon/include/octeonvar.h
442
uint64_t tmp;
sys/arch/octeon/include/octeonvar.h
448
: [tmp]"=r"(tmp));
sys/arch/octeon/include/octeonvar.h
449
return tmp;
sys/arch/octeon/include/octeonvar.h
459
: : [tmp]"r"(val) : "memory");
sys/arch/powerpc/include/atomic.h
28
unsigned int tmp;
sys/arch/powerpc/include/atomic.h
35
" sync" : "=&r" (tmp) : "r" (v), "r" (uip) : "cc", "memory");
sys/arch/powerpc/include/atomic.h
41
unsigned int tmp;
sys/arch/powerpc/include/atomic.h
48
" sync" : "=&r" (tmp) : "r" (v), "r" (uip) : "cc", "memory");
sys/arch/powerpc64/include/atomic.h
28
unsigned int tmp;
sys/arch/powerpc64/include/atomic.h
35
" sync" : "=&r" (tmp) : "r" (v), "r" (uip) : "cc", "memory");
sys/arch/powerpc64/include/atomic.h
41
unsigned int tmp;
sys/arch/powerpc64/include/atomic.h
48
" sync" : "=&r" (tmp) : "r" (v), "r" (uip) : "cc", "memory");
sys/arch/riscv64/include/asm.h
121
#define ENTER_USER_ACCESS(tmp) \
sys/arch/riscv64/include/asm.h
122
li tmp, SSTATUS_SUM; \
sys/arch/riscv64/include/asm.h
123
csrs sstatus, tmp
sys/arch/riscv64/include/asm.h
125
#define EXIT_USER_ACCESS(tmp) \
sys/arch/riscv64/include/asm.h
126
li tmp, SSTATUS_SUM; \
sys/arch/riscv64/include/asm.h
127
csrc sstatus, tmp
sys/arch/riscv64/stand/efiboot/fdt.c
208
char *tmp;
sys/arch/riscv64/stand/efiboot/fdt.c
222
tmp = fdt_get_str(nameid);
sys/arch/riscv64/stand/efiboot/fdt.c
223
if (!strcmp(name, tmp)) {
sys/arch/riscv64/stand/efiboot/fdt.c
240
char *tmp;
sys/arch/riscv64/stand/efiboot/fdt.c
254
tmp = fdt_get_str(nameid);
sys/arch/riscv64/stand/efiboot/fdt.c
256
if (!strcmp(name, tmp)) {
sys/arch/riscv64/stand/efiboot/fdt.c
525
void *tmp;
sys/arch/riscv64/stand/efiboot/fdt.c
528
if ((tmp = fdt_parent_node_recurse(node, child)))
sys/arch/riscv64/stand/efiboot/fdt.c
529
return tmp;
sys/arch/riscv64/stand/efiboot/fdt.c
574
char *tmp, *value;
sys/arch/riscv64/stand/efiboot/fdt.c
593
tmp = fdt_get_str(nameid);
sys/arch/riscv64/stand/efiboot/fdt.c
594
printf("\t%s : ", tmp ? tmp : "NO_NAME");
sys/arch/riscv64/stand/efiboot/fdt.c
599
if (!strcmp(tmp, "device_type") || !strcmp(tmp, "compatible") ||
sys/arch/riscv64/stand/efiboot/fdt.c
600
!strcmp(tmp, "model") || !strcmp(tmp, "bootargs") ||
sys/arch/riscv64/stand/efiboot/fdt.c
601
!strcmp(tmp, "linux,stdout-path")) {
sys/arch/riscv64/stand/efiboot/fdt.c
603
} else if (!strcmp(tmp, "clock-frequency") ||
sys/arch/riscv64/stand/efiboot/fdt.c
604
!strcmp(tmp, "timebase-frequency")) {
sys/arch/sparc64/include/asm.h
57
#define PIC_PROLOGUE(dest,tmp) \
sys/arch/sparc64/include/asm.h
59
rd %pc, tmp; \
sys/arch/sparc64/include/asm.h
61
add dest,tmp,dest
sys/arch/sparc64/include/asm.h
63
#define PIC_PROLOGUE(dest,tmp)
sys/arch/sparc64/sparc64/db_interface.c
1055
int64_t tmp = ldxa(0, ASI_MCCR);
sys/arch/sparc64/sparc64/db_interface.c
1058
tmp &= ~(WATCH_PM|WATCH_PR|WATCH_PW);
sys/arch/sparc64/sparc64/db_interface.c
1061
tmp &= ~(WATCH_VM|WATCH_VR|WATCH_VW);
sys/arch/sparc64/sparc64/db_interface.c
1064
stxa(0, ASI_MCCR, tmp);
sys/arch/sparc64/sparc64/db_interface.c
1067
int64_t tmp = ldxa(0, ASI_MCCR);
sys/arch/sparc64/sparc64/db_interface.c
1068
if (phys) tmp &= ~(WATCH_PM);
sys/arch/sparc64/sparc64/db_interface.c
1069
else tmp &= ~(WATCH_VM);
sys/arch/sparc64/sparc64/db_interface.c
1070
stxa(0, ASI_MCCR, tmp);
sys/arch/sparc64/sparc64/pmap.c
1478
paddr_t *pdir, *ptbl, tmp;
sys/arch/sparc64/sparc64/pmap.c
1519
tmp = (paddr_t)(u_long)pm->pm_segs;
sys/arch/sparc64/sparc64/pmap.c
1521
pmap_free_page(tmp, pm);
sys/arch/sparc64/sparc64/pmap.c
748
struct prom_map tmp;
sys/arch/sparc64/sparc64/pmap.c
749
tmp = prom_map[i];
sys/arch/sparc64/sparc64/pmap.c
751
prom_map[j] = tmp;
sys/arch/sparc64/sparc64/pmap.c
903
struct mem_region tmp;
sys/arch/sparc64/sparc64/pmap.c
904
tmp = avail[i];
sys/arch/sparc64/sparc64/pmap.c
906
avail[j] = tmp;
sys/crypto/aes.c
338
uint32_t tmp;
sys/crypto/aes.c
356
tmp = dec32le((const unsigned char *)key + (i << 2));
sys/crypto/aes.c
357
skey[i] = tmp;
sys/crypto/aes.c
359
tmp = skey[(key_len >> 2) - 1];
sys/crypto/aes.c
362
tmp = (tmp << 24) | (tmp >> 8);
sys/crypto/aes.c
363
tmp = sub_word(tmp) ^ Rcon[k];
sys/crypto/aes.c
365
tmp = sub_word(tmp);
sys/crypto/aes.c
367
tmp ^= skey[i - nk];
sys/crypto/aes.c
368
skey[i] = tmp;
sys/crypto/chacha_private.h
133
u8 tmp[64];
sys/crypto/chacha_private.h
157
for (i = 0;i < bytes;++i) tmp[i] = m[i];
sys/crypto/chacha_private.h
158
m = tmp;
sys/crypto/chacha_private.h
160
c = tmp;
sys/dev/acpi/acpi.c
212
uint32_t tmp = pci_conf_read(pc, tag, reg & ~0x3);
sys/dev/acpi/acpi.c
213
tmp &= ~(0xff << ((reg & 0x3) << 3));
sys/dev/acpi/acpi.c
214
tmp |= (val << ((reg & 0x3) << 3));
sys/dev/acpi/acpi.c
215
pci_conf_write(pc, tag, reg & ~0x3, tmp);
sys/dev/acpi/acpi.c
221
uint32_t tmp = pci_conf_read(pc, tag, reg & ~0x2);
sys/dev/acpi/acpi.c
222
tmp &= ~(0xffff << ((reg & 0x2) << 3));
sys/dev/acpi/acpi.c
223
tmp |= (val << ((reg & 0x2) << 3));
sys/dev/acpi/acpi.c
224
pci_conf_write(pc, tag, reg & ~0x2, tmp);
sys/dev/acpi/acpidmar.c
2182
struct domain_dev *ddev, *tmp;
sys/dev/acpi/acpidmar.c
2184
TAILQ_FOREACH_SAFE(ddev, &dom->devices, link, tmp) {
sys/dev/acpi/acpithinkpad.c
248
int64_t tmp;
sys/dev/acpi/acpithinkpad.c
260
if (thinkpad_get_temp(sc, i, &tmp) != 0)
sys/dev/acpi/acpithinkpad.c
288
int64_t tmp;
sys/dev/acpi/acpithinkpad.c
292
if (thinkpad_get_temp(sc, i, &tmp) != 0) {
sys/dev/acpi/acpithinkpad.c
298
(tmp * 1000000) + 273150000;
sys/dev/acpi/acpithinkpad.c
300
(tmp > 127 || tmp < -127) ? SENSOR_FINVALID : 0;
sys/dev/acpi/acpitz.c
455
int rv = -1, tmp = -1, i;
sys/dev/acpi/acpitz.c
458
tmp = acpitz_getreading(sc, name);
sys/dev/acpi/acpitz.c
459
if (tmp == -1)
sys/dev/acpi/acpitz.c
461
if (KTOC(tmp) >= 0) {
sys/dev/acpi/acpitz.c
462
rv = tmp;
sys/dev/acpi/acpitz.c
466
"debouncing\n", DEVNAME(sc), tmp, name);
sys/dev/acpi/acpitz.c
478
name, tmp, KTOC(tmp), rv);
sys/dev/acpi/dsdt.c
1534
struct aml_value *tmp;
sys/dev/acpi/dsdt.c
1553
aml_parsename(&aml_root, (uint8_t *)def->name, &tmp, 1);
sys/dev/acpi/dsdt.c
1554
_aml_setvalue(tmp, def->type, def->ival, def->bval);
sys/dev/acpi/dsdt.c
1557
*def->gval = tmp;
sys/dev/acpi/dsdt.c
1559
aml_delref(&tmp, 0);
sys/dev/acpi/dsdt.c
1985
struct aml_value *tmp;
sys/dev/acpi/dsdt.c
1990
tmp = aml_convert(pkg->v_package[index],
sys/dev/acpi/dsdt.c
1994
flag = aml_matchtest(tmp->v_integer, v1, op1) &&
sys/dev/acpi/dsdt.c
1995
aml_matchtest(tmp->v_integer, v2, op2);
sys/dev/acpi/dsdt.c
1996
aml_delref(&tmp, "xmatch");
sys/dev/acpi/dsdt.c
2485
struct aml_value tmp;
sys/dev/acpi/dsdt.c
2495
memset(&tmp, 0, sizeof(tmp));
sys/dev/acpi/dsdt.c
2522
tbit = &tmp.v_integer;
sys/dev/acpi/dsdt.c
2534
_aml_setvalue(&tmp, AML_OBJTYPE_BUFFER, tlen >> 3, 0);
sys/dev/acpi/dsdt.c
2535
tbit = tmp.v_buffer;
sys/dev/acpi/dsdt.c
2572
memset(tbit, 0xff, tmp.length);
sys/dev/acpi/dsdt.c
2581
aml_freevalue(&tmp);
sys/dev/acpi/dsdt.c
2792
struct aml_value tmp, *ref1, *ref2;
sys/dev/acpi/dsdt.c
2803
memset(&tmp, 0, sizeof(tmp));
sys/dev/acpi/dsdt.c
2804
tmp.refcnt = 99;
sys/dev/acpi/dsdt.c
2836
tbit = &tmp.v_integer;
sys/dev/acpi/dsdt.c
2846
_aml_setvalue(&tmp, AML_OBJTYPE_INTEGER, indexval, 0);
sys/dev/acpi/dsdt.c
2847
aml_rwfield(ref2, 0, aml_intlen, &tmp, ACPI_IOWRITE);
sys/dev/acpi/dsdt.c
2851
_aml_setvalue(&tmp, AML_OBJTYPE_INTEGER, 0, 0);
sys/dev/acpi/dsdt.c
2854
aml_rwfield(ref1, bpos, len, &tmp, mode);
sys/dev/acpi/dsdt.c
2867
struct aml_value tmp, *ref1, *ref2;
sys/dev/acpi/dsdt.c
2875
memset(&tmp, 0, sizeof(tmp));
sys/dev/acpi/dsdt.c
2876
aml_addref(&tmp, "fld.write");
sys/dev/acpi/dsdt.c
2880
_aml_setvalue(&tmp, AML_OBJTYPE_INTEGER, fld->v_field.ref3, 0);
sys/dev/acpi/dsdt.c
2881
aml_rwfield(ref2, 0, aml_intlen, &tmp, ACPI_IOWRITE);
sys/dev/acpi/dsdt.c
3104
struct aml_value tmp;
sys/dev/acpi/dsdt.c
3112
memset(&tmp, 0, sizeof(tmp));
sys/dev/acpi/dsdt.c
3113
tmp.refcnt=99;
sys/dev/acpi/dsdt.c
3115
rhs = _aml_setvalue(&tmp, AML_OBJTYPE_INTEGER, ival, NULL);
sys/dev/acpi/dsdt.c
3119
aml_rwfield(rhs, 0, rhs->v_field.bitlen, &tmp, ACPI_IOREAD);
sys/dev/acpi/dsdt.c
3120
rhs = &tmp;
sys/dev/acpi/dsdt.c
3196
aml_freevalue(&tmp);
sys/dev/acpi/dsdt.c
3222
struct aml_value *rv, tmp;
sys/dev/acpi/dsdt.c
3481
aml_parsesimple(scope, c, &tmp);
sys/dev/acpi/dsdt.c
3482
dbprintf(arg,"0x%llx", tmp.v_integer);
sys/dev/acpi/dsdt.c
3582
struct aml_value *tmp = my_ret;
sys/dev/acpi/dsdt.c
3586
switch (tmp->type) {
sys/dev/acpi/dsdt.c
3593
aml_nodename(tmp->node),
sys/dev/acpi/dsdt.c
3594
AML_METHOD_ARGCOUNT(tmp->v_method.flags),
sys/dev/acpi/dsdt.c
3596
ms = aml_pushscope(scope, tmp, tmp->node, AMLOP_METHOD);
sys/dev/acpi/dsdt.c
3599
for (idx=0; idx<AML_METHOD_ARGCOUNT(tmp->v_method.flags); idx++) {
sys/dev/acpi/dsdt.c
3615
aml_root.start = tmp->v_method.base;
sys/dev/acpi/dsdt.c
3616
if (tmp->v_method.fneval != NULL) {
sys/dev/acpi/dsdt.c
3617
my_ret = tmp->v_method.fneval(ms, NULL);
sys/dev/acpi/dsdt.c
3623
aml_nodename(tmp->node), ret_type);
sys/dev/acpi/dsdt.c
3635
aml_rwfield(tmp, 0, tmp->v_field.bitlen, my_ret, ACPI_IOREAD);
sys/dev/acpi/dsdt.c
3884
struct aml_value tmp;
sys/dev/acpi/dsdt.c
3889
memset(&tmp, 0, sizeof(tmp));
sys/dev/acpi/dsdt.c
3904
tmp.v_buffer = p_ssdt->aml;
sys/dev/acpi/dsdt.c
3905
tmp.length = p_ssdt->hdr_length - sizeof(p_ssdt->hdr);
sys/dev/acpi/dsdt.c
3907
return aml_pushscope(scope, &tmp, scope->node,
sys/dev/fdt/cwfg.c
316
uint32_t vcell, rtt, tmp;
sys/dev/fdt/cwfg.c
341
tmp = ((val >> VCELL_HI_SHIFT) & VCELL_HI_MASK) << 8;
sys/dev/fdt/cwfg.c
344
tmp |= ((val >> VCELL_LO_SHIFT) & VCELL_LO_MASK);
sys/dev/fdt/cwfg.c
345
vcell += tmp;
sys/dev/fdt/if_mvpp.c
3791
uint8_t tmp;
sys/dev/fdt/if_mvpp.c
3795
tmp = end;
sys/dev/fdt/if_mvpp.c
3797
start = tmp;
sys/dev/fdt/rkclock.c
2869
uint32_t a, tmp;
sys/dev/fdt/rkclock.c
2895
tmp = d;
sys/dev/fdt/rkclock.c
2898
n = tmp;
sys/dev/hid/hidms.c
575
int tmp = dx;
sys/dev/hid/hidms.c
577
dy = tmp;
sys/dev/i2c/adm1024.c
189
int tmp = data * mul;
sys/dev/i2c/adm1024.c
191
if (tmp == 0)
sys/dev/i2c/adm1024.c
194
sens->value = 1350000 / tmp;
sys/dev/i2c/adm1026.c
231
int tmp = data * mul;
sys/dev/i2c/adm1026.c
233
if (tmp == 0)
sys/dev/i2c/adm1026.c
236
sens->value = 1630000 / tmp;
sys/dev/i2c/asb100.c
276
int tmp = data * mul;
sys/dev/i2c/asb100.c
278
if (tmp == 0)
sys/dev/i2c/asb100.c
281
sens->value = 1350000 / tmp;
sys/dev/i2c/gl518sm.c
175
u_int tmp;
sys/dev/i2c/gl518sm.c
205
tmp = data2[0] * sc->sc_fan1_div * 2;
sys/dev/i2c/gl518sm.c
206
if (tmp == 0)
sys/dev/i2c/gl518sm.c
209
sc->sc_sensor[GLENV_FAN1].value = 960000 / tmp;
sys/dev/i2c/gl518sm.c
212
tmp = data2[1] * sc->sc_fan2_div * 2;
sys/dev/i2c/gl518sm.c
213
if (tmp == 0)
sys/dev/i2c/gl518sm.c
216
sc->sc_sensor[GLENV_FAN2].value = 960000 / tmp;
sys/dev/i2c/lm87.c
244
u_int tmp;
sys/dev/i2c/lm87.c
294
tmp = data * sc->sc_fan1_div;
sys/dev/i2c/lm87.c
295
if (tmp == 0)
sys/dev/i2c/lm87.c
298
sc->sc_sensor[sensor].value = 1350000 / tmp;
sys/dev/i2c/lm87.c
306
tmp = data * sc->sc_fan2_div;
sys/dev/i2c/lm87.c
307
if (tmp == 0)
sys/dev/i2c/lm87.c
310
sc->sc_sensor[sensor].value = 1350000 / tmp;
sys/dev/ic/ahci.c
2050
u_int32_t tmp;
sys/dev/ic/ahci.c
2243
tmp = ci_saved;
sys/dev/ic/ahci.c
2244
if (tmp) {
sys/dev/ic/ahci.c
2245
slot = ffs(tmp) - 1;
sys/dev/ic/ahci.c
2246
tmp &= ~(1 << slot);
sys/dev/ic/ahci.c
2247
KASSERT(tmp == 0);
sys/dev/ic/ahci.c
2368
tmp = ci_saved;
sys/dev/ic/ahci.c
2369
while (tmp) {
sys/dev/ic/ahci.c
2370
slot = ffs(tmp) - 1;
sys/dev/ic/ahci.c
2371
tmp &= ~(1 << slot);
sys/dev/ic/ar9003.c
2685
int tmp, i;
sys/dev/ic/ar9003.c
2774
tmp = abs(xtilde[i]);
sys/dev/ic/ar9003.c
2775
if (tmp > maxxtildeabs)
sys/dev/ic/ar9003.c
2776
maxxtildeabs = tmp;
sys/dev/ic/ar9003.c
2778
tmp = abs(b1[i]);
sys/dev/ic/ar9003.c
2779
if (tmp > maxb1abs)
sys/dev/ic/ar9003.c
2780
maxb1abs = tmp;
sys/dev/ic/ar9003.c
2782
tmp = abs(b2[i]);
sys/dev/ic/ar9003.c
2783
if (tmp > maxb2abs)
sys/dev/ic/ar9003.c
2784
maxb2abs = tmp;
sys/dev/ic/ar9003.c
2820
tmp = i * 32;
sys/dev/ic/ar9003.c
2823
y5 = ((beta * tmp) / 64) / order5x;
sys/dev/ic/ar9003.c
2824
y5 = (y5 * tmp) / order5x;
sys/dev/ic/ar9003.c
2825
y5 = (y5 * tmp) / order5x;
sys/dev/ic/ar9003.c
2826
y5 = (y5 * tmp) / order5x;
sys/dev/ic/ar9003.c
2827
y5 = (y5 * tmp) / order5x;
sys/dev/ic/ar9003.c
2831
y3 = (alpha * tmp) / order3x;
sys/dev/ic/ar9003.c
2832
y3 = (y3 * tmp) / order3x;
sys/dev/ic/ar9003.c
2833
y3 = (y3 * tmp) / order3x;
sys/dev/ic/ar9003.c
2836
in = y5 + y3 + (SCALE * tmp) / G;
sys/dev/ic/ar9003.c
2883
tmp = i * 32;
sys/dev/ic/ar9003.c
2887
y5 = (((beta * tmp - 64) / 64) - order5x) / order5x;
sys/dev/ic/ar9003.c
2889
y5 = (((beta * tmp - 64) / 64) + order5x) / order5x;
sys/dev/ic/ar9003.c
2890
y5 = (y5 * tmp) / order5x;
sys/dev/ic/ar9003.c
2891
y5 = (y5 * tmp) / order5x;
sys/dev/ic/ar9003.c
2892
y5 = (y5 * tmp) / order5x;
sys/dev/ic/ar9003.c
2893
y5 = (y5 * tmp) / order5x;
sys/dev/ic/ar9003.c
2898
y3 = (alpha * tmp - order3x) / order3x;
sys/dev/ic/ar9003.c
2900
y3 = (alpha * tmp + order3x) / order3x;
sys/dev/ic/ar9003.c
2901
y3 = (y3 * tmp) / order3x;
sys/dev/ic/ar9003.c
2902
y3 = (y3 * tmp) / order3x;
sys/dev/ic/bt463.c
222
struct bt463data tmp, *data = &tmp;
sys/dev/ic/bt485.c
173
struct bt485data tmp, *data = &tmp;
sys/dev/ic/bwfm.c
1001
LIST_FOREACH_SAFE(core, &sc->sc_chip.ch_list, co_link, tmp) {
sys/dev/ic/bwfm.c
1694
struct bwfm_proto_bcdc_ctl *ctl, *tmp;
sys/dev/ic/bwfm.c
1710
TAILQ_FOREACH_SAFE(ctl, &sc->sc_bcdc_rxctlq, next, tmp) {
sys/dev/ic/bwfm.c
1739
struct bwfm_proto_bcdc_ctl *ctl, *tmp;
sys/dev/ic/bwfm.c
1750
TAILQ_FOREACH_SAFE(ctl, &sc->sc_bcdc_rxctlq, next, tmp) {
sys/dev/ic/bwfm.c
251
uint32_t bandlist[3], tmp;
sys/dev/ic/bwfm.c
256
if (bwfm_fwvar_cmd_get_int(sc, BWFM_C_GET_VERSION, &tmp)) {
sys/dev/ic/bwfm.c
260
sc->sc_io_type = tmp;
sys/dev/ic/bwfm.c
999
struct bwfm_core *core, *tmp;
sys/dev/ic/dc.c
1568
int mac_offset, tmp, i;
sys/dev/ic/dc.c
1712
tmp = sc->dc_pmode;
sys/dev/ic/dc.c
1740
sc->dc_pmode = tmp;
sys/dev/ic/if_wi.c
2952
int8_t tmp;
sys/dev/ic/if_wi.c
2986
tmp = sc->wi_txpower;
sys/dev/ic/if_wi.c
2987
tmp = -12 - tmp;
sys/dev/ic/if_wi.c
2988
tmp <<= 2;
sys/dev/ic/if_wi.c
2990
power = (u_int16_t)tmp;
sys/dev/ic/if_wi.c
3011
int8_t tmp;
sys/dev/ic/if_wi.c
3029
tmp = power;
sys/dev/ic/if_wi.c
3030
tmp >>= 2;
sys/dev/ic/if_wi.c
3031
txpower->i_val = (u_int16_t)(-12 - tmp);
sys/dev/ic/lance.c
696
uint16_t tmp;
sys/dev/ic/lance.c
707
tmp = *bptr;
sys/dev/ic/lance.c
708
*to++ = tmp & 0xff;
sys/dev/ic/lance.c
709
*to++ = (tmp >> 8) & 0xff;
sys/dev/ic/ne2000.c
290
u_int8_t test_buffer[32], tmp;
sys/dev/ic/ne2000.c
302
tmp = bus_space_read_1(asict, asich, NE2000_ASIC_RESET);
sys/dev/ic/ne2000.c
314
bus_space_write_1(asict, asich, NE2000_ASIC_RESET, tmp);
sys/dev/ic/ne2000.c
351
tmp = bus_space_read_1(nict, nich, ED_P0_CR);
sys/dev/ic/ne2000.c
352
if ((tmp & (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
sys/dev/ic/ne2000.c
356
tmp = bus_space_read_1(nict, nich, ED_P0_ISR);
sys/dev/ic/ne2000.c
357
if ((tmp & ED_ISR_RST) != ED_ISR_RST)
sys/dev/ic/qwx.c
11000
struct dp_reo_cmd *cmd, *tmp;
sys/dev/ic/qwx.c
11006
TAILQ_FOREACH_SAFE(cmd, &dp->reo_cmd_list, entry, tmp) {
sys/dev/ic/qwx.c
18183
struct dp_reo_cmd *cmd, *tmp;
sys/dev/ic/qwx.c
18240
TAILQ_FOREACH_SAFE(cmd, &dp->reo_cmd_list, entry, tmp) {
sys/dev/ic/qwx.c
24576
struct dp_reo_cache_flush_elem *elem, *tmp;
sys/dev/ic/qwx.c
24608
TAILQ_FOREACH_SAFE(elem, &dp->reo_cmd_cache_flush_list, entry, tmp) {
sys/dev/ic/qwx.c
9269
tmp = filename;
sys/dev/ic/qwx.c
9299
tmp = fw_entry->data;
sys/dev/ic/qwx.c
9302
ret = ath11k_qmi_load_file_target_mem(ab, tmp, fw_size, file_type);
sys/dev/ic/qwz.c
15531
struct dp_reo_cmd *cmd, *tmp;
sys/dev/ic/qwz.c
15585
TAILQ_FOREACH_SAFE(cmd, &dp->reo_cmd_list, entry, tmp) {
sys/dev/ic/qwz.c
21740
struct dp_reo_cache_flush_elem *elem, *tmp;
sys/dev/ic/qwz.c
21772
TAILQ_FOREACH_SAFE(elem, &dp->reo_cmd_cache_flush_list, entry, tmp) {
sys/dev/ic/qwz.c
8728
struct dp_reo_cmd *cmd, *tmp;
sys/dev/ic/qwz.c
8734
TAILQ_FOREACH_SAFE(cmd, &dp->reo_cmd_list, entry, tmp) {
sys/dev/ic/rt2560.c
2053
uint32_t tmp;
sys/dev/ic/rt2560.c
2066
tmp = RT2560_BBP_WRITE | RT2560_BBP_BUSY | reg << 8 | val;
sys/dev/ic/rt2560.c
2067
RAL_WRITE(sc, RT2560_BBPCSR, tmp);
sys/dev/ic/rt2560.c
2105
uint32_t tmp;
sys/dev/ic/rt2560.c
2118
tmp = RT2560_RF_BUSY | RT2560_RF_20BIT | (val & 0xfffff) << 2 |
sys/dev/ic/rt2560.c
2120
RAL_WRITE(sc, RT2560_RFCSR, tmp);
sys/dev/ic/rt2560.c
2132
uint8_t power, tmp;
sys/dev/ic/rt2560.c
2204
tmp = rt2560_bbp_read(sc, 70);
sys/dev/ic/rt2560.c
2206
tmp &= ~RT2560_JAPAN_FILTER;
sys/dev/ic/rt2560.c
2208
tmp |= RT2560_JAPAN_FILTER;
sys/dev/ic/rt2560.c
2210
rt2560_bbp_write(sc, 70, tmp);
sys/dev/ic/rt2560.c
2226
uint32_t tmp;
sys/dev/ic/rt2560.c
2229
tmp = sc->rf_regs[RT2560_RF1] & ~RT2560_RF1_AUTOTUNE;
sys/dev/ic/rt2560.c
2230
rt2560_rf_write(sc, RT2560_RF1, tmp);
sys/dev/ic/rt2560.c
2233
tmp = sc->rf_regs[RT2560_RF3] & ~RT2560_RF3_AUTOTUNE;
sys/dev/ic/rt2560.c
2234
rt2560_rf_write(sc, RT2560_RF3, tmp);
sys/dev/ic/rt2560.c
2248
uint32_t tmp;
sys/dev/ic/rt2560.c
2253
tmp = 16 * ic->ic_bss->ni_intval;
sys/dev/ic/rt2560.c
2254
RAL_WRITE(sc, RT2560_CSR12, tmp);
sys/dev/ic/rt2560.c
2260
tmp = logcwmin << 16 | preload;
sys/dev/ic/rt2560.c
2261
RAL_WRITE(sc, RT2560_BCNOCSR, tmp);
sys/dev/ic/rt2560.c
2264
tmp = RT2560_ENABLE_TSF | RT2560_ENABLE_TBCN;
sys/dev/ic/rt2560.c
2266
tmp |= RT2560_ENABLE_TSF_SYNC(1);
sys/dev/ic/rt2560.c
2269
tmp |= RT2560_ENABLE_TSF_SYNC(2) |
sys/dev/ic/rt2560.c
2272
RAL_WRITE(sc, RT2560_CSR14, tmp);
sys/dev/ic/rt2560.c
2329
uint32_t tmp;
sys/dev/ic/rt2560.c
2340
tmp = RAL_READ(sc, RT2560_CSR11);
sys/dev/ic/rt2560.c
2341
tmp = (tmp & ~0x1f00) | slottime << 8;
sys/dev/ic/rt2560.c
2342
RAL_WRITE(sc, RT2560_CSR11, tmp);
sys/dev/ic/rt2560.c
2344
tmp = pifs << 16 | sifs;
sys/dev/ic/rt2560.c
2345
RAL_WRITE(sc, RT2560_CSR18, tmp);
sys/dev/ic/rt2560.c
2347
tmp = eifs << 16 | difs;
sys/dev/ic/rt2560.c
2348
RAL_WRITE(sc, RT2560_CSR19, tmp);
sys/dev/ic/rt2560.c
2371
uint32_t tmp;
sys/dev/ic/rt2560.c
2374
tmp = led1 << 16 | led2 << 17 | 70 << 8 | 30;
sys/dev/ic/rt2560.c
2375
RAL_WRITE(sc, RT2560_LEDCSR, tmp);
sys/dev/ic/rt2560.c
2381
uint32_t tmp;
sys/dev/ic/rt2560.c
2383
tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24;
sys/dev/ic/rt2560.c
2384
RAL_WRITE(sc, RT2560_CSR5, tmp);
sys/dev/ic/rt2560.c
2386
tmp = bssid[4] | bssid[5] << 8;
sys/dev/ic/rt2560.c
2387
RAL_WRITE(sc, RT2560_CSR6, tmp);
sys/dev/ic/rt2560.c
2395
uint32_t tmp;
sys/dev/ic/rt2560.c
2397
tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24;
sys/dev/ic/rt2560.c
2398
RAL_WRITE(sc, RT2560_CSR3, tmp);
sys/dev/ic/rt2560.c
2400
tmp = addr[4] | addr[5] << 8;
sys/dev/ic/rt2560.c
2401
RAL_WRITE(sc, RT2560_CSR4, tmp);
sys/dev/ic/rt2560.c
2409
uint32_t tmp;
sys/dev/ic/rt2560.c
2411
tmp = RAL_READ(sc, RT2560_CSR3);
sys/dev/ic/rt2560.c
2412
addr[0] = tmp & 0xff;
sys/dev/ic/rt2560.c
2413
addr[1] = (tmp >> 8) & 0xff;
sys/dev/ic/rt2560.c
2414
addr[2] = (tmp >> 16) & 0xff;
sys/dev/ic/rt2560.c
2415
addr[3] = (tmp >> 24);
sys/dev/ic/rt2560.c
2417
tmp = RAL_READ(sc, RT2560_CSR4);
sys/dev/ic/rt2560.c
2418
addr[4] = tmp & 0xff;
sys/dev/ic/rt2560.c
2419
addr[5] = (tmp >> 8) & 0xff;
sys/dev/ic/rt2560.c
2426
uint32_t tmp;
sys/dev/ic/rt2560.c
2428
tmp = RAL_READ(sc, RT2560_RXCSR0);
sys/dev/ic/rt2560.c
2430
tmp &= ~RT2560_DROP_NOT_TO_ME;
sys/dev/ic/rt2560.c
2432
tmp |= RT2560_DROP_NOT_TO_ME;
sys/dev/ic/rt2560.c
2434
RAL_WRITE(sc, RT2560_RXCSR0, tmp);
sys/dev/ic/rt2560.c
2443
uint32_t tmp;
sys/dev/ic/rt2560.c
2462
tmp = RAL_READ(sc, RT2560_BBPCSR1) & ~0x00070007;
sys/dev/ic/rt2560.c
2463
tmp |= (tx & 0x7) << 16 | (tx & 0x7);
sys/dev/ic/rt2560.c
2464
RAL_WRITE(sc, RT2560_BBPCSR1, tmp);
sys/dev/ic/rt2560.c
2569
uint32_t tmp;
sys/dev/ic/rt2560.c
2585
tmp = RT2560_PRIO_RING_COUNT << 24 |
sys/dev/ic/rt2560.c
2591
RAL_WRITE(sc, RT2560_TXCSR2, tmp);
sys/dev/ic/rt2560.c
2598
tmp = RT2560_RX_RING_COUNT << 8 | RT2560_RX_DESC_SIZE;
sys/dev/ic/rt2560.c
2600
RAL_WRITE(sc, RT2560_RXCSR1, tmp);
sys/dev/ic/rt2560.c
2633
tmp = RT2560_DROP_PHY_ERROR | RT2560_DROP_CRC_ERROR;
sys/dev/ic/rt2560.c
2635
tmp |= RT2560_DROP_CTL | RT2560_DROP_VERSION_ERROR;
sys/dev/ic/rt2560.c
2639
tmp |= RT2560_DROP_TODS;
sys/dev/ic/rt2560.c
2641
tmp |= RT2560_DROP_NOT_TO_ME;
sys/dev/ic/rt2560.c
2643
RAL_WRITE(sc, RT2560_RXCSR0, tmp);
sys/dev/ic/rt2560.c
818
uint32_t tmp;
sys/dev/ic/rt2560.c
854
tmp = RAL_READ(sc, RT2560_CSR21);
sys/dev/ic/rt2560.c
855
val |= ((tmp & RT2560_Q) >> RT2560_SHIFT_Q) << n;
sys/dev/ic/rt2661.c
1027
tmp = RAL_READ(sc, RT2661_E2PROM_CSR);
sys/dev/ic/rt2661.c
1028
val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n;
sys/dev/ic/rt2661.c
2047
uint32_t tmp;
sys/dev/ic/rt2661.c
2060
tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val;
sys/dev/ic/rt2661.c
2061
RAL_WRITE(sc, RT2661_PHY_CSR3, tmp);
sys/dev/ic/rt2661.c
2099
uint32_t tmp;
sys/dev/ic/rt2661.c
2112
tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 |
sys/dev/ic/rt2661.c
2114
RAL_WRITE(sc, RT2661_PHY_CSR4, tmp);
sys/dev/ic/rt2661.c
2140
uint32_t tmp;
sys/dev/ic/rt2661.c
2148
tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
sys/dev/ic/rt2661.c
2149
RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
sys/dev/ic/rt2661.c
2155
RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
sys/dev/ic/rt2661.c
2166
uint32_t tmp;
sys/dev/ic/rt2661.c
2168
tmp = RAL_READ(sc, RT2661_TXRX_CSR4);
sys/dev/ic/rt2661.c
2170
tmp &= ~RT2661_MRR_CCK_FALLBACK;
sys/dev/ic/rt2661.c
2172
tmp |= RT2661_MRR_CCK_FALLBACK;
sys/dev/ic/rt2661.c
2173
tmp |= RT2661_MRR_ENABLED;
sys/dev/ic/rt2661.c
2175
RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp);
sys/dev/ic/rt2661.c
2181
uint32_t tmp;
sys/dev/ic/rt2661.c
2183
tmp = RAL_READ(sc, RT2661_TXRX_CSR4);
sys/dev/ic/rt2661.c
2185
tmp &= ~RT2661_SHORT_PREAMBLE;
sys/dev/ic/rt2661.c
2187
tmp |= RT2661_SHORT_PREAMBLE;
sys/dev/ic/rt2661.c
2189
RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp);
sys/dev/ic/rt2661.c
2218
uint32_t tmp;
sys/dev/ic/rt2661.c
2248
tmp = RAL_READ(sc, RT2661_PHY_CSR0);
sys/dev/ic/rt2661.c
2249
tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ);
sys/dev/ic/rt2661.c
2251
tmp |= RT2661_PA_PE_2GHZ;
sys/dev/ic/rt2661.c
2253
tmp |= RT2661_PA_PE_5GHZ;
sys/dev/ic/rt2661.c
2254
RAL_WRITE(sc, RT2661_PHY_CSR0, tmp);
sys/dev/ic/rt2661.c
2338
uint32_t tmp;
sys/dev/ic/rt2661.c
2340
tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24;
sys/dev/ic/rt2661.c
2341
RAL_WRITE(sc, RT2661_MAC_CSR4, tmp);
sys/dev/ic/rt2661.c
2343
tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16;
sys/dev/ic/rt2661.c
2344
RAL_WRITE(sc, RT2661_MAC_CSR5, tmp);
sys/dev/ic/rt2661.c
2350
uint32_t tmp;
sys/dev/ic/rt2661.c
2352
tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24;
sys/dev/ic/rt2661.c
2353
RAL_WRITE(sc, RT2661_MAC_CSR2, tmp);
sys/dev/ic/rt2661.c
2355
tmp = addr[4] | addr[5] << 8 | 0xff << 16;
sys/dev/ic/rt2661.c
2356
RAL_WRITE(sc, RT2661_MAC_CSR3, tmp);
sys/dev/ic/rt2661.c
2363
uint32_t tmp;
sys/dev/ic/rt2661.c
2365
tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
sys/dev/ic/rt2661.c
2367
tmp &= ~RT2661_DROP_NOT_TO_ME;
sys/dev/ic/rt2661.c
2369
tmp |= RT2661_DROP_NOT_TO_ME;
sys/dev/ic/rt2661.c
2371
RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
sys/dev/ic/rt2661.c
2400
uint32_t tmp;
sys/dev/ic/rt2661.c
2405
tmp = RAL_READ(sc, RT2661_MAC_CSR9);
sys/dev/ic/rt2661.c
2406
tmp = (tmp & ~0xff) | slottime;
sys/dev/ic/rt2661.c
2407
RAL_WRITE(sc, RT2661_MAC_CSR9, tmp);
sys/dev/ic/rt2661.c
2547
uint32_t tmp, sta[3];
sys/dev/ic/rt2661.c
2646
tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff;
sys/dev/ic/rt2661.c
2648
tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR;
sys/dev/ic/rt2661.c
2650
tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR |
sys/dev/ic/rt2661.c
2655
tmp |= RT2661_DROP_TODS;
sys/dev/ic/rt2661.c
2657
tmp |= RT2661_DROP_NOT_TO_ME;
sys/dev/ic/rt2661.c
2660
RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
sys/dev/ic/rt2661.c
2694
uint32_t tmp;
sys/dev/ic/rt2661.c
2709
tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
sys/dev/ic/rt2661.c
2710
RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
sys/dev/ic/rt2661.c
2844
uint32_t tmp;
sys/dev/ic/rt2661.c
2847
tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
sys/dev/ic/rt2661.c
2848
RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
sys/dev/ic/rt2661.c
2870
RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
sys/dev/ic/rt2661.c
2958
uint32_t tmp;
sys/dev/ic/rt2661.c
2969
tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000;
sys/dev/ic/rt2661.c
2972
tmp |= ic->ic_bss->ni_intval * 16;
sys/dev/ic/rt2661.c
2974
tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT;
sys/dev/ic/rt2661.c
2976
tmp |= RT2661_TSF_MODE(1);
sys/dev/ic/rt2661.c
2979
tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON;
sys/dev/ic/rt2661.c
2981
RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp);
sys/dev/ic/rt2661.c
923
uint32_t tmp;
sys/dev/ic/rt2661.c
933
tmp = RAL_READ(sc, RT2661_TXRX_CSR9);
sys/dev/ic/rt2661.c
934
RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff);
sys/dev/ic/rt2661.c
991
uint32_t tmp;
sys/dev/ic/rt2860.c
1010
uint32_t tmp;
sys/dev/ic/rt2860.c
1022
tmp = RAL_READ(sc, RT3070_EFUSE_CTRL);
sys/dev/ic/rt2860.c
1023
tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK);
sys/dev/ic/rt2860.c
1024
tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK;
sys/dev/ic/rt2860.c
1025
RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp);
sys/dev/ic/rt2860.c
1027
tmp = RAL_READ(sc, RT3070_EFUSE_CTRL);
sys/dev/ic/rt2860.c
1028
if (!(tmp & RT3070_EFSROM_KICK))
sys/dev/ic/rt2860.c
1035
if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK)
sys/dev/ic/rt2860.c
1040
tmp = RAL_READ(sc, reg);
sys/dev/ic/rt2860.c
1042
return (addr & 2) ? tmp >> 16 : tmp & 0xffff;
sys/dev/ic/rt2860.c
1049
uint32_t tmp;
sys/dev/ic/rt2860.c
1061
tmp = RAL_READ(sc, RT3290_EFUSE_CTRL);
sys/dev/ic/rt2860.c
1062
tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK);
sys/dev/ic/rt2860.c
1063
tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK;
sys/dev/ic/rt2860.c
1064
RAL_WRITE(sc, RT3290_EFUSE_CTRL, tmp);
sys/dev/ic/rt2860.c
1066
tmp = RAL_READ(sc, RT3290_EFUSE_CTRL);
sys/dev/ic/rt2860.c
1067
if (!(tmp & RT3070_EFSROM_KICK))
sys/dev/ic/rt2860.c
1074
if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK)
sys/dev/ic/rt2860.c
1079
tmp = RAL_READ(sc, reg);
sys/dev/ic/rt2860.c
1081
return (addr & 2) ? tmp >> 16 : tmp & 0xffff;
sys/dev/ic/rt2860.c
1091
uint32_t tmp;
sys/dev/ic/rt2860.c
1127
tmp = RAL_READ(sc, RT2860_PCI_EECTRL);
sys/dev/ic/rt2860.c
1128
val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n;
sys/dev/ic/rt2860.c
1152
uint32_t tmp;
sys/dev/ic/rt2860.c
1159
tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
sys/dev/ic/rt2860.c
1160
tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN);
sys/dev/ic/rt2860.c
1161
RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
sys/dev/ic/rt2860.c
1947
uint32_t tmp;
sys/dev/ic/rt2860.c
1961
tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT |
sys/dev/ic/rt2860.c
1963
RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp);
sys/dev/ic/rt2860.c
1969
uint32_t tmp;
sys/dev/ic/rt2860.c
1982
tmp = RT3070_RF_KICK | reg << 8;
sys/dev/ic/rt2860.c
1983
RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp);
sys/dev/ic/rt2860.c
1986
tmp = RAL_READ(sc, RT3070_RF_CSR_CFG);
sys/dev/ic/rt2860.c
1987
if (!(tmp & RT3070_RF_KICK))
sys/dev/ic/rt2860.c
1996
return tmp & 0xff;
sys/dev/ic/rt2860.c
2002
uint32_t tmp;
sys/dev/ic/rt2860.c
2015
tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val;
sys/dev/ic/rt2860.c
2016
RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp);
sys/dev/ic/rt2860.c
2026
uint32_t tmp;
sys/dev/ic/rt2860.c
2046
tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID);
sys/dev/ic/rt2860.c
2048
for (slot = 0; slot < 4; slot++, tmp >>= 8)
sys/dev/ic/rt2860.c
2049
if ((tmp & 0xff) == cid)
sys/dev/ic/rt2860.c
2062
tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS);
sys/dev/ic/rt2860.c
2063
tmp = (tmp >> (slot * 8)) & 0xff;
sys/dev/ic/rt2860.c
2065
cmd, slot, tmp));
sys/dev/ic/rt2860.c
2069
return (tmp == 1) ? 0 : EIO;
sys/dev/ic/rt2860.c
2099
uint32_t tmp;
sys/dev/ic/rt2860.c
2101
tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG);
sys/dev/ic/rt2860.c
2102
tmp &= ~RT2860_CCK_SHORT_EN;
sys/dev/ic/rt2860.c
2104
tmp |= RT2860_CCK_SHORT_EN;
sys/dev/ic/rt2860.c
2105
RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp);
sys/dev/ic/rt2860.c
2125
uint32_t tmp;
sys/dev/ic/rt2860.c
2156
tmp = RAL_READ(sc, RT2860_TX_BAND_CFG);
sys/dev/ic/rt2860.c
2157
tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P);
sys/dev/ic/rt2860.c
2158
tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P;
sys/dev/ic/rt2860.c
2159
RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp);
sys/dev/ic/rt2860.c
2162
tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN;
sys/dev/ic/rt2860.c
2164
tmp |= RT2860_LNA_PE1_EN;
sys/dev/ic/rt2860.c
2166
tmp |= RT3593_LNA_PE2_EN;
sys/dev/ic/rt2860.c
2168
tmp |= RT2860_PA_PE_G0_EN;
sys/dev/ic/rt2860.c
2170
tmp |= RT2860_PA_PE_G1_EN;
sys/dev/ic/rt2860.c
2172
tmp |= RT3593_PA_PE_G2_EN;
sys/dev/ic/rt2860.c
2174
tmp |= RT2860_PA_PE_A0_EN;
sys/dev/ic/rt2860.c
2176
tmp |= RT2860_PA_PE_A1_EN;
sys/dev/ic/rt2860.c
2178
tmp |= RT3593_PA_PE_A2_EN;
sys/dev/ic/rt2860.c
218
uint32_t tmp, reg;
sys/dev/ic/rt2860.c
2182
RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp);
sys/dev/ic/rt2860.c
2185
RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp);
sys/dev/ic/rt2860.c
2188
tmp = RAL_READ(sc, RT2860_GPIO_CTRL);
sys/dev/ic/rt2860.c
2190
tmp &= ~0x01010000;
sys/dev/ic/rt2860.c
2192
tmp |= 0x00010000;
sys/dev/ic/rt2860.c
2194
tmp &= ~0x00008080;
sys/dev/ic/rt2860.c
2196
tmp |= 0x00000080;
sys/dev/ic/rt2860.c
2198
tmp = (tmp & ~0x00001000) | 0x00000010;
sys/dev/ic/rt2860.c
2199
RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp);
sys/dev/ic/rt2860.c
230
tmp = RAL_READ(sc, reg);
sys/dev/ic/rt2860.c
231
if (tmp != 0 && tmp != 0xffffffff)
sys/dev/ic/rt2860.c
2343
uint8_t h20mhz, rf, tmp;
sys/dev/ic/rt2860.c
2391
tmp = rf;
sys/dev/ic/rt2860.c
2394
if (tmp != rf)
sys/dev/ic/rt2860.c
2395
rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0);
sys/dev/ic/rt2860.c
240
sc->mac_ver = tmp >> 16;
sys/dev/ic/rt2860.c
241
sc->mac_rev = tmp & 0xffff;
sys/dev/ic/rt2860.c
2458
uint32_t tmp;
sys/dev/ic/rt2860.c
2468
tmp = RAL_READ(sc, RT3070_LDO_CFG0);
sys/dev/ic/rt2860.c
2469
tmp &= ~0x1f000000;
sys/dev/ic/rt2860.c
2471
tmp |= 0x0d000000; /* 1.35V */
sys/dev/ic/rt2860.c
2473
tmp |= 0x01000000; /* 1.2V */
sys/dev/ic/rt2860.c
2474
RAL_WRITE(sc, RT3070_LDO_CFG0, tmp);
sys/dev/ic/rt2860.c
2477
tmp = RAL_READ(sc, RT3070_GPIO_SWITCH);
sys/dev/ic/rt2860.c
2478
RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20);
sys/dev/ic/rt2860.c
2521
tmp = RAL_READ(sc, RT3070_OPT_14);
sys/dev/ic/rt2860.c
2522
RAL_WRITE(sc, RT3070_OPT_14, tmp | 1);
sys/dev/ic/rt2860.c
2653
uint32_t tmp;
sys/dev/ic/rt2860.c
2710
tmp = RAL_READ(sc, RT3070_LDO_CFG0);
sys/dev/ic/rt2860.c
2711
tmp = (tmp & ~0x1f000000) | 0x0d000000;
sys/dev/ic/rt2860.c
2712
RAL_WRITE(sc, RT3070_LDO_CFG0, tmp);
sys/dev/ic/rt2860.c
2719
uint32_t tmp;
sys/dev/ic/rt2860.c
2746
tmp = RAL_READ(sc, RT3070_LDO_CFG0);
sys/dev/ic/rt2860.c
2747
tmp = (tmp & ~0x1f000000) | 0x0d000000;
sys/dev/ic/rt2860.c
2748
RAL_WRITE(sc, RT3070_LDO_CFG0, tmp);
sys/dev/ic/rt2860.c
2863
uint32_t tmp;
sys/dev/ic/rt2860.c
2866
tmp = RAL_READ(sc, RT2860_INT_TIMER_EN);
sys/dev/ic/rt2860.c
2867
RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN);
sys/dev/ic/rt2860.c
2872
tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG);
sys/dev/ic/rt2860.c
2874
tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT;
sys/dev/ic/rt2860.c
2875
RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp);
sys/dev/ic/rt2860.c
2878
tmp = RAL_READ(sc, RT2860_INT_TIMER_EN);
sys/dev/ic/rt2860.c
2879
RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN);
sys/dev/ic/rt2860.c
2904
uint32_t tmp;
sys/dev/ic/rt2860.c
2906
tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG);
sys/dev/ic/rt2860.c
2907
tmp &= ~0xff;
sys/dev/ic/rt2860.c
2908
tmp |= (ic->ic_flags & IEEE80211_F_SHSLOT) ?
sys/dev/ic/rt2860.c
2910
RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp);
sys/dev/ic/rt2860.c
2917
uint32_t tmp;
sys/dev/ic/rt2860.c
2919
tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL;
sys/dev/ic/rt2860.c
2921
tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ?
sys/dev/ic/rt2860.c
2926
RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp);
sys/dev/ic/rt2860.c
2930
tmp |= RT2860_PROT_CTRL_RTS_CTS;
sys/dev/ic/rt2860.c
2932
tmp |= RT2860_PROT_CTRL_CTS;
sys/dev/ic/rt2860.c
2934
RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp);
sys/dev/ic/rt2860.c
3177
uint32_t tmp;
sys/dev/ic/rt2860.c
3184
tmp = RAL_READ(sc, RT3290_EFUSE_CTRL);
sys/dev/ic/rt2860.c
3185
DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp));
sys/dev/ic/rt2860.c
3186
if (tmp & RT3070_SEL_EFUSE)
sys/dev/ic/rt2860.c
3189
tmp = RAL_READ(sc, RT3070_EFUSE_CTRL);
sys/dev/ic/rt2860.c
3190
DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp));
sys/dev/ic/rt2860.c
3191
if (tmp & RT3070_SEL_EFUSE)
sys/dev/ic/rt2860.c
3572
uint32_t tmp;
sys/dev/ic/rt2860.c
3576
tmp = RAL_READ(sc, RT3290_WLAN_CTRL);
sys/dev/ic/rt2860.c
3577
tmp |= RT3290_WLAN_EN | RT3290_FRC_WL_ANT_SET |
sys/dev/ic/rt2860.c
3579
RAL_WRITE(sc, RT3290_WLAN_CTRL, tmp);
sys/dev/ic/rt2860.c
3582
tmp = RAL_READ(sc, RT3290_CMB_CTRL);
sys/dev/ic/rt2860.c
3583
if ((tmp & RT3290_PLL_LD) &&
sys/dev/ic/rt2860.c
3584
(tmp & RT3290_XTAL_RDY))
sys/dev/ic/rt2860.c
3592
tmp = RAL_READ(sc, RT3290_WLAN_CTRL);
sys/dev/ic/rt2860.c
3593
tmp |= RT3290_WLAN_RESET | RT3290_WLAN_CLK_EN;
sys/dev/ic/rt2860.c
3594
tmp &= ~RT3290_PCIE_APP0_CLK_REQ;
sys/dev/ic/rt2860.c
3595
RAL_WRITE(sc, RT3290_WLAN_CTRL, tmp);
sys/dev/ic/rt2860.c
3597
tmp &= ~RT3290_WLAN_RESET;
sys/dev/ic/rt2860.c
3598
RAL_WRITE(sc, RT3290_WLAN_CTRL, tmp);
sys/dev/ic/rt2860.c
3610
uint32_t tmp;
sys/dev/ic/rt2860.c
3617
tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
sys/dev/ic/rt2860.c
3618
if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
sys/dev/ic/rt2860.c
3630
tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN |
sys/dev/ic/rt2860.c
3632
RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
sys/dev/ic/rt2860.c
3635
tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR;
sys/dev/ic/rt2860.c
3637
tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL |
sys/dev/ic/rt2860.c
3642
tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL;
sys/dev/ic/rt2860.c
3644
RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp);
sys/dev/ic/rt2860.c
3657
uint32_t tmp;
sys/dev/ic/rt2860.c
3700
tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
sys/dev/ic/rt2860.c
3701
tmp &= 0xff0;
sys/dev/ic/rt2860.c
3702
RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
sys/dev/ic/rt2860.c
3727
tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
sys/dev/ic/rt2860.c
3728
if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
sys/dev/ic/rt2860.c
3738
tmp &= 0xff0;
sys/dev/ic/rt2860.c
3739
RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
sys/dev/ic/rt2860.c
3769
tmp = RAL_READ(sc, RT2860_US_CYC_CNT);
sys/dev/ic/rt2860.c
3770
tmp = (tmp & ~0xff) | 0x7d;
sys/dev/ic/rt2860.c
3771
RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp);
sys/dev/ic/rt2860.c
3829
tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
sys/dev/ic/rt2860.c
3830
if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
sys/dev/ic/rt2860.c
3840
tmp &= 0xff0;
sys/dev/ic/rt2860.c
3841
RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
sys/dev/ic/rt2860.c
3911
tmp = RAL_READ(sc, RT2860_TX_RTS_CFG);
sys/dev/ic/rt2860.c
3912
tmp &= ~0xffff00;
sys/dev/ic/rt2860.c
3913
tmp |= ic->ic_rtsthreshold << 8;
sys/dev/ic/rt2860.c
3914
RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp);
sys/dev/ic/rt2860.c
3959
uint32_t tmp;
sys/dev/ic/rt2860.c
3979
tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL);
sys/dev/ic/rt2860.c
3980
tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
sys/dev/ic/rt2860.c
3981
RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp);
sys/dev/ic/rt2860.c
4086
uint32_t tmp;
sys/dev/ic/rt2860.c
4092
tmp = RAL_READ(sc, RT2860_PCI_EECTRL);
sys/dev/ic/rt2860.c
4094
tmp & ~RT2860_C);
sys/dev/ic/rt2860.c
4095
tmp = RAL_READ(sc, RT2860_GPIO_CTRL);
sys/dev/ic/rt2860.c
4097
(tmp & ~0x0808) | 0x08);
sys/dev/ic/rt2860.c
4104
tmp = RAL_READ(sc, RT2860_PCI_EECTRL);
sys/dev/ic/rt2860.c
4106
tmp | RT2860_C);
sys/dev/ic/rt2860.c
4107
tmp = RAL_READ(sc, RT2860_GPIO_CTRL);
sys/dev/ic/rt2860.c
4109
tmp & ~0x0808);
sys/dev/ic/rt2860.c
4189
uint32_t tmp;
sys/dev/ic/rt2860.c
4191
tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG);
sys/dev/ic/rt2860.c
4193
tmp &= ~0x1fffff;
sys/dev/ic/rt2860.c
4194
tmp |= ic->ic_bss->ni_intval * 16;
sys/dev/ic/rt2860.c
4195
tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN;
sys/dev/ic/rt2860.c
4201
tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT;
sys/dev/ic/rt2860.c
4205
tmp |= RT2860_BCN_TX_EN;
sys/dev/ic/rt2860.c
4210
tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT;
sys/dev/ic/rt2860.c
4212
tmp |= RT2860_BCN_TX_EN;
sys/dev/ic/rt2860.c
4214
tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT;
sys/dev/ic/rt2860.c
4218
RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp);
sys/dev/ic/rt2860.c
820
uint32_t tmp = RAL_READ(sc, RT2860_DEBUG);
sys/dev/ic/rt2860.c
821
if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) {
sys/dev/ic/rt2860.c
907
uint32_t tmp;
sys/dev/ic/rt2860.c
910
tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4);
sys/dev/ic/rt2860.c
911
tmp |= (1 << tid) << 16;
sys/dev/ic/rt2860.c
912
RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp);
sys/dev/ic/rt2860.c
922
uint32_t tmp;
sys/dev/ic/rt2860.c
925
tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4);
sys/dev/ic/rt2860.c
926
tmp &= ~((1 << tid) << 16);
sys/dev/ic/rt2860.c
927
RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp);
sys/dev/ic/rt2860.c
935
uint32_t tmp;
sys/dev/ic/rt2860.c
948
tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG);
sys/dev/ic/rt2860.c
950
tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN |
sys/dev/ic/rtwn.c
528
uint8_t off, msk, tmp;
sys/dev/ic/rtwn.c
556
tmp = (reg & 0xe0) >> 5;
sys/dev/ic/rtwn.c
560
off = ((reg & 0xf0) >> 1) | tmp;
sys/dev/ic/smc91cxx.c
191
u_int16_t tmp;
sys/dev/ic/smc91cxx.c
199
tmp = bus_space_read_2(bst, bsh, REVISION_REG_W);
sys/dev/ic/smc91cxx.c
200
sc->sc_chipid = RR_ID(tmp);
sys/dev/ic/smc91cxx.c
202
if ((tmp & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
sys/dev/ic/smc91cxx.c
204
printf("%s: invalid BSR 0x%04x\n", sc->sc_dev.dv_xname, tmp);
sys/dev/ic/smc91cxx.c
206
idstr = smc91cxx_idstrs[RR_ID(tmp)];
sys/dev/ic/smc91cxx.c
213
printf("revision %d", RR_REV(tmp));
sys/dev/ic/smc91cxx.c
220
tmp = bus_space_read_2(bst, bsh, IAR_ADDR0_REG_W + i);
sys/dev/ic/smc91cxx.c
221
sc->sc_arpcom.ac_enaddr[i + 1] = (tmp >>8) & 0xff;
sys/dev/ic/smc91cxx.c
222
sc->sc_arpcom.ac_enaddr[i] = tmp & 0xff;
sys/dev/ic/smc91cxx.c
254
tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W);
sys/dev/ic/smc91cxx.c
266
if (tmp & CR_MII_SELECT) {
sys/dev/ic/smc91cxx.c
287
aui = tmp & CR_AUI_SELECT;
sys/dev/ic/smc91cxx.c
318
u_int16_t tmp;
sys/dev/ic/smc91cxx.c
338
tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W);
sys/dev/ic/smc91cxx.c
340
tmp |= CR_AUI_SELECT;
sys/dev/ic/smc91cxx.c
342
tmp &= ~CR_AUI_SELECT;
sys/dev/ic/smc91cxx.c
343
bus_space_write_2(bst, bsh, CONFIG_REG_W, tmp);
sys/dev/ic/smc91cxx.c
363
u_int16_t tmp;
sys/dev/ic/smc91cxx.c
382
tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W);
sys/dev/ic/smc91cxx.c
384
IFM_ETHER | ((tmp & CR_AUI_SELECT) ? IFM_10_5 : IFM_10_T);
sys/dev/ic/smc91cxx.c
396
u_int16_t tmp;
sys/dev/ic/smc91cxx.c
458
tmp = RCR_ENABLE | RCR_STRIP_CRC | RCR_ALMUL;
sys/dev/ic/smc91cxx.c
460
tmp |= RCR_PROMISC;
sys/dev/ic/smc91cxx.c
462
bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, tmp);
sys/dev/ic/smc91cxx.c
467
tmp = TCR_ENABLE;
sys/dev/ic/smc91cxx.c
474
tmp |= TCR_PAD_ENABLE;
sys/dev/ic/smc91cxx.c
477
bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, tmp);
sys/dev/ic/ti.c
2025
int tmp;
sys/dev/ic/ti.c
2087
tmp = ifm->ifm_media;
sys/dev/ic/ti.c
2090
ifm->ifm_media = tmp;
sys/dev/isa/ad1848.c
288
u_char tmp, tmp1 = 0xff, tmp2 = 0xff;
sys/dev/isa/ad1848.c
307
tmp = ADREAD(sc, AD1848_IADDR);
sys/dev/isa/ad1848.c
308
if (tmp & SP_IN_INIT) { /* Not a AD1848 */
sys/dev/isa/ad1848.c
310
DPRINTF(("ad_detect_A %x\n", tmp));
sys/dev/isa/ad1848.c
342
tmp = ad_read(sc, SP_MISC_INFO);
sys/dev/isa/ad1848.c
343
ad_write(sc, SP_MISC_INFO, (~tmp) & 0x0f);
sys/dev/isa/ad1848.c
345
if ((tmp & 0x0f) != ((tmp1 = ad_read(sc, SP_MISC_INFO)) & 0x0f)) {
sys/dev/isa/if_ec.c
244
u_int8_t tmp;
sys/dev/isa/if_ec.c
440
case 9: tmp = ELINK2_IDCFR_IRQ2; break;
sys/dev/isa/if_ec.c
441
case 3: tmp = ELINK2_IDCFR_IRQ3; break;
sys/dev/isa/if_ec.c
442
case 4: tmp = ELINK2_IDCFR_IRQ4; break;
sys/dev/isa/if_ec.c
443
case 5: tmp = ELINK2_IDCFR_IRQ5; break;
sys/dev/isa/if_ec.c
457
bus_space_write_1(asict, asich, ELINK2_IDCFR, tmp);
sys/dev/isa/if_ex.c
174
int tmp;
sys/dev/isa/if_ex.c
216
tmp = ex_eeprom_read(sc, EE_IRQ_No) & IRQ_No_Mask;
sys/dev/isa/if_ex.c
218
if (ee2irqmap[tmp] != ia->ia_irq)
sys/dev/isa/if_ex.c
219
printf("ex: WARNING: board's EEPROM is configured for IRQ %d, using %d\n", ee2irqmap[tmp], ia->ia_irq);
sys/dev/isa/if_ex.c
223
sc->irq_no = ee2irqmap[tmp];
sys/dev/isa/if_sm_isa.c
102
tmp = bus_space_read_2(iot, ioh, BANK_SELECT_REG_W);
sys/dev/isa/if_sm_isa.c
103
if ((tmp & BSR_DETECT_MASK) != BSR_DETECT_VALUE)
sys/dev/isa/if_sm_isa.c
111
tmp = bus_space_read_2(iot, ioh, BANK_SELECT_REG_W);
sys/dev/isa/if_sm_isa.c
112
if ((tmp & BSR_DETECT_MASK) != BSR_DETECT_VALUE)
sys/dev/isa/if_sm_isa.c
120
tmp = bus_space_read_2(iot, ioh, BASE_ADDR_REG_W);
sys/dev/isa/if_sm_isa.c
121
if (ia->ia_iobase != ((tmp >> 3) & 0x3e0))
sys/dev/isa/if_sm_isa.c
129
tmp = bus_space_read_2(iot, ioh, REVISION_REG_W);
sys/dev/isa/if_sm_isa.c
130
if (smc91cxx_idstrs[RR_ID(tmp)] == NULL)
sys/dev/isa/if_sm_isa.c
87
u_int16_t tmp;
sys/dev/kcov.c
746
struct kcov_remote *kr, *tmp;
sys/dev/kcov.c
763
tmp = kr_lookup(subsystem, id);
sys/dev/kcov.c
764
if (tmp == NULL)
sys/dev/kcov.c
766
if (tmp->kr_state != KCOV_STATE_DYING) {
sys/dev/kcov.c
774
msleep_nsec(tmp, &kcov_mtx, PWAIT, "kcov", INFSLP);
sys/dev/ofw/fdt.c
218
char *tmp;
sys/dev/ofw/fdt.c
232
tmp = fdt_get_str(nameid);
sys/dev/ofw/fdt.c
233
if (!strcmp(name, tmp)) {
sys/dev/ofw/fdt.c
249
char *tmp;
sys/dev/ofw/fdt.c
263
tmp = fdt_get_str(nameid);
sys/dev/ofw/fdt.c
265
if (!strcmp(name, tmp)) {
sys/dev/ofw/fdt.c
550
void *tmp;
sys/dev/ofw/fdt.c
553
if ((tmp = fdt_parent_node_recurse(node, child)))
sys/dev/ofw/fdt.c
554
return tmp;
sys/dev/ofw/fdt.c
579
void *tmp;
sys/dev/ofw/fdt.c
590
if ((tmp = fdt_find_phandle_recurse(child, phandle)))
sys/dev/ofw/fdt.c
591
return tmp;
sys/dev/ofw/fdt.c
774
char *tmp, *value;
sys/dev/ofw/fdt.c
793
tmp = fdt_get_str(nameid);
sys/dev/ofw/fdt.c
794
printf("\t%s : ", tmp ? tmp : "NO_NAME");
sys/dev/ofw/fdt.c
799
if (!strcmp(tmp, "device_type") || !strcmp(tmp, "compatible") ||
sys/dev/ofw/fdt.c
800
!strcmp(tmp, "model") || !strcmp(tmp, "bootargs") ||
sys/dev/ofw/fdt.c
801
!strcmp(tmp, "linux,stdout-path")) {
sys/dev/ofw/fdt.c
803
} else if (!strcmp(tmp, "clock-frequency") ||
sys/dev/ofw/fdt.c
804
!strcmp(tmp, "timebase-frequency")) {
sys/dev/ofw/ofw_misc.c
663
uint8_t mask, tmp;
sys/dev/ofw/ofw_misc.c
666
error = nd->nd_read(nd->nd_cookie, addr++, &tmp, 1);
sys/dev/ofw/ofw_misc.c
676
*p++ |= (tmp << (8 - offset)) & (mask << (8 - offset));
sys/dev/ofw/ofw_misc.c
683
*p = (tmp >> offset) & mask;
sys/dev/ofw/ofw_misc.c
738
uint8_t mask, tmp;
sys/dev/ofw/ofw_misc.c
741
error = nd->nd_read(nd->nd_cookie, addr, &tmp, 1);
sys/dev/ofw/ofw_misc.c
750
tmp &= ~(mask << offset);
sys/dev/ofw/ofw_misc.c
751
tmp |= (*p++ << offset) & (mask << offset);
sys/dev/ofw/ofw_misc.c
756
tmp &= ~(mask >> (8 - offset));
sys/dev/ofw/ofw_misc.c
757
tmp |= (*p >> (8 - offset)) & (mask >> (8 - offset));
sys/dev/ofw/ofw_misc.c
761
error = nd->nd_write(nd->nd_cookie, addr++, &tmp, 1);
sys/dev/pci/agp_i810.c
231
bus_addr_t mmaddr, gmaddr, tmp;
sys/dev/pci/agp_i810.c
510
&tmp, &isc->scrib_seg) != 0) {
sys/dev/pci/agp_i810.c
552
bus_addr_t tmp;
sys/dev/pci/agp_i810.c
554
tmp = isc->isc_apaddr;
sys/dev/pci/agp_i810.c
556
tmp += isc->dcache_size;
sys/dev/pci/agp_i810.c
558
tmp += isc->stolen << AGP_PAGE_SHIFT;
sys/dev/pci/agp_i810.c
566
for (; tmp < (isc->isc_apaddr + isc->isc_apsize);
sys/dev/pci/agp_i810.c
567
tmp += AGP_PAGE_SIZE)
sys/dev/pci/agp_i810.c
568
agp_i810_unbind_page(isc, tmp);
sys/dev/pci/agp_intel.c
320
pcireg_t tmp;
sys/dev/pci/agp_intel.c
376
tmp = pci_conf_read(isc->isc_pc, isc->isc_tag,
sys/dev/pci/agp_intel.c
379
AGP_INTEL_ERRCMD, tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1524
u32 tmp = RREG32_SMC(_Reg); \
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1525
tmp &= (_Mask); \
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1526
tmp |= ((_Val) & ~(_Mask)); \
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1527
WREG32_SMC(_Reg, tmp); \
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c
543
struct aca_bank_error *bank_error, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c
550
list_for_each_entry_safe(bank_error, tmp, &aerr->list, node) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c
634
struct aca_bank_error *bank_error, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c
640
list_for_each_entry_safe(bank_error, tmp, &aerr->list, node)
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c
71
struct aca_bank_node *node, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c
76
list_for_each_entry_safe(node, tmp, &banks->list, node) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c
764
struct aca_handle *handle, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c
769
list_for_each_entry_safe(handle, tmp, &mgr->list, node)
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1009
tmp->xcp_mode = obj->integer.value & 0xFFFF;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1010
tmp->mem_mode = (obj->integer.value >> 32) & 0xFFFF;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1026
tmp->tmr_base = obj->package.elements[0].integer.value;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1027
tmp->tmr_size = obj->package.elements[1].integer.value;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1032
tmp->sbdf, tmp->supp_xcp_mode, tmp->xcp_mode, tmp->mem_mode,
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1033
tmp->tmr_base, tmp->tmr_size);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1034
list_add_tail(&tmp->list, &amdgpu_acpi_dev_list);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1035
*dev_info = tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1042
kfree(tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1270
struct drm_encoder *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1273
list_for_each_entry(tmp, &adev_to_drm(adev)->mode_config.encoder_list,
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1275
struct amdgpu_encoder *enc = to_amdgpu_encoder(tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
965
struct amdgpu_acpi_dev_info *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
970
tmp = kzalloc(sizeof(struct amdgpu_acpi_dev_info), GFP_KERNEL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
971
if (!tmp)
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
974
INIT_LIST_HEAD(&tmp->xcc_list);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
975
INIT_LIST_HEAD(&tmp->list);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
976
tmp->sbdf = sbdf;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
994
tmp->supp_xcp_mode = obj->integer.value & 0xFFFF;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c
793
u64 tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c
805
tmp = (ttm_tt_pages_limit() << PAGE_SHIFT) / num_online_nodes();
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c
807
tmp = adev->gmc.mem_partitions[mem_id].size;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c
809
do_div(tmp, adev->xcp_mgr->num_xcp_per_mem_partition);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c
810
return ALIGN_DOWN(tmp, PAGE_SIZE);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
1890
struct kfd_mem_attachment *entry, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
1941
list_for_each_entry_safe(entry, tmp, &mem->attachments, list) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1172
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1176
tmp = eng_clock & SET_CLOCK_FREQ_MASK;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1177
tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1179
args.ulTargetEngineClock = cpu_to_le32(tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1600
u32 tmp = RREG32(adev->bios_scratch_reg_offset + 3);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1603
tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1605
tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1607
WREG32(adev->bios_scratch_reg_offset + 3, tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1613
u32 tmp = RREG32(adev->bios_scratch_reg_offset + 2);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1615
tmp &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1616
tmp |= (backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1619
WREG32(adev->bios_scratch_reg_offset + 2, tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1624
u32 tmp = RREG32(adev->bios_scratch_reg_offset + 7);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1626
if (tmp & ATOM_S7_ASIC_INIT_COMPLETE_MASK)
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
58
uint16_t tmp, bios_header_start;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
78
tmp = bios_header_start + 4;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
79
if (size < tmp) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
84
if (!memcmp(bios + tmp, "ATOM", 4) ||
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
85
!memcmp(bios + tmp, "MOTA", 4)) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c
1875
struct drm_sched_job *s_job, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c
1897
list_for_each_entry_safe(s_job, tmp, &sched->pending_list, list) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1517
u32 tmp, reg, and_mask, or_mask;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1529
tmp = or_mask;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1531
tmp = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1532
tmp &= ~and_mask;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1534
tmp |= (or_mask & and_mask);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1536
tmp |= or_mask;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1538
WREG32(reg, tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
4481
int tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
4782
tmp = amdgpu_reset_method;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
4788
amdgpu_reset_method = tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
581
uint32_t hi = ~0, tmp = 0;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
593
tmp = pos >> 31;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
596
if (tmp != hi) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
597
WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
598
hi = tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
1282
struct list_head *el, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
1287
list_for_each_prev_safe(el, tmp, &hw_id_kset->list) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
1300
struct list_head *el, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
1305
list_for_each_prev_safe(el, tmp, &ip_kset->list) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
1320
struct list_head *el, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
1325
list_for_each_prev_safe(el, tmp, &die_kset->list) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
1811
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
1816
tmp = cursor.start >> 31;
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
1818
if (tmp != 0xffffffff)
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
1819
WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
2805
struct amdgpu_userq_mgr *uqm, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
2810
list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
440
uint64_t tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
458
tmp = fault->timestamp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
462
if (fault->timestamp >= tmp)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
497
uint64_t tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
527
tmp = fault->timestamp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
529
} while (fault->timestamp < tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
959
u32 tmp, reg, i;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
965
tmp = (hub_type == AMDGPU_GFXHUB(0)) ?
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
970
tmp |= hub->vm_cntx_cntl_vm_fault;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
972
tmp &= ~hub->vm_cntx_cntl_vm_fault;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
975
WREG32_SOC15_IP(GC, reg, tmp) :
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
976
WREG32_SOC15_IP(MMHUB, reg, tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c
130
struct dma_fence *tmp = NULL;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c
200
((tmp = amdgpu_sync_get_fence(&job->explicit_sync)) ||
sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c
205
if (tmp)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c
206
trace_amdgpu_ib_pipe_sync(job, tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c
208
dma_fence_put(tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c
304
struct dma_fence *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c
314
tmp = amdgpu_sync_peek_fence(&(*id)->active, ring);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c
315
if (tmp) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c
317
*fence = dma_fence_get(tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
155
uint32_t tmp = 0;
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
176
tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
177
if (tmp == 0xABADCAFE)
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
232
uint32_t tmp = 0;
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
253
tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
254
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c
212
struct mca_bank_node *node, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c
217
list_for_each_entry_safe(node, tmp, &mca_set->list, node)
sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c
422
struct mca_bank_node *node, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c
433
list_for_each_entry_safe(node, tmp, &mca_set->list, node) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c
236
unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c
237
fb_div *= tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c
238
ref_div *= tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c
47
unsigned tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c
50
tmp = gcd(*nom, *den);
sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c
51
*nom /= tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c
52
*den /= tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c
56
tmp = DIV_ROUND_UP(nom_min, *nom);
sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c
57
*nom *= tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c
58
*den *= tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c
63
tmp = DIV_ROUND_UP(den_min, *den);
sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c
64
*nom *= tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c
65
*den *= tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
1067
struct amdgpu_ras_block_list *node, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
1073
list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
2009
struct ras_manager *obj, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
2011
list_for_each_entry_safe(obj, tmp, &con->head, node) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
2233
struct ras_manager *con_obj, *ip_obj, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
2236
list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
2533
struct ras_manager *obj, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
2535
list_for_each_entry_safe(obj, tmp, &con->head, node) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4397
struct ras_manager *obj, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4418
list_for_each_entry_safe(obj, tmp, &con->head, node) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4443
struct amdgpu_ras_block_list *node, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4471
list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4513
struct amdgpu_ras_block_list *ras_node, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4523
list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
5174
struct ras_err_node *err_node, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
5176
list_for_each_entry_safe(err_node, tmp, &err_data->err_node_list, node)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
5519
struct ras_critical_region *region, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
5522
list_for_each_entry_safe(region, tmp, &con->critical_region_head, node) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
980
struct ras_manager *obj, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
982
list_for_each_entry_safe(obj, tmp, &con->head, node) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
298
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
300
tmp = ((uint32_t)(rai->rma_status) & 0xFF) |
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
303
pp[0] = cpu_to_le32(tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
311
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
313
tmp = le32_to_cpu(pp[0]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
314
rai->rma_status = tmp & 0xFF;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
315
rai->health_percent = (tmp >> 8) & 0xFF;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
316
rai->ecc_page_threshold = (tmp >> 16) & 0xFFFF;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
504
__le64 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
512
tmp = cpu_to_le64(record->ts);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
513
memcpy(buf + i, &tmp, 8);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
516
tmp = cpu_to_le64((record->offset & 0xffffffffffff));
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
517
memcpy(buf + i, &tmp, 6);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
523
tmp = cpu_to_le64((record->retired_page & 0xffffffffffff));
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
524
memcpy(buf + i, &tmp, 6);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
532
__le64 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
540
memcpy(&tmp, buf + i, 8);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
541
record->ts = le64_to_cpu(tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
544
memcpy(&tmp, buf + i, 6);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
545
record->offset = (le64_to_cpu(tmp) & 0xffffffffffff);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
551
memcpy(&tmp, buf + i, 6);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
552
record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c
486
struct amdgpu_mux_chunk *chunk, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c
496
list_for_each_entry_safe(chunk, tmp, &e->list, entry) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c
286
unsigned int *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c
319
tmp = (unsigned int *)((uintptr_t)rlc_hdr +
sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c
322
adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c
326
tmp = (unsigned int *)((uintptr_t)rlc_hdr +
sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c
329
adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c
260
struct dma_fence *tmp = dma_fence_chain_contained(f);
sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c
262
if (amdgpu_sync_test_fence(adev, mode, owner, tmp)) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c
329
struct hlist_node *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c
332
hash_for_each_safe(sync->fences, i, tmp, e, node) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c
368
struct hlist_node *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c
372
hash_for_each_safe(sync->fences, i, tmp, e, node) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c
403
struct hlist_node *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c
407
hash_for_each_safe(source->fences, i, tmp, e, node) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c
450
struct hlist_node *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c
454
hash_for_each_safe(sync->fences, i, tmp, e, node) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c
474
struct hlist_node *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c
477
hash_for_each_safe(sync->fences, i, tmp, e, node) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c
498
struct hlist_node *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c
501
hash_for_each_safe(sync->fences, i, tmp, e, node)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1020
struct ttm_resource *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1039
r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1044
flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1047
gtt->offset = (u64)tmp->start << PAGE_SHIFT;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1051
ttm_bo_assign_mem(bo, tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c
1003
list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c
1019
struct amdgpu_userq_mgr *uqm, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c
1027
list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c
1048
struct amdgpu_userq_mgr *uqm, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c
1056
list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c
1077
struct amdgpu_userq_mgr *uqm, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c
1089
list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c
1112
struct amdgpu_userq_mgr *uqm, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c
1124
list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c
990
struct amdgpu_userq_mgr *uqm, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c
170
struct amdgpu_userq_fence *userq_fence, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c
182
list_for_each_entry_safe(userq_fence, tmp, &fence_drv->fences, link) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c
206
struct amdgpu_userq_fence *fence, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c
212
list_for_each_entry_safe(fence, tmp, &fence_drv->fences, link) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c
634
unsigned int image_size, tmp, min_dpb_size, num_dpb_buffer;
sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c
698
tmp = max(width_in_mb, height_in_mb);
sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c
699
min_dpb_size += ALIGN(tmp * 7 * 16, 64);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c
1046
tmp = destroyed;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c
1049
tmp = allocated;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c
1053
if (tmp & (1 << i))
sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c
746
uint32_t tmp, handle = 0;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c
790
tmp = amdgpu_ib_get_value(ib, idx + 4);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c
792
tmp, bs_idx);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c
906
tmp = amdgpu_ib_get_value(ib, idx + 4);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c
908
tmp, bs_idx);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c
955
tmp = destroyed;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c
958
tmp = allocated;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c
962
if (tmp & (1 << i))
sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c
983
uint32_t tmp, handle = 0;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
557
uint32_t tmp = 0;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
573
tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
574
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1057
uint32_t i, tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1114
tmp = readl(scratch_reg1);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1115
if (!(tmp & AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK))
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1120
tmp = readl(scratch_reg1);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1121
if (i >= timeout || (tmp & AMDGPU_RLCG_SCRATCH1_ERROR_MASK) != 0) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1123
if (tmp & AMDGPU_RLCG_VFGATE_DISABLED) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1126
} else if (tmp & AMDGPU_RLCG_WRONG_OPERATION_TYPE) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1129
} else if (tmp & AMDGPU_RLCG_REG_NOT_IN_RANGE) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1303
struct amd_sriov_ras_telemetry_error_count *tmp = NULL;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1312
tmp = kmemdup(&host_telemetry->body.error_count, used_size, GFP_KERNEL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1313
if (!tmp)
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1316
if (checksum != amd_sriov_msg_checksum(tmp, used_size, 0, 0))
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1319
memcpy(&adev->virt.count_cache, tmp,
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1322
kfree(tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1514
struct amd_sriov_ras_chk_criti *tmp = NULL;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1523
tmp = kmemdup(&host_telemetry->body.chk_criti, used_size, GFP_KERNEL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1524
if (!tmp)
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1527
if (checksum != amd_sriov_msg_checksum(tmp, used_size, 0, 0))
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1531
*hit = tmp->hit ? true : false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1534
kfree(tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
457
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
509
tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_dimension_pixels;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
510
adev->virt.decode_max_dimension_pixels = max(tmp, adev->virt.decode_max_dimension_pixels);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
512
tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_frame_pixels;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
513
adev->virt.decode_max_frame_pixels = max(tmp, adev->virt.decode_max_frame_pixels);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
515
tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_dimension_pixels;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
516
adev->virt.encode_max_dimension_pixels = max(tmp, adev->virt.encode_max_dimension_pixels);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
518
tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_frame_pixels;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
519
adev->virt.encode_max_frame_pixels = max(tmp, adev->virt.encode_max_frame_pixels);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1214
struct dma_fence *tmp = dma_fence_get_stub();
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1217
swap(vm->last_unlocked, tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1218
dma_fence_put(tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1229
uint64_t tmp, num_entries, addr;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1242
tmp = num_entries /
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1244
for (count = 2; count < tmp; ++count) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1271
tmp = start + num_entries;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1272
r = amdgpu_vm_ptes_update(¶ms, start, tmp, addr, flags);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1277
start = tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1860
uint64_t tmp, lpfn;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1867
if (check_add_overflow(saddr, size, &tmp)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1868
|| check_add_overflow(offset, size, &tmp)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1906
struct amdgpu_bo_va_mapping *mapping, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1919
tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1920
if (tmp) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1924
tmp->start, tmp->last + 1);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2070
struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2096
tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2097
while (tmp) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2099
if (tmp->start < saddr) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2100
before->start = tmp->start;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2102
before->offset = tmp->offset;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2103
before->flags = tmp->flags;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2104
before->bo_va = tmp->bo_va;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2105
list_add(&before->list, &tmp->bo_va->invalids);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2109
if (tmp->last > eaddr) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2111
after->last = tmp->last;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2112
after->offset = tmp->offset;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2113
after->offset += (after->start - tmp->start) << PAGE_SHIFT;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2114
after->flags = tmp->flags;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2115
after->bo_va = tmp->bo_va;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2116
list_add(&after->list, &tmp->bo_va->invalids);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2119
list_del(&tmp->list);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2120
list_add(&tmp->list, &removed);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2122
tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2126
list_for_each_entry_safe(tmp, next, &removed, list) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2127
amdgpu_vm_it_remove(tmp, &vm->va);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2128
list_del(&tmp->list);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2130
if (tmp->start < saddr)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2131
tmp->start = saddr;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2132
if (tmp->last > eaddr)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2133
tmp->last = eaddr;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2135
tmp->bo_va = NULL;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2136
list_add(&tmp->list, &vm->freed);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2137
trace_amdgpu_vm_bo_unmap(NULL, tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2413
uint64_t tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2458
tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2460
tmp >>= amdgpu_vm_block_size - 9;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2461
tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2462
adev->vm_manager.num_level = min_t(unsigned int, max_level, tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2485
adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2841
struct amdgpu_bo_va_mapping *mapping, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2864
list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2884
rbtree_postorder_for_each_entry_safe(mapping, tmp,
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
3127
struct amdgpu_bo_va *bo_va, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
3146
list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
3155
list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
3164
list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
3173
list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
3182
list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
3191
list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
332
struct amdgpu_vm_bo_base *vm_bo, *tmp;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
341
list_for_each_entry_safe(vm_bo, tmp, &vm->idle, vm_status) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_sdma.c
126
struct dma_fence *tmp = dma_fence_get(f);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_sdma.c
128
swap(p->vm->last_unlocked, tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_sdma.c
129
dma_fence_put(tmp);
sys/dev/pci/drm/amd/amdgpu/atombios_dp.c
379
u8 tmp;
sys/dev/pci/drm/amd/amdgpu/atombios_dp.c
387
DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
sys/dev/pci/drm/amd/amdgpu/atombios_dp.c
388
if (tmp & 1)
sys/dev/pci/drm/amd/amdgpu/atombios_dp.c
399
DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
sys/dev/pci/drm/amd/amdgpu/atombios_dp.c
400
if (tmp & 1)
sys/dev/pci/drm/amd/amdgpu/atombios_dp.c
543
u8 tmp;
sys/dev/pci/drm/amd/amdgpu/atombios_dp.c
560
tmp = dp_info->dp_lane_count;
sys/dev/pci/drm/amd/amdgpu/atombios_dp.c
562
tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
sys/dev/pci/drm/amd/amdgpu/atombios_dp.c
563
drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
sys/dev/pci/drm/amd/amdgpu/atombios_dp.c
566
tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
sys/dev/pci/drm/amd/amdgpu/atombios_dp.c
567
drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
sys/dev/pci/drm/amd/amdgpu/atombios_dp.c
729
u8 tmp;
sys/dev/pci/drm/amd/amdgpu/atombios_dp.c
743
if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
sys/dev/pci/drm/amd/amdgpu/atombios_dp.c
745
if (tmp & DP_TPS3_SUPPORTED)
sys/dev/pci/drm/amd/amdgpu/cik.c
1456
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/cik.c
1464
tmp = RREG32_SMC(cntl_reg);
sys/dev/pci/drm/amd/amdgpu/cik.c
1465
tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
sys/dev/pci/drm/amd/amdgpu/cik.c
1467
tmp |= dividers.post_divider;
sys/dev/pci/drm/amd/amdgpu/cik.c
1468
WREG32_SMC(cntl_reg, tmp);
sys/dev/pci/drm/amd/amdgpu/cik.c
1497
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/cik.c
1513
tmp = RREG32_SMC(ixCG_ECLK_CNTL);
sys/dev/pci/drm/amd/amdgpu/cik.c
1514
tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK |
sys/dev/pci/drm/amd/amdgpu/cik.c
1516
tmp |= dividers.post_divider;
sys/dev/pci/drm/amd/amdgpu/cik.c
1517
WREG32_SMC(ixCG_ECLK_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/cik.c
1575
u32 max_lw, current_lw, tmp;
sys/dev/pci/drm/amd/amdgpu/cik.c
1580
tmp = RREG32_PCIE(ixPCIE_LC_STATUS1);
sys/dev/pci/drm/amd/amdgpu/cik.c
1581
max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >>
sys/dev/pci/drm/amd/amdgpu/cik.c
1583
current_lw = (tmp & PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK)
sys/dev/pci/drm/amd/amdgpu/cik.c
1587
tmp = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL);
sys/dev/pci/drm/amd/amdgpu/cik.c
1588
if (tmp & PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK) {
sys/dev/pci/drm/amd/amdgpu/cik.c
1589
tmp &= ~(PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK |
sys/dev/pci/drm/amd/amdgpu/cik.c
1591
tmp |= (max_lw <<
sys/dev/pci/drm/amd/amdgpu/cik.c
1593
tmp |= PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK |
sys/dev/pci/drm/amd/amdgpu/cik.c
1596
WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/cik.c
1620
tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
sys/dev/pci/drm/amd/amdgpu/cik.c
1621
tmp |= PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;
sys/dev/pci/drm/amd/amdgpu/cik.c
1622
WREG32_PCIE(ixPCIE_LC_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/cik.c
1624
tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
sys/dev/pci/drm/amd/amdgpu/cik.c
1625
tmp |= PCIE_LC_CNTL4__LC_REDO_EQ_MASK;
sys/dev/pci/drm/amd/amdgpu/cik.c
1626
WREG32_PCIE(ixPCIE_LC_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/cik.c
1654
tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
sys/dev/pci/drm/amd/amdgpu/cik.c
1655
tmp &= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;
sys/dev/pci/drm/amd/amdgpu/cik.c
1656
WREG32_PCIE(ixPCIE_LC_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/cik.c
1890
int tmp;
sys/dev/pci/drm/amd/amdgpu/cik.c
1922
tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK);
sys/dev/pci/drm/amd/amdgpu/cik.c
1923
cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
sys/dev/pci/drm/amd/amdgpu/cik.c
1924
cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
sys/dev/pci/drm/amd/amdgpu/cik.c
957
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/cik.c
959
tmp = RREG32(mmCONFIG_CNTL);
sys/dev/pci/drm/amd/amdgpu/cik.c
961
tmp |= CONFIG_CNTL__VGA_DIS_MASK;
sys/dev/pci/drm/amd/amdgpu/cik.c
963
tmp &= ~CONFIG_CNTL__VGA_DIS_MASK;
sys/dev/pci/drm/amd/amdgpu/cik.c
964
WREG32(mmCONFIG_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
191
u32 wptr, tmp;
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
204
tmp = RREG32(mmIH_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
205
tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
206
WREG32(mmIH_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
211
tmp &= ~IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
212
WREG32(mmIH_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
351
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
353
if (tmp & SRBM_STATUS__IH_BUSY_MASK)
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
362
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
367
tmp = RREG32(mmSRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK;
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
368
if (!tmp)
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
380
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
382
if (tmp & SRBM_STATUS__IH_BUSY_MASK)
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
386
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
387
tmp |= srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
388
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
389
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
390
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
394
tmp &= ~srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
395
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
396
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1025
u32 tmp = RREG32(mmSRBM_STATUS2);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1027
if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1051
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1054
tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1055
tmp |= SDMA0_F32_CNTL__HALT_MASK;
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1056
WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1060
tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1061
tmp |= SDMA0_F32_CNTL__HALT_MASK;
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1062
WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1066
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1067
tmp |= srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1068
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1069
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1070
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1074
tmp &= ~srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1075
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1076
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
606
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
614
tmp = 0xCAFEDEAD;
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
615
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
629
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
630
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
658
u32 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
667
tmp = 0xCAFEDEAD;
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
668
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
693
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
694
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
193
u32 wptr, tmp;
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
215
tmp = RREG32(mmIH_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
216
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
217
WREG32(mmIH_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
222
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
223
WREG32(mmIH_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
347
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
349
if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
358
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
363
tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
364
if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
375
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
377
if (tmp & SRBM_STATUS__IH_BUSY_MASK)
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
382
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
383
tmp |= srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
384
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
385
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
386
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
390
tmp &= ~srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
391
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
392
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1035
u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1126
tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1127
WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1128
tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1129
tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1130
tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1131
WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1133
tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1134
WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1135
tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1136
tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1137
tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1138
WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1180
u32 offset, tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1184
tmp = RREG32_AUDIO_ENDPT(offset,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1186
if (((tmp &
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1214
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1219
tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1220
tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1221
WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1234
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1257
tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1259
tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1262
tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1264
tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1268
ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1280
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1308
tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1310
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1313
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1316
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1319
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1322
ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1379
u32 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1389
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1391
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1393
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1405
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1407
WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1483
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1485
tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1486
tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1487
WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1488
tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1489
tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1490
WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1492
tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1493
tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1494
WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1495
tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1496
tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1497
WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1499
tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1500
tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1501
WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1502
tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1503
tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1504
WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1540
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1550
tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1551
tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1553
WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1572
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1594
tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1595
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1596
WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1600
tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1607
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1608
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1613
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1614
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1619
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1620
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1625
WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1627
tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1628
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1629
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1630
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1631
WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1633
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1635
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1637
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1638
WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1640
tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1642
tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1643
WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1645
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1647
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1648
WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1652
tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1654
tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1656
tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1657
WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1659
tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1661
tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1662
WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1664
tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1667
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1670
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1672
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1673
WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1677
tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1678
tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1679
WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1681
tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1682
tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1683
WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1685
tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1686
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1687
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1688
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1689
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1690
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1691
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1692
WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1717
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1719
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1721
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1722
WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1724
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1725
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1726
WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1728
tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1730
tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1731
WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1853
u32 tmp, viewport_w, viewport_h;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2013
tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2014
tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2016
WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2034
tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2036
tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2038
tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2039
WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2092
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2094
tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2096
tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2098
tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2099
WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2109
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2113
tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2114
tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2115
tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2116
WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2118
tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2119
tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2120
WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2122
tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2123
tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2124
WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2126
tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2127
tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2128
tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2129
WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2155
tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2156
tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2157
tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2158
tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2159
WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2161
tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2162
tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2163
tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2164
WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2166
tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2167
tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2168
tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2169
WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2171
tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2172
tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2173
tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2174
WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2181
tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2182
tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2183
WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2292
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2294
tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2295
tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2296
WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2303
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2310
tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2311
tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2312
tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2313
WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
239
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
242
tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
243
tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
245
WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2981
u32 srbm_soft_reset = 0, tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2988
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2989
tmp |= srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2990
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2991
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2992
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2996
tmp &= ~srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2997
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2998
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
306
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3069
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3078
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3079
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3080
WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3083
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3084
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3085
WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
312
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
314
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
316
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
317
WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3221
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3228
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3229
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3230
WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3236
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3243
tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3244
tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3245
WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3251
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3258
tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3259
tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3260
WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
333
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
349
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
350
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
351
WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
355
tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
356
tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
357
WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
359
tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
360
tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
363
tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
366
WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
389
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
398
tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
399
tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
400
WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
417
u32 i, j, tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
420
tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
421
if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
430
tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
431
if (tmp != crtc_status[i])
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
446
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
449
tmp = RREG32(mmVGA_HDP_CONTROL);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
451
tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
453
tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
454
WREG32(mmVGA_HDP_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
457
tmp = RREG32(mmVGA_RENDER_CONTROL);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
459
tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
461
tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
462
WREG32(mmVGA_RENDER_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
484
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
495
tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
496
tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
497
WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
512
u32 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
537
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
538
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
539
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
540
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
542
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
543
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
549
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
550
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
551
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
552
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
553
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
555
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
556
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
562
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
563
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
564
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
565
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
566
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
568
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
569
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
577
WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
598
u32 tmp, buffer_alloc, i, mem_cfg;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
628
tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
629
tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
630
WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
632
tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
633
tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
634
WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
637
tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
638
if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
670
u32 tmp = RREG32(mmMC_SHARED_CHMAP);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
672
switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
902
u32 tmp, dmif_size = 12288;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
921
tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
922
tmp = min(dfixed_trunc(a), tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
924
lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1013
tmp = arb_control3;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1014
tmp &= ~(3 << DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK__SHIFT);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1015
tmp |= (1 << DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK__SHIFT);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1016
WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1021
tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1022
tmp &= ~(3 << DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK__SHIFT);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1023
tmp |= (2 << DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK__SHIFT);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1024
WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1062
u32 tmp, buffer_alloc, i;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1079
tmp = 0; /* 1/2 */
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1082
tmp = 2; /* whole */
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1086
tmp = 0;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1091
(tmp << DC_LB_MEMORY_SPLIT__DC_LB_MEMORY_CONFIG__SHIFT));
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1103
switch (tmp) {
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1154
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1157
tmp = RREG32_AUDIO_ENDPT(adev->mode_info.audio.pin[i].offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1159
if (REG_GET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1207
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1227
tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1229
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1232
tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1234
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1238
ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1252
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1275
tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1277
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1279
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1283
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1286
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1290
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1293
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1297
ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1468
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1470
tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1471
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1472
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1473
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1474
WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1485
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1487
tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1488
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1489
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1491
WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1493
tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1494
tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1495
WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1496
tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1497
tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1498
WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1500
tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1501
tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1502
WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1503
tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1504
tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1505
WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1507
tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1508
tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1509
WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1510
tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1511
tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1512
WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1528
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1551
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1553
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1555
WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1564
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1572
tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1573
tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1576
tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1579
tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1582
WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1598
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1600
tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1601
tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1602
WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1604
tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1605
tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1606
WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1608
tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1609
tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1610
WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1612
tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1613
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1614
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1615
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1616
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1617
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1618
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1619
WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1621
tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1622
tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, 0xff);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1623
WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1625
tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1626
tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1627
tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1628
WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1630
tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1631
tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_RESET_FIFO_WHEN_AUDIO_DIS, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1632
tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1633
WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1642
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1644
tmp = RREG32(mmHDMI_GC + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1645
tmp = REG_SET_FIELD(tmp, HDMI_GC, HDMI_GC_AVMUTE, mute ? 1 : 0);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1646
WREG32(mmHDMI_GC + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1655
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1658
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1659
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1660
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1661
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1662
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1663
WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1665
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1666
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1667
WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1669
tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1670
tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1671
WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1673
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1674
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1675
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1676
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1677
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1678
WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1680
tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1681
tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1682
WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1692
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1695
tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1696
tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1697
WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1699
tmp = RREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1700
tmp = REG_SET_FIELD(tmp, DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1701
WREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1703
tmp = RREG32(mmDP_SEC_CNTL + dig->afmt->offset);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1704
tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1705
tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ATP_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1706
tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_AIP_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1707
tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1708
WREG32(mmDP_SEC_CNTL + dig->afmt->offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
270
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
276
tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
278
tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
280
tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
281
WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
287
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2919
u32 srbm_soft_reset = 0, tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2926
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2927
tmp |= srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2928
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2929
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2930
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2934
tmp &= ~srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2935
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2936
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
294
tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
295
tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
296
WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
312
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
321
tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
322
tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
323
WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
332
tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
333
tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
334
WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
358
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
367
tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
368
tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
369
WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
385
u32 i, j, tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
397
tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
398
if (tmp != crtc_status[i])
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
436
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
447
tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
448
tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
449
WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
464
u32 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
485
tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
489
tmp |= FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
494
tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
500
tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
509
WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
523
u32 tmp = RREG32(mmMC_SHARED_CHMAP);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
525
switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
755
u32 tmp, dmif_size = 12288;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
774
tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
775
tmp = min(dfixed_trunc(a), tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
777
lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
892
u32 tmp, arb_control3, lb_vblank_lead_lines = 0;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1079
tmp = wm_mask;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1080
tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1081
tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1082
WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1087
tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1088
tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1089
tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1090
WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1135
u32 offset, tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1139
tmp = RREG32_AUDIO_ENDPT(offset,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1141
if (((tmp &
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1190
u32 tmp = 0, offset;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1213
tmp =
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1219
tmp =
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1226
tmp =
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1232
tmp =
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1239
WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1251
u32 offset, tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1281
tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1282
tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK |
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1285
tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1287
tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1289
tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1290
WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
254
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
260
tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
262
tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
264
tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
265
WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
271
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
278
tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
279
tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
280
WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2891
u32 srbm_soft_reset = 0, tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2898
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2899
tmp |= srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2900
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2901
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2902
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2906
tmp &= ~srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2907
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2908
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
296
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
305
tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
306
tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
307
WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
316
tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
317
tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
318
WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
342
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
351
tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
352
tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
353
WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
369
u32 i, j, tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
381
tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
382
if (tmp != crtc_status[i])
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
397
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
400
tmp = RREG32(mmVGA_HDP_CONTROL);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
402
tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
404
tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
405
WREG32(mmVGA_HDP_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
408
tmp = RREG32(mmVGA_RENDER_CONTROL);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
410
tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
412
tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
413
WREG32(mmVGA_RENDER_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
442
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
453
tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
454
tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
455
WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
470
u32 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
495
tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
500
tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
506
tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
512
tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
518
tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
524
tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
532
WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
553
u32 tmp, buffer_alloc, i;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
565
tmp = 1;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
568
tmp = 2;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
571
tmp = 0;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
575
tmp = 0;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
579
tmp = 1;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
584
(tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) |
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
597
switch (tmp) {
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
623
u32 tmp = RREG32(mmMC_SHARED_CHMAP);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
625
switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
855
u32 tmp, dmif_size = 12288;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
874
tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
875
tmp = min(dfixed_trunc(a), tmp);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
877
lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
988
u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
106
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
109
tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
110
if (tmp & DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY)
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
46
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
49
tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
50
tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
51
WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
59
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
61
tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
62
tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
63
tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
65
return tmp;
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
82
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
88
tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
89
tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
90
tmp |= DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY;
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
91
WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
93
tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
94
tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
95
tmp |= DF_V1_7_MGCG_DISABLE;
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
96
WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
216
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
227
tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DfGlobalCtrl);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
228
adev->df.hash_status.hash_64k = REG_GET_FIELD(tmp,
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
231
adev->df.hash_status.hash_2m = REG_GET_FIELD(tmp,
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
234
adev->df.hash_status.hash_1g = REG_GET_FIELD(tmp,
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
267
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
270
tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
271
tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
272
WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
280
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
283
tmp = RREG32_SOC15(DF, 0, mmDF_GCM_AON0_DramMegaBaseAddress0);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
284
tmp &=
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
287
tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
288
tmp &= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
290
tmp >>= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
292
return tmp;
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
309
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
316
tmp = RREG32_SOC15(DF, 0,
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
318
tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
319
tmp |= DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY;
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
321
mmDF_PIE_AON0_DfGlobalClkGater, tmp);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
323
tmp = RREG32_SOC15(DF, 0,
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
325
tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
326
tmp |= DF_V3_6_MGCG_DISABLE;
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
328
mmDF_PIE_AON0_DfGlobalClkGater, tmp);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
339
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
342
tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
343
if (tmp & DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY)
sys/dev/pci/drm/amd/amdgpu/df_v4_15.c
32
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/df_v4_15.c
37
tmp = RREG32_SOC15(DF, 0, regNCSConfigurationRegister1);
sys/dev/pci/drm/amd/amdgpu/df_v4_15.c
38
tmp |= (dis_lcl_proc << NCSConfigurationRegister1__DisIntAtomicsLclProcessing__SHIFT);
sys/dev/pci/drm/amd/amdgpu/df_v4_15.c
39
WREG32_SOC15(DF, 0, regNCSConfigurationRegister1, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
3827
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
3848
tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
3850
tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
3852
tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
3853
WREG32_SOC15(GC, 0, mmCP_VMID_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4037
uint32_t tmp = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4056
tmp = RREG32(scratch);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4057
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5258
u32 tmp, wgp_active_bitmap = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5303
tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5305
tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5306
tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5307
WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5309
tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5311
tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5312
tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5313
WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5341
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5361
tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5363
tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5365
WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5421
u32 tmp, cp_int_cntl_reg;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5432
tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5433
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5435
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5437
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5439
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5441
WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5470
u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5472
tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5473
WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5521
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5524
tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5525
tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5526
tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5527
WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5850
uint32_t rlc_g_offset, rlc_g_size, tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5865
tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5866
if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5872
tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5873
if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5884
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5889
tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5890
tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5891
WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5895
tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5896
if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5921
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5926
tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5927
tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5928
WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5932
tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5933
if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5958
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5963
tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5964
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5965
WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5969
tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5970
if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5995
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6000
tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6001
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6002
WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6006
tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6007
if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6075
u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6077
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6078
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6079
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6082
WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6084
WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6107
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6136
tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6137
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6138
WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6142
tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6143
if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6157
tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6158
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6159
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6160
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6161
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6162
WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6185
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6214
tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6215
tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6216
WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6220
tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6221
if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6235
tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6236
tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6237
tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6238
tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6239
tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6262
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6291
tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6292
tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6293
WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6297
tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6298
if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6312
tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6313
tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6314
tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6315
tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6316
tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6446
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6448
tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6449
tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6451
WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6457
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6460
tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6462
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6464
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6467
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6470
WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6481
tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6483
WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6489
tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6491
WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6502
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6519
tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6520
tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6522
tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6524
WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6544
WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6562
tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6563
tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6564
WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6581
WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6650
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6666
tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6667
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6668
WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6672
tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6673
if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6687
tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6688
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6689
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6690
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6691
WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6717
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6730
tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6731
tmp &= 0xffffff00;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6732
tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6733
WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp | 0x80);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6736
tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6737
tmp &= 0xffffff00;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6738
tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6739
WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp | 0x80);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6749
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6757
tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6758
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6759
mqd->cp_gfx_hqd_queue_priority = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6767
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6779
tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6780
tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6781
tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6782
tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6783
mqd->cp_gfx_mqd_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6786
tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6787
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6794
tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6795
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6796
mqd->cp_gfx_hqd_quantum = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6816
tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6817
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6818
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6820
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6822
mqd->cp_gfx_hqd_cntl = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6825
tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6827
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6829
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6832
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6834
mqd->cp_rb_doorbell_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6911
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6926
tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6927
tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6930
mqd->cp_hqd_eop_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6933
tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6936
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6938
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6940
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6942
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6945
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6949
mqd->cp_hqd_pq_doorbell_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6962
tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6963
tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6964
mqd->cp_mqd_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6972
tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6973
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6975
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6978
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6980
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6981
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6983
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6984
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6985
mqd->cp_hqd_pq_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7004
tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7005
tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7006
mqd->cp_hqd_persistent_state = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7009
tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7010
tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7011
mqd->cp_hqd_ib_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7594
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7599
tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7602
if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7612
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7616
tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7617
if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7630
if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7637
tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7646
if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7653
if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7671
tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7672
tmp |= grbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7673
dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7674
WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7675
tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7679
tmp &= ~grbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7680
WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7681
tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9417
uint32_t tmp, target;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9429
tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9430
tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9432
WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9434
tmp = RREG32_SOC15_IP(GC, target);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9435
tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9437
WREG32_SOC15_IP(GC, target, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9439
tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9440
tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9442
WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9444
tmp = RREG32_SOC15_IP(GC, target);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9445
tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9447
WREG32_SOC15_IP(GC, target, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9520
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9538
tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9540
tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << ring->queue);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9542
tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << ring->queue);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9545
SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2125
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2137
tmp = RREG32_SOC15(GC, 0, regTA_CNTL2);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2139
REG_GET_FIELD(tmp, TA_CNTL2, TRUNCATE_COORD_MODE);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2149
tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2151
tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2153
WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2208
u32 tmp, cp_int_cntl_reg;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2219
tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2220
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2222
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2224
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2226
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2228
WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2249
u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2251
tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2252
WREG32_SOC15(GC, 0, regRLC_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2298
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2301
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2302
tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2303
tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2304
WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2333
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2366
tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2367
tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2368
tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2369
WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2377
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2396
tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2397
tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2398
WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2415
tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2416
tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2417
WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2490
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2494
tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2495
tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2496
WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2500
tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2501
if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2515
tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2516
tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2517
tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2518
tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2519
tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2520
WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2534
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2538
tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2539
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2540
WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2544
tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2545
if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2559
tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2560
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2561
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2562
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2563
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2564
WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2578
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2582
tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2583
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2585
WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2589
tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2590
if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2604
tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2605
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2606
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2607
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2608
WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2622
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2634
tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2635
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2636
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2637
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2638
WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2646
tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2647
if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2659
tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2660
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2661
WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2664
tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2665
if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2689
tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2691
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2694
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2696
WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2700
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2703
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2705
WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2715
tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2716
tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2717
tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2718
WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2721
tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2722
tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2723
WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2726
tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2727
if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2744
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2756
tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2757
tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2758
tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2759
tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2760
WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2768
tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2769
if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2781
tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2782
tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2783
WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2787
tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2788
if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2812
tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2814
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2817
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2819
WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2823
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2826
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2828
WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2838
tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2839
tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2840
tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2841
WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2844
tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2845
tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2846
WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2849
tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2850
if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2867
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2874
tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2875
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2876
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2877
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2878
WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2880
tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2881
tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2882
tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2883
WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2907
tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2908
tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2909
WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2913
tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2914
if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2926
tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2927
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2928
WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2932
tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2933
if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2952
uint32_t pipe_id, tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2973
tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2974
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2975
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2976
WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2979
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2980
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2981
WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2995
tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2996
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2997
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2998
WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3001
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3002
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3003
WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3017
tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3018
tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3019
tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3020
tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3021
tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3022
WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3025
tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3026
tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3027
tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3028
tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3029
WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3116
u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3118
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3119
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3120
WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3185
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3245
tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3246
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3247
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3248
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3249
WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3257
tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3258
if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3270
tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3271
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3272
WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3275
tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3276
if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3300
tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3302
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3305
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3307
WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3311
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3314
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3316
WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3326
tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3327
tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3328
tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3329
WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3332
tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3333
tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3334
WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3337
tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3338
if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3403
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3463
tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3464
tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3465
tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3466
tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3467
WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3475
tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3476
if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3488
tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3489
tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3490
WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3494
tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3495
if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3519
tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3521
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3524
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3526
WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3530
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3533
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3535
WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3545
tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3546
tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3547
tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3548
WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3551
tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3552
tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3553
WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3556
tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3557
if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3680
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3682
tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3683
tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3685
WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3691
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3693
tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3695
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3697
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3700
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3703
WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3705
tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3707
WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3716
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3733
tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3734
tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3735
WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3755
WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3773
tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3774
tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3775
WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3792
WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3913
u32 tmp, fw_ucode_size, fw_data_size;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3968
tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3969
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3970
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3971
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3972
WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3974
tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3975
tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3976
tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3977
WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4001
tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4002
tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4003
WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4007
tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4008
if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4020
tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4021
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4022
WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4026
tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4027
if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4043
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4047
tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4048
tmp &= 0xffffff00;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4049
tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4050
WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4073
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4081
tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4082
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4083
mqd->cp_gfx_hqd_queue_priority = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4091
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4103
tmp = regCP_GFX_MQD_CONTROL_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4104
tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4105
tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4106
tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4107
mqd->cp_gfx_mqd_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4110
tmp = regCP_GFX_HQD_VMID_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4111
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4118
tmp = regCP_GFX_HQD_QUANTUM_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4119
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4120
mqd->cp_gfx_hqd_quantum = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4140
tmp = regCP_GFX_HQD_CNTL_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4141
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4142
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4144
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4147
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4149
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4150
mqd->cp_gfx_hqd_cntl = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4153
tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4155
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4157
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4160
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4162
mqd->cp_rb_doorbell_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4233
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4248
tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4249
tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4252
mqd->cp_hqd_eop_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4255
tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4258
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4260
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4262
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4264
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4267
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4271
mqd->cp_hqd_pq_doorbell_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4284
tmp = regCP_MQD_CONTROL_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4285
tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4286
mqd->cp_mqd_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4294
tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4295
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4297
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4299
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4300
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4303
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4304
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4307
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4308
mqd->cp_hqd_pq_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4321
tmp = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4324
tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4325
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4328
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4330
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4332
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4336
mqd->cp_hqd_pq_doorbell_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4344
tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4345
tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4346
mqd->cp_hqd_persistent_state = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4349
tmp = regCP_HQD_IB_CONTROL_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4350
tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4351
mqd->cp_hqd_ib_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4674
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4678
tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4679
tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4680
WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4682
tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4683
tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4684
WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4949
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4954
tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) &
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4957
if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4967
u32 i, tmp, val;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4971
tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4972
tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, CLIENTID, 4);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4973
WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4977
if (val == tmp)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4980
tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4984
if (val != tmp)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4999
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5005
tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5006
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5007
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5008
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5009
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5010
WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5098
tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5099
tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5100
WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5115
tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5116
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5117
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5118
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5119
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5120
WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
562
uint32_t tmp = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
585
tmp = RREG32(scratch);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
586
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6697
uint32_t tmp, target;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6706
tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6707
tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6709
WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6711
tmp = RREG32_SOC15_IP(GC, target);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6712
tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6714
WREG32_SOC15_IP(GC, target, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6716
tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6717
tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6719
WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6721
tmp = RREG32_SOC15_IP(GC, target);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6722
tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6724
WREG32_SOC15_IP(GC, target, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1802
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1821
tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1823
tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1825
WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1873
u32 tmp, cp_int_cntl_reg;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1884
tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1885
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1887
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1889
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1891
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1893
WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1914
u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1916
tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1917
WREG32_SOC15(GC, 0, regRLC_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1963
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1966
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1967
tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1968
tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1969
WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1998
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2031
tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2032
tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2033
tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2034
WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2108
uint32_t pipe_id, tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2129
tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2130
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2131
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2132
WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2135
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2136
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2137
WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2151
tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2152
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2153
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2154
WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2157
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2158
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2159
WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2173
tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2174
tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2175
tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2176
tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2177
tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2178
WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2181
tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2182
tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2183
tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2184
tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2185
WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2191
unsigned pipe_id, tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2208
tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2210
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2213
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2215
WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2219
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2222
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2224
WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2233
unsigned pipe_id, tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2250
tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2252
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2255
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2257
WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2261
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2264
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2266
WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2329
u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2331
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2332
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2333
WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2353
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2409
tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2410
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2411
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2412
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2413
WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2421
tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2422
if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2434
tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2435
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2436
WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2439
tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2440
if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2463
tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2464
tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2465
tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2466
WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2469
tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2470
tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2471
WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2474
tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2475
if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2497
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2553
tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2554
tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2555
tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2556
tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2557
WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2565
tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2566
if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2578
tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2579
tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2580
WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2584
tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2585
if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2608
tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2609
tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2610
tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2611
WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2614
tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2615
tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2616
WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2619
tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2620
if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2676
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2678
tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2679
tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2681
WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2687
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2689
tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2691
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2693
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2696
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2699
WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2701
tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2703
WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2712
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2729
tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2730
tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2731
WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2751
WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2808
u32 tmp, fw_ucode_size, fw_data_size;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2863
tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2864
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2865
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2866
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2867
WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2869
tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2870
tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2871
tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2872
WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2894
tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2895
tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2896
WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2900
tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2901
if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2913
tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2914
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2915
WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2919
tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2920
if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2938
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2942
tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2943
tmp &= 0xffffff00;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2944
tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2945
WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2968
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2980
tmp = regCP_GFX_MQD_CONTROL_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2981
tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2982
tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2983
tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2984
mqd->cp_gfx_mqd_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2987
tmp = regCP_GFX_HQD_VMID_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2988
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2993
tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2994
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2995
mqd->cp_gfx_hqd_queue_priority = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2998
tmp = regCP_GFX_HQD_QUANTUM_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2999
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3000
mqd->cp_gfx_hqd_quantum = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3020
tmp = regCP_GFX_HQD_CNTL_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3021
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3022
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3024
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3027
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3029
tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3030
mqd->cp_gfx_hqd_cntl = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3033
tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3035
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3037
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3040
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3042
mqd->cp_rb_doorbell_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3111
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3126
tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3127
tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3130
mqd->cp_hqd_eop_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3133
tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3136
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3138
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3140
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3142
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3145
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3149
mqd->cp_hqd_pq_doorbell_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3162
tmp = regCP_MQD_CONTROL_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3163
tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3164
mqd->cp_mqd_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3172
tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3173
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3175
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3177
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3178
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3180
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3181
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3184
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3185
mqd->cp_hqd_pq_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3198
tmp = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3201
tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3202
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3205
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3207
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3209
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3213
mqd->cp_hqd_pq_doorbell_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3221
tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3222
tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3223
mqd->cp_hqd_persistent_state = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3226
tmp = regCP_HQD_IB_CONTROL_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3227
tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3228
mqd->cp_hqd_ib_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3743
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3767
tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3768
tmp &= 0xffffff00;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3769
WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3807
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3812
tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) &
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3815
if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
454
uint32_t tmp = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
478
tmp = RREG32(scratch);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
479
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1585
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1689
tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1690
adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1791
uint32_t tmp = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1807
tmp = RREG32(mmSCRATCH_REG0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1808
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1899
uint32_t tmp = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1924
tmp = RREG32(mmSCRATCH_REG0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1925
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2072
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2090
tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2093
tmp |= BUF_SWAP_32BIT;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2095
WREG32(mmCP_RB0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2098
WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2110
WREG32(mmCP_RB0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2169
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2179
tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2181
tmp |= BUF_SWAP_32BIT;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2183
WREG32(mmCP_RB1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2185
WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2194
WREG32(mmCP_RB1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2199
tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2201
tmp |= BUF_SWAP_32BIT;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2203
WREG32(mmCP_RB2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2205
WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2213
WREG32(mmCP_RB2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2239
u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2244
tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2247
tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2249
WREG32(mmCP_INT_CNTL_RING0, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2253
tmp = RREG32(mmDB_DEPTH_INFO);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2439
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2441
tmp = RREG32(mmRLC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2442
if (tmp != rlc)
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2489
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2492
tmp = RREG32(mmMC_SEQ_MISC0);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2493
if ((tmp & 0xF0000000) == 0xB0000000)
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2549
u32 data, orig, tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2558
tmp = gfx_v6_0_halt_rlc(adev);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2565
gfx_v6_0_update_rlc(adev, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2589
u32 data, orig, tmp = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2609
tmp = gfx_v6_0_halt_rlc(adev);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2615
gfx_v6_0_update_rlc(adev, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2632
tmp = gfx_v6_0_halt_rlc(adev);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2638
gfx_v6_0_update_rlc(adev, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2766
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2770
tmp = RREG32(mmRLC_MAX_PG_CU);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2771
tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2772
tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2773
WREG32(mmRLC_MAX_PG_CU, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2806
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2812
tmp = RREG32(mmRLC_AUTO_PG_CTRL);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2813
tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2814
tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2815
tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2816
WREG32(mmRLC_AUTO_PG_CTRL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1894
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1962
tmp = RREG32(mmSPI_CONFIG_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1963
tmp |= 0x03000000;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1964
WREG32(mmSPI_CONFIG_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1970
tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1971
tmp |= 0x00000400;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1972
WREG32(mmDB_DEBUG2, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1974
tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1975
tmp |= 0x00020200;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1976
WREG32(mmDB_DEBUG3, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1978
tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1979
tmp |= 0x00018208;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1980
WREG32(mmCB_HW_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2011
tmp = RREG32(mmSPI_ARB_PRIORITY);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2012
tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2013
tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2014
tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2015
tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2016
WREG32(mmSPI_ARB_PRIORITY, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2036
uint32_t tmp = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2051
tmp = RREG32(mmSCRATCH_REG0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2052
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2304
uint32_t tmp = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2329
tmp = RREG32(mmSCRATCH_REG0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2330
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2539
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2560
tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2562
tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2564
WREG32(mmCP_RB0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2567
WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2580
WREG32(mmCP_RB0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2773
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2790
tmp = RREG32(mmCP_HPD_EOP_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2791
tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2792
tmp |= order_base_2(GFX7_MEC_HPD_SIZE / 8);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2793
WREG32(mmCP_HPD_EOP_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2945
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2953
tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2954
tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2955
WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3010
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3014
tmp = RREG32(mmCP_CPF_DEBUG);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3015
tmp |= (1 << 23);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3016
WREG32(mmCP_CPF_DEBUG, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3065
u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3068
tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3071
tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3073
WREG32(mmCP_INT_CNTL_RING0, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3255
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3257
tmp = RREG32(mmRLC_LB_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3259
tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3261
tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3262
WREG32(mmRLC_LB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3297
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3299
tmp = RREG32(mmRLC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3300
if (tmp != rlc)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3335
u32 tmp, i, mask;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3337
tmp = 0x1 | (1 << 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3338
WREG32(mmRLC_GPR_REG2, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3357
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3359
tmp = 0x1 | (0 << 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3360
WREG32(mmRLC_GPR_REG2, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3397
u32 tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3399
tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3400
WREG32(mmGRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3402
tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3403
WREG32(mmGRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3421
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3435
tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3436
WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3492
u32 data, orig, tmp, tmp2;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3499
tmp = gfx_v7_0_halt_rlc(adev);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3511
gfx_v7_0_update_rlc(adev, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3535
u32 data, orig, tmp = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3553
tmp = gfx_v7_0_halt_rlc(adev);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3564
gfx_v7_0_update_rlc(adev, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3604
tmp = gfx_v7_0_halt_rlc(adev);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3614
gfx_v7_0_update_rlc(adev, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3756
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3760
tmp = RREG32(mmRLC_MAX_PG_CU);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3761
tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3762
tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3763
WREG32(mmRLC_MAX_PG_CU, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4138
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4225
tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4226
dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4227
dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4229
tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4230
dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4231
dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4250
tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4251
adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4493
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4498
tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4500
if (!tmp)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4510
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4514
tmp = RREG32(mmGRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4515
if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4524
if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4530
tmp = RREG32(mmGRBM_STATUS2);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4531
if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4535
tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4536
if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4554
tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4555
tmp |= grbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4556
dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4557
WREG32(mmGRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4558
tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4562
tmp &= ~grbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4563
WREG32(mmGRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4564
tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4568
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4569
tmp |= srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4570
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4571
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4572
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4576
tmp &= ~srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4577
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4578
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1092
tmp = (unsigned int *)((uintptr_t)rlc_hdr +
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1095
adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1099
tmp = (unsigned int *)((uintptr_t)rlc_hdr +
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1102
adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1480
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1492
tmp = RREG32(mmGB_EDC_MODE);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1618
tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1619
tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1620
WREG32(mmGB_EDC_MODE, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1622
tmp = RREG32(mmCC_GC_EDC_CONFIG);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1623
tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1624
WREG32(mmCC_GC_EDC_CONFIG, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1643
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1793
tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1794
dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1795
dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1797
tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1798
dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1799
dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1818
tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1819
adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3724
u32 tmp, sh_static_mem_cfg;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3752
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3753
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3754
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3756
WREG32(mmSH_MEM_CONFIG, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3759
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3760
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3761
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3763
WREG32(mmSH_MEM_CONFIG, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3764
tmp = adev->gmc.shared_aperture_start >> 48;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3765
WREG32(mmSH_MEM_BASES, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3794
tmp = RREG32(mmSPI_ARB_PRIORITY);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3795
tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3796
tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3797
tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3798
tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3799
WREG32(mmSPI_ARB_PRIORITY, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3846
u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3848
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3849
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3850
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3851
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3853
WREG32(mmCP_INT_CNTL_RING0, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4086
u32 tmp = RREG32(mmCP_ME_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4089
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4090
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4091
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4093
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4094
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4095
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4097
WREG32(mmCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4195
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4200
tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4203
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4205
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4207
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4210
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4213
WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4218
tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4221
WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4230
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4243
tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4244
tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4245
tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4246
tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4248
tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4250
WREG32(mmCP_RB0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4253
WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4266
WREG32(mmCP_RB0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4294
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4298
tmp = RREG32(mmRLC_CP_SCHEDULERS);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4299
tmp &= 0xffffff00;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4300
tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4301
WREG32(mmRLC_CP_SCHEDULERS, tmp | 0x80);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4404
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4422
tmp = RREG32(mmCP_HQD_EOP_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4423
tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4426
mqd->cp_hqd_eop_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4429
tmp = REG_SET_FIELD(RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL),
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4434
mqd->cp_hqd_pq_doorbell_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4441
tmp = RREG32(mmCP_MQD_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4442
tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4443
mqd->cp_mqd_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4451
tmp = RREG32(mmCP_HQD_PQ_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4452
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4454
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4457
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4459
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4460
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4461
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4462
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4463
mqd->cp_hqd_pq_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4476
tmp = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4479
tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4480
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4483
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4485
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4487
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4491
mqd->cp_hqd_pq_doorbell_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4501
tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4502
tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4503
mqd->cp_hqd_persistent_state = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4506
tmp = RREG32(mmCP_HQD_IB_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4507
tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4508
tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MTYPE, 3);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4509
mqd->cp_hqd_ib_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4511
tmp = RREG32(mmCP_HQD_IQ_TIMER);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4512
tmp = REG_SET_FIELD(tmp, CP_HQD_IQ_TIMER, MTYPE, 3);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4513
mqd->cp_hqd_iq_timer = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4515
tmp = RREG32(mmCP_HQD_CTX_SAVE_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4516
tmp = REG_SET_FIELD(tmp, CP_HQD_CTX_SAVE_CONTROL, MTYPE, 3);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4517
mqd->cp_hqd_ctx_save_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4894
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4897
tmp = RREG32(mmGRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4898
if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4914
tmp = RREG32(mmGRBM_STATUS2);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4915
if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4919
if (REG_GET_FIELD(tmp, GRBM_STATUS2, CPF_BUSY) ||
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4920
REG_GET_FIELD(tmp, GRBM_STATUS2, CPC_BUSY) ||
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4921
REG_GET_FIELD(tmp, GRBM_STATUS2, CPG_BUSY)) {
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4933
tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4934
if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4937
if (REG_GET_FIELD(tmp, SRBM_STATUS, SEM_BUSY))
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4997
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5007
tmp = RREG32(mmGMCON_DEBUG);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5008
tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5009
tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5010
WREG32(mmGMCON_DEBUG, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5015
tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5016
tmp |= grbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5017
dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5018
WREG32(mmGRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5019
tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5023
tmp &= ~grbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5024
WREG32(mmGRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5025
tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5029
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5030
tmp |= srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5031
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5032
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5033
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5037
tmp &= ~srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5038
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5039
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5043
tmp = RREG32(mmGMCON_DEBUG);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5044
tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5045
tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5046
WREG32(mmGMCON_DEBUG, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
841
uint32_t tmp = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
856
tmp = RREG32(mmSCRATCH_REG0);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
857
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
876
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
910
tmp = adev->wb.wb[index];
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
911
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
947
unsigned int *tmp = NULL, i;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1198
uint32_t tmp = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1213
tmp = RREG32(scratch);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1214
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1232
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1266
tmp = adev->wb.wb[index];
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1267
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2643
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2647
tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2648
tmp = REG_SET_FIELD(tmp, SQ_CONFIG, DISABLE_BARRIER_WAITCNT,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2650
WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2662
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2684
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2686
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2688
WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2691
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2693
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2695
WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2696
tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2698
tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2700
WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2753
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2757
tmp= RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2759
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2760
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2761
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2763
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2765
WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2827
u32 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2847
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2848
tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2849
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3243
u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3245
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_INVALIDATE_ICACHE, enable ? 0 : 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3246
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_INVALIDATE_ICACHE, enable ? 0 : 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3247
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_INVALIDATE_ICACHE, enable ? 0 : 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3248
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_PIPE0_RESET, enable ? 0 : 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3249
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_PIPE1_RESET, enable ? 0 : 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3250
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, enable ? 0 : 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3251
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, enable ? 0 : 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3252
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, enable ? 0 : 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3253
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, enable ? 0 : 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3254
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3255
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3256
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3257
WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3323
int r, i, tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3378
tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3380
amdgpu_ring_write(ring, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3391
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3404
tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3405
tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3407
tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3409
WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3426
WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3432
tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3434
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3436
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3439
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3441
WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3443
tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3445
WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3482
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3495
tmp = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3496
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3497
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3498
WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3522
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3526
tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3527
tmp &= 0xffffff00;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3528
tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3529
WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp | 0x80);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3550
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3576
tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3577
tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3580
mqd->cp_hqd_eop_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3583
tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3586
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3588
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3590
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3592
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3595
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3599
mqd->cp_hqd_pq_doorbell_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3613
tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3614
tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3615
mqd->cp_mqd_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3623
tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3624
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3626
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3629
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3631
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3632
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3633
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3634
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3635
mqd->cp_hqd_pq_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3655
tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3656
tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3657
mqd->cp_hqd_persistent_state = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3660
tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3661
tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3662
mqd->cp_hqd_ib_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3995
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4001
tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4002
tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE64KHASH,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4004
tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE2MHASH,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4006
tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE1GHASH,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4008
WREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4137
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4141
tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4142
if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4154
if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4160
tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4161
if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4177
tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4178
tmp |= grbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4179
dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4180
WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4181
tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4185
tmp &= ~grbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4186
WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4187
tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
791
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
795
tmp = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
796
tmp = REG_SET_FIELD(tmp, GC_THROTTLE_CTRL, PATTERN_MODE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
797
WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
799
tmp = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
800
tmp = REG_SET_FIELD(tmp, GC_THROTTLE_CTRL1, PWRBRK_STALL_EN, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
801
WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL1, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
804
tmp = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
805
tmp = REG_SET_FIELD(tmp, PWRBRK_STALL_PATTERN_CTRL, PWRBRK_END_STEP, 0x12);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
806
WREG32_SOC15(GC, 0, regGC_CAC_IND_DATA, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1299
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1309
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1311
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1314
regSH_MEM_CONFIG, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1318
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1320
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1323
regSH_MEM_CONFIG, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1324
tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1327
tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1331
regSH_MEM_BASES, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1508
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1512
tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1514
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1515
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1516
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1518
WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1757
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1772
tmp = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1773
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1774
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1775
WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1802
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1806
tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1807
tmp &= 0xffffff00;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1808
tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1809
WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp | 0x80);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1830
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1852
tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1853
tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1856
mqd->cp_hqd_eop_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1859
tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1862
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1864
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1866
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1868
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1871
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1874
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1878
mqd->cp_hqd_pq_doorbell_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1892
tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1893
tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1894
mqd->cp_mqd_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1902
tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1903
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1905
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1908
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1910
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1911
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1912
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1913
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1914
mqd->cp_hqd_pq_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1934
tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1935
tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1936
mqd->cp_hqd_persistent_state = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1939
tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1940
tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1941
mqd->cp_hqd_ib_control = tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2432
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2436
tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2437
if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2449
if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2455
tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2456
if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2468
tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2469
tmp |= grbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2470
dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2471
WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2472
tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2476
tmp &= ~grbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2477
WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2478
tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
420
uint32_t tmp = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
428
tmp = RREG32(scratch_reg0_offset);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
440
tmp = RREG32(scratch_reg0_offset);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
441
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
459
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4908
u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0, tmp;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
493
tmp = adev->wb.wb[index];
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
494
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4961
tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4962
tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_RELAUNCH_DISABLE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4963
tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_DISPATCH_DISABLE, 1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4964
WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
801
u32 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
813
tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
815
tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
818
tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
189
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
192
tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
194
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
195
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
196
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
198
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
200
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
201
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
204
WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
209
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
218
tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
219
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
220
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
221
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
224
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
226
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
227
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
228
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
229
WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
231
tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
232
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
233
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
234
WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
236
tmp = regGCVM_L2_CNTL3_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
238
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
239
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
242
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
243
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
246
WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
248
tmp = regGCVM_L2_CNTL4_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
249
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
250
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
251
WREG32_SOC15(GC, 0, regGCVM_L2_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
253
tmp = regGCVM_L2_CNTL5_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
254
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
255
WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
260
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
262
tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
263
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
264
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
265
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
267
WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
297
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
300
tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i * hub->ctx_distance);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
301
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
302
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
304
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
306
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
308
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
310
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
312
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
314
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
316
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
318
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
322
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
326
i * hub->ctx_distance, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
339
hub->vm_cntx_cntl = tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
386
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
395
tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
396
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
397
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
399
WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
415
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
418
tmp = RREG32_SOC15(GC, 0, regCP_DEBUG);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
419
tmp = REG_SET_FIELD(tmp, CP_DEBUG, CPG_UTCL1_ERROR_HALT_DISABLE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
420
WREG32_SOC15(GC, 0, regCP_DEBUG, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
428
tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
429
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
431
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
433
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
435
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
437
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
440
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
442
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
444
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
446
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
448
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
450
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
453
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
455
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
458
WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
194
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
197
tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
199
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
200
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
201
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
203
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
205
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
206
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
209
WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
214
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
223
tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
224
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
225
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
226
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
229
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
231
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
232
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
233
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
234
WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
236
tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
237
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
238
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
239
WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
241
tmp = regGCVM_L2_CNTL3_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
243
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
244
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
247
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
248
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
251
WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
253
tmp = regGCVM_L2_CNTL4_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
254
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
255
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
256
WREG32_SOC15(GC, 0, regGCVM_L2_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
258
tmp = regGCVM_L2_CNTL5_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
259
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
260
WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
265
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
267
tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
268
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
269
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
270
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
272
WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
302
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
305
tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
306
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
307
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
309
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
311
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
313
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
315
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
317
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
319
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
321
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
323
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
327
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
331
i * hub->ctx_distance, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
344
hub->vm_cntx_cntl = tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
391
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
400
tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
401
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
402
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
404
WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
420
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
423
tmp = RREG32_SOC15(GC, 0, regCP_DEBUG);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
424
tmp = REG_SET_FIELD(tmp, CP_DEBUG, CPG_UTCL1_ERROR_HALT_DISABLE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
425
WREG32_SOC15(GC, 0, regCP_DEBUG, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
433
tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
434
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
436
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
438
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
440
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
442
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
445
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
447
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
449
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
451
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
453
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
455
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
458
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
460
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
463
WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
156
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
159
tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
161
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
162
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
163
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
165
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
167
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
169
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
171
WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
176
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
179
tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
180
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
181
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
183
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
185
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
186
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
187
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
188
WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
190
tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
191
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
192
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
193
WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
195
tmp = mmVM_L2_CNTL3_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
197
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
198
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
201
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
202
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
205
WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
207
tmp = mmVM_L2_CNTL4_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
209
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
210
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
212
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
213
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
215
WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
220
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
222
tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
223
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
224
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
226
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
228
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
230
WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
254
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
265
tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i * hub->ctx_distance);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
266
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
267
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
269
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
271
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
274
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
276
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
278
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
280
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
282
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
284
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
291
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
296
i * hub->ctx_distance, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
344
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
357
tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
358
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
359
tmp = REG_SET_FIELD(tmp,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
363
WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
379
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
381
tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
382
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
384
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
386
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
388
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
390
tmp = REG_SET_FIELD(tmp,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
394
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
396
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
398
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
400
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
402
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
404
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
407
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
409
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
412
WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
130
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
176
tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL2);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
177
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
179
WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
199
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
204
tmp = RREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
206
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
208
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
210
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
212
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
214
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
216
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
218
WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
225
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
230
tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
231
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
232
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
234
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
236
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
237
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
238
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
239
WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
241
tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_CNTL2);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
242
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
243
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
244
WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
246
tmp = regVM_L2_CNTL3_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
248
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
249
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
252
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
253
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
256
WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL3, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
258
tmp = regVM_L2_CNTL4_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
261
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
262
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
264
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
265
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
267
WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
274
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
278
tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
279
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
280
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
282
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
284
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
286
WREG32_SOC15(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
333
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
346
tmp = RREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
348
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
349
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
351
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
353
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
356
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
358
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
360
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
362
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
364
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
366
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
374
tmp = REG_SET_FIELD(
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
375
tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
381
i * hub->ctx_distance, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
449
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
460
tmp = RREG32_SOC15(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
461
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
462
tmp = REG_SET_FIELD(tmp,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
466
WREG32_SOC15_RLC(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
470
tmp = RREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
471
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
472
WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
490
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
494
tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
495
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
497
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
499
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
501
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
503
tmp = REG_SET_FIELD(tmp,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
507
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
509
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
511
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
513
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
515
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
517
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
520
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
522
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
525
WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
188
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
191
tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
193
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
194
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
195
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
197
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
199
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
202
WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
207
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
214
tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
215
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
216
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
217
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
220
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
222
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
223
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
224
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
225
WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
227
tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
228
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
229
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
230
WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
232
tmp = mmGCVM_L2_CNTL3_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
234
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
235
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
238
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
239
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
242
WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
244
tmp = mmGCVM_L2_CNTL4_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
245
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
246
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
247
WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
249
tmp = mmGCVM_L2_CNTL5_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
250
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
251
WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
256
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
258
tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
259
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
260
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
261
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
263
WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
287
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
290
tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i * hub->ctx_distance);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
291
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
292
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
294
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
296
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
298
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
300
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
302
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
304
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
306
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
308
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
312
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
316
i * hub->ctx_distance, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
329
hub->vm_cntx_cntl = tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
364
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
373
tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
374
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
375
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
377
WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
395
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
397
tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
398
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
400
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
402
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
404
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
406
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
409
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
411
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
413
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
415
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
417
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
419
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
422
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
424
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
427
WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
192
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
195
tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
197
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
198
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
199
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
201
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
203
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
206
WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
211
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
220
tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
221
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
222
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
223
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
226
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
228
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
229
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
230
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
231
WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
233
tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
234
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
235
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
236
WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
238
tmp = mmGCVM_L2_CNTL3_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
240
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
241
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
244
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
245
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
248
WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
250
tmp = mmGCVM_L2_CNTL4_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
251
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
252
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
253
WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
255
tmp = mmGCVM_L2_CNTL5_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
256
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
257
WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
262
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
264
tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
265
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
266
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
267
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
269
WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
299
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
302
tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i * hub->ctx_distance);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
303
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
304
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
306
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
308
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
310
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
312
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
314
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
316
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
318
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
320
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
324
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
328
i * hub->ctx_distance, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
341
hub->vm_cntx_cntl = tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
388
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
397
tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
398
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
399
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
401
WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
420
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
428
tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
429
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
431
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
433
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
435
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
437
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
440
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
442
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
444
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
446
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
448
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
450
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
453
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
455
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
458
WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
511
u32 tmp = 0, disabled_sa = 0;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
537
tmp |= 0x3 << (i * 2);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
540
disabled_sa = tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
625
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
642
tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
643
while ((tmp & (GRBM_STATUS2__EA_BUSY_MASK |
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
648
tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
186
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
189
tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
191
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
192
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
193
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
195
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
197
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
198
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
201
WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
206
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
215
tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
216
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
217
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
218
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
221
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
223
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
224
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
225
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
226
WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
228
tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
229
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
230
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
231
WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
233
tmp = regGCVM_L2_CNTL3_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
235
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
236
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
239
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
240
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
243
WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
245
tmp = regGCVM_L2_CNTL4_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
246
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
247
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
248
WREG32_SOC15(GC, 0, regGCVM_L2_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
250
tmp = regGCVM_L2_CNTL5_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
251
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
252
WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
257
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
259
tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
260
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
261
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
262
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
264
WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
294
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
297
tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i * hub->ctx_distance);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
298
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
299
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
301
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
303
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
305
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
307
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
309
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
311
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
313
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
315
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
319
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
323
i * hub->ctx_distance, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
336
hub->vm_cntx_cntl = tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
383
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
392
tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
393
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
394
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
396
WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
412
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
415
tmp = RREG32_SOC15(GC, 0, regCP_DEBUG);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
416
tmp = REG_SET_FIELD(tmp, CP_DEBUG, CPG_UTCL1_ERROR_HALT_DISABLE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
417
WREG32_SOC15(GC, 0, regCP_DEBUG, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
425
tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
426
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
428
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
430
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
432
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
434
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
437
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
439
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
441
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
443
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
445
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
447
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
450
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
452
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
455
WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
191
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
194
tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
196
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
197
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
198
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
200
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
202
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
203
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
206
WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
211
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
220
tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
221
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
222
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
223
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
226
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
228
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
229
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
230
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
231
WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
233
tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
234
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
235
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
236
WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
238
tmp = regGCVM_L2_CNTL3_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
240
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
241
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
244
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
245
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
248
WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
250
tmp = regGCVM_L2_CNTL4_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
251
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
252
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
253
WREG32_SOC15(GC, 0, regGCVM_L2_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
255
tmp = regGCVM_L2_CNTL5_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
256
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
257
WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
262
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
264
tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
265
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
266
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
267
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
269
WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
299
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
302
tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i * hub->ctx_distance);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
303
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
304
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
306
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
308
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
310
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
312
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
314
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
316
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
318
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
320
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
324
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
328
i * hub->ctx_distance, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
341
hub->vm_cntx_cntl = tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
376
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
385
tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
386
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
387
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
389
WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
405
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
413
tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
414
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
416
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
418
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
420
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
422
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
425
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
427
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
429
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
431
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
433
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
435
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
438
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
440
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
443
WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
261
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
295
tmp = RREG32_RLC_NO_KIQ(sem, hub_ip);
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
296
if (tmp & 0x1)
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
317
tmp = RREG32_RLC_NO_KIQ(ack, hub_ip);
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
318
tmp &= 1 << vmid;
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
319
if (tmp)
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
246
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
283
tmp = RREG32_RLC_NO_KIQ(sem, hub_ip);
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
284
if (tmp & 0x1)
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
297
tmp = RREG32_RLC_NO_KIQ(ack, hub_ip);
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
298
tmp &= 1 << vmid;
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
299
if (tmp)
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
231
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
252
tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
254
if (tmp & 0x1)
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
268
tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack +
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
270
tmp &= 1 << vmid;
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
271
if (tmp)
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
100
WREG32(mmBIF_FB_EN, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1011
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1012
tmp |= srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1013
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1014
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1015
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1019
tmp &= ~srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1020
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1021
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1037
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1047
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1048
tmp &= ~bits;
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1049
WREG32(mmVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1050
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1051
tmp &= ~bits;
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1052
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1055
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1056
tmp |= bits;
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1057
WREG32(mmVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1058
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1059
tmp |= bits;
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1060
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
243
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
246
tmp = RREG32(mmVGA_HDP_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
247
tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK;
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
248
WREG32(mmVGA_HDP_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
251
tmp = RREG32(mmVGA_RENDER_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
252
tmp &= VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK;
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
253
WREG32(mmVGA_RENDER_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
273
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
277
tmp = RREG32(mmMC_ARB_RAMCFG);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
278
if (tmp & (1 << 11))
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
280
else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK)
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
285
tmp = RREG32(mmMC_SHARED_CHMAP);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
286
switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
397
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
399
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
400
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
402
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
404
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
406
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
408
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
410
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
412
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
423
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
430
tmp = RREG32(mmVM_PRT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
431
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
434
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
437
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
440
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
443
WREG32(mmVM_PRT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
824
u32 tmp = RREG32(mmMC_SEQ_MISC0);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
826
tmp &= MC_SEQ_MISC0__MT__MASK;
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
827
adev->gmc.vram_type = gmc_v6_0_convert_vram_type(tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
880
u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
882
tmp <<= 22;
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
883
adev->vm_manager.vram_base_offset = tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
91
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
94
tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
95
tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
96
WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
964
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
966
if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
98
tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
99
tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
992
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
994
if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
998
if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1059
u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1061
tmp <<= 22;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1062
adev->vm_manager.vram_base_offset = tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
114
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1150
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1152
if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
117
tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1177
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1179
if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
118
tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1183
if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
119
WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1195
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1196
tmp |= srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1197
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1198
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1199
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1203
tmp &= ~srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1204
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1205
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
121
tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
122
tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1222
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
123
WREG32(mmBIF_FB_EN, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1233
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1234
tmp &= ~bits;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1235
WREG32(mmVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1237
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1238
tmp &= ~bits;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1239
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1243
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1244
tmp |= bits;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1245
WREG32(mmVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1247
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1248
tmp |= bits;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1249
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
261
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
283
tmp = RREG32(mmVGA_HDP_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
284
tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
285
WREG32(mmVGA_HDP_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
288
tmp = RREG32(mmVGA_RENDER_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
289
tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
290
WREG32(mmVGA_RENDER_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
307
tmp = RREG32(mmHDP_MISC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
308
tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
309
WREG32(mmHDP_MISC_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
311
tmp = RREG32(mmHDP_HOST_PATH_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
312
WREG32(mmHDP_HOST_PATH_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
330
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
334
tmp = RREG32(mmMC_ARB_RAMCFG);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
335
if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE))
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
340
tmp = RREG32(mmMC_SHARED_CHMAP);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
341
switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
442
u32 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
444
if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
445
(tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid)
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
525
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
527
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
528
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
530
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
532
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
534
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
536
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
538
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
540
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
551
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
558
tmp = RREG32(mmVM_PRT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
559
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
561
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
563
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
565
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
567
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
569
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
571
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
573
WREG32(mmVM_PRT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
615
u32 tmp, field;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
626
tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
627
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
628
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
629
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
630
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
631
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
632
WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
634
tmp = RREG32(mmVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
635
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
636
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
637
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
638
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
639
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
640
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
641
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
642
WREG32(mmVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
643
tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
644
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
645
WREG32(mmVM_L2_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
648
tmp = RREG32(mmVM_L2_CNTL3);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
649
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
650
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
651
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
652
WREG32(mmVM_L2_CNTL3, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
660
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
661
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
662
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
663
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
664
WREG32(mmVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
690
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
691
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
692
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
693
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
695
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
702
tmp = RREG32(mmCHUB_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
703
tmp &= ~BYPASS_VM;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
704
WREG32(mmCHUB_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
740
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
746
tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
747
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
748
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
749
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
750
WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
752
tmp = RREG32(mmVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
753
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
754
WREG32(mmVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
994
u32 tmp = RREG32(mmMC_SEQ_MISC0);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
996
tmp &= MC_SEQ_MISC0__MT__MASK;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
997
adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1104
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1108
tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1110
tmp = RREG32(mmMC_SEQ_MISC0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1111
tmp &= MC_SEQ_MISC0__MT__MASK;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1112
adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1174
u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1176
tmp <<= 22;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1177
adev->vm_manager.vram_base_offset = tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1273
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1275
if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1285
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1290
tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1296
if (!tmp)
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1308
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1310
if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1314
if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1355
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1357
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1358
tmp |= srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1359
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1360
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1361
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1365
tmp &= ~srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1366
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1367
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1392
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1404
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1405
tmp &= ~bits;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1406
WREG32(mmVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1408
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1409
tmp &= ~bits;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1410
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1414
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1415
tmp |= bits;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1416
WREG32(mmVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1418
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1419
tmp |= bits;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1420
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
196
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
199
tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
200
tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
201
WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
203
tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
204
tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
205
WREG32(mmBIF_FB_EN, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
436
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
458
tmp = RREG32(mmVGA_HDP_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
459
tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
460
WREG32(mmVGA_HDP_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
463
tmp = RREG32(mmVGA_RENDER_CONTROL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
464
tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
465
WREG32(mmVGA_RENDER_CONTROL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
476
tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
477
tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
478
WREG32(mmMC_VM_FB_LOCATION, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
493
tmp = RREG32(mmHDP_MISC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
494
tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
495
WREG32(mmHDP_MISC_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
497
tmp = RREG32(mmHDP_HOST_PATH_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
498
WREG32(mmHDP_HOST_PATH_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
513
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
520
tmp = RREG32(mmMC_ARB_RAMCFG);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
521
if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE))
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
526
tmp = RREG32(mmMC_SHARED_CHMAP);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
527
switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
560
tmp = RREG32(mmCONFIG_MEMSIZE);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
562
if (tmp & 0xffff0000) {
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
563
DRM_INFO("Probable bad vram size: 0x%08x\n", tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
564
if (tmp & 0xffff)
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
565
tmp &= 0xffff;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
567
adev->gmc.mc_vram_size = tmp * 1024ULL * 1024ULL;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
633
u32 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
635
if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
636
(tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid)
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
740
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
742
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
743
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
745
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
747
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
749
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
751
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
753
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
755
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
757
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
768
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
775
tmp = RREG32(mmVM_PRT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
776
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
778
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
780
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
782
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
784
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
786
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
788
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
790
WREG32(mmVM_PRT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
832
u32 tmp, field;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
843
tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
844
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
845
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
846
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
847
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
848
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
849
WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
851
tmp = RREG32(mmVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
852
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
853
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
854
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
855
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
856
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
857
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
858
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
859
WREG32(mmVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
860
tmp = RREG32(mmVM_L2_CNTL2);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
861
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
862
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
863
WREG32(mmVM_L2_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
866
tmp = RREG32(mmVM_L2_CNTL3);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
867
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
868
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
869
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
870
WREG32(mmVM_L2_CNTL3, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
872
tmp = RREG32(mmVM_L2_CNTL4);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
873
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
874
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
875
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
876
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
877
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
878
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
879
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
880
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
881
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
882
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
883
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
884
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
885
WREG32(mmVM_L2_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
893
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
894
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
895
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
896
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
897
WREG32(mmVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
923
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
924
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
925
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
926
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
927
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
928
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
929
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
930
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
931
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
932
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
933
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
935
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
974
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
980
tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
981
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
982
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
983
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
984
WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
986
tmp = RREG32(mmVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
987
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
988
WREG32(mmVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
417
u32 bits, i, tmp, reg;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
431
tmp = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
432
tmp &= ~bits;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
433
WREG32(reg, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
437
tmp = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
438
tmp &= ~bits;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
439
WREG32(reg, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
445
tmp = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
446
tmp |= bits;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
447
WREG32(reg, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
451
tmp = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
452
tmp |= bits;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
453
WREG32(reg, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
469
u32 tmp, reg, bits, i, j;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
495
tmp = RREG32_SOC15_IP(MMHUB, reg);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
497
tmp = RREG32_XCC(reg, j);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
499
tmp &= ~bits;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
502
WREG32_SOC15_IP(MMHUB, reg, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
504
WREG32_XCC(reg, tmp, j);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
523
tmp = RREG32_SOC15_IP(MMHUB, reg);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
525
tmp = RREG32_XCC(reg, j);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
527
tmp |= bits;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
530
WREG32_SOC15_IP(MMHUB, reg, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
532
WREG32_XCC(reg, tmp, j);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
844
u32 j, inv_req, tmp, sem, req, ack, inst;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
889
tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, GET_INST(GC, inst));
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
891
tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, GET_INST(GC, inst));
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
892
if (tmp & 0x1)
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
917
tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, GET_INST(GC, inst));
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
919
tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, GET_INST(GC, inst));
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
920
if (tmp & (1 << vmid))
sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c
177
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c
180
tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c
181
if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c
190
tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);
sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c
191
if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK)
sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c
193
else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK)
sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c
195
else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK)
sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c
201
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c
203
tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL);
sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c
204
tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK;
sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c
205
WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c
173
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c
176
tmp = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);
sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c
177
if (!(tmp & (HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |
sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c
186
tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c
187
if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK)
sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c
189
else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK)
sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c
191
else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK)
sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c
128
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c
131
tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c
132
if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK)
sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c
134
else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK)
sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c
136
else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK)
sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c
116
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c
119
tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c
120
if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK)
sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c
122
else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK)
sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c
124
else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK)
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
193
u32 wptr, tmp;
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
214
tmp = RREG32(mmIH_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
215
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
216
WREG32(mmIH_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
221
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
222
WREG32(mmIH_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
341
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
343
if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
352
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
357
tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
358
if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
369
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
371
if (tmp & SRBM_STATUS__IH_BUSY_MASK)
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
376
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
377
tmp |= srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
378
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
379
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
380
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
384
tmp &= ~srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
385
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
386
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
132
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
136
tmp = RREG32(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
137
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
143
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
145
if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
148
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
152
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
154
if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
157
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
163
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
168
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
171
if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
174
WREG32(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
269
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
277
tmp = RREG32(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
278
tmp = ih_v6_0_rb_cntl(ih, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
280
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
282
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
283
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
287
if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
292
WREG32(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
325
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
359
tmp = RREG32_SOC15(OSSSYS, 0, regIH_STORM_CLIENT_LIST_CNTL);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
360
tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
362
WREG32_SOC15(OSSSYS, 0, regIH_STORM_CLIENT_LIST_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
364
tmp = RREG32_SOC15(OSSSYS, 0, regIH_INT_FLOOD_CNTL);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
365
tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
366
WREG32_SOC15(OSSSYS, 0, regIH_INT_FLOOD_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
373
tmp = RREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
374
tmp = REG_SET_FIELD(tmp, IH_MSI_STORM_CTRL,
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
376
WREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
380
tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
381
tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
382
WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
384
tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
385
tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 0xa);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
386
tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 0x0);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
387
tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA,
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
390
WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
438
u32 wptr, tmp;
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
459
tmp = (wptr + 32) & ih->ptr_mask;
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
462
wptr, ih->rptr, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
463
ih->rptr = tmp;
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
465
tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
466
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
467
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
472
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
473
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
132
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
136
tmp = RREG32(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
137
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
140
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
143
if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
146
WREG32(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
241
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
249
tmp = RREG32(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
250
tmp = ih_v6_1_rb_cntl(ih, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
252
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
254
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
255
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
259
if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
264
WREG32(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
297
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
330
tmp = RREG32_SOC15(OSSSYS, 0, regIH_STORM_CLIENT_LIST_CNTL);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
331
tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
333
WREG32_SOC15(OSSSYS, 0, regIH_STORM_CLIENT_LIST_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
335
tmp = RREG32_SOC15(OSSSYS, 0, regIH_INT_FLOOD_CNTL);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
336
tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
337
WREG32_SOC15(OSSSYS, 0, regIH_INT_FLOOD_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
344
tmp = RREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
345
tmp = REG_SET_FIELD(tmp, IH_MSI_STORM_CTRL,
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
347
WREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
351
tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
352
tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
353
WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
355
tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
356
tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 0xa);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
357
tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 0x0);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
358
tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA,
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
361
WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
409
u32 wptr, tmp;
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
427
tmp = (wptr + 32) & ih->ptr_mask;
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
430
wptr, ih->rptr, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
431
ih->rptr = tmp;
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
433
tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
434
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
435
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
440
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
441
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
132
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
136
tmp = RREG32(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
137
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
140
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
143
if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
146
WREG32(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
241
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
249
tmp = RREG32(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
250
tmp = ih_v7_0_rb_cntl(ih, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
252
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
254
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
255
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
259
if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
264
WREG32(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
297
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
330
tmp = RREG32_SOC15(OSSSYS, 0, regIH_STORM_CLIENT_LIST_CNTL);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
331
tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
333
WREG32_SOC15(OSSSYS, 0, regIH_STORM_CLIENT_LIST_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
335
tmp = RREG32_SOC15(OSSSYS, 0, regIH_INT_FLOOD_CNTL);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
336
tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
337
WREG32_SOC15(OSSSYS, 0, regIH_INT_FLOOD_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
344
tmp = RREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
345
tmp = REG_SET_FIELD(tmp, IH_MSI_STORM_CTRL,
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
347
WREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
351
tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
352
tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
353
WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
355
tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
356
tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 0xa);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
357
tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 0x0);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
358
tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA,
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
361
WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
409
u32 wptr, tmp;
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
427
tmp = (wptr + 32) & ih->ptr_mask;
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
430
wptr, ih->rptr, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
431
ih->rptr = tmp;
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
433
tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
434
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
435
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
440
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
441
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
438
uint32_t tmp, timeout;
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
509
tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
510
tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
512
tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
513
WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
527
tmp = 0;
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
538
tmp = tmp + 10;
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
539
if (tmp >= timeout) {
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
543
tmp, expected, resp);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
256
uint32_t tmp, timeout;
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
291
tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
292
MMSCH_V4_0_INSERT_DIRECT_WT(tmp, lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
293
tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
294
MMSCH_V4_0_INSERT_DIRECT_WT(tmp, upper_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
295
tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_SIZE);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
296
MMSCH_V4_0_INSERT_DIRECT_WT(tmp, ring->ring_size / 4);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
322
tmp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
323
tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
324
tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
325
WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID, tmp);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
334
tmp = 0;
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
346
tmp = tmp + 10;
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
347
if (tmp >= timeout) {
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
351
tmp, expected, resp);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
454
uint32_t tmp, timeout;
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
489
tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
490
MMSCH_V5_0_INSERT_DIRECT_WT(tmp, lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
491
tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
492
MMSCH_V5_0_INSERT_DIRECT_WT(tmp, upper_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
493
tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JRBC_RB_SIZE);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
494
MMSCH_V5_0_INSERT_DIRECT_WT(tmp, ring->ring_size / 4);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
520
tmp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
521
tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
522
tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
523
WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID, tmp);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
532
tmp = 0;
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
544
tmp = tmp + 10;
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
545
if (tmp >= timeout) {
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
549
tmp, expected, resp);
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
107
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
109
tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_MEM_POWER_CTRL);
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
110
tmp = REG_SET_FIELD(tmp, LSDMA_MEM_POWER_CTRL, MEM_POWER_CTRL_EN, 0);
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
111
WREG32_SOC15(LSDMA, 0, regLSDMA_MEM_POWER_CTRL, tmp);
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
113
tmp = REG_SET_FIELD(tmp, LSDMA_MEM_POWER_CTRL, MEM_POWER_CTRL_EN, enable);
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
114
WREG32_SOC15(LSDMA, 0, regLSDMA_MEM_POWER_CTRL, tmp);
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
45
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
55
tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND);
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
56
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size);
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
57
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0);
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
58
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0);
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
59
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_ADDR_INC, 0);
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
60
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_ADDR_INC, 0);
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
61
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, OVERLAP_DISABLE, 0);
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
62
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 0);
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
63
WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND, tmp);
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
78
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
87
tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND);
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
88
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size);
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
89
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0);
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
90
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0);
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
91
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_ADDR_INC, 0);
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
92
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_ADDR_INC, 0);
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
93
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, OVERLAP_DISABLE, 0);
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
94
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 1);
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
95
WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND, tmp);
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
107
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
109
tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_MEM_POWER_CTRL);
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
110
tmp = REG_SET_FIELD(tmp, LSDMA_MEM_POWER_CTRL, MEM_POWER_CTRL_EN, 0);
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
111
WREG32_SOC15(LSDMA, 0, regLSDMA_MEM_POWER_CTRL, tmp);
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
113
tmp = REG_SET_FIELD(tmp, LSDMA_MEM_POWER_CTRL, MEM_POWER_CTRL_EN, enable);
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
114
WREG32_SOC15(LSDMA, 0, regLSDMA_MEM_POWER_CTRL, tmp);
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
45
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
55
tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND);
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
56
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size);
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
57
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0);
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
58
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0);
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
59
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_ADDR_INC, 0);
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
60
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_ADDR_INC, 0);
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
61
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, OVERLAP_DISABLE, 0);
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
62
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 0);
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
63
WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND, tmp);
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
78
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
87
tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND);
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
88
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size);
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
89
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0);
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
90
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0);
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
91
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_ADDR_INC, 0);
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
92
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_ADDR_INC, 0);
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
93
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, OVERLAP_DISABLE, 0);
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
94
tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 1);
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
95
WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND, tmp);
sys/dev/pci/drm/amd/amdgpu/mes_userqueue.c
208
struct amdgpu_userq_mgr *uqm, *tmp;
sys/dev/pci/drm/amd/amdgpu/mes_userqueue.c
230
list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) {
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1108
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1123
tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1124
tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1129
mqd->cp_hqd_eop_control = tmp;
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1142
tmp = regCP_MQD_CONTROL_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1143
tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1144
mqd->cp_mqd_control = tmp;
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1163
tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1164
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1166
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1168
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1169
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1170
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1171
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1172
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1173
mqd->cp_hqd_pq_control = tmp;
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1176
tmp = 0;
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1178
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1180
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1182
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1184
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1187
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1189
mqd->cp_hqd_pq_doorbell_control = tmp;
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1195
tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1196
tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE,
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1198
mqd->cp_hqd_persistent_state = tmp;
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1544
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1548
tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1549
tmp &= 0xffffff00;
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1550
tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1551
WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80);
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1556
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1559
tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1560
tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK;
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1561
WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1270
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1283
tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1284
tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1289
mqd->cp_hqd_eop_control = tmp;
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1302
tmp = regCP_MQD_CONTROL_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1303
tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1304
mqd->cp_mqd_control = tmp;
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1323
tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1324
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1326
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1328
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1329
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1330
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1331
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1332
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1333
mqd->cp_hqd_pq_control = tmp;
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1336
tmp = 0;
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1338
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1340
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1342
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1344
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1347
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1350
mqd->cp_hqd_pq_doorbell_control = tmp;
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1356
tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1357
tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE,
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1359
mqd->cp_hqd_persistent_state = tmp;
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1726
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1730
tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1731
tmp &= 0xffffff00;
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1732
tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1733
WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
383
u32 i, tmp, val;
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
387
tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
388
tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, CLIENTID, 4);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
389
WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
393
if (val == tmp)
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
396
tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX,
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
400
if (val != tmp)
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
131
tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
132
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
134
WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
139
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
142
tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
144
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
145
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
146
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
148
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
150
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
152
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
154
WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
159
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
165
tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
166
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
167
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
169
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
171
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
172
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
173
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
174
WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
176
tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
177
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
178
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
179
WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
181
tmp = mmVM_L2_CNTL3_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
183
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
184
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
187
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
188
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
191
WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
193
tmp = mmVM_L2_CNTL4_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
194
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
195
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
196
WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
201
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
203
tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
204
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
205
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
206
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
208
WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
235
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
262
tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
263
tmp |= 1 << CONTEXT0_CNTL_ENABLE_OFFSET;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
264
tmp &= ~(3 << CONTEXT0_CNTL_PAGE_TABLE_DEPTH_OFFSET);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
265
WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
268
tmp = 0xfffe;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
269
WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXTS_DISABLE, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
272
tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CNTL4);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
273
tmp |= 1 << VMC_TAP_PDE_REQUEST_SNOOP_OFFSET;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
274
tmp |= 1 << VMC_TAP_PTE_REQUEST_SNOOP_OFFSET;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
275
WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
282
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
293
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i * hub->ctx_distance);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
294
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
295
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
297
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
299
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
302
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
304
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
306
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
308
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
310
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
312
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
316
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
320
i * hub->ctx_distance, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
393
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
402
tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
403
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
404
tmp = REG_SET_FIELD(tmp,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
408
WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
412
tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
413
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
414
WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
427
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
432
tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
433
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
435
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
437
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
439
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
441
tmp = REG_SET_FIELD(tmp,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
445
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
447
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
449
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
451
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
453
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
455
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
458
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
460
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
464
WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
88
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
107
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
149
tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL2);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
150
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
152
WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
157
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
160
tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
162
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
163
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
164
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
166
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
168
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
170
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
172
WREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
178
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
184
tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
186
tmp |= (1 << 15); /* SDMA client is BIT15 */
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
188
regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE, i * distance, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
190
tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
192
tmp |= (1 << 15);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
194
regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE, i * distance, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
201
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
207
tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
208
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
209
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
211
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
213
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
214
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
215
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
216
WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
218
tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL2);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
219
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
220
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
221
WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
223
tmp = regVM_L2_CNTL3_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
225
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
226
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
229
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
230
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
233
WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL3, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
235
tmp = regVM_L2_CNTL4_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
237
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
239
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
242
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
244
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
247
WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
252
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
254
tmp = RREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
255
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
256
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
258
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
260
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
262
WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
290
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
301
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL, i * hub->ctx_distance);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
302
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
303
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
305
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
307
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
310
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
312
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
314
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
316
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
318
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
320
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
326
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
330
i * hub->ctx_distance, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
377
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
386
tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
387
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
388
tmp = REG_SET_FIELD(tmp,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
392
WREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
396
tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
397
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
398
WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
411
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
416
tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
417
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
419
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
421
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
423
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
425
tmp = REG_SET_FIELD(tmp,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
429
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
431
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
433
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
435
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
437
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
439
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
442
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
444
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
448
WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
132
uint32_t tmp, inst_mask;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
186
tmp = RREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL2);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
187
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
189
WREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
195
uint32_t tmp, inst_mask;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
199
tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
201
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
203
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
205
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
207
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
209
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
211
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
213
psp_reg_program_no_ring(&adev->psp, tmp, PSP_REG_MMHUB_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
217
tmp = RREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
219
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
221
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
223
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
225
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
227
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
229
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
231
WREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
239
uint32_t tmp, inst_mask;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
250
tmp = RREG32_SOC15_OFFSET(MMHUB, i,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
252
tmp |= (1 << 15); /* SDMA client is BIT15 */
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
254
regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE, j * distance, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
256
tmp = RREG32_SOC15_OFFSET(MMHUB, i,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
258
tmp |= (1 << 15);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
260
regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE, j * distance, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
267
uint32_t tmp, inst_mask;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
276
tmp = RREG32_SOC15(MMHUB, i, regVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
277
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
278
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
281
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
283
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
285
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
287
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
289
WREG32_SOC15(MMHUB, i, regVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
291
tmp = RREG32_SOC15(MMHUB, i, regVM_L2_CNTL2);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
292
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
294
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
295
WREG32_SOC15(MMHUB, i, regVM_L2_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
297
tmp = regVM_L2_CNTL3_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
299
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
300
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
303
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
304
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
307
WREG32_SOC15(MMHUB, i, regVM_L2_CNTL3, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
309
tmp = regVM_L2_CNTL4_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
312
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
314
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
317
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
319
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
322
WREG32_SOC15(MMHUB, i, regVM_L2_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
328
uint32_t tmp, inst_mask;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
333
tmp = RREG32_SOC15(MMHUB, i, regVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
334
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
335
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
337
tmp = REG_SET_FIELD(tmp,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
340
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
342
WREG32_SOC15(MMHUB, i, regVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
381
uint32_t tmp, inst_mask;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
395
tmp = RREG32_SOC15_OFFSET(MMHUB, j, regVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
397
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
399
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
401
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
403
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
405
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
407
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
409
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
411
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
413
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
415
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
422
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
425
i * hub->ctx_distance, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
482
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
486
tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
487
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
488
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
490
psp_reg_program_no_ring(&adev->psp, tmp, PSP_REG_MMHUB_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
494
tmp = RREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
495
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
497
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
499
WREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
507
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
519
tmp = RREG32_SOC15(MMHUB, j, regVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
520
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
522
WREG32_SOC15(MMHUB, j, regVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
538
u32 tmp, inst_mask;
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
546
tmp = RREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
547
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
549
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
551
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
553
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
555
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
558
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
560
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
562
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
564
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
566
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
568
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
571
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
573
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
577
WREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
224
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
252
tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
253
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
255
WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
260
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
263
tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
265
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
266
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
267
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
269
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
271
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
274
WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
279
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
288
tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
289
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
290
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
291
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
294
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
296
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
297
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
298
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
299
WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
301
tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
302
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
303
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
304
WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
306
tmp = mmMMVM_L2_CNTL3_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
308
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
309
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
312
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
313
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
316
WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
318
tmp = mmMMVM_L2_CNTL4_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
319
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
320
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
321
WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
323
tmp = mmMMVM_L2_CNTL5_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
324
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
325
WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL5, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
330
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
332
tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
333
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
334
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
335
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
337
WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
370
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
373
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i * hub->ctx_distance);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
374
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
375
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
377
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
379
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
382
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
384
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
386
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
388
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
390
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
392
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
396
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
400
i * hub->ctx_distance, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
413
hub->vm_cntx_cntl = tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
448
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
457
tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
458
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
459
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
461
WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
464
tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
465
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
466
WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
478
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
486
tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
487
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
489
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
491
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
493
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
495
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
498
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
500
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
502
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
504
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
506
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
508
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
511
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
513
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
516
WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
154
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
180
tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
181
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
183
WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
188
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
191
tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
193
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
194
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
195
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
197
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
199
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
202
WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
207
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
210
tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
211
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
212
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
213
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
216
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
218
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
219
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
220
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
221
WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
223
tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
224
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
225
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
226
WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
228
tmp = mmMMVM_L2_CNTL3_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
230
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
231
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
234
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
235
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
238
WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
240
tmp = mmMMVM_L2_CNTL4_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
241
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
242
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
243
WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
245
tmp = mmMMVM_L2_CNTL5_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
246
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
247
WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL5, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
252
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
254
tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
255
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
256
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
257
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
259
WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
286
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
289
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i * hub->ctx_distance);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
290
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
291
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
293
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
295
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
298
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
300
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
302
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
304
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
306
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
308
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
312
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
316
i * hub->ctx_distance, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
329
hub->vm_cntx_cntl = tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
378
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
387
tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
388
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
389
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
391
WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
394
tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
395
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
396
WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
409
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
411
tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
412
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
414
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
416
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
418
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
420
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
423
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
425
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
427
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
429
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
431
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
433
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
436
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
438
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
441
WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
171
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
205
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
206
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
208
WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
213
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
216
tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
218
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
219
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
220
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
222
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
224
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
225
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
228
WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
233
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
242
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
243
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
244
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
245
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
248
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
250
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
251
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
252
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
253
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
255
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
256
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
257
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
258
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
260
tmp = regMMVM_L2_CNTL3_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
262
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
263
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
266
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
267
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
270
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
272
tmp = regMMVM_L2_CNTL4_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
273
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
274
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
275
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
277
tmp = regMMVM_L2_CNTL5_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
278
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
279
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
284
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
286
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
287
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
288
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
289
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
291
WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
324
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
327
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
328
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
329
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
331
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
333
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
336
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
338
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
340
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
342
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
344
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
346
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
350
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
354
i * hub->ctx_distance, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
367
hub->vm_cntx_cntl = tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
402
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
411
tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
412
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
413
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
415
WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
418
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
419
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
420
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
432
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
440
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
441
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
443
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
445
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
447
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
449
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
452
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
454
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
456
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
458
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
460
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
462
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
465
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
467
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
470
WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
180
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
211
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
212
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
214
WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
219
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
222
tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
224
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
225
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
226
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
228
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
230
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
231
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
234
WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
239
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
242
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
243
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
244
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
245
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
248
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
250
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
251
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
252
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
253
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
255
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
256
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
257
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
258
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
260
tmp = regMMVM_L2_CNTL3_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
262
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
263
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
266
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
267
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
270
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
272
tmp = regMMVM_L2_CNTL4_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
273
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
274
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
275
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
277
tmp = regMMVM_L2_CNTL5_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
278
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
279
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
284
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
286
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
287
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
288
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
289
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
291
WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
318
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
321
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
322
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
323
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
325
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
327
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
330
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
332
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
334
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
336
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
338
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
340
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
344
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
348
i * hub->ctx_distance, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
361
hub->vm_cntx_cntl = tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
396
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
405
tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
406
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
407
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
409
WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
412
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
413
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
414
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
427
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
429
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
430
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
432
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
434
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
436
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
438
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
441
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
443
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
445
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
447
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
449
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
451
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
454
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
456
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
459
WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
164
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
197
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
198
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
200
WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
205
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
208
tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
210
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
211
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
212
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
214
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
216
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
217
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
220
WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
225
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
234
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
235
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
236
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
237
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
240
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
242
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
243
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
244
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
245
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
247
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
248
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
249
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
250
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
252
tmp = regMMVM_L2_CNTL3_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
254
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
255
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
258
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
259
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
262
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
264
tmp = regMMVM_L2_CNTL4_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
265
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
266
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
267
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
269
tmp = regMMVM_L2_CNTL5_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
270
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
271
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
276
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
278
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
279
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
280
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
281
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
283
WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
316
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
319
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
320
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
321
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
323
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
325
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
328
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
330
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
332
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
334
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
336
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
338
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
342
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
346
i * hub->ctx_distance, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
359
hub->vm_cntx_cntl = tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
394
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
403
tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
404
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
405
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
407
WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
410
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
411
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
412
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
424
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
432
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
433
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
435
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
437
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
439
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
441
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
444
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
446
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
448
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
450
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
452
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
454
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
457
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
459
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
462
WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
272
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
303
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
304
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
306
WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
311
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
314
tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
316
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
317
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
318
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
320
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
322
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
323
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
326
WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
331
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
334
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
335
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
336
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
337
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
340
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
342
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
343
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
344
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
345
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
347
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
348
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
349
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
350
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
352
tmp = regMMVM_L2_CNTL3_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
354
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
355
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
358
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
359
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
362
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
364
tmp = regMMVM_L2_CNTL4_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
365
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
366
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
367
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
369
tmp = regMMVM_L2_CNTL5_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
370
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
371
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
376
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
378
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
379
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
380
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
381
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
384
WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
411
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
414
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
415
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
416
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
418
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
420
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
423
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
425
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
427
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
429
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
431
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
433
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
437
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
441
i * hub->ctx_distance, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
454
hub->vm_cntx_cntl = tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
473
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
491
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
492
tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
493
tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
494
WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
497
tmp = 0xfffe;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
498
WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXTS_DISABLE, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
501
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CNTL4);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
502
tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
503
tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
504
WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
538
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
547
tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
548
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
549
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
551
WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
554
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
555
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
556
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
569
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
571
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
572
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
574
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
576
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
578
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
580
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
583
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
585
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
587
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
589
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
591
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
593
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
596
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
598
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
601
WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
163
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
198
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
199
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
201
WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
206
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
209
tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
211
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
212
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
213
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
215
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
217
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
218
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
221
WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
226
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
235
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
236
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
237
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
238
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
241
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
243
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
244
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
245
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
246
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
248
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
249
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
250
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
251
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
253
tmp = regMMVM_L2_CNTL3_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
255
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
256
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
259
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
260
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
263
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
265
tmp = regMMVM_L2_CNTL4_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
266
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
267
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
268
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
270
tmp = regMMVM_L2_CNTL5_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
271
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
272
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
277
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
279
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
280
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
281
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
282
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
284
WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
317
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
320
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
321
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
322
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
324
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
326
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
329
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
331
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
333
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
335
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
337
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
339
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
343
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
347
i * hub->ctx_distance, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
360
hub->vm_cntx_cntl = tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
395
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
404
tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
405
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
406
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
408
WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
411
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
412
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
413
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
426
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
434
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
435
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
437
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
439
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
441
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
443
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
446
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
448
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
450
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
452
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
454
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
456
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
459
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
461
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
464
WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
114
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
163
tmp = RREG32_SOC15_OFFSET(
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
166
tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
171
tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
177
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
180
tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
184
tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
186
tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
188
tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
190
tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
192
tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
194
tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
198
hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
204
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
212
tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
215
tmp |= (1 << 15); /* SDMA client is BIT15 */
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
218
huboffset + i * distance, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
220
tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
223
tmp |= (1 << 15);
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
226
huboffset + i * distance, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
233
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
236
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
238
tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
240
tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
243
tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
245
tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
247
tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
249
tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
252
hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
254
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
256
tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
258
tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
261
hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
263
tmp = mmVML2PF0_VM_L2_CNTL3_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
265
tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 12);
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
266
tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
269
tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 9);
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
270
tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
274
hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
276
tmp = mmVML2PF0_VM_L2_CNTL4_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
277
tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
279
tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
282
hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
288
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
290
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
292
tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
293
tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
294
tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
297
hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
329
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
340
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
342
tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
344
tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
347
tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
349
tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
352
tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
354
tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
356
tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
358
tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
360
tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
362
tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
366
tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
371
i * hub->ctx_distance, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
439
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
451
tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
454
tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
456
tmp = REG_SET_FIELD(tmp,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
461
j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
464
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
466
tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
469
j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
483
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
487
tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
490
tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
493
tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
496
tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
499
tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
502
tmp = REG_SET_FIELD(tmp,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
506
tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
509
tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
512
tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
515
tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
518
tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
521
tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
525
tmp = REG_SET_FIELD(tmp,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
528
tmp = REG_SET_FIELD(tmp,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
535
i * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
243
u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
245
tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_MAILBOX_INT_CNTL, ACK_INT_EN,
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
247
WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
331
u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
333
tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_MAILBOX_INT_CNTL, VALID_INT_EN,
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
335
WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);
sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c
304
u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c
307
tmp |= 2;
sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c
309
tmp &= ~2;
sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c
311
WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c
398
u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c
401
tmp |= 1;
sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c
403
tmp &= ~1;
sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c
405
WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
504
u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
506
tmp = REG_SET_FIELD(tmp, MAILBOX_INT_CNTL, ACK_INT_EN,
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
508
WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
537
u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
539
tmp = REG_SET_FIELD(tmp, MAILBOX_INT_CNTL, VALID_INT_EN,
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
541
WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
157
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
161
tmp = RREG32(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
162
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
163
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
166
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
169
if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
172
WREG32(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
267
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
275
tmp = RREG32(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
276
tmp = navi10_ih_rb_cntl(ih, tmp);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
278
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
280
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
283
if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
288
WREG32(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
409
u32 wptr, tmp;
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
436
tmp = (wptr + 32) & ih->ptr_mask;
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
438
amdgpu_ih_ring_name(adev, ih), wptr, ih->rptr, tmp);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
439
ih->rptr = tmp;
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
441
tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
442
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
443
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
448
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
449
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c
166
u32 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c
169
tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c
171
REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c
173
REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c
182
WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c
43
u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c
45
tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c
46
tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c
48
return tmp;
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
165
u32 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
168
tmp = REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
170
REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
172
REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
182
tmp);
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
76
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
86
tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
87
tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
88
tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
90
return tmp;
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
161
u32 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
164
tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
166
REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
168
REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
178
tmp);
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
41
u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
43
tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
44
tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
46
return tmp;
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
115
u32 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
118
tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
119
REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
120
REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
128
WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
65
u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
67
tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
68
tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
70
return tmp;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
45
u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
47
tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
48
tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
50
return tmp;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
152
u32 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
155
tmp = REG_SET_FIELD(tmp, BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
157
REG_SET_FIELD(tmp, BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
159
REG_SET_FIELD(tmp, BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
170
WREG32_SOC15(NBIO, 0, regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
40
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
42
tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
43
tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
44
tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
46
return tmp;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
165
u32 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
168
tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
170
REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
172
REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
184
tmp);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
59
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
65
tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
68
tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
72
tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
73
tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
75
return tmp;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
111
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
114
tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0_ALDE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
116
tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
118
tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
119
tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
121
return tmp;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
217
u32 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
220
tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
221
REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
222
REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
230
WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
122
u32 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
125
tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
127
REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
129
REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
141
tmp);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
40
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
42
tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
43
tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
44
tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
46
return tmp;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
244
u32 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
247
tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
249
REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
251
REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
260
WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
395
u32 tmp, px;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
397
tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
398
px = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_STATUS,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
406
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
408
tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
409
tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
413
return (tmp == 0x8);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
418
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
420
tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
421
tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS, NPS_MODE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
428
return ffs(tmp);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
44
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
46
tmp = IP_VERSION_SUBREV(amdgpu_ip_version_full(adev, NBIO_HWIP, 0));
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
48
if (tmp || amdgpu_sriov_vf(adev))
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
49
return tmp;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
52
tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
53
tmp = REG_GET_FIELD(tmp, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
56
return tmp;
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
158
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
161
tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
162
tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
163
tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
166
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
174
tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
175
tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
178
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
537
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
545
tmp = 0xCAFEDEAD;
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
546
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
561
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
562
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
590
u32 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
599
tmp = 0xCAFEDEAD;
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
600
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
629
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
630
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
917
u32 tmp = RREG32(mmSRBM_STATUS2);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
919
if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
929
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
933
tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
936
if (!tmp)
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
947
u32 tmp = RREG32(mmSRBM_STATUS2);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
949
if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
951
tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
952
tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
953
WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
956
if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
958
tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
959
tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
960
WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
965
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
966
tmp |= srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
967
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
968
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
969
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
973
tmp &= ~srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
974
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
975
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1206
u32 tmp = RREG32(mmSRBM_STATUS2);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1208
if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1218
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1222
tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1225
if (!tmp)
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1236
u32 tmp = RREG32(mmSRBM_STATUS2);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1238
if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) ||
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1239
(tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) {
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1295
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1303
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1304
tmp |= srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1305
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1306
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1307
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1311
tmp &= ~srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1312
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1313
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
811
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
819
tmp = 0xCAFEDEAD;
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
820
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
835
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
836
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
864
u32 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
873
tmp = 0xCAFEDEAD;
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
874
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
903
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
904
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1469
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1477
tmp = 0xCAFEDEAD;
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1478
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1493
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1494
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1523
u32 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1531
tmp = 0xCAFEDEAD;
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1532
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1561
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1562
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
2024
u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
2026
if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1065
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1073
tmp = 0xCAFEDEAD;
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1074
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1089
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1090
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1119
u32 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1127
tmp = 0xCAFEDEAD;
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1128
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1157
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1158
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1615
u32 tmp = RREG32_SDMA(i, regSDMA_STATUS_REG);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1617
if (!(tmp & SDMA_STATUS_REG__IDLE_MASK))
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1018
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1021
tmp = 0xCAFEDEAD;
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1030
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1048
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1049
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1081
u32 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1084
tmp = 0xCAFEDEAD;
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1094
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1128
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1130
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1333
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1340
tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1341
tmp |= grbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1342
DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1343
WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1344
tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1348
tmp &= ~grbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1349
WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1350
tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1502
u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1504
if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1027
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1029
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1415
u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1417
if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
769
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
776
tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
777
tmp |= grbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
778
DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
779
WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
780
tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
784
tmp &= ~grbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
785
WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
786
tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
918
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
921
tmp = 0xCAFEDEAD;
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
930
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
948
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
949
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
981
u32 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
984
tmp = 0xCAFEDEAD;
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
994
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1000
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1033
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1035
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1495
u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1497
if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
762
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
768
tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE));
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
769
tmp |= SDMA0_FREEZE__FREEZE_MASK;
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
770
WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
771
tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
772
tmp |= SDMA0_F32_CNTL__HALT_MASK;
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
773
tmp |= SDMA0_F32_CNTL__TH1_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
774
WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
780
tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i;
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
781
WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
782
tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
787
tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
924
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
927
tmp = 0xCAFEDEAD;
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
936
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
954
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
955
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
987
u32 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
990
tmp = 0xCAFEDEAD;
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1004
u32 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1007
tmp = 0xCAFEDEAD;
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1017
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1050
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1052
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1451
u32 tmp = RREG32(sdma_v7_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1453
if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
684
uint32_t tmp, sdma_status, ic_op_cntl;
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
718
tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
719
tmp = REG_SET_FIELD(tmp, SDMA0_IC_CNTL, GPA, 0);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
720
WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_CNTL), tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
727
tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
728
tmp = REG_SET_FIELD(tmp, SDMA0_IC_OP_CNTL, PRIME_ICACHE, 1);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
729
WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL), tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
755
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
764
tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
765
tmp |= SDMA0_MCU_CNTL__HALT_MASK;
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
766
tmp |= SDMA0_MCU_CNTL__RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
767
WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
773
tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i;
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
774
WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
775
tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
780
tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
941
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
944
tmp = 0xCAFEDEAD;
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
953
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
971
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
972
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/si.c
1346
u32 tmp, i;
sys/dev/pci/drm/amd/amdgpu/si.c
1348
tmp = RREG32(mmCG_SPLL_FUNC_CNTL);
sys/dev/pci/drm/amd/amdgpu/si.c
1349
tmp |= CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/si.c
1350
WREG32(mmCG_SPLL_FUNC_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/si.c
1352
tmp = RREG32(mmCG_SPLL_FUNC_CNTL_2);
sys/dev/pci/drm/amd/amdgpu/si.c
1353
tmp |= CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK;
sys/dev/pci/drm/amd/amdgpu/si.c
1354
WREG32(mmCG_SPLL_FUNC_CNTL_2, tmp);
sys/dev/pci/drm/amd/amdgpu/si.c
1362
tmp = RREG32(mmCG_SPLL_FUNC_CNTL_2);
sys/dev/pci/drm/amd/amdgpu/si.c
1363
tmp &= ~(CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK |
sys/dev/pci/drm/amd/amdgpu/si.c
1365
WREG32(mmCG_SPLL_FUNC_CNTL_2, tmp);
sys/dev/pci/drm/amd/amdgpu/si.c
1367
tmp = RREG32(MPLL_CNTL_MODE);
sys/dev/pci/drm/amd/amdgpu/si.c
1368
tmp &= ~MPLL_MCLK_SEL;
sys/dev/pci/drm/amd/amdgpu/si.c
1369
WREG32(MPLL_CNTL_MODE, tmp);
sys/dev/pci/drm/amd/amdgpu/si.c
1374
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/si.c
1376
tmp = RREG32(mmSPLL_CNTL_MODE);
sys/dev/pci/drm/amd/amdgpu/si.c
1377
tmp |= SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK;
sys/dev/pci/drm/amd/amdgpu/si.c
1378
WREG32(mmSPLL_CNTL_MODE, tmp);
sys/dev/pci/drm/amd/amdgpu/si.c
1380
tmp = RREG32(mmCG_SPLL_FUNC_CNTL);
sys/dev/pci/drm/amd/amdgpu/si.c
1381
tmp |= CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/si.c
1382
WREG32(mmCG_SPLL_FUNC_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/si.c
1384
tmp = RREG32(mmCG_SPLL_FUNC_CNTL);
sys/dev/pci/drm/amd/amdgpu/si.c
1385
tmp |= CG_SPLL_FUNC_CNTL__SPLL_SLEEP_MASK;
sys/dev/pci/drm/amd/amdgpu/si.c
1386
WREG32(mmCG_SPLL_FUNC_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/si.c
1388
tmp = RREG32(mmSPLL_CNTL_MODE);
sys/dev/pci/drm/amd/amdgpu/si.c
1389
tmp &= ~SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK;
sys/dev/pci/drm/amd/amdgpu/si.c
1390
WREG32(mmSPLL_CNTL_MODE, tmp);
sys/dev/pci/drm/amd/amdgpu/si.c
1485
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/si.c
1487
tmp = RREG32(mmCG_CLKPIN_CNTL_2);
sys/dev/pci/drm/amd/amdgpu/si.c
1488
if (tmp & CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK)
sys/dev/pci/drm/amd/amdgpu/si.c
1491
tmp = RREG32(mmCG_CLKPIN_CNTL);
sys/dev/pci/drm/amd/amdgpu/si.c
1492
if (tmp & CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK)
sys/dev/pci/drm/amd/amdgpu/si.c
1600
int tmp;
sys/dev/pci/drm/amd/amdgpu/si.c
1632
tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK);
sys/dev/pci/drm/amd/amdgpu/si.c
1633
cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
sys/dev/pci/drm/amd/amdgpu/si.c
1634
cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
sys/dev/pci/drm/amd/amdgpu/si.c
2281
u32 max_lw, current_lw, tmp;
sys/dev/pci/drm/amd/amdgpu/si.c
2286
tmp = RREG32_PCIE(ixPCIE_LC_STATUS1);
sys/dev/pci/drm/amd/amdgpu/si.c
2287
max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >> PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT;
sys/dev/pci/drm/amd/amdgpu/si.c
2288
current_lw = (tmp & PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK) >> PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT;
sys/dev/pci/drm/amd/amdgpu/si.c
2291
tmp = RREG32_PCIE_PORT(ixPCIE_LC_LINK_WIDTH_CNTL);
sys/dev/pci/drm/amd/amdgpu/si.c
2292
if (tmp & PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK) {
sys/dev/pci/drm/amd/amdgpu/si.c
2293
tmp &= ~(PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK | PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK);
sys/dev/pci/drm/amd/amdgpu/si.c
2294
tmp |= (max_lw << PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT);
sys/dev/pci/drm/amd/amdgpu/si.c
2295
tmp |= PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK | PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK | PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK;
sys/dev/pci/drm/amd/amdgpu/si.c
2296
WREG32_PCIE_PORT(ixPCIE_LC_LINK_WIDTH_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/si.c
2319
tmp = RREG32_PCIE_PORT(ixPCIE_LC_CNTL4);
sys/dev/pci/drm/amd/amdgpu/si.c
2320
tmp |= PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;
sys/dev/pci/drm/amd/amdgpu/si.c
2321
WREG32_PCIE_PORT(ixPCIE_LC_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/si.c
2323
tmp = RREG32_PCIE_PORT(ixPCIE_LC_CNTL4);
sys/dev/pci/drm/amd/amdgpu/si.c
2324
tmp |= PCIE_LC_CNTL4__LC_REDO_EQ_MASK;
sys/dev/pci/drm/amd/amdgpu/si.c
2325
WREG32_PCIE_PORT(ixPCIE_LC_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/si.c
2351
tmp = RREG32_PCIE_PORT(ixPCIE_LC_CNTL4);
sys/dev/pci/drm/amd/amdgpu/si.c
2352
tmp &= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;
sys/dev/pci/drm/amd/amdgpu/si.c
2353
WREG32_PCIE_PORT(ixPCIE_LC_CNTL4, tmp);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
214
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/si_dma.c
222
tmp = 0xCAFEDEAD;
sys/dev/pci/drm/amd/amdgpu/si_dma.c
223
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
236
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
237
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/si_dma.c
265
u32 tmp = 0;
sys/dev/pci/drm/amd/amdgpu/si_dma.c
274
tmp = 0xCAFEDEAD;
sys/dev/pci/drm/amd/amdgpu/si_dma.c
275
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
298
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
299
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/si_dma.c
564
u32 tmp = RREG32(mmSRBM_STATUS2);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
566
if (tmp & (SRBM_STATUS2__DMA_BUSY_MASK | SRBM_STATUS2__DMA1_BUSY_MASK))
sys/dev/pci/drm/amd/amdgpu/si_dma.c
694
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/si_dma.c
701
for (tmp = 0; tmp < 5; tmp++)
sys/dev/pci/drm/amd/amdgpu/si_ih.c
111
u32 wptr, tmp;
sys/dev/pci/drm/amd/amdgpu/si_ih.c
120
tmp = RREG32(IH_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
121
tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
sys/dev/pci/drm/amd/amdgpu/si_ih.c
122
WREG32(IH_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
127
tmp &= ~IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
sys/dev/pci/drm/amd/amdgpu/si_ih.c
128
WREG32(IH_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
217
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
219
if (tmp & SRBM_STATUS__IH_BUSY_MASK)
sys/dev/pci/drm/amd/amdgpu/si_ih.c
243
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
245
if (tmp & SRBM_STATUS__IH_BUSY_MASK)
sys/dev/pci/drm/amd/amdgpu/si_ih.c
249
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
250
tmp |= srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/si_ih.c
251
dev_info(adev->dev, "mmSRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
252
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
253
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
257
tmp &= ~srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/si_ih.c
258
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/si_ih.c
259
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/soc15.c
476
u32 tmp, reg;
sys/dev/pci/drm/amd/amdgpu/soc15.c
484
tmp = entry->or_mask;
sys/dev/pci/drm/amd/amdgpu/soc15.c
486
tmp = (entry->hwip == GC_HWIP) ?
sys/dev/pci/drm/amd/amdgpu/soc15.c
489
tmp &= ~(entry->and_mask);
sys/dev/pci/drm/amd/amdgpu/soc15.c
490
tmp |= (entry->or_mask & entry->and_mask);
sys/dev/pci/drm/amd/amdgpu/soc15.c
497
WREG32_RLC(reg, tmp);
sys/dev/pci/drm/amd/amdgpu/soc15.c
500
WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp);
sys/dev/pci/drm/amd/amdgpu/soc15.c
761
int tmp;
sys/dev/pci/drm/amd/amdgpu/soc15.c
794
tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
sys/dev/pci/drm/amd/amdgpu/soc15.c
795
cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
sys/dev/pci/drm/amd/amdgpu/soc15.c
796
cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
sys/dev/pci/drm/amd/amdgpu/soc15.c
808
int tmp;
sys/dev/pci/drm/amd/amdgpu/soc15.c
843
tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
sys/dev/pci/drm/amd/amdgpu/soc15.c
844
cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
sys/dev/pci/drm/amd/amdgpu/soc15.c
845
cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
125
u32 tmp = RREG32(r1); \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
126
if (!(tmp & 0x80000000)) \
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
195
u32 wptr, tmp;
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
218
tmp = RREG32(mmIH_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
219
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
220
WREG32(mmIH_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
225
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
226
WREG32(mmIH_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
359
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
361
if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
370
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
375
tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
376
if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
387
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
389
if (tmp & SRBM_STATUS__IH_BUSY_MASK)
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
430
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
432
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
433
tmp |= srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
434
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
435
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
436
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
440
tmp &= ~srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
441
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
442
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
142
uint32_t tmp = 0;
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
155
tmp = RREG32(mmUVD_CONTEXT_ID);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
156
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
209
u32 tmp, tmp2;
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
213
tmp = RREG32(mmUVD_CGC_CTRL);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
214
tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
215
tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
220
tmp &= ~0x7ffff800;
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
225
tmp |= 0x7ffff800;
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
229
WREG32(mmUVD_CGC_CTRL, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
325
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
358
tmp = RREG32(mmUVD_MPC_CNTL);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
359
WREG32(mmUVD_MPC_CNTL, tmp | 0x10);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
368
tmp = RREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
369
WREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL, tmp & (~0x10));
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
647
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
681
tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
682
amdgpu_ring_write(ring, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
685
tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
686
amdgpu_ring_write(ring, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
689
tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
690
amdgpu_ring_write(ring, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
158
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
174
tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
175
amdgpu_ring_write(ring, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
178
tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
179
amdgpu_ring_write(ring, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
182
tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
183
amdgpu_ring_write(ring, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
287
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
319
tmp = RREG32(mmUVD_MPC_CNTL);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
320
WREG32(mmUVD_MPC_CNTL, tmp | 0x10);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
331
tmp = RREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
332
WREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL, tmp & (~0x10));
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
509
uint32_t tmp = 0;
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
522
tmp = RREG32(mmUVD_CONTEXT_ID);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
523
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
638
u32 tmp, tmp2;
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
642
tmp = RREG32(mmUVD_CGC_CTRL);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
643
tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
644
tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
649
tmp &= ~0x7ffff800;
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
654
tmp |= 0x7ffff800;
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
658
WREG32(mmUVD_CGC_CTRL, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
154
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
171
tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
172
amdgpu_ring_write(ring, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
175
tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
176
amdgpu_ring_write(ring, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
179
tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
180
amdgpu_ring_write(ring, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
322
uint32_t rb_bufsz, tmp;
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
420
tmp = 0;
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
421
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
422
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
423
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
424
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
425
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
426
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
428
WREG32(mmUVD_RBC_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
524
uint32_t tmp = 0;
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
536
tmp = RREG32(mmUVD_CONTEXT_ID);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
537
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1002
tmp = RREG32(mmUVD_CONTEXT_ID);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1003
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1172
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1174
if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1175
REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1209
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1211
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1212
tmp |= srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1213
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1214
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1215
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1219
tmp &= ~srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1220
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1221
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
468
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
485
tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
486
amdgpu_ring_write(ring, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
489
tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
490
amdgpu_ring_write(ring, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
493
tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
494
amdgpu_ring_write(ring, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
729
uint32_t rb_bufsz, tmp;
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
839
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
840
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
841
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
842
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
843
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
844
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
845
WREG32(mmUVD_RBC_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
989
uint32_t tmp = 0;
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1086
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1087
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1088
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1089
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1090
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1091
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1092
WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1255
uint32_t tmp = 0;
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1269
tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1270
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
523
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
549
tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
551
amdgpu_ring_write(ring, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
554
tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
556
amdgpu_ring_write(ring, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
559
tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
561
amdgpu_ring_write(ring, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
791
uint32_t offset, size, tmp;
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
919
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
920
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
921
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
957
uint32_t rb_bufsz, tmp;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
149
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
151
tmp = RREG32(mmVCE_CLOCK_GATING_A);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
152
tmp &= ~0xfff;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
153
tmp |= ((0 << 0) | (4 << 4));
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
154
tmp |= 0x40000;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
155
WREG32(mmVCE_CLOCK_GATING_A, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
157
tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
158
tmp &= ~0xfff;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
159
tmp |= ((0 << 0) | (4 << 4));
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
160
WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
162
tmp = RREG32(mmVCE_CLOCK_GATING_B);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
163
tmp |= 0x10;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
164
tmp &= ~0x100000;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
165
WREG32(mmVCE_CLOCK_GATING_B, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
318
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
321
tmp = RREG32(mmVCE_CLOCK_GATING_B);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
322
tmp |= 0xe70000;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
323
WREG32(mmVCE_CLOCK_GATING_B, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
325
tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
326
tmp |= 0xff000000;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
327
WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
329
tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
330
tmp &= ~0x3fc;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
331
WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
335
tmp = RREG32(mmVCE_CLOCK_GATING_B);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
336
tmp |= 0xe7;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
337
tmp &= ~0xe70000;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
338
WREG32(mmVCE_CLOCK_GATING_B, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
340
tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
341
tmp |= 0x1fe000;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
342
tmp &= ~0xff000000;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
343
WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
345
tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
346
tmp |= 0x3fc;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
347
WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
353
u32 orig, tmp;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
358
tmp = RREG32(mmVCE_CLOCK_GATING_B);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
359
tmp &= ~0x00060006;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
363
tmp |= 0xe10000;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
364
WREG32(mmVCE_CLOCK_GATING_B, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
366
tmp |= 0xe1;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
367
tmp &= ~0xe10000;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
368
WREG32(mmVCE_CLOCK_GATING_B, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
371
orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
372
tmp &= ~0x1fe000;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
373
tmp &= ~0xff000000;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
374
if (tmp != orig)
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
375
WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
377
orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
378
tmp &= ~0x3fc;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
379
if (tmp != orig)
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
380
WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
366
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
373
tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) &
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
377
tmp = (RREG32_SMC(ixCC_HARVEST_FUSES) &
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
381
switch (tmp) {
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
680
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
682
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
683
tmp |= srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
684
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
685
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
686
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
690
tmp &= ~srbm_soft_reset;
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
691
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
692
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1030
uint32_t rb_bufsz, tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1039
tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1040
tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1041
tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1042
WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1048
tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1049
tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1050
tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1051
WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1123
tmp = adev->gfx.config.gb_addr_config;
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1125
WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1126
WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1134
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1135
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1136
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1137
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1138
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1139
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1194
int tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1198
tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1202
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1209
tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1211
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1247
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1255
tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1256
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1258
tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1259
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1261
tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1262
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1264
tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1265
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
850
uint32_t rb_bufsz, tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
859
tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
860
WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
870
tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
871
WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
883
tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
884
tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
885
tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
886
WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
922
tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
923
tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
924
tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
925
WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
965
tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY;
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
966
WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
970
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
971
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
972
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
973
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
974
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
975
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1006
uint32_t rb_bufsz, tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1019
tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1020
WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1034
tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1035
WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1042
tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1043
tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1044
tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1045
WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1077
tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1078
tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1079
tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1080
WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1132
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1133
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1134
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1135
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1136
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1137
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1184
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1192
tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1193
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1195
tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1196
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1198
tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1199
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1219
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1234
tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1238
r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1243
tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1244
tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1245
WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1247
tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1249
r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1828
uint32_t tmp = 0;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1845
tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1846
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1958
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2077
tmp = order_base_2(ring->ring_size);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2078
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2079
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2080
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2081
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2082
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2084
SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2087
tmp = sizeof(struct mmsch_v2_0_cmd_end);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2088
memcpy((void *)init_table, &end, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2089
table_size += (tmp / 4);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
858
uint32_t rb_bufsz, tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
864
tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
865
tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
866
tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
867
WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
876
tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
877
tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
878
tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
880
UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
887
tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
896
UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
953
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
954
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
955
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
956
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
957
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
958
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1002
tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1011
uint32_t rb_bufsz, tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1018
tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1019
tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1020
tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1021
WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1030
tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1031
tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1032
tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1034
VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1041
tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1050
VCN, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1093
tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1094
tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1096
VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1114
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1115
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1116
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1117
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1118
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1119
WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1169
uint32_t rb_bufsz, tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1186
tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1187
WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1204
tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1205
tmp &= ~0xff;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1206
WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 0x8|
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1213
tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1214
tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1215
tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1216
WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1304
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1305
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1306
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1307
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1308
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1309
WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1411
uint32_t offset, size, tmp, i, rb_bufsz;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1527
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1528
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1529
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1530
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1531
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1533
SOC15_REG_OFFSET(VCN, i, mmUVD_RBC_RB_CNTL), tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1552
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1559
tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1560
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1562
tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1563
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1565
tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1566
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1587
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1603
tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1607
r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1612
tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1613
tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1614
WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1616
tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1618
r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
981
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
986
tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
992
tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
994
tmp = UVD_VCPU_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
997
tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
999
tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1034
uint32_t rb_bufsz, tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1041
tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1042
tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1043
tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1044
WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1053
tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1054
tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1055
tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1057
VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1064
tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1073
VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1114
tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1115
tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1117
VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1126
VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1139
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1140
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1141
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1142
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1143
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1144
WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1199
uint32_t rb_bufsz, tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1215
tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1216
WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1233
tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1234
tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1235
tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1236
WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1239
tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1240
WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp |
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1247
tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1248
tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1249
tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1250
WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1330
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1331
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1332
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1333
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1334
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1335
WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1394
uint32_t tmp, timeout;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1519
tmp = order_base_2(ring->ring_size);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1520
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1521
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1522
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1523
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1524
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1527
tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1553
tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1554
tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1556
tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1557
WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1571
tmp = 0;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1581
tmp = tmp + 10;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1582
if (tmp >= timeout) {
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1586
tmp, expected, resp);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1599
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1608
tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1609
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1611
tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1612
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1614
tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1615
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1636
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1652
tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1656
r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1661
tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1662
tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1663
WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1664
tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1666
r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1685
tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1686
tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1687
WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1688
tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1689
tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1690
WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1002
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1009
tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1010
tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1011
tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1012
WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1021
tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1022
tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1024
VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1031
tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1040
VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1068
tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1069
tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1071
VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1074
tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1076
VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1100
tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1101
tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1102
WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1107
tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1108
WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1111
tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1112
tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1113
WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1142
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1160
tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1161
WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1178
tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1179
tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1180
tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1181
WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1184
tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1185
WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1192
tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1193
tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1194
tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1195
WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1290
tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1291
tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1292
WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1297
tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1298
WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1301
tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1302
tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1303
WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1341
uint32_t tmp, timeout;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1515
tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1516
tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1518
tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1519
WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1533
tmp = 0;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1543
tmp = tmp + 10;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1544
if (tmp >= timeout) {
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1548
tmp, expected, resp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1574
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1582
tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1583
SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1610
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1629
tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1633
r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1638
tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1639
tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1640
WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1641
tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1643
r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1662
tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1663
tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1664
WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1665
tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1666
tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1667
WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
969
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
974
tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
980
tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
982
tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
985
tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1135
tmp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1136
tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1137
tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1138
WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1147
tmp = 0;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1157
tmp = tmp + 10;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1158
if (tmp >= timeout) {
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1162
tmp, expected, resp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1193
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1200
tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) |
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1202
WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1220
tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1221
tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1222
tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1223
WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1226
tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1228
tmp | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1234
tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1235
tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1236
tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1237
WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1331
tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1332
tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1333
WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1339
tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1340
tmp |= VCN_RB_ENABLE__RB_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1341
WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1361
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1371
tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1372
SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1402
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1420
tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1424
r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1425
tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1430
tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1431
tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1432
WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1433
tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1435
r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1436
tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1455
tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1456
tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1457
WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1459
tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1460
tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1461
WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
2109
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
2114
tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
2120
tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
2122
tmp = UVD_VCPU_INT_EN2__RASCNTL_VCPU_VCODEC_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
2125
tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
2127
tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
2130
tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
852
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
859
tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
860
tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
861
tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
862
WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
878
tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
879
tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
880
tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
883
VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
890
tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
899
VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
927
tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
928
tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
930
VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
933
tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
935
VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
964
tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
965
tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
966
WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
974
tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
975
tmp |= VCN_RB_ENABLE__RB_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
976
WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
999
uint32_t tmp, timeout;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1013
tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1014
tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1015
WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1020
tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1021
WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1024
tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1025
tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1026
WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1054
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1072
tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1073
WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1090
tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1091
tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1092
tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1093
WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1096
tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1097
WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1104
tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1105
tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1106
tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1107
WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1203
tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1204
tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1205
WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1210
tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1211
WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1214
tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1215
tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1216
WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1237
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1244
tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1245
SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1272
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1292
tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1296
r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1301
tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1302
tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1303
WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1304
tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1306
r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1325
tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1326
tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1327
WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1328
tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1329
tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1330
WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
917
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
924
tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
925
tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
926
tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
927
WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
937
tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
938
tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
940
VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
947
tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
956
VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
984
tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
985
tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
987
VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
990
tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
992
VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
1003
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
1023
tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
1027
r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
1032
tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
1033
tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
1034
WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
1035
tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
1037
r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
1056
tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
1057
tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
1058
WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
1059
tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
1060
tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
1061
WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
701
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
709
tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
710
tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
711
tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
712
WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
718
tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
719
tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
721
VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
728
tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
737
VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
741
tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
742
tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
744
VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
747
tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
749
VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
770
tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
771
tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
772
WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
777
tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
778
WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
781
tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
782
tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
783
WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
811
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
829
tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
830
WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
844
tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
845
tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
846
tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
847
WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
850
tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
851
WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
931
tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
932
tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
933
WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
938
tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
939
WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
942
tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
943
tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
944
WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
967
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
976
tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
977
SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1010
tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1011
tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1012
tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1013
WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1016
tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1017
WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL, tmp |
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1101
tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1102
tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1103
WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1108
tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1109
WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1112
tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1113
tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1114
WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1136
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1150
tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1151
SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1175
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1193
tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1197
r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1202
tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1203
tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1204
WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1205
tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1207
r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1226
tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1227
tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1228
WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1229
tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1230
tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1231
WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
676
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
685
tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
686
tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
687
WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
698
tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
699
tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
701
VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
708
tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
717
VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
721
tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
722
tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
724
VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
727
tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
729
VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
756
tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
757
tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
758
WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
763
tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
764
WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
767
tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
768
tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
769
WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
791
uint32_t tmp, timeout;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
927
tmp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
928
tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
929
tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
930
WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID, tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
939
tmp = 0;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
949
tmp = tmp + 10;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
950
if (tmp >= timeout) {
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
954
tmp, expected, resp);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
984
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
995
tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
996
WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
101
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
105
tmp = RREG32(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
106
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
107
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
110
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
112
if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
117
WREG32(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
212
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
220
tmp = RREG32(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
221
tmp = vega10_ih_rb_cntl(ih, tmp);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
223
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
225
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
227
if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
232
WREG32(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
338
u32 wptr, tmp;
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
366
tmp = (wptr + 32) & ih->ptr_mask;
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
368
amdgpu_ih_ring_name(adev, ih), wptr, ih->rptr, tmp);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
369
ih->rptr = tmp;
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
371
tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
372
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
373
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
378
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
379
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
109
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
113
tmp = RREG32(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
114
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
115
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
121
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
123
if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
126
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
130
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
132
if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
135
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
141
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
146
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
148
if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
153
WREG32(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
248
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
256
tmp = RREG32(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
257
tmp = vega20_ih_rb_cntl(ih, tmp);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
259
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
261
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
263
if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
268
WREG32(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
419
u32 wptr, tmp;
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
450
tmp = (wptr + 32) & ih->ptr_mask;
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
452
amdgpu_ih_ring_name(adev, ih), wptr, ih->rptr, tmp);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
453
ih->rptr = tmp;
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
455
tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
456
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
457
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
462
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
463
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
sys/dev/pci/drm/amd/amdgpu/vi.c
1000
tmp |= dividers.post_divider;
sys/dev/pci/drm/amd/amdgpu/vi.c
1001
WREG32_SMC(cntl_reg, tmp);
sys/dev/pci/drm/amd/amdgpu/vi.c
1004
tmp = RREG32_SMC(status_reg);
sys/dev/pci/drm/amd/amdgpu/vi.c
1006
if (tmp & 0x10000)
sys/dev/pci/drm/amd/amdgpu/vi.c
1009
if (tmp & CG_DCLK_STATUS__DCLK_STATUS_MASK)
sys/dev/pci/drm/amd/amdgpu/vi.c
1055
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/vi.c
1088
tmp = RREG32_SMC(reg_ctrl);
sys/dev/pci/drm/amd/amdgpu/vi.c
1089
tmp &= ~reg_mask;
sys/dev/pci/drm/amd/amdgpu/vi.c
1090
tmp |= dividers.post_divider;
sys/dev/pci/drm/amd/amdgpu/vi.c
1091
WREG32_SMC(reg_ctrl, tmp);
sys/dev/pci/drm/amd/amdgpu/vi.c
1281
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/vi.c
1287
tmp = RREG32(mmBIF_DOORBELL_APER_EN);
sys/dev/pci/drm/amd/amdgpu/vi.c
1289
tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
sys/dev/pci/drm/amd/amdgpu/vi.c
1291
tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
sys/dev/pci/drm/amd/amdgpu/vi.c
1293
WREG32(mmBIF_DOORBELL_APER_EN, tmp);
sys/dev/pci/drm/amd/amdgpu/vi.c
1357
int tmp;
sys/dev/pci/drm/amd/amdgpu/vi.c
1389
tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK);
sys/dev/pci/drm/amd/amdgpu/vi.c
1390
cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
sys/dev/pci/drm/amd/amdgpu/vi.c
1391
cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
sys/dev/pci/drm/amd/amdgpu/vi.c
542
u32 tmp;
sys/dev/pci/drm/amd/amdgpu/vi.c
554
tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
sys/dev/pci/drm/amd/amdgpu/vi.c
555
if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
sys/dev/pci/drm/amd/amdgpu/vi.c
558
tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);
sys/dev/pci/drm/amd/amdgpu/vi.c
559
if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
sys/dev/pci/drm/amd/amdgpu/vi.c
985
uint32_t tmp;
sys/dev/pci/drm/amd/amdgpu/vi.c
993
tmp = RREG32_SMC(cntl_reg);
sys/dev/pci/drm/amd/amdgpu/vi.c
996
tmp &= ~CG_DCLK_CNTL__DCLK_DIVIDER_MASK;
sys/dev/pci/drm/amd/amdgpu/vi.c
998
tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
53
uint64_t tmp = process->exception_enable_mask;
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
58
tmp &= pqn->q->properties.exception_status;
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
60
if (!tmp)
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
73
uint64_t tmp = process->exception_enable_mask
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
76
if (!tmp)
sys/dev/pci/drm/amd/amdkfd/kfd_debugfs.c
130
char tmp[32];
sys/dev/pci/drm/amd/amdkfd/kfd_debugfs.c
133
len = snprintf(tmp, sizeof(tmp), "%u\n", pdd->pasid);
sys/dev/pci/drm/amd/amdkfd/kfd_debugfs.c
135
return simple_read_from_buffer(buf, count, ppos, tmp, len);
sys/dev/pci/drm/amd/amdkfd/kfd_debugfs.c
57
char tmp[16];
sys/dev/pci/drm/amd/amdkfd/kfd_debugfs.c
61
memset(tmp, 0, 16);
sys/dev/pci/drm/amd/amdkfd/kfd_debugfs.c
66
if (copy_from_user(tmp, user_buf, size)) {
sys/dev/pci/drm/amd/amdkfd/kfd_debugfs.c
70
if (kstrtoint(tmp, 10, &gpu_id)) {
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
2161
struct svm_range *tmp;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
2247
list_for_each_entry_safe(prange, tmp, insert_list, list)
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
2249
list_for_each_entry_safe(prange, tmp, &new_list, list)
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
2224
struct kfd_iolink_properties *iolink, *p2plink, *tmp;
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
2230
list_for_each_entry_safe(iolink, tmp, &dev->io_link_props, list) {
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
2246
list_for_each_entry_safe(p2plink, tmp, &dev->p2p_link_props, list) {
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
2266
struct kfd_topology_device *dev, *tmp;
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
2273
list_for_each_entry_safe(dev, tmp, &topology_device_list, list) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
137
struct list_head *entry, *tmp;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
157
list_for_each_safe(entry, tmp, hnd_list) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
201
struct list_head *entry, *tmp;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
212
list_for_each_safe(entry, tmp, hnd_list_low) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
224
list_for_each_safe(entry, tmp, hnd_list_high) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
449
struct list_head *entry, *tmp;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
464
list_for_each_safe(entry, tmp, lh) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
483
struct list_head *entry, *tmp;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
503
list_for_each_safe(entry, tmp, hnd_list_l) {
sys/dev/pci/drm/amd/display/dc/basics/bw_fixed.c
155
uint64_t tmp;
sys/dev/pci/drm/amd/display/dc/basics/bw_fixed.c
163
tmp = arg1_int * arg2_fra;
sys/dev/pci/drm/amd/display/dc/basics/bw_fixed.c
165
ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value));
sys/dev/pci/drm/amd/display/dc/basics/bw_fixed.c
167
res.value += tmp;
sys/dev/pci/drm/amd/display/dc/basics/bw_fixed.c
169
tmp = arg2_int * arg1_fra;
sys/dev/pci/drm/amd/display/dc/basics/bw_fixed.c
171
ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value));
sys/dev/pci/drm/amd/display/dc/basics/bw_fixed.c
173
res.value += tmp;
sys/dev/pci/drm/amd/display/dc/basics/bw_fixed.c
175
tmp = arg1_fra * arg2_fra;
sys/dev/pci/drm/amd/display/dc/basics/bw_fixed.c
177
tmp = (tmp >> BW_FIXED_BITS_PER_FRACTIONAL_PART) +
sys/dev/pci/drm/amd/display/dc/basics/bw_fixed.c
178
(tmp >= (uint64_t)(bw_frc_to_fixed(1, 2).value));
sys/dev/pci/drm/amd/display/dc/basics/bw_fixed.c
180
ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value));
sys/dev/pci/drm/amd/display/dc/basics/bw_fixed.c
182
res.value += tmp;
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
137
unsigned long long tmp;
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
143
tmp = arg1_int * arg2_fra;
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
145
ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
147
res.value += tmp;
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
149
tmp = arg2_int * arg1_fra;
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
151
ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
153
res.value += tmp;
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
155
tmp = arg1_fra * arg2_fra;
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
157
tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) +
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
158
(tmp >= (unsigned long long)dc_fixpt_half.value);
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
160
ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
162
res.value += tmp;
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
180
unsigned long long tmp;
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
186
tmp = arg_int * arg_fra;
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
188
ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
190
res.value += tmp;
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
192
ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
194
res.value += tmp;
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
196
tmp = arg_fra * arg_fra;
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
198
tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) +
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
199
(tmp >= (unsigned long long)dc_fixpt_half.value);
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
201
ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
203
res.value += tmp;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
616
uint32_t tmp = 0;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
660
tmp = timing->h_total -
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
665
tmp,
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
669
tmp = tmp + timing->h_addressable +
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
674
tmp,
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
683
tmp = timing->v_total - (v_sync_start + timing->v_border_top);
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
687
tmp,
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
691
tmp = tmp + timing->v_addressable + timing->v_border_top +
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
696
tmp,
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
256
uint32_t tmp = 0;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
279
tmp = timing->h_total -
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
284
tmp,
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
288
tmp = tmp + timing->h_addressable +
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
293
tmp,
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
302
tmp = timing->v_total - (v_sync_start + timing->v_border_top);
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
306
tmp,
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
310
tmp = tmp + timing->v_addressable + timing->v_border_top +
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
315
tmp,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
364
uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1] = {0};
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
369
tmp,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
370
sizeof(tmp));
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
375
irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
376
irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
377
irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
378
irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
379
irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
380
irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
381
irq_data->bytes.link_service_irq_esi0.raw = tmp[DP_LINK_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
115
unsigned long long tmp;
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
123
tmp = arg1_int * arg2_fra;
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
125
SPL_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
127
res.value += tmp;
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
129
tmp = arg2_int * arg1_fra;
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
131
SPL_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
133
res.value += tmp;
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
135
tmp = arg1_fra * arg2_fra;
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
137
tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) +
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
138
(tmp >= (unsigned long long)spl_fixpt_half.value);
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
140
SPL_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
142
res.value += tmp;
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
160
unsigned long long tmp;
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
168
tmp = arg_int * arg_fra;
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
170
SPL_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
172
res.value += tmp;
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
174
SPL_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
176
res.value += tmp;
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
178
tmp = arg_fra * arg_fra;
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
180
tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) +
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
181
(tmp >= (unsigned long long)spl_fixpt_half.value);
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
183
SPL_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
185
res.value += tmp;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
64
uint32_t tmp;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
72
REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
73
*fb_base = (uint64_t)tmp << 24;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
75
REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
76
*fb_offset = (uint64_t)tmp << 24;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
64
uint32_t tmp;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
72
REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
73
*fb_base = (uint64_t)tmp << 24;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
75
REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
76
*fb_offset = (uint64_t)tmp << 24;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
60
uint32_t tmp;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
68
REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
69
*fb_base = (uint64_t)tmp << 24;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
71
REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
72
*fb_offset = (uint64_t)tmp << 24;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
66
uint32_t tmp;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
74
REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
75
*fb_base = (uint64_t)tmp << 24;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
77
REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
78
*fb_offset = (uint64_t)tmp << 24;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
63
uint32_t tmp;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
73
REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
74
*fb_base = (uint64_t)tmp << 24;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
76
REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
77
*fb_offset = (uint64_t)tmp << 24;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
40
uint32_t tmp;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
48
REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
49
*fb_base = (uint64_t)tmp << 24;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
51
REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
52
*fb_offset = (uint64_t)tmp << 24;
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
1026
char *tmp;
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
1036
tmp = buf_cpy;
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
1037
while ((sub_str = strsep(&tmp, delimiter)) != NULL) {
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
1380
char tmp[2];
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
1384
tmp[0] = *(buf);
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
1385
tmp[1] = '\0';
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
1386
ret = kstrtol(tmp, 0, &profile_mode);
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
2421
char *tmp, *param;
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
2427
tmp = tmp_buf;
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
2429
tmp = skip_spaces(tmp);
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
2430
while ((param = strsep(&tmp, delimiter))) {
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
2432
tmp = skip_spaces(tmp);
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
3652
uint32_t tmp;
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
3744
(void *)&tmp) == -EOPNOTSUPP)
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
3748
(void *)&tmp) == -EOPNOTSUPP)
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
3788
(void *)&tmp) == -EOPNOTSUPP)
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
4674
uint32_t tmp;
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
4742
(void *)&tmp) != -EOPNOTSUPP) {
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1441
u16 tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1443
tmp = 45;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1444
pi->fps_high_t = cpu_to_be16(tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1451
tmp = 30;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1452
pi->fps_low_t = cpu_to_be16(tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2517
u32 tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2528
tmp = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2529
tmp &= ~(CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK |
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2531
tmp |= ((49 + (high_temp / 1000)) << CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT) |
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2533
WREG32_SMC(ixCG_THERMAL_INT_CTRL, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2863
u32 sclk, tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2870
tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) &
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2873
vddc = kv_convert_8bit_index_to_voltage(adev, (u16)tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
575
u32 tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
580
&tmp, pi->sram_end);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
583
pi->dpm_table_start = tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
587
&tmp, pi->sram_end);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
590
pi->soft_regs_start = tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
717
u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
719
tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
720
WREG32_SMC(ixGENERAL_PWRMGT, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c
35
u32 tmp = 0;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c
44
tmp = RREG32(mmSMC_RESP_0) & SMC_RESP_0__SMC_RESP_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c
46
if (tmp != 1) {
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c
47
if (tmp == 0xFF)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c
49
else if (tmp == 0xFE)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
1879
s64 tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
1891
tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
1892
kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
1893
kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2966
u32 tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3001
tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3003
spll_table->freq[i] = cpu_to_be32(tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3005
tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3007
spll_table->ss[i] = cpu_to_be32(tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3360
u32 tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3363
tmp = i_c >> p_b;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3365
while (tmp) {
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3367
tmp >>= 1;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3726
u32 tmp, width, row, column, bank, density;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3729
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3730
is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3731
is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3732
& (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3737
tmp = RREG32(mmMC_ARB_RAMCFG);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3738
row = ((tmp & MC_ARB_RAMCFG__NOOFROWS_MASK) >> MC_ARB_RAMCFG__NOOFROWS__SHIFT) + 10;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3739
column = ((tmp & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT) + 8;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3740
bank = ((tmp & MC_ARB_RAMCFG__NOOFBANK_MASK) >> MC_ARB_RAMCFG__NOOFBANK__SHIFT) + 2;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4000
u32 tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4006
&tmp, si_pi->sram_end);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4010
si_pi->state_table_start = tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4015
&tmp, si_pi->sram_end);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4019
si_pi->soft_regs_start = tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4024
&tmp, si_pi->sram_end);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4028
si_pi->mc_reg_table_start = tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4033
&tmp, si_pi->sram_end);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4037
si_pi->fan_table_start = tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4042
&tmp, si_pi->sram_end);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4046
si_pi->arb_table_start = tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4051
&tmp, si_pi->sram_end);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4055
si_pi->cac_table_start = tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4060
&tmp, si_pi->sram_end);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4064
si_pi->dte_table_start = tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4069
&tmp, si_pi->sram_end);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4073
si_pi->spll_table_start = tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4078
&tmp, si_pi->sram_end);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4082
si_pi->papm_cfg_table_start = tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4191
u32 tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4195
tmp = 0x10;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4197
tmp = 0x1;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4200
WREG32_P(mmMISC_CLK_CNTL, (tmp << MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL__SHIFT), ~MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL_MASK);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4209
u32 tmp, pipe;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4211
tmp = RREG32(mmCG_DISPLAY_GAP_CNTL) & ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MASK);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4213
tmp |= R600_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4215
tmp |= R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4218
tmp |= R600_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4220
tmp |= R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4222
WREG32(mmCG_DISPLAY_GAP_CNTL, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4224
tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4225
pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4230
tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4231
tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4232
WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4316
u32 tmp = RREG32(mmCG_DISPLAY_GAP_CNTL);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4318
tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MASK);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4319
tmp |= (R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT |
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4322
tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MCHG_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MCHG_MASK);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4323
tmp |= (R600_PM_DISPLAY_GAP_VBLANK << CG_DISPLAY_GAP_CNTL__DISP1_GAP_MCHG__SHIFT |
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4325
WREG32(mmCG_DISPLAY_GAP_CNTL, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4743
u32 tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4747
&tmp, si_pi->sram_end);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4751
tmp &= 0x00FFFFFF;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4752
tmp |= MC_CG_ARB_FREQ_F1 << 24;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4755
tmp, si_pi->sram_end);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4772
u32 tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4776
&tmp, si_pi->sram_end);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4780
tmp = (tmp >> 24) & 0xff;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4782
if (tmp == MC_CG_ARB_FREQ_F0)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4785
return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4794
u32 tmp = (RREG32(mmMC_ARB_RAMCFG) & MC_ARB_RAMCFG__NOOFROWS_MASK) >> MC_ARB_RAMCFG__NOOFROWS__SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4796
if (tmp >= 4)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4799
dram_rows = 1 << (tmp + 10);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5339
u64 tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5352
tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5353
do_div(tmp, reference_clock);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5354
fbdiv = (u32) tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5461
u32 tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5469
tmp = freq_nom / reference_clock;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5470
tmp = tmp * tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5474
u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6515
u32 tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6518
tmp = (RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK) >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6519
si_pi->fan_ctrl_default_mode = tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6520
tmp = (RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK) >> CG_FDO_CTRL2__TMIN__SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6521
si_pi->t_min = tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6525
tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6526
tmp |= 0 << CG_FDO_CTRL2__TMIN__SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6527
WREG32(mmCG_FDO_CTRL2, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6529
tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6530
tmp |= mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6531
WREG32(mmCG_FDO_CTRL2, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6541
u32 reference_clock, tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6586
tmp = (RREG32(mmCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK) >> CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6587
fan_table.temp_src = (uint8_t)tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6663
u32 tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6685
tmp = RREG32(mmCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6686
tmp |= duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6687
WREG32(mmCG_FDO_CTRL0, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6719
u32 tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6727
tmp = RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6728
*fan_mode = (tmp >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6758
u32 tach_period, tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6775
tmp = RREG32(mmCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6776
tmp |= tach_period << CG_TACH_CTRL__TARGET_PERIOD__SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6777
WREG32(mmCG_TACH_CTRL, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6788
u32 tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6791
tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6792
tmp |= si_pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6793
WREG32(mmCG_FDO_CTRL2, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6795
tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6796
tmp |= si_pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6797
WREG32(mmCG_FDO_CTRL2, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6812
u32 tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6815
tmp = RREG32(mmCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6816
tmp |= (adev->pm.fan_pulses_per_revolution -1) << CG_TACH_CTRL__EDGE_PER_REV__SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6817
WREG32(mmCG_TACH_CTRL, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6820
tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6821
tmp |= 0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6822
WREG32(mmCG_FDO_CTRL2, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
119
u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
121
tmp &= ~RST_REG;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
123
WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
128
u32 tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
135
tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL) |
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
137
WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
149
u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
152
tmp &= ~CK_DISABLE;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
154
tmp |= CK_DISABLE;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
156
WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
173
u32 tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
197
tmp = RREG32(mmSMC_RESP_0);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
198
if (tmp != 0)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
203
tmp = RREG32(mmSMC_RESP_0);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
204
if (tmp == 0) {
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
210
return (PPSMC_Result)tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
215
u32 tmp;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
222
tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
223
if ((tmp & CKEN) == 0)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c
681
unsigned long tmp;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c
691
tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c
694
ps->validation.singleDisplayOnly = (0 != tmp);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c
696
tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c
699
ps->validation.disallowOnDC = (0 != tmp);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c
724
tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c
727
ps->display.enableVariBright = (0 != tmp);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c
729
tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c
732
ps->memory.dllOff = (0 != tmp);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c
743
tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c
746
ps->software.disableLoadBalancing = tmp;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c
748
tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c
751
ps->software.enableSleepForTimestamps = (0 != tmp);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2787
int tmp;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2789
tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2790
if (tmp)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2793
tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_mclk);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2794
if (tmp)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2797
tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2798
if (tmp)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2801
tmp = smu7_patch_vddci(hwmgr, hwmgr->dyn_state.vddci_dependency_on_mclk);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2802
if (tmp)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2805
tmp = smu7_patch_vce_vddc(hwmgr, hwmgr->dyn_state.vce_clock_voltage_dependency_table);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2806
if (tmp)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2809
tmp = smu7_patch_uvd_vddc(hwmgr, hwmgr->dyn_state.uvd_clock_voltage_dependency_table);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2810
if (tmp)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2813
tmp = smu7_patch_samu_vddc(hwmgr, hwmgr->dyn_state.samu_clock_voltage_dependency_table);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2814
if (tmp)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2817
tmp = smu7_patch_acp_vddc(hwmgr, hwmgr->dyn_state.acp_clock_voltage_dependency_table);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2818
if (tmp)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2821
tmp = smu7_patch_vddc_shed_limit(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2822
if (tmp)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2825
tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_ac);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2826
if (tmp)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2829
tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_dc);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2830
if (tmp)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2833
tmp = smu7_patch_cac_vddc(hwmgr, hwmgr->dyn_state.cac_leakage_table);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2834
if (tmp)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3033
uint32_t level, tmp;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3038
tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3039
while (tmp >>= 1)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3052
tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3053
while (tmp >>= 1)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3067
tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3068
while (tmp >>= 1)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
322
uint32_t tmp;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
391
tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDC);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
393
(data->vddc_voltage_table.count <= tmp),
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
395
phm_trim_voltage_table_to_fit_state_table(tmp,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3956
u32 tmp = 0;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3972
smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetCurrPkgPwr, 0, &tmp);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3973
*query = tmp;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3975
if (tmp != 0)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
398
tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3986
tmp = cgs_read_ind_register(hwmgr->device,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3989
if (tmp != 0)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3992
*query = tmp;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
400
(data->vddgfx_voltage_table.count <= tmp),
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
402
phm_trim_voltage_table_to_fit_state_table(tmp,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
405
tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDCI);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
407
(data->vddci_voltage_table.count <= tmp),
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
409
phm_trim_voltage_table_to_fit_state_table(tmp,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
412
tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_MVDD);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
414
(data->mvdd_voltage_table.count <= tmp),
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
416
phm_trim_voltage_table_to_fit_state_table(tmp,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
4759
uint32_t tmp;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
4772
tmp = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
4774
if (tmp & (1 << 23)) {
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
4943
uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
4946
if (fls(tmp) != ffs(tmp))
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
4952
fls(tmp) - 1,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5622
uint32_t tmp, level;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5627
tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5628
while (tmp >>= 1)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5641
struct profile_mode_setting tmp;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5656
tmp = smu7_profiling[PP_SMC_POWER_PROFILE_CUSTOM];
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5658
if (tmp.bupdate_sclk == 0 && tmp.bupdate_mclk == 0)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5661
tmp.bupdate_sclk = input[0];
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5662
tmp.sclk_up_hyst = input[1];
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5663
tmp.sclk_down_hyst = input[2];
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5664
tmp.sclk_activity = input[3];
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5665
tmp.bupdate_mclk = input[4];
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5666
tmp.mclk_up_hyst = input[5];
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5667
tmp.mclk_down_hyst = input[6];
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5668
tmp.mclk_activity = input[7];
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5669
smu7_profiling[PP_SMC_POWER_PROFILE_CUSTOM] = tmp;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5671
if (!smum_update_dpm_settings(hwmgr, &tmp)) {
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5672
memcpy(&data->current_profile_setting, &tmp, sizeof(struct profile_mode_setting));
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5684
memcpy(&tmp, &smu7_profiling[mode], sizeof(struct profile_mode_setting));
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5685
if (!smum_update_dpm_settings(hwmgr, &tmp)) {
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5686
if (tmp.bupdate_sclk) {
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5687
data->current_profile_setting.bupdate_sclk = tmp.bupdate_sclk;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5688
data->current_profile_setting.sclk_up_hyst = tmp.sclk_up_hyst;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5689
data->current_profile_setting.sclk_down_hyst = tmp.sclk_down_hyst;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5690
data->current_profile_setting.sclk_activity = tmp.sclk_activity;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5692
if (tmp.bupdate_mclk) {
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5693
data->current_profile_setting.bupdate_mclk = tmp.bupdate_mclk;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5694
data->current_profile_setting.mclk_up_hyst = tmp.mclk_up_hyst;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5695
data->current_profile_setting.mclk_down_hyst = tmp.mclk_down_hyst;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5696
data->current_profile_setting.mclk_activity = tmp.mclk_activity;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
579
uint32_t tmp;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
581
tmp = (cgs_read_ind_register(hwmgr->device,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
585
if (tmp == MC_CG_ARB_FREQ_F0)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
589
tmp, MC_CG_ARB_FREQ_F0);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
643
uint32_t tmp;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
661
tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_LINK);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
663
tmp,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
671
max_entry = (tmp < pcie_table->count) ? tmp : pcie_table->count;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
1746
uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
1764
tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) &
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
1766
vddnb = smu8_convert_8Bit_index_to_voltage(hwmgr, tmp) / 4;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
1770
tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) &
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
1772
vddgfx = smu8_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp) / 4;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
970
uint32_t tmp;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
977
tmp = table.mask_low;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
979
if (tmp & 1) {
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
984
tmp >>= 1;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
1073
uint32_t tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
1083
tmp = (freq_nom / reference_clock);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
1084
tmp = tmp * tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
1090
ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2373
uint32_t tmp = 0;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2383
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2386
ci_data->dpm_table_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2393
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2396
data->soft_regs_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2397
ci_data->soft_regs_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2405
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2408
ci_data->mc_reg_table_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2413
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2416
ci_data->fan_table_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2423
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2426
ci_data->arb_table_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2433
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2436
hwmgr->microcode_version_info.SMC = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2777
uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2795
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2796
tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2797
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2809
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2810
tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpH, sizeof(uint8_t));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2811
tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownH, sizeof(uint8_t));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2812
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2830
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2831
tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2832
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2844
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2845
tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpH, sizeof(uint8_t));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2846
tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownH, sizeof(uint8_t));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2847
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
563
uint16_t tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
568
tmp = hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
570
tmp = hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
572
smu_data->power_tune_table.FuzzyFan_PwmSetDelta = CONVERT_FROM_HOST_TO_SMC_US(tmp);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
1864
uint32_t tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
1876
smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
1881
tmp &= 0x00FFFFFF;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
1882
tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
1885
smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
1899
u32 tmp = param_led_dpm.mask_low;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
1902
if (tmp & 1) {
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
1907
tmp >>= 1;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2450
uint32_t tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2457
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2460
smu_data->smu7_data.dpm_table_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2467
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2470
data->soft_regs_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2471
smu_data->smu7_data.soft_regs_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2479
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2482
smu_data->smu7_data.mc_reg_table_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2487
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2490
smu_data->smu7_data.fan_table_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2497
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2500
smu_data->smu7_data.arb_table_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2507
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2510
hwmgr->microcode_version_info.SMC = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2564
uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2582
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2583
tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2584
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2596
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2597
tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2598
tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2599
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2617
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2618
tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2619
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2631
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2632
tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2633
tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2634
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
420
uint32_t tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
421
tmp = raw_setting * 4096 / 100;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
422
return (uint16_t)tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
1114
uint32_t tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
1124
tmp = (freq_nom / reference_clock);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
1125
tmp = tmp * tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
1138
ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2283
uint32_t tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2290
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2293
smu7_data->dpm_table_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2301
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2304
data->soft_regs_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2305
smu7_data->soft_regs_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2314
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2317
smu7_data->mc_reg_table_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2323
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2326
smu7_data->fan_table_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2334
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2337
smu7_data->arb_table_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2346
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2349
hwmgr->microcode_version_info.SMC = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2357
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2360
smu7_data->ulv_setting_starts = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
1780
uint32_t tmp, i;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
1870
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
1873
tmp,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
1880
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
1882
tmp,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2496
uint32_t tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2503
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2506
smu_data->smu7_data.dpm_table_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2513
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2516
data->soft_regs_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2517
smu_data->smu7_data.soft_regs_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2525
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2528
smu_data->smu7_data.mc_reg_table_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2533
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2536
smu_data->smu7_data.fan_table_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2543
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2546
smu_data->smu7_data.arb_table_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2553
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2556
hwmgr->microcode_version_info.SMC = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2602
uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2620
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2621
tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2622
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2634
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2635
tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2636
tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2637
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2655
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2656
tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2657
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2669
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2670
tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2671
tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2672
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
422
uint32_t tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
423
tmp = raw_setting * 4096 / 100;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
424
return (uint16_t)tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
177
uint32_t tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
191
tmp = cgs_read_register(hwmgr->device,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
193
tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
194
tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
195
cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, tmp);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
197
tmp = cgs_read_register(hwmgr->device,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
200
tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
201
tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ATC, 0);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
202
tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
203
tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
204
cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_CNTL, tmp);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
1800
uint32_t tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
1813
smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
1818
tmp &= 0x00FFFFFF;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
1819
tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
1822
smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2762
uint32_t tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2769
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2772
smu_data->smu7_data.dpm_table_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2779
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2782
data->soft_regs_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2783
smu_data->smu7_data.soft_regs_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2792
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2795
smu_data->smu7_data.mc_reg_table_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2800
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2803
smu_data->smu7_data.fan_table_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2810
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2813
smu_data->smu7_data.arb_table_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2820
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2823
hwmgr->microcode_version_info.SMC = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3163
uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3181
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3182
tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3183
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3195
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3196
tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3197
tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3198
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3216
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3217
tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3218
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3230
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3231
tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3232
tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3233
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
866
uint32_t tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
876
tmp = (freq_nom / reference_clock);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
877
tmp = tmp * tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
890
ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1433
uint32_t tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1434
tmp = raw_setting * 4096 / 100;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1435
return (uint16_t)tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1571
uint32_t tmp, i;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1639
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1641
tmp,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1649
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1651
tmp,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
229
uint32_t tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
236
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
239
smu_data->smu7_data.dpm_table_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
246
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
249
data->soft_regs_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
250
smu_data->smu7_data.soft_regs_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
258
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
261
smu_data->smu7_data.mc_reg_table_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
266
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
269
smu_data->smu7_data.fan_table_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
276
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
279
smu_data->smu7_data.arb_table_start = tmp;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
286
&tmp, SMC_RAM_END);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
289
hwmgr->microcode_version_info.SMC = tmp;
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
2220
uint32_t tmp;
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
2252
tmp = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK));
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
2253
tmp &= RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK;
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
2255
aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h
48
struct gpu_metrics_v##frev##_##crev *tmp = (ptr); \
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h
50
(struct metrics_table_header *)tmp; \
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h
51
memset(header, 0xFF, sizeof(*tmp)); \
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h
54
header->structure_size = sizeof(*tmp); \
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h
61
struct amdgpu_partition_metrics_v##fr##_##cr *tmp = (ptr); \
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h
63
(struct metrics_table_header *)tmp; \
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h
64
memset(header, 0xFF, sizeof(*tmp)); \
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h
67
header->structure_size = sizeof(*tmp); \
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h
74
struct amdgpu_baseboard_temp_metrics_v##fr##_##cr *tmp = (ptr); \
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h
76
(struct metrics_table_header *)tmp; \
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h
77
memset(header, 0xFF, sizeof(*tmp)); \
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h
80
header->structure_size = sizeof(*tmp); \
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h
87
struct amdgpu_gpuboard_temp_metrics_v##fr##_##cr *tmp = (ptr); \
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h
89
(struct metrics_table_header *)tmp; \
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h
90
memset(header, 0xFF, sizeof(*tmp)); \
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h
93
header->structure_size = sizeof(*tmp); \
sys/dev/pci/drm/display/drm_dp_dual_mode_helper.c
376
uint8_t tmp;
sys/dev/pci/drm/display/drm_dp_dual_mode_helper.c
387
&tmp, sizeof(tmp));
sys/dev/pci/drm/display/drm_dp_dual_mode_helper.c
395
if (tmp == tmds_oen)
sys/dev/pci/drm/display/drm_dp_mst_topology.c
2932
struct drm_dp_mst_port *port, *tmp;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
2987
list_for_each_entry_safe(port, tmp, &mstb->ports, next) {
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5180
struct drm_dp_mst_atomic_payload *pos, *tmp;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5183
list_for_each_entry_safe(pos, tmp, &mst_state->payloads, next) {
sys/dev/pci/drm/dma-resv.c
74
long tmp;
sys/dev/pci/drm/dma-resv.c
76
tmp = (long)rcu_dereference_check(list->table[index],
sys/dev/pci/drm/dma-resv.c
78
*fence = (struct dma_fence *)(tmp & ~DMA_RESV_LIST_MASK);
sys/dev/pci/drm/dma-resv.c
80
*usage = tmp & DMA_RESV_LIST_MASK;
sys/dev/pci/drm/dma-resv.c
89
long tmp = ((long)fence) | usage;
sys/dev/pci/drm/dma-resv.c
91
RCU_INIT_POINTER(list->table[index], (struct dma_fence *)tmp);
sys/dev/pci/drm/drm_buddy.c
1300
struct drm_buddy_block *block, *tmp;
sys/dev/pci/drm/drm_buddy.c
1308
rbtree_postorder_for_each_entry_safe(block, tmp, root, rb) {
sys/dev/pci/drm/drm_buddy.c
519
struct drm_buddy_block *block, *tmp;
sys/dev/pci/drm/drm_buddy.c
521
rbtree_postorder_for_each_entry_safe(block, tmp, root, rb) {
sys/dev/pci/drm/drm_buddy.c
757
unsigned int tmp;
sys/dev/pci/drm/drm_buddy.c
767
tmp = drm_buddy_block_order(block);
sys/dev/pci/drm/drm_buddy.c
769
for (tmp = order; tmp <= mm->max_order; ++tmp) {
sys/dev/pci/drm/drm_buddy.c
771
root = &mm->free_trees[tree][tmp];
sys/dev/pci/drm/drm_buddy.c
783
for (tmp = order; tmp <= mm->max_order; ++tmp) {
sys/dev/pci/drm/drm_buddy.c
784
root = &mm->free_trees[tree][tmp];
sys/dev/pci/drm/drm_buddy.c
796
while (tmp != order) {
sys/dev/pci/drm/drm_buddy.c
802
tmp--;
sys/dev/pci/drm/drm_buddy.c
807
if (tmp != order)
sys/dev/pci/drm/drm_cache.c
184
struct resource *tmp;
sys/dev/pci/drm/drm_cache.c
206
for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling)
sys/dev/pci/drm/drm_cache.c
207
max_iomem = max(max_iomem, tmp->end);
sys/dev/pci/drm/drm_client_event.c
34
struct drm_client_dev *client, *tmp;
sys/dev/pci/drm/drm_client_event.c
40
list_for_each_entry_safe(client, tmp, &dev->clientlist, list) {
sys/dev/pci/drm/drm_client_modeset.c
839
struct drm_connector **tmp;
sys/dev/pci/drm/drm_client_modeset.c
842
tmp = krealloc(connectors, (connector_count + 1) * sizeof(*connectors), GFP_KERNEL);
sys/dev/pci/drm/drm_client_modeset.c
843
if (!tmp) {
sys/dev/pci/drm/drm_client_modeset.c
848
tmp = kmalloc((connector_count + 1) * sizeof(*connectors), GFP_KERNEL);
sys/dev/pci/drm/drm_client_modeset.c
849
if (!tmp) {
sys/dev/pci/drm/drm_client_modeset.c
853
memcpy(tmp, connectors, connector_count * sizeof(*connectors));
sys/dev/pci/drm/drm_client_modeset.c
857
connectors = tmp;
sys/dev/pci/drm/drm_crtc.c
590
struct drm_crtc *tmp;
sys/dev/pci/drm/drm_crtc.c
600
drm_for_each_crtc(tmp, crtc->dev) {
sys/dev/pci/drm/drm_crtc.c
601
struct drm_plane *plane = tmp->primary;
sys/dev/pci/drm/drm_crtc.c
616
drm_for_each_crtc(tmp, crtc->dev) {
sys/dev/pci/drm/drm_crtc.c
617
struct drm_plane *plane = tmp->primary;
sys/dev/pci/drm/drm_debugfs.c
253
struct drm_info_node *tmp;
sys/dev/pci/drm/drm_debugfs.c
262
tmp = drmm_kzalloc(dev, sizeof(*tmp), GFP_KERNEL);
sys/dev/pci/drm/drm_debugfs.c
263
if (tmp == NULL)
sys/dev/pci/drm/drm_debugfs.c
266
tmp->minor = minor;
sys/dev/pci/drm/drm_debugfs.c
267
tmp->dent = debugfs_create_file(files[i].name,
sys/dev/pci/drm/drm_debugfs.c
268
0444, root, tmp,
sys/dev/pci/drm/drm_debugfs.c
270
tmp->info_ent = &files[i];
sys/dev/pci/drm/drm_drv.c
2170
unsigned long tmp;
sys/dev/pci/drm/drm_drv.c
2172
for (order = 0, tmp = size; tmp >>= 1; ++order)
sys/dev/pci/drm/drm_edid.c
4538
struct drm_display_mode *mode, *tmp;
sys/dev/pci/drm/drm_edid.c
4597
list_for_each_entry_safe(mode, tmp, &list, head) {
sys/dev/pci/drm/drm_exec.c
148
void *tmp;
sys/dev/pci/drm/drm_exec.c
151
tmp = kvrealloc(exec->objects, size + PAGE_SIZE, GFP_KERNEL);
sys/dev/pci/drm/drm_exec.c
152
if (!tmp)
sys/dev/pci/drm/drm_exec.c
155
tmp = kvmalloc(size + PAGE_SIZE, GFP_KERNEL);
sys/dev/pci/drm/drm_exec.c
156
if (!tmp)
sys/dev/pci/drm/drm_exec.c
158
memcpy(tmp, exec->objects, size);
sys/dev/pci/drm/drm_exec.c
162
exec->objects = tmp;
sys/dev/pci/drm/drm_flip_work.c
109
struct drm_flip_task *task, *tmp;
sys/dev/pci/drm/drm_flip_work.c
120
list_for_each_entry_safe(task, tmp, &tasks, node) {
sys/dev/pci/drm/drm_format_helper.c
102
return state->tmp.mem;
sys/dev/pci/drm/drm_format_helper.c
116
if (state->tmp.preallocated)
sys/dev/pci/drm/drm_format_helper.c
119
kfree(state->tmp.mem);
sys/dev/pci/drm/drm_format_helper.c
120
state->tmp.mem = NULL;
sys/dev/pci/drm/drm_format_helper.c
121
state->tmp.size = 0;
sys/dev/pci/drm/drm_format_helper.c
35
state->tmp.mem = NULL;
sys/dev/pci/drm/drm_format_helper.c
36
state->tmp.size = 0;
sys/dev/pci/drm/drm_format_helper.c
37
state->tmp.preallocated = false;
sys/dev/pci/drm/drm_format_helper.c
56
state->tmp.mem = NULL;
sys/dev/pci/drm/drm_format_helper.c
57
state->tmp.size = 0;
sys/dev/pci/drm/drm_format_helper.c
58
state->tmp.preallocated = false;
sys/dev/pci/drm/drm_format_helper.c
81
if (new_size <= state->tmp.size)
sys/dev/pci/drm/drm_format_helper.c
83
else if (state->tmp.preallocated)
sys/dev/pci/drm/drm_format_helper.c
87
mem = krealloc(state->tmp.mem, new_size, flags);
sys/dev/pci/drm/drm_format_helper.c
94
memcpy(mem, state->tmp.mem, state->tmp.size);
sys/dev/pci/drm/drm_format_helper.c
95
kfree(state->tmp.mem);
sys/dev/pci/drm/drm_format_helper.c
98
state->tmp.mem = mem;
sys/dev/pci/drm/drm_format_helper.c
99
state->tmp.size = new_size;
sys/dev/pci/drm/drm_linux.c
1556
struct notifier_block *tmp;
sys/dev/pci/drm/drm_linux.c
1558
SLIST_FOREACH(tmp, &drm_linux_acpi_notify_list, link) {
sys/dev/pci/drm/drm_linux.c
1559
if (tmp == nb) {
sys/dev/pci/drm/drm_linux.c
1794
struct dma_fence_cb *cur, *tmp;
sys/dev/pci/drm/drm_linux.c
1808
list_for_each_entry_safe(cur, tmp, &cb_list, node) {
sys/dev/pci/drm/drm_linux.c
2533
struct dma_fence *prev, *new_prev, *tmp;
sys/dev/pci/drm/drm_linux.c
2551
tmp = atomic_cas_ptr(&chain->prev, prev, new_prev);
sys/dev/pci/drm/drm_linux.c
2552
dma_fence_put(tmp == prev ? prev : new_prev);
sys/dev/pci/drm/drm_modes.c
642
u64 tmp;
sys/dev/pci/drm/drm_modes.c
803
tmp = drm_mode->htotal; /* perform intermediate calcs in u64 */
sys/dev/pci/drm/drm_modes.c
804
tmp *= HV_FACTOR * 1000;
sys/dev/pci/drm/drm_modes.c
805
do_div(tmp, hperiod);
sys/dev/pci/drm/drm_modes.c
806
tmp -= drm_mode->clock % CVT_CLOCK_STEP;
sys/dev/pci/drm/drm_modes.c
807
drm_mode->clock = tmp;
sys/dev/pci/drm/drm_modeset_helper.c
54
struct drm_connector *connector, *tmp;
sys/dev/pci/drm/drm_modeset_helper.c
60
list_for_each_entry_safe(connector, tmp,
sys/dev/pci/drm/drm_plane.c
176
struct drm_plane *tmp;
sys/dev/pci/drm/drm_plane.c
178
drm_for_each_plane(tmp, dev) {
sys/dev/pci/drm/drm_rect.c
256
struct drm_rect tmp;
sys/dev/pci/drm/drm_rect.c
259
tmp = *r;
sys/dev/pci/drm/drm_rect.c
262
r->x1 = width - tmp.x2;
sys/dev/pci/drm/drm_rect.c
263
r->x2 = width - tmp.x1;
sys/dev/pci/drm/drm_rect.c
267
r->y1 = height - tmp.y2;
sys/dev/pci/drm/drm_rect.c
268
r->y2 = height - tmp.y1;
sys/dev/pci/drm/drm_rect.c
276
tmp = *r;
sys/dev/pci/drm/drm_rect.c
277
r->x1 = tmp.y1;
sys/dev/pci/drm/drm_rect.c
278
r->x2 = tmp.y2;
sys/dev/pci/drm/drm_rect.c
279
r->y1 = width - tmp.x2;
sys/dev/pci/drm/drm_rect.c
280
r->y2 = width - tmp.x1;
sys/dev/pci/drm/drm_rect.c
283
tmp = *r;
sys/dev/pci/drm/drm_rect.c
284
r->x1 = width - tmp.x2;
sys/dev/pci/drm/drm_rect.c
285
r->x2 = width - tmp.x1;
sys/dev/pci/drm/drm_rect.c
286
r->y1 = height - tmp.y2;
sys/dev/pci/drm/drm_rect.c
287
r->y2 = height - tmp.y1;
sys/dev/pci/drm/drm_rect.c
290
tmp = *r;
sys/dev/pci/drm/drm_rect.c
291
r->x1 = height - tmp.y2;
sys/dev/pci/drm/drm_rect.c
292
r->x2 = height - tmp.y1;
sys/dev/pci/drm/drm_rect.c
293
r->y1 = tmp.x1;
sys/dev/pci/drm/drm_rect.c
294
r->y2 = tmp.x2;
sys/dev/pci/drm/drm_rect.c
330
struct drm_rect tmp;
sys/dev/pci/drm/drm_rect.c
336
tmp = *r;
sys/dev/pci/drm/drm_rect.c
337
r->x1 = width - tmp.y2;
sys/dev/pci/drm/drm_rect.c
338
r->x2 = width - tmp.y1;
sys/dev/pci/drm/drm_rect.c
339
r->y1 = tmp.x1;
sys/dev/pci/drm/drm_rect.c
340
r->y2 = tmp.x2;
sys/dev/pci/drm/drm_rect.c
343
tmp = *r;
sys/dev/pci/drm/drm_rect.c
344
r->x1 = width - tmp.x2;
sys/dev/pci/drm/drm_rect.c
345
r->x2 = width - tmp.x1;
sys/dev/pci/drm/drm_rect.c
346
r->y1 = height - tmp.y2;
sys/dev/pci/drm/drm_rect.c
347
r->y2 = height - tmp.y1;
sys/dev/pci/drm/drm_rect.c
350
tmp = *r;
sys/dev/pci/drm/drm_rect.c
351
r->x1 = tmp.y1;
sys/dev/pci/drm/drm_rect.c
352
r->x2 = tmp.y2;
sys/dev/pci/drm/drm_rect.c
353
r->y1 = height - tmp.x2;
sys/dev/pci/drm/drm_rect.c
354
r->y2 = height - tmp.x1;
sys/dev/pci/drm/drm_rect.c
361
tmp = *r;
sys/dev/pci/drm/drm_rect.c
364
r->x1 = width - tmp.x2;
sys/dev/pci/drm/drm_rect.c
365
r->x2 = width - tmp.x1;
sys/dev/pci/drm/drm_rect.c
369
r->y1 = height - tmp.y2;
sys/dev/pci/drm/drm_rect.c
370
r->y2 = height - tmp.y1;
sys/dev/pci/drm/drm_rect.c
57
u64 tmp;
sys/dev/pci/drm/drm_rect.c
65
tmp = mul_u32_u32(src, dst - *clip);
sys/dev/pci/drm/drm_rect.c
72
return DIV_ROUND_UP_ULL(tmp, dst);
sys/dev/pci/drm/drm_rect.c
74
return DIV_ROUND_DOWN_ULL(tmp, dst);
sys/dev/pci/drm/drm_suballoc.c
108
list_for_each_entry_safe(sa, tmp, &sa_manager->olist, olist) {
sys/dev/pci/drm/drm_suballoc.c
131
struct drm_suballoc *sa, *tmp;
sys/dev/pci/drm/drm_suballoc.c
137
list_for_each_entry_safe_from(sa, tmp, &sa_manager->olist, olist) {
sys/dev/pci/drm/drm_suballoc.c
232
size_t soffset, best, tmp;
sys/dev/pci/drm/drm_suballoc.c
267
tmp = sa->soffset;
sys/dev/pci/drm/drm_suballoc.c
268
if (tmp < soffset) {
sys/dev/pci/drm/drm_suballoc.c
270
tmp += sa_manager->size;
sys/dev/pci/drm/drm_suballoc.c
272
tmp -= soffset;
sys/dev/pci/drm/drm_suballoc.c
273
if (tmp < best) {
sys/dev/pci/drm/drm_suballoc.c
275
best = tmp;
sys/dev/pci/drm/drm_suballoc.c
97
struct drm_suballoc *sa, *tmp;
sys/dev/pci/drm/drm_syncobj.c
972
struct dma_fence *tmp, **fences;
sys/dev/pci/drm/drm_syncobj.c
980
dma_fence_chain_for_each(tmp, &chain->base)
sys/dev/pci/drm/drm_syncobj.c
988
dma_fence_chain_for_each(tmp, &chain->base)
sys/dev/pci/drm/drm_syncobj.c
989
fences[count++] = dma_fence_get(tmp);
sys/dev/pci/drm/i915/display/g4x_dp.c
341
u32 tmp, flags = 0;
sys/dev/pci/drm/i915/display/g4x_dp.c
350
tmp = intel_de_read(display, intel_dp->output_reg);
sys/dev/pci/drm/i915/display/g4x_dp.c
352
pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
sys/dev/pci/drm/i915/display/g4x_dp.c
371
if (tmp & DP_ENHANCED_FRAMING)
sys/dev/pci/drm/i915/display/g4x_dp.c
374
if (tmp & DP_SYNC_HS_HIGH)
sys/dev/pci/drm/i915/display/g4x_dp.c
379
if (tmp & DP_SYNC_VS_HIGH)
sys/dev/pci/drm/i915/display/g4x_dp.c
387
if (display->platform.g4x && tmp & DP_COLOR_RANGE_16_235)
sys/dev/pci/drm/i915/display/g4x_dp.c
390
pipe_config->lane_count = REG_FIELD_GET(DP_PORT_WIDTH_MASK, tmp) + 1;
sys/dev/pci/drm/i915/display/g4x_hdmi.c
155
u32 tmp, flags = 0;
sys/dev/pci/drm/i915/display/g4x_hdmi.c
160
tmp = intel_de_read(display, intel_hdmi->hdmi_reg);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
162
if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
sys/dev/pci/drm/i915/display/g4x_hdmi.c
167
if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
sys/dev/pci/drm/i915/display/g4x_hdmi.c
172
if (tmp & HDMI_MODE_SELECT_HDMI)
sys/dev/pci/drm/i915/display/g4x_hdmi.c
181
if (tmp & HDMI_AUDIO_ENABLE)
sys/dev/pci/drm/i915/display/g4x_hdmi.c
185
tmp & HDMI_COLOR_RANGE_16_235)
sys/dev/pci/drm/i915/display/g4x_hdmi.c
190
if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
sys/dev/pci/drm/i915/display/i9xx_wm.c
3511
u32 tmp = hw->wm_pipe[pipe];
sys/dev/pci/drm/i915/display/i9xx_wm.c
3520
active->wm[0].pri_val = REG_FIELD_GET(WM0_PIPE_PRIMARY_MASK, tmp);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3521
active->wm[0].spr_val = REG_FIELD_GET(WM0_PIPE_SPRITE_MASK, tmp);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3522
active->wm[0].cur_val = REG_FIELD_GET(WM0_PIPE_CURSOR_MASK, tmp);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3668
u32 tmp;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3670
tmp = intel_de_read(display, DSPFW1(display));
sys/dev/pci/drm/i915/display/i9xx_wm.c
3671
wm->sr.plane = _FW_WM(tmp, SR);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3672
wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3673
wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3674
wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3676
tmp = intel_de_read(display, DSPFW2(display));
sys/dev/pci/drm/i915/display/i9xx_wm.c
3677
wm->fbc_en = tmp & DSPFW_FBC_SR_EN;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3678
wm->sr.fbc = _FW_WM(tmp, FBC_SR);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3679
wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3680
wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3681
wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3682
wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3684
tmp = intel_de_read(display, DSPFW3(display));
sys/dev/pci/drm/i915/display/i9xx_wm.c
3685
wm->hpll_en = tmp & DSPFW_HPLL_SR_EN;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3686
wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3687
wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3688
wm->hpll.plane = _FW_WM(tmp, HPLL_SR);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3695
u32 tmp;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3698
tmp = intel_de_read(display, VLV_DDL(pipe));
sys/dev/pci/drm/i915/display/i9xx_wm.c
3701
(tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3703
(tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3705
(tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3707
(tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3710
tmp = intel_de_read(display, DSPFW1(display));
sys/dev/pci/drm/i915/display/i9xx_wm.c
3711
wm->sr.plane = _FW_WM(tmp, SR);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3712
wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3713
wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3714
wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3716
tmp = intel_de_read(display, DSPFW2(display));
sys/dev/pci/drm/i915/display/i9xx_wm.c
3717
wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3718
wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3719
wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3721
tmp = intel_de_read(display, DSPFW3(display));
sys/dev/pci/drm/i915/display/i9xx_wm.c
3722
wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3725
tmp = intel_de_read(display, DSPFW7_CHV);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3726
wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3727
wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3729
tmp = intel_de_read(display, DSPFW8_CHV);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3730
wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3731
wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3733
tmp = intel_de_read(display, DSPFW9_CHV);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3734
wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3735
wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3737
tmp = intel_de_read(display, DSPHOWM);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3738
wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3739
wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3740
wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3741
wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3742
wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3743
wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3744
wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3745
wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3746
wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3747
wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3749
tmp = intel_de_read(display, DSPFW7);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3750
wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3751
wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3753
tmp = intel_de_read(display, DSPHOWM);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3754
wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3755
wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3756
wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3757
wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3758
wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3759
wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3760
wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
sys/dev/pci/drm/i915/display/icl_dsi.c
1110
u32 tmp;
sys/dev/pci/drm/i915/display/icl_dsi.c
1120
tmp = intel_de_read(display, UTIL_PIN_CTL);
sys/dev/pci/drm/i915/display/icl_dsi.c
1123
tmp |= UTIL_PIN_DIRECTION_INPUT;
sys/dev/pci/drm/i915/display/icl_dsi.c
1124
tmp |= UTIL_PIN_ENABLE;
sys/dev/pci/drm/i915/display/icl_dsi.c
1126
tmp &= ~UTIL_PIN_ENABLE;
sys/dev/pci/drm/i915/display/icl_dsi.c
1128
intel_de_write(display, UTIL_PIN_CTL, tmp);
sys/dev/pci/drm/i915/display/icl_dsi.c
1171
u32 tmp;
sys/dev/pci/drm/i915/display/icl_dsi.c
1182
tmp = intel_de_read(display, DSI_CMD_RXCTL(dsi_trans));
sys/dev/pci/drm/i915/display/icl_dsi.c
1183
tmp &= NUMBER_RX_PLOAD_DW_MASK;
sys/dev/pci/drm/i915/display/icl_dsi.c
1185
tmp = tmp * 4;
sys/dev/pci/drm/i915/display/icl_dsi.c
1187
ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
sys/dev/pci/drm/i915/display/icl_dsi.c
1190
"error setting max return pkt size%d\n", tmp);
sys/dev/pci/drm/i915/display/icl_dsi.c
1343
u32 tmp;
sys/dev/pci/drm/i915/display/icl_dsi.c
1356
tmp = intel_de_read(display, DSI_LP_MSG(dsi_trans));
sys/dev/pci/drm/i915/display/icl_dsi.c
1357
tmp |= LINK_ENTER_ULPS;
sys/dev/pci/drm/i915/display/icl_dsi.c
1358
tmp &= ~LINK_ULPS_TYPE_LP11;
sys/dev/pci/drm/i915/display/icl_dsi.c
1359
intel_de_write(display, DSI_LP_MSG(dsi_trans), tmp);
sys/dev/pci/drm/i915/display/icl_dsi.c
1731
u32 tmp;
sys/dev/pci/drm/i915/display/icl_dsi.c
1740
tmp = intel_de_read(display,
sys/dev/pci/drm/i915/display/icl_dsi.c
1742
switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
sys/dev/pci/drm/i915/display/icl_dsi.c
176
u32 tmp = 0;
sys/dev/pci/drm/i915/display/icl_dsi.c
1760
tmp = intel_de_read(display, TRANSCONF(display, dsi_trans));
sys/dev/pci/drm/i915/display/icl_dsi.c
1761
ret = tmp & TRANSCONF_ENABLE;
sys/dev/pci/drm/i915/display/icl_dsi.c
182
tmp |= *data++ << 8 * j;
sys/dev/pci/drm/i915/display/icl_dsi.c
184
intel_de_write(display, DSI_CMD_TXPYLD(dsi_trans), tmp);
sys/dev/pci/drm/i915/display/icl_dsi.c
197
u32 tmp;
sys/dev/pci/drm/i915/display/icl_dsi.c
202
tmp = intel_de_read(display, DSI_CMD_TXHDR(dsi_trans));
sys/dev/pci/drm/i915/display/icl_dsi.c
205
tmp |= PAYLOAD_PRESENT;
sys/dev/pci/drm/i915/display/icl_dsi.c
207
tmp &= ~PAYLOAD_PRESENT;
sys/dev/pci/drm/i915/display/icl_dsi.c
209
tmp &= ~(VBLANK_FENCE | LP_DATA_TRANSFER | PIPELINE_FLUSH);
sys/dev/pci/drm/i915/display/icl_dsi.c
212
tmp |= LP_DATA_TRANSFER;
sys/dev/pci/drm/i915/display/icl_dsi.c
214
tmp |= PIPELINE_FLUSH;
sys/dev/pci/drm/i915/display/icl_dsi.c
216
tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
sys/dev/pci/drm/i915/display/icl_dsi.c
217
tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT);
sys/dev/pci/drm/i915/display/icl_dsi.c
218
tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT);
sys/dev/pci/drm/i915/display/icl_dsi.c
219
tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT);
sys/dev/pci/drm/i915/display/icl_dsi.c
220
tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT);
sys/dev/pci/drm/i915/display/icl_dsi.c
221
intel_de_write(display, DSI_CMD_TXHDR(dsi_trans), tmp);
sys/dev/pci/drm/i915/display/icl_dsi.c
255
u32 tmp, mask, val;
sys/dev/pci/drm/i915/display/icl_dsi.c
266
tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
sys/dev/pci/drm/i915/display/icl_dsi.c
267
tmp &= ~mask;
sys/dev/pci/drm/i915/display/icl_dsi.c
268
tmp |= val;
sys/dev/pci/drm/i915/display/icl_dsi.c
269
intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
sys/dev/pci/drm/i915/display/icl_dsi.c
276
tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));
sys/dev/pci/drm/i915/display/icl_dsi.c
277
tmp &= ~mask;
sys/dev/pci/drm/i915/display/icl_dsi.c
278
tmp |= val;
sys/dev/pci/drm/i915/display/icl_dsi.c
279
intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);
sys/dev/pci/drm/i915/display/icl_dsi.c
445
u32 tmp;
sys/dev/pci/drm/i915/display/icl_dsi.c
461
tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));
sys/dev/pci/drm/i915/display/icl_dsi.c
462
tmp &= ~FRC_LATENCY_OPTIM_MASK;
sys/dev/pci/drm/i915/display/icl_dsi.c
463
tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
sys/dev/pci/drm/i915/display/icl_dsi.c
464
intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);
sys/dev/pci/drm/i915/display/icl_dsi.c
472
tmp = intel_de_read(display,
sys/dev/pci/drm/i915/display/icl_dsi.c
474
tmp &= ~LATENCY_OPTIM_MASK;
sys/dev/pci/drm/i915/display/icl_dsi.c
475
tmp |= LATENCY_OPTIM_VAL(0x1);
sys/dev/pci/drm/i915/display/icl_dsi.c
477
tmp);
sys/dev/pci/drm/i915/display/icl_dsi.c
487
u32 tmp;
sys/dev/pci/drm/i915/display/icl_dsi.c
492
tmp = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));
sys/dev/pci/drm/i915/display/icl_dsi.c
493
tmp &= ~COMMON_KEEPER_EN;
sys/dev/pci/drm/i915/display/icl_dsi.c
494
intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), tmp);
sys/dev/pci/drm/i915/display/icl_dsi.c
509
tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
sys/dev/pci/drm/i915/display/icl_dsi.c
510
tmp &= ~TX_TRAINING_EN;
sys/dev/pci/drm/i915/display/icl_dsi.c
511
intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
sys/dev/pci/drm/i915/display/icl_dsi.c
520
tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
sys/dev/pci/drm/i915/display/icl_dsi.c
521
tmp |= TX_TRAINING_EN;
sys/dev/pci/drm/i915/display/icl_dsi.c
522
intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
sys/dev/pci/drm/i915/display/icl_dsi.c
626
u32 tmp;
sys/dev/pci/drm/i915/display/icl_dsi.c
630
tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
sys/dev/pci/drm/i915/display/icl_dsi.c
632
tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
sys/dev/pci/drm/i915/display/icl_dsi.c
634
intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp);
sys/dev/pci/drm/i915/display/icl_dsi.c
642
u32 tmp;
sys/dev/pci/drm/i915/display/icl_dsi.c
646
tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
sys/dev/pci/drm/i915/display/icl_dsi.c
648
tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
sys/dev/pci/drm/i915/display/icl_dsi.c
650
intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp);
sys/dev/pci/drm/i915/display/icl_dsi.c
660
u32 tmp;
sys/dev/pci/drm/i915/display/icl_dsi.c
662
tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
sys/dev/pci/drm/i915/display/icl_dsi.c
665
if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)))
sys/dev/pci/drm/i915/display/icl_dsi.c
708
u32 tmp;
sys/dev/pci/drm/i915/display/icl_dsi.c
714
tmp = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));
sys/dev/pci/drm/i915/display/icl_dsi.c
717
tmp &= ~EOTP_DISABLED;
sys/dev/pci/drm/i915/display/icl_dsi.c
719
tmp |= EOTP_DISABLED;
sys/dev/pci/drm/i915/display/icl_dsi.c
723
tmp &= ~LINK_CALIBRATION_MASK;
sys/dev/pci/drm/i915/display/icl_dsi.c
724
tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
sys/dev/pci/drm/i915/display/icl_dsi.c
728
tmp &= ~CONTINUOUS_CLK_MASK;
sys/dev/pci/drm/i915/display/icl_dsi.c
730
tmp |= CLK_ENTER_LP_AFTER_DATA;
sys/dev/pci/drm/i915/display/icl_dsi.c
732
tmp |= CLK_HS_CONTINUOUS;
sys/dev/pci/drm/i915/display/icl_dsi.c
735
tmp &= ~PIX_BUF_THRESHOLD_MASK;
sys/dev/pci/drm/i915/display/icl_dsi.c
736
tmp |= PIX_BUF_THRESHOLD_1_4;
sys/dev/pci/drm/i915/display/icl_dsi.c
739
tmp &= ~PIX_VIRT_CHAN_MASK;
sys/dev/pci/drm/i915/display/icl_dsi.c
740
tmp |= PIX_VIRT_CHAN(0);
sys/dev/pci/drm/i915/display/icl_dsi.c
744
tmp |= BGR_TRANSMISSION;
sys/dev/pci/drm/i915/display/icl_dsi.c
747
tmp &= ~PIX_FMT_MASK;
sys/dev/pci/drm/i915/display/icl_dsi.c
749
tmp |= PIX_FMT_COMPRESSED;
sys/dev/pci/drm/i915/display/icl_dsi.c
756
tmp |= PIX_FMT_RGB565;
sys/dev/pci/drm/i915/display/icl_dsi.c
759
tmp |= PIX_FMT_RGB666_PACKED;
sys/dev/pci/drm/i915/display/icl_dsi.c
762
tmp |= PIX_FMT_RGB666_LOOSE;
sys/dev/pci/drm/i915/display/icl_dsi.c
765
tmp |= PIX_FMT_RGB888;
sys/dev/pci/drm/i915/display/icl_dsi.c
772
tmp |= BLANKING_PACKET_ENABLE;
sys/dev/pci/drm/i915/display/icl_dsi.c
777
tmp &= ~OP_MODE_MASK;
sys/dev/pci/drm/i915/display/icl_dsi.c
783
tmp |= VIDEO_MODE_SYNC_EVENT;
sys/dev/pci/drm/i915/display/icl_dsi.c
786
tmp |= VIDEO_MODE_SYNC_PULSE;
sys/dev/pci/drm/i915/display/icl_dsi.c
798
tmp &= ~OP_MODE_MASK;
sys/dev/pci/drm/i915/display/icl_dsi.c
799
tmp |= CMD_MODE_TE_GATE;
sys/dev/pci/drm/i915/display/icl_dsi.c
800
tmp |= TE_SOURCE_GPIO;
sys/dev/pci/drm/i915/display/icl_dsi.c
803
intel_de_write(display, DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
sys/dev/pci/drm/i915/display/icl_dsi.c
823
tmp = intel_de_read(display,
sys/dev/pci/drm/i915/display/icl_dsi.c
825
tmp &= ~TRANS_DDI_PORT_WIDTH_MASK;
sys/dev/pci/drm/i915/display/icl_dsi.c
826
tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count);
sys/dev/pci/drm/i915/display/icl_dsi.c
829
tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
sys/dev/pci/drm/i915/display/icl_dsi.c
835
tmp |= TRANS_DDI_EDP_INPUT_A_ON;
sys/dev/pci/drm/i915/display/icl_dsi.c
838
tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
sys/dev/pci/drm/i915/display/icl_dsi.c
841
tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
sys/dev/pci/drm/i915/display/icl_dsi.c
844
tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF;
sys/dev/pci/drm/i915/display/icl_dsi.c
849
tmp |= TRANS_DDI_FUNC_ENABLE;
sys/dev/pci/drm/i915/display/icl_dsi.c
851
TRANS_DDI_FUNC_CTL(display, dsi_trans), tmp);
sys/dev/pci/drm/i915/display/intel_audio.c
258
u32 tmp;
sys/dev/pci/drm/i915/display/intel_audio.c
260
tmp = intel_de_read(display, G4X_AUD_CNTL_ST);
sys/dev/pci/drm/i915/display/intel_audio.c
262
return REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp);
sys/dev/pci/drm/i915/display/intel_audio.c
271
u32 tmp;
sys/dev/pci/drm/i915/display/intel_audio.c
273
tmp = intel_de_read(display, G4X_AUD_CNTL_ST);
sys/dev/pci/drm/i915/display/intel_audio.c
274
if ((tmp & G4X_ELD_VALID) == 0)
sys/dev/pci/drm/i915/display/intel_audio.c
357
u32 tmp;
sys/dev/pci/drm/i915/display/intel_audio.c
361
tmp = intel_de_read(display, HSW_AUD_CFG(cpu_transcoder));
sys/dev/pci/drm/i915/display/intel_audio.c
362
tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
sys/dev/pci/drm/i915/display/intel_audio.c
363
tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
sys/dev/pci/drm/i915/display/intel_audio.c
364
tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
sys/dev/pci/drm/i915/display/intel_audio.c
365
tmp |= audio_config_hdmi_pixel_clock(crtc_state);
sys/dev/pci/drm/i915/display/intel_audio.c
371
tmp &= ~AUD_CONFIG_N_MASK;
sys/dev/pci/drm/i915/display/intel_audio.c
372
tmp |= AUD_CONFIG_N(n);
sys/dev/pci/drm/i915/display/intel_audio.c
373
tmp |= AUD_CONFIG_N_PROG_ENABLE;
sys/dev/pci/drm/i915/display/intel_audio.c
378
intel_de_write(display, HSW_AUD_CFG(cpu_transcoder), tmp);
sys/dev/pci/drm/i915/display/intel_audio.c
384
tmp = intel_de_read(display, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
sys/dev/pci/drm/i915/display/intel_audio.c
385
tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
sys/dev/pci/drm/i915/display/intel_audio.c
386
tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
sys/dev/pci/drm/i915/display/intel_audio.c
387
intel_de_write(display, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
sys/dev/pci/drm/i915/display/intel_backlight.c
230
u32 tmp;
sys/dev/pci/drm/i915/display/intel_backlight.c
232
tmp = intel_de_read(display, BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
sys/dev/pci/drm/i915/display/intel_backlight.c
233
intel_de_write(display, BLC_PWM_CPU_CTL, tmp | level);
sys/dev/pci/drm/i915/display/intel_backlight.c
241
u32 tmp, mask;
sys/dev/pci/drm/i915/display/intel_backlight.c
262
tmp = intel_de_read(display, BLC_PWM_CTL) & ~mask;
sys/dev/pci/drm/i915/display/intel_backlight.c
263
intel_de_write(display, BLC_PWM_CTL, tmp | level);
sys/dev/pci/drm/i915/display/intel_backlight.c
271
u32 tmp;
sys/dev/pci/drm/i915/display/intel_backlight.c
273
tmp = intel_de_read(display, VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK;
sys/dev/pci/drm/i915/display/intel_backlight.c
274
intel_de_write(display, VLV_BLC_PWM_CTL(pipe), tmp | level);
sys/dev/pci/drm/i915/display/intel_backlight.c
353
u32 tmp;
sys/dev/pci/drm/i915/display/intel_backlight.c
365
tmp = intel_de_read(display, BLC_PWM_CPU_CTL2);
sys/dev/pci/drm/i915/display/intel_backlight.c
366
if (tmp & BLM_PWM_ENABLE) {
sys/dev/pci/drm/i915/display/intel_backlight.c
369
intel_de_write(display, BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE);
sys/dev/pci/drm/i915/display/intel_cdclk.c
358
u8 tmp = 0;
sys/dev/pci/drm/i915/display/intel_cdclk.c
374
tmp = intel_de_read(display, display->platform.pineview ||
sys/dev/pci/drm/i915/display/intel_cdclk.c
377
vco = vco_table[tmp & 0x7];
sys/dev/pci/drm/i915/display/intel_cdclk.c
380
tmp);
sys/dev/pci/drm/i915/display/intel_cdclk.c
397
u16 tmp = 0;
sys/dev/pci/drm/i915/display/intel_cdclk.c
401
pci_read_config_word(pdev, GCFGC, &tmp);
sys/dev/pci/drm/i915/display/intel_cdclk.c
403
cdclk_sel = (tmp >> 4) & 0x7;
sys/dev/pci/drm/i915/display/intel_cdclk.c
432
cdclk_config->vco, tmp);
sys/dev/pci/drm/i915/display/intel_cdclk.c
479
u16 tmp = 0;
sys/dev/pci/drm/i915/display/intel_cdclk.c
483
pci_read_config_word(pdev, GCFGC, &tmp);
sys/dev/pci/drm/i915/display/intel_cdclk.c
485
cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
sys/dev/pci/drm/i915/display/intel_cdclk.c
511
cdclk_config->vco, tmp);
sys/dev/pci/drm/i915/display/intel_cdclk.c
520
u16 tmp = 0;
sys/dev/pci/drm/i915/display/intel_cdclk.c
524
pci_read_config_word(pdev, GCFGC, &tmp);
sys/dev/pci/drm/i915/display/intel_cdclk.c
526
cdclk_sel = (tmp >> 12) & 0x1;
sys/dev/pci/drm/i915/display/intel_cdclk.c
540
cdclk_config->vco, tmp);
sys/dev/pci/drm/i915/display/intel_color.c
1068
u32 tmp;
sys/dev/pci/drm/i915/display/intel_color.c
1070
tmp = intel_de_read(display, DSPCNTR(display, i9xx_plane));
sys/dev/pci/drm/i915/display/intel_color.c
1072
if (tmp & DISP_PIPE_GAMMA_ENABLE)
sys/dev/pci/drm/i915/display/intel_color.c
1075
if (!HAS_GMCH(display) && tmp & DISP_PIPE_CSC_ENABLE)
sys/dev/pci/drm/i915/display/intel_color.c
1093
u32 tmp;
sys/dev/pci/drm/i915/display/intel_color.c
1098
tmp = intel_de_read(display, SKL_BOTTOM_COLOR(crtc->pipe));
sys/dev/pci/drm/i915/display/intel_color.c
1100
if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
sys/dev/pci/drm/i915/display/intel_color.c
1103
if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
sys/dev/pci/drm/i915/display/intel_color.c
259
u32 tmp;
sys/dev/pci/drm/i915/display/intel_color.c
265
tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_RY_GY(pipe));
sys/dev/pci/drm/i915/display/intel_color.c
266
csc->coeff[0] = tmp >> 16;
sys/dev/pci/drm/i915/display/intel_color.c
267
csc->coeff[1] = tmp & 0xffff;
sys/dev/pci/drm/i915/display/intel_color.c
268
tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_BY(pipe));
sys/dev/pci/drm/i915/display/intel_color.c
269
csc->coeff[2] = tmp >> 16;
sys/dev/pci/drm/i915/display/intel_color.c
271
tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_RU_GU(pipe));
sys/dev/pci/drm/i915/display/intel_color.c
272
csc->coeff[3] = tmp >> 16;
sys/dev/pci/drm/i915/display/intel_color.c
273
csc->coeff[4] = tmp & 0xffff;
sys/dev/pci/drm/i915/display/intel_color.c
274
tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_BU(pipe));
sys/dev/pci/drm/i915/display/intel_color.c
275
csc->coeff[5] = tmp >> 16;
sys/dev/pci/drm/i915/display/intel_color.c
277
tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_RV_GV(pipe));
sys/dev/pci/drm/i915/display/intel_color.c
278
csc->coeff[6] = tmp >> 16;
sys/dev/pci/drm/i915/display/intel_color.c
279
csc->coeff[7] = tmp & 0xffff;
sys/dev/pci/drm/i915/display/intel_color.c
280
tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_BV(pipe));
sys/dev/pci/drm/i915/display/intel_color.c
281
csc->coeff[8] = tmp >> 16;
sys/dev/pci/drm/i915/display/intel_color.c
362
u32 tmp;
sys/dev/pci/drm/i915/display/intel_color.c
368
tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe));
sys/dev/pci/drm/i915/display/intel_color.c
369
csc->coeff[0] = tmp >> 16;
sys/dev/pci/drm/i915/display/intel_color.c
370
csc->coeff[1] = tmp & 0xffff;
sys/dev/pci/drm/i915/display/intel_color.c
371
tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_BY(pipe));
sys/dev/pci/drm/i915/display/intel_color.c
372
csc->coeff[2] = tmp >> 16;
sys/dev/pci/drm/i915/display/intel_color.c
374
tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe));
sys/dev/pci/drm/i915/display/intel_color.c
375
csc->coeff[3] = tmp >> 16;
sys/dev/pci/drm/i915/display/intel_color.c
376
csc->coeff[4] = tmp & 0xffff;
sys/dev/pci/drm/i915/display/intel_color.c
377
tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_BU(pipe));
sys/dev/pci/drm/i915/display/intel_color.c
378
csc->coeff[5] = tmp >> 16;
sys/dev/pci/drm/i915/display/intel_color.c
380
tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe));
sys/dev/pci/drm/i915/display/intel_color.c
381
csc->coeff[6] = tmp >> 16;
sys/dev/pci/drm/i915/display/intel_color.c
382
csc->coeff[7] = tmp & 0xffff;
sys/dev/pci/drm/i915/display/intel_color.c
383
tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_BV(pipe));
sys/dev/pci/drm/i915/display/intel_color.c
384
csc->coeff[8] = tmp >> 16;
sys/dev/pci/drm/i915/display/intel_color.c
663
u32 tmp;
sys/dev/pci/drm/i915/display/intel_color.c
665
tmp = intel_de_read_fw(display, PIPE_WGC_C01_C00(display, pipe));
sys/dev/pci/drm/i915/display/intel_color.c
666
csc->coeff[0] = tmp & 0xffff;
sys/dev/pci/drm/i915/display/intel_color.c
667
csc->coeff[1] = tmp >> 16;
sys/dev/pci/drm/i915/display/intel_color.c
669
tmp = intel_de_read_fw(display, PIPE_WGC_C02(display, pipe));
sys/dev/pci/drm/i915/display/intel_color.c
670
csc->coeff[2] = tmp & 0xffff;
sys/dev/pci/drm/i915/display/intel_color.c
672
tmp = intel_de_read_fw(display, PIPE_WGC_C11_C10(display, pipe));
sys/dev/pci/drm/i915/display/intel_color.c
673
csc->coeff[3] = tmp & 0xffff;
sys/dev/pci/drm/i915/display/intel_color.c
674
csc->coeff[4] = tmp >> 16;
sys/dev/pci/drm/i915/display/intel_color.c
676
tmp = intel_de_read_fw(display, PIPE_WGC_C12(display, pipe));
sys/dev/pci/drm/i915/display/intel_color.c
677
csc->coeff[5] = tmp & 0xffff;
sys/dev/pci/drm/i915/display/intel_color.c
679
tmp = intel_de_read_fw(display, PIPE_WGC_C21_C20(display, pipe));
sys/dev/pci/drm/i915/display/intel_color.c
680
csc->coeff[6] = tmp & 0xffff;
sys/dev/pci/drm/i915/display/intel_color.c
681
csc->coeff[7] = tmp >> 16;
sys/dev/pci/drm/i915/display/intel_color.c
683
tmp = intel_de_read_fw(display, PIPE_WGC_C22(display, pipe));
sys/dev/pci/drm/i915/display/intel_color.c
684
csc->coeff[8] = tmp & 0xffff;
sys/dev/pci/drm/i915/display/intel_color.c
761
u32 tmp;
sys/dev/pci/drm/i915/display/intel_color.c
763
tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF01(pipe));
sys/dev/pci/drm/i915/display/intel_color.c
764
csc->coeff[0] = tmp & 0xffff;
sys/dev/pci/drm/i915/display/intel_color.c
765
csc->coeff[1] = tmp >> 16;
sys/dev/pci/drm/i915/display/intel_color.c
767
tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF23(pipe));
sys/dev/pci/drm/i915/display/intel_color.c
768
csc->coeff[2] = tmp & 0xffff;
sys/dev/pci/drm/i915/display/intel_color.c
769
csc->coeff[3] = tmp >> 16;
sys/dev/pci/drm/i915/display/intel_color.c
771
tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF45(pipe));
sys/dev/pci/drm/i915/display/intel_color.c
772
csc->coeff[4] = tmp & 0xffff;
sys/dev/pci/drm/i915/display/intel_color.c
773
csc->coeff[5] = tmp >> 16;
sys/dev/pci/drm/i915/display/intel_color.c
775
tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF67(pipe));
sys/dev/pci/drm/i915/display/intel_color.c
776
csc->coeff[6] = tmp & 0xffff;
sys/dev/pci/drm/i915/display/intel_color.c
777
csc->coeff[7] = tmp >> 16;
sys/dev/pci/drm/i915/display/intel_color.c
779
tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF8(pipe));
sys/dev/pci/drm/i915/display/intel_color.c
780
csc->coeff[8] = tmp & 0xffff;
sys/dev/pci/drm/i915/display/intel_crt.c
131
u32 tmp, flags = 0;
sys/dev/pci/drm/i915/display/intel_crt.c
133
tmp = intel_de_read(display, crt->adpa_reg);
sys/dev/pci/drm/i915/display/intel_crt.c
135
if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
sys/dev/pci/drm/i915/display/intel_crt.c
140
if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
sys/dev/pci/drm/i915/display/intel_ddi.c
1078
u32 tmp;
sys/dev/pci/drm/i915/display/intel_ddi.c
1080
tmp = intel_de_read(display, DISPIO_CR_TX_BMU_CR0);
sys/dev/pci/drm/i915/display/intel_ddi.c
1081
tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
sys/dev/pci/drm/i915/display/intel_ddi.c
1083
tmp |= iboost << BALANCE_LEG_SHIFT(port);
sys/dev/pci/drm/i915/display/intel_ddi.c
1085
tmp |= BALANCE_LEG_DISABLE(port);
sys/dev/pci/drm/i915/display/intel_ddi.c
1086
intel_de_write(display, DISPIO_CR_TX_BMU_CR0, tmp);
sys/dev/pci/drm/i915/display/intel_ddi.c
1826
u32 tmp;
sys/dev/pci/drm/i915/display/intel_ddi.c
1828
tmp = intel_de_read(display, DDI_CLK_SEL(port));
sys/dev/pci/drm/i915/display/intel_ddi.c
1830
if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
sys/dev/pci/drm/i915/display/intel_ddi.c
1879
u32 tmp;
sys/dev/pci/drm/i915/display/intel_ddi.c
1881
tmp = intel_de_read(display, DDI_CLK_SEL(port));
sys/dev/pci/drm/i915/display/intel_ddi.c
1883
if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
sys/dev/pci/drm/i915/display/intel_ddi.c
1886
tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
sys/dev/pci/drm/i915/display/intel_ddi.c
1888
return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
sys/dev/pci/drm/i915/display/intel_ddi.c
1897
u32 tmp;
sys/dev/pci/drm/i915/display/intel_ddi.c
1899
tmp = intel_de_read(display, DDI_CLK_SEL(port));
sys/dev/pci/drm/i915/display/intel_ddi.c
1901
switch (tmp & DDI_CLK_SEL_MASK) {
sys/dev/pci/drm/i915/display/intel_ddi.c
1912
MISSING_CASE(tmp);
sys/dev/pci/drm/i915/display/intel_ddi.c
1995
u32 tmp;
sys/dev/pci/drm/i915/display/intel_ddi.c
1997
tmp = intel_de_read(display, DPLL_CTRL2);
sys/dev/pci/drm/i915/display/intel_ddi.c
2003
if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0)
sys/dev/pci/drm/i915/display/intel_ddi.c
2006
id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
sys/dev/pci/drm/i915/display/intel_ddi.c
2046
u32 tmp;
sys/dev/pci/drm/i915/display/intel_ddi.c
2048
tmp = intel_de_read(display, PORT_CLK_SEL(port));
sys/dev/pci/drm/i915/display/intel_ddi.c
2050
switch (tmp & PORT_CLK_SEL_MASK) {
sys/dev/pci/drm/i915/display/intel_ddi.c
2070
MISSING_CASE(tmp);
sys/dev/pci/drm/i915/display/intel_ddi.c
807
u32 tmp;
sys/dev/pci/drm/i915/display/intel_ddi.c
818
tmp = intel_de_read(display, DDI_BUF_CTL(port));
sys/dev/pci/drm/i915/display/intel_ddi.c
819
if (!(tmp & DDI_BUF_CTL_ENABLE))
sys/dev/pci/drm/i915/display/intel_ddi.c
823
tmp = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_ddi.c
826
switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
sys/dev/pci/drm/i915/display/intel_ddi.c
828
MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
sys/dev/pci/drm/i915/display/intel_ddi.c
863
tmp = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_ddi.c
868
if ((tmp & port_mask) != ddi_select)
sys/dev/pci/drm/i915/display/intel_ddi.c
871
ddi_mode = tmp & TRANS_DDI_MODE_SELECT_MASK;
sys/dev/pci/drm/i915/display/intel_ddi.c
922
tmp = intel_de_read(display, BXT_PHY_CTL(port));
sys/dev/pci/drm/i915/display/intel_ddi.c
923
if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
sys/dev/pci/drm/i915/display/intel_ddi.c
928
encoder->base.base.id, encoder->base.name, tmp);
sys/dev/pci/drm/i915/display/intel_display.c
2844
u32 tmp;
sys/dev/pci/drm/i915/display/intel_display.c
2846
tmp = intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder));
sys/dev/pci/drm/i915/display/intel_display.c
2847
adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
sys/dev/pci/drm/i915/display/intel_display.c
2848
adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
sys/dev/pci/drm/i915/display/intel_display.c
2851
tmp = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_display.c
2853
adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
sys/dev/pci/drm/i915/display/intel_display.c
2854
adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;
sys/dev/pci/drm/i915/display/intel_display.c
2857
tmp = intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder));
sys/dev/pci/drm/i915/display/intel_display.c
2858
adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
sys/dev/pci/drm/i915/display/intel_display.c
2859
adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
sys/dev/pci/drm/i915/display/intel_display.c
2861
tmp = intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder));
sys/dev/pci/drm/i915/display/intel_display.c
2862
adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
sys/dev/pci/drm/i915/display/intel_display.c
2863
adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
sys/dev/pci/drm/i915/display/intel_display.c
2867
tmp = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_display.c
2869
adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
sys/dev/pci/drm/i915/display/intel_display.c
2870
adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;
sys/dev/pci/drm/i915/display/intel_display.c
2872
tmp = intel_de_read(display, TRANS_VSYNC(display, cpu_transcoder));
sys/dev/pci/drm/i915/display/intel_display.c
2873
adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;
sys/dev/pci/drm/i915/display/intel_display.c
2874
adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;
sys/dev/pci/drm/i915/display/intel_display.c
2914
u32 tmp;
sys/dev/pci/drm/i915/display/intel_display.c
2916
tmp = intel_de_read(display, PIPESRC(display, crtc->pipe));
sys/dev/pci/drm/i915/display/intel_display.c
2919
REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1,
sys/dev/pci/drm/i915/display/intel_display.c
2920
REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1);
sys/dev/pci/drm/i915/display/intel_display.c
2996
u32 tmp;
sys/dev/pci/drm/i915/display/intel_display.c
2998
tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));
sys/dev/pci/drm/i915/display/intel_display.c
3000
if (tmp & PIPE_MISC_YUV420_ENABLE) {
sys/dev/pci/drm/i915/display/intel_display.c
3008
(tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0);
sys/dev/pci/drm/i915/display/intel_display.c
3011
} else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) {
sys/dev/pci/drm/i915/display/intel_display.c
3026
u32 tmp;
sys/dev/pci/drm/i915/display/intel_display.c
3033
tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
sys/dev/pci/drm/i915/display/intel_display.c
3034
if (!(tmp & TRANSCONF_ENABLE))
sys/dev/pci/drm/i915/display/intel_display.c
3044
switch (tmp & TRANSCONF_BPC_MASK) {
sys/dev/pci/drm/i915/display/intel_display.c
3055
MISSING_CASE(tmp);
sys/dev/pci/drm/i915/display/intel_display.c
3061
(tmp & TRANSCONF_COLOR_RANGE_SELECT))
sys/dev/pci/drm/i915/display/intel_display.c
3064
pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp);
sys/dev/pci/drm/i915/display/intel_display.c
3066
pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
sys/dev/pci/drm/i915/display/intel_display.c
3069
(tmp & TRANSCONF_WGC_ENABLE))
sys/dev/pci/drm/i915/display/intel_display.c
3075
pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE;
sys/dev/pci/drm/i915/display/intel_display.c
3085
tmp = pipe_config->dpll_hw_state.i9xx.dpll_md;
sys/dev/pci/drm/i915/display/intel_display.c
3087
((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
sys/dev/pci/drm/i915/display/intel_display.c
3091
tmp = pipe_config->dpll_hw_state.i9xx.dpll;
sys/dev/pci/drm/i915/display/intel_display.c
3093
((tmp & SDVO_MULTIPLIER_MASK)
sys/dev/pci/drm/i915/display/intel_display.c
3271
u32 tmp;
sys/dev/pci/drm/i915/display/intel_display.c
3273
tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));
sys/dev/pci/drm/i915/display/intel_display.c
3275
switch (tmp & PIPE_MISC_BPC_MASK) {
sys/dev/pci/drm/i915/display/intel_display.c
3297
MISSING_CASE(tmp);
sys/dev/pci/drm/i915/display/intel_display.c
3368
u32 tmp;
sys/dev/pci/drm/i915/display/intel_display.c
3375
tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
sys/dev/pci/drm/i915/display/intel_display.c
3376
if (!(tmp & TRANSCONF_ENABLE))
sys/dev/pci/drm/i915/display/intel_display.c
3381
switch (tmp & TRANSCONF_BPC_MASK) {
sys/dev/pci/drm/i915/display/intel_display.c
3398
if (tmp & TRANSCONF_COLOR_RANGE_SELECT)
sys/dev/pci/drm/i915/display/intel_display.c
3401
switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) {
sys/dev/pci/drm/i915/display/intel_display.c
3413
pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp);
sys/dev/pci/drm/i915/display/intel_display.c
3415
pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
sys/dev/pci/drm/i915/display/intel_display.c
3417
pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);
sys/dev/pci/drm/i915/display/intel_display.c
3457
u32 tmp = 0;
sys/dev/pci/drm/i915/display/intel_display.c
3462
tmp = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_display.c
3465
return tmp & TRANS_DDI_FUNC_ENABLE;
sys/dev/pci/drm/i915/display/intel_display.c
3487
u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
sys/dev/pci/drm/i915/display/intel_display.c
3489
if (tmp & UNCOMPRESSED_JOINER_PRIMARY)
sys/dev/pci/drm/i915/display/intel_display.c
3491
if (tmp & UNCOMPRESSED_JOINER_SECONDARY)
sys/dev/pci/drm/i915/display/intel_display.c
3516
u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
sys/dev/pci/drm/i915/display/intel_display.c
3518
if (!(tmp & BIG_JOINER_ENABLE))
sys/dev/pci/drm/i915/display/intel_display.c
3521
if (tmp & PRIMARY_BIG_JOINER_ENABLE)
sys/dev/pci/drm/i915/display/intel_display.c
3586
u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
sys/dev/pci/drm/i915/display/intel_display.c
3588
if (!(tmp & ULTRA_JOINER_ENABLE))
sys/dev/pci/drm/i915/display/intel_display.c
3591
if (tmp & PRIMARY_ULTRA_JOINER_ENABLE)
sys/dev/pci/drm/i915/display/intel_display.c
3745
u32 tmp = 0;
sys/dev/pci/drm/i915/display/intel_display.c
3749
tmp = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_display.c
3752
if (!(tmp & TRANS_DDI_FUNC_ENABLE))
sys/dev/pci/drm/i915/display/intel_display.c
3755
switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
sys/dev/pci/drm/i915/display/intel_display.c
3835
u32 tmp;
sys/dev/pci/drm/i915/display/intel_display.c
3855
tmp = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_display.c
3858
if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF)
sys/dev/pci/drm/i915/display/intel_display.c
3862
tmp = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_display.c
3865
return tmp & TRANSCONF_ENABLE;
sys/dev/pci/drm/i915/display/intel_display.c
3875
u32 tmp;
sys/dev/pci/drm/i915/display/intel_display.c
3898
tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port));
sys/dev/pci/drm/i915/display/intel_display.c
3899
if (!(tmp & DPI_ENABLE))
sys/dev/pci/drm/i915/display/intel_display.c
3902
tmp = intel_de_read(display, MIPI_CTRL(display, port));
sys/dev/pci/drm/i915/display/intel_display.c
3903
if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
sys/dev/pci/drm/i915/display/intel_display.c
3933
u32 tmp;
sys/dev/pci/drm/i915/display/intel_display.c
3963
u32 tmp = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_display.c
3966
if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW)
sys/dev/pci/drm/i915/display/intel_display.c
3979
tmp = intel_de_read(display, WM_LINETIME(crtc->pipe));
sys/dev/pci/drm/i915/display/intel_display.c
3980
pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
sys/dev/pci/drm/i915/display/intel_display.c
3983
REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
sys/dev/pci/drm/i915/display/intel_display.c
4005
tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));
sys/dev/pci/drm/i915/display/intel_display.c
4007
pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
sys/dev/pci/drm/i915/display/intel_display.c
733
u32 tmp;
sys/dev/pci/drm/i915/display/intel_display.c
735
tmp = intel_de_read(display, PIPE_CHICKEN(pipe));
sys/dev/pci/drm/i915/display/intel_display.c
742
tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
sys/dev/pci/drm/i915/display/intel_display.c
749
tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
sys/dev/pci/drm/i915/display/intel_display.c
756
tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2;
sys/dev/pci/drm/i915/display/intel_display.c
758
tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
sys/dev/pci/drm/i915/display/intel_display.c
762
tmp |= DG2_RENDER_CCSTAG_4_3_EN;
sys/dev/pci/drm/i915/display/intel_display.c
764
intel_de_write(display, PIPE_CHICKEN(pipe), tmp);
sys/dev/pci/drm/i915/display/intel_display_irq.c
1799
u32 status, enable, tmp;
sys/dev/pci/drm/i915/display/intel_display_irq.c
1801
tmp = intel_de_read(display, DPINVGTT);
sys/dev/pci/drm/i915/display/intel_display_irq.c
1803
enable = tmp >> 16;
sys/dev/pci/drm/i915/display/intel_display_irq.c
1804
status = tmp & 0xffff;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1465
u32 tmp;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1489
tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW28);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1490
tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1492
vlv_dpio_write(display->drm, phy, CHV_CMN_DW28, tmp);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1495
tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW6_CH1);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1496
tmp |= DPIO_DYNPWRDOWNEN_CH1;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1497
vlv_dpio_write(display->drm, phy, CHV_CMN_DW6_CH1, tmp);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1504
tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW30);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1505
tmp |= DPIO_CL2_LDOFUSE_PWRENB;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1506
vlv_dpio_write(display->drm, phy, CHV_CMN_DW30, tmp);
sys/dev/pci/drm/i915/display/intel_dmc.c
1675
u32 tmp = 0, int_vector;
sys/dev/pci/drm/i915/display/intel_dmc.c
1678
tmp = intel_de_read(display, PIPEDMC_INTERRUPT(pipe));
sys/dev/pci/drm/i915/display/intel_dmc.c
1679
intel_de_write(display, PIPEDMC_INTERRUPT(pipe), tmp);
sys/dev/pci/drm/i915/display/intel_dmc.c
1681
if (tmp & PIPEDMC_FLIPQ_PROG_DONE) {
sys/dev/pci/drm/i915/display/intel_dmc.c
1698
if (tmp & PIPEDMC_ATS_FAULT)
sys/dev/pci/drm/i915/display/intel_dmc.c
1701
if (tmp & PIPEDMC_GTT_FAULT)
sys/dev/pci/drm/i915/display/intel_dmc.c
1704
if (tmp & PIPEDMC_ERROR)
sys/dev/pci/drm/i915/display/intel_dmc.c
1710
if (tmp == 0 && int_vector != 0)
sys/dev/pci/drm/i915/display/intel_dmc.c
1712
crtc->base.base.id, crtc->base.name, tmp);
sys/dev/pci/drm/i915/display/intel_dp.c
4114
u8 tmp;
sys/dev/pci/drm/i915/display/intel_dp.c
4122
tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0;
sys/dev/pci/drm/i915/display/intel_dp.c
4125
DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
sys/dev/pci/drm/i915/display/intel_dp.c
4158
tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
sys/dev/pci/drm/i915/display/intel_dp.c
4161
DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
sys/dev/pci/drm/i915/display/intel_dp.c
4166
tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
sys/dev/pci/drm/i915/display/intel_dp.c
4168
if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
sys/dev/pci/drm/i915/display/intel_dp.c
4171
str_enable_disable(tmp));
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
180
u8 tmp;
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
183
if (drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &tmp) != 1) {
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
190
if (!(tmp & INTEL_EDP_HDR_TCON_BRIGHTNESS_AUX_ENABLE)) {
sys/dev/pci/drm/i915/display/intel_dpll.c
1875
u32 tmp;
sys/dev/pci/drm/i915/display/intel_dpll.c
1881
tmp = vlv_dpio_read(display->drm, phy, VLV_PLL_DW17(ch));
sys/dev/pci/drm/i915/display/intel_dpll.c
1882
tmp &= 0xffffff00;
sys/dev/pci/drm/i915/display/intel_dpll.c
1883
tmp |= 0x00000030;
sys/dev/pci/drm/i915/display/intel_dpll.c
1884
vlv_dpio_write(display->drm, phy, VLV_PLL_DW17(ch), tmp);
sys/dev/pci/drm/i915/display/intel_dpll.c
1886
tmp = vlv_dpio_read(display->drm, phy, VLV_REF_DW11);
sys/dev/pci/drm/i915/display/intel_dpll.c
1887
tmp &= 0x00ffffff;
sys/dev/pci/drm/i915/display/intel_dpll.c
1888
tmp |= 0x8c000000;
sys/dev/pci/drm/i915/display/intel_dpll.c
1889
vlv_dpio_write(display->drm, phy, VLV_REF_DW11, tmp);
sys/dev/pci/drm/i915/display/intel_dpll.c
1891
tmp = vlv_dpio_read(display->drm, phy, VLV_PLL_DW17(ch));
sys/dev/pci/drm/i915/display/intel_dpll.c
1892
tmp &= 0xffffff00;
sys/dev/pci/drm/i915/display/intel_dpll.c
1893
vlv_dpio_write(display->drm, phy, VLV_PLL_DW17(ch), tmp);
sys/dev/pci/drm/i915/display/intel_dpll.c
1895
tmp = vlv_dpio_read(display->drm, phy, VLV_REF_DW11);
sys/dev/pci/drm/i915/display/intel_dpll.c
1896
tmp &= 0x00ffffff;
sys/dev/pci/drm/i915/display/intel_dpll.c
1897
tmp |= 0xb0000000;
sys/dev/pci/drm/i915/display/intel_dpll.c
1898
vlv_dpio_write(display->drm, phy, VLV_REF_DW11, tmp);
sys/dev/pci/drm/i915/display/intel_dpll.c
1909
u32 tmp, coreclk;
sys/dev/pci/drm/i915/display/intel_dpll.c
1923
tmp = vlv_dpio_read(display->drm, phy, VLV_PLL_DW16(ch));
sys/dev/pci/drm/i915/display/intel_dpll.c
1924
tmp &= 0x00ffffff;
sys/dev/pci/drm/i915/display/intel_dpll.c
1925
vlv_dpio_write(display->drm, phy, VLV_PLL_DW16(ch), tmp);
sys/dev/pci/drm/i915/display/intel_dpll.c
1931
tmp = DPIO_M1_DIV(clock->m1) |
sys/dev/pci/drm/i915/display/intel_dpll.c
1943
tmp |= DPIO_S1_DIV(DPIO_S1_DIV_HDMIDP);
sys/dev/pci/drm/i915/display/intel_dpll.c
1944
vlv_dpio_write(display->drm, phy, VLV_PLL_DW3(ch), tmp);
sys/dev/pci/drm/i915/display/intel_dpll.c
1946
tmp |= DPIO_ENABLE_CALIBRATION;
sys/dev/pci/drm/i915/display/intel_dpll.c
1947
vlv_dpio_write(display->drm, phy, VLV_PLL_DW3(ch), tmp);
sys/dev/pci/drm/i915/display/intel_dpll.c
2029
u32 tmp, loopfilter, tribuf_calcntr;
sys/dev/pci/drm/i915/display/intel_dpll.c
2057
tmp = vlv_dpio_read(display->drm, phy, CHV_PLL_DW3(ch));
sys/dev/pci/drm/i915/display/intel_dpll.c
2058
tmp &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
sys/dev/pci/drm/i915/display/intel_dpll.c
2059
tmp |= DPIO_CHV_FEEDFWD_GAIN(2);
sys/dev/pci/drm/i915/display/intel_dpll.c
2061
tmp |= DPIO_CHV_FRAC_DIV_EN;
sys/dev/pci/drm/i915/display/intel_dpll.c
2062
vlv_dpio_write(display->drm, phy, CHV_PLL_DW3(ch), tmp);
sys/dev/pci/drm/i915/display/intel_dpll.c
2065
tmp = vlv_dpio_read(display->drm, phy, CHV_PLL_DW9(ch));
sys/dev/pci/drm/i915/display/intel_dpll.c
2066
tmp &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
sys/dev/pci/drm/i915/display/intel_dpll.c
2068
tmp |= DPIO_CHV_INT_LOCK_THRESHOLD(0x5);
sys/dev/pci/drm/i915/display/intel_dpll.c
2070
tmp |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
sys/dev/pci/drm/i915/display/intel_dpll.c
2071
vlv_dpio_write(display->drm, phy, CHV_PLL_DW9(ch), tmp);
sys/dev/pci/drm/i915/display/intel_dpll.c
2098
tmp = vlv_dpio_read(display->drm, phy, CHV_PLL_DW8(ch));
sys/dev/pci/drm/i915/display/intel_dpll.c
2099
tmp &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
sys/dev/pci/drm/i915/display/intel_dpll.c
2100
tmp |= DPIO_CHV_TDC_TARGET_CNT(tribuf_calcntr);
sys/dev/pci/drm/i915/display/intel_dpll.c
2101
vlv_dpio_write(display->drm, phy, CHV_PLL_DW8(ch), tmp);
sys/dev/pci/drm/i915/display/intel_dpll.c
2119
u32 tmp;
sys/dev/pci/drm/i915/display/intel_dpll.c
2124
tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW14(ch));
sys/dev/pci/drm/i915/display/intel_dpll.c
2125
tmp |= DPIO_DCLKP_EN;
sys/dev/pci/drm/i915/display/intel_dpll.c
2126
vlv_dpio_write(display->drm, phy, CHV_CMN_DW14(ch), tmp);
sys/dev/pci/drm/i915/display/intel_dpll.c
397
u32 tmp;
sys/dev/pci/drm/i915/display/intel_dpll.c
401
tmp = display->state.chv_dpll_md[crtc->pipe];
sys/dev/pci/drm/i915/display/intel_dpll.c
403
tmp = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_dpll.c
406
hw_state->dpll_md = tmp;
sys/dev/pci/drm/i915/display/intel_dpll.c
524
u32 tmp;
sys/dev/pci/drm/i915/display/intel_dpll.c
531
tmp = vlv_dpio_read(display->drm, phy, VLV_PLL_DW3(ch));
sys/dev/pci/drm/i915/display/intel_dpll.c
534
clock.m1 = REG_FIELD_GET(DPIO_M1_DIV_MASK, tmp);
sys/dev/pci/drm/i915/display/intel_dpll.c
535
clock.m2 = REG_FIELD_GET(DPIO_M2_DIV_MASK, tmp);
sys/dev/pci/drm/i915/display/intel_dpll.c
536
clock.n = REG_FIELD_GET(DPIO_N_DIV_MASK, tmp);
sys/dev/pci/drm/i915/display/intel_dpll.c
537
clock.p1 = REG_FIELD_GET(DPIO_P1_DIV_MASK, tmp);
sys/dev/pci/drm/i915/display/intel_dpll.c
538
clock.p2 = REG_FIELD_GET(DPIO_P2_DIV_MASK, tmp);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3017
u64 tmp;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3041
tmp = (u64)m2div_rem * (1 << 22);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3042
do_div(tmp, refclk_khz * m1div);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3043
m2div_frac = tmp;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3100
tmp = mul_u32_u32(dco_khz, 47 * 32);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3101
do_div(tmp, refclk_khz * m1div * 10000);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3102
ssc_stepsize = tmp;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3104
tmp = mul_u32_u32(dco_khz, 1000);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3105
ssc_steplen = DIV_ROUND_UP_ULL(tmp, 32 * 2 * 32);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3215
u64 tmp;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3275
tmp = (u64)m1 * m2_int * ref_clock +
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3277
tmp = div_u64(tmp, 5 * div1 * div2);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3279
return tmp;
sys/dev/pci/drm/i915/display/intel_dsb.c
1012
errors = tmp & dsb_error_int_status(display);
sys/dev/pci/drm/i915/display/intel_dsb.c
990
u32 tmp, errors;
sys/dev/pci/drm/i915/display/intel_dsb.c
992
tmp = intel_de_read_fw(display, DSB_INTERRUPT(pipe, dsb_id));
sys/dev/pci/drm/i915/display/intel_dsb.c
993
intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb_id), tmp);
sys/dev/pci/drm/i915/display/intel_dsb.c
995
if (tmp & DSB_PROG_INT_STATUS) {
sys/dev/pci/drm/i915/display/intel_dvo.c
137
u32 tmp;
sys/dev/pci/drm/i915/display/intel_dvo.c
139
tmp = intel_de_read(display, DVO(port));
sys/dev/pci/drm/i915/display/intel_dvo.c
141
if (!(tmp & DVO_ENABLE))
sys/dev/pci/drm/i915/display/intel_dvo.c
152
u32 tmp;
sys/dev/pci/drm/i915/display/intel_dvo.c
154
tmp = intel_de_read(display, DVO(port));
sys/dev/pci/drm/i915/display/intel_dvo.c
156
*pipe = REG_FIELD_GET(DVO_PIPE_SEL_MASK, tmp);
sys/dev/pci/drm/i915/display/intel_dvo.c
158
return tmp & DVO_ENABLE;
sys/dev/pci/drm/i915/display/intel_dvo.c
166
u32 tmp, flags = 0;
sys/dev/pci/drm/i915/display/intel_dvo.c
170
tmp = intel_de_read(display, DVO(port));
sys/dev/pci/drm/i915/display/intel_dvo.c
171
if (tmp & DVO_HSYNC_ACTIVE_HIGH)
sys/dev/pci/drm/i915/display/intel_dvo.c
175
if (tmp & DVO_VSYNC_ACTIVE_HIGH)
sys/dev/pci/drm/i915/display/intel_fixed.h
101
tmp = (u64)val << 16;
sys/dev/pci/drm/i915/display/intel_fixed.h
102
tmp = DIV_ROUND_UP_ULL(tmp, d);
sys/dev/pci/drm/i915/display/intel_fixed.h
104
return clamp_u64_to_fixed16(tmp);
sys/dev/pci/drm/i915/display/intel_fixed.h
109
u64 tmp;
sys/dev/pci/drm/i915/display/intel_fixed.h
111
tmp = (u64)val << 16;
sys/dev/pci/drm/i915/display/intel_fixed.h
112
tmp = DIV_ROUND_UP_ULL(tmp, d.val);
sys/dev/pci/drm/i915/display/intel_fixed.h
113
WARN_ON(tmp > U32_MAX);
sys/dev/pci/drm/i915/display/intel_fixed.h
115
return (u32)tmp;
sys/dev/pci/drm/i915/display/intel_fixed.h
120
u64 tmp;
sys/dev/pci/drm/i915/display/intel_fixed.h
122
tmp = mul_u32_u32(val, mul.val);
sys/dev/pci/drm/i915/display/intel_fixed.h
124
return clamp_u64_to_fixed16(tmp);
sys/dev/pci/drm/i915/display/intel_fixed.h
130
u64 tmp;
sys/dev/pci/drm/i915/display/intel_fixed.h
132
tmp = (u64)add1.val + add2.val;
sys/dev/pci/drm/i915/display/intel_fixed.h
134
return clamp_u64_to_fixed16(tmp);
sys/dev/pci/drm/i915/display/intel_fixed.h
141
u64 tmp;
sys/dev/pci/drm/i915/display/intel_fixed.h
143
tmp = (u64)add1.val + tmp_add2.val;
sys/dev/pci/drm/i915/display/intel_fixed.h
145
return clamp_u64_to_fixed16(tmp);
sys/dev/pci/drm/i915/display/intel_fixed.h
77
u64 tmp;
sys/dev/pci/drm/i915/display/intel_fixed.h
79
tmp = mul_u32_u32(val, mul.val);
sys/dev/pci/drm/i915/display/intel_fixed.h
80
tmp = DIV_ROUND_UP_ULL(tmp, 1 << 16);
sys/dev/pci/drm/i915/display/intel_fixed.h
81
WARN_ON(tmp > U32_MAX);
sys/dev/pci/drm/i915/display/intel_fixed.h
83
return (u32)tmp;
sys/dev/pci/drm/i915/display/intel_fixed.h
89
u64 tmp;
sys/dev/pci/drm/i915/display/intel_fixed.h
91
tmp = mul_u32_u32(val.val, mul.val);
sys/dev/pci/drm/i915/display/intel_fixed.h
92
tmp = tmp >> 16;
sys/dev/pci/drm/i915/display/intel_fixed.h
94
return clamp_u64_to_fixed16(tmp);
sys/dev/pci/drm/i915/display/intel_fixed.h
99
u64 tmp;
sys/dev/pci/drm/i915/display/intel_flipq.c
213
u32 tmp;
sys/dev/pci/drm/i915/display/intel_flipq.c
242
tmp = intel_de_read(display, PIPEDMC_FPQ_ATOMIC_TP(crtc->pipe));
sys/dev/pci/drm/i915/display/intel_flipq.c
247
REG_FIELD_GET(PIPEDMC_FPQ_PLANEQ_3_TP_MASK, tmp),
sys/dev/pci/drm/i915/display/intel_flipq.c
248
REG_FIELD_GET(PIPEDMC_FPQ_PLANEQ_2_TP_MASK, tmp),
sys/dev/pci/drm/i915/display/intel_flipq.c
249
REG_FIELD_GET(PIPEDMC_FPQ_PLANEQ_1_TP_MASK, tmp),
sys/dev/pci/drm/i915/display/intel_flipq.c
250
REG_FIELD_GET(PIPEDMC_FPQ_GENERALQ_TP_MASK, tmp),
sys/dev/pci/drm/i915/display/intel_flipq.c
251
REG_FIELD_GET(PIPEDMC_FPQ_FASTQ_TP_MASK, tmp));
sys/dev/pci/drm/i915/display/intel_hotplug.c
1208
char tmp[16];
sys/dev/pci/drm/i915/display/intel_hotplug.c
1210
if (len >= sizeof(tmp))
sys/dev/pci/drm/i915/display/intel_hotplug.c
1213
if (copy_from_user(tmp, ubuf, len))
sys/dev/pci/drm/i915/display/intel_hotplug.c
1216
tmp[len] = '\0';
sys/dev/pci/drm/i915/display/intel_hotplug.c
1219
newline = strchr(tmp, '\n');
sys/dev/pci/drm/i915/display/intel_hotplug.c
1223
if (strcmp(tmp, "reset") == 0)
sys/dev/pci/drm/i915/display/intel_hotplug.c
1225
else if (kstrtouint(tmp, 10, &new_threshold) != 0)
sys/dev/pci/drm/i915/display/intel_hotplug.c
1287
char tmp[16];
sys/dev/pci/drm/i915/display/intel_hotplug.c
1291
if (len >= sizeof(tmp))
sys/dev/pci/drm/i915/display/intel_hotplug.c
1294
if (copy_from_user(tmp, ubuf, len))
sys/dev/pci/drm/i915/display/intel_hotplug.c
1297
tmp[len] = '\0';
sys/dev/pci/drm/i915/display/intel_hotplug.c
1300
newline = strchr(tmp, '\n');
sys/dev/pci/drm/i915/display/intel_hotplug.c
1305
if (strcmp(tmp, "reset") == 0)
sys/dev/pci/drm/i915/display/intel_hotplug.c
1307
else if (kstrtobool(tmp, &new_state) != 0)
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
440
u32 tmp = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
443
if (tmp == 0)
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
446
hotplug_status |= tmp;
sys/dev/pci/drm/i915/display/intel_lspcon.c
650
u32 mask, tmp;
sys/dev/pci/drm/i915/display/intel_lspcon.c
661
tmp = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_lspcon.c
665
if (tmp & mask)
sys/dev/pci/drm/i915/display/intel_lvds.c
127
u32 tmp, flags = 0;
sys/dev/pci/drm/i915/display/intel_lvds.c
131
tmp = intel_de_read(display, lvds_encoder->reg);
sys/dev/pci/drm/i915/display/intel_lvds.c
132
if (tmp & LVDS_HSYNC_POLARITY)
sys/dev/pci/drm/i915/display/intel_lvds.c
136
if (tmp & LVDS_VSYNC_POLARITY)
sys/dev/pci/drm/i915/display/intel_lvds.c
145
tmp & LVDS_BORDER_ENABLE;
sys/dev/pci/drm/i915/display/intel_lvds.c
149
tmp = intel_de_read(display, PFIT_CONTROL(display));
sys/dev/pci/drm/i915/display/intel_lvds.c
151
crtc_state->gmch_pfit.control |= tmp & PFIT_PANEL_8TO6_DITHER_ENABLE;
sys/dev/pci/drm/i915/display/intel_opregion.c
807
u32 tmp;
sys/dev/pci/drm/i915/display/intel_opregion.c
814
if (swsci(display, SWSCI_GBDA_SUPPORTED_CALLS, 0, &tmp) == 0) {
sys/dev/pci/drm/i915/display/intel_opregion.c
816
tmp <<= 1;
sys/dev/pci/drm/i915/display/intel_opregion.c
817
opregion->swsci_gbda_sub_functions |= tmp;
sys/dev/pci/drm/i915/display/intel_opregion.c
825
if (swsci(display, SWSCI_GBDA_REQUESTED_CALLBACKS, 0, &tmp) == 0) {
sys/dev/pci/drm/i915/display/intel_opregion.c
827
opregion->swsci_sbcb_sub_functions |= tmp;
sys/dev/pci/drm/i915/display/intel_opregion.c
836
if (swsci(display, SWSCI_SBCB_SUPPORTED_CALLBACKS, 0, &tmp) == 0) {
sys/dev/pci/drm/i915/display/intel_opregion.c
838
u32 low = tmp & 0x7ff;
sys/dev/pci/drm/i915/display/intel_opregion.c
839
u32 high = tmp & ~0xfff; /* bit 11 is reserved */
sys/dev/pci/drm/i915/display/intel_opregion.c
840
tmp = (high << 4) | (low << 1) | 1;
sys/dev/pci/drm/i915/display/intel_opregion.c
845
if ((req & tmp) != req)
sys/dev/pci/drm/i915/display/intel_opregion.c
848
req, tmp);
sys/dev/pci/drm/i915/display/intel_opregion.c
852
opregion->swsci_sbcb_sub_functions |= tmp;
sys/dev/pci/drm/i915/display/intel_overlay.c
1000
if (tmp > 7)
sys/dev/pci/drm/i915/display/intel_overlay.c
1003
tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16;
sys/dev/pci/drm/i915/display/intel_overlay.c
1004
if (tmp > 7)
sys/dev/pci/drm/i915/display/intel_overlay.c
1018
u32 tmp;
sys/dev/pci/drm/i915/display/intel_overlay.c
1083
tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
sys/dev/pci/drm/i915/display/intel_overlay.c
1085
if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
sys/dev/pci/drm/i915/display/intel_overlay.c
1096
tmp = rec->stride_Y*rec->src_height;
sys/dev/pci/drm/i915/display/intel_overlay.c
1097
if (rec->offset_Y + tmp > new_bo->base.size)
sys/dev/pci/drm/i915/display/intel_overlay.c
1107
tmp = rec->stride_Y * rec->src_height;
sys/dev/pci/drm/i915/display/intel_overlay.c
1108
if (rec->offset_Y + tmp > new_bo->base.size)
sys/dev/pci/drm/i915/display/intel_overlay.c
1111
tmp = rec->stride_UV * (rec->src_height / uv_vscale);
sys/dev/pci/drm/i915/display/intel_overlay.c
1112
if (rec->offset_U + tmp > new_bo->base.size ||
sys/dev/pci/drm/i915/display/intel_overlay.c
1113
rec->offset_V + tmp > new_bo->base.size)
sys/dev/pci/drm/i915/display/intel_overlay.c
327
u32 tmp, *cs;
sys/dev/pci/drm/i915/display/intel_overlay.c
335
tmp = intel_de_read(display, DOVSTA);
sys/dev/pci/drm/i915/display/intel_overlay.c
336
if (tmp & (1 << 17))
sys/dev/pci/drm/i915/display/intel_overlay.c
337
drm_dbg(display->drm, "overlay underrun, DOVSTA: %x\n", tmp);
sys/dev/pci/drm/i915/display/intel_overlay.c
955
u32 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display));
sys/dev/pci/drm/i915/display/intel_overlay.c
958
ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, tmp);
sys/dev/pci/drm/i915/display/intel_overlay.c
960
u32 tmp;
sys/dev/pci/drm/i915/display/intel_overlay.c
963
tmp = intel_de_read(display, PFIT_AUTO_RATIOS(display));
sys/dev/pci/drm/i915/display/intel_overlay.c
965
tmp = intel_de_read(display, PFIT_PGM_RATIOS(display));
sys/dev/pci/drm/i915/display/intel_overlay.c
967
ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK, tmp);
sys/dev/pci/drm/i915/display/intel_overlay.c
996
u32 tmp;
sys/dev/pci/drm/i915/display/intel_overlay.c
999
tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16;
sys/dev/pci/drm/i915/display/intel_pch_display.c
504
u32 tmp;
sys/dev/pci/drm/i915/display/intel_pch_display.c
511
tmp = intel_de_read(display, FDI_RX_CTL(pipe));
sys/dev/pci/drm/i915/display/intel_pch_display.c
512
crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
sys/dev/pci/drm/i915/display/intel_pch_display.c
525
tmp = intel_de_read(display, PCH_DPLL_SEL);
sys/dev/pci/drm/i915/display/intel_pch_display.c
526
if (tmp & TRANS_DPLLB_SEL(pipe))
sys/dev/pci/drm/i915/display/intel_pch_display.c
539
tmp = crtc_state->dpll_hw_state.i9xx.dpll;
sys/dev/pci/drm/i915/display/intel_pch_display.c
541
((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
sys/dev/pci/drm/i915/display/intel_pch_display.c
623
u32 tmp;
sys/dev/pci/drm/i915/display/intel_pch_display.c
630
tmp = intel_de_read(display, FDI_RX_CTL(PIPE_A));
sys/dev/pci/drm/i915/display/intel_pch_display.c
631
crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
101
tmp = intel_sbi_read(display, 0x21C4, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
102
tmp |= (1 << 27);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
103
intel_sbi_write(display, 0x21C4, tmp, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
105
tmp = intel_sbi_read(display, 0x20EC, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
106
tmp &= ~(0xF << 28);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
107
tmp |= (4 << 28);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
108
intel_sbi_write(display, 0x20EC, tmp, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
110
tmp = intel_sbi_read(display, 0x21EC, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
111
tmp &= ~(0xF << 28);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
112
tmp |= (4 << 28);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
113
intel_sbi_write(display, 0x21EC, tmp, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
283
u32 reg, tmp;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
294
tmp = intel_sbi_read(display, SBI_SSCCTL, SBI_ICLK);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
295
tmp &= ~SBI_SSCCTL_DISABLE;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
296
tmp |= SBI_SSCCTL_PATHALT;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
297
intel_sbi_write(display, SBI_SSCCTL, tmp, SBI_ICLK);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
302
tmp = intel_sbi_read(display, SBI_SSCCTL, SBI_ICLK);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
303
tmp &= ~SBI_SSCCTL_PATHALT;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
304
intel_sbi_write(display, SBI_SSCCTL, tmp, SBI_ICLK);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
311
tmp = intel_sbi_read(display, reg, SBI_ICLK);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
312
tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
313
intel_sbi_write(display, reg, tmp, SBI_ICLK);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
321
u32 reg, tmp;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
326
tmp = intel_sbi_read(display, reg, SBI_ICLK);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
327
tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
328
intel_sbi_write(display, reg, tmp, SBI_ICLK);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
330
tmp = intel_sbi_read(display, SBI_SSCCTL, SBI_ICLK);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
331
if (!(tmp & SBI_SSCCTL_DISABLE)) {
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
332
if (!(tmp & SBI_SSCCTL_PATHALT)) {
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
333
tmp |= SBI_SSCCTL_PATHALT;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
334
intel_sbi_write(display, SBI_SSCCTL, tmp, SBI_ICLK);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
337
tmp |= SBI_SSCCTL_DISABLE;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
338
intel_sbi_write(display, SBI_SSCCTL, tmp, SBI_ICLK);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
378
u32 tmp;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
390
tmp = 0xAAAAAAAB;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
392
tmp = 0x00000000;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
393
intel_sbi_write(display, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
395
tmp = intel_sbi_read(display, SBI_SSCDIVINTPHASE, SBI_ICLK);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
396
tmp &= 0xffff0000;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
397
tmp |= sscdivintphase[idx];
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
398
intel_sbi_write(display, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
42
u32 tmp;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
46
tmp = intel_sbi_read(display, 0x8008, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
47
tmp &= ~(0xFF << 24);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
48
tmp |= (0x12 << 24);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
49
intel_sbi_write(display, 0x8008, tmp, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
51
tmp = intel_sbi_read(display, 0x2008, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
52
tmp |= (1 << 11);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
53
intel_sbi_write(display, 0x2008, tmp, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
55
tmp = intel_sbi_read(display, 0x2108, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
56
tmp |= (1 << 11);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
57
intel_sbi_write(display, 0x2108, tmp, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
59
tmp = intel_sbi_read(display, 0x206C, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
60
tmp |= (1 << 24) | (1 << 21) | (1 << 18);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
61
intel_sbi_write(display, 0x206C, tmp, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
63
tmp = intel_sbi_read(display, 0x216C, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
64
tmp |= (1 << 24) | (1 << 21) | (1 << 18);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
65
intel_sbi_write(display, 0x216C, tmp, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
67
tmp = intel_sbi_read(display, 0x2080, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
68
tmp &= ~(7 << 13);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
69
tmp |= (5 << 13);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
70
intel_sbi_write(display, 0x2080, tmp, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
72
tmp = intel_sbi_read(display, 0x2180, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
73
tmp &= ~(7 << 13);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
74
tmp |= (5 << 13);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
75
intel_sbi_write(display, 0x2180, tmp, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
77
tmp = intel_sbi_read(display, 0x208C, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
78
tmp &= ~0xFF;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
79
tmp |= 0x1C;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
80
intel_sbi_write(display, 0x208C, tmp, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
82
tmp = intel_sbi_read(display, 0x218C, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
83
tmp &= ~0xFF;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
84
tmp |= 0x1C;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
85
intel_sbi_write(display, 0x218C, tmp, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
87
tmp = intel_sbi_read(display, 0x2098, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
88
tmp &= ~(0xFF << 16);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
89
tmp |= (0x1C << 16);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
90
intel_sbi_write(display, 0x2098, tmp, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
92
tmp = intel_sbi_read(display, 0x2198, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
93
tmp &= ~(0xFF << 16);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
94
tmp |= (0x1C << 16);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
95
intel_sbi_write(display, 0x2198, tmp, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
97
tmp = intel_sbi_read(display, 0x20C4, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
98
tmp |= (1 << 27);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
99
intel_sbi_write(display, 0x20C4, tmp, SBI_MPHY);
sys/dev/pci/drm/i915/display/intel_pfit.c
710
u32 tmp;
sys/dev/pci/drm/i915/display/intel_pfit.c
715
tmp = intel_de_read(display, PFIT_CONTROL(display));
sys/dev/pci/drm/i915/display/intel_pfit.c
716
if (!(tmp & PFIT_ENABLE))
sys/dev/pci/drm/i915/display/intel_pfit.c
721
pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp);
sys/dev/pci/drm/i915/display/intel_pfit.c
728
crtc_state->gmch_pfit.control = tmp;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
173
u32 tmp = intel_de_read(display, PORT_DFT2_G4X(display));
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
175
tmp |= DC_BALANCE_RESET_VLV;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
178
tmp |= PIPE_A_SCRAMBLE_RESET;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
181
tmp |= PIPE_B_SCRAMBLE_RESET;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
184
tmp |= PIPE_C_SCRAMBLE_RESET;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
189
intel_de_write(display, PORT_DFT2_G4X(display), tmp);
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
235
u32 tmp = intel_de_read(display, PORT_DFT2_G4X(display));
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
239
tmp &= ~PIPE_A_SCRAMBLE_RESET;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
242
tmp &= ~PIPE_B_SCRAMBLE_RESET;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
245
tmp &= ~PIPE_C_SCRAMBLE_RESET;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
250
if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
251
tmp &= ~DC_BALANCE_RESET_VLV;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
252
intel_de_write(display, PORT_DFT2_G4X(display), tmp);
sys/dev/pci/drm/i915/display/intel_psr.c
1071
int tmp;
sys/dev/pci/drm/i915/display/intel_psr.c
1073
tmp = map[intel_dp->alpm_parameters.io_wake_lines -
sys/dev/pci/drm/i915/display/intel_psr.c
1075
val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(tmp + TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES);
sys/dev/pci/drm/i915/display/intel_psr.c
1077
tmp = map[intel_dp->alpm_parameters.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];
sys/dev/pci/drm/i915/display/intel_psr.c
1078
val |= TGL_EDP_PSR2_FAST_WAKE(tmp + TGL_EDP_PSR2_FAST_WAKE_MIN_LINES);
sys/dev/pci/drm/i915/display/intel_psr.c
1096
u32 tmp;
sys/dev/pci/drm/i915/display/intel_psr.c
1098
tmp = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_psr.c
1100
drm_WARN_ON(display->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));
sys/dev/pci/drm/i915/display/intel_sdvo.c
1013
u8 hbuf_size, tmp[8];
sys/dev/pci/drm/i915/display/intel_sdvo.c
1032
memset(tmp, 0, 8);
sys/dev/pci/drm/i915/display/intel_sdvo.c
1034
memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
sys/dev/pci/drm/i915/display/intel_sdvo.c
1038
tmp, 8))
sys/dev/pci/drm/i915/display/intel_sdvo.c
3056
struct drm_connector *connector, *tmp;
sys/dev/pci/drm/i915/display/intel_sdvo.c
3058
list_for_each_entry_safe(connector, tmp,
sys/dev/pci/drm/i915/display/intel_tv.c
1098
u32 tv_ctl, hctl1, hctl3, vctl1, vctl2, tmp;
sys/dev/pci/drm/i915/display/intel_tv.c
1145
tmp = intel_de_read(display, TV_WIN_POS);
sys/dev/pci/drm/i915/display/intel_tv.c
1146
xpos = tmp >> 16;
sys/dev/pci/drm/i915/display/intel_tv.c
1147
ypos = tmp & 0xffff;
sys/dev/pci/drm/i915/display/intel_tv.c
1149
tmp = intel_de_read(display, TV_WIN_SIZE);
sys/dev/pci/drm/i915/display/intel_tv.c
1150
xsize = tmp >> 16;
sys/dev/pci/drm/i915/display/intel_tv.c
1151
ysize = tmp & 0xffff;
sys/dev/pci/drm/i915/display/intel_tv.c
919
u32 tmp = intel_de_read(display, TV_CTL);
sys/dev/pci/drm/i915/display/intel_tv.c
921
*pipe = (tmp & TV_ENC_PIPE_SEL_MASK) >> TV_ENC_PIPE_SEL_SHIFT;
sys/dev/pci/drm/i915/display/intel_tv.c
923
return tmp & TV_ENC_ENABLE;
sys/dev/pci/drm/i915/display/intel_vga.c
50
u32 tmp;
sys/dev/pci/drm/i915/display/intel_vga.c
53
tmp = intel_de_read(display, vga_reg);
sys/dev/pci/drm/i915/display/intel_vga.c
54
if (tmp & VGA_DISP_DISABLE)
sys/dev/pci/drm/i915/display/intel_vga.c
58
pipe = REG_FIELD_GET(VGA_PIPE_SEL_MASK_CHV, tmp);
sys/dev/pci/drm/i915/display/intel_vga.c
60
pipe = REG_FIELD_GET(VGA_PIPE_SEL_MASK, tmp);
sys/dev/pci/drm/i915/display/intel_wm.c
294
char tmp[32];
sys/dev/pci/drm/i915/display/intel_wm.c
296
if (len >= sizeof(tmp))
sys/dev/pci/drm/i915/display/intel_wm.c
299
if (copy_from_user(tmp, ubuf, len))
sys/dev/pci/drm/i915/display/intel_wm.c
302
tmp[len] = '\0';
sys/dev/pci/drm/i915/display/intel_wm.c
304
ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
sys/dev/pci/drm/i915/display/skl_scaler.c
697
u32 tmp;
sys/dev/pci/drm/i915/display/skl_scaler.c
701
tmp = glk_nearest_filter_coef(t);
sys/dev/pci/drm/i915/display/skl_scaler.c
704
tmp |= glk_nearest_filter_coef(t) << 16;
sys/dev/pci/drm/i915/display/skl_scaler.c
707
GLK_PS_COEF_DATA_SET(pipe, id, set), tmp);
sys/dev/pci/drm/i915/display/vlv_dsi.c
1312
u32 val, tmp;
sys/dev/pci/drm/i915/display/vlv_dsi.c
1331
tmp = intel_de_read(display, MIPI_CTRL(display, PORT_A));
sys/dev/pci/drm/i915/display/vlv_dsi.c
1332
tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
sys/dev/pci/drm/i915/display/vlv_dsi.c
1334
tmp | ESCAPE_CLOCK_DIVIDER_1);
sys/dev/pci/drm/i915/display/vlv_dsi.c
1337
tmp = intel_de_read(display, MIPI_CTRL(display, port));
sys/dev/pci/drm/i915/display/vlv_dsi.c
1338
tmp &= ~READ_REQUEST_PRIORITY_MASK;
sys/dev/pci/drm/i915/display/vlv_dsi.c
1340
tmp | READ_REQUEST_PRIORITY_HIGH);
sys/dev/pci/drm/i915/display/vlv_dsi.c
1370
tmp = 0;
sys/dev/pci/drm/i915/display/vlv_dsi.c
1372
tmp |= EOT_DISABLE;
sys/dev/pci/drm/i915/display/vlv_dsi.c
1374
tmp |= CLOCKSTOP;
sys/dev/pci/drm/i915/display/vlv_dsi.c
1377
tmp |= BXT_DPHY_DEFEATURE_EN;
sys/dev/pci/drm/i915/display/vlv_dsi.c
1379
tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
sys/dev/pci/drm/i915/display/vlv_dsi.c
1437
intel_de_write(display, MIPI_EOT_DISABLE(display, port), tmp);
sys/dev/pci/drm/i915/display/vlv_dsi.c
347
u32 tmp = intel_de_read(display, MIPI_DEVICE_READY(display, port));
sys/dev/pci/drm/i915/display/vlv_dsi.c
350
GLK_LP_WAKE, (tmp & DEVICE_READY) ? GLK_LP_WAKE : 0);
sys/dev/pci/drm/i915/display/vlv_dsi.c
976
u32 tmp = intel_de_read(display,
sys/dev/pci/drm/i915/display/vlv_dsi.c
978
enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
sys/dev/pci/drm/i915/display/vlv_dsi.c
988
u32 tmp = intel_de_read(display, MIPI_CTRL(display, port));
sys/dev/pci/drm/i915/display/vlv_dsi.c
989
tmp &= BXT_PIPE_SELECT_MASK;
sys/dev/pci/drm/i915/display/vlv_dsi.c
990
tmp >>= BXT_PIPE_SELECT_SHIFT;
sys/dev/pci/drm/i915/display/vlv_dsi.c
992
if (drm_WARN_ON(display->drm, tmp > PIPE_C))
sys/dev/pci/drm/i915/display/vlv_dsi.c
995
*pipe = tmp;
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
252
u32 tmp;
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
258
tmp = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL);
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
259
tmp &= ~DSI_PLL_VCO_EN;
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
260
tmp |= DSI_PLL_LDO_GATE;
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
261
vlv_cck_write(display->drm, CCK_REG_DSI_PLL_CONTROL, tmp);
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
437
u32 tmp;
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
447
tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL);
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
448
tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
449
tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
450
tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
451
tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
478
tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
479
tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
480
tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower);
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
481
tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper);
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
483
intel_de_write(display, BXT_MIPI_CLOCK_CTL, tmp);
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
584
u32 tmp;
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
588
tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL);
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
589
tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
590
tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
591
tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
592
tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
593
intel_de_write(display, BXT_MIPI_CLOCK_CTL, tmp);
sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c
149
struct dma_fence_cb *cur, *tmp;
sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c
153
list_for_each_entry_safe(cur, tmp, list, node) {
sys/dev/pci/drm/i915/gt/intel_engine_pm.h
44
intel_engine_mask_t tmp, mask = engine->mask;
sys/dev/pci/drm/i915/gt/intel_engine_pm.h
46
for_each_engine_masked(tengine, gt, mask, tmp)
sys/dev/pci/drm/i915/gt/intel_engine_pm.h
80
intel_engine_mask_t tmp, mask = engine->mask;
sys/dev/pci/drm/i915/gt/intel_engine_pm.h
82
for_each_engine_masked(tengine, gt, mask, tmp)
sys/dev/pci/drm/i915/gt/intel_gt_pm_debugfs.c
74
unsigned int tmp;
sys/dev/pci/drm/i915/gt/intel_gt_pm_debugfs.c
81
for_each_fw_domain(fw_domain, uncore, tmp)
sys/dev/pci/drm/i915/gt/intel_rc6.c
741
u32 lower, upper, tmp;
sys/dev/pci/drm/i915/gt/intel_rc6.c
764
tmp = upper;
sys/dev/pci/drm/i915/gt/intel_rc6.c
773
} while (upper != tmp && --loop);
sys/dev/pci/drm/i915/gt/intel_reset.c
1486
intel_engine_mask_t tmp;
sys/dev/pci/drm/i915/gt/intel_reset.c
1523
for_each_engine_masked(engine, gt, engine_mask, tmp) {
sys/dev/pci/drm/i915/gt/intel_reset.c
1556
for_each_engine(engine, gt, tmp) {
sys/dev/pci/drm/i915/gt/intel_reset.c
1571
for_each_engine(engine, gt, tmp)
sys/dev/pci/drm/i915/gt/intel_reset.c
328
intel_engine_mask_t tmp;
sys/dev/pci/drm/i915/gt/intel_reset.c
331
for_each_engine_masked(engine, gt, engine_mask, tmp) {
sys/dev/pci/drm/i915/gt/intel_reset.c
524
intel_engine_mask_t tmp;
sys/dev/pci/drm/i915/gt/intel_reset.c
532
for_each_engine_masked(engine, gt, engine_mask, tmp) {
sys/dev/pci/drm/i915/gt/intel_reset.c
554
for_each_engine_masked(engine, gt, unlock_mask, tmp)
sys/dev/pci/drm/i915/gt/intel_reset.c
614
intel_engine_mask_t tmp;
sys/dev/pci/drm/i915/gt/intel_reset.c
620
for_each_engine_masked(engine, gt, engine_mask, tmp) {
sys/dev/pci/drm/i915/gt/intel_reset.c
655
for_each_engine_masked(engine, gt, engine_mask, tmp)
sys/dev/pci/drm/i915/gt/intel_tlb.c
54
intel_engine_mask_t awake, tmp;
sys/dev/pci/drm/i915/gt/intel_tlb.c
97
for_each_engine_masked(engine, gt, awake, tmp) {
sys/dev/pci/drm/i915/gt/selftest_execlists.c
199
struct intel_context *tmp;
sys/dev/pci/drm/i915/gt/selftest_execlists.c
201
tmp = intel_context_create(engine);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
202
if (IS_ERR(tmp)) {
sys/dev/pci/drm/i915/gt/selftest_execlists.c
203
err = PTR_ERR(tmp);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
207
err = intel_context_pin(tmp);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
209
intel_context_put(tmp);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
218
memset(tmp->ring->vaddr,
sys/dev/pci/drm/i915/gt/selftest_execlists.c
220
tmp->ring->vma->size);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
222
ce[n] = tmp;
sys/dev/pci/drm/i915/gt/selftest_execlists.c
2810
struct intel_context *tmp;
sys/dev/pci/drm/i915/gt/selftest_execlists.c
2812
tmp = intel_context_create(engine);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
2813
if (IS_ERR(tmp)) {
sys/dev/pci/drm/i915/gt/selftest_execlists.c
2814
err = PTR_ERR(tmp);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
2818
tmp->ring_size = ring_sz;
sys/dev/pci/drm/i915/gt/selftest_execlists.c
2820
err = intel_context_pin(tmp);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
2822
intel_context_put(tmp);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
2826
memset32(tmp->ring->vaddr,
sys/dev/pci/drm/i915/gt/selftest_execlists.c
2828
tmp->ring->vma->size / sizeof(u32));
sys/dev/pci/drm/i915/gt/selftest_execlists.c
2830
ce[n] = tmp;
sys/dev/pci/drm/i915/gt/selftest_execlists.c
2853
struct i915_request *tmp;
sys/dev/pci/drm/i915/gt/selftest_execlists.c
2855
tmp = intel_context_create_request(ce[0]);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
2856
if (IS_ERR(tmp)) {
sys/dev/pci/drm/i915/gt/selftest_execlists.c
2857
err = PTR_ERR(tmp);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
2862
i915_request_add(tmp);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
361
struct intel_context *tmp;
sys/dev/pci/drm/i915/gt/selftest_execlists.c
363
tmp = intel_context_create(engine);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
364
if (IS_ERR(tmp)) {
sys/dev/pci/drm/i915/gt/selftest_execlists.c
365
err = PTR_ERR(tmp);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
369
err = intel_context_pin(tmp);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
371
intel_context_put(tmp);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
375
memset32(tmp->ring->vaddr,
sys/dev/pci/drm/i915/gt/selftest_execlists.c
377
tmp->ring->vma->size / sizeof(u32));
sys/dev/pci/drm/i915/gt/selftest_execlists.c
379
ce[n] = tmp;
sys/dev/pci/drm/i915/gt/selftest_execlists.c
405
struct i915_request *tmp;
sys/dev/pci/drm/i915/gt/selftest_execlists.c
407
tmp = intel_context_create_request(ce[0]);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
408
if (IS_ERR(tmp)) {
sys/dev/pci/drm/i915/gt/selftest_execlists.c
409
err = PTR_ERR(tmp);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
414
i915_request_add(tmp);
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
1013
for_each_engine(other, gt, tmp) {
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
1016
threads[tmp].resets =
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
1025
threads[tmp].engine = other;
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
1026
threads[tmp].flags = flags;
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
1037
threads[tmp].worker = worker;
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
1039
kthread_init_work(&threads[tmp].work, active_engine);
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
1040
kthread_queue_work(threads[tmp].worker,
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
1041
&threads[tmp].work);
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
1188
for_each_engine(other, gt, tmp) {
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
1191
if (!threads[tmp].worker)
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
1194
WRITE_ONCE(threads[tmp].stop, true);
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
1195
kthread_flush_work(&threads[tmp].work);
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
1196
ret = READ_ONCE(threads[tmp].result);
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
1204
kthread_destroy_worker(threads[tmp].worker);
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
1209
threads[tmp].resets !=
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
1214
threads[tmp].resets);
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
969
enum intel_engine_id id, tmp;
sys/dev/pci/drm/i915/gt/selftest_lrc.c
885
struct intel_context *tmp;
sys/dev/pci/drm/i915/gt/selftest_lrc.c
887
tmp = intel_context_create(data.engine);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
888
if (IS_ERR(tmp)) {
sys/dev/pci/drm/i915/gt/selftest_lrc.c
889
err = PTR_ERR(tmp);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
893
err = intel_context_pin(tmp);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
895
intel_context_put(tmp);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
899
data.ce[i] = tmp;
sys/dev/pci/drm/i915/gt/selftest_reset.c
104
if (i915_memcpy_from_wc(tmp, in, PAGE_SIZE))
sys/dev/pci/drm/i915/gt/selftest_reset.c
105
in = tmp;
sys/dev/pci/drm/i915/gt/selftest_reset.c
142
if (i915_memcpy_from_wc(tmp, in, PAGE_SIZE))
sys/dev/pci/drm/i915/gt/selftest_reset.c
143
in = tmp;
sys/dev/pci/drm/i915/gt/selftest_reset.c
179
kfree(tmp);
sys/dev/pci/drm/i915/gt/selftest_reset.c
30
void *tmp;
sys/dev/pci/drm/i915/gt/selftest_reset.c
45
tmp = kmalloc(PAGE_SIZE, GFP_KERNEL);
sys/dev/pci/drm/i915/gt/selftest_reset.c
46
if (!tmp) {
sys/dev/pci/drm/i915/gt/selftest_timeline.c
412
({ int tmp = last_order; last_order = order; order += tmp; })) {
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
301
struct intel_context *ce, *tmp;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
356
tmp = intel_context_create(engine);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
357
if (IS_ERR(tmp)) {
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
358
err = PTR_ERR(tmp);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
362
ce = tmp;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1066
int i, j, k, tmp, maxregcount = 0;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1074
tmp = guc_cap_list_num_regs(guc->capture, i, j, k);
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1075
if (tmp > maxregcount)
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1076
maxregcount = tmp;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1106
struct guc_mmio_reg tmp;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1189
if (guc_capture_log_get_register(guc, buf, &tmp)) {
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
530
u8 *caplist, *tmp;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
563
tmp = caplist;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
565
listnode = (struct guc_debug_capture_list *)tmp;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
569
tmp += sizeof(struct guc_debug_capture_list);
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
570
guc_capture_list_init(guc, owner, type, classid, (struct guc_mmio_reg *)tmp, num_regs);
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
588
int tmp = sizeof(u32) * 4;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
593
*size = tmp;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
597
null_header = kzalloc(tmp, GFP_KERNEL);
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
605
*size = tmp;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
617
size_t tmp = 0;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
637
if (!guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_GLOBAL, 0, &tmp, true))
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
638
worst_min_size += tmp;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
641
engine->class, &tmp, true)) {
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
642
worst_min_size += tmp;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
645
engine->class, &tmp, true)) {
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
646
worst_min_size += tmp;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
936
struct guc_mmio_reg *tmp[GUC_CAPTURE_LIST_TYPE_MAX];
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
940
tmp[i] = node->reginfo[i].regs;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
941
memset(tmp[i], 0, sizeof(struct guc_mmio_reg) *
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
946
node->reginfo[i].regs = tmp[i];
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
1756
intel_engine_mask_t tmp, mask = ve->mask;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
1759
for_each_engine_masked(engine, ve->gt, mask, tmp)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4002
intel_engine_mask_t tmp, mask = ce->engine->mask;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4005
for_each_engine_masked(engine, ce->engine->gt, mask, tmp)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4013
intel_engine_mask_t tmp, mask = ce->engine->mask;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4023
for_each_engine_masked(engine, ce->engine->gt, mask, tmp)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4029
intel_engine_mask_t tmp, mask = ce->engine->mask;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4032
for_each_engine_masked(engine, ce->engine->gt, mask, tmp)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4040
intel_engine_mask_t tmp, mask = ce->engine->mask;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4043
for_each_engine_masked(engine, ce->engine->gt, mask, tmp)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4281
intel_engine_mask_t tmp, mask = b->engine_mask;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4284
for_each_engine_masked(sibling, b->irq_engine->gt, mask, tmp)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4294
intel_engine_mask_t tmp, mask = b->engine_mask;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4296
for_each_engine_masked(sibling, b->irq_engine->gt, mask, tmp)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4532
intel_engine_mask_t tmp, mask = engine->mask;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4534
for_each_engine_masked(e, engine->gt, mask, tmp)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
5192
intel_engine_mask_t tmp, virtual_mask = ce->engine->mask;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
5195
for_each_engine_masked(e, ce->engine->gt, virtual_mask, tmp) {
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
6005
intel_engine_mask_t tmp, mask = ve->mask;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
6007
for_each_engine_masked(engine, ve->gt, mask, tmp)
sys/dev/pci/drm/i915/gvt/cmd_parser.c
3245
struct hlist_node *tmp;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
3249
hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
sys/dev/pci/drm/i915/gvt/execlist.c
527
intel_engine_mask_t tmp;
sys/dev/pci/drm/i915/gvt/execlist.c
529
for_each_engine_masked(engine, vgpu->gvt->gt, engine_mask, tmp) {
sys/dev/pci/drm/i915/gvt/execlist.c
540
intel_engine_mask_t tmp;
sys/dev/pci/drm/i915/gvt/execlist.c
542
for_each_engine_masked(engine, vgpu->gvt->gt, engine_mask, tmp)
sys/dev/pci/drm/i915/gvt/handlers.c
2849
struct hlist_node *tmp;
sys/dev/pci/drm/i915/gvt/handlers.c
2853
hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node)
sys/dev/pci/drm/i915/gvt/kvmgt.c
339
struct hlist_node *tmp;
sys/dev/pci/drm/i915/gvt/kvmgt.c
342
hash_for_each_safe(info->ptable, i, tmp, p, hnode) {
sys/dev/pci/drm/i915/gvt/scheduler.c
1054
intel_engine_mask_t tmp;
sys/dev/pci/drm/i915/gvt/scheduler.c
1057
for_each_engine_masked(engine, vgpu->gvt->gt, engine_mask, tmp) {
sys/dev/pci/drm/i915/i915_active.c
857
intel_engine_mask_t tmp, mask = engine->mask;
sys/dev/pci/drm/i915/i915_active.c
874
for_each_engine_masked(engine, gt, mask, tmp) {
sys/dev/pci/drm/i915/i915_cmd_parser.c
937
struct hlist_node *tmp;
sys/dev/pci/drm/i915/i915_cmd_parser.c
941
hash_for_each_safe(engine->cmd_hash, i, tmp, desc_node, node) {
sys/dev/pci/drm/i915/i915_gpu_error.c
275
void *tmp;
sys/dev/pci/drm/i915/i915_gpu_error.c
293
c->tmp = NULL;
sys/dev/pci/drm/i915/i915_gpu_error.c
295
c->tmp = pool_alloc(&c->pool, ALLOW_FAIL);
sys/dev/pci/drm/i915/i915_gpu_error.c
334
if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
sys/dev/pci/drm/i915/i915_gpu_error.c
335
zstream->next_in = c->tmp;
sys/dev/pci/drm/i915/i915_gpu_error.c
397
if (c->tmp)
sys/dev/pci/drm/i915/i915_gpu_error.c
398
pool_free(&c->pool, c->tmp);
sys/dev/pci/drm/i915/i915_perf.c
1653
struct i915_oa_config_bo *oa_bo, *tmp;
sys/dev/pci/drm/i915/i915_perf.c
1656
llist_for_each_entry_safe(oa_bo, tmp, stream->oa_config_bos.first, node)
sys/dev/pci/drm/i915/i915_perf.c
4114
u64 tmp = NSEC_PER_SEC;
sys/dev/pci/drm/i915/i915_perf.c
4115
do_div(tmp, oa_period);
sys/dev/pci/drm/i915/i915_perf.c
4116
oa_freq_hz = tmp;
sys/dev/pci/drm/i915/i915_perf.c
4651
struct i915_oa_config *oa_config, *tmp;
sys/dev/pci/drm/i915/i915_perf.c
4756
idr_for_each_entry(&perf->metrics_idr, tmp, id) {
sys/dev/pci/drm/i915/i915_perf.c
4757
if (!strcmp(tmp->uuid, oa_config->uuid)) {
sys/dev/pci/drm/i915/i915_perf.c
4975
intel_engine_mask_t tmp;
sys/dev/pci/drm/i915/i915_perf.c
4981
for_each_engine_masked(engine, gt, ALL_ENGINES, tmp) {
sys/dev/pci/drm/i915/i915_query.c
266
struct i915_oa_config *tmp;
sys/dev/pci/drm/i915/i915_query.c
278
idr_for_each_entry(&perf->metrics_idr, tmp, id) {
sys/dev/pci/drm/i915/i915_query.c
279
if (!strcmp(tmp->uuid, uuid)) {
sys/dev/pci/drm/i915/i915_query.c
280
oa_config = i915_oa_config_get(tmp);
sys/dev/pci/drm/i915/i915_query.c
359
struct i915_oa_config *tmp;
sys/dev/pci/drm/i915/i915_query.c
365
idr_for_each_entry(&perf->metrics_idr, tmp, id)
sys/dev/pci/drm/i915/i915_query.c
397
struct i915_oa_config *tmp;
sys/dev/pci/drm/i915/i915_query.c
422
idr_for_each_entry(&perf->metrics_idr, tmp, id) {
sys/dev/pci/drm/i915/i915_request.c
468
struct i915_request *tmp;
sys/dev/pci/drm/i915/i915_request.c
474
tmp = list_first_entry(&tl->requests, typeof(*tmp), link);
sys/dev/pci/drm/i915/i915_request.c
475
GEM_BUG_ON(!i915_request_completed(tmp));
sys/dev/pci/drm/i915/i915_request.c
476
} while (i915_request_retire(tmp) && tmp != rq);
sys/dev/pci/drm/i915/i915_scheduler.c
392
struct i915_dependency *dep, *tmp;
sys/dev/pci/drm/i915/i915_scheduler.c
402
list_for_each_entry_safe(dep, tmp, &node->signalers_list, signal_link) {
sys/dev/pci/drm/i915/i915_scheduler.c
412
list_for_each_entry_safe(dep, tmp, &node->waiters_list, wait_link) {
sys/dev/pci/drm/i915/intel_clock_gating.c
241
u32 tmp;
sys/dev/pci/drm/i915/intel_clock_gating.c
243
tmp = intel_uncore_read(&i915->uncore, MCH_SSKPD);
sys/dev/pci/drm/i915/intel_clock_gating.c
244
if (REG_FIELD_GET(SSKPD_WM0_MASK_SNB, tmp) != 12)
sys/dev/pci/drm/i915/intel_clock_gating.c
247
tmp);
sys/dev/pci/drm/i915/intel_uncore.c
1920
unsigned int tmp;
sys/dev/pci/drm/i915/intel_uncore.c
1924
for_each_fw_domain_masked(domain, fw_domains, uncore, tmp)
sys/dev/pci/drm/i915/intel_uncore.c
2177
int tmp;
sys/dev/pci/drm/i915/intel_uncore.c
2179
for_each_fw_domain(d, uncore, tmp)
sys/dev/pci/drm/i915/intel_uncore.c
309
unsigned int tmp;
sys/dev/pci/drm/i915/intel_uncore.c
313
for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
sys/dev/pci/drm/i915/intel_uncore.c
318
for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
sys/dev/pci/drm/i915/intel_uncore.c
329
unsigned int tmp;
sys/dev/pci/drm/i915/intel_uncore.c
333
for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
sys/dev/pci/drm/i915/intel_uncore.c
338
for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
sys/dev/pci/drm/i915/intel_uncore.c
348
unsigned int tmp;
sys/dev/pci/drm/i915/intel_uncore.c
352
for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
sys/dev/pci/drm/i915/intel_uncore.c
363
unsigned int tmp;
sys/dev/pci/drm/i915/intel_uncore.c
370
for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
sys/dev/pci/drm/i915/intel_uncore.c
506
unsigned int tmp;
sys/dev/pci/drm/i915/intel_uncore.c
510
for_each_fw_domain(domain, uncore, tmp) {
sys/dev/pci/drm/i915/intel_uncore.c
520
for_each_fw_domain(domain, uncore, tmp) {
sys/dev/pci/drm/i915/intel_uncore.c
698
unsigned int tmp;
sys/dev/pci/drm/i915/intel_uncore.c
702
for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
sys/dev/pci/drm/i915/intel_uncore.c
800
unsigned int tmp;
sys/dev/pci/drm/i915/intel_uncore.c
804
for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
sys/dev/pci/drm/i915/intel_uncore.c
863
unsigned int tmp;
sys/dev/pci/drm/i915/intel_uncore.c
869
for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
sys/dev/pci/drm/i915/intel_uncore.c
909
unsigned int tmp;
sys/dev/pci/drm/i915/intel_uncore.c
930
for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c
1352
struct drm_mm_node tmp;
sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c
1367
memset(&tmp, 0, sizeof(tmp));
sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c
1369
err = drm_mm_insert_node_in_range(&ggtt->vm.mm, &tmp,
sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c
1381
u64 offset = tmp.start + n * PAGE_SIZE;
sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c
1398
u64 offset = tmp.start + order[n] * PAGE_SIZE;
sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c
1409
u64 offset = tmp.start + order[n] * PAGE_SIZE;
sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c
1427
ggtt->vm.clear_range(&ggtt->vm, tmp.start, tmp.size);
sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c
1430
drm_mm_remove_node(&tmp);
sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c
1718
struct drm_mm_node tmp = {};
sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c
1758
err = i915_gem_gtt_insert(&ggtt->vm, NULL, &tmp,
sys/dev/pci/drm/i915/selftests/i915_perf.c
50
struct i915_oa_config *oa_config = NULL, *tmp;
sys/dev/pci/drm/i915/selftests/i915_perf.c
55
idr_for_each_entry(&perf->metrics_idr, tmp, id) {
sys/dev/pci/drm/i915/selftests/i915_perf.c
56
if (!strcmp(tmp->uuid, TEST_OA_CONFIG_UUID)) {
sys/dev/pci/drm/i915/selftests/i915_perf.c
57
oa_config = tmp;
sys/dev/pci/drm/i915/selftests/i915_perf.c
74
struct i915_oa_config *oa_config = NULL, *tmp;
sys/dev/pci/drm/i915/selftests/i915_perf.c
79
idr_for_each_entry(&perf->metrics_idr, tmp, id) {
sys/dev/pci/drm/i915/selftests/i915_perf.c
80
if (!strcmp(tmp->uuid, TEST_OA_CONFIG_UUID)) {
sys/dev/pci/drm/i915/selftests/i915_perf.c
81
oa_config = i915_oa_config_get(tmp);
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
1188
unsigned long *tmp = dst;
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
1193
*tmp++ = *s++;
sys/dev/pci/drm/i915/selftests/intel_uncore.c
168
unsigned int tmp;
sys/dev/pci/drm/i915/selftests/intel_uncore.c
202
for_each_fw_domain(domain, uncore, tmp) {
sys/dev/pci/drm/i915/selftests/intel_uncore.c
224
for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
sys/dev/pci/drm/i915/selftests/intel_uncore.c
239
for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
sys/dev/pci/drm/i915/soc/intel_dram.c
67
u32 tmp;
sys/dev/pci/drm/i915/soc/intel_dram.c
69
tmp = intel_uncore_read(&dev_priv->uncore, CLKCFG);
sys/dev/pci/drm/i915/soc/intel_dram.c
71
switch (tmp & CLKCFG_MEM_MASK) {
sys/dev/pci/drm/include/drm/drm_fixed.h
66
u64 tmp = ((u64)A.full << 13);
sys/dev/pci/drm/include/drm/drm_fixed.h
68
do_div(tmp, B.full);
sys/dev/pci/drm/include/drm/drm_fixed.h
69
tmp += 1;
sys/dev/pci/drm/include/drm/drm_fixed.h
70
tmp /= 2;
sys/dev/pci/drm/include/drm/drm_fixed.h
71
return lower_32_bits(tmp);
sys/dev/pci/drm/include/drm/drm_format_helper.h
33
} tmp;
sys/dev/pci/drm/include/drm/drm_format_helper.h
37
.tmp = { \
sys/dev/pci/drm/include/drm/drm_panic.h
186
u8 *tmp, size_t tmp_size);
sys/dev/pci/drm/include/drm/ttm/ttm_bo.h
482
pgprot_t tmp);
sys/dev/pci/drm/include/drm/ttm/ttm_caching.h
55
pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp);
sys/dev/pci/drm/include/linux/hashtable.h
58
#define hash_for_each_safe(table, i, tmp, obj, member) \
sys/dev/pci/drm/include/linux/hashtable.h
60
hlist_for_each_entry_safe(obj, tmp, &table[i], member)
sys/dev/pci/drm/include/linux/wait.h
291
wait_queue_entry_t *tmp;
sys/dev/pci/drm/include/linux/wait.h
294
list_for_each_entry_safe(wqe, tmp, &wqh->head, entry) {
sys/dev/pci/drm/include/linux/wait.h
308
wait_queue_entry_t *tmp;
sys/dev/pci/drm/include/linux/wait.h
310
list_for_each_entry_safe(wqe, tmp, &wqh->head, entry) {
sys/dev/pci/drm/radeon/atombios_crtc.c
1148
u32 tmp, viewport_w, viewport_h;
sys/dev/pci/drm/radeon/atombios_crtc.c
1312
tmp = rdev->config.cayman.tile_config;
sys/dev/pci/drm/radeon/atombios_crtc.c
1314
tmp = rdev->config.evergreen.tile_config;
sys/dev/pci/drm/radeon/atombios_crtc.c
1316
switch ((tmp & 0xf0) >> 4) {
sys/dev/pci/drm/radeon/atombios_dp.c
413
u8 tmp;
sys/dev/pci/drm/radeon/atombios_dp.c
424
DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
sys/dev/pci/drm/radeon/atombios_dp.c
425
if (tmp & 1)
sys/dev/pci/drm/radeon/atombios_dp.c
436
DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
sys/dev/pci/drm/radeon/atombios_dp.c
437
if (tmp & 1)
sys/dev/pci/drm/radeon/atombios_dp.c
599
u8 tmp;
sys/dev/pci/drm/radeon/atombios_dp.c
616
tmp = dp_info->dp_lane_count;
sys/dev/pci/drm/radeon/atombios_dp.c
618
tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
sys/dev/pci/drm/radeon/atombios_dp.c
619
drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
sys/dev/pci/drm/radeon/atombios_dp.c
622
tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
sys/dev/pci/drm/radeon/atombios_dp.c
623
drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
sys/dev/pci/drm/radeon/atombios_dp.c
790
u8 tmp, frev, crev;
sys/dev/pci/drm/radeon/atombios_dp.c
826
if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
sys/dev/pci/drm/radeon/atombios_dp.c
828
if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
sys/dev/pci/drm/radeon/btc_dpm.c
1307
u32 tmp, bif;
sys/dev/pci/drm/radeon/btc_dpm.c
1309
tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
sys/dev/pci/drm/radeon/btc_dpm.c
1311
if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
sys/dev/pci/drm/radeon/btc_dpm.c
1312
(tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
sys/dev/pci/drm/radeon/btc_dpm.c
1318
tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
sys/dev/pci/drm/radeon/btc_dpm.c
1319
tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
sys/dev/pci/drm/radeon/btc_dpm.c
1320
tmp |= LC_GEN2_EN_STRAP;
sys/dev/pci/drm/radeon/btc_dpm.c
1322
tmp |= LC_CLR_FAILED_SPD_CHANGE_CNT;
sys/dev/pci/drm/radeon/btc_dpm.c
1323
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/pci/drm/radeon/btc_dpm.c
1325
tmp &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
sys/dev/pci/drm/radeon/btc_dpm.c
1326
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/pci/drm/radeon/btc_dpm.c
1330
if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
sys/dev/pci/drm/radeon/btc_dpm.c
1331
(tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
sys/dev/pci/drm/radeon/btc_dpm.c
1337
tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
sys/dev/pci/drm/radeon/btc_dpm.c
1338
tmp &= ~LC_GEN2_EN_STRAP;
sys/dev/pci/drm/radeon/btc_dpm.c
1340
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/pci/drm/radeon/btc_dpm.c
1414
u32 tmp;
sys/dev/pci/drm/radeon/btc_dpm.c
1417
tmp = RREG32(sequence[i]);
sys/dev/pci/drm/radeon/btc_dpm.c
1418
tmp &= ~sequence[i+2];
sys/dev/pci/drm/radeon/btc_dpm.c
1419
tmp |= sequence[i+1] & sequence[i+2];
sys/dev/pci/drm/radeon/btc_dpm.c
1420
WREG32(sequence[i], tmp);
sys/dev/pci/drm/radeon/btc_dpm.c
1891
u32 tmp;
sys/dev/pci/drm/radeon/btc_dpm.c
1896
tmp = RREG32(MC_PMG_CMD_EMRS);
sys/dev/pci/drm/radeon/btc_dpm.c
1901
((tmp & 0xffff0000)) |
sys/dev/pci/drm/radeon/btc_dpm.c
1909
tmp = RREG32(MC_PMG_CMD_MRS);
sys/dev/pci/drm/radeon/btc_dpm.c
1914
(tmp & 0xffff0000) |
sys/dev/pci/drm/radeon/btc_dpm.c
1925
tmp = RREG32(MC_PMG_CMD_MRS1);
sys/dev/pci/drm/radeon/btc_dpm.c
1930
(tmp & 0xffff0000) |
sys/dev/pci/drm/radeon/btc_dpm.c
2039
u32 tmp;
sys/dev/pci/drm/radeon/btc_dpm.c
2043
tmp = RREG32(MC_PMG_AUTO_CFG);
sys/dev/pci/drm/radeon/btc_dpm.c
2044
if ((0x200 & tmp) == 0) {
sys/dev/pci/drm/radeon/btc_dpm.c
2045
tmp = (tmp & 0xfffffc0b) | 0x204;
sys/dev/pci/drm/radeon/btc_dpm.c
2046
WREG32(MC_PMG_AUTO_CFG, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
1073
u32 tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
1096
tmp = RREG32_SMC(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
sys/dev/pci/drm/radeon/ci_dpm.c
1097
tmp |= FDO_STATIC_DUTY(duty);
sys/dev/pci/drm/radeon/ci_dpm.c
1098
WREG32_SMC(CG_FDO_CTRL0, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
1122
u32 tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
1127
tmp = RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
sys/dev/pci/drm/radeon/ci_dpm.c
1128
return (tmp >> FDO_PWM_MODE_SHIFT);
sys/dev/pci/drm/radeon/ci_dpm.c
1156
u32 tach_period, tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
1173
tmp = RREG32_SMC(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
sys/dev/pci/drm/radeon/ci_dpm.c
1174
tmp |= TARGET_PERIOD(tach_period);
sys/dev/pci/drm/radeon/ci_dpm.c
1175
WREG32_SMC(CG_TACH_CTRL, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
1186
u32 tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
1189
tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
sys/dev/pci/drm/radeon/ci_dpm.c
1190
tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode);
sys/dev/pci/drm/radeon/ci_dpm.c
1191
WREG32_SMC(CG_FDO_CTRL2, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
1193
tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
sys/dev/pci/drm/radeon/ci_dpm.c
1194
tmp |= TMIN(pi->t_min);
sys/dev/pci/drm/radeon/ci_dpm.c
1195
WREG32_SMC(CG_FDO_CTRL2, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
1210
u32 tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
1213
tmp = RREG32_SMC(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
sys/dev/pci/drm/radeon/ci_dpm.c
1214
tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution - 1);
sys/dev/pci/drm/radeon/ci_dpm.c
1215
WREG32_SMC(CG_TACH_CTRL, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
1218
tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
sys/dev/pci/drm/radeon/ci_dpm.c
1219
tmp |= TACH_PWM_RESP_RATE(0x28);
sys/dev/pci/drm/radeon/ci_dpm.c
1220
WREG32_SMC(CG_FDO_CTRL2, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
1278
u16 tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
1280
tmp = 45;
sys/dev/pci/drm/radeon/ci_dpm.c
1281
table->FpsHighT = cpu_to_be16(tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
1283
tmp = 30;
sys/dev/pci/drm/radeon/ci_dpm.c
1284
table->FpsLowT = cpu_to_be16(tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
1354
u32 tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
1374
tmp = RREG32_SMC(GENERAL_PWRMGT);
sys/dev/pci/drm/radeon/ci_dpm.c
1376
tmp &= ~THERMAL_PROTECTION_DIS;
sys/dev/pci/drm/radeon/ci_dpm.c
1378
tmp |= THERMAL_PROTECTION_DIS;
sys/dev/pci/drm/radeon/ci_dpm.c
1379
WREG32_SMC(GENERAL_PWRMGT, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
1381
tmp = RREG32_SMC(GENERAL_PWRMGT);
sys/dev/pci/drm/radeon/ci_dpm.c
1382
tmp |= THERMAL_PROTECTION_DIS;
sys/dev/pci/drm/radeon/ci_dpm.c
1383
WREG32_SMC(GENERAL_PWRMGT, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
1489
u32 tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
1491
tmp = RREG32_SMC(GENERAL_PWRMGT);
sys/dev/pci/drm/radeon/ci_dpm.c
1492
tmp |= GLOBAL_PWRMGT_EN;
sys/dev/pci/drm/radeon/ci_dpm.c
1493
WREG32_SMC(GENERAL_PWRMGT, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
1495
tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
sys/dev/pci/drm/radeon/ci_dpm.c
1496
tmp |= DYNAMIC_PM_EN;
sys/dev/pci/drm/radeon/ci_dpm.c
1497
WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
1550
u32 tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
1552
tmp = RREG32_SMC(GENERAL_PWRMGT);
sys/dev/pci/drm/radeon/ci_dpm.c
1553
tmp &= ~GLOBAL_PWRMGT_EN;
sys/dev/pci/drm/radeon/ci_dpm.c
1554
WREG32_SMC(GENERAL_PWRMGT, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
1556
tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
sys/dev/pci/drm/radeon/ci_dpm.c
1557
tmp &= ~DYNAMIC_PM_EN;
sys/dev/pci/drm/radeon/ci_dpm.c
1558
WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
1579
u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
sys/dev/pci/drm/radeon/ci_dpm.c
1582
tmp &= ~SCLK_PWRMGT_OFF;
sys/dev/pci/drm/radeon/ci_dpm.c
1584
tmp |= SCLK_PWRMGT_OFF;
sys/dev/pci/drm/radeon/ci_dpm.c
1585
WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
1617
u32 tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
1626
tmp = RREG32(SMC_RESP_0);
sys/dev/pci/drm/radeon/ci_dpm.c
1627
if (tmp != 0)
sys/dev/pci/drm/radeon/ci_dpm.c
1631
tmp = RREG32(SMC_RESP_0);
sys/dev/pci/drm/radeon/ci_dpm.c
1633
return (PPSMC_Result)tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
1777
u32 tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
1783
&tmp, pi->sram_end);
sys/dev/pci/drm/radeon/ci_dpm.c
1787
pi->dpm_table_start = tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
1792
&tmp, pi->sram_end);
sys/dev/pci/drm/radeon/ci_dpm.c
1796
pi->soft_regs_start = tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
1801
&tmp, pi->sram_end);
sys/dev/pci/drm/radeon/ci_dpm.c
1805
pi->mc_reg_table_start = tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
1810
&tmp, pi->sram_end);
sys/dev/pci/drm/radeon/ci_dpm.c
1814
pi->fan_table_start = tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
1819
&tmp, pi->sram_end);
sys/dev/pci/drm/radeon/ci_dpm.c
1823
pi->arb_table_start = tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
1865
u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
sys/dev/pci/drm/radeon/ci_dpm.c
1868
tmp &= ~THERMAL_PROTECTION_DIS;
sys/dev/pci/drm/radeon/ci_dpm.c
1870
tmp |= THERMAL_PROTECTION_DIS;
sys/dev/pci/drm/radeon/ci_dpm.c
1871
WREG32_SMC(GENERAL_PWRMGT, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
1876
u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
sys/dev/pci/drm/radeon/ci_dpm.c
1878
tmp |= STATIC_PM_EN;
sys/dev/pci/drm/radeon/ci_dpm.c
1880
WREG32_SMC(GENERAL_PWRMGT, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
1945
u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
sys/dev/pci/drm/radeon/ci_dpm.c
1952
tmp &= ~DISP_GAP_MASK;
sys/dev/pci/drm/radeon/ci_dpm.c
1954
tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
sys/dev/pci/drm/radeon/ci_dpm.c
1956
tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/pci/drm/radeon/ci_dpm.c
1957
WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
1966
tmp = pre_vbi_time_in_us * (ref_clock / 100);
sys/dev/pci/drm/radeon/ci_dpm.c
1968
WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
1980
u32 tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
1984
tmp = RREG32_SMC(GENERAL_PWRMGT);
sys/dev/pci/drm/radeon/ci_dpm.c
1985
tmp |= DYN_SPREAD_SPECTRUM_EN;
sys/dev/pci/drm/radeon/ci_dpm.c
1986
WREG32_SMC(GENERAL_PWRMGT, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
1989
tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
sys/dev/pci/drm/radeon/ci_dpm.c
1990
tmp &= ~SSEN;
sys/dev/pci/drm/radeon/ci_dpm.c
1991
WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
1993
tmp = RREG32_SMC(GENERAL_PWRMGT);
sys/dev/pci/drm/radeon/ci_dpm.c
1994
tmp &= ~DYN_SPREAD_SPECTRUM_EN;
sys/dev/pci/drm/radeon/ci_dpm.c
1995
WREG32_SMC(GENERAL_PWRMGT, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
2006
u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
sys/dev/pci/drm/radeon/ci_dpm.c
2008
tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK);
sys/dev/pci/drm/radeon/ci_dpm.c
2009
tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
sys/dev/pci/drm/radeon/ci_dpm.c
2012
WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
2017
u32 tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
2019
tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
sys/dev/pci/drm/radeon/ci_dpm.c
2020
tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
sys/dev/pci/drm/radeon/ci_dpm.c
2021
WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
2035
u32 tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
2037
tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
sys/dev/pci/drm/radeon/ci_dpm.c
2038
tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
sys/dev/pci/drm/radeon/ci_dpm.c
2039
WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
2372
u32 tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
2376
&tmp, pi->sram_end);
sys/dev/pci/drm/radeon/ci_dpm.c
2380
tmp &= 0x00FFFFFF;
sys/dev/pci/drm/radeon/ci_dpm.c
2381
tmp |= MC_CG_ARB_FREQ_F1 << 24;
sys/dev/pci/drm/radeon/ci_dpm.c
2384
tmp, pi->sram_end);
sys/dev/pci/drm/radeon/ci_dpm.c
2412
u32 tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
2420
tmp = sclk / (1 << i);
sys/dev/pci/drm/radeon/ci_dpm.c
2421
if (tmp >= min || i == 0)
sys/dev/pci/drm/radeon/ci_dpm.c
2441
u32 tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
2443
tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8;
sys/dev/pci/drm/radeon/ci_dpm.c
2445
if (tmp == MC_CG_ARB_FREQ_F0)
sys/dev/pci/drm/radeon/ci_dpm.c
2448
return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
sys/dev/pci/drm/radeon/ci_dpm.c
2457
u32 tmp, tmp2;
sys/dev/pci/drm/radeon/ci_dpm.c
2459
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/pci/drm/radeon/ci_dpm.c
2460
patch = (tmp & 0x0000f00) == 0x300;
sys/dev/pci/drm/radeon/ci_dpm.c
2786
u32 tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
2794
tmp = (freq_nom / reference_clock);
sys/dev/pci/drm/radeon/ci_dpm.c
2795
tmp = tmp * tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
2799
u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
sys/dev/pci/drm/radeon/ci_dpm.c
4030
u32 tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
4040
tmp = RREG32_SMC(DPM_TABLE_475);
sys/dev/pci/drm/radeon/ci_dpm.c
4041
tmp &= ~UvdBootLevel_MASK;
sys/dev/pci/drm/radeon/ci_dpm.c
4042
tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel);
sys/dev/pci/drm/radeon/ci_dpm.c
4043
WREG32_SMC(DPM_TABLE_475, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
4070
u32 tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
4078
tmp = RREG32_SMC(DPM_TABLE_475);
sys/dev/pci/drm/radeon/ci_dpm.c
4079
tmp &= ~VceBootLevel_MASK;
sys/dev/pci/drm/radeon/ci_dpm.c
4080
tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel);
sys/dev/pci/drm/radeon/ci_dpm.c
4081
WREG32_SMC(DPM_TABLE_475, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
4103
u32 tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
4108
tmp = RREG32_SMC(DPM_TABLE_475);
sys/dev/pci/drm/radeon/ci_dpm.c
4109
tmp &= ~AcpBootLevel_MASK;
sys/dev/pci/drm/radeon/ci_dpm.c
4110
tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
sys/dev/pci/drm/radeon/ci_dpm.c
4111
WREG32_SMC(DPM_TABLE_475, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
4160
u32 tmp, levels, i;
sys/dev/pci/drm/radeon/ci_dpm.c
4167
tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
sys/dev/pci/drm/radeon/ci_dpm.c
4168
while (tmp >>= 1)
sys/dev/pci/drm/radeon/ci_dpm.c
4175
tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
sys/dev/pci/drm/radeon/ci_dpm.c
4177
if (tmp == levels)
sys/dev/pci/drm/radeon/ci_dpm.c
4186
tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
sys/dev/pci/drm/radeon/ci_dpm.c
4187
while (tmp >>= 1)
sys/dev/pci/drm/radeon/ci_dpm.c
4194
tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
sys/dev/pci/drm/radeon/ci_dpm.c
4196
if (tmp == levels)
sys/dev/pci/drm/radeon/ci_dpm.c
4205
tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
sys/dev/pci/drm/radeon/ci_dpm.c
4206
while (tmp >>= 1)
sys/dev/pci/drm/radeon/ci_dpm.c
4213
tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
sys/dev/pci/drm/radeon/ci_dpm.c
4215
if (tmp == levels)
sys/dev/pci/drm/radeon/ci_dpm.c
4230
tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
sys/dev/pci/drm/radeon/ci_dpm.c
4232
if (tmp == levels)
sys/dev/pci/drm/radeon/ci_dpm.c
4245
tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
sys/dev/pci/drm/radeon/ci_dpm.c
4247
if (tmp == levels)
sys/dev/pci/drm/radeon/ci_dpm.c
4260
tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
sys/dev/pci/drm/radeon/ci_dpm.c
4262
if (tmp == levels)
sys/dev/pci/drm/radeon/ci_dpm.c
4488
u32 tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
4491
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/pci/drm/radeon/ci_dpm.c
4492
patch = (tmp & 0x0000f00) == 0x300;
sys/dev/pci/drm/radeon/ci_dpm.c
4565
tmp = RREG32(MC_SEQ_IO_DEBUG_DATA);
sys/dev/pci/drm/radeon/ci_dpm.c
4566
tmp = (tmp & 0xFFF8FFFF) | (1 << 16);
sys/dev/pci/drm/radeon/ci_dpm.c
4568
WREG32(MC_SEQ_IO_DEBUG_DATA, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
4741
u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
sys/dev/pci/drm/radeon/ci_dpm.c
4743
tmp |= VOLT_PWRMGT_EN;
sys/dev/pci/drm/radeon/ci_dpm.c
4744
WREG32_SMC(GENERAL_PWRMGT, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
5040
u32 tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
5042
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/pci/drm/radeon/ci_dpm.c
5044
if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
sys/dev/pci/drm/radeon/ci_dpm.c
5804
u32 tmp = RREG32_SMC(CNB_PWRMGT_CNTL);
sys/dev/pci/drm/radeon/ci_dpm.c
5808
tmp &= ~GNB_SLOW_MODE_MASK;
sys/dev/pci/drm/radeon/ci_dpm.c
5809
tmp |= GNB_SLOW_MODE(1);
sys/dev/pci/drm/radeon/ci_dpm.c
5812
tmp &= ~GNB_SLOW_MODE_MASK;
sys/dev/pci/drm/radeon/ci_dpm.c
5813
tmp |= GNB_SLOW_MODE(2);
sys/dev/pci/drm/radeon/ci_dpm.c
5816
tmp |= GNB_SLOW;
sys/dev/pci/drm/radeon/ci_dpm.c
5819
tmp |= FORCE_NB_PS1;
sys/dev/pci/drm/radeon/ci_dpm.c
5822
tmp |= DPM_ENABLED;
sys/dev/pci/drm/radeon/ci_dpm.c
5828
WREG32_SMC(CNB_PWRMGT_CNTL, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
845
u32 tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
856
tmp = RREG32_SMC(CG_THERMAL_INT);
sys/dev/pci/drm/radeon/ci_dpm.c
857
tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK);
sys/dev/pci/drm/radeon/ci_dpm.c
858
tmp |= CI_DIG_THERM_INTH(high_temp / 1000) |
sys/dev/pci/drm/radeon/ci_dpm.c
860
WREG32_SMC(CG_THERMAL_INT, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
864
tmp = RREG32_SMC(CG_THERMAL_CTRL);
sys/dev/pci/drm/radeon/ci_dpm.c
865
tmp &= DIG_THERM_DPM_MASK;
sys/dev/pci/drm/radeon/ci_dpm.c
866
tmp |= DIG_THERM_DPM(high_temp / 1000);
sys/dev/pci/drm/radeon/ci_dpm.c
867
WREG32_SMC(CG_THERMAL_CTRL, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
908
u32 tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
911
tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
sys/dev/pci/drm/radeon/ci_dpm.c
912
pi->fan_ctrl_default_mode = tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
913
tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
sys/dev/pci/drm/radeon/ci_dpm.c
914
pi->t_min = tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
918
tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
sys/dev/pci/drm/radeon/ci_dpm.c
919
tmp |= TMIN(0);
sys/dev/pci/drm/radeon/ci_dpm.c
920
WREG32_SMC(CG_FDO_CTRL2, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
922
tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
sys/dev/pci/drm/radeon/ci_dpm.c
923
tmp |= FDO_PWM_MODE(mode);
sys/dev/pci/drm/radeon/ci_dpm.c
924
WREG32_SMC(CG_FDO_CTRL2, tmp);
sys/dev/pci/drm/radeon/ci_dpm.c
934
u32 reference_clock, tmp;
sys/dev/pci/drm/radeon/ci_dpm.c
987
tmp = (RREG32_SMC(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
sys/dev/pci/drm/radeon/ci_dpm.c
988
fan_table.TempSrc = (uint8_t)tmp;
sys/dev/pci/drm/radeon/ci_smc.c
116
u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
sys/dev/pci/drm/radeon/ci_smc.c
118
tmp &= ~RST_REG;
sys/dev/pci/drm/radeon/ci_smc.c
119
WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
sys/dev/pci/drm/radeon/ci_smc.c
124
u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
sys/dev/pci/drm/radeon/ci_smc.c
126
tmp |= RST_REG;
sys/dev/pci/drm/radeon/ci_smc.c
127
WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
sys/dev/pci/drm/radeon/ci_smc.c
139
u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
sys/dev/pci/drm/radeon/ci_smc.c
141
tmp |= CK_DISABLE;
sys/dev/pci/drm/radeon/ci_smc.c
143
WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
sys/dev/pci/drm/radeon/ci_smc.c
148
u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
sys/dev/pci/drm/radeon/ci_smc.c
150
tmp &= ~CK_DISABLE;
sys/dev/pci/drm/radeon/ci_smc.c
152
WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
sys/dev/pci/drm/radeon/ci_smc.c
169
u32 tmp;
sys/dev/pci/drm/radeon/ci_smc.c
176
tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
sys/dev/pci/drm/radeon/ci_smc.c
177
if ((tmp & CKEN) == 0)
sys/dev/pci/drm/radeon/cik.c
1864
u32 running, tmp;
sys/dev/pci/drm/radeon/cik.c
1920
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/pci/drm/radeon/cik.c
1921
if ((rdev->pdev->device == 0x6649) && ((tmp & 0xff00) == 0x5600)) {
sys/dev/pci/drm/radeon/cik.c
3173
u32 tmp;
sys/dev/pci/drm/radeon/cik.c
3269
tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
sys/dev/pci/drm/radeon/cik.c
3270
rdev->config.cik.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
sys/dev/pci/drm/radeon/cik.c
3354
tmp = RREG32(SPI_CONFIG_CNTL);
sys/dev/pci/drm/radeon/cik.c
3355
tmp |= 0x03000000;
sys/dev/pci/drm/radeon/cik.c
3356
WREG32(SPI_CONFIG_CNTL, tmp);
sys/dev/pci/drm/radeon/cik.c
3362
tmp = RREG32(DB_DEBUG2) & ~0xf00fffff;
sys/dev/pci/drm/radeon/cik.c
3363
tmp |= 0x00000400;
sys/dev/pci/drm/radeon/cik.c
3364
WREG32(DB_DEBUG2, tmp);
sys/dev/pci/drm/radeon/cik.c
3366
tmp = RREG32(DB_DEBUG3) & ~0x0002021c;
sys/dev/pci/drm/radeon/cik.c
3367
tmp |= 0x00020200;
sys/dev/pci/drm/radeon/cik.c
3368
WREG32(DB_DEBUG3, tmp);
sys/dev/pci/drm/radeon/cik.c
3370
tmp = RREG32(CB_HW_CONTROL) & ~0x00010000;
sys/dev/pci/drm/radeon/cik.c
3371
tmp |= 0x00018208;
sys/dev/pci/drm/radeon/cik.c
3372
WREG32(CB_HW_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
3396
tmp = RREG32(HDP_MISC_CNTL);
sys/dev/pci/drm/radeon/cik.c
3397
tmp |= HDP_FLUSH_INVALIDATE_CACHE;
sys/dev/pci/drm/radeon/cik.c
3398
WREG32(HDP_MISC_CNTL, tmp);
sys/dev/pci/drm/radeon/cik.c
3448
uint32_t tmp = 0;
sys/dev/pci/drm/radeon/cik.c
3470
tmp = RREG32(scratch);
sys/dev/pci/drm/radeon/cik.c
3471
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/radeon/cik.c
3479
ring->idx, scratch, tmp);
sys/dev/pci/drm/radeon/cik.c
3773
uint32_t tmp = 0;
sys/dev/pci/drm/radeon/cik.c
3815
tmp = RREG32(scratch);
sys/dev/pci/drm/radeon/cik.c
3816
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/radeon/cik.c
3824
scratch, tmp);
sys/dev/pci/drm/radeon/cik.c
4049
u32 tmp;
sys/dev/pci/drm/radeon/cik.c
4070
tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
sys/dev/pci/drm/radeon/cik.c
4072
tmp |= BUF_SWAP_32BIT;
sys/dev/pci/drm/radeon/cik.c
4074
WREG32(CP_RB0_CNTL, tmp);
sys/dev/pci/drm/radeon/cik.c
4077
WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
sys/dev/pci/drm/radeon/cik.c
4089
tmp |= RB_NO_UPDATE;
sys/dev/pci/drm/radeon/cik.c
4092
WREG32(CP_RB0_CNTL, tmp);
sys/dev/pci/drm/radeon/cik.c
4187
u32 j, tmp;
sys/dev/pci/drm/radeon/cik.c
4191
tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
sys/dev/pci/drm/radeon/cik.c
4192
tmp &= ~WPTR_POLL_EN;
sys/dev/pci/drm/radeon/cik.c
4193
WREG32(CP_PQ_WPTR_POLL_CNTL, tmp);
sys/dev/pci/drm/radeon/cik.c
4511
u32 tmp;
sys/dev/pci/drm/radeon/cik.c
4525
tmp = RREG32(CP_CPF_DEBUG);
sys/dev/pci/drm/radeon/cik.c
4526
tmp |= (1 << 23);
sys/dev/pci/drm/radeon/cik.c
4527
WREG32(CP_CPF_DEBUG, tmp);
sys/dev/pci/drm/radeon/cik.c
4547
tmp = RREG32(CP_HPD_EOP_CONTROL);
sys/dev/pci/drm/radeon/cik.c
4548
tmp &= ~EOP_SIZE_MASK;
sys/dev/pci/drm/radeon/cik.c
4549
tmp |= order_base_2(MEC_HPD_SIZE / 8);
sys/dev/pci/drm/radeon/cik.c
4550
WREG32(CP_HPD_EOP_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
4610
tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
sys/dev/pci/drm/radeon/cik.c
4611
tmp &= ~WPTR_POLL_EN;
sys/dev/pci/drm/radeon/cik.c
4612
WREG32(CP_PQ_WPTR_POLL_CNTL, tmp);
sys/dev/pci/drm/radeon/cik.c
4845
u32 tmp;
sys/dev/pci/drm/radeon/cik.c
4848
tmp = RREG32(GRBM_STATUS);
sys/dev/pci/drm/radeon/cik.c
4849
if (tmp & (PA_BUSY | SC_BUSY |
sys/dev/pci/drm/radeon/cik.c
4857
if (tmp & (CP_BUSY | CP_COHERENCY_BUSY))
sys/dev/pci/drm/radeon/cik.c
4861
tmp = RREG32(GRBM_STATUS2);
sys/dev/pci/drm/radeon/cik.c
4862
if (tmp & RLC_BUSY)
sys/dev/pci/drm/radeon/cik.c
4866
tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/cik.c
4867
if (!(tmp & SDMA_IDLE))
sys/dev/pci/drm/radeon/cik.c
4871
tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/cik.c
4872
if (!(tmp & SDMA_IDLE))
sys/dev/pci/drm/radeon/cik.c
4876
tmp = RREG32(SRBM_STATUS2);
sys/dev/pci/drm/radeon/cik.c
4877
if (tmp & SDMA_BUSY)
sys/dev/pci/drm/radeon/cik.c
4880
if (tmp & SDMA1_BUSY)
sys/dev/pci/drm/radeon/cik.c
4884
tmp = RREG32(SRBM_STATUS);
sys/dev/pci/drm/radeon/cik.c
4886
if (tmp & IH_BUSY)
sys/dev/pci/drm/radeon/cik.c
4889
if (tmp & SEM_BUSY)
sys/dev/pci/drm/radeon/cik.c
4892
if (tmp & GRBM_RQ_PENDING)
sys/dev/pci/drm/radeon/cik.c
4895
if (tmp & VMC_BUSY)
sys/dev/pci/drm/radeon/cik.c
4898
if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
sys/dev/pci/drm/radeon/cik.c
4926
u32 tmp;
sys/dev/pci/drm/radeon/cik.c
4954
tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/cik.c
4955
tmp |= SDMA_HALT;
sys/dev/pci/drm/radeon/cik.c
4956
WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/cik.c
4960
tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/cik.c
4961
tmp |= SDMA_HALT;
sys/dev/pci/drm/radeon/cik.c
4962
WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/cik.c
5009
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/cik.c
5010
tmp |= grbm_soft_reset;
sys/dev/pci/drm/radeon/cik.c
5011
dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/radeon/cik.c
5012
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/cik.c
5013
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/cik.c
5017
tmp &= ~grbm_soft_reset;
sys/dev/pci/drm/radeon/cik.c
5018
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/cik.c
5019
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/cik.c
5023
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/cik.c
5024
tmp |= srbm_soft_reset;
sys/dev/pci/drm/radeon/cik.c
5025
dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/radeon/cik.c
5026
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/cik.c
5027
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/cik.c
5031
tmp &= ~srbm_soft_reset;
sys/dev/pci/drm/radeon/cik.c
5032
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/cik.c
5033
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/cik.c
5140
u32 tmp, i;
sys/dev/pci/drm/radeon/cik.c
5157
tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/cik.c
5158
tmp |= SDMA_HALT;
sys/dev/pci/drm/radeon/cik.c
5159
WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/cik.c
5161
tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/cik.c
5162
tmp |= SDMA_HALT;
sys/dev/pci/drm/radeon/cik.c
5163
WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/cik.c
5274
u32 tmp;
sys/dev/pci/drm/radeon/cik.c
5300
tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
sys/dev/pci/drm/radeon/cik.c
5301
tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
sys/dev/pci/drm/radeon/cik.c
5302
WREG32(MC_VM_FB_LOCATION, tmp);
sys/dev/pci/drm/radeon/cik.c
5330
u32 tmp;
sys/dev/pci/drm/radeon/cik.c
5335
tmp = RREG32(MC_ARB_RAMCFG);
sys/dev/pci/drm/radeon/cik.c
5336
if (tmp & CHANSIZE_MASK) {
sys/dev/pci/drm/radeon/cik.c
5341
tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/pci/drm/radeon/cik.c
5342
switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
sys/dev/pci/drm/radeon/cik.c
5496
u32 tmp = RREG32(CHUB_CONTROL);
sys/dev/pci/drm/radeon/cik.c
5497
tmp &= ~BYPASS_VM;
sys/dev/pci/drm/radeon/cik.c
5498
WREG32(CHUB_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
5621
u64 tmp = RREG32(MC_VM_FB_OFFSET);
sys/dev/pci/drm/radeon/cik.c
5622
tmp <<= 22;
sys/dev/pci/drm/radeon/cik.c
5623
rdev->vm_manager.vram_base_offset = tmp;
sys/dev/pci/drm/radeon/cik.c
5760
u32 tmp = RREG32(CP_INT_CNTL_RING0);
sys/dev/pci/drm/radeon/cik.c
5763
tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
sys/dev/pci/drm/radeon/cik.c
5765
tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
sys/dev/pci/drm/radeon/cik.c
5766
WREG32(CP_INT_CNTL_RING0, tmp);
sys/dev/pci/drm/radeon/cik.c
5771
u32 tmp;
sys/dev/pci/drm/radeon/cik.c
5773
tmp = RREG32(RLC_LB_CNTL);
sys/dev/pci/drm/radeon/cik.c
5775
tmp |= LOAD_BALANCE_ENABLE;
sys/dev/pci/drm/radeon/cik.c
5777
tmp &= ~LOAD_BALANCE_ENABLE;
sys/dev/pci/drm/radeon/cik.c
5778
WREG32(RLC_LB_CNTL, tmp);
sys/dev/pci/drm/radeon/cik.c
5808
u32 tmp;
sys/dev/pci/drm/radeon/cik.c
5810
tmp = RREG32(RLC_CNTL);
sys/dev/pci/drm/radeon/cik.c
5811
if (tmp != rlc)
sys/dev/pci/drm/radeon/cik.c
5841
u32 tmp, i, mask;
sys/dev/pci/drm/radeon/cik.c
5843
tmp = REQ | MESSAGE(MSG_ENTER_RLC_SAFE_MODE);
sys/dev/pci/drm/radeon/cik.c
5844
WREG32(RLC_GPR_REG2, tmp);
sys/dev/pci/drm/radeon/cik.c
5862
u32 tmp;
sys/dev/pci/drm/radeon/cik.c
5864
tmp = REQ | MESSAGE(MSG_EXIT_RLC_SAFE_MODE);
sys/dev/pci/drm/radeon/cik.c
5865
WREG32(RLC_GPR_REG2, tmp);
sys/dev/pci/drm/radeon/cik.c
5911
u32 i, size, tmp;
sys/dev/pci/drm/radeon/cik.c
5919
tmp = RREG32(RLC_CGCG_CGLS_CTRL) & 0xfffffffc;
sys/dev/pci/drm/radeon/cik.c
5920
WREG32(RLC_CGCG_CGLS_CTRL, tmp);
sys/dev/pci/drm/radeon/cik.c
5992
u32 data, orig, tmp, tmp2;
sys/dev/pci/drm/radeon/cik.c
5999
tmp = cik_halt_rlc(rdev);
sys/dev/pci/drm/radeon/cik.c
6007
cik_update_rlc(rdev, tmp);
sys/dev/pci/drm/radeon/cik.c
6028
u32 data, orig, tmp = 0;
sys/dev/pci/drm/radeon/cik.c
6046
tmp = cik_halt_rlc(rdev);
sys/dev/pci/drm/radeon/cik.c
6054
cik_update_rlc(rdev, tmp);
sys/dev/pci/drm/radeon/cik.c
6094
tmp = cik_halt_rlc(rdev);
sys/dev/pci/drm/radeon/cik.c
6102
cik_update_rlc(rdev, tmp);
sys/dev/pci/drm/radeon/cik.c
6526
u32 mask = 0, tmp, tmp1;
sys/dev/pci/drm/radeon/cik.c
6530
tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
sys/dev/pci/drm/radeon/cik.c
6534
tmp &= 0xffff0000;
sys/dev/pci/drm/radeon/cik.c
6536
tmp |= tmp1;
sys/dev/pci/drm/radeon/cik.c
6537
tmp >>= 16;
sys/dev/pci/drm/radeon/cik.c
6544
return (~tmp) & mask;
sys/dev/pci/drm/radeon/cik.c
6551
u32 tmp = 0;
sys/dev/pci/drm/radeon/cik.c
6568
tmp |= (cu_bitmap << (i * 16 + j * 8));
sys/dev/pci/drm/radeon/cik.c
6572
WREG32(RLC_PG_AO_CU_MASK, tmp);
sys/dev/pci/drm/radeon/cik.c
6574
tmp = RREG32(RLC_MAX_PG_CU);
sys/dev/pci/drm/radeon/cik.c
6575
tmp &= ~MAX_PU_CU_MASK;
sys/dev/pci/drm/radeon/cik.c
6576
tmp |= MAX_PU_CU(active_cu_number);
sys/dev/pci/drm/radeon/cik.c
6577
WREG32(RLC_MAX_PG_CU, tmp);
sys/dev/pci/drm/radeon/cik.c
6856
u32 tmp;
sys/dev/pci/drm/radeon/cik.c
6859
tmp = RREG32(CP_INT_CNTL_RING0) &
sys/dev/pci/drm/radeon/cik.c
6861
WREG32(CP_INT_CNTL_RING0, tmp);
sys/dev/pci/drm/radeon/cik.c
6863
tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
sys/dev/pci/drm/radeon/cik.c
6864
WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/cik.c
6865
tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
sys/dev/pci/drm/radeon/cik.c
6866
WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/cik.c
6909
tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/cik.c
6910
WREG32(DC_HPD1_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
6911
tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/cik.c
6912
WREG32(DC_HPD2_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
6913
tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/cik.c
6914
WREG32(DC_HPD3_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
6915
tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/cik.c
6916
WREG32(DC_HPD4_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
6917
tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/cik.c
6918
WREG32(DC_HPD5_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
6919
tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/cik.c
6920
WREG32(DC_HPD6_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
7287
u32 tmp;
sys/dev/pci/drm/radeon/cik.c
7364
tmp = RREG32(DC_HPD1_INT_CONTROL);
sys/dev/pci/drm/radeon/cik.c
7365
tmp |= DC_HPDx_INT_ACK;
sys/dev/pci/drm/radeon/cik.c
7366
WREG32(DC_HPD1_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
7369
tmp = RREG32(DC_HPD2_INT_CONTROL);
sys/dev/pci/drm/radeon/cik.c
7370
tmp |= DC_HPDx_INT_ACK;
sys/dev/pci/drm/radeon/cik.c
7371
WREG32(DC_HPD2_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
7374
tmp = RREG32(DC_HPD3_INT_CONTROL);
sys/dev/pci/drm/radeon/cik.c
7375
tmp |= DC_HPDx_INT_ACK;
sys/dev/pci/drm/radeon/cik.c
7376
WREG32(DC_HPD3_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
7379
tmp = RREG32(DC_HPD4_INT_CONTROL);
sys/dev/pci/drm/radeon/cik.c
7380
tmp |= DC_HPDx_INT_ACK;
sys/dev/pci/drm/radeon/cik.c
7381
WREG32(DC_HPD4_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
7384
tmp = RREG32(DC_HPD5_INT_CONTROL);
sys/dev/pci/drm/radeon/cik.c
7385
tmp |= DC_HPDx_INT_ACK;
sys/dev/pci/drm/radeon/cik.c
7386
WREG32(DC_HPD5_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
7389
tmp = RREG32(DC_HPD6_INT_CONTROL);
sys/dev/pci/drm/radeon/cik.c
7390
tmp |= DC_HPDx_INT_ACK;
sys/dev/pci/drm/radeon/cik.c
7391
WREG32(DC_HPD6_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
7394
tmp = RREG32(DC_HPD1_INT_CONTROL);
sys/dev/pci/drm/radeon/cik.c
7395
tmp |= DC_HPDx_RX_INT_ACK;
sys/dev/pci/drm/radeon/cik.c
7396
WREG32(DC_HPD1_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
7399
tmp = RREG32(DC_HPD2_INT_CONTROL);
sys/dev/pci/drm/radeon/cik.c
7400
tmp |= DC_HPDx_RX_INT_ACK;
sys/dev/pci/drm/radeon/cik.c
7401
WREG32(DC_HPD2_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
7404
tmp = RREG32(DC_HPD3_INT_CONTROL);
sys/dev/pci/drm/radeon/cik.c
7405
tmp |= DC_HPDx_RX_INT_ACK;
sys/dev/pci/drm/radeon/cik.c
7406
WREG32(DC_HPD3_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
7409
tmp = RREG32(DC_HPD4_INT_CONTROL);
sys/dev/pci/drm/radeon/cik.c
7410
tmp |= DC_HPDx_RX_INT_ACK;
sys/dev/pci/drm/radeon/cik.c
7411
WREG32(DC_HPD4_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
7414
tmp = RREG32(DC_HPD5_INT_CONTROL);
sys/dev/pci/drm/radeon/cik.c
7415
tmp |= DC_HPDx_RX_INT_ACK;
sys/dev/pci/drm/radeon/cik.c
7416
WREG32(DC_HPD5_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
7419
tmp = RREG32(DC_HPD6_INT_CONTROL);
sys/dev/pci/drm/radeon/cik.c
7420
tmp |= DC_HPDx_RX_INT_ACK;
sys/dev/pci/drm/radeon/cik.c
7421
WREG32(DC_HPD6_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/cik.c
7483
u32 wptr, tmp;
sys/dev/pci/drm/radeon/cik.c
7499
tmp = RREG32(IH_RB_CNTL);
sys/dev/pci/drm/radeon/cik.c
7500
tmp |= IH_WPTR_OVERFLOW_CLEAR;
sys/dev/pci/drm/radeon/cik.c
7501
WREG32(IH_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/cik.c
8751
u32 tmp = 0;
sys/dev/pci/drm/radeon/cik.c
8776
tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
sys/dev/pci/drm/radeon/cik.c
8779
tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(0));
sys/dev/pci/drm/radeon/cik.c
8784
tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
sys/dev/pci/drm/radeon/cik.c
8788
tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(1));
sys/dev/pci/drm/radeon/cik.c
8793
tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
sys/dev/pci/drm/radeon/cik.c
8797
tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(2));
sys/dev/pci/drm/radeon/cik.c
8804
WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/cik.c
8824
u32 tmp, buffer_alloc, i;
sys/dev/pci/drm/radeon/cik.c
8836
tmp = 1;
sys/dev/pci/drm/radeon/cik.c
8839
tmp = 2;
sys/dev/pci/drm/radeon/cik.c
8842
tmp = 0;
sys/dev/pci/drm/radeon/cik.c
8846
tmp = 0;
sys/dev/pci/drm/radeon/cik.c
8850
tmp = 1;
sys/dev/pci/drm/radeon/cik.c
8855
LB_MEMORY_CONFIG(tmp) | LB_MEMORY_SIZE(0x6B0));
sys/dev/pci/drm/radeon/cik.c
8867
switch (tmp) {
sys/dev/pci/drm/radeon/cik.c
8893
u32 tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/pci/drm/radeon/cik.c
8895
switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
sys/dev/pci/drm/radeon/cik.c
9125
u32 tmp, dmif_size = 12288;
sys/dev/pci/drm/radeon/cik.c
9144
tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
sys/dev/pci/drm/radeon/cik.c
9145
tmp = min(dfixed_trunc(a), tmp);
sys/dev/pci/drm/radeon/cik.c
9147
lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
sys/dev/pci/drm/radeon/cik.c
9258
u32 tmp, wm_mask;
sys/dev/pci/drm/radeon/cik.c
9353
tmp = wm_mask;
sys/dev/pci/drm/radeon/cik.c
9354
tmp &= ~LATENCY_WATERMARK_MASK(3);
sys/dev/pci/drm/radeon/cik.c
9355
tmp |= LATENCY_WATERMARK_MASK(1);
sys/dev/pci/drm/radeon/cik.c
9356
WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/cik.c
9361
tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
sys/dev/pci/drm/radeon/cik.c
9362
tmp &= ~LATENCY_WATERMARK_MASK(3);
sys/dev/pci/drm/radeon/cik.c
9363
tmp |= LATENCY_WATERMARK_MASK(2);
sys/dev/pci/drm/radeon/cik.c
9364
WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/cik.c
9432
uint32_t tmp;
sys/dev/pci/drm/radeon/cik.c
9439
tmp = RREG32_SMC(cntl_reg);
sys/dev/pci/drm/radeon/cik.c
9440
tmp &= ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK);
sys/dev/pci/drm/radeon/cik.c
9441
tmp |= dividers.post_divider;
sys/dev/pci/drm/radeon/cik.c
9442
WREG32_SMC(cntl_reg, tmp);
sys/dev/pci/drm/radeon/cik.c
9471
u32 tmp;
sys/dev/pci/drm/radeon/cik.c
9486
tmp = RREG32_SMC(CG_ECLK_CNTL);
sys/dev/pci/drm/radeon/cik.c
9487
tmp &= ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK);
sys/dev/pci/drm/radeon/cik.c
9488
tmp |= dividers.post_divider;
sys/dev/pci/drm/radeon/cik.c
9489
WREG32_SMC(CG_ECLK_CNTL, tmp);
sys/dev/pci/drm/radeon/cik.c
9555
u32 max_lw, current_lw, tmp;
sys/dev/pci/drm/radeon/cik.c
9560
tmp = RREG32_PCIE_PORT(PCIE_LC_STATUS1);
sys/dev/pci/drm/radeon/cik.c
9561
max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
sys/dev/pci/drm/radeon/cik.c
9562
current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
sys/dev/pci/drm/radeon/cik.c
9565
tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
sys/dev/pci/drm/radeon/cik.c
9566
if (tmp & LC_RENEGOTIATION_SUPPORT) {
sys/dev/pci/drm/radeon/cik.c
9567
tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
sys/dev/pci/drm/radeon/cik.c
9568
tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
sys/dev/pci/drm/radeon/cik.c
9569
tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
sys/dev/pci/drm/radeon/cik.c
9570
WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
sys/dev/pci/drm/radeon/cik.c
9594
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
sys/dev/pci/drm/radeon/cik.c
9595
tmp |= LC_SET_QUIESCE;
sys/dev/pci/drm/radeon/cik.c
9596
WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
sys/dev/pci/drm/radeon/cik.c
9598
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
sys/dev/pci/drm/radeon/cik.c
9599
tmp |= LC_REDO_EQ;
sys/dev/pci/drm/radeon/cik.c
9600
WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
sys/dev/pci/drm/radeon/cik.c
9628
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
sys/dev/pci/drm/radeon/cik.c
9629
tmp &= ~LC_SET_QUIESCE;
sys/dev/pci/drm/radeon/cik.c
9630
WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
sys/dev/pci/drm/radeon/cik_sdma.c
650
u32 tmp;
sys/dev/pci/drm/radeon/cik_sdma.c
660
tmp = 0xCAFEDEAD;
sys/dev/pci/drm/radeon/cik_sdma.c
661
rdev->wb.wb[index/4] = cpu_to_le32(tmp);
sys/dev/pci/drm/radeon/cik_sdma.c
676
tmp = le32_to_cpu(rdev->wb.wb[index/4]);
sys/dev/pci/drm/radeon/cik_sdma.c
677
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/radeon/cik_sdma.c
686
ring->idx, tmp);
sys/dev/pci/drm/radeon/cik_sdma.c
707
u32 tmp = 0;
sys/dev/pci/drm/radeon/cik_sdma.c
717
tmp = 0xCAFEDEAD;
sys/dev/pci/drm/radeon/cik_sdma.c
718
rdev->wb.wb[index/4] = cpu_to_le32(tmp);
sys/dev/pci/drm/radeon/cik_sdma.c
750
tmp = le32_to_cpu(rdev->wb.wb[index/4]);
sys/dev/pci/drm/radeon/cik_sdma.c
751
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/radeon/cik_sdma.c
758
DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
sys/dev/pci/drm/radeon/cypress_dpm.c
1579
u32 tmp = RREG32(GENERAL_PWRMGT);
sys/dev/pci/drm/radeon/cypress_dpm.c
1581
if (!(tmp & BACKBIAS_PAD_EN)) {
sys/dev/pci/drm/radeon/cypress_dpm.c
1588
if (tmp & BACKBIAS_VALUE)
sys/dev/pci/drm/radeon/cypress_dpm.c
1698
u32 tmp;
sys/dev/pci/drm/radeon/cypress_dpm.c
1704
&tmp, pi->sram_end);
sys/dev/pci/drm/radeon/cypress_dpm.c
1708
pi->state_table_start = (u16)tmp;
sys/dev/pci/drm/radeon/cypress_dpm.c
1713
&tmp, pi->sram_end);
sys/dev/pci/drm/radeon/cypress_dpm.c
1717
pi->soft_regs_start = (u16)tmp;
sys/dev/pci/drm/radeon/cypress_dpm.c
1722
&tmp, pi->sram_end);
sys/dev/pci/drm/radeon/cypress_dpm.c
1726
eg_pi->mc_reg_table_start = (u16)tmp;
sys/dev/pci/drm/radeon/cypress_dpm.c
1733
u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
sys/dev/pci/drm/radeon/cypress_dpm.c
1735
tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
sys/dev/pci/drm/radeon/cypress_dpm.c
1736
tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
sys/dev/pci/drm/radeon/cypress_dpm.c
1739
tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
sys/dev/pci/drm/radeon/cypress_dpm.c
1740
tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
sys/dev/pci/drm/radeon/cypress_dpm.c
1742
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/pci/drm/radeon/cypress_dpm.c
1747
u32 tmp, pipe;
sys/dev/pci/drm/radeon/cypress_dpm.c
1750
tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
sys/dev/pci/drm/radeon/cypress_dpm.c
1752
tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
sys/dev/pci/drm/radeon/cypress_dpm.c
1754
tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/pci/drm/radeon/cypress_dpm.c
1757
tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
sys/dev/pci/drm/radeon/cypress_dpm.c
1759
tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/pci/drm/radeon/cypress_dpm.c
1761
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/pci/drm/radeon/cypress_dpm.c
1763
tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
sys/dev/pci/drm/radeon/cypress_dpm.c
1764
pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
sys/dev/pci/drm/radeon/cypress_dpm.c
1778
tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
sys/dev/pci/drm/radeon/cypress_dpm.c
1779
tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
sys/dev/pci/drm/radeon/cypress_dpm.c
1780
WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
sys/dev/pci/drm/radeon/cypress_dpm.c
305
u32 tmp;
sys/dev/pci/drm/radeon/cypress_dpm.c
308
tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
sys/dev/pci/drm/radeon/cypress_dpm.c
309
if ((perf_req == PCIE_PERF_REQ_PECI_GEN1) && (tmp & LC_CURRENT_DATA_RATE))
sys/dev/pci/drm/radeon/cypress_dpm.c
330
u32 tmp;
sys/dev/pci/drm/radeon/cypress_dpm.c
336
tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
sys/dev/pci/drm/radeon/cypress_dpm.c
338
if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
sys/dev/pci/drm/radeon/cypress_dpm.c
339
(tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
sys/dev/pci/drm/radeon/cypress_dpm.c
52
u32 tmp, bif;
sys/dev/pci/drm/radeon/cypress_dpm.c
54
tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
sys/dev/pci/drm/radeon/cypress_dpm.c
56
if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
sys/dev/pci/drm/radeon/cypress_dpm.c
57
(tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
sys/dev/pci/drm/radeon/cypress_dpm.c
63
tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
sys/dev/pci/drm/radeon/cypress_dpm.c
64
tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
sys/dev/pci/drm/radeon/cypress_dpm.c
65
tmp |= LC_GEN2_EN_STRAP;
sys/dev/pci/drm/radeon/cypress_dpm.c
67
tmp |= LC_CLR_FAILED_SPD_CHANGE_CNT;
sys/dev/pci/drm/radeon/cypress_dpm.c
68
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/pci/drm/radeon/cypress_dpm.c
70
tmp &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
sys/dev/pci/drm/radeon/cypress_dpm.c
71
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/pci/drm/radeon/cypress_dpm.c
76
tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
sys/dev/pci/drm/radeon/cypress_dpm.c
77
tmp &= ~LC_GEN2_EN_STRAP;
sys/dev/pci/drm/radeon/cypress_dpm.c
79
if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
sys/dev/pci/drm/radeon/cypress_dpm.c
80
(tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
sys/dev/pci/drm/radeon/cypress_dpm.c
81
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/pci/drm/radeon/dce3_1_afmt.c
35
u32 tmp;
sys/dev/pci/drm/radeon/dce3_1_afmt.c
38
tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
sys/dev/pci/drm/radeon/dce3_1_afmt.c
39
tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
sys/dev/pci/drm/radeon/dce3_1_afmt.c
41
tmp |= HDMI_CONNECTION;
sys/dev/pci/drm/radeon/dce3_1_afmt.c
43
tmp |= SPEAKER_ALLOCATION(sadb[0]);
sys/dev/pci/drm/radeon/dce3_1_afmt.c
45
tmp |= SPEAKER_ALLOCATION(5); /* stereo */
sys/dev/pci/drm/radeon/dce3_1_afmt.c
46
WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
sys/dev/pci/drm/radeon/dce3_1_afmt.c
53
u32 tmp;
sys/dev/pci/drm/radeon/dce3_1_afmt.c
56
tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
sys/dev/pci/drm/radeon/dce3_1_afmt.c
57
tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
sys/dev/pci/drm/radeon/dce3_1_afmt.c
59
tmp |= DP_CONNECTION;
sys/dev/pci/drm/radeon/dce3_1_afmt.c
61
tmp |= SPEAKER_ALLOCATION(sadb[0]);
sys/dev/pci/drm/radeon/dce3_1_afmt.c
63
tmp |= SPEAKER_ALLOCATION(5); /* stereo */
sys/dev/pci/drm/radeon/dce3_1_afmt.c
64
WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
sys/dev/pci/drm/radeon/dce6_afmt.c
132
u32 tmp = 0;
sys/dev/pci/drm/radeon/dce6_afmt.c
139
tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
sys/dev/pci/drm/radeon/dce6_afmt.c
142
tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0);
sys/dev/pci/drm/radeon/dce6_afmt.c
145
tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
sys/dev/pci/drm/radeon/dce6_afmt.c
148
tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0);
sys/dev/pci/drm/radeon/dce6_afmt.c
151
AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
sys/dev/pci/drm/radeon/dce6_afmt.c
160
u32 tmp;
sys/dev/pci/drm/radeon/dce6_afmt.c
166
tmp = RREG32_ENDPOINT(dig->pin->offset,
sys/dev/pci/drm/radeon/dce6_afmt.c
168
tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
sys/dev/pci/drm/radeon/dce6_afmt.c
170
tmp |= HDMI_CONNECTION;
sys/dev/pci/drm/radeon/dce6_afmt.c
172
tmp |= SPEAKER_ALLOCATION(sadb[0]);
sys/dev/pci/drm/radeon/dce6_afmt.c
174
tmp |= SPEAKER_ALLOCATION(5); /* stereo */
sys/dev/pci/drm/radeon/dce6_afmt.c
176
AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
sys/dev/pci/drm/radeon/dce6_afmt.c
185
u32 tmp;
sys/dev/pci/drm/radeon/dce6_afmt.c
191
tmp = RREG32_ENDPOINT(dig->pin->offset,
sys/dev/pci/drm/radeon/dce6_afmt.c
193
tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
sys/dev/pci/drm/radeon/dce6_afmt.c
195
tmp |= DP_CONNECTION;
sys/dev/pci/drm/radeon/dce6_afmt.c
197
tmp |= SPEAKER_ALLOCATION(sadb[0]);
sys/dev/pci/drm/radeon/dce6_afmt.c
199
tmp |= SPEAKER_ALLOCATION(5); /* stereo */
sys/dev/pci/drm/radeon/dce6_afmt.c
201
AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
sys/dev/pci/drm/radeon/dce6_afmt.c
66
u32 offset, tmp;
sys/dev/pci/drm/radeon/dce6_afmt.c
70
tmp = RREG32_ENDPOINT(offset,
sys/dev/pci/drm/radeon/dce6_afmt.c
72
if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1)
sys/dev/pci/drm/radeon/evergreen.c
1300
u32 tmp = 0;
sys/dev/pci/drm/radeon/evergreen.c
1325
tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
sys/dev/pci/drm/radeon/evergreen.c
1328
tmp |= FMT_TRUNCATE_EN;
sys/dev/pci/drm/radeon/evergreen.c
1333
tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
sys/dev/pci/drm/radeon/evergreen.c
1337
tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH);
sys/dev/pci/drm/radeon/evergreen.c
1345
WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/evergreen.c
1679
u32 tmp;
sys/dev/pci/drm/radeon/evergreen.c
1685
tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
sys/dev/pci/drm/radeon/evergreen.c
1686
tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
sys/dev/pci/drm/radeon/evergreen.c
1687
WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/evergreen.c
1704
u32 tmp;
sys/dev/pci/drm/radeon/evergreen.c
1710
tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
sys/dev/pci/drm/radeon/evergreen.c
1711
tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
sys/dev/pci/drm/radeon/evergreen.c
1712
WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/evergreen.c
1769
u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
sys/dev/pci/drm/radeon/evergreen.c
1789
WREG32(DC_HPDx_CONTROL(hpd), tmp);
sys/dev/pci/drm/radeon/evergreen.c
1831
u32 tmp, buffer_alloc, i;
sys/dev/pci/drm/radeon/evergreen.c
1856
tmp = 0; /* 1/2 */
sys/dev/pci/drm/radeon/evergreen.c
1859
tmp = 2; /* whole */
sys/dev/pci/drm/radeon/evergreen.c
1863
tmp = 0;
sys/dev/pci/drm/radeon/evergreen.c
1869
tmp += 4;
sys/dev/pci/drm/radeon/evergreen.c
1870
WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/evergreen.c
1884
switch (tmp) {
sys/dev/pci/drm/radeon/evergreen.c
1919
u32 tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/pci/drm/radeon/evergreen.c
1921
switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
sys/dev/pci/drm/radeon/evergreen.c
2169
u32 tmp, arb_control3;
sys/dev/pci/drm/radeon/evergreen.c
2288
tmp = arb_control3;
sys/dev/pci/drm/radeon/evergreen.c
2289
tmp &= ~LATENCY_WATERMARK_MASK(3);
sys/dev/pci/drm/radeon/evergreen.c
2290
tmp |= LATENCY_WATERMARK_MASK(1);
sys/dev/pci/drm/radeon/evergreen.c
2291
WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2296
tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
sys/dev/pci/drm/radeon/evergreen.c
2297
tmp &= ~LATENCY_WATERMARK_MASK(3);
sys/dev/pci/drm/radeon/evergreen.c
2298
tmp |= LATENCY_WATERMARK_MASK(2);
sys/dev/pci/drm/radeon/evergreen.c
2299
WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2362
u32 tmp;
sys/dev/pci/drm/radeon/evergreen.c
2366
tmp = RREG32(SRBM_STATUS) & 0x1F00;
sys/dev/pci/drm/radeon/evergreen.c
2367
if (!tmp)
sys/dev/pci/drm/radeon/evergreen.c
2380
u32 tmp;
sys/dev/pci/drm/radeon/evergreen.c
2387
tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
sys/dev/pci/drm/radeon/evergreen.c
2388
tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
sys/dev/pci/drm/radeon/evergreen.c
2389
if (tmp == 2) {
sys/dev/pci/drm/radeon/evergreen.c
2393
if (tmp) {
sys/dev/pci/drm/radeon/evergreen.c
2402
u32 tmp;
sys/dev/pci/drm/radeon/evergreen.c
2419
tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
sys/dev/pci/drm/radeon/evergreen.c
2424
WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2425
WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2426
WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2428
WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2429
WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2430
WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2435
WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2437
WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2438
WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2439
WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2440
WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2460
u32 tmp;
sys/dev/pci/drm/radeon/evergreen.c
2472
tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
sys/dev/pci/drm/radeon/evergreen.c
2473
WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2474
WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2475
WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2476
WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2477
WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2478
WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2479
WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2493
u32 tmp;
sys/dev/pci/drm/radeon/evergreen.c
2502
tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
sys/dev/pci/drm/radeon/evergreen.c
2506
WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2507
WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2508
WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2509
WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2510
WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2511
WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2512
WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2665
u32 crtc_enabled, tmp, frame_count, blackout;
sys/dev/pci/drm/radeon/evergreen.c
2682
tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
2683
if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
sys/dev/pci/drm/radeon/evergreen.c
2686
tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
sys/dev/pci/drm/radeon/evergreen.c
2687
WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/evergreen.c
2691
tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
2692
if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
sys/dev/pci/drm/radeon/evergreen.c
2695
tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
sys/dev/pci/drm/radeon/evergreen.c
2696
WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/evergreen.c
2720
tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
2721
tmp &= ~EVERGREEN_CRTC_MASTER_EN;
sys/dev/pci/drm/radeon/evergreen.c
2722
WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/evergreen.c
2747
tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
2748
if (!(tmp & EVERGREEN_GRPH_UPDATE_LOCK)) {
sys/dev/pci/drm/radeon/evergreen.c
2749
tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
sys/dev/pci/drm/radeon/evergreen.c
2750
WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/evergreen.c
2752
tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
2753
if (!(tmp & 1)) {
sys/dev/pci/drm/radeon/evergreen.c
2754
tmp |= 1;
sys/dev/pci/drm/radeon/evergreen.c
2755
WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/evergreen.c
2763
u32 tmp, frame_count;
sys/dev/pci/drm/radeon/evergreen.c
2786
tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
2787
if ((tmp & 0x7) != 0) {
sys/dev/pci/drm/radeon/evergreen.c
2788
tmp &= ~0x7;
sys/dev/pci/drm/radeon/evergreen.c
2789
WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/evergreen.c
2791
tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
2792
if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) {
sys/dev/pci/drm/radeon/evergreen.c
2793
tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
sys/dev/pci/drm/radeon/evergreen.c
2794
WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/evergreen.c
2796
tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
2797
if (tmp & 1) {
sys/dev/pci/drm/radeon/evergreen.c
2798
tmp &= ~1;
sys/dev/pci/drm/radeon/evergreen.c
2799
WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/evergreen.c
2802
tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
2803
if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0)
sys/dev/pci/drm/radeon/evergreen.c
2811
tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
sys/dev/pci/drm/radeon/evergreen.c
2812
tmp &= ~BLACKOUT_MODE_MASK;
sys/dev/pci/drm/radeon/evergreen.c
2813
WREG32(MC_SHARED_BLACKOUT_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2820
tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
2821
tmp &= ~EVERGREEN_CRTC_BLANK_DATA_EN;
sys/dev/pci/drm/radeon/evergreen.c
2823
WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/evergreen.c
2826
tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
2827
tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
sys/dev/pci/drm/radeon/evergreen.c
2829
WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/evergreen.c
2852
u32 tmp;
sys/dev/pci/drm/radeon/evergreen.c
2897
tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
sys/dev/pci/drm/radeon/evergreen.c
2898
tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
sys/dev/pci/drm/radeon/evergreen.c
2899
tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
sys/dev/pci/drm/radeon/evergreen.c
2900
WREG32(MC_FUS_VM_FB_OFFSET, tmp);
sys/dev/pci/drm/radeon/evergreen.c
2902
tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
sys/dev/pci/drm/radeon/evergreen.c
2903
tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
sys/dev/pci/drm/radeon/evergreen.c
2904
WREG32(MC_VM_FB_LOCATION, tmp);
sys/dev/pci/drm/radeon/evergreen.c
3065
u32 tmp;
sys/dev/pci/drm/radeon/evergreen.c
3083
tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
sys/dev/pci/drm/radeon/evergreen.c
3085
tmp |= BUF_SWAP_32BIT;
sys/dev/pci/drm/radeon/evergreen.c
3087
WREG32(CP_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
3095
WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
sys/dev/pci/drm/radeon/evergreen.c
3109
tmp |= RB_NO_UPDATE;
sys/dev/pci/drm/radeon/evergreen.c
3114
WREG32(CP_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
3149
u32 hdp_host_path_cntl, tmp;
sys/dev/pci/drm/radeon/evergreen.c
3457
tmp = (((efuse_straps_4 & 0xf) << 4) |
sys/dev/pci/drm/radeon/evergreen.c
3460
tmp = 0;
sys/dev/pci/drm/radeon/evergreen.c
3467
tmp <<= 4;
sys/dev/pci/drm/radeon/evergreen.c
3468
tmp |= rb_disable_bitmap;
sys/dev/pci/drm/radeon/evergreen.c
3472
disabled_rb_mask = tmp;
sys/dev/pci/drm/radeon/evergreen.c
3473
tmp = 0;
sys/dev/pci/drm/radeon/evergreen.c
3475
tmp |= (1 << i);
sys/dev/pci/drm/radeon/evergreen.c
3477
if ((disabled_rb_mask & tmp) == tmp) {
sys/dev/pci/drm/radeon/evergreen.c
3489
tmp <<= 16;
sys/dev/pci/drm/radeon/evergreen.c
3490
tmp |= simd_disable_bitmap;
sys/dev/pci/drm/radeon/evergreen.c
3492
rdev->config.evergreen.active_simds = hweight32(~tmp);
sys/dev/pci/drm/radeon/evergreen.c
3509
tmp = 0x11111111;
sys/dev/pci/drm/radeon/evergreen.c
3512
tmp = 0x00000000;
sys/dev/pci/drm/radeon/evergreen.c
3515
tmp = gb_addr_config & NUM_PIPES_MASK;
sys/dev/pci/drm/radeon/evergreen.c
3516
tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
sys/dev/pci/drm/radeon/evergreen.c
3519
rdev->config.evergreen.backend_map = tmp;
sys/dev/pci/drm/radeon/evergreen.c
3520
WREG32(GB_BACKEND_MAP, tmp);
sys/dev/pci/drm/radeon/evergreen.c
3696
tmp = RREG32(HDP_MISC_CNTL);
sys/dev/pci/drm/radeon/evergreen.c
3697
tmp |= HDP_FLUSH_INVALIDATE_CACHE;
sys/dev/pci/drm/radeon/evergreen.c
3698
WREG32(HDP_MISC_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
3711
u32 tmp;
sys/dev/pci/drm/radeon/evergreen.c
3719
tmp = RREG32(FUS_MC_ARB_RAMCFG);
sys/dev/pci/drm/radeon/evergreen.c
3721
tmp = RREG32(MC_ARB_RAMCFG);
sys/dev/pci/drm/radeon/evergreen.c
3722
if (tmp & CHANSIZE_OVERRIDE) {
sys/dev/pci/drm/radeon/evergreen.c
3724
} else if (tmp & CHANSIZE_MASK) {
sys/dev/pci/drm/radeon/evergreen.c
3729
tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/pci/drm/radeon/evergreen.c
3730
switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
sys/dev/pci/drm/radeon/evergreen.c
3800
u32 i, j, tmp;
sys/dev/pci/drm/radeon/evergreen.c
3812
tmp = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/pci/drm/radeon/evergreen.c
3813
if (tmp != crtc_status[i])
sys/dev/pci/drm/radeon/evergreen.c
3828
u32 tmp;
sys/dev/pci/drm/radeon/evergreen.c
3831
tmp = RREG32(GRBM_STATUS);
sys/dev/pci/drm/radeon/evergreen.c
3832
if (tmp & (PA_BUSY | SC_BUSY |
sys/dev/pci/drm/radeon/evergreen.c
3839
if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
sys/dev/pci/drm/radeon/evergreen.c
3843
if (tmp & GRBM_EE_BUSY)
sys/dev/pci/drm/radeon/evergreen.c
3847
tmp = RREG32(DMA_STATUS_REG);
sys/dev/pci/drm/radeon/evergreen.c
3848
if (!(tmp & DMA_IDLE))
sys/dev/pci/drm/radeon/evergreen.c
3852
tmp = RREG32(SRBM_STATUS2);
sys/dev/pci/drm/radeon/evergreen.c
3853
if (tmp & DMA_BUSY)
sys/dev/pci/drm/radeon/evergreen.c
3857
tmp = RREG32(SRBM_STATUS);
sys/dev/pci/drm/radeon/evergreen.c
3858
if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
sys/dev/pci/drm/radeon/evergreen.c
3861
if (tmp & IH_BUSY)
sys/dev/pci/drm/radeon/evergreen.c
3864
if (tmp & SEM_BUSY)
sys/dev/pci/drm/radeon/evergreen.c
3867
if (tmp & GRBM_RQ_PENDING)
sys/dev/pci/drm/radeon/evergreen.c
3870
if (tmp & VMC_BUSY)
sys/dev/pci/drm/radeon/evergreen.c
3873
if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
sys/dev/pci/drm/radeon/evergreen.c
3881
tmp = RREG32(VM_L2_STATUS);
sys/dev/pci/drm/radeon/evergreen.c
3882
if (tmp & L2_BUSY)
sys/dev/pci/drm/radeon/evergreen.c
3898
u32 tmp;
sys/dev/pci/drm/radeon/evergreen.c
3912
tmp = RREG32(DMA_RB_CNTL);
sys/dev/pci/drm/radeon/evergreen.c
3913
tmp &= ~DMA_RB_ENABLE;
sys/dev/pci/drm/radeon/evergreen.c
3914
WREG32(DMA_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
3972
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/evergreen.c
3973
tmp |= grbm_soft_reset;
sys/dev/pci/drm/radeon/evergreen.c
3974
dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/radeon/evergreen.c
3975
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/evergreen.c
3976
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/evergreen.c
3980
tmp &= ~grbm_soft_reset;
sys/dev/pci/drm/radeon/evergreen.c
3981
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/evergreen.c
3982
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/evergreen.c
3986
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/evergreen.c
3987
tmp |= srbm_soft_reset;
sys/dev/pci/drm/radeon/evergreen.c
3988
dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/radeon/evergreen.c
3989
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/evergreen.c
3990
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/evergreen.c
3994
tmp &= ~srbm_soft_reset;
sys/dev/pci/drm/radeon/evergreen.c
3995
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/evergreen.c
3996
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/evergreen.c
4011
u32 tmp, i;
sys/dev/pci/drm/radeon/evergreen.c
4021
tmp = RREG32(DMA_RB_CNTL);
sys/dev/pci/drm/radeon/evergreen.c
4022
tmp &= ~DMA_RB_ENABLE;
sys/dev/pci/drm/radeon/evergreen.c
4023
WREG32(DMA_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
4397
u32 tmp = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;
sys/dev/pci/drm/radeon/evergreen.c
4398
tmp |= 0xffffffff << rdev->config.cayman.max_simds_per_se;
sys/dev/pci/drm/radeon/evergreen.c
4399
tmp = hweight32(~tmp);
sys/dev/pci/drm/radeon/evergreen.c
4400
if (tmp == rdev->config.cayman.max_simds_per_se) {
sys/dev/pci/drm/radeon/evergreen.c
4460
u32 tmp;
sys/dev/pci/drm/radeon/evergreen.c
4467
tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
sys/dev/pci/drm/radeon/evergreen.c
4468
WREG32(CAYMAN_DMA1_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
4471
tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
sys/dev/pci/drm/radeon/evergreen.c
4472
WREG32(DMA_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen.c
4677
u32 wptr, tmp;
sys/dev/pci/drm/radeon/evergreen.c
4693
tmp = RREG32(IH_RB_CNTL);
sys/dev/pci/drm/radeon/evergreen.c
4694
tmp |= IH_WPTR_OVERFLOW_CLEAR;
sys/dev/pci/drm/radeon/evergreen.c
4695
WREG32(IH_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/evergreen_cs.c
1099
u32 tmp, *ib;
sys/dev/pci/drm/radeon/evergreen_cs.c
1280
tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
sys/dev/pci/drm/radeon/evergreen_cs.c
1281
track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
sys/dev/pci/drm/radeon/evergreen_cs.c
1283
track->vgt_strmout_bo[tmp] = reloc->robj;
sys/dev/pci/drm/radeon/evergreen_cs.c
1290
tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
sys/dev/pci/drm/radeon/evergreen_cs.c
1292
track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
sys/dev/pci/drm/radeon/evergreen_cs.c
1318
tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;
sys/dev/pci/drm/radeon/evergreen_cs.c
1319
track->nsamples = 1 << tmp;
sys/dev/pci/drm/radeon/evergreen_cs.c
1327
tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK;
sys/dev/pci/drm/radeon/evergreen_cs.c
1328
track->nsamples = 1 << tmp;
sys/dev/pci/drm/radeon/evergreen_cs.c
1338
tmp = (reg - CB_COLOR0_VIEW) / 0x3c;
sys/dev/pci/drm/radeon/evergreen_cs.c
1339
track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
sys/dev/pci/drm/radeon/evergreen_cs.c
1346
tmp = ((reg - CB_COLOR8_VIEW) / 0x1c) + 8;
sys/dev/pci/drm/radeon/evergreen_cs.c
1347
track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
sys/dev/pci/drm/radeon/evergreen_cs.c
1358
tmp = (reg - CB_COLOR0_INFO) / 0x3c;
sys/dev/pci/drm/radeon/evergreen_cs.c
1359
track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
sys/dev/pci/drm/radeon/evergreen_cs.c
1368
track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
sys/dev/pci/drm/radeon/evergreen_cs.c
1376
tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8;
sys/dev/pci/drm/radeon/evergreen_cs.c
1377
track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
sys/dev/pci/drm/radeon/evergreen_cs.c
1386
track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
sys/dev/pci/drm/radeon/evergreen_cs.c
1398
tmp = (reg - CB_COLOR0_PITCH) / 0x3c;
sys/dev/pci/drm/radeon/evergreen_cs.c
1399
track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
sys/dev/pci/drm/radeon/evergreen_cs.c
1406
tmp = ((reg - CB_COLOR8_PITCH) / 0x1c) + 8;
sys/dev/pci/drm/radeon/evergreen_cs.c
1407
track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
sys/dev/pci/drm/radeon/evergreen_cs.c
1418
tmp = (reg - CB_COLOR0_SLICE) / 0x3c;
sys/dev/pci/drm/radeon/evergreen_cs.c
1419
track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
sys/dev/pci/drm/radeon/evergreen_cs.c
1420
track->cb_color_slice_idx[tmp] = idx;
sys/dev/pci/drm/radeon/evergreen_cs.c
1427
tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8;
sys/dev/pci/drm/radeon/evergreen_cs.c
1428
track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
sys/dev/pci/drm/radeon/evergreen_cs.c
1429
track->cb_color_slice_idx[tmp] = idx;
sys/dev/pci/drm/radeon/evergreen_cs.c
1460
tmp = ((reg - CB_COLOR0_ATTRIB) / 0x3c);
sys/dev/pci/drm/radeon/evergreen_cs.c
1461
track->cb_color_attrib[tmp] = ib[idx];
sys/dev/pci/drm/radeon/evergreen_cs.c
1488
tmp = ((reg - CB_COLOR8_ATTRIB) / 0x1c) + 8;
sys/dev/pci/drm/radeon/evergreen_cs.c
1489
track->cb_color_attrib[tmp] = ib[idx];
sys/dev/pci/drm/radeon/evergreen_cs.c
1500
tmp = (reg - CB_COLOR0_FMASK) / 0x3c;
sys/dev/pci/drm/radeon/evergreen_cs.c
1507
track->cb_color_fmask_bo[tmp] = reloc->robj;
sys/dev/pci/drm/radeon/evergreen_cs.c
1517
tmp = (reg - CB_COLOR0_CMASK) / 0x3c;
sys/dev/pci/drm/radeon/evergreen_cs.c
1524
track->cb_color_cmask_bo[tmp] = reloc->robj;
sys/dev/pci/drm/radeon/evergreen_cs.c
1534
tmp = (reg - CB_COLOR0_FMASK_SLICE) / 0x3c;
sys/dev/pci/drm/radeon/evergreen_cs.c
1535
track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx);
sys/dev/pci/drm/radeon/evergreen_cs.c
1545
tmp = (reg - CB_COLOR0_CMASK_SLICE) / 0x3c;
sys/dev/pci/drm/radeon/evergreen_cs.c
1546
track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx);
sys/dev/pci/drm/radeon/evergreen_cs.c
1562
tmp = (reg - CB_COLOR0_BASE) / 0x3c;
sys/dev/pci/drm/radeon/evergreen_cs.c
1563
track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
sys/dev/pci/drm/radeon/evergreen_cs.c
1565
track->cb_color_bo[tmp] = reloc->robj;
sys/dev/pci/drm/radeon/evergreen_cs.c
1578
tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8;
sys/dev/pci/drm/radeon/evergreen_cs.c
1579
track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
sys/dev/pci/drm/radeon/evergreen_cs.c
1581
track->cb_color_bo[tmp] = reloc->robj;
sys/dev/pci/drm/radeon/evergreen_cs.c
1794
int tmp;
sys/dev/pci/drm/radeon/evergreen_cs.c
1802
tmp = radeon_get_ib_value(p, idx + 1);
sys/dev/pci/drm/radeon/evergreen_cs.c
1803
pred_op = (tmp >> 16) & 0x7;
sys/dev/pci/drm/radeon/evergreen_cs.c
1822
((u64)(tmp & 0xff) << 32);
sys/dev/pci/drm/radeon/evergreen_cs.c
1825
ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
sys/dev/pci/drm/radeon/evergreen_cs.c
2116
u64 offset, tmp;
sys/dev/pci/drm/radeon/evergreen_cs.c
2156
tmp = radeon_get_ib_value(p, idx) +
sys/dev/pci/drm/radeon/evergreen_cs.c
2159
offset = reloc->gpu_offset + tmp;
sys/dev/pci/drm/radeon/evergreen_cs.c
2161
if ((tmp + size) > radeon_bo_size(reloc->robj)) {
sys/dev/pci/drm/radeon/evergreen_cs.c
2163
tmp + size, radeon_bo_size(reloc->robj));
sys/dev/pci/drm/radeon/evergreen_cs.c
2194
tmp = radeon_get_ib_value(p, idx+2) +
sys/dev/pci/drm/radeon/evergreen_cs.c
2197
offset = reloc->gpu_offset + tmp;
sys/dev/pci/drm/radeon/evergreen_cs.c
2199
if ((tmp + size) > radeon_bo_size(reloc->robj)) {
sys/dev/pci/drm/radeon/evergreen_cs.c
2201
tmp + size, radeon_bo_size(reloc->robj));
sys/dev/pci/drm/radeon/evergreen_cs.c
2767
u32 tmp;
sys/dev/pci/drm/radeon/evergreen_cs.c
2777
tmp = p->rdev->config.cayman.tile_config;
sys/dev/pci/drm/radeon/evergreen_cs.c
2780
tmp = p->rdev->config.evergreen.tile_config;
sys/dev/pci/drm/radeon/evergreen_cs.c
2785
switch (tmp & 0xf) {
sys/dev/pci/drm/radeon/evergreen_cs.c
2801
switch ((tmp & 0xf0) >> 4) {
sys/dev/pci/drm/radeon/evergreen_cs.c
2814
switch ((tmp & 0xf00) >> 8) {
sys/dev/pci/drm/radeon/evergreen_cs.c
2824
switch ((tmp & 0xf000) >> 12) {
sys/dev/pci/drm/radeon/evergreen_cs.c
453
u64 tmp, nby, bsize, size, min = 0;
sys/dev/pci/drm/radeon/evergreen_cs.c
460
tmp = (u64)track->cb_color_bo_offset[id] << 8;
sys/dev/pci/drm/radeon/evergreen_cs.c
463
if ((tmp + size * mslice) <= bsize) {
sys/dev/pci/drm/radeon/evergreen_cs.c
472
tmp += (u64)surf.layer_size * mslice;
sys/dev/pci/drm/radeon/evergreen_cs.c
473
if (tmp <= bsize) {
sys/dev/pci/drm/radeon/evergreen_cs.c
936
unsigned tmp, i;
sys/dev/pci/drm/radeon/evergreen_cs.c
974
tmp = track->cb_target_mask;
sys/dev/pci/drm/radeon/evergreen_cs.c
979
(tmp >> (i * 4)) & 0xF) {
sys/dev/pci/drm/radeon/evergreen_hdmi.c
103
u32 tmp = 0;
sys/dev/pci/drm/radeon/evergreen_hdmi.c
107
tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
sys/dev/pci/drm/radeon/evergreen_hdmi.c
110
tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
113
tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
sys/dev/pci/drm/radeon/evergreen_hdmi.c
116
tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
118
WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
125
u32 tmp;
sys/dev/pci/drm/radeon/evergreen_hdmi.c
128
tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
129
tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
131
tmp |= HDMI_CONNECTION;
sys/dev/pci/drm/radeon/evergreen_hdmi.c
133
tmp |= SPEAKER_ALLOCATION(sadb[0]);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
135
tmp |= SPEAKER_ALLOCATION(5); /* stereo */
sys/dev/pci/drm/radeon/evergreen_hdmi.c
136
WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
143
u32 tmp;
sys/dev/pci/drm/radeon/evergreen_hdmi.c
146
tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
147
tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
149
tmp |= DP_CONNECTION;
sys/dev/pci/drm/radeon/evergreen_hdmi.c
151
tmp |= SPEAKER_ALLOCATION(sadb[0]);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
153
tmp |= SPEAKER_ALLOCATION(5); /* stereo */
sys/dev/pci/drm/radeon/evergreen_hdmi.c
154
WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
43
u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
49
tmp |= AUDIO_ENABLED;
sys/dev/pci/drm/radeon/evergreen_hdmi.c
51
tmp |= PIN0_AUDIO_ENABLED;
sys/dev/pci/drm/radeon/evergreen_hdmi.c
53
tmp |= PIN1_AUDIO_ENABLED;
sys/dev/pci/drm/radeon/evergreen_hdmi.c
55
tmp |= PIN2_AUDIO_ENABLED;
sys/dev/pci/drm/radeon/evergreen_hdmi.c
57
tmp |= PIN3_AUDIO_ENABLED;
sys/dev/pci/drm/radeon/evergreen_hdmi.c
59
tmp &= ~(AUDIO_ENABLED |
sys/dev/pci/drm/radeon/evergreen_hdmi.c
66
WREG32(AZ_HOT_PLUG_CONTROL, tmp);
sys/dev/pci/drm/radeon/kv_dpm.c
1185
u16 tmp;
sys/dev/pci/drm/radeon/kv_dpm.c
1187
tmp = 45;
sys/dev/pci/drm/radeon/kv_dpm.c
1188
pi->fps_high_t = cpu_to_be16(tmp);
sys/dev/pci/drm/radeon/kv_dpm.c
1195
tmp = 30;
sys/dev/pci/drm/radeon/kv_dpm.c
1196
pi->fps_low_t = cpu_to_be16(tmp);
sys/dev/pci/drm/radeon/kv_dpm.c
2253
u32 tmp;
sys/dev/pci/drm/radeon/kv_dpm.c
2264
tmp = RREG32_SMC(CG_THERMAL_INT_CTRL);
sys/dev/pci/drm/radeon/kv_dpm.c
2265
tmp &= ~(DIG_THERM_INTH_MASK | DIG_THERM_INTL_MASK);
sys/dev/pci/drm/radeon/kv_dpm.c
2266
tmp |= (DIG_THERM_INTH(49 + (high_temp / 1000)) |
sys/dev/pci/drm/radeon/kv_dpm.c
2268
WREG32_SMC(CG_THERMAL_INT_CTRL, tmp);
sys/dev/pci/drm/radeon/kv_dpm.c
2604
u32 sclk, tmp;
sys/dev/pci/drm/radeon/kv_dpm.c
2611
tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
sys/dev/pci/drm/radeon/kv_dpm.c
2613
vddc = kv_convert_8bit_index_to_voltage(rdev, (u16)tmp);
sys/dev/pci/drm/radeon/kv_dpm.c
299
u32 tmp;
sys/dev/pci/drm/radeon/kv_dpm.c
304
&tmp, pi->sram_end);
sys/dev/pci/drm/radeon/kv_dpm.c
307
pi->dpm_table_start = tmp;
sys/dev/pci/drm/radeon/kv_dpm.c
311
&tmp, pi->sram_end);
sys/dev/pci/drm/radeon/kv_dpm.c
314
pi->soft_regs_start = tmp;
sys/dev/pci/drm/radeon/kv_dpm.c
487
u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
sys/dev/pci/drm/radeon/kv_dpm.c
489
tmp |= GLOBAL_PWRMGT_EN;
sys/dev/pci/drm/radeon/kv_dpm.c
490
WREG32_SMC(GENERAL_PWRMGT, tmp);
sys/dev/pci/drm/radeon/kv_smc.c
32
u32 tmp = 0;
sys/dev/pci/drm/radeon/kv_smc.c
41
tmp = RREG32(SMC_RESP_0) & SMC_RESP_MASK;
sys/dev/pci/drm/radeon/kv_smc.c
43
if (tmp != 1) {
sys/dev/pci/drm/radeon/kv_smc.c
44
if (tmp == 0xFF)
sys/dev/pci/drm/radeon/kv_smc.c
46
else if (tmp == 0xFE)
sys/dev/pci/drm/radeon/ni.c
1005
tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
sys/dev/pci/drm/radeon/ni.c
1006
rdev->config.cayman.num_tile_pipes = (1 << tmp);
sys/dev/pci/drm/radeon/ni.c
1007
tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
sys/dev/pci/drm/radeon/ni.c
1008
rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
sys/dev/pci/drm/radeon/ni.c
1009
tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
sys/dev/pci/drm/radeon/ni.c
1010
rdev->config.cayman.num_shader_engines = tmp + 1;
sys/dev/pci/drm/radeon/ni.c
1011
tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
sys/dev/pci/drm/radeon/ni.c
1012
rdev->config.cayman.num_gpus = tmp + 1;
sys/dev/pci/drm/radeon/ni.c
1013
tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
sys/dev/pci/drm/radeon/ni.c
1014
rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
sys/dev/pci/drm/radeon/ni.c
1015
tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
sys/dev/pci/drm/radeon/ni.c
1016
rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
sys/dev/pci/drm/radeon/ni.c
1065
tmp = 0;
sys/dev/pci/drm/radeon/ni.c
1072
tmp <<= 4;
sys/dev/pci/drm/radeon/ni.c
1073
tmp |= rb_disable_bitmap;
sys/dev/pci/drm/radeon/ni.c
1076
disabled_rb_mask = tmp;
sys/dev/pci/drm/radeon/ni.c
1077
tmp = 0;
sys/dev/pci/drm/radeon/ni.c
1079
tmp |= (1 << i);
sys/dev/pci/drm/radeon/ni.c
1081
if ((disabled_rb_mask & tmp) == tmp) {
sys/dev/pci/drm/radeon/ni.c
1093
tmp <<= 16;
sys/dev/pci/drm/radeon/ni.c
1094
tmp |= simd_disable_bitmap;
sys/dev/pci/drm/radeon/ni.c
1096
rdev->config.cayman.active_simds = hweight32(~tmp);
sys/dev/pci/drm/radeon/ni.c
1116
tmp = 0x00000000;
sys/dev/pci/drm/radeon/ni.c
1119
tmp = 0x11111111;
sys/dev/pci/drm/radeon/ni.c
1122
tmp = gb_addr_config & NUM_PIPES_MASK;
sys/dev/pci/drm/radeon/ni.c
1123
tmp = r6xx_remap_render_backend(rdev, tmp,
sys/dev/pci/drm/radeon/ni.c
1128
rdev->config.cayman.backend_map = tmp;
sys/dev/pci/drm/radeon/ni.c
1129
WREG32(GB_BACKEND_MAP, tmp);
sys/dev/pci/drm/radeon/ni.c
1214
tmp = RREG32(HDP_MISC_CNTL);
sys/dev/pci/drm/radeon/ni.c
1215
tmp |= HDP_FLUSH_INVALIDATE_CACHE;
sys/dev/pci/drm/radeon/ni.c
1216
WREG32(HDP_MISC_CNTL, tmp);
sys/dev/pci/drm/radeon/ni.c
1227
tmp = RREG32_CG(CG_CGTT_LOCAL_0);
sys/dev/pci/drm/radeon/ni.c
1228
tmp &= ~0x00380000;
sys/dev/pci/drm/radeon/ni.c
1229
WREG32_CG(CG_CGTT_LOCAL_0, tmp);
sys/dev/pci/drm/radeon/ni.c
1230
tmp = RREG32_CG(CG_CGTT_LOCAL_1);
sys/dev/pci/drm/radeon/ni.c
1231
tmp &= ~0x0e000000;
sys/dev/pci/drm/radeon/ni.c
1232
WREG32_CG(CG_CGTT_LOCAL_1, tmp);
sys/dev/pci/drm/radeon/ni.c
1723
u32 tmp;
sys/dev/pci/drm/radeon/ni.c
1726
tmp = RREG32(GRBM_STATUS);
sys/dev/pci/drm/radeon/ni.c
1727
if (tmp & (PA_BUSY | SC_BUSY |
sys/dev/pci/drm/radeon/ni.c
1735
if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
sys/dev/pci/drm/radeon/ni.c
1739
if (tmp & GRBM_EE_BUSY)
sys/dev/pci/drm/radeon/ni.c
1743
tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/ni.c
1744
if (!(tmp & DMA_IDLE))
sys/dev/pci/drm/radeon/ni.c
1748
tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/ni.c
1749
if (!(tmp & DMA_IDLE))
sys/dev/pci/drm/radeon/ni.c
1753
tmp = RREG32(SRBM_STATUS2);
sys/dev/pci/drm/radeon/ni.c
1754
if (tmp & DMA_BUSY)
sys/dev/pci/drm/radeon/ni.c
1757
if (tmp & DMA1_BUSY)
sys/dev/pci/drm/radeon/ni.c
1761
tmp = RREG32(SRBM_STATUS);
sys/dev/pci/drm/radeon/ni.c
1762
if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
sys/dev/pci/drm/radeon/ni.c
1765
if (tmp & IH_BUSY)
sys/dev/pci/drm/radeon/ni.c
1768
if (tmp & SEM_BUSY)
sys/dev/pci/drm/radeon/ni.c
1771
if (tmp & GRBM_RQ_PENDING)
sys/dev/pci/drm/radeon/ni.c
1774
if (tmp & VMC_BUSY)
sys/dev/pci/drm/radeon/ni.c
1777
if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
sys/dev/pci/drm/radeon/ni.c
1785
tmp = RREG32(VM_L2_STATUS);
sys/dev/pci/drm/radeon/ni.c
1786
if (tmp & L2_BUSY)
sys/dev/pci/drm/radeon/ni.c
1802
u32 tmp;
sys/dev/pci/drm/radeon/ni.c
1824
tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/ni.c
1825
tmp &= ~DMA_RB_ENABLE;
sys/dev/pci/drm/radeon/ni.c
1826
WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/ni.c
1831
tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/ni.c
1832
tmp &= ~DMA_RB_ENABLE;
sys/dev/pci/drm/radeon/ni.c
1833
WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/ni.c
1894
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/ni.c
1895
tmp |= grbm_soft_reset;
sys/dev/pci/drm/radeon/ni.c
1896
dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/radeon/ni.c
1897
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/ni.c
1898
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/ni.c
1902
tmp &= ~grbm_soft_reset;
sys/dev/pci/drm/radeon/ni.c
1903
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/ni.c
1904
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/ni.c
1908
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/ni.c
1909
tmp |= srbm_soft_reset;
sys/dev/pci/drm/radeon/ni.c
1910
dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/radeon/ni.c
1911
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/ni.c
1912
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/ni.c
1916
tmp &= ~srbm_soft_reset;
sys/dev/pci/drm/radeon/ni.c
1917
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/ni.c
1918
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/ni.c
2484
u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
sys/dev/pci/drm/radeon/ni.c
2485
tmp <<= 22;
sys/dev/pci/drm/radeon/ni.c
2486
rdev->vm_manager.vram_base_offset = tmp;
sys/dev/pci/drm/radeon/ni.c
874
u32 tmp;
sys/dev/pci/drm/radeon/ni.c
996
tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
sys/dev/pci/drm/radeon/ni.c
997
rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
sys/dev/pci/drm/radeon/ni_dpm.c
1082
u32 tmp;
sys/dev/pci/drm/radeon/ni_dpm.c
1086
tmp = RREG32(LB_SYNC_RESET_SEL) & LB_SYNC_RESET_SEL_MASK;
sys/dev/pci/drm/radeon/ni_dpm.c
1087
if (tmp != 1)
sys/dev/pci/drm/radeon/ni_dpm.c
1102
u32 tmp;
sys/dev/pci/drm/radeon/ni_dpm.c
1108
&tmp, pi->sram_end);
sys/dev/pci/drm/radeon/ni_dpm.c
1113
pi->state_table_start = (u16)tmp;
sys/dev/pci/drm/radeon/ni_dpm.c
1118
&tmp, pi->sram_end);
sys/dev/pci/drm/radeon/ni_dpm.c
1123
pi->soft_regs_start = (u16)tmp;
sys/dev/pci/drm/radeon/ni_dpm.c
1128
&tmp, pi->sram_end);
sys/dev/pci/drm/radeon/ni_dpm.c
1133
eg_pi->mc_reg_table_start = (u16)tmp;
sys/dev/pci/drm/radeon/ni_dpm.c
1138
&tmp, pi->sram_end);
sys/dev/pci/drm/radeon/ni_dpm.c
1143
ni_pi->fan_table_start = (u16)tmp;
sys/dev/pci/drm/radeon/ni_dpm.c
1148
&tmp, pi->sram_end);
sys/dev/pci/drm/radeon/ni_dpm.c
1153
ni_pi->arb_table_start = (u16)tmp;
sys/dev/pci/drm/radeon/ni_dpm.c
1158
&tmp, pi->sram_end);
sys/dev/pci/drm/radeon/ni_dpm.c
1163
ni_pi->cac_table_start = (u16)tmp;
sys/dev/pci/drm/radeon/ni_dpm.c
1168
&tmp, pi->sram_end);
sys/dev/pci/drm/radeon/ni_dpm.c
1173
ni_pi->spll_table_start = (u16)tmp;
sys/dev/pci/drm/radeon/ni_dpm.c
1367
u32 tmp = RREG32(CG_CAC_CTRL) & TID_CNT_MASK;
sys/dev/pci/drm/radeon/ni_dpm.c
1372
return tmp * xclk_period;
sys/dev/pci/drm/radeon/ni_dpm.c
1395
u64 tmp, n, d;
sys/dev/pci/drm/radeon/ni_dpm.c
1422
tmp = div64_u64(n, d);
sys/dev/pci/drm/radeon/ni_dpm.c
1424
if (tmp >> 32)
sys/dev/pci/drm/radeon/ni_dpm.c
1426
power_boost_limit = (u32)tmp;
sys/dev/pci/drm/radeon/ni_dpm.c
1573
u32 tmp;
sys/dev/pci/drm/radeon/ni_dpm.c
1577
&tmp, pi->sram_end);
sys/dev/pci/drm/radeon/ni_dpm.c
1581
tmp &= 0x00FFFFFF;
sys/dev/pci/drm/radeon/ni_dpm.c
1582
tmp |= ((u32)MC_CG_ARB_FREQ_F1) << 24;
sys/dev/pci/drm/radeon/ni_dpm.c
1585
tmp, pi->sram_end);
sys/dev/pci/drm/radeon/ni_dpm.c
1597
u32 tmp;
sys/dev/pci/drm/radeon/ni_dpm.c
1601
&tmp, pi->sram_end);
sys/dev/pci/drm/radeon/ni_dpm.c
1605
tmp = (tmp >> 24) & 0xff;
sys/dev/pci/drm/radeon/ni_dpm.c
1607
if (tmp == MC_CG_ARB_FREQ_F0)
sys/dev/pci/drm/radeon/ni_dpm.c
1610
return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
sys/dev/pci/drm/radeon/ni_dpm.c
2011
u64 tmp;
sys/dev/pci/drm/radeon/ni_dpm.c
2025
tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834;
sys/dev/pci/drm/radeon/ni_dpm.c
2026
do_div(tmp, reference_clock);
sys/dev/pci/drm/radeon/ni_dpm.c
2027
fbdiv = (u32) tmp;
sys/dev/pci/drm/radeon/ni_dpm.c
2102
u32 tmp;
sys/dev/pci/drm/radeon/ni_dpm.c
2140
tmp = ((fb_div << SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
sys/dev/pci/drm/radeon/ni_dpm.c
2142
spll_table->freq[i] = cpu_to_be32(tmp);
sys/dev/pci/drm/radeon/ni_dpm.c
2144
tmp = ((clk_v << SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
sys/dev/pci/drm/radeon/ni_dpm.c
2146
spll_table->ss[i] = cpu_to_be32(tmp);
sys/dev/pci/drm/radeon/ni_dpm.c
2323
u32 tmp = RREG32(DC_STUTTER_CNTL);
sys/dev/pci/drm/radeon/ni_dpm.c
2336
(tmp & DC_STUTTER_ENABLE_A) &&
sys/dev/pci/drm/radeon/ni_dpm.c
2337
(tmp & DC_STUTTER_ENABLE_B))
sys/dev/pci/drm/radeon/ni_dpm.c
3442
u32 tmp;
sys/dev/pci/drm/radeon/ni_dpm.c
3444
tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
sys/dev/pci/drm/radeon/ni_dpm.c
3446
if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
sys/dev/pci/drm/radeon/ni_dpm.c
3447
(tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
sys/dev/pci/drm/radeon/ni_dpm.c
3462
u32 tmp, bif;
sys/dev/pci/drm/radeon/ni_dpm.c
3464
tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
sys/dev/pci/drm/radeon/ni_dpm.c
3466
if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
sys/dev/pci/drm/radeon/ni_dpm.c
3467
(tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
sys/dev/pci/drm/radeon/ni_dpm.c
3474
tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
sys/dev/pci/drm/radeon/ni_dpm.c
3475
tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
sys/dev/pci/drm/radeon/ni_dpm.c
3476
tmp |= LC_GEN2_EN_STRAP;
sys/dev/pci/drm/radeon/ni_dpm.c
3478
tmp |= LC_CLR_FAILED_SPD_CHANGE_CNT;
sys/dev/pci/drm/radeon/ni_dpm.c
3479
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/pci/drm/radeon/ni_dpm.c
3481
tmp &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
sys/dev/pci/drm/radeon/ni_dpm.c
3482
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/pci/drm/radeon/ni_dpm.c
3489
tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
sys/dev/pci/drm/radeon/ni_dpm.c
3490
tmp &= ~LC_GEN2_EN_STRAP;
sys/dev/pci/drm/radeon/ni_dpm.c
3492
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
1151
uint32_t tmp;
sys/dev/pci/drm/radeon/r100.c
1198
tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
sys/dev/pci/drm/radeon/r100.c
1202
tmp |= RADEON_BUF_SWAP_32BIT;
sys/dev/pci/drm/radeon/r100.c
1204
WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
sys/dev/pci/drm/radeon/r100.c
1210
WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
sys/dev/pci/drm/radeon/r100.c
1223
tmp |= RADEON_RB_NO_UPDATE;
sys/dev/pci/drm/radeon/r100.c
1227
WREG32(RADEON_CP_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
1295
u32 tmp;
sys/dev/pci/drm/radeon/r100.c
1308
tmp = value & 0x003fffff;
sys/dev/pci/drm/radeon/r100.c
1309
tmp += (((u32)reloc->gpu_offset) >> 10);
sys/dev/pci/drm/radeon/r100.c
1323
tmp |= tile_flags;
sys/dev/pci/drm/radeon/r100.c
1324
p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
sys/dev/pci/drm/radeon/r100.c
1326
p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
sys/dev/pci/drm/radeon/r100.c
1587
uint32_t tmp;
sys/dev/pci/drm/radeon/r100.c
1659
tmp = idx_value & ~(0x7 << 2);
sys/dev/pci/drm/radeon/r100.c
1660
tmp |= tile_flags;
sys/dev/pci/drm/radeon/r100.c
1661
ib[idx] = tmp + ((u32)reloc->gpu_offset);
sys/dev/pci/drm/radeon/r100.c
169
u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
sys/dev/pci/drm/radeon/r100.c
174
WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/r100.c
1740
tmp = idx_value & ~(0x7 << 16);
sys/dev/pci/drm/radeon/r100.c
1741
tmp |= tile_flags;
sys/dev/pci/drm/radeon/r100.c
1742
ib[idx] = tmp;
sys/dev/pci/drm/radeon/r100.c
1842
tmp = (idx_value >> 23) & 0x7;
sys/dev/pci/drm/radeon/r100.c
1843
if (tmp == 2 || tmp == 6)
sys/dev/pci/drm/radeon/r100.c
1845
tmp = (idx_value >> 27) & 0x7;
sys/dev/pci/drm/radeon/r100.c
1846
if (tmp == 2 || tmp == 6)
sys/dev/pci/drm/radeon/r100.c
1906
tmp = idx_value;
sys/dev/pci/drm/radeon/r100.c
1909
track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
sys/dev/pci/drm/radeon/r100.c
1910
track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
sys/dev/pci/drm/radeon/r100.c
192
tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
sys/dev/pci/drm/radeon/r100.c
193
WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/r100.c
2502
uint32_t tmp;
sys/dev/pci/drm/radeon/r100.c
2505
tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
sys/dev/pci/drm/radeon/r100.c
2506
if (tmp >= n) {
sys/dev/pci/drm/radeon/r100.c
2517
uint32_t tmp;
sys/dev/pci/drm/radeon/r100.c
2523
tmp = RREG32(RADEON_RBBM_STATUS);
sys/dev/pci/drm/radeon/r100.c
2524
if (!(tmp & RADEON_RBBM_ACTIVE)) {
sys/dev/pci/drm/radeon/r100.c
2535
uint32_t tmp;
sys/dev/pci/drm/radeon/r100.c
2539
tmp = RREG32(RADEON_MC_STATUS);
sys/dev/pci/drm/radeon/r100.c
2540
if (tmp & RADEON_MC_IDLE) {
sys/dev/pci/drm/radeon/r100.c
2563
uint32_t tmp;
sys/dev/pci/drm/radeon/r100.c
2565
tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
sys/dev/pci/drm/radeon/r100.c
2566
WREG32(RADEON_BUS_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
2571
u32 tmp;
sys/dev/pci/drm/radeon/r100.c
2574
tmp = RREG32(R_000030_BUS_CNTL);
sys/dev/pci/drm/radeon/r100.c
2575
WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
sys/dev/pci/drm/radeon/r100.c
2577
WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
sys/dev/pci/drm/radeon/r100.c
2579
WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
sys/dev/pci/drm/radeon/r100.c
2580
tmp = RREG32(RADEON_BUS_CNTL);
sys/dev/pci/drm/radeon/r100.c
2589
u32 status, tmp;
sys/dev/pci/drm/radeon/r100.c
2601
tmp = RREG32(RADEON_CP_RB_CNTL);
sys/dev/pci/drm/radeon/r100.c
2602
WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
sys/dev/pci/drm/radeon/r100.c
2605
WREG32(RADEON_CP_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
2645
u32 tmp;
sys/dev/pci/drm/radeon/r100.c
2719
tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
sys/dev/pci/drm/radeon/r100.c
2720
tmp &= ~RADEON_PM_MODE_SEL;
sys/dev/pci/drm/radeon/r100.c
2721
WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
2730
uint32_t tmp;
sys/dev/pci/drm/radeon/r100.c
2740
tmp = RREG32(RADEON_MEM_CNTL);
sys/dev/pci/drm/radeon/r100.c
2741
if (tmp & RV100_HALF_MODE) {
sys/dev/pci/drm/radeon/r100.c
2751
tmp = RREG32(RADEON_MEM_CNTL);
sys/dev/pci/drm/radeon/r100.c
2752
if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
sys/dev/pci/drm/radeon/r100.c
2899
uint32_t save, tmp;
sys/dev/pci/drm/radeon/r100.c
2902
tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
sys/dev/pci/drm/radeon/r100.c
2903
WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
sys/dev/pci/drm/radeon/r100.c
2904
tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
sys/dev/pci/drm/radeon/r100.c
3000
uint32_t csq_stat, csq2_stat, tmp;
sys/dev/pci/drm/radeon/r100.c
3027
tmp = RREG32(RADEON_CP_CSQ_DATA);
sys/dev/pci/drm/radeon/r100.c
3028
seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
sys/dev/pci/drm/radeon/r100.c
3033
tmp = RREG32(RADEON_CP_CSQ_DATA);
sys/dev/pci/drm/radeon/r100.c
3034
seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
sys/dev/pci/drm/radeon/r100.c
3039
tmp = RREG32(RADEON_CP_CSQ_DATA);
sys/dev/pci/drm/radeon/r100.c
3040
seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
sys/dev/pci/drm/radeon/r100.c
3048
uint32_t tmp;
sys/dev/pci/drm/radeon/r100.c
3050
tmp = RREG32(RADEON_CONFIG_MEMSIZE);
sys/dev/pci/drm/radeon/r100.c
3051
seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/r100.c
3052
tmp = RREG32(RADEON_MC_FB_LOCATION);
sys/dev/pci/drm/radeon/r100.c
3053
seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/r100.c
3054
tmp = RREG32(RADEON_BUS_CNTL);
sys/dev/pci/drm/radeon/r100.c
3055
seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/r100.c
3056
tmp = RREG32(RADEON_MC_AGP_LOCATION);
sys/dev/pci/drm/radeon/r100.c
3057
seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/r100.c
3058
tmp = RREG32(RADEON_AGP_BASE);
sys/dev/pci/drm/radeon/r100.c
3059
seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/r100.c
3060
tmp = RREG32(RADEON_HOST_PATH_CNTL);
sys/dev/pci/drm/radeon/r100.c
3061
seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/r100.c
3062
tmp = RREG32(0x01D0);
sys/dev/pci/drm/radeon/r100.c
3063
seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/r100.c
3064
tmp = RREG32(RADEON_AIC_LO_ADDR);
sys/dev/pci/drm/radeon/r100.c
3065
seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/r100.c
3066
tmp = RREG32(RADEON_AIC_HI_ADDR);
sys/dev/pci/drm/radeon/r100.c
3067
seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/r100.c
3068
tmp = RREG32(0x01E4);
sys/dev/pci/drm/radeon/r100.c
3069
seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/r100.c
367
u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
sys/dev/pci/drm/radeon/r100.c
3673
uint32_t tmp = 0;
sys/dev/pci/drm/radeon/r100.c
3693
tmp = RREG32(scratch);
sys/dev/pci/drm/radeon/r100.c
3694
if (tmp == 0xDEADBEEF) {
sys/dev/pci/drm/radeon/r100.c
3703
scratch, tmp);
sys/dev/pci/drm/radeon/r100.c
371
tmp = RREG32(voltage->gpio.reg);
sys/dev/pci/drm/radeon/r100.c
3729
uint32_t tmp = 0;
sys/dev/pci/drm/radeon/r100.c
373
tmp |= voltage->gpio.mask;
sys/dev/pci/drm/radeon/r100.c
375
tmp &= ~(voltage->gpio.mask);
sys/dev/pci/drm/radeon/r100.c
376
WREG32(voltage->gpio.reg, tmp);
sys/dev/pci/drm/radeon/r100.c
3770
tmp = RREG32(scratch);
sys/dev/pci/drm/radeon/r100.c
3771
if (tmp == 0xDEADBEEF) {
sys/dev/pci/drm/radeon/r100.c
3780
scratch, tmp);
sys/dev/pci/drm/radeon/r100.c
380
tmp = RREG32(voltage->gpio.reg);
sys/dev/pci/drm/radeon/r100.c
382
tmp &= ~voltage->gpio.mask;
sys/dev/pci/drm/radeon/r100.c
384
tmp |= voltage->gpio.mask;
sys/dev/pci/drm/radeon/r100.c
385
WREG32(voltage->gpio.reg, tmp);
sys/dev/pci/drm/radeon/r100.c
3850
u32 tmp;
sys/dev/pci/drm/radeon/r100.c
3852
tmp = RREG8(R_0003C2_GENMO_WT);
sys/dev/pci/drm/radeon/r100.c
3853
WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
sys/dev/pci/drm/radeon/r100.c
3888
u32 tmp;
sys/dev/pci/drm/radeon/r100.c
3893
tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
sys/dev/pci/drm/radeon/r100.c
3894
tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
sys/dev/pci/drm/radeon/r100.c
3896
tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
sys/dev/pci/drm/radeon/r100.c
3897
WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
4023
u32 tmp;
sys/dev/pci/drm/radeon/r100.c
4025
tmp = RREG32(RADEON_CP_CSQ_CNTL);
sys/dev/pci/drm/radeon/r100.c
4026
if (tmp) {
sys/dev/pci/drm/radeon/r100.c
4029
tmp = RREG32(RADEON_CP_RB_CNTL);
sys/dev/pci/drm/radeon/r100.c
4030
if (tmp) {
sys/dev/pci/drm/radeon/r100.c
4033
tmp = RREG32(RADEON_SCRATCH_UMSK);
sys/dev/pci/drm/radeon/r100.c
4034
if (tmp) {
sys/dev/pci/drm/radeon/r100.c
465
u32 tmp;
sys/dev/pci/drm/radeon/r100.c
472
tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
sys/dev/pci/drm/radeon/r100.c
473
tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
sys/dev/pci/drm/radeon/r100.c
474
WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
476
tmp = RREG32(RADEON_CRTC_GEN_CNTL);
sys/dev/pci/drm/radeon/r100.c
477
tmp |= RADEON_CRTC_DISP_REQ_EN_B;
sys/dev/pci/drm/radeon/r100.c
478
WREG32(RADEON_CRTC_GEN_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
496
u32 tmp;
sys/dev/pci/drm/radeon/r100.c
503
tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
sys/dev/pci/drm/radeon/r100.c
504
tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
sys/dev/pci/drm/radeon/r100.c
505
WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
507
tmp = RREG32(RADEON_CRTC_GEN_CNTL);
sys/dev/pci/drm/radeon/r100.c
508
tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
sys/dev/pci/drm/radeon/r100.c
509
WREG32(RADEON_CRTC_GEN_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
571
u32 tmp;
sys/dev/pci/drm/radeon/r100.c
576
tmp = RREG32(RADEON_FP_GEN_CNTL);
sys/dev/pci/drm/radeon/r100.c
578
tmp &= ~RADEON_FP_DETECT_INT_POL;
sys/dev/pci/drm/radeon/r100.c
580
tmp |= RADEON_FP_DETECT_INT_POL;
sys/dev/pci/drm/radeon/r100.c
581
WREG32(RADEON_FP_GEN_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
584
tmp = RREG32(RADEON_FP2_GEN_CNTL);
sys/dev/pci/drm/radeon/r100.c
586
tmp &= ~RADEON_FP2_DETECT_INT_POL;
sys/dev/pci/drm/radeon/r100.c
588
tmp |= RADEON_FP2_DETECT_INT_POL;
sys/dev/pci/drm/radeon/r100.c
589
WREG32(RADEON_FP2_GEN_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
673
uint32_t tmp;
sys/dev/pci/drm/radeon/r100.c
676
tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
sys/dev/pci/drm/radeon/r100.c
677
WREG32(RADEON_AIC_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
683
tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
sys/dev/pci/drm/radeon/r100.c
684
WREG32(RADEON_AIC_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
695
uint32_t tmp;
sys/dev/pci/drm/radeon/r100.c
698
tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
sys/dev/pci/drm/radeon/r100.c
699
WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
sys/dev/pci/drm/radeon/r100.c
725
uint32_t tmp = 0;
sys/dev/pci/drm/radeon/r100.c
733
tmp |= RADEON_SW_INT_ENABLE;
sys/dev/pci/drm/radeon/r100.c
737
tmp |= RADEON_CRTC_VBLANK_MASK;
sys/dev/pci/drm/radeon/r100.c
741
tmp |= RADEON_CRTC2_VBLANK_MASK;
sys/dev/pci/drm/radeon/r100.c
744
tmp |= RADEON_FP_DETECT_MASK;
sys/dev/pci/drm/radeon/r100.c
747
tmp |= RADEON_FP2_DETECT_MASK;
sys/dev/pci/drm/radeon/r100.c
749
WREG32(RADEON_GEN_INT_CNTL, tmp);
sys/dev/pci/drm/radeon/r100.c
759
u32 tmp;
sys/dev/pci/drm/radeon/r100.c
764
tmp = RREG32(R_000044_GEN_INT_STATUS);
sys/dev/pci/drm/radeon/r100.c
765
WREG32(R_000044_GEN_INT_STATUS, tmp);
sys/dev/pci/drm/radeon/r100.c
981
u32 tmp;
sys/dev/pci/drm/radeon/r100.c
984
tmp = RREG32(R_000E40_RBBM_STATUS);
sys/dev/pci/drm/radeon/r100.c
985
if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
sys/dev/pci/drm/radeon/r200.c
152
uint32_t tmp;
sys/dev/pci/drm/radeon/r200.c
226
tmp = idx_value & ~(0x7 << 2);
sys/dev/pci/drm/radeon/r200.c
227
tmp |= tile_flags;
sys/dev/pci/drm/radeon/r200.c
228
ib[idx] = tmp + ((u32)reloc->gpu_offset);
sys/dev/pci/drm/radeon/r200.c
298
tmp = idx_value & ~(0x7 << 16);
sys/dev/pci/drm/radeon/r200.c
299
tmp |= tile_flags;
sys/dev/pci/drm/radeon/r200.c
300
ib[idx] = tmp;
sys/dev/pci/drm/radeon/r200.c
421
tmp = (idx_value >> 23) & 0x7;
sys/dev/pci/drm/radeon/r200.c
422
if (tmp == 2 || tmp == 6)
sys/dev/pci/drm/radeon/r200.c
424
tmp = (idx_value >> 27) & 0x7;
sys/dev/pci/drm/radeon/r200.c
425
if (tmp == 2 || tmp == 6)
sys/dev/pci/drm/radeon/r200.c
445
tmp = (idx_value >> 16) & 0x3;
sys/dev/pci/drm/radeon/r200.c
447
switch (tmp) {
sys/dev/pci/drm/radeon/r200.c
531
tmp = idx_value;
sys/dev/pci/drm/radeon/r200.c
534
track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
sys/dev/pci/drm/radeon/r200.c
535
track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
sys/dev/pci/drm/radeon/r300.c
1001
tmp = idx_value & 0x7;
sys/dev/pci/drm/radeon/r300.c
1002
if (tmp == 2 || tmp == 4 || tmp == 6) {
sys/dev/pci/drm/radeon/r300.c
1005
tmp = (idx_value >> 3) & 0x7;
sys/dev/pci/drm/radeon/r300.c
1006
if (tmp == 2 || tmp == 4 || tmp == 6) {
sys/dev/pci/drm/radeon/r300.c
1029
tmp = idx_value & 0x3FFF;
sys/dev/pci/drm/radeon/r300.c
1030
track->textures[i].pitch = tmp + 1;
sys/dev/pci/drm/radeon/r300.c
1032
tmp = ((idx_value >> 15) & 1) << 11;
sys/dev/pci/drm/radeon/r300.c
1033
track->textures[i].width_11 = tmp;
sys/dev/pci/drm/radeon/r300.c
1034
tmp = ((idx_value >> 16) & 1) << 11;
sys/dev/pci/drm/radeon/r300.c
1035
track->textures[i].height_11 = tmp;
sys/dev/pci/drm/radeon/r300.c
1067
tmp = idx_value & 0x7FF;
sys/dev/pci/drm/radeon/r300.c
1068
track->textures[i].width = tmp + 1;
sys/dev/pci/drm/radeon/r300.c
1069
tmp = (idx_value >> 11) & 0x7FF;
sys/dev/pci/drm/radeon/r300.c
1070
track->textures[i].height = tmp + 1;
sys/dev/pci/drm/radeon/r300.c
1071
tmp = (idx_value >> 26) & 0xF;
sys/dev/pci/drm/radeon/r300.c
1072
track->textures[i].num_levels = tmp;
sys/dev/pci/drm/radeon/r300.c
1073
tmp = idx_value & (1 << 31);
sys/dev/pci/drm/radeon/r300.c
1074
track->textures[i].use_pitch = !!tmp;
sys/dev/pci/drm/radeon/r300.c
1075
tmp = (idx_value >> 22) & 0xF;
sys/dev/pci/drm/radeon/r300.c
1076
track->textures[i].txdepth = tmp;
sys/dev/pci/drm/radeon/r300.c
1359
u32 tmp;
sys/dev/pci/drm/radeon/r300.c
1364
tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
sys/dev/pci/drm/radeon/r300.c
1365
tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
sys/dev/pci/drm/radeon/r300.c
1367
tmp |= S_00000D_FORCE_VAP(1);
sys/dev/pci/drm/radeon/r300.c
1368
WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
sys/dev/pci/drm/radeon/r300.c
154
uint32_t tmp;
sys/dev/pci/drm/radeon/r300.c
165
tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
sys/dev/pci/drm/radeon/r300.c
166
WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
sys/dev/pci/drm/radeon/r300.c
168
tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
sys/dev/pci/drm/radeon/r300.c
169
WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
sys/dev/pci/drm/radeon/r300.c
179
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
sys/dev/pci/drm/radeon/r300.c
180
tmp |= RADEON_PCIE_TX_GART_EN;
sys/dev/pci/drm/radeon/r300.c
181
tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
sys/dev/pci/drm/radeon/r300.c
182
WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
sys/dev/pci/drm/radeon/r300.c
193
u32 tmp;
sys/dev/pci/drm/radeon/r300.c
199
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
sys/dev/pci/drm/radeon/r300.c
200
tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
sys/dev/pci/drm/radeon/r300.c
201
WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
sys/dev/pci/drm/radeon/r300.c
349
uint32_t tmp;
sys/dev/pci/drm/radeon/r300.c
353
tmp = RREG32(RADEON_MC_STATUS);
sys/dev/pci/drm/radeon/r300.c
354
if (tmp & R300_MC_IDLE) {
sys/dev/pci/drm/radeon/r300.c
365
uint32_t gb_tile_config, tmp;
sys/dev/pci/drm/radeon/r300.c
398
tmp = RREG32(R300_DST_PIPE_CONFIG);
sys/dev/pci/drm/radeon/r300.c
399
WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
sys/dev/pci/drm/radeon/r300.c
418
u32 status, tmp;
sys/dev/pci/drm/radeon/r300.c
430
tmp = RREG32(RADEON_CP_RB_CNTL);
sys/dev/pci/drm/radeon/r300.c
431
WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
sys/dev/pci/drm/radeon/r300.c
434
WREG32(RADEON_CP_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/r300.c
478
u32 tmp;
sys/dev/pci/drm/radeon/r300.c
482
tmp = RREG32(RADEON_MEM_CNTL);
sys/dev/pci/drm/radeon/r300.c
483
tmp &= R300_MEM_NUM_CHANNELS_MASK;
sys/dev/pci/drm/radeon/r300.c
484
switch (tmp) {
sys/dev/pci/drm/radeon/r300.c
595
uint32_t tmp;
sys/dev/pci/drm/radeon/r300.c
597
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
sys/dev/pci/drm/radeon/r300.c
598
seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/r300.c
599
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
sys/dev/pci/drm/radeon/r300.c
600
seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/r300.c
601
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
sys/dev/pci/drm/radeon/r300.c
602
seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/r300.c
603
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
sys/dev/pci/drm/radeon/r300.c
604
seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/r300.c
605
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
sys/dev/pci/drm/radeon/r300.c
606
seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/r300.c
607
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
sys/dev/pci/drm/radeon/r300.c
608
seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/r300.c
609
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
sys/dev/pci/drm/radeon/r300.c
610
seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/r300.c
634
uint32_t tmp, tile_flags = 0;
sys/dev/pci/drm/radeon/r300.c
726
tmp = idx_value + ((u32)reloc->gpu_offset);
sys/dev/pci/drm/radeon/r300.c
727
tmp |= tile_flags;
sys/dev/pci/drm/radeon/r300.c
728
ib[idx] = tmp;
sys/dev/pci/drm/radeon/r300.c
795
tmp = idx_value & ~(0x7 << 16);
sys/dev/pci/drm/radeon/r300.c
796
tmp |= tile_flags;
sys/dev/pci/drm/radeon/r300.c
797
ib[idx] = tmp;
sys/dev/pci/drm/radeon/r300.c
880
tmp = idx_value & ~(0x7 << 16);
sys/dev/pci/drm/radeon/r300.c
881
tmp |= tile_flags;
sys/dev/pci/drm/radeon/r300.c
882
ib[idx] = tmp;
sys/dev/pci/drm/radeon/r300.c
89
uint32_t tmp;
sys/dev/pci/drm/radeon/r300.c
915
tmp = (idx_value >> 25) & 0x3;
sys/dev/pci/drm/radeon/r300.c
916
track->textures[i].tex_coord_type = tmp;
sys/dev/pci/drm/radeon/r300.c
94
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
sys/dev/pci/drm/radeon/r300.c
95
WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
sys/dev/pci/drm/radeon/r300.c
97
WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
sys/dev/pci/drm/radeon/r420.c
113
tmp = 0;
sys/dev/pci/drm/radeon/r420.c
120
tmp = (0 << 1);
sys/dev/pci/drm/radeon/r420.c
123
tmp = (3 << 1);
sys/dev/pci/drm/radeon/r420.c
126
tmp = (6 << 1);
sys/dev/pci/drm/radeon/r420.c
129
tmp = (7 << 1);
sys/dev/pci/drm/radeon/r420.c
134
tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
sys/dev/pci/drm/radeon/r420.c
135
WREG32(R300_GB_TILE_CONFIG, tmp);
sys/dev/pci/drm/radeon/r420.c
140
tmp = RREG32(R300_DST_PIPE_CONFIG);
sys/dev/pci/drm/radeon/r420.c
141
WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
sys/dev/pci/drm/radeon/r420.c
153
tmp = RREG32(RV530_GB_PIPE_SELECT2);
sys/dev/pci/drm/radeon/r420.c
154
if ((tmp & 3) == 3)
sys/dev/pci/drm/radeon/r420.c
479
uint32_t tmp;
sys/dev/pci/drm/radeon/r420.c
481
tmp = RREG32(R400_GB_PIPE_SELECT);
sys/dev/pci/drm/radeon/r420.c
482
seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/r420.c
483
tmp = RREG32(R300_GB_TILE_CONFIG);
sys/dev/pci/drm/radeon/r420.c
484
seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/r420.c
485
tmp = RREG32(R300_DST_PIPE_CONFIG);
sys/dev/pci/drm/radeon/r420.c
486
seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/r420.c
92
unsigned tmp;
sys/dev/pci/drm/radeon/r520.c
100
switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
sys/dev/pci/drm/radeon/r520.c
117
if (tmp & R520_MC_CHANNEL_SIZE)
sys/dev/pci/drm/radeon/r520.c
39
uint32_t tmp;
sys/dev/pci/drm/radeon/r520.c
43
tmp = RREG32_MC(R520_MC_STATUS);
sys/dev/pci/drm/radeon/r520.c
44
if (tmp & R520_MC_STATUS_IDLE) {
sys/dev/pci/drm/radeon/r520.c
54
unsigned pipe_select_current, gb_pipe_select, tmp;
sys/dev/pci/drm/radeon/r520.c
83
tmp = RREG32(R300_DST_PIPE_CONFIG);
sys/dev/pci/drm/radeon/r520.c
84
pipe_select_current = (tmp >> 2) & 3;
sys/dev/pci/drm/radeon/r520.c
85
tmp = (1 << pipe_select_current) |
sys/dev/pci/drm/radeon/r520.c
87
WREG32_PLL(0x000D, tmp);
sys/dev/pci/drm/radeon/r520.c
95
uint32_t tmp;
sys/dev/pci/drm/radeon/r520.c
99
tmp = RREG32_MC(R520_MC_CNTL0);
sys/dev/pci/drm/radeon/r600.c
1077
u32 tmp;
sys/dev/pci/drm/radeon/r600.c
1099
tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
sys/dev/pci/drm/radeon/r600.c
1100
tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
sys/dev/pci/drm/radeon/r600.c
1101
if (tmp == 2) {
sys/dev/pci/drm/radeon/r600.c
1105
if (tmp) {
sys/dev/pci/drm/radeon/r600.c
1130
u32 tmp;
sys/dev/pci/drm/radeon/r600.c
1148
tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
sys/dev/pci/drm/radeon/r600.c
1152
WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1153
WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1154
WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
sys/dev/pci/drm/radeon/r600.c
1155
WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1156
WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1157
WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1158
WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1159
WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1160
WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1161
WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1162
WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1163
WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1164
WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1165
WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1166
WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
sys/dev/pci/drm/radeon/r600.c
1167
WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
sys/dev/pci/drm/radeon/r600.c
1188
u32 tmp;
sys/dev/pci/drm/radeon/r600.c
1200
tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
sys/dev/pci/drm/radeon/r600.c
1202
WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1203
WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1204
WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1205
WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1206
WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1207
WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1208
WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1209
WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1210
WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1211
WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1212
WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1213
WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1214
WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1215
WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1216
WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1217
WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1230
u32 tmp;
sys/dev/pci/drm/radeon/r600.c
1240
tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
sys/dev/pci/drm/radeon/r600.c
1244
WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1245
WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1246
WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
sys/dev/pci/drm/radeon/r600.c
1247
WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1248
WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1249
WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1250
WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1251
WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1252
WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1253
WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1254
WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1255
WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1256
WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
sys/dev/pci/drm/radeon/r600.c
1257
WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
sys/dev/pci/drm/radeon/r600.c
1265
u32 tmp;
sys/dev/pci/drm/radeon/r600.c
1269
tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
sys/dev/pci/drm/radeon/r600.c
1270
if (!tmp)
sys/dev/pci/drm/radeon/r600.c
1305
u32 tmp;
sys/dev/pci/drm/radeon/r600.c
1344
tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
sys/dev/pci/drm/radeon/r600.c
1345
tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
sys/dev/pci/drm/radeon/r600.c
1346
WREG32(MC_VM_FB_LOCATION, tmp);
sys/dev/pci/drm/radeon/r600.c
1435
u32 tmp;
sys/dev/pci/drm/radeon/r600.c
1442
tmp = RREG32(RAMCFG);
sys/dev/pci/drm/radeon/r600.c
1443
if (tmp & CHANSIZE_OVERRIDE) {
sys/dev/pci/drm/radeon/r600.c
1445
} else if (tmp & CHANSIZE_MASK) {
sys/dev/pci/drm/radeon/r600.c
1450
tmp = RREG32(CHMAP);
sys/dev/pci/drm/radeon/r600.c
1451
switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
sys/dev/pci/drm/radeon/r600.c
1556
u32 tmp = RREG32(R600_BIOS_3_SCRATCH);
sys/dev/pci/drm/radeon/r600.c
1559
tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
sys/dev/pci/drm/radeon/r600.c
1561
tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
sys/dev/pci/drm/radeon/r600.c
1563
WREG32(R600_BIOS_3_SCRATCH, tmp);
sys/dev/pci/drm/radeon/r600.c
1590
u32 i, j, tmp;
sys/dev/pci/drm/radeon/r600.c
1602
tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/pci/drm/radeon/r600.c
1603
if (tmp != crtc_status[i])
sys/dev/pci/drm/radeon/r600.c
1618
u32 tmp;
sys/dev/pci/drm/radeon/r600.c
1621
tmp = RREG32(R_008010_GRBM_STATUS);
sys/dev/pci/drm/radeon/r600.c
1623
if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
sys/dev/pci/drm/radeon/r600.c
1624
G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
sys/dev/pci/drm/radeon/r600.c
1625
G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
sys/dev/pci/drm/radeon/r600.c
1626
G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
sys/dev/pci/drm/radeon/r600.c
1627
G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
sys/dev/pci/drm/radeon/r600.c
1630
if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
sys/dev/pci/drm/radeon/r600.c
1631
G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
sys/dev/pci/drm/radeon/r600.c
1632
G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
sys/dev/pci/drm/radeon/r600.c
1633
G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
sys/dev/pci/drm/radeon/r600.c
1634
G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
sys/dev/pci/drm/radeon/r600.c
1638
if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) |
sys/dev/pci/drm/radeon/r600.c
1639
G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp))
sys/dev/pci/drm/radeon/r600.c
1642
if (G_008010_GRBM_EE_BUSY(tmp))
sys/dev/pci/drm/radeon/r600.c
1646
tmp = RREG32(DMA_STATUS_REG);
sys/dev/pci/drm/radeon/r600.c
1647
if (!(tmp & DMA_IDLE))
sys/dev/pci/drm/radeon/r600.c
1651
tmp = RREG32(R_000E50_SRBM_STATUS);
sys/dev/pci/drm/radeon/r600.c
1652
if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp))
sys/dev/pci/drm/radeon/r600.c
1655
if (G_000E50_IH_BUSY(tmp))
sys/dev/pci/drm/radeon/r600.c
1658
if (G_000E50_SEM_BUSY(tmp))
sys/dev/pci/drm/radeon/r600.c
1661
if (G_000E50_GRBM_RQ_PENDING(tmp))
sys/dev/pci/drm/radeon/r600.c
1664
if (G_000E50_VMC_BUSY(tmp))
sys/dev/pci/drm/radeon/r600.c
1667
if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) |
sys/dev/pci/drm/radeon/r600.c
1668
G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) |
sys/dev/pci/drm/radeon/r600.c
1669
G_000E50_MCDW_BUSY(tmp))
sys/dev/pci/drm/radeon/r600.c
1688
u32 tmp;
sys/dev/pci/drm/radeon/r600.c
1708
tmp = RREG32(DMA_RB_CNTL);
sys/dev/pci/drm/radeon/r600.c
1709
tmp &= ~DMA_RB_ENABLE;
sys/dev/pci/drm/radeon/r600.c
1710
WREG32(DMA_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1784
tmp = RREG32(R_008020_GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/r600.c
1785
tmp |= grbm_soft_reset;
sys/dev/pci/drm/radeon/r600.c
1786
dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/radeon/r600.c
1787
WREG32(R_008020_GRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/r600.c
1788
tmp = RREG32(R_008020_GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/r600.c
1792
tmp &= ~grbm_soft_reset;
sys/dev/pci/drm/radeon/r600.c
1793
WREG32(R_008020_GRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/r600.c
1794
tmp = RREG32(R_008020_GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/r600.c
1798
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/r600.c
1799
tmp |= srbm_soft_reset;
sys/dev/pci/drm/radeon/r600.c
1800
dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/radeon/r600.c
1801
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/r600.c
1802
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/r600.c
1806
tmp &= ~srbm_soft_reset;
sys/dev/pci/drm/radeon/r600.c
1807
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/r600.c
1808
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/r600.c
1823
u32 tmp, i;
sys/dev/pci/drm/radeon/r600.c
1839
tmp = RREG32(DMA_RB_CNTL);
sys/dev/pci/drm/radeon/r600.c
1840
tmp &= ~DMA_RB_ENABLE;
sys/dev/pci/drm/radeon/r600.c
1841
WREG32(DMA_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1857
tmp = RREG32(BUS_CNTL);
sys/dev/pci/drm/radeon/r600.c
1858
tmp |= VGA_COHE_SPEC_TIMER_DIS;
sys/dev/pci/drm/radeon/r600.c
1859
WREG32(BUS_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
1861
tmp = RREG32(BIF_SCRATCH0);
sys/dev/pci/drm/radeon/r600.c
1868
tmp = SOFT_RESET_BIF;
sys/dev/pci/drm/radeon/r600.c
1869
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/r600.c
1941
u32 pipe_rb_ratio, pipe_rb_remain, tmp;
sys/dev/pci/drm/radeon/r600.c
1946
tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
sys/dev/pci/drm/radeon/r600.c
1948
if ((tmp & 0xff) != 0xff)
sys/dev/pci/drm/radeon/r600.c
1949
disabled_rb_mask = tmp;
sys/dev/pci/drm/radeon/r600.c
1994
u32 tmp;
sys/dev/pci/drm/radeon/r600.c
2109
tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
sys/dev/pci/drm/radeon/r600.c
2110
if (tmp > 3) {
sys/dev/pci/drm/radeon/r600.c
2114
tiling_config |= ROW_TILING(tmp);
sys/dev/pci/drm/radeon/r600.c
2115
tiling_config |= SAMPLE_SPLIT(tmp);
sys/dev/pci/drm/radeon/r600.c
2120
tmp = rdev->config.r600.max_simds -
sys/dev/pci/drm/radeon/r600.c
2122
rdev->config.r600.active_simds = tmp;
sys/dev/pci/drm/radeon/r600.c
2125
tmp = 0;
sys/dev/pci/drm/radeon/r600.c
2127
tmp |= (1 << i);
sys/dev/pci/drm/radeon/r600.c
2129
if ((disabled_rb_mask & tmp) == tmp) {
sys/dev/pci/drm/radeon/r600.c
2133
tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
sys/dev/pci/drm/radeon/r600.c
2134
tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
sys/dev/pci/drm/radeon/r600.c
2136
tiling_config |= tmp << 16;
sys/dev/pci/drm/radeon/r600.c
2137
rdev->config.r600.backend_map = tmp;
sys/dev/pci/drm/radeon/r600.c
2145
tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
sys/dev/pci/drm/radeon/r600.c
2146
WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
sys/dev/pci/drm/radeon/r600.c
2147
WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
sys/dev/pci/drm/radeon/r600.c
2159
tmp = RREG32(SX_DEBUG_1);
sys/dev/pci/drm/radeon/r600.c
2160
tmp |= SMX_EVENT_RELEASE;
sys/dev/pci/drm/radeon/r600.c
2162
tmp |= ENABLE_NEW_SMX_ADDRESS;
sys/dev/pci/drm/radeon/r600.c
2163
WREG32(SX_DEBUG_1, tmp);
sys/dev/pci/drm/radeon/r600.c
2184
tmp = RREG32(SQ_MS_FIFO_SIZES);
sys/dev/pci/drm/radeon/r600.c
2189
tmp = (CACHE_FIFO_SIZE(0xa) |
sys/dev/pci/drm/radeon/r600.c
2195
tmp &= ~DONE_FIFO_HIWATER(0xff);
sys/dev/pci/drm/radeon/r600.c
2196
tmp |= DONE_FIFO_HIWATER(0x4);
sys/dev/pci/drm/radeon/r600.c
2198
WREG32(SQ_MS_FIFO_SIZES, tmp);
sys/dev/pci/drm/radeon/r600.c
2313
tmp = rdev->config.r600.max_pipes * 16;
sys/dev/pci/drm/radeon/r600.c
2319
tmp += 32;
sys/dev/pci/drm/radeon/r600.c
2322
tmp += 128;
sys/dev/pci/drm/radeon/r600.c
2327
if (tmp > 256) {
sys/dev/pci/drm/radeon/r600.c
2328
tmp = 256;
sys/dev/pci/drm/radeon/r600.c
2331
WREG32(VGT_GS_PER_ES, tmp);
sys/dev/pci/drm/radeon/r600.c
2362
tmp = TC_L2_SIZE(8);
sys/dev/pci/drm/radeon/r600.c
2366
tmp = TC_L2_SIZE(4);
sys/dev/pci/drm/radeon/r600.c
2369
tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
sys/dev/pci/drm/radeon/r600.c
2372
tmp = TC_L2_SIZE(0);
sys/dev/pci/drm/radeon/r600.c
2375
WREG32(TC_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
2377
tmp = RREG32(HDP_HOST_PATH_CNTL);
sys/dev/pci/drm/radeon/r600.c
2378
WREG32(HDP_HOST_PATH_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
2380
tmp = RREG32(ARB_POP);
sys/dev/pci/drm/radeon/r600.c
2381
tmp |= ENABLE_TC128;
sys/dev/pci/drm/radeon/r600.c
2382
WREG32(ARB_POP, tmp);
sys/dev/pci/drm/radeon/r600.c
2719
u32 tmp;
sys/dev/pci/drm/radeon/r600.c
2731
tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
sys/dev/pci/drm/radeon/r600.c
2733
tmp |= BUF_SWAP_32BIT;
sys/dev/pci/drm/radeon/r600.c
2735
WREG32(CP_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
2742
WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
sys/dev/pci/drm/radeon/r600.c
2756
tmp |= RB_NO_UPDATE;
sys/dev/pci/drm/radeon/r600.c
2761
WREG32(CP_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
2826
uint32_t tmp = 0;
sys/dev/pci/drm/radeon/r600.c
2847
tmp = RREG32(scratch);
sys/dev/pci/drm/radeon/r600.c
2848
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/radeon/r600.c
2856
ring->idx, scratch, tmp);
sys/dev/pci/drm/radeon/r600.c
2973
u32 size_in_bytes, cur_size_in_bytes, tmp;
sys/dev/pci/drm/radeon/r600.c
2999
tmp = upper_32_bits(src_offset) & 0xff;
sys/dev/pci/drm/radeon/r600.c
3001
tmp |= PACKET3_CP_DMA_CP_SYNC;
sys/dev/pci/drm/radeon/r600.c
3004
radeon_ring_write(ring, tmp);
sys/dev/pci/drm/radeon/r600.c
304
u32 tmp = 0;
sys/dev/pci/drm/radeon/r600.c
329
tmp |= FMT_SPATIAL_DITHER_EN;
sys/dev/pci/drm/radeon/r600.c
331
tmp |= FMT_TRUNCATE_EN;
sys/dev/pci/drm/radeon/r600.c
336
tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH);
sys/dev/pci/drm/radeon/r600.c
338
tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH);
sys/dev/pci/drm/radeon/r600.c
3400
uint32_t tmp = 0;
sys/dev/pci/drm/radeon/r600.c
3436
tmp = RREG32(scratch);
sys/dev/pci/drm/radeon/r600.c
3437
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/radeon/r600.c
3445
scratch, tmp);
sys/dev/pci/drm/radeon/r600.c
346
WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/r600.c
3620
u32 tmp;
sys/dev/pci/drm/radeon/r600.c
3623
tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
sys/dev/pci/drm/radeon/r600.c
3624
WREG32(DMA_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
3632
tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
3633
WREG32(DC_HPD1_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3634
tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
3635
WREG32(DC_HPD2_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3636
tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
3637
WREG32(DC_HPD3_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3638
tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
3639
WREG32(DC_HPD4_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3641
tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
3642
WREG32(DC_HPD5_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3643
tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
3644
WREG32(DC_HPD6_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3645
tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/pci/drm/radeon/r600.c
3646
WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
sys/dev/pci/drm/radeon/r600.c
3647
tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/pci/drm/radeon/r600.c
3648
WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
sys/dev/pci/drm/radeon/r600.c
3650
tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/pci/drm/radeon/r600.c
3651
WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3652
tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/pci/drm/radeon/r600.c
3653
WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3658
tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
3659
WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3660
tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
3661
WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3662
tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
3663
WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3664
tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/pci/drm/radeon/r600.c
3665
WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3666
tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/pci/drm/radeon/r600.c
3667
WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3914
u32 tmp;
sys/dev/pci/drm/radeon/r600.c
3951
tmp = RREG32(DC_HPD1_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
3952
tmp |= DC_HPDx_INT_ACK;
sys/dev/pci/drm/radeon/r600.c
3953
WREG32(DC_HPD1_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3955
tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
3956
tmp |= DC_HPDx_INT_ACK;
sys/dev/pci/drm/radeon/r600.c
3957
WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3962
tmp = RREG32(DC_HPD2_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
3963
tmp |= DC_HPDx_INT_ACK;
sys/dev/pci/drm/radeon/r600.c
3964
WREG32(DC_HPD2_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3966
tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
3967
tmp |= DC_HPDx_INT_ACK;
sys/dev/pci/drm/radeon/r600.c
3968
WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3973
tmp = RREG32(DC_HPD3_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
3974
tmp |= DC_HPDx_INT_ACK;
sys/dev/pci/drm/radeon/r600.c
3975
WREG32(DC_HPD3_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3977
tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
3978
tmp |= DC_HPDx_INT_ACK;
sys/dev/pci/drm/radeon/r600.c
3979
WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3983
tmp = RREG32(DC_HPD4_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
3984
tmp |= DC_HPDx_INT_ACK;
sys/dev/pci/drm/radeon/r600.c
3985
WREG32(DC_HPD4_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3989
tmp = RREG32(DC_HPD5_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
3990
tmp |= DC_HPDx_INT_ACK;
sys/dev/pci/drm/radeon/r600.c
3991
WREG32(DC_HPD5_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3994
tmp = RREG32(DC_HPD6_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
3995
tmp |= DC_HPDx_INT_ACK;
sys/dev/pci/drm/radeon/r600.c
3996
WREG32(DC_HPD6_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
3999
tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
sys/dev/pci/drm/radeon/r600.c
4000
tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
sys/dev/pci/drm/radeon/r600.c
4001
WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
sys/dev/pci/drm/radeon/r600.c
4004
tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
sys/dev/pci/drm/radeon/r600.c
4005
tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
sys/dev/pci/drm/radeon/r600.c
4006
WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
sys/dev/pci/drm/radeon/r600.c
4010
tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
sys/dev/pci/drm/radeon/r600.c
4011
tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
sys/dev/pci/drm/radeon/r600.c
4012
WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
4016
tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
sys/dev/pci/drm/radeon/r600.c
4017
tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
sys/dev/pci/drm/radeon/r600.c
4018
WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
4020
tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
sys/dev/pci/drm/radeon/r600.c
4021
tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
sys/dev/pci/drm/radeon/r600.c
4022
WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
4039
u32 wptr, tmp;
sys/dev/pci/drm/radeon/r600.c
4055
tmp = RREG32(IH_RB_CNTL);
sys/dev/pci/drm/radeon/r600.c
4056
tmp |= IH_WPTR_OVERFLOW_CLEAR;
sys/dev/pci/drm/radeon/r600.c
4057
WREG32(IH_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/r600.c
4489
u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
sys/dev/pci/drm/radeon/r600.c
4567
tmp = RREG32(0x541c);
sys/dev/pci/drm/radeon/r600.c
4568
WREG32(0x541c, tmp | 0x8);
sys/dev/pci/drm/radeon/r600.c
862
u32 tmp;
sys/dev/pci/drm/radeon/r600.c
868
tmp = RREG32(DC_HPD1_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
870
tmp &= ~DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
872
tmp |= DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
873
WREG32(DC_HPD1_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
876
tmp = RREG32(DC_HPD2_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
878
tmp &= ~DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
880
tmp |= DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
881
WREG32(DC_HPD2_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
884
tmp = RREG32(DC_HPD3_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
886
tmp &= ~DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
888
tmp |= DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
889
WREG32(DC_HPD3_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
892
tmp = RREG32(DC_HPD4_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
894
tmp &= ~DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
896
tmp |= DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
897
WREG32(DC_HPD4_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
900
tmp = RREG32(DC_HPD5_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
902
tmp &= ~DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
904
tmp |= DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
905
WREG32(DC_HPD5_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
909
tmp = RREG32(DC_HPD6_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
911
tmp &= ~DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
913
tmp |= DC_HPDx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
914
WREG32(DC_HPD6_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
922
tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
924
tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
926
tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
927
WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
930
tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
932
tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
934
tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
935
WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
938
tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
sys/dev/pci/drm/radeon/r600.c
940
tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
942
tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
sys/dev/pci/drm/radeon/r600.c
943
WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
969
u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
sys/dev/pci/drm/radeon/r600.c
971
tmp |= DC_HPDx_EN;
sys/dev/pci/drm/radeon/r600.c
975
WREG32(DC_HPD1_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
978
WREG32(DC_HPD2_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
981
WREG32(DC_HPD3_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
984
WREG32(DC_HPD4_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
988
WREG32(DC_HPD5_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600.c
991
WREG32(DC_HPD6_CONTROL, tmp);
sys/dev/pci/drm/radeon/r600_cs.c
1085
tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
sys/dev/pci/drm/radeon/r600_cs.c
1086
track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
sys/dev/pci/drm/radeon/r600_cs.c
1088
track->vgt_strmout_bo[tmp] = reloc->robj;
sys/dev/pci/drm/radeon/r600_cs.c
1089
track->vgt_strmout_bo_mc[tmp] = reloc->gpu_offset;
sys/dev/pci/drm/radeon/r600_cs.c
1096
tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
sys/dev/pci/drm/radeon/r600_cs.c
1098
track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
sys/dev/pci/drm/radeon/r600_cs.c
1118
tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
sys/dev/pci/drm/radeon/r600_cs.c
1119
track->log_nsamples = tmp;
sys/dev/pci/drm/radeon/r600_cs.c
1120
track->nsamples = 1 << tmp;
sys/dev/pci/drm/radeon/r600_cs.c
1124
tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx));
sys/dev/pci/drm/radeon/r600_cs.c
1125
track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX;
sys/dev/pci/drm/radeon/r600_cs.c
1143
tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
sys/dev/pci/drm/radeon/r600_cs.c
1144
track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
sys/dev/pci/drm/radeon/r600_cs.c
1147
track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
sys/dev/pci/drm/radeon/r600_cs.c
1150
track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
sys/dev/pci/drm/radeon/r600_cs.c
1153
tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
sys/dev/pci/drm/radeon/r600_cs.c
1154
track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
sys/dev/pci/drm/radeon/r600_cs.c
1166
tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4;
sys/dev/pci/drm/radeon/r600_cs.c
1167
track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
sys/dev/pci/drm/radeon/r600_cs.c
1178
tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
sys/dev/pci/drm/radeon/r600_cs.c
1179
track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
sys/dev/pci/drm/radeon/r600_cs.c
1180
track->cb_color_size_idx[tmp] = idx;
sys/dev/pci/drm/radeon/r600_cs.c
1200
tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
sys/dev/pci/drm/radeon/r600_cs.c
1202
if (!track->cb_color_base_last[tmp]) {
sys/dev/pci/drm/radeon/r600_cs.c
1206
track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
sys/dev/pci/drm/radeon/r600_cs.c
1207
track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp];
sys/dev/pci/drm/radeon/r600_cs.c
1208
ib[idx] = track->cb_color_base_last[tmp];
sys/dev/pci/drm/radeon/r600_cs.c
1215
track->cb_color_frag_bo[tmp] = reloc->robj;
sys/dev/pci/drm/radeon/r600_cs.c
1216
track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8;
sys/dev/pci/drm/radeon/r600_cs.c
1219
if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
sys/dev/pci/drm/radeon/r600_cs.c
1231
tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
sys/dev/pci/drm/radeon/r600_cs.c
1233
if (!track->cb_color_base_last[tmp]) {
sys/dev/pci/drm/radeon/r600_cs.c
1237
track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
sys/dev/pci/drm/radeon/r600_cs.c
1238
track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp];
sys/dev/pci/drm/radeon/r600_cs.c
1239
ib[idx] = track->cb_color_base_last[tmp];
sys/dev/pci/drm/radeon/r600_cs.c
1246
track->cb_color_tile_bo[tmp] = reloc->robj;
sys/dev/pci/drm/radeon/r600_cs.c
1247
track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8;
sys/dev/pci/drm/radeon/r600_cs.c
1250
if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
sys/dev/pci/drm/radeon/r600_cs.c
1262
tmp = (reg - R_028100_CB_COLOR0_MASK) / 4;
sys/dev/pci/drm/radeon/r600_cs.c
1263
track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx);
sys/dev/pci/drm/radeon/r600_cs.c
1264
if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
sys/dev/pci/drm/radeon/r600_cs.c
1282
tmp = (reg - CB_COLOR0_BASE) / 4;
sys/dev/pci/drm/radeon/r600_cs.c
1283
track->cb_color_bo_offset[tmp] = (u64)radeon_get_ib_value(p, idx) << 8;
sys/dev/pci/drm/radeon/r600_cs.c
1285
track->cb_color_base_last[tmp] = ib[idx];
sys/dev/pci/drm/radeon/r600_cs.c
1286
track->cb_color_bo[tmp] = reloc->robj;
sys/dev/pci/drm/radeon/r600_cs.c
1287
track->cb_color_bo_mc[tmp] = reloc->gpu_offset;
sys/dev/pci/drm/radeon/r600_cs.c
1652
int tmp;
sys/dev/pci/drm/radeon/r600_cs.c
1660
tmp = radeon_get_ib_value(p, idx + 1);
sys/dev/pci/drm/radeon/r600_cs.c
1661
pred_op = (tmp >> 16) & 0x7;
sys/dev/pci/drm/radeon/r600_cs.c
1680
((u64)(tmp & 0xff) << 32);
sys/dev/pci/drm/radeon/r600_cs.c
1683
ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
sys/dev/pci/drm/radeon/r600_cs.c
1785
u64 offset, tmp;
sys/dev/pci/drm/radeon/r600_cs.c
1808
tmp = radeon_get_ib_value(p, idx) +
sys/dev/pci/drm/radeon/r600_cs.c
1811
offset = reloc->gpu_offset + tmp;
sys/dev/pci/drm/radeon/r600_cs.c
1813
if ((tmp + size) > radeon_bo_size(reloc->robj)) {
sys/dev/pci/drm/radeon/r600_cs.c
1815
tmp + size, radeon_bo_size(reloc->robj));
sys/dev/pci/drm/radeon/r600_cs.c
1838
tmp = radeon_get_ib_value(p, idx+2) +
sys/dev/pci/drm/radeon/r600_cs.c
1841
offset = reloc->gpu_offset + tmp;
sys/dev/pci/drm/radeon/r600_cs.c
1843
if ((tmp + size) > radeon_bo_size(reloc->robj)) {
sys/dev/pci/drm/radeon/r600_cs.c
1845
tmp + size, radeon_bo_size(reloc->robj));
sys/dev/pci/drm/radeon/r600_cs.c
352
u32 slice_tile_max, tmp;
sys/dev/pci/drm/radeon/r600_cs.c
429
tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) *
sys/dev/pci/drm/radeon/r600_cs.c
435
tmp += track->cb_color_view[i] & 0xFF;
sys/dev/pci/drm/radeon/r600_cs.c
439
tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp;
sys/dev/pci/drm/radeon/r600_cs.c
442
if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
sys/dev/pci/drm/radeon/r600_cs.c
454
track->cb_color_bo_offset[i], tmp,
sys/dev/pci/drm/radeon/r600_cs.c
463
tmp = (height * pitch) >> 6;
sys/dev/pci/drm/radeon/r600_cs.c
464
if (tmp < slice_tile_max)
sys/dev/pci/drm/radeon/r600_cs.c
465
slice_tile_max = tmp;
sys/dev/pci/drm/radeon/r600_cs.c
466
tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
sys/dev/pci/drm/radeon/r600_cs.c
468
ib[track->cb_color_size_idx[i]] = tmp;
sys/dev/pci/drm/radeon/r600_cs.c
520
u32 nviews, bpe, ntiles, slice_tile_max, tmp;
sys/dev/pci/drm/radeon/r600_cs.c
559
tmp = radeon_bo_size(track->db_bo) - track->db_offset;
sys/dev/pci/drm/radeon/r600_cs.c
560
tmp = (tmp / bpe) >> 6;
sys/dev/pci/drm/radeon/r600_cs.c
561
if (!tmp) {
sys/dev/pci/drm/radeon/r600_cs.c
567
ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
sys/dev/pci/drm/radeon/r600_cs.c
623
tmp = ntiles * bpe * 64 * nviews * track->nsamples;
sys/dev/pci/drm/radeon/r600_cs.c
624
if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
sys/dev/pci/drm/radeon/r600_cs.c
628
track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
sys/dev/pci/drm/radeon/r600_cs.c
711
u32 tmp;
sys/dev/pci/drm/radeon/r600_cs.c
747
tmp = track->cb_target_mask;
sys/dev/pci/drm/radeon/r600_cs.c
751
tmp |= 0xff;
sys/dev/pci/drm/radeon/r600_cs.c
758
(tmp >> (i * 4)) & 0xF) {
sys/dev/pci/drm/radeon/r600_cs.c
975
u32 m, i, tmp, *ib;
sys/dev/pci/drm/radeon/r600_dma.c
235
u32 tmp;
sys/dev/pci/drm/radeon/r600_dma.c
245
tmp = 0xCAFEDEAD;
sys/dev/pci/drm/radeon/r600_dma.c
246
rdev->wb.wb[index/4] = cpu_to_le32(tmp);
sys/dev/pci/drm/radeon/r600_dma.c
260
tmp = le32_to_cpu(rdev->wb.wb[index/4]);
sys/dev/pci/drm/radeon/r600_dma.c
261
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/radeon/r600_dma.c
270
ring->idx, tmp);
sys/dev/pci/drm/radeon/r600_dma.c
342
u32 tmp = 0;
sys/dev/pci/drm/radeon/r600_dma.c
381
tmp = le32_to_cpu(rdev->wb.wb[index/4]);
sys/dev/pci/drm/radeon/r600_dma.c
382
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/radeon/r600_dma.c
389
DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
sys/dev/pci/drm/radeon/r600_dpm.c
205
u32 tmp;
sys/dev/pci/drm/radeon/r600_dpm.c
208
tmp = i_c >> p_b;
sys/dev/pci/drm/radeon/r600_dpm.c
210
while (tmp) {
sys/dev/pci/drm/radeon/r600_dpm.c
212
tmp >>= 1;
sys/dev/pci/drm/radeon/r600_dpm.c
530
u32 tmp, mask;
sys/dev/pci/drm/radeon/r600_dpm.c
536
tmp = RREG32(VID_UPPER_GPIO_CNTL);
sys/dev/pci/drm/radeon/r600_dpm.c
537
tmp = (tmp & ~mask) | ((pins >> (32 - (3 * ix))) & mask);
sys/dev/pci/drm/radeon/r600_dpm.c
538
WREG32(VID_UPPER_GPIO_CNTL, tmp);
sys/dev/pci/drm/radeon/r600_dpm.c
604
u32 tmp = 0;
sys/dev/pci/drm/radeon/r600_dpm.c
607
tmp = CTXSW_FREQ_DISPLAY_WATERMARK;
sys/dev/pci/drm/radeon/r600_dpm.c
608
WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), tmp, ~CTXSW_FREQ_DISPLAY_WATERMARK);
sys/dev/pci/drm/radeon/r600_dpm.c
615
u32 tmp = 0;
sys/dev/pci/drm/radeon/r600_dpm.c
618
tmp = CTXSW_FREQ_GEN2PCIE_VOLT;
sys/dev/pci/drm/radeon/r600_dpm.c
619
WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), tmp, ~CTXSW_FREQ_GEN2PCIE_VOLT);
sys/dev/pci/drm/radeon/r600_dpm.c
624
u32 tmp;
sys/dev/pci/drm/radeon/r600_dpm.c
626
tmp = RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK;
sys/dev/pci/drm/radeon/r600_dpm.c
627
tmp >>= CURRENT_PROFILE_INDEX_SHIFT;
sys/dev/pci/drm/radeon/r600_dpm.c
628
return tmp;
sys/dev/pci/drm/radeon/r600_dpm.c
633
u32 tmp;
sys/dev/pci/drm/radeon/r600_dpm.c
635
tmp = RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_PROFILE_INDEX_MASK;
sys/dev/pci/drm/radeon/r600_dpm.c
636
tmp >>= TARGET_PROFILE_INDEX_SHIFT;
sys/dev/pci/drm/radeon/r600_dpm.c
637
return tmp;
sys/dev/pci/drm/radeon/r600_hdmi.c
146
u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
sys/dev/pci/drm/radeon/r600_hdmi.c
152
tmp |= AUDIO_ENABLED;
sys/dev/pci/drm/radeon/r600_hdmi.c
154
tmp |= PIN0_AUDIO_ENABLED;
sys/dev/pci/drm/radeon/r600_hdmi.c
156
tmp |= PIN1_AUDIO_ENABLED;
sys/dev/pci/drm/radeon/r600_hdmi.c
158
tmp |= PIN2_AUDIO_ENABLED;
sys/dev/pci/drm/radeon/r600_hdmi.c
160
tmp |= PIN3_AUDIO_ENABLED;
sys/dev/pci/drm/radeon/r600_hdmi.c
162
tmp &= ~(AUDIO_ENABLED |
sys/dev/pci/drm/radeon/r600_hdmi.c
169
WREG32(AZ_HOT_PLUG_CONTROL, tmp);
sys/dev/pci/drm/radeon/radeon_acpi.c
735
struct drm_encoder *tmp;
sys/dev/pci/drm/radeon/radeon_acpi.c
739
list_for_each_entry(tmp, &rdev_to_drm(rdev)->mode_config.encoder_list,
sys/dev/pci/drm/radeon/radeon_acpi.c
741
struct radeon_encoder *enc = to_radeon_encoder(tmp);
sys/dev/pci/drm/radeon/radeon_atombios.c
3069
u32 tmp;
sys/dev/pci/drm/radeon/radeon_atombios.c
3073
tmp = eng_clock & SET_CLOCK_FREQ_MASK;
sys/dev/pci/drm/radeon/radeon_atombios.c
3074
tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
sys/dev/pci/drm/radeon/radeon_atombios.c
3076
args.ulTargetEngineClock = cpu_to_le32(tmp);
sys/dev/pci/drm/radeon/radeon_atombios.c
3099
u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
sys/dev/pci/drm/radeon/radeon_atombios.c
3101
args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */
sys/dev/pci/drm/radeon/radeon_bios.c
817
uint16_t tmp;
sys/dev/pci/drm/radeon/radeon_bios.c
840
tmp = RBIOS16(0x18);
sys/dev/pci/drm/radeon/radeon_bios.c
841
if (RBIOS8(tmp + 0x14) != 0x0) {
sys/dev/pci/drm/radeon/radeon_bios.c
850
tmp = rdev->bios_header_start + 4;
sys/dev/pci/drm/radeon/radeon_bios.c
851
if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
sys/dev/pci/drm/radeon/radeon_bios.c
852
!memcmp(rdev->bios + tmp, "MOTA", 4)) {
sys/dev/pci/drm/radeon/radeon_clocks.c
284
u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV);
sys/dev/pci/drm/radeon/radeon_clocks.c
287
(tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT;
sys/dev/pci/drm/radeon/radeon_clocks.c
289
p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK;
sys/dev/pci/drm/radeon/radeon_clocks.c
477
uint32_t tmp;
sys/dev/pci/drm/radeon/radeon_clocks.c
484
tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
485
tmp &= ~RADEON_DONT_USE_XTALIN;
sys/dev/pci/drm/radeon/radeon_clocks.c
486
WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
488
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
489
tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
sys/dev/pci/drm/radeon/radeon_clocks.c
490
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
494
tmp = RREG32_PLL(RADEON_SPLL_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
495
tmp |= RADEON_SPLL_SLEEP;
sys/dev/pci/drm/radeon/radeon_clocks.c
496
WREG32_PLL(RADEON_SPLL_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
500
tmp = RREG32_PLL(RADEON_SPLL_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
501
tmp |= RADEON_SPLL_RESET;
sys/dev/pci/drm/radeon/radeon_clocks.c
502
WREG32_PLL(RADEON_SPLL_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
506
tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
sys/dev/pci/drm/radeon/radeon_clocks.c
507
tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT);
sys/dev/pci/drm/radeon/radeon_clocks.c
508
tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT;
sys/dev/pci/drm/radeon/radeon_clocks.c
509
WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
512
tmp = RREG32_PLL(RADEON_SPLL_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
513
tmp &= ~RADEON_SPLL_PVG_MASK;
sys/dev/pci/drm/radeon/radeon_clocks.c
515
tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT);
sys/dev/pci/drm/radeon/radeon_clocks.c
517
tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT);
sys/dev/pci/drm/radeon/radeon_clocks.c
518
WREG32_PLL(RADEON_SPLL_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
520
tmp = RREG32_PLL(RADEON_SPLL_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
521
tmp &= ~RADEON_SPLL_SLEEP;
sys/dev/pci/drm/radeon/radeon_clocks.c
522
WREG32_PLL(RADEON_SPLL_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
526
tmp = RREG32_PLL(RADEON_SPLL_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
527
tmp &= ~RADEON_SPLL_RESET;
sys/dev/pci/drm/radeon/radeon_clocks.c
528
WREG32_PLL(RADEON_SPLL_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
532
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
533
tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
sys/dev/pci/drm/radeon/radeon_clocks.c
537
tmp |= 1;
sys/dev/pci/drm/radeon/radeon_clocks.c
540
tmp |= 2;
sys/dev/pci/drm/radeon/radeon_clocks.c
543
tmp |= 3;
sys/dev/pci/drm/radeon/radeon_clocks.c
546
tmp |= 4;
sys/dev/pci/drm/radeon/radeon_clocks.c
549
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
553
tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
554
tmp |= RADEON_DONT_USE_XTALIN;
sys/dev/pci/drm/radeon/radeon_clocks.c
555
WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
562
uint32_t tmp;
sys/dev/pci/drm/radeon/radeon_clocks.c
566
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
570
tmp &=
sys/dev/pci/drm/radeon/radeon_clocks.c
574
tmp &=
sys/dev/pci/drm/radeon/radeon_clocks.c
580
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
584
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
585
tmp &=
sys/dev/pci/drm/radeon/radeon_clocks.c
599
tmp |= RADEON_DYN_STOP_LAT_MASK;
sys/dev/pci/drm/radeon/radeon_clocks.c
600
tmp |=
sys/dev/pci/drm/radeon/radeon_clocks.c
603
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
605
tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
606
tmp &= ~RADEON_SCLK_MORE_FORCEON;
sys/dev/pci/drm/radeon/radeon_clocks.c
607
tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
sys/dev/pci/drm/radeon/radeon_clocks.c
608
WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
610
tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
611
tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
sys/dev/pci/drm/radeon/radeon_clocks.c
613
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
615
tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
616
tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
sys/dev/pci/drm/radeon/radeon_clocks.c
629
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
631
tmp = RREG32_PLL(R300_SCLK_CNTL2);
sys/dev/pci/drm/radeon/radeon_clocks.c
632
tmp &= ~(R300_SCLK_FORCE_TCL |
sys/dev/pci/drm/radeon/radeon_clocks.c
635
tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT |
sys/dev/pci/drm/radeon/radeon_clocks.c
638
WREG32_PLL(R300_SCLK_CNTL2, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
640
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
641
tmp &=
sys/dev/pci/drm/radeon/radeon_clocks.c
655
tmp |= RADEON_DYN_STOP_LAT_MASK;
sys/dev/pci/drm/radeon/radeon_clocks.c
656
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
658
tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
659
tmp &= ~RADEON_SCLK_MORE_FORCEON;
sys/dev/pci/drm/radeon/radeon_clocks.c
660
tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
sys/dev/pci/drm/radeon/radeon_clocks.c
661
WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
663
tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
664
tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
sys/dev/pci/drm/radeon/radeon_clocks.c
666
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
668
tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
669
tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
sys/dev/pci/drm/radeon/radeon_clocks.c
682
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
684
tmp = RREG32_PLL(RADEON_MCLK_MISC);
sys/dev/pci/drm/radeon/radeon_clocks.c
685
tmp |= (RADEON_MC_MCLK_DYN_ENABLE |
sys/dev/pci/drm/radeon/radeon_clocks.c
687
WREG32_PLL(RADEON_MCLK_MISC, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
689
tmp = RREG32_PLL(RADEON_MCLK_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
690
tmp |= (RADEON_FORCEON_MCLKA |
sys/dev/pci/drm/radeon/radeon_clocks.c
693
tmp &= ~(RADEON_FORCEON_YCLKA |
sys/dev/pci/drm/radeon/radeon_clocks.c
701
if ((tmp & R300_DISABLE_MC_MCLKA) &&
sys/dev/pci/drm/radeon/radeon_clocks.c
702
(tmp & R300_DISABLE_MC_MCLKB)) {
sys/dev/pci/drm/radeon/radeon_clocks.c
704
tmp = RREG32_PLL(RADEON_MCLK_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
708
tmp &=
sys/dev/pci/drm/radeon/radeon_clocks.c
711
tmp &=
sys/dev/pci/drm/radeon/radeon_clocks.c
714
tmp &= ~(R300_DISABLE_MC_MCLKA |
sys/dev/pci/drm/radeon/radeon_clocks.c
719
WREG32_PLL(RADEON_MCLK_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
721
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
722
tmp &= ~(R300_SCLK_FORCE_VAP);
sys/dev/pci/drm/radeon/radeon_clocks.c
723
tmp |= RADEON_SCLK_FORCE_CP;
sys/dev/pci/drm/radeon/radeon_clocks.c
724
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
727
tmp = RREG32_PLL(R300_SCLK_CNTL2);
sys/dev/pci/drm/radeon/radeon_clocks.c
728
tmp &= ~(R300_SCLK_FORCE_TCL |
sys/dev/pci/drm/radeon/radeon_clocks.c
731
WREG32_PLL(R300_SCLK_CNTL2, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
734
tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
736
tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK |
sys/dev/pci/drm/radeon/radeon_clocks.c
740
tmp |= (RADEON_ENGIN_DYNCLK_MODE |
sys/dev/pci/drm/radeon/radeon_clocks.c
742
WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
745
tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
746
tmp |= RADEON_SCLK_DYN_START_CNTL;
sys/dev/pci/drm/radeon/radeon_clocks.c
747
WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
753
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
755
tmp &= ~RADEON_SCLK_FORCEON_MASK;
sys/dev/pci/drm/radeon/radeon_clocks.c
767
tmp |= RADEON_SCLK_FORCE_CP;
sys/dev/pci/drm/radeon/radeon_clocks.c
768
tmp |= RADEON_SCLK_FORCE_VIP;
sys/dev/pci/drm/radeon/radeon_clocks.c
771
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
776
tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
777
tmp &= ~RADEON_SCLK_MORE_FORCEON;
sys/dev/pci/drm/radeon/radeon_clocks.c
785
tmp |= RADEON_SCLK_MORE_FORCEON;
sys/dev/pci/drm/radeon/radeon_clocks.c
787
WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
797
tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
798
tmp |= RADEON_TCL_BYPASS_DISABLE;
sys/dev/pci/drm/radeon/radeon_clocks.c
799
WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
804
tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
805
tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
sys/dev/pci/drm/radeon/radeon_clocks.c
813
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
816
tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
817
tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
sys/dev/pci/drm/radeon/radeon_clocks.c
820
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
826
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
827
tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP |
sys/dev/pci/drm/radeon/radeon_clocks.c
834
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
837
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
838
tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
sys/dev/pci/drm/radeon/radeon_clocks.c
846
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
848
tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
849
tmp |= RADEON_SCLK_MORE_FORCEON;
sys/dev/pci/drm/radeon/radeon_clocks.c
850
WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
852
tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
853
tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
sys/dev/pci/drm/radeon/radeon_clocks.c
856
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
858
tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
859
tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
sys/dev/pci/drm/radeon/radeon_clocks.c
873
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
876
tmp = RREG32_PLL(R300_SCLK_CNTL2);
sys/dev/pci/drm/radeon/radeon_clocks.c
877
tmp |= (R300_SCLK_FORCE_TCL |
sys/dev/pci/drm/radeon/radeon_clocks.c
879
WREG32_PLL(R300_SCLK_CNTL2, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
881
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
882
tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
sys/dev/pci/drm/radeon/radeon_clocks.c
890
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
892
tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
893
tmp |= RADEON_SCLK_MORE_FORCEON;
sys/dev/pci/drm/radeon/radeon_clocks.c
894
WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
896
tmp = RREG32_PLL(RADEON_MCLK_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
897
tmp |= (RADEON_FORCEON_MCLKA |
sys/dev/pci/drm/radeon/radeon_clocks.c
901
WREG32_PLL(RADEON_MCLK_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
903
tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
904
tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
sys/dev/pci/drm/radeon/radeon_clocks.c
907
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
909
tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
910
tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
sys/dev/pci/drm/radeon/radeon_clocks.c
924
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
926
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
927
tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2);
sys/dev/pci/drm/radeon/radeon_clocks.c
928
tmp |= RADEON_SCLK_FORCE_SE;
sys/dev/pci/drm/radeon/radeon_clocks.c
931
tmp |= (RADEON_SCLK_FORCE_RB |
sys/dev/pci/drm/radeon/radeon_clocks.c
944
tmp |= (RADEON_SCLK_FORCE_HDP |
sys/dev/pci/drm/radeon/radeon_clocks.c
951
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
957
tmp = RREG32_PLL(R300_SCLK_CNTL2);
sys/dev/pci/drm/radeon/radeon_clocks.c
958
tmp |= (R300_SCLK_FORCE_TCL |
sys/dev/pci/drm/radeon/radeon_clocks.c
961
WREG32_PLL(R300_SCLK_CNTL2, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
966
tmp = RREG32_PLL(RADEON_MCLK_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
967
tmp &= ~(RADEON_FORCEON_MCLKA |
sys/dev/pci/drm/radeon/radeon_clocks.c
969
WREG32_PLL(RADEON_MCLK_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
976
tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
977
tmp |= RADEON_SCLK_MORE_FORCEON;
sys/dev/pci/drm/radeon/radeon_clocks.c
978
WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
982
tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
983
tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
sys/dev/pci/drm/radeon/radeon_clocks.c
991
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_clocks.c
994
tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
sys/dev/pci/drm/radeon/radeon_clocks.c
995
tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
sys/dev/pci/drm/radeon/radeon_clocks.c
997
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_combios.c
1171
int tmp, i;
sys/dev/pci/drm/radeon/radeon_combios.c
1245
tmp = RBIOS16(lcd_info + 64 + i * 2);
sys/dev/pci/drm/radeon/radeon_combios.c
1246
if (tmp == 0)
sys/dev/pci/drm/radeon/radeon_combios.c
1249
if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
sys/dev/pci/drm/radeon/radeon_combios.c
1250
(RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
sys/dev/pci/drm/radeon/radeon_combios.c
1251
u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
sys/dev/pci/drm/radeon/radeon_combios.c
1257
(RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
sys/dev/pci/drm/radeon/radeon_combios.c
1261
(RBIOS8(tmp + 23) * 8);
sys/dev/pci/drm/radeon/radeon_combios.c
1264
(RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
sys/dev/pci/drm/radeon/radeon_combios.c
1266
((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
sys/dev/pci/drm/radeon/radeon_combios.c
1268
((RBIOS16(tmp + 28) & 0xf800) >> 11);
sys/dev/pci/drm/radeon/radeon_combios.c
1270
lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
sys/dev/pci/drm/radeon/radeon_combios.c
2304
uint16_t tmp, connector_object_id;
sys/dev/pci/drm/radeon/radeon_combios.c
2319
tmp = RBIOS16(entry);
sys/dev/pci/drm/radeon/radeon_combios.c
2321
connector = (tmp >> 12) & 0xf;
sys/dev/pci/drm/radeon/radeon_combios.c
2323
ddc_type = (tmp >> 8) & 0xf;
sys/dev/pci/drm/radeon/radeon_combios.c
2333
if ((tmp >> 4) & 0x1)
sys/dev/pci/drm/radeon/radeon_combios.c
2349
if ((tmp >> 4) & 0x1)
sys/dev/pci/drm/radeon/radeon_combios.c
2365
if (tmp & 0x1) {
sys/dev/pci/drm/radeon/radeon_combios.c
2393
if (tmp & 0x1) {
sys/dev/pci/drm/radeon/radeon_combios.c
2416
tmp &= ~(1 << 4);
sys/dev/pci/drm/radeon/radeon_combios.c
2418
if ((tmp >> 4) & 0x1) {
sys/dev/pci/drm/radeon/radeon_combios.c
2447
if ((tmp >> 4) & 0x1) {
sys/dev/pci/drm/radeon/radeon_combios.c
2635
u8 rev, tmp;
sys/dev/pci/drm/radeon/radeon_combios.c
2758
tmp = RBIOS8(offset + 0x5 + 0xd);
sys/dev/pci/drm/radeon/radeon_combios.c
2759
rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
sys/dev/pci/drm/radeon/radeon_combios.c
2766
tmp = RBIOS8(voltage_table_offset + 0x2);
sys/dev/pci/drm/radeon/radeon_combios.c
2767
rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
sys/dev/pci/drm/radeon/radeon_combios.c
3021
uint32_t tmp;
sys/dev/pci/drm/radeon/radeon_combios.c
3040
tmp = RREG32(addr);
sys/dev/pci/drm/radeon/radeon_combios.c
3041
tmp &= and_mask;
sys/dev/pci/drm/radeon/radeon_combios.c
3042
tmp |= or_mask;
sys/dev/pci/drm/radeon/radeon_combios.c
3043
WREG32(addr, tmp);
sys/dev/pci/drm/radeon/radeon_combios.c
3050
tmp = RREG32(addr);
sys/dev/pci/drm/radeon/radeon_combios.c
3051
tmp &= and_mask;
sys/dev/pci/drm/radeon/radeon_combios.c
3052
tmp |= or_mask;
sys/dev/pci/drm/radeon/radeon_combios.c
3053
WREG32(addr, tmp);
sys/dev/pci/drm/radeon/radeon_combios.c
3099
uint32_t val, shift, tmp;
sys/dev/pci/drm/radeon/radeon_combios.c
3117
tmp = RREG32_PLL(addr);
sys/dev/pci/drm/radeon/radeon_combios.c
3118
tmp &= and_mask;
sys/dev/pci/drm/radeon/radeon_combios.c
3119
tmp |= or_mask;
sys/dev/pci/drm/radeon/radeon_combios.c
3120
WREG32_PLL(addr, tmp);
sys/dev/pci/drm/radeon/radeon_combios.c
3124
tmp = 1000;
sys/dev/pci/drm/radeon/radeon_combios.c
3133
while (tmp--) {
sys/dev/pci/drm/radeon/radeon_combios.c
3142
while (tmp--) {
sys/dev/pci/drm/radeon/radeon_combios.c
3150
tmp =
sys/dev/pci/drm/radeon/radeon_combios.c
3152
if (tmp & RADEON_CG_NO1_DEBUG_0) {
sys/dev/pci/drm/radeon/radeon_combios.c
3165
tmp &
sys/dev/pci/drm/radeon/radeon_combios.c
3185
uint32_t tmp;
sys/dev/pci/drm/radeon/radeon_combios.c
3201
tmp = 20000;
sys/dev/pci/drm/radeon/radeon_combios.c
3202
while (tmp--) {
sys/dev/pci/drm/radeon/radeon_combios.c
3212
tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
sys/dev/pci/drm/radeon/radeon_combios.c
3213
tmp &= RADEON_SDRAM_MODE_MASK;
sys/dev/pci/drm/radeon/radeon_combios.c
3214
tmp |= or_mask;
sys/dev/pci/drm/radeon/radeon_combios.c
3215
WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
sys/dev/pci/drm/radeon/radeon_combios.c
3218
tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
sys/dev/pci/drm/radeon/radeon_combios.c
3219
tmp &= RADEON_B3MEM_RESET_MASK;
sys/dev/pci/drm/radeon/radeon_combios.c
3220
tmp |= or_mask;
sys/dev/pci/drm/radeon/radeon_combios.c
3221
WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
sys/dev/pci/drm/radeon/radeon_device.c
206
u32 tmp, reg, and_mask, or_mask;
sys/dev/pci/drm/radeon/radeon_device.c
218
tmp = or_mask;
sys/dev/pci/drm/radeon/radeon_device.c
220
tmp = RREG32(reg);
sys/dev/pci/drm/radeon/radeon_device.c
221
tmp &= ~and_mask;
sys/dev/pci/drm/radeon/radeon_device.c
222
tmp |= or_mask;
sys/dev/pci/drm/radeon/radeon_device.c
224
WREG32(reg, tmp);
sys/dev/pci/drm/radeon/radeon_display.c
1072
unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
sys/dev/pci/drm/radeon/radeon_display.c
1073
fb_div *= tmp;
sys/dev/pci/drm/radeon/radeon_display.c
1074
ref_div *= tmp;
sys/dev/pci/drm/radeon/radeon_display.c
1202
uint64_t tmp;
sys/dev/pci/drm/radeon/radeon_display.c
1206
tmp = (uint64_t)pll->reference_freq * feedback_div;
sys/dev/pci/drm/radeon/radeon_display.c
1207
vco = radeon_div(tmp, ref_div);
sys/dev/pci/drm/radeon/radeon_display.c
1219
tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
sys/dev/pci/drm/radeon/radeon_display.c
1220
tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
sys/dev/pci/drm/radeon/radeon_display.c
1221
current_freq = radeon_div(tmp, ref_div * post_div);
sys/dev/pci/drm/radeon/radeon_display.c
888
unsigned tmp;
sys/dev/pci/drm/radeon/radeon_display.c
891
tmp = gcd(*nom, *den);
sys/dev/pci/drm/radeon/radeon_display.c
892
*nom /= tmp;
sys/dev/pci/drm/radeon/radeon_display.c
893
*den /= tmp;
sys/dev/pci/drm/radeon/radeon_display.c
897
tmp = DIV_ROUND_UP(nom_min, *nom);
sys/dev/pci/drm/radeon/radeon_display.c
898
*nom *= tmp;
sys/dev/pci/drm/radeon/radeon_display.c
899
*den *= tmp;
sys/dev/pci/drm/radeon/radeon_display.c
904
tmp = DIV_ROUND_UP(den_min, *den);
sys/dev/pci/drm/radeon/radeon_display.c
905
*nom *= tmp;
sys/dev/pci/drm/radeon/radeon_display.c
906
*den *= tmp;
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
100
tmp |= (1 << 16);
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
101
WREG32(chan->rec.mask_clk_reg, tmp);
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
104
tmp = RREG32(AUX_CONTROL + aux_offset[instance]);
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
106
tmp &= AUX_HPD_SEL(0x7);
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
107
tmp |= AUX_HPD_SEL(chan->rec.hpd);
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
108
tmp |= AUX_EN | AUX_LS_READ_EN;
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
110
WREG32(AUX_CONTROL + aux_offset[instance], tmp);
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
153
tmp = RREG32(AUX_SW_STATUS + aux_offset[instance]);
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
154
if (tmp & AUX_SW_DONE) {
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
161
dev_err(rdev->dev, "auxch hw never signalled completion, error %08x\n", tmp);
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
166
if (tmp & AUX_SW_RX_TIMEOUT) {
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
170
if (tmp & AUX_RX_ERROR_FLAGS) {
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
171
drm_dbg_kms_ratelimited(dev, "dp_aux_ch flags not zero: %08x\n", tmp);
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
176
bytes = AUX_SW_REPLY_GET_BYTE_COUNT(tmp);
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
181
tmp = RREG32(AUX_SW_DATA + aux_offset[instance]);
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
182
ack = (tmp >> 8) & 0xff;
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
185
tmp = RREG32(AUX_SW_DATA + aux_offset[instance]);
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
187
buf[i] = (tmp >> 8) & 0xff;
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
62
uint32_t tmp, ack = 0;
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
99
tmp = RREG32(chan->rec.mask_clk_reg);
sys/dev/pci/drm/radeon/radeon_fbdev.c
221
unsigned long tmp;
sys/dev/pci/drm/radeon/radeon_fbdev.c
271
tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start;
sys/dev/pci/drm/radeon/radeon_fbdev.c
272
info->fix.smem_start = rdev->mc.aper_base + tmp;
sys/dev/pci/drm/radeon/radeon_fence.c
653
struct radeon_fence *tmp = *fence;
sys/dev/pci/drm/radeon/radeon_fence.c
656
if (tmp)
sys/dev/pci/drm/radeon/radeon_fence.c
657
dma_fence_put(&tmp->base);
sys/dev/pci/drm/radeon/radeon_i2c.c
430
u32 tmp, reg;
sys/dev/pci/drm/radeon/radeon_i2c.c
445
tmp = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/pci/drm/radeon/radeon_i2c.c
446
WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
sys/dev/pci/drm/radeon/radeon_i2c.c
573
tmp = RREG32(i2c_cntl_0);
sys/dev/pci/drm/radeon/radeon_i2c.c
574
if (tmp & RADEON_I2C_GO)
sys/dev/pci/drm/radeon/radeon_i2c.c
576
tmp = RREG32(i2c_cntl_0);
sys/dev/pci/drm/radeon/radeon_i2c.c
577
if (tmp & RADEON_I2C_DONE)
sys/dev/pci/drm/radeon/radeon_i2c.c
580
DRM_DEBUG("i2c write error 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/radeon_i2c.c
581
WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
sys/dev/pci/drm/radeon/radeon_i2c.c
605
tmp = RREG32(i2c_cntl_0);
sys/dev/pci/drm/radeon/radeon_i2c.c
606
if (tmp & RADEON_I2C_GO)
sys/dev/pci/drm/radeon/radeon_i2c.c
608
tmp = RREG32(i2c_cntl_0);
sys/dev/pci/drm/radeon/radeon_i2c.c
609
if (tmp & RADEON_I2C_DONE)
sys/dev/pci/drm/radeon/radeon_i2c.c
612
DRM_DEBUG("i2c read error 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/radeon_i2c.c
613
WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
sys/dev/pci/drm/radeon/radeon_i2c.c
633
tmp = RREG32(i2c_cntl_0);
sys/dev/pci/drm/radeon/radeon_i2c.c
634
if (tmp & RADEON_I2C_GO)
sys/dev/pci/drm/radeon/radeon_i2c.c
636
tmp = RREG32(i2c_cntl_0);
sys/dev/pci/drm/radeon/radeon_i2c.c
637
if (tmp & RADEON_I2C_DONE)
sys/dev/pci/drm/radeon/radeon_i2c.c
640
DRM_DEBUG("i2c write error 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/radeon_i2c.c
641
WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
sys/dev/pci/drm/radeon/radeon_i2c.c
659
tmp = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/pci/drm/radeon/radeon_i2c.c
660
tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
sys/dev/pci/drm/radeon/radeon_i2c.c
661
WREG32(RADEON_BIOS_6_SCRATCH, tmp);
sys/dev/pci/drm/radeon/radeon_i2c.c
682
u32 tmp, reg;
sys/dev/pci/drm/radeon/radeon_i2c.c
692
tmp = RREG32(rec->mask_clk_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
693
tmp &= ~rec->mask_clk_mask;
sys/dev/pci/drm/radeon/radeon_i2c.c
694
WREG32(rec->mask_clk_reg, tmp);
sys/dev/pci/drm/radeon/radeon_i2c.c
695
tmp = RREG32(rec->mask_clk_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
697
tmp = RREG32(rec->mask_data_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
698
tmp &= ~rec->mask_data_mask;
sys/dev/pci/drm/radeon/radeon_i2c.c
699
WREG32(rec->mask_data_reg, tmp);
sys/dev/pci/drm/radeon/radeon_i2c.c
700
tmp = RREG32(rec->mask_data_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
703
tmp = RREG32(rec->a_clk_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
704
tmp &= ~rec->a_clk_mask;
sys/dev/pci/drm/radeon/radeon_i2c.c
705
WREG32(rec->a_clk_reg, tmp);
sys/dev/pci/drm/radeon/radeon_i2c.c
706
tmp = RREG32(rec->a_clk_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
708
tmp = RREG32(rec->a_data_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
709
tmp &= ~rec->a_data_mask;
sys/dev/pci/drm/radeon/radeon_i2c.c
710
WREG32(rec->a_data_reg, tmp);
sys/dev/pci/drm/radeon/radeon_i2c.c
711
tmp = RREG32(rec->a_data_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
714
tmp = RREG32(rec->en_clk_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
715
tmp &= ~rec->en_clk_mask;
sys/dev/pci/drm/radeon/radeon_i2c.c
716
WREG32(rec->en_clk_reg, tmp);
sys/dev/pci/drm/radeon/radeon_i2c.c
717
tmp = RREG32(rec->en_clk_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
719
tmp = RREG32(rec->en_data_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
720
tmp &= ~rec->en_data_mask;
sys/dev/pci/drm/radeon/radeon_i2c.c
721
WREG32(rec->en_data_reg, tmp);
sys/dev/pci/drm/radeon/radeon_i2c.c
722
tmp = RREG32(rec->en_data_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
725
tmp = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/pci/drm/radeon/radeon_i2c.c
726
WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
sys/dev/pci/drm/radeon/radeon_i2c.c
781
tmp = RREG32(AVIVO_DC_I2C_STATUS1);
sys/dev/pci/drm/radeon/radeon_i2c.c
782
if (tmp & AVIVO_DC_I2C_GO)
sys/dev/pci/drm/radeon/radeon_i2c.c
784
tmp = RREG32(AVIVO_DC_I2C_STATUS1);
sys/dev/pci/drm/radeon/radeon_i2c.c
785
if (tmp & AVIVO_DC_I2C_DONE)
sys/dev/pci/drm/radeon/radeon_i2c.c
788
DRM_DEBUG("i2c write error 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/radeon_i2c.c
823
tmp = RREG32(AVIVO_DC_I2C_STATUS1);
sys/dev/pci/drm/radeon/radeon_i2c.c
824
if (tmp & AVIVO_DC_I2C_GO)
sys/dev/pci/drm/radeon/radeon_i2c.c
826
tmp = RREG32(AVIVO_DC_I2C_STATUS1);
sys/dev/pci/drm/radeon/radeon_i2c.c
827
if (tmp & AVIVO_DC_I2C_DONE)
sys/dev/pci/drm/radeon/radeon_i2c.c
830
DRM_DEBUG("i2c read error 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/radeon_i2c.c
866
tmp = RREG32(AVIVO_DC_I2C_STATUS1);
sys/dev/pci/drm/radeon/radeon_i2c.c
867
if (tmp & AVIVO_DC_I2C_GO)
sys/dev/pci/drm/radeon/radeon_i2c.c
869
tmp = RREG32(AVIVO_DC_I2C_STATUS1);
sys/dev/pci/drm/radeon/radeon_i2c.c
870
if (tmp & AVIVO_DC_I2C_DONE)
sys/dev/pci/drm/radeon/radeon_i2c.c
873
DRM_DEBUG("i2c write error 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/radeon_i2c.c
896
tmp = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/pci/drm/radeon/radeon_i2c.c
897
tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
sys/dev/pci/drm/radeon/radeon_i2c.c
898
WREG32(RADEON_BIOS_6_SCRATCH, tmp);
sys/dev/pci/drm/radeon/radeon_irq_kms.c
611
u32 tmp = RREG32(reg);
sys/dev/pci/drm/radeon/radeon_irq_kms.c
614
if (!!(tmp & mask) == enable)
sys/dev/pci/drm/radeon/radeon_irq_kms.c
619
WREG32(reg, tmp |= mask);
sys/dev/pci/drm/radeon/radeon_irq_kms.c
622
WREG32(reg, tmp & ~mask);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1305
uint32_t disp_output_cntl, gpiopad_a, tmp;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1323
tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1324
tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1325
WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1352
tmp = RREG32(RADEON_TV_DAC_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1353
if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1356
} else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1376
uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1388
tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1389
WREG32(RADEON_DAC_CNTL2, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1391
tmp = tv_master_cntl | RADEON_TV_ON;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1392
tmp &= ~(RADEON_TV_ASYNC_RST |
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1397
tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1398
WREG32(RADEON_TV_MASTER_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1400
tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1405
tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1407
tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1408
WREG32(RADEON_TV_DAC_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1410
tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1415
WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1418
tmp = RREG32(RADEON_TV_DAC_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1419
if (tmp & RADEON_TV_DAC_GDACDET) {
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1422
} else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1442
uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1463
tmp = RREG32(RADEON_GPIO_MONID);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1464
tmp &= ~RADEON_GPIO_A_0;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1465
WREG32(RADEON_GPIO_MONID, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1492
tmp = RREG32(RADEON_GPIO_MONID);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1493
if (tmp & RADEON_GPIO_Y_0)
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1530
uint32_t gpiopad_a = 0, pixclks_cntl, tmp;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1593
tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1595
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1598
tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1599
WREG32(RADEON_CRTC_EXT_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1601
tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1602
tmp |= RADEON_CRTC2_CRT2_ON |
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1604
WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1608
tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1609
tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1610
WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1612
tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1613
WREG32(RADEON_DISP_HW_DEBUG, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1617
tmp = RADEON_TV_DAC_NBLANK |
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1622
WREG32(RADEON_TV_DAC_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1624
tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1628
tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1630
tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1633
tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1635
tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1637
WREG32(RADEON_DAC_EXT_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1639
tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1640
WREG32(RADEON_DAC_CNTL2, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
640
uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
659
tmp = vclk_ecp_cntl &
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
661
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
663
tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
664
WREG32(RADEON_CRTC_EXT_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
666
tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
670
tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
672
tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
675
tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
677
tmp |= (0x1ac << RADEON_DAC_FORCE_DATA_SHIFT);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
679
tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
681
WREG32(RADEON_DAC_EXT_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
683
tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
684
tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
685
WREG32(RADEON_DAC_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
687
tmp = dac_macro_cntl;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
688
tmp &= ~(RADEON_DAC_PDWN_R |
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
692
WREG32(RADEON_DAC_MACRO_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
782
uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
787
tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
788
tmp &= 0xfffff;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
791
tmp ^= (1 << 22);
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
802
tmp = tmds->tmds_pll[i].value ;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
809
if (tmp & 0xfff00000)
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
810
tmds_pll_cntl = tmp;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
813
tmds_pll_cntl |= tmp;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
816
tmds_pll_cntl = tmp;
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
305
uint32_t tmp;
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
314
tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
315
if ((tmp & RADEON_HOST_FIFO_WT_ACK) == 0)
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
327
uint32_t tmp;
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
334
tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
335
if ((tmp & RADEON_HOST_FIFO_RD_ACK) == 0)
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
392
uint32_t tmp;
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
400
tmp = ((uint32_t)tv_dac->tv.h_code_timing[i] << 14) | ((uint32_t)tv_dac->tv.h_code_timing[i+1]);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
401
radeon_legacy_tv_write_fifo(radeon_encoder, h_table, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
406
tmp = ((uint32_t)tv_dac->tv.v_code_timing[i+1] << 14) | ((uint32_t)tv_dac->tv.v_code_timing[i]);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
407
radeon_legacy_tv_write_fifo(radeon_encoder, v_table, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
535
uint32_t vert_space, flicker_removal, tmp;
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
612
tmp = RREG32(RADEON_TV_VSCALER_CNTL1);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
613
tmp &= 0xe3ff0000;
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
614
tmp |= (vert_space * (1 << FRAC_BITS) / 10000);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
615
tv_vscaler_cntl1 = tmp;
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
626
tmp = const_ptr->ver_total * 2 * 1000;
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
631
tmp /= NTSC_TV_LINES_PER_FRAME;
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
633
tmp /= PAL_TV_LINES_PER_FRAME;
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
635
flicker_removal = (tmp + 500) / 1000;
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
661
tmp = (tv_vscaler_cntl1 >> RADEON_UV_INC_SHIFT) & RADEON_UV_INC_MASK;
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
662
tmp = ((16384 * 256 * 10) / tmp + 5) / 10;
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
663
tmp = (tmp << RADEON_UV_OUTPUT_POST_SCALE_SHIFT) | 0x000b0000;
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
664
tv_dac->tv.timing_cntl = tmp;
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
749
tmp = RREG32(RADEON_TV_DAC_CNTL);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
750
tmp &= ~RADEON_TV_DAC_NBLANK;
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
751
tmp |= RADEON_TV_DAC_BGSLEEP |
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
755
WREG32(RADEON_TV_DAC_CNTL, tmp);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
831
uint32_t tmp;
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
840
tmp = *h_sync_strt_wid;
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
841
tmp &= ~(RADEON_CRTC_H_SYNC_STRT_PIX | RADEON_CRTC_H_SYNC_STRT_CHAR);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
842
tmp |= (((const_ptr->hor_syncstart / 8) - 1) << RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT) |
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
844
*h_sync_strt_wid = tmp;
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
849
tmp = *v_sync_strt_wid;
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
850
tmp &= ~RADEON_CRTC_V_SYNC_STRT;
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
851
tmp |= ((const_ptr->ver_syncstart - 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT);
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
852
*v_sync_strt_wid = tmp;
sys/dev/pci/drm/radeon/radeon_uvd.c
366
unsigned image_size, tmp, min_dpb_size;
sys/dev/pci/drm/radeon/radeon_uvd.c
400
tmp = max(width_in_mb, height_in_mb);
sys/dev/pci/drm/radeon/radeon_uvd.c
401
min_dpb_size += ALIGN(tmp * 7 * 16, 64);
sys/dev/pci/drm/radeon/radeon_vce.c
590
uint32_t tmp = 0, handle = 0;
sys/dev/pci/drm/radeon/radeon_vce.c
591
uint32_t *size = &tmp;
sys/dev/pci/drm/radeon/radeon_vce.c
668
tmp = radeon_get_ib_value(p, p->idx + 4);
sys/dev/pci/drm/radeon/radeon_vce.c
670
tmp);
sys/dev/pci/drm/radeon/radeon_vm.c
1233
struct radeon_bo_va *bo_va, *tmp;
sys/dev/pci/drm/radeon/radeon_vm.c
1239
rbtree_postorder_for_each_entry_safe(bo_va, tmp,
sys/dev/pci/drm/radeon/radeon_vm.c
1250
list_for_each_entry_safe(bo_va, tmp, &vm->freed, vm_status) {
sys/dev/pci/drm/radeon/radeon_vm.c
483
struct radeon_bo_va *tmp;
sys/dev/pci/drm/radeon/radeon_vm.c
484
tmp = container_of(it, struct radeon_bo_va, it);
sys/dev/pci/drm/radeon/radeon_vm.c
488
soffset, tmp->bo, tmp->it.start, tmp->it.last);
sys/dev/pci/drm/radeon/radeon_vm.c
497
struct radeon_bo_va *tmp;
sys/dev/pci/drm/radeon/radeon_vm.c
498
tmp = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL);
sys/dev/pci/drm/radeon/radeon_vm.c
499
if (!tmp) {
sys/dev/pci/drm/radeon/radeon_vm.c
504
tmp->it.start = bo_va->it.start;
sys/dev/pci/drm/radeon/radeon_vm.c
505
tmp->it.last = bo_va->it.last;
sys/dev/pci/drm/radeon/radeon_vm.c
506
tmp->vm = vm;
sys/dev/pci/drm/radeon/radeon_vm.c
507
tmp->bo = radeon_bo_ref(bo_va->bo);
sys/dev/pci/drm/radeon/radeon_vm.c
514
list_add(&tmp->vm_status, &vm->freed);
sys/dev/pci/drm/radeon/rs400.c
114
uint32_t tmp;
sys/dev/pci/drm/radeon/rs400.c
116
tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
sys/dev/pci/drm/radeon/rs400.c
117
tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
sys/dev/pci/drm/radeon/rs400.c
118
WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
sys/dev/pci/drm/radeon/rs400.c
153
tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
sys/dev/pci/drm/radeon/rs400.c
154
tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
sys/dev/pci/drm/radeon/rs400.c
156
WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
sys/dev/pci/drm/radeon/rs400.c
157
tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
sys/dev/pci/drm/radeon/rs400.c
158
WREG32(RADEON_BUS_CNTL, tmp);
sys/dev/pci/drm/radeon/rs400.c
160
WREG32(RADEON_MC_AGP_LOCATION, tmp);
sys/dev/pci/drm/radeon/rs400.c
161
tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
sys/dev/pci/drm/radeon/rs400.c
162
WREG32(RADEON_BUS_CNTL, tmp);
sys/dev/pci/drm/radeon/rs400.c
165
tmp = (u32)rdev->gart.table_addr & 0xfffff000;
sys/dev/pci/drm/radeon/rs400.c
166
tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
sys/dev/pci/drm/radeon/rs400.c
168
WREG32_MC(RS480_GART_BASE, tmp);
sys/dev/pci/drm/radeon/rs400.c
180
tmp = RREG32_MC(RS480_MC_MISC_CNTL);
sys/dev/pci/drm/radeon/rs400.c
181
tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN;
sys/dev/pci/drm/radeon/rs400.c
182
WREG32_MC(RS480_MC_MISC_CNTL, tmp);
sys/dev/pci/drm/radeon/rs400.c
184
tmp = RREG32_MC(RS480_MC_MISC_CNTL);
sys/dev/pci/drm/radeon/rs400.c
185
tmp |= RS480_GART_INDEX_REG_EN;
sys/dev/pci/drm/radeon/rs400.c
186
WREG32_MC(RS480_MC_MISC_CNTL, tmp);
sys/dev/pci/drm/radeon/rs400.c
200
uint32_t tmp;
sys/dev/pci/drm/radeon/rs400.c
202
tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
sys/dev/pci/drm/radeon/rs400.c
203
tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
sys/dev/pci/drm/radeon/rs400.c
204
WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
sys/dev/pci/drm/radeon/rs400.c
244
uint32_t tmp;
sys/dev/pci/drm/radeon/rs400.c
248
tmp = RREG32(RADEON_MC_STATUS);
sys/dev/pci/drm/radeon/rs400.c
249
if (tmp & RADEON_MC_IDLE) {
sys/dev/pci/drm/radeon/rs400.c
326
uint32_t tmp;
sys/dev/pci/drm/radeon/rs400.c
328
tmp = RREG32(RADEON_HOST_PATH_CNTL);
sys/dev/pci/drm/radeon/rs400.c
329
seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
330
tmp = RREG32(RADEON_BUS_CNTL);
sys/dev/pci/drm/radeon/rs400.c
331
seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
332
tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
sys/dev/pci/drm/radeon/rs400.c
333
seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
335
tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
sys/dev/pci/drm/radeon/rs400.c
336
seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
337
tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
sys/dev/pci/drm/radeon/rs400.c
338
seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
339
tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
sys/dev/pci/drm/radeon/rs400.c
340
seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
341
tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION);
sys/dev/pci/drm/radeon/rs400.c
342
seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
343
tmp = RREG32(RS690_HDP_FB_LOCATION);
sys/dev/pci/drm/radeon/rs400.c
344
seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
346
tmp = RREG32(RADEON_AGP_BASE);
sys/dev/pci/drm/radeon/rs400.c
347
seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
348
tmp = RREG32(RS480_AGP_BASE_2);
sys/dev/pci/drm/radeon/rs400.c
349
seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
350
tmp = RREG32(RADEON_MC_AGP_LOCATION);
sys/dev/pci/drm/radeon/rs400.c
351
seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
353
tmp = RREG32_MC(RS480_GART_BASE);
sys/dev/pci/drm/radeon/rs400.c
354
seq_printf(m, "GART_BASE 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
355
tmp = RREG32_MC(RS480_GART_FEATURE_ID);
sys/dev/pci/drm/radeon/rs400.c
356
seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
357
tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
sys/dev/pci/drm/radeon/rs400.c
358
seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
359
tmp = RREG32_MC(RS480_MC_MISC_CNTL);
sys/dev/pci/drm/radeon/rs400.c
360
seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
361
tmp = RREG32_MC(0x5F);
sys/dev/pci/drm/radeon/rs400.c
362
seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
363
tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
sys/dev/pci/drm/radeon/rs400.c
364
seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
365
tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
sys/dev/pci/drm/radeon/rs400.c
366
seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
367
tmp = RREG32_MC(0x3B);
sys/dev/pci/drm/radeon/rs400.c
368
seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
369
tmp = RREG32_MC(0x3C);
sys/dev/pci/drm/radeon/rs400.c
370
seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
371
tmp = RREG32_MC(0x30);
sys/dev/pci/drm/radeon/rs400.c
372
seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
373
tmp = RREG32_MC(0x31);
sys/dev/pci/drm/radeon/rs400.c
374
seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
375
tmp = RREG32_MC(0x32);
sys/dev/pci/drm/radeon/rs400.c
376
seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
377
tmp = RREG32_MC(0x33);
sys/dev/pci/drm/radeon/rs400.c
378
seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
379
tmp = RREG32_MC(0x34);
sys/dev/pci/drm/radeon/rs400.c
380
seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
381
tmp = RREG32_MC(0x35);
sys/dev/pci/drm/radeon/rs400.c
382
seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
383
tmp = RREG32_MC(0x36);
sys/dev/pci/drm/radeon/rs400.c
384
seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
385
tmp = RREG32_MC(0x37);
sys/dev/pci/drm/radeon/rs400.c
386
seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rs400.c
67
uint32_t tmp;
sys/dev/pci/drm/radeon/rs400.c
72
tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
sys/dev/pci/drm/radeon/rs400.c
73
if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
sys/dev/pci/drm/radeon/rs600.c
123
u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
sys/dev/pci/drm/radeon/rs600.c
127
tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
sys/dev/pci/drm/radeon/rs600.c
128
WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/rs600.c
151
tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
sys/dev/pci/drm/radeon/rs600.c
152
WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/rs600.c
171
u32 tmp = 0;
sys/dev/pci/drm/radeon/rs600.c
191
tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
sys/dev/pci/drm/radeon/rs600.c
193
tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN;
sys/dev/pci/drm/radeon/rs600.c
198
tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN |
sys/dev/pci/drm/radeon/rs600.c
201
tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN |
sys/dev/pci/drm/radeon/rs600.c
212
WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp);
sys/dev/pci/drm/radeon/rs600.c
215
WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp);
sys/dev/pci/drm/radeon/rs600.c
218
WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp);
sys/dev/pci/drm/radeon/rs600.c
221
WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp);
sys/dev/pci/drm/radeon/rs600.c
233
u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
sys/dev/pci/drm/radeon/rs600.c
238
tmp = RREG32(voltage->gpio.reg);
sys/dev/pci/drm/radeon/rs600.c
240
tmp |= voltage->gpio.mask;
sys/dev/pci/drm/radeon/rs600.c
242
tmp &= ~(voltage->gpio.mask);
sys/dev/pci/drm/radeon/rs600.c
243
WREG32(voltage->gpio.reg, tmp);
sys/dev/pci/drm/radeon/rs600.c
247
tmp = RREG32(voltage->gpio.reg);
sys/dev/pci/drm/radeon/rs600.c
249
tmp &= ~voltage->gpio.mask;
sys/dev/pci/drm/radeon/rs600.c
251
tmp |= voltage->gpio.mask;
sys/dev/pci/drm/radeon/rs600.c
252
WREG32(voltage->gpio.reg, tmp);
sys/dev/pci/drm/radeon/rs600.c
327
u32 tmp;
sys/dev/pci/drm/radeon/rs600.c
333
tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
sys/dev/pci/drm/radeon/rs600.c
334
tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
sys/dev/pci/drm/radeon/rs600.c
335
WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/rs600.c
345
u32 tmp;
sys/dev/pci/drm/radeon/rs600.c
351
tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
sys/dev/pci/drm/radeon/rs600.c
352
tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
sys/dev/pci/drm/radeon/rs600.c
353
WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/rs600.c
361
u32 tmp;
sys/dev/pci/drm/radeon/rs600.c
366
tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
sys/dev/pci/drm/radeon/rs600.c
367
if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
sys/dev/pci/drm/radeon/rs600.c
371
tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
sys/dev/pci/drm/radeon/rs600.c
372
if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
sys/dev/pci/drm/radeon/rs600.c
384
u32 tmp;
sys/dev/pci/drm/radeon/rs600.c
389
tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
sys/dev/pci/drm/radeon/rs600.c
391
tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
sys/dev/pci/drm/radeon/rs600.c
393
tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
sys/dev/pci/drm/radeon/rs600.c
394
WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/rs600.c
397
tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
sys/dev/pci/drm/radeon/rs600.c
399
tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
sys/dev/pci/drm/radeon/rs600.c
401
tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
sys/dev/pci/drm/radeon/rs600.c
402
WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/rs600.c
465
u32 status, tmp;
sys/dev/pci/drm/radeon/rs600.c
478
tmp = RREG32(RADEON_CP_RB_CNTL);
sys/dev/pci/drm/radeon/rs600.c
479
WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
sys/dev/pci/drm/radeon/rs600.c
482
WREG32(RADEON_CP_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/rs600.c
529
uint32_t tmp;
sys/dev/pci/drm/radeon/rs600.c
531
tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
sys/dev/pci/drm/radeon/rs600.c
532
tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
sys/dev/pci/drm/radeon/rs600.c
533
WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
sys/dev/pci/drm/radeon/rs600.c
535
tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
sys/dev/pci/drm/radeon/rs600.c
536
tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
sys/dev/pci/drm/radeon/rs600.c
537
WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
sys/dev/pci/drm/radeon/rs600.c
539
tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
sys/dev/pci/drm/radeon/rs600.c
540
tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
sys/dev/pci/drm/radeon/rs600.c
541
WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
sys/dev/pci/drm/radeon/rs600.c
542
tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
sys/dev/pci/drm/radeon/rs600.c
564
u32 tmp;
sys/dev/pci/drm/radeon/rs600.c
575
tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
sys/dev/pci/drm/radeon/rs600.c
576
WREG32(RADEON_BUS_CNTL, tmp);
sys/dev/pci/drm/radeon/rs600.c
614
tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
sys/dev/pci/drm/radeon/rs600.c
615
WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
sys/dev/pci/drm/radeon/rs600.c
616
tmp = RREG32_MC(R_000009_MC_CNTL1);
sys/dev/pci/drm/radeon/rs600.c
617
WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
sys/dev/pci/drm/radeon/rs600.c
628
u32 tmp;
sys/dev/pci/drm/radeon/rs600.c
632
tmp = RREG32_MC(R_000009_MC_CNTL1);
sys/dev/pci/drm/radeon/rs600.c
633
WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
sys/dev/pci/drm/radeon/rs600.c
668
uint32_t tmp = 0;
sys/dev/pci/drm/radeon/rs600.c
687
tmp |= S_000040_SW_INT_EN(1);
sys/dev/pci/drm/radeon/rs600.c
706
WREG32(R_000040_GEN_INT_CNTL, tmp);
sys/dev/pci/drm/radeon/rs600.c
723
u32 tmp;
sys/dev/pci/drm/radeon/rs600.c
736
tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
sys/dev/pci/drm/radeon/rs600.c
737
tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
sys/dev/pci/drm/radeon/rs600.c
738
WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/rs600.c
741
tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
sys/dev/pci/drm/radeon/rs600.c
742
tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
sys/dev/pci/drm/radeon/rs600.c
743
WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
sys/dev/pci/drm/radeon/rs600.c
753
tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
sys/dev/pci/drm/radeon/rs600.c
754
tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);
sys/dev/pci/drm/radeon/rs600.c
755
WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);
sys/dev/pci/drm/radeon/rs690.c
104
rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
sys/dev/pci/drm/radeon/rs690.c
106
rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
sys/dev/pci/drm/radeon/rs690.c
128
tmp.full = dfixed_const(4);
sys/dev/pci/drm/radeon/rs690.c
129
rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
sys/dev/pci/drm/radeon/rs690.c
133
tmp.full = dfixed_const(5);
sys/dev/pci/drm/radeon/rs690.c
136
rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
sys/dev/pci/drm/radeon/rs690.c
137
if (tmp.full < rdev->pm.max_bandwidth.full) {
sys/dev/pci/drm/radeon/rs690.c
139
rdev->pm.max_bandwidth.full = tmp.full;
sys/dev/pci/drm/radeon/rs690.c
144
tmp.full = dfixed_const(14);
sys/dev/pci/drm/radeon/rs690.c
145
rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
sys/dev/pci/drm/radeon/rs690.c
146
tmp.full = dfixed_const(10);
sys/dev/pci/drm/radeon/rs690.c
147
rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
sys/dev/pci/drm/radeon/rs690.c
209
u32 tmp;
sys/dev/pci/drm/radeon/rs690.c
228
tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
sys/dev/pci/drm/radeon/rs690.c
229
tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
sys/dev/pci/drm/radeon/rs690.c
234
tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
sys/dev/pci/drm/radeon/rs690.c
236
tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
sys/dev/pci/drm/radeon/rs690.c
239
tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
sys/dev/pci/drm/radeon/rs690.c
241
tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
sys/dev/pci/drm/radeon/rs690.c
243
tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
sys/dev/pci/drm/radeon/rs690.c
245
tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
sys/dev/pci/drm/radeon/rs690.c
247
tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
sys/dev/pci/drm/radeon/rs690.c
249
WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
sys/dev/pci/drm/radeon/rs690.c
40
uint32_t tmp;
sys/dev/pci/drm/radeon/rs690.c
44
tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
sys/dev/pci/drm/radeon/rs690.c
45
if (G_000090_MC_SYSTEM_IDLE(tmp))
sys/dev/pci/drm/radeon/rs690.c
590
u32 tmp;
sys/dev/pci/drm/radeon/rs690.c
610
tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
sys/dev/pci/drm/radeon/rs690.c
611
tmp &= C_000104_MC_DISP0R_INIT_LAT;
sys/dev/pci/drm/radeon/rs690.c
612
tmp &= C_000104_MC_DISP1R_INIT_LAT;
sys/dev/pci/drm/radeon/rs690.c
614
tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
sys/dev/pci/drm/radeon/rs690.c
616
tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
sys/dev/pci/drm/radeon/rs690.c
617
WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
sys/dev/pci/drm/radeon/rs690.c
632
tmp = (wm0_high.lb_request_fifo_depth - 1);
sys/dev/pci/drm/radeon/rs690.c
633
tmp |= (wm1_high.lb_request_fifo_depth - 1) << 16;
sys/dev/pci/drm/radeon/rs690.c
634
WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
sys/dev/pci/drm/radeon/rs690.c
72
fixed20_12 tmp;
sys/dev/pci/drm/radeon/rs690.c
81
tmp.full = dfixed_const(100);
sys/dev/pci/drm/radeon/rs690.c
83
rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
sys/dev/pci/drm/radeon/rs690.c
88
rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
sys/dev/pci/drm/radeon/rs690.c
95
tmp.full = dfixed_const(100);
sys/dev/pci/drm/radeon/rs690.c
97
rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
sys/dev/pci/drm/radeon/rv515.c
1209
u32 tmp;
sys/dev/pci/drm/radeon/rv515.c
122
uint32_t tmp;
sys/dev/pci/drm/radeon/rv515.c
1225
tmp = wm0_high.lb_request_fifo_depth;
sys/dev/pci/drm/radeon/rv515.c
1226
tmp |= wm1_high.lb_request_fifo_depth << 16;
sys/dev/pci/drm/radeon/rv515.c
1227
WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
sys/dev/pci/drm/radeon/rv515.c
1246
uint32_t tmp;
sys/dev/pci/drm/radeon/rv515.c
126
tmp = RREG32_MC(MC_STATUS);
sys/dev/pci/drm/radeon/rv515.c
1266
tmp = RREG32_MC(MC_MISC_LAT_TIMER);
sys/dev/pci/drm/radeon/rv515.c
1267
tmp &= ~MC_DISP1R_INIT_LAT_MASK;
sys/dev/pci/drm/radeon/rv515.c
1268
tmp &= ~MC_DISP0R_INIT_LAT_MASK;
sys/dev/pci/drm/radeon/rv515.c
127
if (tmp & MC_STATUS_IDLE) {
sys/dev/pci/drm/radeon/rv515.c
1270
tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
sys/dev/pci/drm/radeon/rv515.c
1272
tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
sys/dev/pci/drm/radeon/rv515.c
1273
WREG32_MC(MC_MISC_LAT_TIMER, tmp);
sys/dev/pci/drm/radeon/rv515.c
143
unsigned pipe_select_current, gb_pipe_select, tmp;
sys/dev/pci/drm/radeon/rv515.c
151
tmp = RREG32(R300_DST_PIPE_CONFIG);
sys/dev/pci/drm/radeon/rv515.c
152
pipe_select_current = (tmp >> 2) & 3;
sys/dev/pci/drm/radeon/rv515.c
153
tmp = (1 << pipe_select_current) |
sys/dev/pci/drm/radeon/rv515.c
155
WREG32_PLL(0x000D, tmp);
sys/dev/pci/drm/radeon/rv515.c
166
uint32_t tmp;
sys/dev/pci/drm/radeon/rv515.c
170
tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
sys/dev/pci/drm/radeon/rv515.c
171
switch (tmp) {
sys/dev/pci/drm/radeon/rv515.c
225
uint32_t tmp;
sys/dev/pci/drm/radeon/rv515.c
227
tmp = RREG32(GB_PIPE_SELECT);
sys/dev/pci/drm/radeon/rv515.c
228
seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rv515.c
229
tmp = RREG32(SU_REG_DEST);
sys/dev/pci/drm/radeon/rv515.c
230
seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rv515.c
231
tmp = RREG32(GB_TILE_CONFIG);
sys/dev/pci/drm/radeon/rv515.c
232
seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rv515.c
233
tmp = RREG32(DST_PIPE_CONFIG);
sys/dev/pci/drm/radeon/rv515.c
234
seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rv515.c
241
uint32_t tmp;
sys/dev/pci/drm/radeon/rv515.c
243
tmp = RREG32(0x2140);
sys/dev/pci/drm/radeon/rv515.c
244
seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rv515.c
246
tmp = RREG32(0x425C);
sys/dev/pci/drm/radeon/rv515.c
247
seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/rv515.c
270
u32 crtc_enabled, tmp, frame_count, blackout;
sys/dev/pci/drm/radeon/rv515.c
283
tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
sys/dev/pci/drm/radeon/rv515.c
284
if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {
sys/dev/pci/drm/radeon/rv515.c
287
tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
sys/dev/pci/drm/radeon/rv515.c
288
WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/rv515.c
301
tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
sys/dev/pci/drm/radeon/rv515.c
302
tmp &= ~AVIVO_CRTC_EN;
sys/dev/pci/drm/radeon/rv515.c
303
WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/rv515.c
336
tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
sys/dev/pci/drm/radeon/rv515.c
337
if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) {
sys/dev/pci/drm/radeon/rv515.c
338
tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
sys/dev/pci/drm/radeon/rv515.c
339
WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/rv515.c
341
tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
sys/dev/pci/drm/radeon/rv515.c
342
if (!(tmp & 1)) {
sys/dev/pci/drm/radeon/rv515.c
343
tmp |= 1;
sys/dev/pci/drm/radeon/rv515.c
344
WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/rv515.c
352
u32 tmp, frame_count;
sys/dev/pci/drm/radeon/rv515.c
380
tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
sys/dev/pci/drm/radeon/rv515.c
381
if ((tmp & 0x7) != 3) {
sys/dev/pci/drm/radeon/rv515.c
382
tmp &= ~0x7;
sys/dev/pci/drm/radeon/rv515.c
383
tmp |= 0x3;
sys/dev/pci/drm/radeon/rv515.c
384
WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/rv515.c
386
tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
sys/dev/pci/drm/radeon/rv515.c
387
if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) {
sys/dev/pci/drm/radeon/rv515.c
388
tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
sys/dev/pci/drm/radeon/rv515.c
389
WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/rv515.c
391
tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
sys/dev/pci/drm/radeon/rv515.c
392
if (tmp & 1) {
sys/dev/pci/drm/radeon/rv515.c
393
tmp &= ~1;
sys/dev/pci/drm/radeon/rv515.c
394
WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/rv515.c
397
tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
sys/dev/pci/drm/radeon/rv515.c
398
if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0)
sys/dev/pci/drm/radeon/rv515.c
408
tmp = RREG32(R700_MC_CITF_CNTL);
sys/dev/pci/drm/radeon/rv515.c
410
tmp = RREG32(R600_CITF_CNTL);
sys/dev/pci/drm/radeon/rv515.c
411
tmp &= ~R600_BLACKOUT_MASK;
sys/dev/pci/drm/radeon/rv515.c
413
WREG32(R700_MC_CITF_CNTL, tmp);
sys/dev/pci/drm/radeon/rv515.c
415
WREG32(R600_CITF_CNTL, tmp);
sys/dev/pci/drm/radeon/rv515.c
422
tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
sys/dev/pci/drm/radeon/rv515.c
423
tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
sys/dev/pci/drm/radeon/rv515.c
424
WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
102
u32 tmp;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
104
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL) & ~LC_L0S_INACTIVITY_MASK;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
105
tmp |= LC_L0S_INACTIVITY(3);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
106
WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
111
u32 tmp;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
113
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
114
tmp &= ~LC_L1_INACTIVITY_MASK;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
115
tmp |= LC_L1_INACTIVITY(4);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
116
tmp &= ~LC_PMI_TO_L1_DIS;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
117
tmp &= ~LC_ASPM_TO_L1_DIS;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
118
WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1182
u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1184
tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1186
tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1187
tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1189
tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1190
tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1192
tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1193
tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1195
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
123
u32 tmp;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
125
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL) & ~LC_L1_INACTIVITY_MASK;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
126
tmp |= LC_L1_INACTIVITY(8);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
127
WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
130
tmp = RREG32_PCIE(PCIE_P_CNTL);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
131
tmp |= P_PLL_PWRDN_IN_L1L23;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
132
tmp &= ~P_PLL_BUF_PDNB;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
133
tmp &= ~P_PLL_PDNB;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
134
tmp |= P_ALLOW_PRX_FRONTEND_SHUTOFF;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
135
WREG32_PCIE(PCIE_P_CNTL, tmp);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
412
u32 tmp = 1 << (2 * unit);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
414
return tmp;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
52
u32 tmp;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
55
tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
56
tmp &= LC_GEN2_EN;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
57
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
59
tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
60
tmp |= LC_INITIATE_LINK_SPEED_CHANGE;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
61
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
69
tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
70
tmp &= ~LC_INITIATE_LINK_SPEED_CHANGE;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
71
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
76
u32 tmp;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
78
tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
785
u32 tmp;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
787
tmp = (RREG32(RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
788
dram_rows = 1 << (tmp + 10);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
80
if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
sys/dev/pci/drm/radeon/rv6xx_dpm.c
81
(tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
sys/dev/pci/drm/radeon/rv6xx_dpm.c
82
tmp |= LC_GEN2_EN;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
83
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
90
u32 tmp;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
92
tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
94
tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
96
tmp |= LC_HW_VOLTAGE_IF_CONTROL(0);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
97
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/pci/drm/radeon/rv6xx_dpm.c
983
u32 tmp = (DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM) |
sys/dev/pci/drm/radeon/rv6xx_dpm.c
989
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/pci/drm/radeon/rv730_dpm.c
48
u64 tmp;
sys/dev/pci/drm/radeon/rv730_dpm.c
67
tmp = (u64) engine_clock * reference_divider * post_divider * 16384;
sys/dev/pci/drm/radeon/rv730_dpm.c
68
do_div(tmp, reference_clock);
sys/dev/pci/drm/radeon/rv730_dpm.c
69
fbdiv = (u32) tmp;
sys/dev/pci/drm/radeon/rv740_dpm.c
129
u64 tmp;
sys/dev/pci/drm/radeon/rv740_dpm.c
142
tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
sys/dev/pci/drm/radeon/rv740_dpm.c
143
do_div(tmp, reference_clock);
sys/dev/pci/drm/radeon/rv740_dpm.c
144
fbdiv = (u32) tmp;
sys/dev/pci/drm/radeon/rv770.c
1000
WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
1008
u32 tmp;
sys/dev/pci/drm/radeon/rv770.c
1022
tmp = RREG32(HDP_DEBUG1);
sys/dev/pci/drm/radeon/rv770.c
1052
tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
sys/dev/pci/drm/radeon/rv770.c
1053
tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
sys/dev/pci/drm/radeon/rv770.c
1054
WREG32(MC_VM_FB_LOCATION, tmp);
sys/dev/pci/drm/radeon/rv770.c
1137
u32 tmp, i;
sys/dev/pci/drm/radeon/rv770.c
1142
tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
sys/dev/pci/drm/radeon/rv770.c
1143
tmp &= SCLK_MUX_SEL_MASK;
sys/dev/pci/drm/radeon/rv770.c
1144
tmp |= SCLK_MUX_SEL(1) | SCLK_MUX_UPDATE;
sys/dev/pci/drm/radeon/rv770.c
1145
WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
sys/dev/pci/drm/radeon/rv770.c
1153
tmp &= ~SCLK_MUX_UPDATE;
sys/dev/pci/drm/radeon/rv770.c
1154
WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
sys/dev/pci/drm/radeon/rv770.c
1156
tmp = RREG32(MPLL_CNTL_MODE);
sys/dev/pci/drm/radeon/rv770.c
1158
tmp &= ~RV730_MPLL_MCLK_SEL;
sys/dev/pci/drm/radeon/rv770.c
1160
tmp &= ~MPLL_MCLK_SEL;
sys/dev/pci/drm/radeon/rv770.c
1161
WREG32(MPLL_CNTL_MODE, tmp);
sys/dev/pci/drm/radeon/rv770.c
1185
u32 db_debug4, tmp;
sys/dev/pci/drm/radeon/rv770.c
1304
for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) {
sys/dev/pci/drm/radeon/rv770.c
1305
if (!(inactive_pipes & tmp)) {
sys/dev/pci/drm/radeon/rv770.c
1308
tmp <<= 1;
sys/dev/pci/drm/radeon/rv770.c
1317
tmp = rdev->config.rv770.max_simds -
sys/dev/pci/drm/radeon/rv770.c
1319
rdev->config.rv770.active_simds = tmp;
sys/dev/pci/drm/radeon/rv770.c
1339
tmp = 0;
sys/dev/pci/drm/radeon/rv770.c
1341
tmp |= (1 << i);
sys/dev/pci/drm/radeon/rv770.c
1343
if ((disabled_rb_mask & tmp) == tmp) {
sys/dev/pci/drm/radeon/rv770.c
1347
tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
sys/dev/pci/drm/radeon/rv770.c
1348
tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends,
sys/dev/pci/drm/radeon/rv770.c
1350
gb_tiling_config |= tmp << 16;
sys/dev/pci/drm/radeon/rv770.c
1351
rdev->config.rv770.backend_map = tmp;
sys/dev/pci/drm/radeon/rv770.c
1644
u32 tmp;
sys/dev/pci/drm/radeon/rv770.c
1649
tmp = RREG32(MC_ARB_RAMCFG);
sys/dev/pci/drm/radeon/rv770.c
1650
if (tmp & CHANSIZE_OVERRIDE) {
sys/dev/pci/drm/radeon/rv770.c
1652
} else if (tmp & CHANSIZE_MASK) {
sys/dev/pci/drm/radeon/rv770.c
1657
tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/pci/drm/radeon/rv770.c
1658
switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
sys/dev/pci/drm/radeon/rv770.c
2022
u32 link_width_cntl, lanes, speed_cntl, tmp;
sys/dev/pci/drm/radeon/rv770.c
2067
tmp = RREG32(0x541c);
sys/dev/pci/drm/radeon/rv770.c
2068
WREG32(0x541c, tmp | 0x8);
sys/dev/pci/drm/radeon/rv770.c
789
u32 tmp = RREG32(CG_CLKPIN_CNTL);
sys/dev/pci/drm/radeon/rv770.c
791
if (tmp & MUX_TCLK_TO_XCLK)
sys/dev/pci/drm/radeon/rv770.c
794
if (tmp & XTALIN_DIVIDE)
sys/dev/pci/drm/radeon/rv770.c
804
u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
sys/dev/pci/drm/radeon/rv770.c
808
tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
sys/dev/pci/drm/radeon/rv770.c
809
WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/rv770.c
839
tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
sys/dev/pci/drm/radeon/rv770.c
840
WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/rv770.c
896
u32 tmp;
sys/dev/pci/drm/radeon/rv770.c
913
tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
sys/dev/pci/drm/radeon/rv770.c
917
WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
918
WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
919
WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
921
WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
922
WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
923
WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
924
WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
925
WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
946
u32 tmp;
sys/dev/pci/drm/radeon/rv770.c
959
tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
sys/dev/pci/drm/radeon/rv770.c
960
WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
961
WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
962
WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
963
WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
964
WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
965
WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
966
WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
980
u32 tmp;
sys/dev/pci/drm/radeon/rv770.c
990
tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
sys/dev/pci/drm/radeon/rv770.c
994
WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
995
WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
996
WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
997
WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
998
WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770.c
999
WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770_dpm.c
104
u32 tmp;
sys/dev/pci/drm/radeon/rv770_dpm.c
106
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL);
sys/dev/pci/drm/radeon/rv770_dpm.c
107
tmp &= ~LC_L1_INACTIVITY_MASK;
sys/dev/pci/drm/radeon/rv770_dpm.c
108
tmp |= LC_L1_INACTIVITY(4);
sys/dev/pci/drm/radeon/rv770_dpm.c
109
tmp &= ~LC_PMI_TO_L1_DIS;
sys/dev/pci/drm/radeon/rv770_dpm.c
110
tmp &= ~LC_ASPM_TO_L1_DIS;
sys/dev/pci/drm/radeon/rv770_dpm.c
111
WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770_dpm.c
116
u32 tmp;
sys/dev/pci/drm/radeon/rv770_dpm.c
118
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL) & ~LC_L1_INACTIVITY_MASK;
sys/dev/pci/drm/radeon/rv770_dpm.c
119
tmp |= LC_L1_INACTIVITY(8);
sys/dev/pci/drm/radeon/rv770_dpm.c
120
WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770_dpm.c
123
tmp = RREG32_PCIE(PCIE_P_CNTL);
sys/dev/pci/drm/radeon/rv770_dpm.c
124
tmp |= P_PLL_PWRDN_IN_L1L23;
sys/dev/pci/drm/radeon/rv770_dpm.c
125
tmp &= ~P_PLL_BUF_PDNB;
sys/dev/pci/drm/radeon/rv770_dpm.c
126
tmp &= ~P_PLL_PDNB;
sys/dev/pci/drm/radeon/rv770_dpm.c
127
tmp |= P_ALLOW_PRX_FRONTEND_SHUTOFF;
sys/dev/pci/drm/radeon/rv770_dpm.c
128
WREG32_PCIE(PCIE_P_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770_dpm.c
1345
u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
sys/dev/pci/drm/radeon/rv770_dpm.c
1347
tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
sys/dev/pci/drm/radeon/rv770_dpm.c
1349
tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
sys/dev/pci/drm/radeon/rv770_dpm.c
1350
tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/pci/drm/radeon/rv770_dpm.c
1352
tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/pci/drm/radeon/rv770_dpm.c
1353
tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
sys/dev/pci/drm/radeon/rv770_dpm.c
1355
tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/pci/drm/radeon/rv770_dpm.c
1356
tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/pci/drm/radeon/rv770_dpm.c
1358
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770_dpm.c
1594
u32 tmp;
sys/dev/pci/drm/radeon/rv770_dpm.c
1596
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/pci/drm/radeon/rv770_dpm.c
1598
if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
sys/dev/pci/drm/radeon/rv770_dpm.c
1609
u32 tmp;
sys/dev/pci/drm/radeon/rv770_dpm.c
1611
tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
sys/dev/pci/drm/radeon/rv770_dpm.c
1613
if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
sys/dev/pci/drm/radeon/rv770_dpm.c
1614
(tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
sys/dev/pci/drm/radeon/rv770_dpm.c
1620
if (tmp & LC_CURRENT_DATA_RATE)
sys/dev/pci/drm/radeon/rv770_dpm.c
501
u64 tmp;
sys/dev/pci/drm/radeon/rv770_dpm.c
519
tmp = (u64) engine_clock * reference_divider * post_divider * 16384;
sys/dev/pci/drm/radeon/rv770_dpm.c
520
do_div(tmp, reference_clock);
sys/dev/pci/drm/radeon/rv770_dpm.c
521
fbdiv = (u32) tmp;
sys/dev/pci/drm/radeon/rv770_dpm.c
729
u32 tmp;
sys/dev/pci/drm/radeon/rv770_dpm.c
731
tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
sys/dev/pci/drm/radeon/rv770_dpm.c
732
dram_rows = 1 << (tmp + 10);
sys/dev/pci/drm/radeon/rv770_dpm.c
733
tmp = RREG32(MC_SEQ_MISC0) & 3;
sys/dev/pci/drm/radeon/rv770_dpm.c
734
dram_refresh_rate = 1 << (tmp + 3);
sys/dev/pci/drm/radeon/rv770_dpm.c
74
u32 tmp;
sys/dev/pci/drm/radeon/rv770_dpm.c
76
tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
sys/dev/pci/drm/radeon/rv770_dpm.c
78
tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
sys/dev/pci/drm/radeon/rv770_dpm.c
79
tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
sys/dev/pci/drm/radeon/rv770_dpm.c
80
tmp |= LC_GEN2_EN_STRAP;
sys/dev/pci/drm/radeon/rv770_dpm.c
83
tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
sys/dev/pci/drm/radeon/rv770_dpm.c
84
tmp &= ~LC_GEN2_EN_STRAP;
sys/dev/pci/drm/radeon/rv770_dpm.c
87
if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
sys/dev/pci/drm/radeon/rv770_dpm.c
88
(tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
sys/dev/pci/drm/radeon/rv770_dpm.c
881
u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
sys/dev/pci/drm/radeon/rv770_dpm.c
883
tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
sys/dev/pci/drm/radeon/rv770_dpm.c
884
tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) |
sys/dev/pci/drm/radeon/rv770_dpm.c
886
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770_dpm.c
89
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770_dpm.c
95
u32 tmp;
sys/dev/pci/drm/radeon/rv770_dpm.c
97
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL) & ~LC_L0S_INACTIVITY_MASK;
sys/dev/pci/drm/radeon/rv770_dpm.c
98
tmp |= LC_L0S_INACTIVITY(3);
sys/dev/pci/drm/radeon/rv770_dpm.c
99
WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
sys/dev/pci/drm/radeon/rv770_smc.c
354
u32 tmp, i;
sys/dev/pci/drm/radeon/rv770_smc.c
360
tmp = FIRST_SMC_INT_VECT_REG - smc_first_vector;
sys/dev/pci/drm/radeon/rv770_smc.c
362
if (tmp > byte_count)
sys/dev/pci/drm/radeon/rv770_smc.c
365
byte_count -= tmp;
sys/dev/pci/drm/radeon/rv770_smc.c
366
src += tmp;
sys/dev/pci/drm/radeon/rv770_smc.c
372
tmp = (src[i] << 24) | (src[i + 1] << 16) | (src[i + 2] << 8) | src[i + 3];
sys/dev/pci/drm/radeon/rv770_smc.c
374
WREG32(SMC_ISR_FFD8_FFDB + i, tmp);
sys/dev/pci/drm/radeon/rv770_smc.c
402
u32 tmp;
sys/dev/pci/drm/radeon/rv770_smc.c
404
tmp = RREG32(SMC_IO);
sys/dev/pci/drm/radeon/rv770_smc.c
406
if ((tmp & SMC_RST_N) && (tmp & SMC_CLK_EN))
sys/dev/pci/drm/radeon/rv770_smc.c
414
u32 tmp;
sys/dev/pci/drm/radeon/rv770_smc.c
424
tmp = RREG32(SMC_MSG) & HOST_SMC_RESP_MASK;
sys/dev/pci/drm/radeon/rv770_smc.c
425
tmp >>= HOST_SMC_RESP_SHIFT;
sys/dev/pci/drm/radeon/rv770_smc.c
426
if (tmp != 0)
sys/dev/pci/drm/radeon/rv770_smc.c
431
tmp = RREG32(SMC_MSG) & HOST_SMC_RESP_MASK;
sys/dev/pci/drm/radeon/rv770_smc.c
432
tmp >>= HOST_SMC_RESP_SHIFT;
sys/dev/pci/drm/radeon/rv770_smc.c
434
result = (PPSMC_Result)tmp;
sys/dev/pci/drm/radeon/si.c
1321
u32 tmp;
sys/dev/pci/drm/radeon/si.c
1323
tmp = RREG32(CG_CLKPIN_CNTL_2);
sys/dev/pci/drm/radeon/si.c
1324
if (tmp & MUX_TCLK_TO_XCLK)
sys/dev/pci/drm/radeon/si.c
1327
tmp = RREG32(CG_CLKPIN_CNTL);
sys/dev/pci/drm/radeon/si.c
1328
if (tmp & XTALIN_DIVIDE)
sys/dev/pci/drm/radeon/si.c
1952
u32 tmp, buffer_alloc, i;
sys/dev/pci/drm/radeon/si.c
1969
tmp = 0; /* 1/2 */
sys/dev/pci/drm/radeon/si.c
1972
tmp = 2; /* whole */
sys/dev/pci/drm/radeon/si.c
1976
tmp = 0;
sys/dev/pci/drm/radeon/si.c
1981
DC_LB_MEMORY_CONFIG(tmp));
sys/dev/pci/drm/radeon/si.c
1993
switch (tmp) {
sys/dev/pci/drm/radeon/si.c
2008
u32 tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/pci/drm/radeon/si.c
2010
switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
sys/dev/pci/drm/radeon/si.c
2192
u32 tmp, dmif_size = 12288;
sys/dev/pci/drm/radeon/si.c
2211
tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
sys/dev/pci/drm/radeon/si.c
2212
tmp = min(dfixed_trunc(a), tmp);
sys/dev/pci/drm/radeon/si.c
2214
lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
sys/dev/pci/drm/radeon/si.c
2287
u32 tmp, arb_control3;
sys/dev/pci/drm/radeon/si.c
2412
tmp = arb_control3;
sys/dev/pci/drm/radeon/si.c
2413
tmp &= ~LATENCY_WATERMARK_MASK(3);
sys/dev/pci/drm/radeon/si.c
2414
tmp |= LATENCY_WATERMARK_MASK(1);
sys/dev/pci/drm/radeon/si.c
2415
WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/si.c
2420
tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
sys/dev/pci/drm/radeon/si.c
2421
tmp &= ~LATENCY_WATERMARK_MASK(3);
sys/dev/pci/drm/radeon/si.c
2422
tmp |= LATENCY_WATERMARK_MASK(2);
sys/dev/pci/drm/radeon/si.c
2423
WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
sys/dev/pci/drm/radeon/si.c
3075
u32 tmp;
sys/dev/pci/drm/radeon/si.c
3189
tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
sys/dev/pci/drm/radeon/si.c
3190
rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
sys/dev/pci/drm/radeon/si.c
3323
tmp = RREG32(HDP_MISC_CNTL);
sys/dev/pci/drm/radeon/si.c
3324
tmp |= HDP_FLUSH_INVALIDATE_CACHE;
sys/dev/pci/drm/radeon/si.c
3325
WREG32(HDP_MISC_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
3631
u32 tmp;
sys/dev/pci/drm/radeon/si.c
3650
tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
sys/dev/pci/drm/radeon/si.c
3652
tmp |= BUF_SWAP_32BIT;
sys/dev/pci/drm/radeon/si.c
3654
WREG32(CP_RB0_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
3657
WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
sys/dev/pci/drm/radeon/si.c
3668
tmp |= RB_NO_UPDATE;
sys/dev/pci/drm/radeon/si.c
3673
WREG32(CP_RB0_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
3681
tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
sys/dev/pci/drm/radeon/si.c
3683
tmp |= BUF_SWAP_32BIT;
sys/dev/pci/drm/radeon/si.c
3685
WREG32(CP_RB1_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
3688
WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
sys/dev/pci/drm/radeon/si.c
3697
WREG32(CP_RB1_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
3705
tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
sys/dev/pci/drm/radeon/si.c
3707
tmp |= BUF_SWAP_32BIT;
sys/dev/pci/drm/radeon/si.c
3709
WREG32(CP_RB2_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
3712
WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
sys/dev/pci/drm/radeon/si.c
3721
WREG32(CP_RB2_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
3757
u32 tmp;
sys/dev/pci/drm/radeon/si.c
3760
tmp = RREG32(GRBM_STATUS);
sys/dev/pci/drm/radeon/si.c
3761
if (tmp & (PA_BUSY | SC_BUSY |
sys/dev/pci/drm/radeon/si.c
3769
if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
sys/dev/pci/drm/radeon/si.c
3773
if (tmp & GRBM_EE_BUSY)
sys/dev/pci/drm/radeon/si.c
3777
tmp = RREG32(GRBM_STATUS2);
sys/dev/pci/drm/radeon/si.c
3778
if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
sys/dev/pci/drm/radeon/si.c
3782
tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/si.c
3783
if (!(tmp & DMA_IDLE))
sys/dev/pci/drm/radeon/si.c
3787
tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/si.c
3788
if (!(tmp & DMA_IDLE))
sys/dev/pci/drm/radeon/si.c
3792
tmp = RREG32(SRBM_STATUS2);
sys/dev/pci/drm/radeon/si.c
3793
if (tmp & DMA_BUSY)
sys/dev/pci/drm/radeon/si.c
3796
if (tmp & DMA1_BUSY)
sys/dev/pci/drm/radeon/si.c
3800
tmp = RREG32(SRBM_STATUS);
sys/dev/pci/drm/radeon/si.c
3802
if (tmp & IH_BUSY)
sys/dev/pci/drm/radeon/si.c
3805
if (tmp & SEM_BUSY)
sys/dev/pci/drm/radeon/si.c
3808
if (tmp & GRBM_RQ_PENDING)
sys/dev/pci/drm/radeon/si.c
3811
if (tmp & VMC_BUSY)
sys/dev/pci/drm/radeon/si.c
3814
if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
sys/dev/pci/drm/radeon/si.c
3822
tmp = RREG32(VM_L2_STATUS);
sys/dev/pci/drm/radeon/si.c
3823
if (tmp & L2_BUSY)
sys/dev/pci/drm/radeon/si.c
3839
u32 tmp;
sys/dev/pci/drm/radeon/si.c
3864
tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/si.c
3865
tmp &= ~DMA_RB_ENABLE;
sys/dev/pci/drm/radeon/si.c
3866
WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/si.c
3870
tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/si.c
3871
tmp &= ~DMA_RB_ENABLE;
sys/dev/pci/drm/radeon/si.c
3872
WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/si.c
3931
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/si.c
3932
tmp |= grbm_soft_reset;
sys/dev/pci/drm/radeon/si.c
3933
dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/radeon/si.c
3934
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/si.c
3935
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/si.c
3939
tmp &= ~grbm_soft_reset;
sys/dev/pci/drm/radeon/si.c
3940
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/si.c
3941
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/si.c
3945
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/si.c
3946
tmp |= srbm_soft_reset;
sys/dev/pci/drm/radeon/si.c
3947
dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/pci/drm/radeon/si.c
3948
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/si.c
3949
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/si.c
3953
tmp &= ~srbm_soft_reset;
sys/dev/pci/drm/radeon/si.c
3954
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/si.c
3955
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/si.c
3969
u32 tmp, i;
sys/dev/pci/drm/radeon/si.c
3971
tmp = RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/pci/drm/radeon/si.c
3972
tmp |= SPLL_BYPASS_EN;
sys/dev/pci/drm/radeon/si.c
3973
WREG32(CG_SPLL_FUNC_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
3975
tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
sys/dev/pci/drm/radeon/si.c
3976
tmp |= SPLL_CTLREQ_CHG;
sys/dev/pci/drm/radeon/si.c
3977
WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
sys/dev/pci/drm/radeon/si.c
3985
tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
sys/dev/pci/drm/radeon/si.c
3986
tmp &= ~(SPLL_CTLREQ_CHG | SCLK_MUX_UPDATE);
sys/dev/pci/drm/radeon/si.c
3987
WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
sys/dev/pci/drm/radeon/si.c
3989
tmp = RREG32(MPLL_CNTL_MODE);
sys/dev/pci/drm/radeon/si.c
3990
tmp &= ~MPLL_MCLK_SEL;
sys/dev/pci/drm/radeon/si.c
3991
WREG32(MPLL_CNTL_MODE, tmp);
sys/dev/pci/drm/radeon/si.c
3996
u32 tmp;
sys/dev/pci/drm/radeon/si.c
3998
tmp = RREG32(SPLL_CNTL_MODE);
sys/dev/pci/drm/radeon/si.c
3999
tmp |= SPLL_SW_DIR_CONTROL;
sys/dev/pci/drm/radeon/si.c
4000
WREG32(SPLL_CNTL_MODE, tmp);
sys/dev/pci/drm/radeon/si.c
4002
tmp = RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/pci/drm/radeon/si.c
4003
tmp |= SPLL_RESET;
sys/dev/pci/drm/radeon/si.c
4004
WREG32(CG_SPLL_FUNC_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
4006
tmp = RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/pci/drm/radeon/si.c
4007
tmp |= SPLL_SLEEP;
sys/dev/pci/drm/radeon/si.c
4008
WREG32(CG_SPLL_FUNC_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
4010
tmp = RREG32(SPLL_CNTL_MODE);
sys/dev/pci/drm/radeon/si.c
4011
tmp &= ~SPLL_SW_DIR_CONTROL;
sys/dev/pci/drm/radeon/si.c
4012
WREG32(SPLL_CNTL_MODE, tmp);
sys/dev/pci/drm/radeon/si.c
4018
u32 tmp, i;
sys/dev/pci/drm/radeon/si.c
4031
tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/si.c
4032
tmp &= ~DMA_RB_ENABLE;
sys/dev/pci/drm/radeon/si.c
4033
WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/si.c
4035
tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
sys/dev/pci/drm/radeon/si.c
4036
tmp &= ~DMA_RB_ENABLE;
sys/dev/pci/drm/radeon/si.c
4037
WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/si.c
4124
u32 tmp;
sys/dev/pci/drm/radeon/si.c
4151
tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
sys/dev/pci/drm/radeon/si.c
4152
tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
sys/dev/pci/drm/radeon/si.c
4153
WREG32(MC_VM_FB_LOCATION, tmp);
sys/dev/pci/drm/radeon/si.c
4188
u32 tmp;
sys/dev/pci/drm/radeon/si.c
4193
tmp = RREG32(MC_ARB_RAMCFG);
sys/dev/pci/drm/radeon/si.c
4194
if (tmp & CHANSIZE_OVERRIDE) {
sys/dev/pci/drm/radeon/si.c
4196
} else if (tmp & CHANSIZE_MASK) {
sys/dev/pci/drm/radeon/si.c
4201
tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/pci/drm/radeon/si.c
4202
switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
sys/dev/pci/drm/radeon/si.c
4237
tmp = RREG32(CONFIG_MEMSIZE);
sys/dev/pci/drm/radeon/si.c
4239
if (tmp & 0xffff0000) {
sys/dev/pci/drm/radeon/si.c
4240
DRM_INFO("Probable bad vram size: 0x%08x\n", tmp);
sys/dev/pci/drm/radeon/si.c
4241
if (tmp & 0xffff)
sys/dev/pci/drm/radeon/si.c
4242
tmp &= 0xffff;
sys/dev/pci/drm/radeon/si.c
4244
rdev->mc.mc_vram_size = tmp * 1024ULL * 1024ULL;
sys/dev/pci/drm/radeon/si.c
5128
u32 tmp = RREG32(CP_INT_CNTL_RING0);
sys/dev/pci/drm/radeon/si.c
5133
tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
sys/dev/pci/drm/radeon/si.c
5135
tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
sys/dev/pci/drm/radeon/si.c
5136
WREG32(CP_INT_CNTL_RING0, tmp);
sys/dev/pci/drm/radeon/si.c
5140
tmp = RREG32(DB_DEPTH_INFO);
sys/dev/pci/drm/radeon/si.c
5154
u32 tmp, tmp2;
sys/dev/pci/drm/radeon/si.c
5156
tmp = RREG32(UVD_CGC_CTRL);
sys/dev/pci/drm/radeon/si.c
5157
tmp &= ~(CLK_OD_MASK | CG_DT_MASK);
sys/dev/pci/drm/radeon/si.c
5158
tmp |= DCM | CG_DT(1) | CLK_OD(4);
sys/dev/pci/drm/radeon/si.c
5161
tmp &= ~0x7ffff800;
sys/dev/pci/drm/radeon/si.c
5164
tmp |= 0x7ffff800;
sys/dev/pci/drm/radeon/si.c
5168
WREG32(UVD_CGC_CTRL, tmp);
sys/dev/pci/drm/radeon/si.c
5179
u32 tmp = RREG32(UVD_CGC_CTRL);
sys/dev/pci/drm/radeon/si.c
5180
tmp &= ~DCM;
sys/dev/pci/drm/radeon/si.c
5181
WREG32(UVD_CGC_CTRL, tmp);
sys/dev/pci/drm/radeon/si.c
5203
u32 tmp;
sys/dev/pci/drm/radeon/si.c
5205
tmp = RREG32(RLC_CNTL);
sys/dev/pci/drm/radeon/si.c
5206
if (tmp != rlc)
sys/dev/pci/drm/radeon/si.c
5225
u32 tmp;
sys/dev/pci/drm/radeon/si.c
5230
for (tmp = 0; tmp < 5; tmp++)
sys/dev/pci/drm/radeon/si.c
5237
u32 tmp;
sys/dev/pci/drm/radeon/si.c
5240
tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10);
sys/dev/pci/drm/radeon/si.c
5241
WREG32(RLC_TTOP_D, tmp);
sys/dev/pci/drm/radeon/si.c
5243
tmp = RREG32(RLC_PG_CNTL);
sys/dev/pci/drm/radeon/si.c
5244
tmp |= GFX_PG_ENABLE;
sys/dev/pci/drm/radeon/si.c
5245
WREG32(RLC_PG_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
5247
tmp = RREG32(RLC_AUTO_PG_CTRL);
sys/dev/pci/drm/radeon/si.c
5248
tmp |= AUTO_PG_EN;
sys/dev/pci/drm/radeon/si.c
5249
WREG32(RLC_AUTO_PG_CTRL, tmp);
sys/dev/pci/drm/radeon/si.c
5251
tmp = RREG32(RLC_AUTO_PG_CTRL);
sys/dev/pci/drm/radeon/si.c
5252
tmp &= ~AUTO_PG_EN;
sys/dev/pci/drm/radeon/si.c
5253
WREG32(RLC_AUTO_PG_CTRL, tmp);
sys/dev/pci/drm/radeon/si.c
5255
tmp = RREG32(DB_RENDER_CONTROL);
sys/dev/pci/drm/radeon/si.c
5261
u32 tmp;
sys/dev/pci/drm/radeon/si.c
5265
tmp = RREG32(RLC_PG_CNTL);
sys/dev/pci/drm/radeon/si.c
5266
tmp |= GFX_PG_SRC;
sys/dev/pci/drm/radeon/si.c
5267
WREG32(RLC_PG_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
5271
tmp = RREG32(RLC_AUTO_PG_CTRL);
sys/dev/pci/drm/radeon/si.c
5273
tmp &= ~GRBM_REG_SGIT_MASK;
sys/dev/pci/drm/radeon/si.c
5274
tmp |= GRBM_REG_SGIT(0x700);
sys/dev/pci/drm/radeon/si.c
5275
tmp &= ~PG_AFTER_GRBM_REG_ST_MASK;
sys/dev/pci/drm/radeon/si.c
5276
WREG32(RLC_AUTO_PG_CTRL, tmp);
sys/dev/pci/drm/radeon/si.c
5281
u32 mask = 0, tmp, tmp1;
sys/dev/pci/drm/radeon/si.c
5285
tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
sys/dev/pci/drm/radeon/si.c
5289
tmp &= 0xffff0000;
sys/dev/pci/drm/radeon/si.c
5291
tmp |= tmp1;
sys/dev/pci/drm/radeon/si.c
5292
tmp >>= 16;
sys/dev/pci/drm/radeon/si.c
5299
return (~tmp) & mask;
sys/dev/pci/drm/radeon/si.c
5306
u32 tmp = 0;
sys/dev/pci/drm/radeon/si.c
5323
tmp |= (cu_bitmap << (i * 16 + j * 8));
sys/dev/pci/drm/radeon/si.c
5327
WREG32(RLC_PG_AO_CU_MASK, tmp);
sys/dev/pci/drm/radeon/si.c
5329
tmp = RREG32(RLC_MAX_PG_CU);
sys/dev/pci/drm/radeon/si.c
5330
tmp &= ~MAX_PU_CU_MASK;
sys/dev/pci/drm/radeon/si.c
5331
tmp |= MAX_PU_CU(active_cu_number);
sys/dev/pci/drm/radeon/si.c
5332
WREG32(RLC_MAX_PG_CU, tmp);
sys/dev/pci/drm/radeon/si.c
5338
u32 data, orig, tmp;
sys/dev/pci/drm/radeon/si.c
5347
tmp = si_halt_rlc(rdev);
sys/dev/pci/drm/radeon/si.c
5355
si_update_rlc(rdev, tmp);
sys/dev/pci/drm/radeon/si.c
5378
u32 data, orig, tmp = 0;
sys/dev/pci/drm/radeon/si.c
5398
tmp = si_halt_rlc(rdev);
sys/dev/pci/drm/radeon/si.c
5404
si_update_rlc(rdev, tmp);
sys/dev/pci/drm/radeon/si.c
5421
tmp = si_halt_rlc(rdev);
sys/dev/pci/drm/radeon/si.c
5427
si_update_rlc(rdev, tmp);
sys/dev/pci/drm/radeon/si.c
5434
u32 orig, data, tmp;
sys/dev/pci/drm/radeon/si.c
5437
tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
sys/dev/pci/drm/radeon/si.c
5438
tmp |= 0x3fff;
sys/dev/pci/drm/radeon/si.c
5439
WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, tmp);
sys/dev/pci/drm/radeon/si.c
5449
tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
sys/dev/pci/drm/radeon/si.c
5450
tmp &= ~0x3fff;
sys/dev/pci/drm/radeon/si.c
5451
WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, tmp);
sys/dev/pci/drm/radeon/si.c
5789
u32 tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/pci/drm/radeon/si.c
5791
tmp |= SOFT_RESET_RLC;
sys/dev/pci/drm/radeon/si.c
5792
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/si.c
5794
tmp &= ~SOFT_RESET_RLC;
sys/dev/pci/drm/radeon/si.c
5795
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/pci/drm/radeon/si.c
5819
u32 tmp;
sys/dev/pci/drm/radeon/si.c
5822
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/pci/drm/radeon/si.c
5823
if ((tmp & 0xF0000000) == 0xB0000000)
sys/dev/pci/drm/radeon/si.c
5830
u32 tmp;
sys/dev/pci/drm/radeon/si.c
5832
tmp = RREG32(RLC_LB_CNTL);
sys/dev/pci/drm/radeon/si.c
5834
tmp |= LOAD_BALANCE_ENABLE;
sys/dev/pci/drm/radeon/si.c
5836
tmp &= ~LOAD_BALANCE_ENABLE;
sys/dev/pci/drm/radeon/si.c
5837
WREG32(RLC_LB_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
5931
u32 tmp;
sys/dev/pci/drm/radeon/si.c
5933
tmp = RREG32(CP_INT_CNTL_RING0) &
sys/dev/pci/drm/radeon/si.c
5935
WREG32(CP_INT_CNTL_RING0, tmp);
sys/dev/pci/drm/radeon/si.c
5938
tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
sys/dev/pci/drm/radeon/si.c
5939
WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/si.c
5940
tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
sys/dev/pci/drm/radeon/si.c
5941
WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
sys/dev/pci/drm/radeon/si.c
6192
u32 wptr, tmp;
sys/dev/pci/drm/radeon/si.c
6208
tmp = RREG32(IH_RB_CNTL);
sys/dev/pci/drm/radeon/si.c
6209
tmp |= IH_WPTR_OVERFLOW_CLEAR;
sys/dev/pci/drm/radeon/si.c
6210
WREG32(IH_RB_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
7119
u32 max_lw, current_lw, tmp;
sys/dev/pci/drm/radeon/si.c
7124
tmp = RREG32_PCIE(PCIE_LC_STATUS1);
sys/dev/pci/drm/radeon/si.c
7125
max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
sys/dev/pci/drm/radeon/si.c
7126
current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
sys/dev/pci/drm/radeon/si.c
7129
tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
sys/dev/pci/drm/radeon/si.c
7130
if (tmp & LC_RENEGOTIATION_SUPPORT) {
sys/dev/pci/drm/radeon/si.c
7131
tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
sys/dev/pci/drm/radeon/si.c
7132
tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
sys/dev/pci/drm/radeon/si.c
7133
tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
sys/dev/pci/drm/radeon/si.c
7134
WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
sys/dev/pci/drm/radeon/si.c
7158
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
sys/dev/pci/drm/radeon/si.c
7159
tmp |= LC_SET_QUIESCE;
sys/dev/pci/drm/radeon/si.c
7160
WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
sys/dev/pci/drm/radeon/si.c
7162
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
sys/dev/pci/drm/radeon/si.c
7163
tmp |= LC_REDO_EQ;
sys/dev/pci/drm/radeon/si.c
7164
WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
sys/dev/pci/drm/radeon/si.c
7192
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
sys/dev/pci/drm/radeon/si.c
7193
tmp &= ~LC_SET_QUIESCE;
sys/dev/pci/drm/radeon/si.c
7194
WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
sys/dev/pci/drm/radeon/si_dpm.c
1711
s64 tmp;
sys/dev/pci/drm/radeon/si_dpm.c
1723
tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
sys/dev/pci/drm/radeon/si_dpm.c
1724
kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
sys/dev/pci/drm/radeon/si_dpm.c
1725
kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
sys/dev/pci/drm/radeon/si_dpm.c
2791
u32 tmp;
sys/dev/pci/drm/radeon/si_dpm.c
2827
tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
sys/dev/pci/drm/radeon/si_dpm.c
2829
spll_table->freq[i] = cpu_to_be32(tmp);
sys/dev/pci/drm/radeon/si_dpm.c
2831
tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
sys/dev/pci/drm/radeon/si_dpm.c
2833
spll_table->ss[i] = cpu_to_be32(tmp);
sys/dev/pci/drm/radeon/si_dpm.c
3151
u32 tmp, width, row, column, bank, density;
sys/dev/pci/drm/radeon/si_dpm.c
3154
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/pci/drm/radeon/si_dpm.c
3155
is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
sys/dev/pci/drm/radeon/si_dpm.c
3156
is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
sys/dev/pci/drm/radeon/si_dpm.c
3157
& (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
sys/dev/pci/drm/radeon/si_dpm.c
3162
tmp = RREG32(MC_ARB_RAMCFG);
sys/dev/pci/drm/radeon/si_dpm.c
3163
row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
sys/dev/pci/drm/radeon/si_dpm.c
3164
column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
sys/dev/pci/drm/radeon/si_dpm.c
3165
bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
sys/dev/pci/drm/radeon/si_dpm.c
3424
u32 tmp;
sys/dev/pci/drm/radeon/si_dpm.c
3430
&tmp, si_pi->sram_end);
sys/dev/pci/drm/radeon/si_dpm.c
3434
si_pi->state_table_start = tmp;
sys/dev/pci/drm/radeon/si_dpm.c
3439
&tmp, si_pi->sram_end);
sys/dev/pci/drm/radeon/si_dpm.c
3443
si_pi->soft_regs_start = tmp;
sys/dev/pci/drm/radeon/si_dpm.c
3448
&tmp, si_pi->sram_end);
sys/dev/pci/drm/radeon/si_dpm.c
3452
si_pi->mc_reg_table_start = tmp;
sys/dev/pci/drm/radeon/si_dpm.c
3457
&tmp, si_pi->sram_end);
sys/dev/pci/drm/radeon/si_dpm.c
3461
si_pi->fan_table_start = tmp;
sys/dev/pci/drm/radeon/si_dpm.c
3466
&tmp, si_pi->sram_end);
sys/dev/pci/drm/radeon/si_dpm.c
3470
si_pi->arb_table_start = tmp;
sys/dev/pci/drm/radeon/si_dpm.c
3475
&tmp, si_pi->sram_end);
sys/dev/pci/drm/radeon/si_dpm.c
3479
si_pi->cac_table_start = tmp;
sys/dev/pci/drm/radeon/si_dpm.c
3484
&tmp, si_pi->sram_end);
sys/dev/pci/drm/radeon/si_dpm.c
3488
si_pi->dte_table_start = tmp;
sys/dev/pci/drm/radeon/si_dpm.c
3493
&tmp, si_pi->sram_end);
sys/dev/pci/drm/radeon/si_dpm.c
3497
si_pi->spll_table_start = tmp;
sys/dev/pci/drm/radeon/si_dpm.c
3502
&tmp, si_pi->sram_end);
sys/dev/pci/drm/radeon/si_dpm.c
3506
si_pi->papm_cfg_table_start = tmp;
sys/dev/pci/drm/radeon/si_dpm.c
3615
u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
sys/dev/pci/drm/radeon/si_dpm.c
3618
WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
sys/dev/pci/drm/radeon/si_dpm.c
3626
u32 tmp, pipe;
sys/dev/pci/drm/radeon/si_dpm.c
3629
tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
sys/dev/pci/drm/radeon/si_dpm.c
3631
tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
sys/dev/pci/drm/radeon/si_dpm.c
3633
tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/pci/drm/radeon/si_dpm.c
3636
tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
sys/dev/pci/drm/radeon/si_dpm.c
3638
tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/pci/drm/radeon/si_dpm.c
3640
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/pci/drm/radeon/si_dpm.c
3642
tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
sys/dev/pci/drm/radeon/si_dpm.c
3643
pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
sys/dev/pci/drm/radeon/si_dpm.c
3657
tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
3658
tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
sys/dev/pci/drm/radeon/si_dpm.c
3659
WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
sys/dev/pci/drm/radeon/si_dpm.c
3743
u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
sys/dev/pci/drm/radeon/si_dpm.c
3745
tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
sys/dev/pci/drm/radeon/si_dpm.c
3746
tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
sys/dev/pci/drm/radeon/si_dpm.c
3749
tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
sys/dev/pci/drm/radeon/si_dpm.c
3750
tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
sys/dev/pci/drm/radeon/si_dpm.c
3752
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/pci/drm/radeon/si_dpm.c
4173
u32 tmp;
sys/dev/pci/drm/radeon/si_dpm.c
4176
ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
sys/dev/pci/drm/radeon/si_dpm.c
4180
tmp &= 0x00FFFFFF;
sys/dev/pci/drm/radeon/si_dpm.c
4181
tmp |= MC_CG_ARB_FREQ_F1 << 24;
sys/dev/pci/drm/radeon/si_dpm.c
4183
return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end);
sys/dev/pci/drm/radeon/si_dpm.c
4200
u32 tmp;
sys/dev/pci/drm/radeon/si_dpm.c
4204
&tmp, si_pi->sram_end);
sys/dev/pci/drm/radeon/si_dpm.c
4208
tmp = (tmp >> 24) & 0xff;
sys/dev/pci/drm/radeon/si_dpm.c
4210
if (tmp == MC_CG_ARB_FREQ_F0)
sys/dev/pci/drm/radeon/si_dpm.c
4213
return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
sys/dev/pci/drm/radeon/si_dpm.c
4222
u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
sys/dev/pci/drm/radeon/si_dpm.c
4224
if (tmp >= 4)
sys/dev/pci/drm/radeon/si_dpm.c
4227
dram_rows = 1 << (tmp + 10);
sys/dev/pci/drm/radeon/si_dpm.c
4739
u64 tmp;
sys/dev/pci/drm/radeon/si_dpm.c
4752
tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
sys/dev/pci/drm/radeon/si_dpm.c
4753
do_div(tmp, reference_clock);
sys/dev/pci/drm/radeon/si_dpm.c
4754
fbdiv = (u32) tmp;
sys/dev/pci/drm/radeon/si_dpm.c
4861
u32 tmp;
sys/dev/pci/drm/radeon/si_dpm.c
4869
tmp = freq_nom / reference_clock;
sys/dev/pci/drm/radeon/si_dpm.c
4870
tmp = tmp * tmp;
sys/dev/pci/drm/radeon/si_dpm.c
4874
u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
sys/dev/pci/drm/radeon/si_dpm.c
5954
u32 tmp;
sys/dev/pci/drm/radeon/si_dpm.c
5957
tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
sys/dev/pci/drm/radeon/si_dpm.c
5958
si_pi->fan_ctrl_default_mode = tmp;
sys/dev/pci/drm/radeon/si_dpm.c
5959
tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
sys/dev/pci/drm/radeon/si_dpm.c
5960
si_pi->t_min = tmp;
sys/dev/pci/drm/radeon/si_dpm.c
5964
tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
5965
tmp |= TMIN(0);
sys/dev/pci/drm/radeon/si_dpm.c
5966
WREG32(CG_FDO_CTRL2, tmp);
sys/dev/pci/drm/radeon/si_dpm.c
5968
tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
5969
tmp |= FDO_PWM_MODE(mode);
sys/dev/pci/drm/radeon/si_dpm.c
5970
WREG32(CG_FDO_CTRL2, tmp);
sys/dev/pci/drm/radeon/si_dpm.c
5980
u32 reference_clock, tmp;
sys/dev/pci/drm/radeon/si_dpm.c
6033
tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
sys/dev/pci/drm/radeon/si_dpm.c
6034
fan_table.temp_src = (uint8_t)tmp;
sys/dev/pci/drm/radeon/si_dpm.c
6108
u32 tmp;
sys/dev/pci/drm/radeon/si_dpm.c
6130
tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
6131
tmp |= FDO_STATIC_DUTY(duty);
sys/dev/pci/drm/radeon/si_dpm.c
6132
WREG32(CG_FDO_CTRL0, tmp);
sys/dev/pci/drm/radeon/si_dpm.c
6156
u32 tmp;
sys/dev/pci/drm/radeon/si_dpm.c
6161
tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
6162
return (tmp >> FDO_PWM_MODE_SHIFT);
sys/dev/pci/drm/radeon/si_dpm.c
6190
u32 tach_period, tmp;
sys/dev/pci/drm/radeon/si_dpm.c
6207
tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
6208
tmp |= TARGET_PERIOD(tach_period);
sys/dev/pci/drm/radeon/si_dpm.c
6209
WREG32(CG_TACH_CTRL, tmp);
sys/dev/pci/drm/radeon/si_dpm.c
6220
u32 tmp;
sys/dev/pci/drm/radeon/si_dpm.c
6223
tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
6224
tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
sys/dev/pci/drm/radeon/si_dpm.c
6225
WREG32(CG_FDO_CTRL2, tmp);
sys/dev/pci/drm/radeon/si_dpm.c
6227
tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
6228
tmp |= TMIN(si_pi->t_min);
sys/dev/pci/drm/radeon/si_dpm.c
6229
WREG32(CG_FDO_CTRL2, tmp);
sys/dev/pci/drm/radeon/si_dpm.c
6244
u32 tmp;
sys/dev/pci/drm/radeon/si_dpm.c
6247
tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
6248
tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
sys/dev/pci/drm/radeon/si_dpm.c
6249
WREG32(CG_TACH_CTRL, tmp);
sys/dev/pci/drm/radeon/si_dpm.c
6252
tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
6253
tmp |= TACH_PWM_RESP_RATE(0x28);
sys/dev/pci/drm/radeon/si_dpm.c
6254
WREG32(CG_FDO_CTRL2, tmp);
sys/dev/pci/drm/radeon/si_smc.c
115
u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
sys/dev/pci/drm/radeon/si_smc.c
117
tmp &= ~RST_REG;
sys/dev/pci/drm/radeon/si_smc.c
119
WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
sys/dev/pci/drm/radeon/si_smc.c
124
u32 tmp;
sys/dev/pci/drm/radeon/si_smc.c
131
tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
sys/dev/pci/drm/radeon/si_smc.c
132
tmp |= RST_REG;
sys/dev/pci/drm/radeon/si_smc.c
133
WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
sys/dev/pci/drm/radeon/si_smc.c
145
u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
sys/dev/pci/drm/radeon/si_smc.c
147
tmp |= CK_DISABLE;
sys/dev/pci/drm/radeon/si_smc.c
149
WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
sys/dev/pci/drm/radeon/si_smc.c
154
u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
sys/dev/pci/drm/radeon/si_smc.c
156
tmp &= ~CK_DISABLE;
sys/dev/pci/drm/radeon/si_smc.c
158
WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
sys/dev/pci/drm/radeon/si_smc.c
174
u32 tmp;
sys/dev/pci/drm/radeon/si_smc.c
183
tmp = RREG32(SMC_RESP_0);
sys/dev/pci/drm/radeon/si_smc.c
184
if (tmp != 0)
sys/dev/pci/drm/radeon/si_smc.c
188
tmp = RREG32(SMC_RESP_0);
sys/dev/pci/drm/radeon/si_smc.c
190
return (PPSMC_Result)tmp;
sys/dev/pci/drm/radeon/si_smc.c
195
u32 tmp;
sys/dev/pci/drm/radeon/si_smc.c
202
tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
sys/dev/pci/drm/radeon/si_smc.c
203
if ((tmp & CKEN) == 0)
sys/dev/pci/drm/radeon/trinity_dpm.c
891
u32 tmp = RREG32(CG_MISC_REG);
sys/dev/pci/drm/radeon/trinity_dpm.c
892
tmp &= 0xfffffffd;
sys/dev/pci/drm/radeon/trinity_dpm.c
893
WREG32(CG_MISC_REG, tmp);
sys/dev/pci/drm/radeon/uvd_v1_0.c
160
uint32_t tmp;
sys/dev/pci/drm/radeon/uvd_v1_0.c
186
tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
sys/dev/pci/drm/radeon/uvd_v1_0.c
187
radeon_ring_write(ring, tmp);
sys/dev/pci/drm/radeon/uvd_v1_0.c
190
tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
sys/dev/pci/drm/radeon/uvd_v1_0.c
191
radeon_ring_write(ring, tmp);
sys/dev/pci/drm/radeon/uvd_v1_0.c
194
tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
sys/dev/pci/drm/radeon/uvd_v1_0.c
195
radeon_ring_write(ring, tmp);
sys/dev/pci/drm/radeon/uvd_v1_0.c
423
uint32_t tmp = 0;
sys/dev/pci/drm/radeon/uvd_v1_0.c
438
tmp = RREG32(UVD_CONTEXT_ID);
sys/dev/pci/drm/radeon/uvd_v1_0.c
439
if (tmp == 0xDEADBEEF)
sys/dev/pci/drm/radeon/uvd_v1_0.c
449
ring->idx, tmp);
sys/dev/pci/drm/radeon/vce_v1_0.c
105
u32 tmp;
sys/dev/pci/drm/radeon/vce_v1_0.c
108
tmp = RREG32(VCE_CLOCK_GATING_A);
sys/dev/pci/drm/radeon/vce_v1_0.c
109
tmp |= CGC_DYN_CLOCK_MODE;
sys/dev/pci/drm/radeon/vce_v1_0.c
110
WREG32(VCE_CLOCK_GATING_A, tmp);
sys/dev/pci/drm/radeon/vce_v1_0.c
112
tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/pci/drm/radeon/vce_v1_0.c
113
tmp &= ~0x1ff000;
sys/dev/pci/drm/radeon/vce_v1_0.c
114
tmp |= 0xff800000;
sys/dev/pci/drm/radeon/vce_v1_0.c
115
WREG32(VCE_UENC_CLOCK_GATING, tmp);
sys/dev/pci/drm/radeon/vce_v1_0.c
117
tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
sys/dev/pci/drm/radeon/vce_v1_0.c
118
tmp &= ~0x3ff;
sys/dev/pci/drm/radeon/vce_v1_0.c
119
WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
sys/dev/pci/drm/radeon/vce_v1_0.c
121
tmp = RREG32(VCE_CLOCK_GATING_A);
sys/dev/pci/drm/radeon/vce_v1_0.c
122
tmp &= ~CGC_DYN_CLOCK_MODE;
sys/dev/pci/drm/radeon/vce_v1_0.c
123
WREG32(VCE_CLOCK_GATING_A, tmp);
sys/dev/pci/drm/radeon/vce_v1_0.c
125
tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/pci/drm/radeon/vce_v1_0.c
126
tmp |= 0x1ff000;
sys/dev/pci/drm/radeon/vce_v1_0.c
127
tmp &= ~0xff800000;
sys/dev/pci/drm/radeon/vce_v1_0.c
128
WREG32(VCE_UENC_CLOCK_GATING, tmp);
sys/dev/pci/drm/radeon/vce_v1_0.c
130
tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
sys/dev/pci/drm/radeon/vce_v1_0.c
131
tmp |= 0x3ff;
sys/dev/pci/drm/radeon/vce_v1_0.c
132
WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
sys/dev/pci/drm/radeon/vce_v1_0.c
138
u32 tmp;
sys/dev/pci/drm/radeon/vce_v1_0.c
140
tmp = RREG32(VCE_CLOCK_GATING_A);
sys/dev/pci/drm/radeon/vce_v1_0.c
141
tmp |= CGC_DYN_CLOCK_MODE;
sys/dev/pci/drm/radeon/vce_v1_0.c
142
WREG32(VCE_CLOCK_GATING_A, tmp);
sys/dev/pci/drm/radeon/vce_v1_0.c
144
tmp = RREG32(VCE_CLOCK_GATING_B);
sys/dev/pci/drm/radeon/vce_v1_0.c
145
tmp |= 0x1e;
sys/dev/pci/drm/radeon/vce_v1_0.c
146
tmp &= ~0xe100e1;
sys/dev/pci/drm/radeon/vce_v1_0.c
147
WREG32(VCE_CLOCK_GATING_B, tmp);
sys/dev/pci/drm/radeon/vce_v1_0.c
149
tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/pci/drm/radeon/vce_v1_0.c
150
tmp &= ~0xff9ff000;
sys/dev/pci/drm/radeon/vce_v1_0.c
151
WREG32(VCE_UENC_CLOCK_GATING, tmp);
sys/dev/pci/drm/radeon/vce_v1_0.c
153
tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
sys/dev/pci/drm/radeon/vce_v1_0.c
154
tmp &= ~0x3ff;
sys/dev/pci/drm/radeon/vce_v1_0.c
155
WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
sys/dev/pci/drm/radeon/vce_v2_0.c
133
u32 tmp;
sys/dev/pci/drm/radeon/vce_v2_0.c
135
tmp = RREG32(VCE_CLOCK_GATING_A);
sys/dev/pci/drm/radeon/vce_v2_0.c
136
tmp &= ~(CGC_CLK_GATE_DLY_TIMER_MASK | CGC_CLK_GATER_OFF_DLY_TIMER_MASK);
sys/dev/pci/drm/radeon/vce_v2_0.c
137
tmp |= (CGC_CLK_GATE_DLY_TIMER(0) | CGC_CLK_GATER_OFF_DLY_TIMER(4));
sys/dev/pci/drm/radeon/vce_v2_0.c
138
tmp |= CGC_UENC_WAIT_AWAKE;
sys/dev/pci/drm/radeon/vce_v2_0.c
139
WREG32(VCE_CLOCK_GATING_A, tmp);
sys/dev/pci/drm/radeon/vce_v2_0.c
141
tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/pci/drm/radeon/vce_v2_0.c
142
tmp &= ~(CLOCK_ON_DELAY_MASK | CLOCK_OFF_DELAY_MASK);
sys/dev/pci/drm/radeon/vce_v2_0.c
143
tmp |= (CLOCK_ON_DELAY(0) | CLOCK_OFF_DELAY(4));
sys/dev/pci/drm/radeon/vce_v2_0.c
144
WREG32(VCE_UENC_CLOCK_GATING, tmp);
sys/dev/pci/drm/radeon/vce_v2_0.c
146
tmp = RREG32(VCE_CLOCK_GATING_B);
sys/dev/pci/drm/radeon/vce_v2_0.c
147
tmp |= 0x10;
sys/dev/pci/drm/radeon/vce_v2_0.c
148
tmp &= ~0x100000;
sys/dev/pci/drm/radeon/vce_v2_0.c
149
WREG32(VCE_CLOCK_GATING_B, tmp);
sys/dev/pci/drm/radeon/vce_v2_0.c
41
u32 tmp;
sys/dev/pci/drm/radeon/vce_v2_0.c
44
tmp = RREG32(VCE_CLOCK_GATING_B);
sys/dev/pci/drm/radeon/vce_v2_0.c
45
tmp |= 0xe70000;
sys/dev/pci/drm/radeon/vce_v2_0.c
46
WREG32(VCE_CLOCK_GATING_B, tmp);
sys/dev/pci/drm/radeon/vce_v2_0.c
48
tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/pci/drm/radeon/vce_v2_0.c
49
tmp |= 0xff000000;
sys/dev/pci/drm/radeon/vce_v2_0.c
50
WREG32(VCE_UENC_CLOCK_GATING, tmp);
sys/dev/pci/drm/radeon/vce_v2_0.c
52
tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
sys/dev/pci/drm/radeon/vce_v2_0.c
53
tmp &= ~0x3fc;
sys/dev/pci/drm/radeon/vce_v2_0.c
54
WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
sys/dev/pci/drm/radeon/vce_v2_0.c
58
tmp = RREG32(VCE_CLOCK_GATING_B);
sys/dev/pci/drm/radeon/vce_v2_0.c
59
tmp |= 0xe7;
sys/dev/pci/drm/radeon/vce_v2_0.c
60
tmp &= ~0xe70000;
sys/dev/pci/drm/radeon/vce_v2_0.c
61
WREG32(VCE_CLOCK_GATING_B, tmp);
sys/dev/pci/drm/radeon/vce_v2_0.c
63
tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/pci/drm/radeon/vce_v2_0.c
64
tmp |= 0x1fe000;
sys/dev/pci/drm/radeon/vce_v2_0.c
65
tmp &= ~0xff000000;
sys/dev/pci/drm/radeon/vce_v2_0.c
66
WREG32(VCE_UENC_CLOCK_GATING, tmp);
sys/dev/pci/drm/radeon/vce_v2_0.c
68
tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
sys/dev/pci/drm/radeon/vce_v2_0.c
69
tmp |= 0x3fc;
sys/dev/pci/drm/radeon/vce_v2_0.c
70
WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
sys/dev/pci/drm/radeon/vce_v2_0.c
76
u32 orig, tmp;
sys/dev/pci/drm/radeon/vce_v2_0.c
78
tmp = RREG32(VCE_CLOCK_GATING_B);
sys/dev/pci/drm/radeon/vce_v2_0.c
79
tmp &= ~0x00060006;
sys/dev/pci/drm/radeon/vce_v2_0.c
81
tmp |= 0xe10000;
sys/dev/pci/drm/radeon/vce_v2_0.c
83
tmp |= 0xe1;
sys/dev/pci/drm/radeon/vce_v2_0.c
84
tmp &= ~0xe10000;
sys/dev/pci/drm/radeon/vce_v2_0.c
86
WREG32(VCE_CLOCK_GATING_B, tmp);
sys/dev/pci/drm/radeon/vce_v2_0.c
88
orig = tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/pci/drm/radeon/vce_v2_0.c
89
tmp &= ~0x1fe000;
sys/dev/pci/drm/radeon/vce_v2_0.c
90
tmp &= ~0xff000000;
sys/dev/pci/drm/radeon/vce_v2_0.c
91
if (tmp != orig)
sys/dev/pci/drm/radeon/vce_v2_0.c
92
WREG32(VCE_UENC_CLOCK_GATING, tmp);
sys/dev/pci/drm/radeon/vce_v2_0.c
94
orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
sys/dev/pci/drm/radeon/vce_v2_0.c
95
tmp &= ~0x3fc;
sys/dev/pci/drm/radeon/vce_v2_0.c
96
if (tmp != orig)
sys/dev/pci/drm/radeon/vce_v2_0.c
97
WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
sys/dev/pci/drm/scheduler/sched_main.c
1396
struct drm_sched_job *job, *tmp;
sys/dev/pci/drm/scheduler/sched_main.c
1399
list_for_each_entry_safe_reverse(job, tmp, &sched->pending_list, list) {
sys/dev/pci/drm/scheduler/sched_main.c
1490
struct drm_sched_entity *tmp;
sys/dev/pci/drm/scheduler/sched_main.c
1505
list_for_each_entry_safe(entity, tmp, &rq->entities, list) {
sys/dev/pci/drm/scheduler/sched_main.c
608
struct drm_sched_job *s_job, *tmp;
sys/dev/pci/drm/scheduler/sched_main.c
633
list_for_each_entry_safe_reverse(s_job, tmp, &sched->pending_list,
sys/dev/pci/drm/scheduler/sched_main.c
697
struct drm_sched_job *s_job, *tmp;
sys/dev/pci/drm/scheduler/sched_main.c
704
list_for_each_entry_safe(s_job, tmp, &sched->pending_list, list) {
sys/dev/pci/drm/scheduler/sched_main.c
743
struct drm_sched_job *s_job, *tmp;
sys/dev/pci/drm/scheduler/sched_main.c
748
list_for_each_entry_safe(s_job, tmp, &sched->pending_list, list) {
sys/dev/pci/drm/ttm/ttm_bo_util.c
298
pgprot_t tmp)
sys/dev/pci/drm/ttm/ttm_bo_util.c
307
tmp = pgprot_decrypted(tmp);
sys/dev/pci/drm/ttm/ttm_bo_util.c
312
return ttm_prot_from_caching(caching, tmp);
sys/dev/pci/drm/ttm/ttm_module.c
62
pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp)
sys/dev/pci/drm/ttm/ttm_module.c
66
return tmp;
sys/dev/pci/drm/ttm/ttm_module.c
70
tmp = pgprot_writecombine(tmp);
sys/dev/pci/drm/ttm/ttm_module.c
73
tmp = pgprot_noncached(tmp);
sys/dev/pci/drm/ttm/ttm_module.c
79
tmp = pgprot_writecombine(tmp);
sys/dev/pci/drm/ttm/ttm_module.c
81
tmp = pgprot_noncached(tmp);
sys/dev/pci/drm/ttm/ttm_module.c
84
tmp = pgprot_noncached(tmp);
sys/dev/pci/drm/ttm/ttm_module.c
86
return tmp;
sys/dev/pci/emuxki.c
826
u_int32_t tmp;
sys/dev/pci/emuxki.c
829
tmp = emuxki_read(sc, 0, EMU_A_SPDIF_SAMPLERATE) & 0xfffff1ff;
sys/dev/pci/emuxki.c
830
emuxki_write(sc, 0, EMU_A_SPDIF_SAMPLERATE, tmp | 0x400);
sys/dev/pci/emuxki.c
846
tmp = bus_space_read_4(sc->sc_iot, sc->sc_ioh, EMU_A_IOCFG) & ~0x8; /* Clear bit 3 */
sys/dev/pci/emuxki.c
847
bus_space_write_4(sc->sc_iot, sc->sc_ioh, EMU_A_IOCFG, tmp);
sys/dev/pci/eso.c
1867
uint8_t mixreg, tmp;
sys/dev/pci/eso.c
1914
tmp = eso_read_mixreg(sc, ESO_MIXREG_PCSVR);
sys/dev/pci/eso.c
1915
tmp &= ESO_MIXREG_PCSVR_RESV;
sys/dev/pci/eso.c
1917
tmp |= (sc->sc_gain[port][ESO_LEFT] >> 5);
sys/dev/pci/eso.c
1918
eso_write_mixreg(sc, ESO_MIXREG_PCSVR, tmp);
sys/dev/pci/eso.c
1958
uint8_t tmp;
sys/dev/pci/eso.c
1964
tmp = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ESO_IO_IRQCTL);
sys/dev/pci/eso.c
1965
tmp &= ~(ESO_IO_IRQCTL_MASK);
sys/dev/pci/eso.c
1966
bus_space_write_1(sc->sc_iot, sc->sc_ioh, ESO_IO_IRQCTL, tmp);
sys/dev/pci/eso.c
304
uint8_t a2mode, tmp;
sys/dev/pci/eso.c
329
tmp = eso_read_mixreg(sc, ESO_MIXREG_MVCTL);
sys/dev/pci/eso.c
330
tmp &= ~ESO_MIXREG_MVCTL_SPLIT;
sys/dev/pci/eso.c
331
tmp |= ESO_MIXREG_MVCTL_HVIRQM;
sys/dev/pci/eso.c
332
eso_write_mixreg(sc, ESO_MIXREG_MVCTL, tmp);
sys/dev/pci/eso.c
377
tmp = eso_read_ctlreg(sc, ESO_CTLREG_ACTL);
sys/dev/pci/eso.c
379
tmp |= ESO_CTLREG_ACTL_RECMON;
sys/dev/pci/eso.c
381
tmp &= ~ESO_CTLREG_ACTL_RECMON;
sys/dev/pci/eso.c
382
eso_write_ctlreg(sc, ESO_CTLREG_ACTL, tmp);
sys/dev/pci/eso.c
385
tmp = eso_read_mixreg(sc, ESO_MIXREG_SPAT);
sys/dev/pci/eso.c
387
tmp |= ESO_MIXREG_SPAT_ENB;
sys/dev/pci/eso.c
389
tmp &= ~ESO_MIXREG_SPAT_ENB;
sys/dev/pci/eso.c
391
tmp | ESO_MIXREG_SPAT_RSTREL);
sys/dev/pci/eso.c
795
uint8_t tmp;
sys/dev/pci/eso.c
909
tmp = eso_read_mixreg(sc, ESO_MIXREG_SPAT);
sys/dev/pci/eso.c
911
tmp |= ESO_MIXREG_SPAT_ENB;
sys/dev/pci/eso.c
913
tmp &= ~ESO_MIXREG_SPAT_ENB;
sys/dev/pci/eso.c
915
tmp | ESO_MIXREG_SPAT_RSTREL);
sys/dev/pci/eso.c
961
tmp = eso_read_ctlreg(sc, ESO_CTLREG_ACTL);
sys/dev/pci/eso.c
963
tmp |= ESO_CTLREG_ACTL_RECMON;
sys/dev/pci/eso.c
965
tmp &= ~ESO_CTLREG_ACTL_RECMON;
sys/dev/pci/eso.c
966
eso_write_ctlreg(sc, ESO_CTLREG_ACTL, tmp);
sys/dev/pci/if_bge.c
1754
u_int32_t tmp;
sys/dev/pci/if_bge.c
1757
tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
sys/dev/pci/if_bge.c
1758
if (tmp == 6 || tmp == 7)
sys/dev/pci/if_bwfm_pci.c
2554
struct bwfm_pci_ioctl *ctl, *tmp;
sys/dev/pci/if_bwfm_pci.c
2560
TAILQ_FOREACH_SAFE(ctl, &sc->sc_ioctlq, next, tmp) {
sys/dev/pci/if_de.c
3657
u_int32_t tmp = csr & sc->tulip_intrmask
sys/dev/pci/if_de.c
3672
sc->tulip_statusbits |= tmp;
sys/dev/pci/if_de.c
3674
tulip_print_abnormal_interrupt(sc, tmp);
sys/dev/pci/if_ice.c
11440
struct ice_fltr_list_entry *tmp;
sys/dev/pci/if_ice.c
11445
tmp = (struct ice_fltr_list_entry *)ice_malloc(hw, sizeof(*tmp));
sys/dev/pci/if_ice.c
11446
if (!tmp)
sys/dev/pci/if_ice.c
11449
tmp->fltr_info = *fi;
sys/dev/pci/if_ice.c
11456
tmp->fltr_info.fltr_act = ICE_FWD_TO_VSI;
sys/dev/pci/if_ice.c
11457
tmp->fltr_info.vsi_handle = vsi_handle;
sys/dev/pci/if_ice.c
11458
tmp->fltr_info.fwd_id.hw_vsi_id = hw->vsi_ctx[vsi_handle]->vsi_num;
sys/dev/pci/if_ice.c
11460
TAILQ_INSERT_HEAD(vsi_list_head, tmp, list_entry);
sys/dev/pci/if_ice.c
11726
struct ice_fltr_list_entry *v_list_itr, *tmp;
sys/dev/pci/if_ice.c
11730
TAILQ_FOREACH_SAFE(v_list_itr, v_list, list_entry, tmp) {
sys/dev/pci/if_ice.c
11752
struct ice_fltr_list_entry *fm_entry, *tmp;
sys/dev/pci/if_ice.c
11815
TAILQ_FOREACH_SAFE(fm_entry, &remove_list_head, list_entry, tmp) {
sys/dev/pci/if_ice.c
13194
struct ice_fltr_list_entry *list_itr, *tmp;
sys/dev/pci/if_ice.c
13201
TAILQ_FOREACH_SAFE(list_itr, m_list, list_entry, tmp) {
sys/dev/pci/if_ice.c
17285
struct ice_vsig_vsi *tmp;
sys/dev/pci/if_ice.c
17324
tmp = hw->blk[blk].xlt2.vsig_tbl[idx].first_vsi;
sys/dev/pci/if_ice.c
17327
hw->blk[blk].xlt2.vsis[vsi].next_vsi = tmp;
sys/dev/pci/if_ice.c
18851
struct ice_vsig_vsi *tmp = vsi_cur->next_vsi;
sys/dev/pci/if_ice.c
18865
vsi_cur = tmp;
sys/dev/pci/if_ice.c
18920
struct ice_chs_chg *pos, *tmp;
sys/dev/pci/if_ice.c
18922
TAILQ_FOREACH_SAFE(pos, chg, list_entry, tmp) {
sys/dev/pci/if_ice.c
19141
struct ice_vsig_prof *ent, *tmp;
sys/dev/pci/if_ice.c
19143
TAILQ_FOREACH_SAFE(ent, lst, list, tmp) {
sys/dev/pci/if_ice.c
19673
struct ice_chs_chg *tmp;
sys/dev/pci/if_ice.c
19678
TAILQ_FOREACH(tmp, chgs, list_entry) {
sys/dev/pci/if_ice.c
19679
if (tmp->type != ICE_PTG_ES_ADD || !tmp->add_prof)
sys/dev/pci/if_ice.c
19682
off = tmp->prof_id * hw->blk[blk].es.fvw;
sys/dev/pci/if_ice.c
19690
p->offset = htole16(tmp->prof_id);
sys/dev/pci/if_ice.c
19708
struct ice_chs_chg *tmp;
sys/dev/pci/if_ice.c
19712
TAILQ_FOREACH(tmp, chgs, list_entry) {
sys/dev/pci/if_ice.c
19713
if (tmp->type != ICE_TCAM_ADD || !tmp->add_tcam_idx)
sys/dev/pci/if_ice.c
19723
p->entry[0].addr = htole16(tmp->tcam_idx);
sys/dev/pci/if_ice.c
19724
p->entry[0].prof_id = tmp->prof_id;
sys/dev/pci/if_ice.c
19727
&hw->blk[blk].prof.t[tmp->tcam_idx].key,
sys/dev/pci/if_ice.c
19744
struct ice_chs_chg *tmp;
sys/dev/pci/if_ice.c
19748
TAILQ_FOREACH(tmp, chgs, list_entry) {
sys/dev/pci/if_ice.c
19749
if (tmp->type != ICE_PTG_ES_ADD || !tmp->add_ptg)
sys/dev/pci/if_ice.c
19759
p->offset = htole16(tmp->ptype);
sys/dev/pci/if_ice.c
19760
p->value[0] = tmp->ptg;
sys/dev/pci/if_ice.c
19776
struct ice_chs_chg *tmp;
sys/dev/pci/if_ice.c
19780
TAILQ_FOREACH(tmp, chgs, list_entry) {
sys/dev/pci/if_ice.c
19781
if (tmp->type != ICE_VSIG_ADD &&
sys/dev/pci/if_ice.c
19782
tmp->type != ICE_VSI_MOVE &&
sys/dev/pci/if_ice.c
19783
tmp->type != ICE_VSIG_REM)
sys/dev/pci/if_ice.c
19793
p->offset = htole16(tmp->vsi);
sys/dev/pci/if_ice.c
19794
p->value[0] = htole16(tmp->vsig);
sys/dev/pci/if_ice.c
19939
struct ice_chs_chg *tmp;
sys/dev/pci/if_ice.c
19949
TAILQ_FOREACH(tmp, chgs, list_entry) {
sys/dev/pci/if_ice.c
19950
switch (tmp->type) {
sys/dev/pci/if_ice.c
19952
if (tmp->add_ptg)
sys/dev/pci/if_ice.c
19954
if (tmp->add_prof)
sys/dev/pci/if_ice.c
20115
struct ice_chs_chg *tmp, *del;
sys/dev/pci/if_ice.c
20221
TAILQ_FOREACH_SAFE(del, &chg, list_entry, tmp) {
sys/dev/pci/if_ice.c
20291
struct ice_chs_chg *del, *tmp;
sys/dev/pci/if_ice.c
20311
TAILQ_FOREACH_SAFE(del, &chg, list_entry, tmp) {
sys/dev/pci/if_ice.c
20581
struct ice_rss_cfg *r, *tmp;
sys/dev/pci/if_ice.c
20588
TAILQ_FOREACH_SAFE(r, &hw->rss_list_head, l_entry, tmp) {
sys/dev/pci/if_ice.c
25555
struct ice_chs_chg *tmp, *del;
sys/dev/pci/if_ice.c
25673
TAILQ_FOREACH_SAFE(del, &chg, list_entry, tmp) {
sys/dev/pci/if_ice.c
25933
struct ice_rss_cfg *r, *tmp;
sys/dev/pci/if_ice.c
25948
TAILQ_FOREACH_SAFE(r, &hw->rss_list_head, l_entry, tmp) {
sys/dev/pci/if_ice.c
4187
struct ice_orom_civd_info *tmp;
sys/dev/pci/if_ice.c
4190
tmp = (struct ice_orom_civd_info *)&orom_data[offset];
sys/dev/pci/if_ice.c
4193
if (memcmp("$CIV", tmp->signature, sizeof(tmp->signature)) != 0)
sys/dev/pci/if_ice.c
4200
for (i = 0; i < sizeof(*tmp); i++)
sys/dev/pci/if_ice.c
4201
sum += ((uint8_t *)tmp)[i];
sys/dev/pci/if_ice.c
4211
*civd = *tmp;
sys/dev/pci/if_ice.c
5735
struct ice_sched_node *tmp;
sys/dev/pci/if_ice.c
5737
tmp = ice_sched_find_node_by_teid(start_node->children[i],
sys/dev/pci/if_ice.c
5739
if (tmp)
sys/dev/pci/if_ice.c
5740
return tmp;
sys/dev/pci/if_ice.c
7057
struct ice_fltr_mgmt_list_entry *tmp;
sys/dev/pci/if_ice.c
7059
TAILQ_FOREACH_SAFE(entry, rule_head, list_entry, tmp) {
sys/dev/pci/if_ice.c
7282
struct ice_vsig_vsi *tmp = vsi_cur->next_vsi;
sys/dev/pci/if_ice.c
7287
vsi_cur = tmp;
sys/dev/pci/if_ice.c
7337
struct ice_prof_map *del, *tmp;
sys/dev/pci/if_ice.c
7341
TAILQ_FOREACH_SAFE(del, &es->prof_map, list, tmp) {
sys/dev/pci/if_ice.c
7359
struct ice_flow_prof *p, *tmp;
sys/dev/pci/if_ice.c
7363
TAILQ_FOREACH_SAFE(p, &hw->fl_profs[blk_idx], l_entry, tmp) {
sys/dev/pci/if_ice.c
8031
struct ice_fltr_list_entry *e, *tmp;
sys/dev/pci/if_ice.c
8033
TAILQ_FOREACH_SAFE(e, list, list_entry, tmp) {
sys/dev/pci/if_ipw.c
1441
uint32_t tmp;
sys/dev/pci/if_ipw.c
1457
tmp = CSR_READ_4(sc, IPW_CSR_RST);
sys/dev/pci/if_ipw.c
1458
CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_PRINCETON_RESET);
sys/dev/pci/if_ipw.c
1464
uint32_t tmp;
sys/dev/pci/if_ipw.c
1470
tmp = CSR_READ_4(sc, IPW_CSR_CTL);
sys/dev/pci/if_ipw.c
1471
CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT);
sys/dev/pci/if_ipw.c
1482
tmp = CSR_READ_4(sc, IPW_CSR_RST);
sys/dev/pci/if_ipw.c
1483
CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_SW_RESET);
sys/dev/pci/if_ipw.c
1487
tmp = CSR_READ_4(sc, IPW_CSR_CTL);
sys/dev/pci/if_ipw.c
1488
CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT);
sys/dev/pci/if_ipw.c
1550
uint32_t tmp, dst;
sys/dev/pci/if_ipw.c
1578
tmp = CSR_READ_4(sc, IPW_CSR_CTL);
sys/dev/pci/if_ipw.c
1579
CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_ALLOW_STANDBY);
sys/dev/pci/if_ipw.c
1588
tmp = CSR_READ_4(sc, IPW_CSR_IO);
sys/dev/pci/if_ipw.c
1589
CSR_WRITE_4(sc, IPW_CSR_IO, tmp | IPW_IO_GPIO1_MASK |
sys/dev/pci/if_ipw.c
723
uint32_t tmp;
sys/dev/pci/if_ipw.c
758
tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL);
sys/dev/pci/if_ipw.c
759
val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n;
sys/dev/pci/if_iwi.c
1500
uint32_t tmp;
sys/dev/pci/if_iwi.c
1517
tmp = CSR_READ_4(sc, IWI_CSR_RST);
sys/dev/pci/if_iwi.c
1518
CSR_WRITE_4(sc, IWI_CSR_RST, tmp | IWI_RST_PRINCETON_RESET);
sys/dev/pci/if_iwi.c
1524
uint32_t tmp;
sys/dev/pci/if_iwi.c
1530
tmp = CSR_READ_4(sc, IWI_CSR_CTL);
sys/dev/pci/if_iwi.c
1531
CSR_WRITE_4(sc, IWI_CSR_CTL, tmp | IWI_CTL_INIT);
sys/dev/pci/if_iwi.c
1547
tmp = CSR_READ_4(sc, IWI_CSR_RST);
sys/dev/pci/if_iwi.c
1548
CSR_WRITE_4(sc, IWI_CSR_RST, tmp | IWI_RST_SW_RESET);
sys/dev/pci/if_iwi.c
1552
tmp = CSR_READ_4(sc, IWI_CSR_CTL);
sys/dev/pci/if_iwi.c
1553
CSR_WRITE_4(sc, IWI_CSR_CTL, tmp | IWI_CTL_INIT);
sys/dev/pci/if_iwi.c
1567
uint32_t tmp;
sys/dev/pci/if_iwi.c
1570
tmp = CSR_READ_4(sc, IWI_CSR_RST);
sys/dev/pci/if_iwi.c
1571
CSR_WRITE_4(sc, IWI_CSR_RST, tmp | IWI_RST_STOP_MASTER);
sys/dev/pci/if_iwi.c
1586
tmp = CSR_READ_4(sc, IWI_CSR_RST);
sys/dev/pci/if_iwi.c
1587
CSR_WRITE_4(sc, IWI_CSR_RST, tmp & ~IWI_RST_PRINCETON_RESET);
sys/dev/pci/if_iwi.c
1638
uint32_t sentinel, tmp, ctl, src, dst, sum, len, mlen;
sys/dev/pci/if_iwi.c
1720
tmp = CSR_READ_4(sc, IWI_CSR_RST);
sys/dev/pci/if_iwi.c
1721
tmp &= ~(IWI_RST_MASTER_DISABLED | IWI_RST_STOP_MASTER);
sys/dev/pci/if_iwi.c
1722
CSR_WRITE_4(sc, IWI_CSR_RST, tmp);
sys/dev/pci/if_iwi.c
1748
tmp = CSR_READ_4(sc, IWI_CSR_CTL);
sys/dev/pci/if_iwi.c
1749
CSR_WRITE_4(sc, IWI_CSR_CTL, tmp | IWI_CTL_ALLOW_STANDBY);
sys/dev/pci/if_iwi.c
728
uint32_t tmp;
sys/dev/pci/if_iwi.c
758
tmp = MEM_READ_4(sc, IWI_MEM_EVENT_CTL) & IWI_LED_MASK;
sys/dev/pci/if_iwi.c
759
MEM_WRITE_4(sc, IWI_MEM_EVENT_CTL, tmp | IWI_LED_ASSOC);
sys/dev/pci/if_iwi.c
775
tmp = MEM_READ_4(sc, IWI_MEM_EVENT_CTL) & IWI_LED_MASK;
sys/dev/pci/if_iwi.c
776
MEM_WRITE_4(sc, IWI_MEM_EVENT_CTL, tmp & ~IWI_LED_ASSOC);
sys/dev/pci/if_iwi.c
794
uint32_t tmp;
sys/dev/pci/if_iwi.c
829
tmp = MEM_READ_4(sc, IWI_MEM_EEPROM_CTL);
sys/dev/pci/if_iwi.c
830
val |= ((tmp & IWI_EEPROM_Q) >> IWI_EEPROM_SHIFT_Q) << n;
sys/dev/pci/if_iwm.c
11423
int tmp;
sys/dev/pci/if_iwm.c
11425
tmp = htole32(ict[sc->ict_cur]);
sys/dev/pci/if_iwm.c
11426
if (!tmp)
sys/dev/pci/if_iwm.c
11433
while (tmp) {
sys/dev/pci/if_iwm.c
11434
r1 |= tmp;
sys/dev/pci/if_iwm.c
11437
tmp = htole32(ict[sc->ict_cur]);
sys/dev/pci/if_iwn.c
1018
uint32_t val, tmp;
sys/dev/pci/if_iwn.c
1037
tmp = IWN_READ(sc, IWN_OTP_GP);
sys/dev/pci/if_iwn.c
1038
if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) {
sys/dev/pci/if_iwn.c
1043
if (tmp & IWN_OTP_GP_ECC_CORR_STTS) {
sys/dev/pci/if_iwn.c
3138
uint32_t r1, r2, tmp;
sys/dev/pci/if_iwn.c
3145
tmp = 0;
sys/dev/pci/if_iwn.c
3147
tmp |= sc->ict[sc->ict_cur];
sys/dev/pci/if_iwn.c
3151
tmp = letoh32(tmp);
sys/dev/pci/if_iwn.c
3152
if (tmp == 0xffffffff) /* Shouldn't happen. */
sys/dev/pci/if_iwn.c
3153
tmp = 0;
sys/dev/pci/if_iwn.c
3154
else if (tmp & 0xc0000) /* Workaround a HW bug. */
sys/dev/pci/if_iwn.c
3155
tmp |= 0x8000;
sys/dev/pci/if_iwn.c
3156
r1 = (tmp & 0xff00) << 16 | (tmp & 0xff);
sys/dev/pci/if_iwn.c
3176
tmp = IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL;
sys/dev/pci/if_iwn.c
3178
tmp ? "enabled" : "disabled");
sys/dev/pci/if_iwn.c
3179
if (tmp)
sys/dev/pci/if_iwn.c
6915
uint32_t tmp;
sys/dev/pci/if_iwn.c
6937
tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR);
sys/dev/pci/if_iwn.c
6938
tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK;
sys/dev/pci/if_iwn.c
6939
tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32;
sys/dev/pci/if_iwn.c
6940
iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp);
sys/dev/pci/if_iwn.c
905
uint32_t tmp;
sys/dev/pci/if_iwn.c
907
tmp = iwn_mem_read(sc, addr & ~3);
sys/dev/pci/if_iwn.c
909
tmp = (tmp & 0x0000ffff) | data << 16;
sys/dev/pci/if_iwn.c
911
tmp = (tmp & 0xffff0000) | data;
sys/dev/pci/if_iwn.c
912
iwn_mem_write(sc, addr & ~3, tmp);
sys/dev/pci/if_iwx.c
11316
int tmp;
sys/dev/pci/if_iwx.c
11318
tmp = htole32(ict[sc->ict_cur]);
sys/dev/pci/if_iwx.c
11319
if (!tmp)
sys/dev/pci/if_iwx.c
11326
while (tmp) {
sys/dev/pci/if_iwx.c
11327
r1 |= tmp;
sys/dev/pci/if_iwx.c
11330
tmp = htole32(ict[sc->ict_cur]);
sys/dev/pci/if_ix.c
1000
tmp = IXGBE_DV_X540(frame, frame);
sys/dev/pci/if_ix.c
1003
tmp = IXGBE_DV(frame, frame);
sys/dev/pci/if_ix.c
1006
size = IXGBE_BT2KB(tmp);
sys/dev/pci/if_ix.c
1016
tmp = IXGBE_LOW_DV_X540(frame);
sys/dev/pci/if_ix.c
1019
tmp = IXGBE_LOW_DV(frame);
sys/dev/pci/if_ix.c
1022
hw->fc.low_water[0] = IXGBE_BT2KB(tmp);
sys/dev/pci/if_ix.c
990
uint32_t rxpb, frame, size, tmp;
sys/dev/pci/if_nfe.c
1016
uint32_t tmp;
sys/dev/pci/if_nfe.c
1065
tmp = NFE_READ(sc, NFE_PWR_STATE);
sys/dev/pci/if_nfe.c
1066
NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP);
sys/dev/pci/if_nfe.c
1068
tmp = NFE_READ(sc, NFE_PWR_STATE);
sys/dev/pci/if_nfe.c
1069
NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID);
sys/dev/pci/if_nfe.c
1541
uint32_t tmp;
sys/dev/pci/if_nfe.c
1544
tmp = NFE_READ(sc, NFE_MACADDR_HI);
sys/dev/pci/if_nfe.c
1545
addr[0] = (tmp & 0xff);
sys/dev/pci/if_nfe.c
1546
addr[1] = (tmp >> 8) & 0xff;
sys/dev/pci/if_nfe.c
1547
addr[2] = (tmp >> 16) & 0xff;
sys/dev/pci/if_nfe.c
1548
addr[3] = (tmp >> 24) & 0xff;
sys/dev/pci/if_nfe.c
1550
tmp = NFE_READ(sc, NFE_MACADDR_LO);
sys/dev/pci/if_nfe.c
1551
addr[4] = (tmp & 0xff);
sys/dev/pci/if_nfe.c
1552
addr[5] = (tmp >> 8) & 0xff;
sys/dev/pci/if_nfe.c
1555
tmp = NFE_READ(sc, NFE_MACADDR_LO);
sys/dev/pci/if_nfe.c
1556
addr[0] = (tmp >> 8) & 0xff;
sys/dev/pci/if_nfe.c
1557
addr[1] = (tmp & 0xff);
sys/dev/pci/if_nfe.c
1559
tmp = NFE_READ(sc, NFE_MACADDR_HI);
sys/dev/pci/if_nfe.c
1560
addr[2] = (tmp >> 24) & 0xff;
sys/dev/pci/if_nfe.c
1561
addr[3] = (tmp >> 16) & 0xff;
sys/dev/pci/if_nfe.c
1562
addr[4] = (tmp >> 8) & 0xff;
sys/dev/pci/if_nfe.c
1563
addr[5] = (tmp & 0xff);
sys/dev/pci/if_ngbe.c
2511
uint32_t tmp;
sys/dev/pci/if_ngbe.c
2530
tmp = NGBE_READ_REG_ARRAY(hw, NGBE_MNG_MBOX, 1);
sys/dev/pci/if_ngbe.c
2531
if (tmp == NGBE_CHECKSUM_CAP_ST_PASS)
sys/dev/pci/if_ngbe.c
3340
uint32_t tmp;
sys/dev/pci/if_ngbe.c
3359
tmp = NGBE_READ_REG_ARRAY(hw, NGBE_MNG_MBOX, 1);
sys/dev/pci/if_ngbe.c
3360
if (tmp == NGBE_CHECKSUM_CAP_ST_PASS) {
sys/dev/pci/if_ngbe.c
3361
tmp = NGBE_READ_REG_ARRAY(hw, NGBE_MNG_MBOX, 2);
sys/dev/pci/if_ngbe.c
3362
*data = tmp;
sys/dev/pci/if_ngbe.c
3364
} else if (tmp == NGBE_CHECKSUM_CAP_ST_FAIL) {
sys/dev/pci/if_ngbe.c
3365
*data = tmp;
sys/dev/pci/if_rge.c
3528
uint32_t tmp;
sys/dev/pci/if_rge.c
3530
tmp = (reg >> 1) << RGE_MACOCP_ADDR_SHIFT;
sys/dev/pci/if_rge.c
3531
tmp += val;
sys/dev/pci/if_rge.c
3532
tmp |= RGE_MACOCP_BUSY;
sys/dev/pci/if_rge.c
3533
RGE_WRITE_4(sc, RGE_MACOCP, tmp);
sys/dev/pci/if_rge.c
3550
uint32_t tmp;
sys/dev/pci/if_rge.c
3553
tmp = (reg & RGE_EPHYAR_ADDR_MASK) << RGE_EPHYAR_ADDR_SHIFT;
sys/dev/pci/if_rge.c
3554
tmp |= RGE_EPHYAR_BUSY | (val & RGE_EPHYAR_DATA_MASK);
sys/dev/pci/if_rge.c
3555
RGE_WRITE_4(sc, RGE_EPHYAR, tmp);
sys/dev/pci/if_rge.c
3637
uint32_t tmp;
sys/dev/pci/if_rge.c
3640
tmp = (reg >> 1) << RGE_PHYOCP_ADDR_SHIFT;
sys/dev/pci/if_rge.c
3641
tmp |= RGE_PHYOCP_BUSY | val;
sys/dev/pci/if_rge.c
3642
RGE_WRITE_4(sc, RGE_PHYOCP, tmp);
sys/dev/pci/if_sis.c
1066
u_int16_t tmp[4];
sys/dev/pci/if_sis.c
1068
sis_read_eeprom(sc, (caddr_t)&tmp, NS_EE_NODEADDR,
sys/dev/pci/if_sis.c
1072
tmp[3] = tmp[3] >> 1;
sys/dev/pci/if_sis.c
1073
tmp[3] |= tmp[2] << 15;
sys/dev/pci/if_sis.c
1074
tmp[2] = tmp[2] >> 1;
sys/dev/pci/if_sis.c
1075
tmp[2] |= tmp[1] << 15;
sys/dev/pci/if_sis.c
1076
tmp[1] = tmp[1] >> 1;
sys/dev/pci/if_sis.c
1077
tmp[1] |= tmp[0] << 15;
sys/dev/pci/if_sis.c
1080
tmp[3] = letoh16(sis_reverse(tmp[3]));
sys/dev/pci/if_sis.c
1081
tmp[2] = letoh16(sis_reverse(tmp[2]));
sys/dev/pci/if_sis.c
1082
tmp[1] = letoh16(sis_reverse(tmp[1]));
sys/dev/pci/if_sis.c
1084
bcopy(&tmp[1], sc->arpcom.ac_enaddr,
sys/dev/pci/if_wpi.c
3196
uint32_t tmp;
sys/dev/pci/if_wpi.c
3217
tmp = WPI_READ(sc, WPI_FH_TX_STATUS);
sys/dev/pci/if_wpi.c
3218
if ((tmp & WPI_FH_TX_STATUS_IDLE(chnl)) ==
sys/dev/pci/qle.c
2761
u_int32_t csum, tmp, v;
sys/dev/pci/qle.c
2780
tmp = qle_read(sc, QLE_FLASH_NVRAM_ADDR);
sys/dev/pci/qle.c
2781
if (tmp & (1U << 31)) {
sys/dev/pci/sdhc_pci.c
267
pcireg_t tmp;
sys/dev/pci/sdhc_pci.c
269
tmp = pci_conf_read(pc, tag, reg & ~0x3);
sys/dev/pci/sdhc_pci.c
270
tmp &= ~(0xff << ((reg & 0x3) * 8));
sys/dev/pci/sdhc_pci.c
271
tmp |= (val << ((reg & 0x3) * 8));
sys/dev/pci/sdhc_pci.c
272
pci_conf_write(pc, tag, reg & ~0x3, tmp);
sys/dev/pcmcia/pcmcia.c
391
struct pcmcia_function *tmp;
sys/dev/pcmcia/pcmcia.c
423
SIMPLEQ_FOREACH(tmp, &pf->sc->card.pf_head, pf_list) {
sys/dev/pcmcia/pcmcia.c
424
if ((tmp->pf_flags & PFF_ENABLED) &&
sys/dev/pcmcia/pcmcia.c
425
(pf->ccr_base >= (tmp->ccr_base - tmp->pf_ccr_offset)) &&
sys/dev/pcmcia/pcmcia.c
427
(tmp->ccr_base - tmp->pf_ccr_offset +
sys/dev/pcmcia/pcmcia.c
428
tmp->pf_ccr_realsize))) {
sys/dev/pcmcia/pcmcia.c
429
pf->pf_ccrt = tmp->pf_ccrt;
sys/dev/pcmcia/pcmcia.c
430
pf->pf_ccrh = tmp->pf_ccrh;
sys/dev/pcmcia/pcmcia.c
431
pf->pf_ccr_realsize = tmp->pf_ccr_realsize;
sys/dev/pcmcia/pcmcia.c
438
(tmp->pf_ccr_offset + pf->ccr_base) -
sys/dev/pcmcia/pcmcia.c
439
tmp->ccr_base;
sys/dev/pcmcia/pcmcia.c
440
pf->pf_ccr_window = tmp->pf_ccr_window;
sys/dev/pcmcia/pcmcia.c
445
if (tmp == NULL) {
sys/dev/pcmcia/pcmcia.c
494
SIMPLEQ_FOREACH(tmp, &pf->sc->card.pf_head, pf_list) {
sys/dev/pcmcia/pcmcia.c
497
tmp->sc->dev.dv_xname, tmp->number,
sys/dev/pcmcia/pcmcia.c
498
tmp->pf_ccr_window, tmp->pf_ccr_offset,
sys/dev/pcmcia/pcmcia.c
499
pcmcia_ccr_read(tmp, 0x00),
sys/dev/pcmcia/pcmcia.c
500
pcmcia_ccr_read(tmp, 0x02),
sys/dev/pcmcia/pcmcia.c
501
pcmcia_ccr_read(tmp, 0x04),
sys/dev/pcmcia/pcmcia.c
502
pcmcia_ccr_read(tmp, 0x06),
sys/dev/pcmcia/pcmcia.c
504
pcmcia_ccr_read(tmp, 0x0A),
sys/dev/pcmcia/pcmcia.c
505
pcmcia_ccr_read(tmp, 0x0C),
sys/dev/pcmcia/pcmcia.c
506
pcmcia_ccr_read(tmp, 0x0E),
sys/dev/pcmcia/pcmcia.c
507
pcmcia_ccr_read(tmp, 0x10),
sys/dev/pcmcia/pcmcia.c
509
pcmcia_ccr_read(tmp, 0x12));
sys/dev/pcmcia/pcmcia.c
535
struct pcmcia_function *tmp;
sys/dev/pcmcia/pcmcia.c
559
SIMPLEQ_FOREACH(tmp, &pf->sc->card.pf_head, pf_list) {
sys/dev/pcmcia/pcmcia.c
560
if ((tmp->pf_flags & PFF_ENABLED) &&
sys/dev/pcmcia/pcmcia.c
561
(pf->ccr_base >= (tmp->ccr_base - tmp->pf_ccr_offset)) &&
sys/dev/pcmcia/pcmcia.c
563
(tmp->ccr_base - tmp->pf_ccr_offset + tmp->pf_ccr_realsize)))
sys/dev/pcmcia/pcmcia.c
568
if (tmp == NULL) {
sys/dev/rasops/rasops_bitops.h
160
int tmp, lmask, rmask, height, lnum, rnum, sb, db, cnt, full;
sys/dev/rasops/rasops_bitops.h
209
GETBITS(srp, sb, num, tmp);
sys/dev/rasops/rasops_bitops.h
210
PUTBITS(tmp, db, num, drp);
sys/dev/rasops/rasops_bitops.h
250
GETBITS(sp, src, db, tmp);
sys/dev/rasops/rasops_bitops.h
251
PUTBITS(tmp, 0, db, dp);
sys/dev/rasops/rasops_bitops.h
258
GETBITS(sp, src, 32, tmp);
sys/dev/rasops/rasops_bitops.h
259
*dp-- = tmp;
sys/dev/rasops/rasops_bitops.h
267
GETBITS(sp, sb, lnum, tmp);
sys/dev/rasops/rasops_bitops.h
268
PUTBITS(tmp, rnum, lnum, dp);
sys/dev/rasops/rasops_bitops.h
285
GETBITS(sp, sb, lnum, tmp);
sys/dev/rasops/rasops_bitops.h
286
PUTBITS(tmp, db, lnum, dp);
sys/dev/rasops/rasops_bitops.h
297
GETBITS(sp, sb, 32, tmp);
sys/dev/rasops/rasops_bitops.h
298
*dp++ = tmp;
sys/dev/rasops/rasops_bitops.h
302
GETBITS(sp, sb, rnum, tmp);
sys/dev/rasops/rasops_bitops.h
303
PUTBITS(tmp, 0, rnum, dp);
sys/dev/rasops/rasops_masks.h
57
u_int32_t tmp = (x); \
sys/dev/rasops/rasops_masks.h
58
tmp = ((tmp >> 1) & 0x55555555) | ((tmp << 1) & 0xaaaaaaaa); \
sys/dev/rasops/rasops_masks.h
59
tmp = ((tmp >> 2) & 0x33333333) | ((tmp << 2) & 0xcccccccc); \
sys/dev/rasops/rasops_masks.h
60
tmp = ((tmp >> 4) & 0x0f0f0f0f) | ((tmp << 4) & 0xf0f0f0f0); \
sys/dev/rasops/rasops_masks.h
61
tmp = ((tmp >> 8) & 0x00ff00ff) | ((tmp << 8) & 0xff00ff00); \
sys/dev/rasops/rasops_masks.h
62
tmp = ((tmp >> 16) & 0x0000ffff) | ((tmp << 16) & 0xffff0000); \
sys/dev/rasops/rasops_masks.h
63
tmp; \
sys/dev/sbus/zx.c
497
u_int tmp;
sys/dev/sbus/zx.c
506
tmp = (index & 0x0f) + 0x40;
sys/dev/sbus/zx.c
508
tmp = index & 0x3f;
sys/dev/sbus/zx.c
510
SETREG(zx->zx_type, 0x5800 + tmp);
sys/dev/tc/if_le_ioasic.c
249
u_int16_t tmp;
sys/dev/tc/if_le_ioasic.c
260
tmp = *bptr;
sys/dev/tc/if_le_ioasic.c
261
*to++ = tmp & 0xff;
sys/dev/tc/if_le_ioasic.c
262
*to++ = (tmp >> 8) & 0xff;
sys/dev/usb/dwc2/dwc2_hcdqueue.c
2119
unsigned long tmp;
sys/dev/usb/dwc2/dwc2_hcdqueue.c
2124
tmp = (67667L * (31L + 10L * BitTime (bytecount))) /
sys/dev/usb/dwc2/dwc2_hcdqueue.c
2127
tmp;
sys/dev/usb/dwc2/dwc2_hcdqueue.c
2129
tmp = (66700L * (31L + 10L * BitTime (bytecount))) /
sys/dev/usb/dwc2/dwc2_hcdqueue.c
2132
tmp;
sys/dev/usb/dwc2/dwc2_hcdqueue.c
2136
tmp = (8354L * (31L + 10L * BitTime (bytecount))) /
sys/dev/usb/dwc2/dwc2_hcdqueue.c
2139
tmp;
sys/dev/usb/dwc2/dwc2_hcdqueue.c
2141
tmp = (8354L * (31L + 10L * BitTime (bytecount))) /
sys/dev/usb/dwc2/dwc2_hcdqueue.c
2143
return 9107L + BW_HOST_DELAY + tmp;
sys/dev/usb/dwc2/dwc2_hcdqueue.c
2148
tmp = HS_NSECS_ISO (bytecount);
sys/dev/usb/dwc2/dwc2_hcdqueue.c
2150
tmp = HS_NSECS (bytecount);
sys/dev/usb/dwc2/dwc2_hcdqueue.c
2151
return tmp;
sys/dev/usb/dwc2/dwc2_hcdqueue.c
458
char tmp[64];
sys/dev/usb/dwc2/dwc2_hcdqueue.c
459
char *buf = tmp;
sys/dev/usb/dwc2/dwc2_hcdqueue.c
460
size_t buf_size = sizeof(tmp);
sys/dev/usb/dwc2/dwc2_hcdqueue.c
496
print_fn(tmp, print_data);
sys/dev/usb/if_mtw.c
1006
uint32_t tmp;
sys/dev/usb/if_mtw.c
1010
if ((error = mtw_read(sc, MTW_EFUSE_CTRL, &tmp)) != 0)
sys/dev/usb/if_mtw.c
1021
tmp &= ~(MTW_EFSROM_MODE_MASK | MTW_EFSROM_AIN_MASK);
sys/dev/usb/if_mtw.c
1022
tmp |= (addr & ~0xf) << MTW_EFSROM_AIN_SHIFT | MTW_EFSROM_KICK;
sys/dev/usb/if_mtw.c
1023
mtw_write(sc, MTW_EFUSE_CTRL, tmp);
sys/dev/usb/if_mtw.c
1025
if ((error = mtw_read(sc, MTW_EFUSE_CTRL, &tmp)) != 0)
sys/dev/usb/if_mtw.c
1027
if (!(tmp & MTW_EFSROM_KICK))
sys/dev/usb/if_mtw.c
1034
if ((tmp & MTW_EFUSE_AOUT_MASK) == MTW_EFUSE_AOUT_MASK) {
sys/dev/usb/if_mtw.c
1040
if ((error = mtw_read(sc, reg, &tmp)) != 0)
sys/dev/usb/if_mtw.c
1043
*val = (addr & 2) ? tmp >> 16 : tmp & 0xffff;
sys/dev/usb/if_mtw.c
1051
uint16_t tmp;
sys/dev/usb/if_mtw.c
1059
USETW(req.wLength, sizeof tmp);
sys/dev/usb/if_mtw.c
1060
error = usbd_do_request(sc->sc_udev, &req, &tmp);
sys/dev/usb/if_mtw.c
1062
*val = letoh16(tmp);
sys/dev/usb/if_mtw.c
1078
uint32_t tmp;
sys/dev/usb/if_mtw.c
1082
if ((error = mtw_read(sc, MTW_RF_CSR, &tmp)) != 0)
sys/dev/usb/if_mtw.c
1084
if (!(tmp & MTW_RF_CSR_KICK))
sys/dev/usb/if_mtw.c
1095
tmp = MTW_RF_CSR_KICK | (bank & 0xf) << shift | reg << 8;
sys/dev/usb/if_mtw.c
1096
if ((error = mtw_write(sc, MTW_RF_CSR, tmp)) != 0)
sys/dev/usb/if_mtw.c
1100
if ((error = mtw_read(sc, MTW_RF_CSR, &tmp)) != 0)
sys/dev/usb/if_mtw.c
1102
if (!(tmp & MTW_RF_CSR_KICK))
sys/dev/usb/if_mtw.c
1108
*val = tmp & 0xff;
sys/dev/usb/if_mtw.c
1115
uint32_t tmp;
sys/dev/usb/if_mtw.c
1119
if ((error = mtw_read(sc, MTW_RF_CSR, &tmp)) != 0)
sys/dev/usb/if_mtw.c
1121
if (!(tmp & MTW_RF_CSR_KICK))
sys/dev/usb/if_mtw.c
1132
tmp = MTW_RF_CSR_WRITE | MTW_RF_CSR_KICK | (bank & 0xf) << shift |
sys/dev/usb/if_mtw.c
1134
return mtw_write(sc, MTW_RF_CSR, tmp);
sys/dev/usb/if_mtw.c
1140
uint32_t tmp;
sys/dev/usb/if_mtw.c
1144
if ((error = mtw_read(sc, MTW_BBP_CSR, &tmp)) != 0)
sys/dev/usb/if_mtw.c
1146
if (!(tmp & MTW_BBP_CSR_KICK))
sys/dev/usb/if_mtw.c
1152
tmp = MTW_BBP_CSR_READ | MTW_BBP_CSR_KICK | reg << MTW_BBP_ADDR_SHIFT;
sys/dev/usb/if_mtw.c
1153
if ((error = mtw_write(sc, MTW_BBP_CSR, tmp)) != 0)
sys/dev/usb/if_mtw.c
1157
if ((error = mtw_read(sc, MTW_BBP_CSR, &tmp)) != 0)
sys/dev/usb/if_mtw.c
1159
if (!(tmp & MTW_BBP_CSR_KICK))
sys/dev/usb/if_mtw.c
1165
*val = tmp & 0xff;
sys/dev/usb/if_mtw.c
1172
uint32_t tmp;
sys/dev/usb/if_mtw.c
1176
if ((error = mtw_read(sc, MTW_BBP_CSR, &tmp)) != 0)
sys/dev/usb/if_mtw.c
1178
if (!(tmp & MTW_BBP_CSR_KICK))
sys/dev/usb/if_mtw.c
1184
tmp = MTW_BBP_CSR_KICK | reg << MTW_BBP_ADDR_SHIFT | val;
sys/dev/usb/if_mtw.c
1185
return mtw_write(sc, MTW_BBP_CSR, tmp);
sys/dev/usb/if_mtw.c
1754
uint32_t tmp;
sys/dev/usb/if_mtw.c
1756
mtw_read(sc, MTW_BKOFF_SLOT_CFG, &tmp);
sys/dev/usb/if_mtw.c
1757
tmp &= ~0xff;
sys/dev/usb/if_mtw.c
1758
tmp |= (sc->sc_ic.ic_flags & IEEE80211_F_SHSLOT) ?
sys/dev/usb/if_mtw.c
1760
mtw_write(sc, MTW_BKOFF_SLOT_CFG, tmp);
sys/dev/usb/if_mtw.c
2542
uint32_t tmp;
sys/dev/usb/if_mtw.c
2546
mtw_read(sc, MTW_TX_BAND_CFG, &tmp);
sys/dev/usb/if_mtw.c
2547
tmp &= ~(MTW_TX_BAND_SEL_2G | MTW_TX_BAND_SEL_5G |
sys/dev/usb/if_mtw.c
2549
tmp |= (group == 0) ? MTW_TX_BAND_SEL_2G : MTW_TX_BAND_SEL_5G;
sys/dev/usb/if_mtw.c
2550
mtw_write(sc, MTW_TX_BAND_CFG, tmp);
sys/dev/usb/if_mtw.c
2590
uint32_t tmp;
sys/dev/usb/if_mtw.c
2607
mtw_read(sc, MTW_TX_ALC_CFG0, &tmp);
sys/dev/usb/if_mtw.c
2608
tmp &= ~0x3f3f;
sys/dev/usb/if_mtw.c
2609
tmp |= (txpow1 & 0x3f);
sys/dev/usb/if_mtw.c
2610
mtw_write(sc, MTW_TX_ALC_CFG0, tmp);
sys/dev/usb/if_mtw.c
2668
uint32_t tmp;
sys/dev/usb/if_mtw.c
2670
mtw_read(sc, MTW_BCN_TIME_CFG, &tmp);
sys/dev/usb/if_mtw.c
2671
tmp &= ~0x1fffff;
sys/dev/usb/if_mtw.c
2672
tmp |= ic->ic_bss->ni_intval * 16;
sys/dev/usb/if_mtw.c
2673
tmp |= MTW_TSF_TIMER_EN | MTW_TBTT_TIMER_EN;
sys/dev/usb/if_mtw.c
2676
tmp |= 1 << MTW_TSF_SYNC_MODE_SHIFT;
sys/dev/usb/if_mtw.c
2677
mtw_write(sc, MTW_BCN_TIME_CFG, tmp);
sys/dev/usb/if_mtw.c
2683
uint32_t tmp;
sys/dev/usb/if_mtw.c
2685
mtw_read(sc, MTW_BCN_TIME_CFG, &tmp);
sys/dev/usb/if_mtw.c
2686
tmp &= ~(MTW_BCN_TX_EN | MTW_TSF_TIMER_EN | MTW_TBTT_TIMER_EN);
sys/dev/usb/if_mtw.c
2687
mtw_write(sc, MTW_BCN_TIME_CFG, tmp);
sys/dev/usb/if_mtw.c
2717
uint32_t tmp;
sys/dev/usb/if_mtw.c
2720
mtw_read(sc, MTW_TX_RTS_CFG, &tmp);
sys/dev/usb/if_mtw.c
2721
tmp &= ~0xffff00;
sys/dev/usb/if_mtw.c
2722
tmp |= 0x1000 << MTW_RTS_THRES_SHIFT;
sys/dev/usb/if_mtw.c
2723
mtw_write(sc, MTW_TX_RTS_CFG, tmp);
sys/dev/usb/if_mtw.c
2729
uint32_t tmp;
sys/dev/usb/if_mtw.c
2731
mtw_read(sc, MTW_AUTO_RSP_CFG, &tmp);
sys/dev/usb/if_mtw.c
2733
tmp |= MTW_CCK_SHORT_EN;
sys/dev/usb/if_mtw.c
2735
tmp &= ~MTW_CCK_SHORT_EN;
sys/dev/usb/if_mtw.c
2736
mtw_write(sc, MTW_AUTO_RSP_CFG, tmp);
sys/dev/usb/if_mtw.c
2873
uint32_t tmp;
sys/dev/usb/if_mtw.c
2918
mtw_read(sc, MTW_LDO_CFG0, &tmp);
sys/dev/usb/if_mtw.c
2919
tmp &= ~(1 << 4);
sys/dev/usb/if_mtw.c
2920
tmp |= (1 << 2);
sys/dev/usb/if_mtw.c
2921
mtw_write(sc, MTW_LDO_CFG0, tmp);
sys/dev/usb/if_mtw.c
2993
uint32_t tmp;
sys/dev/usb/if_mtw.c
2997
mtw_read(sc, MTW_MAC_SYS_CTRL, &tmp);
sys/dev/usb/if_mtw.c
3018
mtw_write(sc, MTW_MAC_SYS_CTRL, tmp);
sys/dev/usb/if_mtw.c
3025
uint32_t tmp;
sys/dev/usb/if_mtw.c
3029
mtw_read(sc, MTW_WLAN_CTRL, &tmp);
sys/dev/usb/if_mtw.c
3031
tmp &= ~0xfffff000;
sys/dev/usb/if_mtw.c
3033
tmp &= ~MTW_WLAN_CLK_EN;
sys/dev/usb/if_mtw.c
3034
tmp |= MTW_WLAN_EN;
sys/dev/usb/if_mtw.c
3035
mtw_write(sc, MTW_WLAN_CTRL, tmp);
sys/dev/usb/if_mtw.c
3038
tmp |= MTW_WLAN_CLK_EN;
sys/dev/usb/if_mtw.c
3040
tmp |= (MTW_WLAN_RESET | MTW_WLAN_RESET_RF);
sys/dev/usb/if_mtw.c
3042
mtw_write(sc, MTW_WLAN_CTRL, tmp);
sys/dev/usb/if_mtw.c
3045
mtw_read(sc, MTW_OSC_CTRL, &tmp);
sys/dev/usb/if_mtw.c
3046
tmp |= MTW_OSC_EN;
sys/dev/usb/if_mtw.c
3047
mtw_write(sc, MTW_OSC_CTRL, tmp);
sys/dev/usb/if_mtw.c
3048
tmp |= MTW_OSC_CAL_REQ;
sys/dev/usb/if_mtw.c
3049
mtw_write(sc, MTW_OSC_CTRL, tmp);
sys/dev/usb/if_mtw.c
3051
mtw_read(sc, MTW_WLAN_CTRL, &tmp);
sys/dev/usb/if_mtw.c
3052
tmp &= ~(MTW_WLAN_CLK_EN | MTW_WLAN_EN);
sys/dev/usb/if_mtw.c
3053
mtw_write(sc, MTW_WLAN_CTRL, tmp);
sys/dev/usb/if_mtw.c
3055
mtw_read(sc, MTW_OSC_CTRL, &tmp);
sys/dev/usb/if_mtw.c
3056
tmp &= ~MTW_OSC_EN;
sys/dev/usb/if_mtw.c
3057
mtw_write(sc, MTW_OSC_CTRL, tmp);
sys/dev/usb/if_mtw.c
3065
uint32_t tmp;
sys/dev/usb/if_mtw.c
3070
if ((error = mtw_read(sc, MTW_WPDMA_GLO_CFG, &tmp)) != 0)
sys/dev/usb/if_mtw.c
3072
if ((tmp & (MTW_TX_DMA_BUSY | MTW_RX_DMA_BUSY)) == 0)
sys/dev/usb/if_mtw.c
3081
tmp |= MTW_RX_DMA_EN | MTW_TX_DMA_EN | MTW_TX_WB_DDONE;
sys/dev/usb/if_mtw.c
3082
mtw_write(sc, MTW_WPDMA_GLO_CFG, tmp);
sys/dev/usb/if_mtw.c
3085
tmp = MTW_USB_TX_EN | MTW_USB_RX_EN | MTW_USB_RX_AGG_EN |
sys/dev/usb/if_mtw.c
3087
mtw_write(sc, MTW_USB_DMA_CFG, tmp);
sys/dev/usb/if_mtw.c
3090
tmp = MTW_DROP_CRC_ERR | MTW_DROP_PHY_ERR;
sys/dev/usb/if_mtw.c
3092
tmp |= MTW_DROP_UC_NOME | MTW_DROP_DUPL |
sys/dev/usb/if_mtw.c
3097
tmp |= MTW_DROP_RTS | MTW_DROP_PSPOLL;
sys/dev/usb/if_mtw.c
3099
mtw_write(sc, MTW_RX_FILTR_CFG, tmp);
sys/dev/usb/if_mtw.c
3111
uint32_t tmp;
sys/dev/usb/if_mtw.c
3131
if ((error = mtw_read(sc, MTW_WPDMA_GLO_CFG, &tmp)) != 0)
sys/dev/usb/if_mtw.c
3133
if ((tmp & (MTW_TX_DMA_BUSY | MTW_RX_DMA_BUSY)) == 0)
sys/dev/usb/if_mtw.c
3143
tmp &= 0xff0;
sys/dev/usb/if_mtw.c
3144
tmp |= MTW_TX_WB_DDONE;
sys/dev/usb/if_mtw.c
3145
mtw_write(sc, MTW_WPDMA_GLO_CFG, tmp);
sys/dev/usb/if_mtw.c
3161
if ((error = mtw_read(sc, MTW_MAC_STATUS_REG, &tmp)) != 0)
sys/dev/usb/if_mtw.c
3163
if (!(tmp & (MTW_RX_STATUS_BUSY | MTW_TX_STATUS_BUSY)))
sys/dev/usb/if_mtw.c
3180
mtw_read(sc, MTW_FCE_L2_STUFF, &tmp);
sys/dev/usb/if_mtw.c
3181
tmp &= ~MTW_L2S_WR_MPDU_LEN_EN;
sys/dev/usb/if_mtw.c
3182
mtw_write(sc, MTW_FCE_L2_STUFF, tmp);
sys/dev/usb/if_mtw.c
3197
mtw_read(sc, MTW_US_CYC_CNT, &tmp);
sys/dev/usb/if_mtw.c
3198
tmp = (tmp & ~0xff);
sys/dev/usb/if_mtw.c
3200
tmp |= 0x1e;
sys/dev/usb/if_mtw.c
3201
mtw_write(sc, MTW_US_CYC_CNT, tmp);
sys/dev/usb/if_mtw.c
3225
mtw_read(sc, MTW_CMB_CTRL, &tmp);
sys/dev/usb/if_mtw.c
3226
tmp &= ~(1 << 18 | 1 << 14);
sys/dev/usb/if_mtw.c
3227
mtw_write(sc, MTW_CMB_CTRL, tmp);
sys/dev/usb/if_mtw.c
3234
mtw_read(sc, MTW_USB_DMA_CFG, &tmp);
sys/dev/usb/if_mtw.c
3235
tmp &= ~(MTW_USB_TX_CLEAR | MTW_USB_TXOP_HALT |
sys/dev/usb/if_mtw.c
3237
mtw_write(sc, MTW_USB_DMA_CFG, tmp);
sys/dev/usb/if_mtw.c
3312
uint32_t tmp;
sys/dev/usb/if_mtw.c
3333
mtw_read(sc, MTW_WPDMA_GLO_CFG, &tmp);
sys/dev/usb/if_mtw.c
3334
tmp &= ~(MTW_RX_DMA_EN | MTW_TX_DMA_EN);
sys/dev/usb/if_mtw.c
3335
mtw_write(sc, MTW_WPDMA_GLO_CFG, tmp);
sys/dev/usb/if_mtw.c
3339
if (mtw_read(sc, MTW_WPDMA_GLO_CFG, &tmp) != 0)
sys/dev/usb/if_mtw.c
3341
if ((tmp & (MTW_TX_DMA_BUSY | MTW_RX_DMA_BUSY)) == 0)
sys/dev/usb/if_mtw.c
3351
mtw_read(sc, MTW_MAC_SYS_CTRL, &tmp);
sys/dev/usb/if_mtw.c
3352
tmp &= ~(MTW_MAC_RX_EN | MTW_MAC_TX_EN);
sys/dev/usb/if_mtw.c
3353
mtw_write(sc, MTW_MAC_SYS_CTRL, tmp);
sys/dev/usb/if_mtw.c
3356
mtw_read(sc, MTW_TX_RTS_CFG, &tmp);
sys/dev/usb/if_mtw.c
3357
tmp &= ~0xff;
sys/dev/usb/if_mtw.c
3358
mtw_write(sc, MTW_TX_RTS_CFG, tmp);
sys/dev/usb/if_mtw.c
3361
mtw_read(sc, MTW_US_CYC_CNT, &tmp);
sys/dev/usb/if_mtw.c
3362
tmp = (tmp & ~0xff);
sys/dev/usb/if_mtw.c
3363
mtw_write(sc, MTW_US_CYC_CNT, tmp);
sys/dev/usb/if_mtw.c
3366
mtw_read(sc, MTW_PBF_CFG, &tmp);
sys/dev/usb/if_mtw.c
3367
tmp &= ~0x3;
sys/dev/usb/if_mtw.c
3368
mtw_write(sc, MTW_PBF_CFG, tmp);
sys/dev/usb/if_mtw.c
3372
if ((error = mtw_read(sc, MTW_TXRXQ_PCNT, &tmp)) != 0)
sys/dev/usb/if_mtw.c
3374
if ((tmp & MTW_TX2Q_PCNT_MASK) == 0)
sys/dev/usb/if_mtw.c
3381
mtw_read(sc, MTW_SKEY_MODE_0_7, &tmp);
sys/dev/usb/if_mtw.c
3382
tmp &= ~(0xf << qid * 4);
sys/dev/usb/if_mtw.c
3383
mtw_write(sc, MTW_SKEY_MODE_0_7, tmp);
sys/dev/usb/if_mtw.c
352
uint32_t tmp;
sys/dev/usb/if_mtw.c
387
mtw_usb_dma_read(sc, &tmp);
sys/dev/usb/if_mtw.c
388
mtw_usb_dma_write(sc, tmp | (MTW_USB_RX_EN | MTW_USB_TX_EN));
sys/dev/usb/if_mtw.c
392
if ((error = mtw_read(sc, MTW_MAC_VER_ID, &tmp)) != 0)
sys/dev/usb/if_mtw.c
394
if (tmp != 0 && tmp != 0xffffffff)
sys/dev/usb/if_mtw.c
403
sc->mac_ver = tmp >> 16;
sys/dev/usb/if_mtw.c
404
sc->mac_rev = tmp & 0xffff;
sys/dev/usb/if_mtw.c
667
uint32_t blksz, sent, tmp, xferlen;
sys/dev/usb/if_mtw.c
707
mtw_read(sc, MTW_MCU_FW_IDX, &tmp);
sys/dev/usb/if_mtw.c
708
mtw_write(sc, MTW_MCU_FW_IDX, tmp++);
sys/dev/usb/if_mtw.c
740
uint32_t tmp, iofs, dofs;
sys/dev/usb/if_mtw.c
745
mtw_read_cfg(sc, MTW_MCU_DMA_ADDR, &tmp);
sys/dev/usb/if_mtw.c
746
if (tmp == MTW_MCU_READY)
sys/dev/usb/if_mtw.c
843
if ((error = mtw_read_cfg(sc, MTW_MCU_DMA_ADDR, &tmp)) != 0)
sys/dev/usb/if_mtw.c
845
if (tmp & MTW_MCU_READY)
sys/dev/usb/if_mtw.c
879
uint32_t tmp;
sys/dev/usb/if_mtw.c
883
(uint8_t *)&tmp, sizeof tmp);
sys/dev/usb/if_mtw.c
885
*val = letoh32(tmp);
sys/dev/usb/if_mtw.c
895
uint32_t tmp;
sys/dev/usb/if_mtw.c
903
error = usbd_do_request(sc->sc_udev, &req, &tmp);
sys/dev/usb/if_mtw.c
906
*val = letoh32(tmp);
sys/dev/usb/if_otus.c
1725
uint32_t tmp, offset;
sys/dev/usb/if_otus.c
1735
tmp = letoh32(eep->antCtrlCommon);
sys/dev/usb/if_otus.c
1736
otus_write(sc, AR_PHY_SWITCH_COM, tmp);
sys/dev/usb/if_otus.c
1738
tmp = letoh32(eep->antCtrlChain[0]);
sys/dev/usb/if_otus.c
1739
otus_write(sc, AR_PHY_SWITCH_CHAIN_0, tmp);
sys/dev/usb/if_otus.c
1741
tmp = letoh32(eep->antCtrlChain[1]);
sys/dev/usb/if_otus.c
1742
otus_write(sc, AR_PHY_SWITCH_CHAIN_0 + offset, tmp);
sys/dev/usb/if_otus.c
1745
tmp = otus_phy_get_def(sc, AR_PHY_SETTLING);
sys/dev/usb/if_otus.c
1746
tmp &= ~(0x7f << 7);
sys/dev/usb/if_otus.c
1747
tmp |= (eep->switchSettling & 0x7f) << 7;
sys/dev/usb/if_otus.c
1748
otus_write(sc, AR_PHY_SETTLING, tmp);
sys/dev/usb/if_otus.c
1751
tmp = otus_phy_get_def(sc, AR_PHY_DESIRED_SZ);
sys/dev/usb/if_otus.c
1752
tmp &= ~0xffff;
sys/dev/usb/if_otus.c
1753
tmp |= eep->pgaDesiredSize << 8 | eep->adcDesiredSize;
sys/dev/usb/if_otus.c
1754
otus_write(sc, AR_PHY_DESIRED_SZ, tmp);
sys/dev/usb/if_otus.c
1756
tmp = eep->txEndToXpaOff << 24 | eep->txEndToXpaOff << 16 |
sys/dev/usb/if_otus.c
1758
otus_write(sc, AR_PHY_RF_CTL4, tmp);
sys/dev/usb/if_otus.c
1760
tmp = otus_phy_get_def(sc, AR_PHY_RF_CTL3);
sys/dev/usb/if_otus.c
1761
tmp &= ~(0xff << 16);
sys/dev/usb/if_otus.c
1762
tmp |= eep->txEndToRxOn << 16;
sys/dev/usb/if_otus.c
1763
otus_write(sc, AR_PHY_RF_CTL3, tmp);
sys/dev/usb/if_otus.c
1765
tmp = otus_phy_get_def(sc, AR_PHY_CCA);
sys/dev/usb/if_otus.c
1766
tmp &= ~(0x7f << 12);
sys/dev/usb/if_otus.c
1767
tmp |= (eep->thresh62 & 0x7f) << 12;
sys/dev/usb/if_otus.c
1768
otus_write(sc, AR_PHY_CCA, tmp);
sys/dev/usb/if_otus.c
1770
tmp = otus_phy_get_def(sc, AR_PHY_RXGAIN);
sys/dev/usb/if_otus.c
1771
tmp &= ~(0x3f << 12);
sys/dev/usb/if_otus.c
1772
tmp |= (eep->txRxAttenCh[0] & 0x3f) << 12;
sys/dev/usb/if_otus.c
1773
otus_write(sc, AR_PHY_RXGAIN, tmp);
sys/dev/usb/if_otus.c
1775
tmp = otus_phy_get_def(sc, AR_PHY_RXGAIN + offset);
sys/dev/usb/if_otus.c
1776
tmp &= ~(0x3f << 12);
sys/dev/usb/if_otus.c
1777
tmp |= (eep->txRxAttenCh[1] & 0x3f) << 12;
sys/dev/usb/if_otus.c
1778
otus_write(sc, AR_PHY_RXGAIN + offset, tmp);
sys/dev/usb/if_otus.c
1780
tmp = otus_phy_get_def(sc, AR_PHY_GAIN_2GHZ);
sys/dev/usb/if_otus.c
1781
tmp &= ~(0x3f << 18);
sys/dev/usb/if_otus.c
1782
tmp |= (eep->rxTxMarginCh[0] & 0x3f) << 18;
sys/dev/usb/if_otus.c
1784
tmp &= ~(0xf << 10);
sys/dev/usb/if_otus.c
1785
tmp |= (eep->bswMargin[0] & 0xf) << 10;
sys/dev/usb/if_otus.c
1787
otus_write(sc, AR_PHY_GAIN_2GHZ, tmp);
sys/dev/usb/if_otus.c
1789
tmp = otus_phy_get_def(sc, AR_PHY_GAIN_2GHZ + offset);
sys/dev/usb/if_otus.c
1790
tmp &= ~(0x3f << 18);
sys/dev/usb/if_otus.c
1791
tmp |= (eep->rxTxMarginCh[1] & 0x3f) << 18;
sys/dev/usb/if_otus.c
1792
otus_write(sc, AR_PHY_GAIN_2GHZ + offset, tmp);
sys/dev/usb/if_otus.c
1794
tmp = otus_phy_get_def(sc, AR_PHY_TIMING_CTRL4);
sys/dev/usb/if_otus.c
1795
tmp &= ~(0x3f << 5 | 0x1f);
sys/dev/usb/if_otus.c
1796
tmp |= (eep->iqCalICh[0] & 0x3f) << 5 | (eep->iqCalQCh[0] & 0x1f);
sys/dev/usb/if_otus.c
1797
otus_write(sc, AR_PHY_TIMING_CTRL4, tmp);
sys/dev/usb/if_otus.c
1799
tmp = otus_phy_get_def(sc, AR_PHY_TIMING_CTRL4 + offset);
sys/dev/usb/if_otus.c
1800
tmp &= ~(0x3f << 5 | 0x1f);
sys/dev/usb/if_otus.c
1801
tmp |= (eep->iqCalICh[1] & 0x3f) << 5 | (eep->iqCalQCh[1] & 0x1f);
sys/dev/usb/if_otus.c
1802
otus_write(sc, AR_PHY_TIMING_CTRL4 + offset, tmp);
sys/dev/usb/if_otus.c
1804
tmp = otus_phy_get_def(sc, AR_PHY_TPCRG1);
sys/dev/usb/if_otus.c
1805
tmp &= ~(0xf << 16);
sys/dev/usb/if_otus.c
1806
tmp |= (eep->xpd & 0xf) << 16;
sys/dev/usb/if_otus.c
1807
otus_write(sc, AR_PHY_TPCRG1, tmp);
sys/dev/usb/if_otus.c
1926
uint32_t coeff, exp, man, tmp;
sys/dev/usb/if_otus.c
1933
tmp = IEEE80211_IS_CHAN_2GHZ(c) ? 0x105 : 0x104;
sys/dev/usb/if_otus.c
1934
otus_write(sc, AR_MAC_REG_DYNAMIC_SIFS_ACK, tmp);
sys/dev/usb/if_otus.c
1987
tmp = (sc->txmask == 0x5) ? 0x340 : 0x240;
sys/dev/usb/if_otus.c
1988
otus_write(sc, AR_PHY_TURBO, tmp);
sys/dev/usb/if_ral.c
1444
uint16_t tmp;
sys/dev/usb/if_ral.c
1456
tmp = reg << 8 | val;
sys/dev/usb/if_ral.c
1457
ural_write(sc, RAL_PHY_CSR7, tmp);
sys/dev/usb/if_ral.c
1483
uint32_t tmp;
sys/dev/usb/if_ral.c
1495
tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xfffff) << 2 | (reg & 0x3);
sys/dev/usb/if_ral.c
1496
ural_write(sc, RAL_PHY_CSR9, tmp & 0xffff);
sys/dev/usb/if_ral.c
1497
ural_write(sc, RAL_PHY_CSR10, tmp >> 16);
sys/dev/usb/if_ral.c
1509
uint8_t power, tmp;
sys/dev/usb/if_ral.c
1574
tmp = ural_bbp_read(sc, 70);
sys/dev/usb/if_ral.c
1576
tmp &= ~RAL_JAPAN_FILTER;
sys/dev/usb/if_ral.c
1578
tmp |= RAL_JAPAN_FILTER;
sys/dev/usb/if_ral.c
1580
ural_bbp_write(sc, 70, tmp);
sys/dev/usb/if_ral.c
1596
uint32_t tmp;
sys/dev/usb/if_ral.c
1599
tmp = sc->rf_regs[RAL_RF1] & ~RAL_RF1_AUTOTUNE;
sys/dev/usb/if_ral.c
1600
ural_rf_write(sc, RAL_RF1, tmp);
sys/dev/usb/if_ral.c
1603
tmp = sc->rf_regs[RAL_RF3] & ~RAL_RF3_AUTOTUNE;
sys/dev/usb/if_ral.c
1604
ural_rf_write(sc, RAL_RF3, tmp);
sys/dev/usb/if_ral.c
1617
uint16_t logcwmin, preload, tmp;
sys/dev/usb/if_ral.c
1622
tmp = (16 * ic->ic_bss->ni_intval) << 4;
sys/dev/usb/if_ral.c
1623
ural_write(sc, RAL_TXRX_CSR18, tmp);
sys/dev/usb/if_ral.c
1635
tmp = logcwmin << 12 | preload;
sys/dev/usb/if_ral.c
1636
ural_write(sc, RAL_TXRX_CSR20, tmp);
sys/dev/usb/if_ral.c
1639
tmp = RAL_ENABLE_TSF | RAL_ENABLE_TBCN;
sys/dev/usb/if_ral.c
1641
tmp |= RAL_ENABLE_TSF_SYNC(1);
sys/dev/usb/if_ral.c
1644
tmp |= RAL_ENABLE_TSF_SYNC(2) | RAL_ENABLE_BEACON_GENERATOR;
sys/dev/usb/if_ral.c
1646
ural_write(sc, RAL_TXRX_CSR19, tmp);
sys/dev/usb/if_ral.c
1680
uint16_t tmp;
sys/dev/usb/if_ral.c
1682
tmp = ural_read(sc, RAL_TXRX_CSR10);
sys/dev/usb/if_ral.c
1684
tmp &= ~RAL_SHORT_PREAMBLE;
sys/dev/usb/if_ral.c
1686
tmp |= RAL_SHORT_PREAMBLE;
sys/dev/usb/if_ral.c
1688
ural_write(sc, RAL_TXRX_CSR10, tmp);
sys/dev/usb/if_ral.c
1709
uint16_t tmp;
sys/dev/usb/if_ral.c
1711
tmp = bssid[0] | bssid[1] << 8;
sys/dev/usb/if_ral.c
1712
ural_write(sc, RAL_MAC_CSR5, tmp);
sys/dev/usb/if_ral.c
1714
tmp = bssid[2] | bssid[3] << 8;
sys/dev/usb/if_ral.c
1715
ural_write(sc, RAL_MAC_CSR6, tmp);
sys/dev/usb/if_ral.c
1717
tmp = bssid[4] | bssid[5] << 8;
sys/dev/usb/if_ral.c
1718
ural_write(sc, RAL_MAC_CSR7, tmp);
sys/dev/usb/if_ral.c
1726
uint16_t tmp;
sys/dev/usb/if_ral.c
1728
tmp = addr[0] | addr[1] << 8;
sys/dev/usb/if_ral.c
1729
ural_write(sc, RAL_MAC_CSR2, tmp);
sys/dev/usb/if_ral.c
1731
tmp = addr[2] | addr[3] << 8;
sys/dev/usb/if_ral.c
1732
ural_write(sc, RAL_MAC_CSR3, tmp);
sys/dev/usb/if_ral.c
1734
tmp = addr[4] | addr[5] << 8;
sys/dev/usb/if_ral.c
1735
ural_write(sc, RAL_MAC_CSR4, tmp);
sys/dev/usb/if_ral.c
1745
uint16_t tmp;
sys/dev/usb/if_ral.c
1747
tmp = ural_read(sc, RAL_TXRX_CSR2);
sys/dev/usb/if_ral.c
1749
tmp &= ~RAL_DROP_NOT_TO_ME;
sys/dev/usb/if_ral.c
1751
tmp |= RAL_DROP_NOT_TO_ME;
sys/dev/usb/if_ral.c
1753
ural_write(sc, RAL_TXRX_CSR2, tmp);
sys/dev/usb/if_ral.c
1838
uint16_t tmp;
sys/dev/usb/if_ral.c
1857
tmp = ural_read(sc, RAL_PHY_CSR5) & ~0x7;
sys/dev/usb/if_ral.c
1858
ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7));
sys/dev/usb/if_ral.c
1860
tmp = ural_read(sc, RAL_PHY_CSR6) & ~0x7;
sys/dev/usb/if_ral.c
1861
ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7));
sys/dev/usb/if_ral.c
1889
uint16_t tmp;
sys/dev/usb/if_ral.c
1901
tmp = ural_read(sc, RAL_MAC_CSR17);
sys/dev/usb/if_ral.c
1902
if ((tmp & (RAL_BBP_AWAKE | RAL_RF_AWAKE)) ==
sys/dev/usb/if_ral.c
2010
tmp = RAL_DROP_PHY_ERROR | RAL_DROP_CRC_ERROR;
sys/dev/usb/if_ral.c
2012
tmp |= RAL_DROP_CTL | RAL_DROP_VERSION_ERROR;
sys/dev/usb/if_ral.c
2016
tmp |= RAL_DROP_TODS;
sys/dev/usb/if_ral.c
2018
tmp |= RAL_DROP_NOT_TO_ME;
sys/dev/usb/if_ral.c
2020
ural_write(sc, RAL_TXRX_CSR2, tmp);
sys/dev/usb/if_rum.c
1410
uint32_t tmp = htole32(val);
sys/dev/usb/if_rum.c
1412
rum_write_multi(sc, reg, &tmp, sizeof tmp);
sys/dev/usb/if_rum.c
1442
uint32_t tmp;
sys/dev/usb/if_rum.c
1454
tmp = RT2573_BBP_BUSY | (reg & 0x7f) << 8 | val;
sys/dev/usb/if_rum.c
1455
rum_write(sc, RT2573_PHY_CSR3, tmp);
sys/dev/usb/if_rum.c
1490
uint32_t tmp;
sys/dev/usb/if_rum.c
1502
tmp = RT2573_RF_BUSY | RT2573_RF_20BIT | (val & 0xfffff) << 2 |
sys/dev/usb/if_rum.c
1504
rum_write(sc, RT2573_PHY_CSR4, tmp);
sys/dev/usb/if_rum.c
1516
uint32_t tmp;
sys/dev/usb/if_rum.c
1524
tmp = rum_read(sc, RT2573_TXRX_CSR0);
sys/dev/usb/if_rum.c
1525
rum_write(sc, RT2573_TXRX_CSR0, tmp | RT2573_DISABLE_RX);
sys/dev/usb/if_rum.c
1530
rum_write(sc, RT2573_TXRX_CSR0, tmp);
sys/dev/usb/if_rum.c
1541
uint32_t tmp;
sys/dev/usb/if_rum.c
1543
tmp = rum_read(sc, RT2573_TXRX_CSR4);
sys/dev/usb/if_rum.c
1545
tmp &= ~RT2573_MRR_CCK_FALLBACK;
sys/dev/usb/if_rum.c
1547
tmp |= RT2573_MRR_CCK_FALLBACK;
sys/dev/usb/if_rum.c
1548
tmp |= RT2573_MRR_ENABLED;
sys/dev/usb/if_rum.c
1550
rum_write(sc, RT2573_TXRX_CSR4, tmp);
sys/dev/usb/if_rum.c
1556
uint32_t tmp;
sys/dev/usb/if_rum.c
1558
tmp = rum_read(sc, RT2573_TXRX_CSR4);
sys/dev/usb/if_rum.c
1560
tmp &= ~RT2573_SHORT_PREAMBLE;
sys/dev/usb/if_rum.c
1562
tmp |= RT2573_SHORT_PREAMBLE;
sys/dev/usb/if_rum.c
1564
rum_write(sc, RT2573_TXRX_CSR4, tmp);
sys/dev/usb/if_rum.c
1593
uint32_t tmp;
sys/dev/usb/if_rum.c
1623
tmp = rum_read(sc, RT2573_PHY_CSR0);
sys/dev/usb/if_rum.c
1624
tmp &= ~(RT2573_PA_PE_2GHZ | RT2573_PA_PE_5GHZ);
sys/dev/usb/if_rum.c
1626
tmp |= RT2573_PA_PE_2GHZ;
sys/dev/usb/if_rum.c
1628
tmp |= RT2573_PA_PE_5GHZ;
sys/dev/usb/if_rum.c
1629
rum_write(sc, RT2573_PHY_CSR0, tmp);
sys/dev/usb/if_rum.c
1713
uint32_t tmp;
sys/dev/usb/if_rum.c
1725
tmp = rum_read(sc, RT2573_TXRX_CSR9) & 0xff000000;
sys/dev/usb/if_rum.c
1728
tmp |= ic->ic_bss->ni_intval * 16;
sys/dev/usb/if_rum.c
1730
tmp |= RT2573_TSF_TICKING | RT2573_ENABLE_TBTT;
sys/dev/usb/if_rum.c
1732
tmp |= RT2573_TSF_MODE(1);
sys/dev/usb/if_rum.c
1735
tmp |= RT2573_TSF_MODE(2) | RT2573_GENERATE_BEACON;
sys/dev/usb/if_rum.c
1737
rum_write(sc, RT2573_TXRX_CSR9, tmp);
sys/dev/usb/if_rum.c
1745
uint32_t tmp;
sys/dev/usb/if_rum.c
1750
tmp = rum_read(sc, RT2573_MAC_CSR9);
sys/dev/usb/if_rum.c
1751
tmp = (tmp & ~0xff) | slottime;
sys/dev/usb/if_rum.c
1752
rum_write(sc, RT2573_MAC_CSR9, tmp);
sys/dev/usb/if_rum.c
1760
uint32_t tmp;
sys/dev/usb/if_rum.c
1762
tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24;
sys/dev/usb/if_rum.c
1763
rum_write(sc, RT2573_MAC_CSR4, tmp);
sys/dev/usb/if_rum.c
1765
tmp = bssid[4] | bssid[5] << 8 | RT2573_ONE_BSSID << 16;
sys/dev/usb/if_rum.c
1766
rum_write(sc, RT2573_MAC_CSR5, tmp);
sys/dev/usb/if_rum.c
1772
uint32_t tmp;
sys/dev/usb/if_rum.c
1774
tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24;
sys/dev/usb/if_rum.c
1775
rum_write(sc, RT2573_MAC_CSR2, tmp);
sys/dev/usb/if_rum.c
1777
tmp = addr[4] | addr[5] << 8 | 0xff << 16;
sys/dev/usb/if_rum.c
1778
rum_write(sc, RT2573_MAC_CSR3, tmp);
sys/dev/usb/if_rum.c
1785
uint32_t tmp;
sys/dev/usb/if_rum.c
1787
tmp = rum_read(sc, RT2573_TXRX_CSR0);
sys/dev/usb/if_rum.c
1789
tmp &= ~RT2573_DROP_NOT_TO_ME;
sys/dev/usb/if_rum.c
1791
tmp |= RT2573_DROP_NOT_TO_ME;
sys/dev/usb/if_rum.c
1793
rum_write(sc, RT2573_TXRX_CSR0, tmp);
sys/dev/usb/if_rum.c
1923
uint32_t tmp;
sys/dev/usb/if_rum.c
2030
tmp = rum_read(sc, RT2573_TXRX_CSR0) & 0xffff;
sys/dev/usb/if_rum.c
2032
tmp |= RT2573_DROP_PHY_ERROR | RT2573_DROP_CRC_ERROR;
sys/dev/usb/if_rum.c
2034
tmp |= RT2573_DROP_CTL | RT2573_DROP_VER_ERROR |
sys/dev/usb/if_rum.c
2039
tmp |= RT2573_DROP_TODS;
sys/dev/usb/if_rum.c
2041
tmp |= RT2573_DROP_NOT_TO_ME;
sys/dev/usb/if_rum.c
2043
rum_write(sc, RT2573_TXRX_CSR0, tmp);
sys/dev/usb/if_rum.c
2064
uint32_t tmp;
sys/dev/usb/if_rum.c
2074
tmp = rum_read(sc, RT2573_TXRX_CSR0);
sys/dev/usb/if_rum.c
2075
rum_write(sc, RT2573_TXRX_CSR0, tmp | RT2573_DISABLE_RX);
sys/dev/usb/if_rum.c
266
uint32_t tmp;
sys/dev/usb/if_rum.c
306
if ((tmp = rum_read(sc, RT2573_MAC_CSR0)) != 0)
sys/dev/usb/if_rum.c
320
sc->sc_dev.dv_xname, sc->macbbp_rev, tmp,
sys/dev/usb/if_rum.c
620
uint32_t tmp;
sys/dev/usb/if_rum.c
631
tmp = rum_read(sc, RT2573_TXRX_CSR9);
sys/dev/usb/if_rum.c
632
rum_write(sc, RT2573_TXRX_CSR9, tmp & ~0x00ffffff);
sys/dev/usb/if_run.c
1004
tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK);
sys/dev/usb/if_run.c
1005
tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK;
sys/dev/usb/if_run.c
1006
run_write(sc, RT3070_EFUSE_CTRL, tmp);
sys/dev/usb/if_run.c
1008
if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0)
sys/dev/usb/if_run.c
1010
if (!(tmp & RT3070_EFSROM_KICK))
sys/dev/usb/if_run.c
1017
if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) {
sys/dev/usb/if_run.c
1023
if ((error = run_read(sc, reg, &tmp)) != 0)
sys/dev/usb/if_run.c
1026
tmp >>= (8 * (addr & 0x3));
sys/dev/usb/if_run.c
1027
*val = (addr & 1) ? tmp >> 16 : tmp & 0xffff;
sys/dev/usb/if_run.c
1035
uint32_t tmp;
sys/dev/usb/if_run.c
1039
if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0)
sys/dev/usb/if_run.c
1050
tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK);
sys/dev/usb/if_run.c
1051
tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK;
sys/dev/usb/if_run.c
1052
run_write(sc, RT3070_EFUSE_CTRL, tmp);
sys/dev/usb/if_run.c
1054
if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0)
sys/dev/usb/if_run.c
1056
if (!(tmp & RT3070_EFSROM_KICK))
sys/dev/usb/if_run.c
1063
if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) {
sys/dev/usb/if_run.c
1069
if ((error = run_read(sc, reg, &tmp)) != 0)
sys/dev/usb/if_run.c
1072
*val = (addr & 2) ? tmp >> 16 : tmp & 0xffff;
sys/dev/usb/if_run.c
1080
uint16_t tmp;
sys/dev/usb/if_run.c
1088
USETW(req.wLength, sizeof tmp);
sys/dev/usb/if_run.c
1089
error = usbd_do_request(sc->sc_udev, &req, &tmp);
sys/dev/usb/if_run.c
1091
*val = letoh16(tmp);
sys/dev/usb/if_run.c
1107
uint32_t tmp;
sys/dev/usb/if_run.c
1111
if ((error = run_read(sc, RT2860_RF_CSR_CFG0, &tmp)) != 0)
sys/dev/usb/if_run.c
1113
if (!(tmp & RT2860_RF_REG_CTRL))
sys/dev/usb/if_run.c
1120
tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT |
sys/dev/usb/if_run.c
1122
return run_write(sc, RT2860_RF_CSR_CFG0, tmp);
sys/dev/usb/if_run.c
1128
uint32_t tmp;
sys/dev/usb/if_run.c
1132
if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0)
sys/dev/usb/if_run.c
1134
if (!(tmp & RT3070_RF_KICK))
sys/dev/usb/if_run.c
1140
tmp = RT3070_RF_KICK | reg << 8;
sys/dev/usb/if_run.c
1141
if ((error = run_write(sc, RT3070_RF_CSR_CFG, tmp)) != 0)
sys/dev/usb/if_run.c
1145
if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0)
sys/dev/usb/if_run.c
1147
if (!(tmp & RT3070_RF_KICK))
sys/dev/usb/if_run.c
1153
*val = tmp & 0xff;
sys/dev/usb/if_run.c
1160
uint32_t tmp;
sys/dev/usb/if_run.c
1164
if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0)
sys/dev/usb/if_run.c
1166
if (!(tmp & RT3070_RF_KICK))
sys/dev/usb/if_run.c
1172
tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val;
sys/dev/usb/if_run.c
1173
return run_write(sc, RT3070_RF_CSR_CFG, tmp);
sys/dev/usb/if_run.c
1179
uint32_t tmp;
sys/dev/usb/if_run.c
1183
if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0)
sys/dev/usb/if_run.c
1185
if (!(tmp & RT2860_BBP_CSR_KICK))
sys/dev/usb/if_run.c
1191
tmp = RT2860_BBP_CSR_READ | RT2860_BBP_CSR_KICK | reg << 8;
sys/dev/usb/if_run.c
1192
if ((error = run_write(sc, RT2860_BBP_CSR_CFG, tmp)) != 0)
sys/dev/usb/if_run.c
1196
if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0)
sys/dev/usb/if_run.c
1198
if (!(tmp & RT2860_BBP_CSR_KICK))
sys/dev/usb/if_run.c
1204
*val = tmp & 0xff;
sys/dev/usb/if_run.c
1211
uint32_t tmp;
sys/dev/usb/if_run.c
1215
if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0)
sys/dev/usb/if_run.c
1217
if (!(tmp & RT2860_BBP_CSR_KICK))
sys/dev/usb/if_run.c
1223
tmp = RT2860_BBP_CSR_KICK | reg << 8 | val;
sys/dev/usb/if_run.c
1224
return run_write(sc, RT2860_BBP_CSR_CFG, tmp);
sys/dev/usb/if_run.c
1233
uint32_t tmp;
sys/dev/usb/if_run.c
1237
if ((error = run_read(sc, RT2860_H2M_MAILBOX, &tmp)) != 0)
sys/dev/usb/if_run.c
1239
if (!(tmp & RT2860_H2M_BUSY))
sys/dev/usb/if_run.c
1245
tmp = RT2860_H2M_BUSY | RT2860_TOKEN_NO_INTR << 16 | arg;
sys/dev/usb/if_run.c
1246
if ((error = run_write(sc, RT2860_H2M_MAILBOX, tmp)) == 0)
sys/dev/usb/if_run.c
1417
uint32_t tmp;
sys/dev/usb/if_run.c
1424
run_read(sc, RT3070_EFUSE_CTRL, &tmp);
sys/dev/usb/if_run.c
1425
DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp));
sys/dev/usb/if_run.c
1426
if (tmp & RT3070_SEL_EFUSE || sc->mac_ver == 0x3593)
sys/dev/usb/if_run.c
1786
uint32_t tmp, sta[3];
sys/dev/usb/if_run.c
1802
run_read(sc, RT2860_BCN_TIME_CFG, &tmp);
sys/dev/usb/if_run.c
1804
tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN |
sys/dev/usb/if_run.c
2756
uint32_t tmp;
sys/dev/usb/if_run.c
2835
run_read(sc, RT2860_TX_BAND_CFG, &tmp);
sys/dev/usb/if_run.c
2836
tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P);
sys/dev/usb/if_run.c
2837
tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P;
sys/dev/usb/if_run.c
2838
run_write(sc, RT2860_TX_BAND_CFG, tmp);
sys/dev/usb/if_run.c
2841
tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN;
sys/dev/usb/if_run.c
2843
tmp |= 1 << 29 | 1 << 28;
sys/dev/usb/if_run.c
2845
tmp |= RT2860_LNA_PE1_EN;
sys/dev/usb/if_run.c
2847
tmp |= RT2860_PA_PE_G0_EN;
sys/dev/usb/if_run.c
2849
tmp |= RT2860_PA_PE_G1_EN;
sys/dev/usb/if_run.c
2852
tmp |= 1 << 25;
sys/dev/usb/if_run.c
2855
tmp |= RT2860_PA_PE_A0_EN;
sys/dev/usb/if_run.c
2857
tmp |= RT2860_PA_PE_A1_EN;
sys/dev/usb/if_run.c
2861
run_write(sc, RT2860_TX_PIN_CFG, tmp);
sys/dev/usb/if_run.c
2864
run_write(sc, RT2860_TX_PIN_CFG, tmp);
sys/dev/usb/if_run.c
2872
run_read(sc, RT2860_GPIO_CTRL, &tmp);
sys/dev/usb/if_run.c
2873
tmp &= ~0x01010000;
sys/dev/usb/if_run.c
2875
tmp |= 0x00010000;
sys/dev/usb/if_run.c
2876
tmp = (tmp & ~0x00009090) | 0x00000090;
sys/dev/usb/if_run.c
2877
run_write(sc, RT2860_GPIO_CTRL, tmp);
sys/dev/usb/if_run.c
3023
uint32_t tmp;
sys/dev/usb/if_run.c
3157
run_read(sc, RT2860_GPIO_CTRL, &tmp);
sys/dev/usb/if_run.c
3158
tmp &= ~0x8080;
sys/dev/usb/if_run.c
3160
tmp |= 0x80;
sys/dev/usb/if_run.c
3161
run_write(sc, RT2860_GPIO_CTRL, tmp);
sys/dev/usb/if_run.c
3446
uint32_t tmp;
sys/dev/usb/if_run.c
3451
run_read(sc, RT5592_DEBUG_INDEX, &tmp);
sys/dev/usb/if_run.c
3452
freqs = (tmp & RT5592_SEL_XTAL) ?
sys/dev/usb/if_run.c
3463
run_read(sc, RT3070_LDO_CFG0, &tmp);
sys/dev/usb/if_run.c
3464
tmp &= ~0x1c000000;
sys/dev/usb/if_run.c
3466
tmp |= 0x14000000;
sys/dev/usb/if_run.c
3467
run_write(sc, RT3070_LDO_CFG0, tmp);
sys/dev/usb/if_run.c
3599
uint32_t tmp;
sys/dev/usb/if_run.c
3608
run_read(sc, RT2860_GPIO_CTRL, &tmp);
sys/dev/usb/if_run.c
3609
run_write(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08);
sys/dev/usb/if_run.c
3617
run_read(sc, RT2860_GPIO_CTRL, &tmp);
sys/dev/usb/if_run.c
3618
run_write(sc, RT2860_GPIO_CTRL, tmp & ~0x0808);
sys/dev/usb/if_run.c
3672
uint32_t tmp;
sys/dev/usb/if_run.c
3674
run_read(sc, RT2860_BCN_TIME_CFG, &tmp);
sys/dev/usb/if_run.c
3675
tmp &= ~0x1fffff;
sys/dev/usb/if_run.c
3676
tmp |= ic->ic_bss->ni_intval * 16;
sys/dev/usb/if_run.c
3677
tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN;
sys/dev/usb/if_run.c
3679
tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT;
sys/dev/usb/if_run.c
3680
run_write(sc, RT2860_BCN_TIME_CFG, tmp);
sys/dev/usb/if_run.c
3710
uint32_t tmp;
sys/dev/usb/if_run.c
3712
run_read(sc, RT2860_AUTO_RSP_CFG, &tmp);
sys/dev/usb/if_run.c
3714
tmp |= RT2860_CCK_SHORT_EN;
sys/dev/usb/if_run.c
3716
tmp &= ~RT2860_CCK_SHORT_EN;
sys/dev/usb/if_run.c
3717
run_write(sc, RT2860_AUTO_RSP_CFG, tmp);
sys/dev/usb/if_run.c
3769
uint32_t tmp;
sys/dev/usb/if_run.c
3771
run_read(sc, RT2860_BKOFF_SLOT_CFG, &tmp);
sys/dev/usb/if_run.c
3772
tmp &= ~0xff;
sys/dev/usb/if_run.c
3773
tmp |= (sc->sc_ic.ic_flags & IEEE80211_F_SHSLOT) ?
sys/dev/usb/if_run.c
3775
run_write(sc, RT2860_BKOFF_SLOT_CFG, tmp);
sys/dev/usb/if_run.c
3915
uint32_t tmp;
sys/dev/usb/if_run.c
3943
run_read(sc, RT3070_LDO_CFG0, &tmp);
sys/dev/usb/if_run.c
3944
tmp = (tmp & ~0x0f000000) | 0x0d000000;
sys/dev/usb/if_run.c
3945
run_write(sc, RT3070_LDO_CFG0, tmp);
sys/dev/usb/if_run.c
3952
run_read(sc, RT3070_LDO_CFG0, &tmp);
sys/dev/usb/if_run.c
3953
tmp &= ~0x1f000000;
sys/dev/usb/if_run.c
3955
tmp |= 0x0d000000; /* 1.35V */
sys/dev/usb/if_run.c
3957
tmp |= 0x01000000; /* 1.2V */
sys/dev/usb/if_run.c
3958
run_write(sc, RT3070_LDO_CFG0, tmp);
sys/dev/usb/if_run.c
3961
run_read(sc, RT3070_GPIO_SWITCH, &tmp);
sys/dev/usb/if_run.c
3962
run_write(sc, RT3070_GPIO_SWITCH, tmp & ~0x20);
sys/dev/usb/if_run.c
3968
run_read(sc, RT3070_LDO_CFG0, &tmp);
sys/dev/usb/if_run.c
3969
tmp = (tmp & ~0x1f000000) | 0x0d000000;
sys/dev/usb/if_run.c
3970
run_write(sc, RT3070_LDO_CFG0, tmp);
sys/dev/usb/if_run.c
3975
tmp = (tmp & ~0x1f000000) | 0x01000000;
sys/dev/usb/if_run.c
3976
run_write(sc, RT3070_LDO_CFG0, tmp);
sys/dev/usb/if_run.c
4012
run_read(sc, RT3070_OPT_14, &tmp);
sys/dev/usb/if_run.c
4013
run_write(sc, RT3070_OPT_14, tmp | 1);
sys/dev/usb/if_run.c
4056
uint32_t tmp;
sys/dev/usb/if_run.c
4061
run_read(sc, RT3070_GPIO_SWITCH, &tmp);
sys/dev/usb/if_run.c
4062
tmp &= ~(1 << 4 | 1 << 7);
sys/dev/usb/if_run.c
4063
run_write(sc, RT3070_GPIO_SWITCH, tmp);
sys/dev/usb/if_run.c
4084
run_read(sc, RT3070_LDO_CFG0, &tmp);
sys/dev/usb/if_run.c
4085
tmp = (tmp & ~0x1f000000) | 0x0d000000;
sys/dev/usb/if_run.c
4086
run_write(sc, RT3070_LDO_CFG0, tmp);
sys/dev/usb/if_run.c
4088
tmp = (tmp & ~0x1f000000) | 0x01000000;
sys/dev/usb/if_run.c
4089
run_write(sc, RT3070_LDO_CFG0, tmp);
sys/dev/usb/if_run.c
4098
run_read(sc, RT3070_OPT_14, &tmp);
sys/dev/usb/if_run.c
4099
run_write(sc, RT3070_OPT_14, tmp | 1);
sys/dev/usb/if_run.c
4105
uint32_t tmp;
sys/dev/usb/if_run.c
4162
run_read(sc, RT3070_OPT_14, &tmp);
sys/dev/usb/if_run.c
4163
run_write(sc, RT3070_OPT_14, tmp | 1);
sys/dev/usb/if_run.c
4430
uint32_t tmp;
sys/dev/usb/if_run.c
4435
if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0)
sys/dev/usb/if_run.c
4437
if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
sys/dev/usb/if_run.c
4446
tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | RT2860_TX_WB_DDONE;
sys/dev/usb/if_run.c
4447
run_write(sc, RT2860_WPDMA_GLO_CFG, tmp);
sys/dev/usb/if_run.c
4450
tmp = RT2860_USB_TX_EN | RT2860_USB_RX_EN | RT2860_USB_RX_AGG_EN |
sys/dev/usb/if_run.c
4452
run_write(sc, RT2860_USB_DMA_CFG, tmp);
sys/dev/usb/if_run.c
4455
tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR;
sys/dev/usb/if_run.c
4457
tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL |
sys/dev/usb/if_run.c
4462
tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL;
sys/dev/usb/if_run.c
4464
run_write(sc, RT2860_RX_FILTR_CFG, tmp);
sys/dev/usb/if_run.c
4475
uint8_t rf, tmp;
sys/dev/usb/if_run.c
4478
tmp = rf;
sys/dev/usb/if_run.c
4482
if (tmp != rf)
sys/dev/usb/if_run.c
4483
run_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf);
sys/dev/usb/if_run.c
4491
uint32_t tmp;
sys/dev/usb/if_run.c
4499
if ((error = run_read(sc, RT2860_ASIC_VER_ID, &tmp)) != 0)
sys/dev/usb/if_run.c
4501
if (tmp != 0 && tmp != 0xffffffff)
sys/dev/usb/if_run.c
4532
if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0)
sys/dev/usb/if_run.c
4534
if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
sys/dev/usb/if_run.c
4544
tmp &= 0xff0;
sys/dev/usb/if_run.c
4545
tmp |= RT2860_TX_WB_DDONE;
sys/dev/usb/if_run.c
4546
run_write(sc, RT2860_WPDMA_GLO_CFG, tmp);
sys/dev/usb/if_run.c
4549
run_read(sc, RT2860_SYS_CTRL, &tmp);
sys/dev/usb/if_run.c
4550
run_write(sc, RT2860_SYS_CTRL, tmp & ~RT2860_PME_OEN);
sys/dev/usb/if_run.c
4600
if ((error = run_read(sc, RT2860_MAC_STATUS_REG, &tmp)) != 0)
sys/dev/usb/if_run.c
4602
if (!(tmp & (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY)))
sys/dev/usb/if_run.c
4622
run_read(sc, RT2860_BCN_TIME_CFG, &tmp);
sys/dev/usb/if_run.c
4623
tmp &= ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN |
sys/dev/usb/if_run.c
4625
run_write(sc, RT2860_BCN_TIME_CFG, tmp);
sys/dev/usb/if_run.c
4636
run_read(sc, RT2860_US_CYC_CNT, &tmp);
sys/dev/usb/if_run.c
4637
tmp = (tmp & ~0xff) | 0x1e;
sys/dev/usb/if_run.c
4638
run_write(sc, RT2860_US_CYC_CNT, tmp);
sys/dev/usb/if_run.c
4740
uint32_t tmp;
sys/dev/usb/if_run.c
4761
run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp);
sys/dev/usb/if_run.c
4762
tmp &= ~(RT2860_RX_DMA_EN | RT2860_TX_DMA_EN);
sys/dev/usb/if_run.c
4763
run_write(sc, RT2860_WPDMA_GLO_CFG, tmp);
sys/dev/usb/if_run.c
4766
if (run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp) != 0)
sys/dev/usb/if_run.c
4768
if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
sys/dev/usb/if_run.c
4778
run_read(sc, RT2860_MAC_SYS_CTRL, &tmp);
sys/dev/usb/if_run.c
4779
tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
sys/dev/usb/if_run.c
4780
run_write(sc, RT2860_MAC_SYS_CTRL, tmp);
sys/dev/usb/if_run.c
4784
if (run_read(sc, RT2860_TXRXQ_PCNT, &tmp) != 0)
sys/dev/usb/if_run.c
4786
if ((tmp & RT2860_TX2Q_PCNT_MASK) == 0)
sys/dev/usb/if_run.c
826
uint32_t tmp;
sys/dev/usb/if_run.c
872
if ((error = run_read(sc, RT2860_SYS_CTRL, &tmp)) != 0)
sys/dev/usb/if_run.c
874
if (tmp & RT2860_MCU_READY)
sys/dev/usb/if_run.c
903
uint32_t tmp;
sys/dev/usb/if_run.c
906
error = run_read_region_1(sc, reg, (uint8_t *)&tmp, sizeof tmp);
sys/dev/usb/if_run.c
908
*val = letoh32(tmp);
sys/dev/usb/if_run.c
990
uint32_t tmp;
sys/dev/usb/if_run.c
994
if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0)
sys/dev/usb/if_uath.c
1567
uint32_t tmp;
sys/dev/usb/if_uath.c
1579
error = uath_read_eeprom(sc, UATH_EEPROM_RXBUFSZ, &tmp);
sys/dev/usb/if_uath.c
1585
sc->rxbufsz = betoh32(tmp) & 0xfff;
sys/dev/usb/if_urtw.c
1085
uint16_t o1, o2, o3, tmp;
sys/dev/usb/if_urtw.c
1148
urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp);
sys/dev/usb/if_urtw.c
1149
value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0);
sys/dev/usb/if_zyd.c
1158
uint32_t tmp;
sys/dev/usb/if_zyd.c
1175
(void)zyd_read32(sc, ZYD_CR_RADIO_PD, &tmp);
sys/dev/usb/if_zyd.c
1176
(void)zyd_write32(sc, ZYD_CR_RADIO_PD, tmp & ~1);
sys/dev/usb/if_zyd.c
1177
(void)zyd_write32(sc, ZYD_CR_RADIO_PD, tmp | 1);
sys/dev/usb/if_zyd.c
1199
uint32_t tmp;
sys/dev/usb/if_zyd.c
1203
(void)zyd_read32(sc, ZYD_CR_RADIO_PD, &tmp);
sys/dev/usb/if_zyd.c
1204
(void)zyd_write32(sc, ZYD_CR_RADIO_PD, tmp & ~1);
sys/dev/usb/if_zyd.c
1205
(void)zyd_write32(sc, ZYD_CR_RADIO_PD, tmp | 1);
sys/dev/usb/if_zyd.c
1274
uint16_t tmp;
sys/dev/usb/if_zyd.c
1283
(void)zyd_read16(sc, ZYD_CR203, &tmp);
sys/dev/usb/if_zyd.c
1284
(void)zyd_write16(sc, ZYD_CR203, tmp & ~(1 << 4));
sys/dev/usb/if_zyd.c
1291
(void)zyd_read16(sc, ZYD_CR203, &tmp);
sys/dev/usb/if_zyd.c
1292
(void)zyd_write16(sc, ZYD_CR203, tmp | (1 << 4));
sys/dev/usb/if_zyd.c
1314
uint16_t tmp;
sys/dev/usb/if_zyd.c
1328
(void)zyd_read16(sc, ZYD_CR203, &tmp);
sys/dev/usb/if_zyd.c
1329
(void)zyd_write16(sc, ZYD_CR203, tmp & ~(1 << 4));
sys/dev/usb/if_zyd.c
1340
(void)zyd_read16(sc, ZYD_CR203, &tmp);
sys/dev/usb/if_zyd.c
1341
(void)zyd_write16(sc, ZYD_CR203, tmp | (1 << 4));
sys/dev/usb/if_zyd.c
1355
uint16_t tmp;
sys/dev/usb/if_zyd.c
1364
(void)zyd_read16(sc, ZYD_CR203, &tmp);
sys/dev/usb/if_zyd.c
1365
(void)zyd_write16(sc, ZYD_CR203, tmp & ~(1 << 4));
sys/dev/usb/if_zyd.c
1372
(void)zyd_read16(sc, ZYD_CR203, &tmp);
sys/dev/usb/if_zyd.c
1373
(void)zyd_write16(sc, ZYD_CR203, tmp | (1 << 4));
sys/dev/usb/if_zyd.c
1395
uint16_t tmp;
sys/dev/usb/if_zyd.c
1409
(void)zyd_read16(sc, ZYD_CR203, &tmp);
sys/dev/usb/if_zyd.c
1410
(void)zyd_write16(sc, ZYD_CR203, tmp & ~(1 << 4));
sys/dev/usb/if_zyd.c
1421
(void)zyd_read16(sc, ZYD_CR203, &tmp);
sys/dev/usb/if_zyd.c
1422
(void)zyd_write16(sc, ZYD_CR203, tmp | (1 << 4));
sys/dev/usb/if_zyd.c
1506
uint32_t tmp;
sys/dev/usb/if_zyd.c
1532
if (zyd_read32(sc, ZYD_EEPROM_PHY_REG, &tmp) == 0)
sys/dev/usb/if_zyd.c
1533
(void)zyd_write32(sc, ZYD_CR157, tmp >> 8);
sys/dev/usb/if_zyd.c
1593
uint32_t tmp;
sys/dev/usb/if_zyd.c
1598
(void)zyd_read32(sc, ZYD_EEPROM_MAC_ADDR_P1, &tmp);
sys/dev/usb/if_zyd.c
1599
ic->ic_myaddr[0] = tmp & 0xff;
sys/dev/usb/if_zyd.c
1600
ic->ic_myaddr[1] = tmp >> 8;
sys/dev/usb/if_zyd.c
1601
ic->ic_myaddr[2] = tmp >> 16;
sys/dev/usb/if_zyd.c
1602
ic->ic_myaddr[3] = tmp >> 24;
sys/dev/usb/if_zyd.c
1603
(void)zyd_read32(sc, ZYD_EEPROM_MAC_ADDR_P2, &tmp);
sys/dev/usb/if_zyd.c
1604
ic->ic_myaddr[4] = tmp & 0xff;
sys/dev/usb/if_zyd.c
1605
ic->ic_myaddr[5] = tmp >> 8;
sys/dev/usb/if_zyd.c
1607
(void)zyd_read32(sc, ZYD_EEPROM_POD, &tmp);
sys/dev/usb/if_zyd.c
1608
sc->rf_rev = tmp & 0x0f;
sys/dev/usb/if_zyd.c
1609
sc->fix_cr47 = (tmp >> 8 ) & 0x01;
sys/dev/usb/if_zyd.c
1610
sc->fix_cr157 = (tmp >> 13) & 0x01;
sys/dev/usb/if_zyd.c
1611
sc->pa_rev = (tmp >> 16) & 0x0f;
sys/dev/usb/if_zyd.c
1614
(void)zyd_read32(sc, ZYD_EEPROM_SUBID, &tmp);
sys/dev/usb/if_zyd.c
1615
sc->regdomain = tmp >> 16;
sys/dev/usb/if_zyd.c
1680
uint32_t tmp;
sys/dev/usb/if_zyd.c
1682
tmp = addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0];
sys/dev/usb/if_zyd.c
1683
(void)zyd_write32(sc, ZYD_MAC_MACADRL, tmp);
sys/dev/usb/if_zyd.c
1685
tmp = addr[5] << 8 | addr[4];
sys/dev/usb/if_zyd.c
1686
(void)zyd_write32(sc, ZYD_MAC_MACADRH, tmp);
sys/dev/usb/if_zyd.c
1692
uint32_t tmp;
sys/dev/usb/if_zyd.c
1694
tmp = addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0];
sys/dev/usb/if_zyd.c
1695
(void)zyd_write32(sc, ZYD_MAC_BSSADRL, tmp);
sys/dev/usb/if_zyd.c
1697
tmp = addr[5] << 8 | addr[4];
sys/dev/usb/if_zyd.c
1698
(void)zyd_write32(sc, ZYD_MAC_BSSADRH, tmp);
sys/dev/usb/if_zyd.c
1717
uint32_t tmp;
sys/dev/usb/if_zyd.c
1719
(void)zyd_read32(sc, ZYD_MAC_TX_PE_CONTROL, &tmp);
sys/dev/usb/if_zyd.c
1720
tmp &= ~which;
sys/dev/usb/if_zyd.c
1722
tmp |= which;
sys/dev/usb/if_zyd.c
1723
(void)zyd_write32(sc, ZYD_MAC_TX_PE_CONTROL, tmp);
sys/dev/usb/if_zyd.c
1756
uint32_t tmp;
sys/dev/usb/if_zyd.c
1783
if (zyd_read32(sc, ZYD_EEPROM_PHY_REG, &tmp) == 0)
sys/dev/usb/if_zyd.c
1784
(void)zyd_write16(sc, ZYD_CR47, tmp & 0xff);
sys/dev/usb/if_zyd.c
900
uint32_t tmp;
sys/dev/usb/if_zyd.c
902
(void)zyd_read32(sc, ZYD_MAC_MISC, &tmp);
sys/dev/usb/if_zyd.c
903
tmp &= ~ZYD_UNLOCK_PHY_REGS;
sys/dev/usb/if_zyd.c
904
(void)zyd_write32(sc, ZYD_MAC_MISC, tmp);
sys/dev/usb/if_zyd.c
910
uint32_t tmp;
sys/dev/usb/if_zyd.c
912
(void)zyd_read32(sc, ZYD_MAC_MISC, &tmp);
sys/dev/usb/if_zyd.c
913
tmp |= ZYD_UNLOCK_PHY_REGS;
sys/dev/usb/if_zyd.c
914
(void)zyd_write32(sc, ZYD_MAC_MISC, tmp);
sys/dev/usb/uhidpp.c
765
struct uhidpp_notification *tmp = &sc->sc_notifications[i];
sys/dev/usb/uhidpp.c
767
if (tmp->n_id > 0)
sys/dev/usb/uhidpp.c
770
ntf = tmp;
sys/dev/usb/uhidpp.c
791
struct uhidpp_notification *tmp = &sc->sc_notifications[i];
sys/dev/usb/uhidpp.c
793
if (tmp->n_id > 0 && (ntf == NULL || tmp->n_id < ntf->n_id))
sys/dev/usb/uhidpp.c
794
ntf = tmp;
sys/dev/usb/uvideo.c
1965
uint16_t tmp;
sys/dev/usb/uvideo.c
1970
tmp = VS_PROBE_CONTROL;
sys/dev/usb/uvideo.c
1971
tmp = tmp << 8;
sys/dev/usb/uvideo.c
1972
USETW(req.wValue, tmp);
sys/dev/usb/uvideo.c
2010
uint16_t tmp;
sys/dev/usb/uvideo.c
2016
tmp = VS_PROBE_CONTROL;
sys/dev/usb/uvideo.c
2017
tmp = tmp << 8;
sys/dev/usb/uvideo.c
2018
USETW(req.wValue, tmp);
sys/dev/usb/uvideo.c
2099
uint16_t tmp;
sys/dev/usb/uvideo.c
2103
tmp = VS_COMMIT_CONTROL;
sys/dev/usb/uvideo.c
2104
tmp = tmp << 8;
sys/dev/usb/uvideo.c
2105
USETW(req.wValue, tmp);
sys/dev/vmm/vmm.c
580
struct vcpu *vcpu, *tmp;
sys/dev/vmm/vmm.c
587
SLIST_FOREACH_SAFE(vcpu, &vm->vm_vcpu_list, vc_vcpu_link, tmp) {
sys/dev/wscons/wsdisplay.c
2690
int tmp;
sys/dev/wscons/wsdisplay.c
2706
tmp = fg;
sys/dev/wscons/wsdisplay.c
2708
bg = tmp;
sys/dev/x86emu/x86emu.c
1976
uint8_t *srcreg, destval, tmp;
sys/dev/x86emu/x86emu.c
1981
tmp = destval;
sys/dev/x86emu/x86emu.c
1983
*srcreg = tmp;
sys/dev/x86emu/x86emu.c
1994
uint32_t *srcreg, destval, tmp;
sys/dev/x86emu/x86emu.c
1999
tmp = destval;
sys/dev/x86emu/x86emu.c
2001
*srcreg = tmp;
sys/dev/x86emu/x86emu.c
2008
uint16_t *srcreg, destval, tmp;
sys/dev/x86emu/x86emu.c
2013
tmp = destval;
sys/dev/x86emu/x86emu.c
2015
*srcreg = tmp;
sys/dev/x86emu/x86emu.c
2254
uint32_t tmp;
sys/dev/x86emu/x86emu.c
2257
tmp = emu->x86.R_EAX;
sys/dev/x86emu/x86emu.c
2259
emu->x86.R_ECX = tmp;
sys/dev/x86emu/x86emu.c
2261
tmp = emu->x86.R_AX;
sys/dev/x86emu/x86emu.c
2263
emu->x86.R_CX = (uint16_t) tmp;
sys/dev/x86emu/x86emu.c
2274
uint32_t tmp;
sys/dev/x86emu/x86emu.c
2277
tmp = emu->x86.R_EAX;
sys/dev/x86emu/x86emu.c
2279
emu->x86.R_EDX = tmp;
sys/dev/x86emu/x86emu.c
2281
tmp = emu->x86.R_AX;
sys/dev/x86emu/x86emu.c
2283
emu->x86.R_DX = (uint16_t) tmp;
sys/dev/x86emu/x86emu.c
2294
uint32_t tmp;
sys/dev/x86emu/x86emu.c
2297
tmp = emu->x86.R_EAX;
sys/dev/x86emu/x86emu.c
2299
emu->x86.R_EBX = tmp;
sys/dev/x86emu/x86emu.c
2301
tmp = emu->x86.R_AX;
sys/dev/x86emu/x86emu.c
2303
emu->x86.R_BX = (uint16_t) tmp;
sys/dev/x86emu/x86emu.c
2314
uint32_t tmp;
sys/dev/x86emu/x86emu.c
2317
tmp = emu->x86.R_EAX;
sys/dev/x86emu/x86emu.c
2319
emu->x86.R_ESP = tmp;
sys/dev/x86emu/x86emu.c
2321
tmp = emu->x86.R_AX;
sys/dev/x86emu/x86emu.c
2323
emu->x86.R_SP = (uint16_t) tmp;
sys/dev/x86emu/x86emu.c
2334
uint32_t tmp;
sys/dev/x86emu/x86emu.c
2337
tmp = emu->x86.R_EAX;
sys/dev/x86emu/x86emu.c
2339
emu->x86.R_EBP = tmp;
sys/dev/x86emu/x86emu.c
2341
tmp = emu->x86.R_AX;
sys/dev/x86emu/x86emu.c
2343
emu->x86.R_BP = (uint16_t) tmp;
sys/dev/x86emu/x86emu.c
2354
uint32_t tmp;
sys/dev/x86emu/x86emu.c
2357
tmp = emu->x86.R_EAX;
sys/dev/x86emu/x86emu.c
2359
emu->x86.R_ESI = tmp;
sys/dev/x86emu/x86emu.c
2361
tmp = emu->x86.R_AX;
sys/dev/x86emu/x86emu.c
2363
emu->x86.R_SI = (uint16_t) tmp;
sys/dev/x86emu/x86emu.c
2374
uint32_t tmp;
sys/dev/x86emu/x86emu.c
2377
tmp = emu->x86.R_EAX;
sys/dev/x86emu/x86emu.c
2379
emu->x86.R_EDI = tmp;
sys/dev/x86emu/x86emu.c
2381
tmp = emu->x86.R_AX;
sys/dev/x86emu/x86emu.c
2383
emu->x86.R_DI = (uint16_t) tmp;
sys/kern/kern_acct.c
173
struct timespec booted, elapsed, realstart, st, tmp, uptime, ut;
sys/kern/kern_acct.c
215
timespecadd(&ut, &st, &tmp);
sys/kern/kern_acct.c
216
t = tmp.tv_sec * hz + tmp.tv_nsec / (1000 * tick);
sys/kern/kern_clockintr.c
566
struct clockintr_stat sum, tmp;
sys/kern/kern_clockintr.c
585
tmp = cq->cq_stat;
sys/kern/kern_clockintr.c
588
sum.cs_dispatched += tmp.cs_dispatched;
sys/kern/kern_clockintr.c
589
sum.cs_early += tmp.cs_early;
sys/kern/kern_clockintr.c
590
sum.cs_earliness += tmp.cs_earliness;
sys/kern/kern_clockintr.c
591
sum.cs_lateness += tmp.cs_lateness;
sys/kern/kern_clockintr.c
592
sum.cs_prompt += tmp.cs_prompt;
sys/kern/kern_clockintr.c
593
sum.cs_run += tmp.cs_run;
sys/kern/kern_clockintr.c
594
sum.cs_spurious += tmp.cs_spurious;
sys/kern/kern_descrip.c
414
int i, prev, tmp, newmin, flg = F_POSIX;
sys/kern/kern_descrip.c
491
tmp = prev = fp->f_flag;
sys/kern/kern_descrip.c
492
tmp &= ~FCNTLFLAGS;
sys/kern/kern_descrip.c
493
tmp |= FFLAGS((long)SCARG(uap, arg)) & FCNTLFLAGS;
sys/kern/kern_descrip.c
494
} while (atomic_cas_uint(&fp->f_flag, prev, tmp) != prev);
sys/kern/kern_descrip.c
495
tmp = fp->f_flag & FASYNC;
sys/kern/kern_descrip.c
496
error = (*fp->f_ops->fo_ioctl)(fp, FIOASYNC, (caddr_t)&tmp, p);
sys/kern/kern_descrip.c
500
tmp = 0;
sys/kern/kern_descrip.c
502
(fp, FIOGETOWN, (caddr_t)&tmp, p);
sys/kern/kern_descrip.c
503
*retval = tmp;
sys/kern/kern_descrip.c
507
tmp = (long)SCARG(uap, arg);
sys/kern/kern_descrip.c
509
(fp, FIOSETOWN, (caddr_t)&tmp, p));
sys/kern/kern_resource.c
372
struct tusage tmp;
sys/kern/kern_resource.c
377
tmp = *from;
sys/kern/kern_resource.c
380
tu->tu_uticks += tmp.tu_uticks;
sys/kern/kern_resource.c
381
tu->tu_sticks += tmp.tu_sticks;
sys/kern/kern_resource.c
382
tu->tu_iticks += tmp.tu_iticks;
sys/kern/kern_resource.c
383
tu->tu_ixrss += tmp.tu_ixrss;
sys/kern/kern_resource.c
384
tu->tu_idrss += tmp.tu_idrss;
sys/kern/kern_resource.c
385
tu->tu_isrss += tmp.tu_isrss;
sys/kern/kern_resource.c
386
timespecadd(&tu->tu_runtime, &tmp.tu_runtime, &tu->tu_runtime);
sys/kern/kern_subr.c
197
char tmp = c;
sys/kern/kern_subr.c
199
if (copyout(&tmp, iov->iov_base, sizeof(char)) != 0)
sys/kern/kern_tc.c
443
u_int64_t tmp;
sys/kern/kern_tc.c
460
for (tmp = 1; (tmp & tc->tc_counter_mask) == 0; tmp <<= 1)
sys/kern/kern_tc.c
462
tc->tc_precision = tmp;
sys/kern/kern_tc.c
492
struct timecounter *best = &dummy_timecounter, *tmp;
sys/kern/kern_tc.c
499
SLIST_FOREACH(tmp, &tc_list, tc_next) {
sys/kern/kern_tc.c
500
if (tmp->tc_quality < 0)
sys/kern/kern_tc.c
502
if (tmp->tc_quality < best->tc_quality)
sys/kern/kern_tc.c
504
if (tmp->tc_quality == best->tc_quality &&
sys/kern/kern_tc.c
505
tmp->tc_frequency < best->tc_frequency)
sys/kern/kern_tc.c
507
best = tmp;
sys/kern/kern_tc.c
543
struct timespec tmp;
sys/kern/kern_tc.c
563
BINTIME_TO_TIMESPEC(&old_utc, &tmp);
sys/kern/kern_tc.c
565
(long long)tmp.tv_sec, tmp.tv_nsec,
sys/kern/kern_timeout.c
948
struct timespec tmp, zero;
sys/kern/kern_timeout.c
957
timespecsub(&zero, ts, &tmp);
sys/kern/kern_timeout.c
958
snprintf(buf, sizeof(buf), "-%lld.%09ld", tmp.tv_sec, tmp.tv_nsec);
sys/kern/subr_extent.c
1051
LIST_FOREACH_SAFE(rp, &ex->ex_regions, er_link, tmp) {
sys/kern/subr_extent.c
988
struct extent_region *tmp;
sys/kern/subr_prf.c
742
int tmp;
sys/kern/subr_prf.c
761
tmp = 0;
sys/kern/subr_prf.c
768
KPRINTF_PUTCHAR(tmp ? ',':'<');
sys/kern/subr_prf.c
774
tmp = 1;
sys/kern/subr_prf.c
781
if (tmp) {
sys/kern/subr_tree.c
102
struct rb_entry *tmp;
sys/kern/subr_tree.c
104
tmp = RBE_RIGHT(rbe);
sys/kern/subr_tree.c
105
RBE_RIGHT(rbe) = RBE_LEFT(tmp);
sys/kern/subr_tree.c
107
RBE_PARENT(RBE_LEFT(tmp)) = rbe;
sys/kern/subr_tree.c
110
RBE_PARENT(tmp) = parent;
sys/kern/subr_tree.c
113
RBE_LEFT(parent) = tmp;
sys/kern/subr_tree.c
115
RBE_RIGHT(parent) = tmp;
sys/kern/subr_tree.c
117
RBH_ROOT(rbt) = tmp;
sys/kern/subr_tree.c
119
RBE_LEFT(tmp) = rbe;
sys/kern/subr_tree.c
120
RBE_PARENT(rbe) = tmp;
sys/kern/subr_tree.c
124
rbe_augment(t, tmp);
sys/kern/subr_tree.c
125
parent = RBE_PARENT(tmp);
sys/kern/subr_tree.c
136
struct rb_entry *tmp;
sys/kern/subr_tree.c
138
tmp = RBE_LEFT(rbe);
sys/kern/subr_tree.c
139
RBE_LEFT(rbe) = RBE_RIGHT(tmp);
sys/kern/subr_tree.c
141
RBE_PARENT(RBE_RIGHT(tmp)) = rbe;
sys/kern/subr_tree.c
144
RBE_PARENT(tmp) = parent;
sys/kern/subr_tree.c
147
RBE_LEFT(parent) = tmp;
sys/kern/subr_tree.c
149
RBE_RIGHT(parent) = tmp;
sys/kern/subr_tree.c
151
RBH_ROOT(rbt) = tmp;
sys/kern/subr_tree.c
153
RBE_RIGHT(tmp) = rbe;
sys/kern/subr_tree.c
154
RBE_PARENT(rbe) = tmp;
sys/kern/subr_tree.c
158
rbe_augment(t, tmp);
sys/kern/subr_tree.c
159
parent = RBE_PARENT(tmp);
sys/kern/subr_tree.c
169
struct rb_entry *parent, *gparent, *tmp;
sys/kern/subr_tree.c
176
tmp = RBE_RIGHT(gparent);
sys/kern/subr_tree.c
177
if (tmp != NULL && RBE_COLOR(tmp) == RB_RED) {
sys/kern/subr_tree.c
178
RBE_COLOR(tmp) = RB_BLACK;
sys/kern/subr_tree.c
186
tmp = parent;
sys/kern/subr_tree.c
188
rbe = tmp;
sys/kern/subr_tree.c
194
tmp = RBE_LEFT(gparent);
sys/kern/subr_tree.c
195
if (tmp != NULL && RBE_COLOR(tmp) == RB_RED) {
sys/kern/subr_tree.c
196
RBE_COLOR(tmp) = RB_BLACK;
sys/kern/subr_tree.c
204
tmp = parent;
sys/kern/subr_tree.c
206
rbe = tmp;
sys/kern/subr_tree.c
221
struct rb_entry *tmp;
sys/kern/subr_tree.c
226
tmp = RBE_RIGHT(parent);
sys/kern/subr_tree.c
227
if (RBE_COLOR(tmp) == RB_RED) {
sys/kern/subr_tree.c
228
rbe_set_blackred(tmp, parent);
sys/kern/subr_tree.c
230
tmp = RBE_RIGHT(parent);
sys/kern/subr_tree.c
232
if ((RBE_LEFT(tmp) == NULL ||
sys/kern/subr_tree.c
233
RBE_COLOR(RBE_LEFT(tmp)) == RB_BLACK) &&
sys/kern/subr_tree.c
234
(RBE_RIGHT(tmp) == NULL ||
sys/kern/subr_tree.c
235
RBE_COLOR(RBE_RIGHT(tmp)) == RB_BLACK)) {
sys/kern/subr_tree.c
236
RBE_COLOR(tmp) = RB_RED;
sys/kern/subr_tree.c
240
if (RBE_RIGHT(tmp) == NULL ||
sys/kern/subr_tree.c
241
RBE_COLOR(RBE_RIGHT(tmp)) == RB_BLACK) {
sys/kern/subr_tree.c
244
oleft = RBE_LEFT(tmp);
sys/kern/subr_tree.c
248
RBE_COLOR(tmp) = RB_RED;
sys/kern/subr_tree.c
249
rbe_rotate_right(t, rbt, tmp);
sys/kern/subr_tree.c
250
tmp = RBE_RIGHT(parent);
sys/kern/subr_tree.c
253
RBE_COLOR(tmp) = RBE_COLOR(parent);
sys/kern/subr_tree.c
255
if (RBE_RIGHT(tmp))
sys/kern/subr_tree.c
256
RBE_COLOR(RBE_RIGHT(tmp)) = RB_BLACK;
sys/kern/subr_tree.c
263
tmp = RBE_LEFT(parent);
sys/kern/subr_tree.c
264
if (RBE_COLOR(tmp) == RB_RED) {
sys/kern/subr_tree.c
265
rbe_set_blackred(tmp, parent);
sys/kern/subr_tree.c
267
tmp = RBE_LEFT(parent);
sys/kern/subr_tree.c
270
if ((RBE_LEFT(tmp) == NULL ||
sys/kern/subr_tree.c
271
RBE_COLOR(RBE_LEFT(tmp)) == RB_BLACK) &&
sys/kern/subr_tree.c
272
(RBE_RIGHT(tmp) == NULL ||
sys/kern/subr_tree.c
273
RBE_COLOR(RBE_RIGHT(tmp)) == RB_BLACK)) {
sys/kern/subr_tree.c
274
RBE_COLOR(tmp) = RB_RED;
sys/kern/subr_tree.c
278
if (RBE_LEFT(tmp) == NULL ||
sys/kern/subr_tree.c
279
RBE_COLOR(RBE_LEFT(tmp)) == RB_BLACK) {
sys/kern/subr_tree.c
282
oright = RBE_RIGHT(tmp);
sys/kern/subr_tree.c
286
RBE_COLOR(tmp) = RB_RED;
sys/kern/subr_tree.c
287
rbe_rotate_left(t, rbt, tmp);
sys/kern/subr_tree.c
288
tmp = RBE_LEFT(parent);
sys/kern/subr_tree.c
291
RBE_COLOR(tmp) = RBE_COLOR(parent);
sys/kern/subr_tree.c
293
if (RBE_LEFT(tmp) != NULL)
sys/kern/subr_tree.c
294
RBE_COLOR(RBE_LEFT(tmp)) = RB_BLACK;
sys/kern/subr_tree.c
318
struct rb_entry *tmp;
sys/kern/subr_tree.c
321
while ((tmp = RBE_LEFT(rbe)) != NULL)
sys/kern/subr_tree.c
322
rbe = tmp;
sys/kern/subr_tree.c
342
tmp = RBE_PARENT(old);
sys/kern/subr_tree.c
343
if (tmp != NULL) {
sys/kern/subr_tree.c
344
if (RBE_LEFT(tmp) == old)
sys/kern/subr_tree.c
345
RBE_LEFT(tmp) = rbe;
sys/kern/subr_tree.c
347
RBE_RIGHT(tmp) = rbe;
sys/kern/subr_tree.c
349
rbe_if_augment(t, tmp);
sys/kern/subr_tree.c
358
tmp = parent;
sys/kern/subr_tree.c
360
rbe_augment(t, tmp);
sys/kern/subr_tree.c
361
tmp = RBE_PARENT(tmp);
sys/kern/subr_tree.c
362
} while (tmp != NULL);
sys/kern/subr_tree.c
404
struct rb_entry *tmp;
sys/kern/subr_tree.c
409
tmp = RBH_ROOT(rbt);
sys/kern/subr_tree.c
410
while (tmp != NULL) {
sys/kern/subr_tree.c
411
parent = tmp;
sys/kern/subr_tree.c
413
node = rb_e2n(t, tmp);
sys/kern/subr_tree.c
416
tmp = RBE_LEFT(tmp);
sys/kern/subr_tree.c
418
tmp = RBE_RIGHT(tmp);
sys/kern/subr_tree.c
444
struct rb_entry *tmp = RBH_ROOT(rbt);
sys/kern/subr_tree.c
448
while (tmp != NULL) {
sys/kern/subr_tree.c
449
node = rb_e2n(t, tmp);
sys/kern/subr_tree.c
452
tmp = RBE_LEFT(tmp);
sys/kern/subr_tree.c
454
tmp = RBE_RIGHT(tmp);
sys/kern/subr_tree.c
466
struct rb_entry *tmp = RBH_ROOT(rbt);
sys/kern/subr_tree.c
471
while (tmp != NULL) {
sys/kern/subr_tree.c
472
node = rb_e2n(t, tmp);
sys/kern/subr_tree.c
476
tmp = RBE_LEFT(tmp);
sys/kern/subr_tree.c
478
tmp = RBE_RIGHT(tmp);
sys/kern/subr_userconf.c
450
long *l, tmp;
sys/kern/subr_userconf.c
505
tmp = cd->cf_flags;
sys/kern/subr_userconf.c
506
userconf_modify("flags", &tmp, INT_MAX);
sys/kern/subr_userconf.c
507
userconf_hist_int(tmp);
sys/kern/subr_userconf.c
508
cd->cf_flags = tmp;
sys/kern/subr_userconf.c
544
tmp = pdevinit[devno-userconf_totdev-1].pdev_count;
sys/kern/subr_userconf.c
545
userconf_modify("count", &tmp, INT_MAX);
sys/kern/subr_userconf.c
546
userconf_hist_int(tmp);
sys/kern/subr_userconf.c
547
pdevinit[devno-userconf_totdev-1].pdev_count = tmp;
sys/kern/sys_generic.c
428
int tmp;
sys/kern/sys_generic.c
494
if ((tmp = *(int *)data) != 0)
sys/kern/sys_generic.c
502
if ((tmp = *(int *)data) != 0)
sys/kern/sys_generic.c
506
error = (*fp->f_ops->fo_ioctl)(fp, FIOASYNC, (caddr_t)&tmp, p);
sys/kern/sysv_msg.c
101
struct msqid_ds tmp, *umsq = SCARG(uap, buf);
sys/kern/sysv_msg.c
136
if ((error = copyin(umsq, &tmp, sizeof(struct msqid_ds))))
sys/kern/sysv_msg.c
140
if (tmp.msg_qbytes > que->msqid_ds.msg_qbytes &&
sys/kern/sysv_msg.c
147
if (tmp.msg_qbytes > msginfo.msgmnb)
sys/kern/sysv_msg.c
148
tmp.msg_qbytes = msginfo.msgmnb;
sys/kern/sysv_msg.c
151
if (tmp.msg_qbytes == 0) {
sys/kern/sysv_msg.c
156
que->msqid_ds.msg_perm.uid = tmp.msg_perm.uid;
sys/kern/sysv_msg.c
157
que->msqid_ds.msg_perm.gid = tmp.msg_perm.gid;
sys/kern/sysv_msg.c
160
(tmp.msg_perm.mode & 0777);
sys/kern/sysv_msg.c
161
que->msqid_ds.msg_qbytes = tmp.msg_qbytes;
sys/kern/tty.c
2156
int tmp;
sys/kern/tty.c
2162
tmp = (averunnable.ldavg[0] * 100 + FSCALE / 2) >> FSHIFT;
sys/kern/tty.c
2163
ttyprintf(tp, "load: %d.%02d ", tmp / 100, tmp % 100);
sys/kern/tty_subr.c
460
struct clist tmp;
sys/kern/tty_subr.c
462
tmp = *from;
sys/kern/tty_subr.c
464
*to = tmp;
sys/kern/uipc_usrreq.c
1245
char *tmp;
sys/kern/uipc_usrreq.c
1253
tmp = malloc(control->m_len, M_TEMP, M_WAITOK);
sys/kern/uipc_usrreq.c
1254
memcpy(tmp, mtod(control, caddr_t), control->m_len);
sys/kern/uipc_usrreq.c
1259
free(tmp, M_TEMP, control->m_len);
sys/kern/uipc_usrreq.c
1266
memcpy(cm, tmp, control->m_len);
sys/kern/uipc_usrreq.c
1267
free(tmp, M_TEMP, control->m_len);
sys/lib/libkern/qdivrem.c
107
tmp.uq = uq;
sys/lib/libkern/qdivrem.c
109
u[1] = (digit)HHALF(tmp.ul[H]);
sys/lib/libkern/qdivrem.c
110
u[2] = (digit)LHALF(tmp.ul[H]);
sys/lib/libkern/qdivrem.c
111
u[3] = (digit)HHALF(tmp.ul[L]);
sys/lib/libkern/qdivrem.c
112
u[4] = (digit)LHALF(tmp.ul[L]);
sys/lib/libkern/qdivrem.c
113
tmp.uq = vq;
sys/lib/libkern/qdivrem.c
114
v[1] = (digit)HHALF(tmp.ul[H]);
sys/lib/libkern/qdivrem.c
115
v[2] = (digit)LHALF(tmp.ul[H]);
sys/lib/libkern/qdivrem.c
116
v[3] = (digit)HHALF(tmp.ul[L]);
sys/lib/libkern/qdivrem.c
117
v[4] = (digit)LHALF(tmp.ul[L]);
sys/lib/libkern/qdivrem.c
141
tmp.ul[H] = COMBINE(q1, q2);
sys/lib/libkern/qdivrem.c
142
tmp.ul[L] = COMBINE(q3, q4);
sys/lib/libkern/qdivrem.c
143
return (tmp.q);
sys/lib/libkern/qdivrem.c
249
tmp.ul[H] = COMBINE(uspace[1], uspace[2]);
sys/lib/libkern/qdivrem.c
250
tmp.ul[L] = COMBINE(uspace[3], uspace[4]);
sys/lib/libkern/qdivrem.c
251
*arq = tmp.q;
sys/lib/libkern/qdivrem.c
254
tmp.ul[H] = COMBINE(qspace[1], qspace[2]);
sys/lib/libkern/qdivrem.c
255
tmp.ul[L] = COMBINE(qspace[3], qspace[4]);
sys/lib/libkern/qdivrem.c
256
return (tmp.q);
sys/lib/libkern/qdivrem.c
66
union uu tmp;
sys/lib/libkern/qdivrem.c
80
tmp.ul[H] = tmp.ul[L] = 1 / zero;
sys/lib/libkern/qdivrem.c
83
return (tmp.q);
sys/lib/libz/adler32.c
25
unsigned long tmp = a >> 16; \
sys/lib/libz/adler32.c
27
a += (tmp << 4) - tmp; \
sys/lib/libz/adler32.c
41
z_off64_t tmp = a >> 32; \
sys/lib/libz/adler32.c
43
a += (tmp << 8) - (tmp << 5) + tmp; \
sys/lib/libz/adler32.c
44
tmp = a >> 16; \
sys/lib/libz/adler32.c
46
a += (tmp << 4) - tmp; \
sys/lib/libz/adler32.c
47
tmp = a >> 16; \
sys/lib/libz/adler32.c
49
a += (tmp << 4) - tmp; \
sys/net/if_pppx.c
1028
struct pppac_softc *sc, *tmp;
sys/net/if_pppx.c
1034
LIST_FOREACH(tmp, &pppac_devs, sc_entry) {
sys/net/if_pppx.c
1035
if (tmp->sc_dev == dev) {
sys/net/pf_if.c
940
u_int32_t tmp;
sys/net/pf_if.c
947
tmp = ntohl(m->addr32[j]);
sys/net/pf_if.c
948
for (i = 31; tmp & (1 << i); --i)
sys/net/pf_lb.c
196
u_int32_t tmp;
sys/net/pf_lb.c
199
tmp = low;
sys/net/pf_lb.c
201
high = tmp;
sys/net/pf_lb.c
206
for (tmp = cut; tmp <= high && tmp <= 0xffff; ++tmp) {
sys/net/pf_lb.c
207
key.port[sidx] = htons(tmp);
sys/net/pf_lb.c
212
NULL && !in_baddynamic(tmp, pd->proto)) {
sys/net/pf_lb.c
213
*nport = htons(tmp);
sys/net/pf_lb.c
217
tmp = cut;
sys/net/pf_lb.c
218
for (tmp -= 1; tmp >= low && tmp <= 0xffff; --tmp) {
sys/net/pf_lb.c
219
key.port[sidx] = htons(tmp);
sys/net/pf_lb.c
224
NULL && !in_baddynamic(tmp, pd->proto)) {
sys/net/pf_lb.c
225
*nport = htons(tmp);
sys/net/pf_table.c
96
type tmp = a1; \
sys/net/pf_table.c
98
a2 = tmp; \
sys/net/pfkeyv2_convert.c
737
struct ipsec_ids *tmp;
sys/net/pfkeyv2_convert.c
741
tmp = malloc(sizeof(struct ipsec_ids), M_CREDENTIALS, M_WAITOK);
sys/net/pfkeyv2_convert.c
742
import_identity(&tmp->id_local, swapped ? dstid: srcid, &id_local_sz);
sys/net/pfkeyv2_convert.c
743
import_identity(&tmp->id_remote, swapped ? srcid: dstid, &id_remote_sz);
sys/net/pfkeyv2_convert.c
744
if (tmp->id_local != NULL && tmp->id_remote != NULL) {
sys/net/pfkeyv2_convert.c
745
*ids = ipsp_ids_insert(tmp);
sys/net/pfkeyv2_convert.c
746
if (*ids == tmp)
sys/net/pfkeyv2_convert.c
749
free(tmp->id_local, M_CREDENTIALS, id_local_sz);
sys/net/pfkeyv2_convert.c
750
free(tmp->id_remote, M_CREDENTIALS, id_remote_sz);
sys/net/pfkeyv2_convert.c
751
free(tmp, M_CREDENTIALS, sizeof(*tmp));
sys/net/wg_noise.c
874
uint8_t tmp[NOISE_HASH_LEN];
sys/net/wg_noise.c
876
noise_kdf(ck, tmp, key, psk,
sys/net/wg_noise.c
879
noise_mix_hash(hash, tmp, NOISE_HASH_LEN);
sys/net/wg_noise.c
880
explicit_bzero(tmp, NOISE_HASH_LEN);
sys/net80211/ieee80211_ra.c
86
uint64_t tmp;
sys/net80211/ieee80211_ra.c
92
tmp = (fp & ((uint64_t)-1 >> (64 - RA_FP_SHIFT)));
sys/net80211/ieee80211_ra.c
93
tmp *= 100;
sys/net80211/ieee80211_ra.c
94
*f = (uint32_t)(tmp >> RA_FP_SHIFT);
sys/net80211/ieee80211_ra_vht.c
85
uint64_t tmp;
sys/net80211/ieee80211_ra_vht.c
91
tmp = (fp & ((uint64_t)-1 >> (64 - RA_FP_SHIFT)));
sys/net80211/ieee80211_ra_vht.c
92
tmp *= 100;
sys/net80211/ieee80211_ra_vht.c
93
*f = (uint32_t)(tmp >> RA_FP_SHIFT);
sys/netinet/if_ether.c
130
struct llinfo_arp *tmp;
sys/netinet/if_ether.c
135
tmp = LIST_NEXT((struct llinfo_arp *)iter, la_list);
sys/netinet/if_ether.c
137
tmp = LIST_FIRST(&arp_list);
sys/netinet/if_ether.c
139
while (tmp && tmp->la_rt == NULL)
sys/netinet/if_ether.c
140
tmp = LIST_NEXT(tmp, la_list);
sys/netinet/if_ether.c
147
if (tmp) {
sys/netinet/if_ether.c
148
LIST_INSERT_AFTER(tmp, (struct llinfo_arp *)iter, la_list);
sys/netinet/if_ether.c
149
refcnt_take(&tmp->la_refcnt);
sys/netinet/if_ether.c
152
return tmp;
sys/netinet/in_pcb.c
679
struct inpcb *tmp;
sys/netinet/in_pcb.c
684
tmp = TAILQ_NEXT((struct inpcb *)iter, inp_queue);
sys/netinet/in_pcb.c
686
tmp = TAILQ_FIRST(&table->inpt_queue);
sys/netinet/in_pcb.c
688
while (tmp && tmp->inp_table == NULL)
sys/netinet/in_pcb.c
689
tmp = TAILQ_NEXT(tmp, inp_queue);
sys/netinet/in_pcb.c
696
if (tmp) {
sys/netinet/in_pcb.c
697
TAILQ_INSERT_AFTER(&table->inpt_queue, tmp,
sys/netinet/in_pcb.c
699
in_pcbref(tmp);
sys/netinet/in_pcb.c
702
return tmp;
sys/netinet/inet_ntop.c
105
char tmp[sizeof "255.255.255.255"];
sys/netinet/inet_ntop.c
108
l = snprintf(tmp, sizeof(tmp), "%u.%u.%u.%u",
sys/netinet/inet_ntop.c
113
strlcpy(dst, tmp, size);
sys/netinet/inet_ntop.c
134
char tmp[sizeof "ffff:ffff:ffff:ffff:ffff:ffff:255.255.255.255"];
sys/netinet/inet_ntop.c
175
tp = tmp;
sys/netinet/inet_ntop.c
176
ep = tmp + sizeof(tmp);
sys/netinet/inet_ntop.c
220
if ((size_t)(tp - tmp) > size) {
sys/netinet/inet_ntop.c
223
strlcpy(dst, tmp, size);
sys/netinet6/in6_pcb.c
263
struct sockaddr_in6 tmp;
sys/netinet6/in6_pcb.c
276
tmp = *sin6;
sys/netinet6/in6_pcb.c
277
sin6 = &tmp;
sys/netinet6/nd6.c
246
struct llinfo_nd6 *tmp;
sys/netinet6/nd6.c
251
tmp = TAILQ_NEXT((struct llinfo_nd6 *)iter, ln_list);
sys/netinet6/nd6.c
253
tmp = TAILQ_FIRST(&nd6_list);
sys/netinet6/nd6.c
255
while (tmp && tmp->ln_rt == NULL)
sys/netinet6/nd6.c
256
tmp = TAILQ_NEXT(tmp, ln_list);
sys/netinet6/nd6.c
263
if (tmp) {
sys/netinet6/nd6.c
264
TAILQ_INSERT_AFTER(&nd6_list, tmp, (struct llinfo_nd6 *)iter,
sys/netinet6/nd6.c
266
refcnt_take(&tmp->ln_refcnt);
sys/netinet6/nd6.c
269
return tmp;
sys/netinet6/udp6_output.c
102
struct sockaddr_in6 tmp, valid;
sys/netinet6/udp6_output.c
135
tmp = *sin6;
sys/netinet6/udp6_output.c
136
sin6 = &tmp;
sys/ntfs/ntfs_subr.c
605
cn_t tmp;
sys/ntfs/ntfs_subr.c
629
tmp = ((u_int64_t) - 1) << (sz << 3);
sys/ntfs/ntfs_subr.c
631
tmp |= (u_int64_t) run[off++] << (i << 3);
sys/ntfs/ntfs_subr.c
633
tmp = 0;
sys/ntfs/ntfs_subr.c
635
tmp |= (u_int64_t) run[off++] << (i << 3);
sys/ntfs/ntfs_subr.c
637
if (tmp)
sys/ntfs/ntfs_subr.c
638
prev = cn[cnt] = prev + tmp;
sys/ntfs/ntfs_subr.c
640
cn[cnt] = tmp;
sys/ntfs/ntfs_vfsops.c
553
u_int8_t *tmp;
sys/ntfs/ntfs_vfsops.c
568
tmp = malloc(chunksize, M_TEMP, M_WAITOK);
sys/ntfs/ntfs_vfsops.c
575
offset, chunksize, tmp, NULL);
sys/ntfs/ntfs_vfsops.c
581
if (~tmp[i] & (1 << j))
sys/ntfs/ntfs_vfsops.c
588
free(tmp, M_TEMP, 0);
sys/scsi/scsiconf.c
741
struct scsi_link *link, *tmp;
sys/scsi/scsiconf.c
745
SLIST_FOREACH_SAFE(link, &sb->sc_link_list, bus_list, tmp) {
sys/scsi/scsiconf.c
756
struct scsi_link *link, *tmp;
sys/scsi/scsiconf.c
760
SLIST_FOREACH_SAFE(link, &sb->sc_link_list, bus_list, tmp) {
sys/sys/tree.h
101
#define SPLAY_LINKRIGHT(head, tmp, field) do { \
sys/sys/tree.h
102
SPLAY_RIGHT(tmp, field) = (head)->sph_root; \
sys/sys/tree.h
103
tmp = (head)->sph_root; \
sys/sys/tree.h
337
#define RB_ROTATE_LEFT(head, elm, tmp, field) do { \
sys/sys/tree.h
338
(tmp) = RB_RIGHT(elm, field); \
sys/sys/tree.h
339
if ((RB_RIGHT(elm, field) = RB_LEFT(tmp, field))) { \
sys/sys/tree.h
340
RB_PARENT(RB_LEFT(tmp, field), field) = (elm); \
sys/sys/tree.h
343
if ((RB_PARENT(tmp, field) = RB_PARENT(elm, field))) { \
sys/sys/tree.h
345
RB_LEFT(RB_PARENT(elm, field), field) = (tmp); \
sys/sys/tree.h
347
RB_RIGHT(RB_PARENT(elm, field), field) = (tmp); \
sys/sys/tree.h
349
(head)->rbh_root = (tmp); \
sys/sys/tree.h
350
RB_LEFT(tmp, field) = (elm); \
sys/sys/tree.h
351
RB_PARENT(elm, field) = (tmp); \
sys/sys/tree.h
352
RB_AUGMENT(tmp); \
sys/sys/tree.h
353
if ((RB_PARENT(tmp, field))) \
sys/sys/tree.h
354
RB_AUGMENT(RB_PARENT(tmp, field)); \
sys/sys/tree.h
357
#define RB_ROTATE_RIGHT(head, elm, tmp, field) do { \
sys/sys/tree.h
358
(tmp) = RB_LEFT(elm, field); \
sys/sys/tree.h
359
if ((RB_LEFT(elm, field) = RB_RIGHT(tmp, field))) { \
sys/sys/tree.h
360
RB_PARENT(RB_RIGHT(tmp, field), field) = (elm); \
sys/sys/tree.h
363
if ((RB_PARENT(tmp, field) = RB_PARENT(elm, field))) { \
sys/sys/tree.h
365
RB_LEFT(RB_PARENT(elm, field), field) = (tmp); \
sys/sys/tree.h
367
RB_RIGHT(RB_PARENT(elm, field), field) = (tmp); \
sys/sys/tree.h
369
(head)->rbh_root = (tmp); \
sys/sys/tree.h
370
RB_RIGHT(tmp, field) = (elm); \
sys/sys/tree.h
371
RB_PARENT(elm, field) = (tmp); \
sys/sys/tree.h
372
RB_AUGMENT(tmp); \
sys/sys/tree.h
373
if ((RB_PARENT(tmp, field))) \
sys/sys/tree.h
374
RB_AUGMENT(RB_PARENT(tmp, field)); \
sys/sys/tree.h
405
struct type *parent, *gparent, *tmp; \
sys/sys/tree.h
410
tmp = RB_RIGHT(gparent, field); \
sys/sys/tree.h
411
if (tmp && RB_COLOR(tmp, field) == RB_RED) { \
sys/sys/tree.h
412
RB_COLOR(tmp, field) = RB_BLACK; \
sys/sys/tree.h
418
RB_ROTATE_LEFT(head, parent, tmp, field);\
sys/sys/tree.h
419
tmp = parent; \
sys/sys/tree.h
421
elm = tmp; \
sys/sys/tree.h
424
RB_ROTATE_RIGHT(head, gparent, tmp, field); \
sys/sys/tree.h
426
tmp = RB_LEFT(gparent, field); \
sys/sys/tree.h
427
if (tmp && RB_COLOR(tmp, field) == RB_RED) { \
sys/sys/tree.h
428
RB_COLOR(tmp, field) = RB_BLACK; \
sys/sys/tree.h
434
RB_ROTATE_RIGHT(head, parent, tmp, field);\
sys/sys/tree.h
435
tmp = parent; \
sys/sys/tree.h
437
elm = tmp; \
sys/sys/tree.h
440
RB_ROTATE_LEFT(head, gparent, tmp, field); \
sys/sys/tree.h
449
struct type *tmp; \
sys/sys/tree.h
453
tmp = RB_RIGHT(parent, field); \
sys/sys/tree.h
454
if (RB_COLOR(tmp, field) == RB_RED) { \
sys/sys/tree.h
455
RB_SET_BLACKRED(tmp, parent, field); \
sys/sys/tree.h
456
RB_ROTATE_LEFT(head, parent, tmp, field);\
sys/sys/tree.h
457
tmp = RB_RIGHT(parent, field); \
sys/sys/tree.h
459
if ((RB_LEFT(tmp, field) == NULL || \
sys/sys/tree.h
460
RB_COLOR(RB_LEFT(tmp, field), field) == RB_BLACK) &&\
sys/sys/tree.h
461
(RB_RIGHT(tmp, field) == NULL || \
sys/sys/tree.h
462
RB_COLOR(RB_RIGHT(tmp, field), field) == RB_BLACK)) {\
sys/sys/tree.h
463
RB_COLOR(tmp, field) = RB_RED; \
sys/sys/tree.h
467
if (RB_RIGHT(tmp, field) == NULL || \
sys/sys/tree.h
468
RB_COLOR(RB_RIGHT(tmp, field), field) == RB_BLACK) {\
sys/sys/tree.h
470
if ((oleft = RB_LEFT(tmp, field)))\
sys/sys/tree.h
472
RB_COLOR(tmp, field) = RB_RED; \
sys/sys/tree.h
473
RB_ROTATE_RIGHT(head, tmp, oleft, field);\
sys/sys/tree.h
474
tmp = RB_RIGHT(parent, field); \
sys/sys/tree.h
476
RB_COLOR(tmp, field) = RB_COLOR(parent, field);\
sys/sys/tree.h
478
if (RB_RIGHT(tmp, field)) \
sys/sys/tree.h
479
RB_COLOR(RB_RIGHT(tmp, field), field) = RB_BLACK;\
sys/sys/tree.h
480
RB_ROTATE_LEFT(head, parent, tmp, field);\
sys/sys/tree.h
485
tmp = RB_LEFT(parent, field); \
sys/sys/tree.h
486
if (RB_COLOR(tmp, field) == RB_RED) { \
sys/sys/tree.h
487
RB_SET_BLACKRED(tmp, parent, field); \
sys/sys/tree.h
488
RB_ROTATE_RIGHT(head, parent, tmp, field);\
sys/sys/tree.h
489
tmp = RB_LEFT(parent, field); \
sys/sys/tree.h
491
if ((RB_LEFT(tmp, field) == NULL || \
sys/sys/tree.h
492
RB_COLOR(RB_LEFT(tmp, field), field) == RB_BLACK) &&\
sys/sys/tree.h
493
(RB_RIGHT(tmp, field) == NULL || \
sys/sys/tree.h
494
RB_COLOR(RB_RIGHT(tmp, field), field) == RB_BLACK)) {\
sys/sys/tree.h
495
RB_COLOR(tmp, field) = RB_RED; \
sys/sys/tree.h
499
if (RB_LEFT(tmp, field) == NULL || \
sys/sys/tree.h
500
RB_COLOR(RB_LEFT(tmp, field), field) == RB_BLACK) {\
sys/sys/tree.h
502
if ((oright = RB_RIGHT(tmp, field)))\
sys/sys/tree.h
504
RB_COLOR(tmp, field) = RB_RED; \
sys/sys/tree.h
505
RB_ROTATE_LEFT(head, tmp, oright, field);\
sys/sys/tree.h
506
tmp = RB_LEFT(parent, field); \
sys/sys/tree.h
508
RB_COLOR(tmp, field) = RB_COLOR(parent, field);\
sys/sys/tree.h
510
if (RB_LEFT(tmp, field)) \
sys/sys/tree.h
511
RB_COLOR(RB_LEFT(tmp, field), field) = RB_BLACK;\
sys/sys/tree.h
512
RB_ROTATE_RIGHT(head, parent, tmp, field);\
sys/sys/tree.h
593
struct type *tmp; \
sys/sys/tree.h
596
tmp = RB_ROOT(head); \
sys/sys/tree.h
597
while (tmp) { \
sys/sys/tree.h
598
parent = tmp; \
sys/sys/tree.h
601
tmp = RB_LEFT(tmp, field); \
sys/sys/tree.h
603
tmp = RB_RIGHT(tmp, field); \
sys/sys/tree.h
605
return (tmp); \
sys/sys/tree.h
624
struct type *tmp = RB_ROOT(head); \
sys/sys/tree.h
626
while (tmp) { \
sys/sys/tree.h
627
comp = cmp(elm, tmp); \
sys/sys/tree.h
629
tmp = RB_LEFT(tmp, field); \
sys/sys/tree.h
631
tmp = RB_RIGHT(tmp, field); \
sys/sys/tree.h
633
return (tmp); \
sys/sys/tree.h
642
struct type *tmp = RB_ROOT(head); \
sys/sys/tree.h
645
while (tmp) { \
sys/sys/tree.h
646
comp = cmp(elm, tmp); \
sys/sys/tree.h
648
res = tmp; \
sys/sys/tree.h
649
tmp = RB_LEFT(tmp, field); \
sys/sys/tree.h
652
tmp = RB_RIGHT(tmp, field); \
sys/sys/tree.h
654
return (tmp); \
sys/sys/tree.h
704
struct type *tmp = RB_ROOT(head); \
sys/sys/tree.h
706
while (tmp) { \
sys/sys/tree.h
707
parent = tmp; \
sys/sys/tree.h
709
tmp = RB_LEFT(tmp, field); \
sys/sys/tree.h
711
tmp = RB_RIGHT(tmp, field); \
sys/sys/tree.h
83
#define SPLAY_ROTATE_RIGHT(head, tmp, field) do { \
sys/sys/tree.h
84
SPLAY_LEFT((head)->sph_root, field) = SPLAY_RIGHT(tmp, field); \
sys/sys/tree.h
85
SPLAY_RIGHT(tmp, field) = (head)->sph_root; \
sys/sys/tree.h
86
(head)->sph_root = tmp; \
sys/sys/tree.h
89
#define SPLAY_ROTATE_LEFT(head, tmp, field) do { \
sys/sys/tree.h
90
SPLAY_RIGHT((head)->sph_root, field) = SPLAY_LEFT(tmp, field); \
sys/sys/tree.h
91
SPLAY_LEFT(tmp, field) = (head)->sph_root; \
sys/sys/tree.h
92
(head)->sph_root = tmp; \
sys/sys/tree.h
95
#define SPLAY_LINKLEFT(head, tmp, field) do { \
sys/sys/tree.h
96
SPLAY_LEFT(tmp, field) = (head)->sph_root; \
sys/sys/tree.h
97
tmp = (head)->sph_root; \
sys/tmpfs/tmpfs.h
342
tmpfs_mount_t *tmp = mp->mnt_data;
sys/tmpfs/tmpfs.h
344
KASSERT(tmp != NULL);
sys/tmpfs/tmpfs.h
345
return tmp;
sys/tmpfs/tmpfs_subr.c
104
tmpfs_alloc_node(tmpfs_mount_t *tmp, enum vtype type, uid_t uid, gid_t gid,
sys/tmpfs/tmpfs_subr.c
110
nnode = tmpfs_node_get(tmp);
sys/tmpfs/tmpfs_subr.c
120
rw_enter_write(&tmp->tm_acc_lock);
sys/tmpfs/tmpfs_subr.c
121
nnode->tn_id = ++tmp->tm_highest_inode;
sys/tmpfs/tmpfs_subr.c
123
--tmp->tm_highest_inode;
sys/tmpfs/tmpfs_subr.c
124
rw_exit_write(&tmp->tm_acc_lock);
sys/tmpfs/tmpfs_subr.c
125
tmpfs_node_put(tmp, nnode);
sys/tmpfs/tmpfs_subr.c
128
rw_exit_write(&tmp->tm_acc_lock);
sys/tmpfs/tmpfs_subr.c
179
tmpfs_strname_alloc(tmp, nnode->tn_size);
sys/tmpfs/tmpfs_subr.c
181
tmpfs_node_put(tmp, nnode);
sys/tmpfs/tmpfs_subr.c
190
tmpfs_node_put(tmp, nnode);
sys/tmpfs/tmpfs_subr.c
204
rw_enter_write(&tmp->tm_lock);
sys/tmpfs/tmpfs_subr.c
205
LIST_INSERT_HEAD(&tmp->tm_nodes, nnode, tn_entries);
sys/tmpfs/tmpfs_subr.c
206
rw_exit_write(&tmp->tm_lock);
sys/tmpfs/tmpfs_subr.c
217
tmpfs_free_node(tmpfs_mount_t *tmp, tmpfs_node_t *node)
sys/tmpfs/tmpfs_subr.c
221
rw_enter_write(&tmp->tm_lock);
sys/tmpfs/tmpfs_subr.c
223
rw_exit_write(&tmp->tm_lock);
sys/tmpfs/tmpfs_subr.c
229
tmpfs_strname_free(tmp, node->tn_spec.tn_lnk.tn_link,
sys/tmpfs/tmpfs_subr.c
240
tmpfs_mem_decr(tmp, objsz);
sys/tmpfs/tmpfs_subr.c
250
node == tmp->tm_root);
sys/tmpfs/tmpfs_subr.c
256
rw_enter_write(&tmp->tm_acc_lock);
sys/tmpfs/tmpfs_subr.c
257
if (node->tn_id == tmp->tm_highest_inode)
sys/tmpfs/tmpfs_subr.c
258
--tmp->tm_highest_inode;
sys/tmpfs/tmpfs_subr.c
259
rw_exit_write(&tmp->tm_acc_lock);
sys/tmpfs/tmpfs_subr.c
262
tmpfs_node_put(tmp, node);
sys/tmpfs/tmpfs_subr.c
372
tmpfs_mount_t *tmp = VFS_TO_TMPFS(dvp->v_mount);
sys/tmpfs/tmpfs_subr.c
401
error = tmpfs_alloc_node(tmp, vap->va_type, cnp->cn_cred->cr_uid,
sys/tmpfs/tmpfs_subr.c
407
error = tmpfs_alloc_dirent(tmp, cnp->cn_nameptr, cnp->cn_namelen, &de);
sys/tmpfs/tmpfs_subr.c
409
tmpfs_free_node(tmp, node);
sys/tmpfs/tmpfs_subr.c
417
tmpfs_free_dirent(tmp, de);
sys/tmpfs/tmpfs_subr.c
418
tmpfs_free_node(tmp, node);
sys/tmpfs/tmpfs_subr.c
436
tmpfs_alloc_dirent(tmpfs_mount_t *tmp, const char *name, uint16_t len,
sys/tmpfs/tmpfs_subr.c
441
nde = tmpfs_dirent_get(tmp);
sys/tmpfs/tmpfs_subr.c
445
nde->td_name = tmpfs_strname_alloc(tmp, len);
sys/tmpfs/tmpfs_subr.c
447
tmpfs_dirent_put(tmp, nde);
sys/tmpfs/tmpfs_subr.c
462
tmpfs_free_dirent(tmpfs_mount_t *tmp, tmpfs_dirent_t *de)
sys/tmpfs/tmpfs_subr.c
466
tmpfs_strname_free(tmp, de->td_name, de->td_namelen);
sys/tmpfs/tmpfs_subr.c
467
tmpfs_dirent_put(tmp, de);
sys/tmpfs/tmpfs_subr.c
871
tmpfs_mount_t *tmp = VFS_TO_TMPFS(vp->v_mount);
sys/tmpfs/tmpfs_subr.c
890
if (tmpfs_mem_incr(tmp, bytes) == 0)
sys/tmpfs/tmpfs_subr.c
896
tmpfs_mem_decr(tmp, bytes);
sys/tmpfs/tmpfs_subr.c
917
tmpfs_mem_decr(tmp, (oldpages - newpages) << PAGE_SHIFT);
sys/tmpfs/tmpfs_vfsops.c
102
tmp = mp->mnt_data;
sys/tmpfs/tmpfs_vfsops.c
103
rootvp = tmp->tm_root->tn_vnode;
sys/tmpfs/tmpfs_vfsops.c
111
rw_enter_write(&tmp->tm_lock);
sys/tmpfs/tmpfs_vfsops.c
116
rw_exit_write(&tmp->tm_lock);
sys/tmpfs/tmpfs_vfsops.c
127
tmpfs_mount_t *tmp;
sys/tmpfs/tmpfs_vfsops.c
158
tmp = malloc(sizeof(tmpfs_mount_t), M_MISCFSMNT, M_WAITOK);
sys/tmpfs/tmpfs_vfsops.c
160
tmp->tm_nodes_max = (ino_t)nodes;
sys/tmpfs/tmpfs_vfsops.c
161
tmp->tm_nodes_cnt = 0;
sys/tmpfs/tmpfs_vfsops.c
162
tmp->tm_highest_inode = 1;
sys/tmpfs/tmpfs_vfsops.c
163
LIST_INIT(&tmp->tm_nodes);
sys/tmpfs/tmpfs_vfsops.c
165
rw_init(&tmp->tm_lock, "tmplk");
sys/tmpfs/tmpfs_vfsops.c
166
tmpfs_mntmem_init(tmp, memlimit);
sys/tmpfs/tmpfs_vfsops.c
169
error = tmpfs_alloc_node(tmp, VDIR, args->ta_root_uid,
sys/tmpfs/tmpfs_vfsops.c
181
tmp->tm_root = root;
sys/tmpfs/tmpfs_vfsops.c
183
mp->mnt_data = tmp;
sys/tmpfs/tmpfs_vfsops.c
213
tmpfs_mount_t *tmp = VFS_TO_TMPFS(mp);
sys/tmpfs/tmpfs_vfsops.c
230
LIST_FOREACH(node, &tmp->tm_nodes, tn_entries) {
sys/tmpfs/tmpfs_vfsops.c
242
tmpfs_free_dirent(tmp, de);
sys/tmpfs/tmpfs_vfsops.c
247
while ((node = LIST_FIRST(&tmp->tm_nodes)) != NULL) {
sys/tmpfs/tmpfs_vfsops.c
248
tmpfs_free_node(tmp, node);
sys/tmpfs/tmpfs_vfsops.c
251
if (tmp->tm_mem_limit)
sys/tmpfs/tmpfs_vfsops.c
252
tmpfs_bytes_used -= tmp->tm_mem_limit;
sys/tmpfs/tmpfs_vfsops.c
255
tmpfs_mntmem_destroy(tmp);
sys/tmpfs/tmpfs_vfsops.c
258
free(tmp, M_MISCFSMNT, sizeof(tmpfs_mount_t));
sys/tmpfs/tmpfs_vfsops.c
284
tmpfs_mount_t *tmp = VFS_TO_TMPFS(mp);
sys/tmpfs/tmpfs_vfsops.c
293
rw_enter_write(&tmp->tm_lock);
sys/tmpfs/tmpfs_vfsops.c
294
LIST_FOREACH(node, &tmp->tm_nodes, tn_entries) {
sys/tmpfs/tmpfs_vfsops.c
304
rw_exit_write(&tmp->tm_lock);
sys/tmpfs/tmpfs_vfsops.c
330
tmpfs_mount_t *tmp;
sys/tmpfs/tmpfs_vfsops.c
334
tmp = VFS_TO_TMPFS(mp);
sys/tmpfs/tmpfs_vfsops.c
338
rw_enter_read(&tmp->tm_acc_lock);
sys/tmpfs/tmpfs_vfsops.c
339
avail = tmpfs_pages_avail(tmp);
sys/tmpfs/tmpfs_vfsops.c
340
sbp->f_blocks = tmpfs_pages_total(tmp);
sys/tmpfs/tmpfs_vfsops.c
344
freenodes = MIN(tmp->tm_nodes_max - tmp->tm_nodes_cnt,
sys/tmpfs/tmpfs_vfsops.c
347
sbp->f_files = tmp->tm_nodes_cnt + freenodes;
sys/tmpfs/tmpfs_vfsops.c
350
rw_exit_read(&tmp->tm_acc_lock);
sys/tmpfs/tmpfs_vfsops.c
91
tmpfs_mount_t *tmp;
sys/tmpfs/tmpfs_vnops.c
1048
tmpfs_mount_t *tmp = VFS_TO_TMPFS(vp->v_mount);
sys/tmpfs/tmpfs_vnops.c
1067
tmpfs_free_node(tmp, node);
sys/tmpfs/tmpfs_vnops.c
848
tmpfs_mount_t *tmp = VFS_TO_TMPFS(dvp->v_mount);
sys/tmpfs/tmpfs_vnops.c
908
tmpfs_free_dirent(tmp, de);
sys/ufs/ext2fs/ext2fs_vfsops.c
1061
u_int32_t mask, tmp;
sys/ufs/ext2fs/ext2fs_vfsops.c
1064
tmp = letoh16(fs->e2fs_magic);
sys/ufs/ext2fs/ext2fs_vfsops.c
1065
if (tmp != E2FS_MAGIC) {
sys/ufs/ext2fs/ext2fs_vfsops.c
1066
printf("ext2fs: wrong magic number 0x%x\n", tmp);
sys/ufs/ext2fs/ext2fs_vfsops.c
1070
tmp = letoh32(fs->e2fs_log_bsize);
sys/ufs/ext2fs/ext2fs_vfsops.c
1071
if (tmp > 2) {
sys/ufs/ext2fs/ext2fs_vfsops.c
1073
tmp += 10;
sys/ufs/ext2fs/ext2fs_vfsops.c
1074
printf("ext2fs: wrong log2(block size) %d\n", tmp);
sys/ufs/ext2fs/ext2fs_vfsops.c
1083
tmp = letoh32(fs->e2fs_rev);
sys/ufs/ext2fs/ext2fs_vfsops.c
1084
if (tmp > E2FS_REV1) {
sys/ufs/ext2fs/ext2fs_vfsops.c
1085
printf("ext2fs: wrong revision number 0x%x\n", tmp);
sys/ufs/ext2fs/ext2fs_vfsops.c
1088
else if (tmp == E2FS_REV0)
sys/ufs/ext2fs/ext2fs_vfsops.c
1091
tmp = letoh32(fs->e2fs_first_ino);
sys/ufs/ext2fs/ext2fs_vfsops.c
1092
if (tmp != EXT2_FIRSTINO) {
sys/ufs/ext2fs/ext2fs_vfsops.c
1093
printf("ext2fs: first inode at 0x%x\n", tmp);
sys/ufs/ext2fs/ext2fs_vfsops.c
1097
tmp = letoh32(fs->e2fs_features_incompat);
sys/ufs/ext2fs/ext2fs_vfsops.c
1098
mask = tmp & ~(EXT2F_INCOMPAT_SUPP | EXT4F_RO_INCOMPAT_SUPP);
sys/ufs/ext2fs/ext2fs_vfsops.c
1108
if (!ronly && (tmp & EXT4F_RO_INCOMPAT_SUPP)) {
sys/ufs/ext2fs/ext2fs_vfsops.c
1113
if (tmp & EXT2F_INCOMPAT_RECOVER) {
sys/ufs/ext2fs/ext2fs_vfsops.c
1119
tmp = letoh32(fs->e2fs_features_rocompat) & ~EXT2F_ROCOMPAT_SUPP;
sys/ufs/ext2fs/ext2fs_vfsops.c
1120
if (!ronly && tmp) {
sys/ufs/ext2fs/ext2fs_vfsops.c
1123
if (tmp & ro_compat[i].mask)
sys/ufs/ffs/ffs_vfsops.c
1408
int32_t *lp, tmp; /* XXX */
sys/ufs/ffs/ffs_vfsops.c
1411
tmp = lp[4]; /* XXX */
sys/ufs/ffs/ffs_vfsops.c
1414
lp[0] = tmp; /* XXX */
sys/uvm/uvm_addr.c
172
struct vm_map_entry *tmp, *res;
sys/uvm/uvm_addr.c
174
tmp = RBT_ROOT(uaddr_free_rbtree, free);
sys/uvm/uvm_addr.c
176
while (tmp) {
sys/uvm/uvm_addr.c
177
if (tmp->fspace >= sz) {
sys/uvm/uvm_addr.c
178
res = tmp;
sys/uvm/uvm_addr.c
179
tmp = RBT_LEFT(uaddr_free_rbtree, tmp);
sys/uvm/uvm_addr.c
180
} else if (tmp->fspace < sz)
sys/uvm/uvm_addr.c
181
tmp = RBT_RIGHT(uaddr_free_rbtree, tmp);
sys/uvm/uvm_addr.c
226
vaddr_t tmp;
sys/uvm/uvm_addr.c
241
low_addr = uvm_addr_align_forward(tmp = low_addr, align, offset);
sys/uvm/uvm_addr.c
242
if (low_addr < tmp) /* Overflow during alignment. */
sys/uvm/uvm_addr.c
251
high_addr = uvm_addr_align_backward(tmp = high_addr, align, offset);
sys/uvm/uvm_addr.c
252
if (high_addr > tmp) /* Overflow during alignment. */
sys/uvm/uvm_addr.c
534
vaddr_t tmp;
sys/uvm/uvm_addr.c
559
tmp = hint;
sys/uvm/uvm_addr.c
560
hint = uvm_addr_align_forward(tmp, align, offset);
sys/uvm/uvm_addr.c
562
if (hint < tmp || hint > maxaddr)
sys/uvm/uvm_addr.c
723
vaddr_t tmp;
sys/uvm/uvm_addr.c
727
uvm_addr_fitspace(addr_out, &tmp,
sys/uvm/uvm_amap.c
279
struct vm_amap_chunk *chunk, *tmp;
sys/uvm/uvm_amap.c
385
TAILQ_FOREACH_SAFE(chunk, &amap->am_chunks, ac_list, tmp)
sys/uvm/uvm_amap.c
433
struct vm_amap_chunk *chunk, *tmp;
sys/uvm/uvm_amap.c
449
TAILQ_FOREACH_SAFE(chunk, &amap->am_chunks, ac_list, tmp)
sys/uvm/uvm_map.c
1354
struct vm_map_entry *entry, *tmp;
sys/uvm/uvm_map.c
1356
TAILQ_FOREACH_SAFE(entry, deadq, dfree.deadq, tmp) {
sys/uvm/uvm_map.c
2208
struct vm_map_entry *first, *last, *tmp;
sys/uvm/uvm_map.c
2288
tmp = RBT_NEXT(uvm_map_addr, last);
sys/uvm/uvm_map.c
2290
tmp = last;
sys/uvm/uvm_map.c
2292
uvm_map_pageable_pgon(map, first, tmp, start, end);
sys/uvm/uvm_map.c
2313
tmp = RBT_NEXT(uvm_map_addr, last);
sys/uvm/uvm_map.c
2315
tmp = last;
sys/uvm/uvm_map.c
2317
return uvm_map_pageable_wire(map, first, tmp, start, end,
sys/uvm/uvm_map.c
2464
struct vm_map_entry *entry, *tmp;
sys/uvm/uvm_map.c
2497
if ((tmp = RBT_LEFT(uvm_map_addr, entry)) != NULL)
sys/uvm/uvm_map.c
2498
DEAD_ENTRY_PUSH(&dead_entries, tmp);
sys/uvm/uvm_map.c
2499
if ((tmp = RBT_RIGHT(uvm_map_addr, entry)) != NULL)
sys/uvm/uvm_map.c
2500
DEAD_ENTRY_PUSH(&dead_entries, tmp);
sys/uvm/uvm_map.c
4512
struct vm_map_entry *tmp;
sys/uvm/uvm_map.c
4515
tmp = uvm_mapent_alloc(map, 0);
sys/uvm/uvm_map.c
4518
uvm_map_splitentry(map, entry, tmp, addr);
sys/uvm/uvm_map.c
4533
struct vm_map_entry *tmp;
sys/uvm/uvm_map.c
4543
tmp = uvm_mapent_alloc(map, 0);
sys/uvm/uvm_map.c
4544
uvm_mapent_copy(entry, tmp);
sys/uvm/uvm_map.c
4547
uvm_mapent_addr_insert(map, tmp);
sys/uvm/uvm_map.c
4548
uvm_mapent_free_insert(map, free, tmp);
sys/uvm/uvm_map.c
4551
uvm_map_splitentry(map, tmp, entry, addr);
sys/uvm/uvm_map.c
5010
vaddr_t tmp, pmap_align, pmap_offset;
sys/uvm/uvm_map.c
5027
tmp = (addr & ~(pmap_align - 1)) | pmap_offset;
sys/uvm/uvm_map.c
5028
if (tmp < addr)
sys/uvm/uvm_map.c
5029
tmp += pmap_align;
sys/uvm/uvm_map.c
5030
addr = tmp;
sys/uvm/uvm_map.c
5077
tmp = (addr & ~(pmap_align - 1)) | pmap_offset;
sys/uvm/uvm_map.c
5078
if (tmp < addr)
sys/uvm/uvm_map.c
5079
tmp += pmap_align;
sys/uvm/uvm_map.c
5080
addr = tmp;
usr.bin/awk/run.c
2056
Awkfloat tmp;
usr.bin/awk/run.c
2189
tmp = u;
usr.bin/awk/run.c
2193
tmp = u;
usr.bin/awk/run.c
2197
srand_seed = tmp;
usr.bin/calendar/day.c
269
struct match *matches = NULL, *tmp, *tmp2;
usr.bin/calendar/day.c
453
if ((tmp = malloc(sizeof(struct match))) == NULL)
usr.bin/calendar/day.c
457
tmp->when = f_time - 1 * SECSPERDAY;
usr.bin/calendar/day.c
459
tmp->bodun = 1;
usr.bin/calendar/day.c
461
tmp->when = f_time + v2 * SECSPERDAY;
usr.bin/calendar/day.c
462
tmp->bodun = 0;
usr.bin/calendar/day.c
466
fill_print_date(tmp, &tmtmp);
usr.bin/calendar/day.c
467
tmp->var = varp;
usr.bin/calendar/day.c
468
tmp->next = NULL;
usr.bin/calendar/day.c
469
return(tmp);
usr.bin/calendar/day.c
555
if ((tmp = malloc(sizeof(struct match))) == NULL)
usr.bin/calendar/day.c
557
tmp->when = ttmp;
usr.bin/calendar/day.c
558
fill_print_date(tmp, &tmtmp);
usr.bin/calendar/day.c
559
tmp->bodun = bodun && tdiff == -1;
usr.bin/calendar/day.c
560
tmp->var = varp;
usr.bin/calendar/day.c
561
tmp->next = NULL;
usr.bin/calendar/day.c
563
tmp2->next = tmp;
usr.bin/calendar/day.c
565
matches = tmp;
usr.bin/calendar/day.c
566
tmp2 = tmp;
usr.bin/calendar/io.c
207
tmp = events;
usr.bin/calendar/io.c
208
while (tmp) {
usr.bin/calendar/io.c
209
(void)fprintf(fp, "%s%s\n", tmp->print_date, *(tmp->desc));
usr.bin/calendar/io.c
210
tmp = tmp->next;
usr.bin/calendar/io.c
212
tmp = events;
usr.bin/calendar/io.c
213
while (tmp) {
usr.bin/calendar/io.c
214
events = tmp;
usr.bin/calendar/io.c
215
free(tmp->ldesc);
usr.bin/calendar/io.c
216
tmp = tmp->next;
usr.bin/calendar/io.c
445
struct event *tmp, *tmp2;
usr.bin/calendar/io.c
449
tmp = *head;
usr.bin/calendar/io.c
451
while (tmp->next &&
usr.bin/calendar/io.c
452
tmp->when <= cur_evt->when) {
usr.bin/calendar/io.c
453
tmp2 = tmp;
usr.bin/calendar/io.c
454
tmp = tmp->next;
usr.bin/calendar/io.c
456
if (tmp->when > cur_evt->when) {
usr.bin/calendar/io.c
457
cur_evt->next = tmp;
usr.bin/calendar/io.c
463
cur_evt->next = tmp->next;
usr.bin/calendar/io.c
464
tmp->next = cur_evt;
usr.bin/calendar/io.c
73
struct event *events, *cur_evt, *ev1, *tmp;
usr.bin/cdio/mmc.c
182
u_int16_t feature, profile, tmp;
usr.bin/cdio/mmc.c
192
tmp = htobe16(sizeof(buf));
usr.bin/cdio/mmc.c
193
memcpy(scr.cmd + 7, &tmp, sizeof(u_int16_t));
usr.bin/cdio/mmc.c
439
u_int end_lba, lba, tmp;
usr.bin/cdio/mmc.c
463
tmp = htobe32(lba); /* update lba in cdb */
usr.bin/cdio/mmc.c
464
memcpy(&scr.cmd[2], &tmp, sizeof(tmp));
usr.bin/cdio/mmc.c
512
tmp = htobe32(lba); /* update lba in cdb */
usr.bin/cdio/mmc.c
513
memcpy(&scr.cmd[2], &tmp, sizeof(tmp));
usr.bin/cdio/mmc.c
581
int r, tmp;
usr.bin/cdio/mmc.c
597
memcpy(&tmp, &databuf[16], sizeof(tmp));
usr.bin/cdio/mmc.c
598
*availblk = betoh32(tmp);
usr.bin/cdio/mmc.c
607
int r, tmp;
usr.bin/cdio/mmc.c
623
memcpy(&tmp, &databuf[12], sizeof(tmp));
usr.bin/cdio/mmc.c
624
*nwa = betoh32(tmp);
usr.bin/compress/zopen.c
217
u_char tmp;
usr.bin/compress/zopen.c
235
tmp = (u_char)(zs->zs_maxbits | zs->zs_block_compress);
usr.bin/compress/zopen.c
236
if (write(zs->zs_fd, &tmp, sizeof(tmp)) != sizeof(tmp))
usr.bin/ctfconv/ctfconv.c
310
find_symb(struct itype *tmp, size_t stroff)
usr.bin/ctfconv/ctfconv.c
324
strlcpy(tmp->it_name, p, ITNAME_MAX);
usr.bin/ctfconv/ctfconv.c
326
it = RB_FIND(isymb_tree, &isymbt, tmp);
usr.bin/ctfconv/ctfconv.c
330
strlcpy(tmp->it_name, (strtab + stroff), ITNAME_MAX);
usr.bin/ctfconv/ctfconv.c
338
struct itype *it, tmp;
usr.bin/ctfconv/ctfconv.c
341
memset(&tmp, 0, sizeof(tmp));
usr.bin/ctfconv/ctfconv.c
350
tmp.it_flags = ITF_FUNC;
usr.bin/ctfconv/ctfconv.c
353
tmp.it_flags = ITF_OBJ;
usr.bin/ctfconv/ctfconv.c
359
it = find_symb(&tmp, st->st_name);
usr.bin/ctfconv/ctfconv.c
362
it = it_dup(&tmp);
usr.bin/ctfconv/parse.c
388
ir_add(struct itype *it, struct itype *tmp)
usr.bin/ctfconv/parse.c
392
SIMPLEQ_FOREACH(ir, &tmp->it_refs, ir_next) {
usr.bin/ctfconv/parse.c
399
SIMPLEQ_INSERT_TAIL(&tmp->it_refs, ir, ir_next);
usr.bin/ctfconv/parse.c
462
struct itype *it, *ref, tmp;
usr.bin/ctfconv/parse.c
473
tmp.it_off = it->it_ref + off;
usr.bin/ctfconv/parse.c
474
ref = RB_FIND(ioff_tree, cuot, &tmp);
usr.bin/ctfconv/parse.c
486
tmp.it_off = im->im_ref + off;
usr.bin/ctfconv/parse.c
487
ref = RB_FIND(ioff_tree, cuot, &tmp);
usr.bin/cu/cu.c
177
tmp = find_ucom(line_path, ucomnames);
usr.bin/cu/cu.c
178
if (tmp == NULL)
usr.bin/cu/cu.c
180
line_path = tmp;
usr.bin/cu/cu.c
183
if (asprintf(&tmp, "%s%s", _PATH_DEV, line_path) == -1)
usr.bin/cu/cu.c
185
line_path = tmp;
usr.bin/cu/cu.c
86
char *tmp, *s, *host, *ucomnames;
usr.bin/cvs/buf.c
135
void *tmp;
usr.bin/cvs/buf.c
137
tmp = b->cb_buf;
usr.bin/cvs/buf.c
139
return (tmp);
usr.bin/cvs/diff3.c
323
u_char tmp;
usr.bin/cvs/diff3.c
336
tmp = lp->l_line[lp->l_len - 1];
usr.bin/cvs/diff3.c
343
lp->l_line[lp->l_len - 1] = tmp;
usr.bin/cvs/rcs.c
1060
u_char tmp;
usr.bin/cvs/rcs.c
1074
tmp = lp->l_line[lp->l_len - 1];
usr.bin/cvs/rcs.c
1080
lp->l_line[lp->l_len - 1] = tmp;
usr.bin/cvs/rcs.c
1361
char *tmp, buf[8] = "";
usr.bin/cvs/rcs.c
1380
tmp = xstrdup(buf);
usr.bin/cvs/rcs.c
1382
file->rf_expand = tmp;
usr.bin/cvs/rcs.c
887
char *tmp;
usr.bin/cvs/rcs.c
889
tmp = xstrdup(desc);
usr.bin/cvs/rcs.c
891
file->rf_desc = tmp;
usr.bin/cvs/rcs.c
936
char *tmp;
usr.bin/cvs/rcs.c
938
tmp = xstrdup(comment);
usr.bin/cvs/rcs.c
940
file->rf_comment = tmp;
usr.bin/cvs/rcs.c
952
u_char tmp;
usr.bin/cvs/rcs.c
964
tmp = lp->l_line[lp->l_len - 1];
usr.bin/cvs/rcs.c
973
lp->l_line[lp->l_len - 1] = tmp;
usr.bin/cvs/rcsnum.c
105
char tmp[8];
usr.bin/cvs/rcsnum.c
117
str = rcsnum_itoa(nump->rn_id[i], tmp, sizeof(tmp));
usr.bin/cvs/util.c
153
char tmp[16], *bp;
usr.bin/cvs/util.c
164
if (strlcpy(tmp, "u=", sizeof(tmp)) >= sizeof(tmp) ||
usr.bin/cvs/util.c
165
strlcat(tmp, cvs_modestr[um], sizeof(tmp)) >= sizeof(tmp))
usr.bin/cvs/util.c
168
if (strlcat(buf, tmp, len) >= len)
usr.bin/cvs/util.c
178
if (strlcpy(tmp, "g=", sizeof(tmp)) >= sizeof(tmp) ||
usr.bin/cvs/util.c
179
strlcat(tmp, cvs_modestr[gm], sizeof(tmp)) >= sizeof(tmp))
usr.bin/cvs/util.c
182
if (strlcat(buf, tmp, len) >= len)
usr.bin/cvs/util.c
192
if (strlcpy(tmp, "o=", sizeof(tmp)) >= sizeof(tmp) ||
usr.bin/cvs/util.c
193
strlcat(tmp, cvs_modestr[gm], sizeof(tmp)) >= sizeof(tmp))
usr.bin/cvs/util.c
196
if (strlcat(buf, tmp, len) >= len)
usr.bin/dig/dighost.c
3704
char tmp[NI_MAXHOST];
usr.bin/dig/dighost.c
3720
sockaddrs[i].ss_len, tmp, sizeof(tmp), NULL, 0,
usr.bin/dig/dighost.c
3725
srv = make_server(tmp, host);
usr.bin/dig/dighost.c
452
char tmp[sizeof("ffff:ffff:ffff:ffff:ffff:ffff:255.255.255.255") +
usr.bin/dig/dighost.c
467
tmp, sizeof(tmp));
usr.bin/dig/dighost.c
472
strlcat(tmp, buf, sizeof(tmp));
usr.bin/dig/dighost.c
474
newsrv = make_server(tmp, tmp);
usr.bin/dig/dighost.c
558
char tmp[NI_MAXHOST];
usr.bin/dig/dighost.c
573
sockaddrs[i].ss_len, tmp, sizeof(tmp), NULL, 0,
usr.bin/dig/dighost.c
577
srv = make_server(tmp, opt);
usr.bin/dig/dighost.c
923
uint32_t tmp;
usr.bin/dig/dighost.c
926
tmp = strtonum(arg, 0, max, &errstr);
usr.bin/dig/dighost.c
929
tmp = (tmp + 7) & ~0x7U;
usr.bin/dig/dighost.c
930
return (tmp);
usr.bin/dig/lib/dns/message.c
1700
uint16_t tmp;
usr.bin/dig/lib/dns/message.c
1710
tmp = ((msg->opcode << DNS_MESSAGE_OPCODE_SHIFT)
usr.bin/dig/lib/dns/message.c
1712
tmp |= (msg->rcode & DNS_MESSAGE_RCODE_MASK);
usr.bin/dig/lib/dns/message.c
1713
tmp |= (msg->flags & DNS_MESSAGE_FLAG_MASK);
usr.bin/dig/lib/dns/message.c
1720
isc_buffer_putuint16(target, tmp);
usr.bin/dig/lib/dns/rdata.c
1436
register int tmp = 0;
usr.bin/dig/lib/dns/rdata.c
1443
tmp = 32;
usr.bin/dig/lib/dns/rdata.c
1447
tmp = 64;
usr.bin/dig/lib/dns/rdata.c
1453
(int32_t)(85 * 85 * 85 * 85)) + tmp];
usr.bin/dig/lib/dns/ttl.c
44
char tmp[60];
usr.bin/dig/lib/dns/ttl.c
49
len = snprintf(tmp, sizeof(tmp), "%s%u %s%s",
usr.bin/dig/lib/dns/ttl.c
54
len = snprintf(tmp, sizeof(tmp), "%u%c", t, s[0]);
usr.bin/dig/lib/dns/ttl.c
56
INSIST(len + 1 <= sizeof(tmp));
usr.bin/dig/lib/dns/ttl.c
60
memmove(region.base, tmp, len);
usr.bin/dig/lib/isc/lex.c
63
char *tmp;
usr.bin/dig/lib/isc/lex.c
65
tmp = malloc(lex->max_token * 2 + 1);
usr.bin/dig/lib/isc/lex.c
66
if (tmp == NULL)
usr.bin/dig/lib/isc/lex.c
68
memmove(tmp, lex->data, lex->max_token + 1);
usr.bin/dig/lib/isc/lex.c
69
*currp = tmp + (*currp - lex->data);
usr.bin/dig/lib/isc/lex.c
71
*prevp = tmp + (*prevp - lex->data);
usr.bin/dig/lib/isc/lex.c
73
lex->data = tmp;
usr.bin/dig/lib/isc/sockaddr.c
112
char tmp[NI_MAXHOST];
usr.bin/dig/lib/isc/sockaddr.c
137
tmp, sizeof(tmp), NULL, 0, NI_NUMERICHOST | NI_NUMERICSERV) != 0)
usr.bin/dig/lib/isc/sockaddr.c
139
if (strlen(tmp) > isc_buffer_availablelength(target))
usr.bin/dig/lib/isc/sockaddr.c
141
isc_buffer_putmem(target, tmp, strlen(tmp));
usr.bin/file/file.c
579
char tmp[256] = "";
usr.bin/file/file.c
587
strlcat(tmp, "writable, ", sizeof tmp);
usr.bin/file/file.c
589
strlcat(tmp, "executable, ", sizeof tmp);
usr.bin/file/file.c
591
strlcat(tmp, "regular file, ", sizeof tmp);
usr.bin/file/file.c
592
strlcat(tmp, "no read permission", sizeof tmp);
usr.bin/file/file.c
594
inf->result = xstrdup(tmp);
usr.bin/file/magic-load.c
1073
char *line, *tmp;
usr.bin/file/magic-load.c
1088
tmp = NULL;
usr.bin/file/magic-load.c
1090
while ((slen = getline(&tmp, &size, f)) != -1) {
usr.bin/file/magic-load.c
1091
line = tmp;
usr.bin/file/magic-load.c
1169
free(tmp);
usr.bin/file/magic-test.c
189
char *s, *tmp, *add;
usr.bin/file/magic-test.c
198
if (asprintf(&tmp, ml->result, s) == -1) {
usr.bin/file/magic-test.c
204
if (vasprintf(&tmp, ml->result, ap) == -1) {
usr.bin/file/magic-test.c
212
if (tmp[0] == '\\' && tmp[1] == 'b') {
usr.bin/file/magic-test.c
214
add = tmp + 2;
usr.bin/file/magic-test.c
216
add = tmp;
usr.bin/file/magic-test.c
222
free(tmp);
usr.bin/find/option.c
146
OPTION tmp;
usr.bin/find/option.c
148
tmp.name = name;
usr.bin/find/option.c
149
return ((OPTION *)bsearch(&tmp, options,
usr.bin/ftp/cmds.c
1510
char *tmp;
usr.bin/ftp/cmds.c
1532
tmp = macros[macnum].mac_start;
usr.bin/ftp/cmds.c
1533
while (tmp != macbuf+4096) {
usr.bin/ftp/cmds.c
1539
if ((*tmp = c) == '\n') {
usr.bin/ftp/cmds.c
1540
if (tmp == macros[macnum].mac_start) {
usr.bin/ftp/cmds.c
1541
macros[macnum++].mac_end = tmp;
usr.bin/ftp/cmds.c
1545
if (*(tmp-1) == '\0') {
usr.bin/ftp/cmds.c
1546
macros[macnum++].mac_end = tmp - 1;
usr.bin/ftp/cmds.c
1550
*tmp = '\0';
usr.bin/ftp/cmds.c
1552
tmp++;
usr.bin/ftp/ftp.c
1586
union sockaddr_union tmp;
usr.bin/ftp/ftp.c
1588
tmp = data_addr;
usr.bin/ftp/ftp.c
1589
switch (tmp.sa.sa_family) {
usr.bin/ftp/ftp.c
1597
if (tmp.sa.sa_family == AF_INET6)
usr.bin/ftp/ftp.c
1598
tmp.sin6.sin6_scope_id = 0;
usr.bin/ftp/ftp.c
1599
af_tmp = (tmp.sa.sa_family == AF_INET) ? 1 : 2;
usr.bin/ftp/ftp.c
1600
if (getnameinfo(&tmp.sa, tmp.sa.sa_len, hname,
usr.bin/ftp/main.c
1005
return (tmp);
usr.bin/ftp/main.c
899
char *tmp = argbase; /* will return this if token found */
usr.bin/ftp/ruserpass.c
123
if ((tmp = strchr(hostname, '.')) != NULL &&
usr.bin/ftp/ruserpass.c
124
strcasecmp(tmp, mydomain) == 0 &&
usr.bin/ftp/ruserpass.c
126
(size_t)(tmp - hostname)) == 0 &&
usr.bin/ftp/ruserpass.c
127
tokval[tmp - hostname] == '\0')
usr.bin/ftp/ruserpass.c
129
if ((tmp = strchr(host, '.')) != NULL &&
usr.bin/ftp/ruserpass.c
130
strcasecmp(tmp, mydomain) == 0 &&
usr.bin/ftp/ruserpass.c
132
(size_t)(tmp - host)) == 0 &&
usr.bin/ftp/ruserpass.c
133
tokval[tmp - host] == '\0')
usr.bin/ftp/ruserpass.c
200
tmp = macros[macnum].mac_name;
usr.bin/ftp/ruserpass.c
201
*tmp++ = c;
usr.bin/ftp/ruserpass.c
204
*tmp++ = c;
usr.bin/ftp/ruserpass.c
211
*tmp = '\0';
usr.bin/ftp/ruserpass.c
227
tmp = macros[macnum].mac_start;
usr.bin/ftp/ruserpass.c
228
while (tmp != macbuf + 4096) {
usr.bin/ftp/ruserpass.c
234
*tmp = c;
usr.bin/ftp/ruserpass.c
235
if (*tmp == '\n') {
usr.bin/ftp/ruserpass.c
236
if (tmp == macros[macnum].mac_start) {
usr.bin/ftp/ruserpass.c
237
macros[macnum++].mac_end = tmp;
usr.bin/ftp/ruserpass.c
239
} else if (*(tmp-1) == '\0') {
usr.bin/ftp/ruserpass.c
241
tmp - 1;
usr.bin/ftp/ruserpass.c
244
*tmp = '\0';
usr.bin/ftp/ruserpass.c
246
tmp++;
usr.bin/ftp/ruserpass.c
248
if (tmp == macbuf + 4096) {
usr.bin/ftp/ruserpass.c
78
char *hdir, buf[PATH_MAX], *tmp;
usr.bin/ftp/util.c
218
char tmp[80], *acctname = NULL, host_name[HOST_NAME_MAX+1];
usr.bin/ftp/util.c
281
if (fgets(tmp, sizeof(tmp), stdin) != NULL) {
usr.bin/ftp/util.c
282
tmp[strcspn(tmp, "\n")] = '\0';
usr.bin/ftp/util.c
283
if (tmp[0] != '\0')
usr.bin/ftp/util.c
284
user = tmp;
usr.bin/gencat/gencat.c
313
char *tmp;
usr.bin/gencat/gencat.c
314
tmp = cptr + 1;
usr.bin/gencat/gencat.c
316
if (*tmp && (!ISSPACE(*tmp) || *wskip(tmp))) {
usr.bin/gprof/gprof.c
275
struct gmonhdr tmp;
usr.bin/gprof/gprof.c
282
if (fread(&tmp, sizeof(struct gmonhdr), 1, pfile) != 1)
usr.bin/gprof/gprof.c
284
if ( s_highpc != 0 && ( tmp.lpc != gmonhdr.lpc ||
usr.bin/gprof/gprof.c
285
tmp.hpc != gmonhdr.hpc || tmp.ncnt != gmonhdr.ncnt))
usr.bin/gprof/gprof.c
287
gmonhdr = tmp;
usr.bin/join/join.c
269
LINE *lp, *lastlp, tmp;
usr.bin/join/join.c
311
tmp = F->set[F->setcnt];
usr.bin/join/join.c
313
F->set[F->pushback] = tmp;
usr.bin/lam/lam.c
118
void *tmp;
usr.bin/lam/lam.c
195
tmp = recallocarray(input, inputsize,
usr.bin/lam/lam.c
197
if (tmp == NULL)
usr.bin/lam/lam.c
199
input = tmp;
usr.bin/lex/tblcmp.c
236
int *tmp = tmpstorage, i, j;
usr.bin/lex/tblcmp.c
269
tmp[tecbck[j]] = trans;
usr.bin/lex/tblcmp.c
275
tmp[j] = trans;
usr.bin/lex/tblcmp.c
291
mkentry(tmp, nummecs, lastdfa + i + 1, JAMSTATE,
usr.bin/lex/tblcmp.c
700
int i, numdiff, tmpbase, tmp[CSIZE + 1];
usr.bin/lex/tblcmp.c
743
numdiff = tbldiff(state, firstprot, tmp);
usr.bin/lex/tblcmp.c
744
mkentry(tmp, numecs, statenum, -numtemps, numdiff);
usr.bin/m4/eval.c
907
const char *tmp;
usr.bin/m4/eval.c
942
tmp = from;
usr.bin/m4/eval.c
968
while (*tmp) {
usr.bin/m4/eval.c
969
mapvec[(unsigned char)(*tmp)] = (unsigned char)(*tmp);
usr.bin/m4/eval.c
970
tmp++;
usr.bin/make/targequiv.c
184
GNode *tmp;
usr.bin/make/targequiv.c
186
tmp = gn->sibling;
usr.bin/make/targequiv.c
188
extra->sibling = tmp;
usr.bin/mandoc/read.c
85
struct buf *tmp;
usr.bin/mandoc/read.c
88
tmp = buf;
usr.bin/mandoc/read.c
89
buf = tmp->next;
usr.bin/mandoc/read.c
90
free(tmp->buf);
usr.bin/mandoc/read.c
91
free(tmp);
usr.bin/mg/basic.c
275
char tmp[5];
usr.bin/mg/basic.c
286
col += snprintf(tmp, sizeof(tmp), "\\%o", c);
usr.bin/mg/cmode.c
405
char tmp[5];
usr.bin/mg/cmode.c
419
col += snprintf(tmp, sizeof(tmp), "\\%o", c);
usr.bin/mg/cscope.c
565
char fname[NFILEN], *dir, *path, *pathc, *tmp;
usr.bin/mg/cscope.c
575
if ((tmp = getenv("PATH")) == NULL)
usr.bin/mg/cscope.c
577
if ((pathc = path = strndup(tmp, NFILEN)) == NULL)
usr.bin/mg/dired.c
1184
int tmp;
usr.bin/mg/dired.c
1187
tmp = 0;
usr.bin/mg/dired.c
1189
tmp++;
usr.bin/mg/dired.c
1196
curwp->w_dotline = tmp;
usr.bin/mg/dired.c
1198
tmp--;
usr.bin/mg/dired.c
1203
if (tmp == curbp->b_lines - 1) {
usr.bin/mg/dired.c
425
int tmp;
usr.bin/mg/dired.c
427
tmp = curwp->w_dotline;
usr.bin/mg/dired.c
438
curwp->w_dotline = tmp;
usr.bin/mg/dired.c
445
curwp->w_dotline = tmp;
usr.bin/mg/dired.c
455
curwp->w_dotline = tmp;
usr.bin/mg/dired.c
462
if (tmp > curwp->w_dotline)
usr.bin/mg/dired.c
463
tmp--;
usr.bin/mg/dired.c
467
curwp->w_dotline = tmp;
usr.bin/mg/display.c
150
void *tmp; \
usr.bin/mg/display.c
151
if ((tmp = realloc((a), (n))) == NULL) { \
usr.bin/mg/display.c
154
(a) = tmp; \
usr.bin/mg/display.c
158
void *tmp; \
usr.bin/mg/display.c
159
if ((tmp = reallocarray((a), (n), (m))) == NULL) {\
usr.bin/mg/display.c
162
(a) = tmp; \
usr.bin/mg/echo.c
858
char kname[NKNAME], tmp[100], *cp;
usr.bin/mg/echo.c
892
snprintf(tmp, sizeof(tmp), "%p",
usr.bin/mg/echo.c
894
eputs(tmp);
usr.bin/mg/extend.c
486
char tmp[32], *bufp;
usr.bin/mg/extend.c
490
if ((bufp = eread("%s", tmp, sizeof(tmp), EFNEW, buf)) == NULL)
usr.bin/mg/extend.c
494
(void)strlcat(buf, tmp, sizeof(buf));
usr.bin/mg/extend.c
495
if ((mp = name_map(tmp)) == NULL)
usr.bin/mg/extend.c
496
return (dobeep_msgs("Unknown map", tmp));
usr.bin/mg/extend.c
681
char *funcp, *tmp;
usr.bin/mg/extend.c
715
nl = strtol(argp, &tmp, 10);
usr.bin/mg/extend.c
716
if (*tmp != '\0')
usr.bin/mg/file.c
510
char fname[NFILEN], bn[NBUFN], tmp[NFILEN + 25];
usr.bin/mg/file.c
533
snprintf(tmp, sizeof(tmp), "File `%s' exists; overwrite",
usr.bin/mg/file.c
535
if ((s = eyorn(tmp)) != TRUE)
usr.bin/mg/line.c
70
char *tmp;
usr.bin/mg/line.c
73
if ((tmp = realloc(lp->l_text, newsize)) == NULL)
usr.bin/mg/line.c
75
lp->l_text = tmp;
usr.bin/mg/log.c
163
char buf[4096], tmp[1024];
usr.bin/mg/log.c
184
snprintf(tmp, sizeof(tmp), "%.*s",
usr.bin/mg/log.c
187
(void)strlcat(buf, tmp, sizeof(buf));
usr.bin/mg/log.c
190
snprintf(tmp, sizeof(tmp), " [%d]", rec->region.r_size);
usr.bin/mg/log.c
191
if (strlcat(buf, tmp, sizeof(buf)) >= sizeof(buf)) {
usr.bin/mg/log.c
197
tmp[0] = buf[0] = '\0';
usr.bin/mg/log.c
209
char *curline, *tmp, o;
usr.bin/mg/log.c
229
tmp = " ";
usr.bin/mg/log.c
231
tmp = lp->l_text;
usr.bin/mg/log.c
236
lp->l_size, lp->l_used, o, tmp);
usr.bin/mg/log.c
393
char tmp[NFILEN], *tmp2;
usr.bin/mg/log.c
395
if (strlcpy(tmp, mglogdir, sizeof(tmp)) >
usr.bin/mg/log.c
396
sizeof(tmp))
usr.bin/mg/log.c
398
if (strlcat(tmp, mglogfile, sizeof(tmp)) >
usr.bin/mg/log.c
399
sizeof(tmp))
usr.bin/mg/log.c
401
if ((tmp2 = strndup(tmp, NFILEN)) == NULL)
usr.bin/mg/undo.c
390
char buf[4096], tmp[1024];
usr.bin/mg/undo.c
424
snprintf(tmp, sizeof(tmp), "%.*s", rec->region.r_size,
usr.bin/mg/undo.c
426
(void)strlcat(buf, tmp, sizeof(buf));
usr.bin/mg/undo.c
429
snprintf(tmp, sizeof(tmp), " [%d]", rec->region.r_size);
usr.bin/mg/undo.c
430
if (strlcat(buf, tmp, sizeof(buf)) >= sizeof(buf)) {
usr.bin/mg/util.c
108
char tmp[5];
usr.bin/mg/util.c
122
col += snprintf(tmp, sizeof(tmp), "\\%o", c);
usr.bin/mixerctl/mixerctl.c
70
char tmp[FIELD_NAME_MAX];
usr.bin/mixerctl/mixerctl.c
72
snprintf(tmp, FIELD_NAME_MAX, "%s.%s", p, q);
usr.bin/mixerctl/mixerctl.c
73
strlcpy(out, tmp, FIELD_NAME_MAX);
usr.bin/nc/netcat.c
1505
char *tmp;
usr.bin/nc/netcat.c
1508
if (asprintf(&tmp, "%d", hi) != -1)
usr.bin/nc/netcat.c
1509
portlist[0] = tmp;
usr.bin/newsyslog/newsyslog.c
180
struct conf_entry *p, *q, *tmp;
usr.bin/newsyslog/newsyslog.c
202
TAILQ_FOREACH_SAFE(q, &config, next, tmp)
usr.bin/newsyslog/newsyslog.c
472
char line[BUFSIZ], *parse, *q, *errline, *group, *tmp, *ep;
usr.bin/newsyslog/newsyslog.c
491
tmp = sob(line);
usr.bin/newsyslog/newsyslog.c
492
if (*tmp == '\0' || *tmp == '#')
usr.bin/newsyslog/newsyslog.c
494
errline = strdup(tmp);
usr.bin/newsyslog/newsyslog.c
693
} else if (*q == '"' && (tmp = strchr(q + 1, '"'))) {
usr.bin/newsyslog/newsyslog.c
694
*(parse = tmp) = '\0';
usr.bin/newsyslog/newsyslog.c
929
char *base, tmp[PATH_MAX];
usr.bin/newsyslog/newsyslog.c
933
snprintf(tmp, sizeof(tmp), "%s/%s.0", ent->backdir,
usr.bin/newsyslog/newsyslog.c
936
snprintf(tmp, sizeof(tmp), "%s.0", ent->log);
usr.bin/newsyslog/newsyslog.c
943
printf("%s %s\n", base, tmp);
usr.bin/newsyslog/newsyslog.c
950
(void)execl(COMPRESS, base, "-f", tmp, (char *)NULL);
usr.bin/openssl/apps.c
371
char *tmp, tpass[APP_PASS_LEN];
usr.bin/openssl/apps.c
379
tmp = getenv(arg + 4);
usr.bin/openssl/apps.c
380
if (!tmp) {
usr.bin/openssl/apps.c
385
return strdup(tmp);
usr.bin/openssl/apps.c
438
tmp = strchr(tpass, '\n');
usr.bin/openssl/apps.c
439
if (tmp)
usr.bin/openssl/apps.c
440
*tmp = 0;
usr.bin/openssl/asn1pars.c
312
BIO *tmp;
usr.bin/openssl/asn1pars.c
317
tmp = in;
usr.bin/openssl/asn1pars.c
319
b64 = tmp;
usr.bin/openssl/ca.c
2648
char *tmp = NULL;
usr.bin/openssl/ca.c
2688
free(tmp);
usr.bin/openssl/ca.c
2744
char *tmp = NULL;
usr.bin/openssl/ca.c
2752
if ((tmp = strdup(str)) == NULL) {
usr.bin/openssl/ca.c
2756
p = strchr(tmp, ',');
usr.bin/openssl/ca.c
2757
rtime_str = tmp;
usr.bin/openssl/ca.c
2836
free(tmp);
usr.bin/openssl/cms.c
1810
BIO *tmp;
usr.bin/openssl/cms.c
1814
tmp = BIO_new_file(signerfile, "w");
usr.bin/openssl/cms.c
1815
if (tmp == NULL)
usr.bin/openssl/cms.c
1818
PEM_write_bio_X509(tmp, sk_X509_value(signers, i));
usr.bin/openssl/cms.c
1819
BIO_free(tmp);
usr.bin/openssl/req.c
1133
char *tmp, *dn_sect, *attr_sect;
usr.bin/openssl/req.c
1135
tmp = NCONF_get_string(req_conf, SECTION, PROMPT);
usr.bin/openssl/req.c
1136
if (tmp == NULL)
usr.bin/openssl/req.c
1138
if ((tmp != NULL) && !strcmp(tmp, "no"))
usr.bin/openssl/req.c
1575
const char *tmp;
usr.bin/openssl/req.c
1580
tmp = str + slen - elen;
usr.bin/openssl/req.c
1581
return strcmp(tmp, end);
usr.bin/openssl/smime.c
1085
BIO *tmp;
usr.bin/openssl/smime.c
1089
tmp = BIO_new_file(signerfile, "w");
usr.bin/openssl/smime.c
1090
if (tmp == NULL)
usr.bin/openssl/smime.c
1093
PEM_write_bio_X509(tmp, sk_X509_value(signers, i));
usr.bin/openssl/smime.c
1094
BIO_free(tmp);
usr.bin/patch/pch.c
1423
size_t min_components, min_baselen, min_len, tmp;
usr.bin/patch/pch.c
1440
if ((tmp = num_components(path)) > min_components)
usr.bin/patch/pch.c
1442
if (tmp < min_components) {
usr.bin/patch/pch.c
1443
min_components = tmp;
usr.bin/patch/pch.c
1449
if ((tmp = strlen(bn)) > min_baselen)
usr.bin/patch/pch.c
1451
if (tmp < min_baselen) {
usr.bin/patch/pch.c
1452
min_baselen = tmp;
usr.bin/patch/pch.c
1455
if ((tmp = strlen(path)) > min_len)
usr.bin/patch/pch.c
1457
min_len = tmp;
usr.bin/patch/pch.c
381
struct file_name tmp = names[OLD_FILE];
usr.bin/patch/pch.c
383
names[NEW_FILE] = tmp;
usr.bin/rcs/buf.c
155
void *tmp;
usr.bin/rcs/buf.c
157
tmp = b->cb_buf;
usr.bin/rcs/buf.c
159
return (tmp);
usr.bin/rcs/diff3.c
420
u_char tmp;
usr.bin/rcs/diff3.c
433
tmp = lp->l_line[lp->l_len - 1];
usr.bin/rcs/diff3.c
441
lp->l_line[lp->l_len - 1] = tmp;
usr.bin/rcs/rcs.c
1052
u_char tmp;
usr.bin/rcs/rcs.c
1067
tmp = lp->l_line[lp->l_len - 1];
usr.bin/rcs/rcs.c
1073
lp->l_line[lp->l_len - 1] = tmp;
usr.bin/rcs/rcs.c
1337
char *tmp, buf[8] = "";
usr.bin/rcs/rcs.c
1356
tmp = xstrdup(buf);
usr.bin/rcs/rcs.c
1358
file->rf_expand = tmp;
usr.bin/rcs/rcs.c
777
char *tmp;
usr.bin/rcs/rcs.c
779
tmp = xstrdup(desc);
usr.bin/rcs/rcs.c
781
file->rf_desc = tmp;
usr.bin/rcs/rcs.c
793
char *tmp;
usr.bin/rcs/rcs.c
795
tmp = xstrdup(comment);
usr.bin/rcs/rcs.c
797
file->rf_comment = tmp;
usr.bin/rcs/rcs.c
807
u_char tmp;
usr.bin/rcs/rcs.c
819
tmp = lp->l_line[lp->l_len - 1];
usr.bin/rcs/rcs.c
828
lp->l_line[lp->l_len - 1] = tmp;
usr.bin/rcs/rcsnum.c
128
char tmp[8];
usr.bin/rcs/rcsnum.c
140
str = rcsnum_itoa(nump->rn_id[i], tmp, sizeof(tmp));
usr.bin/rpcgen/rpc_main.c
437
char *filename, *guard, *tmp, *tmp2;
usr.bin/rpcgen/rpc_main.c
448
tmp = guard;
usr.bin/rpcgen/rpc_main.c
449
while (*tmp) {
usr.bin/rpcgen/rpc_main.c
450
if (islower((unsigned char)*tmp))
usr.bin/rpcgen/rpc_main.c
451
*tmp = toupper((unsigned char)*tmp);
usr.bin/rpcgen/rpc_main.c
452
tmp++;
usr.bin/rpcgen/rpc_parse.c
380
char tmp[100];
usr.bin/rpcgen/rpc_parse.c
384
snprintf(tmp, sizeof tmp,
usr.bin/rpcgen/rpc_parse.c
386
error(tmp);
usr.bin/rpcgen/rpc_parse.c
392
snprintf(tmp, sizeof tmp,
usr.bin/rpcgen/rpc_parse.c
395
error(tmp);
usr.bin/rpcinfo/rpcinfo.c
139
if (getul(optarg, &tmp))
usr.bin/rpcinfo/rpcinfo.c
141
if (tmp >= 65536)
usr.bin/rpcinfo/rpcinfo.c
143
portnum = (u_short)tmp;
usr.bin/rpcinfo/rpcinfo.c
93
u_long tmp;
usr.bin/sort/bwstring.c
54
char *tmp;
usr.bin/sort/bwstring.c
66
tmp = nl_langinfo(item[i]);
usr.bin/sort/bwstring.c
68
printf("month[%d]=%s\n", i, tmp);
usr.bin/sort/bwstring.c
69
if (*tmp == '\0')
usr.bin/sort/bwstring.c
71
m = sort_strdup(tmp);
usr.bin/sort/bwstring.c
72
len = strlen(tmp);
usr.bin/sort/bwstring.c
87
tmp = nl_langinfo(item[i]);
usr.bin/sort/bwstring.c
89
printf("month[%d]=%s\n", i, tmp);
usr.bin/sort/bwstring.c
90
if (*tmp == '\0')
usr.bin/sort/bwstring.c
92
len = strlen(tmp);
usr.bin/sort/bwstring.c
95
if (mbstowcs(m, tmp, len) == (size_t)-1) {
usr.bin/sort/coll.c
490
const struct bwstring *tmp;
usr.bin/sort/coll.c
492
tmp = s1;
usr.bin/sort/coll.c
494
s2 = tmp;
usr.bin/sort/file.c
1027
if (fl->tmp) {
usr.bin/sort/file.c
1036
fl->tmp = false; /* already taken care of */
usr.bin/sort/file.c
1042
fl->tmp = new_fl.tmp;
usr.bin/sort/file.c
180
file_list_init(struct file_list *fl, bool tmp)
usr.bin/sort/file.c
185
fl->tmp = tmp;
usr.bin/sort/file.c
227
if (fl->tmp)
usr.bin/sort/file.c
238
fl->tmp = false;
usr.bin/sort/file.c
819
struct file_header *tmp;
usr.bin/sort/file.c
821
tmp = fh[i1];
usr.bin/sort/file.c
823
fh[i2] = tmp;
usr.bin/sort/file.c
925
struct bwstring *tmp;
usr.bin/sort/file.c
927
tmp = file_reader_readline(fh->fr);
usr.bin/sort/file.c
928
if (tmp == NULL) {
usr.bin/sort/file.c
939
sort_list_item_set(fh->si, tmp);
usr.bin/sort/file.h
105
void file_list_init(struct file_list *fl, bool tmp);
usr.bin/sort/file.h
68
bool tmp;
usr.bin/ssh/addr.c
458
struct xaddr tmp;
usr.bin/ssh/addr.c
475
if (addr_pton(addrbuf, &tmp) == -1)
usr.bin/ssh/addr.c
479
masklen = addr_unicast_masklen(tmp.af);
usr.bin/ssh/addr.c
480
if (masklen_valid(tmp.af, masklen) == -1)
usr.bin/ssh/addr.c
482
if (addr_host_is_all0s(&tmp, masklen) != 0)
usr.bin/ssh/addr.c
486
memcpy(n, &tmp, sizeof(*n));
usr.bin/ssh/auth-options.c
254
char *opt, *tmp, *cp, *host, **permits = *permitsp;
usr.bin/ssh/auth-options.c
270
if (asprintf(&tmp, "*:%s", opt) == -1) {
usr.bin/ssh/auth-options.c
276
opt = tmp;
usr.bin/ssh/auth-options.c
278
if ((tmp = strdup(opt)) == NULL) {
usr.bin/ssh/auth-options.c
283
cp = tmp;
usr.bin/ssh/auth-options.c
287
free(tmp);
usr.bin/ssh/auth-options.c
298
free(tmp);
usr.bin/ssh/auth-options.c
304
free(tmp);
usr.bin/ssh/auth-options.c
322
char **oarray, *opt, *cp, *tmp;
usr.bin/ssh/auth-options.c
408
if ((tmp = strchr(opt, '=')) == NULL) {
usr.bin/ssh/auth-options.c
417
l = (size_t)(tmp - opt);
usr.bin/ssh/auth-options.c
535
const char *tmp;
usr.bin/ssh/auth-options.c
547
tmp = primary->required_from_host_cert;
usr.bin/ssh/auth-options.c
548
if (tmp == NULL)
usr.bin/ssh/auth-options.c
549
tmp = additional->required_from_host_cert;
usr.bin/ssh/auth-options.c
550
if (tmp != NULL && (ret->required_from_host_cert = strdup(tmp)) == NULL)
usr.bin/ssh/auth-options.c
552
tmp = primary->required_from_host_keys;
usr.bin/ssh/auth-options.c
553
if (tmp == NULL)
usr.bin/ssh/auth-options.c
554
tmp = additional->required_from_host_keys;
usr.bin/ssh/auth-options.c
555
if (tmp != NULL && (ret->required_from_host_keys = strdup(tmp)) == NULL)
usr.bin/ssh/auth-options.c
734
u_int tmp;
usr.bin/ssh/auth-options.c
737
if ((r = sshbuf_get_u32(m, &tmp)) != 0 ||
usr.bin/ssh/auth-options.c
740
if (tmp > INT_MAX) {
usr.bin/ssh/auth-options.c
744
n = tmp;
usr.bin/ssh/auth-options.c
851
u_int tmp;
usr.bin/ssh/auth-options.c
880
(r = sshbuf_get_u32(m, &tmp)) != 0)
usr.bin/ssh/auth-options.c
882
opts->force_tun_device = f ? -1 : (int)tmp;
usr.bin/ssh/auth2-pubkey.c
383
char *tmp, *username = NULL, *command = NULL, **av = NULL;
usr.bin/ssh/auth2-pubkey.c
449
tmp = percent_expand(av[i],
usr.bin/ssh/auth2-pubkey.c
464
if (tmp == NULL)
usr.bin/ssh/auth2-pubkey.c
467
av[i] = tmp;
usr.bin/ssh/auth2-pubkey.c
663
char uidstr[32], *tmp, *command = NULL, **av = NULL;
usr.bin/ssh/auth2-pubkey.c
716
tmp = percent_expand(av[i],
usr.bin/ssh/auth2-pubkey.c
726
if (tmp == NULL)
usr.bin/ssh/auth2-pubkey.c
729
av[i] = tmp;
usr.bin/ssh/auth2.c
674
struct sshkey **tmp, *dup;
usr.bin/ssh/auth2.c
689
(tmp = recallocarray(authctxt->prev_keys, authctxt->nprev_keys,
usr.bin/ssh/auth2.c
692
authctxt->prev_keys = tmp;
usr.bin/ssh/bitmap.c
82
BITMAP_WTYPE *tmp;
usr.bin/ssh/bitmap.c
89
if ((tmp = recallocarray(b->d, b->len,
usr.bin/ssh/bitmap.c
92
b->d = tmp;
usr.bin/ssh/chacha.c
116
for (i = 0;i < bytes;++i) tmp[i] = m[i];
usr.bin/ssh/chacha.c
117
m = tmp;
usr.bin/ssh/chacha.c
119
c = tmp;
usr.bin/ssh/chacha.c
92
u8 tmp[64];
usr.bin/ssh/clientloop.c
2106
struct sshkey **tmp;
usr.bin/ssh/clientloop.c
2172
if ((tmp = recallocarray(ctx->old_keys, ctx->nold, ctx->nold + 1,
usr.bin/ssh/clientloop.c
2175
ctx->old_keys = tmp;
usr.bin/ssh/clientloop.c
2453
struct sshkey *key = NULL, **tmp;
usr.bin/ssh/clientloop.c
2506
if ((tmp = recallocarray(ctx->keys, ctx->nkeys, ctx->nkeys + 1,
usr.bin/ssh/clientloop.c
2510
ctx->keys = tmp;
usr.bin/ssh/clientloop.c
532
struct timespec tmp;
usr.bin/ssh/clientloop.c
558
tmp.tv_sec = interval_ns / (1000 * 1000 * 1000);
usr.bin/ssh/clientloop.c
559
tmp.tv_nsec = interval_ns % (1000 * 1000 * 1000);
usr.bin/ssh/clientloop.c
561
timespecadd(now, &tmp, next_interval);
usr.bin/ssh/clientloop.c
574
struct timespec now, tmp;
usr.bin/ssh/clientloop.c
645
ms_to_timespec(&tmp, SSH_KEYSTROKE_CHAFF_MIN_MS +
usr.bin/ssh/clientloop.c
647
timespecadd(&now, &tmp, &chaff_until);
usr.bin/ssh/dh.c
235
BIGNUM *tmp;
usr.bin/ssh/dh.c
249
if ((tmp = BN_new()) == NULL) {
usr.bin/ssh/dh.c
253
if (!BN_sub(tmp, dh_p, BN_value_one()) ||
usr.bin/ssh/dh.c
254
BN_cmp(dh_pub, tmp) != -1) { /* pub_exp > p-2 */
usr.bin/ssh/dh.c
255
BN_clear_free(tmp);
usr.bin/ssh/dh.c
259
BN_clear_free(tmp);
usr.bin/ssh/hostfile.c
233
struct hostkey_entry *tmp;
usr.bin/ssh/hostfile.c
246
if ((tmp = recallocarray(hostkeys->entries, hostkeys->num_entries,
usr.bin/ssh/hostfile.c
249
hostkeys->entries = tmp;
usr.bin/ssh/kex-names.c
194
char *ret = NULL, *tmp = NULL, *cp, *p;
usr.bin/ssh/kex-names.c
204
if ((tmp = cp = strdup(b)) == NULL ||
usr.bin/ssh/kex-names.c
206
free(tmp);
usr.bin/ssh/kex-names.c
215
free(tmp);
usr.bin/ssh/kex-names.c
220
free(tmp);
usr.bin/ssh/kex-names.c
234
char *cp, *tmp, *patterns;
usr.bin/ssh/kex-names.c
251
if ((tmp = kex_names_cat(def, list + 1)) == NULL) {
usr.bin/ssh/kex-names.c
256
list = tmp;
usr.bin/ssh/kex-names.c
268
if ((tmp = kex_names_cat(list + 1, def)) == NULL) {
usr.bin/ssh/kex-names.c
273
list = tmp;
usr.bin/ssh/kex-names.c
300
if ((tmp = kex_names_cat(ret, matching)) == NULL) {
usr.bin/ssh/kex-names.c
305
ret = tmp;
usr.bin/ssh/kexgen.c
146
struct sshbuf *tmp = NULL, *server_host_key_blob = NULL;
usr.bin/ssh/kexgen.c
159
if ((tmp = sshbuf_fromb(server_host_key_blob)) == NULL) {
usr.bin/ssh/kexgen.c
163
if ((r = sshkey_fromb(tmp, &server_host_key)) != 0)
usr.bin/ssh/kexgen.c
255
sshbuf_free(tmp);
usr.bin/ssh/kexgexc.c
145
struct sshbuf *tmp = NULL, *server_host_key_blob = NULL;
usr.bin/ssh/kexgexc.c
159
if ((tmp = sshbuf_fromb(server_host_key_blob)) == NULL) {
usr.bin/ssh/kexgexc.c
163
if ((r = sshkey_fromb(tmp, &server_host_key)) != 0 ||
usr.bin/ssh/kexgexc.c
230
sshbuf_free(tmp);
usr.bin/ssh/log.c
156
char **tmp;
usr.bin/ssh/log.c
159
if ((tmp = recallocarray(log_verbose, nlog_verbose, nlog_verbose + 1,
usr.bin/ssh/log.c
161
log_verbose = tmp;
usr.bin/ssh/match.c
319
char *cp, *tmp;
usr.bin/ssh/match.c
328
tmp = orig_prop;
usr.bin/ssh/match.c
330
while ((cp = strsep(&tmp, ",")) != NULL) {
usr.bin/ssh/misc.c
1057
char *uridup, *cp, *tmp, ch;
usr.bin/ssh/misc.c
1076
uridup = tmp = xstrdup(uri);
usr.bin/ssh/misc.c
1079
if ((cp = strchr(tmp, '@')) != NULL) {
usr.bin/ssh/misc.c
1084
if ((delim = strchr(tmp, ';')) != NULL) {
usr.bin/ssh/misc.c
1088
if (*tmp == '\0') {
usr.bin/ssh/misc.c
1092
if ((user = urldecode(tmp)) == NULL)
usr.bin/ssh/misc.c
1094
tmp = cp + 1;
usr.bin/ssh/misc.c
1098
if ((cp = hpdelim2(&tmp, &ch)) == NULL || *cp == '\0')
usr.bin/ssh/misc.c
1104
if (tmp != NULL && *tmp != '\0') {
usr.bin/ssh/misc.c
1107
if ((cp = strchr(tmp, '/')) != NULL)
usr.bin/ssh/misc.c
1109
if ((port = a2port(tmp)) <= 0)
usr.bin/ssh/misc.c
1111
tmp = cp ? cp + 1 : NULL;
usr.bin/ssh/misc.c
1113
if (tmp != NULL && *tmp != '\0') {
usr.bin/ssh/misc.c
1115
if ((path = urldecode(tmp)) == NULL)
usr.bin/ssh/misc.c
861
char *sdup, *tmp;
usr.bin/ssh/misc.c
874
if ((tmp = colon(sdup)) == NULL)
usr.bin/ssh/misc.c
878
*tmp++ = '\0';
usr.bin/ssh/misc.c
879
if (*tmp == '\0')
usr.bin/ssh/misc.c
880
tmp = ".";
usr.bin/ssh/misc.c
881
path = xstrdup(tmp);
usr.bin/ssh/misc.c
884
tmp = strrchr(sdup, '@');
usr.bin/ssh/misc.c
885
if (tmp != NULL) {
usr.bin/ssh/misc.c
886
*tmp++ = '\0';
usr.bin/ssh/misc.c
887
host = xstrdup(cleanhostname(tmp));
usr.bin/ssh/misc.c
928
char *sdup, *cp, *tmp;
usr.bin/ssh/misc.c
939
if ((sdup = tmp = strdup(s)) == NULL)
usr.bin/ssh/misc.c
942
if ((cp = strrchr(tmp, '@')) != NULL) {
usr.bin/ssh/misc.c
944
if (*tmp == '\0')
usr.bin/ssh/misc.c
946
if ((user = strdup(tmp)) == NULL)
usr.bin/ssh/misc.c
948
tmp = cp + 1;
usr.bin/ssh/misc.c
951
if ((cp = hpdelim(&tmp)) == NULL || *cp == '\0')
usr.bin/ssh/misc.c
955
if (tmp != NULL && *tmp != '\0') {
usr.bin/ssh/misc.c
956
if ((port = a2port(tmp)) <= 0)
usr.bin/ssh/moduli.c
403
char tmp[PATH_MAX];
usr.bin/ssh/moduli.c
406
r = snprintf(tmp, sizeof(tmp), "%s.XXXXXXXXXX", cpfile);
usr.bin/ssh/moduli.c
411
if ((r = mkstemp(tmp)) == -1) {
usr.bin/ssh/moduli.c
412
logit("mkstemp(%s): %s", tmp, strerror(errno));
usr.bin/ssh/moduli.c
417
unlink(tmp);
usr.bin/ssh/moduli.c
423
if (writeok && closeok && rename(tmp, cpfile) == 0) {
usr.bin/ssh/moduli.c
429
(void)unlink(tmp);
usr.bin/ssh/packet.c
1205
u_char tmp, padlen, pad = 0;
usr.bin/ssh/packet.c
1263
tmp = state->extra_pad;
usr.bin/ssh/packet.c
1267
if (state->extra_pad < tmp)
usr.bin/ssh/packet.c
1269
tmp = (len + padlen) % state->extra_pad;
usr.bin/ssh/packet.c
1271
if (tmp > state->extra_pad)
usr.bin/ssh/packet.c
1273
pad = state->extra_pad - tmp;
usr.bin/ssh/packet.c
1276
tmp = padlen;
usr.bin/ssh/packet.c
1279
if (padlen < tmp)
usr.bin/ssh/scp.c
1506
char *filename, *tmp = NULL;
usr.bin/ssh/scp.c
1567
tmp = xstrdup(g.gl_pathv[i]);
usr.bin/ssh/scp.c
1568
if ((filename = basename(tmp)) == NULL) {
usr.bin/ssh/scp.c
1569
error("basename %s: %s", tmp, strerror(errno));
usr.bin/ssh/scp.c
1595
free(tmp);
usr.bin/ssh/scp.c
1596
tmp = NULL;
usr.bin/ssh/scp.c
1601
free(tmp);
usr.bin/ssh/scp.c
1941
char *abs_src = NULL, *tmp = NULL;
usr.bin/ssh/scp.c
1986
tmp = xstrdup(g.gl_pathv[i]);
usr.bin/ssh/scp.c
1987
if ((filename = basename(tmp)) == NULL) {
usr.bin/ssh/scp.c
1988
error("basename %s: %s", tmp, strerror(errno));
usr.bin/ssh/scp.c
2010
free(tmp);
usr.bin/ssh/scp.c
2011
tmp = NULL;
usr.bin/ssh/scp.c
2018
free(tmp);
usr.bin/ssh/scp.c
708
char **tmp;
usr.bin/ssh/scp.c
710
if ((tmp = reallocarray(*ap, *np + 1, sizeof(*tmp))) == NULL)
usr.bin/ssh/scp.c
712
tmp[(*np)] = cp;
usr.bin/ssh/scp.c
714
*ap = tmp;
usr.bin/ssh/serverloop.c
507
char *tmp, *ifname = NULL;
usr.bin/ssh/serverloop.c
551
tmp = tun_fwd_ifnames;
usr.bin/ssh/serverloop.c
556
free(tmp);
usr.bin/ssh/session.c
1081
char uidstr[32], *chroot_path, *tmp;
usr.bin/ssh/session.c
1093
tmp = tilde_expand_filename(options.chroot_directory,
usr.bin/ssh/session.c
1097
chroot_path = percent_expand(tmp, "h", pw->pw_dir,
usr.bin/ssh/session.c
1100
free(tmp);
usr.bin/ssh/session.c
1385
Session *s, *tmp;
usr.bin/ssh/session.c
1392
tmp = xrecallocarray(sessions, sessions_nalloc,
usr.bin/ssh/session.c
1394
if (tmp == NULL) {
usr.bin/ssh/session.c
1399
sessions = tmp;
usr.bin/ssh/session.c
255
char *tmp, *cp, *host;
usr.bin/ssh/session.c
262
tmp = cp = xstrdup(auth_opts->permitopen[i]);
usr.bin/ssh/session.c
271
free(tmp);
usr.bin/ssh/session.c
277
tmp = cp = xstrdup(auth_opts->permitlisten[i]);
usr.bin/ssh/session.c
286
free(tmp);
usr.bin/ssh/sftp.c
1535
char *path1, *path2, *tmp;
usr.bin/ssh/sftp.c
1627
if ((tmp = sftp_realpath(conn, path1)) == NULL) {
usr.bin/ssh/sftp.c
1631
if (sftp_stat(conn, tmp, 0, &aa) != 0) {
usr.bin/ssh/sftp.c
1632
free(tmp);
usr.bin/ssh/sftp.c
1638
free(tmp);
usr.bin/ssh/sftp.c
1644
"a directory", tmp);
usr.bin/ssh/sftp.c
1645
free(tmp);
usr.bin/ssh/sftp.c
1650
*pwd = tmp;
usr.bin/ssh/sftp.c
1659
tmp = NULL;
usr.bin/ssh/sftp.c
1661
tmp = *pwd;
usr.bin/ssh/sftp.c
1664
err = do_globbed_ls(conn, path1, tmp, lflag);
usr.bin/ssh/sftp.c
1676
tmp = tilde_expand_filename(path1, getuid());
usr.bin/ssh/sftp.c
1678
path1 = tmp;
usr.bin/ssh/sftp.c
1815
char *tmp;
usr.bin/ssh/sftp.c
1834
tmp = llen > len ? list[y] + len : "";
usr.bin/ssh/sftp.c
1835
mprintf("%-*s", colspace, tmp);
usr.bin/ssh/sftp.c
1854
char *tmp;
usr.bin/ssh/sftp.c
1888
tmp = xstrdup(list[0]);
usr.bin/ssh/sftp.c
1889
tmp[matchlen] = '\0';
usr.bin/ssh/sftp.c
1890
return tmp;
usr.bin/ssh/sftp.c
1902
char *tmp, **list, argterm[3];
usr.bin/ssh/sftp.c
1935
tmp = complete_ambiguous(cmd, list, count);
usr.bin/ssh/sftp.c
1943
if (tmp != NULL) {
usr.bin/ssh/sftp.c
1944
tmplen = strlen(tmp);
usr.bin/ssh/sftp.c
1948
if (el_insertstr(el, tmp + cmdlen) == -1)
usr.bin/ssh/sftp.c
1962
free(tmp);
usr.bin/ssh/sftp.c
1999
char *tmp, *tmp2, ins[8];
usr.bin/ssh/sftp.c
2006
tmp = xstrdup("*");
usr.bin/ssh/sftp.c
2008
xasprintf(&tmp, "%s*", file);
usr.bin/ssh/sftp.c
2011
isabs = path_absolute(tmp);
usr.bin/ssh/sftp.c
2015
tmp = make_absolute_pwd_glob(tmp, remote_path);
usr.bin/ssh/sftp.c
2016
sftp_glob(conn, tmp, GLOB_DOOFFS|GLOB_MARK, NULL, &g);
usr.bin/ssh/sftp.c
2018
(void)glob(tmp, GLOB_DOOFFS|GLOB_MARK, NULL, &g);
usr.bin/ssh/sftp.c
2021
for (hadglob = tmplen = pwdlen = 0; tmp[tmplen] != 0; tmplen++) {
usr.bin/ssh/sftp.c
2023
if (tmp[tmplen] == '*' || tmp[tmplen] == '?') {
usr.bin/ssh/sftp.c
2024
if (tmp[tmplen] != '*' || tmp[tmplen + 1] != '\0')
usr.bin/ssh/sftp.c
2028
if (tmp[tmplen] == '\\' && tmp[tmplen + 1] != '\0')
usr.bin/ssh/sftp.c
2030
if (tmp[tmplen] == '/')
usr.bin/ssh/sftp.c
2033
free(tmp);
usr.bin/ssh/sftp.c
2034
tmp = NULL;
usr.bin/ssh/sftp.c
2047
tmp = path_strip(tmp2, isabs ? NULL : remote_path);
usr.bin/ssh/sftp.c
2050
if (tmp == NULL)
usr.bin/ssh/sftp.c
2053
tmplen = strlen(tmp);
usr.bin/ssh/sftp.c
2067
tmp2 = tmp + filelen - cesc;
usr.bin/ssh/sftp.c
2114
free(tmp);
usr.bin/ssh/sftp.c
2422
int r, in, out, ch, err, tmp, port = -1, noisy = 0;
usr.bin/ssh/sftp.c
2597
switch (parse_uri("sftp", *argv, &user, &host, &tmp, &file1)) {
usr.bin/ssh/sftp.c
2602
if (tmp != -1)
usr.bin/ssh/sftp.c
2603
port = tmp;
usr.bin/ssh/sftp.c
2644
if ((r = argv_split(sftp_direct, &tmp, &cpp, 1)) != 0)
usr.bin/ssh/sftp.c
2649
argv_free(cpp, tmp);
usr.bin/ssh/sftp.c
631
char *filename, *abs_src = NULL, *abs_dst = NULL, *tmp = NULL;
usr.bin/ssh/sftp.c
661
tmp = xstrdup(g.gl_pathv[i]);
usr.bin/ssh/sftp.c
662
if ((filename = basename(tmp)) == NULL) {
usr.bin/ssh/sftp.c
663
error("basename %s: %s", tmp, strerror(errno));
usr.bin/ssh/sftp.c
664
free(tmp);
usr.bin/ssh/sftp.c
684
free(tmp);
usr.bin/ssh/sftp.c
722
char *tmp = NULL, *filename = NULL;
usr.bin/ssh/sftp.c
760
tmp = xstrdup(g.gl_pathv[i]);
usr.bin/ssh/sftp.c
761
if ((filename = basename(tmp)) == NULL) {
usr.bin/ssh/sftp.c
762
error("basename %s: %s", tmp, strerror(errno));
usr.bin/ssh/sftp.c
763
free(tmp);
usr.bin/ssh/sftp.c
784
free(tmp);
usr.bin/ssh/sftp.c
848
char *tmp;
usr.bin/ssh/sftp.c
857
tmp = path_strip(path, strip_path);
usr.bin/ssh/sftp.c
858
m += strlen(tmp);
usr.bin/ssh/sftp.c
859
free(tmp);
usr.bin/ssh/sftp.c
879
char *tmp, *fname;
usr.bin/ssh/sftp.c
884
tmp = sftp_path_append(path, d[n]->filename);
usr.bin/ssh/sftp.c
885
fname = path_strip(tmp, strip_path);
usr.bin/ssh/sftp.c
886
free(tmp);
usr.bin/ssh/sk-usbhid.c
1129
struct sk_resident_key *srk = NULL, **tmp;
usr.bin/ssh/sk-usbhid.c
1260
if ((tmp = recallocarray(*rksp, *nrksp, (*nrksp) + 1,
usr.bin/ssh/sk-usbhid.c
1265
*rksp = tmp;
usr.bin/ssh/srclimit.c
217
struct penalty *penalty, *tmp;
usr.bin/ssh/srclimit.c
220
RB_FOREACH_SAFE(penalty, penalties_by_expiry, by_expiry, tmp) {
usr.bin/ssh/ssh-ecdsa-sk.c
234
char *tmp = NULL;
usr.bin/ssh/ssh-ecdsa-sk.c
299
fprintf(stderr, "%s: sig_r: %s\n", __func__, (tmp = BN_bn2hex(sig_r)));
usr.bin/ssh/ssh-ecdsa-sk.c
300
free(tmp);
usr.bin/ssh/ssh-ecdsa-sk.c
301
fprintf(stderr, "%s: sig_s: %s\n", __func__, (tmp = BN_bn2hex(sig_s)));
usr.bin/ssh/ssh-ecdsa-sk.c
302
free(tmp);
usr.bin/ssh/ssh-keygen.c
1237
char *cp, tmp[PATH_MAX], old[PATH_MAX];
usr.bin/ssh/ssh-keygen.c
1266
if (strlcpy(tmp, identity_file, sizeof(tmp)) >= sizeof(tmp) ||
usr.bin/ssh/ssh-keygen.c
1267
strlcat(tmp, ".XXXXXXXXXX", sizeof(tmp)) >= sizeof(tmp) ||
usr.bin/ssh/ssh-keygen.c
1272
if ((fd = mkstemp(tmp)) == -1)
usr.bin/ssh/ssh-keygen.c
1276
unlink(tmp);
usr.bin/ssh/ssh-keygen.c
1289
unlink(tmp);
usr.bin/ssh/ssh-keygen.c
1301
unlink(tmp);
usr.bin/ssh/ssh-keygen.c
1307
unlink(tmp);
usr.bin/ssh/ssh-keygen.c
1316
if (rename(tmp, identity_file) == -1) {
usr.bin/ssh/ssh-keygen.c
1317
error("rename\"%s\" to \"%s\": %s", tmp, identity_file,
usr.bin/ssh/ssh-keygen.c
1319
unlink(tmp);
usr.bin/ssh/ssh-keygen.c
1699
char valid[64], *otmp, *tmp, *cp, *out, *comment;
usr.bin/ssh/ssh-keygen.c
1708
tmp = tilde_expand_filename(ca_key_path, pw->pw_uid);
usr.bin/ssh/ssh-keygen.c
1711
if ((ca = load_pkcs11_key(tmp)) == NULL)
usr.bin/ssh/ssh-keygen.c
1719
if ((r = sshkey_load_public(tmp, &ca, NULL)) != 0)
usr.bin/ssh/ssh-keygen.c
1720
fatal_r(r, "Cannot load CA public key %s", tmp);
usr.bin/ssh/ssh-keygen.c
1736
fatal("CA key %s not found in agent", tmp);
usr.bin/ssh/ssh-keygen.c
1740
ca = load_identity(tmp, NULL);
usr.bin/ssh/ssh-keygen.c
1748
free(tmp);
usr.bin/ssh/ssh-keygen.c
1766
otmp = tmp = xstrdup(cert_principals);
usr.bin/ssh/ssh-keygen.c
1768
for (; (cp = strsep(&tmp, ",")) != NULL; n++) {
usr.bin/ssh/ssh-keygen.c
1778
tmp = tilde_expand_filename(argv[i], pw->pw_uid);
usr.bin/ssh/ssh-keygen.c
1779
if ((r = sshkey_load_public(tmp, &public, &comment)) != 0)
usr.bin/ssh/ssh-keygen.c
1780
fatal_r(r, "load pubkey \"%s\"", tmp);
usr.bin/ssh/ssh-keygen.c
1783
tmp, sshkey_type(public));
usr.bin/ssh/ssh-keygen.c
1787
fatal_r(r, "Could not upgrade key %s to certificate", tmp);
usr.bin/ssh/ssh-keygen.c
1806
fatal_r(r, "Couldn't certify %s via agent", tmp);
usr.bin/ssh/ssh-keygen.c
1818
fatal_r(r, "Couldn't certify key %s", tmp);
usr.bin/ssh/ssh-keygen.c
1821
if ((cp = strrchr(tmp, '.')) != NULL && strcmp(cp, ".pub") == 0)
usr.bin/ssh/ssh-keygen.c
1823
xasprintf(&out, "%s-cert.pub", tmp);
usr.bin/ssh/ssh-keygen.c
1824
free(tmp);
usr.bin/ssh/ssh-keygen.c
2175
char *tmp;
usr.bin/ssh/ssh-keygen.c
2189
tmp = xmalloc(tlen + 4 + 1);
usr.bin/ssh/ssh-keygen.c
2190
strlcpy(tmp, cp, tlen + 1);
usr.bin/ssh/ssh-keygen.c
2192
tmp[tlen++] = '=';
usr.bin/ssh/ssh-keygen.c
2193
tmp[tlen] = '\0';
usr.bin/ssh/ssh-keygen.c
2197
if ((r = sshbuf_b64tod(b, tmp)) != 0)
usr.bin/ssh/ssh-keygen.c
2199
free(tmp);
usr.bin/ssh/ssh-keygen.c
2372
char *tmp;
usr.bin/ssh/ssh-keygen.c
2388
tmp = tilde_expand_filename(ca_key_path, pw->pw_uid);
usr.bin/ssh/ssh-keygen.c
2389
if ((r = sshkey_load_public(tmp, &ca, NULL)) != 0)
usr.bin/ssh/ssh-keygen.c
2390
fatal_r(r, "Cannot load CA public key %s", tmp);
usr.bin/ssh/ssh-keygen.c
2391
free(tmp);
usr.bin/ssh/ssh-keygen.c
2828
char *principals = NULL, *cp, *tmp;
usr.bin/ssh/ssh-keygen.c
2856
tmp = principals;
usr.bin/ssh/ssh-keygen.c
2857
while ((cp = strsep(&tmp, ",")) != NULL && *cp != '\0')
usr.bin/ssh/ssh-sk-client.c
411
struct sshsk_resident_key *srk = NULL, **srks = NULL, **tmp;
usr.bin/ssh/ssh-sk-client.c
459
if ((tmp = recallocarray(srks, nsrks, nsrks + 1,
usr.bin/ssh/ssh-sk-client.c
468
srks = tmp;
usr.bin/ssh/ssh-sk.c
791
struct sshsk_resident_key *srk = NULL, **srks = NULL, **tmp;
usr.bin/ssh/ssh-sk.c
848
if ((tmp = recallocarray(srks, nsrks, nsrks + 1,
usr.bin/ssh/ssh-sk.c
849
sizeof(*tmp))) == NULL) {
usr.bin/ssh/ssh-sk.c
854
srks = tmp;
usr.bin/ssh/sshbuf-misc.c
166
struct sshbuf *tmp;
usr.bin/ssh/sshbuf-misc.c
169
if ((tmp = sshbuf_new()) == NULL)
usr.bin/ssh/sshbuf-misc.c
171
if (sshbuf_dtob64(buf, tmp, wrap) != 0) {
usr.bin/ssh/sshbuf-misc.c
172
sshbuf_free(tmp);
usr.bin/ssh/sshbuf-misc.c
175
ret = sshbuf_dup_string(tmp);
usr.bin/ssh/sshbuf-misc.c
176
sshbuf_free(tmp);
usr.bin/ssh/sshconnect.c
75
char *tmp, *ret, strport[NI_MAXSERV];
usr.bin/ssh/sshconnect.c
80
xasprintf(&tmp, "exec %s", proxy_command);
usr.bin/ssh/sshconnect.c
81
ret = percent_expand(tmp,
usr.bin/ssh/sshconnect.c
834
char *key_fp = NULL, *keytext = NULL, *tmp;
usr.bin/ssh/sshconnect.c
867
tmp = percent_dollar_expand(av[i],
usr.bin/ssh/sshconnect.c
875
if (tmp == NULL)
usr.bin/ssh/sshconnect.c
878
av[i] = tmp;
usr.bin/ssh/sshconnect.c
88
free(tmp);
usr.bin/ssh/sshconnect2.c
1154
char *allowed, *oallowed, *cp, *tmp, *alg = NULL;
usr.bin/ssh/sshconnect2.c
1188
tmp = match_list(sshkey_sigalg_by_name(cp),
usr.bin/ssh/sshconnect2.c
1190
if (tmp != NULL)
usr.bin/ssh/sshconnect2.c
1192
free(tmp);
usr.bin/ssh/sshconnect2.c
1671
struct identity *id, *id2, *tmp;
usr.bin/ssh/sshconnect2.c
1770
TAILQ_FOREACH_SAFE(id, &files, next, tmp) {
usr.bin/ssh/sshd-session.c
233
struct sshkey *tmp;
usr.bin/ssh/sshd-session.c
240
sensitive_data.host_keys[i], &tmp)) != 0)
usr.bin/ssh/sshd-session.c
244
sensitive_data.host_keys[i] = tmp;
usr.bin/ssh/sshkey.c
1596
struct sshkey *kswap = NULL, tmp;
usr.bin/ssh/sshkey.c
1667
tmp = *kswap;
usr.bin/ssh/sshkey.c
1669
*k = tmp;
usr.bin/ssh/sshkey.c
1689
explicit_bzero(&tmp, sizeof(tmp));
usr.bin/ssh/sshkey.c
1729
struct sshkey *kswap = NULL, tmp;
usr.bin/ssh/sshkey.c
1795
tmp = *kswap;
usr.bin/ssh/sshkey.c
1797
*k = tmp;
usr.bin/ssh/sshkey.c
1805
explicit_bzero(&tmp, sizeof(tmp));
usr.bin/ssh/sshkey.c
2696
BIGNUM *order = NULL, *tmp = NULL;
usr.bin/ssh/sshkey.c
2699
if ((order = BN_new()) == NULL || (tmp = BN_new()) == NULL) {
usr.bin/ssh/sshkey.c
2714
if (!BN_sub(tmp, order, BN_value_one())) {
usr.bin/ssh/sshkey.c
2718
if (BN_cmp(EC_KEY_get0_private_key(key), tmp) >= 0)
usr.bin/ssh/sshkey.c
2723
BN_clear_free(tmp);
usr.bin/ssh/sshkey.c
859
struct sshbuf *tmp;
usr.bin/ssh/sshkey.c
862
if ((tmp = sshbuf_new()) == NULL)
usr.bin/ssh/sshkey.c
864
r = to_blob_buf(key, tmp, force_plain, opts);
usr.bin/ssh/sshkey.c
866
r = sshbuf_put_stringb(b, tmp);
usr.bin/ssh/sshkey.c
867
sshbuf_free(tmp);
usr.bin/ssh/sshsig.c
1081
char *found, *line = NULL, **principals = NULL, **tmp;
usr.bin/ssh/sshsig.c
1111
if ((tmp = recallocarray(principals, nprincipals,
usr.bin/ssh/sshsig.c
1117
principals = tmp;
usr.bin/ssh/sshsig.c
738
char *opts = NULL, *tmp, *cp, *principals = NULL;
usr.bin/ssh/sshsig.c
757
if ((tmp = strdelimw(&cp)) == NULL || cp == NULL) {
usr.bin/ssh/sshsig.c
762
if ((principals = strdup(tmp)) == NULL) {
usr.bin/stat/stat.c
493
char lfmt[24], tmp[20];
usr.bin/stat/stat.c
816
(void)snprintf(tmp, sizeof(tmp), "%d", size);
usr.bin/stat/stat.c
817
(void)strlcat(lfmt, tmp, sizeof(lfmt));
usr.bin/stat/stat.c
841
(void)snprintf(tmp, sizeof(tmp), "%d", size);
usr.bin/stat/stat.c
842
(void)strlcat(lfmt, tmp, sizeof(lfmt));
usr.bin/stat/stat.c
856
(void)snprintf(tmp, sizeof(tmp), "%dld", prec > 9 ? 9 : prec);
usr.bin/stat/stat.c
857
(void)strlcat(lfmt, tmp, sizeof(lfmt));
usr.bin/stat/stat.c
882
(void)snprintf(tmp, sizeof(tmp), "%d", size);
usr.bin/stat/stat.c
883
(void)strlcat(lfmt, tmp, sizeof(lfmt));
usr.bin/stat/stat.c
886
(void)snprintf(tmp, sizeof(tmp), ".%d", prec);
usr.bin/stat/stat.c
887
(void)strlcat(lfmt, tmp, sizeof(lfmt));
usr.bin/systat/cache.c
174
struct sc_queue *tmp;
usr.bin/systat/cache.c
185
tmp = scq_act;
usr.bin/systat/cache.c
187
scq_exp = tmp;
usr.bin/systat/pftop.c
700
u_int32_t tmp;
usr.bin/systat/pftop.c
707
tmp = ntohl(m->addr32[j]);
usr.bin/systat/pftop.c
708
for (i = 31; tmp & (1 << i); --i)
usr.bin/tcpbench/tcpbench.c
1110
char *tmp;
usr.bin/tcpbench/tcpbench.c
1162
if ((tmp = strdup(optarg)) == NULL)
usr.bin/tcpbench/tcpbench.c
1164
ptb->kvars = check_prepare_kvars(tmp);
usr.bin/tcpbench/tcpbench.c
1165
free(tmp);
usr.bin/tcpbench/tcpbench.c
680
char tmp[NI_MAXHOST + 2 + NI_MAXSERV];
usr.bin/tcpbench/tcpbench.c
713
tmp, sizeof(tmp));
usr.bin/tcpbench/tcpbench.c
743
tmp, sc->fd);
usr.bin/tcpbench/tcpbench.c
757
char tmp[NI_MAXHOST + 2 + NI_MAXSERV];
usr.bin/tcpbench/tcpbench.c
759
saddr_ntop(ai->ai_addr, ai->ai_addrlen, tmp, sizeof(tmp));
usr.bin/tcpbench/tcpbench.c
761
fprintf(stderr, "Try to bind to %s\n", tmp);
usr.bin/tcpbench/tcpbench.c
882
char tmp[NI_MAXHOST + 2 + NI_MAXSERV];
usr.bin/tcpbench/tcpbench.c
884
saddr_ntop(ai->ai_addr, ai->ai_addrlen, tmp,
usr.bin/tcpbench/tcpbench.c
885
sizeof(tmp));
usr.bin/tcpbench/tcpbench.c
887
fprintf(stderr, "Trying %s\n", tmp);
usr.bin/tcpbench/tcpbench.c
903
tmp, sizeof(tmp));
usr.bin/tcpbench/tcpbench.c
906
"Try to bind to %s\n", tmp);
usr.bin/telnet/telnet.c
2037
unsigned char tmp[16];
usr.bin/telnet/telnet.c
2044
cp = tmp;
usr.bin/telnet/telnet.c
2052
if (NETROOM() >= cp - tmp) {
usr.bin/telnet/telnet.c
2053
ring_supply_data(&netoring, tmp, cp-tmp);
usr.bin/telnet/telnet.c
2054
printsub('>', tmp+2, cp - tmp - 2);
usr.bin/telnet/telnet.c
2138
unsigned char tmp[16];
usr.bin/telnet/telnet.c
2151
cp = tmp;
usr.bin/telnet/telnet.c
2160
if (NETROOM() >= cp - tmp) {
usr.bin/telnet/telnet.c
2161
ring_supply_data(&netoring, tmp, cp-tmp);
usr.bin/telnet/telnet.c
2162
printsub('>', tmp+2, cp - tmp - 2);
usr.bin/tic/dump_entry.c
1230
char *tmp = _nc_tic_expand(boxchars,
usr.bin/tic/dump_entry.c
1234
while (*tmp != '\0') {
usr.bin/tic/dump_entry.c
1236
size_t next = strlen(tmp);
usr.bin/tic/dump_entry.c
1246
save = tmp[last];
usr.bin/tic/dump_entry.c
1247
tmp[last] = '\0';
usr.bin/tic/dump_entry.c
1249
_nc_STRCAT(buffer, tmp, sizeof(buffer));
usr.bin/tic/dump_entry.c
1257
tmp[last] = save;
usr.bin/tic/dump_entry.c
1258
while ((tmp[next] = tmp[last + next]) != '\0') {
usr.bin/tmux/cmd-capture-pane.c
116
u_int i, sx, top, bottom, tmp;
usr.bin/tmux/cmd-capture-pane.c
181
tmp = bottom;
usr.bin/tmux/cmd-capture-pane.c
183
top = tmp;
usr.bin/tmux/cmd-capture-pane.c
79
char *buf, *line, tmp[5];
usr.bin/tmux/cmd-capture-pane.c
94
tmp[0] = line[i];
usr.bin/tmux/cmd-capture-pane.c
95
tmp[1] = '\0';
usr.bin/tmux/cmd-capture-pane.c
97
xsnprintf(tmp, sizeof tmp, "\\%03hho", line[i]);
usr.bin/tmux/cmd-capture-pane.c
98
buf = cmd_capture_pane_append(buf, len, tmp,
usr.bin/tmux/cmd-capture-pane.c
99
strlen(tmp));
usr.bin/tmux/cmd-command-prompt.c
106
tmp = args_make_commands_get_command(cdata->state);
usr.bin/tmux/cmd-command-prompt.c
107
xasprintf(&prompts, "(%s)", tmp);
usr.bin/tmux/cmd-command-prompt.c
108
free(tmp);
usr.bin/tmux/cmd-command-prompt.c
130
tmp = xstrdup(prompt);
usr.bin/tmux/cmd-command-prompt.c
132
xasprintf(&tmp, "%s ", prompt);
usr.bin/tmux/cmd-command-prompt.c
133
cdata->prompts[cdata->count].prompt = tmp;
usr.bin/tmux/cmd-command-prompt.c
88
char *tmp, *prompts, *prompt, *next_prompt;
usr.bin/tmux/cmd-find.c
930
char *colon, *period, *copy = NULL, tmp[256];
usr.bin/tmux/cmd-find.c
947
*tmp = '\0';
usr.bin/tmux/cmd-find.c
949
strlcat(tmp, "PREFER_UNATTACHED,", sizeof tmp);
usr.bin/tmux/cmd-find.c
951
strlcat(tmp, "QUIET,", sizeof tmp);
usr.bin/tmux/cmd-find.c
953
strlcat(tmp, "WINDOW_INDEX,", sizeof tmp);
usr.bin/tmux/cmd-find.c
955
strlcat(tmp, "DEFAULT_MARKED,", sizeof tmp);
usr.bin/tmux/cmd-find.c
957
strlcat(tmp, "EXACT_SESSION,", sizeof tmp);
usr.bin/tmux/cmd-find.c
959
strlcat(tmp, "EXACT_WINDOW,", sizeof tmp);
usr.bin/tmux/cmd-find.c
961
strlcat(tmp, "CANFAIL,", sizeof tmp);
usr.bin/tmux/cmd-find.c
962
if (*tmp != '\0')
usr.bin/tmux/cmd-find.c
963
tmp[strlen(tmp) - 1] = '\0';
usr.bin/tmux/cmd-find.c
965
strlcat(tmp, "NONE", sizeof tmp);
usr.bin/tmux/cmd-find.c
967
target == NULL ? "none" : target, s, item, tmp);
usr.bin/tmux/cmd-new-session.c
102
tmp = args_get(args, 's');
usr.bin/tmux/cmd-new-session.c
103
if (tmp != NULL) {
usr.bin/tmux/cmd-new-session.c
104
name = format_single(item, tmp, c, NULL, NULL, NULL);
usr.bin/tmux/cmd-new-session.c
167
if ((tmp = args_get(args, 'c')) != NULL)
usr.bin/tmux/cmd-new-session.c
168
cwd = format_single(item, tmp, c, NULL, NULL, NULL);
usr.bin/tmux/cmd-new-session.c
207
tmp = args_get(args, 'x');
usr.bin/tmux/cmd-new-session.c
208
if (strcmp(tmp, "-") == 0) {
usr.bin/tmux/cmd-new-session.c
214
dsx = strtonum(tmp, 1, USHRT_MAX, &errstr);
usr.bin/tmux/cmd-new-session.c
223
tmp = args_get(args, 'y');
usr.bin/tmux/cmd-new-session.c
224
if (strcmp(tmp, "-") == 0) {
usr.bin/tmux/cmd-new-session.c
230
dsy = strtonum(tmp, 1, USHRT_MAX, &errstr);
usr.bin/tmux/cmd-new-session.c
246
tmp = options_get_string(global_s_options, "default-size");
usr.bin/tmux/cmd-new-session.c
247
if (sscanf(tmp, "%ux%u", &sx, &sy) != 2) {
usr.bin/tmux/cmd-new-session.c
79
const char *errstr, *template, *group, *tmp;
usr.bin/tmux/cmd-parse.y
1434
u_int size, i, tmp;
usr.bin/tmux/cmd-parse.y
1515
if ((size == 4 && sscanf(s, "%4x", &tmp) != 1) ||
usr.bin/tmux/cmd-parse.y
1516
(size == 8 && sscanf(s, "%8x", &tmp) != 1)) {
usr.bin/tmux/cmd-parse.y
1520
mlen = wctomb(m, tmp);
usr.bin/tmux/cmd-queue.c
364
char *name, tmp[32], flag, *arguments;
usr.bin/tmux/cmd-queue.c
403
xsnprintf(tmp, sizeof tmp, "hook_argument_%d", i);
usr.bin/tmux/cmd-queue.c
404
cmdq_add_format(new_state, tmp, "%s", args_string(args, i));
usr.bin/tmux/cmd-queue.c
410
xsnprintf(tmp, sizeof tmp, "hook_flag_%c", flag);
usr.bin/tmux/cmd-queue.c
411
cmdq_add_format(new_state, tmp, "1");
usr.bin/tmux/cmd-queue.c
413
xsnprintf(tmp, sizeof tmp, "hook_flag_%c", flag);
usr.bin/tmux/cmd-queue.c
414
cmdq_add_format(new_state, tmp, "%s", value);
usr.bin/tmux/cmd-queue.c
420
xsnprintf(tmp, sizeof tmp, "hook_flag_%c_%d", flag, i);
usr.bin/tmux/cmd-queue.c
421
cmdq_add_format(new_state, tmp, "%s", av->string);
usr.bin/tmux/cmd-queue.c
567
char *tmp;
usr.bin/tmux/cmd-queue.c
572
tmp = cmd_print(item->cmd);
usr.bin/tmux/cmd-queue.c
585
key, tmp);
usr.bin/tmux/cmd-queue.c
588
tmp);
usr.bin/tmux/cmd-queue.c
592
server_add_message("command: %s", tmp);
usr.bin/tmux/cmd-queue.c
593
free(tmp);
usr.bin/tmux/cmd-queue.c
609
char *tmp;
usr.bin/tmux/cmd-queue.c
614
tmp = cmd_print(cmd);
usr.bin/tmux/cmd-queue.c
615
log_debug("%s %s: (%u) %s", __func__, name, item->group, tmp);
usr.bin/tmux/cmd-queue.c
616
free(tmp);
usr.bin/tmux/cmd-queue.c
869
char *msg, *tmp;
usr.bin/tmux/cmd-queue.c
885
tmp = msg;
usr.bin/tmux/cmd-queue.c
886
msg = utf8_sanitize(tmp);
usr.bin/tmux/cmd-queue.c
887
free(tmp);
usr.bin/tmux/cmd-rename-session.c
52
char *newname, *tmp;
usr.bin/tmux/cmd-rename-session.c
54
tmp = format_single_from_target(item, args_string(args, 0));
usr.bin/tmux/cmd-rename-session.c
55
newname = session_check_name(tmp);
usr.bin/tmux/cmd-rename-session.c
57
cmdq_error(item, "invalid session: %s", tmp);
usr.bin/tmux/cmd-rename-session.c
58
free(tmp);
usr.bin/tmux/cmd-rename-session.c
61
free(tmp);
usr.bin/tmux/cmd-show-options.c
155
char *value, *tmp = NULL, *escaped;
usr.bin/tmux/cmd-show-options.c
158
xasprintf(&tmp, "%s[%d]", name, idx);
usr.bin/tmux/cmd-show-options.c
159
name = tmp;
usr.bin/tmux/cmd-show-options.c
196
free(tmp);
usr.bin/tmux/format-draw.c
728
char *tmp;
usr.bin/tmux/format-draw.c
825
tmp = xstrndup(cp + 2, end - (cp + 2));
usr.bin/tmux/format-draw.c
827
if (style_parse(&sy, ¤t_default, tmp) != 0) {
usr.bin/tmux/format-draw.c
828
log_debug("%s: invalid style '%s'", __func__, tmp);
usr.bin/tmux/format-draw.c
829
free(tmp);
usr.bin/tmux/format-draw.c
833
log_debug("%s: style '%s' -> '%s'", __func__, tmp,
usr.bin/tmux/format-draw.c
835
free(tmp);
usr.bin/tmux/format.c
591
char alerts[1024], tmp[16];
usr.bin/tmux/format.c
600
xsnprintf(tmp, sizeof tmp, "%u", wl->idx);
usr.bin/tmux/format.c
604
strlcat(alerts, tmp, sizeof alerts);
usr.bin/tmux/format.c
621
char result[1024], tmp[16];
usr.bin/tmux/format.c
628
xsnprintf(tmp, sizeof tmp, "%u", wl->idx);
usr.bin/tmux/format.c
632
strlcat(result, tmp, sizeof result);
usr.bin/tmux/grid.c
1024
xsnprintf(tmp, sizeof tmp, "%d", s[i]);
usr.bin/tmux/grid.c
1026
xsnprintf(tmp, sizeof tmp, "%d:%d", s[i] / 10,
usr.bin/tmux/grid.c
1029
strlcat(buf, tmp, len);
usr.bin/tmux/grid.c
911
char tmp[64];
usr.bin/tmux/grid.c
929
xsnprintf(tmp, sizeof tmp, "%d;", newc[i]);
usr.bin/tmux/grid.c
931
xsnprintf(tmp, sizeof tmp, "%d", newc[i]);
usr.bin/tmux/grid.c
932
strlcat(buf, tmp, len);
usr.bin/tmux/grid.c
941
char *tmp;
usr.bin/tmux/grid.c
951
xasprintf(&tmp, "id=%s;", id);
usr.bin/tmux/grid.c
952
strlcat(buf, tmp, len);
usr.bin/tmux/grid.c
953
free(tmp);
usr.bin/tmux/grid.c
976
char tmp[64];
usr.bin/tmux/input-keys.c
429
char tmp[64], modifier;
usr.bin/tmux/input-keys.c
469
xsnprintf(tmp, sizeof tmp, "\033[27;%c;%llu~", modifier, key);
usr.bin/tmux/input-keys.c
471
xsnprintf(tmp, sizeof tmp, "\033[%llu;%cu", key, modifier);
usr.bin/tmux/input-keys.c
473
input_key_write(__func__, bev, tmp, strlen(tmp));
usr.bin/tmux/key-string.c
331
char tmp[8];
usr.bin/tmux/key-string.c
422
snprintf(tmp, sizeof tmp, "User%u", (u_int)(key - KEYC_USER));
usr.bin/tmux/key-string.c
423
strlcat(out, tmp, sizeof out);
usr.bin/tmux/key-string.c
454
tmp[0] = key;
usr.bin/tmux/key-string.c
455
tmp[1] = '\0';
usr.bin/tmux/key-string.c
457
xsnprintf(tmp, sizeof tmp, "C-?");
usr.bin/tmux/key-string.c
459
xsnprintf(tmp, sizeof tmp, "\\%llo", key);
usr.bin/tmux/key-string.c
461
strlcat(out, tmp, sizeof out);
usr.bin/tmux/layout-custom.c
78
char tmp[64];
usr.bin/tmux/layout-custom.c
86
tmplen = xsnprintf(tmp, sizeof tmp, "%ux%u,%u,%u,%u",
usr.bin/tmux/layout-custom.c
89
tmplen = xsnprintf(tmp, sizeof tmp, "%ux%u,%u,%u",
usr.bin/tmux/layout-custom.c
92
if (tmplen > (sizeof tmp) - 1)
usr.bin/tmux/layout-custom.c
94
if (strlcat(buf, tmp, len) >= len)
usr.bin/tmux/log.c
143
char tmp[256];
usr.bin/tmux/log.c
146
if (snprintf(tmp, sizeof tmp, "fatal: %s: ", strerror(errno)) < 0)
usr.bin/tmux/log.c
150
log_vwrite(msg, ap, tmp);
usr.bin/tmux/options.c
184
struct options_entry *o, *tmp;
usr.bin/tmux/options.c
186
RB_FOREACH_SAFE(o, options_tree, &oo->tree, tmp)
usr.bin/tmux/screen-redraw.c
823
const struct grid_cell *tmp;
usr.bin/tmux/screen-redraw.c
850
tmp = screen_redraw_draw_borders_style(ctx, x, y, wp);
usr.bin/tmux/screen-redraw.c
851
if (tmp == NULL)
usr.bin/tmux/screen-redraw.c
853
memcpy(&gc, tmp, sizeof gc);
usr.bin/tmux/screen-write.c
1599
struct screen_write_citem *ci, *ci2, *tmp, *before = NULL;
usr.bin/tmux/screen-write.c
1605
TAILQ_FOREACH_SAFE(ci, &cl->items, entry, tmp) {
usr.bin/tmux/screen-write.c
1728
struct screen_write_citem *ci, *tmp;
usr.bin/tmux/screen-write.c
1736
TAILQ_FOREACH_SAFE(ci, &cl->items, entry, tmp) {
usr.bin/tmux/screen-write.c
1768
TAILQ_FOREACH_SAFE(ci, &cl->items, entry, tmp) {
usr.bin/tmux/screen-write.c
399
char *tmp;
usr.bin/tmux/screen-write.c
407
xvasprintf(&tmp, fmt, ap);
usr.bin/tmux/screen-write.c
410
text = utf8_fromcstr(tmp);
usr.bin/tmux/screen-write.c
411
free(tmp);
usr.bin/tmux/screen.c
713
static char tmp[1024];
usr.bin/tmux/screen.c
720
*tmp = '\0';
usr.bin/tmux/screen.c
722
strlcat(tmp, "CURSOR,", sizeof tmp);
usr.bin/tmux/screen.c
724
strlcat(tmp, "INSERT,", sizeof tmp);
usr.bin/tmux/screen.c
726
strlcat(tmp, "KCURSOR,", sizeof tmp);
usr.bin/tmux/screen.c
728
strlcat(tmp, "KKEYPAD,", sizeof tmp);
usr.bin/tmux/screen.c
730
strlcat(tmp, "WRAP,", sizeof tmp);
usr.bin/tmux/screen.c
732
strlcat(tmp, "MOUSE_STANDARD,", sizeof tmp);
usr.bin/tmux/screen.c
734
strlcat(tmp, "MOUSE_BUTTON,", sizeof tmp);
usr.bin/tmux/screen.c
736
strlcat(tmp, "CURSOR_BLINKING,", sizeof tmp);
usr.bin/tmux/screen.c
738
strlcat(tmp, "CURSOR_VERY_VISIBLE,", sizeof tmp);
usr.bin/tmux/screen.c
740
strlcat(tmp, "MOUSE_UTF8,", sizeof tmp);
usr.bin/tmux/screen.c
742
strlcat(tmp, "MOUSE_SGR,", sizeof tmp);
usr.bin/tmux/screen.c
744
strlcat(tmp, "BRACKETPASTE,", sizeof tmp);
usr.bin/tmux/screen.c
746
strlcat(tmp, "FOCUSON,", sizeof tmp);
usr.bin/tmux/screen.c
748
strlcat(tmp, "MOUSE_ALL,", sizeof tmp);
usr.bin/tmux/screen.c
750
strlcat(tmp, "ORIGIN,", sizeof tmp);
usr.bin/tmux/screen.c
752
strlcat(tmp, "CRLF,", sizeof tmp);
usr.bin/tmux/screen.c
754
strlcat(tmp, "KEYS_EXTENDED,", sizeof tmp);
usr.bin/tmux/screen.c
756
strlcat(tmp, "KEYS_EXTENDED_2,", sizeof tmp);
usr.bin/tmux/screen.c
758
strlcat(tmp, "THEME_UPDATES,", sizeof tmp);
usr.bin/tmux/screen.c
759
tmp[strlen(tmp) - 1] = '\0';
usr.bin/tmux/screen.c
760
return (tmp);
usr.bin/tmux/server-client.c
2597
char tmp[32];
usr.bin/tmux/server-client.c
2615
xsnprintf(tmp, sizeof tmp, "pause-after=%u,",
usr.bin/tmux/server-client.c
2617
strlcat(s, tmp, sizeof s);
usr.bin/tmux/sort.c
33
void *tmp, **ll;
usr.bin/tmux/sort.c
42
tmp = ll[i];
usr.bin/tmux/sort.c
44
ll[len - 1 - i] = tmp;
usr.bin/tmux/spawn.c
217
const char *cmd, *tmp, *home = find_home();
usr.bin/tmux/spawn.c
335
tmp = options_get_string(s->options, "default-shell");
usr.bin/tmux/spawn.c
336
if (!checkshell(tmp))
usr.bin/tmux/spawn.c
337
tmp = _PATH_BSHELL;
usr.bin/tmux/spawn.c
339
new_wp->shell = xstrdup(tmp);
usr.bin/tmux/spawn.c
455
tmp = new_wp->argv[0];
usr.bin/tmux/spawn.c
460
execl(new_wp->shell, argv0, "-c", tmp, (char *)NULL);
usr.bin/tmux/spawn.c
60
char tmp[128];
usr.bin/tmux/spawn.c
65
xsnprintf(tmp, sizeof tmp, "wl=%d wp0=%%%u", wl->idx, wp0->id);
usr.bin/tmux/spawn.c
67
xsnprintf(tmp, sizeof tmp, "wl=%d wp0=none", wl->idx);
usr.bin/tmux/spawn.c
69
xsnprintf(tmp, sizeof tmp, "wl=none wp0=%%%u", wp0->id);
usr.bin/tmux/spawn.c
71
xsnprintf(tmp, sizeof tmp, "wl=none wp0=none");
usr.bin/tmux/spawn.c
72
log_debug("%s: s=$%u %s idx=%d", from, s->id, tmp, sc->idx);
usr.bin/tmux/status.c
111
char *history_file, *line, *tmp;
usr.bin/tmux/status.c
135
tmp = xmalloc(length + 1);
usr.bin/tmux/status.c
136
memcpy(tmp, line, length);
usr.bin/tmux/status.c
137
tmp[length] = '\0';
usr.bin/tmux/status.c
1375
struct utf8_data tmp;
usr.bin/tmux/status.c
138
status_prompt_add_typed_history(tmp);
usr.bin/tmux/status.c
139
free(tmp);
usr.bin/tmux/status.c
1592
utf8_copy(&tmp, &c->prompt_buffer[idx - 2]);
usr.bin/tmux/status.c
1595
utf8_copy(&c->prompt_buffer[idx - 1], &tmp);
usr.bin/tmux/status.c
1649
utf8_set(&tmp, key);
usr.bin/tmux/status.c
1651
tmp.width = 2;
usr.bin/tmux/status.c
1653
utf8_to_data(key, &tmp);
usr.bin/tmux/status.c
1661
utf8_copy(&c->prompt_buffer[c->prompt_index], &tmp);
usr.bin/tmux/status.c
1669
utf8_copy(&c->prompt_buffer[c->prompt_index], &tmp);
usr.bin/tmux/status.c
1790
char **list = NULL, *tmp;
usr.bin/tmux/status.c
1822
xasprintf(&tmp, "%.*s", (int)valuelen, value);
usr.bin/tmux/status.c
1823
status_prompt_add_list(&list, size, tmp);
usr.bin/tmux/status.c
1824
free(tmp);
usr.bin/tmux/status.c
1965
char **list = NULL, *tmp;
usr.bin/tmux/status.c
1984
xasprintf(&tmp, "%d", wl->idx);
usr.bin/tmux/status.c
1985
if (strncmp(tmp, word, strlen(word)) != 0) {
usr.bin/tmux/status.c
1986
free(tmp);
usr.bin/tmux/status.c
1989
free(tmp);
usr.bin/tmux/status.c
1994
xasprintf(&tmp, "%d (%s)", wl->idx, wl->window->name);
usr.bin/tmux/status.c
1997
xasprintf(&tmp, "%s:%d (%s)", s->name, wl->idx,
usr.bin/tmux/status.c
2001
item.name = tmp;
usr.bin/tmux/status.c
2005
free(tmp);
usr.bin/tmux/status.c
2018
xasprintf(&tmp, "-%c%s", flag, list[0]);
usr.bin/tmux/status.c
2021
tmp = list[0];
usr.bin/tmux/status.c
2024
return (tmp);
usr.bin/tmux/status.c
2072
char *out, *tmp, n[11];
usr.bin/tmux/status.c
2091
xasprintf(&tmp, "-%c%s", flag, out);
usr.bin/tmux/status.c
2093
out = tmp;
usr.bin/tmux/status.c
688
char *tmp;
usr.bin/tmux/status.c
708
tmp = xstrdup(input);
usr.bin/tmux/status.c
710
tmp = format_expand_time(ft, input);
usr.bin/tmux/status.c
712
c->prompt_last = xstrdup(tmp);
usr.bin/tmux/status.c
716
c->prompt_buffer = utf8_fromcstr(tmp);
usr.bin/tmux/status.c
719
free(tmp);
usr.bin/tmux/status.c
777
char *tmp;
usr.bin/tmux/status.c
783
tmp = format_expand_time(c->prompt_formats, input);
usr.bin/tmux/status.c
784
c->prompt_buffer = utf8_fromcstr(tmp);
usr.bin/tmux/status.c
786
free(tmp);
usr.bin/tmux/status.c
855
char *expanded, *prompt, *tmp;
usr.bin/tmux/status.c
886
tmp = utf8_tocstr(c->prompt_buffer);
usr.bin/tmux/status.c
887
format_add(c->prompt_formats, "prompt-input", "%s", tmp);
usr.bin/tmux/status.c
889
free(tmp);
usr.bin/tmux/style.c
101
else if (strcasecmp(tmp, "set-default") == 0)
usr.bin/tmux/style.c
103
else if (strcasecmp(tmp, "nolist") == 0)
usr.bin/tmux/style.c
105
else if (strncasecmp(tmp, "list=", 5) == 0) {
usr.bin/tmux/style.c
106
if (strcasecmp(tmp + 5, "on") == 0)
usr.bin/tmux/style.c
108
else if (strcasecmp(tmp + 5, "focus") == 0)
usr.bin/tmux/style.c
110
else if (strcasecmp(tmp + 5, "left-marker") == 0)
usr.bin/tmux/style.c
112
else if (strcasecmp(tmp + 5, "right-marker") == 0)
usr.bin/tmux/style.c
116
} else if (strcasecmp(tmp, "norange") == 0) {
usr.bin/tmux/style.c
121
} else if (end > 6 && strncasecmp(tmp, "range=", 6) == 0) {
usr.bin/tmux/style.c
122
found = strchr(tmp + 6, '|');
usr.bin/tmux/style.c
128
if (strcasecmp(tmp + 6, "left") == 0) {
usr.bin/tmux/style.c
134
} else if (strcasecmp(tmp + 6, "right") == 0) {
usr.bin/tmux/style.c
140
} else if (strcasecmp(tmp + 6, "control") == 0) {
usr.bin/tmux/style.c
149
} else if (strcasecmp(tmp + 6, "pane") == 0) {
usr.bin/tmux/style.c
160
} else if (strcasecmp(tmp + 6, "window") == 0) {
usr.bin/tmux/style.c
169
} else if (strcasecmp(tmp + 6, "session") == 0) {
usr.bin/tmux/style.c
180
} else if (strcasecmp(tmp + 6, "user") == 0) {
usr.bin/tmux/style.c
187
} else if (strcasecmp(tmp, "noalign") == 0)
usr.bin/tmux/style.c
189
else if (end > 6 && strncasecmp(tmp, "align=", 6) == 0) {
usr.bin/tmux/style.c
190
if (strcasecmp(tmp + 6, "left") == 0)
usr.bin/tmux/style.c
192
else if (strcasecmp(tmp + 6, "centre") == 0)
usr.bin/tmux/style.c
194
else if (strcasecmp(tmp + 6, "right") == 0)
usr.bin/tmux/style.c
196
else if (strcasecmp(tmp + 6, "absolute-centre") == 0)
usr.bin/tmux/style.c
200
} else if (end > 5 && strncasecmp(tmp, "fill=", 5) == 0) {
usr.bin/tmux/style.c
201
if ((value = colour_fromstring(tmp + 5)) == -1)
usr.bin/tmux/style.c
204
} else if (end > 3 && strncasecmp(tmp + 1, "g=", 2) == 0) {
usr.bin/tmux/style.c
205
if ((value = colour_fromstring(tmp + 3)) == -1)
usr.bin/tmux/style.c
219
} else if (end > 3 && strncasecmp(tmp, "us=", 3) == 0) {
usr.bin/tmux/style.c
220
if ((value = colour_fromstring(tmp + 3)) == -1)
usr.bin/tmux/style.c
226
} else if (strcasecmp(tmp, "none") == 0)
usr.bin/tmux/style.c
228
else if (end > 2 && strncasecmp(tmp, "no", 2) == 0) {
usr.bin/tmux/style.c
229
if (strcmp(tmp + 2, "attr") == 0)
usr.bin/tmux/style.c
232
value = attributes_fromstring(tmp + 2);
usr.bin/tmux/style.c
237
} else if (end > 6 && strncasecmp(tmp, "width=", 6) == 0) {
usr.bin/tmux/style.c
238
if (end > 7 && tmp[end - 1] == '%') {
usr.bin/tmux/style.c
239
tmp[end - 1] = '\0';
usr.bin/tmux/style.c
240
n = strtonum(tmp + 6, 0, 100, &errstr);
usr.bin/tmux/style.c
246
n = strtonum(tmp + 6, 0, UINT_MAX, &errstr);
usr.bin/tmux/style.c
252
} else if (end > 4 && strncasecmp(tmp, "pad=", 4) == 0) {
usr.bin/tmux/style.c
253
n = strtonum(tmp + 4, 0, UINT_MAX, &errstr);
usr.bin/tmux/style.c
258
if ((value = attributes_fromstring(tmp)) == -1)
usr.bin/tmux/style.c
279
const char *comma = "", *tmp = "";
usr.bin/tmux/style.c
287
tmp = "on";
usr.bin/tmux/style.c
289
tmp = "focus";
usr.bin/tmux/style.c
291
tmp = "left-marker";
usr.bin/tmux/style.c
293
tmp = "right-marker";
usr.bin/tmux/style.c
295
tmp);
usr.bin/tmux/style.c
300
tmp = "left";
usr.bin/tmux/style.c
302
tmp = "right";
usr.bin/tmux/style.c
305
tmp = b;
usr.bin/tmux/style.c
308
tmp = b;
usr.bin/tmux/style.c
312
tmp = b;
usr.bin/tmux/style.c
315
tmp = b;
usr.bin/tmux/style.c
318
tmp);
usr.bin/tmux/style.c
323
tmp = "left";
usr.bin/tmux/style.c
325
tmp = "centre";
usr.bin/tmux/style.c
327
tmp = "right";
usr.bin/tmux/style.c
329
tmp = "absolute-centre";
usr.bin/tmux/style.c
331
tmp);
usr.bin/tmux/style.c
336
tmp = "push-default";
usr.bin/tmux/style.c
338
tmp = "pop-default";
usr.bin/tmux/style.c
340
tmp = "set-default";
usr.bin/tmux/style.c
341
off += xsnprintf(s + off, sizeof s - off, "%s%s", comma, tmp);
usr.bin/tmux/style.c
64
char tmp[256], *found;
usr.bin/tmux/style.c
81
if (end > (sizeof tmp) - 1)
usr.bin/tmux/style.c
83
memcpy(tmp, in, end);
usr.bin/tmux/style.c
84
tmp[end] = '\0';
usr.bin/tmux/style.c
86
log_debug("%s: %s", __func__, tmp);
usr.bin/tmux/style.c
87
if (strcasecmp(tmp, "default") == 0) {
usr.bin/tmux/style.c
93
} else if (strcasecmp(tmp, "ignore") == 0)
usr.bin/tmux/style.c
95
else if (strcasecmp(tmp, "noignore") == 0)
usr.bin/tmux/style.c
97
else if (strcasecmp(tmp, "push-default") == 0)
usr.bin/tmux/style.c
99
else if (strcasecmp(tmp, "pop-default") == 0)
usr.bin/tmux/tmux.c
149
char *copy, *next, *tmp, resolved[PATH_MAX], *expanded;
usr.bin/tmux/tmux.c
156
copy = tmp = xstrdup(s);
usr.bin/tmux/tmux.c
157
while ((next = strsep(&tmp, ":")) != NULL) {
usr.bin/tmux/tty-keys.c
1050
char tmp[64];
usr.bin/tmux/tty-keys.c
1072
for (end = 2; end < len && end != sizeof tmp; end++) {
usr.bin/tmux/tty-keys.c
1080
if (end == sizeof tmp || (buf[end] != '~' && buf[end] != 'u'))
usr.bin/tmux/tty-keys.c
1084
memcpy(tmp, buf + 2, end - 2);
usr.bin/tmux/tty-keys.c
1085
tmp[end - 2] = '\0';
usr.bin/tmux/tty-keys.c
1089
if (sscanf(tmp, "27;%u;%u", &modifiers, &number) != 2)
usr.bin/tmux/tty-keys.c
1092
if (sscanf(tmp ,"%u;%u", &number, &modifiers) != 2)
usr.bin/tmux/tty-keys.c
1429
char tmp[128], *endptr, p[32] = { 0 }, *cp, *next;
usr.bin/tmux/tty-keys.c
1450
for (i = 0; i < sizeof tmp; i++) {
usr.bin/tmux/tty-keys.c
1455
tmp[i] = buf[3 + i];
usr.bin/tmux/tty-keys.c
1457
if (i == sizeof tmp)
usr.bin/tmux/tty-keys.c
1461
tmp[i] = '\0';
usr.bin/tmux/tty-keys.c
1465
cp = tmp;
usr.bin/tmux/tty-keys.c
1513
char tmp[128], *endptr, p[32] = { 0 }, *cp, *next;
usr.bin/tmux/tty-keys.c
1534
for (i = 0; i < sizeof tmp; i++) {
usr.bin/tmux/tty-keys.c
1539
tmp[i] = buf[3 + i];
usr.bin/tmux/tty-keys.c
1541
if (i == sizeof tmp)
usr.bin/tmux/tty-keys.c
1545
tmp[i] = '\0';
usr.bin/tmux/tty-keys.c
1549
cp = tmp;
usr.bin/tmux/tty-keys.c
1593
char tmp[128];
usr.bin/tmux/tty-keys.c
1618
for (i = 0; i < (sizeof tmp) - 1; i++) {
usr.bin/tmux/tty-keys.c
1623
tmp[i] = buf[4 + i];
usr.bin/tmux/tty-keys.c
1625
if (i == (sizeof tmp) - 1)
usr.bin/tmux/tty-keys.c
1630
tmp[i - 1] = '\0';
usr.bin/tmux/tty-keys.c
1633
if (strncmp(tmp, "iTerm2 ", 7) == 0)
usr.bin/tmux/tty-keys.c
1635
else if (strncmp(tmp, "tmux ", 5) == 0)
usr.bin/tmux/tty-keys.c
1637
else if (strncmp(tmp, "XTerm(", 6) == 0)
usr.bin/tmux/tty-keys.c
1639
else if (strncmp(tmp, "mintty ", 7) == 0)
usr.bin/tmux/tty-keys.c
1641
else if (strncmp(tmp, "foot(", 5) == 0)
usr.bin/tmux/tty-keys.c
1646
c->term_type = xstrdup(tmp);
usr.bin/tmux/tty-keys.c
1664
char tmp[128];
usr.bin/tmux/tty-keys.c
1692
for (i = 0; i < (sizeof tmp) - 1; i++) {
usr.bin/tmux/tty-keys.c
1699
tmp[i] = buf[5 + i];
usr.bin/tmux/tty-keys.c
1701
if (i == (sizeof tmp) - 1)
usr.bin/tmux/tty-keys.c
1706
if (tmp[i - 1] == '\033')
usr.bin/tmux/tty-keys.c
1707
tmp[i - 1] = '\0';
usr.bin/tmux/tty-keys.c
1709
tmp[i] = '\0';
usr.bin/tmux/tty-keys.c
1712
n = colour_parseX11(tmp);
usr.bin/tmux/tty-keys.c
1738
char tmp[128], *endptr;
usr.bin/tmux/tty-keys.c
1763
for (i = 0; i < (sizeof tmp) - 1; i++) {
usr.bin/tmux/tty-keys.c
1770
tmp[i] = buf[4 + i];
usr.bin/tmux/tty-keys.c
1772
if (i == (sizeof tmp) - 1)
usr.bin/tmux/tty-keys.c
1777
if (tmp[i - 1] == '\033')
usr.bin/tmux/tty-keys.c
1778
tmp[i - 1] = '\0';
usr.bin/tmux/tty-keys.c
1780
tmp[i] = '\0';
usr.bin/tmux/tty-keys.c
1783
idx = strtol(tmp, &endptr, 10);
usr.bin/tmux/tty-keys.c
668
char tmp[64];
usr.bin/tmux/tty-keys.c
691
for (end = 2; end < len && end != sizeof tmp; end++) {
usr.bin/tmux/tty-keys.c
699
if (end == sizeof tmp || buf[end] != 't')
usr.bin/tmux/tty-keys.c
703
memcpy(tmp, buf + 2, end - 2);
usr.bin/tmux/tty-keys.c
704
tmp[end - 2] = '\0';
usr.bin/tmux/tty-keys.c
707
if (sscanf(tmp, "8;%u;%u", &sy, &sx) == 2) {
usr.bin/tmux/tty-keys.c
713
} else if (sscanf(tmp, "4;%u;%u", &ypixel, &xpixel) == 2) {
usr.bin/tmux/tty-keys.c
725
log_debug("%s: unrecognized window size sequence: %s", c->name, tmp);
usr.bin/tmux/tty-term.c
688
char tmp[11];
usr.bin/tmux/tty-term.c
727
xsnprintf(tmp, sizeof tmp, "%d", n);
usr.bin/tmux/tty-term.c
728
s = tmp;
usr.bin/tmux/tty.c
1291
char tmp[64];
usr.bin/tmux/tty.c
1317
xsnprintf(tmp, sizeof tmp, "\033[32;%u;%u;%u;%u$x",
usr.bin/tmux/tty.c
1319
tty_puts(tty, tmp);
usr.bin/tmux/utf8.c
882
struct utf8_data tmp;
usr.bin/tmux/utf8.c
888
if ((more = utf8_open(&tmp, *s)) == UTF8_MORE) {
usr.bin/tmux/utf8.c
890
more = utf8_append(&tmp, *s);
usr.bin/tmux/utf8.c
892
width += tmp.width;
usr.bin/tmux/utf8.c
895
s -= tmp.have;
usr.bin/tmux/window-customize.c
451
char *title, *text, *tmp, *expanded;
usr.bin/tmux/window-customize.c
492
tmp = cmd_list_print(bd->cmdlist, 0);
usr.bin/tmux/window-customize.c
493
xasprintf(&text, "#[ignore]%s", tmp);
usr.bin/tmux/window-customize.c
494
free(tmp);
usr.bin/top/commands.c
276
char *nptr, *tmp;
usr.bin/top/commands.c
278
tmp = tempbuf;
usr.bin/top/commands.c
298
(void) scan_arg(str, &signum, tmp);
usr.bin/tput/tput.c
255
char *tmp = 0;
usr.bin/tput/tput.c
257
numbers[k] = strtol(argv[k], &tmp, 0);
usr.bin/tput/tput.c
258
if (tmp == 0 || *tmp != 0)
usr.bin/tr/str.c
167
CLASS *cp, tmp;
usr.bin/tr/str.c
171
tmp.name = (char *)s->str;
usr.bin/tr/str.c
172
if ((cp = (CLASS *)bsearch(&tmp, classes, sizeof(classes) /
usr.bin/unifdef/unifdef.c
1585
mktempmode(char *tmp, int mode)
usr.bin/unifdef/unifdef.c
1587
int fd = mkstemp(tmp);
usr.bin/unifdef/unifdef.c
255
static FILE * mktempmode(char *tmp, int mode);
usr.bin/uniq/uniq.c
151
tmp = prevline;
usr.bin/uniq/uniq.c
153
thisline = tmp;
usr.bin/uniq/uniq.c
154
tmp = p;
usr.bin/uniq/uniq.c
156
t = tmp;
usr.bin/uniq/uniq.c
61
char *p, *prevline, *t, *thisline, *tmp;
usr.bin/vi/ex/ex.c
1100
if (ex_line(sp, ecp, &cur, &isaddr, &tmp))
usr.bin/vi/ex/ex.c
1102
if (tmp)
usr.bin/vi/ex/ex.c
1193
tmp = *p - '0';
usr.bin/vi/ex/ex.c
1195
exp->argsoff != tmp)
usr.bin/vi/ex/ex.c
1596
rfail: tmp = 1;
usr.bin/vi/ex/ex.c
1598
rsuccess: tmp = 0;
usr.bin/vi/ex/ex.c
1606
return (tmp);
usr.bin/vi/ex/ex.c
207
int newscreen, notempty, tmp, vi_address;
usr.bin/vi/ex/ex.c
343
if (ex_range(sp, ecp, &tmp))
usr.bin/vi/ex/ex.c
345
if (tmp)
usr.bin/vi/ex/ex.c
709
for (tmp = 0; ecp->clen > 0; --ecp->clen, ++ecp->cp) {
usr.bin/vi/ex/ex.c
712
tmp = 1;
usr.bin/vi/ex/ex.c
717
(ecp->cmd == &cmds[C_READ] || tmp))
usr.bin/vi/ex/ex.c
776
tmp = ecp->cp[1];
usr.bin/vi/ex/ex.c
777
if (tmp == '\n' || tmp == '|') {
usr.bin/vi/ex/ex.c
778
if (tmp == '\n') {
usr.bin/vi/ex/ex.c
785
ch = tmp;
usr.bin/vi/vi/v_txt.c
1116
tmp = inword(tp->lb[tp->cno - 1]);
usr.bin/vi/vi/v_txt.c
1118
if (tmp != inword(tp->lb[tp->cno - 1])
usr.bin/vi/vi/v_txt.c
1257
LF_ISSET(TXT_INFOLINE), &tmp, &ab_turnoff))
usr.bin/vi/vi/v_txt.c
1259
if (tmp) {
usr.bin/vi/vi/v_txt.c
1261
rcol -= tmp + 1;
usr.bin/vi/vi/v_txt.c
1312
if (txt_margin(sp, tp, &wmt, &tmp, flags))
usr.bin/vi/vi/v_txt.c
1314
if (tmp) {
usr.bin/vi/vi/v_txt.c
268
int max, tmp;
usr.bin/vi/vi/v_txt.c
695
LF_ISSET(TXT_INFOLINE), &tmp, \
usr.bin/vi/vi/v_txt.c
698
if (tmp) { \
usr.bin/vi/vi/v_txt.c
700
rcol -= tmp + 1; \
usr.bin/vi/vi/vs_refresh.c
161
SMAP *smp, tmp;
usr.bin/vi/vi/vs_refresh.c
346
tmp.lno = LNO;
usr.bin/vi/vi/vs_refresh.c
347
tmp.coff = HMAP->coff;
usr.bin/vi/vi/vs_refresh.c
348
tmp.soff = 1;
usr.bin/vi/vi/vs_refresh.c
349
lcnt = vs_sm_nlines(sp, &tmp, lastline, sp->t_rows);
usr.bin/vi/vi/vs_refresh.c
365
tmp.lno = 1;
usr.bin/vi/vi/vs_refresh.c
366
tmp.coff = HMAP->coff;
usr.bin/vi/vi/vs_refresh.c
367
tmp.soff = 1;
usr.bin/vi/vi/vs_refresh.c
368
lcnt = vs_sm_nlines(sp, &tmp, LNO, HALFTEXT(sp));
usr.bin/vi/vi/vs_smap.c
172
SMAP *p, tmp;
usr.bin/vi/vi/vs_smap.c
191
tmp.lno = 1;
usr.bin/vi/vi/vs_smap.c
192
tmp.coff = 0;
usr.bin/vi/vi/vs_smap.c
193
tmp.soff = 1;
usr.bin/vi/vi/vs_smap.c
197
&tmp, lno, HALFTEXT(sp)) <= HALFTEXT(sp)) {
usr.bin/vi/vi/vs_smap.c
203
if (db_last(sp, &tmp.lno))
usr.bin/vi/vi/vs_smap.c
205
tmp.coff = 0;
usr.bin/vi/vi/vs_smap.c
206
tmp.soff = vs_screens(sp, tmp.lno, NULL);
usr.bin/vi/vi/vs_smap.c
208
&tmp, lno, HALFTEXT(sp)) <= HALFTEXT(sp)) {
usr.bin/vi/vi/vs_smap.c
209
TMAP->lno = tmp.lno;
usr.bin/vi/vi/vs_smap.c
210
TMAP->coff = tmp.coff;
usr.bin/vi/vi/vs_smap.c
211
TMAP->soff = tmp.soff;
usr.bin/vmstat/dkstats.c
104
#define SWAP(fld) tmp = cur.fld; \
usr.bin/vmstat/dkstats.c
106
last.fld = tmp
usr.bin/vmstat/dkstats.c
116
u_int64_t tmp;
usr.bin/w/w.c
312
char *tmp;
usr.bin/w/w.c
314
if ((tmp = hostlookup(p, domain)) != NULL)
usr.bin/w/w.c
315
p = tmp;
usr.bin/xargs/xargs.c
422
char **tmp, **tmp2, **avj;
usr.bin/xargs/xargs.c
440
tmp = calloc(argc + 1, sizeof(char *));
usr.bin/xargs/xargs.c
441
if (tmp == NULL)
usr.bin/xargs/xargs.c
443
tmp2 = tmp;
usr.bin/xargs/xargs.c
449
if ((*tmp++ = strdup(*avj++)) == NULL)
usr.bin/xargs/xargs.c
461
*tmp = *avj++;
usr.bin/xargs/xargs.c
462
if (repls && strstr(*tmp, replstr) != NULL) {
usr.bin/xargs/xargs.c
463
strnsubst(tmp++, replstr, inpline, (size_t)255);
usr.bin/xargs/xargs.c
467
if ((*tmp = strdup(*tmp)) == NULL)
usr.bin/xargs/xargs.c
469
tmp++;
usr.bin/xargs/xargs.c
476
*tmp = NULL;
usr.bin/xargs/xargs.c
482
for (; tmp2 != tmp; tmp--)
usr.bin/xargs/xargs.c
483
free(*tmp);
usr.sbin/acme-client/fileproc.c
35
char *tmp;
usr.sbin/acme-client/fileproc.c
38
if (asprintf(&tmp, "%s.1", real) == -1) {
usr.sbin/acme-client/fileproc.c
42
(void) unlink(tmp);
usr.sbin/acme-client/fileproc.c
43
if (link(real, tmp) == -1 && errno != ENOENT) {
usr.sbin/acme-client/fileproc.c
45
free(tmp);
usr.sbin/acme-client/fileproc.c
48
free(tmp);
usr.sbin/acme-client/fileproc.c
55
if (asprintf(&tmp, "%s.XXXXXXXXXX", real) == -1) {
usr.sbin/acme-client/fileproc.c
59
if ((fd = mkstemp(tmp)) == -1) {
usr.sbin/acme-client/fileproc.c
77
if (rename(tmp, real) == -1) {
usr.sbin/acme-client/fileproc.c
82
free(tmp);
usr.sbin/acme-client/fileproc.c
87
(void) unlink(tmp);
usr.sbin/acme-client/fileproc.c
88
free(tmp);
usr.sbin/acme-client/json.c
104
tmp = build(parse,
usr.sbin/acme-client/json.c
107
if (tmp < 0)
usr.sbin/acme-client/json.c
109
j += tmp;
usr.sbin/acme-client/json.c
110
tmp = build(parse,
usr.sbin/acme-client/json.c
113
if (tmp < 0)
usr.sbin/acme-client/json.c
115
j += tmp;
usr.sbin/acme-client/json.c
127
tmp = build(parse,
usr.sbin/acme-client/json.c
130
if (tmp < 0)
usr.sbin/acme-client/json.c
132
j += tmp;
usr.sbin/acme-client/json.c
76
ssize_t tmp;
usr.sbin/authpf/authpf.c
592
char tmp[PATH_MAX];
usr.sbin/authpf/authpf.c
594
n = snprintf(tmp, sizeof(tmp), "%s/%s", luserdir, luser);
usr.sbin/authpf/authpf.c
595
if (n < 0 || (u_int)n >= sizeof(tmp)) {
usr.sbin/authpf/authpf.c
600
if ((f = fopen(tmp, "r")) == NULL) {
usr.sbin/authpf/authpf.c
614
tmp, strerror(errno));
usr.sbin/authpf/authpf.c
623
luser, tmp);
usr.sbin/authpf/authpf.c
626
strlcpy(tmp, "\n\n-**- Sorry, you have been banned! -**-\n\n",
usr.sbin/authpf/authpf.c
627
sizeof(tmp));
usr.sbin/authpf/authpf.c
628
while (fputs(tmp, stdout) != EOF && !feof(f)) {
usr.sbin/authpf/authpf.c
629
if (fgets(tmp, sizeof(tmp), f) == NULL) {
usr.sbin/bgpctl/bgpctl.c
1689
uint8_t tmp;
usr.sbin/bgpctl/bgpctl.c
1690
if (ibuf_get_n8(&attrbuf, &tmp) == -1)
usr.sbin/bgpctl/bgpctl.c
1692
attrlen = tmp;
usr.sbin/bgpctl/parser.c
1002
struct bgpd_addr tmp;
usr.sbin/bgpctl/parser.c
1010
memset(&tmp, 0, sizeof(tmp));
usr.sbin/bgpctl/parser.c
1022
if (parse_addr(ps, &tmp) == 0) {
usr.sbin/bgpctl/parser.c
1029
if (parse_addr(word, &tmp) == 0)
usr.sbin/bgpctl/parser.c
1032
switch (tmp.aid) {
usr.sbin/bgpctl/parser.c
1047
applymask(addr, &tmp, mask);
usr.sbin/bgpd/config.c
645
struct network *n, *m, *tmp;
usr.sbin/bgpd/config.c
649
TAILQ_FOREACH_SAFE(n, nw, entry, tmp) {
usr.sbin/bgpd/kroute.c
1592
struct kroute *kn, *tmp;
usr.sbin/bgpd/kroute.c
1600
tmp = RB_PREV(kroute_tree, &kt->krt, kn);
usr.sbin/bgpd/kroute.c
1601
while (tmp) {
usr.sbin/bgpd/kroute.c
1602
if (kroute_compare(&s, tmp) == 0)
usr.sbin/bgpd/kroute.c
1603
kn = tmp;
usr.sbin/bgpd/kroute.c
1606
tmp = RB_PREV(kroute_tree, &kt->krt, kn);
usr.sbin/bgpd/kroute.c
1937
struct kroute6 *kn6, *tmp;
usr.sbin/bgpd/kroute.c
1946
tmp = RB_PREV(kroute6_tree, &kt->krt6, kn6);
usr.sbin/bgpd/kroute.c
1947
while (tmp) {
usr.sbin/bgpd/kroute.c
1948
if (kroute6_compare(&s, tmp) == 0)
usr.sbin/bgpd/kroute.c
1949
kn6 = tmp;
usr.sbin/bgpd/kroute.c
1952
tmp = RB_PREV(kroute6_tree, &kt->krt6, kn6);
usr.sbin/bgpd/mrt.c
102
uint8_t tmp;
usr.sbin/bgpd/mrt.c
103
if (ibuf_get_n8(&buf, &tmp) == -1)
usr.sbin/bgpd/mrt.c
105
len = tmp;
usr.sbin/bgpd/mrt.c
224
uint32_t tmp;
usr.sbin/bgpd/mrt.c
258
tmp = htonl(a->med);
usr.sbin/bgpd/mrt.c
259
if (attr_writebuf(buf, ATTR_OPTIONAL, ATTR_MED, &tmp, 4) == -1)
usr.sbin/bgpd/mrt.c
264
tmp = htonl(a->lpref);
usr.sbin/bgpd/mrt.c
265
if (attr_writebuf(buf, ATTR_WELL_KNOWN, ATTR_LOCALPREF, &tmp, 4) == -1)
usr.sbin/bgpd/pftable.c
175
struct pfr_addr *pfa, *tmp;
usr.sbin/bgpd/pftable.c
201
tmp = reallocarray(pft->worklist, pft->nalloc, sizeof(*tmp));
usr.sbin/bgpd/pftable.c
202
if (tmp == NULL) {
usr.sbin/bgpd/pftable.c
212
pft->worklist = tmp;
usr.sbin/bgpd/rde.c
1731
uint32_t tmp;
usr.sbin/bgpd/rde.c
1736
tmp = htonl(peer->conf.remote_as);
usr.sbin/bgpd/rde.c
1739
&tmp, sizeof(tmp)) == -1) {
usr.sbin/bgpd/rde.c
1798
uint32_t tmp;
usr.sbin/bgpd/rde.c
1803
tmp = htonl(peer->conf.remote_as);
usr.sbin/bgpd/rde.c
1806
ATTR_OTC, &tmp,
usr.sbin/bgpd/rde.c
1807
sizeof(tmp)) == -1) {
usr.sbin/bgpd/rde_prefix.c
638
struct ibuf *tmp;
usr.sbin/bgpd/rde_prefix.c
642
if ((tmp = ibuf_dynamic(32, UINT16_MAX)) == NULL)
usr.sbin/bgpd/rde_prefix.c
646
if (ibuf_add_n32(tmp, pathid) == -1)
usr.sbin/bgpd/rde_prefix.c
654
if (ibuf_add_n8(tmp, plen) == -1)
usr.sbin/bgpd/rde_prefix.c
656
if (ibuf_add(tmp, pte->data, PREFIX_SIZE(plen) - 1) == -1)
usr.sbin/bgpd/rde_prefix.c
670
if (ibuf_add_n8(tmp, plen) == -1)
usr.sbin/bgpd/rde_prefix.c
674
if (ibuf_add_n8(tmp, 0x80) == -1 ||
usr.sbin/bgpd/rde_prefix.c
675
ibuf_add_zero(tmp, 2) == -1)
usr.sbin/bgpd/rde_prefix.c
678
if (ibuf_add(tmp, &pvpn4->labelstack,
usr.sbin/bgpd/rde_prefix.c
682
if (ibuf_add(tmp, &pvpn4->rd, sizeof(pvpn4->rd)) == -1 ||
usr.sbin/bgpd/rde_prefix.c
683
ibuf_add(tmp, &pvpn4->prefix4, psize) == -1)
usr.sbin/bgpd/rde_prefix.c
697
if (ibuf_add_n8(tmp, plen) == -1)
usr.sbin/bgpd/rde_prefix.c
701
if (ibuf_add_n8(tmp, 0x80) == -1 ||
usr.sbin/bgpd/rde_prefix.c
702
ibuf_add_zero(tmp, 2) == -1)
usr.sbin/bgpd/rde_prefix.c
705
if (ibuf_add(tmp, &pvpn6->labelstack,
usr.sbin/bgpd/rde_prefix.c
709
if (ibuf_add(tmp, &pvpn6->rd, sizeof(pvpn6->rd)) == -1 ||
usr.sbin/bgpd/rde_prefix.c
710
ibuf_add(tmp, &pvpn6->prefix6, psize) == -1)
usr.sbin/bgpd/rde_prefix.c
714
if (ibuf_add_n8(tmp, pevpn->type) == -1)
usr.sbin/bgpd/rde_prefix.c
726
if (ibuf_add_n8(tmp, PREFIX_SIZE(plen) - 1) == -1)
usr.sbin/bgpd/rde_prefix.c
728
if (ibuf_add_h64(tmp, pevpn->rd) == -1 ||
usr.sbin/bgpd/rde_prefix.c
729
ibuf_add(tmp, pevpn->esi,
usr.sbin/bgpd/rde_prefix.c
731
ibuf_add_h32(tmp, pevpn->ethtag) == -1)
usr.sbin/bgpd/rde_prefix.c
733
if (ibuf_add_n8(tmp, sizeof(pevpn->mac) * 8) == -1 ||
usr.sbin/bgpd/rde_prefix.c
734
ibuf_add(tmp, pevpn->mac, sizeof(pevpn->mac)) == -1)
usr.sbin/bgpd/rde_prefix.c
736
if (ibuf_add_n8(tmp, pevpn->prefixlen) == -1)
usr.sbin/bgpd/rde_prefix.c
743
if (ibuf_add(tmp, &pevpn->prefix4,
usr.sbin/bgpd/rde_prefix.c
748
if (ibuf_add(tmp, &pevpn->prefix6,
usr.sbin/bgpd/rde_prefix.c
755
if (ibuf_add(tmp, pevpn->labelstack,
usr.sbin/bgpd/rde_prefix.c
764
if (ibuf_add_n8(tmp, PREFIX_SIZE(plen) - 1) == -1)
usr.sbin/bgpd/rde_prefix.c
766
if (ibuf_add_h64(tmp, pevpn->rd) == -1 ||
usr.sbin/bgpd/rde_prefix.c
767
ibuf_add_h32(tmp, pevpn->ethtag) == -1)
usr.sbin/bgpd/rde_prefix.c
769
if (ibuf_add_n8(tmp, pevpn->prefixlen) == -1)
usr.sbin/bgpd/rde_prefix.c
773
if (ibuf_add(tmp, &pevpn->prefix4,
usr.sbin/bgpd/rde_prefix.c
778
if (ibuf_add(tmp, &pevpn->prefix6,
usr.sbin/bgpd/rde_prefix.c
791
if (ibuf_add_n8(tmp, flowlen) == -1)
usr.sbin/bgpd/rde_prefix.c
794
if (ibuf_add_n8(tmp, 0xf0 | (flowlen >> 8)) == -1 ||
usr.sbin/bgpd/rde_prefix.c
795
ibuf_add_n8(tmp, flowlen) == -1)
usr.sbin/bgpd/rde_prefix.c
798
if (ibuf_add(tmp, &pflow->flow, flowlen) == -1)
usr.sbin/bgpd/rde_prefix.c
806
if (withdraw && ibuf_left(buf) < ibuf_size(tmp) + 2)
usr.sbin/bgpd/rde_prefix.c
808
if (ibuf_add_ibuf(buf, tmp) == -1)
usr.sbin/bgpd/rde_prefix.c
810
ibuf_free(tmp);
usr.sbin/bgpd/rde_prefix.c
814
ibuf_free(tmp);
usr.sbin/bgpd/rde_update.c
138
uint32_t tmp;
usr.sbin/bgpd/rde_update.c
140
tmp = htonl(peer->conf.local_as);
usr.sbin/bgpd/rde_update.c
143
&tmp, sizeof(tmp)) == -1)
usr.sbin/bgpd/session_bgp.c
984
uint8_t tmp;
usr.sbin/bgpd/session_bgp.c
985
if (ibuf_get_n8(&oparams, &tmp) == -1)
usr.sbin/bgpd/session_bgp.c
987
op_len = tmp;
usr.sbin/bgpd/util.c
626
uint16_t tmp;
usr.sbin/bgpd/util.c
627
if (ibuf_get_n16(&buf, &tmp) == -1) {
usr.sbin/bgpd/util.c
631
as = tmp;
usr.sbin/bgpd/util.c
716
uint8_t tmp;
usr.sbin/bgpd/util.c
723
if (ibuf_get_n8(buf, &tmp) == -1)
usr.sbin/bgpd/util.c
727
*a++ = tmp & addrmask[pfxlen];
usr.sbin/bgpd/util.c
730
*a++ = tmp;
usr.sbin/btrace/ksyms.c
199
tmp = reallocarray(syms->table, syms->nsymb, sizeof *syms->table);
usr.sbin/btrace/ksyms.c
200
if (tmp == NULL)
usr.sbin/btrace/ksyms.c
202
syms->table = tmp;
usr.sbin/btrace/ksyms.c
73
struct sym *tmp;
usr.sbin/cron/crontab.c
427
FILE *tmp;
usr.sbin/cron/crontab.c
444
tmp = spool_mkstemp(TempFilename);
usr.sbin/cron/crontab.c
445
if (tmp == NULL) {
usr.sbin/cron/crontab.c
458
fprintf(tmp, "# DO NOT EDIT THIS FILE - edit the master and reinstall.\n");
usr.sbin/cron/crontab.c
459
fprintf(tmp, "# (%s installed on %-24.24s)\n", Filename, ctime(&now));
usr.sbin/cron/crontab.c
460
fprintf(tmp, "# (Cron version %s)\n", CRON_VERSION);
usr.sbin/cron/crontab.c
467
putc(ch, tmp);
usr.sbin/cron/crontab.c
468
ftruncate(fileno(tmp), ftello(tmp)); /* XXX redundant with "w+"? */
usr.sbin/cron/crontab.c
469
fflush(tmp); rewind(tmp);
usr.sbin/cron/crontab.c
471
if (ferror(tmp)) {
usr.sbin/cron/crontab.c
473
fclose(tmp);
usr.sbin/cron/crontab.c
488
switch (load_env(envstr, tmp)) {
usr.sbin/cron/crontab.c
498
e = load_entry(tmp, check_error, pw, envp);
usr.sbin/cron/crontab.c
509
fclose(tmp);
usr.sbin/cron/crontab.c
514
if (fclose(tmp) == EOF) {
usr.sbin/dhcpd/confpars.c
962
struct tree *tmp;
usr.sbin/dhcpd/confpars.c
965
tmp = parse_ip_addr_or_hostname(cfile, 0);
usr.sbin/dhcpd/confpars.c
967
tree = tree_concat(tree, tmp);
usr.sbin/dhcpd/confpars.c
969
tree = tmp;
usr.sbin/dhcpd/convert.c
100
memcpy(obuf, &tmp, sizeof(tmp));
usr.sbin/dhcpd/convert.c
106
int16_t tmp = htons(val);
usr.sbin/dhcpd/convert.c
108
memcpy(obuf, &tmp, sizeof(tmp));
usr.sbin/dhcpd/convert.c
82
u_int32_t tmp = htonl(val);
usr.sbin/dhcpd/convert.c
84
memcpy(obuf, &tmp, sizeof(tmp));
usr.sbin/dhcpd/convert.c
90
int32_t tmp = htonl(val);
usr.sbin/dhcpd/convert.c
92
memcpy(obuf, &tmp, sizeof(tmp));
usr.sbin/dhcpd/convert.c
98
u_int16_t tmp = htons(val);
usr.sbin/dhcpd/dhcpd.c
178
struct interface_info *tmp = calloc(1, sizeof(*tmp));
usr.sbin/dhcpd/dhcpd.c
179
if (!tmp)
usr.sbin/dhcpd/dhcpd.c
181
strlcpy(tmp->name, argv[0], sizeof(tmp->name));
usr.sbin/dhcpd/dhcpd.c
182
tmp->next = interfaces;
usr.sbin/dhcpd/dhcpd.c
183
interfaces = tmp;
usr.sbin/dhcpd/dispatch.c
117
for (tmp = interfaces; tmp; tmp = tmp->next)
usr.sbin/dhcpd/dispatch.c
118
if (!strcmp(tmp->name, ifa->ifa_name))
usr.sbin/dhcpd/dispatch.c
122
if (tmp == NULL && ir)
usr.sbin/dhcpd/dispatch.c
127
if (tmp == NULL) {
usr.sbin/dhcpd/dispatch.c
128
tmp = calloc(1, sizeof *tmp);
usr.sbin/dhcpd/dispatch.c
129
if (!tmp)
usr.sbin/dhcpd/dispatch.c
132
strlcpy(tmp->name, ifa->ifa_name, sizeof(tmp->name));
usr.sbin/dhcpd/dispatch.c
133
tmp->next = interfaces;
usr.sbin/dhcpd/dispatch.c
134
tmp->noifmedia = tmp->dead = tmp->errors = 0;
usr.sbin/dhcpd/dispatch.c
135
interfaces = tmp;
usr.sbin/dhcpd/dispatch.c
148
tmp->index = sdl->sdl_index;
usr.sbin/dhcpd/dispatch.c
149
tmp->hw_address.hlen = sdl->sdl_alen;
usr.sbin/dhcpd/dispatch.c
150
tmp->hw_address.htype = HTYPE_ETHER; /* XXX */
usr.sbin/dhcpd/dispatch.c
151
memcpy(tmp->hw_address.haddr,
usr.sbin/dhcpd/dispatch.c
164
if (!tmp->ifp) {
usr.sbin/dhcpd/dispatch.c
173
tmp->ifp = tif;
usr.sbin/dhcpd/dispatch.c
174
tmp->primary_address = foo.sin_addr;
usr.sbin/dhcpd/dispatch.c
181
for (tmp = interfaces; tmp; tmp = next) {
usr.sbin/dhcpd/dispatch.c
184
next = tmp->next;
usr.sbin/dhcpd/dispatch.c
186
if (tmp->index == 0) {
usr.sbin/dhcpd/dispatch.c
188
tmp->name);
usr.sbin/dhcpd/dispatch.c
193
last->next = tmp->next;
usr.sbin/dhcpd/dispatch.c
197
if (!tmp->ifp) {
usr.sbin/dhcpd/dispatch.c
199
tmp->name);
usr.sbin/dhcpd/dispatch.c
204
last->next = tmp->next;
usr.sbin/dhcpd/dispatch.c
208
memcpy(&foo, &tmp->ifp->ifr_addr, sizeof tmp->ifp->ifr_addr);
usr.sbin/dhcpd/dispatch.c
221
subnet->interface = tmp;
usr.sbin/dhcpd/dispatch.c
223
} else if (subnet->interface != tmp) {
usr.sbin/dhcpd/dispatch.c
228
tmp->name);
usr.sbin/dhcpd/dispatch.c
231
if (tmp->shared_network &&
usr.sbin/dhcpd/dispatch.c
232
tmp->shared_network != share) {
usr.sbin/dhcpd/dispatch.c
234
tmp->name,
usr.sbin/dhcpd/dispatch.c
237
tmp->shared_network = share;
usr.sbin/dhcpd/dispatch.c
241
share->interface = tmp;
usr.sbin/dhcpd/dispatch.c
242
} else if (share->interface != tmp) {
usr.sbin/dhcpd/dispatch.c
247
tmp->name);
usr.sbin/dhcpd/dispatch.c
251
if (!tmp->shared_network) {
usr.sbin/dhcpd/dispatch.c
253
"subnet declaration for %s.", tmp->name,
usr.sbin/dhcpd/dispatch.c
259
last->next = tmp->next;
usr.sbin/dhcpd/dispatch.c
263
last = tmp;
usr.sbin/dhcpd/dispatch.c
266
for (subnet = (tmp->shared_network ?
usr.sbin/dhcpd/dispatch.c
267
tmp->shared_network->subnets : NULL); subnet;
usr.sbin/dhcpd/dispatch.c
281
if_register_receive(tmp);
usr.sbin/dhcpd/dispatch.c
282
if_register_send(tmp);
usr.sbin/dhcpd/dispatch.c
283
log_info("Listening on %s (%s).", tmp->name,
usr.sbin/dhcpd/dispatch.c
291
for (tmp = interfaces; tmp; tmp = tmp->next)
usr.sbin/dhcpd/dispatch.c
292
add_protocol(tmp->name, tmp->rfdesc, got_one, tmp);
usr.sbin/dhcpd/dispatch.c
87
struct interface_info *tmp;
usr.sbin/eigrpd/kroute.c
522
struct kroute_priority *kprio, *tmp;
usr.sbin/eigrpd/kroute.c
547
TAILQ_FOREACH(tmp, &kp->priorities, entry)
usr.sbin/eigrpd/kroute.c
548
if (tmp->priority > kprio->priority)
usr.sbin/eigrpd/kroute.c
550
if (tmp)
usr.sbin/eigrpd/kroute.c
551
TAILQ_INSERT_BEFORE(tmp, kprio, entry);
usr.sbin/eigrpd/parse.y
1127
struct eigrp *e, *tmp;
usr.sbin/eigrpd/parse.y
1150
TAILQ_FOREACH(tmp, &conf->instances, entry)
usr.sbin/eigrpd/parse.y
1151
if (tmp->af > e->af ||
usr.sbin/eigrpd/parse.y
1152
(tmp->af == e->af && tmp->as > e->as))
usr.sbin/eigrpd/parse.y
1154
if (tmp)
usr.sbin/eigrpd/parse.y
1155
TAILQ_INSERT_BEFORE(tmp, e, entry);
usr.sbin/eigrpd/parse.y
374
struct summary_addr *s, *tmp;
usr.sbin/eigrpd/parse.y
386
TAILQ_FOREACH(tmp, &ei->summary_list, entry) {
usr.sbin/eigrpd/parse.y
388
&tmp->prefix, min(s->prefixlen,
usr.sbin/eigrpd/parse.y
389
tmp->prefixlen)) == 0) {
usr.sbin/eigrpd/rde_dual.c
260
struct eigrp_route *route, *tmp;
usr.sbin/eigrpd/rde_dual.c
274
TAILQ_FOREACH(tmp, &rn->routes, entry)
usr.sbin/eigrpd/rde_dual.c
275
if (eigrp_addrcmp(eigrp->af, &tmp->nexthop,
usr.sbin/eigrpd/rde_dual.c
278
if (tmp)
usr.sbin/eigrpd/rde_dual.c
279
TAILQ_INSERT_BEFORE(tmp, route, entry);
usr.sbin/httpd/httpd.c
527
char *tmp;
usr.sbin/httpd/httpd.c
530
if ((tmp = calloc(1, len)) == NULL) {
usr.sbin/httpd/httpd.c
537
if ((strlcat(tmp, p, len) >= len) ||
usr.sbin/httpd/httpd.c
538
(strlcat(tmp, repl, len) >= len)) {
usr.sbin/httpd/httpd.c
540
free(tmp);
usr.sbin/httpd/httpd.c
546
if (strlcat(tmp, p, len) >= len) {
usr.sbin/httpd/httpd.c
548
free(tmp);
usr.sbin/httpd/httpd.c
551
(void)strlcpy(label, tmp, len); /* always fits */
usr.sbin/httpd/httpd.c
552
free(tmp);
usr.sbin/inetd/inetd.c
728
struct servtab *tmp = cp;
usr.sbin/inetd/inetd.c
731
free(tmp);
usr.sbin/ldapd/auth.c
213
unsigned char tmp[128];
usr.sbin/ldapd/auth.c
224
sz = b64_pton(stored_passwd + 5, tmp, sizeof(tmp));
usr.sbin/ldapd/auth.c
230
return (bcmp(md, tmp, SHA_DIGEST_LENGTH) == 0 ? 1 : 0);
usr.sbin/ldapd/auth.c
232
sz = b64_pton(stored_passwd + 6, tmp, sizeof(tmp));
usr.sbin/ldapd/auth.c
235
salt = tmp + SHA_DIGEST_LENGTH;
usr.sbin/ldapd/auth.c
240
return (bcmp(md, tmp, SHA_DIGEST_LENGTH) == 0 ? 1 : 0);
usr.sbin/ldomctl/config.c
2534
struct mblock *mblock, *tmp;
usr.sbin/ldomctl/config.c
2536
TAILQ_FOREACH_SAFE(mblock, &guest->mblock_list, link, tmp) {
usr.sbin/ldomctl/mdstore.c
598
struct frag *tmp;
usr.sbin/ldomctl/mdstore.c
600
TAILQ_FOREACH_SAFE(frag, &mdstore_frags, link, tmp) {
usr.sbin/ldomd/ldomd.c
357
struct frag *tmp;
usr.sbin/ldomd/ldomd.c
359
TAILQ_FOREACH_SAFE(frag, &free_frags, link, tmp) {
usr.sbin/ldpd/kroute.c
657
struct kroute_priority *kprio, *tmp;
usr.sbin/ldpd/kroute.c
682
TAILQ_FOREACH(tmp, &kp->priorities, entry)
usr.sbin/ldpd/kroute.c
683
if (tmp->priority > kprio->priority)
usr.sbin/ldpd/kroute.c
685
if (tmp)
usr.sbin/ldpd/kroute.c
686
TAILQ_INSERT_BEFORE(tmp, kprio, entry);
usr.sbin/lpd/lp_stty.c
130
struct key *kp, tmp;
usr.sbin/lpd/lp_stty.c
139
tmp.name = name;
usr.sbin/lpd/lp_stty.c
140
if (!(kp = (struct key *)bsearch(&tmp, keys,
usr.sbin/lpd/lp_stty.c
196
int tmp = 1;
usr.sbin/lpd/lp_stty.c
197
(void)ioctl(ip->fd, TIOCEXT, &tmp);
usr.sbin/lpd/lp_stty.c
199
int tmp = 0;
usr.sbin/lpd/lp_stty.c
200
(void)ioctl(ip->fd, TIOCEXT, &tmp);
usr.sbin/lpd/lp_stty.c
273
int tmp;
usr.sbin/lpd/lp_stty.c
275
tmp = TTYDISC;
usr.sbin/lpd/lp_stty.c
276
if (ioctl(0, TIOCSETD, &tmp) == -1)
usr.sbin/lpd/printer.c
597
char *argv[16], *prog, width[16], length[16], indent[16], tmp[512];
usr.sbin/lpd/printer.c
716
while ((n = read(efd, tmp, sizeof(tmp))) > 0)
usr.sbin/lpd/printer.c
717
(void)write(STDERR_FILENO, tmp, n);
usr.sbin/lpd/proc.c
359
void *tmp;
usr.sbin/lpd/proc.c
368
tmp = recallocarray(p->m_out.buf, p->m_out.alloc, alloc, 1);
usr.sbin/lpd/proc.c
369
if (tmp == NULL)
usr.sbin/lpd/proc.c
372
p->m_out.buf = tmp;
usr.sbin/lpr/lpd/key.c
108
tmp.name = name;
usr.sbin/lpr/lpd/key.c
109
if (!(kp = (struct key *)bsearch(&tmp, keys,
usr.sbin/lpr/lpd/key.c
166
int tmp = 1;
usr.sbin/lpr/lpd/key.c
167
(void)ioctl(ip->fd, TIOCEXT, &tmp);
usr.sbin/lpr/lpd/key.c
169
int tmp = 0;
usr.sbin/lpr/lpd/key.c
170
(void)ioctl(ip->fd, TIOCEXT, &tmp);
usr.sbin/lpr/lpd/key.c
243
int tmp;
usr.sbin/lpr/lpd/key.c
245
tmp = TTYDISC;
usr.sbin/lpr/lpd/key.c
246
if (ioctl(0, TIOCSETD, &tmp) < 0)
usr.sbin/lpr/lpd/key.c
99
struct key *kp, tmp;
usr.sbin/makefs/cd9660.c
1005
memcpy(tmp, (iter->o_name), numbts);
usr.sbin/makefs/cd9660.c
1012
snprintf(&tmp[numbts] , ISO_FILENAME_MAXLENGTH_WITH_PADDING - numbts, "%d", digit);
usr.sbin/makefs/cd9660.c
1019
tmp[numbts] = (*naming);
usr.sbin/makefs/cd9660.c
1024
tmp[numbts] = ';';
usr.sbin/makefs/cd9660.c
1025
tmp[numbts+1] = '1';
usr.sbin/makefs/cd9660.c
1026
tmp[numbts+2] = '\0';
usr.sbin/makefs/cd9660.c
1032
memcpy((iter->isoDirRecord->name), tmp, numbts + 3);
usr.sbin/makefs/cd9660.c
1038
free(tmp);
usr.sbin/makefs/cd9660.c
930
char *tmp;
usr.sbin/makefs/cd9660.c
940
tmp = emalloc(ISO_FILENAME_MAXLENGTH_WITH_PADDING);
usr.sbin/makefs/cd9660.c
994
memmove(&tmp[numbts],&tmp[dot],4);
usr.sbin/makefs/cd9660/cd9660_debug.c
138
volume_descriptor *tmp = diskStructure->firstVolumeDescriptor;
usr.sbin/makefs/cd9660/cd9660_debug.c
143
while (tmp != NULL) {
usr.sbin/makefs/cd9660/cd9660_debug.c
145
memcpy(temp, tmp->volumeDescriptorData + 1, 5);
usr.sbin/makefs/cd9660/cd9660_debug.c
148
tmp->sector, tmp->volumeDescriptorData[0], temp);
usr.sbin/makefs/cd9660/cd9660_debug.c
149
switch(tmp->volumeDescriptorData[0]) {
usr.sbin/makefs/cd9660/cd9660_debug.c
165
tmp = tmp->next;
usr.sbin/makefs/walk.c
312
uint64_t tmp;
usr.sbin/makefs/walk.c
347
tmp = entry->st.st_dev;
usr.sbin/makefs/walk.c
348
tmp <<= HTBITS>>1;
usr.sbin/makefs/walk.c
349
tmp |= entry->st.st_ino;
usr.sbin/makefs/walk.c
350
tmp *= HTCONST;
usr.sbin/makefs/walk.c
351
h = tmp >> (HTBITS - htshift);
usr.sbin/makefs/walk.c
352
h2 = 1 | ( tmp >> (HTBITS - (htshift<<1) - 1)); /* must be odd */
usr.sbin/map-mbone/mapper.c
336
Node *tmp = ifc_node->u.alias;
usr.sbin/map-mbone/mapper.c
339
ifc_node = tmp;
usr.sbin/map-mbone/mapper.c
477
Node *tmp = ifc_node->u.alias;
usr.sbin/map-mbone/mapper.c
480
ifc_node = tmp;
usr.sbin/mopd/common/device.c
100
strlcpy(p->if_name, tmp.if_name, IFNAME_SIZE);
usr.sbin/mopd/common/device.c
101
p->iopen = tmp.iopen;
usr.sbin/mopd/common/device.c
103
p->read = tmp.read;
usr.sbin/mopd/common/device.c
105
p->fd = tmp.fd;
usr.sbin/mopd/common/device.c
110
p->eaddr[0] = tmp.eaddr[0];
usr.sbin/mopd/common/device.c
111
p->eaddr[1] = tmp.eaddr[1];
usr.sbin/mopd/common/device.c
112
p->eaddr[2] = tmp.eaddr[2];
usr.sbin/mopd/common/device.c
113
p->eaddr[3] = tmp.eaddr[3];
usr.sbin/mopd/common/device.c
114
p->eaddr[4] = tmp.eaddr[4];
usr.sbin/mopd/common/device.c
115
p->eaddr[5] = tmp.eaddr[5];
usr.sbin/mopd/common/device.c
71
struct if_info *p, tmp;
usr.sbin/mopd/common/device.c
73
strncpy(tmp.if_name, ifname, sizeof(tmp.if_name) - 1);
usr.sbin/mopd/common/device.c
74
tmp.if_name[sizeof(tmp.if_name) - 1] = 0;
usr.sbin/mopd/common/device.c
75
tmp.iopen = pfInit;
usr.sbin/mopd/common/device.c
79
tmp.read = mopReadRC;
usr.sbin/mopd/common/device.c
80
tmp.fd = mopOpenRC(&tmp, trans);
usr.sbin/mopd/common/device.c
83
tmp.read = mopReadDL;
usr.sbin/mopd/common/device.c
84
tmp.fd = mopOpenDL(&tmp, trans);
usr.sbin/mopd/common/device.c
90
if (tmp.fd != -1) {
usr.sbin/mrouted/prune.c
217
u_int32_t tmp;
usr.sbin/mrouted/prune.c
257
tmp = htonl(gt->gt_prsent_timer);
usr.sbin/mrouted/prune.c
259
*p++ = ((char *)&(tmp))[i];
usr.sbin/mtree/misc.c
78
KEY *k, tmp;
usr.sbin/mtree/misc.c
81
tmp.name = name;
usr.sbin/mtree/misc.c
82
k = (KEY *)bsearch(&tmp, keylist, sizeof(keylist) / sizeof(KEY),
usr.sbin/nsd/dname.c
57
uint8_t tmp = label_offsets[i];
usr.sbin/nsd/dname.c
59
label_offsets[label_count - i - 1] = tmp;
usr.sbin/nsd/dname.c
680
uint8_t tmp = label_offsets[i];
usr.sbin/nsd/dname.c
682
label_offsets[label_count - i - 1] = tmp;
usr.sbin/nsd/simdzone/src/generic/ip6.h
102
uint8_t tmp[NS_IN6ADDRSZ], *tp, *endp, *colonp;
usr.sbin/nsd/simdzone/src/generic/ip6.h
109
memset((tp = tmp), '\0', NS_IN6ADDRSZ);
usr.sbin/nsd/simdzone/src/generic/ip6.h
179
memcpy(dst, tmp, NS_IN6ADDRSZ);
usr.sbin/nsd/simdzone/src/generic/ip6.h
49
uint8_t tmp[NS_INADDRSZ], *tp;
usr.sbin/nsd/simdzone/src/generic/ip6.h
54
*(tp = tmp) = 0;
usr.sbin/nsd/simdzone/src/generic/ip6.h
80
memcpy(dst, tmp, NS_INADDRSZ);
usr.sbin/ntpd/config.c
84
struct ntp_addr *h = hn, *tmp;
usr.sbin/ntpd/config.c
86
tmp = h;
usr.sbin/ntpd/config.c
88
free(tmp);
usr.sbin/ntpd/constraint.c
713
struct constraint *cstr, *tmp;
usr.sbin/ntpd/constraint.c
736
TAILQ_FOREACH(tmp, &conf->constraints, entry)
usr.sbin/ntpd/constraint.c
776
struct constraint *n, *tmp;
usr.sbin/ntpd/constraint.c
777
TAILQ_FOREACH_SAFE(n, &conf->constraints, entry, tmp) {
usr.sbin/ntpd/ntp.c
549
struct ntp_peer *peer, *npeer, *tmp;
usr.sbin/ntpd/ntp.c
585
entry, tmp) {
usr.sbin/ospf6d/kroute.c
699
struct kroute_node *kn, *tmp;
usr.sbin/ospf6d/kroute.c
707
tmp = RB_PREV(kroute_tree, &krt, kn);
usr.sbin/ospf6d/kroute.c
708
while (tmp) {
usr.sbin/ospf6d/kroute.c
709
if (kroute_compare(&s, tmp) == 0)
usr.sbin/ospf6d/kroute.c
710
kn = tmp;
usr.sbin/ospf6d/kroute.c
713
tmp = RB_PREV(kroute_tree, &krt, kn);
usr.sbin/ospfd/kroute.c
713
struct kroute_node *kn, *tmp;
usr.sbin/ospfd/kroute.c
721
tmp = RB_PREV(kroute_tree, &krt, kn);
usr.sbin/ospfd/kroute.c
722
while (tmp) {
usr.sbin/ospfd/kroute.c
723
if (kroute_compare(&s, tmp) == 0)
usr.sbin/ospfd/kroute.c
724
kn = tmp;
usr.sbin/ospfd/kroute.c
727
tmp = RB_PREV(kroute_tree, &krt, kn);
usr.sbin/ospfd/rde.c
1246
u_int32_t tmp = ntohl(oan->ls_id);
usr.sbin/ospfd/rde.c
1247
oan->ls_id = htonl(tmp - 1);
usr.sbin/procmap/procmap.c
984
struct namecache n, *tmp;
usr.sbin/procmap/procmap.c
989
tmp = TAILQ_FIRST(&nchead);
usr.sbin/procmap/procmap.c
990
while (tmp != NULL) {
usr.sbin/procmap/procmap.c
991
_KDEREF(kd, (u_long)tmp, &n, sizeof(n));
usr.sbin/procmap/procmap.c
999
tmp = TAILQ_NEXT(&n, nc_lru);
usr.sbin/rbootd/utils.c
75
struct tm *tmp;
usr.sbin/rbootd/utils.c
87
tmp = localtime(&tim);
usr.sbin/rbootd/utils.c
88
fprintf(DbgFp, "%02d:%02d:%02d.%06ld ", tmp->tm_hour, tmp->tm_min,
usr.sbin/rbootd/utils.c
89
tmp->tm_sec, rconn->tstamp.tv_usec);
usr.sbin/relayd/relayd.c
1474
char *tmp;
usr.sbin/relayd/relayd.c
1477
if ((tmp = calloc(1, len)) == NULL) {
usr.sbin/relayd/relayd.c
1484
if ((strlcat(tmp, p, len) >= len) ||
usr.sbin/relayd/relayd.c
1485
(strlcat(tmp, repl, len) >= len)) {
usr.sbin/relayd/relayd.c
1487
free(tmp);
usr.sbin/relayd/relayd.c
1493
if (strlcat(tmp, p, len) >= len) {
usr.sbin/relayd/relayd.c
1495
free(tmp);
usr.sbin/relayd/relayd.c
1498
(void)strlcpy(label, tmp, len); /* always fits */
usr.sbin/relayd/relayd.c
1499
free(tmp);
usr.sbin/ripd/kroute.c
416
struct kroute_node s, *kn, *tmp;
usr.sbin/ripd/kroute.c
424
tmp = RB_PREV(kroute_tree, &krt, kn);
usr.sbin/ripd/kroute.c
425
while (tmp) {
usr.sbin/ripd/kroute.c
426
if (kroute_compare(&s, tmp) == 0)
usr.sbin/ripd/kroute.c
427
kn = tmp;
usr.sbin/ripd/kroute.c
430
tmp = RB_PREV(kroute_tree, &krt, kn);
usr.sbin/sasyncd/monitor.c
142
u_int8_t tmp;
usr.sbin/sasyncd/monitor.c
145
while (m_read(m_state.s, &tmp, 1) > 0)
usr.sbin/sasyncd/timer.c
114
struct timespec now, tmp;
usr.sbin/sasyncd/timer.c
127
tmp.tv_sec = when;
usr.sbin/sasyncd/timer.c
128
tmp.tv_nsec = 0;
usr.sbin/sasyncd/timer.c
130
timespecadd(&now, &tmp, &new->expire);
usr.sbin/smtpd/expand.c
259
char tmp[64];
usr.sbin/smtpd/expand.c
293
(void)snprintf(tmp, sizeof(tmp), "[parent=%p", e->parent);
usr.sbin/smtpd/expand.c
294
if (strlcat(buffer, tmp, sizeof buffer) >= sizeof buffer)
usr.sbin/smtpd/expand.c
297
(void)snprintf(tmp, sizeof(tmp), ", rule=%p", e->rule);
usr.sbin/smtpd/expand.c
298
if (strlcat(buffer, tmp, sizeof buffer) >= sizeof buffer)
usr.sbin/smtpd/expand.c
302
(void)snprintf(tmp, sizeof(tmp), ", dispatcher=%p", e->rule->dispatcher);
usr.sbin/smtpd/expand.c
303
if (strlcat(buffer, tmp, sizeof buffer) >= sizeof buffer)
usr.sbin/smtpd/mail.maildir.c
121
char tmp[PATH_MAX];
usr.sbin/smtpd/mail.maildir.c
178
(void)snprintf(tmp, sizeof tmp, "%s/tmp/%s", dirname, filename);
usr.sbin/smtpd/mail.maildir.c
180
fd = open(tmp, O_CREAT | O_EXCL | O_WRONLY, 0600);
usr.sbin/smtpd/mail.maildir.c
209
if (rename(tmp, new) == -1)
usr.sbin/smtpd/mda_variables.c
106
if (snprintf(tmp, sizeof tmp, "%s@%s",
usr.sbin/smtpd/mda_variables.c
107
dlv->sender.user, dlv->sender.domain) >= (int)sizeof tmp)
usr.sbin/smtpd/mda_variables.c
109
if (strcmp(tmp, "@") == 0)
usr.sbin/smtpd/mda_variables.c
110
(void)strlcpy(tmp, "", sizeof tmp);
usr.sbin/smtpd/mda_variables.c
111
string = tmp;
usr.sbin/smtpd/mda_variables.c
114
if (snprintf(tmp, sizeof tmp, "%s@%s",
usr.sbin/smtpd/mda_variables.c
115
dlv->rcpt.user, dlv->rcpt.domain) >= (int)sizeof tmp)
usr.sbin/smtpd/mda_variables.c
117
if (strcmp(tmp, "@") == 0)
usr.sbin/smtpd/mda_variables.c
118
(void)strlcpy(tmp, "", sizeof tmp);
usr.sbin/smtpd/mda_variables.c
119
string = tmp;
usr.sbin/smtpd/mda_variables.c
122
if (snprintf(tmp, sizeof tmp, "%s@%s",
usr.sbin/smtpd/mda_variables.c
123
dlv->dest.user, dlv->dest.domain) >= (int)sizeof tmp)
usr.sbin/smtpd/mda_variables.c
125
if (strcmp(tmp, "@") == 0)
usr.sbin/smtpd/mda_variables.c
126
(void)strlcpy(tmp, "", sizeof tmp);
usr.sbin/smtpd/mda_variables.c
127
string = tmp;
usr.sbin/smtpd/mda_variables.c
152
if (snprintf(tmp, sizeof tmp, "%s@%s",
usr.sbin/smtpd/mda_variables.c
153
dlv->sender.user, dlv->sender.domain) >= (int)sizeof tmp)
usr.sbin/smtpd/mda_variables.c
155
if (strcmp(tmp, "@") == 0)
usr.sbin/smtpd/mda_variables.c
156
(void)strlcpy(tmp, "MAILER-DAEMON", sizeof tmp);
usr.sbin/smtpd/mda_variables.c
157
string = tmp;
usr.sbin/smtpd/mda_variables.c
162
if (string != tmp) {
usr.sbin/smtpd/mda_variables.c
165
if (strlcpy(tmp, string, sizeof tmp) >= sizeof tmp)
usr.sbin/smtpd/mda_variables.c
167
string = tmp;
usr.sbin/smtpd/mda_variables.c
181
if (!token_modifiers[i].f(tmp, sizeof tmp))
usr.sbin/smtpd/mda_variables.c
192
for (i = 0; (size_t)i < strlen(tmp); ++i)
usr.sbin/smtpd/mda_variables.c
193
if (strchr(MAILADDR_ESCAPE, tmp[i]))
usr.sbin/smtpd/mda_variables.c
194
tmp[i] = ':';
usr.sbin/smtpd/mda_variables.c
325
char tmp[EXPAND_BUFFER];
usr.sbin/smtpd/mda_variables.c
327
if (!lowercase(tmp, buf, sizeof tmp))
usr.sbin/smtpd/mda_variables.c
329
if (strlcpy(buf, tmp, len) >= len)
usr.sbin/smtpd/mda_variables.c
337
char tmp[EXPAND_BUFFER];
usr.sbin/smtpd/mda_variables.c
339
if (!uppercase(tmp, buf, sizeof tmp))
usr.sbin/smtpd/mda_variables.c
341
if (strlcpy(buf, tmp, len) >= len)
usr.sbin/smtpd/mda_variables.c
53
char tmp[EXPAND_BUFFER];
usr.sbin/smtpd/mproc.c
278
void *tmp;
usr.sbin/smtpd/mproc.c
295
tmp = recallocarray(p->m_buf, p->m_alloc, alloc, 1);
usr.sbin/smtpd/mproc.c
296
if (tmp == NULL)
usr.sbin/smtpd/mproc.c
299
p->m_buf = tmp;
usr.sbin/smtpd/mproc.c
623
char *tmp;
usr.sbin/smtpd/mproc.c
632
if ((tmp = strdup(value)) == NULL)
usr.sbin/smtpd/mproc.c
634
dict_set(d, key, tmp);
usr.sbin/smtpd/mta.c
1918
char tmp[32];
usr.sbin/smtpd/mta.c
1925
(void)snprintf(tmp, sizeof tmp, "port=%d", (int)relay->port);
usr.sbin/smtpd/mta.c
1926
(void)strlcat(buf, tmp, sizeof buf);
usr.sbin/smtpd/parser.c
101
tmp->type = P_ADDR;
usr.sbin/smtpd/parser.c
103
tmp->type = P_TOKEN;
usr.sbin/smtpd/parser.c
104
tmp->token = strdup(argv[i]);
usr.sbin/smtpd/parser.c
105
tmp->parent = node;
usr.sbin/smtpd/parser.c
106
TAILQ_INSERT_TAIL(&node->children, tmp, entry);
usr.sbin/smtpd/parser.c
107
node = tmp;
usr.sbin/smtpd/parser.c
177
struct node *node, *tmp, *stack[ARGVMAX], *best;
usr.sbin/smtpd/parser.c
184
TAILQ_FOREACH(tmp, &node->children, entry) {
usr.sbin/smtpd/parser.c
185
if (cmd_check(argv[i], tmp, ¶m[np])) {
usr.sbin/smtpd/parser.c
186
stack[i] = tmp;
usr.sbin/smtpd/parser.c
187
node = tmp;
usr.sbin/smtpd/parser.c
194
if (tmp == NULL) {
usr.sbin/smtpd/parser.c
196
TAILQ_FOREACH(tmp, &node->children, entry) {
usr.sbin/smtpd/parser.c
197
if (tmp->type != P_TOKEN)
usr.sbin/smtpd/parser.c
199
if (strstr(tmp->token, argv[i]) != tmp->token)
usr.sbin/smtpd/parser.c
203
best = tmp;
usr.sbin/smtpd/parser.c
227
TAILQ_FOREACH(tmp, &node->children, entry) {
usr.sbin/smtpd/parser.c
230
fprintf(stderr, "%s%s\n", i?" ":"", tmp->token);
usr.sbin/smtpd/parser.c
57
struct node *node, *tmp;
usr.sbin/smtpd/parser.c
81
TAILQ_FOREACH(tmp, &node->children, entry) {
usr.sbin/smtpd/parser.c
82
if (!strcmp(tmp->token, argv[i])) {
usr.sbin/smtpd/parser.c
83
node = tmp;
usr.sbin/smtpd/parser.c
87
if (tmp == NULL) {
usr.sbin/smtpd/parser.c
88
tmp = calloc(1, sizeof (*tmp));
usr.sbin/smtpd/parser.c
89
TAILQ_INIT(&tmp->children);
usr.sbin/smtpd/parser.c
91
tmp->type = P_STR;
usr.sbin/smtpd/parser.c
93
tmp->type = P_INT;
usr.sbin/smtpd/parser.c
95
tmp->type = P_MSGID;
usr.sbin/smtpd/parser.c
97
tmp->type = P_EVPID;
usr.sbin/smtpd/parser.c
99
tmp->type = P_ROUTEID;
usr.sbin/smtpd/queue_fs.c
312
char *tmp;
usr.sbin/smtpd/queue_fs.c
342
tmp = NULL;
usr.sbin/smtpd/queue_fs.c
343
*evpid = strtoull(dp->d_name, &tmp, 16);
usr.sbin/smtpd/queue_fs.c
344
if (tmp && *tmp != '\0') {
usr.sbin/smtpd/queue_fs.c
580
char *tmp;
usr.sbin/smtpd/queue_fs.c
612
tmp = NULL;
usr.sbin/smtpd/queue_fs.c
613
*evpid = strtoull(e->fts_name, &tmp, 16);
usr.sbin/smtpd/queue_fs.c
614
if (tmp && *tmp != '\0') {
usr.sbin/smtpd/queue_ram.c
249
void *tmp;
usr.sbin/smtpd/queue_ram.c
258
tmp = malloc(len);
usr.sbin/smtpd/queue_ram.c
259
if (tmp == NULL) {
usr.sbin/smtpd/queue_ram.c
263
memmove(tmp, buf, len);
usr.sbin/smtpd/queue_ram.c
266
evp->buf = tmp;
usr.sbin/smtpd/smtp_client.c
773
char *tmp;
usr.sbin/smtpd/smtp_client.c
811
tmp = realloc(proto->reply, len);
usr.sbin/smtpd/smtp_client.c
812
if (tmp == NULL)
usr.sbin/smtpd/smtp_client.c
815
tmp[0] = '\0';
usr.sbin/smtpd/smtp_client.c
817
proto->reply = tmp;
usr.sbin/smtpd/smtp_session.c
1514
char tmp[SMTP_LINE_MAX];
usr.sbin/smtpd/smtp_session.c
1517
(void)strlcpy(tmp, args, sizeof tmp);
usr.sbin/smtpd/smtp_session.c
1518
copy = tmp;
usr.sbin/smtpd/smtp_session.c
1567
char tmp[SMTP_LINE_MAX];
usr.sbin/smtpd/smtp_session.c
1569
(void)strlcpy(tmp, args, sizeof tmp);
usr.sbin/smtpd/smtp_session.c
1570
copy = tmp;
usr.sbin/smtpd/smtp_session.c
1798
char tmp[SMTP_LINE_MAX];
usr.sbin/smtpd/smtp_session.c
1801
(void)strlcpy(tmp, args, sizeof tmp);
usr.sbin/smtpd/smtp_session.c
1803
method = tmp;
usr.sbin/smtpd/smtp_session.c
1804
eom = strchr(tmp, ' ');
usr.sbin/smtpd/smtp_session.c
1806
eom = strchr(tmp, '\t');
usr.sbin/smtpd/smtp_session.c
1832
char tmp[SMTP_LINE_MAX];
usr.sbin/smtpd/smtp_session.c
1834
(void)strlcpy(tmp, args, sizeof tmp);
usr.sbin/smtpd/smtp_session.c
1835
copy = tmp;
usr.sbin/smtpd/smtp_session.c
2100
char buf[LINE_MAX*2], tmp[LINE_MAX*2];
usr.sbin/smtpd/smtp_session.c
2177
strnvis(tmp, s->cmd, sizeof tmp, VIS_SAFE | VIS_CSTYLE);
usr.sbin/smtpd/smtp_session.c
2181
s->id, tmp, n, buf);
usr.sbin/smtpd/smtp_session.c
2343
char tmp[SMTP_LINE_MAX];
usr.sbin/smtpd/smtp_session.c
2345
(void)strlcpy(tmp, line, sizeof tmp);
usr.sbin/smtpd/smtp_session.c
2346
copy = tmp;
usr.sbin/smtpd/smtp_session.c
2424
char tmp[SMTP_LINE_MAX];
usr.sbin/smtpd/smtp_session.c
2426
(void)strlcpy(tmp, line, sizeof tmp);
usr.sbin/smtpd/smtp_session.c
2427
copy = tmp;
usr.sbin/smtpd/smtp_session.c
697
char tmp[SMTP_LINE_MAX];
usr.sbin/smtpd/smtp_session.c
740
tmp[0] = '\0';
usr.sbin/smtpd/smtp_session.c
742
(void)strlcpy(tmp, s->tx->evp.rcpt.user, sizeof tmp);
usr.sbin/smtpd/smtp_session.c
744
(void)strlcat(tmp, "@", sizeof tmp);
usr.sbin/smtpd/smtp_session.c
745
(void)strlcat(tmp, s->tx->evp.rcpt.domain,
usr.sbin/smtpd/smtp_session.c
746
sizeof tmp);
usr.sbin/smtpd/smtp_session.c
754
smtp_reply(s, "%s: <%s>", line, tmp);
usr.sbin/smtpd/smtp_session.c
757
smtp_reply(s, "%s: <%s>", line, tmp);
usr.sbin/smtpd/smtpctl.c
404
static uint64_t *evpids = NULL, *tmp;
usr.sbin/smtpd/smtpctl.c
413
tmp = recallocarray(evpids, alloc, tmpalloc,
usr.sbin/smtpd/smtpctl.c
415
if (tmp == NULL)
usr.sbin/smtpd/smtpctl.c
417
evpids = tmp;
usr.sbin/smtpd/smtpctl.c
750
char *tmp;
usr.sbin/smtpd/smtpctl.c
769
tmp = NULL;
usr.sbin/smtpd/smtpctl.c
770
evpid = strtoull(ftse->fts_name, &tmp, 16);
usr.sbin/smtpd/smtpctl.c
771
if (tmp && *tmp != '\0')
usr.sbin/smtpd/smtpd.c
1647
char *envp[2], *p = NULL, *tmp;
usr.sbin/smtpd/smtpd.c
1725
while ((tmp = strsep(&p, "|")) != NULL)
usr.sbin/smtpd/smtpd.c
1726
addargs(&args, "%s", tmp);
usr.sbin/smtpd/smtpd.c
418
char *tmp;
usr.sbin/smtpd/smtpd.c
419
if (asprintf(&tmp,
usr.sbin/smtpd/smtpd.c
422
cause = tmp;
usr.sbin/smtpd/srs.c
103
if (ret == -1 || ret >= (int)sizeof tmp)
usr.sbin/smtpd/srs.c
107
base64_encode_rfc3548(srs_hash(env->sc_srs_key, tmp), SHA_DIGEST_LENGTH,
usr.sbin/smtpd/srs.c
112
md[0], md[1], md[2], md[3], tmp);
usr.sbin/smtpd/srs.c
123
char tmp[SMTPD_MAXMAILADDRSIZE];
usr.sbin/smtpd/srs.c
133
ret = snprintf(tmp, sizeof tmp, "%s==%s@%s",
usr.sbin/smtpd/srs.c
135
if (ret == -1 || ret >= (int)sizeof tmp)
usr.sbin/smtpd/srs.c
139
base64_encode_rfc3548(srs_hash(env->sc_srs_key, tmp), SHA_DIGEST_LENGTH,
usr.sbin/smtpd/srs.c
144
md[0], md[1], md[2], md[3], tmp);
usr.sbin/smtpd/srs.c
155
char tmp[SMTPD_MAXMAILADDRSIZE];
usr.sbin/smtpd/srs.c
165
ret = snprintf(tmp, sizeof tmp, "%s@%s", maddr.user, rcpt_domain);
usr.sbin/smtpd/srs.c
166
if (ret == -1 || ret >= (int)sizeof tmp)
usr.sbin/smtpd/srs.c
172
if (strlen(tmp) < 5)
usr.sbin/smtpd/srs.c
174
if (tmp[4] != '=' && tmp[4] != '+' && tmp[4] != '-')
usr.sbin/smtpd/srs.c
178
base64_encode_rfc3548(srs_hash(env->sc_srs_key, tmp + 5), SHA_DIGEST_LENGTH,
usr.sbin/smtpd/srs.c
183
md[0], md[1], md[2], md[3], tmp + 5);
usr.sbin/smtpd/srs.c
85
char tmp[SMTPD_MAXMAILADDRSIZE];
usr.sbin/smtpd/srs.c
99
ret = snprintf(tmp, sizeof tmp, "%c%c=%s=%s@%s",
usr.sbin/smtpd/util.c
609
char **tmp;
usr.sbin/smtpd/util.c
624
tmp = reallocarray(args->list, nalloc, sizeof(char *));
usr.sbin/smtpd/util.c
625
if (tmp == NULL)
usr.sbin/smtpd/util.c
627
args->list = tmp;
usr.sbin/snmpd/application.c
304
struct appl_agentcap *cap, *tmp;
usr.sbin/snmpd/application.c
322
TAILQ_FOREACH_SAFE(cap, &(ctx->ac_agentcaps), aa_entry, tmp) {
usr.sbin/snmpd/application_blocklist.c
56
struct appl_varbind *tmp;
usr.sbin/snmpd/application_blocklist.c
60
if ((tmp = recallocarray(response, responsesz, nvarbind,
usr.sbin/snmpd/application_blocklist.c
66
response = tmp;
usr.sbin/tcpdump/pf_print_state.c
324
u_int32_t tmp;
usr.sbin/tcpdump/pf_print_state.c
331
tmp = ntohl(m->addr32[j]);
usr.sbin/tcpdump/pf_print_state.c
332
for (i = 31; tmp & (1 << i); --i)
usr.sbin/tcpdump/pfctl_osfp.c
1010
snprintf(tmp, sizeof(tmp), "%d", fp->fp_wsize);
usr.sbin/tcpdump/pfctl_osfp.c
1011
strlcat(buf, tmp, sizeof(buf));
usr.sbin/tcpdump/pfctl_osfp.c
1015
snprintf(tmp, sizeof(tmp), "%d", fp->fp_ttl);
usr.sbin/tcpdump/pfctl_osfp.c
1016
strlcat(buf, tmp, sizeof(buf));
usr.sbin/tcpdump/pfctl_osfp.c
1030
snprintf(tmp, sizeof(tmp), "%d", fp->fp_psize);
usr.sbin/tcpdump/pfctl_osfp.c
1031
strlcat(buf, tmp, sizeof(buf));
usr.sbin/tcpdump/pfctl_osfp.c
1059
snprintf(tmp, sizeof(tmp), "%d", fp->fp_mss);
usr.sbin/tcpdump/pfctl_osfp.c
1060
strlcat(buf, tmp, sizeof(buf));
usr.sbin/tcpdump/pfctl_osfp.c
1070
snprintf(tmp, sizeof(tmp), "%d", fp->fp_wscale);
usr.sbin/tcpdump/pfctl_osfp.c
1071
strlcat(buf, tmp, sizeof(buf));
usr.sbin/tcpdump/pfctl_osfp.c
1088
snprintf(tmp, sizeof(tmp), "TcpOpts %d 0x%llx", fp->fp_optcnt,
usr.sbin/tcpdump/pfctl_osfp.c
1090
strlcat(buf, tmp, sizeof(buf));
usr.sbin/tcpdump/pfctl_osfp.c
997
char tmp[32];
usr.sbin/tcpdump/print-802_11.c
1439
u_int16_t tmp;
usr.sbin/tcpdump/print-802_11.c
1561
bcopy(t, &tmp, sizeof(u_int16_t));
usr.sbin/tcpdump/print-802_11.c
1562
printf(", quality %u", letoh16(tmp));
usr.sbin/tcpdump/print-802_11.c
1570
bcopy(t, &tmp, sizeof(u_int16_t));
usr.sbin/tcpdump/print-802_11.c
1571
printf(", txatt %u", letoh16(tmp));
usr.sbin/tcpdump/print-802_11.c
1579
bcopy(t, &tmp, sizeof(u_int16_t));
usr.sbin/tcpdump/print-802_11.c
1580
printf(", txatt %udB", letoh16(tmp));
usr.sbin/tokeninit/tokeninit.c
193
unsigned int tmp[8];
usr.sbin/tokeninit/tokeninit.c
197
&tmp[0], &tmp[1], &tmp[2], &tmp[3],
usr.sbin/tokeninit/tokeninit.c
198
&tmp[4], &tmp[5], &tmp[6], &tmp[7])) != 8)
usr.sbin/tokeninit/tokeninit.c
202
&tmp[0], &tmp[1], &tmp[2], &tmp[3],
usr.sbin/tokeninit/tokeninit.c
203
&tmp[4], &tmp[5], &tmp[6], &tmp[7])) != 8)
usr.sbin/tokeninit/tokeninit.c
207
secret[i] = tmp[i] & 0xff;
usr.sbin/unbound/services/outside_network.c
1024
sldns_buffer tmp;
usr.sbin/unbound/services/outside_network.c
1025
sldns_buffer_init_frm_data(&tmp, w->pkt, w->pkt_len);
usr.sbin/unbound/services/outside_network.c
1028
w->sq->zonelen, &tmp);
usr.sbin/unbound/services/outside_network.c
2543
sldns_buffer tmp;
usr.sbin/unbound/services/outside_network.c
2544
sldns_buffer_init_frm_data(&tmp, w->pkt, w->pkt_len);
usr.sbin/unbound/services/outside_network.c
2547
sq->zonelen, &tmp);
usr.sbin/unbound/smallapp/unbound-anchor.c
1092
BIO* tmp = do_chunked_read(ssl);
usr.sbin/unbound/smallapp/unbound-anchor.c
1095
if(!tmp) {
usr.sbin/unbound/smallapp/unbound-anchor.c
1099
l = (size_t)BIO_get_mem_data(tmp, &d);
usr.sbin/unbound/smallapp/unbound-anchor.c
1112
BIO_free(tmp);
usr.sbin/vmd/virtio.c
1262
struct virtio_dev *dev, *tmp;
usr.sbin/vmd/virtio.c
1291
SLIST_FOREACH_SAFE(dev, &virtio_devs, dev_next, tmp) {
usr.sbin/ypldap/entries.c
45
char *tmp;
usr.sbin/ypldap/entries.c
83
tmp = ue->ue_netid_line;
usr.sbin/ypldap/entries.c
84
ue->ue_netid_line = strdup(tmp);
usr.sbin/ypldap/entries.c
88
free(tmp);
usr.sbin/ypserv/revnetgroup/hash.c
175
struct grouplist *tmp,*p;
usr.sbin/ypserv/revnetgroup/hash.c
181
tmp = malloc(sizeof(struct grouplist));
usr.sbin/ypserv/revnetgroup/hash.c
182
tmp->groupname = strdup(data);
usr.sbin/ypserv/revnetgroup/hash.c
183
tmp->next = NULL;
usr.sbin/ypserv/revnetgroup/hash.c
191
free(tmp->groupname);
usr.sbin/ypserv/revnetgroup/hash.c
192
free(tmp);
usr.sbin/ypserv/revnetgroup/hash.c
197
tmp->next = cur->groups;
usr.sbin/ypserv/revnetgroup/hash.c
198
cur->groups = tmp;
usr.sbin/ypserv/revnetgroup/hash.c
208
new->groups = tmp;
usr.sbin/ypserv/revnetgroup/revnetgroup.c
174
struct grouplist *tmp;
usr.sbin/ypserv/revnetgroup/revnetgroup.c
176
tmp = mcur->groups;
usr.sbin/ypserv/revnetgroup/revnetgroup.c
177
while (tmp) {
usr.sbin/ypserv/revnetgroup/revnetgroup.c
178
printf ("%s", tmp->groupname);
usr.sbin/ypserv/revnetgroup/revnetgroup.c
179
tmp = tmp->next;
usr.sbin/ypserv/revnetgroup/revnetgroup.c
180
if (tmp)
usr.sbin/zdump/zdump.c
124
struct tm tm, newtm, *tmp, *newtmp;
usr.sbin/zdump/zdump.c
249
tmp = localtime(&t);
usr.sbin/zdump/zdump.c
250
if (tmp != NULL) {
usr.sbin/zdump/zdump.c
251
tm = *tmp;
usr.sbin/zdump/zdump.c
263
if ((tmp == NULL || newtmp == NULL) ? (tmp != newtmp) :
usr.sbin/zdump/zdump.c
276
tmp = newtmp;
usr.sbin/zdump/zdump.c
340
struct tm tm, *tmp;
usr.sbin/zdump/zdump.c
358
tmp = localtime(&t);
usr.sbin/zdump/zdump.c
359
if (tmp != NULL)
usr.sbin/zdump/zdump.c
360
tm = *tmp;
usr.sbin/zdump/zdump.c
361
if ((lotmp == NULL || tmp == NULL) ? (lotmp == tmp) :
usr.sbin/zdump/zdump.c
367
lotmp = tmp;
usr.sbin/zdump/zdump.c
404
struct tm *tmp;
usr.sbin/zdump/zdump.c
408
tmp = gmtime(&t);
usr.sbin/zdump/zdump.c
409
if (tmp == NULL) {
usr.sbin/zdump/zdump.c
412
dumptime(tmp);
usr.sbin/zdump/zdump.c
417
tmp = localtime(&t);
usr.sbin/zdump/zdump.c
418
dumptime(tmp);
usr.sbin/zdump/zdump.c
419
if (tmp != NULL) {
usr.sbin/zdump/zdump.c
420
if (*abbr(tmp) != '\0')
usr.sbin/zdump/zdump.c
421
printf(" %s", abbr(tmp));
usr.sbin/zdump/zdump.c
423
printf(" isdst=%d", tmp->tm_isdst);
usr.sbin/zdump/zdump.c
425
printf(" gmtoff=%ld", tmp->TM_GMTOFF);
usr.sbin/zdump/zdump.c
430
if (tmp != NULL && *abbr(tmp) != '\0')
usr.sbin/zdump/zdump.c
431
abbrok(abbr(tmp), zone);
usr.sbin/zdump/zdump.c
435
abbr(struct tm *tmp)
usr.sbin/zdump/zdump.c
440
if (tmp->tm_isdst != 0 && tmp->tm_isdst != 1)
usr.sbin/zdump/zdump.c
442
result = tzname[tmp->tm_isdst];
usr.sbin/zdump/zdump.c
71
static char *abbr(struct tm *tmp);
usr.sbin/zdump/zdump.c
74
static void dumptime(const struct tm *tmp);
