#ifndef __PGTREG_H__
#define __PGTREG_H__
#define PGT_TX_LIST_CNT 32
#define PGT_RX_LIST_CNT 8
#define PGT_FRAG_SIZE 1536
#define PGT_DIRECT_MEMORY_OFFSET 0x1000
#define PGT_DIRECT_MEMORY_SIZE 0x1000
#define PGT_FIRMWARE_INTERNAL_OFFSET 0x20000
#define PGT_WRITEIO_DELAY 10
#define PGT_RESET_DELAY 50000
#define PGT_REG_DEV_INT 0x0000
#define PGT_DEV_INT_RESET 0x00000001
#define PGT_DEV_INT_UPDATE 0x00000002
#define PGT_DEV_INT_WAKEUP 0x00000008
#define PGT_DEV_INT_SLEEP 0x00000010
#define PGT_REG_INT_STAT 0x0010
#define PGT_INT_STAT_UPDATE 0x00000002
#define PGT_INT_STAT_INIT 0x00000004
#define PGT_INT_STAT_WAKEUP 0x00000008
#define PGT_INT_STAT_SLEEP 0x00000010
#define PGT_INT_STAT_UNKNOWN0 0x00004000
#define PGT_INT_STAT_UNKNOWN1 0x80000000
#define PGT_INT_STAT_SOURCES 0x8000401e
#define PGT_REG_INT_ACK 0x0014
#define PGT_REG_INT_EN 0x0018
#define PGT_REG_CTRL_BLK_BASE 0x0020
#define PGT_REG_GEN_PURP_COM 0x0024
#define PGT_REG_DIR_MEM_BASE 0x0030
#define PGT_REG_CTRL_STAT 0x0078
#define PGT_CTRL_STAT_SLEEPMODE 0x00000200
#define PGT_CTRL_STAT_CLOCKRUN 0x00800000
#define PGT_CTRL_STAT_RESET 0x10000000
#define PGT_CTRL_STAT_RAMBOOT 0x20000000
#define PGT_CTRL_STAT_STARTHALTED 0x40000000
#define PGT_CTRL_STAT_HOST_OVERRIDE 0x80000000
enum pgt_queue {
PGT_QUEUE_DATA_LOW_RX = 0,
PGT_QUEUE_DATA_LOW_TX = 1,
PGT_QUEUE_DATA_HIGH_RX = 2,
PGT_QUEUE_DATA_HIGH_TX = 3,
PGT_QUEUE_MGMT_RX = 4,
PGT_QUEUE_MGMT_TX = 5
};
#define PGT_QUEUE_COUNT 6
#define PGT_QUEUE_DATA_RX_SIZE 8
#define PGT_QUEUE_DATA_TX_SIZE 32
#define PGT_QUEUE_MGMT_SIZE 4
#define PGT_QUEUE_FULL_THRESHOLD 8
struct pgt_frag {
uint32_t pf_addr;
uint16_t pf_size;
uint16_t pf_flags;
#define PF_FLAG_MF 0x0001
};
struct pgt_control_block {
uint32_t pcb_driver_curfrag[PGT_QUEUE_COUNT];
uint32_t pcb_device_curfrag[PGT_QUEUE_COUNT];
struct pgt_frag pcb_data_low_rx[PGT_QUEUE_DATA_RX_SIZE];
struct pgt_frag pcb_data_low_tx[PGT_QUEUE_DATA_TX_SIZE];
struct pgt_frag pcb_data_high_rx[PGT_QUEUE_DATA_RX_SIZE];
struct pgt_frag pcb_data_high_tx[PGT_QUEUE_DATA_TX_SIZE];
struct pgt_frag pcb_mgmt_rx[PGT_QUEUE_MGMT_SIZE];
struct pgt_frag pcb_mgmt_tx[PGT_QUEUE_MGMT_SIZE];
uint32_t pcb_padding;
};
enum pgt_mgmt_operation {
PMF_OP_GET = 0,
PMF_OP_SET = 1,
PMF_OP_RESPONSE = 2,
PMF_OP_ERROR = 3,
PMF_OP_TRAP = 4
};
struct pgt_mgmt_frame {
uint8_t pmf_version;
#define PMF_VER 0x01
uint8_t pmf_operation;
uint32_t pmf_oid;
uint8_t pmf_device;
#define PMF_DEV 0x00
uint8_t pmf_flags;
#define PMF_FLAG_APP 0x01
#define PMF_FLAG_LE 0x02
#define PMF_FLAG_VALID (PMF_FLAG_APP | PMF_FLAG_LE)
uint32_t pmf_size;
} __packed;
struct pgt_rx_header {
uint16_t pra_unknown0;
uint16_t pra_length;
uint32_t pra_clock;
uint8_t pra_flags;
#define PRA_FLAG_BAD 0x01
uint8_t pra_unknown1;
uint8_t pra_rate;
uint8_t pra_unknown2;
uint16_t pra_frequency;
uint16_t pra_unknown3;
uint8_t pra_rssi;
uint8_t pra_pad[3];
} __packed;
struct pgt_rx_annex {
uint8_t pra_ether_dhost[ETHER_ADDR_LEN];
uint8_t pra_ether_shost[ETHER_ADDR_LEN];
struct pgt_rx_header pra_header;
uint16_t pra_ether_type;
} __packed;
enum pgt_oid {
PGT_OID_MAC_ADDRESS = 0x00000000,
PGT_OID_LINK_STATE = 0x00000001,
PGT_OID_BSS_TYPE = 0x10000000,
#define PGT_BSS_TYPE_NONE 0
#define PGT_BSS_TYPE_STA 1
#define PGT_BSS_TYPE_IBSS 2
#define PGT_BSS_TYPE_ANY 3
PGT_OID_BSSID = 0x10000001,
PGT_OID_SSID = 0x10000002,
PGT_OID_COUNTRY = 0x10000005,
#define PGT_COUNTRY_USA 0
PGT_OID_SSID_OVERRIDE = 0x10000006,
PGT_OID_AUTH_MODE = 0x12000000,
#define PGT_AUTH_MODE_NONE 0
#define PGT_AUTH_MODE_OPEN 1
#define PGT_AUTH_MODE_SHARED 2
#define PGT_AUTH_MODE_BOTH 3
PGT_OID_PRIVACY_INVOKED = 0x12000001,
PGT_OID_EXCLUDE_UNENCRYPTED = 0x12000002,
PGT_OID_DEFAULT_KEYNUM = 0x12000003,
PGT_OID_DEFAULT_KEY0 = 0x12000004,
PGT_OID_DEFAULT_KEY1 = 0x12000005,
PGT_OID_DEFAULT_KEY2 = 0x12000006,
PGT_OID_DEFAULT_KEY3 = 0x12000007,
PGT_OID_STA_KEY = 0x12000008,
PGT_OID_PSM = 0x14000000,
PGT_OID_EAPAUTHSTA = 0x150007de,
PGT_OID_EAPUNAUTHSTA = 0x150007df,
PGT_OID_DOT1X = 0x150007e0,
#define PGT_DOT1X_AUTH_NONE 0
#define PGT_DOT1X_AUTH_ENABLED 1
#define PGT_DOT1X_KEYTX_ENABLED 2
PGT_OID_SLOT_TIME = 0x17000000,
PGT_OID_CHANNEL = 0x17000007,
PGT_OID_PREAMBLE_MODE = 0x17000009,
#define PGT_OID_PREAMBLE_MODE_LONG 0
#define PGT_OID_PREAMBLE_MODE_SHORT 1
#define PGT_OID_PREAMBLE_MODE_DYNAMIC 2
PGT_OID_RATES = 0x1700000a,
PGT_OID_RSSI_VECTOR = 0x1700000d,
PGT_OID_OUTPUT_POWER_TABLE = 0x1700000e,
PGT_OID_OUTPUT_POWER = 0x1700000f,
PGT_OID_SUPPORTED_RATES = 0x17000010,
PGT_OID_NOISE_FLOOR = 0x17000013,
PGT_OID_SLOT_MODE = 0x17000017,
#define PGT_OID_SLOT_MODE_LONG 0
#define PGT_OID_SLOT_MODE_SHORT 1
#define PGT_OID_SLOT_MODE_DYNAMIC 2
PGT_OID_EXTENDED_RATES = 0x17000020,
PGT_OID_FREQUENCY = 0x17000011,
PGT_OID_SUPPORTED_FREQUENCIES = 0x17000012,
PGT_OID_PROFILE = 0x17000019,
#define PGT_PROFILE_B_ONLY 0
#define PGT_PROFILE_MIXED_G_WIFI 1
#define PGT_PROFILE_MIXED_LONG 2
#define PGT_PROFILE_G_ONLY 3
#define PGT_PROFILE_TEST 4
#define PGT_PROFILE_B_WIFI 5
#define PGT_PROFILE_A_ONLY 6
#define PGT_PROFILE_MIXED_SHORT 7
PGT_OID_DEAUTHENTICATE = 0x18000000,
PGT_OID_AUTHENTICATE = 0x18000001,
PGT_OID_DISASSOCIATE = 0x18000002,
PGT_OID_ASSOCIATE = 0x18000003,
PGT_OID_SCAN = 0x18000004,
PGT_OID_BEACON = 0x18000005,
PGT_OID_PROBE = 0x18000006,
PGT_OID_DEAUTHENTICATEEX = 0x18000007,
PGT_OID_AUTHENTICATEEX = 0x18000008,
PGT_OID_DISASSOCIATEEX = 0x18000009,
PGT_OID_ASSOCIATEEX = 0x1800000a,
PGT_OID_REASSOCIATE = 0x1800000b,
PGT_OID_REASSOCIATEEX = 0x1800000c,
PGT_OID_MLME_AUTO_LEVEL = 0x19000001,
#define PGT_MLME_AUTO_LEVEL_AUTO 0
#define PGT_MLME_AUTO_LEVEL_INTERMEDIATE 1
#define PGT_MLME_AUTO_LEVEL_EXTENDED 2
PGT_OID_PSM_BUFFER = 0x19000004,
#define PGT_PSM_BUFFER_FRAME_COUNT 64
PGT_OID_MAX_FRAME_BURST = 0x1b000008,
PGT_OID_BSS_FIND = 0x1c000042,
PGT_OID_BSS_LIST = 0x1c000043,
PGT_OID_MODE = 0xff020003,
#define PGT_MODE_PROMISCUOUS 0
#define PGT_MODE_CLIENT 1
#define PGT_MODE_AP 2
#define PGT_MODE_SNIFFER 3
PGT_OID_CONFIG = 0xff020008,
#define PGT_CONFIG_MANUAL_RUN 0x00000001
#define PGT_CONFIG_FRAME_TRAP 0x00000002
#define PGT_CONFIG_RX_ANNEX 0x00000004
#define PGT_CONFIG_TX_ANNEX 0x00000008
#define PGT_CONFIG_WDS 0x00000010
PGT_OID_PHY = 0xff02000d,
#define PGT_OID_PHY_2400MHZ 0x00000001
#define PGT_OID_PHY_5000MHZ 0x00000002
#define PGT_OID_PHY_FAA 0x80000000
};
struct pgt_obj_ssid {
uint8_t pos_length;
char pos_ssid[33];
} __packed;
struct pgt_obj_key {
uint8_t pok_type;
#define PGT_OBJ_KEY_TYPE_WEP 0
#define PGT_OBJ_KEY_TYPE_TKIP 1
uint8_t pok_length;
uint8_t pok_key[32];
} __packed;
#define PGT_MLME_STATE_NONE 0
#define PGT_MLME_STATE_AUTHING 1
#define PGT_MLME_STATE_AUTH 2
#define PGT_MLME_STATE_ASSOCING 3
#define PGT_MLME_STATE_ASSOC 5
#define PGT_MLME_STATE_IBSS 6
#define PGT_MLME_STATE_WDS 7
struct pgt_obj_mlme {
uint8_t pom_address[6];
uint16_t pom_id;
uint16_t pom_state;
uint16_t pom_code;
} __packed;
struct pgt_obj_mlmeex {
uint8_t pom_address[6];
uint16_t pom_id;
uint16_t pom_state;
uint16_t pom_code;
uint16_t pom_size;
uint8_t pom_data[0];
} __packed;
struct pgt_obj_buffer {
uint32_t pob_size;
uint32_t pob_addr;
} __packed;
struct pgt_obj_bss {
uint8_t pob_address[6];
uint16_t pob_padding0;
uint8_t pob_state;
uint8_t pob_reserved;
uint16_t pob_age;
uint8_t pob_quality;
uint8_t pob_rssi;
struct pgt_obj_ssid pob_ssid;
uint16_t pob_channel;
uint8_t pob_beacon_period;
uint8_t pob_dtim_period;
uint16_t pob_capinfo;
uint16_t pob_rates;
uint16_t pob_basic_rates;
uint16_t pob_padding1;
} __packed;
struct pgt_obj_bsslist {
uint32_t pob_count;
struct pgt_obj_bss pob_bsslist[0];
#define PGT_OBJ_BSSLIST_NBSS 24
} __packed;
struct pgt_obj_frequencies {
uint16_t pof_count;
uint16_t pof_freqlist_mhz[0];
} __packed;
#endif