games/gomoku/bdinit.c

170

int mask, bmask, vertex, s;

games/gomoku/bdinit.c

191

mask = (i == 5) ? 0xC : 0xF;

games/gomoku/bdinit.c

205

str[n] |= (f == 5) ? mask & 0xA : mask;

games/gomoku/pickmove.c

1060

int i, n, mask, flg, verts, idx, fcnt;

games/gomoku/pickmove.c

1084

mask = str[tcbp - frames];

games/gomoku/pickmove.c

1087

if (mask & (1 << n)) {

games/gomoku/pickmove.c

1093

if (tcbp->c_dir == fcbp->c_dir && (mask & (0x10 << n)))

games/gomoku/pickmove.c

1136

mask = str[cbp - frames];

games/gomoku/pickmove.c

1137

if (mask & (1 << n)) {

games/gomoku/pickmove.c

1143

if (cbp->c_dir == fcbp->c_dir && (mask & (0x10 << n)))

games/gomoku/pickmove.c

1443

int d, n, mask;

games/gomoku/pickmove.c

1451

mask = ~((IFLAG | CFLAG) << n);

games/gomoku/pickmove.c

1454

sp->s_flg &= mask;

games/grdc/grdc.c

152

mask = 0;

games/grdc/grdc.c

222

new[i] = (new[i] & ~mask) | (new[i + 1] & mask);

games/grdc/grdc.c

223

new[5] = (new[5] & ~mask) | (next[k] & mask);

games/grdc/grdc.c

225

new[k] = (new[k] & ~mask) | (next[k] & mask);

games/grdc/grdc.c

298

mask |= (next[i] ^ old[i]) & m;

games/grdc/grdc.c

300

if (mask & m)

games/grdc/grdc.c

301

mask |= m;

games/grdc/grdc.c

37

long old[6], next[6], new[6], mask;

games/hack/hack.do_wear.c

187

long mask = 0;

games/hack/hack.do_wear.c

200

mask = W_ARMH;

games/hack/hack.do_wear.c

205

if(!err) mask = W_ARMS;

games/hack/hack.do_wear.c

215

mask = W_ARMG;

games/hack/hack.do_wear.c

223

if(!err) mask = W_ARM;

games/hack/hack.do_wear.c

230

setworn(otmp, mask);

games/hack/hack.do_wear.c

246

long mask = 0;

games/hack/hack.do_wear.c

267

if(uleft) mask = RIGHT_RING;

games/hack/hack.do_wear.c

268

else if(uright) mask = LEFT_RING;

games/hack/hack.do_wear.c

278

mask = LEFT_RING;

games/hack/hack.do_wear.c

282

mask = RIGHT_RING;

games/hack/hack.do_wear.c

285

} while(!mask);

games/hack/hack.do_wear.c

286

setworn(otmp, mask);

games/hack/hack.do_wear.c

290

u.uprops[PROP(otmp->otyp)].p_flgs |= mask;

games/hack/hack.do_wear.c

316

long mask;

games/hack/hack.do_wear.c

318

mask = obj->owornmask & W_RING;

games/hack/hack.do_wear.c

320

if(!(u.uprops[PROP(obj->otyp)].p_flgs & mask))

games/hack/hack.do_wear.c

322

u.uprops[PROP(obj->otyp)].p_flgs &= ~mask;

games/hack/hack.worn.c

84

setworn(struct obj *obj, long mask)

games/hack/hack.worn.c

89

for(wp = worn; wp->w_mask; wp++) if(wp->w_mask & mask) {

games/hunt/huntd/shots.c

454

int mask, count;

games/hunt/huntd/shots.c

477

mask = count = 0;

games/hunt/huntd/shots.c

479

mask |= WEST, count++;

games/hunt/huntd/shots.c

481

mask |= NORTH, count++;

games/hunt/huntd/shots.c

483

mask |= SOUTH, count++;

games/hunt/huntd/shots.c

485

mask |= EAST, count++;

games/hunt/huntd/shots.c

493

dir = mask;

games/hunt/huntd/shots.c

500

if (mask & EAST)

games/hunt/huntd/shots.c

501

mask &= ~EAST, count--;

games/hunt/huntd/shots.c

504

if (mask & WEST)

games/hunt/huntd/shots.c

505

mask &= ~WEST, count--;

games/hunt/huntd/shots.c

508

if (mask & SOUTH)

games/hunt/huntd/shots.c

509

mask &= ~SOUTH, count--;

games/hunt/huntd/shots.c

512

if (mask & NORTH)

games/hunt/huntd/shots.c

513

mask &= ~NORTH, count--;

games/hunt/huntd/shots.c

519

if (n >= 0 && mask & NORTH)

games/hunt/huntd/shots.c

521

if (n >= 0 && mask & SOUTH)

games/hunt/huntd/shots.c

523

if (n >= 0 && mask & EAST)

games/hunt/huntd/shots.c

525

if (n >= 0 && mask & WEST)

games/random/random.c

74

static const uint64_t mask[] = {

games/random/random.c

87

if ((x & mask[i]) == 0)

include/resolv.h

148

u_int32_t mask;

include/resolv.h

166

} addr, mask;

lib/libc/arch/aarch64/gen/fpsetmask.c

23

fpsetmask(fp_except mask)

lib/libc/arch/alpha/gen/fpsetmask.c

40

fpsetmask(mask)

lib/libc/arch/alpha/gen/fpsetmask.c

41

fp_except mask;

lib/libc/arch/alpha/gen/fpsetmask.c

45

a.mask = mask;

lib/libc/arch/alpha/gen/fpsetsticky.c

45

a.mask = sticky;

lib/libc/arch/arm/gen/fpsetmask.c

23

fpsetmask(fp_except mask)

lib/libc/arch/hppa/gen/fpsetmask.c

11

fpsetmask(mask)

lib/libc/arch/hppa/gen/fpsetmask.c

12

fp_except mask;

lib/libc/arch/hppa/gen/fpsetmask.c

19

fpsr = (fpsr & 0xffffffe000000000LL) | ((u_int64_t)(mask & 0x1f) << 32);

lib/libc/arch/hppa/gen/fpsetsticky.c

11

fpsetsticky(mask)

lib/libc/arch/hppa/gen/fpsetsticky.c

12

fp_except mask;

lib/libc/arch/hppa/gen/fpsetsticky.c

19

fpsr = (fpsr & 0x07ffffff00000000LL) | ((u_int64_t)(mask & 0x1f) << 59);

lib/libc/arch/m88k/gen/fpsetmask.c

12

fpsetmask(mask)

lib/libc/arch/m88k/gen/fpsetmask.c

13

fp_except mask;

lib/libc/arch/m88k/gen/fpsetmask.c

22

new |= (mask & 0x1f); /* set them to mask */

lib/libc/arch/mips64/gen/fpsetmask.c

10

fpsetmask(mask)

lib/libc/arch/mips64/gen/fpsetmask.c

11

fp_except mask;

lib/libc/arch/mips64/gen/fpsetmask.c

20

new |= ((mask & 0x1f) << 7);

lib/libc/arch/powerpc/gen/fpsetmask.c

37

fpsetmask(mask)

lib/libc/arch/powerpc/gen/fpsetmask.c

38

fp_except mask;

lib/libc/arch/powerpc/gen/fpsetmask.c

45

fpscr = (fpscr & 0xffffff07ULL) | (mask << 3);

lib/libc/arch/powerpc/gen/fpsetsticky.c

37

fpsetsticky(mask)

lib/libc/arch/powerpc/gen/fpsetsticky.c

38

fp_except mask;

lib/libc/arch/powerpc/gen/fpsetsticky.c

45

fpscr = (fpscr & 0xe1ffffffULL) | ((mask & 0xf) << 25);

lib/libc/arch/powerpc/gen/fpsetsticky.c

46

if (mask & FP_X_INV)

lib/libc/arch/powerpc64/gen/fpsetmask.c

37

fpsetmask(mask)

lib/libc/arch/powerpc64/gen/fpsetmask.c

38

fp_except mask;

lib/libc/arch/powerpc64/gen/fpsetmask.c

45

fpscr = (fpscr & 0xffffff07ULL) | (mask << 3);

lib/libc/arch/powerpc64/gen/fpsetsticky.c

37

fpsetsticky(mask)

lib/libc/arch/powerpc64/gen/fpsetsticky.c

38

fp_except mask;

lib/libc/arch/powerpc64/gen/fpsetsticky.c

45

fpscr = (fpscr & 0xe1ffffffULL) | ((mask & 0xf) << 25);

lib/libc/arch/powerpc64/gen/fpsetsticky.c

46

if (mask & FP_X_INV)

lib/libc/arch/riscv64/gen/fpsetmask.c

21

fpsetmask(fp_except mask)

lib/libc/arch/sh/gen/fpsetmask.c

23

fpsetmask(fp_except mask)

lib/libc/arch/sh/gen/fpsetmask.c

29

__fpscr_values[0] = (__fpscr_values[0] & ~(0x1f << 7)) | (mask << 7);

lib/libc/arch/sh/gen/fpsetmask.c

30

__fpscr_values[1] = (__fpscr_values[1] & ~(0x1f << 7)) | (mask << 7);

lib/libc/arch/sh/gen/fpsetmask.c

33

nfpscr = (fpscr & ~(0x1f << 7)) | (mask << 7);

lib/libc/arch/sh/gen/fpsetsticky.c

23

fpsetsticky(fp_except mask)

lib/libc/arch/sh/gen/fpsetsticky.c

29

__fpscr_values[0] = (__fpscr_values[0] & ~(0x1f << 2)) | (mask << 2);

lib/libc/arch/sh/gen/fpsetsticky.c

30

__fpscr_values[1] = (__fpscr_values[1] & ~(0x1f << 2)) | (mask << 2);

lib/libc/arch/sh/gen/fpsetsticky.c

33

nfpscr = (fpscr & ~(0x1f << 2)) | (mask << 2);

lib/libc/arch/sparc64/fpu/fpu_explode.c

236

exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS);

lib/libc/arch/sparc64/fpu/fpu_explode.c

237

frac = i & mask(SNG_FRACBITS);

lib/libc/arch/sparc64/fpu/fpu_explode.c

256

exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS);

lib/libc/arch/sparc64/fpu/fpu_explode.c

257

frac = i & mask(DBL_FRACBITS - 32);

lib/libc/arch/sparc64/fpu/fpu_explode.c

280

exp = (i >> (32 - 1 - EXT_EXPBITS)) & mask(EXT_EXPBITS);

lib/libc/arch/sparc64/fpu/fpu_explode.c

281

frac = i & mask(EXT_FRACBITS - 3 * 32);

lib/libc/arch/sparc64/gen/fpsetmask.c

11

fpsetmask(mask)

lib/libc/arch/sparc64/gen/fpsetmask.c

12

fp_except mask;

lib/libc/arch/sparc64/gen/fpsetmask.c

21

new |= ((mask & 0x1f) << 23);

lib/libc/citrus/citrus_utf8.c

101

mask = 0x07;

lib/libc/citrus/citrus_utf8.c

122

wch = (unsigned char)*s++ & mask;

lib/libc/citrus/citrus_utf8.c

48

int ch, i, mask, want;

lib/libc/citrus/citrus_utf8.c

89

mask = 0x7f;

lib/libc/citrus/citrus_utf8.c

93

mask = 0x1f;

lib/libc/citrus/citrus_utf8.c

97

mask = 0x0f;

lib/libc/compat-43/sigcompat.c

50

sigsetmask(int mask)

lib/libc/compat-43/sigcompat.c

54

n = WRAP(sigprocmask)(SIG_SETMASK, (sigset_t *) &mask,

lib/libc/compat-43/sigcompat.c

62

sigblock(int mask)

lib/libc/compat-43/sigcompat.c

66

n = WRAP(sigprocmask)(SIG_BLOCK, (sigset_t *) &mask,

lib/libc/compat-43/sigcompat.c

74

sigpause(int mask)

lib/libc/compat-43/sigcompat.c

76

return (sigsuspend((sigset_t *)&mask));

lib/libc/db/hash/hash_page.c

630

u_int32_t i, mask;

lib/libc/db/hash/hash_page.c

632

mask = 0x1;

lib/libc/db/hash/hash_page.c

634

if (!(mask & map))

lib/libc/db/hash/hash_page.c

636

mask = mask << 1;

lib/libc/gen/pause.c

17

sigset_t mask;

lib/libc/gen/pause.c

19

return (sigprocmask(SIG_BLOCK, NULL, &mask) ? -1 : sigsuspend(&mask));

lib/libc/gen/setmode.c

167

mode_t mask, perm, permXbits, who;

lib/libc/gen/setmode.c

184

(void)umask(mask = umask(0));

lib/libc/gen/setmode.c

185

mask = ~mask;

lib/libc/gen/setmode.c

208

ADDCMD('=', (STANDARD_BITS|S_ISTXT), perm, mask);

lib/libc/gen/setmode.c

288

ADDCMD(op, who, perm, mask);

lib/libc/gen/setmode.c

294

ADDCMD('X', who, permXbits, mask);

lib/libc/gen/setmode.c

297

ADDCMD(*p, who, op, mask);

lib/libc/gen/setmode.c

308

ADDCMD(op, who, perm, mask);

lib/libc/gen/setmode.c

312

ADDCMD('X', who, permXbits, mask);

lib/libc/gen/setmode.c

339

addcmd(BITCMD *set, int op, int who, int oparg, u_int mask)

lib/libc/gen/setmode.c

353

set->bits = (who ? who : mask) & oparg;

lib/libc/gen/setmode.c

367

set->bits = mask;

lib/libc/locale/newlocale.c

25

newlocale(int mask, const char *locname, locale_t oldloc)

lib/libc/locale/newlocale.c

30

if (locname == NULL || mask & ~LC_ALL_MASK) {

lib/libc/locale/newlocale.c

38

if (ic != LC_CTYPE && mask & flag &&

lib/libc/locale/newlocale.c

46

if ((mask & LC_CTYPE_MASK) == 0)

lib/libc/net/rcmd.c

116

sigemptyset(&mask);

lib/libc/net/rcmd.c

117

sigaddset(&mask, SIGURG);

lib/libc/net/rcmd.c

118

sigprocmask(SIG_BLOCK, &mask, &oldmask);

lib/libc/net/rcmd.c

68

sigset_t oldmask, mask;

lib/libc/regex/regcomp.c

1048

cs->mask = 1 << ((no) % CHAR_BIT);

lib/libc/regex/regex2.h

107

uch mask; /* bit within array */

lib/libc/regex/regex2.h

114

cs->ptr[(uch)c] |= cs->mask;

lib/libc/regex/regex2.h

121

cs->ptr[(uch)c] &= ~cs->mask;

lib/libc/regex/regex2.h

128

return (cs->ptr[(uch)c] & cs->mask) != 0;

lib/libc/rpc/svc.c

526

fd_mask mask, *maskp;

lib/libc/rpc/svc.c

531

for (mask = *maskp++; (bit = ffs(mask));

lib/libc/rpc/svc.c

532

mask ^= (1 << (bit - 1)))

lib/libc/softfloat/fpsetmask.c

43

fpsetmask(fp_except mask)

lib/libc/softfloat/fpsetmask.c

48

float_exception_mask = mask;

lib/libc/stdlib/abort.c

40

sigset_t mask;

lib/libc/stdlib/abort.c

43

sigfillset(&mask);

lib/libc/stdlib/abort.c

48

sigdelset(&mask, SIGABRT);

lib/libc/stdlib/abort.c

49

(void)sigprocmask(SIG_SETMASK, &mask, NULL);

lib/libc/stdlib/abort.c

60

(void)sigprocmask(SIG_SETMASK, &mask, NULL);

lib/libc/stdlib/malloc.c

1110

unsigned int mask, rounded, rounded_size;

lib/libc/stdlib/malloc.c

1115

mask = (1ULL << shift) - 1;

lib/libc/stdlib/malloc.c

1116

rounded = size + mask; /* XXX: overflow. */

lib/libc/stdlib/malloc.c

1118

rounded_size = rounded & ~mask;

lib/libc/stdlib/malloc.c

602

size_t mask;

lib/libc/stdlib/malloc.c

612

mask = newtotal - 1;

lib/libc/stdlib/malloc.c

625

size_t index = hash(q) & mask;

lib/libc/stdlib/malloc.c

628

index = (index - 1) & mask;

lib/libc/stdlib/malloc.c

655

size_t mask;

lib/libc/stdlib/malloc.c

662

mask = d->regions_total - 1;

lib/libc/stdlib/malloc.c

663

index = hash(p) & mask;

lib/libc/stdlib/malloc.c

667

index = (index - 1) & mask;

lib/libc/stdlib/malloc.c

682

size_t mask = d->regions_total - 1;

lib/libc/stdlib/malloc.c

691

index = hash(p) & mask;

lib/libc/stdlib/malloc.c

695

index = (index - 1) & mask;

lib/libc/stdlib/malloc.c

706

size_t mask = d->regions_total - 1;

lib/libc/stdlib/malloc.c

720

i = (i - 1) & mask;

lib/libc/stdlib/malloc.c

723

r = hash(d->r[i].p) & mask;

lib/libc/stdlib/system.c

45

sigset_t mask, omask;

lib/libc/stdlib/system.c

54

sigemptyset(&mask);

lib/libc/stdlib/system.c

55

sigaddset(&mask, SIGCHLD);

lib/libc/stdlib/system.c

56

sigaddset(&mask, SIGINT);

lib/libc/stdlib/system.c

57

sigaddset(&mask, SIGQUIT);

lib/libc/stdlib/system.c

58

sigprocmask(SIG_BLOCK, &mask, &omask);

lib/libc/stdlib/system.c

75

sigemptyset(&mask);

lib/libc/stdlib/system.c

76

sigaddset(&mask, SIGINT);

lib/libc/stdlib/system.c

77

sigaddset(&mask, SIGQUIT);

lib/libc/stdlib/system.c

78

sigprocmask(SIG_UNBLOCK, &mask, NULL);

lib/libc/string/ffs.c

14

ffs(int mask)

lib/libc/string/ffs.c

17

unsigned int r = mask;

lib/libc/string/ffsl.c

14

ffsl(long mask)

lib/libc/string/ffsl.c

16

return (mask ? __builtin_ctzl(mask) + 1 : 0);

lib/libc/string/ffsll.c

14

ffsll(long long mask)

lib/libc/string/ffsll.c

16

return (mask ? __builtin_ctzll(mask) + 1 : 0);

lib/libc/sys/stack_protector.c

54

sigset_t mask;

lib/libc/sys/stack_protector.c

58

sigfillset(&mask);

lib/libc/sys/stack_protector.c

59

sigdelset(&mask, SIGABRT);

lib/libc/sys/stack_protector.c

60

sigprocmask(SIG_SETMASK, &mask, NULL);

lib/libcrypto/asn1/a_mbstr.c

110

if (!mask)

lib/libcrypto/asn1/a_mbstr.c

111

mask = DIRSTRING_TYPE;

lib/libcrypto/asn1/a_mbstr.c

163

if (traverse_string(in, len, inform, type_str, &mask) < 0) {

lib/libcrypto/asn1/a_mbstr.c

171

if (mask & B_ASN1_PRINTABLESTRING)

lib/libcrypto/asn1/a_mbstr.c

173

else if (mask & B_ASN1_IA5STRING)

lib/libcrypto/asn1/a_mbstr.c

175

else if (mask & B_ASN1_T61STRING)

lib/libcrypto/asn1/a_mbstr.c

177

else if (mask & B_ASN1_BMPSTRING) {

lib/libcrypto/asn1/a_mbstr.c

180

} else if (mask & B_ASN1_UNIVERSALSTRING) {

lib/libcrypto/asn1/a_mbstr.c

89

int inform, unsigned long mask)

lib/libcrypto/asn1/a_mbstr.c

91

return ASN1_mbstring_ncopy(out, in, len, inform, mask, 0, 0);

lib/libcrypto/asn1/a_mbstr.c

97

int inform, unsigned long mask, long minsize, long maxsize)

lib/libcrypto/asn1/a_strnid.c

103

unsigned long mask;

lib/libcrypto/asn1/a_strnid.c

112

mask = strtoul(p + 5, &end, 0);

lib/libcrypto/asn1/a_strnid.c

113

if (errno == ERANGE && mask == ULONG_MAX)

lib/libcrypto/asn1/a_strnid.c

119

mask = ~((unsigned long)(B_ASN1_BMPSTRING|B_ASN1_UTF8STRING));

lib/libcrypto/asn1/a_strnid.c

121

mask = ~((unsigned long)B_ASN1_T61STRING);

lib/libcrypto/asn1/a_strnid.c

123

mask = B_ASN1_UTF8STRING;

lib/libcrypto/asn1/a_strnid.c

125

mask = 0xFFFFFFFFL;

lib/libcrypto/asn1/a_strnid.c

128

ASN1_STRING_set_default_mask(mask);

lib/libcrypto/asn1/a_strnid.c

145

unsigned long mask;

lib/libcrypto/asn1/a_strnid.c

152

mask = tbl->mask;

lib/libcrypto/asn1/a_strnid.c

154

mask &= global_mask;

lib/libcrypto/asn1/a_strnid.c

155

ret = ASN1_mbstring_ncopy(out, in, inlen, inform, mask,

lib/libcrypto/asn1/a_strnid.c

182

.mask = DIRSTRING_TYPE,

lib/libcrypto/asn1/a_strnid.c

189

.mask = B_ASN1_PRINTABLESTRING,

lib/libcrypto/asn1/a_strnid.c

196

.mask = DIRSTRING_TYPE,

lib/libcrypto/asn1/a_strnid.c

203

.mask = DIRSTRING_TYPE,

lib/libcrypto/asn1/a_strnid.c

210

.mask = DIRSTRING_TYPE,

lib/libcrypto/asn1/a_strnid.c

217

.mask = DIRSTRING_TYPE,

lib/libcrypto/asn1/a_strnid.c

224

.mask = B_ASN1_IA5STRING,

lib/libcrypto/asn1/a_strnid.c

231

.mask = PKCS9STRING_TYPE,

lib/libcrypto/asn1/a_strnid.c

238

.mask = PKCS9STRING_TYPE,

lib/libcrypto/asn1/a_strnid.c

245

.mask = DIRSTRING_TYPE,

lib/libcrypto/asn1/a_strnid.c

252

.mask = DIRSTRING_TYPE,

lib/libcrypto/asn1/a_strnid.c

259

.mask = DIRSTRING_TYPE,

lib/libcrypto/asn1/a_strnid.c

266

.mask = DIRSTRING_TYPE,

lib/libcrypto/asn1/a_strnid.c

273

.mask = B_ASN1_PRINTABLESTRING,

lib/libcrypto/asn1/a_strnid.c

280

.mask = B_ASN1_BMPSTRING,

lib/libcrypto/asn1/a_strnid.c

287

.mask = DIRSTRING_TYPE,

lib/libcrypto/asn1/a_strnid.c

294

.mask = B_ASN1_PRINTABLESTRING,

lib/libcrypto/asn1/a_strnid.c

301

.mask = B_ASN1_IA5STRING,

lib/libcrypto/asn1/a_strnid.c

308

.mask = B_ASN1_BMPSTRING,

lib/libcrypto/asn1/a_strnid.c

77

ASN1_STRING_set_default_mask(unsigned long mask)

lib/libcrypto/asn1/a_strnid.c

79

global_mask = mask;

lib/libcrypto/asn1/asn1.h

213

unsigned long mask;

lib/libcrypto/asn1/asn1.h

812

void ASN1_STRING_set_default_mask(unsigned long mask);

lib/libcrypto/asn1/asn1.h

816

int inform, unsigned long mask);

lib/libcrypto/asn1/asn1.h

818

int inform, unsigned long mask, long minsize, long maxsize);

lib/libcrypto/asn1/asn1t.h

838

#define IMPLEMENT_ASN1_MSTRING(itname, mask) \

lib/libcrypto/asn1/asn1t.h

841

.utype = mask, \

lib/libcrypto/bio/bio_lib.c

728

int mt, mask;

lib/libcrypto/bio/bio_lib.c

732

mask = type & 0xff;

lib/libcrypto/bio/bio_lib.c

736

if (!mask) {

lib/libcrypto/bn/bn_add_sub.c

118

BN_ULONG mask, size_t n)

lib/libcrypto/bn/bn_add_sub.c

125

bn_qwaddqw(a[3], a[2], a[1], a[0], b[3] & mask, b[2] & mask,

lib/libcrypto/bn/bn_add_sub.c

126

b[1] & mask, b[0] & mask, carry, &carry, &r[3], &r[2],

lib/libcrypto/bn/bn_add_sub.c

134

bn_addw_addw(a[0], b[0] & mask, carry, &carry, &r[0]);

lib/libcrypto/bn/bn_add_sub.c

152

BN_ULONG mask, size_t n)

lib/libcrypto/bn/bn_add_sub.c

160

bn_qwsubqw(a[3], a[2], a[1], a[0], b[3] & mask, b[2] & mask,

lib/libcrypto/bn/bn_add_sub.c

161

b[1] & mask, b[0] & mask, borrow, &borrow, &r[3], &r[2],

lib/libcrypto/bn/bn_add_sub.c

169

bn_subw_subw(a[0], b[0] & mask, borrow, &borrow, &r[0]);

lib/libcrypto/bn/bn_convert.c

108

mask = 0;

lib/libcrypto/bn/bn_convert.c

114

mask = crypto_ct_lt_mask(j, bn->top);

lib/libcrypto/bn/bn_convert.c

118

out[i] = (w >> b) & mask;

lib/libcrypto/bn/bn_convert.c

91

uint8_t mask, v;

lib/libcrypto/bn/bn_internal.h

36

BN_ULONG mask, size_t n);

lib/libcrypto/bn/bn_internal.h

38

BN_ULONG mask, size_t n);

lib/libcrypto/bn/bn_mod_words.c

30

BN_ULONG carry, mask;

lib/libcrypto/bn/bn_mod_words.c

39

mask = ~(carry - bn_sub_words_borrow(r, m, n));

lib/libcrypto/bn/bn_mod_words.c

40

bn_sub_words_masked(r, r, m, mask, n);

lib/libcrypto/bn/bn_mod_words.c

53

BN_ULONG borrow, mask;

lib/libcrypto/bn/bn_mod_words.c

61

mask = (0 - borrow);

lib/libcrypto/bn/bn_mod_words.c

62

bn_add_words_masked(r, r, m, mask, n);

lib/libcrypto/bn/bn_mont.c

329

BN_ULONG v, mask;

lib/libcrypto/bn/bn_mont.c

348

mask = carry - bn_sub_words(r, a, n, n_len);

lib/libcrypto/bn/bn_mont.c

351

*r = (*r & ~mask) | (*a & mask);

lib/libcrypto/bn/bn_mont.c

473

BN_ULONG a0, b, carry_a, carry_n, carry, mask, w;

lib/libcrypto/bn/bn_mont.c

503

mask = bn_ct_ne_zero(tp[n_len]) - bn_sub_words(rp, tp, np, n_len);

lib/libcrypto/bn/bn_mont.c

506

*rp = (*rp & ~mask) | (*tp & mask);

lib/libcrypto/bn/bn_primitives.c

29

BN_ULONG bits, mask, shift;

lib/libcrypto/bn/bn_primitives.c

32

mask = 0;

lib/libcrypto/bn/bn_primitives.c

35

bits += (shift & mask) - (shift & ~mask);

lib/libcrypto/bn/bn_primitives.c

36

mask = bn_ct_ne_zero_mask(w >> bits);

lib/libcrypto/bn/bn_primitives.c

38

bits += 1 & mask;

lib/libcrypto/bn/bn_primitives.c

52

BN_ULONG mask, w;

lib/libcrypto/bn/bn_primitives.c

57

mask = bn_ct_ne_zero_mask(w);

lib/libcrypto/bn/bn_primitives.c

58

n = ((BN_ULONG)i & mask) | (n & ~mask);

lib/libcrypto/bn/bn_primitives.c

59

x = (w & mask) | (x & ~mask);

lib/libcrypto/bn/bn_rand.c

125

int ret = 0, bit, bytes, mask;

lib/libcrypto/bn/bn_rand.c

148

mask = 0xff << (bit + 1);

lib/libcrypto/bn/bn_rand.c

188

buf[0] &= ~mask;

lib/libcrypto/cmac/cmac.c

106

mask = 0 - (l[0] >> 7);

lib/libcrypto/cmac/cmac.c

107

kn[block_size - 1] = (l[block_size - 1] << 1) ^ (Rb & mask);

lib/libcrypto/cmac/cmac.c

95

unsigned char mask, Rb;

lib/libcrypto/constant_time.h

119

static inline unsigned int constant_time_select(unsigned int mask,

lib/libcrypto/constant_time.h

123

static inline unsigned char constant_time_select_8(unsigned char mask,

lib/libcrypto/constant_time.h

127

static inline int constant_time_select_int(unsigned int mask, int a, int b);

lib/libcrypto/constant_time.h

184

static inline unsigned int constant_time_select(unsigned int mask,

lib/libcrypto/constant_time.h

188

return (mask & a) | (~mask & b);

lib/libcrypto/constant_time.h

191

static inline unsigned char constant_time_select_8(unsigned char mask,

lib/libcrypto/constant_time.h

195

return (unsigned char)(constant_time_select(mask, a, b));

lib/libcrypto/constant_time.h

198

static inline int constant_time_select_int(unsigned int mask, int a, int b)

lib/libcrypto/constant_time.h

200

return (int)(constant_time_select(mask, (unsigned)(a), (unsigned)(b)));

lib/libcrypto/ec/ec_field.c

138

BN_ULONG mask;

lib/libcrypto/ec/ec_field.c

141

mask = bn_ct_eq_zero_mask(conditional);

lib/libcrypto/ec/ec_field.c

144

r->w[i] = (a->w[i] & mask) | (b->w[i] & ~mask);

lib/libcrypto/ec/ecp_hp_methods.c

596

BN_ULONG mask;

lib/libcrypto/ec/ecp_hp_methods.c

604

mask = ~(0 - (ec_point_is_at_infinity(group, point) |

lib/libcrypto/ec/ecp_hp_methods.c

611

point->fe_y.w[i] = (point->fe_y.w[i] & ~mask) | (y.w[i] & mask);

lib/libcrypto/mlkem/mlkem_internal.c

1071

scalar mask, v;

lib/libcrypto/mlkem/mlkem_internal.c

1084

scalar_inner_product(&mask, &priv->s[0], &u[0], rank);

lib/libcrypto/mlkem/mlkem_internal.c

1085

scalar_inverse_ntt(&mask);

lib/libcrypto/mlkem/mlkem_internal.c

1086

scalar_sub(&v, &mask);

lib/libcrypto/mlkem/mlkem_internal.c

1105

uint8_t mask;

lib/libcrypto/mlkem/mlkem_internal.c

1128

mask = constant_time_eq_int_8(timingsafe_memcmp(ciphertext, expected_ciphertext,

lib/libcrypto/mlkem/mlkem_internal.c

1131

out_shared_secret[i] = constant_time_select_8(mask,

lib/libcrypto/mlkem/mlkem_internal.c

198

uint16_t mask = 0u - (subtracted >> 15);

lib/libcrypto/mlkem/mlkem_internal.c

212

return (mask & x) | (~mask & subtracted);

lib/libcrypto/mlkem/mlkem_internal.c

491

uint16_t mask;

lib/libcrypto/mlkem/mlkem_internal.c

503

mask = 0u - (value >> 15);

lib/libcrypto/mlkem/mlkem_internal.c

504

out->c[i] = ((value + kPrime) & mask) | (value & ~mask);

lib/libcrypto/mlkem/mlkem_internal.c

510

mask = 0u - (value >> 15);

lib/libcrypto/mlkem/mlkem_internal.c

511

out->c[i + 1] = ((value + kPrime) & mask) | (value & ~mask);

lib/libcrypto/poly1305/poly1305-donna.c

221

unsigned long mask;

lib/libcrypto/poly1305/poly1305-donna.c

272

mask = (g4 >> ((sizeof(unsigned long) * 8) - 1)) - 1;

lib/libcrypto/poly1305/poly1305-donna.c

273

g0 &= mask;

lib/libcrypto/poly1305/poly1305-donna.c

274

g1 &= mask;

lib/libcrypto/poly1305/poly1305-donna.c

275

g2 &= mask;

lib/libcrypto/poly1305/poly1305-donna.c

276

g3 &= mask;

lib/libcrypto/poly1305/poly1305-donna.c

277

g4 &= mask;

lib/libcrypto/poly1305/poly1305-donna.c

278

mask = ~mask;

lib/libcrypto/poly1305/poly1305-donna.c

279

h0 = (h0 & mask) | g0;

lib/libcrypto/poly1305/poly1305-donna.c

280

h1 = (h1 & mask) | g1;

lib/libcrypto/poly1305/poly1305-donna.c

281

h2 = (h2 & mask) | g2;

lib/libcrypto/poly1305/poly1305-donna.c

282

h3 = (h3 & mask) | g3;

lib/libcrypto/poly1305/poly1305-donna.c

283

h4 = (h4 & mask) | g4;

lib/libcrypto/rsa/rsa.h

327

int PKCS1_MGF1(unsigned char *mask, long len,

lib/libcrypto/rsa/rsa_oaep.c

178

unsigned int good = 0, found_one_byte, mask;

lib/libcrypto/rsa/rsa_oaep.c

225

mask = ~constant_time_is_zero(flen);

lib/libcrypto/rsa/rsa_oaep.c

226

flen -= 1 & mask;

lib/libcrypto/rsa/rsa_oaep.c

227

from -= 1 & mask;

lib/libcrypto/rsa/rsa_oaep.c

228

*--em = *from & mask;

lib/libcrypto/rsa/rsa_oaep.c

299

for (mask = good, i = 0; i < tlen; i++) {

lib/libcrypto/rsa/rsa_oaep.c

303

mask &= ~equals; /* mask = 0 at EOF */

lib/libcrypto/rsa/rsa_oaep.c

304

to[i] = constant_time_select_8(mask, db[msg_index++], to[i]);

lib/libcrypto/rsa/rsa_oaep.c

324

PKCS1_MGF1(unsigned char *mask, long len, const unsigned char *seed,

lib/libcrypto/rsa/rsa_oaep.c

350

if (!EVP_DigestFinal_ex(md_ctx, mask + outlen, NULL))

lib/libcrypto/rsa/rsa_oaep.c

356

memcpy(mask + outlen, md, len - outlen);

lib/libcrypto/x509/x509_addr.c

574

uint8_t mask = (1 << unused_bits) - 1;

lib/libcrypto/x509/x509_addr.c

579

addr[bs->length - 1] &= ~mask;

lib/libcrypto/x509/x509_addr.c

581

addr[bs->length - 1] |= mask;

lib/libcrypto/x509/x509_addr.c

839

unsigned char mask;

lib/libcrypto/x509/x509_addr.c

850

mask = min[i] ^ max[i];

lib/libcrypto/x509/x509_addr.c

851

switch (mask) {

lib/libcrypto/x509/x509_addr.c

876

if ((min[i] & mask) != 0 || (max[i] & mask) != mask)

lib/libcrypto/x509/x509_constraints.c

669

uint8_t *mask;

lib/libcrypto/x509/x509_constraints.c

675

mask = constraint + alen;

lib/libcrypto/x509/x509_constraints.c

677

if ((address[i] & mask[i]) != (constraint[i] & mask[i]))

lib/libcrypto/x509/x509_obj.c

115

int mask[4] = { 1, 1, 1, 1 };

lib/libcrypto/x509/x509_obj.c

130

mask[0] = mask[1] = mask[2] = 0;

lib/libcrypto/x509/x509_obj.c

138

if (mask[i++ & 0x3] == 0)

lib/libcurses/base/lib_getch.c

247

int mask = 0;

lib/libcurses/base/lib_getch.c

249

(void) mask;

lib/libcurses/base/lib_getch.c

259

mask = check_mouse_activity(sp, -1 EVENTLIST_2nd(evl));

lib/libcurses/base/lib_getch.c

261

mask = 0;

lib/libcurses/base/lib_getch.c

263

if (mask & TW_EVENT) {

lib/libcurses/base/lib_getch.c

270

mask = check_mouse_activity(sp, -1 EVENTLIST_2nd(evl));

lib/libcurses/base/lib_getch.c

275

if ((sp->_mouse_fd >= 0) && (mask & TW_MOUSE)) {

lib/libcurses/base/lib_getch.c

288

&& (mask <= 0) && errno == EINTR) {

lib/libcurses/base/lib_mouse.c

260

unsigned short mask = MOUSE_BN1_DOWN | MOUSE_BN2_DOWN | MOUSE_BN3_DOWN;

lib/libcurses/base/lib_mouse.c

268

rc = MouSetEventMask(&mask, hmou);

lib/libcurses/base/lib_mouse.c

270

mask = MOUSE_BN1_DOWN | MOUSE_BN2_DOWN;

lib/libcurses/base/lib_mouse.c

271

rc = MouSetEventMask(&mask, hmou);

lib/libcurses/base/lib_overlay.c

156

attr_t mask;

lib/libcurses/base/lib_overlay.c

161

mask = ~(attr_t) ((bk & A_COLOR) ? A_COLOR : 0);

lib/libcurses/base/lib_overlay.c

201

mask) | bk));

lib/libcurses/base/sigaction.c

48

_nc_sigemptyset(sigset_t * mask)

lib/libcurses/base/sigaction.c

50

*mask = 0;

lib/libcurses/base/sigaction.c

55

_nc_sigprocmask(int mode, sigset_t * mask, sigset_t * omask)

lib/libcurses/base/sigaction.c

63

current |= *mask;

lib/libcurses/base/sigaction.c

65

current &= ~*mask;

lib/libcurses/base/sigaction.c

67

current = *mask;

lib/libcurses/base/sigaction.c

74

_nc_sigaddset(sigset_t * mask, int sig)

lib/libcurses/base/sigaction.c

76

*mask |= sigmask(sig);

lib/libcurses/base/sigaction.c

83

_nc_sigsuspend(sigset_t * mask)

lib/libcurses/base/sigaction.c

85

return sigpause(*mask);

lib/libcurses/base/sigaction.c

89

_nc_sigdelset(sigset_t * mask, int sig)

lib/libcurses/base/sigaction.c

91

*mask &= ~sigmask(sig);

lib/libcurses/base/sigaction.c

96

_nc_sigismember(sigset_t * mask, int sig)

lib/libcurses/base/sigaction.c

98

return (*mask & sigmask(sig)) != 0;

lib/libcurses/curses.h

1121

#define NCURSES_BITS(mask,shift) (NCURSES_CAST(chtype,(mask)) << ((shift) + NCURSES_ATTR_SHIFT))

lib/libcurses/curses.priv.h

1661

#define USE_TRACEF(mask) _nc_use_tracef(mask)

lib/libcurses/curses.priv.h

1665

#define USE_TRACEF(mask) (_nc_tracing & (mask))

lib/libcurses/tinfo/lib_win32con.c

635

decode_mouse(SCREEN *sp, int mask)

lib/libcurses/tinfo/lib_win32con.c

642

if (mask & FROM_LEFT_1ST_BUTTON_PRESSED)

lib/libcurses/tinfo/lib_win32con.c

644

if (mask & FROM_LEFT_2ND_BUTTON_PRESSED)

lib/libcurses/tinfo/lib_win32con.c

646

if (mask & FROM_LEFT_3RD_BUTTON_PRESSED)

lib/libcurses/tinfo/lib_win32con.c

648

if (mask & FROM_LEFT_4TH_BUTTON_PRESSED)

lib/libcurses/tinfo/lib_win32con.c

651

if (mask & RIGHTMOST_BUTTON_PRESSED) {

lib/libcurses/tinfo/obsolete.c

186

unsigned mask = 0;

lib/libcurses/tinfo/obsolete.c

193

mask = (unsigned) *source;

lib/libcurses/tinfo/obsolete.c

196

mask = (unsigned) (*source & 0x1f);

lib/libcurses/tinfo/obsolete.c

199

mask = (unsigned) (*source & 0x0f);

lib/libcurses/tinfo/obsolete.c

202

mask = (unsigned) (*source & 0x07);

lib/libcurses/tinfo/obsolete.c

205

mask = (unsigned) (*source & 0x03);

lib/libcurses/tinfo/obsolete.c

208

mask = (unsigned) (*source & 0x01);

lib/libcurses/tinfo/obsolete.c

235

*target |= mask << shift;

lib/libcurses/tinfo/parse_entry.c

191

usertype2s(int mask)

lib/libcurses/tinfo/parse_entry.c

194

if (mask & (1 << BOOLEAN)) {

lib/libcurses/tinfo/parse_entry.c

196

} else if (mask & (1 << NUMBER)) {

lib/libcurses/tinfo/parse_entry.c

198

} else if (mask & (1 << STRING)) {

lib/libcurses/tinfo/read_entry.c

62

unsigned mask = 0xff;

lib/libcurses/tinfo/read_entry.c

68

mask <<= 8;

lib/libcurses/tinfo/read_entry.c

71

while (mask != 0) {

lib/libcurses/tinfo/read_entry.c

72

Numbers[i] |= (int) mask;

lib/libcurses/tinfo/read_entry.c

73

mask <<= 8;

lib/libcurses/trace/lib_trace.c

120

unsigned mask;

lib/libcurses/trace/lib_trace.c

183

#define SPECIAL_MASK(mask) \

lib/libcurses/trace/lib_trace.c

184

if ((tracelevel & mask) == mask) \

lib/libcurses/trace/lib_trace.c

185

_tracef("- %s (%u)", #mask, mask)

lib/libcurses/trace/lib_trace.c

188

unsigned mask = (1U << bit) & tracelevel;

lib/libcurses/trace/lib_trace.c

189

if ((mask & trace_names[bit].mask) != 0) {

lib/libcurses/trace/lib_trace.c

190

_tracef("- %s (%u)", trace_names[bit].name, mask);

lib/libcurses/trace/lib_trace.c

429

_nc_use_tracef(unsigned mask)

lib/libcurses/trace/lib_trace.c

435

if ((result = (_nc_tracing & (mask))) != 0

lib/libcurses/trace/lib_trace.c

444

result = (_nc_tracing & (mask));

lib/libcurses/tty/lib_tstp.c

143

sigset_t mask, omask;

lib/libcurses/tty/lib_tstp.c

175

(void) sigemptyset(&mask);

lib/libcurses/tty/lib_tstp.c

177

(void) sigaddset(&mask, SIGALRM);

lib/libcurses/tty/lib_tstp.c

180

(void) sigaddset(&mask, SIGWINCH);

lib/libcurses/tty/lib_tstp.c

182

(void) sigprocmask(SIG_BLOCK, &mask, &omask);

lib/libcurses/tty/lib_tstp.c

187

(void) sigemptyset(&mask);

lib/libcurses/tty/lib_tstp.c

188

(void) sigaddset(&mask, SIGTTOU);

lib/libcurses/tty/lib_tstp.c

189

(void) sigprocmask(SIG_BLOCK, &mask, NULL);

lib/libcurses/tty/lib_tstp.c

200

(void) sigemptyset(&mask);

lib/libcurses/tty/lib_tstp.c

201

(void) sigaddset(&mask, SIGTSTP);

lib/libcurses/tty/lib_tstp.c

205

(void) sigaddset(&mask, SIGTTOU);

lib/libcurses/tty/lib_tstp.c

208

(void) sigprocmask(SIG_UNBLOCK, &mask, NULL);

lib/libcurses/tty/lib_vidattr.c

208

attr_t mask = NCURSES_BITS((value & 63)

lib/libcurses/tty/lib_vidattr.c

212

if ((mask & A_REVERSE) != 0

lib/libcurses/tty/lib_vidattr.c

215

mask &= ~A_REVERSE;

lib/libcurses/tty/lib_vidattr.c

217

newmode &= ~mask;

lib/libcurses/tty/lib_vidattr.c

81

#define TurnOn(mask, mode) \

lib/libcurses/tty/lib_vidattr.c

82

if ((turn_on & mask) && mode) { \

lib/libcurses/tty/lib_vidattr.c

87

#define TurnOff(mask, mode) \

lib/libcurses/tty/lib_vidattr.c

88

if ((turn_off & mask) && mode) { \

lib/libcurses/tty/lib_vidattr.c

91

turn_off &= ~mask; \

lib/libcurses/widechar/lib_vid_attr.c

141

attr_t mask = NCURSES_BITS((value & 63)

lib/libcurses/widechar/lib_vid_attr.c

145

if ((mask & A_REVERSE) != 0

lib/libcurses/widechar/lib_vid_attr.c

148

mask &= ~A_REVERSE;

lib/libcurses/widechar/lib_vid_attr.c

150

newmode &= ~mask;

lib/libcurses/widechar/lib_vid_attr.c

48

#define TurnOn(mask, mode) \

lib/libcurses/widechar/lib_vid_attr.c

49

if ((turn_on & mask) && mode) { \

lib/libcurses/widechar/lib_vid_attr.c

54

#define TurnOff(mask, mode) \

lib/libcurses/widechar/lib_vid_attr.c

55

if ((turn_off & mask) && mode) { \

lib/libcurses/widechar/lib_vid_attr.c

58

turn_off &= ~mask; \

lib/libexpat/lib/xmlparse.c

249

#define SECOND_HASH(hash, mask, power) \

lib/libexpat/lib/xmlparse.c

250

((((hash) & ~(mask)) >> ((power) - 1)) & ((mask) >> 2))

lib/libexpat/lib/xmlparse.c

251

#define PROBE_STEP(hash, mask, power) \

lib/libexpat/lib/xmlparse.c

252

((unsigned char)((SECOND_HASH(hash, mask, power)) | 1))

lib/libexpat/lib/xmlparse.c

4168

unsigned long mask = nsAttsSize - 1;

lib/libexpat/lib/xmlparse.c

4169

j = uriHash & mask; /* index into hash table */

lib/libexpat/lib/xmlparse.c

4182

step = PROBE_STEP(uriHash, mask, parser->m_nsAttsPower);

lib/libexpat/lib/xmlparse.c

7880

unsigned long mask = (unsigned long)table->size - 1;

lib/libexpat/lib/xmlparse.c

7882

i = h & mask;

lib/libexpat/lib/xmlparse.c

7887

step = PROBE_STEP(h, mask, table->power);

lib/libfido2/src/assert.c

117

if (assert->ext.mask)

lib/libfido2/src/assert.c

304

if (pin != NULL || assert->ext.mask != 0)

lib/libfido2/src/assert.c

311

(assert->ext.mask & FIDO_EXT_HMAC_SECRET)) {

lib/libfido2/src/assert.c

319

if (r == FIDO_OK && (assert->ext.mask & FIDO_EXT_HMAC_SECRET))

lib/libfido2/src/assert.c

461

if (check_extensions(stmt->authdata_ext.mask, assert->ext.mask) < 0) {

lib/libfido2/src/assert.c

611

assert->ext.mask = 0;

lib/libfido2/src/assert.c

615

assert->ext.mask |= ext;

lib/libfido2/src/cbor.c

1145

authdata_ext->mask |= FIDO_EXT_HMAC_SECRET;

lib/libfido2/src/cbor.c

1152

authdata_ext->mask |= FIDO_EXT_CRED_PROTECT;

lib/libfido2/src/cbor.c

1162

authdata_ext->mask |= FIDO_EXT_CRED_BLOB;

lib/libfido2/src/cbor.c

1169

authdata_ext->mask |= FIDO_EXT_MINPINLEN;

lib/libfido2/src/cbor.c

1234

authdata_ext->mask |= FIDO_EXT_HMAC_SECRET;

lib/libfido2/src/cbor.c

1240

authdata_ext->mask |= FIDO_EXT_CRED_BLOB;

lib/libfido2/src/cbor.c

605

if (ext->mask & FIDO_EXT_CRED_BLOB)

lib/libfido2/src/cbor.c

607

if (ext->mask & FIDO_EXT_HMAC_SECRET)

lib/libfido2/src/cbor.c

609

if (ext->mask & FIDO_EXT_CRED_PROTECT)

lib/libfido2/src/cbor.c

611

if (ext->mask & FIDO_EXT_LARGEBLOB_KEY)

lib/libfido2/src/cbor.c

613

if (ext->mask & FIDO_EXT_MINPINLEN)

lib/libfido2/src/cbor.c

619

if (ext->mask & FIDO_EXT_CRED_BLOB) {

lib/libfido2/src/cbor.c

626

if (ext->mask & FIDO_EXT_CRED_PROTECT) {

lib/libfido2/src/cbor.c

634

if (ext->mask & FIDO_EXT_HMAC_SECRET) {

lib/libfido2/src/cbor.c

640

if (ext->mask & FIDO_EXT_LARGEBLOB_KEY) {

lib/libfido2/src/cbor.c

646

if (ext->mask & FIDO_EXT_MINPINLEN) {

lib/libfido2/src/cbor.c

875

if (ext->mask & FIDO_EXT_CRED_BLOB)

lib/libfido2/src/cbor.c

877

if (ext->mask & FIDO_EXT_HMAC_SECRET)

lib/libfido2/src/cbor.c

879

if (ext->mask & FIDO_EXT_LARGEBLOB_KEY)

lib/libfido2/src/cbor.c

884

if (ext->mask & FIDO_EXT_CRED_BLOB) {

lib/libfido2/src/cbor.c

890

if (ext->mask & FIDO_EXT_HMAC_SECRET) {

lib/libfido2/src/cbor.c

897

if (ext->mask & FIDO_EXT_LARGEBLOB_KEY) {

lib/libfido2/src/cred.c

205

cred->ext.mask != 0)

lib/libfido2/src/cred.c

221

tmp.mask &= ~FIDO_EXT_LARGEBLOB_KEY;

lib/libfido2/src/cred.c

866

cred->ext.mask = 0;

lib/libfido2/src/cred.c

870

cred->ext.mask |= ext;

lib/libfido2/src/cred.c

89

if (cred->ext.mask)

lib/libfido2/src/cred.c

905

cred->ext.mask &= ~FIDO_EXT_CRED_PROTECT;

lib/libfido2/src/cred.c

913

cred->ext.mask |= FIDO_EXT_CRED_PROTECT;

lib/libfido2/src/cred.c

924

cred->ext.mask &= ~FIDO_EXT_MINPINLEN;

lib/libfido2/src/cred.c

926

cred->ext.mask |= FIDO_EXT_MINPINLEN;

lib/libfido2/src/cred.c

941

cred->ext.mask |= FIDO_EXT_CRED_BLOB;

lib/libfido2/src/fido/types.h

135

int mask; /* enabled extensions */

lib/libfido2/src/fido/types.h

162

int mask; /* decoded extensions */

lib/libfido2/src/fido/types.h

179

int mask; /* enabled extensions */

lib/libfuse/fuse_lowlevel.h

92

void (*access) (fuse_req_t req, fuse_ino_t ino, int mask);

lib/libfuse/fuse_ops.c

116

ifuse_ops_access(fuse_req_t req, fuse_ino_t ino, int mask)

lib/libfuse/fuse_ops.c

131

err = f->op.access(realname, mask);

lib/libm/arch/aarch64/fenv.c

257

feenableexcept(int mask)

lib/libm/arch/aarch64/fenv.c

263

fedisableexcept(int mask)

lib/libm/arch/alpha/fenv.c

129

a.mask = fpsticky;

lib/libm/arch/alpha/fenv.c

244

a.mask = 0;

lib/libm/arch/alpha/fenv.c

248

a.mask = 0;

lib/libm/arch/alpha/fenv.c

270

a.mask = envp->__sticky & FE_ALL_EXCEPT;

lib/libm/arch/alpha/fenv.c

274

a.mask = envp->__mask & FE_ALL_EXCEPT;

lib/libm/arch/alpha/fenv.c

325

feenableexcept(int mask)

lib/libm/arch/alpha/fenv.c

330

mask &= FE_ALL_EXCEPT;

lib/libm/arch/alpha/fenv.c

336

fpmask |= mask;

lib/libm/arch/alpha/fenv.c

339

a.mask = fpmask;

lib/libm/arch/alpha/fenv.c

347

fedisableexcept(int mask)

lib/libm/arch/alpha/fenv.c

352

mask &= FE_ALL_EXCEPT;

lib/libm/arch/alpha/fenv.c

358

fpmask &= ~mask;

lib/libm/arch/alpha/fenv.c

361

a.mask = fpmask;

lib/libm/arch/alpha/fenv.c

65

a.mask = fpsticky;

lib/libm/arch/amd64/fenv.c

365

feenableexcept(int mask)

lib/libm/arch/amd64/fenv.c

370

mask &= FE_ALL_EXCEPT;

lib/libm/arch/amd64/fenv.c

376

control &= ~mask;

lib/libm/arch/amd64/fenv.c

379

mxcsr &= ~(mask << _SSE_MASK_SHIFT);

lib/libm/arch/amd64/fenv.c

386

fedisableexcept(int mask)

lib/libm/arch/amd64/fenv.c

391

mask &= FE_ALL_EXCEPT;

lib/libm/arch/amd64/fenv.c

397

control |= mask;

lib/libm/arch/amd64/fenv.c

400

mxcsr |= mask << _SSE_MASK_SHIFT;

lib/libm/arch/arm/fenv.c

300

feenableexcept(int mask)

lib/libm/arch/arm/fenv.c

306

fedisableexcept(int mask)

lib/libm/arch/hppa/fenv.c

328

feenableexcept(int mask)

lib/libm/arch/hppa/fenv.c

333

mask &= FE_ALL_EXCEPT;

lib/libm/arch/hppa/fenv.c

340

u.bits[0] |= mask;

lib/libm/arch/hppa/fenv.c

350

fedisableexcept(int mask)

lib/libm/arch/hppa/fenv.c

355

mask &= FE_ALL_EXCEPT;

lib/libm/arch/hppa/fenv.c

362

u.bits[0] &= ~mask;

lib/libm/arch/i387/fenv.c

408

feenableexcept(int mask)

lib/libm/arch/i387/fenv.c

413

mask &= FE_ALL_EXCEPT;

lib/libm/arch/i387/fenv.c

420

control &= ~mask;

lib/libm/arch/i387/fenv.c

424

mxcsr &= ~(mask << _SSE_MASK_SHIFT);

lib/libm/arch/i387/fenv.c

432

fedisableexcept(int mask)

lib/libm/arch/i387/fenv.c

437

mask &= FE_ALL_EXCEPT;

lib/libm/arch/i387/fenv.c

444

control |= mask;

lib/libm/arch/i387/fenv.c

448

mxcsr |= mask << _SSE_MASK_SHIFT;

lib/libm/arch/m88k/fenv.c

317

feenableexcept(int mask)

lib/libm/arch/m88k/fenv.c

321

mask &= FE_ALL_EXCEPT;

lib/libm/arch/m88k/fenv.c

327

fpcr |= mask;

lib/libm/arch/m88k/fenv.c

337

fedisableexcept(int mask)

lib/libm/arch/m88k/fenv.c

341

mask &= FE_ALL_EXCEPT;

lib/libm/arch/m88k/fenv.c

347

fpcr &= ~mask;

lib/libm/arch/mips64/fenv.c

276

feenableexcept(int mask)

lib/libm/arch/mips64/fenv.c

280

mask &= FE_ALL_EXCEPT;

lib/libm/arch/mips64/fenv.c

286

fcsr |= mask << _MASK_SHIFT;

lib/libm/arch/mips64/fenv.c

296

fedisableexcept(int mask)

lib/libm/arch/mips64/fenv.c

300

mask &= FE_ALL_EXCEPT;

lib/libm/arch/mips64/fenv.c

306

fcsr &= ~(mask << _MASK_SHIFT);

lib/libm/arch/powerpc/fenv.c

290

feenableexcept(int mask)

lib/libm/arch/powerpc/fenv.c

295

mask &= FE_ALL_EXCEPT;

lib/libm/arch/powerpc/fenv.c

301

u.bits[1] |= mask >> _MASK_SHIFT;

lib/libm/arch/powerpc/fenv.c

311

fedisableexcept(int mask)

lib/libm/arch/powerpc/fenv.c

316

mask &= FE_ALL_EXCEPT;

lib/libm/arch/powerpc/fenv.c

322

u.bits[1] &= ~(mask >> _MASK_SHIFT);

lib/libm/arch/powerpc64/fenv.c

290

feenableexcept(int mask)

lib/libm/arch/powerpc64/fenv.c

295

mask &= FE_ALL_EXCEPT;

lib/libm/arch/powerpc64/fenv.c

301

u.bits[1] |= mask >> _MASK_SHIFT;

lib/libm/arch/powerpc64/fenv.c

311

fedisableexcept(int mask)

lib/libm/arch/powerpc64/fenv.c

316

mask &= FE_ALL_EXCEPT;

lib/libm/arch/powerpc64/fenv.c

322

u.bits[1] &= ~(mask >> _MASK_SHIFT);

lib/libm/arch/riscv64/fenv.c

245

feenableexcept(int mask)

lib/libm/arch/riscv64/fenv.c

251

fedisableexcept(int mask)

lib/libm/arch/sh/fenv.c

337

feenableexcept(int mask)

lib/libm/arch/sh/fenv.c

341

mask &= FE_ALL_EXCEPT;

lib/libm/arch/sh/fenv.c

347

fpscr |= mask << _MASK_SHIFT;

lib/libm/arch/sh/fenv.c

348

__fpscr_values[0] |= mask << _MASK_SHIFT;

lib/libm/arch/sh/fenv.c

349

__fpscr_values[1] |= mask << _MASK_SHIFT;

lib/libm/arch/sh/fenv.c

359

fedisableexcept(int mask)

lib/libm/arch/sh/fenv.c

363

mask &= FE_ALL_EXCEPT;

lib/libm/arch/sh/fenv.c

369

fpscr &= ~(mask << _MASK_SHIFT);

lib/libm/arch/sh/fenv.c

370

__fpscr_values[0] &= ~(mask << _MASK_SHIFT);

lib/libm/arch/sh/fenv.c

371

__fpscr_values[1] &= ~(mask << _MASK_SHIFT);

lib/libm/arch/sparc64/fenv.c

302

feenableexcept(int mask)

lib/libm/arch/sparc64/fenv.c

306

mask &= FE_ALL_EXCEPT;

lib/libm/arch/sparc64/fenv.c

311

new_r = old_r | (mask << _MASK_SHIFT);

lib/libm/arch/sparc64/fenv.c

320

fedisableexcept(int mask)

lib/libm/arch/sparc64/fenv.c

324

mask &= FE_ALL_EXCEPT;

lib/libm/arch/sparc64/fenv.c

329

new_r = old_r & ~(mask << _MASK_SHIFT);

lib/libmenu/mf_common.h

88

#define SetStatus(target,mask) (target)->status |= (unsigned short) (mask)

lib/libmenu/mf_common.h

89

#define ClrStatus(target,mask) (target)->status = (unsigned short) (target->status & (~mask))

lib/libpcap/gencode.c

1006

gen_hostop6(struct in6_addr *addr, struct in6_addr *mask, int dir, int proto,

lib/libpcap/gencode.c

1024

b0 = gen_hostop6(addr, mask, Q_SRC, proto, src_off, dst_off);

lib/libpcap/gencode.c

1025

b1 = gen_hostop6(addr, mask, Q_DST, proto, src_off, dst_off);

lib/libpcap/gencode.c

1031

b0 = gen_hostop6(addr, mask, Q_SRC, proto, src_off, dst_off);

lib/libpcap/gencode.c

1032

b1 = gen_hostop6(addr, mask, Q_DST, proto, src_off, dst_off);

lib/libpcap/gencode.c

1042

m = (u_int32_t *)mask;

lib/libpcap/gencode.c

1216

gen_host(bpf_u_int32 addr, bpf_u_int32 mask, int proto, int dir)

lib/libpcap/gencode.c

1223

b0 = gen_host(addr, mask, Q_IP, dir);

lib/libpcap/gencode.c

1224

b1 = gen_host(addr, mask, Q_ARP, dir);

lib/libpcap/gencode.c

1226

b0 = gen_host(addr, mask, Q_RARP, dir);

lib/libpcap/gencode.c

1231

return gen_hostop(addr, mask, dir, ETHERTYPE_IP,

lib/libpcap/gencode.c

1235

return gen_hostop(addr, mask, dir, ETHERTYPE_REVARP,

lib/libpcap/gencode.c

1239

return gen_hostop(addr, mask, dir, ETHERTYPE_ARP,

lib/libpcap/gencode.c

1304

gen_host6(struct in6_addr *addr, struct in6_addr *mask, int proto, int dir)

lib/libpcap/gencode.c

1309

return gen_host6(addr, mask, Q_IPV6, dir);

lib/libpcap/gencode.c

1360

return gen_hostop6(addr, mask, dir, ETHERTYPE_IPV6,

lib/libpcap/gencode.c

2242

bpf_u_int32 mask, addr;

lib/libpcap/gencode.c

2262

mask = 0xffffffff;

lib/libpcap/gencode.c

2265

mask <<= 8;

lib/libpcap/gencode.c

2267

return gen_host(addr, mask, proto, dir);

lib/libpcap/gencode.c

2480

bpf_u_int32 mask;

lib/libpcap/gencode.c

2502

mask = 0xffffffff;

lib/libpcap/gencode.c

2507

mask <<= 8;

lib/libpcap/gencode.c

2512

mask <<= 32 - vlen;

lib/libpcap/gencode.c

2514

return gen_host(v, mask, proto, dir);

lib/libpcap/gencode.c

2565

struct in6_addr mask;

lib/libpcap/gencode.c

2579

if (sizeof(mask) * 8 < masklen)

lib/libpcap/gencode.c

2580

bpf_error("mask length must be <= %u", (unsigned int)(sizeof(mask) * 8));

lib/libpcap/gencode.c

2581

memset(&mask, 0, sizeof(mask));

lib/libpcap/gencode.c

2582

memset(&mask, 0xff, masklen / 8);

lib/libpcap/gencode.c

2584

mask.s6_addr[masklen / 8] =

lib/libpcap/gencode.c

2589

m = (u_int32_t *)&mask;

lib/libpcap/gencode.c

2604

b = gen_host6(addr, &mask, q.proto, q.dir);

lib/libpcap/gencode.c

275

const char *buf, int optimize, bpf_u_int32 mask)

lib/libpcap/gencode.c

289

netmask = mask;

lib/libpcap/gencode.c

322

const char *buf, int optimize, bpf_u_int32 mask)

lib/libpcap/gencode.c

3256

gen_p80211_type(int type, int mask)

lib/libpcap/gencode.c

3271

b0 = gen_mcmp(offset, BPF_B, (bpf_int32)type, (bpf_u_int32)mask);

lib/libpcap/gencode.c

335

netmask = mask;

lib/libpcap/gencode.c

502

gen_mcmp(u_int offset, u_int size, bpf_int32 v, bpf_u_int32 mask)

lib/libpcap/gencode.c

507

if (mask != 0xffffffff) {

lib/libpcap/gencode.c

509

s->s.k = mask;

lib/libpcap/gencode.c

517

gen_mcmp_nl(u_int offset, u_int size, bpf_int32 v, bpf_u_int32 mask)

lib/libpcap/gencode.c

522

if (mask != 0xffffffff) {

lib/libpcap/gencode.c

524

s->s.k = mask;

lib/libpcap/gencode.c

965

gen_hostop(bpf_u_int32 addr, bpf_u_int32 mask, int dir, int proto,

lib/libpcap/gencode.c

982

b0 = gen_hostop(addr, mask, Q_SRC, proto, src_off, dst_off);

lib/libpcap/gencode.c

983

b1 = gen_hostop(addr, mask, Q_DST, proto, src_off, dst_off);

lib/libpcap/gencode.c

989

b0 = gen_hostop(addr, mask, Q_SRC, proto, src_off, dst_off);

lib/libpcap/gencode.c

990

b1 = gen_hostop(addr, mask, Q_DST, proto, src_off, dst_off);

lib/libpcap/gencode.c

999

b1 = gen_mcmp_nl(offset, BPF_W, (bpf_int32)addr, mask);

lib/libssl/s3_cbc.c

151

unsigned char mask = constant_time_ge(padding_length, i);

lib/libssl/s3_cbc.c

155

good &= ~(mask&(padding_length ^ b));

lib/libssl/ssl_srvr.c

1648

uint8_t mask;

lib/libssl/ssl_srvr.c

1725

mask = crypto_ct_eq_mask_u8(valid, 1);

lib/libssl/ssl_srvr.c

1727

pms[i] = (pms[pad_len + i] & mask) | (fakepms[i] & ~mask);

lib/libusbhid/data.c

101

mask = (1 << hsize) - 1;

lib/libusbhid/data.c

102

data &= mask;

lib/libusbhid/data.c

104

mask = ~0;

lib/libusbhid/data.c

107

mask <<= (hpos % 8);

lib/libusbhid/data.c

108

mask = ~mask;

lib/libusbhid/data.c

114

buf[offs + i] = (buf[offs + i] & (mask >> (i*8))) |

lib/libusbhid/data.c

84

uint32_t mask;

lib/libusbhid/parse.c

212

int32_t mask;

lib/libusbhid/parse.c

286

mask = 0;

lib/libusbhid/parse.c

290

mask = 0xFF;

lib/libusbhid/parse.c

296

mask = 0xFFFF;

lib/libusbhid/parse.c

303

mask = 0xFFFFFFFF;

lib/libusbhid/parse.c

403

s->loc_size = dval & mask;

lib/libusbhid/parse.c

406

hid_switch_rid(s, c, dval & mask);

lib/libusbhid/parse.c

410

s->loc_count = dval & mask;

lib/libusbhid/parse.c

442

dval = (dval & mask) | c->_usage_page;

lib/libusbhid/parse.c

461

dval = (dval & mask) | c->_usage_page;

lib/libusbhid/parse.c

469

dval = (dval & mask) | c->_usage_page;

lib/libutil/login_fbtab.c

126

login_protect(const char *path, mode_t mask, uid_t uid, gid_t gid)

lib/libutil/login_fbtab.c

150

if (chmod(gpath, mask) && errno != ENOENT)

lib/libz/inftrees.c

211

mask = used - 1; /* mask for comparing low */

lib/libz/inftrees.c

263

if (len > root && (huff & mask) != low) {

lib/libz/inftrees.c

288

low = huff & mask;

lib/libz/inftrees.c

59

unsigned mask; /* mask for low root bits */

libexec/ld.so/aarch64/rtld_machine.c

127

Elf_Addr *where, value, mask;

libexec/ld.so/aarch64/rtld_machine.c

214

mask = RELOC_VALUE_BITMASK(type);

libexec/ld.so/aarch64/rtld_machine.c

216

value &= mask;

libexec/ld.so/aarch64/rtld_machine.c

218

*where &= ~mask;

libexec/ld.so/amd64/rtld_machine.c

200

Elf_Addr *where, value, mask;

libexec/ld.so/amd64/rtld_machine.c

283

mask = RELOC_VALUE_BITMASK(type);

libexec/ld.so/amd64/rtld_machine.c

285

value &= mask;

libexec/ld.so/amd64/rtld_machine.c

288

*where &= ~mask;

libexec/ld.so/amd64/rtld_machine.c

293

*where32 &= ~mask;

libexec/ld.so/arm/rtld_machine.c

190

Elf_Addr *where, value, mask;

libexec/ld.so/arm/rtld_machine.c

279

mask = RELOC_VALUE_BITMASK(type);

libexec/ld.so/arm/rtld_machine.c

281

value &= mask;

libexec/ld.so/arm/rtld_machine.c

283

*where &= ~mask;

libexec/ld.so/i386/rtld_machine.c

200

Elf_Addr *where, value, mask;

libexec/ld.so/i386/rtld_machine.c

283

mask = RELOC_VALUE_BITMASK(type);

libexec/ld.so/i386/rtld_machine.c

285

value &= mask;

libexec/ld.so/i386/rtld_machine.c

287

*where &= ~mask;

libexec/ld.so/malloc.c

253

size_t mask;

libexec/ld.so/malloc.c

262

mask = newtotal - 1;

libexec/ld.so/malloc.c

272

size_t index = hash(q) & mask;

libexec/ld.so/malloc.c

274

index = (index - 1) & mask;

libexec/ld.so/malloc.c

296

size_t mask;

libexec/ld.so/malloc.c

303

mask = d->regions_total - 1;

libexec/ld.so/malloc.c

304

index = hash(p) & mask;

libexec/ld.so/malloc.c

307

index = (index - 1) & mask;

libexec/ld.so/malloc.c

320

size_t mask = d->regions_total - 1;

libexec/ld.so/malloc.c

327

index = hash(p) & mask;

libexec/ld.so/malloc.c

331

index = (index - 1) & mask;

libexec/ld.so/malloc.c

342

size_t mask = d->regions_total - 1;

libexec/ld.so/malloc.c

355

i = (i - 1) & mask;

libexec/ld.so/malloc.c

358

r = hash(d->r[i].p) & mask;

libexec/ld.so/malloc.c

382

u_int i, offset, mask;

libexec/ld.so/malloc.c

395

mask = MALLOC_CACHE - 1;

libexec/ld.so/malloc.c

399

r = &d->free_regions[(i + offset) & mask];

libexec/ld.so/malloc.c

418

r = &d->free_regions[(i + offset) & mask];

libexec/ld.so/riscv64/rtld_machine.c

126

Elf_Addr *where, value, mask;

libexec/ld.so/riscv64/rtld_machine.c

213

mask = RELOC_VALUE_BITMASK(type);

libexec/ld.so/riscv64/rtld_machine.c

215

value &= mask;

libexec/ld.so/riscv64/rtld_machine.c

217

*where &= ~mask;

libexec/ld.so/sh/rtld_machine.c

445

Elf_Addr *where, value, mask;

libexec/ld.so/sh/rtld_machine.c

535

mask = RELOC_VALUE_BITMASK(type);

libexec/ld.so/sh/rtld_machine.c

537

value &= mask;

libexec/ld.so/sh/rtld_machine.c

539

*where &= ~mask;

libexec/ld.so/sparc64/rtld_machine.c

238

Elf_Addr *where, value, mask;

libexec/ld.so/sparc64/rtld_machine.c

309

mask = RELOC_VALUE_BITMASK(type);

libexec/ld.so/sparc64/rtld_machine.c

311

value &= mask;

libexec/ld.so/sparc64/rtld_machine.c

323

tmp &= ~mask;

libexec/ld.so/sparc64/rtld_machine.c

330

*where &= ~mask;

libexec/ld.so/sparc64/rtld_machine.c

335

*where32 &= ~mask;

libexec/snmpd/snmpd_metrics/kroute.c

1061

static struct in6_addr mask;

libexec/snmpd/snmpd_metrics/kroute.c

1064

bzero(&mask, sizeof(mask));

libexec/snmpd/snmpd_metrics/kroute.c

1066

mask.s6_addr[i] = 0xff;

libexec/snmpd/snmpd_metrics/kroute.c

1069

mask.s6_addr[prefixlen / 8] = 0xff00 >> i;

libexec/snmpd/snmpd_metrics/kroute.c

1071

return (&mask);

libexec/snmpd/snmpd_metrics/kroute.c

1102

if_newaddr(u_short if_index, struct sockaddr *ifa, struct sockaddr *mask,

libexec/snmpd/snmpd_metrics/kroute.c

1123

if (mask)

libexec/snmpd/snmpd_metrics/kroute.c

1124

bcopy(mask, &ka->mask.sa, mask->sa_len);

libexec/snmpd/snmpd_metrics/kroute.c

1126

bzero(&ka->mask, sizeof(ka->mask));

libexec/snmpd/snmpd_metrics/kroute.c

1134

if_deladdr(u_short if_index, struct sockaddr *ifa, struct sockaddr *mask,

libexec/snmpd/snmpd_metrics/mib.c

2798

agentx_varbind_ipaddress(vb, &ka->mask.sin.sin_addr);

libexec/snmpd/snmpd_metrics/snmpd.h

137

union kaddr mask;

libexec/tradcpp/eval.c

305

unsigned mask;

libexec/tradcpp/eval.c

335

mask = ((unsigned)-1) << (CHAR_BIT * sizeof(unsigned) - rv);

libexec/tradcpp/eval.c

336

lv = (int)(((unsigned)lv >> (unsigned)rv) | mask);

regress/lib/libc/locale/uselocale/uselocale.c

91

#define FUNCPARA int mask, const char *locname

regress/lib/libc/locale/uselocale/uselocale.c

92

#define FUNCARGS mask, locname, _LOCALE_NONE

regress/lib/libc/sys/t_pollts.c

163

sigset_t mask;

regress/lib/libc/sys/t_pollts.c

177

ATF_REQUIRE_EQ(sigfillset(&mask), 0);

regress/lib/libc/sys/t_pollts.c

178

ATF_REQUIRE_EQ(sigprocmask(SIG_UNBLOCK, &mask, NULL), 0);

regress/lib/libc/sys/t_pollts.c

184

ATF_REQUIRE_EQ_MSG(ret = POLLTS(&pfd, 1, &timeout, &mask), 1,

regress/lib/libc/sys/t_pollts.c

188

ATF_REQUIRE_EQ(sigprocmask(SIG_SETMASK, NULL, &mask), 0);

regress/lib/libc/sys/t_pollts.c

189

ATF_REQUIRE_EQ_MSG(sigismember(&mask, SIGUSR1), 0,

regress/lib/libc/sys/t_umask.c

124

for (i = 0; i < __arraycount(mask); i++) {

regress/lib/libc/sys/t_umask.c

126

(void)umask(mask[i]);

regress/lib/libc/sys/t_umask.c

141

if ((st.st_mode & mask[i]) != 0) {

regress/lib/libc/sys/t_umask.c

177

for (i = 0; i < __arraycount(mask); i++) {

regress/lib/libc/sys/t_umask.c

179

mode = umask(mask[i]);

regress/lib/libc/sys/t_umask.c

180

mode = umask(mask[i]);

regress/lib/libc/sys/t_umask.c

182

if (mode != mask[i])

regress/lib/libc/sys/t_umask.c

45

static const mode_t mask[] = {

regress/lib/libc/sys/t_umask.c

73

for (i = 0; i < __arraycount(mask) - 1; i++) {

regress/lib/libc/sys/t_umask.c

75

(void)umask(mask[i] | mask[i + 1]);

regress/lib/libc/sys/t_umask.c

84

mode = umask(mask[i]);

regress/lib/libc/sys/t_umask.c

86

if (mode != (mask[i] | mask[i + 1]))

regress/lib/libcrypto/crypto/crypto_test.c

104

(unsigned long long)mask);

regress/lib/libcrypto/crypto/crypto_test.c

119

uint8_t a, b, mask;

regress/lib/libcrypto/crypto/crypto_test.c

130

mask = (a != 0) ? -1 : 0;

regress/lib/libcrypto/crypto/crypto_test.c

131

if (mask != crypto_ct_ne_zero_mask_u8(a)) {

regress/lib/libcrypto/crypto/crypto_test.c

133

"want %x\n", a, crypto_ct_ne_zero_mask_u8(a), mask);

regress/lib/libcrypto/crypto/crypto_test.c

141

mask = (a == 0) ? -1 : 0;

regress/lib/libcrypto/crypto/crypto_test.c

142

if (mask != crypto_ct_eq_zero_mask_u8(a)) {

regress/lib/libcrypto/crypto/crypto_test.c

144

"want %x\n", a, crypto_ct_ne_zero_mask_u8(a), mask);

regress/lib/libcrypto/crypto/crypto_test.c

156

mask = (a != b) ? -1 : 0;

regress/lib/libcrypto/crypto/crypto_test.c

157

if (mask != crypto_ct_ne_mask_u8(a, b)) {

regress/lib/libcrypto/crypto/crypto_test.c

159

"want %x\n", a, b, crypto_ct_ne_mask_u8(a, b), mask);

regress/lib/libcrypto/crypto/crypto_test.c

167

mask = (a == b) ? -1 : 0;

regress/lib/libcrypto/crypto/crypto_test.c

168

if (mask != crypto_ct_eq_mask_u8(a, b)) {

regress/lib/libcrypto/crypto/crypto_test.c

170

"want %x\n", a, b, crypto_ct_eq_mask_u8(a, b), mask);

regress/lib/libcrypto/crypto/crypto_test.c

27

size_t a, b, mask;

regress/lib/libcrypto/crypto/crypto_test.c

44

mask = (a != 0) ? -1 : 0;

regress/lib/libcrypto/crypto/crypto_test.c

45

if (mask != crypto_ct_ne_zero_mask(a)) {

regress/lib/libcrypto/crypto/crypto_test.c

49

(unsigned long long)mask);

regress/lib/libcrypto/crypto/crypto_test.c

58

mask = (a == 0) ? -1 : 0;

regress/lib/libcrypto/crypto/crypto_test.c

59

if (mask != crypto_ct_eq_zero_mask(a)) {

regress/lib/libcrypto/crypto/crypto_test.c

63

(unsigned long long)mask);

regress/lib/libcrypto/crypto/crypto_test.c

79

mask = (a < b) ? -1 : 0;

regress/lib/libcrypto/crypto/crypto_test.c

80

if (mask != crypto_ct_lt_mask(a, b)) {

regress/lib/libcrypto/crypto/crypto_test.c

86

(unsigned long long)mask);

regress/lib/libcrypto/crypto/crypto_test.c

97

mask = (a > b) ? -1 : 0;

regress/lib/libcrypto/crypto/crypto_test.c

98

if (mask != crypto_ct_gt_mask(a, b)) {

regress/lib/libm/msun/fls.c

41

fls(int mask)

regress/lib/libm/msun/fls.c

45

if (mask == 0)

regress/lib/libm/msun/fls.c

47

for (bit = 1; mask != 1; bit++)

regress/lib/libm/msun/fls.c

48

mask = (unsigned int)mask >> 1;

regress/lib/libm/msun/rem_test.c

159

ATF_CHECK(q == (abs(expected_quo) & mask(q)));

regress/lib/libm/msun/rem_test.c

181

ATF_CHECK(q == (abs(expected_quo) & mask(q)));

regress/lib/libm/msun/rem_test.c

203

ATF_CHECK((q & mask(q)) == (abs(expected_quo) & mask(q)));

regress/lib/libpthread/dlopen/dlopen.c

570

sigset_t mask;

regress/lib/libpthread/dlopen/dlopen.c

573

sigemptyset(&mask);

regress/lib/libpthread/dlopen/dlopen.c

574

sigaddset(&mask, SIGALRM);

regress/lib/libpthread/dlopen/dlopen.c

575

sigprocmask(SIG_UNBLOCK, &mask, NULL);

regress/lib/libpthread/dlopen/dlopen.c

594

sigset_t mask;

regress/lib/libpthread/dlopen/dlopen.c

647

sigemptyset(&mask);

regress/lib/libpthread/dlopen/dlopen.c

648

sigaddset(&mask, SIGTERM);

regress/lib/libpthread/dlopen/dlopen.c

649

sigprocmask(SIG_UNBLOCK, &mask, NULL);

regress/lib/libpthread/dlopen/dlopen.c

672

sigemptyset(&mask);

regress/lib/libpthread/dlopen/dlopen.c

673

sigaddset(&mask, SIGALRM);

regress/lib/libpthread/dlopen/dlopen.c

674

sigprocmask(SIG_BLOCK, &mask, NULL);

regress/lib/libpthread/pthread_join/pthread_join.c

102

if (sigprocmask(SIG_BLOCK, &mask, NULL))

regress/lib/libpthread/pthread_join/pthread_join.c

105

if (sigprocmask(SIG_UNBLOCK, &mask, NULL))

regress/lib/libpthread/pthread_join/pthread_join.c

85

sigset_t mask;

regress/lib/libpthread/pthread_join/pthread_join.c

96

sigemptyset(&mask);

regress/lib/libpthread/pthread_join/pthread_join.c

97

sigaddset(&mask, SIGALRM);

regress/lib/libpthread/sigmask/sigmask.c

18

sigset_t mask;

regress/lib/libpthread/sigmask/sigmask.c

31

CHECKe(sigemptyset(&mask));

regress/lib/libpthread/sigmask/sigmask.c

32

CHECKe(sigaddset(&mask, SIGALRM));

regress/lib/libpthread/sigmask/sigmask.c

33

CHECKr(pthread_sigmask(SIG_BLOCK, &mask, NULL));

regress/lib/libpthread/sigmask/sigmask.c

36

r = pthread_sigmask(-1, &mask, NULL);

regress/lib/libpthread/sigmask/sigmask.c

46

CHECKr(sigwait(&mask, &sig));

regress/lib/libpthread/sigmask/sigmask.c

60

CHECKr(pthread_sigmask(SIG_UNBLOCK, &mask, NULL));

regress/lib/libpthread/signal/signal.c

20

sigset_t mask;

regress/lib/libpthread/signal/signal.c

23

sigfillset(&mask);

regress/lib/libpthread/signal/signal.c

24

CHECKe(sigprocmask(SIG_SETMASK, &mask, NULL));

regress/sys/fifofs/fifotest.c

144

sigset_t mask, omask;

regress/sys/fifofs/fifotest.c

147

sigemptyset(&mask);

regress/sys/fifofs/fifotest.c

148

sigaddset(&mask, SIGUSR1);

regress/sys/fifofs/fifotest.c

149

sigprocmask(SIG_BLOCK, &mask, &omask);

regress/sys/fifofs/fifotest.c

165

sigemptyset(&mask);

regress/sys/fifofs/fifotest.c

166

sigsuspend(&mask);

regress/sys/kern/kqueue/kqueue-signal.c

55

sigset_t mask;

regress/sys/kern/kqueue/kqueue-signal.c

85

sigemptyset(&mask);

regress/sys/kern/kqueue/kqueue-signal.c

86

sigaddset(&mask, SIGUSR1);

regress/sys/kern/kqueue/kqueue-signal.c

87

sigaddset(&mask, SIGUSR2);

regress/sys/kern/kqueue/kqueue-signal.c

88

sigprocmask(SIG_BLOCK, &mask, NULL);

regress/sys/kern/signal/sigio/util.c

80

sigset_t mask;

regress/sys/kern/signal/sigio/util.c

82

sigemptyset(&mask);

regress/sys/kern/signal/sigio/util.c

83

sigaddset(&mask, SIGCHLD);

regress/sys/kern/signal/sigio/util.c

84

sigaddset(&mask, SIGIO);

regress/sys/kern/signal/sigio/util.c

85

sigaddset(&mask, SIGURG);

regress/sys/kern/signal/sigio/util.c

86

sigprocmask(SIG_BLOCK, &mask, NULL);

regress/sys/kern/signal/signal-stress/signal-stress.c

36

sigset_t mask, oldmask;

regress/sys/kern/signal/signal-stress/signal-stress.c

61

sigemptyset(&mask);

regress/sys/kern/signal/signal-stress/signal-stress.c

62

sigaddset(&mask, SIGUSR1);

regress/sys/kern/signal/signal-stress/signal-stress.c

63

sigaddset(&mask, SIGUSR2);

regress/sys/kern/signal/signal-stress/signal-stress.c

65

sigprocmask(SIG_BLOCK, &mask, &oldmask);

regress/sys/net/rtable/util.c

114

struct sockaddr *mask = (struct sockaddr *)&ms;

regress/sys/net/rtable/util.c

124

plen = inet_net_ptosa(af, string, dst, mask);

regress/sys/net/rtable/util.c

132

rt_maskedcopy(dst, ndst, mask);

regress/sys/net/rtable/util.c

134

if ((error = rtable_insert(rid, ndst, mask, NULL, 0, rt)) != 0) {

regress/sys/net/rtable/util.c

138

nrt = rtable_lookup(rid, dst, mask, NULL, RTP_ANY);

regress/sys/net/rtable/util.c

155

struct sockaddr *mask = (struct sockaddr *)&ms;

regress/sys/net/rtable/util.c

160

plen = inet_net_ptosa(af, string, dst, mask);

regress/sys/net/rtable/util.c

164

rt = rtable_lookup(0, dst, mask, NULL, RTP_ANY);

regress/sys/net/rtable/util.c

171

assert(rt_plen(rt) == rtable_satoplen(af, mask));

regress/sys/net/rtable/util.c

173

if ((error = rtable_delete(0, dst, mask, rt)) != 0) {

regress/sys/net/rtable/util.c

178

nrt = rtable_lookup(0, dst, mask, NULL, RTP_ANY);

regress/sys/net/rtable/util.c

201

struct sockaddr *mask = (struct sockaddr *)&ms;

regress/sys/net/rtable/util.c

206

plen = inet_net_ptosa(af, string, dst, mask);

regress/sys/net/rtable/util.c

210

rt = rtable_lookup(0, dst, mask, NULL, RTP_ANY);

regress/sys/net/rtable/util.c

216

assert(rt_plen(rt) == rtable_satoplen(af, mask));

regress/sys/net/rtable/util.c

263

struct sockaddr *mask = rt_plen2mask(rt, &sa_mask);

regress/sys/net/rtable/util.c

267

assert(rt_plen(rt) == rtable_satoplen(af, mask));

regress/sys/net/rtable/util.c

270

if ((error = rtable_delete(0, rt_key(rt), mask, rt)) != 0) {

regress/sys/netinet/bindconnect/bindconnect.c

136

mask.au_inaddr.s_addr;

regress/sys/netinet/bindconnect/bindconnect.c

139

~mask.au_inaddr.s_addr & arc4random();

regress/sys/netinet/bindconnect/bindconnect.c

145

mask.au_in6addr.s6_addr32[0];

regress/sys/netinet/bindconnect/bindconnect.c

147

mask.au_in6addr.s6_addr32[1];

regress/sys/netinet/bindconnect/bindconnect.c

149

mask.au_in6addr.s6_addr32[2];

regress/sys/netinet/bindconnect/bindconnect.c

151

mask.au_in6addr.s6_addr32[3];

regress/sys/netinet/bindconnect/bindconnect.c

154

~mask.au_in6addr.s6_addr32[3] & arc4random();

regress/sys/netinet/bindconnect/bindconnect.c

391

in_prefixlen2mask(&mask.au_inaddr, prefix);

regress/sys/netinet/bindconnect/bindconnect.c

393

in6_prefixlen2mask(&mask.au_in6addr, prefix);

regress/sys/netinet/bindconnect/bindconnect.c

58

union inaddr_union addr, mask;

regress/usr.sbin/bgpd/unittests/chash_sub_test.c

29

uint64_t mask;

regress/usr.sbin/bgpd/unittests/chash_sub_test.c

38

memset(&mask, 0x80, sizeof(mask));

regress/usr.sbin/bgpd/unittests/chash_sub_test.c

42

rv = ch_meta_locate(&test, mask);

regress/usr.sbin/bgpd/unittests/chash_sub_test.c

57

rv = ch_meta_locate(&test, mask);

regress/usr.sbin/bgpd/unittests/chash_sub_test.c

68

rv = ch_meta_locate(&test, mask);

regress/usr.sbin/bgpd/unittests/chash_sub_test.c

79

rv = ch_meta_locate(&test, mask);

regress/usr.sbin/bgpd/unittests/rde_trie_test.c

67

int mask = 128;

regress/usr.sbin/bgpd/unittests/rde_trie_test.c

75

mask = strtonum(p+1, 0, 128, &errstr);

regress/usr.sbin/bgpd/unittests/rde_trie_test.c

91

*len = mask;

sbin/dhcp6leased/dhcp6leased.c

750

memcpy(&in6_addreq.ifra_prefixmask.sin6_addr, &address->mask,

sbin/dhcp6leased/dhcp6leased.c

804

struct sockaddr_in6 dst, gw, mask;

sbin/dhcp6leased/dhcp6leased.c

854

memset(&mask, 0, sizeof(mask));

sbin/dhcp6leased/dhcp6leased.c

855

mask.sin6_family = AF_INET6;

sbin/dhcp6leased/dhcp6leased.c

856

mask.sin6_len = sizeof(struct sockaddr_in6);

sbin/dhcp6leased/dhcp6leased.c

857

memcpy(&mask.sin6_addr, &reject_route->mask, sizeof(mask.sin6_addr));

sbin/dhcp6leased/dhcp6leased.c

859

iov[iovcnt].iov_base = &mask;

sbin/dhcp6leased/dhcp6leased.c

860

iov[iovcnt++].iov_len = sizeof(mask);

sbin/dhcp6leased/dhcp6leased.c

861

rtm.rtm_msglen += sizeof(mask);

sbin/dhcp6leased/dhcp6leased.c

862

padlen = ROUNDUP(sizeof(mask)) - sizeof(mask);

sbin/dhcp6leased/dhcp6leased.h

140

struct in_addr mask;

sbin/dhcp6leased/engine.c

1026

memset(&mask, 0, sizeof(mask));

sbin/dhcp6leased/engine.c

1027

in6_prefixlen2mask(&mask, prefix->prefix_len);

sbin/dhcp6leased/engine.c

1029

prefix->prefix.s6_addr[i] &= mask.s6_addr[i];

sbin/dhcp6leased/engine.c

1523

in6_prefixlen2mask(&address.mask, pd_conf->prefix_len);

sbin/dhcp6leased/engine.c

1552

in6_prefixlen2mask(&imsg.mask, prefix_len);

sbin/dhcp6leased/engine.c

974

struct in6_addr mask;

sbin/dhcp6leased/engine.h

22

struct in6_addr mask;

sbin/dhcp6leased/engine.h

31

struct in6_addr mask;

sbin/dhcpleased/dhcpleased.c

1011

struct sockaddr_in dst, mask, gw, ifa;

sbin/dhcpleased/dhcpleased.c

1024

memset(&mask, 0, sizeof(mask));

sbin/dhcpleased/dhcpleased.c

1025

mask.sin_family = AF_INET;

sbin/dhcpleased/dhcpleased.c

1026

mask.sin_len = sizeof(mask);

sbin/dhcpleased/dhcpleased.c

1032

addrnet = imsg->addr.s_addr & imsg->mask.s_addr;

sbin/dhcpleased/dhcpleased.c

1036

mask.sin_addr = imsg->routes[i].mask;

sbin/dhcpleased/dhcpleased.c

1042

imsg->rdomain, &dst, &mask, &ifa, NULL,

sbin/dhcpleased/dhcpleased.c

1044

} else if (mask.sin_addr.s_addr == INADDR_ANY) {

sbin/dhcpleased/dhcpleased.c

1046

gwnet = gw.sin_addr.s_addr & imsg->mask.s_addr;

sbin/dhcpleased/dhcpleased.c

1054

mask.sin_addr.s_addr = 0xffffffff;

sbin/dhcpleased/dhcpleased.c

1056

imsg->rdomain, &gw, &mask, &ifa, NULL,

sbin/dhcpleased/dhcpleased.c

1058

mask.sin_addr = imsg->routes[i].mask;

sbin/dhcpleased/dhcpleased.c

1064

imsg->rdomain, &dst, &mask, &gw, NULL, 0);

sbin/dhcpleased/dhcpleased.c

1068

imsg->rdomain, &dst, &mask, &gw, &ifa,

sbin/dhcpleased/dhcpleased.c

1074

&dst, &mask, &gw, NULL, RTF_GATEWAY);

sbin/dhcpleased/dhcpleased.c

1083

sockaddr_in *dst, struct sockaddr_in *mask, struct sockaddr_in *gw,

sbin/dhcpleased/dhcpleased.c

1132

iov[iovcnt].iov_base = mask;

sbin/dhcpleased/dhcpleased.c

1133

iov[iovcnt++].iov_len = mask->sin_len;

sbin/dhcpleased/dhcpleased.c

1134

rtm.rtm_msglen += mask->sin_len;

sbin/dhcpleased/dhcpleased.c

1135

padlen = ROUNDUP(mask->sin_len) - mask->sin_len;

sbin/dhcpleased/dhcpleased.c

833

struct in_addr addr, mask;

sbin/dhcpleased/dhcpleased.c

843

mask = ((struct sockaddr_in *)ifa->ifa_netmask)->sin_addr;

sbin/dhcpleased/dhcpleased.c

846

if (imsg->mask.s_addr == mask.s_addr)

sbin/dhcpleased/dhcpleased.c

866

req_sin_mask->sin_addr = imsg->mask;

sbin/dhcpleased/dhcpleased.h

190

struct in_addr mask;

sbin/dhcpleased/dhcpleased.h

241

struct in_addr mask;

sbin/dhcpleased/engine.c

110

struct in_addr mask;

sbin/dhcpleased/engine.c

1161

routes[routes_len].mask.s_addr =

sbin/dhcpleased/engine.c

1165

routes[routes_len].mask.s_addr =

sbin/dhcpleased/engine.c

1321

iface->mask = subnet_mask;

sbin/dhcpleased/engine.c

1706

imsg.mask = iface->mask;

sbin/dhcpleased/engine.c

1746

imsg.mask = iface->mask;

sbin/dhcpleased/engine.c

1759

iface->mask.s_addr = INADDR_ANY;

sbin/dhcpleased/engine.c

1775

imsg.mask = iface->mask;

sbin/dhcpleased/engine.c

619

cei.mask = iface->mask;

sbin/dhcpleased/engine.h

23

struct in_addr mask;

sbin/fdisk/gpt.c

1085

uint32_t i, byte, crc, mask;

sbin/fdisk/gpt.c

1093

mask = -(crc & 1);

sbin/fdisk/gpt.c

1094

crc = (crc >> 1) ^ (0xEDB88320 & mask);

sbin/growfs/growfs.c

1534

unsigned char mask;

sbin/growfs/growfs.c

1540

mask = 0x0f << ((h & 0x1) << 2);

sbin/growfs/growfs.c

1541

return ((cp[h >> 1] & mask) == mask);

sbin/growfs/growfs.c

1543

mask = 0x03 << ((h & 0x3) << 1);

sbin/growfs/growfs.c

1544

return ((cp[h >> 2] & mask) == mask);

sbin/growfs/growfs.c

1546

mask = 0x01 << (h & 0x7);

sbin/growfs/growfs.c

1547

return ((cp[h >> 3] & mask) == mask);

sbin/iked/ikev2.c

7166

uint32_t mask, host, lower, upper, start, nhost;

sbin/iked/ikev2.c

7243

mask = prefixlen2mask(ikecfg->cfg.address.addr_mask);

sbin/iked/ikev2.c

7254

if ((in4->sin_addr.s_addr & mask) !=

sbin/iked/ikev2.c

7255

(cfg4->sin_addr.s_addr & mask)) {

sbin/iked/ikev2.c

7281

lower = ntohl(cfg4->sin_addr.s_addr & ~mask);

sbin/iked/ikev2.c

7293

mask = (ikecfg->cfg.address.addr_mask >= 96)

sbin/iked/ikev2.c

7297

lower = ntohl(lower & ~mask);

sbin/iked/ikev2.c

7305

upper = ntohl(~mask);

sbin/iked/ikev2.c

7316

__func__, mask, start, lower, host, upper);

sbin/iked/ikev2.c

7320

(cfg4->sin_addr.s_addr & mask) | htonl(host);

sbin/iked/ikev2.c

7326

nhost = (nhost & mask) | htonl(host);

sbin/iked/parse.y

2237

int mask = -1;

sbin/iked/parse.y

2245

mask = strtonum(p+1, 0, 128, &errstr);

sbin/iked/parse.y

2253

if ((ipa = host_if(ps, mask)) == NULL &&

sbin/iked/parse.y

2254

(ipa = host_ip(ps, mask)) == NULL &&

sbin/iked/parse.y

2255

(ipa = host_dns(ps, mask)) == NULL)

sbin/iked/parse.y

2264

host_ip(const char *s, int mask)

sbin/iked/parse.y

2287

set_ipmask(ipa, mask);

sbin/iked/parse.y

2293

if (mask > -1) {

sbin/iked/parse.y

2295

if (asprintf(&ipa->name, "%s/%d", hbuf, mask) == -1)

sbin/iked/parse.y

2308

host_dns(const char *s, int mask)

sbin/iked/parse.y

2355

set_ipmask(ipa, mask == -1 ? 32 : mask);

sbin/iked/parse.y

2357

if (mask != -1)

sbin/iked/parse.y

2367

host_if(const char *s, int mask)

sbin/iked/parse.y

2433

n->mask = mask2prefixlen((struct sockaddr *)sa_in);

sbin/iked/parse.y

2438

n->mask = mask2prefixlen6((struct sockaddr *)sa_in6);

sbin/iked/parse.y

2599

address->mask = address->af == AF_INET ? 32 : 128;

sbin/iked/parse.y

2601

address->mask = b;

sbin/iked/parse.y

2851

pol.pol_local.addr_mask = ipa->mask;

sbin/iked/parse.y

2860

pol.pol_peer.addr_mask = ipb->mask;

sbin/iked/parse.y

3124

cfg->cfg.address.addr_mask = ipa->mask;

sbin/iked/parse.y

3230

flow->flow_src.addr_mask = ipa->mask;

sbin/iked/parse.y

3237

flow->flow_dst.addr_mask = ipb->mask;

sbin/iked/parse.y

3246

flow->flow_prenat.addr_mask = ippn->mask;

sbin/iked/parse.y

339

uint8_t mask;

sbin/iked/sntrup761.c

1239

int mask;

sbin/iked/sntrup761.c

1244

mask = Ciphertexts_diff_mask(c,cnew);

sbin/iked/sntrup761.c

1245

for (i = 0;i < Inputs_bytes;++i) r_enc[i] ^= mask&(r_enc[i]^rho[i]);

sbin/iked/sntrup761.c

1246

HashSession(k,1+mask,r_enc,c);

sbin/iked/sntrup761.c

125

uint32 mask;

sbin/iked/sntrup761.c

157

mask = -(x>>31);

sbin/iked/sntrup761.c

158

x += mask&(uint32)m; *q += mask;

sbin/iked/sntrup761.c

179

uint32 mask;

sbin/iked/sntrup761.c

184

mask = -(uint32)(ur>>15);

sbin/iked/sntrup761.c

185

ur += mask&m; uq += mask;

sbin/iked/sntrup761.c

764

int mask;

sbin/iked/sntrup761.c

772

mask = Weightw_mask(ev); /* 0 if weight w, else -1 */

sbin/iked/sntrup761.c

773

for (i = 0;i < w;++i) r[i] = ((ev[i]^1)&~mask)^1;

sbin/iked/sntrup761.c

774

for (i = w;i < p;++i) r[i] = ev[i]&~mask;

sbin/iked/util.c

624

prefixlen2mask6(uint8_t prefixlen, uint32_t *mask)

sbin/iked/util.c

639

memcpy(mask, &s6, sizeof(s6));

sbin/iked/vroute.c

228

int mask, unsigned int ifidx)

sbin/iked/vroute.c

242

bzero(&mask, sizeof(mask));

sbin/iked/vroute.c

243

mask4.sin_addr.s_addr = prefixlen2mask(mask ? mask : 32);

sbin/iked/vroute.c

253

prefixlen2mask6(mask ? mask : 128,

sbin/iked/vroute.c

277

struct sockaddr *addr, *mask;

sbin/iked/vroute.c

297

if (left < sizeof(*mask))

sbin/iked/vroute.c

299

mask = (struct sockaddr *) ptr;

sbin/iked/vroute.c

300

if (mask->sa_family != af)

sbin/iked/vroute.c

303

if (left < mask->sa_len)

sbin/iked/vroute.c

305

ptr += mask->sa_len;

sbin/iked/vroute.c

306

left -= mask->sa_len;

sbin/iked/vroute.c

317

vroute_insertaddr(env, ifidx, addr, mask);

sbin/iked/vroute.c

319

vroute_removeaddr(env, ifidx, addr, mask);

sbin/iked/vroute.c

322

return (vroute_doaddr(env, ifname, addr, mask, add));

sbin/iked/vroute.c

380

struct sockaddr *mask)

sbin/iked/vroute.c

393

if (mask != NULL) {

sbin/iked/vroute.c

395

memcpy(&route->vr_mask, mask, mask->sa_len);

sbin/iked/vroute.c

404

struct sockaddr *mask)

sbin/iked/vroute.c

412

if (mask && !(route->vr_flags & RTA_NETMASK))

sbin/iked/vroute.c

414

if (mask &&

sbin/iked/vroute.c

415

sockaddr_cmp(mask, (struct sockaddr *)&route->vr_mask, -1))

sbin/iked/vroute.c

459

struct sockaddr *mask)

sbin/iked/vroute.c

469

memcpy(&vaddr->va_mask, mask, mask->sa_len);

sbin/iked/vroute.c

477

struct sockaddr *mask)

sbin/iked/vroute.c

485

if (sockaddr_cmp(mask, (struct sockaddr *)&vaddr->va_mask, -1))

sbin/iked/vroute.c

496

uint8_t mask, struct sockaddr *ifa)

sbin/iked/vroute.c

498

return (vroute_setroute(env, rdomain, dst, mask, ifa,

sbin/iked/vroute.c

504

uint8_t mask, struct sockaddr *addr)

sbin/iked/vroute.c

506

return (vroute_setroute(env, rdomain, dst, mask, addr,

sbin/iked/vroute.c

512

uint8_t mask, struct sockaddr *addr)

sbin/iked/vroute.c

514

return (vroute_setroute(env, rdomain, dst, mask, addr,

sbin/iked/vroute.c

520

uint8_t mask, struct sockaddr *addr, int type)

sbin/iked/vroute.c

546

in->sin_addr.s_addr = prefixlen2mask(mask);

sbin/iked/vroute.c

555

prefixlen2mask6(mask,

sbin/iked/vroute.c

576

struct sockaddr *dest, *mask = NULL, *gateway = NULL;

sbin/iked/vroute.c

606

mask = (struct sockaddr *)ptr;

sbin/iked/vroute.c

607

if (left < mask->sa_len)

sbin/iked/vroute.c

609

socket_setport(mask, 0);

sbin/iked/vroute.c

610

ptr += mask->sa_len;

sbin/iked/vroute.c

611

left -= mask->sa_len;

sbin/iked/vroute.c

639

vroute_insertroute(env, rdomain, dest, mask);

sbin/iked/vroute.c

641

vroute_removeroute(env, rdomain, dest, mask);

sbin/iked/vroute.c

643

dest, mask, gateway, NULL));

sbin/iked/vroute.c

651

struct sockaddr_storage mask;

sbin/iked/vroute.c

670

bzero(&mask, sizeof(mask));

sbin/iked/vroute.c

685

(struct sockaddr *)&dest, (struct sockaddr *)&mask,

sbin/iked/vroute.c

699

(struct sockaddr *)&dest, (struct sockaddr *)&mask,

sbin/iked/vroute.c

772

struct sockaddr *dest, struct sockaddr *mask, struct sockaddr *addr, int *need_gw)

sbin/iked/vroute.c

823

iov[iovcnt].iov_base = mask;

sbin/iked/vroute.c

824

iov[iovcnt].iov_len = mask->sa_len;

sbin/iked/vroute.c

826

padlen = ROUNDUP(mask->sa_len) - mask->sa_len;

sbin/iked/vroute.c

846

addrs & RTA_NETMASK ? print_addr(mask) : "<>",

sbin/iked/vroute.c

862

return (vroute_process(env, len, &m_rtmsg, dest, mask, addr, need_gw));

sbin/iked/vroute.c

871

struct sockaddr *dest, struct sockaddr *mask, struct sockaddr *addr, int *need_gw)

sbin/iked/vroute.c

904

memcpy(mask, cp, sa->sa_len);

sbin/iked/vroute.c

920

struct sockaddr *mask, int add)

sbin/iked/vroute.c

935

memcpy(&req.ifra_mask, mask, sizeof(req.ifra_addr));

sbin/iked/vroute.c

938

add ? "add" : "del", print_addr(addr), print_addr(mask));

sbin/iked/vroute.c

954

memcpy(&req6.ifra_prefixmask, mask,

sbin/iked/vroute.c

958

add ? "add" : "del", print_addr(addr), print_addr(mask));

sbin/init/init.c

1058

sigemptyset(&mask);

sbin/init/init.c

1059

sigprocmask(SIG_SETMASK, &mask, NULL);

sbin/init/init.c

196

sigset_t mask;

sbin/init/init.c

265

sigfillset(&mask);

sbin/init/init.c

266

delset(&mask, SIGABRT, SIGFPE, SIGILL, SIGSEGV, SIGBUS, SIGSYS,

sbin/init/init.c

269

sigprocmask(SIG_SETMASK, &mask, NULL);

sbin/init/init.c

493

sigset_t mask;

sbin/init/init.c

589

sigemptyset(&mask);

sbin/init/init.c

590

sigprocmask(SIG_SETMASK, &mask, NULL);

sbin/init/init.c

952

sigset_t mask;

sbin/init/init.c

964

sigemptyset(&mask);

sbin/init/init.c

965

sigprocmask(SIG_SETMASK, &mask, NULL);

sbin/init/init.c

988

sigset_t mask;

sbin/ipsecctl/ike.c

635

char mask[NI_MAXHOST], *network, *p;

sbin/ipsecctl/ike.c

640

bzero(mask, sizeof(mask));

sbin/ipsecctl/ike.c

656

if (getnameinfo(sa, sa->sa_len, mask, sizeof(mask), NULL, 0,

sbin/ipsecctl/ike.c

668

fprintf(fd, SET "[%s]:Netmask=%s force\n", p2xid, mask);

sbin/ipsecctl/ike.c

681

ike_section_p2ids_net(&src->mask, src->af, src->name,

sbin/ipsecctl/ike.c

693

ike_section_p2ids_net(&src->srcnat->mask, src->af, src->srcnat->name,

sbin/ipsecctl/ike.c

705

ike_section_p2ids_net(&dst->mask, dst->af, dst->name,

sbin/ipsecctl/ipsecctl.c

403

bits = unmask(&ipa->mask);

sbin/ipsecctl/ipsecctl.h

112

struct ipsec_addr mask;

sbin/ipsecctl/parse.y

1651

int mask, cont = 1;

sbin/ipsecctl/parse.y

1656

mask = strtol(p + 1, &q, 0);

sbin/ipsecctl/parse.y

1657

if (errno == ERANGE || !q || *q || mask > 128 || q == (p + 1))

sbin/ipsecctl/parse.y

1665

mask = -1;

sbin/ipsecctl/parse.y

1669

if (cont && (ipa = host_if(ps, mask)) != NULL)

sbin/ipsecctl/parse.y

1673

if (cont && (ipa = host_v4(s, mask == -1 ? 32 : mask)) != NULL)

sbin/ipsecctl/parse.y

1677

if (cont && (ipa = host_v6(ps, mask == -1 ? 128 : mask)) != NULL)

sbin/ipsecctl/parse.y

1681

if (cont && mask == -1 && (ipa = host_dns(s, mask)) != NULL)

sbin/ipsecctl/parse.y

1741

host_v4(const char *s, int mask)

sbin/ipsecctl/parse.y

1776

host_dns(const char *s, int mask)

sbin/ipsecctl/parse.y

1838

set_ipmask(ipa, mask == -1 ? 32 : mask);

sbin/ipsecctl/parse.y

1840

if (mask != -1)

sbin/ipsecctl/parse.y

1850

host_if(const char *s, int mask)

sbin/ipsecctl/parse.y

1904

memcpy(&n->mask.v4, &((struct sockaddr_in *)

sbin/ipsecctl/parse.y

1912

memcpy(&n->mask.v6, &((struct sockaddr_in6 *)

sbin/ipsecctl/parse.y

2071

ipa = &address->mask;

sbin/ipsecctl/pfkey.c

1062

bcopy(&sa_in->sin_addr, &rule->src->mask.v4,

sbin/ipsecctl/pfkey.c

1067

bcopy(&sa_in6->sin6_addr, &rule->src->mask.v6,

sbin/ipsecctl/pfkey.c

1091

bcopy(&sa_in->sin_addr, &rule->dst->mask.v4,

sbin/ipsecctl/pfkey.c

1096

bcopy(&sa_in6->sin6_addr, &rule->dst->mask.v6,

sbin/ipsecctl/pfkey.c

118

((struct sockaddr_in *)&dmask)->sin_addr = dst->mask.v4;

sbin/ipsecctl/pfkey.c

127

((struct sockaddr_in6 *)&dmask)->sin6_addr = dst->mask.v6;

sbin/ipsecctl/pfkey.c

90

((struct sockaddr_in *)&smask)->sin_addr = src->mask.v4;

sbin/ipsecctl/pfkey.c

99

((struct sockaddr_in6 *)&smask)->sin6_addr = src->mask.v6;

sbin/isakmpd/ipsec.c

2003

struct sockaddr **mask, u_int8_t *tproto, u_int16_t *port)

sbin/isakmpd/ipsec.c

2078

if (text2sockaddr(netmask, NULL, mask, af, 1)) {

sbin/isakmpd/ipsec.c

2086

free(*mask);

sbin/isakmpd/ipsec.c

2127

char *addr = 0, *mask = 0;

sbin/isakmpd/ipsec.c

2147

util_ntoa(&mask, AF_INET, id + ISAKMP_ID_DATA_OFF + 4);

sbin/isakmpd/ipsec.c

2148

snprintf(buf, size, "%s/%s", addr, mask);

sbin/isakmpd/ipsec.c

2158

util_ntoa(&mask, AF_INET6, id + ISAKMP_ID_DATA_OFF +

sbin/isakmpd/ipsec.c

2160

snprintf(buf, size, "%s/%s", addr, mask);

sbin/isakmpd/ipsec.c

2189

free(mask);

sbin/isakmpd/ipsec.c

2214

struct sockaddr *addr, *mask;

sbin/isakmpd/ipsec.c

2220

if (ipsec_get_id(section, &id, &addr, &mask, &tproto, &port))

sbin/isakmpd/ipsec.c

2228

*sz += sockaddr_addrlen(mask);

sbin/isakmpd/ipsec.c

2235

free(mask);

sbin/isakmpd/ipsec.c

2246

sockaddr_addrdata(mask), sockaddr_addrlen(mask));

sbin/isakmpd/ipsec.c

2252

free(mask);

sbin/isakmpd/monitor.c

240

mode_t mask, cur_umask;

sbin/isakmpd/monitor.c

264

mask = S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP | S_IROTH | S_IWOTH;

sbin/isakmpd/monitor.c

265

mask &= ~cur_umask;

sbin/isakmpd/monitor.c

267

fd = monitor_open(path, flags, mask);

sbin/isakmpd/pf_key_v2.c

1462

pf_key_v2_mask_to_bits(u_int32_t mask)

sbin/isakmpd/pf_key_v2.c

1464

u_int32_t hmask = ntohl(mask);

sbin/isakmpd/pf_key_v2.c

1470

pf_key_v2_mask6_to_bits(u_int8_t *mask)

sbin/isakmpd/pf_key_v2.c

1474

bit_ffc(mask, 128, &n);

sbin/isakmpd/pf_key_v2.c

2281

mask4len(const struct sockaddr_in *mask)

sbin/isakmpd/pf_key_v2.c

2287

for (m = 0x80000000; m & ntohl(mask->sin_addr.s_addr); m >>= 1)

sbin/isakmpd/pf_key_v2.c

2299

mask6len(const struct sockaddr_in6 *mask)

sbin/isakmpd/pf_key_v2.c

2306

for (m = 0x80; m & mask->sin6_addr.s6_addr8[i]; m >>= 1)

sbin/isakmpd/policy.c

1101

struct in6_addr net, mask;

sbin/isakmpd/policy.c

1108

16, &mask, sizeof(mask));

sbin/isakmpd/policy.c

1112

mask.s6_addr[i];

sbin/isakmpd/policy.c

1120

~mask.s6_addr[i];

sbin/isakmpd/policy.c

1425

struct in6_addr net, mask;

sbin/isakmpd/policy.c

1432

16, &mask, sizeof(mask));

sbin/isakmpd/policy.c

1436

mask.s6_addr[i];

sbin/isakmpd/policy.c

1444

~mask.s6_addr[i];

sbin/isakmpd/policy.c

809

struct in6_addr net, mask;

sbin/isakmpd/policy.c

816

&mask, sizeof(mask));

sbin/isakmpd/policy.c

819

net.s6_addr[i] &= mask.s6_addr[i];

sbin/isakmpd/policy.c

826

net.s6_addr[i] |= ~mask.s6_addr[i];

sbin/mount/mount.c

585

if (verbose || msdosfs_args->mask != 0755)

sbin/mount/mount.c

587

"mask", msdosfs_args->mask);

sbin/mount_msdos/mount_msdos.c

128

args.mask = sb.st_mode & (S_IRWXU | S_IRWXG | S_IRWXO);

sbin/mount_msdos/mount_msdos.c

94

args.mask = a_mask(optarg);

sbin/newfs/mkfs.c

1054

unsigned char mask;

sbin/newfs/mkfs.c

1060

mask = 0x0f << ((h & 0x1) << 2);

sbin/newfs/mkfs.c

1061

return ((cp[h >> 1] & mask) == mask);

sbin/newfs/mkfs.c

1063

mask = 0x03 << ((h & 0x3) << 1);

sbin/newfs/mkfs.c

1064

return ((cp[h >> 2] & mask) == mask);

sbin/newfs/mkfs.c

1066

mask = 0x01 << (h & 0x7);

sbin/newfs/mkfs.c

1067

return ((cp[h >> 3] & mask) == mask);

sbin/newfs_ext2fs/mke2fs.c

1410

skpc(int mask, size_t size, uint8_t *cp)

sbin/newfs_ext2fs/mke2fs.c

1415

while (cp < end && *cp == (uint8_t)mask)

sbin/newfs_ext2fs/mke2fs.c

764

uint32_t mask;

sbin/newfs_ext2fs/mke2fs.c

811

if (fsm->mask == 0)

sbin/newfs_ext2fs/mke2fs.c

814

if ((v & fsm->mask) == fsm->magic ||

sbin/newfs_ext2fs/mke2fs.c

815

(swap32(v) & fsm->mask) == fsm->magic)

sbin/pfctl/parse.y

3166

unmask(&b->addr.v.a.mask) !=

sbin/pfctl/parse.y

3168

unmask(&e->addr.v.a.mask) !=

sbin/pfctl/parse.y

3179

memcpy(&b->addr.v.a.mask, &e->addr.v.a.addr,

sbin/pfctl/parse.y

3180

sizeof(b->addr.v.a.mask));

sbin/pfctl/parse.y

4663

PF_AZERO(&h->addr.v.a.mask, af)))

sbin/pfctl/parse.y

4673

bits = unmask(&h->addr.v.a.mask);

sbin/pfctl/parse.y

5316

if (PF_AZERO(&r->src.addr.v.a.mask, af) ||

sbin/pfctl/parse.y

5317

PF_AZERO(&r->nat.addr.v.a.mask, af)) {

sbin/pfctl/pf_print_state.c

113

PF_AZERO(&addr->v.a.mask, AF_INET6))) {

sbin/pfctl/pf_print_state.c

114

int bits = unmask(&addr->v.a.mask);

sbin/pfctl/pf_print_state.c

175

memset(&aw.v.a.mask, 0xff, sizeof(aw.v.a.mask));

sbin/pfctl/pf_print_state.c

86

print_addr_str(af, &addr->v.a.mask);

sbin/pfctl/pf_print_state.c

91

PF_AZERO(&addr->v.a.mask, AF_INET6))

sbin/pfctl/pfctl.c

476

pfctl_addrprefix(char *addr, struct pf_addr *mask, int numeric)

sbin/pfctl/pfctl.c

510

bzero(&mask->v4, sizeof(mask->v4));

sbin/pfctl/pfctl.c

511

mask->v4.s_addr = htonl((u_int32_t)

sbin/pfctl/pfctl.c

515

bzero(&mask->v6, sizeof(mask->v6));

sbin/pfctl/pfctl.c

517

memset((void *)&mask->v6, 0xff, q);

sbin/pfctl/pfctl.c

519

*((u_char *)&mask->v6 + q) =

sbin/pfctl/pfctl.c

538

memset(&psnk.psnk_src.addr.v.a.mask, 0xff,

sbin/pfctl/pfctl.c

539

sizeof(psnk.psnk_src.addr.v.a.mask));

sbin/pfctl/pfctl.c

544

&psnk.psnk_src.addr.v.a.mask, (opts & PF_OPT_NODNS));

sbin/pfctl/pfctl.c

561

memset(&psnk.psnk_dst.addr.v.a.mask, 0xff,

sbin/pfctl/pfctl.c

562

sizeof(psnk.psnk_dst.addr.v.a.mask));

sbin/pfctl/pfctl.c

565

&psnk.psnk_dst.addr.v.a.mask,

sbin/pfctl/pfctl.c

614

memset(&psk.psk_src.addr.v.a.mask, 0xff,

sbin/pfctl/pfctl.c

615

sizeof(psk.psk_src.addr.v.a.mask));

sbin/pfctl/pfctl.c

625

&psk.psk_src.addr.v.a.mask, (opts & PF_OPT_NODNS));

sbin/pfctl/pfctl.c

642

memset(&psk.psk_dst.addr.v.a.mask, 0xff,

sbin/pfctl/pfctl.c

643

sizeof(psk.psk_dst.addr.v.a.mask));

sbin/pfctl/pfctl.c

646

&psk.psk_dst.addr.v.a.mask,

sbin/pfctl/pfctl.c

837

memset(&addr->addr.v.a.mask, 0xff, sizeof(struct pf_addr));

sbin/pfctl/pfctl_optimize.c

1050

memcmp(&a->dst.addr.v.a.mask, &b->dst.addr.v.a.mask,

sbin/pfctl/pfctl_optimize.c

1051

sizeof(a->dst.addr.v.a.mask)) ||

sbin/pfctl/pfctl_optimize.c

1061

memcmp(&a->dst.addr.v.a.mask, &b->dst.addr.v.a.mask,

sbin/pfctl/pfctl_optimize.c

1062

sizeof(a->dst.addr.v.a.mask)))

sbin/pfctl/pfctl_optimize.c

1122

memcmp(&a->src.addr.v.a.mask, &b->src.addr.v.a.mask,

sbin/pfctl/pfctl_optimize.c

1123

sizeof(a->src.addr.v.a.mask)) ||

sbin/pfctl/pfctl_optimize.c

1133

memcmp(&a->src.addr.v.a.mask, &b->src.addr.v.a.mask,

sbin/pfctl/pfctl_optimize.c

1134

sizeof(a->src.addr.v.a.mask)))

sbin/pfctl/pfctl_optimize.c

1221

unmask(&node_host.addr.v.a.mask));

sbin/pfctl/pfctl_optimize.c

1536

!sub->src.neg && super->src.addr.v.a.mask.addr32[0] == 0 &&

sbin/pfctl/pfctl_optimize.c

1537

super->src.addr.v.a.mask.addr32[1] == 0 &&

sbin/pfctl/pfctl_optimize.c

1538

super->src.addr.v.a.mask.addr32[2] == 0 &&

sbin/pfctl/pfctl_optimize.c

1539

super->src.addr.v.a.mask.addr32[3] == 0)

sbin/pfctl/pfctl_optimize.c

1545

unmask(&super->src.addr.v.a.mask) <

sbin/pfctl/pfctl_optimize.c

1546

unmask(&sub->src.addr.v.a.mask) &&

sbin/pfctl/pfctl_optimize.c

1549

super->src.addr.v.a.mask.addr32[0]) &&

sbin/pfctl/pfctl_optimize.c

1552

super->src.addr.v.a.mask.addr32[1]) &&

sbin/pfctl/pfctl_optimize.c

1555

super->src.addr.v.a.mask.addr32[2]) &&

sbin/pfctl/pfctl_optimize.c

1558

super->src.addr.v.a.mask.addr32[3])) {

sbin/pfctl/pfctl_optimize.c

1564

!sub->dst.neg && super->dst.addr.v.a.mask.addr32[0] == 0 &&

sbin/pfctl/pfctl_optimize.c

1565

super->dst.addr.v.a.mask.addr32[1] == 0 &&

sbin/pfctl/pfctl_optimize.c

1566

super->dst.addr.v.a.mask.addr32[2] == 0 &&

sbin/pfctl/pfctl_optimize.c

1567

super->dst.addr.v.a.mask.addr32[3] == 0)

sbin/pfctl/pfctl_optimize.c

1573

unmask(&super->dst.addr.v.a.mask) <

sbin/pfctl/pfctl_optimize.c

1574

unmask(&sub->dst.addr.v.a.mask) &&

sbin/pfctl/pfctl_optimize.c

1577

super->dst.addr.v.a.mask.addr32[0]) &&

sbin/pfctl/pfctl_optimize.c

1580

super->dst.addr.v.a.mask.addr32[1]) &&

sbin/pfctl/pfctl_optimize.c

1583

super->dst.addr.v.a.mask.addr32[2]) &&

sbin/pfctl/pfctl_optimize.c

1586

super->dst.addr.v.a.mask.addr32[3])) {

sbin/pfctl/pfctl_parser.c

1352

m = &h->addr.v.a.mask;

sbin/pfctl/pfctl_parser.c

1385

m = &h->addr.v.a.mask;

sbin/pfctl/pfctl_parser.c

1413

if (af == AF_INET && unmask(&n->addr.v.a.mask) > 32)

sbin/pfctl/pfctl_parser.c

1465

copy_satopfaddr(&n->addr.v.a.mask, ifa->ifa_netmask);

sbin/pfctl/pfctl_parser.c

1658

set_ipmask(n, unmask(&p->addr.v.a.mask));

sbin/pfctl/pfctl_parser.c

1700

int mask = -1;

sbin/pfctl/pfctl_parser.c

1708

mask = strtonum(p+1, 0, 128, &errstr);

sbin/pfctl/pfctl_parser.c

1716

if ((h = host_if(ps, mask)) == NULL &&

sbin/pfctl/pfctl_parser.c

1717

(h = host_ip(ps, mask)) == NULL &&

sbin/pfctl/pfctl_parser.c

1718

(h = host_dns(ps, mask, (opts & PF_OPT_NODNS))) == NULL) {

sbin/pfctl/pfctl_parser.c

1734

host_if(const char *s, int mask)

sbin/pfctl/pfctl_parser.c

1759

if ((flags & (PFI_AFLAG_NETWORK|PFI_AFLAG_BROADCAST)) && mask > -1) {

sbin/pfctl/pfctl_parser.c

1767

if (mask > -1)

sbin/pfctl/pfctl_parser.c

1769

set_ipmask(n, mask);

sbin/pfctl/pfctl_parser.c

1778

host_ip(const char *s, int mask)

sbin/pfctl/pfctl_parser.c

1798

if (mask == -1)

sbin/pfctl/pfctl_parser.c

1810

set_ipmask(h, mask);

sbin/pfctl/pfctl_parser.c

1819

host_dns(const char *s, int mask, int numeric)

sbin/pfctl/pfctl_parser.c

1864

set_ipmask(n, mask);

sbin/pfctl/pfctl_parser.c

1956

addr.pfra_net = unmask(&n->addr.v.a.mask);

sbin/pfctl/pfctl_parser.c

429

PF_AZERO(&src->addr.v.a.mask, AF_INET6) &&

sbin/pfctl/pfctl_parser.c

431

PF_AZERO(&dst->addr.v.a.mask, AF_INET6) &&

sbin/pfctl/pfctl_parser.c

672

aw.v.a.mask.addr32[0] = 0xffffffff;

sbin/pfctl/pfctl_parser.c

674

memset(&aw.v.a.mask, 0xff, sizeof(aw.v.a.mask));

sbin/reboot/reboot.c

225

sigfillset(&mask);

sbin/reboot/reboot.c

226

sigprocmask(SIG_BLOCK, &mask, NULL);

sbin/reboot/reboot.c

78

sigset_t mask;

sbin/route/route.c

1697

struct sockaddr *dst = NULL, *gate = NULL, *mask = NULL, *ifa = NULL;

sbin/route/route.c

1735

mask = sa;

sbin/route/route.c

1759

if (dst && mask)

sbin/route/route.c

1760

mask->sa_family = dst->sa_family; /* XXX */

sbin/route/route.c

1763

if (mask) {

sbin/route/route.c

1767

printf(" mask: %s\n", routename(mask));

sbin/route/route.c

422

struct sockaddr *mask, *rti_info[RTAX_MAX];

sbin/route/route.c

429

mask = rti_info[RTAX_NETMASK];

sbin/route/route.c

431

p_sockaddr(sa, mask, rtm->rtm_flags, 20);

sbin/route/route.c

886

u_int32_t mask;

sbin/route/route.c

890

mask = 0;

sbin/route/route.c

894

mask = 0xffffffff << (32 - bits);

sbin/route/route.c

895

net &= mask;

sbin/route/route.c

899

sin->sin_addr.s_addr = htonl(mask);

sbin/route/show.c

301

struct sockaddr *mask, *rti_info[RTAX_MAX];

sbin/route/show.c

329

mask = rti_info[RTAX_NETMASK];

sbin/route/show.c

333

p_sockaddr(sa, mask, rtm->rtm_flags, WID_DST(sa->sa_family));

sbin/route/show.c

387

p_sockaddr(struct sockaddr *sa, struct sockaddr *mask, int flags, int width)

sbin/route/show.c

415

cp = netname((struct sockaddr *)sa6, mask);

sbin/route/show.c

421

if ((flags & RTF_HOST) || mask == NULL)

sbin/route/show.c

424

cp = netname(sa, mask);

sbin/route/show.c

585

in_addr_t mask;

sbin/route/show.c

588

mask = maskp && maskp->sin_len != 0 ? ntohl(maskp->sin_addr.s_addr) : 0;

sbin/route/show.c

594

if (in == INADDR_ANY && mask == INADDR_ANY)

sbin/route/show.c

596

mbits = mask ? 33 - ffs(mask) : 0;

sbin/route/show.c

617

netname6(struct sockaddr_in6 *sa6, struct sockaddr_in6 *mask)

sbin/route/show.c

629

if (mask) {

sbin/route/show.c

630

lim = mask->sin6_len - offsetof(struct sockaddr_in6, sin6_addr);

sbin/route/show.c

633

for (p = (u_char *)&mask->sin6_addr, i = 0; i < lim; p++) {

sbin/route/show.c

713

netname(struct sockaddr *sa, struct sockaddr *mask)

sbin/route/show.c

718

(struct sockaddr_in *)mask);

sbin/route/show.c

721

(struct sockaddr_in6 *)mask);

sbin/scsi/libscsi.c

147

static u_char mask[] = {0, 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f, 0x7f, 0xff};

sbin/scsi/libscsi.c

222

value = (bits >> (shift - width)) & mask[width];

sbin/scsi/libscsi.c

226

shift, bits, value, width, mask[width]);

sbin/slaacd/engine.c

1599

in6_prefixlen2mask(&addr_proposal->mask, addr_proposal->prefix_len);

sbin/slaacd/engine.c

1611

addr_proposal->mask.s6_addr32[i];

sbin/slaacd/engine.c

1637

(iid.s6_addr32[i] & ~addr_proposal->mask.s6_addr32[i]);

sbin/slaacd/engine.c

171

struct in6_addr mask;

sbin/slaacd/engine.c

2143

memcpy(&address.mask, &addr_proposal->mask, sizeof(address.mask));

sbin/slaacd/engine.h

23

struct in6_addr mask;

sbin/slaacd/slaacd.c

658

memcpy(&in6_addreq.ifra_prefixmask.sin6_addr, &address->mask,

sbin/slaacd/slaacd.c

730

struct sockaddr_in6 dst, gw, mask;

sbin/slaacd/slaacd.c

750

memset(&dst, 0, sizeof(mask));

sbin/slaacd/slaacd.c

780

memset(&mask, 0, sizeof(mask));

sbin/slaacd/slaacd.c

781

mask.sin6_family = AF_INET6;

sbin/slaacd/slaacd.c

782

mask.sin6_len = sizeof(struct sockaddr_in6);

sbin/slaacd/slaacd.c

783

iov[iovcnt].iov_base = &mask;

sbin/slaacd/slaacd.c

784

iov[iovcnt++].iov_len = sizeof(mask);

sbin/slaacd/slaacd.c

785

rtm.rtm_msglen += sizeof(mask);

sbin/slaacd/slaacd.c

786

padlen = ROUNDUP(sizeof(mask)) - sizeof(mask);

sbin/unwind/libunbound/util/net_help.c

797

uint8_t mask[8] = {0x0, 0x80, 0xc0, 0xe0, 0xf0, 0xf8, 0xfc, 0xfe};

sbin/unwind/libunbound/util/net_help.c

812

s[net/8] &= mask[net&0x7];

sbin/unwind/libunbound/util/storage/slabhash.c

113

return ((hash & sl->mask) >> sl->shift);

sbin/unwind/libunbound/util/storage/slabhash.c

138

id, (unsigned)sl->size, (unsigned)sl->mask, sl->shift);

sbin/unwind/libunbound/util/storage/slabhash.c

64

sl->mask = (uint32_t)(sl->size - 1);

sbin/unwind/libunbound/util/storage/slabhash.c

65

if(sl->mask == 0) {

sbin/unwind/libunbound/util/storage/slabhash.c

68

log_assert( (sl->size & sl->mask) == 0

sbin/unwind/libunbound/util/storage/slabhash.c

71

while(!(sl->mask & 0x80000000)) {

sbin/unwind/libunbound/util/storage/slabhash.c

72

sl->mask <<= 1;

sbin/unwind/libunbound/util/storage/slabhash.h

61

uint32_t mask;

sys/arch/alpha/alpha/machdep.c

1348

sendsig(sig_t catcher, int sig, sigset_t mask, const siginfo_t *ksip,

sys/arch/alpha/alpha/machdep.c

1385

ksc.sc_mask = mask;

sys/arch/alpha/alpha/pmap.c

2383

pmap_changebit(struct vm_page *pg, u_long set, u_long mask, cpuid_t cpu_id)

sys/arch/alpha/alpha/pmap.c

2394

VM_PAGE_TO_PHYS(pg), set, mask);

sys/arch/alpha/alpha/pmap.c

2406

npte = (*pte | set) & mask;

sys/arch/alpha/alpha/sys_machdep.c

104

m = args.mask;

sys/arch/alpha/include/asm.h

260

.mask 0x4000000,-0x28; \

sys/arch/alpha/include/asm.h

477

.mask _i_mask_|IM_EXC,0; \

sys/arch/alpha/include/sysarch.h

50

fp_except mask;

sys/arch/alpha/pci/sio_pic.c

558

sio_intr_alloc(void *v, int mask, int type, int *irq)

sys/arch/alpha/pci/sio_pic.c

570

mask &= 0xffff;

sys/arch/alpha/pci/sio_pic.c

571

mask &= ~((1 << 13) | (1 << 8) | (1 << 2) | (1 << 1) | (1 << 0));

sys/arch/alpha/pci/sio_pic.c

577

mask &= ~((1 << 12) | (1 << 6));

sys/arch/alpha/pci/sio_pic.c

580

if (LEGAL_IRQ(i) == 0 || (mask & (1<<i)) == 0)

sys/arch/alpha/pci/tsp_dma.c

109

u_int32_t base, mask, physbase, enables;

sys/arch/alpha/pci/tsp_dma.c

123

EDIFF(pccsr->tsp_wsm[i].tsg_r, premap[i].mask) ||

sys/arch/alpha/pci/tsp_dma.c

134

pccsr->tsp_wsm[i].tsg_r = premap[i].mask;

sys/arch/amd64/amd64/identcpu.c

807

int mask;

sys/arch/amd64/amd64/identcpu.c

811

mask = (x << (1 - powerof2)) - 1;

sys/arch/amd64/amd64/identcpu.c

814

if (mask == 0)

sys/arch/amd64/amd64/identcpu.c

816

for (bit = 1; mask != 1; bit++)

sys/arch/amd64/amd64/identcpu.c

817

mask = (unsigned int)mask >> 1;

sys/arch/amd64/amd64/lapic.c

454

lapic_timer_start(uint32_t mode, uint32_t mask, uint32_t cycles)

sys/arch/amd64/amd64/lapic.c

456

lapic_writereg(LAPIC_LVTT, mode | mask | LAPIC_TIMER_VECTOR);

sys/arch/amd64/amd64/lapic.c

462

lapic_timer_oneshot(uint32_t mask, uint32_t cycles)

sys/arch/amd64/amd64/lapic.c

464

lapic_timer_start(LAPIC_LVTT_TM_ONESHOT, mask, cycles);

sys/arch/amd64/amd64/lapic.c

468

lapic_timer_periodic(uint32_t mask, uint32_t cycles)

sys/arch/amd64/amd64/lapic.c

470

lapic_timer_start(LAPIC_LVTT_TM_PERIODIC, mask, cycles);

sys/arch/amd64/amd64/machdep.c

660

sendsig(sig_t catcher, int sig, sigset_t mask, const siginfo_t *ksip,

sys/arch/amd64/amd64/machdep.c

691

ksc.sc_mask = mask;

sys/arch/amd64/amd64/pmap.c

3277

u_int8_t mask[howmany(MAXCPUS, 8)] = { 0 };

sys/arch/amd64/amd64/pmap.c

3284

setbit(mask, ci->ci_cpuid);

sys/arch/amd64/amd64/pmap.c

3295

if (isclr(mask, ci->ci_cpuid))

sys/arch/amd64/amd64/pmap.c

3327

u_int8_t mask[howmany(MAXCPUS, 8)] = { 0 };

sys/arch/amd64/amd64/pmap.c

3334

setbit(mask, ci->ci_cpuid);

sys/arch/amd64/amd64/pmap.c

3346

if (isclr(mask, ci->ci_cpuid))

sys/arch/amd64/amd64/pmap.c

3386

u_int8_t mask[howmany(MAXCPUS, 8)] = { 0 };

sys/arch/amd64/amd64/pmap.c

3394

setbit(mask, ci->ci_cpuid);

sys/arch/amd64/amd64/pmap.c

3403

if (isclr(mask, ci->ci_cpuid))

sys/arch/amd64/amd64/pmap.c

3436

u_int8_t mask[howmany(MAXCPUS, 8)] = { 0 };

sys/arch/amd64/amd64/pmap.c

3445

setbit(mask, ci->ci_cpuid);

sys/arch/amd64/amd64/pmap.c

3457

if (isclr(mask, ci->ci_cpuid))

sys/arch/amd64/amd64/pmap.c

463

u_long mask, shift;

sys/arch/amd64/amd64/pmap.c

470

mask = L4_MASK;

sys/arch/amd64/amd64/pmap.c

473

*offs = (VA_SIGN_POS(va) & mask) >> shift;

sys/arch/amd64/amd64/pmap.c

483

mask >>= 9;

sys/arch/amd64/amd64/ucode.c

278

uint32_t mask = 1UL << platform_id;

sys/arch/amd64/amd64/ucode.c

310

if (cpu_ucode_intel_match(hdr, sig, mask, current))

sys/arch/amd64/amd64/vmm_machdep.c

3510

uint64_t pte, pt_paddr, pte_paddr, mask, low_mask, high_mask;

sys/arch/amd64/amd64/vmm_machdep.c

3547

mask = L4_MASK;

sys/arch/amd64/amd64/vmm_machdep.c

3551

mask = L3_MASK;

sys/arch/amd64/amd64/vmm_machdep.c

3557

mask = 0xFFC00000;

sys/arch/amd64/amd64/vmm_machdep.c

3566

"shift_width=%lld\n", __func__, pte_size, level, mask, shift,

sys/arch/amd64/amd64/vmm_machdep.c

3572

pdidx = (va & mask) >> shift;

sys/arch/amd64/amd64/vmm_machdep.c

3619

mask = mask >> shift_width;

sys/arch/amd64/amd64/vmm_machdep.c

5547

uint64_t ectls, oldcr0, cr4, mask;

sys/arch/amd64/amd64/vmm_machdep.c

5551

mask = vcpu->vc_vmx_cr0_fixed1;

sys/arch/amd64/amd64/vmm_machdep.c

5552

if (~r & mask) {

sys/arch/amd64/amd64/vmm_machdep.c

5562

mask = vcpu->vc_vmx_cr0_fixed0;

sys/arch/amd64/amd64/vmm_machdep.c

5563

if ((r & mask) != mask) {

sys/arch/amd64/amd64/vmm_machdep.c

5672

uint64_t mask;

sys/arch/amd64/amd64/vmm_machdep.c

5675

mask = ~(curcpu()->ci_vmm_cap.vcc_vmx.vmx_cr4_fixed1);

sys/arch/amd64/amd64/vmm_machdep.c

5676

if (r & mask) {

sys/arch/amd64/amd64/vmm_machdep.c

5687

mask = curcpu()->ci_vmm_cap.vcc_vmx.vmx_cr4_fixed0;

sys/arch/amd64/amd64/vmm_machdep.c

5688

if ((r & mask) != mask) {

sys/arch/amd64/amd64/vmm_machdep.c

5951

uint64_t *rdx, *rcx, val, mask = xsave_mask & XFEATURE_XCR0_MASK;

sys/arch/amd64/amd64/vmm_machdep.c

5969

mask |= XFEATURE_PKRU;

sys/arch/amd64/amd64/vmm_machdep.c

5972

if (val & ~mask) {

sys/arch/amd64/include/cpufunc.h

403

xsetbv(uint32_t reg, uint64_t mask)

sys/arch/amd64/include/cpufunc.h

407

lo = mask;

sys/arch/amd64/include/cpufunc.h

408

hi = mask >> 32;

sys/arch/amd64/include/fpu.h

100

xrstors(const struct savefpu *addr, uint64_t mask)

sys/arch/amd64/include/fpu.h

104

lo = mask;

sys/arch/amd64/include/fpu.h

105

hi = mask >> 32;

sys/arch/amd64/include/fpu.h

90

xsave(struct savefpu *addr, uint64_t mask)

sys/arch/amd64/include/fpu.h

94

lo = mask;

sys/arch/amd64/include/fpu.h

95

hi = mask >> 32;

sys/arch/amd64/isa/isa_machdep.c

151

isa_intr_alloc(isa_chipset_tag_t ic, int mask, int type, int *irq)

sys/arch/amd64/isa/isa_machdep.c

164

mask &= 0xdef8;

sys/arch/amd64/isa/isa_machdep.c

170

mask &= 0xefbf;

sys/arch/amd64/isa/isa_machdep.c

173

if (LEGAL_IRQ(i) == 0 || (mask & (1<<i)) == 0)

sys/arch/amd64/pci/pci_machdep.c

355

pcireg_t reg, mask;

sys/arch/amd64/pci/pci_machdep.c

366

mask = pci_conf_read(pc, tag, off + PCI_MSI_MASK64);

sys/arch/amd64/pci/pci_machdep.c

368

mask | (1U << vec));

sys/arch/amd64/pci/pci_machdep.c

370

mask = pci_conf_read(pc, tag, off + PCI_MSI_MASK32);

sys/arch/amd64/pci/pci_machdep.c

372

mask | (1U << vec));

sys/arch/amd64/pci/pci_machdep.c

382

pcireg_t reg, mask;

sys/arch/amd64/pci/pci_machdep.c

393

mask = pci_conf_read(pc, tag, off + PCI_MSI_MASK64);

sys/arch/amd64/pci/pci_machdep.c

395

mask & ~(1U << vec));

sys/arch/amd64/pci/pci_machdep.c

397

mask = pci_conf_read(pc, tag, off + PCI_MSI_MASK32);

sys/arch/amd64/pci/pci_machdep.c

399

mask & ~(1U << vec));

sys/arch/arm/arm/disassem.c

108

u_int mask;

sys/arch/arm/arm/disassem.c

306

if ((insn & i_ptr->mask) == i_ptr->pattern) {

sys/arch/arm/arm/disassem.c

319

if ((i_ptr->mask & 0xf0000000) == 0xf0000000)

sys/arch/arm/arm/sig_machdep.c

129

frame.sf_sc.sc_mask = mask;

sys/arch/arm/arm/sig_machdep.c

77

sendsig(sig_t catcher, int sig, sigset_t mask, const siginfo_t *ksip,

sys/arch/arm/cortex/ampintc.c

567

uint8_t mask, val;

sys/arch/arm/cortex/ampintc.c

570

mask = sc->sc_cpu_mask[ci->ci_cpuid];

sys/arch/arm/cortex/ampintc.c

574

val |= mask;

sys/arch/arm/cortex/ampintc.c

576

val &= ~mask;

sys/arch/arm/include/cpufunc.h

295

#define disable_interrupts(mask) \

sys/arch/arm/include/cpufunc.h

296

(__set_cpsr_c((mask) & (PSR_I | PSR_F), \

sys/arch/arm/include/cpufunc.h

297

(mask) & (PSR_I | PSR_F)))

sys/arch/arm/include/cpufunc.h

299

#define enable_interrupts(mask) \

sys/arch/arm/include/cpufunc.h

300

(__set_cpsr_c((mask) & (PSR_I | PSR_F), 0))

sys/arch/arm64/arm64/disasm.c

2406

const uint64_t mask = (sf == 0) ? 0xffffffff : 0xffffffffffffffffUL;

sys/arch/arm64/arm64/disasm.c

2417

(~(ZeroExtend(16, imm16, 1) & mask)) & mask);

sys/arch/arm64/arm64/disasm.c

2423

~(ZeroExtend(16, imm16, 1) << shift) & mask);

sys/arch/arm64/arm64/disasm.c

3624

uint32_t mask;

sys/arch/arm64/arm64/disasm.c

3990

if ((insn & insn_tables[i].mask) != insn_tables[i].pattern)

sys/arch/arm64/arm64/intr.c

130

uint32_t mask, rid_base, rid;

sys/arch/arm64/arm64/intr.c

146

mask = OF_getpropint(node, "msi-map-mask", 0xffff);

sys/arch/arm64/arm64/intr.c

147

rid = *data & mask;

sys/arch/arm64/arm64/sig_machdep.c

136

frame.sf_sc.sc_mask = mask;

sys/arch/arm64/arm64/sig_machdep.c

98

sendsig(sig_t catcher, int sig, sigset_t mask, const siginfo_t *ksip,

sys/arch/arm64/dev/ampintc.c

594

uint8_t mask, val;

sys/arch/arm64/dev/ampintc.c

597

mask = sc->sc_cpu_mask[ci->ci_cpuid];

sys/arch/arm64/dev/ampintc.c

601

val |= mask;

sys/arch/arm64/dev/ampintc.c

603

val &= ~mask;

sys/arch/arm64/dev/apldart.c

450

uint32_t mask;

sys/arch/arm64/dev/apldart.c

486

mask = HREAD4(sc, DART_SID_ENABLE(sc, sid / 32));

sys/arch/arm64/dev/apldart.c

487

mask |= (1U << (sid % 32));

sys/arch/arm64/dev/apldart.c

488

HWRITE4(sc, DART_SID_ENABLE(sc, sid / 32), mask);

sys/arch/arm64/dev/apldart.c

618

uint32_t mask;

sys/arch/arm64/dev/apldart.c

676

mask = HREAD4(sc, DART_SID_ENABLE(sc, sid / 32));

sys/arch/arm64/dev/apldart.c

677

mask |= (1U << (sid % 32));

sys/arch/arm64/dev/apldart.c

678

HWRITE4(sc, DART_SID_ENABLE(sc, sid / 32), mask);

sys/arch/arm64/dev/apldart.c

741

uint32_t mask;

sys/arch/arm64/dev/apldart.c

746

mask = DART_ALL_STREAMS(sc);

sys/arch/arm64/dev/apldart.c

748

mask = (1U << sid);

sys/arch/arm64/dev/apldart.c

750

HWRITE4(sc, DART_T8020_TLB_SIDMASK, mask);

sys/arch/arm64/stand/efiboot/efiacpi.c

403

const uint32_t mask = ACPI_GTDT_TIMER_TRIGGER_EDGE |

sys/arch/arm64/stand/efiboot/efiacpi.c

411

interrupts[2] = htobe32(map[gtdt->sec_el1_flags & mask]);

sys/arch/arm64/stand/efiboot/efiacpi.c

414

interrupts[5] = htobe32(map[gtdt->nonsec_el1_flags & mask]);

sys/arch/arm64/stand/efiboot/efiacpi.c

417

interrupts[8] = htobe32(map[gtdt->virt_flags & mask]);

sys/arch/arm64/stand/efiboot/efiacpi.c

420

interrupts[11] = htobe32(map[gtdt->nonsec_el2_flags & mask]);

sys/arch/armv7/armv7/intr.c

125

uint32_t mask, rid_base, rid;

sys/arch/armv7/armv7/intr.c

141

mask = OF_getpropint(node, "msi-map-mask", 0xffff);

sys/arch/armv7/armv7/intr.c

142

rid = *data & mask;

sys/arch/armv7/exynos/ec_commands.h

1078

uint32_t mask;

sys/arch/armv7/exynos/ec_commands.h

1082

uint32_t mask;

sys/arch/armv7/exynos/ec_commands.h

507

uint32_t mask; /* Bits in flags to apply */

sys/arch/armv7/exynos/exclock.c

338

uint32_t m, p, s = 0, mask, fout;

sys/arch/armv7/exynos/exclock.c

353

mask = 0x3ff;

sys/arch/armv7/exynos/exclock.c

356

mask = 0x1ff;

sys/arch/armv7/exynos/exclock.c

359

m = (r >> 16) & mask;

sys/arch/armv7/exynos/exiic.c

206

exiic_wait_state(struct exiic_softc *sc, uint32_t reg, uint32_t mask, uint32_t value)

sys/arch/armv7/exynos/exiic.c

212

if (((state = HREAD4(sc, reg)) & mask) == value)

sys/arch/armv7/exynos/exmct.c

70

uint32_t i, mask, reg;

sys/arch/armv7/exynos/exmct.c

88

mask = (1 << 16);

sys/arch/armv7/exynos/exmct.c

93

if (reg & mask) {

sys/arch/armv7/exynos/exmct.c

95

MCT_WRITE_STAT, mask);

sys/arch/armv7/omap/ommmc.c

1027

int mask;

sys/arch/armv7/omap/ommmc.c

1030

mask = ISSET(cmd->c_flags, SCF_CMD_READ) ?

sys/arch/armv7/omap/ommmc.c

1045

if ((error = ommmc_wait_state(sc, mask, mask)) != 0)

sys/arch/armv7/omap/ommmc.c

1109

ommmc_soft_reset(struct ommmc_softc *sc, int mask)

sys/arch/armv7/omap/ommmc.c

1114

DPRINTF(1,("%s: software reset reg=%#x\n", DEVNAME(sc), mask));

sys/arch/armv7/omap/ommmc.c

1116

HSET4(sc, MMCHS_SYSCTL, mask);

sys/arch/armv7/omap/ommmc.c

1125

if (ISSET(HREAD4(sc, MMCHS_SYSCTL), mask))

sys/arch/armv7/omap/ommmc.c

1130

if (!ISSET(HREAD4(sc, MMCHS_SYSCTL), mask))

sys/arch/armv7/omap/ommmc.c

1144

ommmc_wait_intr(struct ommmc_softc *sc, int mask, int sec)

sys/arch/armv7/omap/ommmc.c

1149

mask |= MMCHS_STAT_ERRI;

sys/arch/armv7/omap/ommmc.c

1152

status = sc->intr_status & mask;

sys/arch/armv7/omap/ommmc.c

1159

status = sc->intr_status & mask;

sys/arch/armv7/omap/ommmc.c

829

ommmc_wait_state(struct ommmc_softc *sc, uint32_t mask, uint32_t value)

sys/arch/armv7/omap/ommmc.c

836

mask, value, state, state, MMCHS_PSTATE_FMT));

sys/arch/armv7/omap/ommmc.c

838

if (((state = HREAD4(sc, MMCHS_PSTATE)) & mask) == value)

sys/arch/armv7/omap/prcm.c

220

u_int32_t oreg, reg, mask;

sys/arch/armv7/omap/prcm.c

226

mask = 3;

sys/arch/armv7/omap/prcm.c

227

reg = oreg & ~mask;

sys/arch/armv7/omap/prcm.c

234

mask = 3;

sys/arch/armv7/omap/prcm.c

235

reg = oreg & ~mask;

sys/arch/armv7/omap/prcm.c

286

u_int32_t oreg, reg, mask;

sys/arch/armv7/omap/prcm.c

290

mask = 1;

sys/arch/armv7/omap/prcm.c

291

reg = (oreg &~mask) | (speed & mask);

sys/arch/armv7/omap/prcm.c

296

mask = 1 << (shift);

sys/arch/armv7/omap/prcm.c

297

reg = (oreg & ~mask) | ( (speed << shift) & mask);

sys/arch/armv7/omap/ti_iic.c

361

uint16_t con, stat, mask;

sys/arch/armv7/omap/ti_iic.c

368

mask = I2C_IRQSTATUS_ARDY | I2C_IRQSTATUS_NACK | I2C_IRQSTATUS_AL;

sys/arch/armv7/omap/ti_iic.c

370

mask |= I2C_IRQSTATUS_RDR | I2C_IRQSTATUS_RRDY;

sys/arch/armv7/omap/ti_iic.c

372

mask |= I2C_IRQSTATUS_XDR | I2C_IRQSTATUS_XRDY;

sys/arch/armv7/omap/ti_iic.c

408

I2C_WRITE_REG(sc, AM335X_I2C_IRQENABLE_SET, mask);

sys/arch/armv7/omap/ti_iic.c

431

stat = ti_iic_stat(sc, mask);

sys/arch/armv7/omap/ti_iic.c

527

ti_iic_wait(struct ti_iic_softc *sc, uint16_t mask, uint16_t val, int flags)

sys/arch/armv7/omap/ti_iic.c

531

DPRINTF(("ti_iic_wait mask %#x val %#x flags %#x\n", mask, val, flags));

sys/arch/armv7/omap/ti_iic.c

533

while (((v = I2C_READ_REG(sc, AM335X_I2C_IRQSTATUS_RAW)) & mask) != val) {

sys/arch/armv7/omap/ti_iic.c

537

DEVNAME(sc), mask, val, v);

sys/arch/armv7/omap/ti_iic.c

552

ti_iic_stat(struct ti_iic_softc *sc, uint32_t mask)

sys/arch/armv7/omap/ti_iic.c

556

DPRINTF(("ti_iic_wait mask %#x\n", mask));

sys/arch/armv7/omap/ti_iic.c

558

v = I2C_READ_REG(sc, AM335X_I2C_IRQSTATUS_RAW) & mask;

sys/arch/hppa/dev/viper.h

213

void viper_setintrwnd(u_int32_t mask);

sys/arch/hppa/gsc/harmony.c

1054

u_int32_t bits, mask, val, old;

sys/arch/hppa/gsc/harmony.c

1066

mask = (1 << GAINCTL_OUTPUT_BITS) - 1;

sys/arch/hppa/gsc/harmony.c

1067

val = mask - (sc->sc_output_lvl.left >> (8 - GAINCTL_OUTPUT_BITS));

sys/arch/hppa/gsc/harmony.c

1069

val = mask - (sc->sc_output_lvl.right >> (8 - GAINCTL_OUTPUT_BITS));

sys/arch/hppa/gsc/harmony.c

1073

mask = (1 << GAINCTL_MONITOR_BITS) - 1;

sys/arch/hppa/gsc/harmony.c

1074

val = mask - (sc->sc_monitor_lvl.left >> (8 - GAINCTL_MONITOR_BITS));

sys/arch/hppa/gsc/harmony.c

1093

mask = GAINCTL_LE | GAINCTL_HE | GAINCTL_SE | GAINCTL_IS_MASK;

sys/arch/hppa/gsc/harmony.c

1096

if ((old & mask) != (bits & mask))

sys/arch/hppa/gsc/lpt_gsc.c

105

u_int8_t mask, data;

sys/arch/hppa/gsc/lpt_gsc.c

115

printf("lpt_gsc_probe: mask %x data %x failed\n", mask, \

sys/arch/hppa/gsc/lpt_gsc.c

133

mask = 0xff;

sys/arch/hppa/gsc/lpt_gsc.c

136

if (!lpt_port_test(ga->ga_iot, ioh, base, lpt_data, data, mask))

sys/arch/hppa/gsc/lpt_gsc.c

140

if (!lpt_port_test(ga->ga_iot, ioh, base, lpt_data, data, mask))

sys/arch/hppa/gsc/lpt_gsc.c

145

if (!lpt_port_test(ga->ga_iot, ioh, base, lpt_data, data, mask))

sys/arch/hppa/gsc/lpt_gsc.c

151

if (!lpt_port_test(ga->ga_iot, ioh, base, lpt_data, data, mask))

sys/arch/hppa/hppa/db_disasm.c

1237

u_int shft, mask;

sys/arch/hppa/hppa/db_disasm.c

1257

mask = (1 << i->extbl) - 1;

sys/arch/hppa/hppa/db_disasm.c

1259

if (m->extshft != shft || m->extmask != mask) {

sys/arch/hppa/hppa/db_disasm.c

1265

m->extmask = mask;

sys/arch/hppa/hppa/intr.c

108

mfctl(CR_ITMR, mask);

sys/arch/hppa/hppa/intr.c

109

mtctl(mask - 1, CR_ITMR);

sys/arch/hppa/hppa/intr.c

113

mfctl(CR_EIRR, mask);

sys/arch/hppa/hppa/intr.c

114

mtctl(mask & (1U << 31), CR_EIRR);

sys/arch/hppa/hppa/intr.c

118

ssm(PSL_I, mask);

sys/arch/hppa/hppa/intr.c

234

u_long mask;

sys/arch/hppa/hppa/intr.c

246

mask = imask[pri] ^ imask[pri - 1];

sys/arch/hppa/hppa/intr.c

248

while (ci->ci_ipending & mask) {

sys/arch/hppa/hppa/intr.c

249

bit = fls(ci->ci_ipending & mask) - 1;

sys/arch/hppa/hppa/intr.c

78

u_long mask;

sys/arch/hppa/hppa/intr.c

80

mask = ci->ci_mask | SOFTINT_MASK;

sys/arch/hppa/hppa/intr.c

88

bit = ffs(~mask);

sys/arch/hppa/hppa/intr.c

95

mask |= (1 << bit);

sys/arch/hppa/hppa/machdep.c

1192

sendsig(sig_t catcher, int sig, sigset_t mask, const siginfo_t *ksip,

sys/arch/hppa/hppa/machdep.c

1222

ksc.sc_mask = mask;

sys/arch/hppa/hppa/machdep.c

789

static u_int32_t mask;

sys/arch/hppa/hppa/machdep.c

832

i = ffs(~mask) - 1;

sys/arch/hppa/hppa/machdep.c

841

mask |= 1 << i;

sys/arch/hppa/hppa/mem.c

272

viper_setintrwnd(u_int32_t mask)

sys/arch/hppa/hppa/mem.c

279

sc->sc_vp->vi_intrwd = mask;

sys/arch/hppa/include/cpufunc.h

92

mtsm(register_t mask) {

sys/arch/hppa/include/cpufunc.h

95

"mtsm %1": "=&r" (ret) : "r" (mask));

sys/arch/i386/i386/esm.c

987

esm_bmc_ready(struct esm_softc *sc, int port, u_int8_t mask, u_int8_t val,

sys/arch/i386/i386/esm.c

993

if ((EREAD(sc, port) & mask) == val)

sys/arch/i386/i386/k6_mem.c

112

k6_reg_get(one, addr, mask, wc, uc);

sys/arch/i386/i386/k6_mem.c

114

sc->mr_desc[d].mr_len = ffs(mask) << 17;

sys/arch/i386/i386/k6_mem.c

50

#define k6_reg_get(reg, addr, mask, wc, uc) do { \

sys/arch/i386/i386/k6_mem.c

52

mask = ((reg) & 0x1fffc) >> 2; \

sys/arch/i386/i386/k6_mem.c

57

#define k6_reg_make(addr, mask, wc, uc) \

sys/arch/i386/i386/k6_mem.c

58

((addr) | ((mask) << 2) | ((wc) << 1) | uc)

sys/arch/i386/i386/k6_mem.c

98

u_int32_t addr, mask, wc, uc;

sys/arch/i386/i386/lapic.c

289

lapic_timer_start(uint32_t mode, uint32_t mask, uint32_t cycles)

sys/arch/i386/i386/lapic.c

291

i82489_writereg(LAPIC_LVTT, mode | mask | LAPIC_TIMER_VECTOR);

sys/arch/i386/i386/lapic.c

297

lapic_timer_oneshot(uint32_t mask, uint32_t cycles)

sys/arch/i386/i386/lapic.c

299

lapic_timer_start(LAPIC_LVTT_TM_ONESHOT, mask, cycles);

sys/arch/i386/i386/lapic.c

303

lapic_timer_periodic(uint32_t mask, uint32_t cycles)

sys/arch/i386/i386/lapic.c

305

lapic_timer_start(LAPIC_LVTT_TM_PERIODIC, mask, cycles);

sys/arch/i386/i386/machdep.c

2376

sendsig(sig_t catcher, int sig, sigset_t mask, const siginfo_t *ksip,

sys/arch/i386/i386/machdep.c

2423

frame.sf_sc.sc_mask = mask;

sys/arch/i386/i386/pmap.c

2716

u_int64_t mask = 0;

sys/arch/i386/i386/pmap.c

2722

mask |= (1ULL << ci->ci_cpuid);

sys/arch/i386/i386/pmap.c

2732

if ((mask & (1ULL << ci->ci_cpuid)) == 0)

sys/arch/i386/i386/pmap.c

2753

u_int64_t mask = 0;

sys/arch/i386/i386/pmap.c

2759

mask |= (1ULL << ci->ci_cpuid);

sys/arch/i386/i386/pmap.c

2770

if ((mask & (1ULL << ci->ci_cpuid)) == 0)

sys/arch/i386/i386/pmap.c

2791

u_int64_t mask = 0;

sys/arch/i386/i386/pmap.c

2796

mask |= (1ULL << ci->ci_cpuid);

sys/arch/i386/i386/pmap.c

2805

if ((mask & (1ULL << ci->ci_cpuid)) == 0)

sys/arch/i386/i386/pmap.c

2825

u_int64_t mask = 0;

sys/arch/i386/i386/pmap.c

2831

mask |= (1ULL << ci->ci_cpuid);

sys/arch/i386/i386/pmap.c

2840

if ((mask & (1ULL << ci->ci_cpuid)) == 0)

sys/arch/i386/i386/ucode.c

301

uint32_t mask = 1UL << platform_id;

sys/arch/i386/i386/ucode.c

333

if (cpu_ucode_intel_match(hdr, sig, mask, current))

sys/arch/i386/isa/isa_machdep.c

345

isa_intr_alloc(isa_chipset_tag_t ic, int mask, int type, int *irq)

sys/arch/i386/isa/isa_machdep.c

358

mask &= 0xdef8;

sys/arch/i386/isa/isa_machdep.c

364

mask &= 0xefbf;

sys/arch/i386/isa/isa_machdep.c

367

if (LEGAL_IRQ(i) == 0 || (mask & (1<<i)) == 0)

sys/arch/i386/pci/pci_addr_fixup.c

182

pcireg_t val, mask;

sys/arch/i386/pci/pci_addr_fixup.c

214

mask = pci_conf_read(pc, tag, mapreg);

sys/arch/i386/pci/pci_addr_fixup.c

234

size = PCI_MAPREG_MEM_SIZE(mask);

sys/arch/i386/pci/pci_addr_fixup.c

239

size = PCI_MAPREG_IO_SIZE(mask);

sys/arch/i386/pci/via8231.c

108

int mask;

sys/arch/i386/pci/via8231.c

126

via8231_routing_cnfg[(pirq)].mask)

sys/arch/i386/pci/via8231.c

129

(((reg) & ~(via8231_routing_cnfg[(pirq)].mask << \

sys/arch/i386/pci/via8231.c

131

(((cfg) & via8231_routing_cnfg[(pirq)].mask) << \

sys/arch/loongson/dev/bonito.c

582

uint64_t imr, isr, mask;

sys/arch/loongson/dev/bonito.c

615

if ((mask = isr & bonito_imask[frame->ipl]) != 0) {

sys/arch/loongson/dev/bonito.c

616

isr &= ~mask;

sys/arch/loongson/dev/bonito.c

617

imr &= ~mask;

sys/arch/loongson/dev/bonito.c

639

uint64_t imr, isr, mask;

sys/arch/loongson/dev/bonito.c

660

if ((mask = isr & bonito_imask[frame->ipl]) != 0) {

sys/arch/loongson/dev/bonito.c

661

isr &= ~mask;

sys/arch/loongson/dev/bonito.c

662

imr &= ~mask;

sys/arch/loongson/dev/bonito.c

687

uint64_t tmpisr, mask;

sys/arch/loongson/dev/bonito.c

696

for (bitno = startbit, mask = 1UL << bitno; mask != 0;

sys/arch/loongson/dev/bonito.c

697

bitno--, mask >>= 1) {

sys/arch/loongson/dev/bonito.c

698

if ((tmpisr & mask) == 0)

sys/arch/loongson/dev/bonito.c

723

if ((isr ^= mask) == 0)

sys/arch/loongson/dev/bonito.c

725

if ((tmpisr ^= mask) == 0)

sys/arch/loongson/dev/voyager.c

211

uint32_t isr, imr, mask, bitno;

sys/arch/loongson/dev/voyager.c

221

for (bitno = 0, mask = 1 << 0; isr != 0; bitno++, mask <<= 1) {

sys/arch/loongson/dev/voyager.c

222

if ((isr & mask) == 0)

sys/arch/loongson/dev/voyager.c

224

isr ^= mask;

sys/arch/loongson/dev/voyager.c

307

int32_t data, mask;

sys/arch/loongson/dev/voyager.c

315

mask = 1 << pin;

sys/arch/loongson/dev/voyager.c

318

return data & mask ? GPIO_PIN_HIGH : GPIO_PIN_LOW;

sys/arch/loongson/dev/voyager.c

326

int32_t data, mask;

sys/arch/loongson/dev/voyager.c

334

mask = 1 << pin;

sys/arch/loongson/dev/voyager.c

337

data |= mask;

sys/arch/loongson/dev/voyager.c

339

data &= ~mask;

sys/arch/loongson/dev/voyager.c

349

int32_t data, mask;

sys/arch/loongson/dev/voyager.c

357

mask = 1 << pin;

sys/arch/loongson/dev/voyager.c

360

data |= mask;

sys/arch/loongson/dev/voyager.c

362

data &= ~mask;

sys/arch/loongson/loongson/generic2e_machdep.c

242

uint64_t isr, mask = 0;

sys/arch/loongson/loongson/generic2e_machdep.c

280

mask |= isr;

sys/arch/loongson/loongson/generic2e_machdep.c

318

if (mask != 0)

sys/arch/loongson/loongson/generic2e_machdep.c

319

loongson_set_isa_imr(loongson_isaimr | mask);

sys/arch/loongson/loongson/generic2e_machdep.c

321

return mask == 0 ? 0 : hwpend;

sys/arch/loongson/loongson/loongson2_machdep.c

218

loongson2f_setup_window(uint master, uint window, uint64_t base, uint64_t mask,

sys/arch/loongson/loongson/loongson2_machdep.c

230

*awrreg = mask;

sys/arch/loongson/loongson/loongson3_intr.c

371

uint32_t imr, isr, mask;

sys/arch/loongson/loongson/loongson3_intr.c

389

if ((mask = isr & loongson3_imask[frame->ipl]) != 0) {

sys/arch/loongson/loongson/loongson3_intr.c

390

isr &= ~mask;

sys/arch/loongson/loongson/loongson3_intr.c

391

imr &= ~mask;

sys/arch/loongson/loongson/loongson3_intr.c

444

uint32_t imr, isr, mask;

sys/arch/loongson/loongson/loongson3_intr.c

462

if ((mask = isr & loongson3_ht_imask[frame->ipl]) != 0) {

sys/arch/loongson/loongson/loongson3_intr.c

463

isr &= ~mask;

sys/arch/loongson/loongson/loongson3_intr.c

464

imr &= ~mask;

sys/arch/loongson/loongson/yeeloong_machdep.c

346

uint64_t imr, isr, mask;

sys/arch/loongson/loongson/yeeloong_machdep.c

372

if ((mask = isr & (BONITO_ISA_MASK(bonito_imask[frame->ipl]))) != 0) {

sys/arch/loongson/loongson/yeeloong_machdep.c

373

isr &= ~mask;

sys/arch/loongson/loongson/yeeloong_machdep.c

374

imr &= ~mask;

sys/arch/loongson/loongson/yeeloong_machdep.c

391

for (bitno = bit, mask = 1UL << bitno; mask != 0;

sys/arch/loongson/loongson/yeeloong_machdep.c

392

bitno--, mask >>= 1) {

sys/arch/loongson/loongson/yeeloong_machdep.c

393

if ((tmpisr & mask) == 0)

sys/arch/loongson/loongson/yeeloong_machdep.c

423

if ((isr ^= mask) == 0)

sys/arch/loongson/loongson/yeeloong_machdep.c

425

if ((tmpisr ^= mask) == 0)

sys/arch/m88k/m88k/db_disasm.c

1057

while (p->mask != 0) {

sys/arch/m88k/m88k/db_disasm.c

1058

if ((inst & p->mask) == p->match) {

sys/arch/m88k/m88k/db_disasm.c

843

u_int32_t mask, match;

sys/arch/m88k/m88k/db_interface.c

113

static const u_int mask[16] = {

sys/arch/m88k/m88k/db_interface.c

156

(d & mask[DMT_ENBITS(t)]) >> shift[DMT_ENBITS(t)],

sys/arch/m88k/m88k/db_trace.c

122

u_int32_t mask, value;

sys/arch/m88k/m88k/db_trace.c

160

if ((instruction & ptr->mask) == ptr->value)

sys/arch/m88k/m88k/m88k_machdep.c

324

int q, mask;

sys/arch/m88k/m88k/m88k_machdep.c

331

mask = 1 << q;

sys/arch/m88k/m88k/m88k_machdep.c

332

if (mask & sir)

sys/arch/m88k/m88k/sig_machdep.c

102

sendsig(sig_t catcher, int sig, sigset_t mask, const siginfo_t *ksip,

sys/arch/m88k/m88k/sig_machdep.c

137

sf.sf_sc.sc_mask = mask;

sys/arch/macppc/dev/awacs.c

670

if (mc->un.mask == sc->sc_output_mask)

sys/arch/macppc/dev/awacs.c

673

if (mc->un.mask & 1 << 0)

sys/arch/macppc/dev/awacs.c

675

if (mc->un.mask & 1 << 1)

sys/arch/macppc/dev/awacs.c

679

sc->sc_output_mask = mc->un.mask;

sys/arch/macppc/dev/awacs.c

698

if (mc->un.mask == sc->sc_record_source)

sys/arch/macppc/dev/awacs.c

700

switch(mc->un.mask) {

sys/arch/macppc/dev/awacs.c

719

sc->sc_record_source = mc->un.mask;

sys/arch/macppc/dev/awacs.c

736

mc->un.mask = sc->sc_output_mask;

sys/arch/macppc/dev/awacs.c

743

mc->un.mask = 1 << 0;

sys/arch/macppc/dev/awacs.c

753

mc->un.mask = 1 << 1;

sys/arch/macppc/dev/awacs.c

760

mc->un.mask = sc->sc_record_source;

sys/arch/macppc/dev/awacs.c

767

mc->un.mask = sc->sc_record_source;

sys/arch/macppc/dev/awacs.c

795

dip->un.s.member[0].mask = 1 << 0;

sys/arch/macppc/dev/awacs.c

798

dip->un.s.member[1].mask = 1 << 1;

sys/arch/macppc/dev/awacs.c

831

dip->un.s.member[0].mask = 1 << 0;

sys/arch/macppc/dev/awacs.c

834

dip->un.s.member[1].mask = 1 << 1;

sys/arch/macppc/dev/awacs.c

837

dip->un.s.member[2].mask = 1 << 2;

sys/arch/macppc/dev/i2s.c

325

if (mc->un.mask == sc->sc_output_mask)

sys/arch/macppc/dev/i2s.c

331

if (mc->un.mask & I2S_SELECT_SPEAKER)

sys/arch/macppc/dev/i2s.c

333

if (mc->un.mask & I2S_SELECT_HEADPHONE)

sys/arch/macppc/dev/i2s.c

335

if (mc->un.mask & I2S_SELECT_LINEOUT)

sys/arch/macppc/dev/i2s.c

338

sc->sc_output_mask = mc->un.mask;

sys/arch/macppc/dev/i2s.c

381

if (mc->un.mask == sc->sc_record_source)

sys/arch/macppc/dev/i2s.c

383

switch (mc->un.mask) {

sys/arch/macppc/dev/i2s.c

392

(*sc->sc_setinput)(sc, mc->un.mask);

sys/arch/macppc/dev/i2s.c

393

sc->sc_record_source = mc->un.mask;

sys/arch/macppc/dev/i2s.c

413

mc->un.mask = sc->sc_output_mask;

sys/arch/macppc/dev/i2s.c

426

mc->un.mask = sc->sc_record_source;

sys/arch/macppc/dev/i2s.c

469

dip->un.s.member[n++].mask = I2S_SELECT_SPEAKER;

sys/arch/macppc/dev/i2s.c

474

dip->un.s.member[n++].mask = I2S_SELECT_HEADPHONE;

sys/arch/macppc/dev/i2s.c

479

dip->un.s.member[n++].mask = I2S_SELECT_LINEOUT;

sys/arch/macppc/dev/i2s.c

519

dip->un.s.member[0].mask = I2S_SELECT_SPEAKER;

sys/arch/macppc/dev/i2s.c

522

dip->un.s.member[1].mask = I2S_SELECT_HEADPHONE;

sys/arch/macppc/dev/onyx.c

189

onyx_set_input(struct onyx_softc *sc, int mask)

sys/arch/macppc/dev/onyx.c

193

sc->sc_record_source = mask;

sys/arch/macppc/dev/onyx.c

195

switch (mask) {

sys/arch/macppc/dev/snapper.c

544

snapper_set_input(struct snapper_softc *sc, int mask)

sys/arch/macppc/dev/snapper.c

548

switch (mask) {

sys/arch/macppc/macppc/machdep.c

444

sendsig(sig_t catcher, int sig, sigset_t mask, const siginfo_t *ksip,

sys/arch/macppc/macppc/machdep.c

472

frame.sf_sc.sc_mask = mask;

sys/arch/mips64/mips64/clock.c

121

cp0_int5(uint32_t mask, struct trapframe *tf)

sys/arch/mips64/mips64/interrupt.c

157

set_intr(int pri, uint32_t mask,

sys/arch/mips64/mips64/interrupt.c

171

if ((mask & ~CR_INT_MASK) != 0)

sys/arch/mips64/mips64/interrupt.c

172

panic("set_intr: invalid mask 0x%x", mask);

sys/arch/mips64/mips64/interrupt.c

175

(cpu_int_tab[pri].int_mask != mask ||

sys/arch/mips64/mips64/interrupt.c

180

cpu_int_tab[pri].int_mask = mask;

sys/arch/mips64/mips64/interrupt.c

181

idle_mask |= mask;

sys/arch/mips64/mips64/sendsig.c

124

ksc.sc_mask = mask;

sys/arch/mips64/mips64/sendsig.c

95

sendsig(sig_t catcher, int sig, sigset_t mask, const siginfo_t *ksip,

sys/arch/mips64/mips64/softintr.c

58

int sir, q, mask;

sys/arch/mips64/mips64/softintr.c

72

mask = 1 << q;

sys/arch/mips64/mips64/softintr.c

73

if (sir & mask)

sys/arch/mips64/mips64/trap.c

1123

uint32_t instr, mask;

sys/arch/mips64/mips64/trap.c

1214

mask = 0;

sys/arch/mips64/mips64/trap.c

1261

if (mask & (1 << i.IType.rt))

sys/arch/mips64/mips64/trap.c

1263

mask |= (1 << i.IType.rt);

sys/arch/octeon/dev/amdcf.c

913

cfi_make_cmd(uint8_t cmd, u_int mask)

sys/arch/octeon/dev/amdcf.c

919

if (mask & (0xff << (i*8)))

sys/arch/octeon/dev/octcib.c

278

uint64_t en, isr, mask;

sys/arch/octeon/dev/octcib.c

290

mask = 1ul << bit;

sys/arch/octeon/dev/octcib.c

292

if ((isr & mask) == 0)

sys/arch/octeon/dev/octcib.c

294

isr &= ~mask;

sys/arch/octeon/dev/octcib.c

300

CIB_RAW_WR(sc, mask);

sys/arch/octeon/dev/octciu.c

403

uint64_t mask[NBANKS] = {};

sys/arch/octeon/dev/octciu.c

406

mask[IRQ_TO_BANK(irq)] |=

sys/arch/octeon/dev/octciu.c

408

scpu->scpu_imask[level][0] = mask[0];

sys/arch/octeon/dev/octciu.c

409

scpu->scpu_imask[level][1] = mask[1];

sys/arch/octeon/dev/octciu.c

410

scpu->scpu_imask[level][2] = mask[2];

sys/arch/octeon/dev/octciu.c

469

uint64_t imr, isr, mask;

sys/arch/octeon/dev/octciu.c

492

if ((mask = isr & scpu->scpu_imask[frame->ipl][bank->id])

sys/arch/octeon/dev/octciu.c

494

isr &= ~mask;

sys/arch/octeon/dev/octciu.c

495

imr &= ~mask;

sys/arch/octeon/dev/octmmc.c

965

octmmc_wait_intr(struct octmmc_softc *sc, uint64_t mask, int secs)

sys/arch/octeon/dev/octmmc.c

969

mask |= MIO_EMM_INT_CMD_ERR | MIO_EMM_INT_DMA_ERR;

sys/arch/octeon/dev/octmmc.c

972

while ((sc->sc_intr_status & mask) == 0) {

sys/arch/powerpc/ddb/db_disasm.c

1163

for (i=0; opcodeset[i].mask != 0; i++) {

sys/arch/powerpc/ddb/db_disasm.c

1165

if ((instr & op->mask) == op->code) {

sys/arch/powerpc/ddb/db_disasm.c

126

u_int32_t mask;

sys/arch/powerpc/ddb/db_disasm.c

473

u_int32_t mask = (1 << width) - 1;

sys/arch/powerpc/ddb/db_disasm.c

474

return ((value >> (31 - base)) & mask);

sys/arch/powerpc/powerpc/softintr.c

58

int sir, q, mask;

sys/arch/powerpc/powerpc/softintr.c

67

mask = SI_TO_IRQBIT(q);

sys/arch/powerpc/powerpc/softintr.c

68

if (sir & mask)

sys/arch/powerpc64/powerpc64/db_disasm.c

1163

for (i=0; opcodeset[i].mask != 0; i++) {

sys/arch/powerpc64/powerpc64/db_disasm.c

1165

if ((instr & op->mask) == op->code) {

sys/arch/powerpc64/powerpc64/db_disasm.c

126

u_int32_t mask;

sys/arch/powerpc64/powerpc64/db_disasm.c

473

u_int32_t mask = (1 << width) - 1;

sys/arch/powerpc64/powerpc64/db_disasm.c

474

return ((value >> (31 - base)) & mask);

sys/arch/powerpc64/powerpc64/machdep.c

915

sendsig(sig_t catcher, int sig, sigset_t mask, const siginfo_t *ksip,

sys/arch/powerpc64/powerpc64/machdep.c

966

frame.sf_sc.sc_mask = mask;

sys/arch/riscv64/dev/plic.c

697

uint32_t val, mask;

sys/arch/riscv64/dev/plic.c

704

mask = (1 << (irq % 32));

sys/arch/riscv64/dev/plic.c

708

val |= mask;

sys/arch/riscv64/dev/plic.c

710

val &= ~mask;

sys/arch/riscv64/dev/sfcc.c

102

vaddr_t end, mask;

sys/arch/riscv64/dev/sfcc.c

105

mask = sc->sc_line_size - 1;

sys/arch/riscv64/dev/sfcc.c

106

end = (va + len + mask) & ~mask;

sys/arch/riscv64/dev/sfcc.c

107

va &= ~mask;

sys/arch/riscv64/dev/smtclock.c

426

uint32_t mask, val;

sys/arch/riscv64/dev/smtclock.c

462

mask = assert_mask | deassert_mask;

sys/arch/riscv64/dev/smtclock.c

463

val = HREAD4(sc, reset->reg) & ~mask;

sys/arch/riscv64/dev/smtiic.c

171

smtiic_wait_state(struct smtiic_softc *sc, uint32_t mask, uint32_t value)

sys/arch/riscv64/dev/smtiic.c

177

if (((state = HREAD4(sc, ISR)) & mask) == value)

sys/arch/riscv64/dev/stfpcie.c

585

uint32_t mask;

sys/arch/riscv64/dev/stfpcie.c

594

mask = HREAD4(sc, IMASK_LOCAL);

sys/arch/riscv64/dev/stfpcie.c

595

mask &= ~(IMASK_INT_INTA << pin);

sys/arch/riscv64/dev/stfpcie.c

596

HWRITE4(sc, IMASK_LOCAL, mask);

sys/arch/riscv64/dev/stfpcie.c

612

mask = HREAD4(sc, IMASK_LOCAL);

sys/arch/riscv64/dev/stfpcie.c

613

mask |= (IMASK_INT_INTA << pin);

sys/arch/riscv64/dev/stfpcie.c

614

HWRITE4(sc, IMASK_LOCAL, mask);

sys/arch/riscv64/dev/stfpcie.c

624

uint32_t mask;

sys/arch/riscv64/dev/stfpcie.c

627

mask = HREAD4(sc, IMASK_LOCAL);

sys/arch/riscv64/dev/stfpcie.c

628

mask &= ~(IMASK_INT_INTA << si->si_pin);

sys/arch/riscv64/dev/stfpcie.c

629

HWRITE4(sc, IMASK_LOCAL, mask);

sys/arch/riscv64/dev/stfpcie.c

639

mask = HREAD4(sc, IMASK_LOCAL);

sys/arch/riscv64/dev/stfpcie.c

640

mask |= (IMASK_INT_INTA << si->si_pin);

sys/arch/riscv64/dev/stfpcie.c

641

HWRITE4(sc, IMASK_LOCAL, mask);

sys/arch/riscv64/riscv64/cpu.c

398

vaddr_t end, mask;

sys/arch/riscv64/riscv64/cpu.c

400

mask = zicbom_dcache_line_size - 1;

sys/arch/riscv64/riscv64/cpu.c

401

end = (va + len + mask) & ~mask;

sys/arch/riscv64/riscv64/cpu.c

402

va &= ~mask;

sys/arch/riscv64/riscv64/cpu.c

416

vaddr_t end, mask;

sys/arch/riscv64/riscv64/cpu.c

418

mask = zicbom_dcache_line_size - 1;

sys/arch/riscv64/riscv64/cpu.c

419

end = (va + len + mask) & ~mask;

sys/arch/riscv64/riscv64/cpu.c

420

va &= ~mask;

sys/arch/riscv64/riscv64/cpu.c

434

vaddr_t end, mask;

sys/arch/riscv64/riscv64/cpu.c

436

mask = zicbom_dcache_line_size - 1;

sys/arch/riscv64/riscv64/cpu.c

437

end = (va + len + mask) & ~mask;

sys/arch/riscv64/riscv64/cpu.c

438

va &= ~mask;

sys/arch/riscv64/riscv64/cpu.c

452

vaddr_t end, mask;

sys/arch/riscv64/riscv64/cpu.c

454

mask = thead_dcache_line_size - 1;

sys/arch/riscv64/riscv64/cpu.c

455

end = (va + len + mask) & ~mask;

sys/arch/riscv64/riscv64/cpu.c

456

va &= ~mask;

sys/arch/riscv64/riscv64/cpu.c

470

vaddr_t end, mask;

sys/arch/riscv64/riscv64/cpu.c

472

mask = thead_dcache_line_size - 1;

sys/arch/riscv64/riscv64/cpu.c

473

end = (va + len + mask) & ~mask;

sys/arch/riscv64/riscv64/cpu.c

474

va &= ~mask;

sys/arch/riscv64/riscv64/cpu.c

489

vaddr_t end, mask;

sys/arch/riscv64/riscv64/cpu.c

491

mask = thead_dcache_line_size - 1;

sys/arch/riscv64/riscv64/cpu.c

492

end = (va + len + mask) & ~mask;

sys/arch/riscv64/riscv64/cpu.c

493

va &= ~mask;

sys/arch/riscv64/riscv64/db_disasm.c

83

int mask;

sys/arch/riscv64/riscv64/db_disasm.c

91

if (((insn ^ op->match) & op->mask) == 0)

sys/arch/riscv64/riscv64/intr.c

104

uint32_t mask, rid_base, rid;

sys/arch/riscv64/riscv64/intr.c

120

mask = OF_getpropint(node, "msi-map-mask", 0xffff);

sys/arch/riscv64/riscv64/intr.c

121

rid = *data & mask;

sys/arch/riscv64/riscv64/sig_machdep.c

143

frame.sf_sc.sc_mask = mask;

sys/arch/riscv64/riscv64/sig_machdep.c

96

sendsig(sig_t catcher, int sig, sigset_t mask, const siginfo_t *ksip,

sys/arch/sh/sh/cache_sh4.c

184

cache_sh4_op_line_32(vaddr_t va, vaddr_t base, uint32_t mask, uint32_t bits)

sys/arch/sh/sh/cache_sh4.c

188

cca = base | (va & mask);

sys/arch/sh/sh/cache_sh4.c

198

cache_sh4_op_8lines_32(vaddr_t va, vaddr_t base, uint32_t mask, uint32_t bits)

sys/arch/sh/sh/cache_sh4.c

201

(base | (va & mask));

sys/arch/sh/sh/cache_sh4.c

350

cache_sh4_emode_op_line_32(vaddr_t va, vaddr_t base, uint32_t mask,

sys/arch/sh/sh/cache_sh4.c

356

va &= mask;

sys/arch/sh/sh/cache_sh4.c

372

cache_sh4_emode_op_8lines_32(vaddr_t va, vaddr_t base, uint32_t mask,

sys/arch/sh/sh/cache_sh4.c

378

va &= mask;

sys/arch/sh/sh/sh_machdep.c

450

sendsig(sig_t catcher, int sig, sigset_t mask, const siginfo_t *ksip,

sys/arch/sh/sh/sh_machdep.c

485

frame.sf_uc.sc_mask = mask;

sys/arch/sparc64/dev/auxio.c

156

auxio_flip(struct auxio_softc *sc, uint32_t mask, uint32_t set)

sys/arch/sparc64/dev/auxio.c

168

led = (led & ~mask) | set;

sys/arch/sparc64/dev/ce4231.c

588

ce4231_set_outputs(struct ce4231_softc *sc, int mask)

sys/arch/sparc64/dev/ce4231.c

593

if (!(mask & OUT_PORT_SPKR))

sys/arch/sparc64/dev/ce4231.c

598

if (!(mask & OUT_PORT_LINE))

sys/arch/sparc64/dev/ce4231.c

600

if (!(mask & OUT_PORT_HP))

sys/arch/sparc64/dev/ce4231.c

608

int mask = 0;

sys/arch/sparc64/dev/ce4231.c

612

mask |= OUT_PORT_SPKR;

sys/arch/sparc64/dev/ce4231.c

616

mask |= OUT_PORT_LINE;

sys/arch/sparc64/dev/ce4231.c

618

mask |= OUT_PORT_HP;

sys/arch/sparc64/dev/ce4231.c

620

return (mask);

sys/arch/sparc64/dev/ce4231.c

663

ce4231_set_outputs(sc, cp->un.mask);

sys/arch/sparc64/dev/ce4231.c

810

cp->un.mask = ce4231_get_outputs(sc);

sys/arch/sparc64/dev/ce4231.c

944

dip->un.s.member[0].mask = OUT_PORT_LINE;

sys/arch/sparc64/dev/ce4231.c

946

dip->un.s.member[1].mask = OUT_PORT_HP;

sys/arch/sparc64/dev/ce4231.c

948

dip->un.s.member[2].mask = OUT_PORT_SPKR;

sys/arch/sparc64/dev/creator.c

303

error = copyout(sc->sc_curs_mask, curs->mask, l);

sys/arch/sparc64/dev/creator.c

343

u_int8_t r[2], g[2], b[2], image[128], mask[128];

sys/arch/sparc64/dev/creator.c

373

error = copyin(curs->mask, mask, imcount);

sys/arch/sparc64/dev/creator.c

400

bcopy(mask, sc->sc_curs_mask, imcount);

sys/arch/sparc64/dev/ifb.c

1089

int32_t mask;

sys/arch/sparc64/dev/ifb.c

1092

mask = IFB_PIXELMASK & bg;

sys/arch/sparc64/dev/ifb.c

1093

if (mask != 0) {

sys/arch/sparc64/dev/ifb.c

1094

ifb_rop(sc, x, y, x, y, w, h, IFB_ROP_SET, mask);

sys/arch/sparc64/dev/ifb.c

1099

mask = IFB_PIXELMASK & ~bg;

sys/arch/sparc64/dev/ifb.c

1100

if (mask != 0) {

sys/arch/sparc64/dev/ifb.c

1101

ifb_rop(sc, x, y, x, y, w, h, IFB_ROP_CLEAR, mask);

sys/arch/sparc64/dev/vbus.c

123

vbus_cmp_cells(int *cell1, int *cell2, int *mask, int ncells)

sys/arch/sparc64/dev/vbus.c

128

if (((cell1[i] ^ cell2[i]) & mask[i]) != 0)

sys/arch/sparc64/fpu/fpu.c

277

int opf, rdtype, rd, err, mask, cx, fsr;

sys/arch/sparc64/fpu/fpu.c

399

mask = (fsr >> FSR_TEM_SHIFT) & FSR_TEM_MASK;

sys/arch/sparc64/fpu/fpu.c

400

if (cx & mask) {

sys/arch/sparc64/fpu/fpu.c

404

(cx_to_trapx[(cx & mask) - 1] << FSR_CX_SHIFT);

sys/arch/sparc64/fpu/fpu_explode.c

175

exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS);

sys/arch/sparc64/fpu/fpu_explode.c

176

frac = i & mask(SNG_FRACBITS);

sys/arch/sparc64/fpu/fpu_explode.c

193

exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS);

sys/arch/sparc64/fpu/fpu_explode.c

194

frac = i & mask(DBL_FRACBITS - 32);

sys/arch/sparc64/fpu/fpu_explode.c

215

exp = (i >> (32 - 1 - EXT_EXPBITS)) & mask(EXT_EXPBITS);

sys/arch/sparc64/fpu/fpu_explode.c

216

frac = i & mask(EXT_FRACBITS - 3 * 32);

sys/arch/sparc64/include/pmap.h

105

u_int64_t mask;

sys/arch/sparc64/sparc64/machdep.c

382

sendsig(sig_t catcher, int sig, sigset_t mask, const siginfo_t *ksip,

sys/arch/sparc64/sparc64/machdep.c

419

sf.sf_sc.sc_mask = mask;

sys/arch/sparc64/sparc64/ofw_machdep.c

791

static int compare_cells (int *cell1, int *cell2, int *mask, int ncells);

sys/arch/sparc64/sparc64/ofw_machdep.c

793

compare_cells(int *cell1, int *cell2, int *mask, int ncells)

sys/arch/sparc64/sparc64/ofw_machdep.c

800

mask[i], ((cell1[i] ^ cell2[i]) & mask[i])));

sys/arch/sparc64/sparc64/ofw_machdep.c

801

if (((cell1[i] ^ cell2[i]) & mask[i]) != 0)

sys/arch/sparc64/sparc64/pmap.c

1072

for (k = 0; page_size_map[k].mask; k++) {

sys/arch/sparc64/sparc64/pmap.c

1075

page_size_map[k].mask) == 0 &&

sys/arch/sparc64/sparc64/pmap.c

1076

page_size_map[k].mask <

sys/crypto/gmac.c

44

uint32_t mask;

sys/crypto/gmac.c

54

mask = !!(x[i >> 3] & (1 << (~i & 7)));

sys/crypto/gmac.c

55

mask = ~(mask - 1);

sys/crypto/gmac.c

56

z[0] ^= v[0] & mask;

sys/crypto/gmac.c

57

z[1] ^= v[1] & mask;

sys/crypto/gmac.c

58

z[2] ^= v[2] & mask;

sys/crypto/gmac.c

59

z[3] ^= v[3] & mask;

sys/crypto/gmac.c

62

mask = ~((v[3] & 1) - 1);

sys/crypto/gmac.c

66

v[0] = (v[0] >> 1) ^ (0xe1000000 & mask);

sys/crypto/poly1305.c

201

unsigned long mask;

sys/crypto/poly1305.c

252

mask = (g4 >> ((sizeof(unsigned long) * 8) - 1)) - 1;

sys/crypto/poly1305.c

253

g0 &= mask;

sys/crypto/poly1305.c

254

g1 &= mask;

sys/crypto/poly1305.c

255

g2 &= mask;

sys/crypto/poly1305.c

256

g3 &= mask;

sys/crypto/poly1305.c

257

g4 &= mask;

sys/crypto/poly1305.c

258

mask = ~mask;

sys/crypto/poly1305.c

259

h0 = (h0 & mask) | g0;

sys/crypto/poly1305.c

260

h1 = (h1 & mask) | g1;

sys/crypto/poly1305.c

261

h2 = (h2 & mask) | g2;

sys/crypto/poly1305.c

262

h3 = (h3 & mask) | g3;

sys/crypto/poly1305.c

263

h4 = (h4 & mask) | g4;

sys/ddb/db_examine.c

333

db_expr_t mask;

sys/ddb/db_examine.c

372

if (!db_expression(&mask))

sys/ddb/db_examine.c

373

mask = (int) ~0;

sys/ddb/db_examine.c

388

db_search(addr, size, value, mask, count);

sys/ddb/db_examine.c

392

db_search(vaddr_t addr, int size, db_expr_t value, db_expr_t mask,

sys/ddb/db_examine.c

398

if ((db_get_value(addr, size, 0) & mask) == value)

sys/dev/acpi/acpi.c

2344

uint8_t mask, en;

sys/dev/acpi/acpi.c

2347

mask = (1L << (gpe & 7));

sys/dev/acpi/acpi.c

2350

gpe, (en & mask) ? "en" : "dis", en);

sys/dev/acpi/acpi.c

2351

acpi_write_pmreg(sc, ACPIREG_GPE_EN, gpe>>3, en | mask);

sys/dev/acpi/acpi.c

2421

uint8_t mask, en;

sys/dev/acpi/acpi.c

2426

mask = (1L << (gpe & 7));

sys/dev/acpi/acpi.c

2428

acpi_write_pmreg(sc, ACPIREG_GPE_STS, gpe>>3, mask);

sys/dev/acpi/acpi.c

2430

acpi_write_pmreg(sc, ACPIREG_GPE_EN, gpe>>3, en | mask);

sys/dev/acpi/acpidmar.h

234

iommu_rmw32(void *ov, uint32_t mask, uint32_t shift, uint32_t nv)

sys/dev/acpi/acpidmar.h

236

*(uint32_t *)ov &= ~(mask << shift);

sys/dev/acpi/acpidmar.h

237

*(uint32_t *)ov |= (nv & mask) << shift;

sys/dev/acpi/acpidmar.h

241

iommu_rmw64(void *ov, uint32_t mask, uint32_t shift, uint64_t nv)

sys/dev/acpi/acpidmar.h

243

*(uint64_t *)ov &= ~(mask << shift);

sys/dev/acpi/acpidmar.h

244

*(uint64_t *)ov |= (nv & mask) << shift;

sys/dev/acpi/acpiec.c

101

while (((stat = acpiec_status(sc)) & mask) != val) {

sys/dev/acpi/acpiec.c

365

uint8_t mask, stat, en;

sys/dev/acpi/acpiec.c

388

mask = (1L << (gpe & 7));

sys/dev/acpi/acpiec.c

390

acpi_write_pmreg(acpi_sc, ACPIREG_GPE_EN, gpe>>3, en | mask);

sys/dev/acpi/acpiec.c

91

acpiec_wait(struct acpiec_softc *sc, uint8_t mask, uint8_t val)

sys/dev/acpi/acpiec.c

98

DEVNAME(sc), (int)mask,

sys/dev/acpi/acpithinkpad.c

420

int64_t mask;

sys/dev/acpi/acpithinkpad.c

425

0, NULL, &mask)) {

sys/dev/acpi/acpithinkpad.c

431

mask |= (THINKPAD_MASK_MIC_MUTE |

sys/dev/acpi/acpithinkpad.c

436

DPRINTF(("%s: setting event mask to 0x%llx\n", DEVNAME(sc), mask));

sys/dev/acpi/acpithinkpad.c

443

args[1].v_integer = (((1 << i) & mask) != 0);

sys/dev/acpi/acpitimer.c

117

uint32_t mask = acpi_timecounter.tc_counter_mask;

sys/dev/acpi/acpitimer.c

126

count += (val2 - val1) & mask;

sys/dev/acpi/acpiwmi.c

296

int maxval = 1, mask = 0;

sys/dev/acpi/acpiwmi.c

301

mask = 0x80;

sys/dev/acpi/acpiwmi.c

311

asus_dev_set(wh, devid, *val | mask);

sys/dev/acpi/tpm.c

606

uint32_t r, mask;

sys/dev/acpi/tpm.c

617

mask = TPM_CRB_LOC_STATE_ASSIGNED | TPM_CRB_LOC_VALID;

sys/dev/acpi/tpm.c

620

while ((r & mask) != mask && to--) {

sys/dev/acpi/tpm.c

625

if ((r & mask) != mask) {

sys/dev/acpi/tpm.c

693

tpm_waitfor(struct tpm_softc *sc, bus_size_t offset, uint32_t mask,

sys/dev/acpi/tpm.c

702

if ((r & mask) == val)

sys/dev/acpi/tpm.c

707

if ((r & mask) == val)

sys/dev/acpi/tpm.c

714

sc->sc_dev.dv_xname, __func__, r, mask));

sys/dev/acpi/tpm.c

719

tpm_waitfor_status(struct tpm_softc *sc, uint8_t mask, int msecs)

sys/dev/acpi/tpm.c

726

while (((status = tpm_status(sc)) & mask) != mask) {

sys/dev/acpi/tpm.c

729

sc->sc_dev.dv_xname, __func__, status, mask));

sys/dev/acpi/tpm.c

783

uint32_t sz = 0, mask, rc;

sys/dev/acpi/tpm.c

829

mask = TPM_CRB_CTRL_STS_IDLE_BIT;

sys/dev/acpi/tpm.c

830

if (tpm_waitfor(sc, TPM_CRB_CTRL_STS, mask, mask, 200)) {

sys/dev/acpi/tpm.c

917

uint32_t r, mask;

sys/dev/acpi/tpm.c

948

mask = TPM_CRB_CTRL_STS_IDLE_BIT;

sys/dev/acpi/tpm.c

949

if (tpm_waitfor(sc, TPM_CRB_CTRL_STS, mask, mask, 200)) {

sys/dev/acpi/tpm.c

958

mask = TPM_CRB_CTRL_REQ_GO_READY;

sys/dev/acpi/tpm.c

959

if (tpm_waitfor(sc, TPM_CRB_CTRL_STS, mask, !mask, 200)) {

sys/dev/acpi/tpm.c

986

mask = ~0;

sys/dev/acpi/tpm.c

987

if (tpm_waitfor(sc, TPM_CRB_CTRL_START, mask, ~mask, 200)) {

sys/dev/adb/ams.c

446

int i, button_bit, max_byte, mask;

sys/dev/adb/ams.c

483

for (mask = 0x80; i < max_byte;

sys/dev/adb/ams.c

484

i += (mask == 0x80), button_bit <<= 1) {

sys/dev/adb/ams.c

486

if (!(event->bytes[i] & mask))

sys/dev/adb/ams.c

490

mask = ((mask >> 4) & 0xf)

sys/dev/adb/ams.c

491

| ((mask & 0xf) << 4);

sys/dev/cardbus/cardbus_map.c

100

bus_addr_t mask = size - 1;

sys/dev/cardbus/cardbus_map.c

102

mask = 0xffffffff;

sys/dev/cardbus/cardbus_map.c

103

if ((*cf->cardbus_space_alloc)(cc, rbustag, base, size, mask,

sys/dev/cardbus/rbus.c

55

bus_addr_t mask, bus_addr_t align, int flags, bus_addr_t *addrp,

sys/dev/cardbus/rbus.c

59

addr, size, mask, align, flags, addrp, bshp));

sys/dev/cardbus/rbus.c

65

bus_addr_t mask, bus_addr_t align, int flags, bus_addr_t *addrp,

sys/dev/cardbus/rbus.c

68

bus_addr_t decodesize = mask + 1;

sys/dev/cardbus/rbus.c

75

(u_long)addr, (u_long)size, (u_long)mask, (u_long)align));

sys/dev/cardbus/rbus.c

77

if (mask == 0) {

sys/dev/fdt/amlpwrc.c

119

amlpwrc_toggle(struct regmap *rm, bus_size_t reg, uint32_t mask, int on)

sys/dev/fdt/amlpwrc.c

125

val &= ~mask;

sys/dev/fdt/amlpwrc.c

127

val |= mask;

sys/dev/fdt/axppmic.c

879

uint8_t mask = sc->sc_sensdata[i].base;

sys/dev/fdt/axppmic.c

884

sc->sc_sensor[i].value = (value & mask) ? 1 : 0;

sys/dev/fdt/axppmic.c

885

if (value & mask) {

sys/dev/fdt/axppmic.c

897

uint8_t mask = sc->sc_sensdata[i].base;

sys/dev/fdt/axppmic.c

902

sc->sc_sensor[i].value = (value & mask) * 1000;

sys/dev/fdt/axppmic.c

905

if ((value & mask) <= sc->sc_crit)

sys/dev/fdt/axppmic.c

907

else if ((value & mask) <= sc->sc_warn)

sys/dev/fdt/bcm2835_bsc.c

184

bcmbsc_wait(struct bcmbsc_softc *sc, uint32_t mask, uint32_t value)

sys/dev/fdt/bcm2835_bsc.c

191

if ((stat & mask) == value)

sys/dev/fdt/bcmstbgpio.c

235

uint32_t mask, stat;

sys/dev/fdt/bcmstbgpio.c

239

mask = HREAD4(sc, GIO_MASK(bank));

sys/dev/fdt/bcmstbgpio.c

240

stat = HREAD4(sc, GIO_STAT(bank)) & mask;

sys/dev/fdt/bd718x7.c

142

bd->bd_mask = sc->sc_regdata[i].mask;

sys/dev/fdt/bd718x7.c

36

uint8_t reg, mask;

sys/dev/fdt/dwpcie.c

1045

uint32_t reg, mask;

sys/dev/fdt/dwpcie.c

1047

mask = PCIE_GLOBAL_STATUS_RDLH_LINK_UP;

sys/dev/fdt/dwpcie.c

1048

mask |= PCIE_GLOBAL_STATUS_PHY_LINK_UP;

sys/dev/fdt/dwpcie.c

1050

return ((reg & mask) == mask);

sys/dev/fdt/dwpcie.c

1645

uint32_t mask = (1U << pin);

sys/dev/fdt/dwpcie.c

1655

PCIE_CLIENT_INTR_MASK_LEGACY, (mask << 16) | mask);

sys/dev/fdt/dwpcie.c

1672

PCIE_CLIENT_INTR_MASK_LEGACY, mask << 16);

sys/dev/fdt/dwpcie.c

1682

uint32_t mask = (1U << di->di_pin);

sys/dev/fdt/dwpcie.c

1686

PCIE_CLIENT_INTR_MASK_LEGACY, (mask << 16) | mask);

sys/dev/fdt/dwpcie.c

1697

PCIE_CLIENT_INTR_MASK_LEGACY, mask << 16);

sys/dev/fdt/es8316ac.c

396

uint8_t mask[2];

sys/dev/fdt/es8316ac.c

425

.mask = {

sys/dev/fdt/es8316ac.c

444

.mask = {

sys/dev/fdt/es8316ac.c

462

.mask = {

sys/dev/fdt/es8316ac.c

485

.mask = {

sys/dev/fdt/es8316ac.c

508

.mask = {

sys/dev/fdt/es8316ac.c

540

shift = 8 - fls(mix->mask[ch]);

sys/dev/fdt/es8316ac.c

543

nvol = mix->mask[ch] - nvol;

sys/dev/fdt/es8316ac.c

547

val &= ~(mix->mask[ch] << mix->shift[ch]);

sys/dev/fdt/es8316ac.c

548

val |= (nvol & mix->mask[ch]) << mix->shift[ch];

sys/dev/fdt/es8316ac.c

560

val |= mix->mask[0];

sys/dev/fdt/es8316ac.c

562

val &= ~mix->mask[0];

sys/dev/fdt/es8316ac.c

589

shift = 8 - fls(mix->mask[ch]);

sys/dev/fdt/es8316ac.c

590

nvol = (val >> mix->shift[ch]) & mix->mask[ch];

sys/dev/fdt/es8316ac.c

592

nvol = mix->mask[ch] - nvol;

sys/dev/fdt/es8316ac.c

602

mc->un.ord = (val & mix->mask[0]) != 0;

sys/dev/fdt/es8316ac.c

633

256 / (mix->mask[0] + 1);

sys/dev/fdt/if_mvpp.c

3486

uint8_t mask = MVPP2_PRS_PORT_MASK;

sys/dev/fdt/if_mvpp.c

3489

pe->tcam.byte[enable_off] &= ~mask;

sys/dev/fdt/if_mvpp.c

3557

uint8_t byte, mask;

sys/dev/fdt/if_mvpp.c

3561

mvpp2_prs_tcam_data_byte_get(pe, position, &byte, &mask);

sys/dev/fdt/if_mvpp.c

3563

((uint8_t *)enable)[index] = mask;

sys/dev/fdt/if_mvpp.c

3588

mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe, uint32_t bits, uint32_t mask)

sys/dev/fdt/if_mvpp.c

3593

if (!(mask & BIT(i)))

sys/dev/fdt/if_mvpp.c

3614

mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe, uint32_t bits, uint32_t mask)

sys/dev/fdt/if_mvpp.c

3619

if (!(mask & BIT(i)))

sys/dev/fdt/if_mvpp.c

4230

int mask, tid;

sys/dev/fdt/if_mvpp.c

4249

mask = MVPP2_PRS_IPV4_BC_MASK;

sys/dev/fdt/if_mvpp.c

4250

mvpp2_prs_tcam_data_byte_set(&pe, 0, mask, mask);

sys/dev/fdt/if_mvpp.c

4251

mvpp2_prs_tcam_data_byte_set(&pe, 1, mask, mask);

sys/dev/fdt/if_mvpp.c

4252

mvpp2_prs_tcam_data_byte_set(&pe, 2, mask, mask);

sys/dev/fdt/if_mvpp.c

4253

mvpp2_prs_tcam_data_byte_set(&pe, 3, mask, mask);

sys/dev/fdt/if_mvpp.c

4341

uint8_t *mask)

sys/dev/fdt/if_mvpp.c

4349

if (tcam_mask != mask[index])

sys/dev/fdt/if_mvpp.c

4351

if ((tcam_mask & tcam_byte) != (da[index] & mask[index]))

sys/dev/fdt/if_mvpp.c

4360

uint8_t *mask, int udf_type)

sys/dev/fdt/if_mvpp.c

4376

if (mvpp2_prs_mac_range_equals(&pe, da, mask) &&

sys/dev/fdt/if_mvpp.c

4390

uint8_t mask[ETHER_ADDR_LEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };

sys/dev/fdt/if_mvpp.c

4395

tid = mvpp2_prs_mac_da_range_find(sc, BIT(port->sc_id), da, mask,

sys/dev/fdt/if_mvppreg.h

230

#define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)

sys/dev/fdt/if_mvppreg.h

231

#define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)

sys/dev/fdt/imxccm.c

1013

mux &= sc->sc_muxs[idx].mask;

sys/dev/fdt/imxccm.c

1042

mux &= sc->sc_muxs[idx].mask;

sys/dev/fdt/imxccm.c

1063

mux &= sc->sc_muxs[idx].mask;

sys/dev/fdt/imxccm.c

1090

mux &= sc->sc_muxs[idx].mask;

sys/dev/fdt/imxccm.c

1111

mux &= sc->sc_muxs[idx].mask;

sys/dev/fdt/imxccm.c

1134

mux &= sc->sc_muxs[idx].mask;

sys/dev/fdt/imxccm.c

1323

reg &= ~(sc->sc_divs[idx].mask << sc->sc_divs[idx].shift);

sys/dev/fdt/imxccm.c

1327

sc->sc_predivs[idx].mask << sc->sc_predivs[idx].shift);

sys/dev/fdt/imxccm.c

1512

div = div & sc->sc_divs[idx].mask;

sys/dev/fdt/imxccm.c

1561

div = div & sc->sc_divs[idx].mask;

sys/dev/fdt/imxccm.c

1563

pre = pre & sc->sc_predivs[idx].mask;

sys/dev/fdt/imxccm.c

1613

div = div & sc->sc_divs[idx].mask;

sys/dev/fdt/imxccm.c

1615

pre = pre & sc->sc_predivs[idx].mask;

sys/dev/fdt/imxccm.c

1677

div = div & sc->sc_divs[idx].mask;

sys/dev/fdt/imxccm.c

1679

pre = pre & sc->sc_predivs[idx].mask;

sys/dev/fdt/imxccm.c

1836

reg &= ~(sc->sc_divs[idx].mask << sc->sc_divs[idx].shift);

sys/dev/fdt/imxccm.c

1869

mux &= ~(sc->sc_muxs[idx].mask << sc->sc_muxs[idx].shift);

sys/dev/fdt/imxccm.c

1880

mux &= ~(sc->sc_muxs[idx].mask << sc->sc_muxs[idx].shift);

sys/dev/fdt/imxccm.c

1889

mux &= ~(sc->sc_muxs[idx].mask << sc->sc_muxs[idx].shift);

sys/dev/fdt/imxccm.c

1898

mux &= ~(sc->sc_muxs[idx].mask << sc->sc_muxs[idx].shift);

sys/dev/fdt/imxccm.c

1907

mux &= ~(sc->sc_muxs[idx].mask << sc->sc_muxs[idx].shift);

sys/dev/fdt/imxccm.c

1918

mux &= ~(sc->sc_muxs[idx].mask << sc->sc_muxs[idx].shift);

sys/dev/fdt/imxccm.c

1926

mux &= ~(sc->sc_muxs[idx].mask << sc->sc_muxs[idx].shift);

sys/dev/fdt/imxccm.c

1934

mux &= ~(sc->sc_muxs[idx].mask << sc->sc_muxs[idx].shift);

sys/dev/fdt/imxccm.c

194

uint16_t mask;

sys/dev/fdt/imxccm.c

1942

mux &= ~(sc->sc_muxs[idx].mask << sc->sc_muxs[idx].shift);

sys/dev/fdt/imxccm.c

1950

mux &= ~(sc->sc_muxs[idx].mask << sc->sc_muxs[idx].shift);

sys/dev/fdt/imxccm.c

1958

mux &= ~(sc->sc_muxs[idx].mask << sc->sc_muxs[idx].shift);

sys/dev/fdt/imxccm.c

1966

mux &= ~(sc->sc_muxs[idx].mask << sc->sc_muxs[idx].shift);

sys/dev/fdt/imxccm.c

1978

mux &= ~(sc->sc_muxs[idx].mask << sc->sc_muxs[idx].shift);

sys/dev/fdt/imxccm.c

1989

mux &= ~(sc->sc_muxs[idx].mask << sc->sc_muxs[idx].shift);

sys/dev/fdt/imxccm.c

1998

mux &= ~(sc->sc_muxs[idx].mask << sc->sc_muxs[idx].shift);

sys/dev/fdt/imxccm.c

2007

mux &= ~(sc->sc_muxs[idx].mask << sc->sc_muxs[idx].shift);

sys/dev/fdt/imxccm.c

2016

mux &= ~(sc->sc_muxs[idx].mask << sc->sc_muxs[idx].shift);

sys/dev/fdt/imxccm.c

202

uint16_t mask;

sys/dev/fdt/imxccm.c

571

mux &= sc->sc_muxs[idx].mask;

sys/dev/fdt/imxccm.c

594

mux &= sc->sc_muxs[idx].mask;

sys/dev/fdt/imxccm.c

617

mux &= sc->sc_muxs[idx].mask;

sys/dev/fdt/imxccm.c

638

mux &= sc->sc_muxs[idx].mask;

sys/dev/fdt/imxccm.c

781

mux &= sc->sc_muxs[idx].mask;

sys/dev/fdt/imxccm.c

804

mux &= sc->sc_muxs[idx].mask;

sys/dev/fdt/imxccm.c

833

mux &= sc->sc_muxs[idx].mask;

sys/dev/fdt/imxccm.c

854

mux &= sc->sc_muxs[idx].mask;

sys/dev/fdt/imxccm.c

875

mux &= sc->sc_muxs[idx].mask;

sys/dev/fdt/imxccm.c

898

mux &= sc->sc_muxs[idx].mask;

sys/dev/fdt/imxccm.c

921

mux &= sc->sc_muxs[idx].mask;

sys/dev/fdt/imxccm.c

944

mux &= sc->sc_muxs[idx].mask;

sys/dev/fdt/imxccm.c

967

mux &= sc->sc_muxs[idx].mask;

sys/dev/fdt/imxccm.c

990

mux &= sc->sc_muxs[idx].mask;

sys/dev/fdt/imxesdhc.c

1005

int mask;

sys/dev/fdt/imxesdhc.c

1029

mask = ISSET(cmd->c_flags, SCF_CMD_READ) ?

sys/dev/fdt/imxesdhc.c

1045

if ((error = imxesdhc_wait_state(sc, mask, mask)) != 0)

sys/dev/fdt/imxesdhc.c

1112

imxesdhc_soft_reset(struct imxesdhc_softc *sc, int mask)

sys/dev/fdt/imxesdhc.c

1116

DPRINTF(1,("%s: software reset reg=%#x\n", HDEVNAME(sc), mask));

sys/dev/fdt/imxesdhc.c

1122

HSET4(sc, SDHC_SYS_CTRL, mask);

sys/dev/fdt/imxesdhc.c

1126

if (!ISSET(HREAD4(sc, SDHC_SYS_CTRL), mask))

sys/dev/fdt/imxesdhc.c

1140

imxesdhc_wait_intr(struct imxesdhc_softc *sc, int mask, int secs)

sys/dev/fdt/imxesdhc.c

1145

mask |= SDHC_INT_STATUS_ERR;

sys/dev/fdt/imxesdhc.c

1149

if (mask & (SDHC_INT_STATUS_BRR | SDHC_INT_STATUS_BWR))

sys/dev/fdt/imxesdhc.c

1153

status = sc->intr_status & mask;

sys/dev/fdt/imxesdhc.c

1160

status = sc->intr_status & mask;

sys/dev/fdt/imxesdhc.c

780

imxesdhc_wait_state(struct imxesdhc_softc *sc, uint32_t mask, uint32_t value)

sys/dev/fdt/imxesdhc.c

787

HDEVNAME(sc), mask, value, state));

sys/dev/fdt/imxesdhc.c

789

if (((state = HREAD4(sc, SDHC_PRES_STATE)) & mask) == value)

sys/dev/fdt/imxgpio.c

207

uint32_t status, pending, mask;

sys/dev/fdt/imxgpio.c

211

mask = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_IMR);

sys/dev/fdt/imxgpio.c

213

status &= mask;

sys/dev/fdt/imxgpio.c

320

uint32_t mask;

sys/dev/fdt/imxgpio.c

330

mask = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_IMR);

sys/dev/fdt/imxgpio.c

331

mask &= ~(1 << ih->ih_irq);

sys/dev/fdt/imxgpio.c

332

bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_IMR, mask);

sys/dev/fdt/imxgpio.c

390

uint32_t mask;

sys/dev/fdt/imxgpio.c

394

mask = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_IMR);

sys/dev/fdt/imxgpio.c

395

mask |= (1 << ih->ih_irq);

sys/dev/fdt/imxgpio.c

396

bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_IMR, mask);

sys/dev/fdt/imxgpio.c

405

uint32_t mask;

sys/dev/fdt/imxgpio.c

409

mask = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_IMR);

sys/dev/fdt/imxgpio.c

410

mask &= ~(1 << ih->ih_irq);

sys/dev/fdt/imxgpio.c

411

bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_IMR, mask);

sys/dev/fdt/imxspi.c

292

imxspi_wait_state(struct imxspi_softc *sc, uint32_t mask, uint32_t value)

sys/dev/fdt/imxspi.c

298

if (((state = HREAD4(sc, SPI_STATREG)) & mask) == value)

sys/dev/fdt/imxspi.c

302

printf("%s: timeout mask %x value %x\n", __func__, mask, value);

sys/dev/fdt/mtxhci.c

185

uint32_t mask, val;

sys/dev/fdt/mtxhci.c

218

mask = (STA_XHCI | STA_PLL | STA_SYS | STA_REF);

sys/dev/fdt/mtxhci.c

220

mask |= STA_USB3;

sys/dev/fdt/mtxhci.c

244

if ((val & mask) == mask)

sys/dev/fdt/mviic.c

177

mviic_wait_state(struct mviic_softc *sc, uint32_t mask, uint32_t value)

sys/dev/fdt/mviic.c

183

if (((state = HREAD4(sc, ISR)) & mask) == value)

sys/dev/fdt/mvspi.c

209

mvspi_wait_state(struct mvspi_softc *sc, uint32_t mask, uint32_t value)

sys/dev/fdt/mvspi.c

216

if (((state = HREAD4(sc, SPI_CTRL)) & mask) == value)

sys/dev/fdt/mvspi.c

220

printf("%s: timeout mask %x value %x\n", __func__, mask, value);

sys/dev/fdt/rkclock.c

1044

uint32_t mask = (1 << (idx % 16));

sys/dev/fdt/rkclock.c

1047

mask << 16 | (on ? mask : 0));

sys/dev/fdt/rkclock.c

1581

uint32_t mask = (1 << (idx % 16));

sys/dev/fdt/rkclock.c

1584

mask << 16 | (on ? mask : 0));

sys/dev/fdt/rkclock.c

2287

uint32_t mask = (1 << (idx % 16));

sys/dev/fdt/rkclock.c

2290

mask << 16 | (on ? mask : 0));

sys/dev/fdt/rkclock.c

3090

uint32_t mask = (1 << (idx % 16));

sys/dev/fdt/rkclock.c

3093

mask << 16 | (on ? mask : 0));

sys/dev/fdt/rkclock.c

3346

uint32_t bit, mask, reg;

sys/dev/fdt/rkclock.c

3398

mask = (1 << bit);

sys/dev/fdt/rkclock.c

3399

HWRITE4(sc, reg, mask << 16 | (on ? mask : 0));

sys/dev/fdt/rkclock.c

3931

uint32_t mask = (1 << (idx % 16));

sys/dev/fdt/rkclock.c

3934

mask << 16 | (on ? mask : 0));

sys/dev/fdt/rkclock.c

4415

uint32_t bit, mask, reg;

sys/dev/fdt/rkclock.c

4463

mask = (1 << bit);

sys/dev/fdt/rkclock.c

4464

HWRITE4(sc, reg, mask << 16 | (on ? mask : 0));

sys/dev/fdt/rkclock.c

5133

uint32_t bit, mask, reg;

sys/dev/fdt/rkclock.c

5305

mask = (1 << bit);

sys/dev/fdt/rkclock.c

5306

HWRITE4(sc, reg, mask << 16 | (on ? mask : 0));

sys/dev/fdt/rkgpio.c

360

uint32_t mask = bit << 16;

sys/dev/fdt/rkgpio.c

365

HWRITE4(sc, GPIO_INT_TYPE_L + off * 4, mask | bit);

sys/dev/fdt/rkgpio.c

366

HWRITE4(sc, GPIO_INT_POLARITY_L + off * 4, mask | bit);

sys/dev/fdt/rkgpio.c

369

HWRITE4(sc, GPIO_INT_TYPE_L + off * 4, mask | bit);

sys/dev/fdt/rkgpio.c

370

HWRITE4(sc, GPIO_INT_POLARITY_L + off * 4, mask);

sys/dev/fdt/rkgpio.c

373

HWRITE4(sc, GPIO_INT_TYPE_L + off * 4, mask);

sys/dev/fdt/rkgpio.c

374

HWRITE4(sc, GPIO_INT_POLARITY_L + off * 4, mask | bit);

sys/dev/fdt/rkgpio.c

377

HWRITE4(sc, GPIO_INT_TYPE_L + off * 4, mask);

sys/dev/fdt/rkgpio.c

378

HWRITE4(sc, GPIO_INT_POLARITY_L + off * 4, mask);

sys/dev/fdt/rkgpio.c

384

HWRITE4(sc, GPIO_SWPORT_DDR_L + off, mask);

sys/dev/fdt/rkgpio.c

385

HWRITE4(sc, GPIO_INT_MASK_L + off, mask);

sys/dev/fdt/rkgpio.c

422

uint32_t mask = bit << 16;

sys/dev/fdt/rkgpio.c

434

HWRITE4(sc, GPIO_INT_MASK_L + off, mask | bit);

sys/dev/fdt/rkgpio.c

489

uint32_t mask = bit << 16;

sys/dev/fdt/rkgpio.c

495

HWRITE4(sc, GPIO_INT_MASK_L + off, mask);

sys/dev/fdt/rkgpio.c

507

uint32_t mask = bit << 16;

sys/dev/fdt/rkgpio.c

513

HWRITE4(sc, GPIO_INT_MASK_L + off, mask | bit);

sys/dev/fdt/rkpinctrl.c

1184

uint32_t mask, bits;

sys/dev/fdt/rkpinctrl.c

1220

mask = (0x7 << ((idx % 4) * 4));

sys/dev/fdt/rkpinctrl.c

1222

regmap_write_4(rm, iomux_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

1227

mask = (0x3 << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

1229

regmap_write_4(rm, p_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

1235

mask = (0x3f << ((idx % 2) * 8));

sys/dev/fdt/rkpinctrl.c

1237

regmap_write_4(rm, ds_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

1243

mask = (0x3 << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

1245

regmap_write_4(rm, ie_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

1294

uint32_t mask, bits;

sys/dev/fdt/rkpinctrl.c

1354

mask = (0xf << ((idx % 4) * 4));

sys/dev/fdt/rkpinctrl.c

1356

regmap_write_4(rm, iomux_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

1361

mask = (0x3 << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

1363

regmap_write_4(rm, p_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

1369

mask = (0xf << ((idx % 4) * 4));

sys/dev/fdt/rkpinctrl.c

1371

regmap_write_4(rm, ds_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

1377

mask = (0x1 << (idx % 8));

sys/dev/fdt/rkpinctrl.c

1379

regmap_write_4(rm, smt_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

1503

uint32_t mask, bits;

sys/dev/fdt/rkpinctrl.c

1550

mask = (0xf << ((idx % 4) * 4));

sys/dev/fdt/rkpinctrl.c

1552

regmap_write_4(rm, iomux_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

1558

regmap_write_4(rm, iomux_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

1564

mask = (0x3 << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

1566

regmap_write_4(rm, p_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

1572

mask = (0xf << ((idx % 4) * 4));

sys/dev/fdt/rkpinctrl.c

1574

regmap_write_4(rm, ds_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

1580

mask = (0x1 << (idx % 8));

sys/dev/fdt/rkpinctrl.c

1582

regmap_write_4(rm, smt_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

285

uint32_t mask, bits;

sys/dev/fdt/rkpinctrl.c

315

mask = (0x7 << ((idx % 4) * 4));

sys/dev/fdt/rkpinctrl.c

318

mask = (0x3 << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

327

regmap_write_4(rm, base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

332

mask = (0x3 << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

334

regmap_write_4(rm, base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

340

mask = (0x3 << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

342

regmap_write_4(rm, base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

428

uint32_t mask, bits;

sys/dev/fdt/rkpinctrl.c

450

mask = (0xf << 12);

sys/dev/fdt/rkpinctrl.c

454

mask = 0x3;

sys/dev/fdt/rkpinctrl.c

457

mask = (0x3 << ((idx - 16) * 2));

sys/dev/fdt/rkpinctrl.c

460

mask = (0xf << (((idx - 18) * 4) + 4));

sys/dev/fdt/rkpinctrl.c

464

mask = (0xf << ((idx - 21) * 4));

sys/dev/fdt/rkpinctrl.c

467

mask = (0xf << (((idx - 12) * 4) + 8));

sys/dev/fdt/rkpinctrl.c

470

mask = (0x3 << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

473

regmap_write_4(rm, base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

478

mask = (0x3 << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

480

regmap_write_4(rm, base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

486

mask = (0x3 << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

488

regmap_write_4(rm, base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

574

uint32_t mask, bits;

sys/dev/fdt/rkpinctrl.c

596

mask = 0x7;

sys/dev/fdt/rkpinctrl.c

599

mask = (0x7 << ((idx - 16) * 3));

sys/dev/fdt/rkpinctrl.c

602

mask = (0x7 << ((idx - 21) * 3));

sys/dev/fdt/rkpinctrl.c

605

mask = (0x7 << (idx * 3));

sys/dev/fdt/rkpinctrl.c

608

mask = (0x7 << ((idx - 5) * 3));

sys/dev/fdt/rkpinctrl.c

611

mask = (0x7 << ((idx - 8) * 3));

sys/dev/fdt/rkpinctrl.c

614

mask = (0x7 << ((idx - 13) * 3));

sys/dev/fdt/rkpinctrl.c

617

mask = (0x3 << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

628

regmap_write_4(rm, base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

633

mask = (0x3 << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

635

regmap_write_4(rm, base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

641

mask = (0x3 << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

643

regmap_write_4(rm, base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

764

uint32_t mask, bits;

sys/dev/fdt/rkpinctrl.c

791

mask = (0x3 << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

793

regmap_write_4(rm, base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

798

mask = (0x3 << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

800

regmap_write_4(rm, base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

808

mask = (((1 << shift) - 1) << ((idx % 8) * shift));

sys/dev/fdt/rkpinctrl.c

810

if (mask & 0x0000ffff) {

sys/dev/fdt/rkpinctrl.c

812

mask << 16 | (bits & 0x0000ffff));

sys/dev/fdt/rkpinctrl.c

814

if (mask & 0xffff0000) {

sys/dev/fdt/rkpinctrl.c

816

(mask & 0xffff0000) | bits >> 16);

sys/dev/fdt/rkpinctrl.c

909

uint32_t mask, bits;

sys/dev/fdt/rkpinctrl.c

960

mask = (0x7 << ((idx % 4) * 4));

sys/dev/fdt/rkpinctrl.c

962

regmap_write_4(rm, iomux_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

967

mask = (0x3 << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

969

regmap_write_4(rm, p_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

975

mask = (0x3f << ((idx % 2) * 8));

sys/dev/fdt/rkpinctrl.c

977

regmap_write_4(rm, ds_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

983

mask = (0x1 << (idx % 8));

sys/dev/fdt/rkpinctrl.c

985

regmap_write_4(rm, st_base + off, mask << 16 | bits);

sys/dev/fdt/rkrng.c

263

uint32_t mask;

sys/dev/fdt/rkrng.c

266

mask = TRNG_V1_STAT_SEEDED;

sys/dev/fdt/rkrng.c

267

mask |= TRNG_V1_STAT_GENERATING | TRNG_V1_STAT_RESEEDING;

sys/dev/fdt/rkrng.c

270

if ((stat & mask) == TRNG_V1_STAT_SEEDED)

sys/dev/fdt/rkspi.c

252

rkspi_wait_state(struct rkspi_softc *sc, uint32_t mask, uint32_t value)

sys/dev/fdt/rkspi.c

257

if ((HREAD4(sc, SPI_SR) & mask) == value)

sys/dev/fdt/rkvop.c

581

uint32_t mask, val;

sys/dev/fdt/rkvop.c

587

mask = RK3399_VOP_MIPI_POL(RK3399_VOP_POL_MASK);

sys/dev/fdt/rkvop.c

591

mask = RK3399_VOP_EDP_POL(RK3399_VOP_POL_MASK);

sys/dev/fdt/rkvop.c

595

mask = RK3399_VOP_HDMI_POL(RK3399_VOP_POL_MASK);

sys/dev/fdt/rkvop.c

599

mask = RK3399_VOP_DP_POL(RK3399_VOP_POL_MASK);

sys/dev/fdt/rkvop.c

606

val &= ~mask;

sys/dev/fdt/sunxireg.h

26

#define SXICMS1(sc, reg, mask, bits) \

sys/dev/fdt/sunxireg.h

27

SXIWRITE1((sc), (reg), (SXIREAD1((sc), (reg)) & ~(mask)) | (bits))

sys/dev/fdt/sunxireg.h

37

#define SXICMS4(sc, reg, mask, bits) \

sys/dev/fdt/sunxireg.h

38

SXIWRITE4((sc), (reg), (SXIREAD4((sc), (reg)) & ~(mask)) | (bits))

sys/dev/fdt/sximmc.c

550

sximmc_wait_rint(struct sximmc_softc *sc, uint32_t mask, int timeout)

sys/dev/fdt/sximmc.c

557

if (sc->sc_intr_rint & mask)

sys/dev/fdt/sximmc.c

568

if (sc->sc_intr_rint & mask)

sys/dev/fdt/sximmc.c

572

if (sc->sc_intr_rint & mask)

sys/dev/fdt/sxipio.c

316

int group, port, pin, off, mask;

sys/dev/fdt/sxipio.c

382

off = (pin & 0x7) << 2, mask = (0x7 << off);

sys/dev/fdt/sxipio.c

383

SXICMS4(sc, SXIPIO_CFG(port, pin), mask, mux << off);

sys/dev/fdt/sxipio.c

384

off = (pin & 0xf) << 1, mask = (0x3 << off);

sys/dev/fdt/sxipio.c

386

SXICMS4(sc, SXIPIO_DRV(port, pin), mask, drive << off);

sys/dev/fdt/sxipio.c

388

SXICMS4(sc, SXIPIO_PUL(port, pin), mask, pull << off);

sys/dev/gpio/gpio.c

169

gpio_pin_map(void *gpio, int offset, u_int32_t mask, struct gpio_pinmap *map)

sys/dev/gpio/gpio.c

174

npins = gpio_npins(mask);

sys/dev/gpio/gpio.c

179

if (mask & (1 << i)) {

sys/dev/gpio/gpio.c

238

gpio_npins(u_int32_t mask)

sys/dev/gpio/gpio.c

243

if (mask & (1 << i))

sys/dev/gpio/gpiosim.c

117

sc->sc_state = (sc->sc_state & ~op->mask) |

sys/dev/gpio/gpiosim.c

118

(op->state & op->mask);

sys/dev/gpio/gpiosim.c

43

u_int32_t mask;

sys/dev/hid/hidkbd.c

507

if ((kbd->sc_odata.var[i] & kbd->sc_var[i].mask) !=

sys/dev/hid/hidkbd.c

508

(ud->var[i] & kbd->sc_var[i].mask)) {

sys/dev/hid/hidkbd.c

510

((ud->var[i] & kbd->sc_var[i].mask) ?

sys/dev/hid/hidkbd.c

761

kbd->sc_var[i].mask = 1 << (i % 8);

sys/dev/hid/hidkbdsc.h

44

u_int8_t mask;

sys/dev/i2c/i2c_bitbang.c

175

uint8_t mask;

sys/dev/i2c/i2c_bitbang.c

180

for (mask = 0x80; mask != 0; mask >>= 1) {

sys/dev/i2c/i2c_bitbang.c

181

bit = (val & mask) ? SDA : 0;

sys/dev/i2c/i2c_scan.c

184

u_int16_t temp, thyst, tos, tlow, thigh, mask = LM75TMASK;

sys/dev/i2c/i2c_scan.c

206

temp &= mask;

sys/dev/i2c/i2c_scan.c

207

thyst &= mask;

sys/dev/i2c/i2c_scan.c

208

tos &= mask;

sys/dev/i2c/i2c_scan.c

228

if ((iicprobew(LM75TEMP) & mask) != (iicprobew(i) & mask) ||

sys/dev/i2c/i2c_scan.c

229

(iicprobew(LM75Thyst) & mask) != (iicprobew(i) & mask) ||

sys/dev/i2c/i2c_scan.c

230

(iicprobew(LM75Tos) & mask) != (iicprobew(i) & mask))

sys/dev/i2c/i2c_scan.c

250

if ((iicprobew(LM75TEMP) & mask) != (iicprobew(i) & mask) ||

sys/dev/i2c/i2c_scan.c

251

(iicprobew(LM75Thyst) & mask) != (iicprobew(i) & mask) ||

sys/dev/i2c/i2c_scan.c

252

(iicprobew(LM75Tos) & mask) != (iicprobew(i) & mask))

sys/dev/i2c/i2c_scan.c

271

mask = LM77TMASK;

sys/dev/i2c/i2c_scan.c

274

thyst = iicprobew(LM75Thyst) & mask;

sys/dev/i2c/i2c_scan.c

275

tos = iicprobew(LM75Tos) & mask;

sys/dev/i2c/i2c_scan.c

276

tlow = iicprobew(LM77Tlow) & mask;

sys/dev/i2c/i2c_scan.c

277

thigh = iicprobew(LM77Thigh) & mask;

sys/dev/i2c/i2c_scan.c

283

thyst != (iicprobew(LM75Thyst + i) & mask) ||

sys/dev/i2c/i2c_scan.c

284

tos != (iicprobew(LM75Tos + i) & mask))

sys/dev/i2c/i2c_scan.c

292

tos = iicprobew(LM75Tos) & mask;

sys/dev/i2c/i2c_scan.c

293

if (tos != (iicprobew(0x06 + i) & mask) ||

sys/dev/i2c/i2c_scan.c

294

tos != (iicprobew(0x07 + i) & mask))

sys/dev/i2c/i2c_scan.c

308

tos = iicprobew(LM75Tos) & mask;

sys/dev/i2c/i2c_scan.c

309

if (tos != (iicprobew(LM77Tlow + i) & mask) ||

sys/dev/i2c/i2c_scan.c

310

tos != (iicprobew(LM77Thigh + i) & mask))

sys/dev/i2c/i2c_scan.c

317

if (tlow != (iicprobew(LM77Tlow + i) & mask) ||

sys/dev/i2c/i2c_scan.c

318

thigh != (iicprobew(LM77Thigh + i) & mask))

sys/dev/ic/aac.c

1918

aac_sa_clear_istatus(struct aac_softc *sc, int mask)

sys/dev/ic/aac.c

1920

AAC_SETREG2(sc, AAC_SA_DOORBELL0_CLEAR, mask);

sys/dev/ic/aac.c

1924

aac_rx_clear_istatus(struct aac_softc *sc, int mask)

sys/dev/ic/aac.c

1926

AAC_SETREG4(sc, AAC_RX_ODBR, mask);

sys/dev/ic/aac.c

1930

aac_fa_clear_istatus(struct aac_softc *sc, int mask)

sys/dev/ic/aac.c

1932

AAC_SETREG2(sc, AAC_FA_DOORBELL0_CLEAR, mask);

sys/dev/ic/aac.c

1937

aac_rkt_clear_istatus(struct aac_softc *sc, int mask)

sys/dev/ic/aac.c

1939

AAC_SETREG4(sc, AAC_RKT_ODBR, mask);

sys/dev/ic/aacvar.h

188

#define AAC_CLEAR_ISTATUS(sc, mask) \

sys/dev/ic/aacvar.h

189

((sc)->aac_if.aif_set_istatus((sc), (mask)))

sys/dev/ic/aacvar.h

45

#define AAC_DPRINTF(mask, args) if (aac_debug & (mask)) printf args

sys/dev/ic/aacvar.h

62

#define AAC_DPRINTF(mask, args)

sys/dev/ic/ac97.c

1039

u_int16_t mask;

sys/dev/ic/ac97.c

1060

mask = (1 << si->bits) - 1;

sys/dev/ic/ac97.c

1064

if (cp->un.ord > mask || cp->un.ord < 0)

sys/dev/ic/ac97.c

1070

mask |= (mask << 8);

sys/dev/ic/ac97.c

1071

mask = mask << si->ofs;

sys/dev/ic/ac97.c

1074

mask = 0x8080;

sys/dev/ic/ac97.c

1076

mask = mask << si->ofs;

sys/dev/ic/ac97.c

1080

mask |= mask << 8;

sys/dev/ic/ac97.c

1113

newval = ((l & mask) << si->ofs);

sys/dev/ic/ac97.c

1115

newval |= ((r & mask) << (si->ofs + 8));

sys/dev/ic/ac97.c

1116

mask |= (mask << 8);

sys/dev/ic/ac97.c

1118

mask = mask << si->ofs;

sys/dev/ic/ac97.c

1125

error = ac97_write(as, si->reg, (val & ~mask) | newval);

sys/dev/ic/ac97.c

1320

u_int16_t mask;

sys/dev/ic/ac97.c

1335

mask = (1 << si->bits) - 1;

sys/dev/ic/ac97.c

1339

cp->un.ord = (val >> si->ofs) & mask;

sys/dev/ic/ac97.c

1341

mask, cp->un.ord));

sys/dev/ic/ac97.c

1353

l = r = (val >> si->ofs) & mask;

sys/dev/ic/ac97.c

1356

l = (val >> si->ofs) & mask;

sys/dev/ic/ac97.c

1357

r = (val >> (si->ofs + 8)) & mask;

sys/dev/ic/ac97.c

1359

r = (val >> si->ofs) & mask;

sys/dev/ic/ac97.c

1360

l = (val >> (si->ofs + 8)) & mask;

sys/dev/ic/ac97.c

355

u_int8_t mask;

sys/dev/ic/ac97.c

818

if (codec->id == (id & codec->mask))

sys/dev/ic/ac97.c

821

if (codec >= vendor->codecs && codec->mask) {

sys/dev/ic/ahci.c

1254

u_int32_t mask;

sys/dev/ic/ahci.c

1256

mask = ahci_pread(ap, AHCI_PREG_CI);

sys/dev/ic/ahci.c

1258

mask |= ahci_pread(ap, AHCI_PREG_SACT);

sys/dev/ic/ahci.c

1259

return mask;

sys/dev/ic/ahci.c

1267

u_int32_t mask;

sys/dev/ic/ahci.c

1287

mask = ahci_active_mask(ap);

sys/dev/ic/ahci.c

1288

if (mask != 0) {

sys/dev/ic/ahci.c

1291

mask);

sys/dev/ic/ahci.c

2717

ahci_wait_ne(struct ahci_softc *sc, bus_size_t r, u_int32_t mask,

sys/dev/ic/ahci.c

2723

if ((ahci_read(sc, r) & mask) != target)

sys/dev/ic/ahci.c

2748

ahci_pwait_eq(struct ahci_port *ap, bus_size_t r, u_int32_t mask,

sys/dev/ic/ahci.c

2754

if ((ahci_pread(ap, r) & mask) == target)

sys/dev/ic/aic79xx.c

4785

int mask;

sys/dev/ic/aic79xx.c

4794

mask = ~0x23;

sys/dev/ic/aic79xx.c

4802

mask = ~0x03;

sys/dev/ic/aic79xx.c

4810

ahd_inb_scbram(ahd, SCB_CONTROL) & mask);

sys/dev/ic/aic79xx.c

4811

scb->hscb->control &= mask;

sys/dev/ic/aic79xx.c

8560

uint32_t mask;

sys/dev/ic/aic79xx.c

8562

mask = 0x01 << i;

sys/dev/ic/aic79xx.c

8563

if ((instr.integer & mask) != 0)

sys/dev/ic/aic79xx.c

8648

if (((value & table[entry].mask) != table[entry].value)

sys/dev/ic/aic79xx.c

8649

|| ((printed_mask & table[entry].mask) ==

sys/dev/ic/aic79xx.c

8650

table[entry].mask))

sys/dev/ic/aic79xx.c

8656

printed_mask |= table[entry].mask;

sys/dev/ic/aic79xx_openbsd.c

322

u_int mask;

sys/dev/ic/aic79xx_openbsd.c

376

mask = SCB_GET_TARGET_MASK(ahd, scb);

sys/dev/ic/aic79xx_openbsd.c

378

if ((tstate->discenable & mask) != 0)

sys/dev/ic/aic79xx_openbsd.c

381

if ((tstate->tagenable & mask) != 0)

sys/dev/ic/aic79xx_openbsd.c

390

if ((tstate->auto_negotiate & mask) != 0) {

sys/dev/ic/aic7xxx.c

3532

int mask;

sys/dev/ic/aic7xxx.c

3541

mask = ~0x23;

sys/dev/ic/aic7xxx.c

3549

mask = ~0x03;

sys/dev/ic/aic7xxx.c

3557

ahc_inb(ahc, SCB_CONTROL) & mask);

sys/dev/ic/aic7xxx.c

3558

scb->hscb->control &= mask;

sys/dev/ic/aic7xxx.c

4846

uint16_t mask;

sys/dev/ic/aic7xxx.c

4850

mask = (0x01 << i);

sys/dev/ic/aic7xxx.c

4861

| (ultraenb & mask)

sys/dev/ic/aic7xxx.c

4885

&& (ultraenb & mask) != 0) {

sys/dev/ic/aic7xxx.c

4888

ultraenb &= ~mask;

sys/dev/ic/aic7xxx.c

4892

(ultraenb & mask)

sys/dev/ic/aic7xxx.c

6334

uint32_t mask;

sys/dev/ic/aic7xxx.c

6336

mask = 0x01 << i;

sys/dev/ic/aic7xxx.c

6337

if ((instr.integer & mask) != 0)

sys/dev/ic/aic7xxx.c

6393

if (((value & table[entry].mask) != table[entry].value)

sys/dev/ic/aic7xxx.c

6394

|| ((printed_mask & table[entry].mask) ==

sys/dev/ic/aic7xxx.c

6395

table[entry].mask))

sys/dev/ic/aic7xxx.c

6401

printed_mask |= table[entry].mask;

sys/dev/ic/aic7xxx_openbsd.c

306

u_int mask;

sys/dev/ic/aic7xxx_openbsd.c

376

mask = SCB_GET_TARGET_MASK(ahc, scb);

sys/dev/ic/aic7xxx_openbsd.c

380

if ((tstate->ultraenb & mask) != 0)

sys/dev/ic/aic7xxx_openbsd.c

383

if ((tstate->discenable & mask) != 0)

sys/dev/ic/aic7xxx_openbsd.c

386

if ((tstate->auto_negotiate & mask) != 0) {

sys/dev/ic/aic7xxx_openbsd.c

391

if ((tstate->tagenable & mask) != 0)

sys/dev/ic/ar5008.c

1214

uint16_t mask = 0;

sys/dev/ic/ar5008.c

1219

mask |= MS(reg, AR_ISR_S0_QCU_TXOK);

sys/dev/ic/ar5008.c

1220

mask |= MS(reg, AR_ISR_S0_QCU_TXDESC);

sys/dev/ic/ar5008.c

1223

mask |= MS(reg, AR_ISR_S1_QCU_TXERR);

sys/dev/ic/ar5008.c

1224

mask |= MS(reg, AR_ISR_S1_QCU_TXEOL);

sys/dev/ic/ar5008.c

1226

DPRINTFN(4, ("Tx interrupt mask=0x%x\n", mask));

sys/dev/ic/ar5008.c

1227

for (qid = 0; mask != 0; mask >>= 1, qid++) {

sys/dev/ic/ar5008.c

1228

if (mask & 1)

sys/dev/ic/ar5008.c

2412

uint32_t mask[4], reg;

sys/dev/ic/ar5008.c

2419

mask[i] = 0;

sys/dev/ic/ar5008.c

2422

mask[i] |= 1 << bit;

sys/dev/ic/ar5008.c

2429

AR_WRITE(sc, AR_PHY_TIMING7, mask[0]);

sys/dev/ic/ar5008.c

2430

AR_WRITE(sc, AR_PHY_TIMING9, mask[0]);

sys/dev/ic/ar5008.c

2432

AR_WRITE(sc, AR_PHY_TIMING8, mask[1]);

sys/dev/ic/ar5008.c

2433

AR_WRITE(sc, AR_PHY_TIMING10, mask[1]);

sys/dev/ic/ar5008.c

2435

AR_WRITE(sc, AR_PHY_PILOT_MASK_01_30, mask[2]);

sys/dev/ic/ar5008.c

2436

AR_WRITE(sc, AR_PHY_CHANNEL_MASK_01_30, mask[2]);

sys/dev/ic/ar5008.c

2438

AR_WRITE(sc, AR_PHY_PILOT_MASK_31_60, mask[3]);

sys/dev/ic/ar5008.c

2439

AR_WRITE(sc, AR_PHY_CHANNEL_MASK_31_60, mask[3]);

sys/dev/ic/ar5210.c

1586

ar5k_ar5210_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask)

sys/dev/ic/ar5210.c

242

u_int32_t mask = val ? val : ~0;

sys/dev/ic/ar5210.c

256

mask &=

sys/dev/ic/ar5210.c

260

ret = ar5k_register_timeout(hal, AR5K_AR5210_RC, mask, val, AH_FALSE);

sys/dev/ic/ar5211.c

1692

ar5k_ar5211_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask)

sys/dev/ic/ar5211.c

239

u_int32_t mask = val ? val : ~0;

sys/dev/ic/ar5211.c

255

mask &=

sys/dev/ic/ar5211.c

258

ret = ar5k_register_timeout(hal, AR5K_AR5211_RC, mask, val, AH_FALSE);

sys/dev/ic/ar5212.c

2008

ar5k_ar5212_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask)

sys/dev/ic/ar5212.c

2012

low_id = AR5K_LOW_ID(mask);

sys/dev/ic/ar5212.c

2013

high_id = 0x0000ffff & AR5K_HIGH_ID(mask);

sys/dev/ic/ar5212.c

284

u_int32_t mask = val ? val : ~0;

sys/dev/ic/ar5212.c

300

mask &=

sys/dev/ic/ar5212.c

303

ret = ar5k_register_timeout(hal, AR5K_AR5212_RC, mask, val, AH_FALSE);

sys/dev/ic/ar5xxx.c

1274

u_int32_t mask, entry, last, data, shift, position;

sys/dev/ic/ar5xxx.c

1296

mask = (((1 << last) - 1) ^ ((1 << position) - 1)) <<

sys/dev/ic/ar5xxx.c

1300

rf[entry] &= ~mask;

sys/dev/ic/ar5xxx.c

1301

rf[entry] |= ((data << position) << (col * 8)) & mask;

sys/dev/ic/ar5xxx.c

1304

data = (((rf[entry] & mask) >> (col * 8)) >>

sys/dev/ic/ar9285.c

660

uint32_t reg, mask, clcgain, rf2g5_svg;

sys/dev/ic/ar9285.c

671

mask = 0;

sys/dev/ic/ar9285.c

679

if (!(mask & (1 << clcgain))) {

sys/dev/ic/ar9285.c

680

mask |= 1 << clcgain;

sys/dev/ic/arcofi.c

615

arcofi_portmask_to_cr3(int mask)

sys/dev/ic/arcofi.c

617

switch (mask) {

sys/dev/ic/athnreg.h

1480

#define AR_SETBITS(sc, reg, mask) \

sys/dev/ic/athnreg.h

1481

AR_WRITE(sc, reg, AR_READ(sc, reg) | (mask))

sys/dev/ic/athnreg.h

1483

#define AR_CLRBITS(sc, reg, mask) \

sys/dev/ic/athnreg.h

1484

AR_WRITE(sc, reg, AR_READ(sc, reg) & ~(mask))

sys/dev/ic/atw.c

1566

(sc->sc_srom[ATW_SR_CSR20] & mask) |

sys/dev/ic/atw.c

1916

uint32_t bits, mask, reg;

sys/dev/ic/atw.c

1942

for (mask = (1 << (nbits - 1)); mask != 0; mask >>= 1) {

sys/dev/ic/atw.c

1943

if ((bits & mask) != 0)

sys/dev/ic/atwreg.h

77

#define MASK_AND_RSHIFT(x, mask) (((x) & (mask)) >> MASK_TO_SHIFT(mask))

sys/dev/ic/atwreg.h

78

#define LSHIFT(x, mask) ((x) << MASK_TO_SHIFT(mask))

sys/dev/ic/atwreg.h

79

#define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask))

sys/dev/ic/atwvar.h

426

#define ATW_SET(sc, reg, mask) \

sys/dev/ic/atwvar.h

427

ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) | (mask))

sys/dev/ic/atwvar.h

429

#define ATW_CLR(sc, reg, mask) \

sys/dev/ic/atwvar.h

430

ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) & ~(mask))

sys/dev/ic/atwvar.h

432

#define ATW_ISSET(sc, reg, mask) \

sys/dev/ic/atwvar.h

433

(ATW_READ((sc), (reg)) & (mask))

sys/dev/ic/bcm2835_vcprop.h

224

uint32_t mask;

sys/dev/ic/bt485.c

393

if ((error = copyin(cursorp->mask, data->curmask,

sys/dev/ic/bt485.c

445

error = copyout(data->curmask, cursorp->mask, count);

sys/dev/ic/bwi.c

2902

uint16_t mask = 0x000f;

sys/dev/ic/bwi.c

2905

CSR_FILT_SETBITS_2(mac->mac_sc, BWI_BBP_ATTEN, ~mask,

sys/dev/ic/bwi.c

2906

__SHIFTIN(bbp_atten, mask));

sys/dev/ic/bwi.c

2909

mask <<= 2;

sys/dev/ic/bwi.c

2911

mask <<= 3;

sys/dev/ic/bwi.c

2912

PHY_FILT_SETBITS(mac, BWI_PHYR_BBP_ATTEN, ~mask,

sys/dev/ic/bwi.c

2913

__SHIFTIN(bbp_atten, mask));

sys/dev/ic/bwi.c

4621

uint16_t sprom_ofs, val, mask;

sys/dev/ic/bwi.c

4742

mask = BWI_SPROM_IDLE_TSSI_MASK_11A;

sys/dev/ic/bwi.c

4744

mask = BWI_SPROM_IDLE_TSSI_MASK_11BG;

sys/dev/ic/bwi.c

4746

rf->rf_idle_tssi0 = (int)__SHIFTOUT(val, mask);

sys/dev/ic/bwi.c

603

uint32_t mask;

sys/dev/ic/bwi.c

606

mask = BWI_TXRX_RX_INTRS;

sys/dev/ic/bwi.c

608

mask = BWI_TXRX_TX_INTRS;

sys/dev/ic/bwi.c

611

CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;

sys/dev/ic/gdtvar.h

42

#define GDT_DPRINTF(mask, args) if (gdt_debug & (mask)) printf args

sys/dev/ic/gdtvar.h

52

#define GDT_DPRINTF(mask, args)

sys/dev/ic/i82365.c

835

int i, mask, mhandle;

sys/dev/ic/i82365.c

845

mask = (1 << sizepg) - 1;

sys/dev/ic/i82365.c

851

if ((sc->subregionmask & (mask << i)) == (mask << i)) {

sys/dev/ic/i82365.c

856

mhandle = mask << i;

sys/dev/ic/i82596.c

382

i82596_start_cmd(struct ie_softc *sc, int cmd, int iecmdbuf, int mask,

sys/dev/ic/i82596.c

390

sc, cmd, iecmdbuf, mask, IE_STAT_BITS, async?"a":"");

sys/dev/ic/i82596.c

426

if (status & mask) {

sys/dev/ic/i82596var.h

289

ie_ack(struct ie_softc *sc, u_int mask) /* in native byte-order */

sys/dev/ic/i82596var.h

296

i82596_start_cmd(sc, status & mask, 0, 0, 0);

sys/dev/ic/if_wi.c

112

#define DPRINTF(mask,args) if (widebug & (mask)) printf args;

sys/dev/ic/if_wi.c

115

#define DPRINTF(mask,args)

sys/dev/ic/imxiic.c

132

imxiic_wait_state(struct imxiic_softc *sc, uint32_t mask, uint32_t value)

sys/dev/ic/imxiic.c

137

if (((state = HREAD1(sc, I2C_I2SR)) & mask) == value)

sys/dev/ic/iosf.c

149

uint32_t offset, uint32_t bits, uint32_t mask)

sys/dev/ic/iosf.c

159

CLR(mdr, mask);

sys/dev/ic/iosf.c

160

SET(mdr, bits & mask);

sys/dev/ic/iosf.c

205

uint32_t bits, uint32_t mask)

sys/dev/ic/iosf.c

215

iosf_mbi_mdr_modify(mbi, port, opcode, offset, bits, mask);

sys/dev/ic/lpt.c

113

bus_size_t off, u_int8_t data, u_int8_t mask)

sys/dev/ic/lpt.c

118

data &= mask;

sys/dev/ic/lpt.c

123

temp = bus_space_read_1(iot, ioh, off) & mask;

sys/dev/ic/mfi.c

2327

u_int32_t mask;

sys/dev/ic/mfi.c

2346

mask = MFI_BBU_STATE_BAD_IBBU;

sys/dev/ic/mfi.c

2350

mask = MFI_BBU_STATE_BAD_BBU;

sys/dev/ic/mfi.c

2371

sc->sc_bbu[0].value = ((status & mask) || soh_bad) ? 0 : 1;

sys/dev/ic/mfi.c

2372

sc->sc_bbu[0].status = ((status & mask) || soh_bad) ? SENSOR_S_CRIT :

sys/dev/ic/mpi.c

1717

mpi_wait_eq(struct mpi_softc *sc, bus_size_t r, u_int32_t mask,

sys/dev/ic/mpi.c

1723

mask, target);

sys/dev/ic/mpi.c

1726

if ((mpi_read(sc, r) & mask) == target)

sys/dev/ic/mpi.c

1735

mpi_wait_ne(struct mpi_softc *sc, bus_size_t r, u_int32_t mask,

sys/dev/ic/mpi.c

1741

mask, target);

sys/dev/ic/mpi.c

1744

if ((mpi_read(sc, r) & mask) != target)

sys/dev/ic/mtd8xx.c

216

u_int32_t miir, mask, data;

sys/dev/ic/mtd8xx.c

231

for (mask = 0; mask; mask >>= 1) {

sys/dev/ic/mtd8xx.c

233

if (mask & data)

sys/dev/ic/mtd8xx.c

240

if (mask == 0x4 && opcode == MII_OPCODE_RD)

sys/dev/ic/mtd8xx.c

256

u_int32_t miir, mask, data;

sys/dev/ic/mtd8xx.c

259

for (mask = 0x8000, data = 0; mask; mask >>= 1) {

sys/dev/ic/mtd8xx.c

264

data |= mask;

sys/dev/ic/mtd8xx.c

286

u_int32_t miir, mask;

sys/dev/ic/mtd8xx.c

289

for (mask = 0x8000; mask; mask >>= 1) {

sys/dev/ic/mtd8xx.c

291

if (mask & (u_int32_t)val)

sys/dev/ic/qwx.c

15533

qwx_dp_tx_htt_h2t_ppdu_stats_req(struct qwx_softc *sc, uint32_t mask,

sys/dev/ic/qwx.c

15557

mask);

sys/dev/ic/qwx.c

22921

qwx_get_num_chains(uint32_t mask)

sys/dev/ic/qwx.c

22925

while (mask) {

sys/dev/ic/qwx.c

22926

if (mask & 0x1)

sys/dev/ic/qwx.c

22928

mask >>= 1;

sys/dev/ic/qwx.c

9548

uint8_t mask = 1 << ring_num;

sys/dev/ic/qwx.c

9552

if (mask & grp_mask[ext_group_num])

sys/dev/ic/qwz.c

13235

qwz_dp_tx_htt_h2t_ppdu_stats_req(struct qwz_softc *sc, uint32_t mask,

sys/dev/ic/qwz.c

13259

mask);

sys/dev/ic/qwz.c

20160

qwz_get_num_chains(uint32_t mask)

sys/dev/ic/qwz.c

20164

while (mask) {

sys/dev/ic/qwz.c

20165

if (mask & 0x1)

sys/dev/ic/qwz.c

20167

mask >>= 1;

sys/dev/ic/qwz.c

6896

uint8_t mask = 1 << ring_num;

sys/dev/ic/qwz.c

6900

if (mask & grp_mask[ext_group_num])

sys/dev/ic/r92creg.h

1167

uint32_t mask;

sys/dev/ic/rtsx.c

1384

rtsx_wait_intr(struct rtsx_softc *sc, int mask, int secs)

sys/dev/ic/rtsx.c

1390

mask |= RTSX_TRANS_FAIL_INT;

sys/dev/ic/rtsx.c

1393

status = sc->intr_status & mask;

sys/dev/ic/rtsx.c

1401

status = sc->intr_status & mask;

sys/dev/ic/rtsx.c

747

rtsx_write(struct rtsx_softc *sc, u_int16_t addr, u_int8_t mask, u_int8_t val)

sys/dev/ic/rtsx.c

755

(mask << 8) | val));

sys/dev/ic/rtsx.c

854

u_int32_t mask, u_int32_t val)

sys/dev/ic/rtsx.c

860

if (mask & 0xff) {

sys/dev/ic/rtsx.c

861

RTSX_WRITE(sc, RTSX_CFGDATA0 + i, val & mask & 0xff);

sys/dev/ic/rtsx.c

864

mask >>= 8;

sys/dev/ic/rtsx.c

891

u_int8_t mask, u_int8_t data)

sys/dev/ic/rtsx.c

897

((u_int32_t)(mask) << 8) |

sys/dev/ic/rtw.c

2512

u_int8_t mask, newval, val;

sys/dev/ic/rtw.c

2528

newval = mask = RTW_PSR_LEDGPO0 | RTW_PSR_LEDGPO1;

sys/dev/ic/rtw.c

2536

mask = RTW_9346CR_EEM_MASK | RTW_9346CR_EEDI | RTW_9346CR_EECS;

sys/dev/ic/rtw.c

2548

val &= ~mask;

sys/dev/ic/rtw.c

4736

u_int32_t mask, reg;

sys/dev/ic/rtw.c

4749

mask = 0x1;

sys/dev/ic/rtw.c

4751

mask = 1 << (nbits - 1);

sys/dev/ic/rtw.c

4756

__func__, bits, mask, bits & mask));

sys/dev/ic/rtw.c

4758

if ((bits & mask) != 0)

sys/dev/ic/rtw.c

4774

mask <<= 1;

sys/dev/ic/rtw.c

4776

mask >>= 1;

sys/dev/ic/rtw.c

4793

u_int32_t mask;

sys/dev/ic/rtw.c

4814

mask = 0x1;

sys/dev/ic/rtw.c

4816

mask = 1 << (nbits - 1);

sys/dev/ic/rtw.c

4821

__func__, bits, mask, bits & mask));

sys/dev/ic/rtw.c

4823

if ((bits & mask) != 0)

sys/dev/ic/rtw.c

4839

mask <<= 1;

sys/dev/ic/rtw.c

4841

mask >>= 1;

sys/dev/ic/rtwn.c

869

cmd.mask = htole32(mode << 28 | basicrates);

sys/dev/ic/rtwn.c

883

cmd.mask = htole32(mode << 28 | rates);

sys/dev/ic/rtwreg.h

1135

#define RTW_ISSET(regs, reg, mask) \

sys/dev/ic/rtwreg.h

1136

(RTW_READ((regs), (reg)) & (mask))

sys/dev/ic/rtwreg.h

1138

#define RTW_CLR(regs, reg, mask) \

sys/dev/ic/rtwreg.h

1139

RTW_WRITE((regs), (reg), RTW_READ((regs), (reg)) & ~(mask))

sys/dev/ic/rtwreg.h

69

#define MASK_AND_RSHIFT(x, mask) (((x) & (mask)) >> MASK_TO_SHIFT(mask))

sys/dev/ic/rtwreg.h

70

#define LSHIFT(x, mask) ((x) << MASK_TO_SHIFT(mask))

sys/dev/ic/rtwreg.h

71

#define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask))

sys/dev/ic/sili.c

1000

while ((sili_pread(sp, r) & mask) != value) {

sys/dev/ic/sili.c

1012

sili_pwait_ne(struct sili_port *sp, bus_size_t r, u_int32_t mask,

sys/dev/ic/sili.c

1015

while ((sili_pread(sp, r) & mask) == value) {

sys/dev/ic/sili.c

997

sili_pwait_eq(struct sili_port *sp, bus_size_t r, u_int32_t mask,

sys/dev/ic/smc91cxx.c

700

u_int8_t mask, interrupts, status;

sys/dev/ic/smc91cxx.c

712

mask = bus_space_read_1(bst, bsh, INTR_MASK_REG_B);

sys/dev/ic/smc91cxx.c

719

status = interrupts & mask;

sys/dev/ic/smc91cxx.c

758

mask &= ~IM_ALLOC_INT;

sys/dev/ic/smc91cxx.c

840

mask &= ~IM_TX_EMPTY_INT;

sys/dev/ic/smc91cxx.c

874

mask |= bus_space_read_1(bst, bsh, INTR_MASK_REG_B);

sys/dev/ic/smc91cxx.c

875

bus_space_write_1(bst, bsh, INTR_MASK_REG_B, mask);

sys/dev/ic/tcic2.c

768

int i, mask, mhandle;

sys/dev/ic/tcic2.c

787

mask = (1 << sizepg) - 1;

sys/dev/ic/tcic2.c

794

if ((h->sc->subregionmask & (mask << i)) == (mask << i)) {

sys/dev/ic/tcic2.c

799

mhandle = mask << i;

sys/dev/ic/wdc.c

1088

wdc_wait_for_status(struct channel_softc *chp, int mask, int bits, int timeout)

sys/dev/ic/wdc.c

1111

if ((status & WDCS_BSY) == 0 && (status & mask) == bits)

sys/dev/ic/wdcvar.h

294

#define wdcwait(chp, status, mask, timeout) ((wdc_wait_for_status((chp), (status), (mask), (timeout)) >= 0) ? 0 : -1)

sys/dev/ipmi.c

1091

int mask;

sys/dev/ipmi.c

1096

mask = 1L << (bitpos & 7);

sys/dev/ipmi.c

1097

if (bytes[bitpos >> 3] & mask)

sys/dev/ipmi.c

277

if ((v & a->mask) == a->value)

sys/dev/ipmi.c

284

DEVNAME(sc), v, a->mask, a->value, a->lbl);

sys/dev/ipmi.c

331

a.mask = BT_BMC_BUSY;

sys/dev/ipmi.c

354

a.mask = BT_HOST2BMC_ATN | BT_BMC_BUSY;

sys/dev/ipmi.c

371

a.mask = BT_BMC2HOST_ATN;

sys/dev/ipmi.c

463

smic_wait(struct ipmi_softc *sc, u_int8_t mask, u_int8_t val, const char *lbl)

sys/dev/ipmi.c

470

a.mask = mask;

sys/dev/ipmi.c

622

kcs_wait(struct ipmi_softc *sc, u_int8_t mask, u_int8_t value, const char *lbl)

sys/dev/ipmi.c

628

a.mask = mask;

sys/dev/ipmivar.h

54

u_int8_t mask;

sys/dev/isa/ess.c

1585

return (ess_set_in_ports(sc, cp->un.mask));

sys/dev/isa/ess.c

1701

cp->un.mask = sc->in_mask;

sys/dev/isa/ess.c

1907

dip->un.s.member[0].mask = 1 << ESS_DAC_REC_VOL;

sys/dev/isa/ess.c

1911

dip->un.s.member[1].mask = 1 << ESS_MIC_REC_VOL;

sys/dev/isa/ess.c

1914

dip->un.s.member[2].mask = 1 << ESS_LINE_REC_VOL;

sys/dev/isa/ess.c

1917

dip->un.s.member[3].mask = 1 << ESS_SYNTH_REC_VOL;

sys/dev/isa/ess.c

1920

dip->un.s.member[4].mask = 1 << ESS_CD_REC_VOL;

sys/dev/isa/ess.c

1923

dip->un.s.member[5].mask = 1 << ESS_AUXB_REC_VOL;

sys/dev/isa/ess.c

2225

ess_set_in_ports(struct ess_softc *sc, int mask)

sys/dev/isa/ess.c

2230

DPRINTF(("ess_set_in_ports: mask=0x%x\n", mask));

sys/dev/isa/ess.c

2248

port = ffs(di.un.s.member[i].mask);

sys/dev/isa/ess.c

2255

ess_set_gain(sc, port, mask & di.un.s.member[i].mask);

sys/dev/isa/ess.c

2258

sc->in_mask = mask;

sys/dev/isa/ess.c

2423

ess_clear_xreg_bits(struct ess_softc *sc, u_char reg, u_char mask)

sys/dev/isa/ess.c

2425

if (ess_write_x_reg(sc, reg, ess_read_x_reg(sc, reg) & ~mask) == -1)

sys/dev/isa/ess.c

2431

ess_set_xreg_bits(struct ess_softc *sc, u_char reg, u_char mask)

sys/dev/isa/ess.c

2433

if (ess_write_x_reg(sc, reg, ess_read_x_reg(sc, reg) | mask) == -1)

sys/dev/isa/ess.c

2476

ess_clear_mreg_bits(struct ess_softc *sc, u_char reg, u_char mask)

sys/dev/isa/ess.c

2478

ess_write_mix_reg(sc, reg, ess_read_mix_reg(sc, reg) & ~mask);

sys/dev/isa/ess.c

2482

ess_set_mreg_bits(struct ess_softc *sc, u_char reg, u_char mask)

sys/dev/isa/ess.c

2484

ess_write_mix_reg(sc, reg, ess_read_mix_reg(sc, reg) | mask);

sys/dev/isa/if_ie.c

1653

command_and_wait(struct ie_softc *sc, int cmd, volatile void *pcmd, int mask)

sys/dev/isa/if_ie.c

1675

if ((cc->ie_cmd_status & mask))

sys/dev/isa/if_ie.c

344

ie_ack(struct ie_softc *sc, u_int mask)

sys/dev/isa/if_ie.c

348

scb->ie_command = scb->ie_status & mask;

sys/dev/isa/isagpio.c

133

u_int8_t mask;

sys/dev/isa/isagpio.c

135

mask = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 0);

sys/dev/isa/isagpio.c

136

return ((mask >> pin) & 0x01);

sys/dev/isa/lpt_isa.c

105

u_int8_t mask, data;

sys/dev/isa/lpt_isa.c

111

printf("lpt_isa_probe: mask %x data %x failed\n", mask, \

sys/dev/isa/lpt_isa.c

126

mask = 0xff;

sys/dev/isa/lpt_isa.c

129

if (!lpt_port_test(iot, ioh, base, lpt_data, data, mask))

sys/dev/isa/lpt_isa.c

133

if (!lpt_port_test(iot, ioh, base, lpt_data, data, mask))

sys/dev/isa/lpt_isa.c

138

if (!lpt_port_test(iot, ioh, base, lpt_data, data, mask))

sys/dev/isa/lpt_isa.c

144

if (!lpt_port_test(iot, ioh, base, lpt_data, data, mask))

sys/dev/isa/sbdsp.c

1378

sbdsp_adjust(int val, int mask)

sys/dev/isa/sbdsp.c

1380

val += (MAXVAL - mask) >> 1;

sys/dev/isa/sbdsp.c

1383

return val & mask;

sys/dev/isa/sbdsp.c

1493

int mask, bits;

sys/dev/isa/sbdsp.c

1590

return sbdsp_set_in_ports(sc, cp->un.mask);

sys/dev/isa/sbdsp.c

1606

mask = SB16P_SW_CD;

sys/dev/isa/sbdsp.c

1609

mask = SB16P_SW_MIC;

sys/dev/isa/sbdsp.c

1612

mask = SB16P_SW_LINE;

sys/dev/isa/sbdsp.c

1619

bits = bits & ~mask;

sys/dev/isa/sbdsp.c

1621

bits = bits | mask;

sys/dev/isa/sbdsp.c

1646

mask = lmask | rmask;

sys/dev/isa/sbdsp.c

1647

lbits = sbdsp_mix_read(sc, SB16P_ISWITCH_L) & ~mask;

sys/dev/isa/sbdsp.c

1648

rbits = sbdsp_mix_read(sc, SB16P_ISWITCH_R) & ~mask;

sys/dev/isa/sbdsp.c

1658

mask = lmask;

sys/dev/isa/sbdsp.c

1660

rmask = mask;

sys/dev/isa/sbdsp.c

1744

cp->un.mask = sc->in_mask;

sys/dev/isa/sbdsp.c

1874

dip->un.s.member[0].mask = 1 << SB_MIC_VOL;

sys/dev/isa/sbdsp.c

1877

dip->un.s.member[1].mask = 1 << SB_CD_VOL;

sys/dev/isa/sbdsp.c

1880

dip->un.s.member[2].mask = 1 << SB_LINE_IN_VOL;

sys/dev/isa/sbdsp.c

1884

dip->un.s.member[3].mask = 1 << SB_MIDI_VOL;

sys/dev/isa/sbdsp.c

673

sbdsp_set_in_ports(struct sbdsp_softc *sc, int mask)

sys/dev/isa/sbdsp.c

682

sc->sc_mixer_model, mask));

sys/dev/isa/sbdsp.c

688

if (mask != (1 << SB_MIC_VOL))

sys/dev/isa/sbdsp.c

692

switch (mask) {

sys/dev/isa/sbdsp.c

709

if (mask & ~((1<<SB_MIDI_VOL) | (1<<SB_LINE_IN_VOL) |

sys/dev/isa/sbdsp.c

713

if (mask & (1<<SB_MIDI_VOL)) bitsr |= SBP_MIDI_SRC_R;

sys/dev/isa/sbdsp.c

714

if (mask & (1<<SB_LINE_IN_VOL)) bitsr |= SBP_LINE_SRC_R;

sys/dev/isa/sbdsp.c

715

if (mask & (1<<SB_CD_VOL)) bitsr |= SBP_CD_SRC_R;

sys/dev/isa/sbdsp.c

717

if (mask & (1<<SB_MIC_VOL)) {

sys/dev/isa/sbdsp.c

725

sc->in_mask = mask;

sys/dev/isa/wds.c

187

wds_wait(bus_space_tag_t iot, bus_space_handle_t ioh, int port, int mask,

sys/dev/isa/wds.c

190

while ((bus_space_read_1(iot, ioh, port) & mask) != val)

sys/dev/microcode/aic7xxx/aic79xx_reg.h

13

uint8_t mask;

sys/dev/microcode/aic7xxx/aic7xxx_reg.h

13

uint8_t mask;

sys/dev/microcode/aic7xxx/aicasm_gram.y

1402

sym->info.finfo->mask = value;

sys/dev/microcode/aic7xxx/aicasm_gram.y

1404

sym->info.finfo->mask = field_symbol->info.finfo->value;

sys/dev/microcode/aic7xxx/aicasm_gram.y

1406

sym->info.finfo->mask = 0xFF;

sys/dev/microcode/aic7xxx/aicasm_gram.y

1424

cur_symbol->info.rinfo->valid_bitmask |= sym->info.finfo->mask;

sys/dev/microcode/aic7xxx/aicasm_gram.y

92

static void process_field(int field_type, symbol_t *sym, int mask);

sys/dev/microcode/aic7xxx/aicasm_symbol.c

454

curnode->symbol->info.finfo->mask);

sys/dev/microcode/aic7xxx/aicasm_symbol.h

90

uint8_t mask;

sys/dev/ofw/ofw_misc.c

1124

uint32_t mask, rid_base;

sys/dev/ofw/ofw_misc.c

1135

mask = OF_getpropint(node, "iommu-map-mask", 0xffff);

sys/dev/ofw/ofw_misc.c

1136

rid = rid & mask;

sys/dev/ofw/ofw_misc.c

663

uint8_t mask, tmp;

sys/dev/ofw/ofw_misc.c

671

mask = 0xff;

sys/dev/ofw/ofw_misc.c

673

mask = (1 << bitlen) - 1;

sys/dev/ofw/ofw_misc.c

676

*p++ |= (tmp << (8 - offset)) & (mask << (8 - offset));

sys/dev/ofw/ofw_misc.c

678

mask >>= offset;

sys/dev/ofw/ofw_misc.c

683

*p = (tmp >> offset) & mask;

sys/dev/ofw/ofw_misc.c

738

uint8_t mask, tmp;

sys/dev/ofw/ofw_misc.c

746

mask = 0xff;

sys/dev/ofw/ofw_misc.c

748

mask = (1 << bitlen) - 1;

sys/dev/ofw/ofw_misc.c

750

tmp &= ~(mask << offset);

sys/dev/ofw/ofw_misc.c

751

tmp |= (*p++ << offset) & (mask << offset);

sys/dev/ofw/ofw_misc.c

756

tmp &= ~(mask >> (8 - offset));

sys/dev/ofw/ofw_misc.c

757

tmp |= (*p >> (8 - offset)) & (mask >> (8 - offset));

sys/dev/onewire/onewire.c

298

u_int64_t mask, rom = startrom, lastrom;

sys/dev/onewire/onewire.c

330

mask = dir;

sys/dev/onewire/onewire.c

333

mask = 0;

sys/dev/onewire/onewire.c

336

mask = 1;

sys/dev/onewire/onewire.c

345

rom |= (mask << i);

sys/dev/pci/amas.c

203

int mask;

sys/dev/pci/amas.c

215

mask = AMAS_INTL_ENABLE(base_reg, limit_reg);

sys/dev/pci/amas.c

217

return mask == 0 ? 0 : mask + 1;

sys/dev/pci/arc.c

2001

u_int32_t mask;

sys/dev/pci/arc.c

2019

mask = htole32(sc->sc_ledmask);

sys/dev/pci/arc.c

2020

bcopy(&mask, &request[2], 4);

sys/dev/pci/arc.c

2744

arc_wait_eq(struct arc_softc *sc, bus_size_t r, u_int32_t mask,

sys/dev/pci/arc.c

2750

DEVNAME(sc), r, mask, target);

sys/dev/pci/arc.c

2753

if ((arc_read(sc, r) & mask) == target)

sys/dev/pci/arc.c

2762

arc_wait_ne(struct arc_softc *sc, bus_size_t r, u_int32_t mask,

sys/dev/pci/arc.c

2768

DEVNAME(sc), r, mask, target);

sys/dev/pci/arc.c

2771

if ((arc_read(sc, r) & mask) != target)

sys/dev/pci/auacer.c

272

auacer_ready_codec(struct auacer_softc *sc, int mask)

sys/dev/pci/auacer.c

278

if (val & mask)

sys/dev/pci/autri.c

176

autri_reg_set_1(struct autri_softc *sc, int no, uint8_t mask)

sys/dev/pci/autri.c

179

(bus_space_read_1(sc->memt, sc->memh, no) | mask));

sys/dev/pci/autri.c

183

autri_reg_clear_1(struct autri_softc *sc, int no, uint8_t mask)

sys/dev/pci/autri.c

186

(bus_space_read_1(sc->memt, sc->memh, no) & ~mask));

sys/dev/pci/autri.c

190

autri_reg_set_4(struct autri_softc *sc, int no, uint32_t mask)

sys/dev/pci/autri.c

193

(bus_space_read_4(sc->memt, sc->memh, no) | mask));

sys/dev/pci/autri.c

197

autri_reg_clear_4(struct autri_softc *sc, int no, uint32_t mask)

sys/dev/pci/autri.c

200

(bus_space_read_4(sc->memt, sc->memh, no) & ~mask));

sys/dev/pci/autri.c

735

u_int32_t mask, active[2];

sys/dev/pci/autri.c

761

mask = 1 << (ch & 0x1f);

sys/dev/pci/autri.c

762

if (active[(ch & 0x20) ? 1 : 0] & mask) {

sys/dev/pci/autri.c

765

TWRITE4(sc, (ch & 0x20) ? AUTRI_AIN_B : AUTRI_AIN_A, mask);

sys/dev/pci/autri.c

767

autri_reg_clear_4(sc,(ch & 0x20) ? AUTRI_AINTEN_B : AUTRI_AINTEN_A, mask);

sys/dev/pci/autri.c

792

autri_reg_set_4(sc, (ch & 0x20) ? AUTRI_AINTEN_B : AUTRI_AINTEN_A, mask);

sys/dev/pci/azalia.c

2437

this->playvols.mask = 0;

sys/dev/pci/azalia.c

2449

this->playvols.mask |= (1 << j);

sys/dev/pci/azalia.c

2530

this->recvols.mask = 0;

sys/dev/pci/azalia.c

2554

this->recvols.mask |= (1 << j);

sys/dev/pci/azalia.h

612

int mask;

sys/dev/pci/azalia.h

640

int mask;

sys/dev/pci/azalia_codec.c

1022

d->un.s.member[k].mask = 1 << j;

sys/dev/pci/azalia_codec.c

1103

d->un.s.member[k].mask = 1 << j;

sys/dev/pci/azalia_codec.c

1263

d->un.s.member[j].mask = 1 << i;

sys/dev/pci/azalia_codec.c

1318

d->un.s.member[j].mask = (1 << i);

sys/dev/pci/azalia_codec.c

1371

d->un.s.member[j].mask = (1 << i);

sys/dev/pci/azalia_codec.c

1544

mc.un.mask |= 1 << j;

sys/dev/pci/azalia_codec.c

1838

mc->un.mask = result & 0xff & ~(CORB_DCC_DIGEN | CORB_DCC_NAUDIO);

sys/dev/pci/azalia_codec.c

1875

mc->un.mask = 0;

sys/dev/pci/azalia_codec.c

1885

mc->un.mask |= (result & CORB_GAGM_MUTE) ? 0 : (1 << i);

sys/dev/pci/azalia_codec.c

1898

mc->un.mask = 0;

sys/dev/pci/azalia_codec.c

1902

mc->un.mask |= (1 << i);

sys/dev/pci/azalia_codec.c

1909

mc->un.mask = this->spkr_muters;

sys/dev/pci/azalia_codec.c

1927

mc->un.mask = this->playvols.cur;

sys/dev/pci/azalia_codec.c

1947

mc->un.mask = this->recvols.cur;

sys/dev/pci/azalia_codec.c

2226

result |= mc->un.mask & 0xff & ~CORB_DCC_DIGEN;

sys/dev/pci/azalia_codec.c

2290

if ((mc->un.mask & (1 << i)) == 0)

sys/dev/pci/azalia_codec.c

2307

if ((mc->un.mask & (1 << i)) == 0)

sys/dev/pci/azalia_codec.c

2325

this->spkr_muters = mc->un.mask;

sys/dev/pci/azalia_codec.c

2403

(mc->un.mask & this->playvols.mask);

sys/dev/pci/azalia_codec.c

2478

this->recvols.cur = (mc->un.mask & this->recvols.mask);

sys/dev/pci/azalia_codec.c

2551

uint32_t data, mask, dir;

sys/dev/pci/azalia_codec.c

2554

azalia_comresp(this, this->audiofunc, CORB_GET_GPIO_ENABLE_MASK, 0, &mask);

sys/dev/pci/azalia_codec.c

2558

mask |= 1 << pin;

sys/dev/pci/azalia_codec.c

2561

azalia_comresp(this, this->audiofunc, CORB_SET_GPIO_ENABLE_MASK, mask, NULL);

sys/dev/pci/azalia_codec.c

2587

azalia_pin_config_ov(widget_t *w, int mask, int val)

sys/dev/pci/azalia_codec.c

2591

switch (mask) {

sys/dev/pci/azalia_codec.c

2604

w->d.pin.config &= ~(mask);

sys/dev/pci/azalia_codec.c

2606

if (mask == CORB_CD_DEVICE_MASK)

sys/dev/pci/cmpci.c

1221

cmpci_adjust(int val, int mask)

sys/dev/pci/cmpci.c

1223

val += (MAXVAL - mask) >> 1;

sys/dev/pci/cmpci.c

1226

return val & mask;

sys/dev/pci/cmpci.c

1233

int bits, mask;

sys/dev/pci/cmpci.c

1303

mask = CMPCI_SB16_SW_CD;

sys/dev/pci/cmpci.c

1306

mask = CMPCI_SB16_SW_MIC;

sys/dev/pci/cmpci.c

1309

mask = CMPCI_SB16_SW_LINE;

sys/dev/pci/cmpci.c

1313

bits = bits & ~mask;

sys/dev/pci/cmpci.c

1315

bits = bits | mask;

sys/dev/pci/cmpci.c

1514

int mask;

sys/dev/pci/cmpci.c

1517

mask = sc->sc_in_mask;

sys/dev/pci/cmpci.c

1524

bitsr = mask & (CMPCI_RECORD_SOURCE_CD | CMPCI_RECORD_SOURCE_LINE_IN |

sys/dev/pci/cmpci.c

1528

if (mask & CMPCI_RECORD_SOURCE_MIC) {

sys/dev/pci/cmpci.c

1535

if (mask & CMPCI_RECORD_SOURCE_AUX_IN)

sys/dev/pci/cmpci.c

1542

if (mask & CMPCI_RECORD_SOURCE_WAVE)

sys/dev/pci/cmpci.c

1553

if (mask & CMPCI_RECORD_SOURCE_SPDIF) {

sys/dev/pci/cmpci.c

1611

if (cp->un.mask & ~(CMPCI_RECORD_SOURCE_MIC |

sys/dev/pci/cmpci.c

1617

if (cp->un.mask & CMPCI_RECORD_SOURCE_SPDIF)

sys/dev/pci/cmpci.c

1618

cp->un.mask = CMPCI_RECORD_SOURCE_SPDIF;

sys/dev/pci/cmpci.c

1620

sc->sc_in_mask = cp->un.mask;

sys/dev/pci/cmpci.c

1714

cp->un.mask = sc->sc_in_mask;

sys/dev/pci/cmpci.c

195

unsigned mask, unsigned val)

sys/dev/pci/cmpci.c

199

(bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) & ~(mask<<shift)));

sys/dev/pci/cmpci.c

205

uint32_t mask, uint32_t val)

sys/dev/pci/cmpci.c

209

(bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) & ~(mask<<shift)));

sys/dev/pci/cmpci.c

215

cmpci_reg_set_1(struct cmpci_softc *sc, int no, uint8_t mask)

sys/dev/pci/cmpci.c

218

(bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) | mask));

sys/dev/pci/cmpci.c

223

cmpci_reg_clear_1(struct cmpci_softc *sc, int no, uint8_t mask)

sys/dev/pci/cmpci.c

226

(bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) & ~mask));

sys/dev/pci/cmpci.c

231

cmpci_reg_set_4(struct cmpci_softc *sc, int no, uint32_t mask)

sys/dev/pci/cmpci.c

237

(bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) | mask));

sys/dev/pci/cmpci.c

242

cmpci_reg_clear_4(struct cmpci_softc *sc, int no, uint32_t mask)

sys/dev/pci/cmpci.c

248

(bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) & ~mask));

sys/dev/pci/cmpci.c

257

cmpci_reg_set_reg_misc(struct cmpci_softc *sc, uint32_t mask)

sys/dev/pci/cmpci.c

259

sc->sc_reg_misc |= mask;

sys/dev/pci/cmpci.c

266

cmpci_reg_clear_reg_misc(struct cmpci_softc *sc, uint32_t mask)

sys/dev/pci/cmpci.c

268

sc->sc_reg_misc &= ~mask;

sys/dev/pci/cmpci.c

945

dip->un.s.member[0].mask = CMPCI_RECORD_SOURCE_MIC;

sys/dev/pci/cmpci.c

948

dip->un.s.member[1].mask = CMPCI_RECORD_SOURCE_CD;

sys/dev/pci/cmpci.c

951

dip->un.s.member[2].mask = CMPCI_RECORD_SOURCE_LINE_IN;

sys/dev/pci/cmpci.c

954

dip->un.s.member[3].mask = CMPCI_RECORD_SOURCE_AUX_IN;

sys/dev/pci/cmpci.c

957

dip->un.s.member[4].mask = CMPCI_RECORD_SOURCE_WAVE;

sys/dev/pci/cmpci.c

960

dip->un.s.member[5].mask = CMPCI_RECORD_SOURCE_FM;

sys/dev/pci/cmpci.c

963

dip->un.s.member[6].mask = CMPCI_RECORD_SOURCE_SPDIF;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1410

uint32_t expected_value, uint32_t mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1505

#define WREG32_P(reg, val, mask) \

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1508

tmp_ &= (mask); \

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1509

tmp_ |= ((val) & ~(mask)); \

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1514

#define WREG32_PLL_P(reg, val, mask) \

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1517

tmp_ &= (mask); \

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1518

tmp_ |= ((val) & ~(mask)); \

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

826

uint32_t mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c

593

if (!handle->mask || !list_empty(&handle->node))

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c

609

if ((type < 0) || (!(BIT(type) & handle->mask)))

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c

666

handle->mask = ras_info->mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.h

181

u32 mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.h

210

u32 mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

205

static void amdgpu_atif_parse_notification(struct amdgpu_atif_notifications *n, u32 mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

207

n->thermal_state = mask & ATIF_THERMAL_STATE_CHANGE_REQUEST_SUPPORTED;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

208

n->forced_power_state = mask & ATIF_FORCED_POWER_STATE_CHANGE_REQUEST_SUPPORTED;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

209

n->system_power_state = mask & ATIF_SYSTEM_POWER_SOURCE_CHANGE_REQUEST_SUPPORTED;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

210

n->brightness_change = mask & ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST_SUPPORTED;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

211

n->dgpu_display_event = mask & ATIF_DGPU_DISPLAY_EVENT_SUPPORTED;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

212

n->gpu_package_power_limit = mask & ATIF_GPU_PACKAGE_POWER_LIMIT_REQUEST_SUPPORTED;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

225

static void amdgpu_atif_parse_functions(struct amdgpu_atif_functions *f, u32 mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

227

f->system_params = mask & ATIF_GET_SYSTEM_PARAMETERS_SUPPORTED;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

228

f->sbios_requests = mask & ATIF_GET_SYSTEM_BIOS_REQUESTS_SUPPORTED;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

229

f->temperature_change = mask & ATIF_TEMPERATURE_CHANGE_NOTIFICATION_SUPPORTED;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

231

mask & ATIF_QUERY_BACKLIGHT_TRANSFER_CHARACTERISTICS_SUPPORTED;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

232

f->ready_to_undock = mask & ATIF_READY_TO_UNDOCK_NOTIFICATION_SUPPORTED;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

233

f->external_gpu_information = mask & ATIF_GET_EXTERNAL_GPU_INFORMATION_SUPPORTED;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

587

static void amdgpu_atcs_parse_functions(struct amdgpu_atcs_functions *f, u32 mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

589

f->get_ext_state = mask & ATCS_GET_EXTERNAL_STATE_SUPPORTED;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

590

f->pcie_perf_req = mask & ATCS_PCIE_PERFORMANCE_REQUEST_SUPPORTED;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

591

f->pcie_dev_rdy = mask & ATCS_PCIE_DEVICE_READY_NOTIFICATION_SUPPORTED;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

592

f->pcie_bus_width = mask & ATCS_SET_PCIE_BUS_WIDTH_SUPPORTED;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

593

f->power_shift_control = mask & ATCS_SET_POWER_SHIFT_CONTROL_SUPPORTED;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

400

static uint32_t trap_mask_map_sw_to_hw(uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

402

uint32_t trap_on_start = (mask & KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START) ? 1 : 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

403

uint32_t trap_on_end = (mask & KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END) ? 1 : 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

404

uint32_t excp_en = mask & (KFD_DBG_TRAP_MASK_FP_INVALID |

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

422

static uint32_t trap_mask_map_hw_to_sw(uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

424

uint32_t ret = REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, EXCP_EN);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

426

if (REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_START))

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

429

if (REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_END))

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

672

static uint32_t trap_mask_map_sw_to_hw(uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

674

uint32_t trap_on_start = (mask & KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START) ? 1 : 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

675

uint32_t trap_on_end = (mask & KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END) ? 1 : 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

676

uint32_t excp_en = mask & (KFD_DBG_TRAP_MASK_FP_INVALID |

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

694

static uint32_t trap_mask_map_hw_to_sw(uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

696

uint32_t ret = REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, EXCP_EN);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

698

if (REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_START))

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

701

if (REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_END))

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

239

static uint32_t trap_mask_map_sw_to_hw(uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

241

uint32_t trap_on_start = (mask & KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START) ? 1 : 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

242

uint32_t trap_on_end = (mask & KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END) ? 1 : 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

243

uint32_t excp_en = mask & (KFD_DBG_TRAP_MASK_FP_INVALID |

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

261

static uint32_t trap_mask_map_hw_to_sw(uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

263

uint32_t ret = REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, EXCP_EN);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

265

if (REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_START))

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

268

if (REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_END))

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

206

gpio.mask = (1 << pin->ucGpioPinBitShift);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

231

switch(gpio->mask) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

217

pcireg_t address, mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

226

mask = pci_conf_read(adev->pc, adev->pa_tag, PCI_ROM_REG);

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

230

size = PCI_ROM_SIZE(mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7797

uint32_t expected_value, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7804

while ((tmp_ & (mask)) != (expected_value)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7817

(uint32_t)(tmp_ & (mask)));

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

3366

pcireg_t addr, mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

3455

mask = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG);

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

3459

if (addr == 0 && PCI_ROM_SIZE(mask) != 0 && pa->pa_memex) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

3463

size = PCI_ROM_SIZE(mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

109

void amdgpu_gfx_parse_disable_cu(unsigned int *mask, unsigned int max_se, unsigned int max_sh)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

114

memset(mask, 0, sizeof(*mask) * max_se * max_sh);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

132

mask[se * max_sh + sh] |= 1u << cu;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2369

u64 mask = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2375

mask = (1ULL << adev->gfx.num_gfx_rings) - 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2376

if ((val & mask) == 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2395

u64 mask = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2403

mask |= 1ULL << i;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2406

*val = mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2439

u64 mask = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2445

mask = (1ULL << adev->gfx.num_compute_rings) - 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2446

if ((val & mask) == 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2466

u64 mask = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2474

mask |= 1ULL << i;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2477

*val = mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

568

void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

810

uint32_t ref, uint32_t mask,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

821

ref, mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

828

ref, mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

435

uint32_t ref, uint32_t mask,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ip.c

52

uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ip.c

57

while (mask) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ip.c

58

log_inst = ffs(mask) - 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ip.c

61

mask &= ~(1 << log_inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

362

u64 mask = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

368

mask = (1ULL << (adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings)) - 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

369

if ((val & mask) == 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

390

u64 mask = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

399

mask |= 1ULL << ((i * adev->jpeg.num_jpeg_rings) + j);

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

402

*val = mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_lsdma.c

31

uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_lsdma.c

38

if ((val & mask) == reg_val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_lsdma.h

44

uint32_t reg_val, uint32_t mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

504

uint32_t ref, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

513

op_input.wrm_reg.mask = mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

328

uint32_t mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

432

uint32_t ref, uint32_t mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

568

u32 mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

579

uint32_t mask, uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

596

if ((val & mask) == reg_val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

605

reg_index, mask, val, reg_val);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

611

uint32_t reg_val, uint32_t mask, uint32_t msec_timeout)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

622

if ((val & mask) == reg_val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

539

uint32_t field_val, uint32_t mask, uint32_t flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

541

uint32_t field_val, uint32_t mask, uint32_t msec_timeout);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

436

uint32_t mask, inst_mask = data->inject.instance_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

450

mask = GENMASK(num_xcc - 1, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

453

mask = GENMASK(adev->sdma.num_instances - 1, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

457

mask = GENMASK(adev->vcn.num_vcn_inst - 1, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

460

mask = inst_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

465

data->inject.instance_mask &= mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

441

uint32_t ref, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

444

amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

277

uint32_t val, uint32_t mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

280

uint32_t ref, uint32_t mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

355

u64 mask = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

372

mask = BIT_ULL(adev->sdma.num_instances * num_ring) - 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

374

if ((val & mask) == 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

402

u64 mask = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

422

mask |= BIT_ULL(i * num_ring);

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

424

mask &= ~BIT_ULL(i * num_ring);

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

428

mask |= BIT_ULL(i * num_ring + 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

430

mask &= ~BIT_ULL(i * num_ring + 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

434

*val = mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1504

uint32_t mask = 0xffffffff << shift;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1508

mask &= 0xffffffff >> (bytes - size) * 8;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1512

if (mask != 0xffffffff) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1515

value &= ~mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1516

value |= (*(uint32_t *)buf << shift) & mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1519

value = (value & mask) >> shift;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1402

u64 mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1408

mask = (1ULL << adev->vcn.num_vcn_inst) - 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1409

if ((val & mask) == 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1427

u64 mask = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1435

mask |= 1ULL << i;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1437

*val = mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

80

#define RREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, mask, sram_sel) \

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

81

({ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

90

#define WREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, value, mask, sram_sel) \

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

93

WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c

180

unsigned int mask, shift, idx;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c

186

mask = amdgpu_vm_pt_entries_mask(adev, cursor->level);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c

190

idx = (cursor->pfn >> shift) & mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c

814

unsigned int shift, parent_shift, mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c

878

mask = amdgpu_vm_pt_entries_mask(adev, cursor.level);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c

879

pe_start = ((cursor.pfn >> shift) & mask) * 8;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c

888

entry_end = ((uint64_t)mask + 1) << shift;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

597

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

608

amdgpu_ring_write(ring, mask); /* mask */

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1244

.mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK,

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

538

u32 mask, avail_inst, inst_mask = adev->sdma.sdma_mask;

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

548

for (mask = (1 << adev->sdma.num_inst_per_aid) - 1; inst_mask;

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

550

avail_inst = inst_mask & mask;

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

551

if (avail_inst == mask || avail_inst == 0x3 ||

sys/dev/pci/drm/amd/amdgpu/atom.c

786

uint32_t dst, mask, src, saved;

sys/dev/pci/drm/amd/amdgpu/atom.c

790

mask = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr);

sys/dev/pci/drm/amd/amdgpu/atom.c

791

SDEBUG(" mask: 0x%08x", mask);

sys/dev/pci/drm/amd/amdgpu/atom.c

794

dst &= mask;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3305

uint32_t disp_int, mask;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3315

mask = interrupt_status_offsets[hpd].hpd;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3317

if (disp_int & mask) {

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3197

uint32_t disp_int, mask;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3207

mask = interrupt_status_offsets[hpd].hpd;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3209

if (disp_int & mask) {

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3213

uint32_t disp_int, mask;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3223

mask = interrupt_status_offsets[hpd].hpd;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3225

if (disp_int & mask) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10120

u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10142

mask = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10153

if (bitmap & mask) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10155

ao_bitmap |= mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10158

mask <<= 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4013

uint32_t addr1, uint32_t ref, uint32_t mask,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4029

amdgpu_ring_write(ring, mask);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5085

u32 data, mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5093

mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5096

return (~data) & mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9028

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9030

gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9035

uint32_t ref, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9045

ref, mask, 0x20);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9048

ref, mask);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

523

uint32_t addr1, uint32_t ref, uint32_t mask,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

539

amdgpu_ring_write(ring, mask);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6293

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6295

gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6300

uint32_t ref, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6305

ref, mask, 0x20);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7476

u32 mask, bitmap;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7490

mask = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7516

if (bitmap & mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7519

mask <<= 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

431

uint32_t mask, uint32_t inv)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

446

amdgpu_ring_write(ring, mask);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4678

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4680

gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4685

uint32_t ref, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4690

ref, mask, 0x20);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5720

u32 mask, bitmap;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5734

mask = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5760

if (bitmap & mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5763

mask <<= 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1331

u32 data, mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1338

mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1341

return ~data & mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1536

u32 data, mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1541

mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1542

return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1549

u32 data, mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1559

mask = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1561

mask <<= k;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1562

if (active_cu & mask) {

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1563

data &= ~mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2240

u32 mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2255

mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2257

if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3546

u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3563

mask = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3574

if (bitmap & mask) {

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3576

ao_bitmap |= mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3579

mask <<= 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1594

u32 data, mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1602

mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1605

return (~data) & mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3268

u32 mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3284

mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3289

if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3335

u32 tmp, i, mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3340

mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3343

if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3741

u32 data, mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3749

mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3751

return (~data) & mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

5024

u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

5041

mask = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

5052

if (bitmap & mask) {

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

5054

ao_bitmap |= mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

5057

mask <<= 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3419

u32 data, mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3426

mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3429

return (~data) & mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3808

u32 mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3832

mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3837

if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7035

u32 data, mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7040

mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7042

return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7048

u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7065

mask = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7076

if (bitmap & mask) {

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7078

ao_bitmap |= mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

7081

mask <<= 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1174

uint32_t addr1, uint32_t ref, uint32_t mask,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1190

amdgpu_ring_write(ring, mask);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1671

uint32_t mask, cu_bitmap, counter;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1683

mask = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1689

if (cu_info->bitmap[0][i][j] & mask) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1693

cu_bitmap |= mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1698

mask <<= 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2523

u32 data, mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2531

mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2534

return (~data) & mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2715

u32 mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2739

mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2744

if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5898

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5900

gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5905

uint32_t ref, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5914

ref, mask, 0x20);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5917

ref, mask);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7744

u32 data, mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7752

mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7754

return (~data) & mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7761

u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7781

mask = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7804

if (bitmap & mask) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7806

ao_bitmap |= mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7809

mask <<= 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

453

uint32_t *wb_ptr, uint32_t mask,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

469

if (((1 << wave) & mask) &&

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1467

u32 mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1494

mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1499

if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3037

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3039

gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3044

uint32_t ref, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3047

ref, mask);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

390

uint32_t addr1, uint32_t ref, uint32_t mask,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

412

amdgpu_ring_write(ring, mask);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4891

u32 data, mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4899

mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4901

return (~data) & mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4908

u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0, tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4931

mask = 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4944

if (bitmap & mask) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4946

ao_bitmap |= mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4949

mask <<= 1;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

916

.mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

438

u32 mask = 0x0;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

446

mask |= 1 << vmid;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

449

WREG32(mmVM_INVALIDATE_REQUEST, mask);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

629

u32 mask = 0x0;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

637

mask |= 1 << vmid;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

640

WREG32(mmVM_INVALIDATE_REQUEST, mask);

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

112

ring->ring[ptr++] = mask;

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

355

uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

380

amdgpu_ring_write(ring, mask);

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

387

uint32_t data0, data1, mask;

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

394

mask = 0xffffffff;

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

395

jpeg_v1_0_decode_ring_emit_reg_wait(ring, data0, data1, mask);

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

61

uint32_t reg, reg_offset, val, mask, i;

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

97

mask = 0x1;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

614

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

637

amdgpu_ring_write(ring, mask);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

644

uint32_t data0, data1, mask;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

651

mask = 0xffffffff;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

652

jpeg_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.h

55

uint32_t val, uint32_t mask);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1444

.mask = ACA_ERROR_UE_MASK,

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

887

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

916

amdgpu_ring_write(ring, mask);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

923

uint32_t data0, data1, mask;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

930

mask = 0xffffffff;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

931

jpeg_v4_0_3_dec_ring_emit_reg_wait(ring, data0, data1, mask);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.h

72

uint32_t val, uint32_t mask);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

1059

.mask = ACA_ERROR_UE_MASK,

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

404

u32 reg, data, mask;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

412

mask = ~(JPEG_SYS_INT_EN__DJRBC0_MASK << ring->pipe);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

413

WREG32_P(reg, data, mask);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

416

mask = ~(JPEG_SYS_INT_EN__DJRBC0_MASK << (ring->pipe+12));

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

417

WREG32_P(reg, data, mask);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

620

misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

628

misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

663

misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

671

misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

841

.mask = ACA_ERROR_UE_MASK,

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

110

uint32_t mask, uint32_t data)

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

113

direct_rd_mod_wt->mask_value = mask;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

122

uint32_t mask, uint32_t wait)

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

125

direct_poll->mask_value = mask;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

130

#define MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

133

(mask), (data)); \

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

146

#define MMSCH_V1_0_INSERT_DIRECT_POLL(reg, mask, wait) { \

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

149

(mask), (wait)); \

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

294

uint32_t mask, uint32_t data)

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

297

direct_rd_mod_wt->mask_value = mask;

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

306

uint32_t mask, uint32_t wait)

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

309

direct_poll->mask_value = mask;

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

314

#define MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

317

(mask), (data)); \

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

330

#define MMSCH_V2_0_INSERT_DIRECT_POLL(reg, mask, wait) { \

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

333

(mask), (wait)); \

sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h

113

#define MMSCH_V3_0_INSERT_DIRECT_POLL(reg, mask, wait) { \

sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h

117

direct_poll.mask_value = mask; \

sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h

92

#define MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \

sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h

96

direct_rd_mod_wt.mask_value = mask; \

sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h

104

#define MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \

sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h

108

direct_rd_mod_wt.mask_value = mask; \

sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h

125

#define MMSCH_V4_0_INSERT_DIRECT_POLL(reg, mask, wait) { \

sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h

129

direct_poll.mask_value = mask; \

sys/dev/pci/drm/amd/amdgpu/mmsch_v5_0.h

103

#define MMSCH_V5_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \

sys/dev/pci/drm/amd/amdgpu/mmsch_v5_0.h

107

direct_rd_mod_wt.mask_value = mask; \

sys/dev/pci/drm/amd/amdgpu/mmsch_v5_0.h

124

#define MMSCH_V5_0_INSERT_DIRECT_POLL(reg, mask, wait) { \

sys/dev/pci/drm/amd/amdgpu/mmsch_v5_0.h

128

direct_poll.mask_value = mask; \

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

323

u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

331

while (reg & mask) {

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

370

u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

375

if (!(reg & mask))

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

392

u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, TRN_MSG_ACK);

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

396

while (!(reg & mask)) {

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1732

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1734

sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

831

uint32_t ref, uint32_t mask,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

848

amdgpu_ring_write(ring, mask); /* mask */

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1328

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1330

sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2587

.mask = ACA_ERROR_UE_MASK,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

398

uint32_t ref, uint32_t mask,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

415

amdgpu_ring_write(ring, mask); /* mask */

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1307

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1315

amdgpu_ring_write(ring, mask); /* mask */

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1322

uint32_t ref, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1327

amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1228

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1236

amdgpu_ring_write(ring, mask); /* mask */

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1243

uint32_t ref, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1248

amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1231

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1239

amdgpu_ring_write(ring, mask); /* mask */

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1246

uint32_t ref, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1251

amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1233

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1241

amdgpu_ring_write(ring, mask); /* mask */

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1248

uint32_t ref, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1253

amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);

sys/dev/pci/drm/amd/amdgpu/si.c

1557

u32 link_width_cntl, mask;

sys/dev/pci/drm/amd/amdgpu/si.c

1564

mask = LC_LINK_WIDTH_X0;

sys/dev/pci/drm/amd/amdgpu/si.c

1567

mask = LC_LINK_WIDTH_X1;

sys/dev/pci/drm/amd/amdgpu/si.c

1570

mask = LC_LINK_WIDTH_X2;

sys/dev/pci/drm/amd/amdgpu/si.c

1573

mask = LC_LINK_WIDTH_X4;

sys/dev/pci/drm/amd/amdgpu/si.c

1576

mask = LC_LINK_WIDTH_X8;

sys/dev/pci/drm/amd/amdgpu/si.c

1579

mask = LC_LINK_WIDTH_X16;

sys/dev/pci/drm/amd/amdgpu/si.c

1588

link_width_cntl |= mask << PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT;

sys/dev/pci/drm/amd/amdgpu/si.c

1668

uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;

sys/dev/pci/drm/amd/amdgpu/si.c

1670

if ((RREG32(cg_upll_func_cntl) & mask) == mask)

sys/dev/pci/drm/amd/amdgpu/si.c

1895

uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;

sys/dev/pci/drm/amd/amdgpu/si.c

1897

if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask)

sys/dev/pci/drm/amd/amdgpu/soc15.h

105

#define SOC15_REG_FIELD_VAL(val, mask, shift) (((val) & mask) >> shift)

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

100

#define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

103

#reg, expected_value, mask)

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

105

#define SOC15_WAIT_ON_RREG_OFFSET(ip, inst, reg, offset, expected_value, mask) \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

108

#reg, expected_value, mask)

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

31

#define GET_MASK(ip, mask) \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

33

adev->ip_map.logical_to_dev_mask(adev, ip##_HWIP, mask) : mask)

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

504

.mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK | ACA_ERROR_DEFERRED_MASK,

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1385

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1397

amdgpu_ring_write(ring, mask);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1407

uint32_t data0, data1, mask;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1414

mask = 0xffffffff;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1415

uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1438

uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1442

amdgpu_ring_write(ring, mask);

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

603

u32 mask = 0;

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

605

mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE0) ? 0 : SRBM_STATUS2__VCE0_BUSY_MASK;

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

606

mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE1) ? 0 : SRBM_STATUS2__VCE1_BUSY_MASK;

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

608

return !(RREG32(mmSRBM_STATUS2) & mask);

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

742

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

746

amdgpu_ring_write(ring, mask);

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c

57

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c

61

amdgpu_ring_write(ring, mask);

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c

69

uint32_t data0, data1, mask;

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c

76

mask = 0xffffffff;

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c

77

vcn_dec_sw_ring_emit_reg_wait(ring, data0, data1, mask);

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.h

38

uint32_t val, uint32_t mask);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1618

uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1630

amdgpu_ring_write(ring, mask);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1640

uint32_t data0, data1, mask;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1647

mask = 0xffffffff;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1648

vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1773

uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1777

amdgpu_ring_write(ring, mask);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1594

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1605

amdgpu_ring_write(ring, mask);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1616

uint32_t data0, data1, mask;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1623

mask = 0xffffffff;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1624

vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1764

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1768

amdgpu_ring_write(ring, mask);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.h

35

uint32_t val, uint32_t mask);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.h

48

uint32_t val, uint32_t mask);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1532

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1540

amdgpu_ring_write(ring, mask);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

2062

.mask = ACA_ERROR_UE_MASK,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.h

36

uint32_t val, uint32_t mask);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1687

.mask = ACA_ERROR_UE_MASK,

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

3056

args->set_node_address_watch.mask,

sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.c

69

__poll_t mask = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.c

75

mask = EPOLLIN | EPOLLRDNORM;

sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.c

78

return mask;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3249

u64 mask = 0xffff;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3258

res = (val & mask) >> shift;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3280

mask <<= 16;

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

133

uint32_t mask = 1 << i;

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

135

if (mantissa & mask)

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

136

value |= mask;

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

142

uint32_t mask = 1 << j;

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

144

if (exponenta & mask)

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

145

value |= mask << i;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1836

info->mask = (uint32_t) (1 <<

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1838

info->mask_y = info->mask + 2;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1839

info->mask_en = info->mask + 1;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1840

info->mask_mask = info->mask - 1;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

861

uint32_t mask = get_support_mask_for_device_id(id);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

863

return (le16_to_cpu(bp->object_info_tbl.v1_1->usDeviceSupport) & mask) != 0;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

1590

uint32_t mask = get_support_mask_for_device_id(id);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

1595

return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & mask) != 0;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

1598

return (le16_to_cpu(bp->object_info_tbl.v1_5->supporteddevices) & mask) != 0;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

694

info->mask = (uint32_t) (1 <<

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

696

info->mask_y = info->mask + 2;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

697

info->mask_en = info->mask + 1;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

698

info->mask_mask = info->mask - 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2595

if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2602

pin_info.mask);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

100

ASSERT(mask != 0);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

102

field_value_mask->value = (field_value_mask->value & ~mask) | (mask & (value << shift));

sys/dev/pci/drm/amd/display/dc/dc_helper.c

103

field_value_mask->mask = field_value_mask->mask | mask;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

111

uint32_t shift, mask, field_value;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

120

mask = va_arg(ap, uint32_t);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

124

field_value, mask, shift);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

200

seq->modify_mask = field_value_mask->mask;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

208

uint32_t mask, uint32_t shift, uint32_t condition_value, uint32_t time_out_us)

sys/dev/pci/drm/amd/display/dc/dc_helper.c

216

cmd_buf->reg_wait.condition_field_value = mask & (condition_value << shift);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

217

cmd_buf->reg_wait.mask = mask;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

244

reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

265

reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

278

uint8_t shift, uint32_t mask, uint32_t *field_value)

sys/dev/pci/drm/amd/display/dc/dc_helper.c

281

*field_value = get_reg_field_value_ex(reg_val, mask, shift);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

428

uint32_t addr, uint32_t shift, uint32_t mask, uint32_t condition_value,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

438

dmub_reg_wait_done_pack(ctx, addr, mask, shift, condition_value,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

461

field_value = get_reg_field_value_ex(reg_val, mask, shift);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

511

uint32_t shift, mask, *field_value;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

524

mask = va_arg(ap, uint32_t);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

527

*field_value = get_reg_field_value_ex(value, mask, shift);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

542

uint32_t shift, mask, field_value;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

553

mask = va_arg(ap, uint32_t);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

556

reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

572

uint32_t shift, mask, field_value;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

583

mask = va_arg(ap, uint32_t);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

586

reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

601

uint32_t shift, mask, *field_value;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

614

mask = va_arg(ap, uint32_t);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

617

*field_value = get_reg_field_value_ex(value, mask, shift);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

91

uint32_t mask;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

97

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

51

aux110->shift->field_name, aux110->mask->field_name

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

512

const struct dce110_aux_registers_mask *mask,

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

524

aux_engine110->mask = mask;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

265

const struct dce110_aux_registers_mask *mask;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

293

const struct dce110_aux_registers_mask *mask,

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c

277

const struct dce_panel_cntl_mask *mask)

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c

288

dce_panel_cntl->mask = mask;

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c

47

dce_panel_cntl->shift->field_name, dce_panel_cntl->mask->field_name

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.h

119

const struct dce_panel_cntl_mask *mask;

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.h

127

const struct dce_panel_cntl_mask *mask);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

524

void dcn10_clear_status_bits(struct dc *dc, unsigned int mask)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

535

if (mask == 0x0)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

536

mask = 0xFFFFFFFF;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

538

if (mask & DC_HW_STATE_MASK_HUBP_UNDERFLOW)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

541

if (mask & DC_HW_STATE_MASK_OTPC_UNDERFLOW)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

545

void dcn10_get_hw_state(struct dc *dc, char *pBuf, unsigned int bufSize, unsigned int mask)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

566

if (mask == 0x0)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

567

mask = 0xFFFF; // Default, capture all, invariant only

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

569

if ((mask & DC_HW_STATE_MASK_HUBBUB) && remaining_buf_size > 0) {

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

575

if ((mask & DC_HW_STATE_MASK_HUBP) && remaining_buf_size > 0) {

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

576

chars_printed = dcn10_get_hubp_states(dc, pBuf, remaining_buf_size, mask & DC_HW_STATE_INVAR_ONLY);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

581

if ((mask & DC_HW_STATE_MASK_RQ) && remaining_buf_size > 0) {

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

587

if ((mask & DC_HW_STATE_MASK_DLG) && remaining_buf_size > 0) {

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

593

if ((mask & DC_HW_STATE_MASK_TTU) && remaining_buf_size > 0) {

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

599

if ((mask & DC_HW_STATE_MASK_CM) && remaining_buf_size > 0) {

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

605

if ((mask & DC_HW_STATE_MASK_MPCC) && remaining_buf_size > 0) {

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

611

if ((mask & DC_HW_STATE_MASK_OTG) && remaining_buf_size > 0) {

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

617

if ((mask & DC_HW_STATE_MASK_CLOCKS) && remaining_buf_size > 0) {

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.h

33

void dcn10_clear_status_bits(struct dc *dc, unsigned int mask);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.h

41

unsigned int mask);

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

209

const struct dcn301_panel_cntl_mask *mask)

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

213

dcn301_panel_cntl->mask = mask;

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

46

dcn301_panel_cntl->shift->field_name, dcn301_panel_cntl->mask->field_name

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.h

87

const struct dcn301_panel_cntl_mask *mask;

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.h

95

const struct dcn301_panel_cntl_mask *mask);

sys/dev/pci/drm/amd/display/dc/dm_services.h

105

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/dm_services.h

108

ASSERT(mask != 0);

sys/dev/pci/drm/amd/display/dc/dm_services.h

109

return (reg_value & ~mask) | (mask & (value << shift));

sys/dev/pci/drm/amd/display/dc/dm_services.h

142

uint32_t addr, uint32_t mask, uint32_t shift, uint32_t condition_value,

sys/dev/pci/drm/amd/display/dc/dm_services.h

90

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/dm_services.h

93

return (mask & reg_value) >> shift;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

415

static bool are_timings_trivially_synchronizable(struct dml2_display_cfg *display_config, int mask)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

425

if (mask & (0x1 << i)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

454

static int find_smallest_idle_time_in_vblank_us(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out, int mask)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

464

if (mask & (0x1 << i)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

197

static bool are_timings_trivially_synchronizable(struct display_configuation_with_meta *display_config, int mask)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

207

if (mask & (0x1 << i)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1009

unsigned int mask)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1017

if (is_bit_set_in_bitfield(mask, i)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1018

if (mask != pmo->scratch.pmo_dcn4.synchronized_timing_group_masks[i]) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1040

unsigned int mask)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1047

if (is_bit_set_in_bitfield(mask, i)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1078

unsigned int mask)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1101

if (is_bit_set_in_bitfield(mask, (unsigned char)plane_descriptor->stream_index)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1125

if (is_bit_set_in_bitfield(mask, i)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

991

unsigned int mask)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

998

if (is_bit_set_in_bitfield(mask, i)) {

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

106

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

121

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

190

info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

222

info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

257

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

260

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

263

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

266

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

269

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

272

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

275

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

286

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

289

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

292

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

295

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

298

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

301

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

312

info->mask = DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

316

info->mask = DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

329

info->mask = DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

333

info->mask =

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

338

info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

342

info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

360

info->mask_y = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

361

info->mask_en = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

362

info->mask_mask = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

41

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

49

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

79

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

101

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

128

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

143

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

212

info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

244

info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

279

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

282

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

285

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

288

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

291

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

294

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

297

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

308

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

311

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

314

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

317

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

320

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

323

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

334

info->mask = DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

338

info->mask = DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

351

info->mask = DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

355

info->mask =

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

360

info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

364

info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

382

info->mask_y = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

383

info->mask_en = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

384

info->mask_mask = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

63

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

71

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

103

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

130

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

145

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

166

*en = index_from_vector(mask);

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

219

info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

251

info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

286

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

289

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

292

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

295

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

298

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

301

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

304

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

315

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

318

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

321

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

324

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

327

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

330

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

341

info->mask = DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

345

info->mask = DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

358

info->mask = DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

362

info->mask =

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

367

info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

371

info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

380

info->mask = (1 << en);

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

381

result = (info->mask <= GPIO_GPIO_PAD_MAX);

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

394

info->mask_y = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

395

info->mask_en = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

396

info->mask_mask = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

48

uint32_t mask = 1;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

51

if (vector == mask)

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

55

mask <<= 1;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

56

} while (mask);

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

65

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

73

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

103

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

130

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

145

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

166

*en = index_from_vector(mask);

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

219

info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

251

info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

286

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

289

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

292

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

295

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

298

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

301

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

304

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

315

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

318

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

321

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

324

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

327

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

330

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

341

info->mask = DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

345

info->mask = DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

358

info->mask = DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

362

info->mask =

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

367

info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

371

info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

380

info->mask = (1 << en);

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

381

result = (info->mask <= GPIO_GPIO_PAD_MAX);

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

394

info->mask_y = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

395

info->mask_en = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

396

info->mask_mask = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

48

uint32_t mask = 1;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

51

if (vector == mask)

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

55

mask <<= 1;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

56

} while (mask);

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

65

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

73

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

101

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

128

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

143

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

212

info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

244

info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

279

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

282

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

285

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

288

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

291

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

294

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

297

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

308

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

311

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

314

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

317

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

320

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

323

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

334

info->mask = DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

338

info->mask = DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

351

info->mask = DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

355

info->mask =

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

360

info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

364

info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

382

info->mask_y = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

383

info->mask_en = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

384

info->mask_mask = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

63

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

71

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

105

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

132

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

201

info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

231

info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

264

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

267

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

270

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

273

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

276

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

279

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

282

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

293

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

296

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

299

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

302

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

305

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

308

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

355

info->mask_y = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

356

info->mask_en = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

357

info->mask_mask = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

67

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

75

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

104

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

131

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

197

info->mask = DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

224

info->mask = DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

254

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

257

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

260

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

263

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

266

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

269

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

272

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

283

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

286

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

289

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

292

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

295

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

298

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

345

info->mask_y = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

346

info->mask_en = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

347

info->mask_mask = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

66

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

74

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

112

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

139

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

208

info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

238

info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

271

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

274

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

277

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

280

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

283

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

286

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

289

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

300

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

303

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

306

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

309

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

312

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

315

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

362

info->mask_y = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

363

info->mask_en = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

364

info->mask_mask = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

74

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

82

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

105

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

132

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

198

info->mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

225

info->mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

255

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

258

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

261

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

264

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

267

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

270

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

273

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

284

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

287

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

290

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

293

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

296

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

299

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

346

info->mask_y = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

347

info->mask_en = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

348

info->mask_mask = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

67

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

75

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

100

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

124

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

179

info->mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

206

info->mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

236

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

239

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

242

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

245

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

248

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

251

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

262

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

265

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

268

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

271

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

274

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

321

info->mask_y = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

322

info->mask_en = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

323

info->mask_mask = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

65

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

73

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

163

info->mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

190

info->mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

220

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

223

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

226

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

229

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

232

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

235

info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

246

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

249

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

252

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

255

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

258

info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

305

info->mask_y = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

306

info->mask_en = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

307

info->mask_mask = info->mask;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

40

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

48

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

75

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

99

switch (mask) {

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

129

uint32_t mask)

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

134

if (!service->translate.funcs->offset_to_id(offset, mask, &id, &en)) {

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

145

uint32_t mask)

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

151

if (!service->translate.funcs->offset_to_id(offset, mask, &id, &en)) {

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

186

pin.mask = 0xFFFFFFFF;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

491

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

498

if (!service->translate.funcs->offset_to_id(offset, mask, &id, &en))

sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.c

191

pin->store.mask = 0;

sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.c

45

REG_GET(MASK_reg, MASK, &gpio->store.mask);

sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.c

54

REG_UPDATE(MASK_reg, MASK, gpio->store.mask);

sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.h

36

uint32_t mask;

sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.h

98

uint32_t mask;

sys/dev/pci/drm/amd/display/dc/gpio/hw_translate.h

32

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

166

unsigned int mask);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

167

void dcn10_clear_status_bits(struct dc *dc, unsigned int mask);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

366

unsigned int bufSize, unsigned int mask);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

367

void (*clear_status_bits)(struct dc *dc, unsigned int mask);

sys/dev/pci/drm/amd/display/dc/inc/hw/gpio.h

86

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

392

uint8_t shift, uint32_t mask, uint32_t *field_value);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c

117

pin_info.mask);

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

112

uint32_t mask = 1 << i;

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

114

if (mantissa & mask)

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

115

value |= mask;

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

121

uint32_t mask = 1 << j;

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

123

if (exponenta & mask)

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

124

value |= mask << i;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1752

uint32_t mask; /**< Mask for register bits */

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

177

const struct dmub_srv_common_reg_mask mask;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

178

const struct dmub_srv_dcn31_reg_mask mask;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

51

#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

194

struct dmub_srv_dcn32_reg_mask mask;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

49

#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

196

struct dmub_srv_dcn35_reg_mask mask;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn351.c

26

#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn36.c

26

#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

196

const struct dmub_srv_dcn401_reg_mask mask;

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

100

reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

105

uint32_t mask, uint32_t *field_value)

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

108

*field_value = get_reg_field_value_ex(reg_val, mask, shift);

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

31

uint32_t mask;

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

36

uint32_t value, uint32_t mask, uint8_t shift)

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

39

(field_value_mask->value & ~mask) | (mask & (value << shift));

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

40

field_value_mask->mask = field_value_mask->mask | mask;

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

48

uint32_t shift, mask, field_value;

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

57

mask = va_arg(ap, uint32_t);

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

60

set_reg_field_value_masks(field_value_mask, field_value, mask,

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

66

static inline uint32_t get_reg_field_value_ex(uint32_t reg_value, uint32_t mask,

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

69

return (mask & reg_value) >> shift;

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

85

reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

121

uint32_t mask, uint32_t *field_value);

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

45

#define FD(reg_field) (REGS)->shift.reg_field, (REGS)->mask.reg_field

sys/dev/pci/drm/amd/display/include/gpio_service_interface.h

52

uint32_t mask);

sys/dev/pci/drm/amd/display/include/gpio_service_interface.h

57

uint32_t mask);

sys/dev/pci/drm/amd/display/include/gpio_service_interface.h

74

uint32_t mask,

sys/dev/pci/drm/amd/display/include/gpio_types.h

82

uint32_t mask;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

425

int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

607

uint32_t mask;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

735

uint32_t mask;

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1319

uint32_t mask)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1330

mask);

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1021

static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1031

*mask = 0;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1042

*mask |= 1 << level;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1058

uint32_t mask = 0;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1060

ret = amdgpu_read_mask(buf, count, &mask);

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1068

ret = amdgpu_dpm_force_clock_level(adev, type, mask);

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1711

uint32_t mask,

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1896

uint32_t mask, enum amdgpu_device_attr_states *states)

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1905

uint32_t mask, enum amdgpu_device_attr_states *states)

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1922

uint32_t mask, enum amdgpu_device_attr_states *states)

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1942

if (!(attr->flags & mask))

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1949

uint32_t mask, enum amdgpu_device_attr_states *states)

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1956

if (!(attr->flags & mask)) {

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1981

uint32_t mask, enum amdgpu_device_attr_states *states)

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1990

if (!(attr->flags & mask)) {

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

2557

uint32_t mask, enum amdgpu_device_attr_states *states)

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

2563

if (!(attr->flags & mask)) {

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

2663

uint32_t mask, struct list_head *attr_list)

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

2672

uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

2682

ret = attr_update(adev, attr, mask, &attr_states);

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

2723

uint32_t mask,

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

2730

ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list);

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

4673

uint32_t mask = 0;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

4701

mask = ATTR_FLAG_ONEVF;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

4704

mask = 0;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

4708

mask = ATTR_FLAG_MASK_ALL;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

4715

mask,

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

511

uint32_t mask);

sys/dev/pci/drm/amd/pm/inc/amdgpu_pm.h

89

uint32_t mask, enum amdgpu_device_attr_states *states);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1505

u32 mask;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1514

mask = 1 << pi->uvd_boot_level;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1516

mask = 0x1f;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1529

mask);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

412

cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

426

data &= ~config_regs->mask;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

427

data |= ((config_regs->value << config_regs->shift) & config_regs->mask);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

72

u32 mask;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c

126

u32 data, original_data, addr, extra_shift, t_byte, count, mask;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c

145

mask = 0;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c

149

mask = (mask << 8) | 0xff;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c

154

mask <<= 8;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c

157

mask = (mask << 8) | 0xff;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c

162

data |= original_data & mask;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2868

data &= ~config_regs->mask;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2869

data |= ((config_regs->value << config_regs->shift) & config_regs->mask);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

862

u32 mask;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

691

enum pp_clock_type type, uint32_t mask)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

708

return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c

114

if (!baco_cmd_handler(hwmgr, entry[i].cmd, reg, entry[i].mask,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c

27

static bool baco_wait_register(struct pp_hwmgr *hwmgr, u32 reg, u32 mask, u32 value)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c

36

} while (value != (data & mask) && (timeout != 0));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c

44

static bool baco_cmd_handler(struct pp_hwmgr *hwmgr, u32 command, u32 reg, u32 mask,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c

57

data = (data & (~mask)) | (value << shift);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c

61

ret = baco_wait_register(hwmgr, reg, mask, value);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c

93

if (!baco_cmd_handler(hwmgr, entry[i].cmd, reg, entry[i].mask,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.h

39

uint32_t mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.h

51

uint32_t mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

926

uint32_t mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

931

mask = 0xFFFFFFFF;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

933

mask = (1 << ((end_index - start_index) + 1)) - 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

944

*efuse = result ? 0 : le32_to_cpu(efuse_param.ulEfuseValue) & mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

973

enum pp_clock_type type, uint32_t mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

980

low = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

981

high = mask ? (fls(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

174

enum pp_clock_type type, uint32_t mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4919

enum pp_clock_type type, uint32_t mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4923

if (mask == 0)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4931

data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4938

data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4943

uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

48

uint32_t mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

908

cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

928

data &= ~config_regs->mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

929

data |= ((config_regs->value << config_regs->shift) & config_regs->mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1547

enum pp_clock_type type, uint32_t mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1553

mask,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1557

mask,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

101

original_data &= ~mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

111

uint32_t value, uint32_t mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

123

if ((cur_value & mask) == (value & mask))

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

144

uint32_t mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

152

return phm_wait_on_register(hwmgr, indirect_port + 1, value, mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

157

uint32_t value, uint32_t mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

168

if ((cur_value & mask) != (value & mask))

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

183

uint32_t mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

190

value, mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

375

int32_t mask = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

379

mask = mask << 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

381

mask |= 0x1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

383

mask &= 0xFFFFFFFE;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

386

return mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

535

uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

539

while (0 == (mask & (1 << level)))

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

92

u32 mask = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

97

mask = 0xFF << shift;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

99

mask = 0xFFFF << shift;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

100

uint32_t value, uint32_t mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

106

uint32_t mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

176

#define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

177

phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

180

#define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

181

PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

187

#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

189

mm##port##_INDEX, index, value, mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

191

#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

192

PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

201

port, index, value, mask) \

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

203

mm##port##_INDEX_11, index, value, mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

205

#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

206

PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

215

port, index, value, mask) \

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

217

mm##port##_INDEX_11, index, value, mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

219

#define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

220

PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

228

index, value, mask) \

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

230

index, value, mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

232

#define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

234

mm##reg, value, mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

64

uint32_t value, uint32_t mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

68

uint32_t value, uint32_t mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

91

extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4275

enum pp_clock_type type, uint32_t mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4281

data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4282

data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4294

data->smc_state_table.mem_boot_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4295

data->smc_state_table.mem_max_level = mask ? (fls(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4308

data->smc_state_table.soc_boot_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4309

data->smc_state_table.soc_max_level = mask ? (fls(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

969

uint32_t mask = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

980

mask |= (uint32_t)(i << (8 * j));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

988

pp_table->LedPin0 = (uint8_t)(mask & 0xff);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

989

pp_table->LedPin1 = (uint8_t)((mask >> 8) & 0xff);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

990

pp_table->LedPin2 = (uint8_t)((mask >> 16) & 0xff);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

759

data &= ~config_regs->mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

760

data |= ((config_regs->value << config_regs->shift) & config_regs->mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

765

data &= ~config_regs->mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

766

data |= ((config_regs->value << config_regs->shift) & config_regs->mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

771

data &= ~config_regs->mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

772

data |= ((config_regs->value << config_regs->shift) & config_regs->mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

791

data &= ~config_regs->mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

792

data |= ((config_regs->value << config_regs->shift) & config_regs->mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.h

47

uint32_t mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.h

55

uint32_t mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2026

enum pp_clock_type type, uint32_t mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2034

soft_min_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2035

soft_max_level = mask ? (fls(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2054

soft_min_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2055

soft_max_level = mask ? (fls(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2075

soft_min_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2076

soft_max_level = mask ? (fls(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2103

hard_min_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

58

enum pp_clock_type type, uint32_t mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2567

enum pp_clock_type type, uint32_t mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2575

soft_min_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2576

soft_max_level = mask ? (fls(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2602

soft_min_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2603

soft_max_level = mask ? (fls(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2630

soft_min_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2631

soft_max_level = mask ? (fls(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2658

soft_min_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2659

soft_max_level = mask ? (fls(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2686

hard_min_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2708

soft_min_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2709

soft_max_level = mask ? (fls(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

313

int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1892

u32 mask = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1903

mask |= (i << (8 * j));

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1910

if (mask)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1913

mask,

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2623

uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2637

ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2639

smu->user_dpm_profile.clk_mask[clk_type] = mask;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2649

uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2687

return smu_force_smuclk_levels(smu, clk_type, mask);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

64

uint32_t mask);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1124

int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1131

enum smu_feature_mask mask);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

744

int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1003

enum smu_clk_type type, uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1017

soft_min_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1018

soft_max_level = mask ? (fls(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1660

enum smu_clk_type clk_type, uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1666

soft_min_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1667

soft_max_level = mask ? (fls(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1441

enum smu_clk_type clk_type, uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1446

soft_min_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1447

soft_max_level = mask ? (fls(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1167

enum smu_clk_type clk_type, uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1173

soft_min_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1174

soft_max_level = mask ? (fls(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

793

enum smu_clk_type clk_type, uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

799

soft_min_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

800

soft_max_level = mask ? (fls(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1040

enum smu_clk_type type, uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1047

soft_min_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1048

soft_max_level = mask ? (fls(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1987

uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1996

soft_min_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1997

soft_max_level = mask ? (fls(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

888

uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

894

soft_min_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

895

soft_max_level = mask ? (fls(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

936

enum smu_clk_type clk_type, uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

942

soft_min_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

943

soft_max_level = mask ? (fls(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1641

enum smu_clk_type type, uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1648

soft_min_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1649

soft_max_level = mask ? (fls(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1976

uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1985

soft_min_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1986

soft_max_level = mask ? (fls(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1118

enum smu_clk_type clk_type, uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1124

soft_min_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1125

soft_max_level = mask ? (fls(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1266

uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1272

soft_min_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1273

soft_max_level = mask ? (fls(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1382

uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1391

soft_min_level = mask ? (ffs(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1392

soft_max_level = mask ? (fls(mask) - 1) : 0;

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

598

enum smu_feature_mask mask)

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

605

mask);

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

621

enum smu_feature_mask mask)

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

642

mask);

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

777

enum smu_feature_mask mask,

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

784

mask);

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

899

enum smu_feature_mask mask)

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

904

if (mask != SMU_FEATURE_COUNT) {

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

907

mask);

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h

129

enum smu_feature_mask mask);

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h

132

enum smu_feature_mask mask);

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h

149

enum smu_feature_mask mask,

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h

159

enum smu_feature_mask mask);

sys/dev/pci/drm/amd/pm/swsmu/smu_internal.h

61

#define smu_feature_get_enabled_mask(smu, mask) smu_ppt_funcs(get_enabled_mask, -EOPNOTSUPP, smu, mask)

sys/dev/pci/drm/amd/pm/swsmu/smu_internal.h

62

#define smu_feature_is_enabled(smu, mask) smu_ppt_funcs(feature_is_enabled, 0, smu, mask)

sys/dev/pci/drm/amd/pm/swsmu/smu_internal.h

63

#define smu_disable_all_features_with_exception(smu, mask) smu_ppt_funcs(disable_all_features_with_exception, 0, smu, mask)

sys/dev/pci/drm/apple/parser.c

837

static int parse_nchans_mask(struct dcp_parse_ctx *handle, unsigned int *mask)

sys/dev/pci/drm/apple/parser.c

842

*mask = 0;

sys/dev/pci/drm/apple/parser.c

850

*mask |= 1 << nchans;

sys/dev/pci/drm/apple/parser.c

860

struct dcp_sound_format_mask mask = {0, 0, 0};

sys/dev/pci/drm/apple/parser.c

866

ret = parse_sample_rate_bit(it.handle, &mask.rates);

sys/dev/pci/drm/apple/parser.c

868

ret = parse_sample_fmtbit(it.handle, &mask.formats);

sys/dev/pci/drm/apple/parser.c

870

ret = parse_nchans_mask(it.handle, &mask.nchans);

sys/dev/pci/drm/apple/parser.c

878

trace_avep_sound_mode(handle->dcp, mask.rates, mask.formats, mask.nchans);

sys/dev/pci/drm/apple/parser.c

880

if (!(mask.rates & sieve->rates) || !(mask.formats & sieve->formats) ||

sys/dev/pci/drm/apple/parser.c

881

!(mask.nchans & sieve->nchans))

sys/dev/pci/drm/apple/parser.c

885

hits->rates |= mask.rates;

sys/dev/pci/drm/apple/parser.c

886

hits->formats |= mask.formats;

sys/dev/pci/drm/apple/parser.c

887

hits->nchans |= mask.nchans;

sys/dev/pci/drm/display/drm_dp_helper.c

292

u8 rd_interval, mask;

sys/dev/pci/drm/display/drm_dp_helper.c

300

mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;

sys/dev/pci/drm/display/drm_dp_helper.c

307

mask = DP_TRAINING_AUX_RD_MASK;

sys/dev/pci/drm/display/drm_dp_helper.c

316

mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;

sys/dev/pci/drm/display/drm_dp_helper.c

323

mask = DP_TRAINING_AUX_RD_MASK;

sys/dev/pci/drm/display/drm_dp_helper.c

339

return parse(aux, rd_interval & mask);

sys/dev/pci/drm/display/drm_dp_tunnel.c

1197

u8 mask = DP_BW_ALLOCATION_CAPABILITY_CHANGED | DP_ESTIMATED_BW_CHANGED;

sys/dev/pci/drm/display/drm_dp_tunnel.c

1203

val &= mask;

sys/dev/pci/drm/display/drm_dp_tunnel.c

914

u8 mask = DP_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE | DP_UNMASK_BW_ALLOCATION_IRQ;

sys/dev/pci/drm/display/drm_dp_tunnel.c

921

val |= mask;

sys/dev/pci/drm/display/drm_dp_tunnel.c

923

val &= ~mask;

sys/dev/pci/drm/drm_client_modeset.c

423

const u64 mask = BIT_ULL(connector_count) - 1;

sys/dev/pci/drm/drm_client_modeset.c

524

if ((conn_configured & mask) != mask) {

sys/dev/pci/drm/drm_client_modeset.c

628

unsigned long conn_configured, conn_seq, mask;

sys/dev/pci/drm/drm_client_modeset.c

654

mask = GENMASK(count - 1, 0);

sys/dev/pci/drm/drm_client_modeset.c

766

if ((conn_configured & mask) != mask && conn_configured != conn_seq)

sys/dev/pci/drm/drm_edid.c

4866

u16 mask;

sys/dev/pci/drm/drm_edid.c

4923

mask = (db[10 + offset] << 8) | db[11 + offset];

sys/dev/pci/drm/drm_edid.c

4925

mask = 0xffff;

sys/dev/pci/drm/drm_edid.c

4928

if (mask & (1 << i))

sys/dev/pci/drm/drm_fb_helper.c

855

u32 mask = (1 << info->var.transp.length) - 1;

sys/dev/pci/drm/drm_fb_helper.c

857

mask <<= info->var.transp.offset;

sys/dev/pci/drm/drm_fb_helper.c

858

value |= mask;

sys/dev/pci/drm/drm_file.c

662

__poll_t mask = 0;

sys/dev/pci/drm/drm_file.c

667

mask |= EPOLLIN | EPOLLRDNORM;

sys/dev/pci/drm/drm_file.c

669

return mask;

sys/dev/pci/drm/i915/display/icl_dsi.c

255

u32 tmp, mask, val;

sys/dev/pci/drm/i915/display/icl_dsi.c

263

mask = SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK;

sys/dev/pci/drm/i915/display/icl_dsi.c

267

tmp &= ~mask;

sys/dev/pci/drm/i915/display/icl_dsi.c

270

intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), mask, val);

sys/dev/pci/drm/i915/display/icl_dsi.c

272

mask = SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |

sys/dev/pci/drm/i915/display/icl_dsi.c

277

tmp &= ~mask;

sys/dev/pci/drm/i915/display/icl_dsi.c

280

intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), mask, val);

sys/dev/pci/drm/i915/display/icl_dsi.c

282

mask = POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |

sys/dev/pci/drm/i915/display/icl_dsi.c

286

intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), mask, val);

sys/dev/pci/drm/i915/display/icl_dsi.c

291

mask, val);

sys/dev/pci/drm/i915/display/intel_backlight.c

241

u32 tmp, mask;

sys/dev/pci/drm/i915/display/intel_backlight.c

256

mask = BACKLIGHT_DUTY_CYCLE_MASK;

sys/dev/pci/drm/i915/display/intel_backlight.c

259

mask = BACKLIGHT_DUTY_CYCLE_MASK_PNV;

sys/dev/pci/drm/i915/display/intel_backlight.c

262

tmp = intel_de_read(display, BLC_PWM_CTL) & ~mask;

sys/dev/pci/drm/i915/display/intel_combo_phy.c

100

if ((val & mask) != expected_val) {

sys/dev/pci/drm/i915/display/intel_combo_phy.c

105

reg.reg, val, mask, expected_val);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

95

enum phy phy, i915_reg_t reg, u32 mask,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3177

u32 mask;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3184

mask = XELPDP_DDI_CLOCK_SELECT_MASK(display);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3188

mask |= XELPDP_FORWARD_CLOCK_UNGATE;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3192

mask, val);

sys/dev/pci/drm/i915/display/intel_ddi.c

2348

int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED;

sys/dev/pci/drm/i915/display/intel_ddi.c

2353

err || (status & mask),

sys/dev/pci/drm/i915/display/intel_de.h

110

u32 mask, u32 value, unsigned int timeout_ms)

sys/dev/pci/drm/i915/display/intel_de.h

112

return intel_wait_for_register(__to_uncore(display), reg, mask,

sys/dev/pci/drm/i915/display/intel_de.h

119

u32 mask, u32 value,

sys/dev/pci/drm/i915/display/intel_de.h

122

return __intel_wait_for_register(__to_uncore(display), reg, mask,

sys/dev/pci/drm/i915/display/intel_de.h

128

u32 mask, u32 value, unsigned int timeout_ms)

sys/dev/pci/drm/i915/display/intel_de.h

134

ret = __intel_de_wait_for_register_nowl(display, reg, mask, value,

sys/dev/pci/drm/i915/display/intel_de.h

144

u32 mask, u32 value, unsigned int timeout_ms, u32 *out_value)

sys/dev/pci/drm/i915/display/intel_de.h

150

ret = intel_wait_for_register_fw(__to_uncore(display), reg, mask,

sys/dev/pci/drm/i915/display/intel_de.h

160

u32 mask, u32 value,

sys/dev/pci/drm/i915/display/intel_de.h

168

ret = __intel_wait_for_register(__to_uncore(display), reg, mask,

sys/dev/pci/drm/i915/display/intel_de.h

179

u32 mask, unsigned int timeout_ms)

sys/dev/pci/drm/i915/display/intel_de.h

181

return intel_de_wait(display, reg, mask, mask, timeout_ms);

sys/dev/pci/drm/i915/display/intel_de.h

186

u32 mask, unsigned int timeout_ms)

sys/dev/pci/drm/i915/display/intel_de.h

188

return intel_de_wait(display, reg, mask, 0, timeout_ms);

sys/dev/pci/drm/i915/display/intel_display.c

1603

u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;

sys/dev/pci/drm/i915/display/intel_display.c

1606

mask, enable ? mask : 0);

sys/dev/pci/drm/i915/display/intel_display.c

1947

struct intel_power_domain_mask *mask)

sys/dev/pci/drm/i915/display/intel_display.c

1955

bitmap_zero(mask->bits, POWER_DOMAIN_NUM);

sys/dev/pci/drm/i915/display/intel_display.c

1960

set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);

sys/dev/pci/drm/i915/display/intel_display.c

1961

set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);

sys/dev/pci/drm/i915/display/intel_display.c

1964

set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);

sys/dev/pci/drm/i915/display/intel_display.c

1970

set_bit(intel_encoder->power_domain, mask->bits);

sys/dev/pci/drm/i915/display/intel_display.c

1974

set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);

sys/dev/pci/drm/i915/display/intel_display.c

1977

set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);

sys/dev/pci/drm/i915/display/intel_display.c

1980

set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);

sys/dev/pci/drm/i915/display/intel_display.c

1995

crtc->enabled_power_domains.mask.bits,

sys/dev/pci/drm/i915/display/intel_display.c

1998

crtc->enabled_power_domains.mask.bits,

sys/dev/pci/drm/i915/display/intel_display.c

5036

#define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \

sys/dev/pci/drm/i915/display/intel_display.c

5037

if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \

sys/dev/pci/drm/i915/display/intel_display.c

5042

current_config->name & (mask), \

sys/dev/pci/drm/i915/display/intel_display.c

5043

pipe_config->name & (mask)); \

sys/dev/pci/drm/i915/display/intel_display.c

5157

#define PIPE_CONF_CHECK_FLAGS(name, mask) do { \

sys/dev/pci/drm/i915/display/intel_display.c

5158

if ((current_config->name ^ pipe_config->name) & (mask)) { \

sys/dev/pci/drm/i915/display/intel_display.c

5161

(mask), \

sys/dev/pci/drm/i915/display/intel_display.c

5162

current_config->name & (mask), \

sys/dev/pci/drm/i915/display/intel_display.c

5163

pipe_config->name & (mask)); \

sys/dev/pci/drm/i915/display/intel_display.c

5523

const char *reason, u8 mask)

sys/dev/pci/drm/i915/display/intel_display.c

5528

for_each_intel_crtc_in_pipe_mask(display->drm, crtc, mask) {

sys/dev/pci/drm/i915/display/intel_display_core.h

520

unsigned long mask;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1005

mask = GEN8_AUX_CHANNEL_A;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1007

mask |= GEN9_AUX_CHANNEL_B |

sys/dev/pci/drm/i915/display/intel_display_irq.c

1012

mask |= ICL_AUX_CHANNEL_F;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1013

mask |= ICL_AUX_CHANNEL_E;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1016

return mask;

sys/dev/pci/drm/i915/display/intel_display_irq.c

2132

u32 mask;

sys/dev/pci/drm/i915/display/intel_display_irq.c

2138

mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;

sys/dev/pci/drm/i915/display/intel_display_irq.c

2140

mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;

sys/dev/pci/drm/i915/display/intel_display_irq.c

2142

mask = SDE_GMBUS_CPT;

sys/dev/pci/drm/i915/display/intel_display_irq.c

2144

intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2347

u32 mask = SDE_GMBUS_ICP;

sys/dev/pci/drm/i915/display/intel_display_irq.c

2349

intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff);

sys/dev/pci/drm/i915/display/intel_display_irq.c

977

u32 mask;

sys/dev/pci/drm/i915/display/intel_display_power.c

1003

mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;

sys/dev/pci/drm/i915/display/intel_display_power.c

1006

mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;

sys/dev/pci/drm/i915/display/intel_display_power.c

1009

mask |= DC_STATE_EN_UPTO_DC6;

sys/dev/pci/drm/i915/display/intel_display_power.c

1012

mask |= DC_STATE_EN_UPTO_DC5;

sys/dev/pci/drm/i915/display/intel_display_power.c

1016

drm_dbg_kms(display->drm, "Allowed DC state mask %02x\n", mask);

sys/dev/pci/drm/i915/display/intel_display_power.c

1018

return mask;

sys/dev/pci/drm/i915/display/intel_display_power.c

1157

u32 mask, val, i;

sys/dev/pci/drm/i915/display/intel_display_power.c

1162

mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK |

sys/dev/pci/drm/i915/display/intel_display_power.c

1180

intel_de_rmw(display, MBUS_ABOX_CTL(i), mask, val);

sys/dev/pci/drm/i915/display/intel_display_power.c

1810

unsigned int mask;

sys/dev/pci/drm/i915/display/intel_display_power.c

1812

mask = status & DPLL_PORTB_READY_MASK;

sys/dev/pci/drm/i915/display/intel_display_power.c

1813

if (mask == 0xf)

sys/dev/pci/drm/i915/display/intel_display_power.c

1814

mask = 0x0;

sys/dev/pci/drm/i915/display/intel_display_power.c

1820

PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);

sys/dev/pci/drm/i915/display/intel_display_power.c

1822

mask = (status & DPLL_PORTC_READY_MASK) >> 4;

sys/dev/pci/drm/i915/display/intel_display_power.c

1823

if (mask == 0xf)

sys/dev/pci/drm/i915/display/intel_display_power.c

1824

mask = 0x0;

sys/dev/pci/drm/i915/display/intel_display_power.c

1830

PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);

sys/dev/pci/drm/i915/display/intel_display_power.c

1841

unsigned int mask;

sys/dev/pci/drm/i915/display/intel_display_power.c

1843

mask = status & DPLL_PORTD_READY_MASK;

sys/dev/pci/drm/i915/display/intel_display_power.c

1845

if (mask == 0xf)

sys/dev/pci/drm/i915/display/intel_display_power.c

1846

mask = 0x0;

sys/dev/pci/drm/i915/display/intel_display_power.c

1852

PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);

sys/dev/pci/drm/i915/display/intel_display_power.c

361

struct intel_power_domain_mask *mask)

sys/dev/pci/drm/i915/display/intel_display_power.c

363

bitmap_or(mask->bits,

sys/dev/pci/drm/i915/display/intel_display_power.c

408

const char *prefix, struct intel_power_domain_mask *mask)

sys/dev/pci/drm/i915/display/intel_display_power.c

415

drm_dbg_kms(display->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM));

sys/dev/pci/drm/i915/display/intel_display_power.c

416

for_each_power_domain(domain, mask)

sys/dev/pci/drm/i915/display/intel_display_power.c

460

struct intel_power_domain_mask *mask)

sys/dev/pci/drm/i915/display/intel_display_power.c

465

__async_put_domains_mask(power_domains, mask);

sys/dev/pci/drm/i915/display/intel_display_power.c

655

struct intel_power_domain_mask *mask)

sys/dev/pci/drm/i915/display/intel_display_power.c

665

for_each_power_domain(domain, mask) {

sys/dev/pci/drm/i915/display/intel_display_power.c

889

drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits));

sys/dev/pci/drm/i915/display/intel_display_power.c

895

set_bit(domain, power_domain_set->mask.bits);

sys/dev/pci/drm/i915/display/intel_display_power.c

905

drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits));

sys/dev/pci/drm/i915/display/intel_display_power.c

914

set_bit(domain, power_domain_set->mask.bits);

sys/dev/pci/drm/i915/display/intel_display_power.c

922

struct intel_power_domain_mask *mask)

sys/dev/pci/drm/i915/display/intel_display_power.c

928

!bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM));

sys/dev/pci/drm/i915/display/intel_display_power.c

931

for_each_power_domain(domain, mask) {

sys/dev/pci/drm/i915/display/intel_display_power.c

938

clear_bit(domain, power_domain_set->mask.bits);

sys/dev/pci/drm/i915/display/intel_display_power.c

953

u32 mask;

sys/dev/pci/drm/i915/display/intel_display_power.c

980

mask = display->platform.geminilake || display->platform.broxton ||

sys/dev/pci/drm/i915/display/intel_display_power.h

160

struct intel_power_domain_mask mask;

sys/dev/pci/drm/i915/display/intel_display_power.h

263

struct intel_power_domain_mask *mask);

sys/dev/pci/drm/i915/display/intel_display_power.h

269

intel_display_power_put_mask_in_set(display, power_domain_set, &power_domain_set->mask);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1126

u32 mask;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1132

mask = PUNIT_PWRGT_MASK(pw_idx);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1139

if ((val & mask) == state)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1143

ctrl &= ~mask;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1148

(val & mask) == state,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1177

u32 mask;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1181

mask = PUNIT_PWRGT_MASK(pw_idx);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1186

state = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS) & mask;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1200

ctrl = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL) & mask;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1558

enum dpio_channel ch, bool override, unsigned int mask)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1586

if (!override || mask == 0xf) {

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1599

} else if (mask != 0x0) {

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1655

bool override, unsigned int mask)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1665

display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1677

phy, ch, mask, display->power.chv_phy_control);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1681

assert_chv_phy_powergate(display, phy, ch, override, mask);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

608

u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) |

sys/dev/pci/drm/i915/display/intel_display_power_well.c

624

return (val & mask) == mask;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

715

u32 mask;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

717

mask = DC_STATE_EN_UPTO_DC5;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

720

mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6

sys/dev/pci/drm/i915/display/intel_display_power_well.c

723

mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

725

mask |= DC_STATE_EN_DC9;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

727

mask |= DC_STATE_EN_UPTO_DC6;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

729

return mask;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

775

u32 mask;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

789

mask = gen9_dc_mask(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

791

val & mask, state);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

794

if ((val & mask) != power_domains->dc_state)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

796

power_domains->dc_state, val & mask);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

803

val &= ~mask;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

811

power_domains->dc_state = val & mask;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

932

u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

936

if (bios_req & mask) {

sys/dev/pci/drm/i915/display/intel_display_power_well.c

939

if (!(drv_req & mask))

sys/dev/pci/drm/i915/display/intel_display_power_well.c

940

intel_de_write(display, regs->driver, drv_req | mask);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

941

intel_de_write(display, regs->bios, bios_req & ~mask);

sys/dev/pci/drm/i915/display/intel_display_power_well.h

153

bool override, unsigned int mask);

sys/dev/pci/drm/i915/display/intel_display_regs.h

172

#define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11))

sys/dev/pci/drm/i915/display/intel_display_types.h

1870

unsigned long mask;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

792

u8 mask = 0;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

808

mask |= BIT(to_intel_crtc(conn_state->base.crtc)->pipe);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

811

return mask;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

515

i915_reg_t reg, u32 mask, u32 expected,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

523

if ((val & mask) == expected)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

532

phy, &vaf, reg.reg, val, (val & ~mask) | expected,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

533

mask);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

544

u32 mask;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

549

#define _CHK(reg, mask, exp, fmt, ...) \

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

550

__phy_reg_verify_state(display, phy, reg, mask, exp, fmt, \

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

567

mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

568

ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

582

mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

584

ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

587

mask = GRC_DIS | GRC_RDY_OVRD;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

588

ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

643

u8 mask;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

647

mask = 0;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

653

mask |= BIT(lane);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

656

return mask;

sys/dev/pci/drm/i915/display/intel_dsb.c

374

static u32 intel_dsb_mask_to_byte_en(u32 mask)

sys/dev/pci/drm/i915/display/intel_dsb.c

376

return (!!(mask & 0xff000000) << 3 |

sys/dev/pci/drm/i915/display/intel_dsb.c

377

!!(mask & 0x00ff0000) << 2 |

sys/dev/pci/drm/i915/display/intel_dsb.c

378

!!(mask & 0x0000ff00) << 1 |

sys/dev/pci/drm/i915/display/intel_dsb.c

379

!!(mask & 0x000000ff) << 0);

sys/dev/pci/drm/i915/display/intel_dsb.c

384

i915_reg_t reg, u32 mask, u32 val)

sys/dev/pci/drm/i915/display/intel_dsb.c

388

(intel_dsb_mask_to_byte_en(mask) << DSB_BYTE_EN_SHIFT) |

sys/dev/pci/drm/i915/display/intel_dsb.c

514

i915_reg_t reg, u32 mask, u32 val,

sys/dev/pci/drm/i915/display/intel_dsb.c

520

intel_dsb_reg_write(dsb, DSB_POLLMASK(pipe, dsb->id), mask);

sys/dev/pci/drm/i915/display/intel_dsb.h

44

i915_reg_t reg, u32 mask, u32 val);

sys/dev/pci/drm/i915/display/intel_dsb.h

62

i915_reg_t reg, u32 mask, u32 val,

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

561

u32 value, mask, reg_address;

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

569

mask = get_unaligned_le32(data + 11);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

573

value, mask);

sys/dev/pci/drm/i915/display/intel_fb.c

445

static bool plane_caps_contain_any(u8 caps, u8 mask)

sys/dev/pci/drm/i915/display/intel_fb.c

447

return caps & mask;

sys/dev/pci/drm/i915/display/intel_fb.c

450

static bool plane_caps_contain_all(u8 caps, u8 mask)

sys/dev/pci/drm/i915/display/intel_fb.c

452

return (caps & mask) == mask;

sys/dev/pci/drm/i915/display/intel_hdmi.c

569

u32 mask;

sys/dev/pci/drm/i915/display/intel_hdmi.c

571

mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |

sys/dev/pci/drm/i915/display/intel_hdmi.c

576

mask |= VIDEO_DIP_ENABLE_DRM_GLK;

sys/dev/pci/drm/i915/display/intel_hdmi.c

579

mask |= VIDEO_DIP_ENABLE_AS_ADL;

sys/dev/pci/drm/i915/display/intel_hdmi.c

581

return val & mask;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1097

u32 mask = XELPDP_TBT_HOTPLUG_ENABLE |

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1104

mask, enable ? mask : 0);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

187

u32 mask, u32 bits)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

190

drm_WARN_ON(display->drm, bits & ~mask);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

192

intel_de_rmw(display, PORT_HOTPLUG_EN(display), mask, bits);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

208

u32 mask,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

212

i915_hotplug_interrupt_update_locked(display, mask, bits);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

496

u32 mask = PORTA_HOTPLUG_STATUS_MASK |

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

500

dig_hotplug_reg &= ~mask;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

26

u32 mask, u32 bits);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

28

u32 mask, u32 bits);

sys/dev/pci/drm/i915/display/intel_lspcon.c

650

u32 mask, tmp;

sys/dev/pci/drm/i915/display/intel_lspcon.c

663

mask = VIDEO_DIP_ENABLE_GMP_HSW;

sys/dev/pci/drm/i915/display/intel_lspcon.c

665

if (tmp & mask)

sys/dev/pci/drm/i915/display/intel_pmdemand.c

539

#define update_reg(reg, field, mask) do { \

sys/dev/pci/drm/i915/display/intel_pmdemand.c

540

u32 current_val = serialized ? 0 : REG_FIELD_GET((mask), *(reg)); \

sys/dev/pci/drm/i915/display/intel_pmdemand.c

544

*(reg) &= ~(mask); \

sys/dev/pci/drm/i915/display/intel_pmdemand.c

545

*(reg) |= REG_FIELD_PREP((mask), max3(old_val, new_val, current_val)); \

sys/dev/pci/drm/i915/display/intel_pps.c

607

u32 mask, u32 value)

sys/dev/pci/drm/i915/display/intel_pps.c

626

mask, value,

sys/dev/pci/drm/i915/display/intel_pps.c

631

(val & mask) == value,

sys/dev/pci/drm/i915/display/intel_psr.c

1857

u32 mask = 0;

sys/dev/pci/drm/i915/display/intel_psr.c

1881

mask = EDP_PSR_DEBUG_MASK_HPD;

sys/dev/pci/drm/i915/display/intel_psr.c

1884

mask |= EDP_PSR_DEBUG_MASK_MEMUP;

sys/dev/pci/drm/i915/display/intel_psr.c

1895

mask |= EDP_PSR_DEBUG_MASK_LPSP;

sys/dev/pci/drm/i915/display/intel_psr.c

1898

mask |= EDP_PSR_DEBUG_MASK_MAX_SLEEP;

sys/dev/pci/drm/i915/display/intel_psr.c

1905

mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;

sys/dev/pci/drm/i915/display/intel_psr.c

1909

mask |= EDP_PSR_DEBUG_MASK_SPRITE_ENABLE;

sys/dev/pci/drm/i915/display/intel_psr.c

1912

intel_de_write(display, psr_debug_reg(display, cpu_transcoder), mask);

sys/dev/pci/drm/i915/display/intel_psr.c

3153

u32 mask;

sys/dev/pci/drm/i915/display/intel_psr.c

3162

mask = EDP_PSR2_STATUS_STATE_MASK;

sys/dev/pci/drm/i915/display/intel_psr.c

3165

mask = EDP_PSR_STATUS_STATE_MASK;

sys/dev/pci/drm/i915/display/intel_psr.c

3170

err = intel_de_wait_for_clear(display, reg, mask, 50);

sys/dev/pci/drm/i915/display/intel_psr.c

378

u32 mask;

sys/dev/pci/drm/i915/display/intel_psr.c

383

mask = psr_irq_psr_error_bit_get(intel_dp);

sys/dev/pci/drm/i915/display/intel_psr.c

385

mask |= psr_irq_post_exit_bit_get(intel_dp) |

sys/dev/pci/drm/i915/display/intel_psr.c

389

psr_irq_mask_get(intel_dp), ~mask);

sys/dev/pci/drm/i915/display/intel_quirks.c

16

display->quirks.mask |= BIT(quirk);

sys/dev/pci/drm/i915/display/intel_quirks.c

21

intel_dp->quirks.mask |= BIT(quirk);

sys/dev/pci/drm/i915/display/intel_quirks.c

303

return display->quirks.mask & BIT(quirk);

sys/dev/pci/drm/i915/display/intel_quirks.c

308

return intel_dp->quirks.mask & BIT(quirk);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2568

u16 mask = 0;

sys/dev/pci/drm/i915/display/intel_sdvo.c

2577

mask |= SDVO_OUTPUT_LVDS1;

sys/dev/pci/drm/i915/display/intel_sdvo.c

2580

mask |= SDVO_OUTPUT_LVDS0;

sys/dev/pci/drm/i915/display/intel_sdvo.c

2583

mask |= SDVO_OUTPUT_TMDS1;

sys/dev/pci/drm/i915/display/intel_sdvo.c

2586

mask |= SDVO_OUTPUT_TMDS0;

sys/dev/pci/drm/i915/display/intel_sdvo.c

2589

mask |= SDVO_OUTPUT_RGB1;

sys/dev/pci/drm/i915/display/intel_sdvo.c

2592

mask |= SDVO_OUTPUT_RGB0;

sys/dev/pci/drm/i915/display/intel_sdvo.c

2597

mask &= sdvo->caps.output_flags;

sys/dev/pci/drm/i915/display/intel_sdvo.c

2598

num_bits = hweight16(mask);

sys/dev/pci/drm/i915/display/intel_tc.c

1021

u32 mask = 0;

sys/dev/pci/drm/i915/display/intel_tc.c

1029

mask |= BIT(TC_PORT_DP_ALT);

sys/dev/pci/drm/i915/display/intel_tc.c

1031

mask |= BIT(TC_PORT_TBT_ALT);

sys/dev/pci/drm/i915/display/intel_tc.c

1034

mask |= BIT(TC_PORT_LEGACY);

sys/dev/pci/drm/i915/display/intel_tc.c

1036

return mask;

sys/dev/pci/drm/i915/display/intel_tc.c

1275

u32 mask;

sys/dev/pci/drm/i915/display/intel_tc.c

1277

mask = tc->phy_ops->hpd_live_status(tc);

sys/dev/pci/drm/i915/display/intel_tc.c

1280

drm_WARN_ON_ONCE(display->drm, hweight32(mask) > 1);

sys/dev/pci/drm/i915/display/intel_tc.c

1282

return mask;

sys/dev/pci/drm/i915/display/intel_tc.c

1721

u32 mask = ~0;

sys/dev/pci/drm/i915/display/intel_tc.c

1726

mask = BIT(tc->mode);

sys/dev/pci/drm/i915/display/intel_tc.c

1728

return tc_phy_hpd_live_status(tc) & mask;

sys/dev/pci/drm/i915/display/intel_tc.c

301

u32 mask;

sys/dev/pci/drm/i915/display/intel_tc.c

309

mask = TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK;

sys/dev/pci/drm/i915/display/intel_tc.c

312

mask = DP_PIN_ASSIGNMENT_MASK(tc->phy_fia_idx);

sys/dev/pci/drm/i915/display/intel_tc.c

321

pin_assignment = (val & mask) >> (ffs(mask) - 1);

sys/dev/pci/drm/i915/display/intel_tc.c

533

u32 mask = 0;

sys/dev/pci/drm/i915/display/intel_tc.c

544

return mask;

sys/dev/pci/drm/i915/display/intel_tc.c

548

mask |= BIT(TC_PORT_TBT_ALT);

sys/dev/pci/drm/i915/display/intel_tc.c

550

mask |= BIT(TC_PORT_DP_ALT);

sys/dev/pci/drm/i915/display/intel_tc.c

553

mask |= BIT(TC_PORT_LEGACY);

sys/dev/pci/drm/i915/display/intel_tc.c

555

return mask;

sys/dev/pci/drm/i915/display/intel_tc.c

825

u32 mask = 0;

sys/dev/pci/drm/i915/display/intel_tc.c

833

mask |= BIT(TC_PORT_DP_ALT);

sys/dev/pci/drm/i915/display/intel_tc.c

835

mask |= BIT(TC_PORT_TBT_ALT);

sys/dev/pci/drm/i915/display/intel_tc.c

838

mask |= BIT(TC_PORT_LEGACY);

sys/dev/pci/drm/i915/display/intel_tc.c

840

return mask;

sys/dev/pci/drm/i915/display/vlv_dsi.c

230

u32 mask;

sys/dev/pci/drm/i915/display/vlv_dsi.c

248

mask = SPL_PKT_SENT_INTERRUPT;

sys/dev/pci/drm/i915/display/vlv_dsi.c

249

if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port), mask, 100))

sys/dev/pci/drm/i915/display/vlv_dsi.c

92

u32 mask;

sys/dev/pci/drm/i915/display/vlv_dsi.c

94

mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |

sys/dev/pci/drm/i915/display/vlv_dsi.c

98

mask, 100))

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

275

u32 mask;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

277

mask = BXT_DSI_PLL_DO_ENABLE | BXT_DSI_PLL_LOCKED;

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

279

enabled = (val & mask) == mask;

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1340

intel_gt_handle_error(engine->gt, engine->mask, 0,

sys/dev/pci/drm/i915/gem/i915_gem_create.c

280

u32 mask;

sys/dev/pci/drm/i915/gem/i915_gem_create.c

303

mask = 0;

sys/dev/pci/drm/i915/gem/i915_gem_create.c

321

if (mask & BIT(mr->id)) {

sys/dev/pci/drm/i915/gem/i915_gem_create.c

330

mask |= BIT(mr->id);

sys/dev/pci/drm/i915/gem/i915_gem_create.c

344

ext_data->placement_mask = mask;

sys/dev/pci/drm/i915/gem/i915_gem_shmem.c

678

gfp_t mask;

sys/dev/pci/drm/i915/gem/i915_gem_shmem.c

689

mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;

sys/dev/pci/drm/i915/gem/i915_gem_shmem.c

692

mask &= ~__GFP_HIGHMEM;

sys/dev/pci/drm/i915/gem/i915_gem_shmem.c

693

mask |= __GFP_DMA32;

sys/dev/pci/drm/i915/gem/i915_gem_shmem.c

698

mapping_set_gfp_mask(mapping, mask);

sys/dev/pci/drm/i915/gem/i915_gem_ttm.c

202

gfp_t mask;

sys/dev/pci/drm/i915/gem/i915_gem_ttm.c

208

mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;

sys/dev/pci/drm/i915/gem/i915_gem_ttm.c

211

mapping_set_gfp_mask(mapping, mask);

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1355

u64 mask;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1363

mask = ((max_page_size << 1ULL) - 1) & LINUX_PAGE_MASK;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1364

size = prandom_u32_state(prng) & mask;

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

151

const u64 mask = ~0ull << gen8_pd_shift(lvl + 1);

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

154

end += ~mask >> gen8_pd_shift(1);

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

157

if ((start ^ end) & mask)

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

165

const u64 mask = ~0ull << gen8_pd_shift(lvl + 1);

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

168

return (start ^ end) & mask && (start & ~mask) == 0;

sys/dev/pci/drm/i915/gt/intel_engine.h

230

void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask);

sys/dev/pci/drm/i915/gt/intel_engine.h

85

#define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \

sys/dev/pci/drm/i915/gt/intel_engine.h

88

((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1000

gt->info.num_engines = hweight32(mask);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

370

void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

380

ENGINE_WRITE(engine, RING_HWSTAM, mask);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

382

ENGINE_WRITE16(engine, RING_HWSTAM, mask);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

478

BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

483

engine->mask = BIT(id);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

961

unsigned int mask = 0;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

968

GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

988

mask |= BIT(i);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

997

if (drm_WARN_ON(&i915->drm, mask != engine_mask))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

998

gt->info.engine_mask = mask;

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

130

intel_gt_handle_error(engine->gt, engine->mask,

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

216

intel_gt_handle_error(engine->gt, engine->mask,

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

44

intel_engine_mask_t tmp, mask = engine->mask;

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

46

for_each_engine_masked(tengine, gt, mask, tmp)

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

80

intel_engine_mask_t tmp, mask = engine->mask;

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

82

for_each_engine_masked(tengine, gt, mask, tmp)

sys/dev/pci/drm/i915/gt/intel_engine_types.h

376

intel_engine_mask_t mask;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1003

if (!(rq->execution_mask & engine->mask)) /* We peeked too soon! */

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1450

GEM_BUG_ON(!(rq->execution_mask & engine->mask));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1533

if (rq->execution_mask != engine->mask)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2650

intel_gt_handle_error(engine->gt, engine->mask, 0,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3795

intel_engine_mask_t mask;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3802

mask = rq->execution_mask;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3803

if (unlikely(!mask)) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3806

mask = ve->siblings[0]->mask;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3811

mask, ve->base.sched_engine->queue_priority_hint);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3813

return mask;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3823

intel_engine_mask_t mask;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3827

mask = virtual_submission_mask(ve);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3829

if (unlikely(!mask))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3843

if (unlikely(!(mask & sibling->mask))) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

4008

GEM_BUG_ON(!is_power_of_2(sibling->mask));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

4009

if (sibling->mask & ve->base.mask) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

4034

ve->base.mask |= sibling->mask;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

580

rq->execution_mask != engine->mask)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

853

if (rq->execution_mask != engine->mask &&

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

334

u32 mask = gt->type == GT_MEDIA ?

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

342

intel_uncore_rmw(uncore, MTL_GUC_MGUC_INTR_MASK, mask, 0);

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

504

void gen5_gt_enable_irq(struct intel_gt *gt, u32 mask)

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

506

gen5_gt_update_irq(gt, mask, mask);

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

510

void gen5_gt_disable_irq(struct intel_gt *gt, u32 mask)

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

512

gen5_gt_update_irq(gt, mask, 0);

sys/dev/pci/drm/i915/gt/intel_gt_irq.h

35

void gen5_gt_disable_irq(struct intel_gt *gt, u32 mask);

sys/dev/pci/drm/i915/gt/intel_gt_irq.h

36

void gen5_gt_enable_irq(struct intel_gt *gt, u32 mask);

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

846

u32 mask,

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

855

#define done ((intel_gt_mcr_read_any(gt, reg) & mask) == value)

sys/dev/pci/drm/i915/gt/intel_gt_mcr.h

45

u32 mask,

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c

17

u32 mask = gt->pm_imr;

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c

22

mask <<= 16; /* pm is in upper half */

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c

29

intel_uncore_write(uncore, reg, mask);

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c

52

void gen6_gt_pm_unmask_irq(struct intel_gt *gt, u32 mask)

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c

54

gen6_gt_pm_update_irq(gt, mask, mask);

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c

57

void gen6_gt_pm_mask_irq(struct intel_gt *gt, u32 mask)

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c

59

gen6_gt_pm_update_irq(gt, mask, 0);

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c

78

u32 mask = gt->pm_ier;

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c

83

mask <<= 16; /* pm is in upper half */

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c

90

intel_uncore_write(uncore, reg, mask);

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.h

13

void gen6_gt_pm_unmask_irq(struct intel_gt *gt, u32 mask);

sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.h

14

void gen6_gt_pm_mask_irq(struct intel_gt *gt, u32 mask);

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

513

u32 mask;

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

523

bool val = rps_read_mask_mmio(&gt->rps, t_attr->reg32(gt), t_attr->mask);

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

533

.mask = mask__, \

sys/dev/pci/drm/i915/gt/intel_gtt.h

535

const u32 mask = NUM_PTE(pde_shift) - 1;

sys/dev/pci/drm/i915/gt/intel_gtt.h

537

return (address >> PAGE_SHIFT) & mask;

sys/dev/pci/drm/i915/gt/intel_gtt.h

547

const u64 mask = ~((1ULL << pde_shift) - 1);

sys/dev/pci/drm/i915/gt/intel_gtt.h

555

if ((addr & mask) != (end & mask))

sys/dev/pci/drm/i915/gt/intel_reset.c

1336

return __intel_gt_reset(engine->gt, engine->mask);

sys/dev/pci/drm/i915/gt/intel_reset.c

1530

engine_mask &= ~engine->mask;

sys/dev/pci/drm/i915/gt/intel_reset.c

454

*unlock_mask |= paired_vecs->mask;

sys/dev/pci/drm/i915/gt/intel_reset.c

456

*unlock_mask |= engine->mask;

sys/dev/pci/drm/i915/gt/intel_reset.c

564

u32 request, mask, ack;

sys/dev/pci/drm/i915/gt/intel_reset.c

577

mask = RESET_CTL_CAT_ERROR;

sys/dev/pci/drm/i915/gt/intel_reset.c

583

mask = RESET_CTL_READY_TO_RESET;

sys/dev/pci/drm/i915/gt/intel_reset.c

590

ret = __intel_wait_for_register_fw(uncore, reg, mask, ack,

sys/dev/pci/drm/i915/gt/intel_reset.c

664

intel_engine_mask_t mask,

sys/dev/pci/drm/i915/gt/intel_reset.c

905

awake |= engine->mask;

sys/dev/pci/drm/i915/gt/intel_reset.c

933

__intel_engine_reset(engine, stalled_mask & engine->mask);

sys/dev/pci/drm/i915/gt/intel_reset.c

959

if (awake & engine->mask)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

37

static void set_hwstam(struct intel_engine_cs *engine, u32 mask)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

45

mask &= ~BIT(0);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

47

mask &= ~I915_USER_INTERRUPT;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

50

intel_engine_set_hwsp_writemask(engine, mask);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

673

intel_gt_handle_error(engine->gt, engine->mask, 0,

sys/dev/pci/drm/i915/gt/intel_rps.c

176

u32 mask = 0;

sys/dev/pci/drm/i915/gt/intel_rps.c

180

mask |= (GEN6_PM_RP_UP_EI_EXPIRED |

sys/dev/pci/drm/i915/gt/intel_rps.c

185

mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;

sys/dev/pci/drm/i915/gt/intel_rps.c

187

mask &= rps->pm_events;

sys/dev/pci/drm/i915/gt/intel_rps.c

189

return rps_pm_sanitize_mask(rps, ~mask);

sys/dev/pci/drm/i915/gt/intel_rps.c

2729

i915_reg_t reg32, u32 mask)

sys/dev/pci/drm/i915/gt/intel_rps.c

2731

return rps_read_mmio(rps, reg32) & mask;

sys/dev/pci/drm/i915/gt/intel_rps.c

70

static u32 rps_pm_sanitize_mask(struct intel_rps *rps, u32 mask)

sys/dev/pci/drm/i915/gt/intel_rps.c

72

return mask & ~rps->pm_intrmsk_mbz;

sys/dev/pci/drm/i915/gt/intel_rps.h

63

bool rps_read_mask_mmio(struct intel_rps *rps, i915_reg_t reg32, u32 mask);

sys/dev/pci/drm/i915/gt/intel_sseu.c

107

u16 mask = sseu_get_eus(sseu, s, ss);

sys/dev/pci/drm/i915/gt/intel_sseu.c

111

(mask >> (BITS_PER_BYTE * i)) & 0xff;

sys/dev/pci/drm/i915/gt/intel_sseu.c

719

u32 mask, val = slices;

sys/dev/pci/drm/i915/gt/intel_sseu.c

722

mask = GEN11_RPCS_S_CNT_MASK;

sys/dev/pci/drm/i915/gt/intel_sseu.c

725

mask = GEN8_RPCS_S_CNT_MASK;

sys/dev/pci/drm/i915/gt/intel_sseu.c

729

GEM_BUG_ON(val & ~mask);

sys/dev/pci/drm/i915/gt/intel_sseu.c

730

val &= mask;

sys/dev/pci/drm/i915/gt/intel_sseu.h

66

#define XEHP_BITMAP_BITS(mask) ((int)BITS_PER_TYPE(typeof(mask.xehp)))

sys/dev/pci/drm/i915/gt/intel_tlb.c

80

awake |= engine->mask;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

324

u32 mask, u32 val)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

326

wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

331

u32 mask, u32 val)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

333

wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);

sys/dev/pci/drm/i915/gt/mock_engine.c

360

engine->base.mask = BIT(id);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3948

request[n]->execution_mask = siblings[nsibling - n - 1]->mask;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4257

rq->execution_mask = engine->mask;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1286

static u32 fake_hangcheck(struct intel_gt *gt, intel_engine_mask_t mask)

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1290

intel_gt_reset(gt, mask, NULL);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1556

fake_hangcheck(gt, rq->engine->mask);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1859

intel_gt_handle_error(gt, engine->mask, 0, NULL);

sys/dev/pci/drm/i915/gt/selftest_mocs.c

378

intel_gt_reset(gt, ce->engine->mask, "mocs");

sys/dev/pci/drm/i915/gt/selftest_reset.c

113

if (mask == ALL_ENGINES) {

sys/dev/pci/drm/i915/gt/selftest_reset.c

114

intel_gt_reset(gt, mask, NULL);

sys/dev/pci/drm/i915/gt/selftest_reset.c

117

if (mask & engine->mask)

sys/dev/pci/drm/i915/gt/selftest_reset.c

19

intel_engine_mask_t mask,

sys/dev/pci/drm/i915/gt/selftest_reset.c

201

err = __igt_reset_stolen(gt, engine->mask, engine->name);

sys/dev/pci/drm/i915/gt/selftest_reset.c

62

if (!(mask & engine->mask))

sys/dev/pci/drm/i915/gt/selftest_timeline.c

413

unsigned int mask = BIT(order) - 1;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

425

u64 id = (u64)(count & mask) << order;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

253

intel_gt_reset(engine->gt, engine->mask, "live_workarounds");

sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h

91

u32 mask;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc.c

100

intel_engine_mask_t mask;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc.c

111

mask = INTEL_INFO(gt->i915)->platform_engine_mask;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc.c

113

mask = gt->info.engine_mask;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc.c

115

return __HAS_ENGINE(mask, GSC0);

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

498

static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask)

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

501

guc->msg_enabled_mask |= mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

505

static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask)

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

508

guc->msg_enabled_mask &= ~mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

684

u32 mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

688

mask = info_map_read(info_map, engine_enabled_masks[GUC_RENDER_CLASS]);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

689

mask |= info_map_read(info_map, engine_enabled_masks[GUC_COMPUTE_CLASS]);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

693

mask = info_map_read(info_map, engine_enabled_masks[GUC_VIDEO_CLASS]);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

697

mask = info_map_read(info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS]);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

701

mask = info_map_read(info_map, engine_enabled_masks[GUC_BLITTER_CLASS]);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

705

mask = info_map_read(info_map, engine_enabled_masks[GUC_GSC_OTHER_CLASS]);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

709

mask = 0;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

712

return mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

432

ptr[i].mask = match->list[i].mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

443

ptr[i].mask = matchext->extlist[j].mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

877

read += guc_capture_log_remove_dw(guc, buf, &reg->mask);

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

380

u32 mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1756

intel_engine_mask_t tmp, mask = ve->mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1759

for_each_engine_masked(engine, ve->gt, mask, tmp)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1895

guilty = stalled & ce->engine->mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2803

GEM_BUG_ON(!engine->mask);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2870

GEM_BUG_ON(!engine->mask);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4002

intel_engine_mask_t tmp, mask = ce->engine->mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4005

for_each_engine_masked(engine, ce->engine->gt, mask, tmp)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4013

intel_engine_mask_t tmp, mask = ce->engine->mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4023

for_each_engine_masked(engine, ce->engine->gt, mask, tmp)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4029

intel_engine_mask_t tmp, mask = ce->engine->mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4032

for_each_engine_masked(engine, ce->engine->gt, mask, tmp)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4040

intel_engine_mask_t tmp, mask = ce->engine->mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4043

for_each_engine_masked(engine, ce->engine->gt, mask, tmp)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4281

intel_engine_mask_t tmp, mask = b->engine_mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4284

for_each_engine_masked(sibling, b->irq_engine->gt, mask, tmp)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4294

intel_engine_mask_t tmp, mask = b->engine_mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4296

for_each_engine_masked(sibling, b->irq_engine->gt, mask, tmp)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4327

engine->breadcrumbs->engine_mask |= engine->mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4532

intel_engine_mask_t tmp, mask = engine->mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4534

for_each_engine_masked(e, engine->gt, mask, tmp)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5192

intel_engine_mask_t tmp, virtual_mask = ce->engine->mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5200

engine_mask |= e->mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5213

engine_mask = ce->engine->mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5225

__guc_reset_context(ce, ce->engine->mask);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5378

guc->submission_state.reset_fail_mask |= engine->mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5415

if (!(ce->engine->mask & engine->mask))

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5474

if (!(ce->engine->mask & engine->mask))

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5941

ve->base.mask = VIRTUAL_ENGINES;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5948

GEM_BUG_ON(!is_power_of_2(sibling->mask));

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5949

if (sibling->mask & ve->base.mask) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5956

ve->base.mask |= sibling->mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

6005

intel_engine_mask_t tmp, mask = ve->mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

6007

for_each_engine_masked(engine, ve->gt, mask, tmp)

sys/dev/pci/drm/i915/gt/uc/intel_huc.c

272

intel_engine_mask_t mask = gt->info.engine_mask;

sys/dev/pci/drm/i915/gt/uc/intel_huc.c

286

mask = INTEL_INFO(gt->i915)->platform_engine_mask;

sys/dev/pci/drm/i915/gt/uc/intel_huc.c

288

mask = gt->info.engine_mask;

sys/dev/pci/drm/i915/gt/uc/intel_huc.c

290

return __ENGINE_INSTANCES_MASK(mask, VCS0, I915_MAX_VCS);

sys/dev/pci/drm/i915/gt/uc/intel_huc.c

316

huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_LOAD_SUCCESSFUL;

sys/dev/pci/drm/i915/gt/uc/intel_huc.c

320

huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_FW_VERIFIED;

sys/dev/pci/drm/i915/gt/uc/intel_huc.c

326

huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HUC_LOAD_SUCCESSFUL;

sys/dev/pci/drm/i915/gt/uc/intel_huc.c

330

huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HECI1_FWSTS5_HUC_AUTH_DONE;

sys/dev/pci/drm/i915/gt/uc/intel_huc.c

489

huc->status[type].mask,

sys/dev/pci/drm/i915/gt/uc/intel_huc.c

600

return (status & huc->status[type].mask) == huc->status[type].value;

sys/dev/pci/drm/i915/gt/uc/intel_huc.h

39

u32 mask;

sys/dev/pci/drm/i915/gt/uc/intel_uc.c

370

u32 mask;

sys/dev/pci/drm/i915/gt/uc/intel_uc.c

388

mask = GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED;

sys/dev/pci/drm/i915/gt/uc/intel_uc.c

389

err = intel_uncore_write_and_verify(uncore, GUC_WOPCM_SIZE, size, mask,

sys/dev/pci/drm/i915/gt/uc/intel_uc.c

394

mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;

sys/dev/pci/drm/i915/gt/uc/intel_uc.c

396

base | huc_agent, mask,

sys/dev/pci/drm/i915/gvt/cfg_space.c

73

u8 mask, new, old;

sys/dev/pci/drm/i915/gvt/cfg_space.c

78

mask = pci_cfg_space_rw_bmp[off + i];

sys/dev/pci/drm/i915/gvt/cfg_space.c

80

new = src[i] & mask;

sys/dev/pci/drm/i915/gvt/cfg_space.c

88

new = (~new & old) & mask;

sys/dev/pci/drm/i915/gvt/cfg_space.c

90

cfg_base[off + i] = (old & ~mask) | new;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1803

!(s->vgpu->scan_nonprivbb & s->engine->mask))

sys/dev/pci/drm/i915/gvt/cmd_parser.c

2866

if (bypass_scan_mask & workload->engine->mask || gma_head == gma_tail)

sys/dev/pci/drm/i915/gvt/cmd_parser.c

675

e->info->rings & engine->mask)

sys/dev/pci/drm/i915/gvt/execlist.c

406

if (workload->status || vgpu->resetting_eng & workload->engine->mask)

sys/dev/pci/drm/i915/gvt/execlist.h

92

u32 mask :16;

sys/dev/pci/drm/i915/gvt/handlers.c

2084

engine->mask,

sys/dev/pci/drm/i915/gvt/handlers.c

3116

u32 mask, old_vreg;

sys/dev/pci/drm/i915/gvt/handlers.c

3120

mask = vgpu_vreg(vgpu, offset) >> 16;

sys/dev/pci/drm/i915/gvt/handlers.c

3121

vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) |

sys/dev/pci/drm/i915/gvt/handlers.c

3122

(vgpu_vreg(vgpu, offset) & mask);

sys/dev/pci/drm/i915/gvt/handlers.c

3197

u32 mask = vgpu_vreg(vgpu, offset) >> 16;

sys/dev/pci/drm/i915/gvt/handlers.c

3199

vgpu_vreg(vgpu, offset) = (old_vreg & ~mask)

sys/dev/pci/drm/i915/gvt/handlers.c

3200

| (vgpu_vreg(vgpu, offset) & mask);

sys/dev/pci/drm/i915/gvt/mmio_context.c

239

*cs++ = vgpu_vreg_t(vgpu, mmio->reg) | (mmio->mask << 16);

sys/dev/pci/drm/i915/gvt/mmio_context.c

511

if (mmio->mask)

sys/dev/pci/drm/i915/gvt/mmio_context.c

513

~(mmio->mask << 16);

sys/dev/pci/drm/i915/gvt/mmio_context.c

53

u32 mask;

sys/dev/pci/drm/i915/gvt/mmio_context.c

532

if (mmio->mask)

sys/dev/pci/drm/i915/gvt/mmio_context.c

534

(mmio->mask << 16);

sys/dev/pci/drm/i915/gvt/mmio_context.c

540

if (mmio->mask)

sys/dev/pci/drm/i915/gvt/mmio_context.c

541

new_v = mmio->value | (mmio->mask << 16);

sys/dev/pci/drm/i915/i915_active.c

857

intel_engine_mask_t tmp, mask = engine->mask;

sys/dev/pci/drm/i915/i915_active.c

873

GEM_BUG_ON(!mask);

sys/dev/pci/drm/i915/i915_active.c

874

for_each_engine_masked(engine, gt, mask, tmp) {

sys/dev/pci/drm/i915/i915_cmd_parser.c

1085

if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0)

sys/dev/pci/drm/i915/i915_cmd_parser.c

1106

u32 mask;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1108

if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0)

sys/dev/pci/drm/i915/i915_cmd_parser.c

1115

mask = engine->get_cmd_length_mask(cmd_header);

sys/dev/pci/drm/i915/i915_cmd_parser.c

1116

if (!mask)

sys/dev/pci/drm/i915/i915_cmd_parser.c

1120

default_desc->cmd.mask = ~0u << MIN_OPCODE_SHIFT;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1121

default_desc->length.mask = mask;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1244

return desc->cmd.value == (cmd & desc->cmd.mask);

sys/dev/pci/drm/i915/i915_cmd_parser.c

1270

const u32 reg_addr = cmd[offset] & desc->reg.mask;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1284

if (reg->mask) {

sys/dev/pci/drm/i915/i915_cmd_parser.c

129

u32 mask;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1299

(cmd[offset + 1] & reg->mask) != reg->value)) {

sys/dev/pci/drm/i915/i915_cmd_parser.c

1314

if (desc->bits[i].mask == 0)

sys/dev/pci/drm/i915/i915_cmd_parser.c

1334

desc->bits[i].mask;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1339

desc->bits[i].mask,

sys/dev/pci/drm/i915/i915_cmd_parser.c

141

u32 mask;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1504

length = (*cmd & desc->length.mask) + LENGTH_BIAS;

sys/dev/pci/drm/i915/i915_cmd_parser.c

155

u32 mask;

sys/dev/pci/drm/i915/i915_cmd_parser.c

173

u32 mask;

sys/dev/pci/drm/i915/i915_cmd_parser.c

229

.reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ),

sys/dev/pci/drm/i915/i915_cmd_parser.c

231

.reg = { .offset = 1, .mask = 0x007FFFFC },

sys/dev/pci/drm/i915/i915_cmd_parser.c

234

.mask = MI_GLOBAL_GTT,

sys/dev/pci/drm/i915/i915_cmd_parser.c

238

.reg = { .offset = 1, .mask = 0x007FFFFC },

sys/dev/pci/drm/i915/i915_cmd_parser.c

241

.mask = MI_GLOBAL_GTT,

sys/dev/pci/drm/i915/i915_cmd_parser.c

264

.mask = MI_GLOBAL_GTT,

sys/dev/pci/drm/i915/i915_cmd_parser.c

271

.mask = MI_GLOBAL_GTT,

sys/dev/pci/drm/i915/i915_cmd_parser.c

277

.mask = MI_REPORT_PERF_COUNT_GGTT,

sys/dev/pci/drm/i915/i915_cmd_parser.c

283

.mask = MI_GLOBAL_GTT,

sys/dev/pci/drm/i915/i915_cmd_parser.c

291

.mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK,

sys/dev/pci/drm/i915/i915_cmd_parser.c

300

.mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY),

sys/dev/pci/drm/i915/i915_cmd_parser.c

305

.mask = (PIPE_CONTROL_GLOBAL_GTT_IVB |

sys/dev/pci/drm/i915/i915_cmd_parser.c

322

.reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ),

sys/dev/pci/drm/i915/i915_cmd_parser.c

342

.mask = MI_GLOBAL_GTT,

sys/dev/pci/drm/i915/i915_cmd_parser.c

349

.mask = MI_FLUSH_DW_NOTIFY,

sys/dev/pci/drm/i915/i915_cmd_parser.c

354

.mask = MI_FLUSH_DW_USE_GTT,

sys/dev/pci/drm/i915/i915_cmd_parser.c

361

.mask = MI_FLUSH_DW_STORE_INDEX,

sys/dev/pci/drm/i915/i915_cmd_parser.c

369

.mask = MI_GLOBAL_GTT,

sys/dev/pci/drm/i915/i915_cmd_parser.c

386

.mask = MI_GLOBAL_GTT,

sys/dev/pci/drm/i915/i915_cmd_parser.c

393

.mask = MI_FLUSH_DW_NOTIFY,

sys/dev/pci/drm/i915/i915_cmd_parser.c

398

.mask = MI_FLUSH_DW_USE_GTT,

sys/dev/pci/drm/i915/i915_cmd_parser.c

405

.mask = MI_FLUSH_DW_STORE_INDEX,

sys/dev/pci/drm/i915/i915_cmd_parser.c

413

.mask = MI_GLOBAL_GTT,

sys/dev/pci/drm/i915/i915_cmd_parser.c

423

.mask = MI_GLOBAL_GTT,

sys/dev/pci/drm/i915/i915_cmd_parser.c

430

.mask = MI_FLUSH_DW_NOTIFY,

sys/dev/pci/drm/i915/i915_cmd_parser.c

435

.mask = MI_FLUSH_DW_USE_GTT,

sys/dev/pci/drm/i915/i915_cmd_parser.c

442

.mask = MI_FLUSH_DW_STORE_INDEX,

sys/dev/pci/drm/i915/i915_cmd_parser.c

486

.reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ),

sys/dev/pci/drm/i915/i915_cmd_parser.c

489

.reg = { .offset = 1, .mask = 0x007FFFFC } ),

sys/dev/pci/drm/i915/i915_cmd_parser.c

492

.reg = { .offset = 1, .mask = 0x007FFFFC } ),

sys/dev/pci/drm/i915/i915_cmd_parser.c

494

.reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ),

sys/dev/pci/drm/i915/i915_cmd_parser.c

505

.mask = MI_BB_START_OPERAND_MASK,

sys/dev/pci/drm/i915/i915_cmd_parser.c

576

u32 mask;

sys/dev/pci/drm/i915/i915_cmd_parser.c

668

.mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,

sys/dev/pci/drm/i915/i915_cmd_parser.c

671

.mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 |

sys/dev/pci/drm/i915/i915_cmd_parser.c

820

u32 curr = desc->cmd.value & desc->cmd.mask;

sys/dev/pci/drm/i915/i915_drv.h

509

const u32 mask = info->platform_mask[pi];

sys/dev/pci/drm/i915/i915_drv.h

518

return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);

sys/dev/pci/drm/i915/i915_gpu_error.c

1821

ee->hung = engine->mask & engine_mask;

sys/dev/pci/drm/i915/i915_irq.h

28

void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);

sys/dev/pci/drm/i915/i915_irq.h

29

void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);

sys/dev/pci/drm/i915/i915_irq.h

35

u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915, u32 mask);

sys/dev/pci/drm/i915/i915_perf.c

1056

u32 mask = (OA_BUFFER_SIZE - 1);

sys/dev/pci/drm/i915/i915_perf.c

1088

head = (head + report_size) & mask) {

sys/dev/pci/drm/i915/i915_perf.c

1427

u32 ctx_id, mask;

sys/dev/pci/drm/i915/i915_perf.c

1435

mask = ((1U << GEN12_GUC_SW_CTX_ID_WIDTH) - 1) <<

sys/dev/pci/drm/i915/i915_perf.c

1441

mask = ((1U << XEHP_SW_CTX_ID_WIDTH) - 1) <<

sys/dev/pci/drm/i915/i915_perf.c

1447

mask = ((1U << GEN11_SW_CTX_ID_WIDTH) - 1) <<

sys/dev/pci/drm/i915/i915_perf.c

1450

stream->specific_ctx_id = ctx_id & mask;

sys/dev/pci/drm/i915/i915_perf.c

1451

stream->specific_ctx_id_mask = mask;

sys/dev/pci/drm/i915/i915_perf.c

746

u32 mask = (OA_BUFFER_SIZE - 1);

sys/dev/pci/drm/i915/i915_perf.c

778

head = (head + report_size) & mask) {

sys/dev/pci/drm/i915/i915_pmu.c

140

u32 mask = 0;

sys/dev/pci/drm/i915/i915_pmu.c

143

mask |= config_mask(__I915_PMU_ACTUAL_FREQUENCY(i)) |

sys/dev/pci/drm/i915/i915_pmu.c

146

return mask;

sys/dev/pci/drm/i915/i915_reg_defs.h

108

#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))

sys/dev/pci/drm/i915/i915_reg_defs.h

109

#define _MASKED_FIELD(mask, value) ({ \

sys/dev/pci/drm/i915/i915_reg_defs.h

110

if (__builtin_constant_p(mask)) \

sys/dev/pci/drm/i915/i915_reg_defs.h

111

BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \

sys/dev/pci/drm/i915/i915_reg_defs.h

114

if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \

sys/dev/pci/drm/i915/i915_reg_defs.h

115

BUILD_BUG_ON_MSG((value) & ~(mask), \

sys/dev/pci/drm/i915/i915_reg_defs.h

117

__MASKED_FIELD(mask, value); })

sys/dev/pci/drm/i915/i915_request.c

1028

rq->execution_mask = ce->engine->mask;

sys/dev/pci/drm/i915/i915_request.c

1288

const intel_engine_mask_t mask = READ_ONCE(from->engine)->mask;

sys/dev/pci/drm/i915/i915_request.c

1310

if (already_busywaiting(to) & mask)

sys/dev/pci/drm/i915/i915_request.c

1323

to->sched.semaphores |= mask;

sys/dev/pci/drm/i915/i915_request.c

1766

bool pow2 = is_power_of_2(READ_ONCE(prev->engine)->mask |

sys/dev/pci/drm/i915/i915_request.c

1767

rq->engine->mask);

sys/dev/pci/drm/i915/i915_utils.h

92

#define __mask_next_bit(mask) ({ \

sys/dev/pci/drm/i915/i915_utils.h

93

int __idx = ffs(mask) - 1; \

sys/dev/pci/drm/i915/i915_utils.h

94

mask &= ~BIT(__idx); \

sys/dev/pci/drm/i915/intel_device_info.c

236

u32 mask = 0;

sys/dev/pci/drm/i915/intel_device_info.c

244

mask = BIT(INTEL_SUBPLATFORM_ULT);

sys/dev/pci/drm/i915/intel_device_info.c

247

mask = BIT(INTEL_SUBPLATFORM_ULX);

sys/dev/pci/drm/i915/intel_device_info.c

250

mask |= BIT(INTEL_SUBPLATFORM_ULT);

sys/dev/pci/drm/i915/intel_device_info.c

254

mask = BIT(INTEL_SUBPLATFORM_PORTF);

sys/dev/pci/drm/i915/intel_device_info.c

257

mask = BIT(INTEL_SUBPLATFORM_UY);

sys/dev/pci/drm/i915/intel_device_info.c

260

mask = BIT(INTEL_SUBPLATFORM_N);

sys/dev/pci/drm/i915/intel_device_info.c

263

mask = BIT(INTEL_SUBPLATFORM_RPL);

sys/dev/pci/drm/i915/intel_device_info.c

266

mask |= BIT(INTEL_SUBPLATFORM_RPLU);

sys/dev/pci/drm/i915/intel_device_info.c

269

mask = BIT(INTEL_SUBPLATFORM_G10);

sys/dev/pci/drm/i915/intel_device_info.c

272

mask = BIT(INTEL_SUBPLATFORM_G11);

sys/dev/pci/drm/i915/intel_device_info.c

275

mask = BIT(INTEL_SUBPLATFORM_G12);

sys/dev/pci/drm/i915/intel_device_info.c

278

mask = BIT(INTEL_SUBPLATFORM_ARL_H);

sys/dev/pci/drm/i915/intel_device_info.c

281

mask = BIT(INTEL_SUBPLATFORM_ARL_U);

sys/dev/pci/drm/i915/intel_device_info.c

284

mask = BIT(INTEL_SUBPLATFORM_ARL_S);

sys/dev/pci/drm/i915/intel_device_info.c

290

mask |= BIT(INTEL_SUBPLATFORM_D);

sys/dev/pci/drm/i915/intel_device_info.c

292

GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);

sys/dev/pci/drm/i915/intel_device_info.c

294

RUNTIME_INFO(i915)->platform_mask[pi] |= mask;

sys/dev/pci/drm/i915/intel_uncore.c

154

GEM_BUG_ON(d->uncore->fw_domains_timer & d->mask);

sys/dev/pci/drm/i915/intel_uncore.c

155

d->uncore->fw_domains_timer |= d->mask;

sys/dev/pci/drm/i915/intel_uncore.c

2140

d->mask = BIT(domain_id);

sys/dev/pci/drm/i915/intel_uncore.c

2769

u32 mask,

sys/dev/pci/drm/i915/intel_uncore.c

2776

#define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value)

sys/dev/pci/drm/i915/intel_uncore.c

2818

u32 mask,

sys/dev/pci/drm/i915/intel_uncore.c

2835

reg, mask, value,

sys/dev/pci/drm/i915/intel_uncore.c

2844

(reg_value & mask) == value,

sys/dev/pci/drm/i915/intel_uncore.c

452

uncore->fw_domains_timer &= ~domain->mask;

sys/dev/pci/drm/i915/intel_uncore.c

456

fw_domains_put(uncore, domain->mask);

sys/dev/pci/drm/i915/intel_uncore.c

479

uncore->fw_domains_timer &= ~domain->mask;

sys/dev/pci/drm/i915/intel_uncore.c

483

fw_domains_put(uncore, domain->mask);

sys/dev/pci/drm/i915/intel_uncore.c

522

active_domains |= domain->mask;

sys/dev/pci/drm/i915/intel_uncore.c

704

fw_domains &= ~domain->mask;

sys/dev/pci/drm/i915/intel_uncore.c

813

!(domain->uncore->fw_domains_timer & domain->mask))

sys/dev/pci/drm/i915/intel_uncore.c

816

fw_domains_put(uncore, domain->mask);

sys/dev/pci/drm/i915/intel_uncore.c

934

if (uncore->fw_domains_timer & domain->mask)

sys/dev/pci/drm/i915/intel_uncore.h

182

enum forcewake_domains mask;

sys/dev/pci/drm/i915/intel_uncore.h

288

u32 mask,

sys/dev/pci/drm/i915/intel_uncore.h

296

u32 mask,

sys/dev/pci/drm/i915/intel_uncore.h

300

return __intel_wait_for_register(uncore, reg, mask, value, 2,

sys/dev/pci/drm/i915/intel_uncore.h

306

u32 mask,

sys/dev/pci/drm/i915/intel_uncore.h

314

u32 mask,

sys/dev/pci/drm/i915/intel_uncore.h

319

return __intel_wait_for_register_fw(uncore, reg, mask, value,

sys/dev/pci/drm/i915/intel_uncore.h

490

u32 mask, u32 expected_val)

sys/dev/pci/drm/i915/intel_uncore.h

497

return (reg_val & mask) != expected_val ? -EINVAL : 0;

sys/dev/pci/drm/i915/pxp/intel_pxp_irq.c

57

const u32 mask = interrupts << 16;

sys/dev/pci/drm/i915/pxp/intel_pxp_irq.c

59

intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, mask);

sys/dev/pci/drm/i915/pxp/intel_pxp_irq.c

60

intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK, ~mask);

sys/dev/pci/drm/i915/pxp/intel_pxp_session.c

35

u32 mask = BIT(id);

sys/dev/pci/drm/i915/pxp/intel_pxp_session.c

45

mask,

sys/dev/pci/drm/i915/pxp/intel_pxp_session.c

46

in_play ? mask : 0,

sys/dev/pci/drm/i915/vlv_suspend.c

282

u32 mask, u32 val)

sys/dev/pci/drm/i915/vlv_suspend.c

296

intel_uncore_read_notrace(&i915->uncore, reg)) & mask)

sys/dev/pci/drm/i915/vlv_suspend.c

332

u32 mask;

sys/dev/pci/drm/i915/vlv_suspend.c

340

mask = VLV_GTLC_ALLOWWAKEACK;

sys/dev/pci/drm/i915/vlv_suspend.c

341

val = allow ? mask : 0;

sys/dev/pci/drm/i915/vlv_suspend.c

343

err = vlv_wait_for_pw_status(i915, mask, val);

sys/dev/pci/drm/i915/vlv_suspend.c

353

u32 mask;

sys/dev/pci/drm/i915/vlv_suspend.c

356

mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;

sys/dev/pci/drm/i915/vlv_suspend.c

357

val = wait_for_on ? mask : 0;

sys/dev/pci/drm/i915/vlv_suspend.c

366

if (vlv_wait_for_pw_status(dev_priv, mask, val))

sys/dev/pci/drm/i915/vlv_suspend.c

385

u32 mask;

sys/dev/pci/drm/i915/vlv_suspend.c

397

mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;

sys/dev/pci/drm/i915/vlv_suspend.c

399

(intel_uncore_read(&dev_priv->uncore, VLV_GTLC_WAKE_CTRL) & mask) != mask);

sys/dev/pci/drm/include/linux/bitops.h

104

fls64(long long mask)

sys/dev/pci/drm/include/linux/bitops.h

108

if (mask == 0)

sys/dev/pci/drm/include/linux/bitops.h

110

for (bit = 1; mask != 1; bit++)

sys/dev/pci/drm/include/linux/bitops.h

111

mask = (unsigned long long)mask >> 1;

sys/dev/pci/drm/include/linux/bitops.h

116

__fls(long mask)

sys/dev/pci/drm/include/linux/bitops.h

118

return (flsl(mask) - 1);

sys/dev/pci/drm/include/linux/radix-tree.h

60

#define RADIX_TREE_INIT(mask) \

sys/dev/pci/drm/include/linux/radix-tree.h

61

{ .rnode = NULL, .gfp_mask = mask, .height = 0 };

sys/dev/pci/drm/include/linux/radix-tree.h

62

#define INIT_RADIX_TREE(root, mask) \

sys/dev/pci/drm/include/linux/radix-tree.h

63

{ (root)->rnode = NULL; (root)->gfp_mask = mask; (root)->height = 0; }

sys/dev/pci/drm/include/linux/radix-tree.h

64

#define RADIX_TREE(name, mask) \

sys/dev/pci/drm/include/linux/radix-tree.h

65

struct radix_tree_root name = RADIX_TREE_INIT(mask)

sys/dev/pci/drm/include/uapi/drm/radeon_drm.h

686

unsigned int __user *mask;

sys/dev/pci/drm/include/uapi/linux/kfd_ioctl.h

1350

__u32 mask;

sys/dev/pci/drm/linux_radix.c

103

if ((index & mask) == 0)

sys/dev/pci/drm/linux_radix.c

91

unsigned long mask = RADIX_TREE_MAP_MASK << (RADIX_TREE_MAP_SHIFT * height);

sys/dev/pci/drm/radeon/atom.c

767

uint32_t dst, mask, src, saved;

sys/dev/pci/drm/radeon/atom.c

771

mask = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr);

sys/dev/pci/drm/radeon/atom.c

772

SDEBUG(" mask: 0x%08x", mask);

sys/dev/pci/drm/radeon/atom.c

775

dst &= mask;

sys/dev/pci/drm/radeon/ci_dpm.c

550

cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);

sys/dev/pci/drm/radeon/ci_dpm.c

564

data &= ~config_regs->mask;

sys/dev/pci/drm/radeon/ci_dpm.c

565

data |= ((config_regs->value << config_regs->shift) & config_regs->mask);

sys/dev/pci/drm/radeon/ci_dpm.h

168

u32 mask;

sys/dev/pci/drm/radeon/cik.c

3052

u32 i, mask = 0;

sys/dev/pci/drm/radeon/cik.c

3055

mask <<= 1;

sys/dev/pci/drm/radeon/cik.c

3056

mask |= 1;

sys/dev/pci/drm/radeon/cik.c

3058

return mask;

sys/dev/pci/drm/radeon/cik.c

3075

u32 data, mask;

sys/dev/pci/drm/radeon/cik.c

3086

mask = cik_create_bitmask(max_rb_num_per_se / sh_per_se);

sys/dev/pci/drm/radeon/cik.c

3088

return data & mask;

sys/dev/pci/drm/radeon/cik.c

3106

u32 data, mask;

sys/dev/pci/drm/radeon/cik.c

3122

mask = 1;

sys/dev/pci/drm/radeon/cik.c

3124

if (!(disabled_rbs & mask))

sys/dev/pci/drm/radeon/cik.c

3125

enabled_rbs |= mask;

sys/dev/pci/drm/radeon/cik.c

3126

mask <<= 1;

sys/dev/pci/drm/radeon/cik.c

5784

u32 mask;

sys/dev/pci/drm/radeon/cik.c

5798

mask = SE_MASTER_BUSY_MASK | GC_MASTER_BUSY | TC0_MASTER_BUSY | TC1_MASTER_BUSY;

sys/dev/pci/drm/radeon/cik.c

5800

if ((RREG32(RLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)

sys/dev/pci/drm/radeon/cik.c

5841

u32 tmp, i, mask;

sys/dev/pci/drm/radeon/cik.c

5846

mask = GFX_POWER_STATUS | GFX_CLOCK_STATUS;

sys/dev/pci/drm/radeon/cik.c

5848

if ((RREG32(RLC_GPM_STAT) & mask) == mask)

sys/dev/pci/drm/radeon/cik.c

6526

u32 mask = 0, tmp, tmp1;

sys/dev/pci/drm/radeon/cik.c

6540

mask <<= 1;

sys/dev/pci/drm/radeon/cik.c

6541

mask |= 1;

sys/dev/pci/drm/radeon/cik.c

6544

return (~tmp) & mask;

sys/dev/pci/drm/radeon/cik.c

6550

u32 mask, counter, cu_bitmap;

sys/dev/pci/drm/radeon/cik.c

6555

mask = 1;

sys/dev/pci/drm/radeon/cik.c

6559

if (cik_get_cu_active_bitmap(rdev, i, j) & mask) {

sys/dev/pci/drm/radeon/cik.c

6561

cu_bitmap |= mask;

sys/dev/pci/drm/radeon/cik.c

6564

mask <<= 1;

sys/dev/pci/drm/radeon/cik_reg.h

230

uint32_t mask:24;

sys/dev/pci/drm/radeon/cik_sdma.c

777

u32 mask;

sys/dev/pci/drm/radeon/cik_sdma.c

780

mask = RADEON_RESET_DMA;

sys/dev/pci/drm/radeon/cik_sdma.c

782

mask = RADEON_RESET_DMA1;

sys/dev/pci/drm/radeon/cik_sdma.c

784

if (!(reset_mask & mask)) {

sys/dev/pci/drm/radeon/evergreen.c

4371

u32 mask = RLC_ENABLE;

sys/dev/pci/drm/radeon/evergreen.c

4374

mask |= GFX_POWER_GATING_ENABLE | GFX_POWER_GATING_SRC;

sys/dev/pci/drm/radeon/evergreen.c

4377

WREG32(RLC_CNTL, mask);

sys/dev/pci/drm/radeon/evergreen.c

4705

u32 mask;

sys/dev/pci/drm/radeon/evergreen.c

4754

mask = LB_D1_VBLANK_INTERRUPT;

sys/dev/pci/drm/radeon/evergreen.c

4768

mask = LB_D1_VLINE_INTERRUPT;

sys/dev/pci/drm/radeon/evergreen.c

4776

if (!(disp_int[crtc_idx] & mask)) {

sys/dev/pci/drm/radeon/evergreen.c

4781

disp_int[crtc_idx] &= ~mask;

sys/dev/pci/drm/radeon/evergreen.c

4798

mask = DC_HPD1_INTERRUPT;

sys/dev/pci/drm/radeon/evergreen.c

4804

mask = DC_HPD1_RX_INTERRUPT;

sys/dev/pci/drm/radeon/evergreen.c

4814

if (!(disp_int[hpd_idx] & mask))

sys/dev/pci/drm/radeon/evergreen.c

4817

disp_int[hpd_idx] &= ~mask;

sys/dev/pci/drm/radeon/kv_dpm.c

1249

u32 mask;

sys/dev/pci/drm/radeon/kv_dpm.c

1258

mask = 1 << pi->uvd_boot_level;

sys/dev/pci/drm/radeon/kv_dpm.c

1260

mask = 0x1f;

sys/dev/pci/drm/radeon/kv_dpm.c

1273

mask);

sys/dev/pci/drm/radeon/kv_dpm.c

169

cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);

sys/dev/pci/drm/radeon/kv_dpm.c

183

data &= ~config_regs->mask;

sys/dev/pci/drm/radeon/kv_dpm.c

184

data |= ((config_regs->value << config_regs->shift) & config_regs->mask);

sys/dev/pci/drm/radeon/kv_dpm.h

46

u32 mask;

sys/dev/pci/drm/radeon/kv_smc.c

122

u32 data, original_data, addr, extra_shift, t_byte, count, mask;

sys/dev/pci/drm/radeon/kv_smc.c

141

mask = 0;

sys/dev/pci/drm/radeon/kv_smc.c

145

mask = (mask << 8) | 0xff;

sys/dev/pci/drm/radeon/kv_smc.c

150

mask <<= 8;

sys/dev/pci/drm/radeon/kv_smc.c

153

mask = (mask << 8) | 0xff;

sys/dev/pci/drm/radeon/kv_smc.c

158

data |= original_data & mask;

sys/dev/pci/drm/radeon/ni_dma.c

289

u32 mask;

sys/dev/pci/drm/radeon/ni_dma.c

292

mask = RADEON_RESET_DMA;

sys/dev/pci/drm/radeon/ni_dma.c

294

mask = RADEON_RESET_DMA1;

sys/dev/pci/drm/radeon/ni_dma.c

296

if (!(reset_mask & mask)) {

sys/dev/pci/drm/radeon/r100.c

373

tmp |= voltage->gpio.mask;

sys/dev/pci/drm/radeon/r100.c

375

tmp &= ~(voltage->gpio.mask);

sys/dev/pci/drm/radeon/r100.c

382

tmp &= ~voltage->gpio.mask;

sys/dev/pci/drm/radeon/r100.c

384

tmp |= voltage->gpio.mask;

sys/dev/pci/drm/radeon/r300.c

503

uint32_t link_width_cntl, mask;

sys/dev/pci/drm/radeon/r300.c

515

mask = RADEON_PCIE_LC_LINK_WIDTH_X0;

sys/dev/pci/drm/radeon/r300.c

518

mask = RADEON_PCIE_LC_LINK_WIDTH_X1;

sys/dev/pci/drm/radeon/r300.c

521

mask = RADEON_PCIE_LC_LINK_WIDTH_X2;

sys/dev/pci/drm/radeon/r300.c

524

mask = RADEON_PCIE_LC_LINK_WIDTH_X4;

sys/dev/pci/drm/radeon/r300.c

527

mask = RADEON_PCIE_LC_LINK_WIDTH_X8;

sys/dev/pci/drm/radeon/r300.c

530

mask = RADEON_PCIE_LC_LINK_WIDTH_X12;

sys/dev/pci/drm/radeon/r300.c

534

mask = RADEON_PCIE_LC_LINK_WIDTH_X16;

sys/dev/pci/drm/radeon/r300.c

541

(mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))

sys/dev/pci/drm/radeon/r300.c

548

link_width_cntl |= mask;

sys/dev/pci/drm/radeon/r600.c

1942

u32 data = 0, mask = 1 << (max_rb_num - 1);

sys/dev/pci/drm/radeon/r600.c

1967

if (!(mask & disabled_rb_mask)) {

sys/dev/pci/drm/radeon/r600.c

1978

mask >>= 1;

sys/dev/pci/drm/radeon/r600.c

4399

u32 link_width_cntl, mask;

sys/dev/pci/drm/radeon/r600.c

4415

mask = RADEON_PCIE_LC_LINK_WIDTH_X0;

sys/dev/pci/drm/radeon/r600.c

4418

mask = RADEON_PCIE_LC_LINK_WIDTH_X1;

sys/dev/pci/drm/radeon/r600.c

4421

mask = RADEON_PCIE_LC_LINK_WIDTH_X2;

sys/dev/pci/drm/radeon/r600.c

4424

mask = RADEON_PCIE_LC_LINK_WIDTH_X4;

sys/dev/pci/drm/radeon/r600.c

4427

mask = RADEON_PCIE_LC_LINK_WIDTH_X8;

sys/dev/pci/drm/radeon/r600.c

4431

mask = RADEON_PCIE_LC_LINK_WIDTH_X12;

sys/dev/pci/drm/radeon/r600.c

4434

mask = RADEON_PCIE_LC_LINK_WIDTH_X16;

sys/dev/pci/drm/radeon/r600.c

4443

link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT;

sys/dev/pci/drm/radeon/r600_dpm.c

520

u64 mask)

sys/dev/pci/drm/radeon/r600_dpm.c

522

WREG32(LOWER_GPIO_ENABLE, mask & 0xffffffff);

sys/dev/pci/drm/radeon/r600_dpm.c

523

WREG32(UPPER_GPIO_ENABLE, upper_32_bits(mask));

sys/dev/pci/drm/radeon/r600_dpm.c

530

u32 tmp, mask;

sys/dev/pci/drm/radeon/r600_dpm.c

535

mask = 7 << (3 * ix);

sys/dev/pci/drm/radeon/r600_dpm.c

537

tmp = (tmp & ~mask) | ((pins >> (32 - (3 * ix))) & mask);

sys/dev/pci/drm/radeon/r600_dpm.c

542

u64 mask)

sys/dev/pci/drm/radeon/r600_dpm.c

547

gpio &= ~mask;

sys/dev/pci/drm/radeon/r600_dpm.c

551

gpio &= ~mask;

sys/dev/pci/drm/radeon/r600_dpm.c

555

gpio &= ~mask;

sys/dev/pci/drm/radeon/r600_dpm.h

191

u64 mask);

sys/dev/pci/drm/radeon/r600_dpm.h

195

u64 mask);

sys/dev/pci/drm/radeon/radeon.h

2580

#define WREG32_P(reg, val, mask) \

sys/dev/pci/drm/radeon/radeon.h

2583

tmp_ &= (mask); \

sys/dev/pci/drm/radeon/radeon.h

2584

tmp_ |= ((val) & ~(mask)); \

sys/dev/pci/drm/radeon/radeon.h

2589

#define WREG32_PLL_P(reg, val, mask) \

sys/dev/pci/drm/radeon/radeon.h

2592

tmp_ &= (mask); \

sys/dev/pci/drm/radeon/radeon.h

2593

tmp_ |= ((val) & ~(mask)); \

sys/dev/pci/drm/radeon/radeon.h

2596

#define WREG32_SMC_P(reg, val, mask) \

sys/dev/pci/drm/radeon/radeon.h

2599

tmp_ &= (mask); \

sys/dev/pci/drm/radeon/radeon.h

2600

tmp_ |= ((val) & ~(mask)); \

sys/dev/pci/drm/radeon/radeon.h

3001

u32 reg, u32 mask,

sys/dev/pci/drm/radeon/radeon_acpi.c

161

static void radeon_atif_parse_notification(struct radeon_atif_notifications *n, u32 mask)

sys/dev/pci/drm/radeon/radeon_acpi.c

163

n->display_switch = mask & ATIF_DISPLAY_SWITCH_REQUEST_SUPPORTED;

sys/dev/pci/drm/radeon/radeon_acpi.c

164

n->expansion_mode_change = mask & ATIF_EXPANSION_MODE_CHANGE_REQUEST_SUPPORTED;

sys/dev/pci/drm/radeon/radeon_acpi.c

165

n->thermal_state = mask & ATIF_THERMAL_STATE_CHANGE_REQUEST_SUPPORTED;

sys/dev/pci/drm/radeon/radeon_acpi.c

166

n->forced_power_state = mask & ATIF_FORCED_POWER_STATE_CHANGE_REQUEST_SUPPORTED;

sys/dev/pci/drm/radeon/radeon_acpi.c

167

n->system_power_state = mask & ATIF_SYSTEM_POWER_SOURCE_CHANGE_REQUEST_SUPPORTED;

sys/dev/pci/drm/radeon/radeon_acpi.c

168

n->display_conf_change = mask & ATIF_DISPLAY_CONF_CHANGE_REQUEST_SUPPORTED;

sys/dev/pci/drm/radeon/radeon_acpi.c

169

n->px_gfx_switch = mask & ATIF_PX_GFX_SWITCH_REQUEST_SUPPORTED;

sys/dev/pci/drm/radeon/radeon_acpi.c

170

n->brightness_change = mask & ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST_SUPPORTED;

sys/dev/pci/drm/radeon/radeon_acpi.c

171

n->dgpu_display_event = mask & ATIF_DGPU_DISPLAY_EVENT_SUPPORTED;

sys/dev/pci/drm/radeon/radeon_acpi.c

184

static void radeon_atif_parse_functions(struct radeon_atif_functions *f, u32 mask)

sys/dev/pci/drm/radeon/radeon_acpi.c

186

f->system_params = mask & ATIF_GET_SYSTEM_PARAMETERS_SUPPORTED;

sys/dev/pci/drm/radeon/radeon_acpi.c

187

f->sbios_requests = mask & ATIF_GET_SYSTEM_BIOS_REQUESTS_SUPPORTED;

sys/dev/pci/drm/radeon/radeon_acpi.c

188

f->select_active_disp = mask & ATIF_SELECT_ACTIVE_DISPLAYS_SUPPORTED;

sys/dev/pci/drm/radeon/radeon_acpi.c

189

f->lid_state = mask & ATIF_GET_LID_STATE_SUPPORTED;

sys/dev/pci/drm/radeon/radeon_acpi.c

190

f->get_tv_standard = mask & ATIF_GET_TV_STANDARD_FROM_CMOS_SUPPORTED;

sys/dev/pci/drm/radeon/radeon_acpi.c

191

f->set_tv_standard = mask & ATIF_SET_TV_STANDARD_IN_CMOS_SUPPORTED;

sys/dev/pci/drm/radeon/radeon_acpi.c

192

f->get_panel_expansion_mode = mask & ATIF_GET_PANEL_EXPANSION_MODE_FROM_CMOS_SUPPORTED;

sys/dev/pci/drm/radeon/radeon_acpi.c

193

f->set_panel_expansion_mode = mask & ATIF_SET_PANEL_EXPANSION_MODE_IN_CMOS_SUPPORTED;

sys/dev/pci/drm/radeon/radeon_acpi.c

194

f->temperature_change = mask & ATIF_TEMPERATURE_CHANGE_NOTIFICATION_SUPPORTED;

sys/dev/pci/drm/radeon/radeon_acpi.c

195

f->graphics_device_types = mask & ATIF_GET_GRAPHICS_DEVICE_TYPES_SUPPORTED;

sys/dev/pci/drm/radeon/radeon_acpi.c

484

static void radeon_atcs_parse_functions(struct radeon_atcs_functions *f, u32 mask)

sys/dev/pci/drm/radeon/radeon_acpi.c

486

f->get_ext_state = mask & ATCS_GET_EXTERNAL_STATE_SUPPORTED;

sys/dev/pci/drm/radeon/radeon_acpi.c

487

f->pcie_perf_req = mask & ATCS_PCIE_PERFORMANCE_REQUEST_SUPPORTED;

sys/dev/pci/drm/radeon/radeon_acpi.c

488

f->pcie_dev_rdy = mask & ATCS_PCIE_DEVICE_READY_NOTIFICATION_SUPPORTED;

sys/dev/pci/drm/radeon/radeon_acpi.c

489

f->pcie_bus_width = mask & ATCS_SET_PCIE_BUS_WIDTH_SUPPORTED;

sys/dev/pci/drm/radeon/radeon_atombios.c

224

gpio.mask = (1 << pin->ucGpioPinBitShift);

sys/dev/pci/drm/radeon/radeon_atombios.c

253

switch(gpio->mask) {

sys/dev/pci/drm/radeon/radeon_bios.c

152

pcireg_t address, mask;

sys/dev/pci/drm/radeon/radeon_bios.c

161

mask = pci_conf_read(rdev->pc, rdev->pa_tag, PCI_ROM_REG);

sys/dev/pci/drm/radeon/radeon_bios.c

165

size = PCI_ROM_SIZE(mask);

sys/dev/pci/drm/radeon/radeon_combios.c

2759

rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);

sys/dev/pci/drm/radeon/radeon_combios.c

2767

rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);

sys/dev/pci/drm/radeon/radeon_drv.c

1073

mask = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG);

sys/dev/pci/drm/radeon/radeon_drv.c

1077

if (addr == 0 && PCI_ROM_SIZE(mask) != 0 && pa->pa_memex) {

sys/dev/pci/drm/radeon/radeon_drv.c

1081

size = PCI_ROM_SIZE(mask);

sys/dev/pci/drm/radeon/radeon_drv.c

957

pcireg_t addr, mask;

sys/dev/pci/drm/radeon/radeon_irq_kms.c

608

u32 reg, u32 mask,

sys/dev/pci/drm/radeon/radeon_irq_kms.c

614

if (!!(tmp & mask) == enable)

sys/dev/pci/drm/radeon/radeon_irq_kms.c

619

WREG32(reg, tmp |= mask);

sys/dev/pci/drm/radeon/radeon_irq_kms.c

622

WREG32(reg, tmp & ~mask);

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

303

uint32_t mask;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

306

mask = (RADEON_CRTC2_DISP_DIS |

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

311

mask = (RADEON_CRTC_DISPLAY_DIS |

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

331

WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

335

WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl));

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

347

WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

351

WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl));

sys/dev/pci/drm/radeon/radeon_mode.h

481

u32 mask;

sys/dev/pci/drm/radeon/radeon_uvd.c

1026

uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;

sys/dev/pci/drm/radeon/radeon_uvd.c

1027

if ((RREG32(cg_upll_func_cntl) & mask) == mask)

sys/dev/pci/drm/radeon/radeon_vm.c

818

uint64_t mask = RADEON_VM_PTE_COUNT - 1;

sys/dev/pci/drm/radeon/radeon_vm.c

836

if ((addr & ~mask) == (end & ~mask))

sys/dev/pci/drm/radeon/radeon_vm.c

839

nptes = RADEON_VM_PTE_COUNT - (addr & mask);

sys/dev/pci/drm/radeon/radeon_vm.c

842

pte += (addr & mask) * 8;

sys/dev/pci/drm/radeon/rs600.c

240

tmp |= voltage->gpio.mask;

sys/dev/pci/drm/radeon/rs600.c

242

tmp &= ~(voltage->gpio.mask);

sys/dev/pci/drm/radeon/rs600.c

249

tmp &= ~voltage->gpio.mask;

sys/dev/pci/drm/radeon/rs600.c

251

tmp |= voltage->gpio.mask;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

704

u32 mask, set_pins;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

709

&set_pins, &mask);

sys/dev/pci/drm/radeon/si.c

2945

u32 i, mask = 0;

sys/dev/pci/drm/radeon/si.c

2948

mask <<= 1;

sys/dev/pci/drm/radeon/si.c

2949

mask |= 1;

sys/dev/pci/drm/radeon/si.c

2951

return mask;

sys/dev/pci/drm/radeon/si.c

2956

u32 data, mask;

sys/dev/pci/drm/radeon/si.c

2967

mask = si_create_bitmask(cu_per_sh);

sys/dev/pci/drm/radeon/si.c

2969

return ~data & mask;

sys/dev/pci/drm/radeon/si.c

2977

u32 data, mask, active_cu;

sys/dev/pci/drm/radeon/si.c

2985

mask = 1;

sys/dev/pci/drm/radeon/si.c

2987

mask <<= k;

sys/dev/pci/drm/radeon/si.c

2988

if (active_cu & mask) {

sys/dev/pci/drm/radeon/si.c

2989

data &= ~mask;

sys/dev/pci/drm/radeon/si.c

3003

u32 data, mask;

sys/dev/pci/drm/radeon/si.c

3014

mask = si_create_bitmask(max_rb_num_per_se / sh_per_se);

sys/dev/pci/drm/radeon/si.c

3016

return data & mask;

sys/dev/pci/drm/radeon/si.c

3024

u32 data, mask;

sys/dev/pci/drm/radeon/si.c

3037

mask = 1;

sys/dev/pci/drm/radeon/si.c

3039

if (!(disabled_rbs & mask))

sys/dev/pci/drm/radeon/si.c

3040

enabled_rbs |= mask;

sys/dev/pci/drm/radeon/si.c

3041

mask <<= 1;

sys/dev/pci/drm/radeon/si.c

5129

u32 mask;

sys/dev/pci/drm/radeon/si.c

5142

mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;

sys/dev/pci/drm/radeon/si.c

5144

if ((RREG32(RLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))

sys/dev/pci/drm/radeon/si.c

5281

u32 mask = 0, tmp, tmp1;

sys/dev/pci/drm/radeon/si.c

5295

mask <<= 1;

sys/dev/pci/drm/radeon/si.c

5296

mask |= 1;

sys/dev/pci/drm/radeon/si.c

5299

return (~tmp) & mask;

sys/dev/pci/drm/radeon/si.c

5305

u32 mask, counter, cu_bitmap;

sys/dev/pci/drm/radeon/si.c

5310

mask = 1;

sys/dev/pci/drm/radeon/si.c

5314

if (si_get_cu_active_bitmap(rdev, i, j) & mask) {

sys/dev/pci/drm/radeon/si.c

5316

cu_bitmap |= mask;

sys/dev/pci/drm/radeon/si.c

5319

mask <<= 1;

sys/dev/pci/drm/radeon/si.c

6229

u32 mask;

sys/dev/pci/drm/radeon/si.c

6278

mask = LB_D1_VBLANK_INTERRUPT;

sys/dev/pci/drm/radeon/si.c

6292

mask = LB_D1_VLINE_INTERRUPT;

sys/dev/pci/drm/radeon/si.c

6300

if (!(disp_int[crtc_idx] & mask)) {

sys/dev/pci/drm/radeon/si.c

6305

disp_int[crtc_idx] &= ~mask;

sys/dev/pci/drm/radeon/si.c

6322

mask = DC_HPD1_INTERRUPT;

sys/dev/pci/drm/radeon/si.c

6328

mask = DC_HPD1_RX_INTERRUPT;

sys/dev/pci/drm/radeon/si.c

6338

if (!(disp_int[hpd_idx] & mask))

sys/dev/pci/drm/radeon/si.c

6341

disp_int[hpd_idx] &= ~mask;

sys/dev/pci/drm/radeon/si.c

7445

uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;

sys/dev/pci/drm/radeon/si.c

7446

if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask)

sys/dev/pci/drm/radeon/si_dma.c

43

u32 mask;

sys/dev/pci/drm/radeon/si_dma.c

46

mask = RADEON_RESET_DMA;

sys/dev/pci/drm/radeon/si_dma.c

48

mask = RADEON_RESET_DMA1;

sys/dev/pci/drm/radeon/si_dma.c

50

if (!(reset_mask & mask)) {

sys/dev/pci/drm/radeon/si_dpm.c

2693

data &= ~config_regs->mask;

sys/dev/pci/drm/radeon/si_dpm.c

2694

data |= ((config_regs->value << config_regs->shift) & config_regs->mask);

sys/dev/pci/drm/radeon/si_dpm.h

37

u32 mask;

sys/dev/pci/drm/radeon/sumo_smc.c

167

u32 mask = 0xFFF;

sys/dev/pci/drm/radeon/sumo_smc.c

200

sclk_dpm_tdp_limit &= ~(mask << shift);

sys/dev/pci/eap.c

1108

m = sc->sc_record_source = cp->un.mask;

sys/dev/pci/eap.c

1131

m = sc->sc_input_source = cp->un.mask;

sys/dev/pci/eap.c

1223

cp->un.mask = sc->sc_record_source;

sys/dev/pci/eap.c

1228

cp->un.mask = sc->sc_input_source;

sys/dev/pci/eap.c

1363

dip->un.s.member[0].mask = 1 << EAP_MIC_VOL;

sys/dev/pci/eap.c

1366

dip->un.s.member[1].mask = 1 << EAP_CD_VOL;

sys/dev/pci/eap.c

1369

dip->un.s.member[2].mask = 1 << EAP_LINE_VOL;

sys/dev/pci/eap.c

1372

dip->un.s.member[3].mask = 1 << EAP_FM_VOL;

sys/dev/pci/eap.c

1375

dip->un.s.member[4].mask = 1 << EAP_AUX_VOL;

sys/dev/pci/eap.c

1378

dip->un.s.member[5].mask = 1 << EAP_VOICE_VOL;

sys/dev/pci/eap.c

1388

dip->un.s.member[0].mask = 1 << EAP_MIC_VOL;

sys/dev/pci/eap.c

1391

dip->un.s.member[1].mask = 1 << EAP_CD_VOL;

sys/dev/pci/eap.c

1394

dip->un.s.member[2].mask = 1 << EAP_LINE_VOL;

sys/dev/pci/eap.c

1397

dip->un.s.member[3].mask = 1 << EAP_FM_VOL;

sys/dev/pci/eap.c

1400

dip->un.s.member[4].mask = 1 << EAP_AUX_VOL;

sys/dev/pci/eap.c

1403

dip->un.s.member[5].mask = 1 << EAP_VOICE_VOL;

sys/dev/pci/eap.c

479

ctl.un.mask = 1 << EAP_VOICE_VOL | 1 << EAP_FM_VOL |

sys/dev/pci/eap.c

499

ctl.un.mask = 1 << EAP_MIC_VOL;

sys/dev/pci/emuxki.c

578

u_int32_t ptr, mask = 0xffffffff;

sys/dev/pci/emuxki.c

588

mask = ((1 << size) - 1) << offset;

sys/dev/pci/emuxki.c

592

ptr = (bus_space_read_4(sc->sc_iot, sc->sc_ioh, EMU_DATA) & mask)

sys/dev/pci/emuxki.c

601

u_int32_t ptr, mask;

sys/dev/pci/emuxki.c

616

mask = ((1 << size) - 1) << offset;

sys/dev/pci/emuxki.c

617

data = ((data << offset) & mask) |

sys/dev/pci/emuxki.c

618

(emuxki_read(sc, chano, reg & 0xffff) & ~mask);

sys/dev/pci/envy.c

1132

envy_gpio_setmask(struct envy_softc *sc, int mask)

sys/dev/pci/envy.c

1135

envy_ccs_write(sc, ENVY_CCS_GPIOMASK0, mask & 0xff);

sys/dev/pci/envy.c

1136

envy_ccs_write(sc, ENVY_CCS_GPIOMASK1, (mask >> 8) & 0xff);

sys/dev/pci/envy.c

1137

envy_ccs_write(sc, ENVY_CCS_GPIOMASK2, (mask >> 16) & 0xff);

sys/dev/pci/envy.c

1139

envy_cci_write(sc, ENVY_CCI_GPIOMASK, mask);

sys/dev/pci/envy.c

1198

int mask, reg;

sys/dev/pci/envy.c

1202

for (mask = 0x80; mask != 0; mask >>= 1) {

sys/dev/pci/envy.c

1204

reg |= (val & mask) ? sda : 0;

sys/dev/pci/envy.c

1547

int reg, shift, mask, sel;

sys/dev/pci/envy.c

1560

mask = ENVY_MT_HTSRC_MASK << shift;

sys/dev/pci/envy.c

1562

reg = (reg & ~mask) | (sel << shift);

sys/dev/pci/envy.c

1579

mask = ENVY_MT_INSEL_MASK << shift;

sys/dev/pci/envy.c

1581

reg = (reg & ~mask) | (sel << shift);

sys/dev/pci/envy.c

1599

mask = ENVY_MT_OUTSRC_MASK << shift;

sys/dev/pci/envy.c

1601

reg = (reg & ~mask) | (sel << shift);

sys/dev/pci/envy.c

1633

int reg, shift, mask, sel;

sys/dev/pci/envy.c

1647

mask = ENVY_MT_SPDSEL_MASK << shift;

sys/dev/pci/envy.c

1648

reg = (reg & ~mask) | (sel << shift);

sys/dev/pci/envy.c

1664

mask = ENVY_MT_SPDSRC_MASK << shift;

sys/dev/pci/envy.c

1665

reg = (reg & ~mask) | (sel << shift);

sys/dev/pci/envy.c

1987

sc->intrs[i].mask,

sys/dev/pci/envy.c

2025

sc->intrs[sc->nintr].mask = envy_mt_read_1(sc, ENVY_MT_IMASK);

sys/dev/pci/envy.c

590

int attn, bits, mask, reg;

sys/dev/pci/envy.c

602

for (mask = 0x8000; mask != 0; mask >>= 1) {

sys/dev/pci/envy.c

604

reg |= (bits & mask) ? REVO51_GPIO_DOUT : 0;

sys/dev/pci/envyvar.h

87

int ipos, opos, st, mask, ctl, iactive, oactive;

sys/dev/pci/if_aq_pci.c

3876

uint32_t tag, uint32_t mask, uint32_t action)

sys/dev/pci/if_aq_pci.c

3890

AQ_WRITE_REG(sc, AQ2_RPF_ACT_ART_REQ_MASK_REG(idx), mask);

sys/dev/pci/if_aq_pci.c

622

#define AQ_WRITE_REG_BIT(sc, reg, mask, val) \

sys/dev/pci/if_aq_pci.c

626

_v &= ~(mask); \

sys/dev/pci/if_aq_pci.c

628

_v |= __SHIFTIN((val), (mask)); \

sys/dev/pci/if_bnx.c

1731

u_int32_t mask;

sys/dev/pci/if_bnx.c

1737

mask = FLASH_BACKUP_STRAP_MASK;

sys/dev/pci/if_bnx.c

1739

mask = FLASH_STRAP_MASK;

sys/dev/pci/if_bnx.c

1745

if ((val & mask) == (flash->strapping & mask)) {

sys/dev/pci/if_bnxt.c

3671

req.mask = htole32(rx_mask);

sys/dev/pci/if_bnxtreg.h

45682

uint32_t mask;

sys/dev/pci/if_bnxtreg.h

55962

uint8_t mask[8];

sys/dev/pci/if_bwfm_pci.c

2347

uint32_t status, mask;

sys/dev/pci/if_bwfm_pci.c

2367

mask = BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H_DB;

sys/dev/pci/if_bwfm_pci.c

2369

mask = BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H_DB;

sys/dev/pci/if_bwfm_pci.c

2371

if (status & mask) {

sys/dev/pci/if_de.c

3566

u_int32_t mask;

sys/dev/pci/if_de.c

3571

for (sep = " ", mask = 1; mask <= csr; mask <<= 1, msgp++) {

sys/dev/pci/if_de.c

3572

if ((csr & mask) && *msgp != NULL) {

sys/dev/pci/if_de.c

3574

if (mask == TULIP_STS_TXUNDERFLOW && (sc->tulip_flags & TULIP_NEWTXTHRESH)) {

sys/dev/pci/if_em.c

3283

uint32_t mask;

sys/dev/pci/if_em.c

3286

mask = sc->msix_queuesmask | sc->msix_linkmask;

sys/dev/pci/if_em.c

3287

E1000_WRITE_REG(&sc->hw, EIAC, mask);

sys/dev/pci/if_em.c

3288

E1000_WRITE_REG(&sc->hw, EIAM, mask);

sys/dev/pci/if_em.c

3289

E1000_WRITE_REG(&sc->hw, EIMS, mask);

sys/dev/pci/if_em_hw.c

4772

uint32_t mask;

sys/dev/pci/if_em_hw.c

4779

mask = 0x01;

sys/dev/pci/if_em_hw.c

4780

mask <<= (count - 1);

sys/dev/pci/if_em_hw.c

4789

while (mask) {

sys/dev/pci/if_em_hw.c

4796

if (data & mask)

sys/dev/pci/if_em_hw.c

4809

mask = mask >> 1;

sys/dev/pci/if_em_hw.c

4870

em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask)

sys/dev/pci/if_em_hw.c

4873

uint32_t swmask = mask;

sys/dev/pci/if_em_hw.c

4874

uint32_t fwmask = mask << 16;

sys/dev/pci/if_em_hw.c

4914

em_swfw_sync_release(struct em_hw *hw, uint16_t mask)

sys/dev/pci/if_em_hw.c

4917

uint32_t swmask = mask;

sys/dev/pci/if_em_hw.c

6585

uint32_t mask;

sys/dev/pci/if_em_hw.c

6591

mask = 0x01 << (count - 1);

sys/dev/pci/if_em_hw.c

6608

if (data & mask)

sys/dev/pci/if_em_hw.c

6619

mask = mask >> 1;

sys/dev/pci/if_em_hw.c

6621

} while (mask);

sys/dev/pci/if_em_hw.h

994

volatile uint32_t mask; /* Flexible Filter Mask (RW) */

sys/dev/pci/if_iavf.c

2031

unsigned int mask;

sys/dev/pci/if_iavf.c

2052

mask = sc->sc_tx_ring_ndescs - 1;

sys/dev/pci/if_iavf.c

2072

prod &= mask;

sys/dev/pci/if_iavf.c

2099

prod &= mask;

sys/dev/pci/if_iavf.c

2134

unsigned int mask;

sys/dev/pci/if_iavf.c

2148

mask = sc->sc_tx_ring_ndescs - 1;

sys/dev/pci/if_iavf.c

2170

cons &= mask;

sys/dev/pci/if_iavf.c

2333

unsigned int mask;

sys/dev/pci/if_iavf.c

2350

mask = sc->sc_rx_ring_ndescs - 1;

sys/dev/pci/if_iavf.c

2411

cons &= mask;

sys/dev/pci/if_iavf.c

2439

unsigned int mask;

sys/dev/pci/if_iavf.c

2449

mask = sc->sc_rx_ring_ndescs - 1;

sys/dev/pci/if_iavf.c

2479

prod &= mask;

sys/dev/pci/if_iavf.c

96

#define I40E_MASK(mask, shift) ((mask) << (shift))

sys/dev/pci/if_ice.c

14034

unsigned int mask;

sys/dev/pci/if_ice.c

14059

mask = txq->desc_count - 1;

sys/dev/pci/if_ice.c

14120

prod &= mask;

sys/dev/pci/if_ice.c

14142

prod &= mask;

sys/dev/pci/if_ice.c

1760

ice_debug_array(struct ice_hw *hw, uint64_t mask, uint32_t rowsize,

sys/dev/pci/if_ice.c

1764

if (!(mask & ice_debug))

sys/dev/pci/if_ice.c

17846

ice_aq_set_event_mask(struct ice_hw *hw, uint8_t port_num, uint16_t mask,

sys/dev/pci/if_ice.c

17858

cmd->event_mask = htole16(mask);

sys/dev/pci/if_ice.c

18480

ice_bits_max_set(const uint8_t *mask, uint16_t size, uint16_t max)

sys/dev/pci/if_ice.c

18488

if (!mask[i])

sys/dev/pci/if_ice.c

18499

count += ice_popcount16(mask[i]);

sys/dev/pci/if_ice.c

2195

uint8_t src_byte, dest_byte, mask;

sys/dev/pci/if_ice.c

2204

mask = (uint8_t)(BIT(ce_info->width) - 1);

sys/dev/pci/if_ice.c

2207

src_byte &= mask;

sys/dev/pci/if_ice.c

2210

mask <<= shift_width;

sys/dev/pci/if_ice.c

2218

dest_byte &= ~mask; /* get the bits not changing */

sys/dev/pci/if_ice.c

2235

uint16_t src_word, mask;

sys/dev/pci/if_ice.c

2245

mask = BIT(ce_info->width) - 1;

sys/dev/pci/if_ice.c

2251

src_word &= mask;

sys/dev/pci/if_ice.c

2254

mask <<= shift_width;

sys/dev/pci/if_ice.c

2262

dest_word &= ~(htole16(mask)); /* get the bits not changing */

sys/dev/pci/if_ice.c

2279

uint32_t src_dword, mask;

sys/dev/pci/if_ice.c

2295

mask = BIT(ce_info->width) - 1;

sys/dev/pci/if_ice.c

2297

mask = (uint32_t)~0;

sys/dev/pci/if_ice.c

2303

src_dword &= mask;

sys/dev/pci/if_ice.c

2306

mask <<= shift_width;

sys/dev/pci/if_ice.c

2314

dest_dword &= ~(htole32(mask)); /* get the bits not changing */

sys/dev/pci/if_ice.c

2331

uint64_t src_qword, mask;

sys/dev/pci/if_ice.c

2347

mask = BIT_ULL(ce_info->width) - 1;

sys/dev/pci/if_ice.c

2349

mask = (uint64_t)~0;

sys/dev/pci/if_ice.c

2355

src_qword &= mask;

sys/dev/pci/if_ice.c

2358

mask <<= shift_width;

sys/dev/pci/if_ice.c

2366

dest_qword &= ~(htole64(mask)); /* get the bits not changing */

sys/dev/pci/if_ice.c

25763

seg->fields[fld].src.mask = mask_loc;

sys/dev/pci/if_ice.c

29352

unsigned int mask;

sys/dev/pci/if_ice.c

29367

mask = rxq->desc_count - 1;

sys/dev/pci/if_ice.c

29444

cons &= mask;

sys/dev/pci/if_ice.c

29477

unsigned int mask;

sys/dev/pci/if_ice.c

29491

mask = txq->desc_count - 1;

sys/dev/pci/if_ice.c

29517

cons &= mask;

sys/dev/pci/if_ice.c

7869

unsigned int mask;

sys/dev/pci/if_ice.c

7879

mask = rxq->desc_count - 1;

sys/dev/pci/if_ice.c

7909

prod &= mask;

sys/dev/pci/if_icevar.h

2375

uint16_t mask[ICE_NUM_WORDS_RECIPE];

sys/dev/pci/if_icevar.h

290

ice_bitmap_t res = 0, mask;

sys/dev/pci/if_icevar.h

2946

uint16_t mask; /* Offset where the mask/prefix value is located */

sys/dev/pci/if_icevar.h

305

mask = LAST_CHUNK_MASK(size);

sys/dev/pci/if_icevar.h

306

dst[i] = (dst[i] & ~mask) | ((bmp1[i] & bmp2[i]) & mask);

sys/dev/pci/if_icevar.h

307

res |= dst[i] & mask;

sys/dev/pci/if_icevar.h

327

ice_bitmap_t mask;

sys/dev/pci/if_icevar.h

339

mask = LAST_CHUNK_MASK(size);

sys/dev/pci/if_icevar.h

340

dst[i] = (dst[i] & ~mask) | ((bmp1[i] | bmp2[i]) & mask);

sys/dev/pci/if_icevar.h

358

ice_bitmap_t mask;

sys/dev/pci/if_icevar.h

370

mask = LAST_CHUNK_MASK(size);

sys/dev/pci/if_icevar.h

371

dst[i] = (dst[i] & ~mask) | ((bmp1[i] ^ bmp2[i]) & mask);

sys/dev/pci/if_icevar.h

389

ice_bitmap_t mask;

sys/dev/pci/if_icevar.h

401

mask = LAST_CHUNK_MASK(size);

sys/dev/pci/if_icevar.h

402

dst[i] = (dst[i] & ~mask) | ((bmp1[i] & ~bmp2[i]) & mask);

sys/dev/pci/if_icevar.h

4244

ice_bitstr_t *curbitstr, mask;

sys/dev/pci/if_icevar.h

4258

mask = ice_bit_make_mask(start,

sys/dev/pci/if_icevar.h

4260

value += ice_popcount32(*curbitstr & mask);

sys/dev/pci/if_icevar.h

4272

mask = ice_bit_make_mask(0, ice_bit_offset(nbits - 1));

sys/dev/pci/if_icevar.h

4273

value += ice_popcount32(*curbitstr & mask);

sys/dev/pci/if_icevar.h

4285

ice_bitstr_t mask;

sys/dev/pci/if_icevar.h

4294

mask = match ? 0 : ICE_BITSTR_MASK;

sys/dev/pci/if_icevar.h

4296

test = mask ^ *curbitstr;

sys/dev/pci/if_icevar.h

4300

test = mask ^ *(++curbitstr);

sys/dev/pci/if_icevar.h

4314

ice_bitstr_t *curbitstr, mask, test;

sys/dev/pci/if_icevar.h

4321

mask = match ? ICE_BITSTR_MASK : 0;

sys/dev/pci/if_icevar.h

4326

for (last = size - 1, test |= mask ^ *curbitstr;

sys/dev/pci/if_icevar.h

4329

last -= ICE_BITSTR_BITS, test = mask ^ *++curbitstr) {

sys/dev/pci/if_icevar.h

548

ice_bitmap_t mask;

sys/dev/pci/if_icevar.h

557

mask = LAST_CHUNK_MASK(size);

sys/dev/pci/if_icevar.h

558

if ((bmp1[i] & mask) != (bmp2[i] & mask))

sys/dev/pci/if_igc.c

1025

prod &= mask;

sys/dev/pci/if_igc.c

1046

prod &= mask;

sys/dev/pci/if_igc.c

1080

unsigned int mask;

sys/dev/pci/if_igc.c

1092

mask = sc->num_tx_desc - 1;

sys/dev/pci/if_igc.c

1113

cons &= mask;

sys/dev/pci/if_igc.c

1771

uint32_t mask;

sys/dev/pci/if_igc.c

1773

mask = (sc->msix_queuesmask | sc->msix_linkmask);

sys/dev/pci/if_igc.c

1774

IGC_WRITE_REG(hw, IGC_EIAC, mask);

sys/dev/pci/if_igc.c

1775

IGC_WRITE_REG(hw, IGC_EIAM, mask);

sys/dev/pci/if_igc.c

1776

IGC_WRITE_REG(hw, IGC_EIMS, mask);

sys/dev/pci/if_igc.c

970

unsigned int mask;

sys/dev/pci/if_igc.c

992

mask = sc->num_tx_desc - 1;

sys/dev/pci/if_iwm.c

1127

iwm_poll_bit(struct iwm_softc *sc, int reg, uint32_t bits, uint32_t mask,

sys/dev/pci/if_iwm.c

1131

if ((IWM_READ(sc, reg) & mask) == (bits & mask)) {

sys/dev/pci/if_iwm.c

1189

uint32_t mask)

sys/dev/pci/if_iwm.c

1194

val = iwm_read_prph(sc, reg) & mask;

sys/dev/pci/if_iwm.c

2152

uint32_t mask, val, reg_val = 0;

sys/dev/pci/if_iwm.c

2171

mask = IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH |

sys/dev/pci/if_iwm.c

2180

val &= ~mask;

sys/dev/pci/if_iwmreg.h

6830

#define IWM_SETBITS(sc, reg, mask) \

sys/dev/pci/if_iwmreg.h

6831

IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask))

sys/dev/pci/if_iwmreg.h

6833

#define IWM_CLRBITS(sc, reg, mask) \

sys/dev/pci/if_iwmreg.h

6834

IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask))

sys/dev/pci/if_iwn.c

4290

uint8_t mask, agc;

sys/dev/pci/if_iwn.c

4293

mask = (letoh16(phy->antenna) >> 4) & IWN_ANT_ABC;

sys/dev/pci/if_iwn.c

4297

if (mask & IWN_ANT_A)

sys/dev/pci/if_iwn.c

4299

if (mask & IWN_ANT_B)

sys/dev/pci/if_iwn.c

4301

if (mask & IWN_ANT_C)

sys/dev/pci/if_iwn.c

867

iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask)

sys/dev/pci/if_iwn.c

869

iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask);

sys/dev/pci/if_iwn.c

873

iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask)

sys/dev/pci/if_iwn.c

875

iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask);

sys/dev/pci/if_iwnreg.h

2105

#define IWN_SETBITS(sc, reg, mask) \

sys/dev/pci/if_iwnreg.h

2106

IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask))

sys/dev/pci/if_iwnreg.h

2108

#define IWN_CLRBITS(sc, reg, mask) \

sys/dev/pci/if_iwnreg.h

2109

IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask))

sys/dev/pci/if_iwx.c

1669

uint32_t mask = iwx_prph_addr_mask(sc);

sys/dev/pci/if_iwx.c

1670

IWX_WRITE(sc, IWX_HBUS_TARG_PRPH_RADDR, ((addr & mask) | (3 << 24)));

sys/dev/pci/if_iwx.c

1685

uint32_t mask = iwx_prph_addr_mask(sc);

sys/dev/pci/if_iwx.c

1686

IWX_WRITE(sc, IWX_HBUS_TARG_PRPH_WADDR, ((addr & mask) | (3 << 24)));

sys/dev/pci/if_iwx.c

1766

iwx_poll_bit(struct iwx_softc *sc, int reg, uint32_t bits, uint32_t mask,

sys/dev/pci/if_iwx.c

1770

if ((IWX_READ(sc, reg) & mask) == (bits & mask)) {

sys/dev/pci/if_iwx.c

1784

uint32_t access_req, ready, mask;

sys/dev/pci/if_iwx.c

1795

mask = IWX_CSR_GP_CNTRL_REG_FLAG_MAC_STATUS;

sys/dev/pci/if_iwx.c

1799

mask = IWX_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |

sys/dev/pci/if_iwx.c

1807

if (iwx_poll_bit(sc, IWX_CSR_GP_CNTRL, ready, mask, 150000)) {

sys/dev/pci/if_iwx.c

1842

uint32_t mask)

sys/dev/pci/if_iwx.c

1847

val = iwx_read_prph(sc, reg) & mask;

sys/dev/pci/if_iwx.c

2823

uint32_t mask, val, reg_val = 0;

sys/dev/pci/if_iwx.c

2842

mask = IWX_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH |

sys/dev/pci/if_iwx.c

2851

val &= ~mask;

sys/dev/pci/if_iwxreg.h

8945

#define IWX_SETBITS(sc, reg, mask) \

sys/dev/pci/if_iwxreg.h

8946

IWX_WRITE(sc, reg, IWX_READ(sc, reg) | (mask))

sys/dev/pci/if_iwxreg.h

8948

#define IWX_CLRBITS(sc, reg, mask) \

sys/dev/pci/if_iwxreg.h

8949

IWX_WRITE(sc, reg, IWX_READ(sc, reg) & ~(mask))

sys/dev/pci/if_ix.c

1036

uint32_t mask;

sys/dev/pci/if_ix.c

1039

mask = (IXGBE_EIMS_RTX_QUEUE & queue);

sys/dev/pci/if_ix.c

1040

IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMS, mask);

sys/dev/pci/if_ix.c

1042

mask = (queue & 0xFFFFFFFF);

sys/dev/pci/if_ix.c

1043

if (mask)

sys/dev/pci/if_ix.c

1044

IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMS_EX(0), mask);

sys/dev/pci/if_ix.c

1045

mask = (queue >> 32);

sys/dev/pci/if_ix.c

1046

if (mask)

sys/dev/pci/if_ix.c

1047

IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMS_EX(1), mask);

sys/dev/pci/if_ix.c

1065

uint32_t mask;

sys/dev/pci/if_ix.c

1068

mask = (IXGBE_EIMS_RTX_QUEUE & queue);

sys/dev/pci/if_ix.c

1069

IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC, mask);

sys/dev/pci/if_ix.c

1071

mask = (queue & 0xFFFFFFFF);

sys/dev/pci/if_ix.c

1072

if (mask)

sys/dev/pci/if_ix.c

1073

IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC_EX(0), mask);

sys/dev/pci/if_ix.c

1074

mask = (queue >> 32);

sys/dev/pci/if_ix.c

1075

if (mask)

sys/dev/pci/if_ix.c

1076

IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC_EX(1), mask);

sys/dev/pci/if_ix.c

3446

uint32_t mask, fwsm;

sys/dev/pci/if_ix.c

3448

mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);

sys/dev/pci/if_ix.c

3451

mask |= IXGBE_EIMS_GPI_SDP1;

sys/dev/pci/if_ix.c

3455

mask |= IXGBE_EIMS_ECC;

sys/dev/pci/if_ix.c

3457

mask |= IXGBE_EIMS_GPI_SDP0;

sys/dev/pci/if_ix.c

3459

mask |= IXGBE_EIMS_GPI_SDP1;

sys/dev/pci/if_ix.c

3460

mask |= IXGBE_EIMS_GPI_SDP2;

sys/dev/pci/if_ix.c

3463

mask |= IXGBE_EIMS_ECC;

sys/dev/pci/if_ix.c

3467

mask |= IXGBE_EIMS_TS;

sys/dev/pci/if_ix.c

3472

mask |= IXGBE_EIMS_ECC;

sys/dev/pci/if_ix.c

3474

mask |= IXGBE_EIMS_TS;

sys/dev/pci/if_ix.c

3478

mask |= IXGBE_EIMS_GPI_SDP0_X540;

sys/dev/pci/if_ix.c

3483

IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);

sys/dev/pci/if_ix.c

3487

mask = IXGBE_EIMS_ENABLE_MASK;

sys/dev/pci/if_ix.c

3489

mask &= ~IXGBE_EIMS_OTHER;

sys/dev/pci/if_ix.c

3490

mask &= ~IXGBE_EIMS_LSC;

sys/dev/pci/if_ix.c

3491

IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);

sys/dev/pci/if_ixl.c

103

#define I40E_MASK(mask, shift) ((mask) << (shift))

sys/dev/pci/if_ixl.c

2865

unsigned int mask;

sys/dev/pci/if_ixl.c

2887

mask = sc->sc_tx_ring_ndescs - 1;

sys/dev/pci/if_ixl.c

2907

prod &= mask;

sys/dev/pci/if_ixl.c

2934

prod &= mask;

sys/dev/pci/if_ixl.c

2969

unsigned int mask;

sys/dev/pci/if_ixl.c

2983

mask = sc->sc_tx_ring_ndescs - 1;

sys/dev/pci/if_ixl.c

3005

cons &= mask;

sys/dev/pci/if_ixl.c

3229

unsigned int mask;

sys/dev/pci/if_ixl.c

3243

mask = sc->sc_rx_ring_ndescs - 1;

sys/dev/pci/if_ixl.c

3315

cons &= mask;

sys/dev/pci/if_ixl.c

3349

unsigned int mask;

sys/dev/pci/if_ixl.c

3359

mask = sc->sc_rx_ring_ndescs - 1;

sys/dev/pci/if_ixl.c

3389

prod &= mask;

sys/dev/pci/if_ixl.c

4473

uint64_t mask;

sys/dev/pci/if_ixl.c

4479

mask = 1ULL << phy_type;

sys/dev/pci/if_ixl.c

4484

if (ISSET(itype->phy_type, mask))

sys/dev/pci/if_ixv.c

1096

uint32_t mask;

sys/dev/pci/if_ixv.c

1100

mask = (1 << sc->linkvec);

sys/dev/pci/if_ixv.c

1102

mask |= (1 << que->msix);

sys/dev/pci/if_ixv.c

1103

IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, mask);

sys/dev/pci/if_ixv.c

434

uint32_t mask;

sys/dev/pci/if_ixv.c

498

mask = (1 << sc->linkvec);

sys/dev/pci/if_ixv.c

500

mask |= (1 << que->msix);

sys/dev/pci/if_ixv.c

501

IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, mask);

sys/dev/pci/if_ixv.c

538

uint32_t mask;

sys/dev/pci/if_ixv.c

540

mask = (IXGBE_EIMS_RTX_QUEUE & queue);

sys/dev/pci/if_ixv.c

541

IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);

sys/dev/pci/if_ixv.c

549

uint32_t mask;

sys/dev/pci/if_ixv.c

551

mask = (IXGBE_EIMS_RTX_QUEUE & queue);

sys/dev/pci/if_ixv.c

552

IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, mask);

sys/dev/pci/if_mwx.c

1047

uint32_t mask = MT_INT_RX_DONE_ALL|MT_INT_TX_DONE_ALL|MT_INT_MCU_CMD;

sys/dev/pci/if_mwx.c

1052

mwx_write(sc, MT_WFDMA0_HOST_INT_ENA, mask);

sys/dev/pci/if_mwx.c

1059

if (intr & ~mask)

sys/dev/pci/if_mwx.c

1061

intr & ~mask);

sys/dev/pci/if_mwx.c

1063

intr &= mask;

sys/dev/pci/if_mwx.c

1087

mwx_write(sc, MT_WFDMA0_HOST_INT_ENA, mask);

sys/dev/pci/if_mwx.c

481

mwx_rmw(struct mwx_softc *sc, uint32_t reg, uint32_t val, uint32_t mask)

sys/dev/pci/if_mwx.c

484

val |= bus_space_read_4(sc->sc_st, sc->sc_memh, reg) & ~mask;

sys/dev/pci/if_mwx.c

519

mwx_poll(struct mwx_softc *sc, uint32_t reg, uint32_t val, uint32_t mask,

sys/dev/pci/if_mwx.c

527

cur = bus_space_read_4(sc->sc_st, sc->sc_memh, reg) & mask;

sys/dev/pci/if_mwx.c

534

DEVNAME(sc), reg, val, mask, cur);

sys/dev/pci/if_myx.c

328

pcireg_t mask = PCI_PCIE_DCSR_MPS | PCI_PCIE_DCSR_ERO;

sys/dev/pci/if_myx.c

338

if ((dcsr & mask) != dc) {

sys/dev/pci/if_myx.c

339

CLR(dcsr, mask);

sys/dev/pci/if_nfe.c

1490

uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN];

sys/dev/pci/if_nfe.c

1504

bzero(mask, ETHER_ADDR_LEN);

sys/dev/pci/if_nfe.c

1509

bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN);

sys/dev/pci/if_nfe.c

1515

mask[i] &= ~enm->enm_addrlo[i];

sys/dev/pci/if_nfe.c

1522

mask[i] |= addr[i];

sys/dev/pci/if_nfe.c

1532

mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]);

sys/dev/pci/if_nfe.c

1534

mask[5] << 8 | mask[4]);

sys/dev/pci/if_ngbe.c

2460

uint32_t mask;

sys/dev/pci/if_ngbe.c

2462

mask = (queue & 0xffffffff);

sys/dev/pci/if_ngbe.c

2463

if (mask)

sys/dev/pci/if_ngbe.c

2464

NGBE_WRITE_REG(&sc->hw, NGBE_PX_IMS, mask);

sys/dev/pci/if_ngbe.c

2546

uint32_t mask;

sys/dev/pci/if_ngbe.c

2550

mask = NGBE_PX_MISC_IEN_MASK;

sys/dev/pci/if_ngbe.c

2552

mask |= NGBE_PX_MISC_IEN_OVER_HEAT;

sys/dev/pci/if_ngbe.c

2559

NGBE_WRITE_REG(hw, NGBE_PX_MISC_IEN, mask);

sys/dev/pci/if_ngbe.c

2573

uint32_t mask;

sys/dev/pci/if_ngbe.c

2575

mask = (queue & 0xffffffff);

sys/dev/pci/if_ngbe.c

2576

if (mask)

sys/dev/pci/if_ngbe.c

2577

NGBE_WRITE_REG(&sc->hw, NGBE_PX_IMC, mask);

sys/dev/pci/if_ngbe.c

3607

ngbe_acquire_swfw_sync(struct ngbe_softc *sc, uint32_t mask)

sys/dev/pci/if_ngbe.c

3611

uint32_t swmask = mask;

sys/dev/pci/if_ngbe.c

3612

uint32_t fwmask = mask << 16;

sys/dev/pci/if_ngbe.c

3648

ngbe_release_swfw_sync(struct ngbe_softc *sc, uint32_t mask)

sys/dev/pci/if_ngbe.c

3654

NGBE_WRITE_REG_MASK(hw, NGBE_MNG_SWFW_SYNC, mask, 0);

sys/dev/pci/if_ngbe.c

372

NGBE_READ_REG_MASK(struct ngbe_hw *hw, uint32_t reg, uint32_t mask)

sys/dev/pci/if_ngbe.c

379

return val & mask;

sys/dev/pci/if_ngbe.c

383

NGBE_WRITE_REG_MASK(struct ngbe_hw *hw, uint32_t reg, uint32_t mask,

sys/dev/pci/if_ngbe.c

391

val = ((val & ~mask) | (field & mask));

sys/dev/pci/if_qwx_pci.c

1975

uint32_t mask)

sys/dev/pci/if_qwx_pci.c

1981

if ((v & mask) == value)

sys/dev/pci/if_qwx_pci.c

1985

qwx_pcic_write32(sc, offset, (v & ~mask) | value);

sys/dev/pci/if_qwx_pci.c

1988

if ((v & mask) == value)

sys/dev/pci/if_qwx_pci.c

1995

offset, v & mask, value);

sys/dev/pci/if_qwz_pci.c

1842

uint32_t mask)

sys/dev/pci/if_qwz_pci.c

1848

if ((v & mask) == value)

sys/dev/pci/if_qwz_pci.c

1852

qwz_pcic_write32(sc, offset, (v & ~mask) | value);

sys/dev/pci/if_qwz_pci.c

1855

if ((v & mask) == value)

sys/dev/pci/if_qwz_pci.c

1862

offset, v & mask, value);

sys/dev/pci/if_wpi.c

475

wpi_prph_setbits(struct wpi_softc *sc, uint32_t addr, uint32_t mask)

sys/dev/pci/if_wpi.c

477

wpi_prph_write(sc, addr, wpi_prph_read(sc, addr) | mask);

sys/dev/pci/if_wpi.c

481

wpi_prph_clrbits(struct wpi_softc *sc, uint32_t addr, uint32_t mask)

sys/dev/pci/if_wpi.c

483

wpi_prph_write(sc, addr, wpi_prph_read(sc, addr) & ~mask);

sys/dev/pci/if_wpireg.h

375

uint32_t mask;

sys/dev/pci/if_wpireg.h

828

#define WPI_SETBITS(sc, reg, mask) \

sys/dev/pci/if_wpireg.h

829

WPI_WRITE(sc, reg, WPI_READ(sc, reg) | (mask))

sys/dev/pci/if_wpireg.h

831

#define WPI_CLRBITS(sc, reg, mask) \

sys/dev/pci/if_wpireg.h

832

WPI_WRITE(sc, reg, WPI_READ(sc, reg) & ~(mask))

sys/dev/pci/igc_base.c

22

uint16_t mask = IGC_SWFW_PHY0_SM;

sys/dev/pci/igc_base.c

27

mask = IGC_SWFW_PHY1_SM;

sys/dev/pci/igc_base.c

29

return hw->mac.ops.acquire_swfw_sync(hw, mask);

sys/dev/pci/igc_base.c

41

uint16_t mask = IGC_SWFW_PHY0_SM;

sys/dev/pci/igc_base.c

46

mask = IGC_SWFW_PHY1_SM;

sys/dev/pci/igc_base.c

48

hw->mac.ops.release_swfw_sync(hw, mask);

sys/dev/pci/igc_i225.c

270

igc_acquire_swfw_sync_i225(struct igc_hw *hw, uint16_t mask)

sys/dev/pci/igc_i225.c

273

uint32_t swmask = mask;

sys/dev/pci/igc_i225.c

274

uint32_t fwmask = mask << 16;

sys/dev/pci/igc_i225.c

321

igc_release_swfw_sync_i225(struct igc_hw *hw, uint16_t mask)

sys/dev/pci/igc_i225.c

331

swfw_sync &= ~mask;

sys/dev/pci/ixgb_ee.c

110

uint32_t mask;

sys/dev/pci/ixgb_ee.c

115

mask = 0x01 << (count - 1);

sys/dev/pci/ixgb_ee.c

126

if(data & mask)

sys/dev/pci/ixgb_ee.c

136

mask = mask >> 1;

sys/dev/pci/ixgb_ee.c

138

} while(mask);

sys/dev/pci/ixgbe.c

1571

uint32_t mask;

sys/dev/pci/ixgbe.c

1582

mask = 0x01 << (count - 1);

sys/dev/pci/ixgbe.c

1592

if (data & mask)

sys/dev/pci/ixgbe.c

1609

mask = mask >> 1;

sys/dev/pci/ixgbe.c

2741

int32_t ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, uint32_t mask)

sys/dev/pci/ixgbe.c

2744

uint32_t swmask = mask;

sys/dev/pci/ixgbe.c

2745

uint32_t fwmask = mask << 5;

sys/dev/pci/ixgbe.c

2788

void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, uint32_t mask)

sys/dev/pci/ixgbe.c

2791

uint32_t swmask = mask;

sys/dev/pci/ixgbe.c

4738

static int32_t ixgbe_check_for_bit_vf(struct ixgbe_hw *hw, uint32_t mask)

sys/dev/pci/ixgbe.c

4742

if (vf_mailbox & mask)

sys/dev/pci/ixgbe.c

4924

int32_t ixgbe_check_for_bit_pf(struct ixgbe_hw *hw, uint32_t mask, int32_t index)

sys/dev/pci/ixgbe.c

4928

if (pfmbicr & mask)

sys/dev/pci/ixgbe.c

73

int32_t ixgbe_check_for_bit_pf(struct ixgbe_hw *hw, uint32_t mask,

sys/dev/pci/ixgbe.h

209

int32_t ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, uint32_t mask);

sys/dev/pci/ixgbe.h

210

void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, uint32_t mask);

sys/dev/pci/ixgbe_x540.c

69

int32_t ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, uint32_t mask);

sys/dev/pci/ixgbe_x540.c

691

int32_t ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, uint32_t mask)

sys/dev/pci/ixgbe_x540.c

693

uint32_t swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;

sys/dev/pci/ixgbe_x540.c

695

uint32_t swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;

sys/dev/pci/ixgbe_x540.c

70

void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, uint32_t mask);

sys/dev/pci/ixgbe_x540.c

707

if (mask & IXGBE_GSSR_SW_MNG_SM)

sys/dev/pci/ixgbe_x540.c

788

void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, uint32_t mask)

sys/dev/pci/ixgbe_x540.c

790

uint32_t swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);

sys/dev/pci/ixgbe_x540.c

795

if (mask & IXGBE_GSSR_I2C_MASK)

sys/dev/pci/ixgbe_x540.c

796

swmask |= mask & IXGBE_GSSR_I2C_MASK;

sys/dev/pci/ixgbe_x550.c

102

int32_t ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, uint32_t mask);

sys/dev/pci/ixgbe_x550.c

103

void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, uint32_t mask);

sys/dev/pci/ixgbe_x550.c

2937

const uint32_t mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;

sys/dev/pci/ixgbe_x550.c

2954

status = hw->mac.ops.acquire_swfw_sync(hw, mask);

sys/dev/pci/ixgbe_x550.c

2965

hw->mac.ops.release_swfw_sync(hw, mask);

sys/dev/pci/ixgbe_x550.c

2982

const uint32_t mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;

sys/dev/pci/ixgbe_x550.c

2992

status = hw->mac.ops.acquire_swfw_sync(hw, mask);

sys/dev/pci/ixgbe_x550.c

3041

hw->mac.ops.release_swfw_sync(hw, mask);

sys/dev/pci/ixgbe_x550.c

4022

int32_t ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, uint32_t mask)

sys/dev/pci/ixgbe_x550.c

4028

status = ixgbe_acquire_swfw_sync_X540(hw, mask);

sys/dev/pci/ixgbe_x550.c

4032

if (mask & IXGBE_GSSR_I2C_MASK)

sys/dev/pci/ixgbe_x550.c

4045

void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, uint32_t mask)

sys/dev/pci/ixgbe_x550.c

4049

if (mask & IXGBE_GSSR_I2C_MASK)

sys/dev/pci/ixgbe_x550.c

4052

ixgbe_release_swfw_sync_X540(hw, mask);

sys/dev/pci/ixgbe_x550.c

4062

int32_t ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, uint32_t mask)

sys/dev/pci/ixgbe_x550.c

4064

uint32_t hmask = mask & ~IXGBE_GSSR_TOKEN_SM;

sys/dev/pci/ixgbe_x550.c

4079

if (!(mask & IXGBE_GSSR_TOKEN_SM))

sys/dev/pci/ixgbe_x550.c

41

extern int32_t ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, uint32_t mask);

sys/dev/pci/ixgbe_x550.c

4112

void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, uint32_t mask)

sys/dev/pci/ixgbe_x550.c

4114

uint32_t hmask = mask & ~IXGBE_GSSR_TOKEN_SM;

sys/dev/pci/ixgbe_x550.c

4118

if (mask & IXGBE_GSSR_TOKEN_SM)

sys/dev/pci/ixgbe_x550.c

4140

uint32_t mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;

sys/dev/pci/ixgbe_x550.c

4144

if (hw->mac.ops.acquire_swfw_sync(hw, mask))

sys/dev/pci/ixgbe_x550.c

4149

hw->mac.ops.release_swfw_sync(hw, mask);

sys/dev/pci/ixgbe_x550.c

4168

uint32_t mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;

sys/dev/pci/ixgbe_x550.c

4172

if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {

sys/dev/pci/ixgbe_x550.c

4175

hw->mac.ops.release_swfw_sync(hw, mask);

sys/dev/pci/ixgbe_x550.c

42

extern void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, uint32_t mask);

sys/dev/pci/ixgbe_x550.c

44

int32_t ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, uint32_t mask);

sys/dev/pci/ixgbe_x550.c

45

void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, uint32_t mask);

sys/dev/pci/mfii.c

3804

u_int32_t mask;

sys/dev/pci/mfii.c

3823

mask = MFI_BBU_STATE_BAD_IBBU;

sys/dev/pci/mfii.c

3827

mask = MFI_BBU_STATE_BAD_BBU;

sys/dev/pci/mfii.c

3848

sc->sc_bbu[0].value = ((status & mask) || soh_bad) ? 0 : 1;

sys/dev/pci/mfii.c

3849

sc->sc_bbu[0].status = ((status & mask) || soh_bad) ? SENSOR_S_CRIT :

sys/dev/pci/mpii.c

1022

mpii_wait_eq(struct mpii_softc *sc, bus_size_t r, u_int32_t mask,

sys/dev/pci/mpii.c

1028

mask, target);

sys/dev/pci/mpii.c

1031

if ((mpii_read(sc, r) & mask) == target)

sys/dev/pci/mpii.c

1040

mpii_wait_ne(struct mpii_softc *sc, bus_size_t r, u_int32_t mask,

sys/dev/pci/mpii.c

1046

mask, target);

sys/dev/pci/mpii.c

1049

if ((mpii_read(sc, r) & mask) != target)

sys/dev/pci/pccbb.c

150

bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align,

sys/dev/pci/pccbb.c

1622

bus_addr_t mask;

sys/dev/pci/pccbb.c

1631

mask = 0x3ff;

sys/dev/pci/pccbb.c

1633

start &= mask;

sys/dev/pci/pccbb.c

1649

mask = (1 << shifts);

sys/dev/pci/pccbb.c

1650

if (mask < size) {

sys/dev/pci/pccbb.c

1651

mask <<= 1;

sys/dev/pci/pccbb.c

1653

mask--;

sys/dev/pci/pccbb.c

1663

if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) {

sys/dev/pci/pccbb.c

2482

bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align,

sys/dev/pci/pccbb.c

2489

addr, size, mask, align));

sys/dev/pci/pccbb.c

2492

mask = max(mask, (4 - 1));

sys/dev/pci/pccbb.c

2495

mask = max(mask, (0x1000 - 1));

sys/dev/pci/pccbb.c

2500

if (mask < 0x0100) {

sys/dev/pci/pccbb.c

2501

mask = 0x3ff;

sys/dev/pci/pccbb.c

2506

if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) {

sys/dev/pci/pccbb.c

2652

bus_addr_t mask = ~(align - 1);

sys/dev/pci/pccbb.c

2673

win[0].win_start = chainp->wc_start & mask;

sys/dev/pci/pccbb.c

2674

win[0].win_limit = chainp->wc_end & mask;

sys/dev/pci/pccbb.c

2684

(chainp->wc_start & mask))) {

sys/dev/pci/pccbb.c

2686

win[0].win_limit = chainp->wc_end & mask;

sys/dev/pci/pccbb.c

2689

win[1].win_start = chainp->wc_start & mask;

sys/dev/pci/pccbb.c

2690

win[1].win_limit = chainp->wc_end & mask;

sys/dev/pci/pccbb.c

2702

(chainp->wc_start & mask) -

sys/dev/pci/pccbb.c

2703

((chainp->wc_end & mask) + align)) {

sys/dev/pci/pccbb.c

2710

chainp->wc_start & mask;

sys/dev/pci/pccbb.c

2712

chainp->wc_end & mask;

sys/dev/pci/pccbb.c

2715

chainp->wc_end & mask;

sys/dev/pci/pccbb.c

2723

win[1].win_start = chainp->wc_start & mask;

sys/dev/pci/pccbb.c

2724

win[1].win_limit = chainp->wc_end & mask;

sys/dev/pci/pccbb.c

2730

win[0].win_limit = chainp->wc_end & mask;

sys/dev/pci/pccbb.c

2739

win[1].win_limit = chainp->wc_end & mask;

sys/dev/pci/pci.c

1345

pcireg_t addr, mask, bhlc;

sys/dev/pci/pci.c

1360

mask = pci_conf_read(pc, tag, PCI_ROM_REG);

sys/dev/pci/pci.c

1373

PCI_ROM_SIZE(mask) % sizeof(buf)) != 0)

sys/dev/pci/pci.c

1382

if (rom->pr_romlen < PCI_ROM_SIZE(mask)) {

sys/dev/pci/pci.c

1388

PCI_ROM_SIZE(mask), 0, &h);

sys/dev/pci/pci.c

1393

len = PCI_ROM_SIZE(mask);

sys/dev/pci/pci.c

1408

bus_space_unmap(pci->sc_memt, h, PCI_ROM_SIZE(mask));

sys/dev/pci/pci.c

1411

rom->pr_romlen = PCI_ROM_SIZE(mask);

sys/dev/pci/pci.c

893

pcireg_t addr, mask, type;

sys/dev/pci/pci.c

994

mask = pci_conf_read(pc, tag, PCI_ROM_REG);

sys/dev/pci/pci.c

999

size = PCI_ROM_SIZE(mask);

sys/dev/pci/pci_map.c

100

mask = pci_conf_read(pc, tag, reg);

sys/dev/pci/pci_map.c

113

if (PCI_MAPREG_IO_SIZE(mask) == 0) {

sys/dev/pci/pci_map.c

123

*sizep = PCI_MAPREG_IO_SIZE(mask);

sys/dev/pci/pci_map.c

134

pcireg_t address, mask, address1 = 0, mask1 = 0xffffffff, csr;

sys/dev/pci/pci_map.c

171

mask = pci_conf_read(pc, tag, reg);

sys/dev/pci/pci_map.c

200

wmask = (u_int64_t)mask1 << 32UL | mask;

sys/dev/pci/pci_map.c

203

(!is64bit && PCI_MAPREG_MEM_SIZE(mask) == 0)) {

sys/dev/pci/pci_map.c

242

*sizep = PCI_MAPREG_MEM_SIZE(mask);

sys/dev/pci/pci_map.c

266

pcireg_t address, mask, csr;

sys/dev/pci/pci_map.c

276

mask = pci_conf_read(pc, tag, reg);

sys/dev/pci/pci_map.c

282

if (mask == 0) /* unimplemented mapping register */

sys/dev/pci/pci_map.c

69

pcireg_t address, mask, csr;

sys/dev/pci/ppb.c

577

pcireg_t addr, mask;

sys/dev/pci/ppb.c

649

mask = pci_conf_read(pc, tag, reg_rom);

sys/dev/pci/ppb.c

651

if (PCI_ROM_SIZE(mask))

sys/dev/pci/sti_pci.c

213

pcireg_t address, mask;

sys/dev/pci/sti_pci.c

226

mask = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG);

sys/dev/pci/sti_pci.c

235

romsize = PCI_ROM_SIZE(mask);

sys/dev/pci/sv.c

1037

reg &= ~(ports[idx].mask);

sys/dev/pci/sv.c

1038

lval = ((AUDIO_MAX_GAIN - lval) * ports[idx].mask) / AUDIO_MAX_GAIN;

sys/dev/pci/sv.c

1044

reg &= ~(ports[idx].mask);

sys/dev/pci/sv.c

1046

rval = ((AUDIO_MAX_GAIN - rval) * ports[idx].mask) / AUDIO_MAX_GAIN;

sys/dev/pci/sv.c

1177

reg &= ports[idx].mask;

sys/dev/pci/sv.c

1179

val = AUDIO_MAX_GAIN - ((reg * AUDIO_MAX_GAIN) / ports[idx].mask);

sys/dev/pci/sv.c

1185

reg &= ports[idx].mask;

sys/dev/pci/sv.c

1187

val = AUDIO_MAX_GAIN - ((reg * AUDIO_MAX_GAIN) / ports[idx].mask);

sys/dev/pci/sv.c

822

u_int8_t mask;

sys/dev/pckbc/pms.c

1102

syn->mask = SYNAPTICS_MASK_NEWABS_RELAXED;

sys/dev/pckbc/pms.c

1104

syn->mask = SYNAPTICS_MASK_NEWABS_STRICT;

sys/dev/pckbc/pms.c

115

int mask;

sys/dev/pckbc/pms.c

1280

if ((data & syn->mask) != SYNAPTICS_VALID_NEWABS_FIRST)

sys/dev/pckbc/pms.c

1284

if ((data & syn->mask) != SYNAPTICS_VALID_NEWABS_NEXT)

sys/dev/pckbc/pms.c

1459

alps->mask = alps_models[i].mask;

sys/dev/pckbc/pms.c

1622

if ((data & alps->mask) != alps->mask)

sys/dev/pckbc/pms.c

199

int mask;

sys/dev/pckbc/pms.c

93

int mask;

sys/dev/pcmcia/cfxga.c

826

cfxga_wait(struct cfxga_softc *sc, u_int mask, u_int result)

sys/dev/pcmcia/cfxga.c

831

if ((cfxga_read_1(sc, CFREG_BITBLT_CONTROL) & mask) == result)

sys/dev/pcmcia/if_xe.c

883

u_int32_t mask;

sys/dev/pcmcia/if_xe.c

885

for (mask = 1 << (len - 1); mask; mask >>= 1)

sys/dev/pcmcia/if_xe.c

886

xe_mdi_pulse(sc, data & mask);

sys/dev/pcmcia/if_xe.c

895

u_int32_t mask;

sys/dev/pcmcia/if_xe.c

907

for (mask = 1 << 15; mask; mask >>= 1)

sys/dev/pcmcia/if_xe.c

909

data |= mask;

sys/dev/rasops/rasops_masks.c

365

u_int32_t *mask;

sys/dev/rasops/rasops_masks.c

370

mask = (u_int32_t *)rasops_lmask;

sys/dev/rasops/rasops_masks.c

372

*mask++ = MBE(*mask);

sys/dev/rasops/rasops_masks.c

373

mask = (u_int32_t *)rasops_rmask;

sys/dev/rasops/rasops_masks.c

375

*mask++ = MBE(*mask);

sys/dev/rasops/rasops_masks.c

376

mask = (u_int32_t *)rasops_pmask;

sys/dev/rasops/rasops_masks.c

378

*mask++ = MBE(*mask);

sys/dev/sbus/cgsix.c

340

error = copyout(sc->sc_curs_mask, curs->mask, l);

sys/dev/sbus/cgsix.c

375

u_int8_t r[2], g[2], b[2], image[128], mask[128];

sys/dev/sbus/cgsix.c

405

error = copyin(curs->mask, mask, imcount);

sys/dev/sbus/cgsix.c

433

bcopy(mask, sc->sc_curs_mask, imcount);

sys/dev/sbus/vigra.c

106

u_int32_t mask;

sys/dev/sbus/vigra.c

137

u_int32_t mask;

sys/dev/sdmmc/sdhc.c

1093

int mask;

sys/dev/sdmmc/sdhc.c

1117

mask = ISSET(cmd->c_flags, SCF_CMD_READ) ?

sys/dev/sdmmc/sdhc.c

1140

if ((error = sdhc_wait_state(hp, mask, mask)) != 0)

sys/dev/sdmmc/sdhc.c

1205

sdhc_soft_reset(struct sdhc_host *hp, int mask)

sys/dev/sdmmc/sdhc.c

1209

DPRINTF(1,("%s: software reset reg=%#x\n", DEVNAME(hp->sc), mask));

sys/dev/sdmmc/sdhc.c

1211

HWRITE1(hp, SDHC_SOFTWARE_RESET, mask);

sys/dev/sdmmc/sdhc.c

1213

if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask))

sys/dev/sdmmc/sdhc.c

1229

sdhc_wait_intr_cold(struct sdhc_host *hp, int mask, int secs)

sys/dev/sdmmc/sdhc.c

1233

mask |= SDHC_ERROR_INTERRUPT;

sys/dev/sdmmc/sdhc.c

1236

while ((status & mask) == 0) {

sys/dev/sdmmc/sdhc.c

1274

hp->intr_status &= ~(status & mask);

sys/dev/sdmmc/sdhc.c

1275

return (status & mask);

sys/dev/sdmmc/sdhc.c

1279

sdhc_wait_intr(struct sdhc_host *hp, int mask, int secs)

sys/dev/sdmmc/sdhc.c

1285

return (sdhc_wait_intr_cold(hp, mask, secs));

sys/dev/sdmmc/sdhc.c

1287

mask |= SDHC_ERROR_INTERRUPT;

sys/dev/sdmmc/sdhc.c

1290

status = hp->intr_status & mask;

sys/dev/sdmmc/sdhc.c

1297

status = hp->intr_status & mask;

sys/dev/sdmmc/sdhc.c

858

sdhc_wait_state(struct sdhc_host *hp, u_int32_t mask, u_int32_t value)

sys/dev/sdmmc/sdhc.c

864

if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask)

sys/dev/sdmmc/sdmmcreg.h

299

u_int32_t dst, mask;

sys/dev/sdmmc/sdmmcreg.h

306

mask = len % 32 ? UINT_MAX >> (32 - (len % 32)) : UINT_MAX;

sys/dev/sdmmc/sdmmcreg.h

321

dst &= mask;

sys/dev/tc/bba.c

546

int mask;

sys/dev/tc/bba.c

550

mask = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_INTR);

sys/dev/tc/bba.c

552

if (mask & IOASIC_INTR_ISDN_TXLOAD) {

sys/dev/tc/bba.c

561

if (mask & IOASIC_INTR_ISDN_RXLOAD) {

sys/dev/usb/dwc2/dwc2_core.c

952

int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,

sys/dev/usb/dwc2/dwc2_core.c

958

if (dwc2_readl(hsotg, offset) & mask)

sys/dev/usb/dwc2/dwc2_core.c

975

int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,

sys/dev/usb/dwc2/dwc2_core.c

981

if (!(dwc2_readl(hsotg, offset) & mask))

sys/dev/usb/dwc2/dwc2_hcd.h

486

u32 mask = dwc2_readl(hsotg, HCINTMSK(chnum));

sys/dev/usb/dwc2/dwc2_hcd.h

488

mask &= ~intr;

sys/dev/usb/dwc2/dwc2_hcd.h

489

dwc2_writel(hsotg, mask, HCINTMSK(chnum));

sys/dev/usb/if_uath.c

1704

crypto.mask = htobe32(0xffff);

sys/dev/usb/if_uathreg.h

171

uint32_t mask;

sys/dev/usb/if_urtw.c

1087

uint32_t mask = 0x80000000, value = 0;

sys/dev/usb/if_urtw.c

1101

for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) {

sys/dev/usb/if_urtw.c

1102

bit = ((d2w & mask) != 0) ? 1 : 0;

sys/dev/usb/if_urtw.c

1112

mask = mask >> 1;

sys/dev/usb/if_urtw.c

1115

bit = ((d2w & mask) != 0) ? 1 : 0;

sys/dev/usb/if_urtw.c

1133

mask = 0x800;

sys/dev/usb/if_urtw.c

1134

for (i = 0; i < rlen; i++, mask = mask >> 1) {

sys/dev/usb/if_urtw.c

1149

value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0);

sys/dev/usb/uaudio.c

904

uaudio_rates_indexof(int mask, int rate)

sys/dev/usb/uaudio.c

911

if ((mask & (1 << i)) == 0)

sys/dev/usb/uhidpp.c

302

nlevels(uint8_t mask)

sys/dev/usb/uhidpp.c

306

for (; mask > 0; mask >>= 1) {

sys/dev/usb/uhidpp.c

307

if (mask & 1)

sys/dev/wscons/wsconsio.h

509

u_char *mask; /* mask data */

sys/dev/wscons/wskbd.c

1473

update_modifier(struct wskbd_internal *id, u_int type, int toggle, int mask)

sys/dev/wscons/wskbd.c

1477

id->t_modifiers ^= mask;

sys/dev/wscons/wskbd.c

1480

id->t_modifiers |= mask;

sys/dev/wscons/wskbd.c

1482

id->t_modifiers &= ~mask;

sys/dev/wscons/wskbd.c

1484

if (mask & MOD_ANYLED)

sys/dev/wscons/wskbd.c

218

#define MOD_ONESET(id, mask) (((id)->t_modifiers & (mask)) != 0)

sys/dev/wscons/wskbd.c

219

#define MOD_ALLSET(id, mask) (((id)->t_modifiers & (mask)) == (mask))

sys/dev/wscons/wsmouse.c

607

set_x(struct position *pos, int x, u_int *sync, u_int mask)

sys/dev/wscons/wsmouse.c

609

if (*sync & mask) {

sys/dev/wscons/wsmouse.c

621

*sync |= mask;

sys/dev/wscons/wsmouse.c

626

set_y(struct position *pos, int y, u_int *sync, u_int mask)

sys/dev/wscons/wsmouse.c

628

if (*sync & mask) {

sys/dev/wscons/wsmouse.c

640

*sync |= mask;

sys/dev/wscons/wstpad.c

1131

u_int mask;

sys/dev/wscons/wstpad.c

1156

mask = ~0;

sys/dev/wscons/wstpad.c

1160

mask &= (1 << slot);

sys/dev/wscons/wstpad.c

1161

input->mt.ptr_mask = mask;

sys/dev/x86emu/x86emu.c

5063

uint32_t srcval, *shiftreg, mask;

sys/dev/x86emu/x86emu.c

5069

mask = 0x1 << bit;

sys/dev/x86emu/x86emu.c

5070

CONDITIONAL_SET_FLAG(srcval & mask, F_CF);

sys/dev/x86emu/x86emu.c

5076

write_back_long(emu, srcval | mask);

sys/dev/x86emu/x86emu.c

5079

write_back_long(emu, srcval & ~mask);

sys/dev/x86emu/x86emu.c

5082

write_back_long(emu, srcval ^ mask);

sys/dev/x86emu/x86emu.c

5091

uint16_t srcval, *shiftreg, mask;

sys/dev/x86emu/x86emu.c

5097

mask = 0x1 << bit;

sys/dev/x86emu/x86emu.c

5098

CONDITIONAL_SET_FLAG(srcval & mask, F_CF);

sys/dev/x86emu/x86emu.c

5104

write_back_word(emu, srcval | mask);

sys/dev/x86emu/x86emu.c

5107

write_back_word(emu, srcval & ~mask);

sys/dev/x86emu/x86emu.c

5110

write_back_word(emu, srcval ^ mask);

sys/dev/x86emu/x86emu.c

5527

uint32_t srcval, mask;

sys/dev/x86emu/x86emu.c

5536

mask = (0x1 << bit);

sys/dev/x86emu/x86emu.c

5540

write_back_long(emu, srcval | mask);

sys/dev/x86emu/x86emu.c

5543

write_back_long(emu, srcval & ~mask);

sys/dev/x86emu/x86emu.c

5546

write_back_long(emu, srcval ^ mask);

sys/dev/x86emu/x86emu.c

5549

CONDITIONAL_SET_FLAG(srcval & mask, F_CF);

sys/dev/x86emu/x86emu.c

5557

uint16_t srcval, mask;

sys/dev/x86emu/x86emu.c

5566

mask = (0x1 << bit);

sys/dev/x86emu/x86emu.c

5569

write_back_word(emu, srcval | mask);

sys/dev/x86emu/x86emu.c

5572

write_back_word(emu, srcval & ~mask);

sys/dev/x86emu/x86emu.c

5575

write_back_word(emu, srcval ^ mask);

sys/dev/x86emu/x86emu.c

5578

CONDITIONAL_SET_FLAG(srcval & mask, F_CF);

sys/dev/x86emu/x86emu.c

6714

unsigned int res, cnt, mask, cf;

sys/dev/x86emu/x86emu.c

6757

mask = (1 << (cnt - 1)) - 1;

sys/dev/x86emu/x86emu.c

6758

res |= (d >> (9 - cnt)) & mask;

sys/dev/x86emu/x86emu.c

6785

unsigned int res, cnt, mask, cf;

sys/dev/x86emu/x86emu.c

6791

mask = (1 << (cnt - 1)) - 1;

sys/dev/x86emu/x86emu.c

6792

res |= (d >> (17 - cnt)) & mask;

sys/dev/x86emu/x86emu.c

6810

uint32_t res, cnt, mask, cf;

sys/dev/x86emu/x86emu.c

6816

mask = (1 << (cnt - 1)) - 1;

sys/dev/x86emu/x86emu.c

6817

res |= (d >> (33 - cnt)) & mask;

sys/dev/x86emu/x86emu.c

6836

uint32_t mask, cf, ocf = 0;

sys/dev/x86emu/x86emu.c

6878

mask = (1 << (8 - cnt)) - 1;

sys/dev/x86emu/x86emu.c

6879

res = (d >> cnt) & mask;

sys/dev/x86emu/x86emu.c

6914

uint32_t mask, cf, ocf = 0;

sys/dev/x86emu/x86emu.c

6924

mask = (1 << (16 - cnt)) - 1;

sys/dev/x86emu/x86emu.c

6925

res = (d >> cnt) & mask;

sys/dev/x86emu/x86emu.c

6947

uint32_t mask, cf, ocf = 0;

sys/dev/x86emu/x86emu.c

6957

mask = (1 << (32 - cnt)) - 1;

sys/dev/x86emu/x86emu.c

6958

res = (d >> cnt) & mask;

sys/dev/x86emu/x86emu.c

6980

unsigned int res, cnt, mask;

sys/dev/x86emu/x86emu.c

7001

mask = (1 << cnt) - 1;

sys/dev/x86emu/x86emu.c

7002

res |= (d >> (8 - cnt)) & mask;

sys/dev/x86emu/x86emu.c

7027

unsigned int res, cnt, mask;

sys/dev/x86emu/x86emu.c

7032

mask = (1 << cnt) - 1;

sys/dev/x86emu/x86emu.c

7033

res |= (d >> (16 - cnt)) & mask;

sys/dev/x86emu/x86emu.c

7053

uint32_t res, cnt, mask;

sys/dev/x86emu/x86emu.c

7058

mask = (1 << cnt) - 1;

sys/dev/x86emu/x86emu.c

7059

res |= (d >> (32 - cnt)) & mask;

sys/dev/x86emu/x86emu.c

7079

unsigned int res, cnt, mask;

sys/dev/x86emu/x86emu.c

7099

mask = (1 << (8 - cnt)) - 1;

sys/dev/x86emu/x86emu.c

7100

res |= (d >> (cnt)) & mask;

sys/dev/x86emu/x86emu.c

7123

unsigned int res, cnt, mask;

sys/dev/x86emu/x86emu.c

7128

mask = (1 << (16 - cnt)) - 1;

sys/dev/x86emu/x86emu.c

7129

res |= (d >> (cnt)) & mask;

sys/dev/x86emu/x86emu.c

7147

uint32_t res, cnt, mask;

sys/dev/x86emu/x86emu.c

7152

mask = (1 << (32 - cnt)) - 1;

sys/dev/x86emu/x86emu.c

7153

res |= (d >> (cnt)) & mask;

sys/dev/x86emu/x86emu.c

7408

unsigned int cnt, res, cf, mask, sf;

sys/dev/x86emu/x86emu.c

7414

mask = (1 << (8 - cnt)) - 1;

sys/dev/x86emu/x86emu.c

7416

res = (d >> cnt) & mask;

sys/dev/x86emu/x86emu.c

7419

res |= ~mask;

sys/dev/x86emu/x86emu.c

7449

unsigned int cnt, res, cf, mask, sf;

sys/dev/x86emu/x86emu.c

7455

mask = (1 << (16 - cnt)) - 1;

sys/dev/x86emu/x86emu.c

7457

res = (d >> cnt) & mask;

sys/dev/x86emu/x86emu.c

7460

res |= ~mask;

sys/dev/x86emu/x86emu.c

7490

uint32_t cnt, res, cf, mask, sf;

sys/dev/x86emu/x86emu.c

7496

mask = (1 << (32 - cnt)) - 1;

sys/dev/x86emu/x86emu.c

7498

res = (d >> cnt) & mask;

sys/dev/x86emu/x86emu.c

7501

res |= ~mask;

sys/kern/kern_clockintr.c

299

uint32_t mask)

sys/kern/kern_clockintr.c

308

while ((off = (random() & mask)) == 0)

sys/kern/kern_event.c

211

#define KN_HASH(val, mask) (((val) ^ (val >> 8)) & (mask))

sys/kern/kern_ktrace.c

283

ktrpsig(struct proc *p, int sig, sig_t action, int mask, int code,

sys/kern/kern_ktrace.c

293

kp.mask = mask;

sys/kern/kern_sig.c

1028

if (sigignore & mask)

sys/kern/kern_sig.c

1030

if (sigmask & mask) {

sys/kern/kern_sig.c

1032

if (sigcatch & mask)

sys/kern/kern_sig.c

1034

} else if (sigcatch & mask) {

sys/kern/kern_sig.c

1099

mask = 0;

sys/kern/kern_sig.c

1124

mask = 0;

sys/kern/kern_sig.c

1164

if (sigmask & mask)

sys/kern/kern_sig.c

1180

mask = 0;

sys/kern/kern_sig.c

1193

mask = 0;

sys/kern/kern_sig.c

1207

mask = 0;

sys/kern/kern_sig.c

1231

atomic_setbits_int(siglist, mask);

sys/kern/kern_sig.c

1232

mask = 0;

sys/kern/kern_sig.c

1247

if (mask)

sys/kern/kern_sig.c

1248

atomic_setbits_int(siglist, mask);

sys/kern/kern_sig.c

1275

sigset_t mask;

sys/kern/kern_sig.c

1278

mask = sigmask(signum);

sys/kern/kern_sig.c

1281

sctx->sig_reset = (ps->ps_sigreset & mask) != 0;

sys/kern/kern_sig.c

1282

sctx->sig_info = (ps->ps_siginfo & mask) != 0;

sys/kern/kern_sig.c

1283

sctx->sig_intr = (ps->ps_sigintr & mask) != 0;

sys/kern/kern_sig.c

1284

sctx->sig_onstack = (ps->ps_sigonstack & mask) != 0;

sys/kern/kern_sig.c

1285

sctx->sig_ignore = (ps->ps_sigignore & mask) != 0;

sys/kern/kern_sig.c

1286

sctx->sig_catch = (ps->ps_sigcatch & mask) != 0;

sys/kern/kern_sig.c

1324

int signum, mask, keep = 0, prop;

sys/kern/kern_sig.c

1332

mask = SIGPENDING(p);

sys/kern/kern_sig.c

1334

mask &= ~STOPSIGMASK;

sys/kern/kern_sig.c

1335

signum = ffs(mask);

sys/kern/kern_sig.c

1338

mask = sigmask(signum);

sys/kern/kern_sig.c

1342

ps_siglist & ~mask) != ps_siglist) {

sys/kern/kern_sig.c

1346

atomic_clearbits_int(&p->p_siglist, mask);

sys/kern/kern_sig.c

1373

keep |= mask;

sys/kern/kern_sig.c

1388

mask = sigmask(signum);

sys/kern/kern_sig.c

1404

if ((p->p_sigmask & mask) != 0) {

sys/kern/kern_sig.c

1405

atomic_setbits_int(&p->p_siglist, mask);

sys/kern/kern_sig.c

1491

atomic_setbits_int(&p->p_siglist, mask | keep);

sys/kern/kern_sig.c

1735

int mask, returnmask;

sys/kern/kern_sig.c

1742

mask = sigmask(signum);

sys/kern/kern_sig.c

1743

atomic_clearbits_int(&p->p_siglist, mask);

sys/kern/kern_sig.c

1776

if (sctx->sig_action == SIG_IGN || (p->p_sigmask & mask))

sys/kern/kern_sig.c

2096

sigset_t mask = SCARG(uap, sigmask) &~ sigcantmask;

sys/kern/kern_sig.c

2118

dosigsuspend(p, p->p_sigmask &~ mask);

sys/kern/kern_sig.c

2123

if (smask & mask) {

sys/kern/kern_sig.c

414

int nc, mask;

sys/kern/kern_sig.c

426

mask = sigmask(nc);

sys/kern/kern_sig.c

427

ps->ps_sigcatch &= ~mask;

sys/kern/kern_sig.c

430

ps->ps_sigignore |= mask;

sys/kern/kern_sig.c

431

atomic_clearbits_int(&p->p_siglist, mask);

sys/kern/kern_sig.c

432

atomic_clearbits_int(&p->p_p->ps_siglist, mask);

sys/kern/kern_sig.c

458

syscallarg(sigset_t) mask;

sys/kern/kern_sig.c

461

sigset_t mask;

sys/kern/kern_sig.c

466

mask = SCARG(uap, mask) &~ sigcantmask;

sys/kern/kern_sig.c

470

SET(p->p_sigmask, mask);

sys/kern/kern_sig.c

473

CLR(p->p_sigmask, mask);

sys/kern/kern_sig.c

476

p->p_sigmask = mask;

sys/kern/kern_sig.c

515

syscallarg(int) mask;

sys/kern/kern_sig.c

518

dosigsuspend(p, SCARG(uap, mask) &~ sigcantmask);

sys/kern/kern_sig.c

770

sigset_t mask = sigmask(signum);

sys/kern/kern_sig.c

774

ps->ps_sigcatch &= ~mask;

sys/kern/kern_sig.c

776

ps->ps_sigignore |= mask;

sys/kern/kern_sig.c

793

int mask;

sys/kern/kern_sig.c

808

mask = sigmask(signum);

sys/kern/kern_sig.c

811

(p->p_sigmask & mask) == 0) {

sys/kern/kern_sig.c

840

signum != SIGKILL && (p->p_sigmask & mask) != 0) {

sys/kern/kern_sig.c

843

mask = sigmask(signum);

sys/kern/kern_sig.c

870

((p->p_sigmask & mask) || ctx.sig_ignore) &&

sys/kern/kern_sig.c

931

sigset_t mask, sigmask;

sys/kern/kern_sig.c

948

mask = sigmask(signum);

sys/kern/kern_sig.c

956

atomic_setbits_int(&pr->ps_siglist, mask);

sys/kern/kern_sig.c

967

(tmpmask & mask) == 0) {

sys/kern/kern_sig.c

988

if ((tmpmask & mask) != 0)

sys/kern/subr_blist.c

549

u_swblk_t mask;

sys/kern/subr_blist.c

553

mask = (u_swblk_t)-1 >> (BLIST_BMAP_RADIX/2);

sys/kern/subr_blist.c

556

if ((orig & mask) == 0) {

sys/kern/subr_blist.c

561

mask >>= j;

sys/kern/subr_blist.c

576

u_swblk_t mask;

sys/kern/subr_blist.c

578

mask = (u_swblk_t)-1 >> n;

sys/kern/subr_blist.c

581

if ((orig & mask) == mask) {

sys/kern/subr_blist.c

582

scan->u.bmu_bitmap &= ~mask;

sys/kern/subr_blist.c

585

mask = (mask << 1);

sys/kern/subr_blist.c

719

u_swblk_t mask;

sys/kern/subr_blist.c

721

mask = ((u_swblk_t)-1 << n) &

sys/kern/subr_blist.c

724

if (scan->u.bmu_bitmap & mask)

sys/kern/subr_blist.c

726

scan->u.bmu_bitmap |= mask;

sys/kern/subr_blist.c

861

u_swblk_t mask, bitmap;

sys/kern/subr_blist.c

863

mask = ((u_swblk_t)-1 << n) &

sys/kern/subr_blist.c

867

bitmap = scan->u.bmu_bitmap & mask;

sys/kern/subr_blist.c

871

scan->u.bmu_bitmap &= ~mask;

sys/kern/sys_generic.c

569

syscallarg(const sigset_t *) mask;

sys/kern/sys_generic.c

587

if (SCARG(uap, mask) != NULL) {

sys/kern/sys_generic.c

588

if ((error = copyin(SCARG(uap, mask), &ss, sizeof ss)) != 0)

sys/kern/sys_generic.c

894

syscallarg(const sigset_t *) mask;

sys/kern/sys_generic.c

913

if (SCARG(uap, mask) != NULL) {

sys/kern/sys_generic.c

914

if ((error = copyin(SCARG(uap, mask), &ss, sizeof ss)) != 0)

sys/kern/tty_subr.c

274

u_char mask;

sys/kern/tty_subr.c

286

mask = ((1 << (ebi - sbi)) - 1) << sbi;

sys/kern/tty_subr.c

287

cp[sby] &= ~mask;

sys/kern/tty_subr.c

289

mask = (1<<sbi) - 1;

sys/kern/tty_subr.c

290

cp[sby++] &= mask;

sys/kern/tty_subr.c

295

mask = (1<<ebi) - 1;

sys/kern/tty_subr.c

296

if (mask) /* if no mask, eby may be 1 too far */

sys/kern/tty_subr.c

297

cp[eby] &= ~mask;

sys/kern/vfs_subr.c

1631

mode_t mask;

sys/kern/vfs_subr.c

1642

mask = 0;

sys/kern/vfs_subr.c

1647

mask |= S_IXUSR;

sys/kern/vfs_subr.c

1649

mask |= S_IRUSR;

sys/kern/vfs_subr.c

1651

mask |= S_IWUSR;

sys/kern/vfs_subr.c

1652

return (file_mode & mask) == mask ? 0 : EACCES;

sys/kern/vfs_subr.c

1658

mask |= S_IXGRP;

sys/kern/vfs_subr.c

1660

mask |= S_IRGRP;

sys/kern/vfs_subr.c

1662

mask |= S_IWGRP;

sys/kern/vfs_subr.c

1663

return (file_mode & mask) == mask ? 0 : EACCES;

sys/kern/vfs_subr.c

1668

mask |= S_IXOTH;

sys/kern/vfs_subr.c

1670

mask |= S_IROTH;

sys/kern/vfs_subr.c

1672

mask |= S_IWOTH;

sys/kern/vfs_subr.c

1673

return (file_mode & mask) == mask ? 0 : EACCES;

sys/lib/libkern/ctzdi2.c

16

ffsl(long mask)

sys/lib/libkern/ctzdi2.c

19

unsigned long r = mask;

sys/lib/libkern/ctzdi2.c

49

ffsl(long mask)

sys/lib/libkern/ctzdi2.c

51

return ffs(mask);

sys/lib/libkern/ctzdi2.c

56

__ctzdi2(long mask)

sys/lib/libkern/ctzdi2.c

58

if (mask == 0)

sys/lib/libkern/ctzdi2.c

60

return ffsl(mask) - 1;

sys/lib/libkern/ffs.c

14

ffs(int mask)

sys/lib/libkern/ffs.c

17

unsigned int r = mask;

sys/lib/libkern/fls.c

37

fls(int mask)

sys/lib/libkern/fls.c

41

if (mask == 0)

sys/lib/libkern/fls.c

43

for (bit = 1; mask != 1; bit++)

sys/lib/libkern/fls.c

44

mask = (unsigned int)mask >> 1;

sys/lib/libkern/flsl.c

37

flsl(long mask)

sys/lib/libkern/flsl.c

41

if (mask == 0)

sys/lib/libkern/flsl.c

43

for (bit = 1; mask != 1; bit++)

sys/lib/libkern/flsl.c

44

mask = (unsigned long)mask >> 1;

sys/lib/libkern/scanc.c

39

scanc(u_int size, const u_char *cp, const u_char table[], int mask)

sys/lib/libkern/scanc.c

43

while (cp < end && (table[*cp] & (u_char)mask) == 0)

sys/lib/libkern/skpc.c

39

skpc(int mask, size_t size, u_char *cp)

sys/lib/libkern/skpc.c

43

while (cp < end && *cp == (u_char) mask)

sys/lib/libz/inftrees.c

211

mask = used - 1; /* mask for comparing low */

sys/lib/libz/inftrees.c

263

if (len > root && (huff & mask) != low) {

sys/lib/libz/inftrees.c

288

low = huff & mask;

sys/lib/libz/inftrees.c

59

unsigned mask; /* mask for low root bits */

sys/msdosfs/msdosfs_vfsops.c

197

pmp->pm_mask = args->mask;

sys/net/if.c

3396

if_group_routechange(const struct sockaddr *dst, const struct sockaddr *mask)

sys/net/if.c

3401

mask && (mask->sa_len == 0 ||

sys/net/if.c

3402

satosin_const(mask)->sin_addr.s_addr == INADDR_ANY))

sys/net/if.c

3408

&in6addr_any) && mask && (mask->sa_len == 0 ||

sys/net/if.c

3409

IN6_ARE_ADDR_EQUAL(&(satosin6_const(mask))->sin6_addr,

sys/net/if_gre.c

3304

uint32_t mask = GRE_KEY_MASK;

sys/net/if_gre.c

3310

mask = GRE_KEY_ENTROPY;

sys/net/if_gre.c

3319

tunnel->t_key_mask = mask;

sys/net/if_gre.c

3357

uint32_t mask, key;

sys/net/if_gre.c

3362

mask = ifr->ifr_vnetid ? GRE_KEY_ENTROPY : GRE_KEY_MASK;

sys/net/if_gre.c

3363

if (tunnel->t_key_mask == mask) {

sys/net/if_gre.c

3369

if (mask == GRE_KEY_ENTROPY) {

sys/net/if_gre.c

3378

tunnel->t_key_mask = mask;

sys/net/if_gre.c

4166

uint32_t mask;

sys/net/if_gre.c

4182

mask = a->t_key_mask & b->t_key_mask;

sys/net/if_gre.c

4184

ka = a->t_key & mask;

sys/net/if_gre.c

4185

kb = b->t_key & mask;

sys/net/if_gre.c

4511

uint32_t mask = 0;

sys/net/if_gre.c

4535

mask = 1;

sys/net/if_gre.c

4571

mask = 1;

sys/net/if_gre.c

4586

tunnel->t_key_mask = mask; /* set if dstaddr set */

sys/net/if_media.c

380

ifmedia_match(struct ifmedia *ifm, uint64_t target, uint64_t mask)

sys/net/if_media.c

385

match = ifmedia_get(ifm, target, mask);

sys/net/if_media.c

392

ifmedia_get(struct ifmedia *ifm, uint64_t target, uint64_t mask)

sys/net/if_media.c

399

mask = ~mask;

sys/net/if_media.c

402

if ((next->ifm_media & mask) == (target & mask)) {

sys/net/if_media.c

407

target, mask, IFM_INST(match->ifm_media));

sys/net/if_spppsubr.c

2133

u_long mask;

sys/net/if_spppsubr.c

2175

for (i = 0, mask = 1; i < IDX_COUNT; i++, mask <<= 1)

sys/net/if_spppsubr.c

2176

if (sp->lcp.protos & mask && ((cps[i])->flags & CP_LCP) == 0)

sys/net/if_spppsubr.c

2192

u_long mask;

sys/net/if_spppsubr.c

2204

for (i = 0, mask = 1; i < IDX_COUNT; i++, mask <<= 1)

sys/net/if_spppsubr.c

2205

if (sp->lcp.protos & mask && ((cps[i])->flags & CP_LCP) == 0) {

sys/net/if_spppsubr.c

2279

int i, mask;

sys/net/if_spppsubr.c

2281

for (i = 0, mask = 1; i < IDX_COUNT; i++, mask <<= 1)

sys/net/if_spppsubr.c

2282

if (sp->lcp.protos & mask && (cps[i])->flags & CP_NCP)

sys/net/if_spppsubr.c

4746

u_long mask;

sys/net/if_spppsubr.c

4758

for (i = 0, mask = 1; i < IDX_COUNT; i++, mask <<= 1)

sys/net/if_spppsubr.c

4759

if (sp->lcp.protos & mask && ((cps[i])->flags & CP_NCP))

sys/net/pf.c

2617

if (PF_ANEQ(&aw1->v.a.mask, &aw2->v.a.mask, AF_INET6))

sys/net/pf_if.c

470

dyn->pfid_net = pfi_unmask(&aw->v.a.mask);

sys/net/pf_ioctl.c

146

u_int32_t mask;

sys/net/pf_ioctl.c

2836

&psk->psk_src.addr.v.a.mask,

sys/net/pf_ioctl.c

2840

&psk->psk_dst.addr.v.a.mask,

sys/net/pf_ioctl.c

2928

pf_trans_set.mask |= PF_TSET_STATUSIF;

sys/net/pf_ioctl.c

3110

pf_trans_set.mask |= PF_TSET_DEBUG;

sys/net/pf_ioctl.c

3838

&psnk->psnk_src.addr.v.a.mask,

sys/net/pf_ioctl.c

3842

&psnk->psnk_dst.addr.v.a.mask,

sys/net/pf_ioctl.c

3876

pf_trans_set.mask |= PF_TSET_HOSTID;

sys/net/pf_ioctl.c

3948

pf_trans_set.mask |= PF_TSET_REASS;

sys/net/pf_ioctl.c

4000

if (pf_trans_set.mask & PF_TSET_STATUSIF)

sys/net/pf_ioctl.c

4002

if (pf_trans_set.mask & PF_TSET_DEBUG)

sys/net/pf_ioctl.c

4004

if (pf_trans_set.mask & PF_TSET_HOSTID)

sys/net/pf_ioctl.c

4006

if (pf_trans_set.mask & PF_TSET_REASS)

sys/net/pf_ioctl.c

819

PF_MD5_UPD(pfr, addr.v.a.mask.addr32);

sys/net/pf_lb.c

286

rmask = &rpool->addr.v.a.mask;

sys/net/pf_lb.c

332

pf_rand_addr(uint32_t mask)

sys/net/pf_lb.c

336

mask = ~ntohl(mask);

sys/net/pf_lb.c

337

addr = arc4random_uniform(mask + 1);

sys/net/pf_lb.c

350

struct pf_addr *rmask = &rpool->addr.v.a.mask;

sys/net/pf_lb.c

393

rmask = &rpool->addr.v.a.mask;

sys/net/pf_lb.c

726

pf_poolmask(&naddr, &naddr, &r->rdr.addr.v.a.mask,

sys/net/pf_lb.c

840

&r->rdr.addr.v.a.mask);

sys/net/pf_lb.c

847

&r->rdr.addr.v.a.mask, NULL);

sys/net/pf_lb.c

856

&r->dst.addr.v.a.mask, NULL);

sys/net/pf_lb.c

867

&r->nat.addr.v.a.mask, NULL);

sys/net/pf_table.c

1287

union sockaddr_union mask;

sys/net/pf_table.c

1306

pfr_prepare_network(&mask, ke->pfrke_af, ke->pfrke_net);

sys/net/pf_table.c

1307

rn = rn_addroute(&ke->pfrke_sa, &mask, head, ke->pfrke_node, 0);

sys/net/pf_table.c

1317

union sockaddr_union mask;

sys/net/pf_table.c

1335

pfr_prepare_network(&mask, ke->pfrke_af, ke->pfrke_net);

sys/net/pf_table.c

1336

rn = rn_delete(&ke->pfrke_sa, &mask, head, NULL);

sys/net/pf_table.c

1393

union sockaddr_union mask;

sys/net/pf_table.c

1455

pfr_prepare_network(&mask, AF_INET, ke->pfrke_net);

sys/net/pf_table.c

1459

&mask, AF_INET);

sys/net/pf_table.c

1465

pfr_prepare_network(&mask, AF_INET6, ke->pfrke_net);

sys/net/pf_table.c

1469

&mask, AF_INET6);

sys/net/pf_table.c

2617

union sockaddr_union mask;

sys/net/pf_table.c

2773

pfr_prepare_network(&mask, AF_INET, ke2->pfrke_net);

sys/net/pf_table.c

2774

pf_poolmask(addr, addr, SUNION2PF(&mask, af), &pfr_ffaddr, af);

sys/net/pf_table.c

881

union sockaddr_union sa, mask;

sys/net/pf_table.c

901

pfr_prepare_network(&mask, ad->pfra_af, ad->pfra_net);

sys/net/pf_table.c

902

ke = (struct pfr_kentry *)rn_lookup(&sa, &mask, head);

sys/net/pf_table.c

914

union sockaddr_union mask;

sys/net/pf_table.c

931

pfr_prepare_network(&mask, key->pfrke_af, key->pfrke_net);

sys/net/pf_table.c

932

ke = (struct pfr_kentry *)rn_lookup(&key->pfrke_sa, &mask,

sys/net/pfvar.h

189

struct pf_addr mask;

sys/net/pfvar.h

295

&(aw)->v.a.mask, (x), (af))) || \

sys/net/pfvar.h

297

!PF_AZERO(&(aw)->v.a.mask, (af)) && \

sys/net/pfvar.h

299

&(aw)->v.a.mask, (x), (af))))) != \

sys/net/route.c

1203

rt_copysa(const struct sockaddr *src, const struct sockaddr *mask,

sys/net/route.c

1225

plen = rtable_satoplen(src->sa_family, mask);

sys/net/rtable.c

432

const struct sockaddr *mask, const struct sockaddr *gateway, uint8_t prio)

sys/net/rtable.c

447

if (mask == NULL) {

sys/net/rtable.c

451

plen = rtable_satoplen(dst->sa_family, mask);

sys/net/rtable.c

549

const struct sockaddr *mask, const struct sockaddr *gateway, uint8_t prio,

sys/net/rtable.c

564

plen = rtable_satoplen(dst->sa_family, mask);

sys/net/rtable.c

650

const struct sockaddr *mask, struct rtentry *rt)

sys/net/rtable.c

663

plen = rtable_satoplen(dst->sa_family, mask);

sys/net/rtable.c

924

rtable_satoplen(sa_family_t af, const struct sockaddr *mask)

sys/net/rtable.c

942

if (mask == NULL)

sys/net/rtable.c

945

mlen = mask->sa_len;

sys/net/rtable.c

951

ap = (uint8_t *)((uint8_t *)mask) + dp->dom_rtoffset;

sys/net/rtable.c

952

ep = (uint8_t *)((uint8_t *)mask) + mlen;

sys/net/trunklacp.h

278

#define LACP_STATE_EQ(s1, s2, mask) \

sys/net/trunklacp.h

279

((((s1) ^ (s2)) & (mask)) == 0)

sys/net80211/ieee80211.c

1375

uint64_t mask;

sys/net80211/ieee80211.c

1378

mask = rate & IEEE80211_RATE_VAL;

sys/net80211/ieee80211.c

1381

mask |= IFM_IEEE80211_11A;

sys/net80211/ieee80211.c

1384

mask |= IFM_IEEE80211_11B;

sys/net80211/ieee80211.c

1390

mask |= IFM_IEEE80211_11G;

sys/net80211/ieee80211.c

1400

if (rates[i].m == mask)

sys/netinet/in.c

132

in_mask2len(struct in_addr *mask)

sys/netinet/in.c

137

p = (u_char *)mask;

sys/netinet/in.c

138

for (x = 0; x < sizeof(*mask); x++) {

sys/netinet/in.c

143

if (x < sizeof(*mask)) {

sys/netinet/in.c

153

in_len2mask(struct in_addr *mask, int len)

sys/netinet/in.c

158

p = (u_char *)mask;

sys/netinet/in.c

159

bzero(mask, sizeof(*mask));

sys/netinet6/in6.c

129

in6_mask2len(struct in6_addr *mask, u_char *lim0)

sys/netinet6/in6.c

135

if (lim0 == NULL || lim0 - (u_char *)mask > sizeof(*mask))

sys/netinet6/in6.c

136

lim = (u_char *)mask + sizeof(*mask);

sys/netinet6/in6.c

137

for (p = (u_char *)mask; p < lim; x++, p++) {

sys/netinet6/ip6_output.c

405

int mask = 0;

sys/netinet6/ip6_output.c

408

mask |= 0xfc;

sys/netinet6/ip6_output.c

410

mask |= 0x03;

sys/netinet6/ip6_output.c

411

if (mask != 0)

sys/netinet6/ip6_output.c

413

htonl((opt->ip6po_tclass & mask) << 20);

sys/ntfs/ntfs_vnops.c

310

mode_t mask, mode = ap->a_mode;

sys/ntfs/ntfs_vnops.c

333

mask = 0;

sys/ntfs/ntfs_vnops.c

338

mask |= S_IXUSR;

sys/ntfs/ntfs_vnops.c

340

mask |= S_IRUSR;

sys/ntfs/ntfs_vnops.c

342

mask |= S_IWUSR;

sys/ntfs/ntfs_vnops.c

343

return ((ip->i_mp->ntm_mode & mask) == mask ? 0 : EACCES);

sys/ntfs/ntfs_vnops.c

350

mask |= S_IXGRP;

sys/ntfs/ntfs_vnops.c

352

mask |= S_IRGRP;

sys/ntfs/ntfs_vnops.c

354

mask |= S_IWGRP;

sys/ntfs/ntfs_vnops.c

355

return ((ip->i_mp->ntm_mode&mask) == mask ? 0 : EACCES);

sys/ntfs/ntfs_vnops.c

360

mask |= S_IXOTH;

sys/ntfs/ntfs_vnops.c

362

mask |= S_IROTH;

sys/ntfs/ntfs_vnops.c

364

mask |= S_IWOTH;

sys/ntfs/ntfs_vnops.c

365

return ((ip->i_mp->ntm_mode & mask) == mask ? 0 : EACCES);

sys/stand/efi/include/efidebug.h

113

INTN mask,

sys/sys/audioio.h

149

int mask;

sys/sys/audioio.h

166

int mask; /* set */

sys/sys/ktrace.h

123

int mask;

sys/sys/mount.h

190

mode_t mask; /* mask to be applied for msdosfs perms */

sys/sys/syscallargs.h

225

syscallarg(sigset_t) mask;

sys/sys/syscallargs.h

554

syscallarg(const sigset_t *) mask;

sys/sys/syscallargs.h

563

syscallarg(const sigset_t *) mask;

sys/sys/syscallargs.h

567

syscallarg(int) mask;

sys/ufs/ext2fs/ext2fs.h

276

uint32_t mask;

sys/ufs/ext2fs/ext2fs_vfsops.c

1061

u_int32_t mask, tmp;

sys/ufs/ext2fs/ext2fs_vfsops.c

1098

mask = tmp & ~(EXT2F_INCOMPAT_SUPP | EXT4F_RO_INCOMPAT_SUPP);

sys/ufs/ext2fs/ext2fs_vfsops.c

1099

if (mask) {

sys/ufs/ext2fs/ext2fs_vfsops.c

1102

if (mask & incompat[i].mask)

sys/ufs/ext2fs/ext2fs_vfsops.c

1123

if (tmp & ro_compat[i].mask)

sys/ufs/ffs/ffs_subr.c

130

u_char mask;

sys/ufs/ffs/ffs_subr.c

137

mask = 0x0f << ((h & 0x1) << 2);

sys/ufs/ffs/ffs_subr.c

138

return ((cp[h >> 1] & mask) == mask);

sys/ufs/ffs/ffs_subr.c

140

mask = 0x03 << ((h & 0x3) << 1);

sys/ufs/ffs/ffs_subr.c

141

return ((cp[h >> 2] & mask) == mask);

sys/ufs/ffs/ffs_subr.c

143

mask = 0x01 << (h & 0x7);

sys/ufs/ffs/ffs_subr.c

144

return ((cp[h >> 3] & mask) == mask);

sys/uvm/uvm_map.c

3060

vm_prot_t mask;

sys/uvm/uvm_map.c

3168

mask = UVM_ET_ISCOPYONWRITE(iter) ?

sys/uvm/uvm_map.c

3185

if ((iter->protection & mask) == PROT_NONE &&

sys/uvm/uvm_map.c

3203

iter->protection & mask);

usr.bin/apply/apply.c

203

sigset_t mask, omask;

usr.bin/apply/apply.c

217

sigemptyset(&mask);

usr.bin/apply/apply.c

218

sigaddset(&mask, SIGCHLD);

usr.bin/apply/apply.c

219

sigprocmask(SIG_BLOCK, &mask, &omask);

usr.bin/bc/bc.y

281

sigset_t mask;

usr.bin/bc/bc.y

286

sigprocmask(SIG_BLOCK, NULL, &mask);

usr.bin/bc/bc.y

287

sigsuspend(&mask);

usr.bin/compress/main.c

803

mode_t mask = umask(022);

usr.bin/compress/main.c

804

fchmod(fd, DEFFILEMODE & ~mask);

usr.bin/compress/main.c

805

umask(mask);

usr.bin/dig/lib/dns/rdata/in_1/a6_38.c

107

mask = 0xff >> (prefixlen % 8);

usr.bin/dig/lib/dns/rdata/in_1/a6_38.c

108

sr.base[0] &= mask; /* Ensure pad bits are zero. */

usr.bin/dig/lib/dns/rdata/in_1/a6_38.c

30

unsigned char mask;

usr.bin/dig/lib/dns/rdata/in_1/a6_38.c

52

mask = 0xff >> (prefixlen % 8);

usr.bin/dig/lib/dns/rdata/in_1/a6_38.c

53

addr[octets] &= mask;

usr.bin/dig/lib/dns/rdata/in_1/a6_38.c

76

unsigned char mask;

usr.bin/find/function.c

1506

mode_t mask;

usr.bin/find/function.c

1512

mask = S_IFBLK;

usr.bin/find/function.c

1515

mask = S_IFCHR;

usr.bin/find/function.c

1518

mask = S_IFDIR;

usr.bin/find/function.c

1521

mask = S_IFREG;

usr.bin/find/function.c

1524

mask = S_IFLNK;

usr.bin/find/function.c

1527

mask = S_IFIFO;

usr.bin/find/function.c

1530

mask = S_IFSOCK;

usr.bin/find/function.c

1537

new->m_data = mask;

usr.bin/jot/jot.c

138

mask |= STEP;

usr.bin/jot/jot.c

146

mask |= ENDER;

usr.bin/jot/jot.c

154

mask |= BEGIN;

usr.bin/jot/jot.c

166

mask |= REPS;

usr.bin/jot/jot.c

195

switch (mask) { /* Four cases involve both begin and ender. */

usr.bin/jot/jot.c

86

unsigned int mask = 0;

usr.bin/kdump/kdump.c

1427

sigset(psig->mask);

usr.bin/kstat/kstat.c

164

sigset_t empty, mask;

usr.bin/kstat/kstat.c

205

sigemptyset(&mask);

usr.bin/kstat/kstat.c

206

sigaddset(&mask, SIGALRM);

usr.bin/kstat/kstat.c

207

if (sigprocmask(SIG_BLOCK, &mask, NULL) == -1)

usr.bin/less/charset.c

290

unsigned char mask;

usr.bin/less/charset.c

291

mask = (~((1 << (8-len)) - 1)) & 0xFF;

usr.bin/less/charset.c

292

if (s[0] == mask && (s[1] & mask) == 0x80)

usr.bin/make/var.c

1384

#define LOOP(mask, value, do_stuff) \

usr.bin/make/var.c

1386

if ((t[i]->flags & (mask)) == (value)) { \

usr.bin/mandoc/dba.c

210

dba_page_alias(struct dba_array *page, const char *name, uint64_t mask)

usr.bin/mandoc/dba.c

218

maskbyte = mask & NAME_MASK;

usr.bin/mandoc/mandocdb.c

104

uint64_t mask; /* set unless handler returns 0 */

usr.bin/mandoc/mandocdb.c

1122

if ( ! (NAME_TITLE & str->mask))

usr.bin/mandoc/mandocdb.c

1587

if (handler->mask)

usr.bin/mandoc/mandocdb.c

1589

handler->mask, handler->taboo);

usr.bin/mandoc/mandocdb.c

1603

uint64_t mask;

usr.bin/mandoc/mandocdb.c

1605

mask = TYPE_Fa;

usr.bin/mandoc/mandocdb.c

1607

mask |= TYPE_Vt;

usr.bin/mandoc/mandocdb.c

1609

putmdockey(mpage, n->child, mask, 0);

usr.bin/mandoc/mandocdb.c

1682

uint64_t mask;

usr.bin/mandoc/mandocdb.c

1691

mask = TYPE_Fa;

usr.bin/mandoc/mandocdb.c

1693

mask |= TYPE_Vt;

usr.bin/mandoc/mandocdb.c

1694

putmdockey(mpage, n, mask, 0);

usr.bin/mandoc/mandocdb.c

1869

s->mask |= v;

usr.bin/mandoc/mandocdb.c

1877

s->mask = v;

usr.bin/mandoc/mandocdb.c

2076

uint64_t mask;

usr.bin/mandoc/mandocdb.c

2136

dba_page_alias(mpage->dba, key->key, key->mask);

usr.bin/mandoc/mandocdb.c

2143

for (mask = TYPE_Xr; mask <= TYPE_Lb; mask *= 2) {

usr.bin/mandoc/mandocdb.c

2144

if (key->mask & mask)

usr.bin/mandoc/mandocdb.c

64

uint64_t mask; /* bitmask in sequence */

usr.bin/mandoc/roff.c

3263

int mask;

usr.bin/mandoc/roff.c

3272

mask = MPARSE_MDOC | MPARSE_QUICK;

usr.bin/mandoc/roff.c

3279

mask = MPARSE_QUICK;

usr.bin/mandoc/roff.c

3284

if ((r->options & mask) == 0)

usr.bin/mixerctl/mixerctl.c

111

if (m->un.mask & p->infp->un.s.member[i].mask)

usr.bin/mixerctl/mixerctl.c

167

int i, mask;

usr.bin/mixerctl/mixerctl.c

196

mask = 0;

usr.bin/mixerctl/mixerctl.c

204

mask |= p->infp->un.s.member[i].mask;

usr.bin/mixerctl/mixerctl.c

208

m->un.mask = mask;

usr.bin/netstat/route.c

281

struct sockaddr *mask = (struct sockaddr *)&sock2;

usr.bin/netstat/route.c

292

mask = plentosa(sa->sa_family, rt_plen(rt), mask);

usr.bin/netstat/route.c

294

p_addr(sa, mask, rt->rt_flags);

usr.bin/netstat/show.c

242

struct sockaddr *mask, *rti_info[RTAX_MAX];

usr.bin/netstat/show.c

259

mask = rti_info[RTAX_NETMASK];

usr.bin/netstat/show.c

263

p_sockaddr(sa, mask, rtm->rtm_flags, WID_DST(sa->sa_family));

usr.bin/netstat/show.c

318

p_addr(struct sockaddr *sa, struct sockaddr *mask, int flags)

usr.bin/netstat/show.c

320

p_sockaddr(sa, mask, flags, WID_DST(sa->sa_family));

usr.bin/netstat/show.c

330

p_sockaddr(struct sockaddr *sa, struct sockaddr *mask, int flags, int width)

usr.bin/netstat/show.c

358

cp = netname((struct sockaddr *)sa6, mask);

usr.bin/netstat/show.c

364

if ((flags & RTF_HOST) || mask == NULL)

usr.bin/netstat/show.c

367

cp = netname(sa, mask);

usr.bin/netstat/show.c

527

netname4(in_addr_t in, in_addr_t mask)

usr.bin/netstat/show.c

532

mask = ntohl(mask);

usr.bin/netstat/show.c

533

mbits = mask ? 33 - ffs(mask) : 0;

usr.bin/netstat/show.c

534

if (in == INADDR_ANY && mask == INADDR_ANY)

usr.bin/netstat/show.c

553

netname6(struct sockaddr_in6 *sa6, struct sockaddr_in6 *mask)

usr.bin/netstat/show.c

565

if (mask) {

usr.bin/netstat/show.c

566

lim = mask->sin6_len - offsetof(struct sockaddr_in6, sin6_addr);

usr.bin/netstat/show.c

569

for (p = (u_char *)&mask->sin6_addr, i = 0; i < lim; p++) {

usr.bin/netstat/show.c

649

netname(struct sockaddr *sa, struct sockaddr *mask)

usr.bin/netstat/show.c

654

mask->sa_len == 0 ? 0 :

usr.bin/netstat/show.c

655

((struct sockaddr_in *)mask)->sin_addr.s_addr);

usr.bin/netstat/show.c

658

(struct sockaddr_in6 *)mask);

usr.bin/openssl/apps.c

153

unsigned long mask;

usr.bin/openssl/apps.c

968

*flags &= ~ptbl->mask;

usr.bin/signify/fe25519.c

142

crypto_uint32 mask = b;

usr.bin/signify/fe25519.c

143

mask = -mask;

usr.bin/signify/fe25519.c

144

for(i=0;i<32;i++) r->v[i] ^= mask & (x->v[i] ^ r->v[i]);

usr.bin/signify/sc25519.c

32

crypto_uint32 mask;

usr.bin/signify/sc25519.c

43

mask = b - 1;

usr.bin/signify/sc25519.c

45

r->v[i] ^= mask & (r->v[i] ^ t[i]);

usr.bin/sndiod/listen.c

106

omask = umask(mask);

usr.bin/sndiod/listen.c

122

if (sb.st_uid != uid || (sb.st_mode & mask) != 0) {

usr.bin/sndiod/listen.c

83

mode_t mask, omask;

usr.bin/sndiod/listen.c

88

mask = 022;

usr.bin/sndiod/listen.c

92

mask = 077;

usr.bin/sndiod/sock.c

1164

unsigned int size, type, mask;

usr.bin/sndiod/sock.c

1301

mask = f->ctlslot->self;

usr.bin/sndiod/sock.c

1305

if ((c->desc_mask & mask) == 0 ||

usr.bin/sndiod/sock.c

1306

(c->refs_mask & mask) == 0) {

usr.bin/sndiod/sock.c

1313

c->desc_mask &= ~mask;

usr.bin/sndiod/sock.c

1314

c->val_mask &= ~mask;

usr.bin/sndiod/sock.c

1340

c->refs_mask &= ~mask;

usr.bin/sndiod/sock.c

1363

mask = f->ctlslot->self;

usr.bin/sndiod/sock.c

1367

if ((c->val_mask & mask) == 0)

usr.bin/sndiod/sock.c

1369

c->val_mask &= ~mask;

usr.bin/sort/file.c

118

sigset_t mask, oldmask;

usr.bin/sort/file.c

123

sigfillset(&mask);

usr.bin/sort/file.c

124

sigprocmask(SIG_BLOCK, &mask, &oldmask);

usr.bin/ssh/ed25519.c

260

crypto_uint32 mask = b;

usr.bin/ssh/ed25519.c

261

mask = -mask;

usr.bin/ssh/ed25519.c

262

for(i=0;i<32;i++) r->v[i] ^= mask & (x->v[i] ^ r->v[i]);

usr.bin/ssh/ed25519.c

533

crypto_uint32 mask;

usr.bin/ssh/ed25519.c

544

mask = b - 1;

usr.bin/ssh/ed25519.c

546

r->v[i] ^= mask & (r->v[i] ^ t[i]);

usr.bin/ssh/libcrux_mlkem768_sha3.h

1557

uint8_t mask = core_num__u8__wrapping_sub(

usr.bin/ssh/libcrux_mlkem768_sha3.h

1565

(uint32_t)mask) |

usr.bin/ssh/libcrux_mlkem768_sha3.h

1567

(uint32_t)~mask);

usr.bin/ssh/libcrux_mlkem768_sha3.h

5913

int16_t mask = shifted >> 15U;

usr.bin/ssh/libcrux_mlkem768_sha3.h

5914

int16_t shifted_to_positive = mask ^ shifted;

usr.bin/ssh/scp.c

1622

mode_t mode, omode, mask;

usr.bin/ssh/scp.c

1639

mask = umask(0);

usr.bin/ssh/scp.c

1641

mask |= 07000;

usr.bin/ssh/scp.c

1642

(void) umask(mask);

usr.bin/ssh/scp.c

1749

mode &= ~mask;

usr.bin/ssh/scp.c

1902

if (fchmod(ofd, omode & ~mask)) {

usr.bin/ssh/sftp-server.c

1877

long mask;

usr.bin/ssh/sftp-server.c

1943

mask = strtol(optarg, &cp, 8);

usr.bin/ssh/sftp-server.c

1944

if (mask < 0 || mask > 0777 || *cp != '\0' ||

usr.bin/ssh/sftp-server.c

1945

cp == optarg || (mask == 0 && errno != 0))

usr.bin/ssh/sftp-server.c

1947

(void)umask((mode_t)mask);

usr.bin/ssh/sntrup761.c

1720

uint32_t qpart, mask, v = 0x80000000 / m;

usr.bin/ssh/sntrup761.c

1729

mask = crypto_int32_negative_mask(x);

usr.bin/ssh/sntrup761.c

1730

x += mask & (uint32_t)m;

usr.bin/ssh/sntrup761.c

1731

*Q += mask;

usr.bin/ssh/sntrup761.c

1997

int mask, i;

usr.bin/ssh/sntrup761.c

2002

mask = Weightw_mask(ev);

usr.bin/ssh/sntrup761.c

2003

for (i = 0; i < w; ++i) r[i] = ((ev[i] ^ 1) & ~mask) ^ 1;

usr.bin/ssh/sntrup761.c

2004

for (i = w; i < p; ++i) r[i] = ev[i] & ~mask;

usr.bin/ssh/sntrup761.c

2138

int mask, i;

usr.bin/ssh/sntrup761.c

2141

mask = Ciphertexts_diff_mask(c, cnew);

usr.bin/ssh/sntrup761.c

2142

for (i = 0; i < Small_bytes; ++i) r_enc[i] ^= mask & (r_enc[i] ^ rho[i]);

usr.bin/ssh/sntrup761.c

2143

HashSession(k, 1 + mask, r_enc, c);

usr.bin/systat/pftop.c

1160

tb_print_addrw(struct pf_addr_wrap *addr, struct pf_addr *mask, u_int8_t af)

usr.bin/systat/pftop.c

1164

tb_print_addr(&addr->v.a.addr, mask, af);

usr.bin/systat/pftop.c

717

tb_print_addr(struct pf_addr * addr, struct pf_addr * mask, int af)

usr.bin/systat/pftop.c

728

if (mask != NULL) {

usr.bin/systat/pftop.c

729

if (!PF_AZERO(mask, af))

usr.bin/systat/pftop.c

730

tbprintf("/%u", unmask(mask));

usr.bin/systat/pftop.c

75

#define PT_MASK(x) (&(x)->addr.v.a.mask)

usr.bin/telnet/sys_bsd.c

350

sigset_t mask;

usr.bin/telnet/sys_bsd.c

353

sigemptyset(&mask);

usr.bin/telnet/sys_bsd.c

354

sigaddset(&mask, SIGTSTP);

usr.bin/telnet/sys_bsd.c

355

sigprocmask(SIG_UNBLOCK, &mask, NULL);

usr.bin/tmux/grid.c

1001

if (((~attr & attrs[i].mask) &&

usr.bin/tmux/grid.c

1002

(lastattr & attrs[i].mask)) ||

usr.bin/tmux/grid.c

1011

if ((attr & attrs[i].mask) && !(lastattr & attrs[i].mask))

usr.bin/tmux/grid.c

980

u_int mask;

usr.bin/tmux/server.c

113

mode_t mask;

usr.bin/tmux/server.c

129

mask = umask(S_IXUSR|S_IXGRP|S_IRWXO);

usr.bin/tmux/server.c

131

mask = umask(S_IXUSR|S_IRWXG|S_IRWXO);

usr.bin/tmux/server.c

138

umask(mask);

usr.bin/top/top.c

384

sigset_t mask, oldmask;

usr.bin/top/top.c

499

sigemptyset(&mask);

usr.bin/top/top.c

500

sigaddset(&mask, SIGINT);

usr.bin/top/top.c

501

sigaddset(&mask, SIGQUIT);

usr.bin/top/top.c

502

sigaddset(&mask, SIGTSTP);

usr.bin/top/top.c

503

sigprocmask(SIG_BLOCK, &mask, &oldmask);

usr.bin/top/top.c

678

sigset_t mask;

usr.bin/top/top.c

714

sigemptyset(&mask);

usr.bin/top/top.c

715

sigaddset(&mask, SIGTSTP);

usr.bin/top/top.c

716

sigprocmask(SIG_UNBLOCK, &mask, NULL);

usr.bin/vi/common/key.c

229

CHAR_T *chp, mask;

usr.bin/vi/common/key.c

278

for (len = 2, mask = 7 << (SHIFT - 3),

usr.bin/vi/common/key.c

279

cnt = BITS / 3; cnt-- > 0; mask >>= 3, shift -= 3)

usr.bin/vi/common/key.c

280

sp->cname[len++] = octdigit[(ch & mask) >> shift];

usr.bin/wall/ttymsg.c

160

(void) sigemptyset(&mask);

usr.bin/wall/ttymsg.c

161

(void) sigprocmask(SIG_SETMASK, &mask, NULL);

usr.bin/wall/ttymsg.c

65

sigset_t mask;

usr.sbin/amd/amd/nfs_start.c

137

sigprocmask(SIG_BLOCK, mask, NULL);

usr.sbin/amd/amd/nfs_start.c

184

sigset_t mask, omask;

usr.sbin/amd/amd/nfs_start.c

186

sigemptyset(&mask);

usr.sbin/amd/amd/nfs_start.c

187

sigaddset(&mask, SIGINT);

usr.sbin/amd/amd/nfs_start.c

188

sigaddset(&mask, SIGTERM);

usr.sbin/amd/amd/nfs_start.c

189

sigaddset(&mask, SIGCHLD);

usr.sbin/amd/amd/nfs_start.c

190

sigaddset(&mask, SIGHUP);

usr.sbin/amd/amd/nfs_start.c

191

sigprocmask(SIG_BLOCK, &mask, &omask);

usr.sbin/amd/amd/nfs_start.c

262

nsel = do_select(&mask, &omask, fdsn + 1, fdsp, &tvv);

usr.sbin/amd/amd/nfs_start.c

99

do_select(sigset_t *mask, sigset_t *omask, int fds, fd_set *fdp,

usr.sbin/amd/amd/sched.c

107

sigset_t mask, omask;

usr.sbin/amd/amd/sched.c

111

sigemptyset(&mask);

usr.sbin/amd/amd/sched.c

112

sigaddset(&mask, SIGCHLD);

usr.sbin/amd/amd/sched.c

113

sigprocmask(SIG_BLOCK, &mask, &omask);

usr.sbin/authpf/authpf.c

920

memset(&psk.psk_src.addr.v.a.mask, 0xff,

usr.sbin/authpf/authpf.c

921

sizeof(psk.psk_src.addr.v.a.mask));

usr.sbin/authpf/authpf.c

929

memset(&psk.psk_dst.addr.v.a.mask, 0xff,

usr.sbin/authpf/authpf.c

930

sizeof(psk.psk_dst.addr.v.a.mask));

usr.sbin/bgpctl/parser.c

1005

int mask = -1;

usr.sbin/bgpctl/parser.c

1014

mask = strtonum(p + 1, 0, 128, &errstr);

usr.sbin/bgpctl/parser.c

1034

if (mask == -1)

usr.sbin/bgpctl/parser.c

1035

mask = 32;

usr.sbin/bgpctl/parser.c

1036

if (mask > 32)

usr.sbin/bgpctl/parser.c

1040

if (mask == -1)

usr.sbin/bgpctl/parser.c

1041

mask = 128;

usr.sbin/bgpctl/parser.c

1047

applymask(addr, &tmp, mask);

usr.sbin/bgpctl/parser.c

1048

*prefixlen = mask;

usr.sbin/bgpd/chash.c

140

ch_meta_locate(struct ch_group *g, uint64_t mask)

usr.sbin/bgpd/chash.c

145

lookup = g->cg_meta ^ mask;

usr.sbin/bgpd/chash.c

204

uint64_t mask;

usr.sbin/bgpd/chash.c

210

memset(&mask, CH_H3(h), sizeof(mask));

usr.sbin/bgpd/chash.c

213

hits = ch_meta_locate(g, mask);

usr.sbin/bgpd/chash.c

260

uint64_t mask;

usr.sbin/bgpd/chash.c

266

memset(&mask, CH_H3(h), sizeof(mask));

usr.sbin/bgpd/chash.c

268

hits = ch_meta_locate(g, mask);

usr.sbin/bgpd/chash.c

298

uint64_t mask;

usr.sbin/bgpd/chash.c

304

memset(&mask, CH_H3(h), sizeof(mask));

usr.sbin/bgpd/chash.c

306

hits = ch_meta_locate(g, mask);

usr.sbin/bgpd/chash.c

328

uint64_t mask;

usr.sbin/bgpd/chash.c

334

memset(&mask, CH_H3(h), sizeof(mask));

usr.sbin/bgpd/chash.c

336

hits = ch_meta_locate(g, mask);

usr.sbin/bgpd/config.c

526

int mask = 128;

usr.sbin/bgpd/config.c

534

mask = strtonum(p+1, 0, 128, &errstr);

usr.sbin/bgpd/config.c

551

*len = mask;

usr.sbin/bgpd/flowspec.c

541

static char buf[36], bit[17], mask[17];

usr.sbin/bgpd/flowspec.c

579

fmt_flags(val2, bits, mask, sizeof(mask)));

usr.sbin/bgpd/flowspec.c

588

fmt_flags(val, bits, mask, sizeof(mask)));

usr.sbin/bgpd/flowspec.c

593

fmt_flags(val, bits, mask, sizeof(mask)));

usr.sbin/bgpd/kroute.c

2496

mask2prefixlen(sa_family_t af, struct sockaddr *mask)

usr.sbin/bgpd/kroute.c

2500

return mask2prefixlen4((struct sockaddr_in *)mask);

usr.sbin/bgpd/kroute.c

2502

return mask2prefixlen6((struct sockaddr_in6 *)mask);

usr.sbin/bgpd/kroute.c

2690

struct sockaddr_storage prefix, nexthop, mask, ifp, label, mpls;

usr.sbin/bgpd/kroute.c

2772

memset(&mask, 0, sizeof(mask));

usr.sbin/bgpd/kroute.c

2775

memcpy(&mask, sa, salen);

usr.sbin/bgpd/kroute.c

2780

iov[iovcnt].iov_base = &mask;

usr.sbin/bgpd/mrt.c

132

uint8_t aid, mask;

usr.sbin/bgpd/mrt.c

147

mask = in ? CAPA_AP_RECV : CAPA_AP_SEND;

usr.sbin/bgpd/mrt.c

149

if (peer->capa.neg.add_path[0] & mask) {

usr.sbin/bgpd/mrt.c

152

(peer->capa.neg.add_path[aid] & mask)) {

usr.sbin/bgpd/rde_aspa.c

361

ra->mask = hsize - 1;

usr.sbin/bgpd/rde_aspa.c

389

h = hash(cas) & ra->mask;

usr.sbin/bgpd/rde_aspa.c

405

for (i = 0; i <= ra->mask; i++) {

usr.sbin/bgpd/rde_aspa.c

47

uint32_t mask;

usr.sbin/bgpd/rde_aspa.c

90

h = hash(asnum) & ra->mask;

usr.sbin/bgpd/rde_community.c

278

struct community test, mask;

usr.sbin/bgpd/rde_community.c

287

if (fc2c(fc, peer, &test, &mask) == -1)

usr.sbin/bgpd/rde_community.c

292

&mask) == 0)

usr.sbin/bgpd/rde_community.c

33

uint32_t *mask)

usr.sbin/bgpd/rde_community.c

37

if (mask == NULL)

usr.sbin/bgpd/rde_community.c

384

struct community test, mask;

usr.sbin/bgpd/rde_community.c

40

*mask = 0;

usr.sbin/bgpd/rde_community.c

402

if (fc2c(fc, peer, &test, &mask) == -1)

usr.sbin/bgpd/rde_community.c

407

&mask) == 0) {

usr.sbin/bgpd/rde_community.c

56

if (mask)

usr.sbin/bgpd/rde_community.c

57

*mask = UINT32_MAX;

usr.sbin/bgpd/util.c

1003

in_addr_t mask, aa, ba;

usr.sbin/bgpd/util.c

1022

mask = htonl(prefixlen2mask(prefixlen));

usr.sbin/bgpd/util.c

1023

aa = ntohl(a->v4.s_addr & mask);

usr.sbin/bgpd/util.c

1024

ba = ntohl(b->v4.s_addr & mask);

usr.sbin/bgpd/util.c

1071

struct in_addr mask;

usr.sbin/bgpd/util.c

1073

mask.s_addr = htonl(prefixlen2mask(prefixlen));

usr.sbin/bgpd/util.c

1074

dest->s_addr = src->s_addr & mask.s_addr;

usr.sbin/bgpd/util.c

1080

struct in6_addr mask;

usr.sbin/bgpd/util.c

1083

memset(&mask, 0, sizeof(mask));

usr.sbin/bgpd/util.c

1085

mask.s6_addr[i] = 0xff;

usr.sbin/bgpd/util.c

1088

mask.s6_addr[prefixlen / 8] = 0xff00 >> i;

usr.sbin/bgpd/util.c

1091

dest->s6_addr[i] = src->s6_addr[i] & mask.s6_addr[i];

usr.sbin/bgpd/util.c

1317

unsigned int mask, rounded, rounded_size;

usr.sbin/bgpd/util.c

1322

mask = (1U << shift) - 1;

usr.sbin/bgpd/util.c

1323

rounded = size + mask; /* XXX: overflow. */

usr.sbin/bgpd/util.c

1325

rounded_size = rounded & ~mask;

usr.sbin/bgplgd/qs.c

146

int mask;

usr.sbin/bgplgd/qs.c

150

mask = strtonum(p+1, 0, 128, &errstr);

usr.sbin/bgplgd/qs.c

163

if (res->ai_family == AF_INET && mask > 32)

usr.sbin/cron/cron.c

349

cron_sleep(time_t target, sigset_t *mask)

usr.sbin/cron/cron.c

372

nfds = ppoll(pfd, 1, &timeout, mask);

usr.sbin/dhcpd/inet.c

106

if (mask.iabuf[i + j]) {

usr.sbin/dhcpd/inet.c

107

if (habuf[i] > (mask.iabuf[i + j] ^ 0xFF)) {

usr.sbin/dhcpd/inet.c

126

host_addr(struct iaddr addr, struct iaddr mask)

usr.sbin/dhcpd/inet.c

137

rv.iabuf[i] = addr.iabuf[i] & ~mask.iabuf[i];

usr.sbin/dhcpd/inet.c

65

subnet_number(struct iaddr addr, struct iaddr mask)

usr.sbin/dhcpd/inet.c

73

if (addr.len != mask.len)

usr.sbin/dhcpd/inet.c

78

rv.iabuf[i] = addr.iabuf[i] & mask.iabuf[i];

usr.sbin/dhcpd/inet.c

88

ip_addr(struct iaddr subnet, struct iaddr mask, u_int32_t host_address)

usr.sbin/dhcpd/pfutils.c

182

memset(&psk.psk_src.addr.v.a.mask, 0xff,

usr.sbin/dhcpd/pfutils.c

183

sizeof(psk.psk_src.addr.v.a.mask));

usr.sbin/dhcpd/pfutils.c

192

memset(&psk.psk_dst.addr.v.a.mask, 0xff,

usr.sbin/dhcpd/pfutils.c

193

sizeof(psk.psk_dst.addr.v.a.mask));

usr.sbin/dhcpleasectl/dhcpleasectl.c

242

if (inet_ntop(AF_INET, &cei->mask, maskbuf, sizeof(maskbuf))

usr.sbin/dhcpleasectl/dhcpleasectl.c

250

if (inet_ntop(AF_INET, &cei->routes[i].mask, maskbuf,

usr.sbin/dhcpleasectl/dhcpleasectl.c

258

&& cei->routes[i].mask.s_addr == INADDR_ANY)

usr.sbin/dhcpleasectl/dhcpleasectl.c

263

ffs(ntohl(cei->routes[i].mask.s_addr)),

usr.sbin/dvmrpctl/dvmrpctl.c

270

mask2prefixlen(iface->mask.s_addr)) == -1)

usr.sbin/dvmrpctl/dvmrpctl.c

305

mask2prefixlen(iface->mask.s_addr));

usr.sbin/dvmrpctl/dvmrpctl.c

352

mask2prefixlen(iface->mask.s_addr)) == -1)

usr.sbin/dvmrpd/dvmrpd.h

189

struct in_addr mask;

usr.sbin/dvmrpd/dvmrpd.h

270

struct in_addr mask;

usr.sbin/dvmrpd/dvmrpe.h

72

struct in_addr mask;

usr.sbin/dvmrpd/interface.c

213

iface->mask = sain->sin_addr;

usr.sbin/dvmrpd/interface.c

641

memcpy(&ictl.mask, &iface->mask, sizeof(ictl.mask));

usr.sbin/dvmrpd/kmroute.c

50

rr.net.s_addr = iface->addr.s_addr & iface->mask.s_addr;

usr.sbin/dvmrpd/kmroute.c

51

rr.mask = iface->mask;

usr.sbin/dvmrpd/packet.c

294

iface->mask.s_addr) == (src.s_addr &

usr.sbin/dvmrpd/packet.c

295

iface->mask.s_addr) && !iface->passive)

usr.sbin/dvmrpd/rde_srt.c

177

rn->prefixlen = mask2prefixlen(rr->mask.s_addr);

usr.sbin/dvmrpd/rde_srt.c

271

rr.mask.s_addr = ntohl(prefixlen2mask(r->prefixlen));

usr.sbin/dvmrpd/rde_srt.c

349

rr->mask.s_addr = 0;

usr.sbin/dvmrpd/rde_srt.c

361

rn = rt_find(rr->net.s_addr, mask2prefixlen(rr->mask.s_addr));

usr.sbin/dvmrpd/rde_srt.c

606

rr.mask.s_addr = ntohl(prefixlen2mask(rn->prefixlen));

usr.sbin/dvmrpd/rde_srt.c

617

rr.mask.s_addr = ntohl(prefixlen2mask(rn->prefixlen));

usr.sbin/dvmrpd/report.c

134

rr.mask.s_addr = netmask;

usr.sbin/dvmrpd/report.c

247

netmask = le->re->mask.s_addr;

usr.sbin/dvmrpd/report.c

273

if (mask2prefixlen(le2->re->mask.s_addr) !=

usr.sbin/eigrpctl/parser.c

456

int mask = -1;

usr.sbin/eigrpctl/parser.c

466

mask = strtonum(p + 1, 0, 128, &errstr);

usr.sbin/eigrpctl/parser.c

486

if (mask == UINT8_MAX)

usr.sbin/eigrpctl/parser.c

487

mask = 32;

usr.sbin/eigrpctl/parser.c

488

if (mask > 32)

usr.sbin/eigrpctl/parser.c

492

if (mask == UINT8_MAX)

usr.sbin/eigrpctl/parser.c

493

mask = 128;

usr.sbin/eigrpctl/parser.c

494

if (mask > 128)

usr.sbin/eigrpctl/parser.c

500

eigrp_applymask(*family, addr, addr, mask);

usr.sbin/eigrpctl/parser.c

501

*prefixlen = mask;

usr.sbin/eigrpd/kroute.c

1044

struct sockaddr_in mask;

usr.sbin/eigrpd/kroute.c

1093

memset(&mask, 0, sizeof(mask));

usr.sbin/eigrpd/kroute.c

1094

mask.sin_len = sizeof(mask);

usr.sbin/eigrpd/kroute.c

1095

mask.sin_family = AF_INET;

usr.sbin/eigrpd/kroute.c

1096

mask.sin_addr.s_addr = prefixlen2mask(kr->prefixlen);

usr.sbin/eigrpd/kroute.c

1099

hdr.rtm_msglen += sizeof(mask);

usr.sbin/eigrpd/kroute.c

1101

iov[iovcnt].iov_base = &mask;

usr.sbin/eigrpd/kroute.c

1102

iov[iovcnt++].iov_len = sizeof(mask);

usr.sbin/eigrpd/kroute.c

1133

} prefix, nexthop, mask;

usr.sbin/eigrpd/kroute.c

1183

memset(&mask, 0, sizeof(mask));

usr.sbin/eigrpd/kroute.c

1184

mask.addr.sin6_len = sizeof(struct sockaddr_in6);

usr.sbin/eigrpd/kroute.c

1185

mask.addr.sin6_family = AF_INET6;

usr.sbin/eigrpd/kroute.c

1186

mask.addr.sin6_addr = *prefixlen2mask6(kr->prefixlen);

usr.sbin/eigrpd/kroute.c

1193

iov[iovcnt].iov_base = &mask;

usr.sbin/eigrpd/kroute.c

872

if_newaddr(unsigned short ifindex, struct sockaddr *ifa, struct sockaddr *mask,

usr.sbin/eigrpd/kroute.c

891

mask4 = (struct sockaddr_in *) mask;

usr.sbin/eigrpd/kroute.c

909

mask6 = (struct sockaddr_in6 *) mask;

usr.sbin/eigrpd/kroute.c

939

if_deladdr(unsigned short ifindex, struct sockaddr *ifa, struct sockaddr *mask,

usr.sbin/eigrpd/kroute.c

961

mask4 = (struct sockaddr_in *) mask;

usr.sbin/eigrpd/kroute.c

976

mask6 = (struct sockaddr_in6 *) mask;

usr.sbin/eigrpd/packet.c

674

in_addr_t mask;

usr.sbin/eigrpd/packet.c

692

mask = prefixlen2mask(if_addr->prefixlen);

usr.sbin/eigrpd/packet.c

694

if ((if_addr->addr.v4.s_addr & mask) ==

usr.sbin/eigrpd/packet.c

695

(src->v4.s_addr & mask))

usr.sbin/eigrpd/util.c

102

static struct in6_addr mask;

usr.sbin/eigrpd/util.c

105

memset(&mask, 0, sizeof(mask));

usr.sbin/eigrpd/util.c

107

mask.s6_addr[i] = 0xff;

usr.sbin/eigrpd/util.c

110

mask.s6_addr[prefixlen / 8] = 0xff00 >> i;

usr.sbin/eigrpd/util.c

112

return (&mask);

usr.sbin/eigrpd/util.c

119

struct in6_addr mask;

usr.sbin/eigrpd/util.c

127

memset(&mask, 0, sizeof(mask));

usr.sbin/eigrpd/util.c

129

mask.s6_addr[i] = 0xff;

usr.sbin/eigrpd/util.c

132

mask.s6_addr[prefixlen / 8] = 0xff00 >> i;

usr.sbin/eigrpd/util.c

136

mask.s6_addr[i];

usr.sbin/eigrpd/util.c

183

in_addr_t mask, aa, ba;

usr.sbin/eigrpd/util.c

193

mask = htonl(prefixlen2mask(prefixlen));

usr.sbin/eigrpd/util.c

194

aa = htonl(a->v4.s_addr) & mask;

usr.sbin/eigrpd/util.c

195

ba = htonl(b->v4.s_addr) & mask;

usr.sbin/ftp-proxy/filter.c

214

memset(&pfr.rule.src.addr.v.a.mask.addr8, 255, 4);

usr.sbin/ftp-proxy/filter.c

217

memset(&pfr.rule.dst.addr.v.a.mask.addr8, 255, 4);

usr.sbin/ftp-proxy/filter.c

221

memset(&pfr.rule.src.addr.v.a.mask.addr8, 255, 16);

usr.sbin/ftp-proxy/filter.c

224

memset(&pfr.rule.dst.addr.v.a.mask.addr8, 255, 16);

usr.sbin/ftp-proxy/filter.c

58

memset(&pfp->addr.v.a.mask.addr8, 255, 4);

usr.sbin/ftp-proxy/filter.c

62

memset(&pfp->addr.v.a.mask.addr8, 255, 16);

usr.sbin/gpioctl/gpioctl.c

110

char *driver, *offset, *mask;

usr.sbin/gpioctl/gpioctl.c

117

mask = argv[4];

usr.sbin/gpioctl/gpioctl.c

124

lval = strtol(mask, &ep, 0);

usr.sbin/gpioctl/gpioctl.c

125

if (*mask == '\0' || *ep != '\0')

usr.sbin/gpioctl/gpioctl.c

157

fl |= bs->mask;

usr.sbin/gpioctl/gpioctl.c

288

if (set.gp_caps & bs->mask)

usr.sbin/gpioctl/gpioctl.c

292

if (set.gp_flags & bs->mask)

usr.sbin/gpioctl/gpioctl.c

297

if (fl & bs->mask)

usr.sbin/gpioctl/gpioctl.c

319

devattach(char *dvname, int offset, u_int32_t mask, u_int32_t flags)

usr.sbin/gpioctl/gpioctl.c

326

attach.ga_mask = mask;

usr.sbin/gpioctl/gpioctl.c

53

unsigned int mask;

usr.sbin/hostapd/handle.c

74

hostapd_handle_addr(const u_int32_t mask, u_int32_t *flags, u_int8_t *addr,

usr.sbin/hostapd/handle.c

79

if ((*flags & mask) & HOSTAPD_FRAME_TABLE) {

usr.sbin/hostapd/handle.c

85

if ((ret == 1 && (*flags & mask) & HOSTAPD_FRAME_N) ||

usr.sbin/hostapd/handle.c

86

(ret == 0 && ((*flags & mask) & HOSTAPD_FRAME_N) == 0))

usr.sbin/hostapd/handle.c

87

*flags &= ~mask;

usr.sbin/hostapd/parse.y

1034

| mask lladdr

usr.sbin/hostapd/parse.y

1101

mask : '&'

usr.sbin/httpd/httpd.c

894

prefixlen2mask6(uint8_t prefixlen, uint32_t *mask)

usr.sbin/httpd/httpd.c

909

memcpy(mask, &s6, sizeof(s6));

usr.sbin/inetd/inetd.c

815

mode_t mask = 0;

usr.sbin/inetd/inetd.c

860

mask = umask(0111);

usr.sbin/inetd/inetd.c

863

umask(mask);

usr.sbin/installboot/util.c

196

u_int32_t i, byte, crc, mask;

usr.sbin/installboot/util.c

204

mask = -(crc & 1);

usr.sbin/installboot/util.c

205

crc = (crc >> 1) ^ (0xEDB88320 & mask);

usr.sbin/iscsid/iscsid.c

362

int mask;

usr.sbin/iscsid/iscsid.c

369

mask = mine->HeaderDigest & his->HeaderDigest;

usr.sbin/iscsid/iscsid.c

370

mask = ffs(mask) - 1;

usr.sbin/iscsid/iscsid.c

371

if (mask == -1)

usr.sbin/iscsid/iscsid.c

374

res->HeaderDigest = 1 << mask;

usr.sbin/iscsid/iscsid.c

376

mask = mine->DataDigest & his->DataDigest;

usr.sbin/iscsid/iscsid.c

377

mask = ffs(mask) - 1;

usr.sbin/iscsid/iscsid.c

378

if (mask == -1)

usr.sbin/iscsid/iscsid.c

381

res->DataDigest = 1 << mask;

usr.sbin/ldpd/kroute.c

1018

mask4 = (struct sockaddr_in *) mask;

usr.sbin/ldpd/kroute.c

1036

mask6 = (struct sockaddr_in6 *) mask;

usr.sbin/ldpd/kroute.c

1066

if_deladdr(unsigned short ifindex, struct sockaddr *ifa, struct sockaddr *mask,

usr.sbin/ldpd/kroute.c

1088

mask4 = (struct sockaddr_in *) mask;

usr.sbin/ldpd/kroute.c

1103

mask6 = (struct sockaddr_in6 *) mask;

usr.sbin/ldpd/kroute.c

1181

struct sockaddr_in dst, mask, nexthop;

usr.sbin/ldpd/kroute.c

1249

memset(&mask, 0, sizeof(mask));

usr.sbin/ldpd/kroute.c

1250

mask.sin_len = sizeof(mask);

usr.sbin/ldpd/kroute.c

1251

mask.sin_family = AF_INET;

usr.sbin/ldpd/kroute.c

1252

mask.sin_addr.s_addr = prefixlen2mask(kr->prefixlen);

usr.sbin/ldpd/kroute.c

1255

hdr.rtm_msglen += sizeof(mask);

usr.sbin/ldpd/kroute.c

1257

iov[iovcnt].iov_base = &mask;

usr.sbin/ldpd/kroute.c

1258

iov[iovcnt++].iov_len = sizeof(mask);

usr.sbin/ldpd/kroute.c

1316

struct sockaddr_in6 dst, mask, nexthop;

usr.sbin/ldpd/kroute.c

1393

memset(&mask, 0, sizeof(mask));

usr.sbin/ldpd/kroute.c

1394

mask.sin6_len = sizeof(mask);

usr.sbin/ldpd/kroute.c

1395

mask.sin6_family = AF_INET6;

usr.sbin/ldpd/kroute.c

1396

mask.sin6_addr = *prefixlen2mask6(kr->prefixlen);

usr.sbin/ldpd/kroute.c

1401

hdr.rtm_msglen += ROUNDUP(sizeof(mask));

usr.sbin/ldpd/kroute.c

1403

iov[iovcnt].iov_base = &mask;

usr.sbin/ldpd/kroute.c

1404

iov[iovcnt++].iov_len = ROUNDUP(sizeof(mask));

usr.sbin/ldpd/kroute.c

999

if_newaddr(unsigned short ifindex, struct sockaddr *ifa, struct sockaddr *mask,

usr.sbin/ldpd/ldpd.c

1234

in_addr_t mask;

usr.sbin/ldpd/ldpd.c

1244

mask = prefixlen2mask(auth->idlen);

usr.sbin/ldpd/ldpd.c

1245

if ((needle->id.s_addr & mask) != (auth->id.s_addr & mask))

usr.sbin/ldpd/packet.c

267

in_addr_t mask;

usr.sbin/ldpd/packet.c

296

mask = prefixlen2mask(if_addr->prefixlen);

usr.sbin/ldpd/packet.c

297

if ((if_addr->addr.v4.s_addr & mask) ==

usr.sbin/ldpd/packet.c

298

(src->v4.s_addr & mask))

usr.sbin/ldpd/pfkey.c

416

in_addr_t mask = prefixlen2mask(auth->idlen);

usr.sbin/ldpd/pfkey.c

417

if ((auth->id.s_addr & mask) != (nbr->id.s_addr & mask))

usr.sbin/ldpd/util.c

101

static struct in6_addr mask;

usr.sbin/ldpd/util.c

104

memset(&mask, 0, sizeof(mask));

usr.sbin/ldpd/util.c

106

mask.s6_addr[i] = 0xff;

usr.sbin/ldpd/util.c

109

mask.s6_addr[prefixlen / 8] = 0xff00 >> i;

usr.sbin/ldpd/util.c

111

return (&mask);

usr.sbin/ldpd/util.c

118

struct in6_addr mask;

usr.sbin/ldpd/util.c

126

memset(&mask, 0, sizeof(mask));

usr.sbin/ldpd/util.c

128

mask.s6_addr[i] = 0xff;

usr.sbin/ldpd/util.c

131

mask.s6_addr[prefixlen / 8] = 0xff00 >> i;

usr.sbin/ldpd/util.c

135

mask.s6_addr[i];

usr.sbin/ldpd/util.c

182

in_addr_t mask, aa, ba;

usr.sbin/ldpd/util.c

192

mask = htonl(prefixlen2mask(prefixlen));

usr.sbin/ldpd/util.c

193

aa = htonl(a->v4.s_addr) & mask;

usr.sbin/ldpd/util.c

194

ba = htonl(b->v4.s_addr) & mask;

usr.sbin/lpr/lpd/lpd.c

123

sigset_t mask, omask;

usr.sbin/lpr/lpd/lpd.c

257

sigemptyset(&mask);

usr.sbin/lpr/lpd/lpd.c

258

sigaddset(&mask, SIGHUP);

usr.sbin/lpr/lpd/lpd.c

259

sigaddset(&mask, SIGINT);

usr.sbin/lpr/lpd/lpd.c

260

sigaddset(&mask, SIGQUIT);

usr.sbin/lpr/lpd/lpd.c

261

sigaddset(&mask, SIGTERM);

usr.sbin/lpr/lpd/lpd.c

262

sigprocmask(SIG_BLOCK, &mask, &omask);

usr.sbin/makefs/ffs/ffs_alloc.c

406

scanc(u_int size, const u_char *cp, const u_char table[], int mask)

usr.sbin/makefs/ffs/ffs_alloc.c

410

while (cp < end && (table[*cp] & mask) == 0)

usr.sbin/makefs/ffs/ffs_subr.c

56

u_char mask;

usr.sbin/makefs/ffs/ffs_subr.c

62

mask = 0x0f << ((h & 0x1) << 2);

usr.sbin/makefs/ffs/ffs_subr.c

63

return ((cp[h >> 1] & mask) == mask);

usr.sbin/makefs/ffs/ffs_subr.c

65

mask = 0x03 << ((h & 0x3) << 1);

usr.sbin/makefs/ffs/ffs_subr.c

66

return ((cp[h >> 2] & mask) == mask);

usr.sbin/makefs/ffs/ffs_subr.c

68

mask = 0x01 << (h & 0x7);

usr.sbin/makefs/ffs/ffs_subr.c

69

return ((cp[h >> 3] & mask) == mask);

usr.sbin/mrouted/cfparse.y

230

u_int32_t subnet, mask;

usr.sbin/mrouted/cfparse.y

232

mask = $2;

usr.sbin/mrouted/cfparse.y

233

subnet = v->uv_lcl_addr & mask;

usr.sbin/mrouted/cfparse.y

234

if (!inet_valid_subnet(subnet, mask))

usr.sbin/mrouted/cfparse.y

237

v->uv_subnetmask = mask;

usr.sbin/mrouted/cfparse.y

238

v->uv_subnetbcast = subnet | ~mask;

usr.sbin/mrouted/cfparse.y

371

| ADDR { $$.addr = $1; $$.mask = 0; }

usr.sbin/mrouted/cfparse.y

490

yylval.addrmask.mask = n;

usr.sbin/mrouted/cfparse.y

64

int mask;

usr.sbin/mrouted/config.c

105

v->uv_name, inet_fmt(addr, s1), inet_fmts(subnet, mask, s2),

usr.sbin/mrouted/config.c

27

u_int32_t addr, mask, subnet;

usr.sbin/mrouted/config.c

55

mask = ((struct sockaddr_in *)ifa->ifa_netmask)->sin_addr.s_addr;

usr.sbin/mrouted/config.c

56

subnet = addr & mask;

usr.sbin/mrouted/config.c

57

if (!inet_valid_subnet(subnet, mask) ||

usr.sbin/mrouted/config.c

59

addr == (subnet | ~mask)) {

usr.sbin/mrouted/config.c

62

ifa->ifa_name, inet_fmt(addr, s1), inet_fmt(mask, s2));

usr.sbin/mrouted/config.c

72

(v->uv_subnet & mask) == subnet) {

usr.sbin/mrouted/config.c

96

v->uv_subnetmask = mask;

usr.sbin/mrouted/config.c

97

v->uv_subnetbcast = subnet | ~mask;

usr.sbin/mrouted/defs.h

150

extern void update_route(u_int32_t origin, u_int32_t mask,

usr.sbin/mrouted/defs.h

206

extern char * inet_fmts(u_int32_t addr, u_int32_t mask, char *s);

usr.sbin/mrouted/defs.h

210

extern int inet_valid_mask(u_int32_t mask);

usr.sbin/mrouted/defs.h

263

extern int find_src_grp(u_int32_t src, u_int32_t mask,

usr.sbin/mrouted/inet.c

121

inet_fmts(u_int32_t addr, u_int32_t mask, char *s)

usr.sbin/mrouted/inet.c

126

if ((addr == 0) && (mask == 0)) {

usr.sbin/mrouted/inet.c

131

m = (u_char *)&mask;

usr.sbin/mrouted/inet.c

132

bits = 33 - ffs(ntohl(mask));

usr.sbin/mrouted/inet.c

48

inet_valid_mask(u_int32_t mask)

usr.sbin/mrouted/inet.c

50

if (~(((mask & -mask) - 1) | mask) != 0) {

usr.sbin/mrouted/inet.c

70

u_int32_t subnet, mask;

usr.sbin/mrouted/inet.c

73

mask = ntohl(nmask);

usr.sbin/mrouted/inet.c

75

if ((subnet & mask) != subnet) return (FALSE);

usr.sbin/mrouted/inet.c

78

return (mask == 0);

usr.sbin/mrouted/inet.c

81

if (mask < 0xff000000 ||

usr.sbin/mrouted/inet.c

89

if (subnet & ~mask) {

usr.sbin/mrouted/inet.c

93

if (!inet_valid_mask(mask)) {

usr.sbin/mrouted/main.c

266

(void)sigemptyset(&mask);

usr.sbin/mrouted/main.c

267

(void)sigaddset(&mask, SIGALRM);

usr.sbin/mrouted/main.c

268

if (sigprocmask(SIG_BLOCK, &mask, &omask) == -1)

usr.sbin/mrouted/main.c

482

sigset_t mask, omask;

usr.sbin/mrouted/main.c

489

(void)sigemptyset(&mask);

usr.sbin/mrouted/main.c

490

(void)sigaddset(&mask, SIGALRM);

usr.sbin/mrouted/main.c

491

if (sigprocmask(SIG_BLOCK, &mask, &omask) == -1)

usr.sbin/mrouted/main.c

84

sigset_t mask, omask;

usr.sbin/mrouted/prune.c

115

find_src_grp(u_int32_t src, u_int32_t mask, u_int32_t grp)

usr.sbin/mrouted/prune.c

123

(mask ? (gt->gt_route->rt_origin == src &&

usr.sbin/mrouted/prune.c

124

gt->gt_route->rt_originmask == mask) :

usr.sbin/mrouted/prune.c

130

(ntohl(mask) < ntohl(gt->gt_route->rt_originmask) ||

usr.sbin/mrouted/prune.c

131

(mask == gt->gt_route->rt_originmask &&

usr.sbin/mrouted/route.c

1002

if (r->rt_originmask != mask || datalen == 0) {

usr.sbin/mrouted/route.c

1003

mask = r->rt_originmask;

usr.sbin/mrouted/route.c

1006

*p++ = ((char *)&mask)[1];

usr.sbin/mrouted/route.c

1007

*p++ = ((char *)&mask)[2];

usr.sbin/mrouted/route.c

1008

*p++ = ((char *)&mask)[3];

usr.sbin/mrouted/route.c

251

find_route(u_int32_t origin, u_int32_t mask)

usr.sbin/mrouted/route.c

257

if (origin == r->rt_origin && mask == r->rt_originmask) {

usr.sbin/mrouted/route.c

261

if (ntohl(mask) < ntohl(r->rt_originmask) ||

usr.sbin/mrouted/route.c

262

(mask == r->rt_originmask &&

usr.sbin/mrouted/route.c

282

create_route(u_int32_t origin, u_int32_t mask)

usr.sbin/mrouted/route.c

292

r->rt_originmask = mask;

usr.sbin/mrouted/route.c

293

if (((char *)&mask)[3] != 0) r->rt_originwidth = 4;

usr.sbin/mrouted/route.c

294

else if (((char *)&mask)[2] != 0) r->rt_originwidth = 3;

usr.sbin/mrouted/route.c

295

else if (((char *)&mask)[1] != 0) r->rt_originwidth = 2;

usr.sbin/mrouted/route.c

341

update_route(u_int32_t origin, u_int32_t mask, u_int metric, u_int32_t src,

usr.sbin/mrouted/route.c

355

inet_fmt(src, s1), metric, inet_fmts(origin, mask, s2));

usr.sbin/mrouted/route.c

364

if (!find_route(origin, mask)) {

usr.sbin/mrouted/route.c

373

if (src != 0 && !inet_valid_subnet(origin, mask)) {

usr.sbin/mrouted/route.c

376

inet_fmt(src, s1), inet_fmt(origin, s2), ntohl(mask));

usr.sbin/mrouted/route.c

384

create_route(origin, mask);

usr.sbin/mrouted/route.c

44

static int find_route(u_int32_t origin, u_int32_t mask);

usr.sbin/mrouted/route.c

45

static void create_route(u_int32_t origin, u_int32_t mask);

usr.sbin/mrouted/route.c

698

u_int32_t mask;

usr.sbin/mrouted/route.c

709

u_int32_t m1 = ntohl(r1->mask);

usr.sbin/mrouted/route.c

710

u_int32_t m2 = ntohl(r2->mask);

usr.sbin/mrouted/route.c

738

u_int32_t mask;

usr.sbin/mrouted/route.c

766

((u_char *)&mask)[0] = 0xff; width = 1;

usr.sbin/mrouted/route.c

767

if ((((u_char *)&mask)[1] = *p++) != 0) width = 2;

usr.sbin/mrouted/route.c

768

if ((((u_char *)&mask)[2] = *p++) != 0) width = 3;

usr.sbin/mrouted/route.c

769

if ((((u_char *)&mask)[3] = *p++) != 0) width = 4;

usr.sbin/mrouted/route.c

770

if (!inet_valid_mask(ntohl(mask))) {

usr.sbin/mrouted/route.c

773

inet_fmt(src, s1), ntohl(mask), inet_fmt(mask, s2));

usr.sbin/mrouted/route.c

790

rt[nrt].mask = mask;

usr.sbin/mrouted/route.c

803

rt[nrt-1].mask = 0;

usr.sbin/mrouted/route.c

809

rt[i].mask == rt[i-1].mask) {

usr.sbin/mrouted/route.c

811

inet_fmt(src, s1), inet_fmts(rt[i].origin, rt[i].mask, s2));

usr.sbin/mrouted/route.c

814

update_route(rt[i].origin, rt[i].mask, rt[i].metric,

usr.sbin/mrouted/route.c

835

u_int32_t mask = 0;

usr.sbin/mrouted/route.c

869

if (datalen + ((r->rt_originmask == mask) ?

usr.sbin/mrouted/route.c

878

mask = 0;

usr.sbin/mrouted/route.c

881

if (r->rt_originmask != mask || datalen == 0) {

usr.sbin/mrouted/route.c

882

mask = r->rt_originmask;

usr.sbin/mrouted/route.c

885

*p++ = ((char *)&mask)[1];

usr.sbin/mrouted/route.c

886

*p++ = ((char *)&mask)[2];

usr.sbin/mrouted/route.c

887

*p++ = ((char *)&mask)[3];

usr.sbin/mrouted/route.c

970

u_int32_t mask = 0;

usr.sbin/mrouted/route.c

994

if (datalen + ((r->rt_originmask == mask) ?

usr.sbin/mrouted/rsrr.c

108

sigset_t mask, omask;

usr.sbin/mrouted/rsrr.c

119

sigemptyset(&mask);

usr.sbin/mrouted/rsrr.c

120

sigaddset(&mask, SIGALRM);

usr.sbin/mrouted/rsrr.c

121

sigprocmask(SIG_BLOCK, &mask, &omask);

usr.sbin/npppd/common/addr_range.c

133

m0 = 0xffffffff ^ a->mask;

usr.sbin/npppd/common/addr_range.c

134

if (a->mask == b->mask && (

usr.sbin/npppd/common/addr_range.c

145

, INT4_CHARS(a->addr), bitmask2masklen(a->mask)

usr.sbin/npppd/common/addr_range.c

146

, INT4_CHARS(b->addr), bitmask2masklen(b->mask)

usr.sbin/npppd/common/addr_range.c

150

b->mask = m0;

usr.sbin/npppd/common/addr_range.c

157

, INT4_CHARS(a->addr), bitmask2masklen(a->mask)

usr.sbin/npppd/common/addr_range.c

158

, INT4_CHARS(b->addr), bitmask2masklen(b->mask)

usr.sbin/npppd/common/addr_range.c

162

a->mask = m0;

usr.sbin/npppd/common/addr_range.c

178

if ((addr0 & cur->mask) == (cur->addr & cur->mask))

usr.sbin/npppd/common/addr_range.c

186

u_int32_t mask)

usr.sbin/npppd/common/addr_range.c

194

ent->mask = mask;

usr.sbin/npppd/common/addr_range.c

197

if ((ent->addr & (*cur)->mask) ==

usr.sbin/npppd/common/addr_range.c

198

((*cur)->addr & (*cur)->mask)) {

usr.sbin/npppd/common/addr_range.c

203

if ((ent->addr & ent->mask) == ((*cur)->addr & ent->mask)) {

usr.sbin/npppd/common/addr_range.c

224

int is_range = 0, is_masklen = 0, is_maskaddr = 0, mask;

usr.sbin/npppd/common/addr_range.c

243

if (sscanf(p1, "%d", &mask) != 1) {

usr.sbin/npppd/common/addr_range.c

253

if (mask < 0 || 32 < mask) {

usr.sbin/npppd/common/addr_range.c

256

mask);

usr.sbin/npppd/common/addr_range.c

298

if (mask == 0)

usr.sbin/npppd/common/addr_range.c

301

i1 = 0xffffffffL << (32 - mask);

usr.sbin/npppd/common/addr_range.c

333

static int bitmask2masklen(u_int32_t mask)

usr.sbin/npppd/common/addr_range.c

335

switch(mask) {

usr.sbin/npppd/common/addr_range.c

425

, INT4_CHARS(cur->addr), bitmask2masklen(cur->mask)

usr.sbin/npppd/common/addr_range.h

32

u_int32_t mask; // !! Host byte order

usr.sbin/npppd/common/net_utils.c

172

netmask2prefixlen(uint32_t mask)

usr.sbin/npppd/common/net_utils.c

174

switch(mask) {

usr.sbin/npppd/common/radish.c

167

struct sockaddr *mask;

usr.sbin/npppd/common/radish.c

169

mask = rd_mask(m_arg, head, &masklen);

usr.sbin/npppd/common/radish.c

184

new->rd_mask = mask;

usr.sbin/npppd/npppd/ipcp.c

68

#define u32maskcmp(mask, a, b) (((a) & (mask)) == ((b) & (mask)))

usr.sbin/npppd/npppd/npppd_pool.c

164

A(range->addr), netmask2prefixlen(range->mask));

usr.sbin/npppd/npppd/npppd_pool.c

180

A(range->addr), netmask2prefixlen(range->mask));

usr.sbin/npppd/npppd/npppd_pool.c

194

for (i = 0; i <= ~(range->mask); i++) {

usr.sbin/npppd/npppd/npppd_pool.c

229

sin4b.sin_addr.s_addr = htonl(range->mask);

usr.sbin/npppd/npppd/npppd_pool.c

234

snp->snp_mask.s_addr = htonl(range->mask);

usr.sbin/npppd/npppd/npppd_pool.c

256

A(range->addr), netmask2prefixlen(range->mask),

usr.sbin/npppd/npppd/npppd_pool.c

266

A(range->addr), netmask2prefixlen(range->mask));

usr.sbin/npppd/npppd/npppd_pool.c

365

}, mask = {

usr.sbin/npppd/npppd/npppd_pool.c

383

mask.sin_addr = ppp->ppp_framed_ip_netmask;

usr.sbin/npppd/npppd/npppd_pool.c

384

addr.sin_addr.s_addr &= mask.sin_addr.s_addr;

usr.sbin/npppd/npppd/npppd_pool.c

386

if (rd_delete(SA(&addr), SA(&mask), _this->npppd->rd, &rtent) == 0) {

usr.sbin/npppd/npppd/npppd_pool.c

400

(struct sockaddr *)&mask, _this->npppd->rd, &ppp->snp)) != 0) {

usr.sbin/npppd/npppd/npppd_pool.c

420

}, mask = {

usr.sbin/npppd/npppd/npppd_pool.c

432

mask.sin_addr = ppp->ppp_framed_ip_netmask;

usr.sbin/npppd/npppd/npppd_pool.c

433

addr.sin_addr.s_addr &= mask.sin_addr.s_addr;

usr.sbin/npppd/npppd/npppd_pool.c

436

(struct sockaddr *)&mask, ppp->pppd->rd, &item)) != 0) {

usr.sbin/npppd/npppd/npppd_pool.c

457

if (rd_insert(SA(&addr), SA(&mask), ppp->pppd->rd,

usr.sbin/npppd/npppd/npppd_subr.c

132

in_route0(int type, struct in_addr *dest, struct in_addr *mask,

usr.sbin/npppd/npppd/npppd_subr.c

161

if (mask != NULL)

usr.sbin/npppd/npppd/npppd_subr.c

162

smask.sin_addr = *mask;

usr.sbin/npppd/npppd/npppd_subr.c

176

if (mask == NULL)

usr.sbin/npppd/npppd/npppd_subr.c

190

if (mask != NULL)

usr.sbin/npppd/npppd/npppd_subr.c

210

if (mask != NULL) {

usr.sbin/npppd/npppd/npppd_subr.c

287

in_route_add(struct in_addr *dest, struct in_addr *mask, struct in_addr *gate,

usr.sbin/npppd/npppd/npppd_subr.c

290

return in_route0(RTM_ADD, dest, mask, gate, mtu, ifname, rtm_flags);

usr.sbin/npppd/npppd/npppd_subr.c

295

in_route_delete(struct in_addr *dest, struct in_addr *mask,

usr.sbin/npppd/npppd/npppd_subr.c

298

return in_route0(RTM_DELETE, dest, mask, gate, 0, NULL, rtm_flags);

usr.sbin/npppd/npppd/npppd_subr.c

378

struct in_addr dest, mask, loop;

usr.sbin/npppd/npppd/npppd_subr.c

382

mask.s_addr = htonl(range0->mask);

usr.sbin/npppd/npppd/npppd_subr.c

384

in_route_add(&dest, &mask, &loop, LOOPBACK_IFNAME,

usr.sbin/npppd/npppd/npppd_subr.c

394

struct in_addr dest, mask, loop;

usr.sbin/npppd/npppd/npppd_subr.c

398

mask.s_addr = htonl(range0->mask);

usr.sbin/npppd/npppd/npppd_subr.c

401

in_route_delete(&dest, &mask, &loop, RTF_BLACKHOLE);

usr.sbin/nsd/bitset.c

102

mask = (1 << ((srcset2->size % CHAR_BIT) + 1)) - 1;

usr.sbin/nsd/bitset.c

104

bits |= (srcset2->bits[i] & mask);

usr.sbin/nsd/bitset.c

75

unsigned int mask;

usr.sbin/nsd/bitset.c

92

mask = (1 << ((srcset1->size % CHAR_BIT) + 1)) - 1;

usr.sbin/nsd/bitset.c

94

bits |= (srcset1->bits[i] & mask);

usr.sbin/nsd/options.c

2170

acl_addr_match_mask(uint32_t* a, uint32_t* b, uint32_t* mask, size_t sz)

usr.sbin/nsd/options.c

2179

if(((*a++)&*mask) != ((*b++)&*mask))

usr.sbin/nsd/options.c

2181

++mask;

usr.sbin/nsd/options.c

2645

parse_acl_range_type(char* ip, char** mask)

usr.sbin/nsd/options.c

2650

*mask = p+1;

usr.sbin/nsd/options.c

2655

*mask = p+1;

usr.sbin/nsd/options.c

2660

*mask = p+1;

usr.sbin/nsd/options.c

2663

*mask = 0;

usr.sbin/nsd/options.h

602

int acl_addr_match_mask(uint32_t* a, uint32_t* b, uint32_t* mask, size_t sz);

usr.sbin/nsd/options.h

650

int parse_acl_range_type(char* ip, char** mask);

usr.sbin/nsd/simdzone/include/zone.h

455

uint32_t mask;

usr.sbin/nsd/simdzone/include/zone.h

639

(((parser)->options.log.mask & ZONE_ERROR) ? \

usr.sbin/nsd/simdzone/include/zone.h

654

(((parser)->options.mask & ZONE_WARNING) ? \

usr.sbin/nsd/simdzone/include/zone.h

669

(((parser)->options.mask & ZONE_INFO) ? \

usr.sbin/nsd/simdzone/src/fallback/bits.h

15

static really_inline uint64_t trailing_zeroes(uint64_t mask)

usr.sbin/nsd/simdzone/src/fallback/bits.h

18

if (_BitScanForward64(&index, mask))

usr.sbin/nsd/simdzone/src/fallback/bits.h

24

static really_inline uint64_t leading_zeroes(uint64_t mask)

usr.sbin/nsd/simdzone/src/fallback/bits.h

27

if (_BitScanReverse64(&index, mask))

usr.sbin/nsd/simdzone/src/fallback/bits.h

35

static really_inline uint64_t trailing_zeroes(uint64_t mask)

usr.sbin/nsd/simdzone/src/fallback/bits.h

38

return (uint64_t)__builtin_ctzll(mask);

usr.sbin/nsd/simdzone/src/fallback/bits.h

54

return magictable[((mask ^ (mask - 1)) * magic) >> 58];

usr.sbin/nsd/simdzone/src/fallback/bits.h

58

static really_inline uint64_t leading_zeroes(uint64_t mask)

usr.sbin/nsd/simdzone/src/fallback/bits.h

61

return (uint64_t)__builtin_clzll(mask);

usr.sbin/nsd/simdzone/src/fallback/bits.h

77

mask |= mask >> 1;

usr.sbin/nsd/simdzone/src/fallback/bits.h

78

mask |= mask >> 2;

usr.sbin/nsd/simdzone/src/fallback/bits.h

79

mask |= mask >> 4;

usr.sbin/nsd/simdzone/src/fallback/bits.h

80

mask |= mask >> 8;

usr.sbin/nsd/simdzone/src/fallback/bits.h

81

mask |= mask >> 16;

usr.sbin/nsd/simdzone/src/fallback/bits.h

82

mask |= mask >> 32;

usr.sbin/nsd/simdzone/src/fallback/bits.h

84

return magictable[(mask * magic) >> 58];

usr.sbin/nsd/simdzone/src/generic/algorithm.h

137

uint64_t matches, mask, name;

usr.sbin/nsd/simdzone/src/generic/algorithm.h

143

memcpy(&mask, algorithm_hash_map[index].mask + 8, 8);

usr.sbin/nsd/simdzone/src/generic/algorithm.h

145

matches &= (input & mask) == name;

usr.sbin/nsd/simdzone/src/generic/algorithm.h

148

memcpy(&mask, algorithm_hash_map[index].mask + 16, 8);

usr.sbin/nsd/simdzone/src/generic/algorithm.h

150

matches &= (input & mask) == name;

usr.sbin/nsd/simdzone/src/generic/algorithm.h

52

uint8_t mask[24];

usr.sbin/nsd/simdzone/src/generic/gpos.h

102

switch (mask) {

usr.sbin/nsd/simdzone/src/generic/gpos.h

28

int32_t mask = ((digits[0] <= 9) << 0) | // 0b0001

usr.sbin/nsd/simdzone/src/generic/gpos.h

36

switch (mask) {

usr.sbin/nsd/simdzone/src/generic/gpos.h

93

int32_t mask = ((digits[0] <= 9) << 0) | // 0b00001

usr.sbin/nsd/simdzone/src/generic/name.h

101

if (unlikely(block.backslashes & mask)) {

usr.sbin/nsd/simdzone/src/generic/name.h

104

mask = block.backslashes - 1;

usr.sbin/nsd/simdzone/src/generic/name.h

105

block.dots &= mask;

usr.sbin/nsd/simdzone/src/generic/name.h

106

count = count_ones(mask);

usr.sbin/nsd/simdzone/src/generic/name.h

116

block.dots &= mask;

usr.sbin/nsd/simdzone/src/generic/name.h

52

uint64_t mask = (1llu << count) - 1u;

usr.sbin/nsd/simdzone/src/generic/name.h

55

if (unlikely(block.backslashes & mask))

usr.sbin/nsd/simdzone/src/generic/name.h

63

block.dots &= mask;

usr.sbin/nsd/simdzone/src/generic/name.h

97

mask = (1llu << count) - 1u;

usr.sbin/nsd/simdzone/src/generic/text.h

62

uint64_t mask = (1llu << count) - 1u;

usr.sbin/nsd/simdzone/src/generic/text.h

65

if (unlikely(block.backslashes & mask))

usr.sbin/nsd/simdzone/src/generic/text.h

80

mask = (1llu << count) - 1u;

usr.sbin/nsd/simdzone/src/generic/text.h

83

if (unlikely(block.backslashes & mask)) {

usr.sbin/nsd/simdzone/src/generic/text.h

86

mask = block.backslashes - 1;

usr.sbin/nsd/simdzone/src/generic/text.h

87

count = count_ones(mask);

usr.sbin/nsd/simdzone/src/generic/wks.h

100

key &= mask;

usr.sbin/nsd/simdzone/src/generic/wks.h

94

uint64_t mask;

usr.sbin/nsd/simdzone/src/generic/wks.h

96

memcpy(&mask, zero_mask, 8);

usr.sbin/nsd/simdzone/src/haswell/bits.h

45

__m128i mask = _mm_set_epi64x(0ULL, (long long)bitmask);

usr.sbin/nsd/simdzone/src/haswell/bits.h

51

: [mask] "+x" (mask)

usr.sbin/nsd/simdzone/src/haswell/bits.h

56

mask = _mm_clmulepi64_si128(mask, all_ones, 0);

usr.sbin/nsd/simdzone/src/haswell/bits.h

58

return (uint64_t)_mm_cvtsi128_si64(mask);

usr.sbin/nsd/simdzone/src/westmere/bits.h

30

static inline uint64_t trailing_zeroes(uint64_t mask) {

usr.sbin/nsd/simdzone/src/westmere/bits.h

32

return (uint64_t)__builtin_ctzll(mask);

usr.sbin/nsd/simdzone/src/westmere/bits.h

37

: [mask] "mr" (mask));

usr.sbin/nsd/simdzone/src/westmere/bits.h

47

static inline uint64_t leading_zeroes(uint64_t mask) {

usr.sbin/nsd/simdzone/src/westmere/bits.h

49

return (uint64_t)__builtin_clzll(mask);

usr.sbin/nsd/simdzone/src/westmere/bits.h

54

[mask] "mr" (mask));

usr.sbin/nsd/simdzone/src/zone.c

500

if (!(priority & ~parser->options.log.mask))

usr.sbin/ospf6ctl/parser.c

357

int mask;

usr.sbin/ospf6ctl/parser.c

363

mask = strtonum(p + 1, 0, 128, &errstr);

usr.sbin/ospf6ctl/parser.c

377

inet6applymask(addr, addr, mask);

usr.sbin/ospf6ctl/parser.c

378

*prefixlen = mask;

usr.sbin/ospf6d/kroute.c

1038

if_deladdr(u_short ifindex, struct sockaddr_in6 *ifa, struct sockaddr_in6 *mask,

usr.sbin/ospf6d/kroute.c

1117

} prefix, nexthop, mask;

usr.sbin/ospf6d/kroute.c

1198

bzero(&mask, sizeof(mask));

usr.sbin/ospf6d/kroute.c

1199

mask.addr.sin6_len = sizeof(struct sockaddr_in6);

usr.sbin/ospf6d/kroute.c

1200

mask.addr.sin6_family = AF_INET6;

usr.sbin/ospf6d/kroute.c

1201

mask.addr.sin6_addr = *prefixlen2mask(kroute->prefixlen);

usr.sbin/ospf6d/kroute.c

1208

iov[iovcnt].iov_base = &mask;

usr.sbin/ospf6d/kroute.c

964

if_newaddr(u_short ifindex, struct sockaddr_in6 *ifa, struct sockaddr_in6 *mask,

usr.sbin/ospf6d/kroute.c

998

if (mask)

usr.sbin/ospf6d/kroute.c

999

ia->prefixlen = mask2prefixlen(mask);

usr.sbin/ospf6d/parse.y

1301

int mask;

usr.sbin/ospf6d/parse.y

1307

mask = strtonum(p + 1, 0, 128, &errstr);

usr.sbin/ospf6d/parse.y

1320

inet6applymask(addr, addr, mask);

usr.sbin/ospf6d/parse.y

1321

*plen = mask;

usr.sbin/ospf6d/rde.c

1741

lsa->data.sum.mask = prefixlen2mask(rte->prefixlen);

usr.sbin/ospf6d/rde.c

1743

lsa->data.sum.mask = 0; /* must be zero per RFC */

usr.sbin/ospf6d/util.c

146

static struct in6_addr mask;

usr.sbin/ospf6d/util.c

149

bzero(&mask, sizeof(mask));

usr.sbin/ospf6d/util.c

151

mask.s6_addr[i] = 0xff;

usr.sbin/ospf6d/util.c

154

mask.s6_addr[prefixlen / 8] = 0xff00 >> i;

usr.sbin/ospf6d/util.c

156

return (&mask);

usr.sbin/ospf6d/util.c

162

struct in6_addr mask;

usr.sbin/ospf6d/util.c

165

bzero(&mask, sizeof(mask));

usr.sbin/ospf6d/util.c

167

mask.s6_addr[i] = 0xff;

usr.sbin/ospf6d/util.c

170

mask.s6_addr[prefixlen / 8] = 0xff00 >> i;

usr.sbin/ospf6d/util.c

173

dest->s6_addr[i] = src->s6_addr[i] & mask.s6_addr[i];

usr.sbin/ospfctl/output.c

156

mask2prefixlen(iface->mask.s_addr)) == -1)

usr.sbin/ospfctl/output.c

165

mask2prefixlen(iface->mask.s_addr));

usr.sbin/ospfctl/output.c

547

addr.s_addr = lsa->data.asext.mask;

usr.sbin/ospfctl/output.c

564

addr.s_addr = lsa->data.net.mask;

usr.sbin/ospfctl/output.c

634

addr.s_addr = lsa->data.sum.mask;

usr.sbin/ospfd/hello.c

137

if (hello.mask != iface->mask.s_addr) {

usr.sbin/ospfd/hello.c

74

hello.mask = iface->mask.s_addr;

usr.sbin/ospfd/interface.c

209

iface->mask = ka->mask;

usr.sbin/ospfd/interface.c

595

memcpy(&ictl.mask, &iface->mask, sizeof(ictl.mask));

usr.sbin/ospfd/kroute.c

1094

if_newaddr(u_short ifindex, struct sockaddr_in *ifa, struct sockaddr_in *mask,

usr.sbin/ospfd/kroute.c

1110

if (mask)

usr.sbin/ospfd/kroute.c

1111

ka->mask = mask->sin_addr;

usr.sbin/ospfd/kroute.c

1113

ka->mask.s_addr = INADDR_NONE;

usr.sbin/ospfd/kroute.c

1122

ifn.mask = ka->mask;

usr.sbin/ospfd/kroute.c

1129

if_deladdr(u_short ifindex, struct sockaddr_in *ifa, struct sockaddr_in *mask,

usr.sbin/ospfd/kroute.c

1187

struct sockaddr_in mask;

usr.sbin/ospfd/kroute.c

1236

bzero(&mask, sizeof(mask));

usr.sbin/ospfd/kroute.c

1237

mask.sin_len = sizeof(mask);

usr.sbin/ospfd/kroute.c

1238

mask.sin_family = AF_INET;

usr.sbin/ospfd/kroute.c

1239

mask.sin_addr.s_addr = prefixlen2mask(kroute->prefixlen);

usr.sbin/ospfd/kroute.c

1242

hdr.rtm_msglen += sizeof(mask);

usr.sbin/ospfd/kroute.c

1244

iov[iovcnt].iov_base = &mask;

usr.sbin/ospfd/kroute.c

1245

iov[iovcnt++].iov_len = sizeof(mask);

usr.sbin/ospfd/ospf.h

149

u_int32_t mask;

usr.sbin/ospfd/ospf.h

231

u_int32_t mask;

usr.sbin/ospfd/ospf.h

240

u_int32_t mask;

usr.sbin/ospfd/ospf.h

245

u_int32_t mask;

usr.sbin/ospfd/ospfd.c

609

r->mask.s_addr == INADDR_ANY) {

usr.sbin/ospfd/ospfd.c

618

if ((kr->prefix.s_addr & r->mask.s_addr) ==

usr.sbin/ospfd/ospfd.c

619

(r->addr.s_addr & r->mask.s_addr) &&

usr.sbin/ospfd/ospfd.c

620

kr->prefixlen >= mask2prefixlen(r->mask.s_addr)) {

usr.sbin/ospfd/ospfd.c

934

i->mask.s_addr == iface->mask.s_addr)

usr.sbin/ospfd/ospfd.h

151

struct in_addr mask;

usr.sbin/ospfd/ospfd.h

336

struct in_addr mask;

usr.sbin/ospfd/ospfd.h

371

struct in_addr mask;

usr.sbin/ospfd/ospfd.h

428

struct in_addr mask;

usr.sbin/ospfd/ospfd.h

460

struct in_addr mask;

usr.sbin/ospfd/ospfe.c

1142

if (ibuf_add(buf, &iface->mask, sizeof(iface->mask)))

usr.sbin/ospfd/ospfe.c

366

iface->mask = ifc->mask;

usr.sbin/ospfd/ospfe.c

911

iface->mask.s_addr;

usr.sbin/ospfd/ospfe.c

912

rtr_link.data = iface->mask.s_addr;

usr.sbin/ospfd/ospfe.c

964

iface->addr.s_addr & iface->mask.s_addr;

usr.sbin/ospfd/ospfe.c

965

rtr_link.data = iface->mask.s_addr;

usr.sbin/ospfd/packet.c

351

(iface->addr.s_addr & iface->mask.s_addr) ==

usr.sbin/ospfd/packet.c

352

(src.s_addr & iface->mask.s_addr) &&

usr.sbin/ospfd/parse.y

1492

host(const char *s, struct in_addr *addr, struct in_addr *mask)

usr.sbin/ospfd/parse.y

1507

mask->s_addr = prefixlen2mask(bits);

usr.sbin/ospfd/parse.y

312

r->mask.s_addr = prefixlen2mask($5);

usr.sbin/ospfd/parse.y

337

else if (host($3, &r->addr, &r->mask)) {

usr.sbin/ospfd/printconf.c

96

mask2prefixlen(r->mask.s_addr));

usr.sbin/ospfd/rde.c

1184

if ((iface->addr.s_addr & iface->mask.s_addr) ==

usr.sbin/ospfd/rde.c

1185

(prefix & iface->mask.s_addr) && (plen == -1 ||

usr.sbin/ospfd/rde.c

1186

iface->mask.s_addr == prefixlen2mask(plen)))

usr.sbin/ospfd/rde.c

1199

u_int32_t mask;

usr.sbin/ospfd/rde.c

1229

mask = prefixlen2mask(oan->r.prefixlen);

usr.sbin/ospfd/rde.c

1232

while (v && v->lsa->data.asext.mask != mask) {

usr.sbin/ospfd/rde.c

1234

if (ntohl(v->lsa->data.asext.mask) < ntohl(mask)) {

usr.sbin/ospfd/rde.c

1236

mask = v->lsa->data.asext.mask;

usr.sbin/ospfd/rde.c

1237

oan = asext_find(v->lsa->hdr.ls_id & mask,

usr.sbin/ospfd/rde.c

1238

mask2prefixlen(mask));

usr.sbin/ospfd/rde.c

1244

oan->ls_id |= ~mask;

usr.sbin/ospfd/rde.c

1257

mask = prefixlen2mask(oan->r.prefixlen);

usr.sbin/ospfd/rde.c

1349

lsa->data.asext.mask = prefixlen2mask(kr->prefixlen);

usr.sbin/ospfd/rde.c

1473

lsa->data.sum.mask = prefixlen2mask(rte->prefixlen);

usr.sbin/ospfd/rde.c

1475

lsa->data.sum.mask = 0; /* must be zero per RFC */

usr.sbin/ospfd/rde_spf.c

222

addr.s_addr = htonl(v->ls_id) & v->lsa->data.net.mask;

usr.sbin/ospfd/rde_spf.c

224

rt_update(addr, mask2prefixlen(v->lsa->data.net.mask),

usr.sbin/ospfd/rde_spf.c

258

addr.s_addr = htonl(v->ls_id) & v->lsa->data.sum.mask;

usr.sbin/ospfd/rde_spf.c

259

rt_update(addr, mask2prefixlen(v->lsa->data.sum.mask),

usr.sbin/ospfd/rde_spf.c

327

addr.s_addr = htonl(v->ls_id) & v->lsa->data.asext.mask;

usr.sbin/ospfd/rde_spf.c

346

rt_update(addr, mask2prefixlen(v->lsa->data.asext.mask),

usr.sbin/ospfd/rde_spf.c

405

dst->lsa->data.net.mask) ==

usr.sbin/ospfd/rde_spf.c

407

dst->lsa->data.net.mask)) {

usr.sbin/ospfd/rde_spf.c

432

parent->lsa->data.net.mask) ==

usr.sbin/ospfd/rde_spf.c

434

parent->lsa->data.net.mask))

usr.sbin/pcidump/pcidump.c

751

u_int64_t mask;

usr.sbin/pcidump/pcidump.c

787

mask = reg1;

usr.sbin/pcidump/pcidump.c

794

mask |= (u_int64_t)reg1 << 32;

usr.sbin/pcidump/pcidump.c

798

PCI_MAPREG_MEM64_SIZE(mask));

usr.sbin/pppd/auth.c

1021

mask = ~ (u_int32_t) 0;

usr.sbin/pppd/auth.c

1034

mask <<= 32 - bit_count;

usr.sbin/pppd/auth.c

1046

mask = IN_CLASSA_NET;

usr.sbin/pppd/auth.c

1048

mask = IN_CLASSB_NET;

usr.sbin/pppd/auth.c

1050

mask = IN_CLASSC_NET;

usr.sbin/pppd/auth.c

1064

if (((addr ^ ina.s_addr) & htonl(mask)) == 0)

usr.sbin/pppd/auth.c

994

u_int32_t mask, ah;

usr.sbin/pppd/ipcp.c

1125

u_int32_t mask;

usr.sbin/pppd/ipcp.c

1181

mask = GetMask(go->ouraddr);

usr.sbin/pppd/ipcp.c

1182

if (!sifaddr(f->unit, go->ouraddr, ho->hisaddr, mask)) {

usr.sbin/pppd/ipcp.c

1206

mask = GetMask(go->ouraddr);

usr.sbin/pppd/ipcp.c

1209

if (!sifaddr(f->unit, go->ouraddr, ho->hisaddr, mask)) {

usr.sbin/pppd/ipcp.c

1224

if (!sifaddr(f->unit, go->ouraddr, ho->hisaddr, mask)) {

usr.sbin/pppd/main.c

183

sigset_t mask;

usr.sbin/pppd/main.c

301

sigemptyset(&mask);

usr.sbin/pppd/main.c

302

sigaddset(&mask, SIGHUP);

usr.sbin/pppd/main.c

303

sigaddset(&mask, SIGINT);

usr.sbin/pppd/main.c

304

sigaddset(&mask, SIGTERM);

usr.sbin/pppd/main.c

305

sigaddset(&mask, SIGCHLD);

usr.sbin/pppd/main.c

315

sa.sa_mask = mask;

usr.sbin/pppd/pppstats/pppstats.c

161

sigset_t oldmask, mask;

usr.sbin/pppd/pppstats/pppstats.c

287

sigemptyset(&mask);

usr.sbin/pppd/pppstats/pppstats.c

288

sigaddset(&mask, SIGALRM);

usr.sbin/pppd/pppstats/pppstats.c

289

sigprocmask(SIG_BLOCK, &mask, &oldmask);

usr.sbin/pppd/pppstats/pppstats.c

291

sigemptyset(&mask);

usr.sbin/pppd/pppstats/pppstats.c

292

sigsuspend(&mask);

usr.sbin/pppd/sys-bsd.c

1080

struct sockaddr_in mask;

usr.sbin/pppd/sys-bsd.c

1101

rtmsg.mask.sin_len = sizeof(rtmsg.mask);

usr.sbin/pppd/sys-bsd.c

1102

rtmsg.mask.sin_family = AF_INET;

usr.sbin/pppd/sys-bsd.c

1281

u_int32_t ina, mask;

usr.sbin/pppd/sys-bsd.c

1310

mask = ((struct sockaddr_in *)ifa->ifa_netmask)->sin_addr.s_addr;

usr.sbin/pppd/sys-bsd.c

1311

if ((ipaddr & mask) != (ina & mask))

usr.sbin/pppd/sys-bsd.c

1358

u_int32_t mask, nmask, ina;

usr.sbin/pppd/sys-bsd.c

1369

mask = netmask | htonl(nmask);

usr.sbin/pppd/sys-bsd.c

1376

return mask;

usr.sbin/pppd/sys-bsd.c

1397

mask |= ((struct sockaddr_in *)ifa->ifa_netmask)->sin_addr.s_addr;

usr.sbin/pppd/sys-bsd.c

1401

return mask;

usr.sbin/pstat/pstat.c

239

uint32_t mask = ~0;

usr.sbin/pstat/pstat.c

252

mask = 0xff;

usr.sbin/pstat/pstat.c

272

mask = 0xffff;

usr.sbin/pstat/pstat.c

274

mask = 0xff;

usr.sbin/pstat/pstat.c

326

switch (mask) {

usr.sbin/pstat/pstat.c

338

printf(format, ((uint32_t)v) & mask);

usr.sbin/radiusd/parse.y

208

client0->mask = $3.mask;

usr.sbin/radiusd/parse.y

263

$$.mask.addr.ipv4.s_addr = htonl((uint32_t)

usr.sbin/radiusd/parse.y

274

memset(&$$.mask.addr.ipv6, 0,

usr.sbin/radiusd/parse.y

275

sizeof($$.mask.addr.ipv6));

usr.sbin/radiusd/parse.y

277

memset(&$$.mask.addr.ipv6, 0xff, q);

usr.sbin/radiusd/parse.y

279

*((u_char *)&$$.mask.addr.ipv6 + q) =

usr.sbin/radiusd/parse.y

89

struct radiusd_addr mask;

usr.sbin/radiusd/radiusd.c

466

&in(peer), &client->addr, &client->mask))

usr.sbin/radiusd/radiusd.c

469

&in6(peer), &client->addr, &client->mask))

usr.sbin/radiusd/radiusd_ipcp.c

1883

uint32_t mask;

usr.sbin/radiusd/radiusd_ipcp.c

1914

mask = 0xFFFFFFFFUL;

usr.sbin/radiusd/radiusd_ipcp.c

1916

mask <<= (32 - masklen);

usr.sbin/radiusd/radiusd_ipcp.c

1917

start.s_addr = ntohl(start.s_addr) & mask;

usr.sbin/radiusd/radiusd_local.h

68

struct radiusd_addr mask;

usr.sbin/relayd/pfe_filter.c

232

memset(&psnk.psnk_dst.addr.v.a.mask, 0xff,

usr.sbin/relayd/pfe_filter.c

233

sizeof(psnk.psnk_dst.addr.v.a.mask));

usr.sbin/relayd/pfe_filter.c

436

rio.rule.dst.addr.v.a.mask.addr32[0] = 0xffffffff;

usr.sbin/relayd/pfe_filter.c

443

memset(&rio.rule.dst.addr.v.a.mask.addr8, 0xff, 16);

usr.sbin/relayd/pfe_route.c

128

struct sockaddr_storage dst, gw, mask, label;

usr.sbin/relayd/pfe_route.c

149

pfe_apply_prefixlen(&mask, dst.ss_family, crt->nr.prefixlen);

usr.sbin/relayd/pfe_route.c

159

iov[iovcnt].iov_base = &mask;

usr.sbin/relayd/pfe_route.c

160

iov[iovcnt++].iov_len = ROUNDUP(mask.ss_len);

usr.sbin/relayd/pfe_route.c

161

hdr.rtm_msglen += ROUNDUP(mask.ss_len);

usr.sbin/relayd/relayd.c

1849

prefixlen2mask6(u_int8_t prefixlen, u_int32_t *mask)

usr.sbin/relayd/relayd.c

1864

memcpy(mask, &s6, sizeof(s6));

usr.sbin/ripctl/ripctl.c

320

mask2prefixlen(iface->mask.s_addr)) == -1)

usr.sbin/ripd/interface.c

441

iface->mask = sain->sin_addr;

usr.sbin/ripd/interface.c

481

memcpy(&ictl.mask, &iface->mask, sizeof(ictl.mask));

usr.sbin/ripd/kroute.c

727

struct sockaddr_in mask;

usr.sbin/ripd/kroute.c

772

bzero(&mask, sizeof(mask));

usr.sbin/ripd/kroute.c

773

mask.sin_len = sizeof(mask);

usr.sbin/ripd/kroute.c

774

mask.sin_family = AF_INET;

usr.sbin/ripd/kroute.c

775

mask.sin_addr.s_addr = kroute->netmask.s_addr;

usr.sbin/ripd/kroute.c

778

hdr.rtm_msglen += sizeof(mask);

usr.sbin/ripd/kroute.c

780

iov[iovcnt].iov_base = &mask;

usr.sbin/ripd/kroute.c

781

iov[iovcnt++].iov_len = sizeof(mask);

usr.sbin/ripd/message.c

126

netmask = rr->mask.s_addr;

usr.sbin/ripd/message.c

194

netmask = entry->rr->mask.s_addr;

usr.sbin/ripd/message.c

275

netmask = entry->rr->mask.s_addr;

usr.sbin/ripd/message.c

288

if ((nexthop & iface->mask.s_addr) !=

usr.sbin/ripd/message.c

289

(iface->addr.s_addr & iface->mask.s_addr))

usr.sbin/ripd/message.c

362

rr.mask.s_addr = e->mask;

usr.sbin/ripd/message.c

416

r.mask.s_addr = e->mask;

usr.sbin/ripd/message.c

419

((i->addr.s_addr & i->mask.s_addr) !=

usr.sbin/ripd/message.c

420

(e->nexthop & i->mask.s_addr)))

usr.sbin/ripd/packet.c

244

if ((iface->addr.s_addr & iface->mask.s_addr) ==

usr.sbin/ripd/packet.c

245

(src.s_addr & iface->mask.s_addr))

usr.sbin/ripd/parse.y

224

else if (host($3, &r->addr, &r->mask))

usr.sbin/ripd/parse.y

924

host(const char *s, struct in_addr *addr, struct in_addr *mask)

usr.sbin/ripd/parse.y

939

mask->s_addr = prefixlen2mask(bits);

usr.sbin/ripd/printconf.c

93

mask2prefixlen(r->mask.s_addr));

usr.sbin/ripd/rde.c

416

if ((rn = rt_find(e->address.s_addr, e->mask.s_addr)) == NULL) {

usr.sbin/ripd/rde.c

476

rr.mask.s_addr = rn->netmask.s_addr;

usr.sbin/ripd/rde_rib.c

179

rn->netmask.s_addr = e->mask.s_addr;

usr.sbin/ripd/rde_rib.c

224

rr.mask = r->netmask;

usr.sbin/ripd/rde_rib.c

257

if ((rn = rt_find(rr->address.s_addr, rr->mask.s_addr)) == NULL)

usr.sbin/ripd/rip.h

60

u_int32_t mask;

usr.sbin/ripd/ripd.c

504

r->mask.s_addr == INADDR_ANY) {

usr.sbin/ripd/ripd.c

511

if ((kr->prefix.s_addr & r->mask.s_addr) ==

usr.sbin/ripd/ripd.c

512

(r->addr.s_addr & r->mask.s_addr) &&

usr.sbin/ripd/ripd.c

513

(kr->netmask.s_addr & r->mask.s_addr) ==

usr.sbin/ripd/ripd.c

514

r->mask.s_addr)

usr.sbin/ripd/ripd.h

169

struct in_addr mask;

usr.sbin/ripd/ripd.h

193

struct in_addr mask;

usr.sbin/ripd/ripd.h

215

struct in_addr mask;

usr.sbin/ripd/ripd.h

268

struct in_addr mask;

usr.sbin/route6d/route6d.c

1513

struct sockaddr_in6 mask;

usr.sbin/route6d/route6d.c

1656

mask.sin6_len = sizeof(mask);

usr.sbin/route6d/route6d.c

1657

memset(&mask.sin6_addr, 0xff,

usr.sbin/route6d/route6d.c

1658

sizeof(mask.sin6_addr));

usr.sbin/route6d/route6d.c

1659

rta[RTAX_NETMASK] = &mask;

usr.sbin/route6d/route6d.c

245

sigset_t mask, omask;

usr.sbin/route6d/route6d.c

371

sigemptyset(&mask);

usr.sbin/route6d/route6d.c

372

sigaddset(&mask, SIGALRM);

usr.sbin/route6d/route6d.c

402

sigprocmask(SIG_BLOCK, &mask, &omask);

usr.sbin/route6d/route6d.c

407

sigprocmask(SIG_BLOCK, &mask, &omask);

usr.sbin/rpki-client/rsync.c

249

sigset_t mask, oldmask;

usr.sbin/rpki-client/rsync.c

299

if (sigemptyset(&mask) == -1)

usr.sbin/rpki-client/rsync.c

303

if (sigaddset(&mask, SIGCHLD) == -1)

usr.sbin/rpki-client/rsync.c

305

if (sigprocmask(SIG_BLOCK, &mask, &oldmask) == -1)

usr.sbin/smtpd/scheduler.c

476

int mask, r, delay;

usr.sbin/smtpd/scheduler.c

481

mask = SCHED_UPDATE;

usr.sbin/smtpd/scheduler.c

484

mask |= SCHED_EXPIRE | SCHED_REMOVE | SCHED_BOUNCE;

usr.sbin/smtpd/scheduler.c

486

mask |= SCHED_MDA;

usr.sbin/smtpd/scheduler.c

488

mask |= SCHED_MTA;

usr.sbin/smtpd/scheduler.c

493

log_trace(TRACE_SCHEDULER, "scheduler: getting batch: mask=0x%x, count=%zu", mask, count);

usr.sbin/smtpd/scheduler.c

495

r = backend->batch(mask, &delay, &count, evpids, types);

usr.sbin/smtpd/scheduler_ramqueue.c

463

scheduler_ram_batch(int mask, int *delay, size_t *count, uint64_t *evpids, int *types)

usr.sbin/smtpd/scheduler_ramqueue.c

480

if (mask & SCHED_REMOVE && (evp = TAILQ_FIRST(&ramqueue.q_removed))) {

usr.sbin/smtpd/scheduler_ramqueue.c

490

if (mask & SCHED_EXPIRE && (evp = TAILQ_FIRST(&ramqueue.q_expired))) {

usr.sbin/smtpd/scheduler_ramqueue.c

500

if (mask & SCHED_UPDATE && (evp = TAILQ_FIRST(&ramqueue.q_update))) {

usr.sbin/smtpd/scheduler_ramqueue.c

522

if (mask & SCHED_BOUNCE && (evp = TAILQ_FIRST(&ramqueue.q_bounce))) {

usr.sbin/smtpd/scheduler_ramqueue.c

535

if (mask & SCHED_MDA && (evp = TAILQ_FIRST(&ramqueue.q_mda))) {

usr.sbin/smtpd/scheduler_ramqueue.c

548

if (mask & SCHED_MTA && (evp = TAILQ_FIRST(&ramqueue.q_mta))) {

usr.sbin/smtpd/table.c

340

table_check_type(struct table *t, uint32_t mask)

usr.sbin/smtpd/table.c

342

return t->t_type & mask;

usr.sbin/smtpd/table.c

346

table_check_service(struct table *t, uint32_t mask)

usr.sbin/smtpd/table.c

348

return t->t_services & mask;

usr.sbin/smtpd/table.c

443

in_addr_t mask;

usr.sbin/smtpd/table.c

447

mask = 0;

usr.sbin/smtpd/table.c

449

mask = (mask >> 1) | 0x80000000;

usr.sbin/smtpd/table.c

450

mask = htonl(mask);

usr.sbin/smtpd/table.c

453

if ((ss->sin_addr.s_addr & mask) ==

usr.sbin/smtpd/table.c

454

(((struct sockaddr_in *)ssmask)->sin_addr.s_addr & mask))

usr.sbin/smtpd/table.c

465

struct in6_addr mask;

usr.sbin/smtpd/table.c

468

memset(&mask, 0, sizeof(mask));

usr.sbin/smtpd/table.c

470

mask.s6_addr[i] = 0xff;

usr.sbin/smtpd/table.c

473

mask.s6_addr[ssmask->bits / 8] = 0xff00 >> i;

usr.sbin/smtpd/table.c

479

if ((in->s6_addr[i] & mask.s6_addr[i]) !=

usr.sbin/smtpd/table.c

480

(inmask->s6_addr[i] & mask.s6_addr[i]))

usr.sbin/snmpd/application_agentx.c

150

mode_t mask;

usr.sbin/snmpd/application_agentx.c

154

mask = umask(0777);

usr.sbin/snmpd/application_agentx.c

160

umask(mask);

usr.sbin/snmpd/application_agentx.c

163

umask(mask);

usr.sbin/tcpdump/addrtoname.c

835

init_addrtoname(u_int32_t localnet, u_int32_t mask)

usr.sbin/tcpdump/addrtoname.c

837

netmask = mask;

usr.sbin/tcpdump/addrtoname.c

840

f_netmask = mask;

usr.sbin/tcpdump/pf_print_state.c

106

if (! PF_AZERO(&addr->v.a.mask, af)) {

usr.sbin/tcpdump/pf_print_state.c

107

int bits = unmask(&addr->v.a.mask);

usr.sbin/tcpdump/pf_print_state.c

151

aw.v.a.mask.addr32[0] = 0xffffffff;

usr.sbin/tcpdump/pf_print_state.c

153

memset(&aw.v.a.mask, 0xff, sizeof(aw.v.a.mask));

usr.sbin/tcpdump/pf_print_state.c

87

PF_AZERO(&addr->v.a.mask, AF_INET6))

usr.sbin/tcpdump/print-dvmrp.c

160

u_int32_t mask, origin;

usr.sbin/tcpdump/print-dvmrp.c

168

mask = (u_int32_t)0xff << 24 | bp[0] << 16 | bp[1] << 8 | bp[2];

usr.sbin/tcpdump/print-dvmrp.c

177

printf("\n\tMask %s", intoa(htonl(mask)));

usr.sbin/tcpdump/print-ofp.c

765

int class, field, mask, len;

usr.sbin/tcpdump/print-ofp.c

770

mask = OFP_OXM_GET_HASMASK(oxm);

usr.sbin/tcpdump/print-ofp.c

774

print_map(field, ofp_xm_t_map), mask, len);

usr.sbin/tcpdump/print-ofp.c

794

oxm_print_word(bp, length, mask, 0);

usr.sbin/tcpdump/print-ofp.c

799

oxm_print_quad(bp, length, mask, 1);

usr.sbin/tcpdump/print-ofp.c

808

oxm_print_ether(bp, length, mask);

usr.sbin/tcpdump/print-ofp.c

812

oxm_print_halfword(bp, length, mask, 1);

usr.sbin/tcpdump/print-ofp.c

840

oxm_print_halfword(bp, length, mask, 0);

usr.sbin/tcpdump/print-ofp.c

848

oxm_print_byte(bp, length, mask, 1);

usr.sbin/tcpdump/print-ofp.c

856

oxm_print_word(bp, length, mask, 1);

usr.sbin/tcpdump/print-ofp.c

864

oxm_print_byte(bp, length, mask, 0);

usr.sbin/tcpdump/print-ofp.c

870

oxm_print_data(bp, length, mask, sizeof(struct in6_addr));

usr.sbin/tcpdump/print-ofp.c

874

oxm_print_data(bp, length, mask, 3);

usr.sbin/tftp-proxy/filter.c

197

memset(&pfr.rule.src.addr.v.a.mask.addr8, 255, 4);

usr.sbin/tftp-proxy/filter.c

200

memset(&pfr.rule.dst.addr.v.a.mask.addr8, 255, 4);

usr.sbin/tftp-proxy/filter.c

204

memset(&pfr.rule.src.addr.v.a.mask.addr8, 255, 16);

usr.sbin/tftp-proxy/filter.c

207

memset(&pfr.rule.dst.addr.v.a.mask.addr8, 255, 16);

usr.sbin/tftp-proxy/filter.c

92

memset(&pfr.rule.rdr.addr.v.a.mask.addr8, 255, 4);

usr.sbin/tftp-proxy/filter.c

96

memset(&pfr.rule.rdr.addr.v.a.mask.addr8, 255, 16);

usr.sbin/unbound/util/net_help.c

797

uint8_t mask[8] = {0x0, 0x80, 0xc0, 0xe0, 0xf0, 0xf8, 0xfc, 0xfe};

usr.sbin/unbound/util/net_help.c

812

s[net/8] &= mask[net&0x7];

usr.sbin/unbound/util/storage/slabhash.c

113

return ((hash & sl->mask) >> sl->shift);

usr.sbin/unbound/util/storage/slabhash.c

138

id, (unsigned)sl->size, (unsigned)sl->mask, sl->shift);

usr.sbin/unbound/util/storage/slabhash.c

64

sl->mask = (uint32_t)(sl->size - 1);

usr.sbin/unbound/util/storage/slabhash.c

65

if(sl->mask == 0) {

usr.sbin/unbound/util/storage/slabhash.c

68

log_assert( (sl->size & sl->mask) == 0

usr.sbin/unbound/util/storage/slabhash.c

71

while(!(sl->mask & 0x80000000)) {

usr.sbin/unbound/util/storage/slabhash.c

72

sl->mask <<= 1;

usr.sbin/unbound/util/storage/slabhash.h

61

uint32_t mask;

usr.sbin/vmctl/vmctl.c

663

vm_state(unsigned int mask)

usr.sbin/vmctl/vmctl.c

665

if (mask & VM_STATE_PAUSED)

usr.sbin/vmctl/vmctl.c

667

else if (mask & VM_STATE_WAITING)

usr.sbin/vmctl/vmctl.c

669

else if (mask & VM_STATE_SHUTDOWN)

usr.sbin/vmctl/vmctl.c

671

else if (mask & VM_STATE_RUNNING)

usr.sbin/vmctl/vmctl.c

674

else if (!mask || (mask & VM_STATE_DISABLED))

usr.sbin/vmd/dhcp.c

220

resp.options[o++] = sizeof(mask);

usr.sbin/vmd/dhcp.c

221

mask.s_addr = htonl(0xfffffffe);

usr.sbin/vmd/dhcp.c

222

memcpy(&resp.options[o], &mask, sizeof(mask));

usr.sbin/vmd/dhcp.c

223

o += sizeof(mask);

usr.sbin/vmd/dhcp.c

52

struct in_addr server_addr, mask, client_addr, requested_addr;

usr.sbin/vmd/parse.y

1424

int mask = 16;

usr.sbin/vmd/parse.y

1431

mask = strtonum(p + 1, 1, 16, errstr);

usr.sbin/vmd/parse.y

1467

if ((addr.s_addr & prefixlen2mask(mask)) != addr.s_addr) {

usr.sbin/vmd/parse.y

1475

out->lp_mask.s_addr = prefixlen2mask(mask);

usr.sbin/vmd/parse.y

1490

int mask = 64, err;

usr.sbin/vmd/parse.y

1497

mask = strtonum(p + 1, 0, 64, errstr);

usr.sbin/vmd/parse.y

1524

prefixlen2mask6(mask, &mask6);

usr.sbin/vmd/vioblk.c

283

cmd_desc_idx = avail->ring[idx & vq_info->mask];

usr.sbin/vmd/vioblk.c

306

desc = &table[desc->next & vq_info->mask];

usr.sbin/vmd/vioblk.c

341

desc = &table[desc->next & vq_info->mask];

usr.sbin/vmd/vioblk.c

366

used->ring[used->idx & vq_info->mask].id = cmd_desc_idx;

usr.sbin/vmd/vioblk.c

367

used->ring[used->idx & vq_info->mask].len = cmd_len;

usr.sbin/vmd/vioblk.c

680

*desc = &desc_tbl[(*desc)->next & vq_info->mask];

usr.sbin/vmd/vionet.c

347

hdr_idx = avail->ring[idx & vq_info->mask];

usr.sbin/vmd/vionet.c

348

desc = &table[hdr_idx & vq_info->mask];

usr.sbin/vmd/vionet.c

391

desc = &table[desc->next & vq_info->mask];

usr.sbin/vmd/vionet.c

444

used->ring[used->idx & vq_info->mask].id = hdr_idx;

usr.sbin/vmd/vionet.c

445

used->ring[used->idx & vq_info->mask].len = sz;

usr.sbin/vmd/vionet.c

688

hdr_idx = avail->ring[idx & vq_info->mask];

usr.sbin/vmd/vionet.c

689

desc = &table[hdr_idx & vq_info->mask];

usr.sbin/vmd/vionet.c

725

desc = &table[desc->next & vq_info->mask];

usr.sbin/vmd/vionet.c

795

used->ring[used->idx & vq_info->mask].id = hdr_idx;

usr.sbin/vmd/vionet.c

796

used->ring[used->idx & vq_info->mask].len = chain_len;

usr.sbin/vmd/vioscsi.c

2202

acct.idx = vq_info->last_avail & vq_info->mask;

usr.sbin/vmd/vioscsi.c

2204

if ((acct.avail->idx & vq_info->mask) == acct.idx) {

usr.sbin/vmd/vioscsi.c

2210

while (acct.idx != (acct.avail->idx & vq_info->mask)) {

usr.sbin/vmd/vioscsi.c

2218

acct.req_idx = acct.avail->ring[acct.idx] & vq_info->mask;

usr.sbin/vmd/vioscsi.c

2359

acct.idx = (acct.idx + 1) & vq_info->mask;

usr.sbin/vmd/vioscsi.c

237

*idx = cur->next & vq_info->mask;

usr.sbin/vmd/vioscsi.c

246

used->ring[used->idx & vq_info->mask].id = idx;

usr.sbin/vmd/vioscsi.c

247

used->ring[used->idx & vq_info->mask].len = desc->len;

usr.sbin/vmd/vioscsi.c

251

vq_info->last_avail = avail->idx & vq_info->mask;

usr.sbin/vmd/virtio.c

1391

vq_info->mask = dev->queue_size - 1;

usr.sbin/vmd/virtio.c

213

vq_info->mask = vq_info->qs - 1;

usr.sbin/vmd/virtio.c

291

aidx = avail->idx & vq_info->mask;

usr.sbin/vmd/virtio.c

292

uidx = used->idx & vq_info->mask;

usr.sbin/vmd/virtio.c

294

dxx = avail->ring[aidx] & vq_info->mask;

usr.sbin/vmd/virtio.h

190

uint32_t mask;

usr.sbin/vmd/vm_agentx.c

440

vm_agentx_adminstate(int mask)

usr.sbin/vmd/vm_agentx.c

442

if (mask & VM_STATE_PAUSED)

usr.sbin/vmd/vm_agentx.c

444

else if (mask & VM_STATE_RUNNING)

usr.sbin/vmd/vm_agentx.c

446

else if (mask & VM_STATE_SHUTDOWN)

usr.sbin/vmd/vm_agentx.c

449

else if (!mask || (mask & VM_STATE_DISABLED))

usr.sbin/vmd/vm_agentx.c

456

vm_agentx_operstate(int mask)

usr.sbin/vmd/vm_agentx.c

458

if (mask & VM_STATE_PAUSED)

usr.sbin/vmd/vm_agentx.c

460

else if (mask & VM_STATE_RUNNING)

usr.sbin/vmd/vm_agentx.c

462

else if (mask & VM_STATE_SHUTDOWN)

usr.sbin/vmd/vm_agentx.c

465

else if (!mask || (mask & VM_STATE_DISABLED))

usr.sbin/vmd/vmd.c

1742

prefixlen2mask6(uint8_t prefixlen, struct in6_addr *mask)

usr.sbin/vmd/vmd.c

1757

memcpy(mask, &s6, sizeof(s6));

usr.sbin/vmd/x86_vm.c

1020

uint64_t pte, pt_paddr, pte_paddr, mask, low_mask, high_mask;

usr.sbin/vmd/x86_vm.c

1048

mask = L4_MASK;

usr.sbin/vmd/x86_vm.c

1053

mask = L3_MASK;

usr.sbin/vmd/x86_vm.c

1060

mask = 0xFFC00000;

usr.sbin/vmd/x86_vm.c

1070

pdidx = (va & mask) >> shift;

usr.sbin/vmd/x86_vm.c

1110

mask = mask >> shift_width;

usr.sbin/wsmoused/wsmoused.c

336

int button, i, mask;

usr.sbin/wsmoused/wsmoused.c

362

mask = act->flags & MOUSE_BUTTONS;

usr.sbin/wsmoused/wsmoused.c

363

if (mask == 0)

usr.sbin/wsmoused/wsmoused.c

368

for (i = 0; (i < MOUSE_MAXBUTTON) && (mask != 0); i++) {

usr.sbin/wsmoused/wsmoused.c

369

if (mask & 1) {

usr.sbin/wsmoused/wsmoused.c

376

mask >>= 1;

usr.sbin/ypserv/ypserv/acl.c

104

acl_add_net(int allow, struct in_addr *addr, struct in_addr *mask)

usr.sbin/ypserv/ypserv/acl.c

112

acl->s_mask = mask->s_addr;

usr.sbin/ypserv/ypserv/acl.c

127

struct in_addr mask;

usr.sbin/ypserv/ypserv/acl.c

129

mask.s_addr = htonl(0xffffffff);

usr.sbin/ypserv/ypserv/acl.c

130

acl_add_net(allow, addr, &mask);

usr.sbin/ypserv/ypserv/acl.c

139

struct in_addr addr, mask, *host_addr;

usr.sbin/ypserv/ypserv/acl.c

158

addr.s_addr = mask.s_addr = 0;

usr.sbin/ypserv/ypserv/acl.c

220

acl_add_net(allow, &addr, &mask);

usr.sbin/ypserv/ypserv/acl.c

282

mask.s_addr = htonl(0xffffff00);

usr.sbin/ypserv/ypserv/acl.c

284

mask.s_addr = htonl(0xffff0000);

usr.sbin/ypserv/ypserv/acl.c

286

mask.s_addr = htonl(0xff000000);

usr.sbin/ypserv/ypserv/acl.c

287

acl_add_net(allow, &addr, &mask);

usr.sbin/ypserv/ypserv/acl.c

331

(void)inet_aton(k, &mask);

usr.sbin/ypserv/ypserv/acl.c

345

acl_add_net(allow, &addr, &mask);

usr.sbin/ypserv/ypserv/acl.c

399

addr.s_addr = mask.s_addr = 0;

usr.sbin/ypserv/ypserv/acl.c

401

acl_add_net(allow, &addr, &mask);

usr.sbin/ypserv/ypserv/acl.c

411

struct in_addr addr, mask;

usr.sbin/ypserv/ypserv/acl.c

419

mask.s_addr = htonl(0xffffffff);

usr.sbin/ypserv/ypserv/acl.c

421

acl_add_net(allow, &addr, &mask);

usr.sbin/ypserv/ypserv/acl.c

433

addr.s_addr = mask.s_addr = 0;

usr.sbin/ypserv/ypserv/acl.c

453

(void)inet_aton(k, &mask);

usr.sbin/ypserv/ypserv/acl.c

485

acl_add_net(allow, &addr, &mask);

usr.sbin/ypserv/ypserv/acl.c

516

addr.s_addr = mask.s_addr = 0;

usr.sbin/ypserv/ypserv/acl.c

518

acl_add_net(allow, &addr, &mask);

usr.sbin/ypserv/ypserv/acl.c

523

addr.s_addr = mask.s_addr = 0;

usr.sbin/ypserv/ypserv/acl.c

525

acl_add_net(allow, &addr, &mask);