IPL_SOFTCLOCK
*machdep == (1 << (IPL_SOFTCLOCK - IPL_SOFTCLOCK)));
*machdep == (1 << (IPL_SOFTBIO - IPL_SOFTCLOCK)));
*machdep == (1 << (IPL_SOFTNET - IPL_SOFTCLOCK)));
*machdep == (1 << (IPL_SOFTSERIAL - IPL_SOFTCLOCK)));
(softints & (1 << (opl - IPL_SOFTCLOCK))) == 0);
if (ci->ci_softints & (1 << (IPL_SOFT ## n - IPL_SOFTCLOCK))) {\
~(1 << (IPL_SOFT ## n - IPL_SOFTCLOCK)); \
#elif IPL_SOFTBIO != IPL_SOFTCLOCK + 1
#elif !(IPL_SOFTCLOCK > IPL_NONE)
(((IPL_SOFTSERIAL - IPL_SOFTCLOCK) << (SOFTINT_SERIAL * 4)) | \
((IPL_SOFTNET - IPL_SOFTCLOCK) << (SOFTINT_NET * 4)) | \
((IPL_SOFTBIO - IPL_SOFTCLOCK) << (SOFTINT_BIO * 4)) | \
((IPL_SOFTCLOCK - IPL_SOFTCLOCK) << (SOFTINT_CLOCK * 4)))
CTASSERT(SOFTIPLMASK(IPL_SOFTCLOCK) == 0x0000000e);
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
__CTASSERT(IPL_SOFTCLOCK == ALPHA_PSL_IPL_SOFT_LO);
__CTASSERT(SOFTINTS_ELIGIBLE(IPL_SOFTCLOCK) == ALPHA_IPL2_SOFTINTS);
[IPL_SOFTCLOCK] = PSL_IPL1|PSL_S,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
imask[IPL_SOFTCLOCK] |= imask[IPL_NONE];
imask[IPL_SOFTNET] |= imask[IPL_SOFTCLOCK];
#elif IPL_SOFTBIO != IPL_SOFTCLOCK + 1
#elif !(IPL_SOFTCLOCK > IPL_NONE)
(((IPL_SOFTSERIAL - IPL_SOFTCLOCK) << (SOFTINT_SERIAL * 4)) | \
((IPL_SOFTNET - IPL_SOFTCLOCK) << (SOFTINT_NET * 4)) | \
((IPL_SOFTBIO - IPL_SOFTCLOCK) << (SOFTINT_BIO * 4)) | \
((IPL_SOFTCLOCK - IPL_SOFTCLOCK) << (SOFTINT_CLOCK * 4)))
KASSERT(level != SOFTINT_CLOCK || *machdep == (1 << (IPL_SOFTCLOCK - IPL_SOFTCLOCK)));
KASSERT(level != SOFTINT_BIO || *machdep == (1 << (IPL_SOFTBIO - IPL_SOFTCLOCK)));
KASSERT(level != SOFTINT_NET || *machdep == (1 << (IPL_SOFTNET - IPL_SOFTCLOCK)));
KASSERT(level != SOFTINT_SERIAL || *machdep == (1 << (IPL_SOFTSERIAL - IPL_SOFTCLOCK)));
KASSERT(opl == IPL_NONE || (softints & (1 << (opl - IPL_SOFTCLOCK))) == 0);
if (ci->ci_softints & (1 << (IPL_SOFT ## n - IPL_SOFTCLOCK))) { \
~(1 << (IPL_SOFT ## n - IPL_SOFTCLOCK)); \
spl_masks[IPL_SOFTCLOCK] = irqmasks[IPL_SOFTCLOCK];
KASSERT(aic_imask[IPL_SOFTCLOCK] == 0);
sc->sc_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_SOFTCLOCK);
intr_establish_xname(SOFTINT_CLOCK, IPL_SOFTCLOCK, IST_MPSAFE | IST_EDGE,
KASSERT(vic1_imask[IPL_SOFTCLOCK] == 0);
KASSERT(vic2_imask[IPL_SOFTCLOCK] == 0);
#define spllowersoftclock() (void)_spllower(IPL_SOFTCLOCK)
KASSERT(footbridge_imask[IPL_SOFTCLOCK] == 0);
#define splsoftclock() raisespl(IPL_SOFTCLOCK)
KASSERT(imask[IPL_SOFTCLOCK] == 0);
KASSERT(pci_imask[IPL_SOFTCLOCK] == 0);
s3c24x0_soft_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTSERIAL) |
[SI_SOFTCLOCK] = IPL_SOFTCLOCK,
[SI_SOFTCLOCK] = IPL_SOFTCLOCK,
s3c24x0_soft_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTSERIAL) |
becc_intr_establish(ICU_SOFT, IPL_SOFTCLOCK, becc_softint, NULL);
KASSERT(i80321_imask[IPL_SOFTCLOCK] == 0);
[SI_SOFTCLOCK] = IPL_SOFTCLOCK,
ixp425_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK);
KASSERT(ixp425_imask[IPL_SOFTCLOCK] == 0);
[IPL_SOFTCLOCK] = PSL_S | PSL_IPL1,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0 | MIPS_INT_MASK_0,
mutex_init(&sc->sc_event_lock, MUTEX_DEFAULT, IPL_SOFTCLOCK);
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
iq80310_imask[IPL_SOFTCLOCK] = 0;
iq80310_imask[IPL_SOFTNET] |= iq80310_imask[IPL_SOFTCLOCK];
IPL_SOFTCLOCK, /* SI_SOFTCLOCK */
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0 | MIPS_INT_MASK_5,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
#define splsoftclock() splraise(IPL_SOFTCLOCK)
[IPL_SOFTCLOCK] = PSL_S | MACHINE_PSL_IPL_SOFTCLOCK,
ipl2psl_table[IPL_SOFTCLOCK] = PSL_S|PSL_IPL1;
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
#define IPL_SOFTBIO (IPL_SOFTCLOCK) /* shares SWINT with softclock */
KASSERT((status ^ sr_map[IPL_SOFTCLOCK]) == MIPS_INT_MASK);
KASSERT(ci->ci_cpl == IPL_SOFTCLOCK);
KASSERT(s == IPL_SOFTCLOCK);
for (int r = IPL_SOFTCLOCK; r <= IPL_HIGH; r++) {
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
IPL_SOFTCLOCK, ipl_eimr_map[IPL_SOFTCLOCK]);
[IPL_SOFTCLOCK] = MIPS_INT_MASK_SPL_SOFT0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
return _splraise(IPL_SOFTCLOCK);
intc_intr_establish(I_CH10_TIMER1, IPL_SOFTCLOCK, timer1_intr, 0);
[IPL_SOFTCLOCK] = 1,
KDASSERT(ipl >= IPL_SOFTCLOCK && ipl <= IPL_SOFTSERIAL);
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
return splraise(IPL_SOFTCLOCK);
|(1 << IPL_SOFTBIO ) | (1 << IPL_SOFTCLOCK ) \
|(IPL_SOFTCLOCK << (4*SOFTINT_CLOCK )))
|(SOFTINT_CLOCK << (4*IPL_SOFTCLOCK )))
__CTASSERT(IPL_NONE < IPL_SOFTCLOCK);
__CTASSERT(IPL_SOFTCLOCK < IPL_SOFTBIO);
KASSERT(old_ipl < IPL_SOFTCLOCK);
if (softints & (1 << IPL_SOFTCLOCK)) {
softint_deliver(ci, IPL_SOFTCLOCK);
#define IPL_SOFTBIO (IPL_SOFTCLOCK + 1)
if (ci->ci_softints & (1 << (IPL_SOFT ## n - IPL_SOFTCLOCK))) { \
~(1 << (IPL_SOFT ## n - IPL_SOFTCLOCK)); \
(((IPL_SOFTSERIAL - IPL_SOFTCLOCK) << (SOFTINT_SERIAL * 4)) | \
((IPL_SOFTNET - IPL_SOFTCLOCK) << (SOFTINT_NET * 4)) | \
((IPL_SOFTBIO - IPL_SOFTCLOCK) << (SOFTINT_BIO * 4)) | \
((IPL_SOFTCLOCK - IPL_SOFTCLOCK) << (SOFTINT_CLOCK * 4)))
KASSERT(level != SOFTINT_CLOCK || *machdep == (1 << (IPL_SOFTCLOCK - IPL_SOFTCLOCK)));
KASSERT(level != SOFTINT_BIO || *machdep == (1 << (IPL_SOFTBIO - IPL_SOFTCLOCK)));
KASSERT(level != SOFTINT_NET || *machdep == (1 << (IPL_SOFTNET - IPL_SOFTCLOCK)));
KASSERT(level != SOFTINT_SERIAL || *machdep == (1 << (IPL_SOFTSERIAL - IPL_SOFTCLOCK)));
KASSERT(opl == IPL_NONE || (softints & (1 << (opl - IPL_SOFTCLOCK))) == 0);
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0 | MIPS_INT_MASK_5,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0, \
intc_intr_establish(SH_INTEVT_WDT_ITI, IST_LEVEL, IPL_SOFTCLOCK,
irqmasks[IPL_SOFTCLOCK] &= irqmasks[IPL_NONE];
irqmasks[IPL_SOFTBIO] &= irqmasks[IPL_SOFTCLOCK];
pil = IPL_SOFTCLOCK;
#define SOFTINT_IPLS ((IPL_SOFTCLOCK << (SOFTINT_CLOCK * 5)) \
[IPL_SOFTCLOCK] = PSL_S | PSL_IPL1,
[IPL_SOFTCLOCK] = PSL_S | PSL_IPL1,
fake_softclock_intrhand.ih_level = IPL_SOFTCLOCK;
cemac_handle_reset_work, sc, PRI_NONE, IPL_SOFTCLOCK,
0, 0, 0, "dmiostate", NULL, IPL_SOFTCLOCK);
0, 0, 0, "dmiourstate", NULL, IPL_SOFTCLOCK);
NULL, PWAIT, IPL_SOFTCLOCK, 0);
mutex_init(&ds->ds_lock, MUTEX_DEFAULT, IPL_SOFTCLOCK);
mutex_init(&sc.sc_cmd_mtx, MUTEX_DEFAULT, IPL_SOFTCLOCK);
mutex_init(&sc->sc_cmd_mtx, MUTEX_DEFAULT, IPL_SOFTCLOCK);
mutex_init(&sc->sc_poll_mtx, MUTEX_DEFAULT, IPL_SOFTCLOCK);
mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SOFTCLOCK);
aq_handle_reset_work, sc, PRI_SOFTNET, IPL_SOFTCLOCK,
bge_handle_reset_work, sc, PRI_NONE, IPL_SOFTCLOCK,
vmxnet3_reset_work, sc, VMXNET3_WORKQUEUE_PRI, IPL_SOFTCLOCK,
wm_handle_reset_work, sc, WM_WORKQUEUE_PRI, IPL_SOFTCLOCK,
mutex_init(&pm->lk_flags, MUTEX_DEFAULT, IPL_SOFTCLOCK);
mutex_init(&sme->sme_work_mtx, MUTEX_DEFAULT, IPL_SOFTCLOCK);
sme_events_worker, sme, PRI_NONE, IPL_SOFTCLOCK, WQ_MPSAFE);
mutex_init(&sysmon_wdog_mtx, MUTEX_DEFAULT, IPL_SOFTCLOCK);
NULL, PRI_NONE, IPL_SOFTCLOCK, WQ_MPSAFE | WQ_PERCPU);
mutex_init(&unp->unp_mcastlock, MUTEX_DEFAULT, IPL_SOFTCLOCK);
if (ipl == IPL_NONE || ipl == IPL_SOFTCLOCK ||
IPL_SOFTCLOCK);
if (pp->pr_ipl == IPL_SOFTNET || pp->pr_ipl == IPL_SOFTCLOCK ||
vmem_rehash_all, NULL, PRI_VM, IPL_SOFTCLOCK, WQ_MPSAFE);
#if IPL_SOFTCLOCK != IPL_SOFTBIO
#if IPL_SOFTCLOCK != IPL_SOFTBIO
case IPL_SOFTCLOCK:
if_slowtimo_work, NULL, PRI_SOFTNET, IPL_SOFTCLOCK, WQ_MPSAFE);
mutex_init(&isd->isd_lock, MUTEX_DEFAULT, IPL_SOFTCLOCK);
} else if (ipl == IPL_NONE || ipl == IPL_SOFTCLOCK ||
#if defined(IPL_SOFTCLOCK)