#ifndef _FOOTBRIDGE_INTR_H_
#define _FOOTBRIDGE_INTR_H_
#ifndef _LOCORE
typedef uint8_t ipl_t;
typedef struct {
ipl_t _ipl;
} ipl_cookie_t;
#include <arm/mutex.h>
#endif
#include <arm/cpu.h>
#include <arm/armreg.h>
#define IPL_NONE 0
#define IPL_SOFTCLOCK 1
#define IPL_SOFTBIO 2
#define IPL_SOFTNET 3
#define IPL_SOFTSERIAL 4
#define IPL_VM 5
#define IPL_SCHED 6
#define IPL_HIGH 7
#define NIPL 8
#define IST_UNUSABLE -1
#define IST_NONE 0
#define IST_PULSE 1
#define IST_EDGE 2
#define IST_LEVEL 3
#define ARM_IRQ_HANDLER _C_LABEL(footbridge_intr_dispatch)
#ifndef _LOCORE
#include <arm/cpufunc.h>
#include <arm/footbridge/dc21285mem.h>
#include <arm/footbridge/dc21285reg.h>
#define INT_SWMASK \
((1U << IRQ_SOFTINT) | (1U << IRQ_RESERVED0) | \
(1U << IRQ_RESERVED1) | (1U << IRQ_RESERVED2))
#define ICU_INT_HWMASK (0xffffffff & ~(INT_SWMASK | (1U << IRQ_RESERVED3)))
static inline void __attribute__((__unused__))
footbridge_set_intrmask(void)
{
extern volatile uint32_t intr_enabled;
volatile uint32_t * const dc21285_armcsr_vbase =
(volatile uint32_t *)(DC21285_ARMCSR_VBASE);
uint32_t tmp = intr_enabled & ICU_INT_HWMASK;
dc21285_armcsr_vbase[IRQ_ENABLE_SET>>2] = tmp;
dc21285_armcsr_vbase[IRQ_ENABLE_CLEAR>>2] = ~tmp;
}
static inline void __attribute__((__unused__))
footbridge_splx(int ipl)
{
extern int footbridge_imask[];
extern volatile uint32_t intr_enabled;
extern volatile int footbridge_ipending;
int oldirqstate, hwpend;
__insn_barrier();
set_curcpl(ipl);
hwpend = footbridge_ipending & ICU_INT_HWMASK & ~footbridge_imask[ipl];
if (hwpend != 0) {
oldirqstate = disable_interrupts(I32_bit);
intr_enabled |= hwpend;
footbridge_set_intrmask();
restore_interrupts(oldirqstate);
}
#ifdef __HAVE_FAST_SOFTINTS
cpu_dosoftints();
#endif
}
static inline int __attribute__((__unused__))
footbridge_splraise(int ipl)
{
int old;
old = curcpl();
set_curcpl(ipl);
__insn_barrier();
return (old);
}
static inline int __attribute__((__unused__))
footbridge_spllower(int ipl)
{
int old = curcpl();
footbridge_splx(ipl);
return(old);
}
#if !defined(ARM_SPL_NOINLINE)
#define splx(newspl) footbridge_splx(newspl)
#define _spllower(ipl) footbridge_spllower(ipl)
#define _splraise(ipl) footbridge_splraise(ipl)
#else
int _splraise(int);
int _spllower(int);
void splx(int);
#endif
#include <sys/evcnt.h>
#include <sys/queue.h>
#include <machine/irqhandler.h>
#define splsoft() _splraise(IPL_SOFT)
#define spl0() (void)_spllower(IPL_NONE)
#define spllowersoftclock() (void)_spllower(IPL_SOFTCLOCK)
static inline ipl_cookie_t
makeiplcookie(ipl_t ipl)
{
return (ipl_cookie_t){._ipl = ipl};
}
static inline int
splraiseipl(ipl_cookie_t icookie)
{
return _splraise(icookie._ipl);
}
#include <sys/spl.h>
#define NIRQ 32
struct intrhand {
TAILQ_ENTRY(intrhand) ih_list;
int (*ih_func)(void *);
void *ih_arg;
int ih_ipl;
int ih_irq;
};
#define IRQNAMESIZE sizeof("footbridge irq 31")
struct intrq {
TAILQ_HEAD(, intrhand) iq_list;
struct evcnt iq_ev;
int iq_mask;
int iq_levels;
int iq_ist;
int iq_ipl;
char iq_name[IRQNAMESIZE];
};
#endif
#endif