sys/arch/acorn32/acorn32/autoconf.c

177

irqmasks[IPL_AUDIO], irqmasks[IPL_CLOCK], irqmasks[IPL_HIGH],

sys/arch/acorn32/acorn32/rpc_machdep.c

212

irqmasks[IPL_AUDIO], irqmasks[IPL_CLOCK], irqmasks[IPL_NONE]);

sys/arch/acorn32/eb7500atx/eb7500atx_machdep.c

218

irqmasks[IPL_AUDIO], irqmasks[IPL_CLOCK], irqmasks[IPL_NONE]);

sys/arch/arc/isa/timer_isa.c

147

IPL_CLOCK, (int (*)(void *))hardclock,

sys/arch/arm/acpi/gtmr_acpi.c

75

const int ipl = IPL_CLOCK;

sys/arch/arm/at91/at91st.c

267

at91_intr_establish(sc->sc_pid, IPL_CLOCK, INTR_HIGH_LEVEL, at91st_intr, NULL);

sys/arch/arm/at91/at91tctmr.c

288

at91_intr_establish(sc->sc_pid, IPL_CLOCK, INTR_HIGH_LEVEL, at91tctmr_intr, sc);

sys/arch/arm/broadcom/bcm2835_tmr.c

152

sc->sc_ih = fdtbus_intr_establish_xname(phandle, BCMTIMER, IPL_CLOCK,

sys/arch/arm/clps711x/clpssoc.c

233

intr_establish(IRQ_TC1DI, IPL_CLOCK, 0, clpssoc_clockintr, NULL);

sys/arch/arm/cortex/a9tmr.c

157

sc->sc_global_ih = intr_establish(mpcaa->mpcaa_irq, IPL_CLOCK,

sys/arch/arm/cortex/gtmr.c

154

sc->sc_global_ih = intr_establish(mpcaa->mpcaa_irq, IPL_CLOCK,

sys/arch/arm/ep93xx/epclk.c

231

ep93xx_intr_establish(sc->sc_intr, IPL_CLOCK, epclk_intr, NULL);

sys/arch/arm/fdt/a9ptmr_fdt.c

115

void *ih = fdtbus_intr_establish_xname(phandle, 0, IPL_CLOCK,

sys/arch/arm/fdt/a9tmr_fdt.c

115

void *ih = fdtbus_intr_establish_xname(phandle, 0, IPL_CLOCK,

sys/arch/arm/fdt/gtmr_fdt.c

94

void *ih = fdtbus_intr_establish_xname(phandle, GTMR_VTIMER, IPL_CLOCK,

sys/arch/arm/footbridge/footbridge_clock.c

290

clock_sc->sc_clockintr = footbridge_intr_claim(IRQ_TIMER_1, IPL_CLOCK,

sys/arch/arm/gemini/gemini_timer.c

314

intr_establish(clock_sc->sc_intr, IPL_CLOCK, IST_LEVEL_HIGH,

sys/arch/arm/imx/imx23_timrot.c

136

void *ih = fdtbus_intr_establish_xname(phandle, 0, IPL_CLOCK, 0,

sys/arch/arm/imx/imx23_timrot.c

151

ih = fdtbus_intr_establish_xname(phandle, 1, IPL_CLOCK, 0,

sys/arch/arm/imx/imxclock.c

110

imxclock->sc_ih = intr_establish(imxclock->sc_intr, IPL_CLOCK,

sys/arch/arm/iomd/iomd_clock.c

145

mutex_init(&tmr_lock, MUTEX_DEFAULT, IPL_CLOCK);

sys/arch/arm/iomd/iomd_clock.c

284

clockirq = intr_claim(IRQ_TIMER0, IPL_CLOCK, "tmr0 hard clk",

sys/arch/arm/iomd/iomd_clock.c

293

statclockirq = intr_claim(IRQ_TIMER1, IPL_CLOCK,

sys/arch/arm/ixp12x0/ixp12x0_clk.c

263

ixp12x0_intr_establish(IXPPCI_INTR_T1, IPL_CLOCK, ixpclk_intr, NULL);

sys/arch/arm/marvell/mvsoctmr.c

269

clock_ih = marvell_intr_establish(sc->sc_irq, IPL_CLOCK,

sys/arch/arm/marvell/mvsoctmr.c

273

MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ, IPL_CLOCK, clockhandler,

sys/arch/arm/ofw/ofwgencfg_clock.c

124

clockirq = intr_claim(IRQ_TIMER0, IPL_CLOCK,

sys/arch/arm/s3c2xx0/s3c24x0_clk.c

261

s3c24x0_intr_establish(S3C24X0_INT_TIMER4, IPL_CLOCK,

sys/arch/arm/s3c2xx0/s3c2800_clk.c

259

s3c2800_intr_establish(S3C2800_INT_TIMER0, IPL_CLOCK,

sys/arch/arm/s3c2xx0/s3c2xx0_intr.c

116

s3c2xx0_imask[IPL_CLOCK] &= s3c2xx0_imask[IPL_VM];

sys/arch/arm/s3c2xx0/s3c2xx0_intr.c

117

s3c2xx0_imask[IPL_HIGH] &= s3c2xx0_imask[IPL_CLOCK];

sys/arch/arm/sa11x0/sa11x0_ost.c

252

sa11x0_intr_establish(0, 26, 1, IPL_CLOCK, clockintr, 0);

sys/arch/arm/sa11x0/sa11x0_ost.c

253

sa11x0_intr_establish(0, 27, 1, IPL_CLOCK, statintr, 0);

sys/arch/arm/samsung/mct.c

196

sc->sc_global_ih = fdtbus_intr_establish_xname(sc->sc_phandle, 0, IPL_CLOCK,

sys/arch/arm/sunxi/sunxi_hstimer.c

189

sc->sc_ih = fdtbus_intr_establish_xname(sc->sc_phandle, 0, IPL_CLOCK,

sys/arch/arm/sunxi/sunxi_timer.c

147

ih = fdtbus_intr_establish_xname(sc->sc_phandle, 0, IPL_CLOCK,

sys/arch/arm/ti/am18xx_timer.c

144

void *ih = fdtbus_intr_establish_xname(phandle, 0, IPL_CLOCK, 0,

sys/arch/arm/ti/ti_omaptimer.c

144

ih = fdtbus_intr_establish_xname(sc->sc_phandle, 0, IPL_CLOCK,

sys/arch/arm/xscale/becc_timer.c

152

clock_ih = becc_intr_establish(ICU_TIMERA, IPL_CLOCK,

sys/arch/arm/xscale/i80321_timer.c

236

clock_ih = i80321_intr_establish(ICU_INT_TMR0, IPL_CLOCK,

sys/arch/arm/xscale/ixp425_timer.c

162

clock_ih = ixp425_intr_establish(IXP425_INT_TMR0, IPL_CLOCK,

sys/arch/cats/cats/autoconf.c

156

footbridge_imask[IPL_AUDIO], footbridge_imask[IPL_CLOCK],

sys/arch/emips/ebus/clock_ebus.c

325

ebus_intr_establish(parent, (void *)ia->ia_cookie, IPL_CLOCK,

sys/arch/epoc32/windermere/windermere.c

258

intr_establish(8, IPL_CLOCK, 0, windermere_clockintr, NULL);

sys/arch/evbarm/ifpga/ifpga_clock.c

291

IPL_CLOCK, clockhandler, 0);

sys/arch/evbarm/iq80310/iq80310_intr.c

210

iq80310_imask[IPL_CLOCK] |= iq80310_imask[IPL_AUDIO];

sys/arch/evbarm/iq80310/iq80310_intr.c

216

iq80310_imask[IPL_STATCLOCK] |= iq80310_imask[IPL_CLOCK];

sys/arch/evbarm/iq80310/iq80310_intr.c

225

iq80310_imask[IPL_HIGH] |= iq80310_imask[IPL_CLOCK];

sys/arch/evbarm/iq80310/iq80310_timer.c

212

clock_ih = iq80310_intr_establish(XINT3_IRQ(XINT3_TIMER), IPL_CLOCK,

sys/arch/evbarm/nslu2/nslu2_leds.c

240

sc->sc_tmr_ih = ixp425_intr_establish(IXP425_INT_TMR0, IPL_CLOCK,

sys/arch/hpcmips/tx/tx39io.c

183

return (tx_intr_establish(sc->sc_tc, src, IST_EDGE, IPL_CLOCK, func,

sys/arch/hpcmips/tx/tx39io.c

197

return (tx_intr_establish(sc->sc_tc, src, IST_EDGE, IPL_CLOCK, func,

sys/arch/hpcmips/tx/tx39power.c

127

IST_EDGE, IPL_CLOCK,

sys/arch/hpcmips/tx/tx39power.c

130

IST_EDGE, IPL_CLOCK,

sys/arch/hpcmips/tx/tx39power.c

134

IST_EDGE, IPL_CLOCK,

sys/arch/hpcmips/tx/tx39power.c

137

IST_EDGE, IPL_CLOCK,

sys/arch/hpcmips/tx/tx39power.c

141

IST_EDGE, IPL_CLOCK,

sys/arch/hpcmips/tx/tx39power.c

144

IST_EDGE, IPL_CLOCK,

sys/arch/hpcmips/vr/rtc.c

169

IPL_CLOCK, 0, 0))) {

sys/arch/hpcsh/dev/j6x0pwr.c

270

s = _cpu_intr_resume(IPL_CLOCK << 4);

sys/arch/hppa/dev/cpu.c

178

sc->sc_ihclk = hppa_intr_establish(IPL_CLOCK, clock_intr,

sys/arch/mips/sibyte/dev/sbtimer.c

108

ipl = IPL_CLOCK;

sys/arch/netwinder/netwinder/autoconf.c

104

footbridge_imask[IPL_AUDIO], footbridge_imask[IPL_CLOCK],

sys/arch/playstation2/ee/timer.c

79

intc_intr_establish(I_CH9_TIMER0, IPL_CLOCK, timer0_intr, 0);

sys/arch/powerpc/booke/e500_intr.c

1390

if (e500_intr_cpu_establish(ci, E500_CLOCK_TIMER, IPL_CLOCK, IST_TIMER,

sys/arch/powerpc/ibm4xx/clock.c

129

if (IPL_CLOCK > s) {

sys/arch/powerpc/ibm4xx/clock.c

168

if (pcpl >= IPL_CLOCK) {

sys/arch/powerpc/powerpc/clock.c

165

if (pri >= IPL_CLOCK) {

sys/arch/sh3/sh3/clock.c

259

intc_intr_establish(SH_INTEVT_TMU0_TUNI0, IST_LEVEL, IPL_CLOCK,

sys/arch/shark/isa/clock.c

522

(void)isa_intr_establish(NULL, IRQ_RTC, IST_LEVEL, IPL_CLOCK,

sys/arch/shark/isa/isa_irqhandler.c

304

irqmasks[IPL_CLOCK] &= irqmasks[IPL_VM];

sys/arch/shark/isa/isa_irqhandler.c

305

irqmasks[IPL_HIGH] &= irqmasks[IPL_CLOCK];

sys/arch/shark/ofw/ofw.c

332

irqmasks[IPL_CLOCK], irqmasks[IPL_NONE]);

sys/arch/x86/isa/clock.c

571

(void)isa_intr_establish(NULL, 0, IST_PULSE, IPL_CLOCK,

sys/arch/x86/x86/intr.c

1417

fake_timer_intrhand.ih_level = IPL_CLOCK;

sys/arch/xen/xen/xen_clock.c

736

ci, IPL_CLOCK, NULL, intr_xname, true, ci) == NULL)

sys/dev/tc/tcvar.h

63

#define TC_IPL_CLOCK IPL_CLOCK