reset_control_assert
ret = reset_control_assert(rstc);
ret = reset_control_assert(rstc);
reset_control_assert(rstc);
reset_control_assert(rstpcie0);
reset_control_assert(rstpcie0);
reset_control_assert(rstpcie0);
reset_control_assert(priv->rcdev_ahci);
reset_control_assert(priv->rcdev_ahci);
err = reset_control_assert(plat->axi_rst);
err = reset_control_assert(plat->sw_rst);
err = reset_control_assert(plat->reg_rst);
err = reset_control_assert(drv_data->pwr);
err = reset_control_assert(drv_data->pwr);
reset_control_assert(tegra->sata_oob_rst);
reset_control_assert(tegra->sata_cold_rst);
reset_control_assert(tegra->sata_rst);
reset_control_assert(tegra->sata_oob_rst);
reset_control_assert(tegra->sata_cold_rst);
return reset_control_assert(hpriv->rsts);
reset_control_assert(nxpdev->pdn);
reset_control_assert(nxpdev->pdn);
reset_control_assert(data->ssc_bcr);
reset_control_assert(data->ssc_reset);
ret = reset_control_assert(data->ssc_bcr);
ret = reset_control_assert(data->ssc_reset);
reset_control_assert(rsb->rstc);
reset_control_assert(gmi->rst);
reset_control_assert(gmi->rst);
reset_control_assert(ddata->rsts);
reset_control_assert(ddata->rsts);
reset_control_assert(ddata->rsts);
reset_control_assert(ddata->rsts);
reset_control_assert(ddata->rsts);
reset_control_assert(trng->rst);
reset_control_assert(trng->rst);
reset_control_assert(rst);
reset_control_assert(priv->rst);
ret = reset_control_assert(rstc);
reset_control_assert(priv->rsts);
reset_control_assert(priv->rsts);
reset_control_assert(rstc);
reset_control_assert(rstc);
reset_control_assert(data->reset);
reset_control_assert(td->dvco_rst);
reset_control_assert(td->dfll_rst);
reset_control_assert(td->dvco_rst);
reset_control_assert(td->dfll_rst);
reset_control_assert(td->dvco_rst);
reset_control_assert(td->dfll_rst);
reset_control_assert(rstc);
reset_control_assert(rstc);
reset_control_assert(rstc);
reset_control_assert(ss->reset);
reset_control_assert(ce->reset);
reset_control_assert(ss->reset);
reset_control_assert(ce->reset);
reset_control_assert(rkdev->rst);
reset_control_assert(crypto_info->rst);
reset_control_assert(cryp->rst);
reset_control_assert(cryp->rst);
reset_control_assert(rst);
reset_control_assert(hdev->rst);
reset_control_assert(d->rst);
reset_control_assert(pl330->rstc_ocp);
reset_control_assert(pl330->rstc);
reset_control_assert(pl330->rstc_ocp);
reset_control_assert(pl330->rstc);
reset_control_assert(adev->clk_reset);
reset_control_assert(adev->c0_reset);
reset_control_assert(adev->c1_reset);
reset_control_assert(adev->c2_reset);
reset_control_assert(dmac->rstc);
reset_control_assert(dmac->rstc);
reset_control_assert(rst);
reset_control_assert(rst);
reset_control_assert(rst);
reset_control_assert(sdc->rstc);
reset_control_assert(sdc->rstc);
err = reset_control_assert(tdma->rst);
ret = reset_control_assert(priv->bridge_reset);
reset_control_assert(gpio->rst);
reset_control_assert(dsi->dsi_p_rst);
ret = reset_control_assert(dsi->rst_dpi);
ret = reset_control_assert(dsi->rst_byte);
ret = reset_control_assert(dsi->rst_esc);
ret = reset_control_assert(dsi->rst_pclk);
reset_control_assert(apb_rst);
reset_control_assert(apb_rst);
err = reset_control_assert(gpu->rst);
reset_control_assert(ctx->reset);
err = reset_control_assert(pvr_dev->reset);
reset_control_assert(dev->reset);
reset_control_assert(mipi_dsi->top_rst);
reset_control_assert(reset);
reset_control_assert(tdev->rst);
reset_control_assert(pfdev->rstc);
reset_control_assert(pfdev->rstc);
reset_control_assert(pfdev->rstc);
reset_control_assert(lvds->rstc);
reset_control_assert(lvds->rstc);
reset_control_assert(dsi->rstc);
reset_control_assert(dsi->rstc);
reset_control_assert(rcrtc->rstc);
reset_control_assert(dsi->prstc);
reset_control_assert(dsi->arstc);
reset_control_assert(dsi->arstc);
reset_control_assert(dsi->rstc);
reset_control_assert(dp->rst);
reset_control_assert(dp->apbrst);
reset_control_assert(dp->core_rst);
reset_control_assert(dp->dptx_rst);
reset_control_assert(dp->apb_rst);
reset_control_assert(dp->spdif_rst);
reset_control_assert(ahb_rst);
reset_control_assert(vop->dclk_rst);
reset_control_assert(rstc);
reset_control_assert(rstc);
reset_control_assert(backend->sat_reset);
reset_control_assert(backend->sat_reset);
reset_control_assert(backend->reset);
reset_control_assert(backend->reset);
reset_control_assert(frontend->reset);
reset_control_assert(hdmi->reset);
reset_control_assert(tcon->lcd_rst);
reset_control_assert(tv->reset);
reset_control_assert(tv->reset);
reset_control_assert(drc->reset);
reset_control_assert(drc->reset);
reset_control_assert(dsi->reset);
reset_control_assert(hdmi->rst_ctrl);
reset_control_assert(hdmi->rst_ctrl);
reset_control_assert(phy->rst_phy);
reset_control_assert(phy->rst_phy);
reset_control_assert(mixer->reset);
reset_control_assert(mixer->reset);
reset_control_assert(tcon_top->rst);
reset_control_assert(tcon_top->rst);
err = reset_control_assert(dc->rst);
err = reset_control_assert(dc->rst);
err = reset_control_assert(dpaux->rst);
err = reset_control_assert(dsi->rst);
err = reset_control_assert(gr2d->resets[RST_MC].rstc);
err = reset_control_assert(hdmi->rst);
err = reset_control_assert(wgrp->rst);
err = reset_control_assert(hub->rst);
err = reset_control_assert(wgrp->rst);
err = reset_control_assert(hub->rst);
err = reset_control_assert(sor->rst);
err = reset_control_assert(sor->rst);
reset_control_assert(vic->rst);
err = reset_control_assert(vic->rst);
reset_control_assert(dp->reset);
reset_control_assert(rst);
reset_control_assert(priv->reset);
reset_control_assert(priv->rst);
reset_control_assert(pvt->rst);
reset_control_assert(sfctemp->rst_bus);
reset_control_assert(sfctemp->rst_sense);
reset_control_assert(sfctemp->rst_bus);
ret = reset_control_assert(sfctemp->rst_sense);
ret = reset_control_assert(sfctemp->rst_bus);
reset_control_assert(priv->reset);
reset_control_assert(priv->reset);
reset_control_assert(bus->rst);
reset_control_assert(id->reset);
reset_control_assert(id->reset);
reset_control_assert(dev->rst);
reset_control_assert(drv_data->rstc);
return reset_control_assert(riic->rstc);
reset_control_assert(riic->rstc);
reset_control_assert(rst);
reset_control_assert(rst);
reset_control_assert(p2wi->rstc);
reset_control_assert(p2wi->rstc);
reset_control_assert(master->core_rst);
reset_control_assert(master->core_rst);
ret = reset_control_assert(i3c->presetn);
ret = reset_control_assert(i3c->tresetn);
reset_control_assert(i3c->tresetn);
reset_control_assert(i3c->presetn);
reset_control_assert(rst);
reset_control_assert(info->reset);
reset_control_assert(reset);
reset_control_assert(rst);
ret = reset_control_assert(rstc);
reset_control_assert(rst);
reset_control_assert(lradc->reset);
reset_control_assert(lradc->reset);
reset_control_assert(kbc->rst);
reset_control_assert(iommu->reset);
reset_control_assert(iommu->reset);
reset_control_assert(rst);
reset_control_assert(priv->reset);
reset_control_assert(priv->reset);
reset_control_assert(rst);
reset_control_assert(v->reset);
reset_control_assert(csi2rx->pixel_rst[i - 1]);
reset_control_assert(csi2rx->sys_rst);
reset_control_assert(csi2rx->pixel_rst[i]);
reset_control_assert(csi2rx->p_rst);
reset_control_assert(dev->resets);
reset_control_assert(dev->resets);
reset_control_assert(video->ece.reset);
reset_control_assert(video->reset);
err = reset_control_assert(vde->rst_mc);
err = reset_control_assert(vde->rst_mc);
err = reset_control_assert(vde->rst);
reset_control_assert(csis->mrst);
ret = reset_control_assert(state->rst);
ret = reset_control_assert(core->resets[i]);
reset_control_assert(priv->rstc);
reset_control_assert(isp->rstc);
reset_control_assert(csi2->presetn);
ret = reset_control_assert(csi2->cmn_rstb);
ret = reset_control_assert(csi2->cmn_rstb);
reset_control_assert(csi2->cmn_rstb);
reset_control_assert(cru->aresetn);
reset_control_assert(cru->aresetn);
reset_control_assert(cru->presetn);
reset_control_assert(cru->aresetn);
reset_control_assert(cru->presetn);
reset_control_assert(vsp1->rstc);
reset_control_assert(vsp1->rstc);
reset_control_assert(core_rst);
reset_control_assert(axi_rst);
reset_control_assert(ahb_rst);
reset_control_assert(rkcif->reset);
ret = reset_control_assert(rstc);
ret = reset_control_assert(dcmi->rstc);
ret = reset_control_assert(rstc);
reset_control_assert(csi->rst);
reset_control_assert(csi_dev->reset);
reset_control_assert(csi_dev->reset);
reset_control_assert(csi2_dev->reset);
reset_control_assert(csi2_dev->reset);
reset_control_assert(csi2_dev->reset);
reset_control_assert(csi2_dev->reset);
reset_control_assert(dev->rstc);
reset_control_assert(dev->rstc);
reset_control_assert(dev->rstc);
reset_control_assert(csi2->reset);
reset_control_assert(vpu->resets);
reset_control_assert(vpu->resets);
reset_control_assert(rc_dev->rstc);
reset_control_assert(ir->rst);
reset_control_assert(ir->rst);
reset_control_assert(rstc);
reset_control_assert(reset);
reset_control_assert(rstc);
reset_control_assert(priv->rstc);
reset_control_assert(priv->rstc);
reset_control_assert(pwrseq->reset_ctrl);
reset_control_assert(pwrseq->reset_ctrl);
reset_control_assert(host->pdata->rstc);
reset_control_assert(host->pdata->rstc);
reset_control_assert(host->pdata->rstc);
reset_control_assert(host->rst);
reset_control_assert(host->rst);
reset_control_assert(host->reset);
reset_control_assert(owl_host->reset);
ret = reset_control_assert(priv->rstc);
reset_control_assert(priv->rstc);
reset_control_assert(priv->rst_hw);
ret = reset_control_assert(reset);
ret = reset_control_assert(rstc);
ret = reset_control_assert(priv->reset);
reset_control_assert(priv->reset);
reset_control_assert(priv->rst);
reset_control_assert(rstc);
reset_control_assert(rstc);
reset_control_assert(pdata->rstc);
rc = reset_control_assert(tegra_host->rst);
reset_control_assert(tegra_host->rst);
reset_control_assert(tegra_host->rst);
reset_control_assert(priv->rst);
reset_control_assert(rst);
int ret = reset_control_assert(host->rstc);
reset_control_assert(host->reset);
reset_control_assert(host->reset);
reset_control_assert(priv->rst);
reset_control_assert(priv->rst_br);
reset_control_assert(priv->rst);
reset_control_assert(priv->rst_hw);
reset_control_assert(dt->rst);
reset_control_assert(dt->rst_reg);
reset_control_assert(dt->rst);
reset_control_assert(dt->rst_reg);
reset_control_assert(rstc);
reset_control_assert(nfc->reset);
reset_control_assert(nfc->reset);
reset_control_assert(cdev->rst);
reset_control_assert(cdev->rst);
reset_control_assert(cdev->rst);
reset_control_assert(cdev->rst);
reset_control_assert(gpriv->rstc2);
reset_control_assert(gpriv->rstc1);
reset_control_assert(gpriv->rstc2);
reset_control_assert(gpriv->rstc1);
reset_control_assert(priv->reset);
reset_control_assert(priv->reset);
reset_control_assert(priv->reset);
reset_control_assert(priv->rstc);
reset_control_assert(priv->rstc);
reset_control_assert(priv->rcdev);
ret = reset_control_assert(priv->rcdev);
reset_control_assert(gphy_fw->reset);
reset_control_assert(priv->rstc);
reset_control_assert(priv->rstc);
reset_control_assert(priv->rstc);
reset_control_assert(priv->sw_reset);
ret = reset_control_assert(priv->sw_reset);
ret = reset_control_assert(priv->reset_ctl);
reset_control_assert(priv->reset);
reset_control_assert(ag->mac_reset);
reset_control_assert(mdio_reset);
reset_control_assert(ag->mac_reset);
err = reset_control_assert(priv->rst);
reset_control_assert(priv->mac_rst);
reset_control_assert(priv->phy_rst);
reset_control_assert(priv->mac_core_rst);
reset_control_assert(priv->phy_rst);
reset_control_assert(priv->mac_ifc_rst);
ret = reset_control_assert(rstc);
reset_control_assert(rstc);
reset_control_assert(priv->rstc);
return reset_control_assert(priv->rstc);
reset_control_assert(priv->rst[nr]);
reset_control_assert(priv->rst[i]);
err = reset_control_assert(eqos->rst);
reset_control_assert(eqos->rst);
reset_control_assert(gbeth->rstc);
ret = reset_control_assert(gbeth->rstc);
reset_control_assert(priv->phy_reset);
reset_control_assert(priv->phy_reset);
reset_control_assert(priv->phy_reset);
reset_control_assert(dwmac->stmmac_ocp_rst);
reset_control_assert(dwmac->stmmac_rst);
reset_control_assert(dwmac->stmmac_ocp_rst);
reset_control_assert(dwmac->stmmac_rst);
reset_control_assert(gmac->rst_ephy);
err = reset_control_assert(mgbe->rst_mac);
err = reset_control_assert(mgbe->rst_pcs);
return reset_control_assert(mgbe->rst_mac);
ret = reset_control_assert(priv->plat->stmmac_rst);
reset_control_assert(priv->plat->stmmac_rst);
reset_control_assert(priv->plat->stmmac_ahb_rst);
reset_control_assert(comm->rstc);
reset_control_assert(priv->reset);
reset_control_assert(priv->reset);
reset_control_assert(ctx->reset);
reset_control_assert(ctx->reset);
reset_control_assert(mdiodev->reset_ctrl);
ret = reset_control_assert(ar_ahb->core_cold_rst);
ret = reset_control_assert(ar_ahb->radio_cold_rst);
ret = reset_control_assert(ar_ahb->radio_warm_rst);
ret = reset_control_assert(ar_ahb->radio_srif_rst);
ret = reset_control_assert(ar_ahb->cpu_init_rst);
return reset_control_assert(dev->rstc);
ret = reset_control_assert(anv->reset);
ret = reset_control_assert(rst);
ret = reset_control_assert(otp->rst);
reset_control_assert(imx_pcie->pciephy_reset);
reset_control_assert(imx_pcie->apps_reset);
reset_control_assert(mrst->port);
reset_control_assert(mrst->apb);
reset_control_assert(pci->core_rsts[DW_PCIE_STICKY_RST].rstc);
reset_control_assert(pci->core_rsts[DW_PCIE_CORE_RST].rstc);
reset_control_assert(pci->core_rsts[DW_PCIE_PIPE_RST].rstc);
reset_control_assert(pci->core_rsts[DW_PCIE_PHY_RST].rstc);
reset_control_assert(pci->core_rsts[DW_PCIE_HOT_RST].rstc);
reset_control_assert(pci->core_rsts[DW_PCIE_PWR_RST].rstc);
ret = reset_control_assert(rockchip->rst);
reset_control_assert(hipcie->soft_reset);
reset_control_assert(hipcie->sys_reset);
reset_control_assert(hipcie->bus_reset);
reset_control_assert(hipcie->soft_reset);
reset_control_assert(hipcie->sys_reset);
reset_control_assert(hipcie->bus_reset);
reset_control_assert(pcie->core_rst);
ret = reset_control_assert(pcie_ep->core_reset);
ret = reset_control_assert(res->rst);
reset_control_assert(res->core);
reset_control_assert(res->core);
ret = reset_control_assert(res->rst);
reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
reset_control_assert(stm32_pcie->rst);
reset_control_assert(stm32_pcie->rst);
reset_control_assert(pcie->core_apb_rst);
ret = reset_control_assert(pcie->core_rst);
ret = reset_control_assert(pcie->core_apb_rst);
reset_control_assert(pcie->core_rst);
reset_control_assert(pcie->core_apb_rst);
reset_control_assert(pcie->core_rst);
reset_control_assert(pcie->core_apb_rst);
reset_control_assert(pcie->core_rst);
reset_control_assert(priv->rst_gio);
reset_control_assert(priv->rst);
reset_control_assert(pcie->rst);
reset_control_assert(pcie->afi_rst);
reset_control_assert(pcie->pcie_xrst);
reset_control_assert(pcie->afi_rst);
reset_control_assert(pcie->pex_rst);
reset_control_assert(pcie->pcie_xrst);
reset_control_assert(pcie->pex_rst);
reset_control_assert(pcie->pex_rst);
reset_control_assert(pcie->h2xrst);
reset_control_assert(port->perst);
ret = reset_control_assert(pcie->swinit_reset);
ret = reset_control_assert(pcie->bridge_reset);
ret = reset_control_assert(pcie->perst_reset);
reset_control_assert(pcie->mac_reset);
reset_control_assert(pcie->mac_reset);
reset_control_assert(pcie->mac_reset);
reset_control_assert(port->reset);
reset_control_assert(port->pcie_rst);
reset_control_assert(port->pcie_rst);
reset_control_assert(pcie->resets);
ret = reset_control_assert(priv->rst);
reset_control_assert(data);
reset_control_assert(phy->reset);
reset_control_assert(phy->reset);
reset_control_assert(phy2->reset);
reset_control_assert(phy->reset);
reset_control_assert(phy2->reset);
reset_control_assert(phy->reset);
reset_control_assert(phy->reset);
reset_control_assert(dphy->reset);
reset_control_assert(phy->reset);
ret = reset_control_assert(priv->reset);
ret = reset_control_assert(priv->reset);
reset_control_assert(sp->apb_rst);
reset_control_assert(phy->phy_rst);
reset_control_assert(phy->apb_rst);
reset_control_assert(phy->phys[i].lnk_rst);
return reset_control_assert(ins->lnk_rst);
reset_control_assert(sp->phy_rst);
ret = reset_control_assert(cdns_phy->phy_rst);
return reset_control_assert(inst->lnk_rst);
reset_control_assert(cdns_phy->apb_rst);
reset_control_assert(cdns_phy->phy_rst);
reset_control_assert(cdns_phy->apb_rst);
reset_control_assert(cdns_phy->phys[i].lnk_rst);
reset_control_assert(cdns_phy->phy_rst);
reset_control_assert(cdns_phy->apb_rst);
reset_control_assert(cdns_phy->phys[i].lnk_rst);
reset_control_assert(cdns_phy->phys[i].lnk_rst);
reset_control_assert(cdns_phy->apb_rst);
reset_control_assert(imx8_phy->reset);
reset_control_assert(imx8_phy->perst);
reset_control_assert(imx8_phy->reset);
reset_control_assert(imx8_phy->reset);
reset_control_assert(port->utmi_rst);
reset_control_assert(priv->por_rst);
reset_control_assert(priv->por_rst);
reset_control_assert(cbphy->core_rst);
reset_control_assert(cbphy->phy_rst);
ret = reset_control_assert(iphy->app_rst);
reset_control_assert(priv->phy_reset);
reset_control_assert(priv->phy_reset);
ret = reset_control_assert(priv->phy_reset);
reset_control_assert(priv->phy_reset);
ret = reset_control_assert(priv->pcie_reset);
ret = reset_control_assert(priv->phy_reset);
reset_control_assert(xfi_tphy->reset);
reset_control_assert(ta->resets[i]);
reset_control_assert(resets[i]);
reset_control_assert(ta->resets[i]);
ret = reset_control_assert(phy->phy_reset);
err = reset_control_assert(priv->no_suspend_override);
err = reset_control_assert(priv->reset);
reset_control_assert(phy->por_rst);
reset_control_assert(phy->por_rst);
reset_control_assert(phy->srif_rst);
reset_control_assert(phy->reset);
reset_control_assert(qphy->reset);
reset_control_assert(qphy->pipe_reset);
reset_control_assert(qphy->phy_reset);
reset_control_assert(qphy->phy_reset);
reset_control_assert(qphy->lane_rst);
reset_control_assert(qphy->lane_rst);
ret = reset_control_assert(qmp->nocsr_reset);
reset_control_assert(qmp->nocsr_reset);
ret = reset_control_assert(qmp->ufs_reset);
ret = reset_control_assert(qphy->phy_reset);
reset_control_assert(qphy->phy_reset);
reset_control_assert(qphy->phy_reset);
ret = reset_control_assert(hsphy->phy_reset);
reset_control_assert(hsphy->phy_reset);
return reset_control_assert(phy->resets);
ret = reset_control_assert(phy->resets);
ret = reset_control_assert(priv->phy_reset);
ret = reset_control_assert(priv->por_reset);
ret = reset_control_assert(priv->reset_com);
ret = reset_control_assert(priv->reset_phy);
reset_control_assert(phy->rstdev);
reset_control_assert(phy->rsthost);
return reset_control_assert(channel->rstc);
reset_control_assert(channel->rstc);
reset_control_assert(data);
reset_control_assert(r->rstc);
reset_control_assert(r->rstc);
ret = reset_control_assert(rphy->phy_reset);
reset_control_assert(priv->phy_rst);
ret = reset_control_assert(priv->phy_rst);
err = reset_control_assert(rk_phy->phy_rst);
reset_control_assert(rk_phy->phy_rst);
err = reset_control_assert(rk_phy->phy_rst);
reset_control_assert(samsung->m_phy_rst);
reset_control_assert(samsung->apb_rst);
reset_control_assert(hdptx->rsts[RST_APB].rstc);
reset_control_assert(hdptx->rsts[RST_LANE].rstc);
reset_control_assert(hdptx->rsts[RST_CMN].rstc);
reset_control_assert(hdptx->rsts[RST_INIT].rstc);
reset_control_assert(hdptx->rsts[RST_LANE].rstc);
reset_control_assert(hdptx->rsts[RST_CMN].rstc);
reset_control_assert(hdptx->rsts[RST_INIT].rstc);
reset_control_assert(hdptx->rsts[RST_APB].rstc);
reset_control_assert(hdptx->rsts[RST_APB].rstc);
reset_control_assert(hdptx->rsts[RST_LANE].rstc);
reset_control_assert(hdptx->rsts[RST_CMN].rstc);
reset_control_assert(hdptx->rsts[RST_INIT].rstc);
reset_control_assert(priv->p30phy);
reset_control_assert(priv->p30phy);
reset_control_assert(tcphy->tcphy_rst);
reset_control_assert(tcphy->uphy_rst);
reset_control_assert(tcphy->pipe_rst);
reset_control_assert(tcphy->uphy_rst);
reset_control_assert(tcphy->tcphy_rst);
reset_control_assert(tcphy->tcphy_rst);
reset_control_assert(tcphy->uphy_rst);
reset_control_assert(tcphy->pipe_rst);
reset_control_assert(phy->reset);
reset_control_assert(priv->rst_tx);
reset_control_assert(priv->rst_pm);
reset_control_assert(priv->rst_rx);
reset_control_assert(priv->rst_tx);
reset_control_assert(priv->rst_pm);
reset_control_assert(priv->rst_parent);
reset_control_assert(priv->rst_parent_gio);
reset_control_assert(priv->rst_parent);
reset_control_assert(priv->rst_parent_gio);
reset_control_assert(priv->rst);
reset_control_assert(priv->rst);
reset_control_assert(priv->rst);
reset_control_assert(priv->rst_gio);
reset_control_assert(priv->rst);
reset_control_assert(priv->rst);
reset_control_assert(priv->rst);
reset_control_assert(priv->rst_parent);
reset_control_assert(priv->rst_parent_gio);
reset_control_assert(priv->rst_parent);
reset_control_assert(priv->rst);
reset_control_assert(priv->rst);
reset_control_assert(priv->rst_parent);
reset_control_assert(priv->rst_parent_gio);
reset_control_assert(priv->rst_parent);
err = reset_control_assert(miphy_phy->miphy_rst);
reset_control_assert(phy_dev->rstport);
return reset_control_assert(phy_dev->rstport);
reset_control_assert(combophy->phy_reset);
reset_control_assert(usbphyc->rst);
reset_control_assert(dphy->rstc);
ret = reset_control_assert(dphy->sys_rst);
reset_control_assert(usbphy->rstc);
reset_control_assert(usbphy->rstc);
reset_control_assert(pcie->rst);
reset_control_assert(sata->rst);
reset_control_assert(padctl->rst);
err = reset_control_assert(padctl->rst);
reset_control_assert(padctl->rst);
err = reset_control_assert(padctl->rst);
ret = reset_control_assert(pwrc_domain->rstc);
reset_control_assert(domain->reset);
reset_control_assert(ctx->clkgen_reset);
err = reset_control_assert(ctx->gpu_reset);
err = reset_control_assert(ctx->clkgen_reset);
reset_control_assert(hi_pwm_chip->rstc);
reset_control_assert(hi_pwm_chip->rstc);
reset_control_assert(rst);
reset_control_assert(sun4ichip->rst);
reset_control_assert(sun4ichip->rst);
reset_control_assert(pc->rst);
reset_control_assert(pc->rst);
reset_control_assert(priv->rst[nr]);
reset_control_assert(priv->rst[i]);
ret = reset_control_assert(drproc->dsp_reset);
ret = reset_control_assert(dsp_reset);
reset_control_assert(priv->run_stall);
return reset_control_assert(priv->run_stall);
reset_control_assert(ksproc->reset);
ret = reset_control_assert(oproc->reset);
ret = reset_control_assert(oproc->reset);
reset_control_assert(adsp->pdc_sync_reset);
reset_control_assert(adsp->restart);
reset_control_assert(adsp->pdc_sync_reset);
reset_control_assert(adsp->restart);
reset_control_assert(qproc->pdc_reset);
reset_control_assert(qproc->pdc_reset);
reset_control_assert(qproc->mss_restart);
reset_control_assert(qproc->pdc_reset);
reset_control_assert(qproc->mss_restart);
ret = reset_control_assert(qproc->mss_restart);
reset_control_assert(qproc->pdc_reset);
reset_control_assert(wcss->wcss_q6_reset);
reset_control_assert(wcss->wcss_reset);
reset_control_assert(wcss->wcss_reset);
ret = reset_control_assert(wcss->wcss_reset);
reset_control_assert(wcss->wcss_aon_reset);
reset_control_assert(wcss->wcss_reset);
reset_control_assert(wcss->wcss_reset);
reset_control_assert(wcss->wcss_q6_reset);
err = reset_control_assert(priv->rst);
reset_control_assert(ddata->sw_reset);
sw_err = reset_control_assert(ddata->sw_reset);
pwr_err = reset_control_assert(ddata->pwr_reset);
err = reset_control_assert(ddata->hold_boot_rst);
err = reset_control_assert(ddata->rst);
ret = reset_control_assert(kproc->reset);
ret = reset_control_assert(kproc->reset);
ret = reset_control_assert(core->kproc->reset);
if (reset_control_assert(core->kproc->reset))
error = reset_control_assert(wkupm3->rsts);
reset_control_assert(rstc);
ret = reset_control_assert(resets->rstc[i]);
reset_control_assert(resets->rstc[i]);
EXPORT_SYMBOL_GPL(reset_control_assert);
ret = reset_control_assert(rstcs[i].rstc);
reset_control_assert(rstcs[i++].rstc);
reset_control_assert(priv->rstc);
reset_control_assert(priv->rstc);
ret = reset_control_assert(priv->rstc);
reset_control_assert(priv->rstc);
ret = reset_control_assert(priv->rstc);
reset_control_assert(sp_rtc->rstc);
reset_control_assert(sp_rtc->rstc);
ret = reset_control_assert(svsp->rst);
reset_control_assert(svsp->rst));
err = reset_control_assert(pg->reset);
err = reset_control_assert(pg->reset);
err = reset_control_assert(pg->reset);
reset_control_assert(rstc_ref);
reset_control_assert(rstc);
reset_control_assert(rstc_ocp);
reset_control_assert(xspi->rstc);
reset_control_assert(dwsmmio->rstc);
reset_control_assert(dwsmmio->rstc);
reset_control_assert(dwsmmio->rstc);
reset_control_assert(q->resets);
reset_control_assert(priv->reset);
reset_control_assert(data);
reset_control_assert(ospi->rstc);
reset_control_assert(rstc);
reset_control_assert(rst);
reset_control_assert(sspi->rstc);
reset_control_assert(data);
return reset_control_assert(pspim->rstc);
return reset_control_assert(pspim->rstc);
reset_control_assert(tspi->rst);
reset_control_assert(tspi->rst);
reset_control_assert(tspi->rst);
reset_control_assert(tspi->rst);
reset_control_assert(tsd->rst);
reset_control_assert(tsd->rst);
reset_control_assert(tspi->rst);
reset_control_assert(tspi->rst);
reset_control_assert(tspi->rst);
reset_control_assert(tspi->rst);
reset_control_assert(dev->rstc);
reset_control_assert(dev->rstc);
reset_control_assert(isp_dev->reset);
reset_control_assert(isp_dev->reset);
reset_control_assert(nvec->rst);
ret = reset_control_assert(reset);
reset_control_assert(priv->rstc);
reset_control_assert(priv->rstc);
return reset_control_assert(priv->rstc);
reset_control_assert(reset);
reset_control_assert(data);
reset_control_assert(tegra->reset);
err = reset_control_assert(ts->rst);
err = reset_control_assert(ts->rst);
reset_control_assert(data);
reset_control_assert(priv->rst);
reset_control_assert(priv->rst);
reset_control_assert(info->rst);
reset_control_assert(uart->rst);
reset_control_assert(uart->rst);
reset_control_assert(tup->rst);
reset_control_assert(data);
return reset_control_assert(sport->rstc);
reset_control_assert(data);
reset_control_assert(cdns_uart_data->rstc);
ret = reset_control_assert(host->rstc);
ret = reset_control_assert(host->rstphy);
reset_control_assert(host->rst);
reset_control_assert(host->hci_reset);
reset_control_assert(host->crypto_reset);
reset_control_assert(host->unipro_reset);
reset_control_assert(host->mphy_reset);
ret = reset_control_assert(host->core_reset);
reset_control_assert(host->rst);
reset_control_assert(priv->rci[SPRD_UFSHCI_SOFT_RST].rc);
reset_control_assert(priv->rci[SPRD_UFS_DEV_RST].rc);
reset_control_assert(data->resets);
reset_control_assert(reset);
err = reset_control_assert(rst);
reset_control_assert(data);
reset_control_assert(dwc->reset);
reset_control_assert(dwc->reset);
reset_control_assert(dwc->reset);
ret_reset = reset_control_assert(appledwc->reset);
ret = reset_control_assert(appledwc->reset);
ret = reset_control_assert(appledwc->reset);
reset_control_assert(data);
ret = reset_control_assert(dwc3g->resets);
ret = reset_control_assert(google->non_sticky_rst);
reset_control_assert(simple->resets);
reset_control_assert(simple->resets);
reset_control_assert(simple->resets);
ret = reset_control_assert(qcom->resets);
reset_control_assert(qcom->resets);
reset_control_assert(qcom->resets);
ret = reset_control_assert(qcom->resets);
reset_control_assert(dwc3_data->rstc_rst);
reset_control_assert(dwc3_data->rstc_pwrdn);
reset_control_assert(dwc3_data->rstc_pwrdn);
reset_control_assert(dwc3_data->rstc_rst);
reset_control_assert(dwc3_data->rstc_pwrdn);
reset_control_assert(dwc3_data->rstc_rst);
ret = reset_control_assert(crst);
ret = reset_control_assert(crst);
ret = reset_control_assert(hibrst);
ret = reset_control_assert(apbrst);
reset_control_assert(vhub->rst);
reset_control_assert(usb3->usbp_rstc);
reset_control_assert(usb3->usbp_rstc);
reset_control_assert(usb3->drd_rstc);
reset_control_assert(usb3->drd_rstc);
reset_control_assert(priv->rsts);
reset_control_assert(priv->rsts);
ret = reset_control_assert(priv->rsts);
reset_control_assert(priv->rsts);
reset_control_assert(priv->rst);
reset_control_assert(priv->pwr);
reset_control_assert(priv->pwr);
reset_control_assert(priv->rst);
reset_control_assert(priv->resets);
reset_control_assert(priv->resets);
ret = reset_control_assert(priv->resets);
reset_control_assert(priv->resets);
reset_control_assert(priv->pwr);
reset_control_assert(priv->rst);
reset_control_assert(priv->rst);
reset_control_assert(priv->pwr);
reset_control_assert(uhci->rsts);
reset_control_assert(uhci->rsts);
reset_control_assert(histb->soft_reset);
reset_control_assert(xhci->reset);
reset_control_assert(xhci->reset);
reset_control_assert(xhci->reset);
reset_control_assert(glue->rst);
reset_control_assert(glue->rst);
ret = reset_control_assert(phy->pad_rst);
ret = reset_control_assert(phy->pad_rst);
reset_control_assert(priv->rsts);
reset_control_assert(priv->rsts);
ret = reset_control_assert(priv->rsts);
reset_control_assert(priv->rst);
reset_control_assert(dw_wdt->rst);
reset_control_assert(dw_wdt->rst);
reset_control_assert(dw_wdt->rst);
ret = reset_control_assert(priv->rstc);
ret = reset_control_assert(priv->rstc);
reset_control_assert(data);
int reset_control_assert(struct reset_control *rstc);
rc = reset_control_assert(hda->reset);
reset_control_assert(ak4458->reset);
reset_control_assert(ntp8835->reset);
reset_control_assert(ntp8835->reset);
reset_control_assert(ntp8918->reset);
reset_control_assert(ntp8918->reset);
reset_control_assert(rk3308->reset);
reset_control_assert(wsa883x->sd_reset);
reset_control_assert(wsa884x->sd_reset);
reset_control_assert(dev->reset);
reset_control_assert(dev->reset);
ret = reset_control_assert(xcvr->reset);
reset_control_assert(rst);
reset_control_assert(i2s->rst);
reset_control_assert(prl->rst);
reset_control_assert(rst);
reset_control_assert(spdif->rst);
ret = reset_control_assert(fifo->arb);
reset_control_assert(priv->reset);
reset_control_assert(priv->reset);
reset_control_assert(ssi->rstc);
return reset_control_assert(ssi->rstc);
reset_control_assert(i2s_tdm->tx_reset);
reset_control_assert(i2s_tdm->rx_reset);
reset_control_assert(rc);
reset_control_assert(pdm->reset);
reset_control_assert(sai->rst_h);
reset_control_assert(sai->rst_m);
reset_control_assert(chip->run_stall);
reset_control_assert(i2s->reset);
reset_control_assert(rst);
reset_control_assert(rst);
reset_control_assert(rst);
reset_control_assert(i2s->rst);
reset_control_assert(i2s->rst);
ret = reset_control_assert(ac97->reset);
ret = reset_control_assert(i2s->reset);
ret = reset_control_assert(spdif->reset);
reset_control_assert(aio->chip->rst);
reset_control_assert(aio->chip->rst);
reset_control_assert(chip->rst);
reset_control_assert(chip->rst);
reset_control_assert(evea->rst_adamv);
reset_control_assert(evea->rst_exiv);
reset_control_assert(evea->rst);
reset_control_assert(evea->rst_exiv);
reset_control_assert(evea->rst);
reset_control_assert(evea->rst_adamv);
reset_control_assert(evea->rst_exiv);
reset_control_assert(evea->rst);
reset_control_assert(evea->rst_adamv);
reset_control_assert(evea->rst_exiv);
reset_control_assert(evea->rst);