arch/arm/include/asm/assembler.h
569
1: .inst 0xde02
arch/arm/include/asm/assembler.h
571
1: .inst 0xe7f001f2
arch/arm/include/asm/uaccess-asm.h
13
.inst.w 0xf3af8014
arch/arm/include/asm/uaccess-asm.h
15
.inst 0xe320f014
arch/arm/kernel/iwmmxt.h
19
.inst 0xedd00100 | (.L\reg << 12) | (.L\base << 16) | (\offset >> 2)
arch/arm/kernel/iwmmxt.h
23
.inst 0xfd900100 | (.L\reg << 12) | (.L\base << 16) | (\offset >> 2)
arch/arm/kernel/iwmmxt.h
27
.inst 0xedc00100 | (.L\reg << 12) | (.L\base << 16) | (\offset >> 2)
arch/arm/kernel/iwmmxt.h
31
.inst 0xfd800100 | (.L\reg << 12) | (.L\base << 16) | (\offset >> 2)
arch/arm/mach-omap2/cm.h
60
void (*module_enable)(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
arch/arm/mach-omap2/cm.h
61
void (*module_disable)(u8 part, u16 inst, u16 clkctrl_offs);
arch/arm/mach-omap2/cm.h
62
u32 (*xlate_clkctrl)(u8 part, u16 inst, u16 clkctrl_offs);
arch/arm/mach-omap2/cm.h
71
int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
arch/arm/mach-omap2/cm.h
72
int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs);
arch/arm/mach-omap2/cm.h
73
u32 omap_cm_xlate_clkctrl(u8 part, u16 inst, u16 clkctrl_offs);
arch/arm/mach-omap2/cm1_44xx.h
28
#define OMAP44XX_CM1_REGADDR(inst, reg) \
arch/arm/mach-omap2/cm1_44xx.h
29
OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg))
arch/arm/mach-omap2/cm1_54xx.h
24
#define OMAP54XX_CM_CORE_AON_REGADDR(inst, reg) \
arch/arm/mach-omap2/cm1_54xx.h
25
OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE + (inst) + (reg))
arch/arm/mach-omap2/cm1_7xx.h
25
#define DRA7XX_CM_CORE_AON_REGADDR(inst, reg) \
arch/arm/mach-omap2/cm1_7xx.h
26
OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE + (inst) + (reg))
arch/arm/mach-omap2/cm2_44xx.h
28
#define OMAP44XX_CM2_REGADDR(inst, reg) \
arch/arm/mach-omap2/cm2_44xx.h
29
OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (inst) + (reg))
arch/arm/mach-omap2/cm2_54xx.h
24
#define OMAP54XX_CM_CORE_REGADDR(inst, reg) \
arch/arm/mach-omap2/cm2_54xx.h
25
OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE + (inst) + (reg))
arch/arm/mach-omap2/cm2_7xx.h
25
#define DRA7XX_CM_CORE_REGADDR(inst, reg) \
arch/arm/mach-omap2/cm2_7xx.h
26
OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_BASE + (inst) + (reg))
arch/arm/mach-omap2/cm33xx.c
105
static bool _is_module_ready(u16 inst, u16 clkctrl_offs)
arch/arm/mach-omap2/cm33xx.c
109
v = _clkctrl_idlest(inst, clkctrl_offs);
arch/arm/mach-omap2/cm33xx.c
124
static void _clktrctrl_write(u8 c, u16 inst, u16 cdoffs)
arch/arm/mach-omap2/cm33xx.c
128
v = am33xx_cm_read_reg(inst, cdoffs);
arch/arm/mach-omap2/cm33xx.c
131
am33xx_cm_write_reg(v, inst, cdoffs);
arch/arm/mach-omap2/cm33xx.c
144
static bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs)
arch/arm/mach-omap2/cm33xx.c
148
v = am33xx_cm_read_reg(inst, cdoffs);
arch/arm/mach-omap2/cm33xx.c
163
static void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs)
arch/arm/mach-omap2/cm33xx.c
165
_clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs);
arch/arm/mach-omap2/cm33xx.c
177
static void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs)
arch/arm/mach-omap2/cm33xx.c
179
_clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs);
arch/arm/mach-omap2/cm33xx.c
190
static void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs)
arch/arm/mach-omap2/cm33xx.c
192
_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs);
arch/arm/mach-omap2/cm33xx.c
203
static void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs)
arch/arm/mach-omap2/cm33xx.c
205
_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs);
arch/arm/mach-omap2/cm33xx.c
224
static int am33xx_cm_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs,
arch/arm/mach-omap2/cm33xx.c
229
omap_test_timeout(_is_module_ready(inst, clkctrl_offs),
arch/arm/mach-omap2/cm33xx.c
247
static int am33xx_cm_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs,
arch/arm/mach-omap2/cm33xx.c
252
omap_test_timeout((_clkctrl_idlest(inst, clkctrl_offs) ==
arch/arm/mach-omap2/cm33xx.c
268
static void am33xx_cm_module_enable(u8 mode, u8 part, u16 inst,
arch/arm/mach-omap2/cm33xx.c
273
v = am33xx_cm_read_reg(inst, clkctrl_offs);
arch/arm/mach-omap2/cm33xx.c
276
am33xx_cm_write_reg(v, inst, clkctrl_offs);
arch/arm/mach-omap2/cm33xx.c
287
static void am33xx_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs)
arch/arm/mach-omap2/cm33xx.c
291
v = am33xx_cm_read_reg(inst, clkctrl_offs);
arch/arm/mach-omap2/cm33xx.c
293
am33xx_cm_write_reg(v, inst, clkctrl_offs);
arch/arm/mach-omap2/cm33xx.c
351
static u32 am33xx_cm_xlate_clkctrl(u8 part, u16 inst, u16 offset)
arch/arm/mach-omap2/cm33xx.c
353
return cm_base.pa + inst + offset;
arch/arm/mach-omap2/cm33xx.c
46
static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx)
arch/arm/mach-omap2/cm33xx.c
48
return readl_relaxed(cm_base.va + inst + idx);
arch/arm/mach-omap2/cm33xx.c
52
static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx)
arch/arm/mach-omap2/cm33xx.c
54
writel_relaxed(val, cm_base.va + inst + idx);
arch/arm/mach-omap2/cm33xx.c
58
static inline u32 am33xx_cm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
arch/arm/mach-omap2/cm33xx.c
62
v = am33xx_cm_read_reg(inst, idx);
arch/arm/mach-omap2/cm33xx.c
65
am33xx_cm_write_reg(v, inst, idx);
arch/arm/mach-omap2/cm33xx.c
70
static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask)
arch/arm/mach-omap2/cm33xx.c
74
v = am33xx_cm_read_reg(inst, idx);
arch/arm/mach-omap2/cm33xx.c
89
static u32 _clkctrl_idlest(u16 inst, u16 clkctrl_offs)
arch/arm/mach-omap2/cm33xx.c
91
u32 v = am33xx_cm_read_reg(inst, clkctrl_offs);
arch/arm/mach-omap2/cm33xx.h
19
#define AM33XX_CM_REGADDR(inst, reg) \
arch/arm/mach-omap2/cm33xx.h
20
AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg))
arch/arm/mach-omap2/cm_common.c
131
int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs)
arch/arm/mach-omap2/cm_common.c
139
cm_ll_data->module_enable(mode, part, inst, clkctrl_offs);
arch/arm/mach-omap2/cm_common.c
153
int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs)
arch/arm/mach-omap2/cm_common.c
161
cm_ll_data->module_disable(part, inst, clkctrl_offs);
arch/arm/mach-omap2/cm_common.c
165
u32 omap_cm_xlate_clkctrl(u8 part, u16 inst, u16 clkctrl_offs)
arch/arm/mach-omap2/cm_common.c
172
return cm_ll_data->xlate_clkctrl(part, inst, clkctrl_offs);
arch/arm/mach-omap2/cminst44xx.c
102
static bool _is_module_ready(u8 part, u16 inst, u16 clkctrl_offs)
arch/arm/mach-omap2/cminst44xx.c
106
v = _clkctrl_idlest(part, inst, clkctrl_offs);
arch/arm/mach-omap2/cminst44xx.c
113
static u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx)
arch/arm/mach-omap2/cminst44xx.c
118
return readl_relaxed(_cm_bases[part].va + inst + idx);
arch/arm/mach-omap2/cminst44xx.c
122
static void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx)
arch/arm/mach-omap2/cminst44xx.c
127
writel_relaxed(val, _cm_bases[part].va + inst + idx);
arch/arm/mach-omap2/cminst44xx.c
131
static u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst,
arch/arm/mach-omap2/cminst44xx.c
136
v = omap4_cminst_read_inst_reg(part, inst, idx);
arch/arm/mach-omap2/cminst44xx.c
139
omap4_cminst_write_inst_reg(v, part, inst, idx);
arch/arm/mach-omap2/cminst44xx.c
144
static u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx)
arch/arm/mach-omap2/cminst44xx.c
146
return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx);
arch/arm/mach-omap2/cminst44xx.c
149
static u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst,
arch/arm/mach-omap2/cminst44xx.c
152
return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx);
arch/arm/mach-omap2/cminst44xx.c
155
static u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask)
arch/arm/mach-omap2/cminst44xx.c
159
v = omap4_cminst_read_inst_reg(part, inst, idx);
arch/arm/mach-omap2/cminst44xx.c
180
static void _clktrctrl_write(u8 c, u8 part, u16 inst, u16 cdoffs)
arch/arm/mach-omap2/cminst44xx.c
184
v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
arch/arm/mach-omap2/cminst44xx.c
187
omap4_cminst_write_inst_reg(v, part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
arch/arm/mach-omap2/cminst44xx.c
199
static bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs)
arch/arm/mach-omap2/cminst44xx.c
203
v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
arch/arm/mach-omap2/cminst44xx.c
219
static void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs)
arch/arm/mach-omap2/cminst44xx.c
221
_clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs);
arch/arm/mach-omap2/cminst44xx.c
234
static void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs)
arch/arm/mach-omap2/cminst44xx.c
236
_clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs);
arch/arm/mach-omap2/cminst44xx.c
248
static void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs)
arch/arm/mach-omap2/cminst44xx.c
250
_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs);
arch/arm/mach-omap2/cminst44xx.c
257
static void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs)
arch/arm/mach-omap2/cminst44xx.c
259
_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs);
arch/arm/mach-omap2/cminst44xx.c
274
static int omap4_cminst_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs,
arch/arm/mach-omap2/cminst44xx.c
279
omap_test_timeout(_is_module_ready(part, inst, clkctrl_offs),
arch/arm/mach-omap2/cminst44xx.c
297
static int omap4_cminst_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs,
arch/arm/mach-omap2/cminst44xx.c
302
omap_test_timeout((_clkctrl_idlest(part, inst, clkctrl_offs) ==
arch/arm/mach-omap2/cminst44xx.c
318
static void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst,
arch/arm/mach-omap2/cminst44xx.c
323
v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
arch/arm/mach-omap2/cminst44xx.c
326
omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
arch/arm/mach-omap2/cminst44xx.c
337
static void omap4_cminst_module_disable(u8 part, u16 inst, u16 clkctrl_offs)
arch/arm/mach-omap2/cminst44xx.c
341
v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
arch/arm/mach-omap2/cminst44xx.c
343
omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
arch/arm/mach-omap2/cminst44xx.c
476
static u32 omap4_cminst_xlate_clkctrl(u8 part, u16 inst, u16 offset)
arch/arm/mach-omap2/cminst44xx.c
478
return _cm_bases[part].pa + inst + offset;
arch/arm/mach-omap2/cminst44xx.c
74
static u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx);
arch/arm/mach-omap2/cminst44xx.c
85
static u32 _clkctrl_idlest(u8 part, u16 inst, u16 clkctrl_offs)
arch/arm/mach-omap2/cminst44xx.c
87
u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
arch/arm/mach-omap2/prcm_mpu44xx.c
28
u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 reg)
arch/arm/mach-omap2/prcm_mpu44xx.c
30
return readl_relaxed(OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
arch/arm/mach-omap2/prcm_mpu44xx.c
33
void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 reg)
arch/arm/mach-omap2/prcm_mpu44xx.c
35
writel_relaxed(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
arch/arm/mach-omap2/prcm_mpu44xx.h
29
#define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) \
arch/arm/mach-omap2/prcm_mpu44xx.h
30
OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg))
arch/arm/mach-omap2/prcm_mpu54xx.h
26
#define OMAP54XX_PRCM_MPU_REGADDR(inst, reg) \
arch/arm/mach-omap2/prcm_mpu54xx.h
27
OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE + (inst) + (reg))
arch/arm/mach-omap2/prcm_mpu7xx.h
26
#define DRA7XX_PRCM_MPU_REGADDR(inst, reg) \
arch/arm/mach-omap2/prcm_mpu7xx.h
27
OMAP2_L4_IO_ADDRESS(DRA7XX_PRCM_MPU_BASE + (inst) + (reg))
arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
27
extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
28
extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
arch/arm/mach-omap2/prm.h
137
bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx);
arch/arm/mach-omap2/prm.h
138
void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx);
arch/arm/mach-omap2/prm.h
158
extern bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx);
arch/arm/mach-omap2/prm.h
159
extern void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx);
arch/arm/mach-omap2/prm33xx.c
112
s16 inst, u16 rstctrl_offs,
arch/arm/mach-omap2/prm33xx.c
119
if (am33xx_prm_is_hardreset_asserted(shift, 0, inst, rstctrl_offs) == 0)
arch/arm/mach-omap2/prm33xx.c
123
am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs);
arch/arm/mach-omap2/prm33xx.c
128
am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
arch/arm/mach-omap2/prm33xx.c
131
omap_test_timeout(am33xx_prm_is_hardreset_asserted(st_shift, 0, inst,
arch/arm/mach-omap2/prm33xx.c
20
static u32 am33xx_prm_read_reg(s16 inst, u16 idx)
arch/arm/mach-omap2/prm33xx.c
22
return readl_relaxed(prm_base.va + inst + idx);
arch/arm/mach-omap2/prm33xx.c
26
static void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
arch/arm/mach-omap2/prm33xx.c
28
writel_relaxed(val, prm_base.va + inst + idx);
arch/arm/mach-omap2/prm33xx.c
32
static u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
arch/arm/mach-omap2/prm33xx.c
36
v = am33xx_prm_read_reg(inst, idx);
arch/arm/mach-omap2/prm33xx.c
39
am33xx_prm_write_reg(v, inst, idx);
arch/arm/mach-omap2/prm33xx.c
56
static int am33xx_prm_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
arch/arm/mach-omap2/prm33xx.c
61
v = am33xx_prm_read_reg(inst, rstctrl_offs);
arch/arm/mach-omap2/prm33xx.c
82
static int am33xx_prm_assert_hardreset(u8 shift, u8 part, s16 inst,
arch/arm/mach-omap2/prm33xx.c
87
am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs);
arch/arm/mach-omap2/prm33xx.h
16
#define AM33XX_PRM_REGADDR(inst, reg) \
arch/arm/mach-omap2/prm33xx.h
17
AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE + (inst) + (reg))
arch/arm/mach-omap2/prm44xx.c
102
static void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
arch/arm/mach-omap2/prm44xx.c
104
writel_relaxed(val, prm_base.va + inst + reg);
arch/arm/mach-omap2/prm44xx.c
108
static u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
arch/arm/mach-omap2/prm44xx.c
112
v = omap4_prm_read_inst_reg(inst, reg);
arch/arm/mach-omap2/prm44xx.c
115
omap4_prm_write_inst_reg(v, inst, reg);
arch/arm/mach-omap2/prm44xx.c
170
s32 inst = omap4_prmst_get_prm_dev_inst();
arch/arm/mach-omap2/prm44xx.c
172
if (inst == PRM_INSTANCE_UNKNOWN)
arch/arm/mach-omap2/prm44xx.c
176
inst, offset);
arch/arm/mach-omap2/prm44xx.c
181
s32 inst = omap4_prmst_get_prm_dev_inst();
arch/arm/mach-omap2/prm44xx.c
183
if (inst == PRM_INSTANCE_UNKNOWN)
arch/arm/mach-omap2/prm44xx.c
187
inst, offset);
arch/arm/mach-omap2/prm44xx.c
192
s32 inst = omap4_prmst_get_prm_dev_inst();
arch/arm/mach-omap2/prm44xx.c
194
if (inst == PRM_INSTANCE_UNKNOWN)
arch/arm/mach-omap2/prm44xx.c
199
inst,
arch/arm/mach-omap2/prm44xx.c
308
s32 inst = omap4_prmst_get_prm_dev_inst();
arch/arm/mach-omap2/prm44xx.c
310
if (inst == PRM_INSTANCE_UNKNOWN)
arch/arm/mach-omap2/prm44xx.c
316
inst,
arch/arm/mach-omap2/prm44xx.c
319
(((omap4_prm_read_inst_reg(inst,
arch/arm/mach-omap2/prm44xx.c
329
inst,
arch/arm/mach-omap2/prm44xx.c
332
(((omap4_prm_read_inst_reg(inst,
arch/arm/mach-omap2/prm44xx.c
353
s32 inst = omap4_prmst_get_prm_dev_inst();
arch/arm/mach-omap2/prm44xx.c
355
if (inst == PRM_INSTANCE_UNKNOWN)
arch/arm/mach-omap2/prm44xx.c
360
inst,
arch/arm/mach-omap2/prm44xx.c
375
s32 inst = omap4_prmst_get_prm_dev_inst();
arch/arm/mach-omap2/prm44xx.c
377
if (inst == PRM_INSTANCE_UNKNOWN)
arch/arm/mach-omap2/prm44xx.c
381
v = omap4_prm_read_inst_reg(inst,
arch/arm/mach-omap2/prm44xx.c
404
static bool omap44xx_prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx)
arch/arm/mach-omap2/prm44xx.c
406
return (omap4_prminst_read_inst_reg(part, inst, idx)) ? 1 : 0;
arch/arm/mach-omap2/prm44xx.c
419
static void omap44xx_prm_clear_context_loss_flags_old(u8 part, s16 inst,
arch/arm/mach-omap2/prm44xx.c
422
omap4_prminst_write_inst_reg(0xffffffff, part, inst, idx);
arch/arm/mach-omap2/prm44xx.c
96
static u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
arch/arm/mach-omap2/prm44xx.c
98
return readl_relaxed(prm_base.va + inst + reg);
arch/arm/mach-omap2/prm44xx.h
30
#define OMAP44XX_PRM_REGADDR(inst, reg) \
arch/arm/mach-omap2/prm44xx.h
31
OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
arch/arm/mach-omap2/prm54xx.h
26
#define OMAP54XX_PRM_REGADDR(inst, reg) \
arch/arm/mach-omap2/prm54xx.h
27
OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE + (inst) + (reg))
arch/arm/mach-omap2/prm7xx.h
28
#define DRA7XX_PRM_REGADDR(inst, reg) \
arch/arm/mach-omap2/prm7xx.h
29
OMAP2_L4_IO_ADDRESS(DRA7XX_PRM_BASE + (inst) + (reg))
arch/arm/mach-omap2/prm_common.c
365
bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx)
arch/arm/mach-omap2/prm_common.c
370
ret = prm_ll_data->was_any_context_lost_old(part, inst, idx);
arch/arm/mach-omap2/prm_common.c
389
void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx)
arch/arm/mach-omap2/prm_common.c
392
prm_ll_data->clear_context_loss_flags_old(part, inst, idx);
arch/arm/mach-omap2/prminst44xx.c
104
v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs);
arch/arm/mach-omap2/prminst44xx.c
123
int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
arch/arm/mach-omap2/prminst44xx.c
128
omap4_prminst_rmw_inst_reg_bits(mask, mask, part, inst, rstctrl_offs);
arch/arm/mach-omap2/prminst44xx.c
152
int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst,
arch/arm/mach-omap2/prminst44xx.c
160
if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
arch/arm/mach-omap2/prminst44xx.c
165
omap4_prminst_rmw_inst_reg_bits(0xffffffff, st_mask, part, inst,
arch/arm/mach-omap2/prminst44xx.c
168
omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
arch/arm/mach-omap2/prminst44xx.c
171
inst, rstst_offs),
arch/arm/mach-omap2/prminst44xx.c
181
s32 inst = omap4_prmst_get_prm_dev_inst();
arch/arm/mach-omap2/prminst44xx.c
183
if (inst == PRM_INSTANCE_UNKNOWN)
arch/arm/mach-omap2/prminst44xx.c
186
v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, inst,
arch/arm/mach-omap2/prminst44xx.c
190
inst, OMAP4_PRM_RSTCTRL_OFFSET);
arch/arm/mach-omap2/prminst44xx.c
194
inst, OMAP4_PRM_RSTCTRL_OFFSET);
arch/arm/mach-omap2/prminst44xx.c
58
u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
arch/arm/mach-omap2/prminst44xx.c
63
return readl_relaxed(_prm_bases[part].va + inst + idx);
arch/arm/mach-omap2/prminst44xx.c
67
void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
arch/arm/mach-omap2/prminst44xx.c
72
writel_relaxed(val, _prm_bases[part].va + inst + idx);
arch/arm/mach-omap2/prminst44xx.c
76
u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
arch/arm/mach-omap2/prminst44xx.c
81
v = omap4_prminst_read_inst_reg(part, inst, idx);
arch/arm/mach-omap2/prminst44xx.c
84
omap4_prminst_write_inst_reg(v, part, inst, idx);
arch/arm/mach-omap2/prminst44xx.c
99
int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
arch/arm/mach-omap2/prminst44xx.h
20
extern u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx);
arch/arm/mach-omap2/prminst44xx.h
21
extern void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);
arch/arm/mach-omap2/prminst44xx.h
23
s16 inst, u16 idx);
arch/arm/mach-omap2/prminst44xx.h
27
extern int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
arch/arm/mach-omap2/prminst44xx.h
29
extern int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
arch/arm/mach-omap2/prminst44xx.h
32
s16 inst, u16 rstctrl_offs,
arch/arm/mm/alignment.c
770
static int alignment_get_arm(struct pt_regs *regs, u32 *ip, u32 *inst)
arch/arm/mm/alignment.c
780
*inst = __mem_to_opcode_arm(instr);
arch/arm/mm/alignment.c
785
static int alignment_get_thumb(struct pt_regs *regs, u16 *ip, u16 *inst)
arch/arm/mm/alignment.c
795
*inst = __mem_to_opcode_thumb16(instr);
arch/arm/net/bpf_jit_32.c
271
static inline void _emit(int cond, u32 inst, struct jit_ctx *ctx)
arch/arm/net/bpf_jit_32.c
273
inst |= (cond << 28);
arch/arm/net/bpf_jit_32.c
274
inst = __opcode_to_mem_arm(inst);
arch/arm/net/bpf_jit_32.c
277
ctx->target[ctx->idx] = inst;
arch/arm/net/bpf_jit_32.c
285
static inline void emit(u32 inst, struct jit_ctx *ctx)
arch/arm/net/bpf_jit_32.c
287
_emit(ARM_COND_AL, inst, ctx);
arch/arm/net/bpf_jit_32.h
169
#define _AL3_SR(inst) (inst | (1 << 4))
arch/arm/vfp/vfpdouble.c
1127
u32 vfp_double_cpdo(u32 inst, u32 fpscr)
arch/arm/vfp/vfpdouble.c
1129
u32 op = inst & FOP_MASK;
arch/arm/vfp/vfpdouble.c
1132
unsigned int dn = vfp_get_dn(inst);
arch/arm/vfp/vfpdouble.c
1139
fop = (op == FOP_EXT) ? &fops_ext[FEXT_TO_IDX(inst)] : &fops[FOP_TO_IDX(op)];
arch/arm/vfp/vfpdouble.c
1146
dest = vfp_get_sd(inst);
arch/arm/vfp/vfpdouble.c
1148
dest = vfp_get_dd(inst);
arch/arm/vfp/vfpdouble.c
1154
dm = vfp_get_sm(inst);
arch/arm/vfp/vfpdouble.c
1156
dm = vfp_get_dm(inst);
arch/arm/vfp/vfpinstr.h
10
#define INST_CPRTDO(inst) (((inst) & 0x0f000000) == 0x0e000000)
arch/arm/vfp/vfpinstr.h
11
#define INST_CPRT(inst) ((inst) & (1 << 4))
arch/arm/vfp/vfpinstr.h
12
#define INST_CPRT_L(inst) ((inst) & (1 << 20))
arch/arm/vfp/vfpinstr.h
13
#define INST_CPRT_Rd(inst) (((inst) & (15 << 12)) >> 12)
arch/arm/vfp/vfpinstr.h
14
#define INST_CPRT_OP(inst) (((inst) >> 21) & 7)
arch/arm/vfp/vfpinstr.h
15
#define INST_CPNUM(inst) ((inst) & 0xf00)
arch/arm/vfp/vfpinstr.h
30
#define FOP_TO_IDX(inst) ((inst & 0x00b00000) >> 20 | (inst & (1 << 6)) >> 4)
arch/arm/vfp/vfpinstr.h
49
#define FEXT_TO_IDX(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
arch/arm/vfp/vfpinstr.h
51
#define vfp_get_sd(inst) ((inst & 0x0000f000) >> 11 | (inst & (1 << 22)) >> 22)
arch/arm/vfp/vfpinstr.h
52
#define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12 | (inst & (1 << 22)) >> 18)
arch/arm/vfp/vfpinstr.h
53
#define vfp_get_sm(inst) ((inst & 0x0000000f) << 1 | (inst & (1 << 5)) >> 5)
arch/arm/vfp/vfpinstr.h
54
#define vfp_get_dm(inst) ((inst & 0x0000000f) | (inst & (1 << 5)) >> 1)
arch/arm/vfp/vfpinstr.h
55
#define vfp_get_sn(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
arch/arm/vfp/vfpinstr.h
56
#define vfp_get_dn(inst) ((inst & 0x000f0000) >> 16 | (inst & (1 << 7)) >> 3)
arch/arm/vfp/vfpinstr.h
58
#define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00)
arch/arm/vfp/vfpinstr.h
79
u32 vfp_single_cpdo(u32 inst, u32 fpscr);
arch/arm/vfp/vfpinstr.h
80
u32 vfp_single_cprt(u32 inst, u32 fpscr, struct pt_regs *regs);
arch/arm/vfp/vfpinstr.h
82
u32 vfp_double_cpdo(u32 inst, u32 fpscr);
arch/arm/vfp/vfpmodule.c
256
static void vfp_panic(char *reason, u32 inst)
arch/arm/vfp/vfpmodule.c
262
fmrx(FPEXC), fmrx(FPSCR), inst);
arch/arm/vfp/vfpmodule.c
271
static int vfp_raise_exceptions(u32 exceptions, u32 inst, u32 fpscr)
arch/arm/vfp/vfpmodule.c
278
vfp_panic("unhandled bounce", inst);
arch/arm/vfp/vfpmodule.c
313
static u32 vfp_emulate_instruction(u32 inst, u32 fpscr, struct pt_regs *regs)
arch/arm/vfp/vfpmodule.c
317
pr_debug("VFP: emulate: INST=0x%08x SCR=0x%08x\n", inst, fpscr);
arch/arm/vfp/vfpmodule.c
319
if (INST_CPRTDO(inst)) {
arch/arm/vfp/vfpmodule.c
320
if (!INST_CPRT(inst)) {
arch/arm/vfp/vfpmodule.c
324
if (vfp_single(inst)) {
arch/arm/vfp/vfpmodule.c
325
exceptions = vfp_single_cpdo(inst, fpscr);
arch/arm/vfp/vfpmodule.c
327
exceptions = vfp_double_cpdo(inst, fpscr);
arch/arm/vfp/vfpsingle.c
1172
u32 vfp_single_cpdo(u32 inst, u32 fpscr)
arch/arm/vfp/vfpsingle.c
1174
u32 op = inst & FOP_MASK;
arch/arm/vfp/vfpsingle.c
1177
unsigned int sn = vfp_get_sn(inst);
arch/arm/vfp/vfpsingle.c
1178
unsigned int sm = vfp_get_sm(inst);
arch/arm/vfp/vfpsingle.c
1184
fop = (op == FOP_EXT) ? &fops_ext[FEXT_TO_IDX(inst)] : &fops[FOP_TO_IDX(op)];
arch/arm/vfp/vfpsingle.c
1193
dest = vfp_get_dd(inst);
arch/arm/vfp/vfpsingle.c
1195
dest = vfp_get_sd(inst);
arch/arm64/include/asm/asm-uaccess.h
91
.macro user_ldst l, inst, reg, addr, post_inc
arch/arm64/include/asm/kvm_nested.h
407
void kvm_handle_s1e2_tlbi(struct kvm_vcpu *vcpu, u32 inst, u64 val);
arch/arm64/include/asm/sysreg.h
58
#define __emit_inst(x) .inst(x)
arch/arm64/kernel/compat_alignment.c
284
static int alignment_get_arm(struct pt_regs *regs, __le32 __user *ip, u32 *inst)
arch/arm64/kernel/compat_alignment.c
293
*inst = __le32_to_cpu(instr);
arch/arm64/kernel/compat_alignment.c
297
static int alignment_get_thumb(struct pt_regs *regs, __le16 __user *ip, u16 *inst)
arch/arm64/kernel/compat_alignment.c
306
*inst = __le16_to_cpu(instr);
arch/arm64/kvm/nested.c
1085
static void compute_s1_tlbi_range(struct kvm_vcpu *vcpu, u32 inst, u64 val,
arch/arm64/kvm/nested.c
1088
switch (inst) {
arch/arm64/kvm/nested.c
1206
void kvm_handle_s1e2_tlbi(struct kvm_vcpu *vcpu, u32 inst, u64 val)
arch/arm64/kvm/nested.c
1210
compute_s1_tlbi_range(vcpu, inst, val, &scope);
arch/loongarch/include/asm/kvm_csr.h
187
int kvm_emu_iocsr(larch_inst inst, struct kvm_run *run, struct kvm_vcpu *vcpu);
arch/loongarch/include/asm/kvm_vcpu.h
58
int kvm_emu_mmio_read(struct kvm_vcpu *vcpu, larch_inst inst);
arch/loongarch/include/asm/kvm_vcpu.h
59
int kvm_emu_mmio_write(struct kvm_vcpu *vcpu, larch_inst inst);
arch/loongarch/kvm/exit.c
112
static int kvm_handle_csr(struct kvm_vcpu *vcpu, larch_inst inst)
arch/loongarch/kvm/exit.c
123
rd = inst.reg2csr_format.rd;
arch/loongarch/kvm/exit.c
124
rj = inst.reg2csr_format.rj;
arch/loongarch/kvm/exit.c
125
csrid = inst.reg2csr_format.csr;
arch/loongarch/kvm/exit.c
156
int kvm_emu_iocsr(larch_inst inst, struct kvm_run *run, struct kvm_vcpu *vcpu)
arch/loongarch/kvm/exit.c
165
rd = inst.reg2_format.rd;
arch/loongarch/kvm/exit.c
166
rj = inst.reg2_format.rj;
arch/loongarch/kvm/exit.c
167
opcode = inst.reg2_format.opcode;
arch/loongarch/kvm/exit.c
24
static int kvm_emu_cpucfg(struct kvm_vcpu *vcpu, larch_inst inst)
arch/loongarch/kvm/exit.c
278
larch_inst inst;
arch/loongarch/kvm/exit.c
283
inst.word = vcpu->arch.badi;
arch/loongarch/kvm/exit.c
287
trace_kvm_exit_gspr(vcpu, inst.word);
arch/loongarch/kvm/exit.c
289
switch (((inst.word >> 24) & 0xff)) {
arch/loongarch/kvm/exit.c
29
if (inst.reg2_format.opcode != cpucfg_op)
arch/loongarch/kvm/exit.c
292
er = kvm_emu_cpucfg(vcpu, inst);
arch/loongarch/kvm/exit.c
296
er = kvm_handle_csr(vcpu, inst);
arch/loongarch/kvm/exit.c
299
switch (((inst.word >> 22) & 0x3ff)) {
arch/loongarch/kvm/exit.c
305
switch (((inst.word >> 15) & 0x1ffff)) {
arch/loongarch/kvm/exit.c
307
er = kvm_emu_iocsr(inst, run, vcpu);
arch/loongarch/kvm/exit.c
32
rd = inst.reg2_format.rd;
arch/loongarch/kvm/exit.c
33
rj = inst.reg2_format.rj;
arch/loongarch/kvm/exit.c
330
curr_pc, __func__, inst.word);
arch/loongarch/kvm/exit.c
368
int kvm_emu_mmio_read(struct kvm_vcpu *vcpu, larch_inst inst)
arch/loongarch/kvm/exit.c
376
op8 = (inst.word >> 24) & 0xff;
arch/loongarch/kvm/exit.c
381
rd = inst.reg2i14_format.rd;
arch/loongarch/kvm/exit.c
382
opcode = inst.reg2i14_format.opcode;
arch/loongarch/kvm/exit.c
397
rd = inst.reg2i12_format.rd;
arch/loongarch/kvm/exit.c
398
opcode = inst.reg2i12_format.opcode;
arch/loongarch/kvm/exit.c
431
rd = inst.reg3_format.rd;
arch/loongarch/kvm/exit.c
432
opcode = inst.reg3_format.opcode;
arch/loongarch/kvm/exit.c
495
inst.word, vcpu->arch.pc, vcpu->arch.badv);
arch/loongarch/kvm/exit.c
544
int kvm_emu_mmio_write(struct kvm_vcpu *vcpu, larch_inst inst)
arch/loongarch/kvm/exit.c
559
op8 = (inst.word >> 24) & 0xff;
arch/loongarch/kvm/exit.c
564
rd = inst.reg2i14_format.rd;
arch/loongarch/kvm/exit.c
565
opcode = inst.reg2i14_format.opcode;
arch/loongarch/kvm/exit.c
582
rd = inst.reg2i12_format.rd;
arch/loongarch/kvm/exit.c
583
opcode = inst.reg2i12_format.opcode;
arch/loongarch/kvm/exit.c
609
rd = inst.reg3_format.rd;
arch/loongarch/kvm/exit.c
610
opcode = inst.reg3_format.opcode;
arch/loongarch/kvm/exit.c
660
inst.word, vcpu->arch.pc, vcpu->arch.badv);
arch/loongarch/kvm/exit.c
670
larch_inst inst;
arch/loongarch/kvm/exit.c
684
inst.word = vcpu->arch.badi;
arch/loongarch/kvm/exit.c
686
er = kvm_emu_mmio_write(vcpu, inst);
arch/loongarch/kvm/exit.c
694
er = kvm_emu_mmio_read(vcpu, inst);
arch/loongarch/kvm/exit.c
881
larch_inst inst;
arch/loongarch/kvm/exit.c
884
inst.word = vcpu->arch.badi;
arch/loongarch/kvm/exit.c
885
code = inst.reg0i15_format.immediate;
arch/loongarch/kvm/exit.c
940
unsigned int inst;
arch/loongarch/kvm/exit.c
944
inst = vcpu->arch.badi;
arch/loongarch/kvm/exit.c
947
ecode, vcpu->arch.pc, inst, badv, read_gcsr_estat());
arch/loongarch/net/bpf_jit.c
1644
u32 *inst;
arch/loongarch/net/bpf_jit.c
1646
inst = kvmalloc(len, GFP_KERNEL);
arch/loongarch/net/bpf_jit.c
1647
if (!inst)
arch/loongarch/net/bpf_jit.c
1651
inst[i] = INSN_BREAK;
arch/loongarch/net/bpf_jit.c
1655
if (larch_insn_text_copy(dst, inst, len))
arch/loongarch/net/bpf_jit.c
1660
kvfree(inst);
arch/m68k/include/asm/uaccess.h
105
#define __get_user_asm(inst, res, x, ptr, type, bwl, reg, err) ({ \
arch/m68k/include/asm/uaccess.h
108
"1: "inst"."#bwl" %2,%1\n" \
arch/m68k/include/asm/uaccess.h
126
#define __get_user_asm8(inst, res, x, ptr) \
arch/m68k/include/asm/uaccess.h
135
"1: "inst".l (%2)+,%1\n" \
arch/m68k/include/asm/uaccess.h
136
"2: "inst".l (%2),%R1\n" \
arch/m68k/include/asm/uaccess.h
31
#define __put_user_asm(inst, res, x, ptr, bwl, reg, err) \
arch/m68k/include/asm/uaccess.h
33
"1: "inst"."#bwl" %2,%1\n" \
arch/m68k/include/asm/uaccess.h
49
#define __put_user_asm8(inst, res, x, ptr) \
arch/m68k/include/asm/uaccess.h
54
"1: "inst".l %2,(%1)+\n" \
arch/m68k/include/asm/uaccess.h
55
"2: "inst".l %R2,(%1)\n" \
arch/microblaze/mm/fault.c
48
unsigned int inst;
arch/microblaze/mm/fault.c
50
if (get_user(inst, (unsigned int __user *)regs->pc))
arch/microblaze/mm/fault.c
53
if (((inst >> 21) & 0x1f) != 1)
arch/microblaze/mm/fault.c
56
if ((inst & 0xd0000000) == 0xd0000000)
arch/mips/include/asm/branch.h
89
union mips16e_instruction *inst)
arch/mips/include/asm/branch.h
92
if (inst->ri.opcode == MIPS16e_extend_op) {
arch/mips/include/asm/kvm_host.h
867
enum emulation_result kvm_mips_emulate_store(union mips_instruction inst,
arch/mips/include/asm/kvm_host.h
870
enum emulation_result kvm_mips_emulate_load(union mips_instruction inst,
arch/mips/include/asm/kvm_host.h
880
union mips_instruction inst);
arch/mips/include/asm/mips-r2-to-r6-emul.h
78
int (*func)(struct pt_regs *regs, u32 inst);
arch/mips/include/asm/mips-r2-to-r6-emul.h
87
static inline int mipsr2_decoder(struct pt_regs *regs, u32 inst,
arch/mips/include/asm/mips-r2-to-r6-emul.h
95
extern int mipsr2_decoder(struct pt_regs *regs, u32 inst,
arch/mips/kernel/branch.c
31
unsigned short inst;
arch/mips/kernel/branch.c
323
union mips16e_instruction inst;
arch/mips/kernel/branch.c
332
if (__get_user(inst.full, addr)) {
arch/mips/kernel/branch.c
337
switch (inst.ri.opcode) {
arch/mips/kernel/branch.c
35
if (__get_user(inst, (u16 __user *) msk_isa16_mode(epc))) {
arch/mips/kernel/branch.c
351
fullinst = ((unsigned)inst.full << 16) | inst2;
arch/mips/kernel/branch.c
365
if (!inst.jal.x)
arch/mips/kernel/branch.c
374
if (inst.rr.func == MIPS16e_jr_func) {
arch/mips/kernel/branch.c
376
if (inst.rr.ra)
arch/mips/kernel/branch.c
380
regs->regs[reg16to32[inst.rr.rx]];
arch/mips/kernel/branch.c
382
if (inst.rr.l) {
arch/mips/kernel/branch.c
383
if (inst.rr.nd)
arch/mips/kernel/branch.c
43
inst_mips16e.full = inst;
arch/mips/kernel/branch.c
48
} else if (mm_insn_16bit(inst))
arch/mips/kernel/mips-r2-to-r6-emul.c
1108
if (MIPSInst_RT(inst)) {
arch/mips/kernel/mips-r2-to-r6-emul.c
1137
switch (MIPSInst_OPCODE(inst)) {
arch/mips/kernel/mips-r2-to-r6-emul.c
1206
rt = regs->regs[MIPSInst_RT(inst)];
arch/mips/kernel/mips-r2-to-r6-emul.c
1207
vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
arch/mips/kernel/mips-r2-to-r6-emul.c
1271
if (MIPSInst_RT(inst) && !err)
arch/mips/kernel/mips-r2-to-r6-emul.c
1272
regs->regs[MIPSInst_RT(inst)] = rt;
arch/mips/kernel/mips-r2-to-r6-emul.c
1279
rt = regs->regs[MIPSInst_RT(inst)];
arch/mips/kernel/mips-r2-to-r6-emul.c
1280
vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
arch/mips/kernel/mips-r2-to-r6-emul.c
1345
if (MIPSInst_RT(inst) && !err)
arch/mips/kernel/mips-r2-to-r6-emul.c
1346
regs->regs[MIPSInst_RT(inst)] = rt;
arch/mips/kernel/mips-r2-to-r6-emul.c
1353
rt = regs->regs[MIPSInst_RT(inst)];
arch/mips/kernel/mips-r2-to-r6-emul.c
1354
vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
arch/mips/kernel/mips-r2-to-r6-emul.c
1423
rt = regs->regs[MIPSInst_RT(inst)];
arch/mips/kernel/mips-r2-to-r6-emul.c
1424
vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
arch/mips/kernel/mips-r2-to-r6-emul.c
1498
rt = regs->regs[MIPSInst_RT(inst)];
arch/mips/kernel/mips-r2-to-r6-emul.c
1499
vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
arch/mips/kernel/mips-r2-to-r6-emul.c
1605
if (MIPSInst_RT(inst) && !err)
arch/mips/kernel/mips-r2-to-r6-emul.c
1606
regs->regs[MIPSInst_RT(inst)] = rt;
arch/mips/kernel/mips-r2-to-r6-emul.c
1617
rt = regs->regs[MIPSInst_RT(inst)];
arch/mips/kernel/mips-r2-to-r6-emul.c
1618
vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
arch/mips/kernel/mips-r2-to-r6-emul.c
1724
if (MIPSInst_RT(inst) && !err)
arch/mips/kernel/mips-r2-to-r6-emul.c
1725
regs->regs[MIPSInst_RT(inst)] = rt;
arch/mips/kernel/mips-r2-to-r6-emul.c
1736
rt = regs->regs[MIPSInst_RT(inst)];
arch/mips/kernel/mips-r2-to-r6-emul.c
1737
vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
arch/mips/kernel/mips-r2-to-r6-emul.c
1854
rt = regs->regs[MIPSInst_RT(inst)];
arch/mips/kernel/mips-r2-to-r6-emul.c
1855
vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
arch/mips/kernel/mips-r2-to-r6-emul.c
1967
vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
arch/mips/kernel/mips-r2-to-r6-emul.c
2016
if (MIPSInst_RT(inst) && !err)
arch/mips/kernel/mips-r2-to-r6-emul.c
2017
regs->regs[MIPSInst_RT(inst)] = res;
arch/mips/kernel/mips-r2-to-r6-emul.c
2023
vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
arch/mips/kernel/mips-r2-to-r6-emul.c
2055
res = regs->regs[MIPSInst_RT(inst)];
arch/mips/kernel/mips-r2-to-r6-emul.c
2073
if (MIPSInst_RT(inst) && !err)
arch/mips/kernel/mips-r2-to-r6-emul.c
2074
regs->regs[MIPSInst_RT(inst)] = res;
arch/mips/kernel/mips-r2-to-r6-emul.c
2086
vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
arch/mips/kernel/mips-r2-to-r6-emul.c
2134
if (MIPSInst_RT(inst) && !err)
arch/mips/kernel/mips-r2-to-r6-emul.c
2135
regs->regs[MIPSInst_RT(inst)] = res;
arch/mips/kernel/mips-r2-to-r6-emul.c
2147
vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
arch/mips/kernel/mips-r2-to-r6-emul.c
2179
res = regs->regs[MIPSInst_RT(inst)];
arch/mips/kernel/mips-r2-to-r6-emul.c
2197
if (MIPSInst_RT(inst) && !err)
arch/mips/kernel/mips-r2-to-r6-emul.c
2198
regs->regs[MIPSInst_RT(inst)] = res;
arch/mips/kernel/mips-r2-to-r6-emul.c
2216
err = get_user(inst, (u32 __user *)regs->cp0_epc);
arch/mips/kernel/mips-r2-to-r6-emul.c
885
static inline int mipsr2_find_op_func(struct pt_regs *regs, u32 inst,
arch/mips/kernel/mips-r2-to-r6-emul.c
892
if ((inst & p->mask) == p->code) {
arch/mips/kernel/mips-r2-to-r6-emul.c
893
err = (p->func)(regs, inst);
arch/mips/kernel/mips-r2-to-r6-emul.c
906
int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31)
arch/mips/kernel/mips-r2-to-r6-emul.c
925
inst, epc, pass);
arch/mips/kernel/mips-r2-to-r6-emul.c
927
switch (MIPSInst_OPCODE(inst)) {
arch/mips/kernel/mips-r2-to-r6-emul.c
929
err = mipsr2_find_op_func(regs, inst, spec_op_table);
arch/mips/kernel/mips-r2-to-r6-emul.c
937
err = mipsr2_find_op_func(regs, inst, spec2_op_table);
arch/mips/kernel/mips-r2-to-r6-emul.c
940
rt = MIPSInst_RT(inst);
arch/mips/kernel/mips-r2-to-r6-emul.c
941
rs = MIPSInst_RS(inst);
arch/mips/kernel/mips-r2-to-r6-emul.c
944
if ((long)regs->regs[rs] >= MIPSInst_SIMM(inst))
arch/mips/kernel/mips-r2-to-r6-emul.c
951
if (regs->regs[rs] >= MIPSInst_UIMM(inst))
arch/mips/kernel/mips-r2-to-r6-emul.c
958
if ((long)regs->regs[rs] < MIPSInst_SIMM(inst))
arch/mips/kernel/mips-r2-to-r6-emul.c
965
if (regs->regs[rs] < MIPSInst_UIMM(inst))
arch/mips/kernel/mips-r2-to-r6-emul.c
972
if (regs->regs[rs] == MIPSInst_SIMM(inst))
arch/mips/kernel/mips-r2-to-r6-emul.c
979
if (regs->regs[rs] != MIPSInst_SIMM(inst))
arch/mips/kernel/traps.c
827
union mips_instruction inst = { .word = opcode };
arch/mips/kernel/traps.c
833
switch (inst.i_format.opcode) {
arch/mips/kernel/uprobes.c
30
union mips_instruction inst;
arch/mips/kernel/uprobes.c
39
inst.word = aup->insn[0];
arch/mips/kernel/uprobes.c
41
if (__insn_is_compact_branch(inst)) {
arch/mips/kernel/uprobes.c
46
aup->ixol[0] = aup->insn[insn_has_delay_slot(inst)];
arch/mips/kernel/uprobes.c
64
union mips_instruction inst;
arch/mips/kernel/uprobes.c
66
inst.word = *insn;
arch/mips/kernel/uprobes.c
68
switch (inst.i_format.opcode) {
arch/mips/kernel/uprobes.c
70
switch (inst.r_format.func) {
arch/mips/kernel/uprobes.c
83
switch (inst.u_format.rt) {
arch/mips/kvm/emulate.c
1193
rt = inst.loongson3_lsdc2_format.rt;
arch/mips/kvm/emulate.c
1194
switch (inst.loongson3_lsdc2_format.opcode1) {
arch/mips/kvm/emulate.c
1237
inst.word);
arch/mips/kvm/emulate.c
1244
inst.word);
arch/mips/kvm/emulate.c
1268
enum emulation_result kvm_mips_emulate_load(union mips_instruction inst,
arch/mips/kvm/emulate.c
1278
rt = inst.i_format.rt;
arch/mips/kvm/emulate.c
1279
op = inst.i_format.opcode;
arch/mips/kvm/emulate.c
1453
rt = inst.loongson3_lsdc2_format.rt;
arch/mips/kvm/emulate.c
1454
switch (inst.loongson3_lsdc2_format.opcode1) {
arch/mips/kvm/emulate.c
1481
inst.word);
arch/mips/kvm/emulate.c
1489
inst.word);
arch/mips/kvm/emulate.c
968
enum emulation_result kvm_mips_emulate_store(union mips_instruction inst,
arch/mips/kvm/emulate.c
989
rt = inst.i_format.rt;
arch/mips/kvm/emulate.c
996
switch (inst.i_format.opcode) {
arch/mips/kvm/hypcall.c
18
union mips_instruction inst)
arch/mips/kvm/hypcall.c
20
unsigned int code = (inst.co_format.code >> 5) & 0x3ff;
arch/mips/kvm/mips.c
1175
u32 inst;
arch/mips/kvm/mips.c
1293
inst = 0;
arch/mips/kvm/mips.c
1294
kvm_get_badinstr(opc, vcpu, &inst);
arch/mips/kvm/mips.c
1296
exccode, opc, inst, badvaddr,
arch/mips/kvm/vz.c
1006
val = mips_process_maar(inst.c0r_format.rs,
arch/mips/kvm/vz.c
1066
curr_pc, __func__, inst.word);
arch/mips/kvm/vz.c
1074
static enum emulation_result kvm_vz_gpsi_cache(union mips_instruction inst,
arch/mips/kvm/vz.c
1093
base = inst.i_format.rs;
arch/mips/kvm/vz.c
1094
op_inst = inst.i_format.rt;
arch/mips/kvm/vz.c
1096
offset = inst.spec3_format.simmediate;
arch/mips/kvm/vz.c
1098
offset = inst.i_format.simmediate;
arch/mips/kvm/vz.c
1143
static enum emulation_result kvm_vz_gpsi_lwc2(union mips_instruction inst,
arch/mips/kvm/vz.c
1161
rs = inst.loongson3_lscsr_format.rs;
arch/mips/kvm/vz.c
1162
rd = inst.loongson3_lscsr_format.rd;
arch/mips/kvm/vz.c
1163
switch (inst.loongson3_lscsr_format.fr) {
arch/mips/kvm/vz.c
1195
inst.loongson3_lscsr_format.fr, vcpu->arch.gprs[rs], curr_pc);
arch/mips/kvm/vz.c
1203
curr_pc, __func__, inst.word, inst.loongson3_lscsr_format.fr);
arch/mips/kvm/vz.c
1217
union mips_instruction inst;
arch/mips/kvm/vz.c
1226
err = kvm_get_badinstr(opc, vcpu, &inst.word);
arch/mips/kvm/vz.c
1230
switch (inst.r_format.opcode) {
arch/mips/kvm/vz.c
1232
er = kvm_vz_gpsi_cop0(inst, opc, cause, vcpu);
arch/mips/kvm/vz.c
1237
er = kvm_vz_gpsi_cache(inst, opc, cause, vcpu);
arch/mips/kvm/vz.c
1242
er = kvm_vz_gpsi_lwc2(inst, opc, cause, vcpu);
arch/mips/kvm/vz.c
1246
switch (inst.spec3_format.func) {
arch/mips/kvm/vz.c
1250
er = kvm_vz_gpsi_cache(inst, opc, cause, vcpu);
arch/mips/kvm/vz.c
1254
if (inst.r_format.rs || (inst.r_format.re >> 3))
arch/mips/kvm/vz.c
1257
rd = inst.r_format.rd;
arch/mips/kvm/vz.c
1258
rt = inst.r_format.rt;
arch/mips/kvm/vz.c
1259
sel = inst.r_format.re & 0x7;
arch/mips/kvm/vz.c
1285
opc, inst.word);
arch/mips/kvm/vz.c
1299
union mips_instruction inst;
arch/mips/kvm/vz.c
1307
err = kvm_get_badinstr(opc, vcpu, &inst.word);
arch/mips/kvm/vz.c
1312
if (inst.c0r_format.opcode == cop0_op &&
arch/mips/kvm/vz.c
1313
inst.c0r_format.rs == mtc_op &&
arch/mips/kvm/vz.c
1314
inst.c0r_format.z == 0) {
arch/mips/kvm/vz.c
1315
int rt = inst.c0r_format.rt;
arch/mips/kvm/vz.c
1316
int rd = inst.c0r_format.rd;
arch/mips/kvm/vz.c
1317
int sel = inst.c0r_format.sel;
arch/mips/kvm/vz.c
1405
opc, inst.word);
arch/mips/kvm/vz.c
1413
opc, inst.word);
arch/mips/kvm/vz.c
1436
union mips_instruction inst;
arch/mips/kvm/vz.c
1442
err = kvm_get_badinstr(opc, vcpu, &inst.word);
arch/mips/kvm/vz.c
1455
er = kvm_mips_emul_hypcall(vcpu, inst);
arch/mips/kvm/vz.c
1467
u32 inst;
arch/mips/kvm/vz.c
1474
kvm_get_badinstr(opc, vcpu, &inst);
arch/mips/kvm/vz.c
1477
gexccode, opc, inst, read_gc0_status());
arch/mips/kvm/vz.c
1629
union mips_instruction inst;
arch/mips/kvm/vz.c
1643
err = kvm_get_badinstr(opc, vcpu, &inst.word);
arch/mips/kvm/vz.c
1650
er = kvm_mips_emulate_load(inst, cause, vcpu);
arch/mips/kvm/vz.c
1676
union mips_instruction inst;
arch/mips/kvm/vz.c
1690
err = kvm_get_badinstr(opc, vcpu, &inst.word);
arch/mips/kvm/vz.c
1697
er = kvm_mips_emulate_store(inst, cause, vcpu);
arch/mips/kvm/vz.c
577
static bool is_eva_access(union mips_instruction inst)
arch/mips/kvm/vz.c
579
if (inst.spec3_format.opcode != spec3_op)
arch/mips/kvm/vz.c
582
switch (inst.spec3_format.func) {
arch/mips/kvm/vz.c
649
union mips_instruction inst;
arch/mips/kvm/vz.c
668
err = kvm_get_badinstr(opc, vcpu, &inst.word);
arch/mips/kvm/vz.c
669
if (!err && is_eva_access(inst))
arch/mips/kvm/vz.c
823
u32 inst = 0;
arch/mips/kvm/vz.c
830
kvm_get_badinstr(opc, vcpu, &inst);
arch/mips/kvm/vz.c
833
exccode, opc, inst, badvaddr,
arch/mips/kvm/vz.c
875
static enum emulation_result kvm_vz_gpsi_cop0(union mips_instruction inst,
arch/mips/kvm/vz.c
894
if (inst.co_format.co) {
arch/mips/kvm/vz.c
895
switch (inst.co_format.func) {
arch/mips/kvm/vz.c
903
rt = inst.c0r_format.rt;
arch/mips/kvm/vz.c
904
rd = inst.c0r_format.rd;
arch/mips/kvm/vz.c
905
sel = inst.c0r_format.sel;
arch/mips/kvm/vz.c
907
switch (inst.c0r_format.rs) {
arch/mips/kvm/vz.c
964
if (inst.c0r_format.rs == mfc_op)
arch/mips/kvm/vz.c
969
trace_kvm_hwr(vcpu, (inst.c0r_format.rs == mfc_op) ?
arch/mips/kvm/vz.c
980
trace_kvm_hwr(vcpu, (inst.c0r_format.rs == mtc_op) ?
arch/parisc/include/asm/traps.h
17
unsigned long parisc_acctyp(unsigned long code, unsigned int inst);
arch/parisc/mm/fault.c
109
if (bits23_25set(inst) == BITSSET)
arch/parisc/mm/fault.c
54
parisc_acctyp(unsigned long code, unsigned int inst)
arch/parisc/mm/fault.c
59
switch (inst & 0xf0000000) {
arch/parisc/mm/fault.c
70
if (bit22set(inst))
arch/parisc/mm/fault.c
75
if (bit22set(inst)) {
arch/parisc/mm/fault.c
93
if (isGraphicsFlushRead(inst))
arch/powerpc/include/asm/disassemble.h
14
static inline unsigned int get_op(u32 inst)
arch/powerpc/include/asm/disassemble.h
16
return inst >> 26;
arch/powerpc/include/asm/disassemble.h
19
static inline unsigned int get_xop(u32 inst)
arch/powerpc/include/asm/disassemble.h
21
return (inst >> 1) & 0x3ff;
arch/powerpc/include/asm/disassemble.h
24
static inline unsigned int get_sprn(u32 inst)
arch/powerpc/include/asm/disassemble.h
26
return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0);
arch/powerpc/include/asm/disassemble.h
29
static inline unsigned int get_dcrn(u32 inst)
arch/powerpc/include/asm/disassemble.h
31
return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0);
arch/powerpc/include/asm/disassemble.h
34
static inline unsigned int get_tmrn(u32 inst)
arch/powerpc/include/asm/disassemble.h
36
return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0);
arch/powerpc/include/asm/disassemble.h
39
static inline unsigned int get_rt(u32 inst)
arch/powerpc/include/asm/disassemble.h
41
return (inst >> 21) & 0x1f;
arch/powerpc/include/asm/disassemble.h
44
static inline unsigned int get_rs(u32 inst)
arch/powerpc/include/asm/disassemble.h
46
return (inst >> 21) & 0x1f;
arch/powerpc/include/asm/disassemble.h
49
static inline unsigned int get_ra(u32 inst)
arch/powerpc/include/asm/disassemble.h
51
return (inst >> 16) & 0x1f;
arch/powerpc/include/asm/disassemble.h
54
static inline unsigned int get_rb(u32 inst)
arch/powerpc/include/asm/disassemble.h
56
return (inst >> 11) & 0x1f;
arch/powerpc/include/asm/disassemble.h
59
static inline unsigned int get_rc(u32 inst)
arch/powerpc/include/asm/disassemble.h
61
return inst & 0x1;
arch/powerpc/include/asm/disassemble.h
64
static inline unsigned int get_ws(u32 inst)
arch/powerpc/include/asm/disassemble.h
66
return (inst >> 11) & 0x1f;
arch/powerpc/include/asm/disassemble.h
69
static inline unsigned int get_d(u32 inst)
arch/powerpc/include/asm/disassemble.h
71
return inst & 0xffff;
arch/powerpc/include/asm/disassemble.h
74
static inline unsigned int get_oc(u32 inst)
arch/powerpc/include/asm/disassemble.h
76
return (inst >> 11) & 0x7fff;
arch/powerpc/include/asm/disassemble.h
79
static inline unsigned int get_tx_or_sx(u32 inst)
arch/powerpc/include/asm/disassemble.h
81
return (inst) & 0x1;
arch/powerpc/include/asm/disassemble.h
84
#define IS_XFORM(inst) (get_op(inst) == 31)
arch/powerpc/include/asm/disassemble.h
85
#define IS_DSFORM(inst) (get_op(inst) >= 56)
arch/powerpc/include/asm/inst.h
142
static inline int __copy_inst_from_kernel_nofault(ppc_inst_t *inst, u32 *src)
arch/powerpc/include/asm/inst.h
149
*inst = ppc_inst_prefix(val, suffix);
arch/powerpc/include/asm/inst.h
151
*inst = ppc_inst(val);
arch/powerpc/include/asm/inst.h
158
static inline int copy_inst_from_kernel_nofault(ppc_inst_t *inst, u32 *src)
arch/powerpc/include/asm/inst.h
163
return __copy_inst_from_kernel_nofault(inst, src);
arch/powerpc/include/asm/kvm_book3s.h
274
extern u32 kvmppc_alignment_dsisr(struct kvm_vcpu *vcpu, unsigned int inst);
arch/powerpc/include/asm/kvm_book3s.h
275
extern ulong kvmppc_alignment_dar(struct kvm_vcpu *vcpu, unsigned int inst);
arch/powerpc/include/asm/kvm_ppc.h
295
unsigned int inst, int *advance);
arch/powerpc/include/asm/kvm_ppc.h
328
enum instruction_fetch_type type, ppc_inst_t *inst)
arch/powerpc/include/asm/kvm_ppc.h
340
*inst = ppc_inst(KVM_INST_FETCH_FAILED);
arch/powerpc/include/asm/kvm_ppc.h
353
*inst = ppc_inst_prefix(prefix, suffix);
arch/powerpc/include/asm/kvm_ppc.h
361
*inst = ppc_inst(fetched_inst);
arch/powerpc/include/asm/kvm_ppc.h
376
static inline u32 kvmppc_get_field(u64 inst, int msb, int lsb)
arch/powerpc/include/asm/kvm_ppc.h
384
r = (inst >> (63 - lsb)) & mask;
arch/powerpc/include/asm/kvm_ppc.h
392
static inline u32 kvmppc_set_field(u64 inst, int msb, int lsb, int value)
arch/powerpc/include/asm/kvm_ppc.h
400
r = (inst & ~mask) | ((value << (63 - lsb)) & mask);
arch/powerpc/include/asm/kvm_ppc.h
89
unsigned long *inst);
arch/powerpc/include/asm/probes.h
35
static inline bool can_single_step(u32 inst)
arch/powerpc/include/asm/probes.h
37
switch (get_op(inst)) {
arch/powerpc/include/asm/probes.h
42
switch (get_xop(inst)) {
arch/powerpc/include/asm/probes.h
59
switch (get_xop(inst)) {
arch/powerpc/include/asm/static_call.h
10
inst " \n" \
arch/powerpc/include/asm/static_call.h
5
#define __PPC_SCT(name, inst) \
arch/powerpc/kernel/epapr_paravirt.c
40
ppc_inst_t inst = ppc_inst(be32_to_cpu(insts[i]));
arch/powerpc/kernel/epapr_paravirt.c
41
patch_instruction(epapr_hypercall_start + i, inst);
arch/powerpc/kernel/epapr_paravirt.c
43
patch_instruction(epapr_ev_idle_start + i, inst);
arch/powerpc/kernel/kvm.c
100
static void __init kvm_patch_ins_std(u32 *inst, long addr, u32 rt)
arch/powerpc/kernel/kvm.c
103
kvm_patch_ins(inst, KVM_INST_STD | rt | (addr & 0x0000fffc));
arch/powerpc/kernel/kvm.c
105
kvm_patch_ins(inst, KVM_INST_STW | rt | ((addr + 4) & 0x0000fffc));
arch/powerpc/kernel/kvm.c
109
static void __init kvm_patch_ins_stw(u32 *inst, long addr, u32 rt)
arch/powerpc/kernel/kvm.c
111
kvm_patch_ins(inst, KVM_INST_STW | rt | (addr & 0x0000fffc));
arch/powerpc/kernel/kvm.c
114
static void __init kvm_patch_ins_nop(u32 *inst)
arch/powerpc/kernel/kvm.c
116
kvm_patch_ins(inst, KVM_INST_NOP);
arch/powerpc/kernel/kvm.c
119
static void __init kvm_patch_ins_b(u32 *inst, int addr)
arch/powerpc/kernel/kvm.c
125
if ((ulong)inst < (ulong)&__end_interrupts)
arch/powerpc/kernel/kvm.c
129
kvm_patch_ins(inst, KVM_INST_B | (addr & KVM_INST_B_MASK));
arch/powerpc/kernel/kvm.c
155
static void __init kvm_patch_ins_mtmsrd(u32 *inst, u32 rt)
arch/powerpc/kernel/kvm.c
167
distance_start = (ulong)p - (ulong)inst;
arch/powerpc/kernel/kvm.c
168
next_inst = ((ulong)inst + 4);
arch/powerpc/kernel/kvm.c
194
p[kvm_emulate_mtmsrd_orig_ins_offs] = *inst;
arch/powerpc/kernel/kvm.c
198
kvm_patch_ins_b(inst, distance_start);
arch/powerpc/kernel/kvm.c
208
static void __init kvm_patch_ins_mtmsr(u32 *inst, u32 rt)
arch/powerpc/kernel/kvm.c
220
distance_start = (ulong)p - (ulong)inst;
arch/powerpc/kernel/kvm.c
221
next_inst = ((ulong)inst + 4);
arch/powerpc/kernel/kvm.c
254
p[kvm_emulate_mtmsr_orig_ins_offs] = *inst;
arch/powerpc/kernel/kvm.c
258
kvm_patch_ins_b(inst, distance_start);
arch/powerpc/kernel/kvm.c
269
static void __init kvm_patch_ins_wrtee(u32 *inst, u32 rt, int imm_one)
arch/powerpc/kernel/kvm.c
281
distance_start = (ulong)p - (ulong)inst;
arch/powerpc/kernel/kvm.c
282
next_inst = ((ulong)inst + 4);
arch/powerpc/kernel/kvm.c
315
p[kvm_emulate_wrtee_orig_ins_offs] = *inst;
arch/powerpc/kernel/kvm.c
319
kvm_patch_ins_b(inst, distance_start);
arch/powerpc/kernel/kvm.c
326
static void __init kvm_patch_ins_wrteei_0(u32 *inst)
arch/powerpc/kernel/kvm.c
338
distance_start = (ulong)p - (ulong)inst;
arch/powerpc/kernel/kvm.c
339
next_inst = ((ulong)inst + 4);
arch/powerpc/kernel/kvm.c
353
kvm_patch_ins_b(inst, distance_start);
arch/powerpc/kernel/kvm.c
367
static void __init kvm_patch_ins_mtsrin(u32 *inst, u32 rt, u32 rb)
arch/powerpc/kernel/kvm.c
379
distance_start = (ulong)p - (ulong)inst;
arch/powerpc/kernel/kvm.c
380
next_inst = ((ulong)inst + 4);
arch/powerpc/kernel/kvm.c
394
p[kvm_emulate_mtsrin_orig_ins_offs] = *inst;
arch/powerpc/kernel/kvm.c
398
kvm_patch_ins_b(inst, distance_start);
arch/powerpc/kernel/kvm.c
418
static void __init kvm_check_ins(u32 *inst, u32 features)
arch/powerpc/kernel/kvm.c
420
u32 _inst = *inst;
arch/powerpc/kernel/kvm.c
427
kvm_patch_ins_ld(inst, magic_var(msr), inst_rt);
arch/powerpc/kernel/kvm.c
430
kvm_patch_ins_ld(inst, magic_var(sprg0), inst_rt);
arch/powerpc/kernel/kvm.c
433
kvm_patch_ins_ld(inst, magic_var(sprg1), inst_rt);
arch/powerpc/kernel/kvm.c
436
kvm_patch_ins_ld(inst, magic_var(sprg2), inst_rt);
arch/powerpc/kernel/kvm.c
439
kvm_patch_ins_ld(inst, magic_var(sprg3), inst_rt);
arch/powerpc/kernel/kvm.c
442
kvm_patch_ins_ld(inst, magic_var(srr0), inst_rt);
arch/powerpc/kernel/kvm.c
445
kvm_patch_ins_ld(inst, magic_var(srr1), inst_rt);
arch/powerpc/kernel/kvm.c
452
kvm_patch_ins_ld(inst, magic_var(dar), inst_rt);
arch/powerpc/kernel/kvm.c
455
kvm_patch_ins_lwz(inst, magic_var(dsisr), inst_rt);
arch/powerpc/kernel/kvm.c
461
kvm_patch_ins_lwz(inst, magic_var(mas0), inst_rt);
arch/powerpc/kernel/kvm.c
465
kvm_patch_ins_lwz(inst, magic_var(mas1), inst_rt);
arch/powerpc/kernel/kvm.c
469
kvm_patch_ins_ld(inst, magic_var(mas2), inst_rt);
arch/powerpc/kernel/kvm.c
473
kvm_patch_ins_lwz(inst, magic_var(mas7_3) + 4, inst_rt);
arch/powerpc/kernel/kvm.c
477
kvm_patch_ins_lwz(inst, magic_var(mas4), inst_rt);
arch/powerpc/kernel/kvm.c
481
kvm_patch_ins_lwz(inst, magic_var(mas6), inst_rt);
arch/powerpc/kernel/kvm.c
485
kvm_patch_ins_lwz(inst, magic_var(mas7_3), inst_rt);
arch/powerpc/kernel/kvm.c
494
kvm_patch_ins_ld(inst, magic_var(sprg4), inst_rt);
arch/powerpc/kernel/kvm.c
501
kvm_patch_ins_ld(inst, magic_var(sprg5), inst_rt);
arch/powerpc/kernel/kvm.c
508
kvm_patch_ins_ld(inst, magic_var(sprg6), inst_rt);
arch/powerpc/kernel/kvm.c
515
kvm_patch_ins_ld(inst, magic_var(sprg7), inst_rt);
arch/powerpc/kernel/kvm.c
521
kvm_patch_ins_lwz(inst, magic_var(esr), inst_rt);
arch/powerpc/kernel/kvm.c
527
kvm_patch_ins_lwz(inst, magic_var(pir), inst_rt);
arch/powerpc/kernel/kvm.c
533
kvm_patch_ins_std(inst, magic_var(sprg0), inst_rt);
arch/powerpc/kernel/kvm.c
536
kvm_patch_ins_std(inst, magic_var(sprg1), inst_rt);
arch/powerpc/kernel/kvm.c
539
kvm_patch_ins_std(inst, magic_var(sprg2), inst_rt);
arch/powerpc/kernel/kvm.c
542
kvm_patch_ins_std(inst, magic_var(sprg3), inst_rt);
arch/powerpc/kernel/kvm.c
545
kvm_patch_ins_std(inst, magic_var(srr0), inst_rt);
arch/powerpc/kernel/kvm.c
548
kvm_patch_ins_std(inst, magic_var(srr1), inst_rt);
arch/powerpc/kernel/kvm.c
555
kvm_patch_ins_std(inst, magic_var(dar), inst_rt);
arch/powerpc/kernel/kvm.c
558
kvm_patch_ins_stw(inst, magic_var(dsisr), inst_rt);
arch/powerpc/kernel/kvm.c
563
kvm_patch_ins_stw(inst, magic_var(mas0), inst_rt);
arch/powerpc/kernel/kvm.c
567
kvm_patch_ins_stw(inst, magic_var(mas1), inst_rt);
arch/powerpc/kernel/kvm.c
571
kvm_patch_ins_std(inst, magic_var(mas2), inst_rt);
arch/powerpc/kernel/kvm.c
575
kvm_patch_ins_stw(inst, magic_var(mas7_3) + 4, inst_rt);
arch/powerpc/kernel/kvm.c
579
kvm_patch_ins_stw(inst, magic_var(mas4), inst_rt);
arch/powerpc/kernel/kvm.c
583
kvm_patch_ins_stw(inst, magic_var(mas6), inst_rt);
arch/powerpc/kernel/kvm.c
587
kvm_patch_ins_stw(inst, magic_var(mas7_3), inst_rt);
arch/powerpc/kernel/kvm.c
593
kvm_patch_ins_std(inst, magic_var(sprg4), inst_rt);
arch/powerpc/kernel/kvm.c
597
kvm_patch_ins_std(inst, magic_var(sprg5), inst_rt);
arch/powerpc/kernel/kvm.c
601
kvm_patch_ins_std(inst, magic_var(sprg6), inst_rt);
arch/powerpc/kernel/kvm.c
605
kvm_patch_ins_std(inst, magic_var(sprg7), inst_rt);
arch/powerpc/kernel/kvm.c
611
kvm_patch_ins_stw(inst, magic_var(esr), inst_rt);
arch/powerpc/kernel/kvm.c
617
kvm_patch_ins_nop(inst);
arch/powerpc/kernel/kvm.c
622
kvm_patch_ins_mtmsrd(inst, inst_rt);
arch/powerpc/kernel/kvm.c
626
kvm_patch_ins_mtmsr(inst, inst_rt);
arch/powerpc/kernel/kvm.c
630
kvm_patch_ins_wrtee(inst, inst_rt, 0);
arch/powerpc/kernel/kvm.c
640
kvm_patch_ins_mtsrin(inst, inst_rt, inst_rb);
arch/powerpc/kernel/kvm.c
649
kvm_patch_ins_wrteei_0(inst);
arch/powerpc/kernel/kvm.c
653
kvm_patch_ins_wrtee(inst, 0, 1);
arch/powerpc/kernel/kvm.c
71
static void __init kvm_patch_ins(u32 *inst, u32 new_inst)
arch/powerpc/kernel/kvm.c
73
*inst = new_inst;
arch/powerpc/kernel/kvm.c
74
flush_icache_range((ulong)inst, (ulong)inst + 4);
arch/powerpc/kernel/kvm.c
77
static void __init kvm_patch_ins_ll(u32 *inst, long addr, u32 rt)
arch/powerpc/kernel/kvm.c
80
kvm_patch_ins(inst, KVM_INST_LD | rt | (addr & 0x0000fffc));
arch/powerpc/kernel/kvm.c
82
kvm_patch_ins(inst, KVM_INST_LWZ | rt | (addr & 0x0000fffc));
arch/powerpc/kernel/kvm.c
86
static void __init kvm_patch_ins_ld(u32 *inst, long addr, u32 rt)
arch/powerpc/kernel/kvm.c
89
kvm_patch_ins(inst, KVM_INST_LD | rt | (addr & 0x0000fffc));
arch/powerpc/kernel/kvm.c
91
kvm_patch_ins(inst, KVM_INST_LWZ | rt | ((addr + 4) & 0x0000fffc));
arch/powerpc/kernel/kvm.c
95
static void __init kvm_patch_ins_lwz(u32 *inst, long addr, u32 rt)
arch/powerpc/kernel/kvm.c
97
kvm_patch_ins(inst, KVM_INST_LWZ | rt | (addr & 0x0000ffff));
arch/powerpc/kernel/trace/ftrace.c
203
ppc_inst_t inst;
arch/powerpc/kernel/trace/ftrace.c
267
ret = ftrace_get_call_inst(rec, (unsigned long)ftrace_caller, &inst);
arch/powerpc/kernel/trace/ftrace.c
277
inst = ftrace_create_branch_inst(ftrace_get_ool_stub(rec) + MCOUNT_INSN_SIZE,
arch/powerpc/kernel/trace/ftrace.c
280
ool_stub_template.insn[1] = ppc_inst_val(inst);
arch/powerpc/kernel/trace/ftrace.c
283
if (!ret && create_branch(&inst, &ool_stub->insn[3], rec->ip + MCOUNT_INSN_SIZE, 0))
arch/powerpc/kernel/trace/ftrace.c
285
ool_stub_template.insn[3] = ppc_inst_val(inst);
arch/powerpc/kernel/trace/ftrace.c
88
static inline int ftrace_validate_inst(unsigned long ip, ppc_inst_t inst)
arch/powerpc/kernel/trace/ftrace.c
94
if (!ret && !ppc_inst_equal(op, inst)) {
arch/powerpc/kernel/trace/ftrace.c
96
ip, ppc_inst_as_ulong(inst), ppc_inst_as_ulong(op));
arch/powerpc/kvm/book3s.c
490
enum instruction_fetch_type type, unsigned long *inst)
arch/powerpc/kvm/book3s.c
512
*inst = ((u64)iw << 32) | suffix;
arch/powerpc/kvm/book3s.c
514
*inst = iw;
arch/powerpc/kvm/book3s.h
19
unsigned int inst, int *advance);
arch/powerpc/kvm/book3s_emulate.c
1034
u32 kvmppc_alignment_dsisr(struct kvm_vcpu *vcpu, unsigned int inst)
arch/powerpc/kvm/book3s_emulate.c
1036
return make_dsisr(inst);
arch/powerpc/kvm/book3s_emulate.c
1039
ulong kvmppc_alignment_dar(struct kvm_vcpu *vcpu, unsigned int inst)
arch/powerpc/kvm/book3s_emulate.c
1048
ulong ra = get_ra(inst);
arch/powerpc/kvm/book3s_emulate.c
1049
ulong rb = get_rb(inst);
arch/powerpc/kvm/book3s_emulate.c
1051
switch (get_op(inst)) {
arch/powerpc/kvm/book3s_emulate.c
1058
dar += (s32)((s16)inst);
arch/powerpc/kvm/book3s_emulate.c
1066
printk(KERN_INFO "KVM: Unaligned instruction 0x%x\n", inst);
arch/powerpc/kvm/book3s_emulate.c
235
unsigned int inst, int *advance)
arch/powerpc/kvm/book3s_emulate.c
238
int rt = get_rt(inst);
arch/powerpc/kvm/book3s_emulate.c
239
int rs = get_rs(inst);
arch/powerpc/kvm/book3s_emulate.c
240
int ra = get_ra(inst);
arch/powerpc/kvm/book3s_emulate.c
241
int rb = get_rb(inst);
arch/powerpc/kvm/book3s_emulate.c
244
switch (get_op(inst)) {
arch/powerpc/kvm/book3s_emulate.c
248
(inst == swab32(inst_sc))) {
arch/powerpc/kvm/book3s_emulate.c
262
switch (get_xop(inst)) {
arch/powerpc/kvm/book3s_emulate.c
293
switch (get_xop(inst)) {
arch/powerpc/kvm/book3s_emulate.c
300
if (inst & 0x10000) {
arch/powerpc/kvm/book3s_emulate.c
316
srnum = kvmppc_get_field(inst, 12 + 32, 15 + 32);
arch/powerpc/kvm/book3s_emulate.c
338
(inst >> 16) & 0xf,
arch/powerpc/kvm/book3s_emulate.c
349
bool large = (inst & 0x00200000) ? true : false;
arch/powerpc/kvm/book3s_emulate.c
406
if (!(inst & 1) || !vcpu->arch.mmu.slbfee) {
arch/powerpc/kvm/book3s_emulate.c
506
if ((inst >> 21) & 0x1)
arch/powerpc/kvm/book3s_hv.c
1536
u32 inst, rb, thr;
arch/powerpc/kvm/book3s_hv.c
1544
inst = ppc_inst_val(pinst);
arch/powerpc/kvm/book3s_hv.c
1545
if (get_op(inst) != 31)
arch/powerpc/kvm/book3s_hv.c
1547
rb = get_rb(inst);
arch/powerpc/kvm/book3s_hv.c
1549
switch (get_xop(inst)) {
arch/powerpc/kvm/book3s_hv.c
1573
switch (get_sprn(inst)) {
arch/powerpc/kvm/book3s_hv.c
1583
kvmppc_set_gpr(vcpu, get_rt(inst), arg);
arch/powerpc/kvm/book3s_hv.c
5923
unsigned int inst, int *advance)
arch/powerpc/kvm/book3s_paired_singles.c
1000
switch (inst_get_field(inst, 21, 30)) {
arch/powerpc/kvm/book3s_paired_singles.c
1099
switch (inst_get_field(inst, 21, 30)) {
arch/powerpc/kvm/book3s_paired_singles.c
1121
switch (inst_get_field(inst, 26, 30)) {
arch/powerpc/kvm/book3s_paired_singles.c
1145
switch (inst_get_field(inst, 21, 30)) {
arch/powerpc/kvm/book3s_paired_singles.c
1165
u32 cr_shift = inst_get_field(inst, 6, 8) * 4;
arch/powerpc/kvm/book3s_paired_singles.c
1176
u32 cr_shift = inst_get_field(inst, 6, 8) * 4;
arch/powerpc/kvm/book3s_paired_singles.c
1225
switch (inst_get_field(inst, 26, 30)) {
arch/powerpc/kvm/book3s_paired_singles.c
339
static inline u32 inst_get_field(u32 inst, int msb, int lsb)
arch/powerpc/kvm/book3s_paired_singles.c
341
return kvmppc_get_field(inst, msb + 32, lsb + 32);
arch/powerpc/kvm/book3s_paired_singles.c
344
static bool kvmppc_inst_is_paired_single(struct kvm_vcpu *vcpu, u32 inst)
arch/powerpc/kvm/book3s_paired_singles.c
349
switch (get_op(inst)) {
arch/powerpc/kvm/book3s_paired_singles.c
365
switch (inst_get_field(inst, 21, 30)) {
arch/powerpc/kvm/book3s_paired_singles.c
383
switch (inst_get_field(inst, 25, 30)) {
arch/powerpc/kvm/book3s_paired_singles.c
389
switch (inst_get_field(inst, 26, 30)) {
arch/powerpc/kvm/book3s_paired_singles.c
411
switch (inst_get_field(inst, 21, 30)) {
arch/powerpc/kvm/book3s_paired_singles.c
419
switch (inst_get_field(inst, 26, 30)) {
arch/powerpc/kvm/book3s_paired_singles.c
429
switch (inst_get_field(inst, 21, 30)) {
arch/powerpc/kvm/book3s_paired_singles.c
451
switch (inst_get_field(inst, 26, 30)) {
arch/powerpc/kvm/book3s_paired_singles.c
462
switch (inst_get_field(inst, 21, 30)) {
arch/powerpc/kvm/book3s_paired_singles.c
480
static int get_d_signext(u32 inst)
arch/powerpc/kvm/book3s_paired_singles.c
482
int d = inst & 0x8ff;
arch/powerpc/kvm/book3s_paired_singles.c
623
u32 inst;
arch/powerpc/kvm/book3s_paired_singles.c
637
inst = ppc_inst_val(pinst);
arch/powerpc/kvm/book3s_paired_singles.c
641
ax_rd = inst_get_field(inst, 6, 10);
arch/powerpc/kvm/book3s_paired_singles.c
642
ax_ra = inst_get_field(inst, 11, 15);
arch/powerpc/kvm/book3s_paired_singles.c
643
ax_rb = inst_get_field(inst, 16, 20);
arch/powerpc/kvm/book3s_paired_singles.c
644
ax_rc = inst_get_field(inst, 21, 25);
arch/powerpc/kvm/book3s_paired_singles.c
645
full_d = inst_get_field(inst, 16, 31);
arch/powerpc/kvm/book3s_paired_singles.c
652
rcomp = (inst & 1) ? true : false;
arch/powerpc/kvm/book3s_paired_singles.c
655
if (!kvmppc_inst_is_paired_single(vcpu, inst))
arch/powerpc/kvm/book3s_paired_singles.c
677
switch (get_op(inst)) {
arch/powerpc/kvm/book3s_paired_singles.c
681
bool w = inst_get_field(inst, 16, 16) ? true : false;
arch/powerpc/kvm/book3s_paired_singles.c
682
int i = inst_get_field(inst, 17, 19);
arch/powerpc/kvm/book3s_paired_singles.c
684
addr += get_d_signext(inst);
arch/powerpc/kvm/book3s_paired_singles.c
691
bool w = inst_get_field(inst, 16, 16) ? true : false;
arch/powerpc/kvm/book3s_paired_singles.c
692
int i = inst_get_field(inst, 17, 19);
arch/powerpc/kvm/book3s_paired_singles.c
694
addr += get_d_signext(inst);
arch/powerpc/kvm/book3s_paired_singles.c
704
bool w = inst_get_field(inst, 16, 16) ? true : false;
arch/powerpc/kvm/book3s_paired_singles.c
705
int i = inst_get_field(inst, 17, 19);
arch/powerpc/kvm/book3s_paired_singles.c
707
addr += get_d_signext(inst);
arch/powerpc/kvm/book3s_paired_singles.c
714
bool w = inst_get_field(inst, 16, 16) ? true : false;
arch/powerpc/kvm/book3s_paired_singles.c
715
int i = inst_get_field(inst, 17, 19);
arch/powerpc/kvm/book3s_paired_singles.c
717
addr += get_d_signext(inst);
arch/powerpc/kvm/book3s_paired_singles.c
726
switch (inst_get_field(inst, 21, 30)) {
arch/powerpc/kvm/book3s_paired_singles.c
734
bool w = inst_get_field(inst, 21, 21) ? true : false;
arch/powerpc/kvm/book3s_paired_singles.c
735
int i = inst_get_field(inst, 22, 24);
arch/powerpc/kvm/book3s_paired_singles.c
748
bool w = inst_get_field(inst, 21, 21) ? true : false;
arch/powerpc/kvm/book3s_paired_singles.c
749
int i = inst_get_field(inst, 22, 24);
arch/powerpc/kvm/book3s_paired_singles.c
821
switch (inst_get_field(inst, 25, 30)) {
arch/powerpc/kvm/book3s_paired_singles.c
825
bool w = inst_get_field(inst, 21, 21) ? true : false;
arch/powerpc/kvm/book3s_paired_singles.c
826
int i = inst_get_field(inst, 22, 24);
arch/powerpc/kvm/book3s_paired_singles.c
835
bool w = inst_get_field(inst, 21, 21) ? true : false;
arch/powerpc/kvm/book3s_paired_singles.c
836
int i = inst_get_field(inst, 22, 24);
arch/powerpc/kvm/book3s_paired_singles.c
847
switch (inst_get_field(inst, 26, 30)) {
arch/powerpc/kvm/booke.h
74
unsigned int inst, int *advance);
arch/powerpc/kvm/booke.h
98
unsigned int inst, int *advance);
arch/powerpc/kvm/booke_emulate.c
43
unsigned int inst, int *advance)
arch/powerpc/kvm/booke_emulate.c
46
int rs = get_rs(inst);
arch/powerpc/kvm/booke_emulate.c
47
int rt = get_rt(inst);
arch/powerpc/kvm/booke_emulate.c
49
switch (get_op(inst)) {
arch/powerpc/kvm/booke_emulate.c
51
switch (get_xop(inst)) {
arch/powerpc/kvm/booke_emulate.c
77
switch (get_xop(inst)) {
arch/powerpc/kvm/booke_emulate.c
97
| (inst & MSR_EE);
arch/powerpc/kvm/e500_emulate.c
115
static int kvmppc_e500_emul_mftmr(struct kvm_vcpu *vcpu, unsigned int inst,
arch/powerpc/kvm/e500_emulate.c
119
if (get_tmrn(inst) == TMRN_TMCFG0) {
arch/powerpc/kvm/e500_emulate.c
129
unsigned int inst, int *advance)
arch/powerpc/kvm/e500_emulate.c
132
int ra = get_ra(inst);
arch/powerpc/kvm/e500_emulate.c
133
int rb = get_rb(inst);
arch/powerpc/kvm/e500_emulate.c
134
int rt = get_rt(inst);
arch/powerpc/kvm/e500_emulate.c
137
switch (get_op(inst)) {
arch/powerpc/kvm/e500_emulate.c
139
switch (get_xop(inst)) {
arch/powerpc/kvm/e500_emulate.c
181
emulated = kvmppc_e500_emul_mftmr(vcpu, inst, rt);
arch/powerpc/kvm/e500_emulate.c
185
emulated = kvmppc_e500_emul_ehpriv(vcpu, inst, advance);
arch/powerpc/kvm/e500_emulate.c
199
emulated = kvmppc_booke_emulate_op(vcpu, inst, advance);
arch/powerpc/kvm/e500_emulate.c
87
unsigned int inst, int *advance)
arch/powerpc/kvm/e500_emulate.c
91
switch (get_oc(inst)) {
arch/powerpc/kvm/emulate.c
196
u32 inst;
arch/powerpc/kvm/emulate.c
206
inst = ppc_inst_val(pinst);
arch/powerpc/kvm/emulate.c
210
pr_debug("Emulating opcode %d / %d\n", get_op(inst), get_xop(inst));
arch/powerpc/kvm/emulate.c
212
rs = get_rs(inst);
arch/powerpc/kvm/emulate.c
213
rt = get_rt(inst);
arch/powerpc/kvm/emulate.c
214
sprn = get_sprn(inst);
arch/powerpc/kvm/emulate.c
216
switch (get_op(inst)) {
arch/powerpc/kvm/emulate.c
229
switch (get_xop(inst)) {
arch/powerpc/kvm/emulate.c
274
if (inst == KVMPPC_INST_SW_BREAKPOINT) {
arch/powerpc/kvm/emulate.c
290
emulated = vcpu->kvm->arch.kvm_ops->emulate_op(vcpu, inst,
arch/powerpc/kvm/emulate.c
297
"(op %d xop %d)\n", inst, get_op(inst), get_xop(inst));
arch/powerpc/kvm/emulate.c
301
trace_kvm_ppc_instr(inst, kvmppc_get_pc(vcpu), emulated);
arch/powerpc/kvm/emulate_loadstore.c
360
trace_kvm_ppc_instr(ppc_inst_val(inst), kvmppc_get_pc(vcpu), emulated);
arch/powerpc/kvm/emulate_loadstore.c
364
kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) + ppc_inst_len(inst));
arch/powerpc/kvm/emulate_loadstore.c
74
ppc_inst_t inst;
arch/powerpc/kvm/emulate_loadstore.c
81
emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &inst);
arch/powerpc/kvm/emulate_loadstore.c
96
if (analyse_instr(&op, &vcpu->arch.regs, inst) == 0) {
arch/powerpc/kvm/trace.h
14
TP_PROTO(unsigned int inst, unsigned long _pc, unsigned int emulate),
arch/powerpc/kvm/trace.h
15
TP_ARGS(inst, _pc, emulate),
arch/powerpc/kvm/trace.h
18
__field( unsigned int, inst )
arch/powerpc/kvm/trace.h
24
__entry->inst = inst;
arch/powerpc/kvm/trace.h
30
__entry->inst, __entry->pc, __entry->emulate)
arch/powerpc/lib/feature-fixups.c
612
ppc_inst_t inst;
arch/powerpc/lib/feature-fixups.c
623
inst = ppc_inst_read(src);
arch/powerpc/lib/feature-fixups.c
624
raw_patch_instruction(dest, inst);
arch/powerpc/lib/test-code-patching.c
340
ppc_inst_t inst = ppc_inst_prefix(OP_PREFIX << 26, 0);
arch/powerpc/lib/test-code-patching.c
345
patch_instruction(iptr, inst);
arch/powerpc/platforms/powermac/low_i2c.c
1203
struct pmac_i2c_pf_inst *inst;
arch/powerpc/platforms/powermac/low_i2c.c
1223
inst = kzalloc_obj(struct pmac_i2c_pf_inst);
arch/powerpc/platforms/powermac/low_i2c.c
1224
if (inst == NULL) {
arch/powerpc/platforms/powermac/low_i2c.c
1228
inst->bus = bus;
arch/powerpc/platforms/powermac/low_i2c.c
1229
inst->addr = pmac_i2c_get_dev_addr(func->node);
arch/powerpc/platforms/powermac/low_i2c.c
1230
inst->quirks = (int)(long)func->driver_data;
arch/powerpc/platforms/powermac/low_i2c.c
1231
return inst;
arch/powerpc/platforms/powermac/low_i2c.c
1236
struct pmac_i2c_pf_inst *inst = instdata;
arch/powerpc/platforms/powermac/low_i2c.c
1238
if (inst == NULL)
arch/powerpc/platforms/powermac/low_i2c.c
1240
pmac_i2c_close(inst->bus);
arch/powerpc/platforms/powermac/low_i2c.c
1241
kfree(inst);
arch/powerpc/platforms/powermac/low_i2c.c
1246
struct pmac_i2c_pf_inst *inst = instdata;
arch/powerpc/platforms/powermac/low_i2c.c
1248
inst->bytes = len;
arch/powerpc/platforms/powermac/low_i2c.c
1249
return pmac_i2c_xfer(inst->bus, inst->addr | pmac_i2c_read, 0, 0,
arch/powerpc/platforms/powermac/low_i2c.c
1250
inst->buffer, len);
arch/powerpc/platforms/powermac/low_i2c.c
1255
struct pmac_i2c_pf_inst *inst = instdata;
arch/powerpc/platforms/powermac/low_i2c.c
1257
return pmac_i2c_xfer(inst->bus, inst->addr | pmac_i2c_write, 0, 0,
arch/powerpc/platforms/powermac/low_i2c.c
1267
static void pmac_i2c_do_apply_rmw(struct pmac_i2c_pf_inst *inst,
arch/powerpc/platforms/powermac/low_i2c.c
1272
if (inst->quirks & pmac_i2c_quirk_invmask) {
arch/powerpc/platforms/powermac/low_i2c.c
1274
inst->scratch[i] = (inst->buffer[i] & mask[i]) | val[i];
arch/powerpc/platforms/powermac/low_i2c.c
1277
inst->scratch[i] = (inst->buffer[i] & ~mask[i])
arch/powerpc/platforms/powermac/low_i2c.c
1286
struct pmac_i2c_pf_inst *inst = instdata;
arch/powerpc/platforms/powermac/low_i2c.c
1288
if (masklen > inst->bytes || valuelen > inst->bytes ||
arch/powerpc/platforms/powermac/low_i2c.c
1289
totallen > inst->bytes || valuelen > masklen)
arch/powerpc/platforms/powermac/low_i2c.c
1292
pmac_i2c_do_apply_rmw(inst, masklen, maskdata, valuedata);
arch/powerpc/platforms/powermac/low_i2c.c
1294
return pmac_i2c_xfer(inst->bus, inst->addr | pmac_i2c_write, 0, 0,
arch/powerpc/platforms/powermac/low_i2c.c
1295
inst->scratch, totallen);
arch/powerpc/platforms/powermac/low_i2c.c
1300
struct pmac_i2c_pf_inst *inst = instdata;
arch/powerpc/platforms/powermac/low_i2c.c
1302
inst->bytes = len;
arch/powerpc/platforms/powermac/low_i2c.c
1303
return pmac_i2c_xfer(inst->bus, inst->addr | pmac_i2c_read, 1, subaddr,
arch/powerpc/platforms/powermac/low_i2c.c
1304
inst->buffer, len);
arch/powerpc/platforms/powermac/low_i2c.c
1310
struct pmac_i2c_pf_inst *inst = instdata;
arch/powerpc/platforms/powermac/low_i2c.c
1312
return pmac_i2c_xfer(inst->bus, inst->addr | pmac_i2c_write, 1,
arch/powerpc/platforms/powermac/low_i2c.c
1318
struct pmac_i2c_pf_inst *inst = instdata;
arch/powerpc/platforms/powermac/low_i2c.c
1320
return pmac_i2c_setmode(inst->bus, mode);
arch/powerpc/platforms/powermac/low_i2c.c
1327
struct pmac_i2c_pf_inst *inst = instdata;
arch/powerpc/platforms/powermac/low_i2c.c
1329
if (masklen > inst->bytes || valuelen > inst->bytes ||
arch/powerpc/platforms/powermac/low_i2c.c
1330
totallen > inst->bytes || valuelen > masklen)
arch/powerpc/platforms/powermac/low_i2c.c
1333
pmac_i2c_do_apply_rmw(inst, masklen, maskdata, valuedata);
arch/powerpc/platforms/powermac/low_i2c.c
1335
return pmac_i2c_xfer(inst->bus, inst->addr | pmac_i2c_write, 1,
arch/powerpc/platforms/powermac/low_i2c.c
1336
subaddr, inst->scratch, totallen);
arch/powerpc/platforms/powermac/low_i2c.c
1343
struct pmac_i2c_pf_inst *inst = instdata;
arch/powerpc/platforms/powermac/low_i2c.c
1351
if (len > inst->bytes)
arch/powerpc/platforms/powermac/low_i2c.c
1355
if ((inst->buffer[i] & maskdata[i]) != valuedata[i])
arch/powerpc/sysdev/fsl_pci.c
1067
u32 inst;
arch/powerpc/sysdev/fsl_pci.c
1083
ret = copy_from_user_nofault(&inst,
arch/powerpc/sysdev/fsl_pci.c
1084
(void __user *)regs->nip, sizeof(inst));
arch/powerpc/sysdev/fsl_pci.c
1086
ret = get_kernel_nofault(inst, (void *)regs->nip);
arch/powerpc/sysdev/fsl_pci.c
1088
if (!ret && mcheck_handle_load(regs, inst)) {
arch/powerpc/sysdev/fsl_pci.c
947
static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
arch/powerpc/sysdev/fsl_pci.c
951
rd = get_rt(inst);
arch/powerpc/sysdev/fsl_pci.c
952
ra = get_ra(inst);
arch/powerpc/sysdev/fsl_pci.c
953
rb = get_rb(inst);
arch/powerpc/sysdev/fsl_pci.c
954
d = get_d(inst);
arch/powerpc/sysdev/fsl_pci.c
956
switch (get_op(inst)) {
arch/powerpc/sysdev/fsl_pci.c
958
switch (get_xop(inst)) {
arch/powerpc/xmon/xmon.c
3001
typedef int (*instruction_dump_func)(unsigned long inst, unsigned long addr);
arch/powerpc/xmon/xmon.c
3009
ppc_inst_t inst, last_inst = ppc_inst(0);
arch/powerpc/xmon/xmon.c
3012
for (first_adr = adr; count > 0; --count, adr += ppc_inst_len(inst)) {
arch/powerpc/xmon/xmon.c
3013
nr = mread_instr(adr, &inst);
arch/powerpc/xmon/xmon.c
3021
if (adr > first_adr && ppc_inst_equal(inst, last_inst)) {
arch/powerpc/xmon/xmon.c
3029
last_inst = inst;
arch/powerpc/xmon/xmon.c
3031
printf(REG" %08lx", adr, ppc_inst_as_ulong(inst));
arch/powerpc/xmon/xmon.c
3033
if (!ppc_inst_prefixed(inst))
arch/powerpc/xmon/xmon.c
3034
dump_func(ppc_inst_val(inst), adr);
arch/powerpc/xmon/xmon.c
3036
dump_func(ppc_inst_as_ulong(inst), adr);
arch/sh/kernel/traps_32.c
574
unsigned short inst = 0;
arch/sh/kernel/traps_32.c
583
get_user(inst, ((unsigned short *) regs->pc));
arch/sh/kernel/traps_32.c
585
inst &= 0xf000;
arch/sh/kernel/traps_32.c
588
if ((inst == 0xf000) || (inst == 0x4000))
arch/sh/kernel/traps_32.c
623
unsigned short inst = 0;
arch/sh/kernel/traps_32.c
626
get_user(inst, (unsigned short __user *)regs->pc);
arch/sh/kernel/traps_32.c
628
err = do_fpu_inst(inst, regs);
arch/sh/kernel/traps_32.c
630
regs->pc += instruction_size(inst);
arch/sh/kernel/traps_32.c
655
static int emulate_branch(unsigned short inst, struct pt_regs *regs)
arch/sh/kernel/traps_32.c
668
if (((inst & 0xf000) == 0xb000) || /* bsr */
arch/sh/kernel/traps_32.c
669
((inst & 0xf0ff) == 0x0003) || /* bsrf */
arch/sh/kernel/traps_32.c
670
((inst & 0xf0ff) == 0x400b)) /* jsr */
arch/sh/kernel/traps_32.c
673
if ((inst & 0xfd00) == 0x8d00) { /* bfs, bts */
arch/sh/kernel/traps_32.c
674
regs->pc += SH_PC_8BIT_OFFSET(inst);
arch/sh/kernel/traps_32.c
678
if ((inst & 0xe000) == 0xa000) { /* bra, bsr */
arch/sh/kernel/traps_32.c
679
regs->pc += SH_PC_12BIT_OFFSET(inst);
arch/sh/kernel/traps_32.c
683
if ((inst & 0xf0df) == 0x0003) { /* braf, bsrf */
arch/sh/kernel/traps_32.c
684
regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
arch/sh/kernel/traps_32.c
688
if ((inst & 0xf0df) == 0x400b) { /* jmp, jsr */
arch/sh/kernel/traps_32.c
689
regs->pc = regs->regs[(inst & 0x0f00) >> 8];
arch/sh/kernel/traps_32.c
693
if ((inst & 0xffff) == 0x000b) { /* rts */
arch/sh/kernel/traps_32.c
705
unsigned long inst;
arch/sh/kernel/traps_32.c
711
get_user(inst, (unsigned short __user *)regs->pc + 1);
arch/sh/kernel/traps_32.c
712
if (!do_fpu_inst(inst, regs)) {
arch/sh/kernel/traps_32.c
713
get_user(inst, (unsigned short __user *)regs->pc);
arch/sh/kernel/traps_32.c
714
if (!emulate_branch(inst, regs))
arch/sh/kernel/traps_32.c
721
inst = lookup_exception_vector();
arch/sh/kernel/traps_32.c
725
die_if_no_fixup("illegal slot instruction", regs, inst);
arch/sh/math-emu/math.c
494
int do_fpu_inst(unsigned short inst, struct pt_regs *regs)
arch/sh/math-emu/math.c
507
return fpu_emulate(inst, fpu, regs);
arch/sparc/prom/tree_32.c
298
phandle prom_inst2pkg(int inst)
arch/sparc/prom/tree_32.c
304
node = (*romvec->pv_v2devops.v2_inst2pkg)(inst);
arch/sparc/prom/tree_64.c
359
inline phandle prom_inst2pkg(int inst)
arch/sparc/prom/tree_64.c
367
args[3] = (unsigned int) inst;
arch/x86/include/asm/asm.h
32
#define __ASM_SIZE(inst, ...) __ASM_SEL(inst##l##__VA_ARGS__, \
arch/x86/include/asm/asm.h
33
inst##q##__VA_ARGS__)
arch/x86/include/asm/efi.h
202
#define efi_table_attr(inst, attr) \
arch/x86/include/asm/efi.h
203
(efi_is_native() ? (inst)->attr \
arch/x86/include/asm/efi.h
204
: efi_mixed_table_attr((inst), attr))
arch/x86/include/asm/efi.h
206
#define efi_mixed_table_attr(inst, attr) \
arch/x86/include/asm/efi.h
207
(__typeof__(inst->attr)) \
arch/x86/include/asm/efi.h
208
_Generic(inst->mixed_mode.attr, \
arch/x86/include/asm/efi.h
209
u32: (unsigned long)(inst->mixed_mode.attr), \
arch/x86/include/asm/efi.h
210
default: (inst->mixed_mode.attr))
arch/x86/include/asm/efi.h
333
#define __efi64_thunk_map(inst, func, ...) \
arch/x86/include/asm/efi.h
334
efi64_thunk(inst->mixed_mode.func, \
arch/x86/include/asm/efi.h
354
#define efi_fn_call(inst, func, ...) \
arch/x86/include/asm/efi.h
355
(efi_is_native() ? (inst)->func(__VA_ARGS__) \
arch/x86/include/asm/efi.h
356
: efi_mixed_call((inst), func, ##__VA_ARGS__))
arch/x86/include/asm/efi.h
358
#define efi_mixed_call(inst, func, ...) \
arch/x86/include/asm/efi.h
359
_Generic(inst->func(__VA_ARGS__), \
arch/x86/include/asm/efi.h
362
__efi64_thunk_map(inst, func, ##__VA_ARGS__)), \
arch/x86/include/asm/efi.h
365
(__typeof__(inst->func(__VA_ARGS__))) \
arch/x86/include/asm/efi.h
366
__efi64_thunk_map(inst, func, ##__VA_ARGS__))
crypto/adiantum.c
499
struct skcipher_instance *inst = skcipher_alg_instance(tfm);
crypto/adiantum.c
500
struct adiantum_instance_ctx *ictx = skcipher_instance_ctx(inst);
crypto/adiantum.c
541
static void adiantum_free_instance(struct skcipher_instance *inst)
crypto/adiantum.c
543
struct adiantum_instance_ctx *ictx = skcipher_instance_ctx(inst);
crypto/adiantum.c
547
kfree(inst);
crypto/adiantum.c
574
struct skcipher_instance *inst;
crypto/adiantum.c
584
inst = kzalloc(sizeof(*inst) + sizeof(*ictx), GFP_KERNEL);
crypto/adiantum.c
585
if (!inst)
crypto/adiantum.c
587
ictx = skcipher_instance_ctx(inst);
crypto/adiantum.c
591
skcipher_crypto_instance(inst),
crypto/adiantum.c
600
skcipher_crypto_instance(inst),
crypto/adiantum.c
628
if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME,
crypto/adiantum.c
632
if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME,
crypto/adiantum.c
637
inst->alg.base.cra_blocksize = BLOCKCIPHER_BLOCK_SIZE;
crypto/adiantum.c
638
inst->alg.base.cra_ctxsize = sizeof(struct adiantum_tfm_ctx);
crypto/adiantum.c
639
inst->alg.base.cra_alignmask = streamcipher_alg->base.cra_alignmask;
crypto/adiantum.c
646
inst->alg.base.cra_priority = (4 * streamcipher_alg->base.cra_priority +
crypto/adiantum.c
650
inst->alg.setkey = adiantum_setkey;
crypto/adiantum.c
651
inst->alg.encrypt = adiantum_encrypt;
crypto/adiantum.c
652
inst->alg.decrypt = adiantum_decrypt;
crypto/adiantum.c
653
inst->alg.init = adiantum_init_tfm;
crypto/adiantum.c
654
inst->alg.exit = adiantum_exit_tfm;
crypto/adiantum.c
655
inst->alg.min_keysize = streamcipher_alg->min_keysize;
crypto/adiantum.c
656
inst->alg.max_keysize = streamcipher_alg->max_keysize;
crypto/adiantum.c
657
inst->alg.ivsize = TWEAK_SIZE;
crypto/adiantum.c
659
inst->free = adiantum_free_instance;
crypto/adiantum.c
661
err = skcipher_register_instance(tmpl, inst);
crypto/adiantum.c
664
adiantum_free_instance(inst);
crypto/aead.c
166
static void crypto_aead_free_instance(struct crypto_instance *inst)
crypto/aead.c
168
struct aead_instance *aead = aead_instance(inst);
crypto/aead.c
191
struct crypto_instance *inst,
crypto/aead.c
195
return crypto_grab_spawn(&spawn->base, inst, name, type, mask);
crypto/aead.c
297
struct aead_instance *inst)
crypto/aead.c
301
if (WARN_ON(!inst->free))
crypto/aead.c
304
err = aead_prepare_alg(&inst->alg);
crypto/aead.c
308
return crypto_register_instance(tmpl, aead_crypto_instance(inst));
crypto/ahash.c
1015
void ahash_free_singlespawn_instance(struct ahash_instance *inst)
crypto/ahash.c
1017
crypto_drop_spawn(ahash_instance_ctx(inst));
crypto/ahash.c
1018
kfree(inst);
crypto/ahash.c
782
static void crypto_ahash_free_instance(struct crypto_instance *inst)
crypto/ahash.c
784
struct ahash_instance *ahash = ahash_instance(inst);
crypto/ahash.c
831
struct crypto_instance *inst,
crypto/ahash.c
835
return crypto_grab_spawn(&spawn->base, inst, name, type, mask);
crypto/ahash.c
970
struct ahash_instance *inst)
crypto/ahash.c
974
if (WARN_ON(!inst->free))
crypto/ahash.c
977
err = ahash_prepare_alg(&inst->alg);
crypto/ahash.c
981
return crypto_register_instance(tmpl, ahash_crypto_instance(inst));
crypto/akcipher.c
100
struct crypto_instance *inst,
crypto/akcipher.c
104
return crypto_grab_spawn(&spawn->base, inst, name, type, mask);
crypto/akcipher.c
158
struct akcipher_instance *inst)
crypto/akcipher.c
160
if (WARN_ON(!inst->free))
crypto/akcipher.c
162
akcipher_prepare_alg(&inst->alg);
crypto/akcipher.c
163
return crypto_register_instance(tmpl, akcipher_crypto_instance(inst));
crypto/akcipher.c
75
static void crypto_akcipher_free_instance(struct crypto_instance *inst)
crypto/akcipher.c
77
struct akcipher_instance *akcipher = akcipher_instance(inst);
crypto/algapi.c
134
return &n->inst->alg.cra_users;
crypto/algapi.c
137
static void crypto_remove_instance(struct crypto_instance *inst,
crypto/algapi.c
140
struct crypto_template *tmpl = inst->tmpl;
crypto/algapi.c
142
if (crypto_is_dead(&inst->alg))
crypto/algapi.c
145
inst->alg.cra_flags |= CRYPTO_ALG_DEAD;
crypto/algapi.c
150
list_del_init(&inst->alg.cra_list);
crypto/algapi.c
151
hlist_del(&inst->list);
crypto/algapi.c
152
hlist_add_head(&inst->list, &tmpl->dead);
crypto/algapi.c
154
BUG_ON(!list_empty(&inst->alg.cra_users));
crypto/algapi.c
156
crypto_alg_put(&inst->alg);
crypto/algapi.c
191
struct crypto_instance *inst;
crypto/algapi.c
195
inst = spawn->inst;
crypto/algapi.c
198
spawn->dead = !spawn->registered || &inst->alg != nalg;
crypto/algapi.c
203
BUG_ON(&inst->alg == alg);
crypto/algapi.c
205
if (&inst->alg == nalg)
crypto/algapi.c
208
spawns = &inst->alg.cra_users;
crypto/algapi.c
240
crypto_remove_instance(spawn->inst, list);
crypto/algapi.c
579
struct crypto_instance *inst;
crypto/algapi.c
590
hlist_for_each_entry(inst, list, list) {
crypto/algapi.c
591
int err = crypto_remove_alg(&inst->alg, &users);
crypto/algapi.c
598
hlist_for_each_entry_safe(inst, n, list, list) {
crypto/algapi.c
599
BUG_ON(refcount_read(&inst->alg.cra_refcnt) != 1);
crypto/algapi.c
600
crypto_free_instance(inst);
crypto/algapi.c
644
struct crypto_instance *inst)
crypto/algapi.c
652
err = crypto_check_alg(&inst->alg);
crypto/algapi.c
656
inst->alg.cra_module = tmpl->module;
crypto/algapi.c
657
inst->alg.cra_flags |= CRYPTO_ALG_INSTANCE;
crypto/algapi.c
658
inst->alg.cra_destroy = crypto_destroy_instance;
crypto/algapi.c
663
for (spawn = inst->spawns; spawn;) {
crypto/algapi.c
67
static void crypto_free_instance(struct crypto_instance *inst)
crypto/algapi.c
670
spawn->inst = inst;
crypto/algapi.c
680
inst->alg.cra_flags |= (fips_internal & CRYPTO_ALG_FIPS_INTERNAL);
crypto/algapi.c
682
larval = __crypto_register_alg(&inst->alg, &algs_to_put);
crypto/algapi.c
688
hlist_add_head(&inst->list, &tmpl->instances);
crypto/algapi.c
689
inst->tmpl = tmpl;
crypto/algapi.c
69
inst->alg.cra_type->free(inst);
crypto/algapi.c
706
void crypto_unregister_instance(struct crypto_instance *inst)
crypto/algapi.c
712
crypto_remove_spawns(&inst->alg, &list, NULL);
crypto/algapi.c
713
crypto_remove_instance(inst, &list);
crypto/algapi.c
721
int crypto_grab_spawn(struct crypto_spawn *spawn, struct crypto_instance *inst,
crypto/algapi.c
727
if (WARN_ON_ONCE(inst == NULL))
crypto/algapi.c
744
spawn->next = inst->spawns;
crypto/algapi.c
745
inst->spawns = spawn;
crypto/algapi.c
746
inst->alg.cra_flags |=
crypto/algapi.c
76
struct crypto_instance *inst;
crypto/algapi.c
81
hlist_for_each_entry_safe(inst, n, &tmpl->dead, list) {
crypto/algapi.c
82
if (refcount_read(&inst->alg.cra_refcnt) != -1)
crypto/algapi.c
84
hlist_del(&inst->list);
crypto/algapi.c
85
hlist_add_head(&inst->list, &list);
crypto/algapi.c
89
hlist_for_each_entry_safe(inst, n, &list, list)
crypto/algapi.c
90
crypto_free_instance(inst);
crypto/algapi.c
924
int __crypto_inst_setname(struct crypto_instance *inst, const char *name,
crypto/algapi.c
927
if (snprintf(inst->alg.cra_name, CRYPTO_MAX_ALG_NAME, "%s(%s)", name,
crypto/algapi.c
931
if (snprintf(inst->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s(%s)",
crypto/algapi.c
95
struct crypto_instance *inst = container_of(alg,
crypto/algapi.c
98
struct crypto_template *tmpl = inst->tmpl;
crypto/authenc.c
113
struct aead_instance *inst = aead_alg_instance(authenc);
crypto/authenc.c
114
struct authenc_instance_ctx *ictx = aead_instance_ctx(inst);
crypto/authenc.c
148
struct aead_instance *inst = aead_alg_instance(authenc);
crypto/authenc.c
150
struct authenc_instance_ctx *ictx = aead_instance_ctx(inst);
crypto/authenc.c
190
struct aead_instance *inst = aead_alg_instance(authenc);
crypto/authenc.c
192
struct authenc_instance_ctx *ictx = aead_instance_ctx(inst);
crypto/authenc.c
232
struct aead_instance *inst = aead_alg_instance(authenc);
crypto/authenc.c
234
struct authenc_instance_ctx *ictx = aead_instance_ctx(inst);
crypto/authenc.c
282
struct aead_instance *inst = aead_alg_instance(authenc);
crypto/authenc.c
284
struct authenc_instance_ctx *ictx = aead_instance_ctx(inst);
crypto/authenc.c
306
struct aead_instance *inst = aead_alg_instance(tfm);
crypto/authenc.c
307
struct authenc_instance_ctx *ictx = aead_instance_ctx(inst);
crypto/authenc.c
350
static void crypto_authenc_free(struct aead_instance *inst)
crypto/authenc.c
352
struct authenc_instance_ctx *ctx = aead_instance_ctx(inst);
crypto/authenc.c
356
kfree(inst);
crypto/authenc.c
363
struct aead_instance *inst;
crypto/authenc.c
374
inst = kzalloc(sizeof(*inst) + sizeof(*ctx), GFP_KERNEL);
crypto/authenc.c
375
if (!inst)
crypto/authenc.c
377
ctx = aead_instance_ctx(inst);
crypto/authenc.c
379
err = crypto_grab_ahash(&ctx->auth, aead_crypto_instance(inst),
crypto/authenc.c
386
err = crypto_grab_skcipher(&ctx->enc, aead_crypto_instance(inst),
crypto/authenc.c
395
if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME,
crypto/authenc.c
401
if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME,
crypto/authenc.c
406
inst->alg.base.cra_priority = enc->base.cra_priority * 10 +
crypto/authenc.c
408
inst->alg.base.cra_blocksize = enc->base.cra_blocksize;
crypto/authenc.c
409
inst->alg.base.cra_alignmask = enc->base.cra_alignmask;
crypto/authenc.c
410
inst->alg.base.cra_ctxsize = sizeof(struct crypto_authenc_ctx);
crypto/authenc.c
412
inst->alg.ivsize = enc->ivsize;
crypto/authenc.c
413
inst->alg.chunksize = enc->chunksize;
crypto/authenc.c
414
inst->alg.maxauthsize = auth->digestsize;
crypto/authenc.c
416
inst->alg.init = crypto_authenc_init_tfm;
crypto/authenc.c
417
inst->alg.exit = crypto_authenc_exit_tfm;
crypto/authenc.c
419
inst->alg.setkey = crypto_authenc_setkey;
crypto/authenc.c
420
inst->alg.encrypt = crypto_authenc_encrypt;
crypto/authenc.c
421
inst->alg.decrypt = crypto_authenc_decrypt;
crypto/authenc.c
423
inst->free = crypto_authenc_free;
crypto/authenc.c
425
err = aead_register_instance(tmpl, inst);
crypto/authenc.c
428
crypto_authenc_free(inst);
crypto/authencesn.c
310
struct aead_instance *inst = aead_alg_instance(tfm);
crypto/authencesn.c
311
struct authenc_esn_instance_ctx *ictx = aead_instance_ctx(inst);
crypto/authencesn.c
356
static void crypto_authenc_esn_free(struct aead_instance *inst)
crypto/authencesn.c
358
struct authenc_esn_instance_ctx *ctx = aead_instance_ctx(inst);
crypto/authencesn.c
362
kfree(inst);
crypto/authencesn.c
369
struct aead_instance *inst;
crypto/authencesn.c
380
inst = kzalloc(sizeof(*inst) + sizeof(*ctx), GFP_KERNEL);
crypto/authencesn.c
381
if (!inst)
crypto/authencesn.c
383
ctx = aead_instance_ctx(inst);
crypto/authencesn.c
385
err = crypto_grab_ahash(&ctx->auth, aead_crypto_instance(inst),
crypto/authencesn.c
397
err = crypto_grab_skcipher(&ctx->enc, aead_crypto_instance(inst),
crypto/authencesn.c
404
if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME,
crypto/authencesn.c
409
if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME,
crypto/authencesn.c
414
inst->alg.base.cra_priority = enc->base.cra_priority * 10 +
crypto/authencesn.c
416
inst->alg.base.cra_blocksize = enc->base.cra_blocksize;
crypto/authencesn.c
417
inst->alg.base.cra_alignmask = enc->base.cra_alignmask;
crypto/authencesn.c
418
inst->alg.base.cra_ctxsize = sizeof(struct crypto_authenc_esn_ctx);
crypto/authencesn.c
420
inst->alg.ivsize = enc->ivsize;
crypto/authencesn.c
421
inst->alg.chunksize = enc->chunksize;
crypto/authencesn.c
422
inst->alg.maxauthsize = auth->digestsize;
crypto/authencesn.c
424
inst->alg.init = crypto_authenc_esn_init_tfm;
crypto/authencesn.c
425
inst->alg.exit = crypto_authenc_esn_exit_tfm;
crypto/authencesn.c
427
inst->alg.setkey = crypto_authenc_esn_setkey;
crypto/authencesn.c
428
inst->alg.setauthsize = crypto_authenc_esn_setauthsize;
crypto/authencesn.c
429
inst->alg.encrypt = crypto_authenc_esn_encrypt;
crypto/authencesn.c
430
inst->alg.decrypt = crypto_authenc_esn_decrypt;
crypto/authencesn.c
432
inst->free = crypto_authenc_esn_free;
crypto/authencesn.c
434
err = aead_register_instance(tmpl, inst);
crypto/authencesn.c
437
crypto_authenc_esn_free(inst);
crypto/cbc.c
140
struct lskcipher_instance *inst;
crypto/cbc.c
143
inst = lskcipher_alloc_instance_simple(tmpl, tb);
crypto/cbc.c
144
if (IS_ERR(inst))
crypto/cbc.c
145
return PTR_ERR(inst);
crypto/cbc.c
148
if (!is_power_of_2(inst->alg.co.base.cra_blocksize))
crypto/cbc.c
151
if (inst->alg.co.statesize)
crypto/cbc.c
154
inst->alg.encrypt = crypto_cbc_encrypt;
crypto/cbc.c
155
inst->alg.decrypt = crypto_cbc_decrypt;
crypto/cbc.c
157
err = lskcipher_register_instance(tmpl, inst);
crypto/cbc.c
160
inst->free(inst);
crypto/ccm.c
391
struct aead_instance *inst = aead_alg_instance(tfm);
crypto/ccm.c
392
struct ccm_instance_ctx *ictx = aead_instance_ctx(inst);
crypto/ccm.c
433
static void crypto_ccm_free(struct aead_instance *inst)
crypto/ccm.c
435
struct ccm_instance_ctx *ctx = aead_instance_ctx(inst);
crypto/ccm.c
439
kfree(inst);
crypto/ccm.c
449
struct aead_instance *inst;
crypto/ccm.c
458
inst = kzalloc(sizeof(*inst) + sizeof(*ictx), GFP_KERNEL);
crypto/ccm.c
459
if (!inst)
crypto/ccm.c
461
ictx = aead_instance_ctx(inst);
crypto/ccm.c
463
err = crypto_grab_ahash(&ictx->mac, aead_crypto_instance(inst),
crypto/ccm.c
474
err = crypto_grab_skcipher(&ictx->ctr, aead_crypto_instance(inst),
crypto/ccm.c
491
if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME,
crypto/ccm.c
495
if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME,
crypto/ccm.c
500
inst->alg.base.cra_priority = (mac->base.cra_priority +
crypto/ccm.c
502
inst->alg.base.cra_blocksize = 1;
crypto/ccm.c
503
inst->alg.base.cra_alignmask = ctr->base.cra_alignmask;
crypto/ccm.c
504
inst->alg.ivsize = 16;
crypto/ccm.c
505
inst->alg.chunksize = ctr->chunksize;
crypto/ccm.c
506
inst->alg.maxauthsize = 16;
crypto/ccm.c
507
inst->alg.base.cra_ctxsize = sizeof(struct crypto_ccm_ctx);
crypto/ccm.c
508
inst->alg.init = crypto_ccm_init_tfm;
crypto/ccm.c
509
inst->alg.exit = crypto_ccm_exit_tfm;
crypto/ccm.c
510
inst->alg.setkey = crypto_ccm_setkey;
crypto/ccm.c
511
inst->alg.setauthsize = crypto_ccm_setauthsize;
crypto/ccm.c
512
inst->alg.encrypt = crypto_ccm_encrypt;
crypto/ccm.c
513
inst->alg.decrypt = crypto_ccm_decrypt;
crypto/ccm.c
515
inst->free = crypto_ccm_free;
crypto/ccm.c
517
err = aead_register_instance(tmpl, inst);
crypto/ccm.c
520
crypto_ccm_free(inst);
crypto/ccm.c
664
struct aead_instance *inst = aead_alg_instance(tfm);
crypto/ccm.c
665
struct crypto_aead_spawn *spawn = aead_instance_ctx(inst);
crypto/ccm.c
694
static void crypto_rfc4309_free(struct aead_instance *inst)
crypto/ccm.c
696
crypto_drop_aead(aead_instance_ctx(inst));
crypto/ccm.c
697
kfree(inst);
crypto/ccm.c
704
struct aead_instance *inst;
crypto/ccm.c
713
inst = kzalloc(sizeof(*inst) + sizeof(*spawn), GFP_KERNEL);
crypto/ccm.c
714
if (!inst)
crypto/ccm.c
717
spawn = aead_instance_ctx(inst);
crypto/ccm.c
718
err = crypto_grab_aead(spawn, aead_crypto_instance(inst),
crypto/ccm.c
736
if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME,
crypto/ccm.c
739
snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME,
crypto/ccm.c
744
inst->alg.base.cra_priority = alg->base.cra_priority;
crypto/ccm.c
745
inst->alg.base.cra_blocksize = 1;
crypto/ccm.c
746
inst->alg.base.cra_alignmask = alg->base.cra_alignmask;
crypto/ccm.c
748
inst->alg.ivsize = 8;
crypto/ccm.c
749
inst->alg.chunksize = crypto_aead_alg_chunksize(alg);
crypto/ccm.c
750
inst->alg.maxauthsize = 16;
crypto/ccm.c
752
inst->alg.base.cra_ctxsize = sizeof(struct crypto_rfc4309_ctx);
crypto/ccm.c
754
inst->alg.init = crypto_rfc4309_init_tfm;
crypto/ccm.c
755
inst->alg.exit = crypto_rfc4309_exit_tfm;
crypto/ccm.c
757
inst->alg.setkey = crypto_rfc4309_setkey;
crypto/ccm.c
758
inst->alg.setauthsize = crypto_rfc4309_setauthsize;
crypto/ccm.c
759
inst->alg.encrypt = crypto_rfc4309_encrypt;
crypto/ccm.c
760
inst->alg.decrypt = crypto_rfc4309_decrypt;
crypto/ccm.c
762
inst->free = crypto_rfc4309_free;
crypto/ccm.c
764
err = aead_register_instance(tmpl, inst);
crypto/ccm.c
767
crypto_rfc4309_free(inst);
crypto/ccm.c
828
struct crypto_instance *inst = (void *)tfm->__crt_alg;
crypto/ccm.c
829
struct crypto_cipher_spawn *spawn = crypto_instance_ctx(inst);
crypto/ccm.c
849
struct shash_instance *inst;
crypto/ccm.c
859
inst = kzalloc(sizeof(*inst) + sizeof(*spawn), GFP_KERNEL);
crypto/ccm.c
860
if (!inst)
crypto/ccm.c
862
spawn = shash_instance_ctx(inst);
crypto/ccm.c
864
err = crypto_grab_cipher(spawn, shash_crypto_instance(inst),
crypto/ccm.c
870
err = crypto_inst_setname(shash_crypto_instance(inst), tmpl->name, alg);
crypto/ccm.c
874
inst->alg.base.cra_priority = alg->cra_priority;
crypto/ccm.c
875
inst->alg.base.cra_blocksize = alg->cra_blocksize;
crypto/ccm.c
877
inst->alg.digestsize = alg->cra_blocksize;
crypto/ccm.c
878
inst->alg.descsize = alg->cra_blocksize;
crypto/ccm.c
880
inst->alg.base.cra_flags = CRYPTO_AHASH_ALG_BLOCK_ONLY;
crypto/ccm.c
881
inst->alg.base.cra_ctxsize = sizeof(struct cbcmac_tfm_ctx);
crypto/ccm.c
882
inst->alg.base.cra_init = cbcmac_init_tfm;
crypto/ccm.c
883
inst->alg.base.cra_exit = cbcmac_exit_tfm;
crypto/ccm.c
885
inst->alg.init = crypto_cbcmac_digest_init;
crypto/ccm.c
886
inst->alg.update = crypto_cbcmac_digest_update;
crypto/ccm.c
887
inst->alg.finup = crypto_cbcmac_digest_finup;
crypto/ccm.c
888
inst->alg.setkey = crypto_cbcmac_digest_setkey;
crypto/ccm.c
890
inst->free = shash_free_singlespawn_instance;
crypto/ccm.c
892
err = shash_register_instance(tmpl, inst);
crypto/ccm.c
895
shash_free_singlespawn_instance(inst);
crypto/chacha20poly1305.c
331
struct aead_instance *inst = aead_alg_instance(tfm);
crypto/chacha20poly1305.c
332
struct chachapoly_instance_ctx *ictx = aead_instance_ctx(inst);
crypto/chacha20poly1305.c
363
static void chachapoly_free(struct aead_instance *inst)
crypto/chacha20poly1305.c
365
struct chachapoly_instance_ctx *ctx = aead_instance_ctx(inst);
crypto/chacha20poly1305.c
368
kfree(inst);
crypto/chacha20poly1305.c
375
struct aead_instance *inst;
crypto/chacha20poly1305.c
388
inst = kzalloc(sizeof(*inst) + sizeof(*ctx), GFP_KERNEL);
crypto/chacha20poly1305.c
389
if (!inst)
crypto/chacha20poly1305.c
391
ctx = aead_instance_ctx(inst);
crypto/chacha20poly1305.c
394
err = crypto_grab_skcipher(&ctx->chacha, aead_crypto_instance(inst),
crypto/chacha20poly1305.c
418
if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME,
crypto/chacha20poly1305.c
422
if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME,
crypto/chacha20poly1305.c
427
inst->alg.base.cra_priority = chacha->base.cra_priority;
crypto/chacha20poly1305.c
428
inst->alg.base.cra_blocksize = 1;
crypto/chacha20poly1305.c
429
inst->alg.base.cra_alignmask = chacha->base.cra_alignmask;
crypto/chacha20poly1305.c
430
inst->alg.base.cra_ctxsize = sizeof(struct chachapoly_ctx) +
crypto/chacha20poly1305.c
432
inst->alg.ivsize = ivsize;
crypto/chacha20poly1305.c
433
inst->alg.chunksize = chacha->chunksize;
crypto/chacha20poly1305.c
434
inst->alg.maxauthsize = POLY1305_DIGEST_SIZE;
crypto/chacha20poly1305.c
435
inst->alg.init = chachapoly_init;
crypto/chacha20poly1305.c
436
inst->alg.exit = chachapoly_exit;
crypto/chacha20poly1305.c
437
inst->alg.encrypt = chachapoly_encrypt;
crypto/chacha20poly1305.c
438
inst->alg.decrypt = chachapoly_decrypt;
crypto/chacha20poly1305.c
439
inst->alg.setkey = chachapoly_setkey;
crypto/chacha20poly1305.c
440
inst->alg.setauthsize = chachapoly_setauthsize;
crypto/chacha20poly1305.c
442
inst->free = chachapoly_free;
crypto/chacha20poly1305.c
444
err = aead_register_instance(tmpl, inst);
crypto/chacha20poly1305.c
447
chachapoly_free(inst);
crypto/cmac.c
139
struct shash_instance *inst = shash_alg_instance(tfm);
crypto/cmac.c
144
spawn = shash_instance_ctx(inst);
crypto/cmac.c
162
struct shash_instance *inst;
crypto/cmac.c
172
inst = kzalloc(sizeof(*inst) + sizeof(*spawn), GFP_KERNEL);
crypto/cmac.c
173
if (!inst)
crypto/cmac.c
175
spawn = shash_instance_ctx(inst);
crypto/cmac.c
177
err = crypto_grab_cipher(spawn, shash_crypto_instance(inst),
crypto/cmac.c
192
err = crypto_inst_setname(shash_crypto_instance(inst), tmpl->name, alg);
crypto/cmac.c
196
inst->alg.base.cra_priority = alg->cra_priority;
crypto/cmac.c
197
inst->alg.base.cra_blocksize = alg->cra_blocksize;
crypto/cmac.c
198
inst->alg.base.cra_ctxsize = sizeof(struct cmac_tfm_ctx) +
crypto/cmac.c
200
inst->alg.base.cra_flags = CRYPTO_AHASH_ALG_BLOCK_ONLY |
crypto/cmac.c
203
inst->alg.digestsize = alg->cra_blocksize;
crypto/cmac.c
204
inst->alg.descsize = alg->cra_blocksize;
crypto/cmac.c
205
inst->alg.init = crypto_cmac_digest_init;
crypto/cmac.c
206
inst->alg.update = crypto_cmac_digest_update;
crypto/cmac.c
207
inst->alg.finup = crypto_cmac_digest_finup;
crypto/cmac.c
208
inst->alg.setkey = crypto_cmac_digest_setkey;
crypto/cmac.c
209
inst->alg.init_tfm = cmac_init_tfm;
crypto/cmac.c
210
inst->alg.exit_tfm = cmac_exit_tfm;
crypto/cmac.c
212
inst->free = shash_free_singlespawn_instance;
crypto/cmac.c
214
err = shash_register_instance(tmpl, inst);
crypto/cmac.c
217
shash_free_singlespawn_instance(inst);
crypto/cryptd.c
195
struct crypto_instance *inst = crypto_tfm_alg_instance(tfm);
crypto/cryptd.c
196
struct cryptd_instance_ctx *ictx = crypto_instance_ctx(inst);
crypto/cryptd.c
216
static int cryptd_init_instance(struct crypto_instance *inst,
crypto/cryptd.c
219
if (snprintf(inst->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME,
crypto/cryptd.c
224
memcpy(inst->alg.cra_name, alg->cra_name, CRYPTO_MAX_ALG_NAME);
crypto/cryptd.c
226
inst->alg.cra_priority = alg->cra_priority + 50;
crypto/cryptd.c
227
inst->alg.cra_blocksize = alg->cra_blocksize;
crypto/cryptd.c
228
inst->alg.cra_alignmask = alg->cra_alignmask;
crypto/cryptd.c
347
struct skcipher_instance *inst = skcipher_alg_instance(tfm);
crypto/cryptd.c
348
struct skcipherd_instance_ctx *ictx = skcipher_instance_ctx(inst);
crypto/cryptd.c
371
static void cryptd_skcipher_free(struct skcipher_instance *inst)
crypto/cryptd.c
373
struct skcipherd_instance_ctx *ctx = skcipher_instance_ctx(inst);
crypto/cryptd.c
376
kfree(inst);
crypto/cryptd.c
385
struct skcipher_instance *inst;
crypto/cryptd.c
393
inst = kzalloc(sizeof(*inst) + sizeof(*ctx), GFP_KERNEL);
crypto/cryptd.c
394
if (!inst)
crypto/cryptd.c
397
ctx = skcipher_instance_ctx(inst);
crypto/cryptd.c
400
err = crypto_grab_skcipher(&ctx->spawn, skcipher_crypto_instance(inst),
crypto/cryptd.c
406
err = cryptd_init_instance(skcipher_crypto_instance(inst), &alg->base);
crypto/cryptd.c
410
inst->alg.base.cra_flags |= CRYPTO_ALG_ASYNC |
crypto/cryptd.c
412
inst->alg.ivsize = alg->ivsize;
crypto/cryptd.c
413
inst->alg.chunksize = alg->chunksize;
crypto/cryptd.c
414
inst->alg.min_keysize = alg->min_keysize;
crypto/cryptd.c
415
inst->alg.max_keysize = alg->max_keysize;
crypto/cryptd.c
417
inst->alg.base.cra_ctxsize = sizeof(struct cryptd_skcipher_ctx);
crypto/cryptd.c
419
inst->alg.init = cryptd_skcipher_init_tfm;
crypto/cryptd.c
420
inst->alg.exit = cryptd_skcipher_exit_tfm;
crypto/cryptd.c
422
inst->alg.setkey = cryptd_skcipher_setkey;
crypto/cryptd.c
423
inst->alg.encrypt = cryptd_skcipher_encrypt_enqueue;
crypto/cryptd.c
424
inst->alg.decrypt = cryptd_skcipher_decrypt_enqueue;
crypto/cryptd.c
426
inst->free = cryptd_skcipher_free;
crypto/cryptd.c
428
err = skcipher_register_instance(tmpl, inst);
crypto/cryptd.c
431
cryptd_skcipher_free(inst);
crypto/cryptd.c
438
struct ahash_instance *inst = ahash_alg_instance(tfm);
crypto/cryptd.c
439
struct hashd_instance_ctx *ictx = ahash_instance_ctx(inst);
crypto/cryptd.c
642
static void cryptd_hash_free(struct ahash_instance *inst)
crypto/cryptd.c
644
struct hashd_instance_ctx *ctx = ahash_instance_ctx(inst);
crypto/cryptd.c
647
kfree(inst);
crypto/cryptd.c
655
struct ahash_instance *inst;
crypto/cryptd.c
663
inst = kzalloc(sizeof(*inst) + sizeof(*ctx), GFP_KERNEL);
crypto/cryptd.c
664
if (!inst)
crypto/cryptd.c
667
ctx = ahash_instance_ctx(inst);
crypto/cryptd.c
670
err = crypto_grab_shash(&ctx->spawn, ahash_crypto_instance(inst),
crypto/cryptd.c
676
err = cryptd_init_instance(ahash_crypto_instance(inst), &alg->base);
crypto/cryptd.c
680
inst->alg.halg.base.cra_flags |= CRYPTO_ALG_ASYNC |
crypto/cryptd.c
683
inst->alg.halg.digestsize = alg->digestsize;
crypto/cryptd.c
684
inst->alg.halg.statesize = alg->statesize;
crypto/cryptd.c
685
inst->alg.halg.base.cra_ctxsize = sizeof(struct cryptd_hash_ctx);
crypto/cryptd.c
687
inst->alg.init_tfm = cryptd_hash_init_tfm;
crypto/cryptd.c
688
inst->alg.exit_tfm = cryptd_hash_exit_tfm;
crypto/cryptd.c
690
inst->alg.init = cryptd_hash_init_enqueue;
crypto/cryptd.c
691
inst->alg.update = cryptd_hash_update_enqueue;
crypto/cryptd.c
692
inst->alg.final = cryptd_hash_final_enqueue;
crypto/cryptd.c
693
inst->alg.finup = cryptd_hash_finup_enqueue;
crypto/cryptd.c
694
inst->alg.export = cryptd_hash_export;
crypto/cryptd.c
695
inst->alg.import = cryptd_hash_import;
crypto/cryptd.c
697
inst->alg.setkey = cryptd_hash_setkey;
crypto/cryptd.c
698
inst->alg.digest = cryptd_hash_digest_enqueue;
crypto/cryptd.c
700
inst->free = cryptd_hash_free;
crypto/cryptd.c
702
err = ahash_register_instance(tmpl, inst);
crypto/cryptd.c
705
cryptd_hash_free(inst);
crypto/cryptd.c
826
struct aead_instance *inst = aead_alg_instance(tfm);
crypto/cryptd.c
827
struct aead_instance_ctx *ictx = aead_instance_ctx(inst);
crypto/cryptd.c
849
static void cryptd_aead_free(struct aead_instance *inst)
crypto/cryptd.c
851
struct aead_instance_ctx *ctx = aead_instance_ctx(inst);
crypto/cryptd.c
854
kfree(inst);
crypto/cryptd.c
863
struct aead_instance *inst;
crypto/cryptd.c
871
inst = kzalloc(sizeof(*inst) + sizeof(*ctx), GFP_KERNEL);
crypto/cryptd.c
872
if (!inst)
crypto/cryptd.c
875
ctx = aead_instance_ctx(inst);
crypto/cryptd.c
878
err = crypto_grab_aead(&ctx->aead_spawn, aead_crypto_instance(inst),
crypto/cryptd.c
884
err = cryptd_init_instance(aead_crypto_instance(inst), &alg->base);
crypto/cryptd.c
888
inst->alg.base.cra_flags |= CRYPTO_ALG_ASYNC |
crypto/cryptd.c
890
inst->alg.base.cra_ctxsize = sizeof(struct cryptd_aead_ctx);
crypto/cryptd.c
892
inst->alg.ivsize = crypto_aead_alg_ivsize(alg);
crypto/cryptd.c
893
inst->alg.maxauthsize = crypto_aead_alg_maxauthsize(alg);
crypto/cryptd.c
895
inst->alg.init = cryptd_aead_init_tfm;
crypto/cryptd.c
896
inst->alg.exit = cryptd_aead_exit_tfm;
crypto/cryptd.c
897
inst->alg.setkey = cryptd_aead_setkey;
crypto/cryptd.c
898
inst->alg.setauthsize = cryptd_aead_setauthsize;
crypto/cryptd.c
899
inst->alg.encrypt = cryptd_aead_encrypt_enqueue;
crypto/cryptd.c
900
inst->alg.decrypt = cryptd_aead_decrypt_enqueue;
crypto/cryptd.c
902
inst->free = cryptd_aead_free;
crypto/cryptd.c
904
err = aead_register_instance(tmpl, inst);
crypto/cryptd.c
907
cryptd_aead_free(inst);
crypto/ctr.c
129
struct skcipher_instance *inst;
crypto/ctr.c
133
inst = skcipher_alloc_instance_simple(tmpl, tb);
crypto/ctr.c
134
if (IS_ERR(inst))
crypto/ctr.c
135
return PTR_ERR(inst);
crypto/ctr.c
137
alg = skcipher_ialg_simple(inst);
crypto/ctr.c
149
inst->alg.base.cra_blocksize = 1;
crypto/ctr.c
155
inst->alg.chunksize = alg->cra_blocksize;
crypto/ctr.c
157
inst->alg.encrypt = crypto_ctr_crypt;
crypto/ctr.c
158
inst->alg.decrypt = crypto_ctr_crypt;
crypto/ctr.c
160
err = skcipher_register_instance(tmpl, inst);
crypto/ctr.c
163
inst->free(inst);
crypto/ctr.c
220
struct skcipher_instance *inst = skcipher_alg_instance(tfm);
crypto/ctr.c
221
struct crypto_skcipher_spawn *spawn = skcipher_instance_ctx(inst);
crypto/ctr.c
249
static void crypto_rfc3686_free(struct skcipher_instance *inst)
crypto/ctr.c
251
struct crypto_skcipher_spawn *spawn = skcipher_instance_ctx(inst);
crypto/ctr.c
254
kfree(inst);
crypto/ctr.c
260
struct skcipher_instance *inst;
crypto/ctr.c
270
inst = kzalloc(sizeof(*inst) + sizeof(*spawn), GFP_KERNEL);
crypto/ctr.c
271
if (!inst)
crypto/ctr.c
274
spawn = skcipher_instance_ctx(inst);
crypto/ctr.c
276
err = crypto_grab_skcipher(spawn, skcipher_crypto_instance(inst),
crypto/ctr.c
293
if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME,
crypto/ctr.c
296
if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME,
crypto/ctr.c
301
inst->alg.base.cra_priority = alg->base.cra_priority;
crypto/ctr.c
302
inst->alg.base.cra_blocksize = 1;
crypto/ctr.c
303
inst->alg.base.cra_alignmask = alg->base.cra_alignmask;
crypto/ctr.c
305
inst->alg.ivsize = CTR_RFC3686_IV_SIZE;
crypto/ctr.c
306
inst->alg.chunksize = alg->chunksize;
crypto/ctr.c
307
inst->alg.min_keysize = alg->min_keysize + CTR_RFC3686_NONCE_SIZE;
crypto/ctr.c
308
inst->alg.max_keysize = alg->max_keysize + CTR_RFC3686_NONCE_SIZE;
crypto/ctr.c
310
inst->alg.setkey = crypto_rfc3686_setkey;
crypto/ctr.c
311
inst->alg.encrypt = crypto_rfc3686_crypt;
crypto/ctr.c
312
inst->alg.decrypt = crypto_rfc3686_crypt;
crypto/ctr.c
314
inst->alg.base.cra_ctxsize = sizeof(struct crypto_rfc3686_ctx);
crypto/ctr.c
316
inst->alg.init = crypto_rfc3686_init_tfm;
crypto/ctr.c
317
inst->alg.exit = crypto_rfc3686_exit_tfm;
crypto/ctr.c
319
inst->free = crypto_rfc3686_free;
crypto/ctr.c
321
err = skcipher_register_instance(tmpl, inst);
crypto/ctr.c
324
crypto_rfc3686_free(inst);
crypto/cts.c
285
struct skcipher_instance *inst = skcipher_alg_instance(tfm);
crypto/cts.c
286
struct crypto_skcipher_spawn *spawn = skcipher_instance_ctx(inst);
crypto/cts.c
318
static void crypto_cts_free(struct skcipher_instance *inst)
crypto/cts.c
320
crypto_drop_skcipher(skcipher_instance_ctx(inst));
crypto/cts.c
321
kfree(inst);
crypto/cts.c
328
struct skcipher_instance *inst;
crypto/cts.c
336
inst = kzalloc(sizeof(*inst) + sizeof(*spawn), GFP_KERNEL);
crypto/cts.c
337
if (!inst)
crypto/cts.c
340
spawn = skcipher_instance_ctx(inst);
crypto/cts.c
342
err = crypto_grab_skcipher(spawn, skcipher_crypto_instance(inst),
crypto/cts.c
356
err = crypto_inst_setname(skcipher_crypto_instance(inst), "cts",
crypto/cts.c
361
inst->alg.base.cra_priority = alg->base.cra_priority;
crypto/cts.c
362
inst->alg.base.cra_blocksize = alg->base.cra_blocksize;
crypto/cts.c
363
inst->alg.base.cra_alignmask = alg->base.cra_alignmask;
crypto/cts.c
365
inst->alg.ivsize = alg->base.cra_blocksize;
crypto/cts.c
366
inst->alg.chunksize = alg->chunksize;
crypto/cts.c
367
inst->alg.min_keysize = alg->min_keysize;
crypto/cts.c
368
inst->alg.max_keysize = alg->max_keysize;
crypto/cts.c
370
inst->alg.base.cra_ctxsize = sizeof(struct crypto_cts_ctx);
crypto/cts.c
372
inst->alg.init = crypto_cts_init_tfm;
crypto/cts.c
373
inst->alg.exit = crypto_cts_exit_tfm;
crypto/cts.c
375
inst->alg.setkey = crypto_cts_setkey;
crypto/cts.c
376
inst->alg.encrypt = crypto_cts_encrypt;
crypto/cts.c
377
inst->alg.decrypt = crypto_cts_decrypt;
crypto/cts.c
379
inst->free = crypto_cts_free;
crypto/cts.c
381
err = skcipher_register_instance(tmpl, inst);
crypto/cts.c
384
crypto_cts_free(inst);
crypto/dh.c
298
static void dh_safe_prime_free_instance(struct kpp_instance *inst)
crypto/dh.c
300
struct dh_safe_prime_instance_ctx *ctx = kpp_instance_ctx(inst);
crypto/dh.c
303
kfree(inst);
crypto/dh.c
549
struct kpp_instance *inst;
crypto/dh.c
564
inst = kzalloc(sizeof(*inst) + sizeof(*ctx), GFP_KERNEL);
crypto/dh.c
565
if (!inst)
crypto/dh.c
568
ctx = kpp_instance_ctx(inst);
crypto/dh.c
570
err = crypto_grab_kpp(&ctx->dh_spawn, kpp_crypto_instance(inst),
crypto/dh.c
582
err = crypto_inst_setname(kpp_crypto_instance(inst),
crypto/dh.c
587
inst->alg.set_secret = dh_safe_prime_set_secret;
crypto/dh.c
588
inst->alg.generate_public_key = dh_safe_prime_generate_public_key;
crypto/dh.c
589
inst->alg.compute_shared_secret = dh_safe_prime_compute_shared_secret;
crypto/dh.c
590
inst->alg.max_size = dh_safe_prime_max_size;
crypto/dh.c
591
inst->alg.init = dh_safe_prime_init_tfm;
crypto/dh.c
592
inst->alg.exit = dh_safe_prime_exit_tfm;
crypto/dh.c
593
inst->alg.base.cra_priority = dh_alg->base.cra_priority;
crypto/dh.c
594
inst->alg.base.cra_module = THIS_MODULE;
crypto/dh.c
595
inst->alg.base.cra_ctxsize = sizeof(struct dh_safe_prime_tfm_ctx);
crypto/dh.c
597
inst->free = dh_safe_prime_free_instance;
crypto/dh.c
599
err = kpp_register_instance(tmpl, inst);
crypto/dh.c
606
dh_safe_prime_free_instance(inst);
crypto/ecb.c
101
struct lskcipher_instance *inst;
crypto/ecb.c
110
inst = kzalloc(sizeof(*inst) + sizeof(*spawn), GFP_KERNEL);
crypto/ecb.c
111
if (!inst)
crypto/ecb.c
113
spawn = lskcipher_instance_ctx(inst);
crypto/ecb.c
115
err = crypto_grab_cipher(spawn, lskcipher_crypto_instance(inst),
crypto/ecb.c
121
err = crypto_inst_setname(lskcipher_crypto_instance(inst), tmpl->name,
crypto/ecb.c
126
inst->free = lskcipher_free_instance_simple2;
crypto/ecb.c
129
inst->alg.co.base.cra_blocksize = cipher_alg->cra_blocksize;
crypto/ecb.c
130
inst->alg.co.base.cra_alignmask = cipher_alg->cra_alignmask;
crypto/ecb.c
131
inst->alg.co.base.cra_priority = cipher_alg->cra_priority;
crypto/ecb.c
132
inst->alg.co.min_keysize = cipher_alg->cra_cipher.cia_min_keysize;
crypto/ecb.c
133
inst->alg.co.max_keysize = cipher_alg->cra_cipher.cia_max_keysize;
crypto/ecb.c
134
inst->alg.co.ivsize = cipher_alg->cra_blocksize;
crypto/ecb.c
137
inst->alg.co.base.cra_ctxsize = sizeof(struct crypto_cipher *);
crypto/ecb.c
138
inst->alg.setkey = lskcipher_setkey_simple2;
crypto/ecb.c
139
inst->alg.init = lskcipher_init_tfm_simple2;
crypto/ecb.c
140
inst->alg.exit = lskcipher_exit_tfm_simple2;
crypto/ecb.c
142
return inst;
crypto/ecb.c
145
lskcipher_free_instance_simple2(inst);
crypto/ecb.c
151
struct lskcipher_instance *inst;
crypto/ecb.c
154
inst = lskcipher_alloc_instance_simple2(tmpl, tb);
crypto/ecb.c
155
if (IS_ERR(inst))
crypto/ecb.c
156
return PTR_ERR(inst);
crypto/ecb.c
159
inst->alg.co.ivsize = 0;
crypto/ecb.c
161
inst->alg.encrypt = crypto_ecb_encrypt2;
crypto/ecb.c
162
inst->alg.decrypt = crypto_ecb_decrypt2;
crypto/ecb.c
164
err = lskcipher_register_instance(tmpl, inst);
crypto/ecb.c
166
inst->free(inst);
crypto/ecb.c
175
struct lskcipher_instance *inst;
crypto/ecb.c
178
inst = lskcipher_alloc_instance_simple(tmpl, tb);
crypto/ecb.c
179
if (IS_ERR(inst)) {
crypto/ecb.c
184
spawn = lskcipher_instance_ctx(inst);
crypto/ecb.c
188
inst->alg.co.ivsize = 0;
crypto/ecb.c
192
inst->alg.co.base.cra_ctxsize = cipher_alg->co.base.cra_ctxsize;
crypto/ecb.c
193
inst->alg.setkey = cipher_alg->setkey;
crypto/ecb.c
194
inst->alg.encrypt = cipher_alg->encrypt;
crypto/ecb.c
195
inst->alg.decrypt = cipher_alg->decrypt;
crypto/ecb.c
196
inst->alg.init = cipher_alg->init;
crypto/ecb.c
197
inst->alg.exit = cipher_alg->exit;
crypto/ecb.c
199
err = lskcipher_register_instance(tmpl, inst);
crypto/ecb.c
201
inst->free(inst);
crypto/ecb.c
70
struct lskcipher_instance *inst = lskcipher_alg_instance(tfm);
crypto/ecb.c
75
spawn = lskcipher_instance_ctx(inst);
crypto/ecb.c
91
static void lskcipher_free_instance_simple2(struct lskcipher_instance *inst)
crypto/ecb.c
93
crypto_drop_cipher(lskcipher_instance_ctx(inst));
crypto/ecb.c
94
kfree(inst);
crypto/ecdsa-p1363.c
102
struct sig_instance *inst;
crypto/ecdsa-p1363.c
111
inst = kzalloc(sizeof(*inst) + sizeof(*spawn), GFP_KERNEL);
crypto/ecdsa-p1363.c
112
if (!inst)
crypto/ecdsa-p1363.c
115
spawn = sig_instance_ctx(inst);
crypto/ecdsa-p1363.c
117
err = crypto_grab_sig(spawn, sig_crypto_instance(inst),
crypto/ecdsa-p1363.c
128
err = crypto_inst_setname(sig_crypto_instance(inst), tmpl->name,
crypto/ecdsa-p1363.c
133
inst->alg.base.cra_priority = ecdsa_alg->base.cra_priority;
crypto/ecdsa-p1363.c
134
inst->alg.base.cra_ctxsize = sizeof(struct ecdsa_p1363_ctx);
crypto/ecdsa-p1363.c
136
inst->alg.init = ecdsa_p1363_init_tfm;
crypto/ecdsa-p1363.c
137
inst->alg.exit = ecdsa_p1363_exit_tfm;
crypto/ecdsa-p1363.c
139
inst->alg.verify = ecdsa_p1363_verify;
crypto/ecdsa-p1363.c
140
inst->alg.key_size = ecdsa_p1363_key_size;
crypto/ecdsa-p1363.c
141
inst->alg.max_size = ecdsa_p1363_max_size;
crypto/ecdsa-p1363.c
142
inst->alg.digest_size = ecdsa_p1363_digest_size;
crypto/ecdsa-p1363.c
143
inst->alg.set_pub_key = ecdsa_p1363_set_pub_key;
crypto/ecdsa-p1363.c
145
inst->free = ecdsa_p1363_free;
crypto/ecdsa-p1363.c
147
err = sig_register_instance(tmpl, inst);
crypto/ecdsa-p1363.c
150
ecdsa_p1363_free(inst);
crypto/ecdsa-p1363.c
70
struct sig_instance *inst = sig_alg_instance(tfm);
crypto/ecdsa-p1363.c
71
struct crypto_sig_spawn *spawn = sig_instance_ctx(inst);
crypto/ecdsa-p1363.c
91
static void ecdsa_p1363_free(struct sig_instance *inst)
crypto/ecdsa-p1363.c
93
struct crypto_sig_spawn *spawn = sig_instance_ctx(inst);
crypto/ecdsa-p1363.c
96
kfree(inst);
crypto/ecdsa-x962.c
147
struct sig_instance *inst = sig_alg_instance(tfm);
crypto/ecdsa-x962.c
148
struct crypto_sig_spawn *spawn = sig_instance_ctx(inst);
crypto/ecdsa-x962.c
168
static void ecdsa_x962_free(struct sig_instance *inst)
crypto/ecdsa-x962.c
170
struct crypto_sig_spawn *spawn = sig_instance_ctx(inst);
crypto/ecdsa-x962.c
173
kfree(inst);
crypto/ecdsa-x962.c
179
struct sig_instance *inst;
crypto/ecdsa-x962.c
188
inst = kzalloc(sizeof(*inst) + sizeof(*spawn), GFP_KERNEL);
crypto/ecdsa-x962.c
189
if (!inst)
crypto/ecdsa-x962.c
192
spawn = sig_instance_ctx(inst);
crypto/ecdsa-x962.c
194
err = crypto_grab_sig(spawn, sig_crypto_instance(inst),
crypto/ecdsa-x962.c
205
err = crypto_inst_setname(sig_crypto_instance(inst), tmpl->name,
crypto/ecdsa-x962.c
210
inst->alg.base.cra_priority = ecdsa_alg->base.cra_priority;
crypto/ecdsa-x962.c
211
inst->alg.base.cra_ctxsize = sizeof(struct ecdsa_x962_ctx);
crypto/ecdsa-x962.c
213
inst->alg.init = ecdsa_x962_init_tfm;
crypto/ecdsa-x962.c
214
inst->alg.exit = ecdsa_x962_exit_tfm;
crypto/ecdsa-x962.c
216
inst->alg.verify = ecdsa_x962_verify;
crypto/ecdsa-x962.c
217
inst->alg.key_size = ecdsa_x962_key_size;
crypto/ecdsa-x962.c
218
inst->alg.max_size = ecdsa_x962_max_size;
crypto/ecdsa-x962.c
219
inst->alg.digest_size = ecdsa_x962_digest_size;
crypto/ecdsa-x962.c
220
inst->alg.set_pub_key = ecdsa_x962_set_pub_key;
crypto/ecdsa-x962.c
222
inst->free = ecdsa_x962_free;
crypto/ecdsa-x962.c
224
err = sig_register_instance(tmpl, inst);
crypto/ecdsa-x962.c
227
ecdsa_x962_free(inst);
crypto/echainiv.c
103
struct aead_instance *inst;
crypto/echainiv.c
106
inst = aead_geniv_alloc(tmpl, tb);
crypto/echainiv.c
108
if (IS_ERR(inst))
crypto/echainiv.c
109
return PTR_ERR(inst);
crypto/echainiv.c
112
if (inst->alg.ivsize & (sizeof(u64) - 1) || !inst->alg.ivsize)
crypto/echainiv.c
115
inst->alg.encrypt = echainiv_encrypt;
crypto/echainiv.c
116
inst->alg.decrypt = echainiv_decrypt;
crypto/echainiv.c
118
inst->alg.init = aead_init_geniv;
crypto/echainiv.c
119
inst->alg.exit = aead_exit_geniv;
crypto/echainiv.c
121
inst->alg.base.cra_ctxsize = sizeof(struct aead_geniv_ctx);
crypto/echainiv.c
122
inst->alg.base.cra_ctxsize += inst->alg.ivsize;
crypto/echainiv.c
124
err = aead_register_instance(tmpl, inst);
crypto/echainiv.c
127
inst->free(inst);
crypto/essiv.c
297
struct skcipher_instance *inst = skcipher_alg_instance(tfm);
crypto/essiv.c
298
struct essiv_instance_ctx *ictx = skcipher_instance_ctx(inst);
crypto/essiv.c
322
struct aead_instance *inst = aead_alg_instance(tfm);
crypto/essiv.c
323
struct essiv_instance_ctx *ictx = aead_instance_ctx(inst);
crypto/essiv.c
371
static void essiv_skcipher_free_instance(struct skcipher_instance *inst)
crypto/essiv.c
373
struct essiv_instance_ctx *ictx = skcipher_instance_ctx(inst);
crypto/essiv.c
376
kfree(inst);
crypto/essiv.c
379
static void essiv_aead_free_instance(struct aead_instance *inst)
crypto/essiv.c
381
struct essiv_instance_ctx *ictx = aead_instance_ctx(inst);
crypto/essiv.c
384
kfree(inst);
crypto/essiv.c
448
struct crypto_instance *inst;
crypto/essiv.c
480
inst = skcipher_crypto_instance(skcipher_inst);
crypto/essiv.c
482
ictx = crypto_instance_ctx(inst);
crypto/essiv.c
485
err = crypto_grab_skcipher(&ictx->u.skcipher_spawn, inst,
crypto/essiv.c
500
inst = aead_crypto_instance(aead_inst);
crypto/essiv.c
502
ictx = crypto_instance_ctx(inst);
crypto/essiv.c
505
err = crypto_grab_aead(&ictx->u.aead_spawn, inst,
crypto/gcm.c
298
struct aead_instance *inst = aead_alg_instance(tfm);
crypto/gcm.c
299
struct gcm_instance_ctx *ictx = aead_instance_ctx(inst);
crypto/gcm.c
325
static void crypto_gcm_free(struct aead_instance *inst)
crypto/gcm.c
327
struct gcm_instance_ctx *ctx = aead_instance_ctx(inst);
crypto/gcm.c
330
kfree(inst);
crypto/gcm.c
338
struct aead_instance *inst;
crypto/gcm.c
346
inst = kzalloc(sizeof(*inst) + sizeof(*ctx), GFP_KERNEL);
crypto/gcm.c
347
if (!inst)
crypto/gcm.c
349
ctx = aead_instance_ctx(inst);
crypto/gcm.c
351
err = crypto_grab_skcipher(&ctx->ctr, aead_crypto_instance(inst),
crypto/gcm.c
364
if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME,
crypto/gcm.c
368
if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME,
crypto/gcm.c
373
inst->alg.base.cra_priority = ctr->base.cra_priority;
crypto/gcm.c
374
inst->alg.base.cra_blocksize = 1;
crypto/gcm.c
375
inst->alg.base.cra_alignmask = ctr->base.cra_alignmask;
crypto/gcm.c
376
inst->alg.base.cra_ctxsize = sizeof(struct crypto_gcm_ctx);
crypto/gcm.c
377
inst->alg.ivsize = GCM_AES_IV_SIZE;
crypto/gcm.c
378
inst->alg.chunksize = ctr->chunksize;
crypto/gcm.c
379
inst->alg.maxauthsize = 16;
crypto/gcm.c
380
inst->alg.init = crypto_gcm_init_tfm;
crypto/gcm.c
381
inst->alg.exit = crypto_gcm_exit_tfm;
crypto/gcm.c
382
inst->alg.setkey = crypto_gcm_setkey;
crypto/gcm.c
383
inst->alg.setauthsize = crypto_gcm_setauthsize;
crypto/gcm.c
384
inst->alg.encrypt = crypto_gcm_encrypt;
crypto/gcm.c
385
inst->alg.decrypt = crypto_gcm_decrypt;
crypto/gcm.c
387
inst->free = crypto_gcm_free;
crypto/gcm.c
389
err = aead_register_instance(tmpl, inst);
crypto/gcm.c
392
crypto_gcm_free(inst);
crypto/gcm.c
539
struct aead_instance *inst = aead_alg_instance(tfm);
crypto/gcm.c
540
struct crypto_aead_spawn *spawn = aead_instance_ctx(inst);
crypto/gcm.c
569
static void crypto_rfc4106_free(struct aead_instance *inst)
crypto/gcm.c
571
crypto_drop_aead(aead_instance_ctx(inst));
crypto/gcm.c
572
kfree(inst);
crypto/gcm.c
579
struct aead_instance *inst;
crypto/gcm.c
588
inst = kzalloc(sizeof(*inst) + sizeof(*spawn), GFP_KERNEL);
crypto/gcm.c
589
if (!inst)
crypto/gcm.c
592
spawn = aead_instance_ctx(inst);
crypto/gcm.c
593
err = crypto_grab_aead(spawn, aead_crypto_instance(inst),
crypto/gcm.c
611
if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME,
crypto/gcm.c
614
snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME,
crypto/gcm.c
619
inst->alg.base.cra_priority = alg->base.cra_priority;
crypto/gcm.c
620
inst->alg.base.cra_blocksize = 1;
crypto/gcm.c
621
inst->alg.base.cra_alignmask = alg->base.cra_alignmask;
crypto/gcm.c
623
inst->alg.base.cra_ctxsize = sizeof(struct crypto_rfc4106_ctx);
crypto/gcm.c
625
inst->alg.ivsize = GCM_RFC4106_IV_SIZE;
crypto/gcm.c
626
inst->alg.chunksize = crypto_aead_alg_chunksize(alg);
crypto/gcm.c
627
inst->alg.maxauthsize = crypto_aead_alg_maxauthsize(alg);
crypto/gcm.c
629
inst->alg.init = crypto_rfc4106_init_tfm;
crypto/gcm.c
630
inst->alg.exit = crypto_rfc4106_exit_tfm;
crypto/gcm.c
632
inst->alg.setkey = crypto_rfc4106_setkey;
crypto/gcm.c
633
inst->alg.setauthsize = crypto_rfc4106_setauthsize;
crypto/gcm.c
634
inst->alg.encrypt = crypto_rfc4106_encrypt;
crypto/gcm.c
635
inst->alg.decrypt = crypto_rfc4106_decrypt;
crypto/gcm.c
637
inst->free = crypto_rfc4106_free;
crypto/gcm.c
639
err = aead_register_instance(tmpl, inst);
crypto/gcm.c
642
crypto_rfc4106_free(inst);
crypto/gcm.c
721
struct aead_instance *inst = aead_alg_instance(tfm);
crypto/gcm.c
722
struct crypto_rfc4543_instance_ctx *ictx = aead_instance_ctx(inst);
crypto/gcm.c
752
static void crypto_rfc4543_free(struct aead_instance *inst)
crypto/gcm.c
754
struct crypto_rfc4543_instance_ctx *ctx = aead_instance_ctx(inst);
crypto/gcm.c
758
kfree(inst);
crypto/gcm.c
765
struct aead_instance *inst;
crypto/gcm.c
774
inst = kzalloc(sizeof(*inst) + sizeof(*ctx), GFP_KERNEL);
crypto/gcm.c
775
if (!inst)
crypto/gcm.c
778
ctx = aead_instance_ctx(inst);
crypto/gcm.c
779
err = crypto_grab_aead(&ctx->aead, aead_crypto_instance(inst),
crypto/gcm.c
797
if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME,
crypto/gcm.c
800
snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME,
crypto/gcm.c
805
inst->alg.base.cra_priority = alg->base.cra_priority;
crypto/gcm.c
806
inst->alg.base.cra_blocksize = 1;
crypto/gcm.c
807
inst->alg.base.cra_alignmask = alg->base.cra_alignmask;
crypto/gcm.c
809
inst->alg.base.cra_ctxsize = sizeof(struct crypto_rfc4543_ctx);
crypto/gcm.c
811
inst->alg.ivsize = GCM_RFC4543_IV_SIZE;
crypto/gcm.c
812
inst->alg.chunksize = crypto_aead_alg_chunksize(alg);
crypto/gcm.c
813
inst->alg.maxauthsize = crypto_aead_alg_maxauthsize(alg);
crypto/gcm.c
815
inst->alg.init = crypto_rfc4543_init_tfm;
crypto/gcm.c
816
inst->alg.exit = crypto_rfc4543_exit_tfm;
crypto/gcm.c
818
inst->alg.setkey = crypto_rfc4543_setkey;
crypto/gcm.c
819
inst->alg.setauthsize = crypto_rfc4543_setauthsize;
crypto/gcm.c
820
inst->alg.encrypt = crypto_rfc4543_encrypt;
crypto/gcm.c
821
inst->alg.decrypt = crypto_rfc4543_decrypt;
crypto/gcm.c
823
inst->free = crypto_rfc4543_free;
crypto/gcm.c
825
err = aead_register_instance(tmpl, inst);
crypto/gcm.c
828
crypto_rfc4543_free(inst);
crypto/geniv.c
102
aead_geniv_free(inst);
crypto/geniv.c
103
inst = ERR_PTR(err);
crypto/geniv.c
111
struct aead_instance *inst = aead_alg_instance(aead);
crypto/geniv.c
119
child = crypto_spawn_aead(aead_instance_ctx(inst));
crypto/geniv.c
34
static void aead_geniv_free(struct aead_instance *inst)
crypto/geniv.c
36
crypto_drop_aead(aead_instance_ctx(inst));
crypto/geniv.c
37
kfree(inst);
crypto/geniv.c
44
struct aead_instance *inst;
crypto/geniv.c
55
inst = kzalloc(sizeof(*inst) + sizeof(*spawn), GFP_KERNEL);
crypto/geniv.c
56
if (!inst)
crypto/geniv.c
59
spawn = aead_instance_ctx(inst);
crypto/geniv.c
61
err = crypto_grab_aead(spawn, aead_crypto_instance(inst),
crypto/geniv.c
76
if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME,
crypto/geniv.c
80
if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME,
crypto/geniv.c
85
inst->alg.base.cra_priority = alg->base.cra_priority;
crypto/geniv.c
86
inst->alg.base.cra_blocksize = alg->base.cra_blocksize;
crypto/geniv.c
87
inst->alg.base.cra_alignmask = alg->base.cra_alignmask;
crypto/geniv.c
88
inst->alg.base.cra_ctxsize = sizeof(struct aead_geniv_ctx);
crypto/geniv.c
90
inst->alg.setkey = aead_geniv_setkey;
crypto/geniv.c
91
inst->alg.setauthsize = aead_geniv_setauthsize;
crypto/geniv.c
93
inst->alg.ivsize = ivsize;
crypto/geniv.c
94
inst->alg.maxauthsize = maxauthsize;
crypto/geniv.c
96
inst->free = aead_geniv_free;
crypto/geniv.c
99
return inst;
crypto/hctr2.c
275
struct skcipher_instance *inst = skcipher_alg_instance(tfm);
crypto/hctr2.c
276
struct hctr2_instance_ctx *ictx = skcipher_instance_ctx(inst);
crypto/hctr2.c
316
static void hctr2_free_instance(struct skcipher_instance *inst)
crypto/hctr2.c
318
struct hctr2_instance_ctx *ictx = skcipher_instance_ctx(inst);
crypto/hctr2.c
322
kfree(inst);
crypto/hctr2.c
330
struct skcipher_instance *inst;
crypto/hctr2.c
341
inst = kzalloc(sizeof(*inst) + sizeof(*ictx), GFP_KERNEL);
crypto/hctr2.c
342
if (!inst)
crypto/hctr2.c
344
ictx = skcipher_instance_ctx(inst);
crypto/hctr2.c
348
skcipher_crypto_instance(inst),
crypto/hctr2.c
367
skcipher_crypto_instance(inst),
crypto/hctr2.c
381
if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME, "hctr2(%s)",
crypto/hctr2.c
384
if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME,
crypto/hctr2.c
389
inst->alg.base.cra_blocksize = BLOCKCIPHER_BLOCK_SIZE;
crypto/hctr2.c
390
inst->alg.base.cra_ctxsize = sizeof(struct hctr2_tfm_ctx);
crypto/hctr2.c
391
inst->alg.base.cra_alignmask = xctr_alg->base.cra_alignmask;
crypto/hctr2.c
392
inst->alg.base.cra_priority = (2 * xctr_alg->base.cra_priority +
crypto/hctr2.c
396
inst->alg.setkey = hctr2_setkey;
crypto/hctr2.c
397
inst->alg.encrypt = hctr2_encrypt;
crypto/hctr2.c
398
inst->alg.decrypt = hctr2_decrypt;
crypto/hctr2.c
399
inst->alg.init = hctr2_init_tfm;
crypto/hctr2.c
400
inst->alg.exit = hctr2_exit_tfm;
crypto/hctr2.c
401
inst->alg.min_keysize = xctr_alg->min_keysize;
crypto/hctr2.c
402
inst->alg.max_keysize = xctr_alg->max_keysize;
crypto/hctr2.c
403
inst->alg.ivsize = TWEAK_SIZE;
crypto/hctr2.c
405
inst->free = hctr2_free_instance;
crypto/hctr2.c
407
err = skcipher_register_instance(tmpl, inst);
crypto/hctr2.c
410
hctr2_free_instance(inst);
crypto/hmac.c
149
struct shash_instance *inst = shash_alg_instance(parent);
crypto/hmac.c
150
struct crypto_shash_spawn *spawn = shash_instance_ctx(inst);
crypto/hmac.c
171
struct shash_instance *inst;
crypto/hmac.c
179
inst = kzalloc(sizeof(*inst) + sizeof(*spawn), GFP_KERNEL);
crypto/hmac.c
180
if (!inst)
crypto/hmac.c
182
spawn = shash_instance_ctx(inst);
crypto/hmac.c
185
err = crypto_grab_shash(spawn, shash_crypto_instance(inst),
crypto/hmac.c
203
err = crypto_inst_setname(shash_crypto_instance(inst), "hmac",
crypto/hmac.c
208
inst->alg.base.cra_priority = alg->cra_priority;
crypto/hmac.c
209
inst->alg.base.cra_blocksize = alg->cra_blocksize;
crypto/hmac.c
210
inst->alg.base.cra_ctxsize = sizeof(struct hmac_ctx) + (ss * 2);
crypto/hmac.c
212
inst->alg.digestsize = ds;
crypto/hmac.c
213
inst->alg.statesize = ss;
crypto/hmac.c
214
inst->alg.descsize = sizeof(struct shash_desc) + salg->descsize;
crypto/hmac.c
215
inst->alg.init = hmac_init;
crypto/hmac.c
216
inst->alg.update = hmac_update;
crypto/hmac.c
217
inst->alg.finup = hmac_finup;
crypto/hmac.c
218
inst->alg.export = hmac_export;
crypto/hmac.c
219
inst->alg.import = hmac_import;
crypto/hmac.c
220
inst->alg.export_core = hmac_export_core;
crypto/hmac.c
221
inst->alg.import_core = hmac_import_core;
crypto/hmac.c
222
inst->alg.setkey = hmac_setkey;
crypto/hmac.c
223
inst->alg.init_tfm = hmac_init_tfm;
crypto/hmac.c
224
inst->alg.exit_tfm = hmac_exit_tfm;
crypto/hmac.c
226
inst->free = shash_free_singlespawn_instance;
crypto/hmac.c
228
err = shash_register_instance(tmpl, inst);
crypto/hmac.c
231
shash_free_singlespawn_instance(inst);
crypto/hmac.c
395
struct ahash_instance *inst = ahash_alg_instance(parent);
crypto/hmac.c
399
hash = crypto_spawn_ahash(ahash_instance_ctx(inst));
crypto/hmac.c
422
struct ahash_instance *inst;
crypto/hmac.c
427
inst = kzalloc(sizeof(*inst) + sizeof(*spawn), GFP_KERNEL);
crypto/hmac.c
428
if (!inst)
crypto/hmac.c
430
spawn = ahash_instance_ctx(inst);
crypto/hmac.c
433
err = crypto_grab_ahash(spawn, ahash_crypto_instance(inst),
crypto/hmac.c
450
err = crypto_inst_setname(ahash_crypto_instance(inst), tmpl->name, alg);
crypto/hmac.c
454
inst->alg.halg.base.cra_flags = alg->cra_flags &
crypto/hmac.c
456
inst->alg.halg.base.cra_flags |= CRYPTO_ALG_REQ_VIRT;
crypto/hmac.c
457
inst->alg.halg.base.cra_priority = alg->cra_priority + 100;
crypto/hmac.c
458
inst->alg.halg.base.cra_blocksize = alg->cra_blocksize;
crypto/hmac.c
459
inst->alg.halg.base.cra_ctxsize = sizeof(struct ahash_hmac_ctx) +
crypto/hmac.c
461
inst->alg.halg.base.cra_reqsize = sizeof(struct ahash_request) +
crypto/hmac.c
464
inst->alg.halg.digestsize = ds;
crypto/hmac.c
465
inst->alg.halg.statesize = ss;
crypto/hmac.c
466
inst->alg.init = hmac_init_ahash;
crypto/hmac.c
467
inst->alg.update = hmac_update_ahash;
crypto/hmac.c
468
inst->alg.finup = hmac_finup_ahash;
crypto/hmac.c
469
inst->alg.digest = hmac_digest_ahash;
crypto/hmac.c
470
inst->alg.export = hmac_export_ahash;
crypto/hmac.c
471
inst->alg.import = hmac_import_ahash;
crypto/hmac.c
472
inst->alg.export_core = hmac_export_core_ahash;
crypto/hmac.c
473
inst->alg.import_core = hmac_import_core_ahash;
crypto/hmac.c
474
inst->alg.setkey = hmac_setkey_ahash;
crypto/hmac.c
475
inst->alg.init_tfm = hmac_init_ahash_tfm;
crypto/hmac.c
476
inst->alg.exit_tfm = hmac_exit_ahash_tfm;
crypto/hmac.c
478
inst->free = ahash_free_singlespawn_instance;
crypto/hmac.c
480
err = ahash_register_instance(tmpl, inst);
crypto/hmac.c
483
ahash_free_singlespawn_instance(inst);
crypto/internal.h
41
void (*free)(struct crypto_instance *inst);
crypto/kpp.c
128
struct kpp_instance *inst)
crypto/kpp.c
130
if (WARN_ON(!inst->free))
crypto/kpp.c
133
kpp_prepare_alg(&inst->alg);
crypto/kpp.c
135
return crypto_register_instance(tmpl, kpp_crypto_instance(inst));
crypto/kpp.c
58
static void crypto_kpp_free_instance(struct crypto_instance *inst)
crypto/kpp.c
60
struct kpp_instance *kpp = kpp_instance(inst);
crypto/kpp.c
89
struct crypto_instance *inst,
crypto/kpp.c
93
return crypto_grab_spawn(&spawn->base, inst, name, type, mask);
crypto/krb5enc.c
135
struct aead_instance *inst = aead_alg_instance(krb5enc);
crypto/krb5enc.c
137
struct krb5enc_instance_ctx *ictx = aead_instance_ctx(inst);
crypto/krb5enc.c
179
struct aead_instance *inst = aead_alg_instance(krb5enc);
crypto/krb5enc.c
180
struct krb5enc_instance_ctx *ictx = aead_instance_ctx(inst);
crypto/krb5enc.c
205
struct aead_instance *inst = aead_alg_instance(krb5enc);
crypto/krb5enc.c
207
struct krb5enc_instance_ctx *ictx = aead_instance_ctx(inst);
crypto/krb5enc.c
245
struct aead_instance *inst = aead_alg_instance(krb5enc);
crypto/krb5enc.c
246
struct krb5enc_instance_ctx *ictx = aead_instance_ctx(inst);
crypto/krb5enc.c
276
struct aead_instance *inst = aead_alg_instance(krb5enc);
crypto/krb5enc.c
278
struct krb5enc_instance_ctx *ictx = aead_instance_ctx(inst);
crypto/krb5enc.c
320
struct aead_instance *inst = aead_alg_instance(krb5enc);
crypto/krb5enc.c
322
struct krb5enc_instance_ctx *ictx = aead_instance_ctx(inst);
crypto/krb5enc.c
357
struct aead_instance *inst = aead_alg_instance(tfm);
crypto/krb5enc.c
358
struct krb5enc_instance_ctx *ictx = aead_instance_ctx(inst);
crypto/krb5enc.c
398
static void krb5enc_free(struct aead_instance *inst)
crypto/krb5enc.c
400
struct krb5enc_instance_ctx *ctx = aead_instance_ctx(inst);
crypto/krb5enc.c
404
kfree(inst);
crypto/krb5enc.c
415
struct aead_instance *inst;
crypto/krb5enc.c
426
inst = kzalloc(sizeof(*inst) + sizeof(*ictx), GFP_KERNEL);
crypto/krb5enc.c
427
if (!inst)
crypto/krb5enc.c
429
ictx = aead_instance_ctx(inst);
crypto/krb5enc.c
431
err = crypto_grab_ahash(&ictx->auth, aead_crypto_instance(inst),
crypto/krb5enc.c
440
err = crypto_grab_skcipher(&ictx->enc, aead_crypto_instance(inst),
crypto/krb5enc.c
451
if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME,
crypto/krb5enc.c
457
if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME,
crypto/krb5enc.c
462
inst->alg.base.cra_priority = enc->base.cra_priority * 10 +
crypto/krb5enc.c
464
inst->alg.base.cra_blocksize = enc->base.cra_blocksize;
crypto/krb5enc.c
465
inst->alg.base.cra_alignmask = enc->base.cra_alignmask;
crypto/krb5enc.c
466
inst->alg.base.cra_ctxsize = sizeof(struct krb5enc_ctx);
crypto/krb5enc.c
468
inst->alg.ivsize = enc->ivsize;
crypto/krb5enc.c
469
inst->alg.chunksize = enc->chunksize;
crypto/krb5enc.c
470
inst->alg.maxauthsize = auth->digestsize;
crypto/krb5enc.c
472
inst->alg.init = krb5enc_init_tfm;
crypto/krb5enc.c
473
inst->alg.exit = krb5enc_exit_tfm;
crypto/krb5enc.c
475
inst->alg.setkey = krb5enc_setkey;
crypto/krb5enc.c
476
inst->alg.encrypt = krb5enc_encrypt;
crypto/krb5enc.c
477
inst->alg.decrypt = krb5enc_decrypt;
crypto/krb5enc.c
479
inst->free = krb5enc_free;
crypto/krb5enc.c
481
err = aead_register_instance(tmpl, inst);
crypto/krb5enc.c
490
krb5enc_free(inst);
crypto/lrw.c
267
struct skcipher_instance *inst = skcipher_alg_instance(tfm);
crypto/lrw.c
268
struct crypto_skcipher_spawn *spawn = skcipher_instance_ctx(inst);
crypto/lrw.c
293
static void lrw_free_instance(struct skcipher_instance *inst)
crypto/lrw.c
295
crypto_drop_skcipher(skcipher_instance_ctx(inst));
crypto/lrw.c
296
kfree(inst);
crypto/lrw.c
303
struct skcipher_instance *inst;
crypto/lrw.c
317
inst = kzalloc(sizeof(*inst) + sizeof(*spawn), GFP_KERNEL);
crypto/lrw.c
318
if (!inst)
crypto/lrw.c
321
spawn = skcipher_instance_ctx(inst);
crypto/lrw.c
323
err = crypto_grab_skcipher(spawn, skcipher_crypto_instance(inst),
crypto/lrw.c
332
skcipher_crypto_instance(inst),
crypto/lrw.c
348
err = crypto_inst_setname(skcipher_crypto_instance(inst), "lrw",
crypto/lrw.c
371
if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME,
crypto/lrw.c
379
inst->alg.base.cra_priority = alg->base.cra_priority;
crypto/lrw.c
380
inst->alg.base.cra_blocksize = LRW_BLOCK_SIZE;
crypto/lrw.c
381
inst->alg.base.cra_alignmask = alg->base.cra_alignmask |
crypto/lrw.c
384
inst->alg.ivsize = LRW_BLOCK_SIZE;
crypto/lrw.c
385
inst->alg.min_keysize = alg->min_keysize + LRW_BLOCK_SIZE;
crypto/lrw.c
386
inst->alg.max_keysize = alg->max_keysize + LRW_BLOCK_SIZE;
crypto/lrw.c
388
inst->alg.base.cra_ctxsize = sizeof(struct lrw_tfm_ctx);
crypto/lrw.c
390
inst->alg.init = lrw_init_tfm;
crypto/lrw.c
391
inst->alg.exit = lrw_exit_tfm;
crypto/lrw.c
393
inst->alg.setkey = lrw_setkey;
crypto/lrw.c
394
inst->alg.encrypt = lrw_encrypt;
crypto/lrw.c
395
inst->alg.decrypt = lrw_decrypt;
crypto/lrw.c
397
inst->free = lrw_free_instance;
crypto/lrw.c
399
err = skcipher_register_instance(tmpl, inst);
crypto/lrw.c
402
lrw_free_instance(inst);
crypto/lskcipher.c
241
static void crypto_lskcipher_free_instance(struct crypto_instance *inst)
crypto/lskcipher.c
244
container_of(inst, struct lskcipher_instance, s.base);
crypto/lskcipher.c
327
struct crypto_instance *inst,
crypto/lskcipher.c
331
return crypto_grab_spawn(&spawn->base, inst, name, type, mask);
crypto/lskcipher.c
405
struct lskcipher_instance *inst)
crypto/lskcipher.c
409
if (WARN_ON(!inst->free))
crypto/lskcipher.c
412
err = lskcipher_prepare_alg(&inst->alg);
crypto/lskcipher.c
416
return crypto_register_instance(tmpl, lskcipher_crypto_instance(inst));
crypto/lskcipher.c
433
struct lskcipher_instance *inst = lskcipher_alg_instance(tfm);
crypto/lskcipher.c
438
spawn = lskcipher_instance_ctx(inst);
crypto/lskcipher.c
454
static void lskcipher_free_instance_simple(struct lskcipher_instance *inst)
crypto/lskcipher.c
456
crypto_drop_lskcipher(lskcipher_instance_ctx(inst));
crypto/lskcipher.c
457
kfree(inst);
crypto/lskcipher.c
481
struct lskcipher_instance *inst;
crypto/lskcipher.c
496
inst = kzalloc(sizeof(*inst) + sizeof(*spawn), GFP_KERNEL);
crypto/lskcipher.c
497
if (!inst)
crypto/lskcipher.c
500
spawn = lskcipher_instance_ctx(inst);
crypto/lskcipher.c
502
lskcipher_crypto_instance(inst),
crypto/lskcipher.c
513
lskcipher_crypto_instance(inst),
crypto/lskcipher.c
522
err = crypto_inst_setname(lskcipher_crypto_instance(inst), tmpl->name,
crypto/lskcipher.c
542
if (snprintf(inst->alg.co.base.cra_name, CRYPTO_MAX_ALG_NAME,
crypto/lskcipher.c
548
snprintf(inst->alg.co.base.cra_driver_name,
crypto/lskcipher.c
564
inst->free = lskcipher_free_instance_simple;
crypto/lskcipher.c
567
inst->alg.co.base.cra_blocksize = cipher_alg->co.base.cra_blocksize;
crypto/lskcipher.c
568
inst->alg.co.base.cra_alignmask = cipher_alg->co.base.cra_alignmask;
crypto/lskcipher.c
569
inst->alg.co.base.cra_priority = cipher_alg->co.base.cra_priority;
crypto/lskcipher.c
570
inst->alg.co.min_keysize = cipher_alg->co.min_keysize;
crypto/lskcipher.c
571
inst->alg.co.max_keysize = cipher_alg->co.max_keysize;
crypto/lskcipher.c
572
inst->alg.co.ivsize = cipher_alg->co.base.cra_blocksize;
crypto/lskcipher.c
573
inst->alg.co.statesize = cipher_alg->co.statesize;
crypto/lskcipher.c
576
inst->alg.co.base.cra_ctxsize = sizeof(struct crypto_lskcipher *);
crypto/lskcipher.c
577
inst->alg.setkey = lskcipher_setkey_simple;
crypto/lskcipher.c
578
inst->alg.init = lskcipher_init_tfm_simple;
crypto/lskcipher.c
579
inst->alg.exit = lskcipher_exit_tfm_simple;
crypto/lskcipher.c
581
return inst;
crypto/lskcipher.c
584
lskcipher_free_instance_simple(inst);
crypto/pcrypt.c
189
struct aead_instance *inst = aead_alg_instance(tfm);
crypto/pcrypt.c
190
struct pcrypt_instance_ctx *ictx = aead_instance_ctx(inst);
crypto/pcrypt.c
218
static void pcrypt_free(struct aead_instance *inst)
crypto/pcrypt.c
220
struct pcrypt_instance_ctx *ctx = aead_instance_ctx(inst);
crypto/pcrypt.c
225
kfree(inst);
crypto/pcrypt.c
228
static int pcrypt_init_instance(struct crypto_instance *inst,
crypto/pcrypt.c
231
if (snprintf(inst->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME,
crypto/pcrypt.c
235
memcpy(inst->alg.cra_name, alg->cra_name, CRYPTO_MAX_ALG_NAME);
crypto/pcrypt.c
237
inst->alg.cra_priority = alg->cra_priority + 100;
crypto/pcrypt.c
238
inst->alg.cra_blocksize = alg->cra_blocksize;
crypto/pcrypt.c
239
inst->alg.cra_alignmask = alg->cra_alignmask;
crypto/pcrypt.c
248
struct aead_instance *inst;
crypto/pcrypt.c
253
inst = kzalloc(sizeof(*inst) + sizeof(*ctx), GFP_KERNEL);
crypto/pcrypt.c
254
if (!inst)
crypto/pcrypt.c
259
ctx = aead_instance_ctx(inst);
crypto/pcrypt.c
268
err = crypto_grab_aead(&ctx->spawn, aead_crypto_instance(inst),
crypto/pcrypt.c
274
err = pcrypt_init_instance(aead_crypto_instance(inst), &alg->base);
crypto/pcrypt.c
278
inst->alg.base.cra_flags |= CRYPTO_ALG_ASYNC;
crypto/pcrypt.c
280
inst->alg.ivsize = crypto_aead_alg_ivsize(alg);
crypto/pcrypt.c
281
inst->alg.maxauthsize = crypto_aead_alg_maxauthsize(alg);
crypto/pcrypt.c
283
inst->alg.base.cra_ctxsize = sizeof(struct pcrypt_aead_ctx);
crypto/pcrypt.c
285
inst->alg.init = pcrypt_aead_init_tfm;
crypto/pcrypt.c
286
inst->alg.exit = pcrypt_aead_exit_tfm;
crypto/pcrypt.c
288
inst->alg.setkey = pcrypt_aead_setkey;
crypto/pcrypt.c
289
inst->alg.setauthsize = pcrypt_aead_setauthsize;
crypto/pcrypt.c
290
inst->alg.encrypt = pcrypt_aead_encrypt;
crypto/pcrypt.c
291
inst->alg.decrypt = pcrypt_aead_decrypt;
crypto/pcrypt.c
293
inst->free = pcrypt_free;
crypto/pcrypt.c
295
err = aead_register_instance(tmpl, inst);
crypto/pcrypt.c
298
pcrypt_free(inst);
crypto/rsa-pkcs1pad.c
277
struct akcipher_instance *inst = akcipher_alg_instance(tfm);
crypto/rsa-pkcs1pad.c
278
struct pkcs1pad_inst_ctx *ictx = akcipher_instance_ctx(inst);
crypto/rsa-pkcs1pad.c
301
static void pkcs1pad_free(struct akcipher_instance *inst)
crypto/rsa-pkcs1pad.c
303
struct pkcs1pad_inst_ctx *ctx = akcipher_instance_ctx(inst);
crypto/rsa-pkcs1pad.c
307
kfree(inst);
crypto/rsa-pkcs1pad.c
313
struct akcipher_instance *inst;
crypto/rsa-pkcs1pad.c
322
inst = kzalloc(sizeof(*inst) + sizeof(*ctx), GFP_KERNEL);
crypto/rsa-pkcs1pad.c
323
if (!inst)
crypto/rsa-pkcs1pad.c
326
ctx = akcipher_instance_ctx(inst);
crypto/rsa-pkcs1pad.c
328
err = crypto_grab_akcipher(&ctx->spawn, akcipher_crypto_instance(inst),
crypto/rsa-pkcs1pad.c
341
if (snprintf(inst->alg.base.cra_name,
crypto/rsa-pkcs1pad.c
346
if (snprintf(inst->alg.base.cra_driver_name,
crypto/rsa-pkcs1pad.c
351
inst->alg.base.cra_priority = rsa_alg->base.cra_priority;
crypto/rsa-pkcs1pad.c
352
inst->alg.base.cra_ctxsize = sizeof(struct pkcs1pad_ctx);
crypto/rsa-pkcs1pad.c
354
inst->alg.init = pkcs1pad_init_tfm;
crypto/rsa-pkcs1pad.c
355
inst->alg.exit = pkcs1pad_exit_tfm;
crypto/rsa-pkcs1pad.c
357
inst->alg.encrypt = pkcs1pad_encrypt;
crypto/rsa-pkcs1pad.c
358
inst->alg.decrypt = pkcs1pad_decrypt;
crypto/rsa-pkcs1pad.c
359
inst->alg.set_pub_key = pkcs1pad_set_pub_key;
crypto/rsa-pkcs1pad.c
360
inst->alg.set_priv_key = pkcs1pad_set_priv_key;
crypto/rsa-pkcs1pad.c
361
inst->alg.max_size = pkcs1pad_get_max_size;
crypto/rsa-pkcs1pad.c
363
inst->free = pkcs1pad_free;
crypto/rsa-pkcs1pad.c
365
err = akcipher_register_instance(tmpl, inst);
crypto/rsa-pkcs1pad.c
368
pkcs1pad_free(inst);
crypto/rsassa-pkcs1.c
162
struct sig_instance *inst = sig_alg_instance(tfm);
crypto/rsassa-pkcs1.c
163
struct rsassa_pkcs1_inst_ctx *ictx = sig_instance_ctx(inst);
crypto/rsassa-pkcs1.c
220
struct sig_instance *inst = sig_alg_instance(tfm);
crypto/rsassa-pkcs1.c
221
struct rsassa_pkcs1_inst_ctx *ictx = sig_instance_ctx(inst);
crypto/rsassa-pkcs1.c
325
struct sig_instance *inst = sig_alg_instance(tfm);
crypto/rsassa-pkcs1.c
326
struct rsassa_pkcs1_inst_ctx *ictx = sig_instance_ctx(inst);
crypto/rsassa-pkcs1.c
346
static void rsassa_pkcs1_free(struct sig_instance *inst)
crypto/rsassa-pkcs1.c
348
struct rsassa_pkcs1_inst_ctx *ctx = sig_instance_ctx(inst);
crypto/rsassa-pkcs1.c
352
kfree(inst);
crypto/rsassa-pkcs1.c
359
struct sig_instance *inst;
crypto/rsassa-pkcs1.c
368
inst = kzalloc(sizeof(*inst) + sizeof(*ctx), GFP_KERNEL);
crypto/rsassa-pkcs1.c
369
if (!inst)
crypto/rsassa-pkcs1.c
372
ctx = sig_instance_ctx(inst);
crypto/rsassa-pkcs1.c
374
err = crypto_grab_akcipher(&ctx->spawn, sig_crypto_instance(inst),
crypto/rsassa-pkcs1.c
399
if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME,
crypto/rsassa-pkcs1.c
404
if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME,
crypto/rsassa-pkcs1.c
409
inst->alg.base.cra_priority = rsa_alg->base.cra_priority;
crypto/rsassa-pkcs1.c
410
inst->alg.base.cra_ctxsize = sizeof(struct rsassa_pkcs1_ctx);
crypto/rsassa-pkcs1.c
412
inst->alg.init = rsassa_pkcs1_init_tfm;
crypto/rsassa-pkcs1.c
413
inst->alg.exit = rsassa_pkcs1_exit_tfm;
crypto/rsassa-pkcs1.c
415
inst->alg.sign = rsassa_pkcs1_sign;
crypto/rsassa-pkcs1.c
416
inst->alg.verify = rsassa_pkcs1_verify;
crypto/rsassa-pkcs1.c
417
inst->alg.key_size = rsassa_pkcs1_key_size;
crypto/rsassa-pkcs1.c
418
inst->alg.set_pub_key = rsassa_pkcs1_set_pub_key;
crypto/rsassa-pkcs1.c
419
inst->alg.set_priv_key = rsassa_pkcs1_set_priv_key;
crypto/rsassa-pkcs1.c
421
inst->free = rsassa_pkcs1_free;
crypto/rsassa-pkcs1.c
423
err = sig_register_instance(tmpl, inst);
crypto/rsassa-pkcs1.c
426
rsassa_pkcs1_free(inst);
crypto/seqiv.c
128
struct aead_instance *inst;
crypto/seqiv.c
131
inst = aead_geniv_alloc(tmpl, tb);
crypto/seqiv.c
133
if (IS_ERR(inst))
crypto/seqiv.c
134
return PTR_ERR(inst);
crypto/seqiv.c
137
if (inst->alg.ivsize != sizeof(u64))
crypto/seqiv.c
140
inst->alg.encrypt = seqiv_aead_encrypt;
crypto/seqiv.c
141
inst->alg.decrypt = seqiv_aead_decrypt;
crypto/seqiv.c
143
inst->alg.init = aead_init_geniv;
crypto/seqiv.c
144
inst->alg.exit = aead_exit_geniv;
crypto/seqiv.c
146
inst->alg.base.cra_ctxsize = sizeof(struct aead_geniv_ctx);
crypto/seqiv.c
147
inst->alg.base.cra_ctxsize += inst->alg.ivsize;
crypto/seqiv.c
149
err = aead_register_instance(tmpl, inst);
crypto/seqiv.c
152
inst->free(inst);
crypto/shash.c
326
static void crypto_shash_free_instance(struct crypto_instance *inst)
crypto/shash.c
328
struct shash_instance *shash = shash_instance(inst);
crypto/shash.c
375
struct crypto_instance *inst,
crypto/shash.c
379
return crypto_grab_spawn(&spawn->base, inst, name, type, mask);
crypto/shash.c
525
struct shash_instance *inst)
crypto/shash.c
529
if (WARN_ON(!inst->free))
crypto/shash.c
532
err = shash_prepare_alg(&inst->alg);
crypto/shash.c
536
return crypto_register_instance(tmpl, shash_crypto_instance(inst));
crypto/shash.c
540
void shash_free_singlespawn_instance(struct shash_instance *inst)
crypto/shash.c
542
crypto_drop_spawn(shash_instance_ctx(inst));
crypto/shash.c
543
kfree(inst);
crypto/sig.c
157
struct sig_instance *inst)
crypto/sig.c
161
if (WARN_ON(!inst->free))
crypto/sig.c
164
err = sig_prepare_alg(&inst->alg);
crypto/sig.c
168
return crypto_register_instance(tmpl, sig_crypto_instance(inst));
crypto/sig.c
173
struct crypto_instance *inst,
crypto/sig.c
177
return crypto_grab_spawn(&spawn->base, inst, name, type, mask);
crypto/sig.c
40
static void crypto_sig_free_instance(struct crypto_instance *inst)
crypto/sig.c
42
struct sig_instance *sig = sig_instance(inst);
crypto/skcipher.c
565
static void crypto_skcipher_free_instance(struct crypto_instance *inst)
crypto/skcipher.c
568
container_of(inst, struct skcipher_instance, s.base);
crypto/skcipher.c
626
struct crypto_instance *inst,
crypto/skcipher.c
630
return crypto_grab_spawn(&spawn->base, inst, name, type, mask);
crypto/skcipher.c
761
struct skcipher_instance *inst)
crypto/skcipher.c
765
if (WARN_ON(!inst->free))
crypto/skcipher.c
768
err = skcipher_prepare_alg(&inst->alg);
crypto/skcipher.c
772
return crypto_register_instance(tmpl, skcipher_crypto_instance(inst));
crypto/skcipher.c
789
struct skcipher_instance *inst = skcipher_alg_instance(tfm);
crypto/skcipher.c
790
struct crypto_cipher_spawn *spawn = skcipher_instance_ctx(inst);
crypto/skcipher.c
809
static void skcipher_free_instance_simple(struct skcipher_instance *inst)
crypto/skcipher.c
811
crypto_drop_cipher(skcipher_instance_ctx(inst));
crypto/skcipher.c
812
kfree(inst);
crypto/skcipher.c
835
struct skcipher_instance *inst;
crypto/skcipher.c
844
inst = kzalloc(sizeof(*inst) + sizeof(*spawn), GFP_KERNEL);
crypto/skcipher.c
845
if (!inst)
crypto/skcipher.c
847
spawn = skcipher_instance_ctx(inst);
crypto/skcipher.c
849
err = crypto_grab_cipher(spawn, skcipher_crypto_instance(inst),
crypto/skcipher.c
855
err = crypto_inst_setname(skcipher_crypto_instance(inst), tmpl->name,
crypto/skcipher.c
860
inst->free = skcipher_free_instance_simple;
crypto/skcipher.c
863
inst->alg.base.cra_blocksize = cipher_alg->cra_blocksize;
crypto/skcipher.c
864
inst->alg.base.cra_alignmask = cipher_alg->cra_alignmask;
crypto/skcipher.c
865
inst->alg.base.cra_priority = cipher_alg->cra_priority;
crypto/skcipher.c
866
inst->alg.min_keysize = cipher_alg->cra_cipher.cia_min_keysize;
crypto/skcipher.c
867
inst->alg.max_keysize = cipher_alg->cra_cipher.cia_max_keysize;
crypto/skcipher.c
868
inst->alg.ivsize = cipher_alg->cra_blocksize;
crypto/skcipher.c
871
inst->alg.base.cra_ctxsize = sizeof(struct skcipher_ctx_simple);
crypto/skcipher.c
872
inst->alg.setkey = skcipher_setkey_simple;
crypto/skcipher.c
873
inst->alg.init = skcipher_init_tfm_simple;
crypto/skcipher.c
874
inst->alg.exit = skcipher_exit_tfm_simple;
crypto/skcipher.c
876
return inst;
crypto/skcipher.c
879
skcipher_free_instance_simple(inst);
crypto/xcbc.c
108
struct crypto_instance *inst = (void *)tfm->__crt_alg;
crypto/xcbc.c
109
struct crypto_cipher_spawn *spawn = crypto_instance_ctx(inst);
crypto/xcbc.c
129
struct shash_instance *inst;
crypto/xcbc.c
139
inst = kzalloc(sizeof(*inst) + sizeof(*spawn), GFP_KERNEL);
crypto/xcbc.c
140
if (!inst)
crypto/xcbc.c
142
spawn = shash_instance_ctx(inst);
crypto/xcbc.c
144
err = crypto_grab_cipher(spawn, shash_crypto_instance(inst),
crypto/xcbc.c
154
err = crypto_inst_setname(shash_crypto_instance(inst), tmpl->name, alg);
crypto/xcbc.c
158
inst->alg.base.cra_priority = alg->cra_priority;
crypto/xcbc.c
159
inst->alg.base.cra_blocksize = alg->cra_blocksize;
crypto/xcbc.c
160
inst->alg.base.cra_ctxsize = sizeof(struct xcbc_tfm_ctx) +
crypto/xcbc.c
162
inst->alg.base.cra_flags = CRYPTO_AHASH_ALG_BLOCK_ONLY |
crypto/xcbc.c
165
inst->alg.digestsize = alg->cra_blocksize;
crypto/xcbc.c
166
inst->alg.descsize = alg->cra_blocksize;
crypto/xcbc.c
168
inst->alg.base.cra_init = xcbc_init_tfm;
crypto/xcbc.c
169
inst->alg.base.cra_exit = xcbc_exit_tfm;
crypto/xcbc.c
171
inst->alg.init = crypto_xcbc_digest_init;
crypto/xcbc.c
172
inst->alg.update = crypto_xcbc_digest_update;
crypto/xcbc.c
173
inst->alg.finup = crypto_xcbc_digest_finup;
crypto/xcbc.c
174
inst->alg.setkey = crypto_xcbc_digest_setkey;
crypto/xcbc.c
176
inst->free = shash_free_singlespawn_instance;
crypto/xcbc.c
178
err = shash_register_instance(tmpl, inst);
crypto/xcbc.c
181
shash_free_singlespawn_instance(inst);
crypto/xctr.c
133
struct skcipher_instance *inst;
crypto/xctr.c
137
inst = skcipher_alloc_instance_simple(tmpl, tb);
crypto/xctr.c
138
if (IS_ERR(inst))
crypto/xctr.c
139
return PTR_ERR(inst);
crypto/xctr.c
141
alg = skcipher_ialg_simple(inst);
crypto/xctr.c
149
inst->alg.base.cra_blocksize = 1;
crypto/xctr.c
155
inst->alg.chunksize = alg->cra_blocksize;
crypto/xctr.c
157
inst->alg.encrypt = crypto_xctr_crypt;
crypto/xctr.c
158
inst->alg.decrypt = crypto_xctr_crypt;
crypto/xctr.c
160
err = skcipher_register_instance(tmpl, inst);
crypto/xctr.c
163
inst->free(inst);
crypto/xts.c
297
struct skcipher_instance *inst = skcipher_alg_instance(tfm);
crypto/xts.c
298
struct xts_instance_ctx *ictx = skcipher_instance_ctx(inst);
crypto/xts.c
331
static void xts_free_instance(struct skcipher_instance *inst)
crypto/xts.c
333
struct xts_instance_ctx *ictx = skcipher_instance_ctx(inst);
crypto/xts.c
337
kfree(inst);
crypto/xts.c
344
struct skcipher_instance *inst;
crypto/xts.c
358
inst = kzalloc(sizeof(*inst) + sizeof(*ctx), GFP_KERNEL);
crypto/xts.c
359
if (!inst)
crypto/xts.c
362
ctx = skcipher_instance_ctx(inst);
crypto/xts.c
364
err = crypto_grab_skcipher(&ctx->spawn, skcipher_crypto_instance(inst),
crypto/xts.c
373
skcipher_crypto_instance(inst),
crypto/xts.c
389
err = crypto_inst_setname(skcipher_crypto_instance(inst), "xts",
crypto/xts.c
412
if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME,
crypto/xts.c
421
skcipher_crypto_instance(inst), name, 0, mask);
crypto/xts.c
425
inst->alg.base.cra_priority = alg->base.cra_priority;
crypto/xts.c
426
inst->alg.base.cra_blocksize = XTS_BLOCK_SIZE;
crypto/xts.c
427
inst->alg.base.cra_alignmask = alg->base.cra_alignmask |
crypto/xts.c
430
inst->alg.ivsize = XTS_BLOCK_SIZE;
crypto/xts.c
431
inst->alg.min_keysize = alg->min_keysize * 2;
crypto/xts.c
432
inst->alg.max_keysize = alg->max_keysize * 2;
crypto/xts.c
434
inst->alg.base.cra_ctxsize = sizeof(struct xts_tfm_ctx);
crypto/xts.c
436
inst->alg.init = xts_init_tfm;
crypto/xts.c
437
inst->alg.exit = xts_exit_tfm;
crypto/xts.c
439
inst->alg.setkey = xts_setkey;
crypto/xts.c
440
inst->alg.encrypt = xts_encrypt;
crypto/xts.c
441
inst->alg.decrypt = xts_decrypt;
crypto/xts.c
443
inst->free = xts_free_instance;
crypto/xts.c
445
err = skcipher_register_instance(tmpl, inst);
crypto/xts.c
448
xts_free_instance(inst);
drivers/accel/habanalabs/common/habanalabs.h
248
void (*fn)(struct hl_device *hdev, int block, int inst, u32 offset,
drivers/accel/habanalabs/gaudi2/gaudi2.c
2586
int dcore, inst, tpc_seq;
drivers/accel/habanalabs/gaudi2/gaudi2.c
2593
for (inst = 0; inst < NUM_OF_TPC_PER_DCORE; inst++) {
drivers/accel/habanalabs/gaudi2/gaudi2.c
2594
tpc_seq = dcore * NUM_OF_TPC_PER_DCORE + inst;
drivers/accel/habanalabs/gaudi2/gaudi2.c
2599
offset = (DCORE_OFFSET * dcore) + (DCORE_TPC_OFFSET * inst);
drivers/accel/habanalabs/gaudi2/gaudi2.c
2601
ctx->fn(hdev, dcore, inst, offset, ctx);
drivers/accel/habanalabs/gaudi2/gaudi2.c
2604
dcore, inst);
drivers/accel/habanalabs/gaudi2/gaudi2.c
4260
int dcore, inst;
drivers/accel/habanalabs/gaudi2/gaudi2.c
4274
for (inst = 0 ; inst < NUM_OF_EDMA_PER_DCORE ; inst++) {
drivers/accel/habanalabs/gaudi2/gaudi2.c
4275
u8 seq = dcore * NUM_OF_EDMA_PER_DCORE + inst;
drivers/accel/habanalabs/gaudi2/gaudi2.c
4282
inst * DCORE_EDMA_OFFSET;
drivers/accel/habanalabs/gaudi2/gaudi2.c
4372
int dcore, inst;
drivers/accel/habanalabs/gaudi2/gaudi2.c
4385
for (inst = 0 ; inst < NUM_OF_EDMA_PER_DCORE ; inst++) {
drivers/accel/habanalabs/gaudi2/gaudi2.c
4386
u8 seq = dcore * NUM_OF_EDMA_PER_DCORE + inst;
drivers/accel/habanalabs/gaudi2/gaudi2.c
4393
inst * DCORE_EDMA_OFFSET;
drivers/accel/habanalabs/gaudi2/gaudi2.c
4460
int dcore, inst;
drivers/accel/habanalabs/gaudi2/gaudi2.c
4473
for (inst = 0 ; inst < NUM_OF_EDMA_PER_DCORE ; inst++) {
drivers/accel/habanalabs/gaudi2/gaudi2.c
4474
u8 seq = dcore * NUM_OF_EDMA_PER_DCORE + inst;
drivers/accel/habanalabs/gaudi2/gaudi2.c
4481
inst * DCORE_EDMA_OFFSET;
drivers/accel/habanalabs/gaudi2/gaudi2.c
5632
int dcore, inst;
drivers/accel/habanalabs/gaudi2/gaudi2.c
5638
for (inst = 0 ; inst < NUM_OF_EDMA_PER_DCORE ; inst++) {
drivers/accel/habanalabs/gaudi2/gaudi2.c
5639
u8 seq = dcore * NUM_OF_EDMA_PER_DCORE + inst;
drivers/accel/habanalabs/gaudi2/gaudi2.c
5880
static void gaudi2_init_tpc_config(struct hl_device *hdev, int dcore, int inst,
drivers/accel/habanalabs/gaudi2/gaudi2.c
5888
queue_id_base = cfg_data->dcore_tpc_qid_base[dcore] + (inst * NUM_OF_PQ_PER_QMAN);
drivers/accel/habanalabs/gaudi2/gaudi2.c
5890
if (dcore == 0 && inst == (NUM_DCORE0_TPC - 1))
drivers/accel/habanalabs/gaudi2/gaudi2.c
5894
seq = dcore * NUM_OF_TPC_PER_DCORE + inst;
drivers/accel/habanalabs/gaudi2/gaudi2.c
7682
static void gaudi2_is_tpc_engine_idle(struct hl_device *hdev, int dcore, int inst, u32 offset,
drivers/accel/habanalabs/gaudi2/gaudi2.c
7690
if ((dcore == 0) && (inst == (NUM_DCORE0_TPC - 1)))
drivers/accel/habanalabs/gaudi2/gaudi2.c
7694
dcore * GAUDI2_ENGINE_ID_DCORE_OFFSET + inst;
drivers/accel/habanalabs/gaudi2/gaudi2.c
7710
idle_data->tpc_fmt, dcore, inst,
drivers/accel/habanalabs/gaudi2/gaudi2.c
8147
static void gaudi2_tpc_mmu_prepare(struct hl_device *hdev, int dcore, int inst, u32 offset,
drivers/accel/habanalabs/gaudi2/gaudi2_security.c
2604
static void gaudi2_config_tpcs_glbl_sec(struct hl_device *hdev, int dcore, int inst, u32 offset,
drivers/accel/habanalabs/gaudi2/gaudi2_security.c
2684
static void gaudi2_config_tpcs_pb_ranges(struct hl_device *hdev, int dcore, int inst, u32 offset,
drivers/accel/habanalabs/gaudi2/gaudi2_security.c
3573
static void gaudi2_ack_pb_tpc_config(struct hl_device *hdev, int dcore, int inst, u32 offset,
drivers/char/ipmi/ipmi_plat_data.c
11
struct platform_device *ipmi_platform_add(const char *name, unsigned int inst,
drivers/char/ipmi/ipmi_plat_data.c
48
pdev = platform_device_alloc(name, inst);
drivers/char/ipmi/ipmi_plat_data.c
51
name, inst);
drivers/char/ipmi/ipmi_plat_data.h
24
struct platform_device *ipmi_platform_add(const char *name, unsigned int inst,
drivers/crypto/intel/keembay/keembay-ocs-ecc.c
152
u32 inst,
drivers/crypto/intel/keembay/keembay-ocs-ecc.c
156
iowrite32(op_size | inst, dev->base_reg + HW_OFFS_OCS_ECC_COMMAND);
drivers/crypto/intel/keembay/keembay-ocs-ecc.c
165
u32 inst)
drivers/crypto/intel/keembay/keembay-ocs-ecc.c
170
iowrite32(op_size | inst, ecc_dev->base_reg + HW_OFFS_OCS_ECC_COMMAND);
drivers/crypto/intel/keembay/keembay-ocs-ecc.c
303
unsigned int ndigits, const u32 inst)
drivers/crypto/intel/keembay/keembay-ocs-ecc.c
331
rc = ocs_ecc_trigger_op(ecc_dev, op_size, inst);
drivers/crypto/intel/qat/qat_common/adf_common_drv.h
105
void qat_compression_put_instance(struct qat_compression_instance *inst);
drivers/crypto/intel/qat/qat_common/adf_common_drv.h
96
void qat_crypto_put_instance(struct qat_crypto_instance *inst);
drivers/crypto/intel/qat/qat_common/qat_algs.c
1022
ret = qat_bl_sgl_to_bufl(ctx->inst->accel_dev, req->src, req->dst,
drivers/crypto/intel/qat/qat_common/qat_algs.c
1043
ret = qat_alg_send_sym_message(qat_req, ctx->inst, &req->base);
drivers/crypto/intel/qat/qat_common/qat_algs.c
1045
qat_bl_free_bufl(ctx->inst->accel_dev, &qat_req->buf);
drivers/crypto/intel/qat/qat_common/qat_algs.c
1111
struct qat_crypto_instance *inst = ctx->inst;
drivers/crypto/intel/qat/qat_common/qat_algs.c
1114
if (!inst)
drivers/crypto/intel/qat/qat_common/qat_algs.c
1117
dev = &GET_DEV(inst->accel_dev);
drivers/crypto/intel/qat/qat_common/qat_algs.c
1128
qat_crypto_put_instance(inst);
drivers/crypto/intel/qat/qat_common/qat_algs.c
1164
struct qat_crypto_instance *inst = ctx->inst;
drivers/crypto/intel/qat/qat_common/qat_algs.c
1167
if (!inst)
drivers/crypto/intel/qat/qat_common/qat_algs.c
1170
dev = &GET_DEV(inst->accel_dev);
drivers/crypto/intel/qat/qat_common/qat_algs.c
1185
qat_crypto_put_instance(inst);
drivers/crypto/intel/qat/qat_common/qat_algs.c
341
bool aes_v2_capable = HW_CAP_AES_V2(ctx->inst->accel_dev);
drivers/crypto/intel/qat/qat_common/qat_algs.c
417
bool aes_v2_capable = HW_CAP_AES_V2(ctx->inst->accel_dev);
drivers/crypto/intel/qat/qat_common/qat_algs.c
531
struct qat_crypto_instance *inst = NULL;
drivers/crypto/intel/qat/qat_common/qat_algs.c
536
inst = qat_crypto_get_instance_node(node);
drivers/crypto/intel/qat/qat_common/qat_algs.c
537
if (!inst)
drivers/crypto/intel/qat/qat_common/qat_algs.c
539
dev = &GET_DEV(inst->accel_dev);
drivers/crypto/intel/qat/qat_common/qat_algs.c
540
ctx->inst = inst;
drivers/crypto/intel/qat/qat_common/qat_algs.c
574
ctx->inst = NULL;
drivers/crypto/intel/qat/qat_common/qat_algs.c
575
qat_crypto_put_instance(inst);
drivers/crypto/intel/qat/qat_common/qat_algs.c
594
struct qat_crypto_instance *inst = ctx->inst;
drivers/crypto/intel/qat/qat_common/qat_algs.c
599
qat_bl_free_bufl(inst->accel_dev, &qat_req->buf);
drivers/crypto/intel/qat/qat_common/qat_algs.c
643
struct device *dev = &GET_DEV(ctx->inst->accel_dev);
drivers/crypto/intel/qat/qat_common/qat_algs.c
664
struct qat_crypto_instance *inst = ctx->inst;
drivers/crypto/intel/qat/qat_common/qat_algs.c
669
qat_bl_free_bufl(inst->accel_dev, &qat_req->buf);
drivers/crypto/intel/qat/qat_common/qat_algs.c
694
struct qat_crypto_instance *inst,
drivers/crypto/intel/qat/qat_common/qat_algs.c
700
alg_req->tx_ring = inst->sym_tx;
drivers/crypto/intel/qat/qat_common/qat_algs.c
702
alg_req->backlog = &inst->backlog;
drivers/crypto/intel/qat/qat_common/qat_algs.c
72
struct qat_crypto_instance *inst;
drivers/crypto/intel/qat/qat_common/qat_algs.c
725
ret = qat_bl_sgl_to_bufl(ctx->inst->accel_dev, areq->src, areq->dst,
drivers/crypto/intel/qat/qat_common/qat_algs.c
746
ret = qat_alg_send_sym_message(qat_req, ctx->inst, &areq->base);
drivers/crypto/intel/qat/qat_common/qat_algs.c
748
qat_bl_free_bufl(ctx->inst->accel_dev, &qat_req->buf);
drivers/crypto/intel/qat/qat_common/qat_algs.c
769
ret = qat_bl_sgl_to_bufl(ctx->inst->accel_dev, areq->src, areq->dst,
drivers/crypto/intel/qat/qat_common/qat_algs.c
792
ret = qat_alg_send_sym_message(qat_req, ctx->inst, &areq->base);
drivers/crypto/intel/qat/qat_common/qat_algs.c
794
qat_bl_free_bufl(ctx->inst->accel_dev, &qat_req->buf);
drivers/crypto/intel/qat/qat_common/qat_algs.c
815
struct qat_crypto_instance *inst = NULL;
drivers/crypto/intel/qat/qat_common/qat_algs.c
82
struct qat_crypto_instance *inst;
drivers/crypto/intel/qat/qat_common/qat_algs.c
820
inst = qat_crypto_get_instance_node(node);
drivers/crypto/intel/qat/qat_common/qat_algs.c
821
if (!inst)
drivers/crypto/intel/qat/qat_common/qat_algs.c
823
dev = &GET_DEV(inst->accel_dev);
drivers/crypto/intel/qat/qat_common/qat_algs.c
824
ctx->inst = inst;
drivers/crypto/intel/qat/qat_common/qat_algs.c
857
ctx->inst = NULL;
drivers/crypto/intel/qat/qat_common/qat_algs.c
858
qat_crypto_put_instance(inst);
drivers/crypto/intel/qat/qat_common/qat_algs.c
917
if (HW_CAP_AES_V2(ctx->inst->accel_dev))
drivers/crypto/intel/qat/qat_common/qat_algs.c
928
bool aes_v2_capable = HW_CAP_AES_V2(ctx->inst->accel_dev);
drivers/crypto/intel/qat/qat_common/qat_algs.c
955
ret = qat_bl_sgl_to_bufl(ctx->inst->accel_dev, req->src, req->dst,
drivers/crypto/intel/qat/qat_common/qat_algs.c
975
ret = qat_alg_send_sym_message(qat_req, ctx->inst, &req->base);
drivers/crypto/intel/qat/qat_common/qat_algs.c
977
qat_bl_free_bufl(ctx->inst->accel_dev, &qat_req->buf);
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
1017
struct qat_crypto_instance *inst = ctx->inst;
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
1018
struct device *dev = &GET_DEV(inst->accel_dev);
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
1042
struct qat_crypto_instance *inst = ctx->inst;
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
1043
struct device *dev = &GET_DEV(inst->accel_dev);
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
1078
struct qat_crypto_instance *inst = ctx->inst;
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
1079
struct device *dev = &GET_DEV(inst->accel_dev);
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
112
struct qat_crypto_instance *inst;
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
1215
struct device *dev = &GET_DEV(ctx->inst->accel_dev);
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
1280
struct qat_crypto_instance *inst =
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
1283
if (!inst)
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
1289
ctx->inst = inst;
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
1296
struct device *dev = &GET_DEV(ctx->inst->accel_dev);
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
1299
qat_crypto_put_instance(ctx->inst);
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
145
struct qat_crypto_instance *inst,
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
151
alg_req->tx_ring = inst->pke_tx;
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
153
alg_req->backlog = &inst->backlog;
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
162
struct device *dev = &GET_DEV(req->ctx.dh->inst->accel_dev);
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
223
struct qat_crypto_instance *inst = ctx->inst;
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
224
struct device *dev = &GET_DEV(inst->accel_dev);
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
354
ret = qat_alg_send_asym_message(qat_req, inst, &req->base);
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
430
struct qat_crypto_instance *inst = ctx->inst;
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
431
struct device *dev = &GET_DEV(inst->accel_dev);
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
479
struct device *dev = &GET_DEV(ctx->inst->accel_dev);
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
529
struct qat_crypto_instance *inst =
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
534
if (!inst)
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
550
ctx->inst = inst;
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
557
struct device *dev = &GET_DEV(ctx->inst->accel_dev);
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
563
qat_crypto_put_instance(ctx->inst);
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
570
struct device *dev = &GET_DEV(req->ctx.rsa->inst->accel_dev);
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
702
struct qat_crypto_instance *inst = ctx->inst;
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
703
struct device *dev = &GET_DEV(inst->accel_dev);
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
78
struct qat_crypto_instance *inst;
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
803
ret = qat_alg_send_asym_message(qat_req, inst, &req->base);
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
836
struct qat_crypto_instance *inst = ctx->inst;
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
837
struct device *dev = &GET_DEV(inst->accel_dev);
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
953
ret = qat_alg_send_asym_message(qat_req, inst, &req->base);
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
985
struct qat_crypto_instance *inst = ctx->inst;
drivers/crypto/intel/qat/qat_common/qat_asym_algs.c
986
struct device *dev = &GET_DEV(inst->accel_dev);
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
131
struct qat_compression_instance *inst;
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
148
struct qat_compression_instance *inst,
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
154
alg_req->tx_ring = inst->dc_tx;
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
156
alg_req->backlog = &inst->backlog;
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
166
struct adf_accel_dev *accel_dev = ctx->inst->accel_dev;
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
168
struct qat_compression_instance *inst = ctx->inst;
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
213
memset(inst->dc_data->ovf_buff, 0,
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
214
inst->dc_data->ovf_buff_sz);
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
251
struct qat_compression_instance *inst;
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
260
inst = qat_compression_get_instance_node(node, alg);
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
261
if (!inst)
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
263
ctx->inst = inst;
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
265
ret = qat_comp_build_ctx(inst->accel_dev, ctx->comp_ctx, alg);
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
267
qat_compression_put_instance(inst);
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
283
qat_compression_put_instance(ctx->inst);
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
294
struct qat_compression_instance *inst = ctx->inst;
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
314
params.extra_dst_buff = inst->dc_data->ovf_buff_p;
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
315
ovf_buff_sz = inst->dc_data->ovf_buff_sz;
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
319
ret = qat_bl_sgl_to_bufl(ctx->inst->accel_dev, areq->src, areq->dst,
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
344
ret = qat_alg_send_dc_message(qat_req, inst, &areq->base);
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
346
qat_bl_free_bufl(inst->accel_dev, &qat_req->buf);
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
375
dev_err(&GET_DEV(ctx->inst->accel_dev),
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
382
dev_dbg(&GET_DEV(ctx->inst->accel_dev), "Window size=0x%llx\n",
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
414
dev_dbg(&GET_DEV(qat_ctx->inst->accel_dev),
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
469
dev_dbg(&GET_DEV(qat_ctx->inst->accel_dev),
drivers/crypto/intel/qat/qat_common/qat_compression.c
121
inst = tmp_inst;
drivers/crypto/intel/qat/qat_common/qat_compression.c
125
if (inst) {
drivers/crypto/intel/qat/qat_common/qat_compression.c
130
atomic_inc(&inst->refctr);
drivers/crypto/intel/qat/qat_common/qat_compression.c
132
return inst;
drivers/crypto/intel/qat/qat_common/qat_compression.c
137
struct qat_compression_instance *inst;
drivers/crypto/intel/qat/qat_common/qat_compression.c
157
inst = kzalloc_node(sizeof(*inst), GFP_KERNEL,
drivers/crypto/intel/qat/qat_common/qat_compression.c
159
if (!inst) {
drivers/crypto/intel/qat/qat_common/qat_compression.c
164
list_add_tail(&inst->list, &accel_dev->compression_list);
drivers/crypto/intel/qat/qat_common/qat_compression.c
165
inst->id = i;
drivers/crypto/intel/qat/qat_common/qat_compression.c
166
atomic_set(&inst->refctr, 0);
drivers/crypto/intel/qat/qat_common/qat_compression.c
167
inst->accel_dev = accel_dev;
drivers/crypto/intel/qat/qat_common/qat_compression.c
18
void qat_compression_put_instance(struct qat_compression_instance *inst)
drivers/crypto/intel/qat/qat_common/qat_compression.c
190
msg_size, key, NULL, 0, &inst->dc_tx);
drivers/crypto/intel/qat/qat_common/qat_compression.c
198
&inst->dc_rx);
drivers/crypto/intel/qat/qat_common/qat_compression.c
20
atomic_dec(&inst->refctr);
drivers/crypto/intel/qat/qat_common/qat_compression.c
202
inst->dc_data = accel_dev->dc_data;
drivers/crypto/intel/qat/qat_common/qat_compression.c
203
INIT_LIST_HEAD(&inst->backlog.list);
drivers/crypto/intel/qat/qat_common/qat_compression.c
204
spin_lock_init(&inst->backlog.lock);
drivers/crypto/intel/qat/qat_common/qat_compression.c
21
adf_dev_put(inst->accel_dev);
drivers/crypto/intel/qat/qat_common/qat_compression.c
26
struct qat_compression_instance *inst;
drivers/crypto/intel/qat/qat_common/qat_compression.c
31
inst = list_entry(list_ptr,
drivers/crypto/intel/qat/qat_common/qat_compression.c
34
for (i = 0; i < atomic_read(&inst->refctr); i++)
drivers/crypto/intel/qat/qat_common/qat_compression.c
35
qat_compression_put_instance(inst);
drivers/crypto/intel/qat/qat_common/qat_compression.c
37
if (inst->dc_tx)
drivers/crypto/intel/qat/qat_common/qat_compression.c
38
adf_remove_ring(inst->dc_tx);
drivers/crypto/intel/qat/qat_common/qat_compression.c
40
if (inst->dc_rx)
drivers/crypto/intel/qat/qat_common/qat_compression.c
41
adf_remove_ring(inst->dc_rx);
drivers/crypto/intel/qat/qat_common/qat_compression.c
44
kfree(inst);
drivers/crypto/intel/qat/qat_common/qat_compression.c
51
struct qat_compression_instance *inst = NULL;
drivers/crypto/intel/qat/qat_common/qat_crypto.c
102
atomic_inc(&inst->refctr);
drivers/crypto/intel/qat/qat_common/qat_crypto.c
104
return inst;
drivers/crypto/intel/qat/qat_common/qat_crypto.c
137
struct qat_crypto_instance *inst;
drivers/crypto/intel/qat/qat_common/qat_crypto.c
152
inst = kzalloc_node(sizeof(*inst), GFP_KERNEL,
drivers/crypto/intel/qat/qat_common/qat_crypto.c
154
if (!inst) {
drivers/crypto/intel/qat/qat_common/qat_crypto.c
159
list_add_tail(&inst->list, &accel_dev->crypto_list);
drivers/crypto/intel/qat/qat_common/qat_crypto.c
160
inst->id = i;
drivers/crypto/intel/qat/qat_common/qat_crypto.c
161
atomic_set(&inst->refctr, 0);
drivers/crypto/intel/qat/qat_common/qat_crypto.c
162
inst->accel_dev = accel_dev;
drivers/crypto/intel/qat/qat_common/qat_crypto.c
18
void qat_crypto_put_instance(struct qat_crypto_instance *inst)
drivers/crypto/intel/qat/qat_common/qat_crypto.c
20
atomic_dec(&inst->refctr);
drivers/crypto/intel/qat/qat_common/qat_crypto.c
206
msg_size, key, NULL, 0, &inst->sym_tx);
drivers/crypto/intel/qat/qat_common/qat_crypto.c
21
adf_dev_put(inst->accel_dev);
drivers/crypto/intel/qat/qat_common/qat_crypto.c
213
msg_size, key, NULL, 0, &inst->pke_tx);
drivers/crypto/intel/qat/qat_common/qat_crypto.c
221
&inst->sym_rx);
drivers/crypto/intel/qat/qat_common/qat_crypto.c
228
&inst->pke_rx);
drivers/crypto/intel/qat/qat_common/qat_crypto.c
232
INIT_LIST_HEAD(&inst->backlog.list);
drivers/crypto/intel/qat/qat_common/qat_crypto.c
233
spin_lock_init(&inst->backlog.lock);
drivers/crypto/intel/qat/qat_common/qat_crypto.c
26
struct qat_crypto_instance *inst, *tmp;
drivers/crypto/intel/qat/qat_common/qat_crypto.c
29
list_for_each_entry_safe(inst, tmp, &accel_dev->crypto_list, list) {
drivers/crypto/intel/qat/qat_common/qat_crypto.c
30
for (i = 0; i < atomic_read(&inst->refctr); i++)
drivers/crypto/intel/qat/qat_common/qat_crypto.c
31
qat_crypto_put_instance(inst);
drivers/crypto/intel/qat/qat_common/qat_crypto.c
33
if (inst->sym_tx)
drivers/crypto/intel/qat/qat_common/qat_crypto.c
34
adf_remove_ring(inst->sym_tx);
drivers/crypto/intel/qat/qat_common/qat_crypto.c
36
if (inst->sym_rx)
drivers/crypto/intel/qat/qat_common/qat_crypto.c
37
adf_remove_ring(inst->sym_rx);
drivers/crypto/intel/qat/qat_common/qat_crypto.c
39
if (inst->pke_tx)
drivers/crypto/intel/qat/qat_common/qat_crypto.c
40
adf_remove_ring(inst->pke_tx);
drivers/crypto/intel/qat/qat_common/qat_crypto.c
42
if (inst->pke_rx)
drivers/crypto/intel/qat/qat_common/qat_crypto.c
43
adf_remove_ring(inst->pke_rx);
drivers/crypto/intel/qat/qat_common/qat_crypto.c
45
list_del(&inst->list);
drivers/crypto/intel/qat/qat_common/qat_crypto.c
46
kfree(inst);
drivers/crypto/intel/qat/qat_common/qat_crypto.c
54
struct qat_crypto_instance *inst = NULL, *tmp_inst;
drivers/crypto/intel/qat/qat_common/qat_crypto.c
93
inst = tmp_inst;
drivers/crypto/intel/qat/qat_common/qat_crypto.c
97
if (inst) {
drivers/crypto/intel/qat/qat_common/qat_hal.c
28
#define INSERT_IMMED_GPRA_CONST(inst, const_val) \
drivers/crypto/intel/qat/qat_common/qat_hal.c
29
(inst = ((inst & 0xFFFF00C03FFull) | \
drivers/crypto/intel/qat/qat_common/qat_hal.c
32
#define INSERT_IMMED_GPRB_CONST(inst, const_val) \
drivers/crypto/intel/qat/qat_common/qat_hal.c
33
(inst = ((inst & 0xFFFF00FFF00ull) | \
drivers/crypto/intel/qat/qat_common/qat_hal.c
45
static const u64 inst[] = {
drivers/crypto/intel/qat/qat_common/qat_hal.c
642
qat_hal_wr_uwords(handle, ae, 0, ARRAY_SIZE(inst),
drivers/crypto/intel/qat/qat_common/qat_hal.c
643
(u64 *)inst);
drivers/crypto/marvell/octeontx/otx_cptvf_reqmgr.c
247
static void cpt_fill_inst(union otx_cpt_inst_s *inst,
drivers/crypto/marvell/octeontx/otx_cptvf_reqmgr.c
251
inst->u[0] = 0x0;
drivers/crypto/marvell/octeontx/otx_cptvf_reqmgr.c
252
inst->s.doneint = true;
drivers/crypto/marvell/octeontx/otx_cptvf_reqmgr.c
253
inst->s.res_addr = (u64)info->comp_baddr;
drivers/crypto/marvell/octeontx/otx_cptvf_reqmgr.c
254
inst->u[2] = 0x0;
drivers/crypto/marvell/octeontx/otx_cptvf_reqmgr.c
255
inst->s.wq_ptr = 0;
drivers/crypto/marvell/octeontx/otx_cptvf_reqmgr.c
256
inst->s.ei0 = cmd->cmd.u64;
drivers/crypto/marvell/octeontx/otx_cptvf_reqmgr.c
257
inst->s.ei1 = cmd->dptr;
drivers/crypto/marvell/octeontx/otx_cptvf_reqmgr.c
258
inst->s.ei2 = cmd->rptr;
drivers/crypto/marvell/octeontx/otx_cptvf_reqmgr.c
259
inst->s.ei3 = cmd->cptr.u64;
drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c
603
lfs->ops->send_cmd((union otx2_cpt_inst_s *)req->inst, 1,
drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c
1496
union otx2_cpt_inst_s inst;
drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c
1566
otx2_cpt_fill_inst(&inst, &iq_cmd, result_baddr);
drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c
1567
lfs->ops->send_cmd(&inst, 1, &cptpf->lfs.lf[0]);
drivers/dma/lgm/lgm-dma.c
1577
d->inst = device_get_match_data(dev);
drivers/dma/lgm/lgm-dma.c
1578
if (!d->inst) {
drivers/dma/lgm/lgm-dma.c
260
const struct ldma_inst_data *inst;
drivers/dma/lgm/lgm-dma.c
352
if (d->inst->type != DMA_TYPE_TX)
drivers/dma/lgm/lgm-dma.c
381
if (d->inst->type == DMA_TYPE_MCPY)
drivers/dma/lgm/lgm-dma.c
409
if (d->inst->type == DMA_TYPE_RX)
drivers/dma/lgm/lgm-dma.c
413
if (d->inst->orrc > 0 && d->inst->orrc <= DMA_ORRC_MAX_CNT)
drivers/dma/lgm/lgm-dma.c
414
val = DMA_ORRC_EN | FIELD_PREP(DMA_ORRC_ORRCNT, d->inst->orrc);
drivers/dma/lgm/lgm-dma.c
442
if (d->inst->type != DMA_TYPE_RX && d->inst->type != DMA_TYPE_MCPY)
drivers/dma/lgm/lgm-dma.c
458
if (d->inst->type != DMA_TYPE_TX)
drivers/dma/lgm/lgm-dma.c
514
d->inst->name, readl(d->base + DMA_CTRL));
drivers/dma/lgm/lgm-dma.c
581
if (d->inst->type == DMA_TYPE_MCPY || val > DMA_MAX_CLASS)
drivers/dma/lgm/lgm-dma.c
936
if (d->inst->chan_fc)
drivers/dma/lgm/lgm-dma.c
939
if (d->inst->desc_fod)
drivers/dma/lgm/lgm-dma.c
942
if (d->inst->desc_in_sram)
drivers/dma/lgm/lgm-dma.c
945
if (d->inst->valid_desc_fetch_ack)
drivers/edac/edac_device.c
107
inst = &dev_inst[instance];
drivers/edac/edac_device.c
108
inst->ctl = dev_ctl;
drivers/edac/edac_device.c
109
inst->nr_blocks = nr_blocks;
drivers/edac/edac_device.c
111
inst->blocks = blk_p;
drivers/edac/edac_device.c
114
snprintf(inst->name, sizeof(inst->name), "%s%u", dev_name, instance);
drivers/edac/edac_device.c
119
blk->instance = inst;
drivers/edac/edac_device.c
124
instance, inst, block, blk, blk->name);
drivers/edac/edac_device.c
62
struct edac_device_instance *dev_inst, *inst;
drivers/edac/mem_repair.c
102
u8 inst = TO_MR_DEV_ATTR(attr)->instance; \
drivers/edac/mem_repair.c
105
ctx->mem_repair[inst].mem_repair_ops; \
drivers/edac/mem_repair.c
113
ret = ops->cb(ras_feat_dev->parent, ctx->mem_repair[inst].private, \
drivers/edac/mem_repair.c
138
u8 inst = TO_MR_DEV_ATTR(attr)->instance; \
drivers/edac/mem_repair.c
140
const struct edac_mem_repair_ops *ops = ctx->mem_repair[inst].mem_repair_ops; \
drivers/edac/mem_repair.c
148
ret = ops->cb(ras_feat_dev->parent, ctx->mem_repair[inst].private, data); \
drivers/edac/mem_repair.c
162
u8 inst = TO_MR_DEV_ATTR(dev_attr)->instance;
drivers/edac/mem_repair.c
163
const struct edac_mem_repair_ops *ops = ctx->mem_repair[inst].mem_repair_ops;
drivers/edac/mem_repair.c
64
u8 inst = TO_MR_DEV_ATTR(attr)->instance; \
drivers/edac/mem_repair.c
67
ctx->mem_repair[inst].mem_repair_ops; \
drivers/edac/mem_repair.c
71
ret = ops->cb(ras_feat_dev->parent, ctx->mem_repair[inst].private, \
drivers/edac/scrub.c
42
u8 inst = TO_SCRUB_DEV_ATTR(attr)->instance; \
drivers/edac/scrub.c
44
const struct edac_scrub_ops *ops = ctx->scrub[inst].scrub_ops; \
drivers/edac/scrub.c
48
ret = ops->cb(ras_feat_dev->parent, ctx->scrub[inst].private, &data); \
drivers/edac/scrub.c
67
u8 inst = TO_SCRUB_DEV_ATTR(attr)->instance; \
drivers/edac/scrub.c
69
const struct edac_scrub_ops *ops = ctx->scrub[inst].scrub_ops; \
drivers/edac/scrub.c
77
ret = ops->cb(ras_feat_dev->parent, ctx->scrub[inst].private, data); \
drivers/edac/scrub.c
93
u8 inst = TO_SCRUB_DEV_ATTR(dev_attr)->instance;
drivers/edac/scrub.c
95
const struct edac_scrub_ops *ops = ctx->scrub[inst].scrub_ops;
drivers/firmware/efi/libstub/efistub.h
58
#define efi_table_attr(inst, attr) (inst)->attr
drivers/firmware/efi/libstub/efistub.h
59
#define efi_fn_call(inst, func, ...) (inst)->func(__VA_ARGS__)
drivers/firmware/efi/libstub/efistub.h
63
#define efi_call_proto(inst, func, ...) ({ \
drivers/firmware/efi/libstub/efistub.h
64
__typeof__(inst) __inst = (inst); \
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1177
uint8_t ip, uint8_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1182
return adev->ip_versions[ip][inst] & ~0xFFU;
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1186
uint8_t ip, uint8_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1189
return adev->ip_versions[ip][inst];
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1263
#define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst)
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1264
#define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst)
drivers/gpu/drm/amd/amdgpu/amdgpu.h
146
u32 inst;
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1632
enum amdgpu_uid_type type, uint8_t inst,
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1635
enum amdgpu_uid_type type, uint8_t inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
861
u32 inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
863
struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst];
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
272
u32 inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
130
uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
287
uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
295
kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
299
hqd_base = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_MQD_BASE_ADDR);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
300
hqd_end = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_AQL_DISPATCH_ID_HI);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
303
WREG32_XCC(reg, mqd_hqd[reg - hqd_base], inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
309
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_DOORBELL_CONTROL, data);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
338
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_LO,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
340
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
342
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
344
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
346
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_PQ_WPTR_POLL_CNTL1,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
351
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_EOP_RPTR,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
355
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_ACTIVE, data);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
357
kgd_gfx_v9_release_queue(adev, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
468
uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
493
WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
496
watch_address_high, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
498
WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
501
watch_address_low, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
1018
uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
1049
uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
1075
uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
1082
uint32_t inst, unsigned int utimeout)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
141
uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
211
uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
292
uint32_t doorbell_off, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
344
uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
475
uint32_t queue_id, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
516
uint32_t queue_id, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
679
uint32_t sq_cmd, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
84
uint32_t sh_mem_bases, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
891
uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
96
unsigned int vmid, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h
48
uint32_t inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h
53
uint32_t inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h
63
uint32_t inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h
67
uint32_t inst,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
110
uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
182
uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
278
uint32_t doorbell_off, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
330
uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
461
uint32_t queue_id, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
503
uint32_t queue_id, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
591
uint32_t sq_cmd, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
634
uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
84
uint32_t sh_mem_bases, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
97
unsigned int vmid, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
106
uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
167
struct mm_struct *mm, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
263
uint32_t doorbell_off, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
315
uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
450
uint32_t pipe_id, uint32_t queue_id, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
491
uint32_t queue_id, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
576
uint32_t sq_cmd, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
747
uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
791
uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
798
uint32_t inst, unsigned int utimeout)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
82
uint32_t sh_mem_bases, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
93
unsigned int vmid, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
107
uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
165
uint32_t sq_cmd, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
322
uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
57
static int init_interrupts_v12(struct amdgpu_device *adev, uint32_t pipe_id, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
110
uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
125
acquire_queue(adev, pipe_id, queue_id, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
127
for (reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_MQD_BASE_ADDR);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
128
reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI); reg++)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
131
release_queue(adev, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
168
uint32_t sq_cmd, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
174
WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regGRBM_GFX_INDEX), gfx_index_val);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
175
WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regSQ_CMD), sq_cmd);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
184
WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regGRBM_GFX_INDEX), data);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
31
uint32_t queue, uint32_t vmid, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
325
uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
34
amdgpu_gfx_select_me_pipe_q(adev, mec, pipe, queue, vmid, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
350
WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regTCP_WATCH0_ADDR_H) +
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
352
watch_address_high, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
354
WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regTCP_WATCH0_ADDR_L) +
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
356
watch_address_low, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
37
static void unlock_srbm(struct amdgpu_device *adev, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
39
amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
44
uint32_t queue_id, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
49
lock_srbm(adev, mec, pipe, queue_id, 0, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
52
static void release_queue(struct amdgpu_device *adev, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
54
unlock_srbm(adev, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
57
static int init_interrupts_v12_1(struct amdgpu_device *adev, uint32_t pipe_id, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
65
lock_srbm(adev, mec, pipe, 0, 0, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
67
WREG32_SOC15(GC, GET_INST(GC, inst), regCPC_INT_CNTL,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
71
unlock_srbm(adev, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
118
uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
162
uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
206
uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
322
uint32_t queue_id, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
362
uint32_t queue_id, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
498
uint32_t sq_cmd, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
81
uint32_t sh_mem_bases, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
94
unsigned int vmid, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
113
uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
157
uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
230
uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
354
uint32_t queue_id, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
394
uint32_t queue_id, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
544
uint32_t sq_cmd, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
75
uint32_t sh_mem_bases, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
88
unsigned int vmid, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
102
unsigned int vmid, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1024
int *max_waves_per_cu, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1034
soc15_grbm_select(adev, 1, 0, 0, 0, GET_INST(GC, inst));
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1046
amdgpu_gfx_select_se_sh(adev, se_idx, 0, 0xffffffff, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1047
queue_map = RREG32_SOC15(GC, GET_INST(GC, inst), mmSPI_CSQ_WF_ACTIVE_STATUS);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1067
inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1071
amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1072
soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, inst));
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1104
uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1106
kgd_gfx_v9_lock_srbm(adev, 0, 0, 0, vmid, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1111
WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TBA_LO,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1113
WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TBA_HI,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1119
WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TMA_LO,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1121
WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TMA_HI,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1124
kgd_gfx_v9_unlock_srbm(adev, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1129
uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1134
kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1135
amdgpu_gfx_rlc_enter_safe_mode(adev, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1137
if (!RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE))
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1140
low = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1141
high = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1150
amdgpu_gfx_rlc_exit_safe_mode(adev, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1151
kgd_gfx_v9_release_queue(adev, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1157
static int kgd_gfx_v9_hqd_dequeue_wait(struct amdgpu_device *adev, uint32_t inst,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1163
uint32_t temp = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1177
uint32_t inst, unsigned int utimeout)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1182
kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1183
amdgpu_gfx_rlc_enter_safe_mode(adev, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1185
if (!RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE))
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1188
low = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1189
high = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1198
inst, pipe_id, queue_id);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1201
WREG32_SOC15(GC, GET_INST(GC, inst), mmSPI_COMPUTE_QUEUE_RESET, 0x1);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1203
if (!kgd_gfx_v9_hqd_dequeue_wait(adev, inst, utimeout))
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1206
pr_debug("Attempting pipe reset on XCC %i pipe id %i\n", inst, pipe_id);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1211
WREG32_SOC15(GC, GET_INST(GC, inst), mmCP_MEC_CNTL, pipe_reset_data);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1212
WREG32_SOC15(GC, GET_INST(GC, inst), mmCP_MEC_CNTL, 0);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1214
if (kgd_gfx_v9_hqd_dequeue_wait(adev, inst, utimeout))
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1219
inst, pipe_id, queue_id, !!queue_addr ? "succeeded!" : "failed!");
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1220
amdgpu_gfx_rlc_exit_safe_mode(adev, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1221
kgd_gfx_v9_release_queue(adev, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
161
uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
169
kgd_gfx_v9_lock_srbm(adev, mec, pipe, 0, 0, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
171
WREG32_SOC15(GC, GET_INST(GC, inst), mmCPC_INT_CNTL,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
175
kgd_gfx_v9_unlock_srbm(adev, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
226
uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
234
kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
238
hqd_base = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_MQD_BASE_ADDR);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
241
reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
242
WREG32_XCC(reg, mqd_hqd[reg - hqd_base], inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
248
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL, data);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
277
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_LO,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
279
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
281
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
283
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
285
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_PQ_WPTR_POLL_CNTL1,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
290
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_EOP_RPTR,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
294
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE, data);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
296
kgd_gfx_v9_release_queue(adev, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
303
uint32_t doorbell_off, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
305
struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[inst].ring;
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
312
kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
320
spin_lock(&adev->gfx.kiq[inst].ring_lock);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
347
spin_unlock(&adev->gfx.kiq[inst].ring_lock);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
348
kgd_gfx_v9_release_queue(adev, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
355
uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
370
kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
372
for (reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_MQD_BASE_ADDR);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
373
reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
376
kgd_gfx_v9_release_queue(adev, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
486
uint32_t queue_id, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
492
kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
493
act = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
498
if (low == RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE) &&
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
499
high == RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI))
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
502
kgd_gfx_v9_release_queue(adev, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
51
uint32_t queue, uint32_t vmid, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
527
uint32_t queue_id, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
537
kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
54
soc15_grbm_select(adev, mec, pipe, queue, vmid, GET_INST(GC, inst));
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
540
WREG32_FIELD15_RLC(GC, GET_INST(GC, inst), RLC_CP_SCHEDULERS, scheduler1, 0);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
557
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_DEQUEUE_REQUEST, type);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
561
temp = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
566
kgd_gfx_v9_release_queue(adev, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
57
static void kgd_gfx_v9_unlock_srbm(struct amdgpu_device *adev, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
572
kgd_gfx_v9_release_queue(adev, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
59
soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, inst));
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
629
uint32_t sq_cmd, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
635
WREG32_SOC15_RLC_SHADOW(GC, GET_INST(GC, inst), mmGRBM_GFX_INDEX, gfx_index_val);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
636
WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_CMD, sq_cmd);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
64
uint32_t queue_id, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
645
WREG32_SOC15_RLC_SHADOW(GC, GET_INST(GC, inst), mmGRBM_GFX_INDEX, data);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
69
kgd_gfx_v9_lock_srbm(adev, mec, pipe, queue_id, 0, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
81
void kgd_gfx_v9_release_queue(struct amdgpu_device *adev, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
824
uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
83
kgd_gfx_v9_unlock_srbm(adev, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
90
uint32_t sh_mem_bases, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
906
uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
909
*wait_times = RREG32_SOC15_RLC(GC, GET_INST(GC, inst),
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
92
kgd_gfx_v9_lock_srbm(adev, 0, 0, 0, vmid, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
94
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_CONFIG, sh_mem_config);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
95
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_BASES, sh_mem_bases);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
951
struct kfd_cu_occupancy *queue_cnt, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
964
soc15_grbm_select(adev, 1, pipe_idx, queue_slot, 0, GET_INST(GC, inst));
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
965
reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
971
(RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL) &
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
98
kgd_gfx_v9_unlock_srbm(adev, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
109
uint32_t inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
113
uint32_t inst,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
26
uint32_t sh_mem_bases, uint32_t inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
28
unsigned int vmid, uint32_t inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
30
uint32_t inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
34
struct mm_struct *mm, uint32_t inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
37
uint32_t doorbell_off, uint32_t inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
40
uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
43
uint32_t queue_id, uint32_t inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
47
uint32_t queue_id, uint32_t inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
50
uint32_t sq_cmd, uint32_t inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
57
int *max_waves_per_cu, uint32_t inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
60
uint32_t inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
62
uint32_t queue_id, uint32_t inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
65
void kgd_gfx_v9_release_queue(struct amdgpu_device *adev, uint32_t inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
94
uint32_t inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
99
uint32_t inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
2185
amdgpu_debugfs_vcn_fwlog_init(adev, i, &adev->vcn.inst[i]);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
6937
enum amdgpu_uid_type type, uint8_t inst,
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
6949
if (inst >= AMDGPU_UID_INST_MAX) {
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
6951
inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
6955
if (uid_info->uid[type][inst] != 0) {
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
6959
uid_info->uid[type][inst], type, inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
6962
uid_info->uid[type][inst] = uid;
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
6966
enum amdgpu_uid_type type, uint8_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
6977
if (inst >= AMDGPU_UID_INST_MAX) {
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
6979
inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
6983
return uid_info->uid[type][inst];
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
1140
uint16_t hw_id, uint8_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
1149
harvest = ((1 << inst) & adev->vcn.inst_mask) == 0;
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
1159
harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0;
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
1162
harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0;
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
1179
uint8_t inst;
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
1195
inst = ip->instance_number;
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
1197
if (amdgpu_discovery_validate_ip(adev, inst, hw_id) ||
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
1499
uint8_t inst;
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
1541
inst = ip->instance_number;
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
1543
if (amdgpu_discovery_validate_ip(adev, inst, hw_id))
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
1564
adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config =
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
1950
adev->vcn.inst[v].vcn_codec_disable_mask =
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
765
uint8_t inst;
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
783
inst = ip->number_instance;
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
785
if (amdgpu_discovery_validate_ip(adev, inst, hw_id))
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
792
if (inst == 0) {
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
844
u8 inst = harvest_info->list[i].number_instance;
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
849
if (inst >= 32) {
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
852
inst, hw_id);
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
859
adev->vcn.harvest_config |= BIT(inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
860
adev->jpeg.harvest_config |= BIT(inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
862
adev->vcn.inst_mask &= ~BIT(inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
863
adev->jpeg.inst_mask &= ~BIT(inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
869
umc_harvest_config |= BIT_ULL(inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
873
adev->gfx.xcc_mask &= ~BIT(inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
876
adev->sdma.sdma_mask &= ~BIT(inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
880
adev->isp.harvest_config |= ~BIT(inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
420
ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index;
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
421
ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index;
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
517
int num_xcc, inc, inst = 0;
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
539
i = inst;
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
787
uint32_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
789
struct amdgpu_ring *ring = &adev->gfx.kiq[inst].ring;
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
790
struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst];
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
812
inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
817
inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
821
inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
833
spin_lock(&adev->gfx.kiq[inst].ring_lock);
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
836
spin_unlock(&adev->gfx.kiq[inst].ring_lock);
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
849
spin_unlock(&adev->gfx.kiq[inst].ring_lock);
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
854
spin_unlock(&adev->gfx.kiq[inst].ring_lock);
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
160
uint32_t inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
449
uint32_t inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
53
#define IMU_RLC_RAM_GOLDEN_VALUE(ip, inst, reg, data, addr_mask) \
drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
54
{ ip##_HWIP, inst, reg##_BASE_IDX, reg, data, addr_mask }
drivers/gpu/drm/amd/amdgpu/amdgpu_ip.c
29
int8_t inst)
drivers/gpu/drm/amd/amdgpu/amdgpu_ip.c
38
dev_inst = adev->ip_map.dev_inst[block][inst];
drivers/gpu/drm/amd/amdgpu/amdgpu_ip.c
43
dev_inst = inst;
drivers/gpu/drm/amd/amdgpu/amdgpu_ip.h
92
int8_t inst);
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
121
fences += amdgpu_fence_count_emitted(&adev->jpeg.inst[i].ring_dec[j]);
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
167
WREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe], 0xCAFEDEAD);
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
169
RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
176
tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
253
tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
299
!adev->jpeg.inst[i].ras_poison_irq.funcs)
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
302
r = amdgpu_irq_get(adev, &adev->jpeg.inst[i].ras_poison_irq, 0);
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
345
.mc_addr = adev->jpeg.inst[inst_idx].dpg_sram_gpu_addr,
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
346
.ucode_size = ((uintptr_t)adev->jpeg.inst[inst_idx].dpg_sram_curr_addr -
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
347
(uintptr_t)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr),
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
373
ring = &adev->jpeg.inst[i].ring_dec[j];
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
396
ring = &adev->jpeg.inst[i].ring_dec[j];
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
58
&adev->jpeg.inst[i].dpg_sram_bo,
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
59
&adev->jpeg.inst[i].dpg_sram_gpu_addr,
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
60
&adev->jpeg.inst[i].dpg_sram_cpu_addr);
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
81
&adev->jpeg.inst[i].dpg_sram_bo,
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
82
&adev->jpeg.inst[i].dpg_sram_gpu_addr,
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
83
(void **)&adev->jpeg.inst[i].dpg_sram_cpu_addr);
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
86
amdgpu_ring_fini(&adev->jpeg.inst[i].ring_dec[j]);
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
133
struct amdgpu_jpeg_inst inst[AMDGPU_MAX_JPEG_INSTANCES];
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
55
*adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = \
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
57
*adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = \
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
98
*adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = offset; \
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
99
*adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = value; \
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
499
if (adev->uvd.inst[i].ring.sched.ready &&
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
500
!adev->uvd.inst[i].ring.no_user_submission)
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
522
if (adev->uvd.inst[i].ring_enc[j].sched.ready &&
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
523
!adev->uvd.inst[i].ring_enc[j].no_user_submission)
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
535
if (adev->vcn.inst[i].ring_dec.sched.ready &&
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
536
!adev->vcn.inst[i].ring_dec.no_user_submission)
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
548
for (j = 0; j < adev->vcn.inst[i].num_enc_rings; j++)
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
549
if (adev->vcn.inst[i].ring_enc[j].sched.ready &&
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
550
!adev->vcn.inst[i].ring_enc[j].no_user_submission)
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
565
if (adev->jpeg.inst[i].ring_dec[j].sched.ready &&
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
566
!adev->jpeg.inst[i].ring_dec[j].no_user_submission)
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
383
#define AMDGPU_RAS_REG_ENTRY(ip, inst, reg_lo, reg_hi) \
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
384
ip##_HWIP, inst, reg_lo##_BASE_IDX, reg_lo, reg_hi##_BASE_IDX, reg_hi
drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c
936
uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, uint32_t inst,
drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c
957
inst, reg_name, (uint32_t)expected_value,
drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h
159
uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, uint32_t inst,
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
1300
fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring);
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
1302
fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]);
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
337
&adev->uvd.inst[j].vcpu_bo,
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
338
&adev->uvd.inst[j].gpu_addr,
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
339
&adev->uvd.inst[j].cpu_addr);
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
385
kvfree(adev->uvd.inst[j].saved_bo);
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
387
amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo,
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
388
&adev->uvd.inst[j].gpu_addr,
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
389
(void **)&adev->uvd.inst[j].cpu_addr);
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
391
amdgpu_ring_fini(&adev->uvd.inst[j].ring);
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
394
amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
412
if (ring == &adev->uvd.inst[0].ring) {
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
448
if (adev->uvd.inst[j].vcpu_bo == NULL)
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
451
size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo);
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
452
ptr = adev->uvd.inst[j].cpu_addr;
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
454
adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL);
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
455
if (!adev->uvd.inst[j].saved_bo)
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
461
memset(adev->uvd.inst[j].saved_bo, 0, size);
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
463
memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
490
if (adev->uvd.inst[i].vcpu_bo == NULL)
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
493
size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo);
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
494
ptr = adev->uvd.inst[i].cpu_addr;
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
496
if (adev->uvd.inst[i].saved_bo != NULL) {
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
498
memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size);
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
501
kvfree(adev->uvd.inst[i].saved_bo);
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
502
adev->uvd.inst[i].saved_bo = NULL;
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
511
memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset,
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
520
amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring, NULL);
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
528
struct amdgpu_ring *ring = &adev->uvd.inst[0].ring;
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
556
struct amdgpu_bo *vcpu_bo = adev->uvd.inst[0].vcpu_bo;
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
996
(start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) {
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
62
struct amdgpu_uvd_inst inst[AMDGPU_MAX_UVD_INSTANCES];
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
1006
if (adev->vcn.inst[ring->me].using_unified_queue)
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
1020
if (adev->vcn.inst[ring->me].using_unified_queue)
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
1042
if (adev->vcn.inst[ring->me].using_unified_queue)
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
107
adev->vcn.inst[i].adev = adev;
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
108
adev->vcn.inst[i].inst = i;
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
112
r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw,
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
1144
hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data;
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
1152
adev->firmware.ucode[idx].fw = adev->vcn.inst[i].fw;
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
116
amdgpu_ucode_release(&adev->vcn.inst[i].fw);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
118
if (!adev->vcn.inst[0].fw) {
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
119
r = amdgpu_ucode_request(adev, &adev->vcn.inst[0].fw,
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
123
amdgpu_ucode_release(&adev->vcn.inst[0].fw);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
127
adev->vcn.inst[i].fw = adev->vcn.inst[0].fw;
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
1304
!adev->vcn.inst[i].ras_poison_irq.funcs)
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
1307
r = amdgpu_irq_get(adev, &adev->vcn.inst[i].ras_poison_irq, 0);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
1352
.mc_addr = adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
1353
.ucode_size = ((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
1354
(uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr),
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
141
mutex_init(&adev->vcn.inst[i].vcn1_jpeg1_workaround);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
1416
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
142
mutex_init(&adev->vcn.inst[i].vcn_pg_lock);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
143
mutex_init(&adev->vcn.inst[i].engine_reset_mutex);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
1437
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
144
atomic_set(&adev->vcn.inst[i].total_submission_cnt, 0);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
145
INIT_DELAYED_WORK(&adev->vcn.inst[i].idle_work, amdgpu_vcn_idle_work_handler);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
1457
if (adev->vcn.num_vcn_inst <= 1 || !adev->vcn.inst[0].using_unified_queue)
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
146
atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
1480
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
149
adev->vcn.inst[i].indirect_sram = true;
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
1504
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me];
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
1507
if (adev->vcn.inst[ring->me].using_unified_queue)
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
163
adev->vcn.inst[i].indirect_sram = false;
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
170
adev->vcn.inst[i].using_unified_queue =
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
173
hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data;
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
174
adev->vcn.inst[i].fw_version = le32_to_cpu(hdr->ucode_version);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
228
&adev->vcn.inst[i].vcpu_bo,
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
229
&adev->vcn.inst[i].gpu_addr,
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
230
&adev->vcn.inst[i].cpu_addr);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
236
adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr +
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
238
adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr +
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
241
adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size;
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
244
adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
245
adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
246
adev->vcn.inst[i].fw_shared.log_offset = log_offset;
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
249
if (adev->vcn.inst[i].indirect_sram) {
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
253
&adev->vcn.inst[i].dpg_sram_bo,
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
254
&adev->vcn.inst[i].dpg_sram_gpu_addr,
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
255
&adev->vcn.inst[i].dpg_sram_cpu_addr);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
273
&adev->vcn.inst[i].dpg_sram_bo,
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
274
&adev->vcn.inst[i].dpg_sram_gpu_addr,
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
275
(void **)&adev->vcn.inst[i].dpg_sram_cpu_addr);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
277
kvfree(adev->vcn.inst[i].saved_bo);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
279
amdgpu_bo_free_kernel(&adev->vcn.inst[i].vcpu_bo,
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
280
&adev->vcn.inst[i].gpu_addr,
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
281
(void **)&adev->vcn.inst[i].cpu_addr);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
283
amdgpu_ring_fini(&adev->vcn.inst[i].ring_dec);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
285
for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j)
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
286
amdgpu_ring_fini(&adev->vcn.inst[i].ring_enc[j]);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
289
amdgpu_ucode_release(&adev->vcn.inst[i].fw);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
291
amdgpu_ucode_release(&adev->vcn.inst[0].fw);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
292
adev->vcn.inst[i].fw = NULL;
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
298
mutex_destroy(&adev->vcn.inst[i].vcn_pg_lock);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
299
mutex_destroy(&adev->vcn.inst[i].vcn1_jpeg1_workaround);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
305
int vcn_config = adev->vcn.inst[vcn_instance].vcn_config;
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
325
if (adev->vcn.inst[i].vcpu_bo == NULL)
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
328
size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
329
ptr = adev->vcn.inst[i].cpu_addr;
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
331
adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
332
if (!adev->vcn.inst[i].saved_bo)
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
336
memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
379
if (adev->vcn.inst[i].vcpu_bo == NULL)
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
382
size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
383
ptr = adev->vcn.inst[i].cpu_addr;
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
385
if (adev->vcn.inst[i].saved_bo != NULL) {
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
387
memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
390
kvfree(adev->vcn.inst[i].saved_bo);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
391
adev->vcn.inst[i].saved_bo = NULL;
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
396
hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data;
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
400
memcpy_toio(adev->vcn.inst[i].cpu_addr,
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
401
adev->vcn.inst[i].fw->data + offset,
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
441
if (adev->vcn.inst[i].cur_state != AMD_PG_STATE_GATE) {
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
468
unsigned int i = vcn_inst->inst, j;
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
473
for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j)
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
478
!adev->vcn.inst[i].using_unified_queue) {
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
487
adev->vcn.inst[i].pause_dpg_mode(vcn_inst, &new_state);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
507
struct amdgpu_vcn_inst *vcn_inst = &adev->vcn.inst[ring->me];
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
550
!adev->vcn.inst[ring->me].using_unified_queue)
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
551
atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
553
atomic_dec(&ring->adev->vcn.inst[ring->me].total_submission_cnt);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
555
schedule_delayed_work(&ring->adev->vcn.inst[ring->me].idle_work,
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
570
WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
574
amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.scratch9, 0));
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
578
tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
639
ib->ptr[0] = PACKET0(adev->vcn.inst[ring->me].internal.data0, 0);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
641
ib->ptr[2] = PACKET0(adev->vcn.inst[ring->me].internal.data1, 0);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
643
ib->ptr[4] = PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
646
ib->ptr[i] = PACKET0(adev->vcn.inst[ring->me].internal.nop, 0);
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
809
if (adev->vcn.inst[ring->me].using_unified_queue)
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
822
if (adev->vcn.inst[ring->me].using_unified_queue) {
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
841
if (adev->vcn.inst[ring->me].using_unified_queue)
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
939
if (adev->vcn.inst[ring->me].using_unified_queue)
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
953
if (adev->vcn.inst[ring->me].using_unified_queue)
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
975
if (adev->vcn.inst[ring->me].using_unified_queue)
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
156
*adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
158
*adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
209
*adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
211
*adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
302
int inst;
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
348
struct amdgpu_vcn_inst inst[AMDGPU_MAX_VCN_INSTANCES];
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h
35
uint32_t (*get_reg_offset)(struct amdgpu_vpe *vpe, uint32_t inst, uint32_t offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h
98
#define vpe_get_reg_offset(vpe, inst, offset) \
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h
99
((vpe)->funcs->get_reg_offset ? (vpe)->funcs->get_reg_offset((vpe), (inst), (offset)) : 0)
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
689
int inst = 0, i, j, r, n;
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
709
xgmi_regs->inst_header.instance = inst++;
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
763
int inst = 0, i, j, r, n;
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
783
wafl_regs->inst_header.instance = inst++;
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
876
int inst = 0, i, n, r, arr_size;
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
908
usr_regs->inst_header.instance = inst++;
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
4716
uint32_t inst;
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
4728
inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
4731
ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
4741
inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
4744
ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
1567
uint32_t inst;
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
1579
inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
1582
ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
1592
inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
1595
ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
1366
uint32_t inst;
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
1378
inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
1381
ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
1391
inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
1394
ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
2190
uint32_t inst;
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
2202
inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
2205
ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
7021
gfx_v9_0_ras_fields[i].inst != reg->inst)
drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c
838
gfx_v9_4_ras_fields[i].inst != reg->inst)
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
1474
gfx_v9_4_2_ras_fields[i].inst != reg->inst)
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
1013
uint32_t *ptr, num_xcc, inst;
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
1027
inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
1030
ptr = kcalloc(reg_count * inst * num_xcc, sizeof(uint32_t), GFP_KERNEL);
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
1671
int inst, struct amdgpu_ring *ring, unsigned int vmid)
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
1675
reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL);
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
1686
WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data);
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
1688
WREG32_SOC15(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data);
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
1701
int i, inst;
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
1711
inst = adev->ip_map.logical_to_dev_inst ?
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
1715
reg = adev->reg_offset[entry->hwip][inst][entry->segment] +
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
334
bool all_hub, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
326
bool all_hub, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
347
bool all_hub, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
246
uint8_t vmid, uint8_t inst,
drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
251
if (inst/4)
drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
252
index = 0xA + inst%4;
drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
254
index = 0x2 + inst%4;
drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
333
u32 inst;
drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
340
inst = 0;
drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
342
inst = vmhub;
drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
347
if (((adev->gfx.kiq[inst].ring.sched.ready ||
drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
348
adev->mes.ring[MES_PIPE_INST(inst, 0)].sched.ready) &&
drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
357
1 << vmid, inst);
drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
378
bool all_hub, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
386
input.xcc_id = inst;
drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
391
if (!amdgpu_gfx_is_master_xcc(adev, inst))
drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
414
valid = gmc_v12_1_get_vmid_pasid_mapping_info(adev, vmid, inst,
drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
425
gmc_v12_1_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(inst),
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
430
bool all_hub, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
621
bool all_hub, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
780
u32 j, inv_req, tmp, sem, req, ack, inst;
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
793
inst = 0;
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
795
inst = vmhub;
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
800
if (adev->gfx.kiq[inst].ring.sched.ready &&
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
806
1 << vmid, inst);
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
825
tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, GET_INST(GC, inst));
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
827
tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, GET_INST(GC, inst));
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
838
WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, GET_INST(GC, inst));
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
840
WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, GET_INST(GC, inst));
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
853
tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, GET_INST(GC, inst));
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
855
tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, GET_INST(GC, inst));
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
868
WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, GET_INST(GC, inst));
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
870
WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, GET_INST(GC, inst));
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
894
bool all_hub, uint32_t inst)
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
447
amdgpu_fence_process(adev->jpeg.inst->ring_dec);
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
491
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->jpeg.inst->irq);
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
495
ring = adev->jpeg.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
498
r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq,
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
503
adev->jpeg.internal.jpeg_pitch[0] = adev->jpeg.inst->external.jpeg_pitch[0] =
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
520
amdgpu_ring_fini(adev->jpeg.inst->ring_dec);
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
533
struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
591
adev->jpeg.inst->ring_dec->funcs = &jpeg_v1_0_decode_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
601
adev->jpeg.inst->irq.funcs = &jpeg_v1_0_irq_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
607
bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
610
mutex_lock(&adev->vcn.inst[0].vcn1_jpeg1_workaround);
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
612
if (amdgpu_fence_wait_empty(&adev->vcn.inst->ring_dec))
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
615
for (cnt = 0; cnt < adev->vcn.inst[0].num_enc_rings; cnt++) {
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
616
if (amdgpu_fence_wait_empty(&adev->vcn.inst->ring_enc[cnt]))
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
103
ring = adev->jpeg.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
108
r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq,
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
114
adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
121
amdgpu_get_soft_full_reset_mask(adev->jpeg.inst[0].ring_dec);
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
161
struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
337
struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
758
amdgpu_fence_process(adev->jpeg.inst->ring_dec);
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
836
adev->jpeg.inst->ring_dec->funcs = &jpeg_v2_0_dec_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
846
adev->jpeg.inst->irq.num_types = 1;
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
847
adev->jpeg.inst->irq.funcs = &jpeg_v2_0_irq_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
91
VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
116
VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst[i].irq);
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
122
VCN_2_6__SRCID_DJPEG0_POISON, &adev->jpeg.inst[i].ras_poison_irq);
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
128
VCN_2_6__SRCID_EJPEG0_POISON, &adev->jpeg.inst[i].ras_poison_irq);
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
145
ring = adev->jpeg.inst[i].ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
153
r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst[i].irq,
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
159
adev->jpeg.inst[i].external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_PITCH);
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
171
amdgpu_get_soft_full_reset_mask(adev->jpeg.inst[0].ring_dec);
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
218
ring = adev->jpeg.inst[i].ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
253
amdgpu_irq_put(adev, &adev->jpeg.inst[i].ras_poison_irq, 0);
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
299
static void jpeg_v2_5_disable_clock_gating(struct amdgpu_device *adev, int inst)
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
303
data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
311
WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data);
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
313
data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE);
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
318
WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data);
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
320
data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
325
WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data);
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
328
static void jpeg_v2_5_enable_clock_gating(struct amdgpu_device *adev, int inst)
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
332
data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE);
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
338
WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data);
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
343
struct amdgpu_ring *ring = adev->jpeg.inst[i].ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
638
amdgpu_fence_process(adev->jpeg.inst[ip_instance].ring_dec);
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
765
adev->jpeg.inst[i].ring_dec->funcs = &jpeg_v2_5_dec_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
767
adev->jpeg.inst[i].ring_dec->funcs = &jpeg_v2_6_dec_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
768
adev->jpeg.inst[i].ring_dec->me = i;
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
790
adev->jpeg.inst[i].irq.num_types = 1;
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
791
adev->jpeg.inst[i].irq.funcs = &jpeg_v2_5_irq_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
793
adev->jpeg.inst[i].ras_poison_irq.num_types = 1;
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
794
adev->jpeg.inst[i].ras_poison_irq.funcs = &jpeg_v2_6_ras_irq_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
841
uint32_t inst = 0, sub = 0, poison_stat = 0;
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
843
for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++)
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
846
jpeg_v2_6_query_poison_by_instance(adev, inst, sub);
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
106
VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
118
ring = adev->jpeg.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
123
r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
129
adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
136
amdgpu_get_soft_full_reset_mask(adev->jpeg.inst[0].ring_dec);
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
176
struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
353
struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
550
amdgpu_fence_process(adev->jpeg.inst->ring_dec);
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
628
adev->jpeg.inst->ring_dec->funcs = &jpeg_v3_0_dec_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
638
adev->jpeg.inst->irq.num_types = 1;
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
639
adev->jpeg.inst->irq.funcs = &jpeg_v3_0_irq_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
100
VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
106
VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
112
VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
124
ring = adev->jpeg.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
130
r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
136
adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
147
amdgpu_get_soft_full_reset_mask(adev->jpeg.inst[0].ring_dec);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
186
struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
231
amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
390
struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
472
ring = adev->jpeg.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
715
amdgpu_fence_process(adev->jpeg.inst->ring_dec);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
793
adev->jpeg.inst->ring_dec->funcs = &jpeg_v4_0_dec_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
807
adev->jpeg.inst->irq.num_types = 1;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
808
adev->jpeg.inst->irq.funcs = &jpeg_v4_0_irq_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
810
adev->jpeg.inst->ras_poison_irq.num_types = 1;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
811
adev->jpeg.inst->ras_poison_irq.funcs = &jpeg_v4_0_ras_irq_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
849
uint32_t inst = 0, sub = 0, poison_stat = 0;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
851
for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++)
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
854
jpeg_v4_0_query_poison_by_instance(adev, inst, sub);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
1109
uint32_t i, inst;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
1114
for (inst = 0; inst < adev->jpeg.num_jpeg_inst; ++inst)
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
1115
if (adev->jpeg.inst[inst].aid_id == i)
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
1118
if (inst >= adev->jpeg.num_jpeg_inst) {
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
1127
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[0]);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
1130
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[1]);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
1133
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[2]);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
1136
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[3]);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
1139
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[4]);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
1142
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[5]);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
1145
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[6]);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
1148
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[7]);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
1189
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me];
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
1258
adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v4_0_3_dec_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
1259
adev->jpeg.inst[i].ring_dec[j].me = i;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
1260
adev->jpeg.inst[i].ring_dec[j].pipe = j;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
1263
adev->jpeg.inst[i].aid_id =
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
1283
adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
1285
adev->jpeg.inst->irq.funcs = &jpeg_v4_0_3_irq_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
1287
adev->jpeg.inst->ras_poison_irq.num_types = 1;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
1288
adev->jpeg.inst->ras_poison_irq.funcs = &jpeg_v4_0_3_ras_irq_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
1412
uint32_t inst = 0, sub = 0, poison_stat = 0;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
1414
for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++)
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
1417
jpeg_v4_0_3_query_poison_by_instance(adev, inst, sub);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
147
amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
1503
adev->jpeg.inst->ras_poison_irq.funcs) {
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
1504
r = amdgpu_irq_get(adev, &adev->jpeg.inst->ras_poison_irq, 0);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
154
VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
160
VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
176
ring = &adev->jpeg.inst[i].ring_dec[j];
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
178
ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
193
sprintf(ring->name, "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
194
r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
201
adev->jpeg.inst[i].external.jpeg_pitch[j] =
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
220
amdgpu_get_soft_full_reset_mask(adev->jpeg.inst[0].ring_dec);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
288
ring = &adev->jpeg.inst[i].ring_dec[j];
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
383
ring = &adev->jpeg.inst[i].ring_dec[j];
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
399
ring = adev->jpeg.inst[i].ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
406
adev->jpeg.inst[i].aid_id);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
409
ring = &adev->jpeg.inst[i].ring_dec[j];
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
448
amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
543
static void jpeg_v4_0_3_start_inst(struct amdgpu_device *adev, int inst)
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
545
int jpeg_inst = GET_INST(JPEG, inst);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
559
jpeg_v4_0_3_disable_clock_gating(adev, inst);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
627
ring = &adev->jpeg.inst[i].ring_dec[j];
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
635
static void jpeg_v4_0_3_stop_inst(struct amdgpu_device *adev, int inst)
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
637
int jpeg_inst = GET_INST(JPEG, inst);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
643
jpeg_v4_0_3_enable_clock_gating(adev, inst);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
130
VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst[i].irq);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
136
VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst[i].irq);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
142
VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst[i].irq);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
159
ring = adev->jpeg.inst[i].ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
164
r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst[i].irq,
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
170
adev->jpeg.inst[i].external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, i, regUVD_JPEG_PITCH);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
178
amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
231
ring = adev->jpeg.inst[i].ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
307
static void jpeg_v4_0_5_disable_clock_gating(struct amdgpu_device *adev, int inst)
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
311
data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
321
WREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL, data);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
323
data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
328
WREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE, data);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
331
static void jpeg_v4_0_5_enable_clock_gating(struct amdgpu_device *adev, int inst)
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
335
data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
345
WREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL, data);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
347
data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
352
WREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE, data);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
374
static int jpeg_v4_0_5_disable_static_power_gating(struct amdgpu_device *adev, int inst)
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
377
WREG32(SOC15_REG_OFFSET(JPEG, inst, regUVD_IPX_DLDO_CONFIG),
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
379
SOC15_WAIT_ON_RREG(JPEG, inst, regUVD_IPX_DLDO_STATUS,
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
384
WREG32_P(SOC15_REG_OFFSET(JPEG, inst, regUVD_JPEG_POWER_STATUS), 0,
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
388
WREG32_P(SOC15_REG_OFFSET(JPEG, inst, regUVD_JPEG_POWER_STATUS), 0,
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
394
static int jpeg_v4_0_5_enable_static_power_gating(struct amdgpu_device *adev, int inst)
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
397
WREG32_P(SOC15_REG_OFFSET(JPEG, inst, regUVD_JPEG_POWER_STATUS),
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
402
WREG32(SOC15_REG_OFFSET(JPEG, inst, regUVD_IPX_DLDO_CONFIG),
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
404
SOC15_WAIT_ON_RREG(JPEG, inst, regUVD_IPX_DLDO_STATUS,
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
423
struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
445
adev->jpeg.inst[inst_idx].dpg_sram_curr_addr =
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
446
(uint32_t *)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
513
ring = adev->jpeg.inst[i].ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
756
amdgpu_fence_process(adev->jpeg.inst[ip_instance].ring_dec);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
844
adev->jpeg.inst[i].ring_dec->funcs = &jpeg_v4_0_5_dec_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
845
adev->jpeg.inst[i].ring_dec->me = i;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
861
adev->jpeg.inst[i].irq.num_types = 1;
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
862
adev->jpeg.inst[i].irq.funcs = &jpeg_v4_0_5_irq_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
105
ring = adev->jpeg.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
111
r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
117
adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
124
amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
163
struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
343
struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
354
adev->jpeg.inst[inst_idx].dpg_sram_curr_addr =
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
355
(uint32_t *)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
427
struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
636
amdgpu_fence_process(adev->jpeg.inst->ring_dec);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
714
adev->jpeg.inst->ring_dec->funcs = &jpeg_v5_0_0_dec_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
724
adev->jpeg.inst->irq.num_types = 1;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
725
adev->jpeg.inst->irq.funcs = &jpeg_v5_0_0_irq_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
93
VCN_5_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
1087
adev->jpeg.inst->ras_poison_irq.funcs) {
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
1088
r = amdgpu_irq_get(adev, &adev->jpeg.inst->ras_poison_irq, 0);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
145
amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
151
VCN_5_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
157
VCN_5_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
173
ring = &adev->jpeg.inst[i].ring_dec[j];
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
175
ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
185
sprintf(ring->name, "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
186
r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
193
adev->jpeg.inst[i].external.jpeg_pitch[j] =
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
212
amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
262
ring = &adev->jpeg.inst[i].ring_dec[j];
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
276
ring = adev->jpeg.inst[i].ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
280
adev->jpeg.inst[i].aid_id);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
283
ring = &adev->jpeg.inst[i].ring_dec[j];
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
319
amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
486
ring = &adev->jpeg.inst[i].ring_dec[j];
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
577
ring = &adev->jpeg.inst[i].ring_dec[j];
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
762
u32 i, inst;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
767
for (inst = 0; inst < adev->jpeg.num_jpeg_inst; ++inst)
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
768
if (adev->jpeg.inst[inst].aid_id == i)
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
771
if (inst >= adev->jpeg.num_jpeg_inst) {
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
780
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[0]);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
783
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[1]);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
786
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[2]);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
789
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[3]);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
792
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[4]);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
795
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[5]);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
798
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[6]);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
801
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[7]);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
804
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[8]);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
807
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[9]);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
848
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me];
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
923
adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v5_0_1_dec_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
924
adev->jpeg.inst[i].ring_dec[j].me = i;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
925
adev->jpeg.inst[i].ring_dec[j].pipe = j;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
928
adev->jpeg.inst[i].aid_id =
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
948
adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
950
adev->jpeg.inst->irq.funcs = &jpeg_v5_0_1_irq_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
952
adev->jpeg.inst->ras_poison_irq.num_types = 1;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
953
adev->jpeg.inst->ras_poison_irq.funcs = &jpeg_v5_0_1_ras_irq_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
992
uint32_t inst = 0, sub = 0, poison_stat = 0;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
994
for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++)
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
997
jpeg_v5_0_1_query_poison_by_instance(adev, inst, sub);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
142
amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
159
ring = &adev->jpeg.inst[i].ring_dec[j];
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
161
ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
165
sprintf(ring->name, "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
166
r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
173
adev->jpeg.inst[i].external.jpeg_pitch[j] =
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
184
amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
231
ring = adev->jpeg.inst[i].ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
241
adev->jpeg.inst[i].aid_id);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
244
ring = &adev->jpeg.inst[i].ring_dec[j];
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
420
ring = &adev->jpeg.inst[i].ring_dec[j];
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
590
u32 i, inst;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
595
for (inst = 0; inst < adev->jpeg.num_jpeg_inst; ++inst)
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
596
if (adev->jpeg.inst[inst].aid_id == i)
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
599
if (inst >= adev->jpeg.num_jpeg_inst) {
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
608
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[0]);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
611
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[1]);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
614
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[2]);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
617
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[3]);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
620
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[4]);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
623
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[5]);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
626
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[6]);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
629
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[7]);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
632
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[8]);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
635
amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[9]);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
741
adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v5_0_2_dec_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
742
adev->jpeg.inst[i].ring_dec[j].me = i;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
743
adev->jpeg.inst[i].ring_dec[j].pipe = j;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
746
adev->jpeg.inst[i].aid_id =
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
761
adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c
763
adev->jpeg.inst->irq.funcs = &jpeg_v5_0_2_irq_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c
102
adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c
106
amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c
146
struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c
326
struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c
337
adev->jpeg.inst[inst_idx].dpg_sram_curr_addr =
drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c
338
(uint32_t *)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c
410
struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c
619
amdgpu_fence_process(adev->jpeg.inst->ring_dec);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c
695
adev->jpeg.inst->ring_dec->funcs = &jpeg_v5_3_0_dec_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c
705
adev->jpeg.inst->irq.num_types = 1;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c
706
adev->jpeg.inst->irq.funcs = &jpeg_v5_3_0_irq_funcs;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c
78
VCN_5_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c
90
ring = adev->jpeg.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c
96
r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1000
memcpy(adev->mes.ucode_fw_ptr[inst], fw_data, fw_size);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1002
amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[inst]);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1003
amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[inst]);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1012
int r, inst = MES_PIPE_INST(xcc_id, pipe);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1027
&adev->mes.data_fw_obj[inst],
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1028
&adev->mes.data_fw_gpu_addr[inst],
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1029
(void **)&adev->mes.data_fw_ptr[inst]);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1035
memcpy(adev->mes.data_fw_ptr[inst], fw_data, fw_size);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1037
amdgpu_bo_kunmap(adev->mes.data_fw_obj[inst]);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1038
amdgpu_bo_unreserve(adev->mes.data_fw_obj[inst]);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1047
int inst = MES_PIPE_INST(xcc_id, pipe);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1049
amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[inst],
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1050
&adev->mes.data_fw_gpu_addr[inst],
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1051
(void **)&adev->mes.data_fw_ptr[inst]);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1053
amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[inst],
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1054
&adev->mes.ucode_fw_gpu_addr[inst],
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1055
(void **)&adev->mes.ucode_fw_ptr[inst]);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1140
int r, inst = MES_PIPE_INST(xcc_id, pipe);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1166
lower_32_bits(adev->mes.ucode_fw_gpu_addr[inst]));
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1168
upper_32_bits(adev->mes.ucode_fw_gpu_addr[inst]));
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1175
lower_32_bits(adev->mes.data_fw_gpu_addr[inst]));
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1177
upper_32_bits(adev->mes.data_fw_gpu_addr[inst]));
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1205
int r, inst = MES_PIPE_INST(xcc_id, pipe);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1210
&adev->mes.eop_gpu_obj[inst],
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1211
&adev->mes.eop_gpu_addr[inst],
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1219
adev->mes.eop_gpu_obj[inst]->tbo.base.size);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1221
amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[inst]);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1222
amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[inst]);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1231
int r, inst = MES_PIPE_INST(xcc_id, pipe);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1235
&adev->mes.shared_cmd_buf_obj[inst],
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1236
&adev->mes.shared_cmd_buf_gpu_addr[inst],
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1423
int r, inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1434
kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[inst]);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1485
int inst = MES_PIPE_INST(xcc_id, pipe);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1487
ring = &adev->mes.ring[inst];
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1499
ring->eop_gpu_addr = adev->mes.eop_gpu_addr[inst];
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1523
int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_KIQ_PIPE);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1538
ring->eop_gpu_addr = adev->mes.eop_gpu_addr[inst];
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1559
int inst = MES_PIPE_INST(xcc_id, pipe);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1564
ring = &adev->mes.ring[inst];
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1580
adev->mes.mqd_backup[inst] = kmalloc(mqd_size, GFP_KERNEL);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1581
if (!adev->mes.mqd_backup[inst])
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1639
int pipe, inst, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1643
inst = MES_PIPE_INST(xcc_id, pipe);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1645
amdgpu_bo_free_kernel(&adev->mes.shared_cmd_buf_obj[inst],
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1646
&adev->mes.shared_cmd_buf_gpu_addr[inst],
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1649
kfree(adev->mes.mqd_backup[inst]);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1651
amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[inst],
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1652
&adev->mes.eop_gpu_addr[inst],
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1656
amdgpu_bo_free_kernel(&adev->mes.ring[inst].mqd_obj,
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1657
&adev->mes.ring[inst].mqd_gpu_addr,
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1658
&adev->mes.ring[inst].mqd_ptr);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1659
amdgpu_ring_fini(&adev->mes.ring[inst]);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1741
int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_KIQ_PIPE);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1746
mes_v12_1_kiq_setting(&adev->mes.ring[inst], xcc_id);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1812
int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1814
if (adev->mes.ring[inst].sched.ready) {
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1817
&adev->mes.ring[inst],
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1822
adev->mes.ring[inst].sched.ready = false;
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
291
int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
294
xcc_id = mes->master_xcc_ids[inst];
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
352
int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
355
xcc_id = mes->master_xcc_ids[inst];
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
651
int master_xcc_id, inst = MES_PIPE_INST(xcc_id, pipe);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
665
master_xcc_id = mes->master_xcc_ids[inst];
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
933
int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
937
xcc_id = mes->master_xcc_ids[inst];
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
977
int r, inst = MES_PIPE_INST(xcc_id, pipe);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
992
&adev->mes.ucode_fw_obj[inst],
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
993
&adev->mes.ucode_fw_gpu_addr[inst],
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
994
(void **)&adev->mes.ucode_fw_ptr[inst]);
drivers/gpu/drm/amd/amdgpu/mmsch_v3_0.h
52
struct mmsch_v3_0_table_info inst[MMSCH_V3_0_VCN_INSTANCES];
drivers/gpu/drm/amd/amdgpu/mmsch_v4_0.h
63
struct mmsch_v4_0_table_info inst[MMSCH_V4_0_VCN_INSTANCES];
drivers/gpu/drm/amd/amdgpu/nv.c
379
if (!adev->reg_offset[en->hwip][en->inst])
drivers/gpu/drm/amd/amdgpu/nv.c
381
else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
1529
int inst, instances, queue, xcc_id = 0;
drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
1543
inst = ((entry->ring_id & 0xf0) >> 4) +
drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
1546
if (inst == GET_INST(SDMA0, instances))
drivers/gpu/drm/amd/amdgpu/soc15.c
428
if (!adev->reg_offset[en->hwip][en->inst])
drivers/gpu/drm/amd/amdgpu/soc15.c
430
else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
drivers/gpu/drm/amd/amdgpu/soc15.h
100
#define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \
drivers/gpu/drm/amd/amdgpu/soc15.h
101
{ ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask }
drivers/gpu/drm/amd/amdgpu/soc15.h
55
uint32_t inst;
drivers/gpu/drm/amd/amdgpu/soc15.h
62
uint32_t inst;
drivers/gpu/drm/amd/amdgpu/soc15.h
72
uint32_t inst;
drivers/gpu/drm/amd/amdgpu/soc15.h
81
uint32_t inst;
drivers/gpu/drm/amd/amdgpu/soc15.h
90
#define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg
drivers/gpu/drm/amd/amdgpu/soc15.h
91
#define SOC15_REG_ENTRY_STR(ip, inst, reg) \
drivers/gpu/drm/amd/amdgpu/soc15.h
92
{ ip##_HWIP, inst, reg##_BASE_IDX, reg, #reg }
drivers/gpu/drm/amd/amdgpu/soc15.h
94
#define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)
drivers/gpu/drm/amd/amdgpu/soc15.h
97
#define SOC15_REG_ENTRY_OFFSET_INST(entry, inst) \
drivers/gpu/drm/amd/amdgpu/soc15.h
98
(adev->reg_offset[entry.hwip][inst][entry.seg] + entry.reg_offset)
drivers/gpu/drm/amd/amdgpu/soc15_common.h
100
#define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
101
amdgpu_device_wait_on_rreg(adev, inst, \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
102
(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)), \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
105
#define SOC15_WAIT_ON_RREG_OFFSET(ip, inst, reg, offset, expected_value, mask) \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
106
amdgpu_device_wait_on_rreg(adev, inst, \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
107
(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg) + (offset)), \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
113
#define WREG32_RLC_EX(prefix, reg, value, inst) \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
118
uint32_t r0 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG0_BASE_IDX] + prefix##SCRATCH_REG0; \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
119
uint32_t r1 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG1; \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
120
uint32_t spare_int = adev->reg_offset[GC_HWIP][inst][prefix##RLC_SPARE_INT_BASE_IDX] + prefix##RLC_SPARE_INT; \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
138
#define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
139
__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS_RLC, GC_HWIP, inst)
drivers/gpu/drm/amd/amdgpu/soc15_common.h
151
#define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
153
uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\
drivers/gpu/drm/amd/amdgpu/soc15_common.h
155
uint32_t r2 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG2; \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
156
uint32_t r3 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG3; \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
157
uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][inst][prefix##GRBM_GFX_CNTL_BASE_IDX] + prefix##GRBM_GFX_CNTL; \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
158
uint32_t grbm_idx = adev->reg_offset[GC_HWIP][inst][prefix##GRBM_GFX_INDEX_BASE_IDX] + prefix##GRBM_GFX_INDEX; \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
169
#define RREG32_SOC15_RLC(ip, inst, reg) \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
170
__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, AMDGPU_REGS_RLC, ip##_HWIP, inst)
drivers/gpu/drm/amd/amdgpu/soc15_common.h
172
#define WREG32_SOC15_RLC(ip, inst, reg, value) \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
174
uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\
drivers/gpu/drm/amd/amdgpu/soc15_common.h
175
__WREG32_SOC15_RLC__(target_reg, value, AMDGPU_REGS_RLC, ip##_HWIP, inst); \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
178
#define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
180
uint32_t target_reg = adev->reg_offset[GC_HWIP][inst][reg##_BASE_IDX] + reg;\
drivers/gpu/drm/amd/amdgpu/soc15_common.h
181
WREG32_RLC_EX(prefix, target_reg, value, inst); \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
191
#define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
192
__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value, AMDGPU_REGS_RLC, ip##_HWIP, inst)
drivers/gpu/drm/amd/amdgpu/soc15_common.h
194
#define RREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset) \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
195
__RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, AMDGPU_REGS_RLC, ip##_HWIP, inst)
drivers/gpu/drm/amd/amdgpu/soc15_common.h
198
#define RREG32_SOC15_EXT(ip, inst, reg, ext) \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
199
RREG32_PCIE_EXT((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
201
amdgpu_reg_get_smn_base64(adev, ip##_HWIP, inst))
drivers/gpu/drm/amd/amdgpu/soc15_common.h
203
#define WREG32_SOC15_EXT(ip, inst, reg, ext, value) \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
205
(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) * \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
207
amdgpu_reg_get_smn_base64(adev, ip##_HWIP, inst), \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
28
#define GET_INST(ip, inst) \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
30
adev->ip_map.logical_to_dev_inst(adev, ip##_HWIP, inst) : inst)
drivers/gpu/drm/amd/amdgpu/soc15_common.h
36
#define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
drivers/gpu/drm/amd/amdgpu/soc15_common.h
37
#define SOC15_REG_OFFSET1(ip, inst, reg, offset) \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
38
(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)+(offset))
drivers/gpu/drm/amd/amdgpu/soc15_common.h
40
#define __WREG32_SOC15_RLC__(reg, value, flag, hwip, inst) \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
42
amdgpu_sriov_wreg(adev, reg, value, flag, hwip, inst) : \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
45
#define __RREG32_SOC15_RLC__(reg, flag, hwip, inst) \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
47
amdgpu_sriov_rreg(adev, reg, flag, hwip, inst) : \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
66
#define RREG32_SOC15(ip, inst, reg) \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
67
__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
68
0, ip##_HWIP, inst)
drivers/gpu/drm/amd/amdgpu/soc15_common.h
72
#define RREG32_SOC15_IP_NO_KIQ(ip, reg, inst) __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst)
drivers/gpu/drm/amd/amdgpu/soc15_common.h
74
#define RREG32_SOC15_NO_KIQ(ip, inst, reg) \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
75
__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
76
AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst)
drivers/gpu/drm/amd/amdgpu/soc15_common.h
78
#define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
79
__RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)) + \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
80
(offset), 0, ip##_HWIP, inst)
drivers/gpu/drm/amd/amdgpu/soc15_common.h
82
#define WREG32_SOC15(ip, inst, reg, value) \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
83
__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
84
value, 0, ip##_HWIP, inst)
drivers/gpu/drm/amd/amdgpu/soc15_common.h
89
#define WREG32_SOC15_IP_NO_KIQ(ip, reg, value, inst) \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
90
__WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst)
drivers/gpu/drm/amd/amdgpu/soc15_common.h
92
#define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
93
__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
94
value, AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst)
drivers/gpu/drm/amd/amdgpu/soc15_common.h
96
#define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
97
__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, \
drivers/gpu/drm/amd/amdgpu/soc15_common.h
98
value, 0, ip##_HWIP, inst)
drivers/gpu/drm/amd/amdgpu/soc21.c
331
if (!adev->reg_offset[en->hwip][en->inst])
drivers/gpu/drm/amd/amdgpu/soc21.c
333
else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
drivers/gpu/drm/amd/amdgpu/soc24.c
158
if (!adev->reg_offset[en->hwip][en->inst])
drivers/gpu/drm/amd/amdgpu/soc24.c
160
else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
drivers/gpu/drm/amd/amdgpu/soc_v1_0.c
212
if (!adev->reg_offset[en->hwip][en->inst])
drivers/gpu/drm/amd/amdgpu/soc_v1_0.c
214
else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
203
adev->uvd.inst->ring.funcs = &uvd_v3_1_ring_funcs;
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
250
addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
267
addr = (adev->uvd.inst->gpu_addr >> 28) & 0xF;
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
271
addr = (adev->uvd.inst->gpu_addr >> 32) & 0xFF;
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
332
struct amdgpu_ring *ring = &adev->uvd.inst->ring;
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
527
amdgpu_fence_process(&adev->uvd.inst->ring);
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
539
adev->uvd.inst->irq.num_types = 1;
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
540
adev->uvd.inst->irq.funcs = &uvd_v3_1_irq_funcs;
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
564
r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
572
ring = &adev->uvd.inst->ring;
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
574
r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0,
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
584
ptr = adev->uvd.inst[0].cpu_addr;
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
656
struct amdgpu_ring *ring = &adev->uvd.inst->ring;
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
116
r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
124
ring = &adev->uvd.inst->ring;
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
126
r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0,
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
162
struct amdgpu_ring *ring = &adev->uvd.inst->ring;
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
289
struct amdgpu_ring *ring = &adev->uvd.inst->ring;
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
585
addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
602
addr = (adev->uvd.inst->gpu_addr >> 28) & 0xF;
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
606
addr = (adev->uvd.inst->gpu_addr >> 32) & 0xFF;
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
713
amdgpu_fence_process(&adev->uvd.inst->ring);
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
802
adev->uvd.inst->ring.funcs = &uvd_v4_2_ring_funcs;
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
812
adev->uvd.inst->irq.num_types = 1;
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
813
adev->uvd.inst->irq.funcs = &uvd_v4_2_irq_funcs;
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
109
r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
117
ring = &adev->uvd.inst->ring;
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
119
r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0,
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
153
struct amdgpu_ring *ring = &adev->uvd.inst->ring;
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
287
lower_32_bits(adev->uvd.inst->gpu_addr));
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
289
upper_32_bits(adev->uvd.inst->gpu_addr));
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
321
struct amdgpu_ring *ring = &adev->uvd.inst->ring;
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
629
amdgpu_fence_process(&adev->uvd.inst->ring);
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
904
adev->uvd.inst->ring.funcs = &uvd_v5_0_ring_funcs;
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
914
adev->uvd.inst->irq.num_types = 1;
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
915
adev->uvd.inst->irq.funcs = &uvd_v5_0_irq_funcs;
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
1180
adev->uvd.inst->srbm_soft_reset = srbm_soft_reset;
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
1183
adev->uvd.inst->srbm_soft_reset = 0;
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
1192
if (!adev->uvd.inst->srbm_soft_reset)
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
1204
if (!adev->uvd.inst->srbm_soft_reset)
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
1206
srbm_soft_reset = adev->uvd.inst->srbm_soft_reset;
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
1234
if (!adev->uvd.inst->srbm_soft_reset)
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
125
if (ring == &adev->uvd.inst->ring_enc[0])
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
1260
amdgpu_fence_process(&adev->uvd.inst->ring);
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
1264
amdgpu_fence_process(&adev->uvd.inst->ring_enc[0]);
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
1270
amdgpu_fence_process(&adev->uvd.inst->ring_enc[1]);
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
156
if (ring == &adev->uvd.inst->ring_enc[0])
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
1635
adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
1638
adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_phys_funcs;
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
1648
adev->uvd.inst->ring_enc[i].funcs = &uvd_v6_0_enc_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
1661
adev->uvd.inst->irq.num_types = adev->uvd.num_enc_rings + 1;
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
1663
adev->uvd.inst->irq.num_types = 1;
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
1665
adev->uvd.inst->irq.funcs = &uvd_v6_0_irq_funcs;
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
387
r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
394
r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP, &adev->uvd.inst->irq);
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
406
adev->uvd.inst->ring_enc[i].funcs = NULL;
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
408
adev->uvd.inst->irq.num_types = 1;
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
414
ring = &adev->uvd.inst->ring;
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
416
r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0,
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
427
ring = &adev->uvd.inst->ring_enc[i];
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
430
&adev->uvd.inst->irq, 0,
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
451
amdgpu_ring_fini(&adev->uvd.inst->ring_enc[i]);
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
467
struct amdgpu_ring *ring = &adev->uvd.inst->ring;
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
508
ring = &adev->uvd.inst->ring_enc[i];
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
613
lower_32_bits(adev->uvd.inst->gpu_addr));
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
615
upper_32_bits(adev->uvd.inst->gpu_addr));
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
728
struct amdgpu_ring *ring = &adev->uvd.inst->ring;
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
868
ring = &adev->uvd.inst->ring_enc[0];
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
875
ring = &adev->uvd.inst->ring_enc[1];
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
95
if (ring == &adev->uvd.inst->ring_enc[0])
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1117
ring = &adev->uvd.inst[k].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1124
ring = &adev->uvd.inst[k].ring_enc[1];
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
123
if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1498
amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1501
amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[0]);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1505
amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[1]);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1607
adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1608
adev->uvd.inst[i].ring.me = i;
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
161
if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1621
adev->uvd.inst[j].ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1622
adev->uvd.inst[j].ring_enc[i].me = j;
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1641
adev->uvd.inst[i].irq.num_types = adev->uvd.num_enc_rings + 1;
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1642
adev->uvd.inst[i].irq.funcs = &uvd_v7_0_irq_funcs;
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
411
r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->uvd.inst[j].irq);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
417
r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + UVD_7_0__SRCID__UVD_ENC_GEN_PURP, &adev->uvd.inst[j].irq);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
448
ring = &adev->uvd.inst[j].ring;
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
452
&adev->uvd.inst[j].irq, 0,
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
459
ring = &adev->uvd.inst[j].ring_enc[i];
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
474
&adev->uvd.inst[j].irq, 0,
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
507
amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
536
ring = &adev->uvd.inst[j].ring;
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
577
ring = &adev->uvd.inst[j].ring_enc[i];
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
696
lower_32_bits(adev->uvd.inst[i].gpu_addr));
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
698
upper_32_bits(adev->uvd.inst[i].gpu_addr));
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
707
lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
709
upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
714
lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
716
upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
762
WDOORBELL32(adev->uvd.inst[i].ring_enc[0].doorbell_index, 0);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
763
*adev->uvd.inst[i].ring_enc[0].wptr_cpu_addr = 0;
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
764
adev->uvd.inst[i].ring_enc[0].wptr = 0;
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
765
adev->uvd.inst[i].ring_enc[0].wptr_old = 0;
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
820
ring = &adev->uvd.inst[i].ring;
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
838
lower_32_bits(adev->uvd.inst[i].gpu_addr));
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
840
upper_32_bits(adev->uvd.inst[i].gpu_addr));
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
850
lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
852
upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
857
lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
859
upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
89
if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
923
ring = &adev->uvd.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
979
ring = &adev->uvd.inst[k].ring;
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1003
ring = &adev->vcn.inst->ring_enc[1];
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1023
struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
108
adev->vcn.inst[0].num_enc_rings = 2;
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
109
adev->vcn.inst[0].set_pg_state = vcn_v1_0_set_pg_state;
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1294
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1301
if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1303
adev->vcn.inst[inst_idx].pause_state.fw_based,
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1304
adev->vcn.inst[inst_idx].pause_state.jpeg,
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1327
ring = &adev->vcn.inst->ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1334
ring = &adev->vcn.inst->ring_enc[1];
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1352
adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1356
if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) {
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1358
adev->vcn.inst[inst_idx].pause_state.fw_based,
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1359
adev->vcn.inst[inst_idx].pause_state.jpeg,
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
137
VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq);
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1387
ring = adev->jpeg.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1412
adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg;
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
142
for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
144
&adev->vcn.inst->irq);
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1440
struct amdgpu_vcn_inst *vinst = adev->vcn.inst;
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
154
adev->vcn.inst[0].idle_work.work.func = vcn_v1_0_idle_work_handler;
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
162
ring = &adev->vcn.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
165
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1672
if (ring == &adev->vcn.inst->ring_enc[0])
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1689
if (ring == &adev->vcn.inst->ring_enc[0])
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
170
adev->vcn.inst[0].internal.scratch9 = adev->vcn.inst->external.scratch9 =
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1706
if (ring == &adev->vcn.inst->ring_enc[0])
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
172
adev->vcn.inst[0].internal.data0 = adev->vcn.inst->external.data0 =
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
174
adev->vcn.inst[0].internal.data1 = adev->vcn.inst->external.data1 =
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
176
adev->vcn.inst[0].internal.cmd = adev->vcn.inst->external.cmd =
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
178
adev->vcn.inst[0].internal.nop = adev->vcn.inst->external.nop =
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
181
for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1812
amdgpu_fence_process(&adev->vcn.inst->ring_dec);
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1815
amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1818
amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
184
ring = &adev->vcn.inst->ring_enc[i];
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
187
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1875
for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i)
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1876
fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]);
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1886
if (amdgpu_fence_count_emitted(adev->jpeg.inst->ring_dec))
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1891
adev->vcn.inst->pause_dpg_mode(vcn_inst, &new_state);
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1894
fences += amdgpu_fence_count_emitted(adev->jpeg.inst->ring_dec);
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1895
fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_dec);
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1905
schedule_delayed_work(&adev->vcn.inst[0].idle_work, VCN_IDLE_TIMEOUT);
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1912
bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1914
mutex_lock(&adev->vcn.inst[0].vcn1_jpeg1_workaround);
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1916
if (amdgpu_fence_wait_empty(ring->adev->jpeg.inst->ring_dec))
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
193
adev->vcn.inst[0].pause_dpg_mode = vcn_v1_0_pause_dpg_mode;
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1940
for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i)
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1941
fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]);
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1948
if (amdgpu_fence_count_emitted(adev->jpeg.inst->ring_dec))
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1958
adev->vcn.inst->pause_dpg_mode(adev->vcn.inst, &new_state);
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
196
struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1964
schedule_delayed_work(&ring->adev->vcn.inst[0].idle_work, VCN_IDLE_TIMEOUT);
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
1965
mutex_unlock(&ring->adev->vcn.inst[0].vcn1_jpeg1_workaround);
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
199
amdgpu_vcn_fwlog_init(adev->vcn.inst);
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
2100
if (reg == PACKET0(p->adev->vcn.inst[0].internal.data0, 0)) {
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
2102
} else if (reg == PACKET0(p->adev->vcn.inst[0].internal.data1, 0)) {
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
2104
} else if (reg == PACKET0(p->adev->vcn.inst[0].internal.cmd, 0)) {
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
2182
adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
2189
for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i)
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
2190
adev->vcn.inst->ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
2200
adev->vcn.inst->irq.num_types = adev->vcn.inst[0].num_enc_rings + 2;
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
2201
adev->vcn.inst->irq.funcs = &vcn_v1_0_irq_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
250
struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
257
for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
258
ring = &adev->vcn.inst->ring_enc[i];
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
264
ring = adev->jpeg.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
280
struct amdgpu_vcn_inst *vinst = adev->vcn.inst;
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
306
idle_work_unexecuted = cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
351
uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
364
lower_32_bits(adev->vcn.inst->gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
366
upper_32_bits(adev->vcn.inst->gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
376
lower_32_bits(adev->vcn.inst->gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
378
upper_32_bits(adev->vcn.inst->gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
384
lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
386
upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
419
uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
435
lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
437
upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
447
lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
449
upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
457
lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
460
upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
843
struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
996
ring = &adev->vcn.inst->ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1004
struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1005
struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1014
return vcn_v2_0_start_dpg_mode(vinst, adev->vcn.inst->indirect_sram);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1155
ring = &adev->vcn.inst->ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
116
adev->vcn.inst[0].num_enc_rings = 1;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1164
ring = &adev->vcn.inst->ring_enc[1];
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
118
adev->vcn.inst[0].num_enc_rings = 2;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
120
adev->vcn.inst->set_pg_state = vcn_v2_0_set_pg_state;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1294
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1300
if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1302
adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1311
struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1327
ring = &adev->vcn.inst->ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1337
ring = &adev->vcn.inst->ring_enc[1];
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1363
adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1410
vcn_v2_0_enable_clock_gating(&adev->vcn.inst[0]);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1413
vcn_v2_0_disable_clock_gating(&adev->vcn.inst[0]);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
145
&adev->vcn.inst->irq);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1483
amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1485
amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
150
for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1500
amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[0].internal.cmd, 0));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1520
amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.nop, 0));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
153
&adev->vcn.inst->irq);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1541
amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.context_id, 0));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1544
amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1547
amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1550
amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1553
amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1556
amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1559
amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1582
amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_vmid, 0));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1585
amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_bar_low, 0));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1587
amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_bar_high, 0));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1589
amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_size, 0));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1598
amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1601
amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1604
amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.gp_scratch8, 0));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1607
amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1632
amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1635
amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1638
amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1654
if (ring == &adev->vcn.inst->ring_enc[0])
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1671
if (ring == &adev->vcn.inst->ring_enc[0]) {
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
168
ring = &adev->vcn.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1695
if (ring == &adev->vcn.inst->ring_enc[0]) {
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
175
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
180
adev->vcn.inst[0].internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1808
amdgpu_fence_process(&adev->vcn.inst->ring_dec);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
181
adev->vcn.inst[0].internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1811
amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1814
amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
182
adev->vcn.inst[0].internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
183
adev->vcn.inst[0].internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1835
WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1839
amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
184
adev->vcn.inst[0].internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1841
amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.scratch9, 0));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1845
tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
185
adev->vcn.inst[0].internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
187
adev->vcn.inst[0].internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
188
adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
189
adev->vcn.inst[0].internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
190
adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
191
adev->vcn.inst[0].internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
192
adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1921
adev->vcn.inst->ring_dec.wptr = 0;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1922
adev->vcn.inst->ring_dec.wptr_old = 0;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1923
vcn_v2_0_dec_ring_set_wptr(&adev->vcn.inst->ring_dec);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1925
for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1926
adev->vcn.inst->ring_enc[i].wptr = 0;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1927
adev->vcn.inst->ring_enc[i].wptr_old = 0;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1928
vcn_v2_0_enc_ring_set_wptr(&adev->vcn.inst->ring_enc[i]);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
193
adev->vcn.inst[0].internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
194
adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
195
adev->vcn.inst[0].internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
196
adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
198
for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
1984
size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
2005
lower_32_bits(adev->vcn.inst->gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
2009
upper_32_bits(adev->vcn.inst->gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
201
ring = &adev->vcn.inst->ring_enc[i];
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
2023
lower_32_bits(adev->vcn.inst->gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
2027
upper_32_bits(adev->vcn.inst->gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
2038
lower_32_bits(adev->vcn.inst->gpu_addr + offset +
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
2043
upper_32_bits(adev->vcn.inst->gpu_addr + offset +
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
2052
for (r = 0; r < adev->vcn.inst[0].num_enc_rings; ++r) {
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
2053
ring = &adev->vcn.inst->ring_enc[r];
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
2066
ring = &adev->vcn.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
209
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
215
adev->vcn.inst[0].pause_dpg_mode = vcn_v2_0_pause_dpg_mode;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
216
adev->vcn.inst[0].reset = vcn_v2_0_reset;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
2178
adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
2185
for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i)
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
2186
adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
219
amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
2196
adev->vcn.inst->irq.num_types = adev->vcn.inst[0].num_enc_rings + 1;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
2197
adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
227
fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
231
amdgpu_vcn_fwlog_init(adev->vcn.inst);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
255
struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
285
struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
302
for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
303
ring = &adev->vcn.inst->ring_enc[i];
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
322
struct amdgpu_vcn_inst *vinst = adev->vcn.inst;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
384
uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
400
lower_32_bits(adev->vcn.inst->gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
402
upper_32_bits(adev->vcn.inst->gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
412
lower_32_bits(adev->vcn.inst->gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
414
upper_32_bits(adev->vcn.inst->gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
420
lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
422
upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
428
lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
430
upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
442
uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
468
lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
471
upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
489
lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
492
upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
509
lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
512
upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
521
lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
524
upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
856
struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
857
struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
870
adev->vcn.inst->dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst->dpg_sram_cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1002
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1003
struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1018
adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1105
ring = &adev->vcn.inst[inst_idx].ring_dec;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1159
int i = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1161
adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1173
return vcn_v2_5_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
121
struct amdgpu_vcn_inst *v = &adev->vcn.inst[i];
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1295
ring = &adev->vcn.inst[i].ring_dec;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1321
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1330
ring = &adev->vcn.inst[i].ring_enc[1];
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1432
size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1450
lower_32_bits(adev->vcn.inst[i].gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1454
upper_32_bits(adev->vcn.inst[i].gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1467
lower_32_bits(adev->vcn.inst[i].gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1471
upper_32_bits(adev->vcn.inst[i].gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
148
if (!fences && !atomic_read(&adev->vcn.inst[0].total_submission_cnt)) {
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1481
lower_32_bits(adev->vcn.inst[i].gpu_addr + offset +
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1486
upper_32_bits(adev->vcn.inst[i].gpu_addr + offset +
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1495
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1508
ring = &adev->vcn.inst[i].ring_dec;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
153
schedule_delayed_work(&adev->vcn.inst[0].idle_work, VCN_IDLE_TIMEOUT);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1545
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1580
int i = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
160
struct amdgpu_vcn_inst *v = &adev->vcn.inst[ring->me];
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
162
atomic_inc(&adev->vcn.inst[0].total_submission_cnt);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
164
cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1655
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1661
if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1663
adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1672
struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1690
ring = &adev->vcn.inst[inst_idx].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
170
mutex_lock(&adev->vcn.inst[0].vcn_pg_lock);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1700
ring = &adev->vcn.inst[inst_idx].ring_enc[1];
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1722
adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1821
if (ring == &adev->vcn.inst[ring->me].ring_enc[0])
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1838
if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1862
if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1917
adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1918
adev->vcn.inst[i].ring_dec.me = i;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1929
for (i = 0; i < adev->vcn.inst[j].num_enc_rings; ++i) {
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1930
adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1931
adev->vcn.inst[j].ring_enc[i].me = j;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
196
mutex_unlock(&adev->vcn.inst[0].vcn_pg_lock);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1989
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
2064
amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
2067
amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
207
!adev->vcn.inst[ring->me].using_unified_queue)
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
2070
amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
208
atomic_dec(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
2098
adev->vcn.inst[i].irq.num_types = adev->vcn.inst[i].num_enc_rings + 1;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
2099
adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
210
atomic_dec(&adev->vcn.inst[0].total_submission_cnt);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
2101
adev->vcn.inst[i].ras_poison_irq.num_types = adev->vcn.inst[i].num_enc_rings + 1;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
2102
adev->vcn.inst[i].ras_poison_irq.funcs = &vcn_v2_6_ras_irq_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
212
schedule_delayed_work(&adev->vcn.inst[0].idle_work,
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
2181
uint32_t inst, sub;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
2184
for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++)
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
2187
vcn_v2_6_query_poison_by_instance(adev, inst, sub);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
233
adev->vcn.inst[i].num_enc_rings = 1;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
242
adev->vcn.inst[i].num_enc_rings = 2;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
256
adev->vcn.inst[i].set_pg_state = vcn_v2_5_set_pg_state;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
286
VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[j].irq);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
291
for (i = 0; i < adev->vcn.inst[j].num_enc_rings; ++i) {
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
293
i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[j].irq);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
300
VCN_2_6__SRCID_UVD_POISON, &adev->vcn.inst[j].ras_poison_irq);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
309
adev->vcn.inst[j].idle_work.work.func = vcn_v2_5_idle_work_handler;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
317
adev->vcn.inst[j].internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
318
adev->vcn.inst[j].internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
319
adev->vcn.inst[j].internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
320
adev->vcn.inst[j].internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
321
adev->vcn.inst[j].internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
322
adev->vcn.inst[j].internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
324
adev->vcn.inst[j].internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
325
adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
326
adev->vcn.inst[j].internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
327
adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
328
adev->vcn.inst[j].internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
329
adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
330
adev->vcn.inst[j].internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
331
adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
332
adev->vcn.inst[j].internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
333
adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
335
ring = &adev->vcn.inst[j].ring_dec;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
347
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq,
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
352
for (i = 0; i < adev->vcn.inst[j].num_enc_rings; ++i) {
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
355
ring = &adev->vcn.inst[j].ring_enc[i];
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
369
&adev->vcn.inst[j].irq, 0,
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
375
fw_shared = adev->vcn.inst[j].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
379
amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
382
adev->vcn.inst[j].pause_dpg_mode = vcn_v2_5_pause_dpg_mode;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
383
adev->vcn.inst[j].reset = vcn_v2_5_reset;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
387
amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
429
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
472
adev->vcn.inst[j].ring_enc[0].sched.ready = true;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
473
adev->vcn.inst[j].ring_enc[1].sched.ready = false;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
474
adev->vcn.inst[j].ring_enc[2].sched.ready = false;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
475
adev->vcn.inst[j].ring_dec.sched.ready = true;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
478
ring = &adev->vcn.inst[j].ring_dec;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
487
for (i = 0; i < adev->vcn.inst[j].num_enc_rings; ++i) {
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
488
ring = &adev->vcn.inst[j].ring_enc[i];
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
512
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
591
int i = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
598
size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
609
lower_32_bits(adev->vcn.inst[i].gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
611
upper_32_bits(adev->vcn.inst[i].gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
620
lower_32_bits(adev->vcn.inst[i].gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
622
upper_32_bits(adev->vcn.inst[i].gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
628
lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
630
upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
636
lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
638
upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
648
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
649
uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst_idx].fw->size + 4);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
675
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
678
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
696
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
699
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
716
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
719
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
728
lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
731
upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
753
int i = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
863
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
919
int i = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
974
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1003
WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1005
data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1025
WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1031
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1032
struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1047
adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1136
ring = &adev->vcn.inst[inst_idx].ring_dec;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1196
int i = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1327
ring = &adev->vcn.inst[i].ring_dec;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1337
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
135
adev->vcn.inst[i].num_enc_rings = 1;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1359
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1368
ring = &adev->vcn.inst[i].ring_enc[1];
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1418
header.inst[i].init_status = 0;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1419
header.inst[i].table_offset = 0;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1420
header.inst[i].table_size = 0;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1435
cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1451
lower_32_bits(adev->vcn.inst[i].gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1454
upper_32_bits(adev->vcn.inst[i].gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
146
adev->vcn.inst[i].num_enc_rings = 0;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1465
cache_addr = adev->vcn.inst[i].gpu_addr + offset;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1479
cache_addr = adev->vcn.inst[i].gpu_addr + offset +
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
148
adev->vcn.inst[i].num_enc_rings = 2;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1494
for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) {
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1495
ring = &adev->vcn.inst[i].ring_enc[j];
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1509
ring = &adev->vcn.inst[i].ring_dec;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1533
header.inst[i].init_status = 0;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1534
header.inst[i].table_offset = header.total_size;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1535
header.inst[i].table_size = table_size;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
157
adev->vcn.inst[i].set_pg_state = vcn_v3_0_set_pg_state;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1597
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1635
int i = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1717
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1724
if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1726
adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1752
fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1754
ring = &adev->vcn.inst[inst_idx].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1764
ring = &adev->vcn.inst[inst_idx].ring_enc[1];
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1790
adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1841
fw_shared = adev->vcn.inst[ring->me].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
2024
if (reg == PACKET0(p->adev->vcn.inst[ring->me].internal.data0, 0)) {
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
2026
} else if (reg == PACKET0(p->adev->vcn.inst[ring->me].internal.data1, 0)) {
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
2028
} else if (reg == PACKET0(p->adev->vcn.inst[ring->me].internal.cmd, 0) &&
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
2083
if (ring == &adev->vcn.inst[ring->me].ring_enc[0])
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
209
adev->vcn.inst[i].internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
210
adev->vcn.inst[i].internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
2100
if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
211
adev->vcn.inst[i].internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
212
adev->vcn.inst[i].internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
2124
if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
213
adev->vcn.inst[i].internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
214
adev->vcn.inst[i].internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
216
adev->vcn.inst[i].internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
217
adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
218
adev->vcn.inst[i].internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
2181
adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
2183
adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
2184
adev->vcn.inst[i].ring_dec.me = i;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
219
adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
2196
for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) {
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
2197
adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
2198
adev->vcn.inst[i].ring_enc[j].me = i;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
220
adev->vcn.inst[i].internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
221
adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
222
adev->vcn.inst[i].internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
223
adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
224
adev->vcn.inst[i].internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
225
adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
2256
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
229
VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
233
atomic_set(&adev->vcn.inst[i].sched_score, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
2331
amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
2334
amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
2337
amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
235
ring = &adev->vcn.inst[i].ring_dec;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
2361
adev->vcn.inst[i].irq.num_types = adev->vcn.inst[i].num_enc_rings + 1;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
2362
adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
238
ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.inst[i].num_enc_rings + 1);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
244
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
246
&adev->vcn.inst[i].sched_score);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
250
for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) {
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
255
j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
259
ring = &adev->vcn.inst[i].ring_enc[j];
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
262
ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.inst[i].num_enc_rings + 1) + 1 + j;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
268
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
269
hw_prio, &adev->vcn.inst[i].sched_score);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
274
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
287
amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
290
adev->vcn.inst[i].pause_dpg_mode = vcn_v3_0_pause_dpg_mode;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
291
adev->vcn.inst[i].reset = vcn_v3_0_reset;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
295
amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
334
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
381
ring = &adev->vcn.inst[i].ring_dec;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
393
for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) {
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
394
ring = &adev->vcn.inst[i].ring_enc[j];
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
412
ring = &adev->vcn.inst[i].ring_dec;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
421
for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) {
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
422
ring = &adev->vcn.inst[i].ring_enc[j];
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
446
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
523
int inst = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
524
uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst].fw->size + 4);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
529
WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
530
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
531
WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
532
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
533
WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
536
WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
537
lower_32_bits(adev->vcn.inst[inst].gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
538
WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
539
upper_32_bits(adev->vcn.inst[inst].gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
541
WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0,
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
544
WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
547
WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
548
lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
549
WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
550
upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
551
WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
552
WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
555
WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
556
lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
557
WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
558
upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
559
WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
560
WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
563
WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
564
lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
565
WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
566
upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
567
WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
568
WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0,
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
576
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
577
uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst_idx].fw->size + 4);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
603
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
606
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
624
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
627
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
644
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
647
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
656
lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
659
upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
674
int inst = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
693
WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
694
SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS,
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
711
WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
712
SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
715
data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
721
WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
727
int inst = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
732
data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
735
WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
751
WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
767
SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
781
int inst = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
785
data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
792
WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
794
data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
816
WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
818
SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
820
data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
841
WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
843
data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
875
WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
877
data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
883
WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
885
data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
905
WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
913
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
969
int inst = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
973
data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
980
WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
982
data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1000
struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1015
adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1094
ring = &adev->vcn.inst[inst_idx].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1139
int i = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1151
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1154
return vcn_v4_0_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1281
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
132
adev->vcn.inst[i].num_enc_rings = 1;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1370
header.inst[i].init_status = 0;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1371
header.inst[i].table_offset = 0;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1372
header.inst[i].table_size = 0;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
139
adev->vcn.inst[i].set_pg_state = vcn_v4_0_set_pg_state;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1390
cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1406
lower_32_bits(adev->vcn.inst[i].gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1409
upper_32_bits(adev->vcn.inst[i].gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1420
cache_addr = adev->vcn.inst[i].gpu_addr + offset;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1434
cache_addr = adev->vcn.inst[i].gpu_addr + offset +
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1449
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1452
ring_enc = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1464
rb_setup->rb_info[0].rb_addr_lo = lower_32_bits(adev->vcn.inst[0].ring_enc[0].gpu_addr);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1465
rb_setup->rb_info[0].rb_addr_hi = upper_32_bits(adev->vcn.inst[0].ring_enc[0].gpu_addr);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1466
rb_setup->rb_info[0].rb_size = adev->vcn.inst[0].ring_enc[0].ring_size / 4;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1469
rb_setup->rb_info[2].rb_addr_lo = lower_32_bits(adev->vcn.inst[1].ring_enc[0].gpu_addr);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1470
rb_setup->rb_info[2].rb_addr_hi = upper_32_bits(adev->vcn.inst[1].ring_enc[0].gpu_addr);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1471
rb_setup->rb_info[2].rb_size = adev->vcn.inst[1].ring_enc[0].ring_size / 4;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1483
lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1486
upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1495
header.inst[i].init_status = 0;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1496
header.inst[i].table_offset = header.total_size;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1497
header.inst[i].table_size = table_size;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
153
fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1553
init_status = ((struct mmsch_v4_0_init_header *)(table_loc))->inst[enabled_vcn].init_status;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1572
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1608
int i = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1616
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
169
amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1702
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1707
if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1709
adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1735
adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1752
if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1769
if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1789
if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1985
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
203
atomic_set(&adev->vcn.inst[i].sched_score, 1);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
2049
adev->vcn.inst[i].ring_enc[0].funcs =
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
205
atomic_set(&adev->vcn.inst[i].sched_score, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
2051
adev->vcn.inst[i].ring_enc[0].me = i;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
209
VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
2118
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
215
VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].ras_poison_irq);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
219
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
2216
amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
223
(adev->vcn.inst[i].num_enc_rings + 1) + 1;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
2251
adev->vcn.inst[i].irq.num_types = adev->vcn.inst[i].num_enc_rings + 1;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
2252
adev->vcn.inst[i].irq.funcs = &vcn_v4_0_irq_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
2254
adev->vcn.inst[i].ras_poison_irq.num_types = adev->vcn.inst[i].num_enc_rings + 1;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
2255
adev->vcn.inst[i].ras_poison_irq.funcs = &vcn_v4_0_ras_irq_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
229
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
230
AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
2307
uint32_t inst, sub;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
2310
for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++)
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
2313
vcn_v4_0_query_poison_by_instance(adev, inst, sub);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
237
adev->vcn.inst[i].pause_dpg_mode = vcn_v4_0_pause_dpg_mode;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
241
amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
286
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
333
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
344
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
371
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
450
int inst = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
454
hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
459
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
460
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
461
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
462
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
463
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
466
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
467
lower_32_bits(adev->vcn.inst[inst].gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
468
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
469
upper_32_bits(adev->vcn.inst[inst].gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
471
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
473
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
476
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
477
lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
478
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
479
upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
480
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
481
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
484
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
485
lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
486
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
487
upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
488
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
489
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
492
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
493
lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
494
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
495
upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
496
WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
497
WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
513
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
516
hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
542
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
545
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
563
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
566
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
583
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
586
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
595
lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
598
upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
621
int inst = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
640
WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
641
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
646
value = (inst) ? 0x2200800 : 0;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
662
WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
663
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, value, 0x3F3FFFFF);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
666
data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
672
WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
687
int inst = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
692
data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
695
WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
711
WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
727
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, data, 0x3F3FFFFF);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
743
int inst = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
750
data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
754
WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
756
data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
778
WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
779
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
781
data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
802
WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
804
data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
829
WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
831
data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
842
WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
859
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
914
int inst = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
921
data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
925
WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
927
data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
948
WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
950
data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
961
WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
968
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
999
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1062
cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1079
lower_32_bits(adev->vcn.inst[i].gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1082
upper_32_bits(adev->vcn.inst[i].gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1093
cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1103
cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset +
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1118
fw_shared = adev->vcn.inst[vcn_inst].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1121
ring_enc = &adev->vcn.inst[vcn_inst].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1133
lower_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1136
upper_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
120
adev->vcn.inst[i].num_enc_rings = 1;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1210
int i = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1217
return vcn_v4_0_3_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
127
adev->vcn.inst[i].set_pg_state = vcn_v4_0_3_set_pg_state;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1339
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1340
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1381
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1424
int i = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1431
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1515
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1520
if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1522
adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1545
adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1562
if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
157
amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1579
if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1645
if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1657
static int vcn_v4_0_3_reset_jpeg_pre_helper(struct amdgpu_device *adev, int inst)
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1664
ring = &adev->jpeg.inst[inst].ring_dec[i];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1681
static int vcn_v4_0_3_reset_jpeg_post_helper(struct amdgpu_device *adev, int inst)
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1687
ring = &adev->jpeg.inst[inst].ring_dec[i];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1693
VCN, GET_INST(VCN, inst),
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1706
i, inst);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
171
fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1718
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1751
vcn_v4_0_3_start_dpg_mode(vinst, adev->vcn.inst[ring->me].indirect_sram);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
176
amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1818
adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_3_unified_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1819
adev->vcn.inst[i].ring_enc[0].me = i;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1821
adev->vcn.inst[i].aid_id =
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1883
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1957
uint32_t i, inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
196
VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst->irq);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1963
for (inst = 0; inst < adev->vcn.num_vcn_inst; ++inst)
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1964
if (adev->vcn.inst[inst].aid_id == i)
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1967
if (inst >= adev->vcn.num_vcn_inst) {
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1976
amdgpu_fence_process(&adev->vcn.inst[inst].ring_enc[0]);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
2017
adev->vcn.inst->irq.num_types++;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
2019
adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
202
VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst->ras_poison_irq);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
2021
adev->vcn.inst->ras_poison_irq.num_types = 1;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
2022
adev->vcn.inst->ras_poison_irq.funcs = &vcn_v4_0_3_ras_irq_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
2132
uint32_t inst, sub;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
2135
for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++)
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
2138
vcn_v4_0_3_query_poison_by_instance(adev, inst, sub);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
218
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
2223
adev->vcn.inst->ras_poison_irq.funcs) {
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
2224
r = amdgpu_irq_get(adev, &adev->vcn.inst->ras_poison_irq, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
230
ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
231
sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
236
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[0].irq, 0,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
238
&adev->vcn.inst[i].sched_score);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
245
adev->vcn.inst[i].pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
285
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
314
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
317
ring = &adev->vcn.inst[inst_idx].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
321
adev->vcn.inst[inst_idx].aid_id);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
354
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
369
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
370
vinst = &adev->vcn.inst[i];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
374
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
400
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
409
amdgpu_irq_put(adev, &adev->vcn.inst->ras_poison_irq, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
472
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
476
hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
494
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
497
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
506
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
508
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
515
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
518
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
527
lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
530
upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
549
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
553
hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
581
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
584
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
602
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
605
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
622
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
626
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
636
lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
639
upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
663
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
761
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
810
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
864
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
866
adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
884
inst_idx, adev->vcn.inst[inst_idx].aid_id);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
885
adev->vcn.inst[inst_idx].dpg_sram_curr_addr =
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
886
(uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
889
adev->vcn.inst[inst_idx].aid_id, 0, true);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
970
ring = &adev->vcn.inst[inst_idx].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
1007
ring = &adev->vcn.inst[inst_idx].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
1051
int i = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
1063
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
1066
return vcn_v4_0_5_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
1194
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
123
adev->vcn.inst[i].num_enc_rings = 1;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
1236
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
1270
int i = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
1278
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
128
adev->vcn.inst[i].set_pg_state = vcn_v4_0_5_set_pg_state;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
1365
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
1370
if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
1372
adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
1399
adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
1416
if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
1433
if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
1453
if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
1469
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
1531
adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_5_unified_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
1532
adev->vcn.inst[i].ring_enc[0].me = i;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
1599
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
1665
amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
167
atomic_set(&adev->vcn.inst[i].sched_score, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
1698
adev->vcn.inst[i].irq.num_types = adev->vcn.inst[i].num_enc_rings + 1;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
1699
adev->vcn.inst[i].irq.funcs = &vcn_v4_0_5_irq_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
171
VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
177
VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
181
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
185
i * (adev->vcn.inst[i].num_enc_rings + 1) + 1;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
192
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
193
AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
197
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
213
amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
216
adev->vcn.inst[i].pause_dpg_mode = vcn_v4_0_5_pause_dpg_mode;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
219
adev->vcn.supported_reset = amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
257
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
298
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
324
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
401
int inst = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
405
hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
410
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
411
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
412
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
413
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
414
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
417
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
418
lower_32_bits(adev->vcn.inst[inst].gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
419
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
420
upper_32_bits(adev->vcn.inst[inst].gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
422
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
424
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
427
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
428
lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
429
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
430
upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
431
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
432
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
435
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
436
lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
437
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
438
upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
439
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
440
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
443
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
444
lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
445
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
446
upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
447
WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
448
WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
464
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
468
hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
496
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
499
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
517
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
520
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
538
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
542
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
552
lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
555
upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
578
int inst = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
582
WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
584
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
586
WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
588
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
591
WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
593
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
596
WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
598
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
602
WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
604
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
606
WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
608
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
610
WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
612
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
614
WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
616
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
620
data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
625
WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
638
int inst = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
643
data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
646
WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
648
WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
650
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
653
WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
655
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
658
WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
660
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
663
WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
665
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
681
int inst = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
688
data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
692
WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
694
data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
716
WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
717
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
719
data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
740
WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
742
data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
767
WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
769
data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
780
WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
797
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
852
int inst = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
859
data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
863
WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
865
data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
886
WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
888
data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
899
WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
914
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
915
struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
930
adev->vcn.inst[inst_idx].dpg_sram_curr_addr =
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
931
(uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
1001
int i = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
1009
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
102
adev->vcn.inst[i].num_enc_rings = 1;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
108
adev->vcn.inst[i].set_pg_state = vcn_v5_0_0_set_pg_state;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
1093
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
1098
if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
1100
adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
1123
adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
1140
if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
1157
if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
1177
if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
1193
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
1285
adev->vcn.inst[i].ring_enc[0].funcs =
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
1288
adev->vcn.inst[i].ring_enc[0].funcs =
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
1290
adev->vcn.inst[i].ring_enc[0].me = i;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
1357
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
1423
amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
1456
adev->vcn.inst[i].irq.num_types = adev->vcn.inst[i].num_enc_rings + 1;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
1457
adev->vcn.inst[i].irq.funcs = &vcn_v5_0_0_irq_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
147
atomic_set(&adev->vcn.inst[i].sched_score, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
151
VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
157
VCN_5_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
161
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
168
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
169
AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
173
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
182
amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
185
adev->vcn.inst[i].pause_dpg_mode = vcn_v5_0_0_pause_dpg_mode;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
189
amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
223
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
262
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
288
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
365
int inst = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
369
hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
374
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
375
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
376
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
377
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
378
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
381
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
382
lower_32_bits(adev->vcn.inst[inst].gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
383
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
384
upper_32_bits(adev->vcn.inst[inst].gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
386
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
388
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
391
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
392
lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
393
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
394
upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
395
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
396
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
399
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
400
lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
401
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
402
upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
403
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
404
WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
407
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
408
lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
409
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
410
upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
411
WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
412
WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0,
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
428
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
432
hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
458
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
461
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
479
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
482
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
499
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
502
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
511
lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
514
upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
539
int inst = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
544
WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
545
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0,
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
549
WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
550
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
555
WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
556
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
561
WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
562
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
567
WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
568
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0,
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
572
WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
573
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0,
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
577
WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
578
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0,
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
582
WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
583
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0,
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
587
data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
593
WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
607
int inst = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
612
data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
615
WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
618
WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
619
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
624
WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
625
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
630
WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
631
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
636
WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG, data);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
637
SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
698
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
699
struct amdgpu_vcn5_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
715
adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
764
ring = &adev->vcn.inst[inst_idx].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
808
int i = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
820
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
823
return vcn_v5_0_0_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
922
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
965
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
106
adev->vcn.inst[i].set_pg_state = vcn_v5_0_1_set_pg_state;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1088
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1135
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1173
int i = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1180
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
121
amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1255
if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1272
if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1292
if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1304
static int vcn_v5_0_1_reset_jpeg_pre_helper(struct amdgpu_device *adev, int inst)
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1311
ring = &adev->jpeg.inst[inst].ring_dec[i];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1327
static int vcn_v5_0_1_reset_jpeg_post_helper(struct amdgpu_device *adev, int inst)
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1333
ring = &adev->jpeg.inst[inst].ring_dec[i];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1339
VCN, GET_INST(VCN, inst),
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1352
i, inst);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1364
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
141
fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1462
adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v5_0_1_unified_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1463
adev->vcn.inst[i].ring_enc[0].me = i;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1465
adev->vcn.inst[i].aid_id = vcn_inst / adev->vcn.num_inst_per_aid;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
150
amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1525
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1580
uint32_t i, inst;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1586
for (inst = 0; inst < adev->vcn.num_vcn_inst; ++inst)
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1587
if (adev->vcn.inst[inst].aid_id == i)
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1589
if (inst >= adev->vcn.num_vcn_inst) {
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1598
amdgpu_fence_process(&adev->vcn.inst[inst].ring_enc[0]);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1639
adev->vcn.inst->irq.num_types++;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1641
adev->vcn.inst->irq.funcs = &vcn_v5_0_1_irq_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1643
adev->vcn.inst->ras_poison_irq.num_types = 1;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1644
adev->vcn.inst->ras_poison_irq.funcs = &vcn_v5_0_1_ras_irq_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
168
VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst->irq);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1701
uint32_t inst, sub;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1704
for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++)
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1707
vcn_v5_0_1_query_poison_by_instance(adev, inst, sub);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
174
VCN_5_0__SRCID_UVD_POISON, &adev->vcn.inst->ras_poison_irq);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1795
adev->vcn.inst->ras_poison_irq.funcs) {
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1796
r = amdgpu_irq_get(adev, &adev->vcn.inst->ras_poison_irq, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
189
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
200
ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
201
sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
203
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
204
AMDGPU_RING_PRIO_DEFAULT, &adev->vcn.inst[i].sched_score);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
248
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
279
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
285
adev->vcn.inst[i].aid_id);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
309
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
319
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
347
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
349
cancel_delayed_work_sync(&adev->vcn.inst[i].idle_work);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
355
amdgpu_irq_put(adev, &adev->vcn.inst->ras_poison_irq, 0);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
398
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
423
int inst = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
427
hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
430
vcn_inst = GET_INST(VCN, inst);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
434
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
436
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
441
lower_32_bits(adev->vcn.inst[inst].gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
443
upper_32_bits(adev->vcn.inst[inst].gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
452
lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
454
upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
460
lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
462
upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
468
lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
470
upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
488
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
492
hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
520
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
523
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
541
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
544
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
561
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
565
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
575
lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
578
upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
627
vcn_inst = GET_INST(VCN, vinst->inst);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
670
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
672
adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
690
adev->vcn.inst[inst_idx].dpg_sram_curr_addr =
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
691
(uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
694
adev->vcn.inst[inst_idx].aid_id, 0, true);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
750
ring = &adev->vcn.inst[inst_idx].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
833
cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
850
lower_32_bits(adev->vcn.inst[i].gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
853
upper_32_bits(adev->vcn.inst[i].gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
864
cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
874
cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset +
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
889
fw_shared = adev->vcn.inst[vcn_inst].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
892
ring_enc = &adev->vcn.inst[vcn_inst].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
904
lower_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
907
upper_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
981
int i = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
987
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
99
adev->vcn.inst[i].num_enc_rings = 1;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
990
return vcn_v5_0_1_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
1036
adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v5_0_2_unified_ring_vm_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
1037
adev->vcn.inst[i].ring_enc[0].me = i;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
1039
adev->vcn.inst[i].aid_id = vcn_inst / adev->vcn.num_inst_per_aid;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
1099
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
111
VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst->irq);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
1144
uint32_t i, inst;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
1150
for (inst = 0; inst < adev->vcn.num_vcn_inst; ++inst)
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
1151
if (adev->vcn.inst[inst].aid_id == i)
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
1154
if (inst >= adev->vcn.num_vcn_inst) {
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
1163
amdgpu_fence_process(&adev->vcn.inst[inst].ring_enc[0]);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
1190
adev->vcn.inst->irq.num_types++;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
1191
adev->vcn.inst->irq.funcs = &vcn_v5_0_2_irq_funcs;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
128
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
134
ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
135
sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
137
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
138
AMDGPU_RING_PRIO_DEFAULT, &adev->vcn.inst[i].sched_score);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
147
amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
168
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
210
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
221
adev->vcn.inst[i].aid_id);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
247
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
249
cancel_delayed_work_sync(&adev->vcn.inst[i].idle_work);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
295
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
320
int inst = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
324
hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
327
vcn_inst = GET_INST(VCN, inst);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
331
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
333
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
338
lower_32_bits(adev->vcn.inst[inst].gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
340
upper_32_bits(adev->vcn.inst[inst].gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
349
lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
351
upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
357
lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
359
upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
365
lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
367
upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
385
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
389
hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
417
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
420
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
438
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
441
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
458
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
462
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
472
lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
475
upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
524
vcn_inst = GET_INST(VCN, vinst->inst);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
566
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
568
adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
586
adev->vcn.inst[inst_idx].dpg_sram_curr_addr =
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
587
(uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
590
adev->vcn.inst[inst_idx].aid_id, 0, true);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
64
adev->vcn.inst[i].num_enc_rings = 1;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
646
ring = &adev->vcn.inst[inst_idx].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
685
int i = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
691
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
694
return vcn_v5_0_2_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
70
adev->vcn.inst[i].set_pg_state = vcn_v5_0_2_set_pg_state;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
792
ring = &adev->vcn.inst[i].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
834
int inst_idx = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
84
fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
867
int i = vinst->inst;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
874
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
93
amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]);
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
944
if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
961
if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
981
if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c
38
static uint32_t vpe_v2_0_get_reg_offset(struct amdgpu_vpe *vpe, uint32_t inst, uint32_t offset)
drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c
42
base = vpe->ring.adev->reg_offset[VPE_HWIP][inst][0];
drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c
64
static uint32_t vpe_v6_1_get_reg_offset(struct amdgpu_vpe *vpe, uint32_t inst, uint32_t offset)
drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c
68
base = vpe->ring.adev->reg_offset[VPE_HWIP][inst][0];
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
102
uint32_t *se_mask, uint32_t inst)
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
112
int xcc_inst = inst + ffs(mm->dev->xcc_mask) - 1;
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
194
i = inst;
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
302
uint32_t inst)
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
309
inst, doorbell_id);
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h
168
uint32_t *se_mask, uint32_t inst);
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h
204
uint32_t inst);
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
115
struct mqd_update_info *minfo, uint32_t inst)
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
124
minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, inst);
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
51
uint32_t *se_mask, uint32_t inst)
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
536
int xcc_id, err, inst = 0;
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
545
xcc_mqd = mqd + mqd_offset * inst;
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
550
pr_debug("Destroy MQD failed for xcc: %d\n", inst);
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
553
++inst;
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
566
int xcc_id, err, inst = 0;
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
571
xcc_mqd = mqd + mqd_stride_size * inst;
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
577
pr_debug("Load MQD failed for xcc: %d\n", inst);
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
580
++inst;
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
60
int xcc_inst = inst + ffs(mm->dev->xcc_mask) - 1;
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
93
i = inst;
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
107
inst, m->compute_static_thread_mgmt_se0,
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
651
int xcc_id, err = 0, inst = 0;
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
656
xcc_mqd = mqd + hiq_mqd_size * inst;
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
661
pr_debug("Failed to load HIQ MQD for XCC: %d\n", inst);
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
664
++inst;
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
675
int xcc_id, err = 0, inst = 0;
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
681
m = get_mqd(mqd + hiq_mqd_size * inst);
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
688
pr_debug("Destroy HIQ MQD failed for xcc: %d\n", inst);
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
691
++inst;
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
701
int inst = 0, xcc_id;
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
706
m = get_mqd(mqd + hiq_mqd_size * inst);
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
708
m->queue_doorbell_id0, inst);
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
71
struct mqd_update_info *minfo, uint32_t inst)
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
710
++inst;
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
80
minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, inst);
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
882
int xcc_id, err = 0, inst = 0;
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
891
xcc_mqd = mqd + mqd_offset * inst;
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
896
pr_debug("Destroy MQD failed for xcc: %d\n", inst);
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
899
++inst;
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
912
int xcc_id, err = 0, inst = 0;
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
917
xcc_mqd = mqd + mqd_stride_size * inst;
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
923
pr_debug("Load MQD failed for xcc: %d\n", inst);
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
926
++inst;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10778
int i, inst;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10806
inst = aconnector->audio_inst;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10810
amdgpu_dm_audio_eld_notify(adev, inst);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10841
inst = status->audio_inst;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10842
aconnector->audio_inst = inst;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10845
amdgpu_dm_audio_eld_notify(adev, inst);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1264
adev->dm.dc->res_pool->audios[i]->inst;
drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
142
cfg->pipe_idx = (uint8_t)pipe_ctx->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
174
pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
202
pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
119
dpp_inst = clk_mgr->base.ctx->dc->res_pool->dpps[i]->inst;
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
64
#define CLK_SRI(reg_name, block, inst)\
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
115
#define CLK_SR_DCN321(reg_name, block, inst)\
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
280
!(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
281
tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
283
dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
338
dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
405
pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
456
pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
270
!(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
271
tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
273
dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
308
dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
333
if (old_dpp && !dppclk_active[old_dpp->inst])
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
334
clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, old_dpp->inst, 0);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
57
#define CLK_SR_DCN401(reg_name, block, inst)\
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
571
dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
181
dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
206
if (old_dpp && !dppclk_active[old_dpp->inst])
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
207
clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, old_dpp->inst, 0);
drivers/gpu/drm/amd/display/dc/core/dc.c
2592
mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst;
drivers/gpu/drm/amd/display/dc/core/dc.c
4010
hwss_add_dccg_set_dto_dscclk(seq_state, dccg, dsc->inst,
drivers/gpu/drm/amd/display/dc/core/dc.c
4021
hwss_add_dccg_set_dto_dscclk(seq_state, dccg, odm_dsc->inst,
drivers/gpu/drm/amd/display/dc/core/dc.c
4122
pipe_ctx->stream_res.opp->inst);
drivers/gpu/drm/amd/display/dc/core/dc.c
4484
update_dirty_rect->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/core/dc.c
4545
update_dirty_rect->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/core/dc.c
4851
inst_flags.dig_inst = (uint8_t)top_pipe_to_program->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/core/dc.c
4942
pipe_ctx->plane_res.hubp->inst);
drivers/gpu/drm/amd/display/dc/core/dc.c
5120
inst_flags.dig_inst = (uint8_t)top_pipe_to_program->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/core/dc.c
547
mux_mapping.otg_output_num = pipe->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/core/dc.c
613
mux_mapping.otg_output_num = pipe->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/core/dc.c
6200
if (pipe_ctx->stream_res.tg->inst != otg_inst)
drivers/gpu/drm/amd/display/dc/core/dc.c
6761
otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/core/dc.c
7057
pipe->stream_res.abm->funcs->set_abm_pause(pipe->stream_res.abm, !enable, i, pipe->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/core/dc.c
7262
dc->res_pool->timing_generators[i]->inst == primary_otg_inst) {
drivers/gpu/drm/amd/display/dc/core/dc.c
7321
state->hubp[i].vtg_sel = pipe_ctx->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/core/dc.c
7546
int hpo_le_inst = pipe_ctx->link_res.hpo_frl_link_enc->inst;
drivers/gpu/drm/amd/display/dc/core/dc.c
7571
state->dsc[i].dscrm_dsc_opp_pipe_source = pipe_ctx->stream_res.opp->inst;
drivers/gpu/drm/amd/display/dc/core/dc.c
7620
state->mpc.mpcc_opp_id[i] = pipe_ctx->stream_res.opp->inst;
drivers/gpu/drm/amd/display/dc/core/dc.c
7755
state->opp[i].dscrm_dsc_opp_pipe_source = pipe_ctx->stream_res.opp->inst;
drivers/gpu/drm/amd/display/dc/core/dc.c
7778
state->optc[i].otg_master_inst = pipe_ctx->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/core/dc.c
7814
state->optc[i].optc_seg0_src_sel = pipe_ctx->stream_res.opp ? pipe_ctx->stream_res.opp->inst : 0;
drivers/gpu/drm/amd/display/dc/core/dc.c
7815
state->optc[i].optc_seg1_src_sel = pipe_ctx->next_odm_pipe->stream_res.opp ? pipe_ctx->next_odm_pipe->stream_res.opp->inst : 0;
drivers/gpu/drm/amd/display/dc/core/dc.c
7818
state->optc[i].optc_seg0_src_sel = pipe_ctx->stream_res.opp ? pipe_ctx->stream_res.opp->inst : 0;
drivers/gpu/drm/amd/display/dc/core/dc.c
844
pipes->stream_res.opp->inst);
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
1117
block_sequence[*num_steps].params.update_visual_confirm_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
1123
block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
1130
block_sequence[*num_steps].params.set_output_csc_params.opp_id = current_mpc_pipe->stream_res.opp->inst;
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
1137
block_sequence[*num_steps].params.set_ocsc_default_params.opp_id = current_mpc_pipe->stream_res.opp->inst;
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
2572
mpcc_inst = hubp->inst;
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
2640
int inst = params->dccg_set_dto_dscclk_params.inst;
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
2644
dccg->funcs->set_dto_dscclk(dccg, inst, num_slices_h);
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
2746
dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
3853
struct dccg *dccg, int inst, int num_slices_h)
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
3858
seq_state->steps[*seq_state->num_steps].params.dccg_set_dto_dscclk_params.inst = inst;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
1022
*dpp_offset *= pipe_ctx->plane_res.dpp->inst;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2395
pipe->plane_res.dpp->inst,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2396
pipe->stream_res.opp->inst,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2397
pipe->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2399
pipe->plane_res.dpp->inst,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2400
pipe->stream_res.opp->inst,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2401
pipe->stream_res.tg->inst, is_phantom_pipe);
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2407
pipe->stream_res.opp->inst,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2408
pipe->stream_res.opp->inst,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2409
pipe->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2411
pipe->plane_res.dpp->inst,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2412
pipe->stream_res.opp->inst,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2413
pipe->stream_res.tg->inst, is_phantom_pipe);
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2419
pipe->plane_res.dpp->inst,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2420
pipe->stream_res.opp->inst);
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2422
pipe->plane_res.dpp->inst,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2423
pipe->stream_res.opp->inst,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2424
pipe->stream_res.tg->inst, is_phantom_pipe);
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2429
pipe->plane_res.dpp->inst,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2430
pipe->stream_res.opp->inst);
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2432
pipe->plane_res.dpp->inst,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2433
pipe->stream_res.opp->inst,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2434
pipe->stream_res.tg->inst, is_phantom_pipe);
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2439
pipe->plane_res.dpp->inst);
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2441
pipe->plane_res.dpp->inst,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2442
pipe->stream_res.opp->inst,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2443
pipe->stream_res.tg->inst, is_phantom_pipe);
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2448
pipe->plane_res.dpp->inst);
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2450
pipe->plane_res.dpp->inst,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2451
pipe->stream_res.opp->inst,
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2452
pipe->stream_res.tg->inst, is_phantom_pipe);
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
2654
split_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[i]->inst;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
3943
unsigned int i, inst, tg_inst = 0;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
3951
inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
3953
if (inst == ENGINE_ID_UNKNOWN)
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
3957
if (pool->stream_enc[i]->id == inst) {
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4002
pipe_ctx->plane_res.mpcc_inst = (uint8_t)pool->dpps[id_src[i]]->inst;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4146
pipe_ctx->plane_res.mpcc_inst = (uint8_t)pool->dpps[pipe_idx]->inst;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4299
pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst];
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4304
context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4309
pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
5871
sec_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[pipe_idx]->inst;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
5880
dcn20_acquire_dsc(dc, &state->res_ctx, &sec_pipe->stream_res.dsc, sec_pipe->stream_res.opp->inst);
drivers/gpu/drm/amd/display/dc/core/dc_surface.c
78
pipe_mask |= (uint8_t)(1 << pipe_ctx->plane_res.hubp->inst);
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
1071
payload->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
1263
cntl->data.otg_inst = pipe_ctx->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
1292
cntl->data.otg_inst = pipe->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
436
fams_pipe_data->pipe_index[pipe_idx++] = (uint8_t)head_pipe->plane_res.hubp->inst;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
441
fams_pipe_data->pipe_index[pipe_idx++] = (uint8_t)split_pipe->plane_res.hubp->inst;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
815
pipe_data->pipe_config.subvp_data.main_pipe_index = (uint8_t)subvp_pipe->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
859
pipe_data->pipe_config.subvp_data.phantom_pipe_index = (uint8_t)phantom_pipe->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
861
pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = (uint8_t)phantom_pipe->bottom_pipe->plane_res.hubp->inst;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
863
pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = (uint8_t)phantom_pipe->next_odm_pipe->plane_res.hubp->inst;
drivers/gpu/drm/amd/display/dc/dc_dsc.h
45
int inst;
drivers/gpu/drm/amd/display/dc/dc_trace.h
43
#define TRACE_OPTC_LOCK_UNLOCK_STATE(optc, inst, lock) \
drivers/gpu/drm/amd/display/dc/dc_trace.h
44
trace_dcn_optc_lock_unlock_state(optc, inst, lock, __func__, __LINE__)
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
59
#define DCCG_SFI(reg_name, field_name, field_prefix, inst, post_fix)\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
60
.field_prefix ## _ ## field_name[inst] = reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
62
#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
63
.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
356
void dccg31_disable_dscclk(struct dccg *dccg, int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
363
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
400
void dccg31_enable_dscclk(struct dccg *dccg, int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
407
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
251
void dccg31_disable_dscclk(struct dccg *dccg, int inst);
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
253
void dccg31_enable_dscclk(struct dccg *dccg, int inst);
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
32
#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
33
.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
31
#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
32
.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1006
int inst,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1009
dccg35_set_symclk_fe_rcg(dccg, inst, false);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1010
dccg35_set_symclk_fe_src_new(dccg, src, inst);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1015
int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1017
dccg35_set_symclk_fe_src_new(dccg, SYMCLK_FE_REFCLK, inst);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1018
dccg35_set_symclk_fe_rcg(dccg, inst, true);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1023
int inst,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1026
dccg35_set_symclk_be_rcg(dccg, inst, false);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1027
dccg35_set_symclk_be_src_new(dccg, inst, src);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1032
int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1037
dccg35_set_symclk_be_src_new(dccg, inst, SYMCLK_BE_REFCLK);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1043
if (dccg35_is_symclk_fe_src_functional_be(dccg, i, inst))
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1048
dccg35_set_symclk_be_rcg(dccg, inst, true);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1053
int inst,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1056
dccg35_set_symclk32_se_rcg(dccg, inst, false);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1057
dccg35_set_symclk32_se_src_new(dccg, inst, src);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1062
int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1064
dccg35_set_symclk32_se_src_new(dccg, SYMCLK32_SE_REFCLK, inst);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1065
dccg35_set_symclk32_se_rcg(dccg, inst, true);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1070
int inst,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1073
dccg35_set_symclk32_le_rcg(dccg, inst, false);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1074
dccg35_set_symclk32_le_src_new(dccg, inst, src);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1079
int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1084
dccg35_set_symclk32_le_src_new(dccg, inst, SYMCLK32_LE_REFCLK);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1091
if (dccg35_is_symclk32_se_src_functional_le_new(dccg, i, inst))
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1096
dccg35_set_symclk32_le_rcg(dccg, inst, true);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1100
int inst,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1103
dccg35_set_physymclk_rcg(dccg, inst, false);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1104
dccg35_set_physymclk_src_new(dccg, src, inst);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1108
int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1110
dccg35_set_physymclk_src_new(dccg, PHYSYMCLK_REFCLK, inst);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1111
dccg35_set_physymclk_rcg(dccg, inst, true);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1116
int inst,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1121
if (inst < 0) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1125
dccg35_set_dppclk_rcg(dccg, inst, false);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1126
dcn35_set_dppclk_src_new(dccg, inst, src);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1128
REG_SET_2(DPPCLK_DTO_PARAM[inst], 0,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1136
int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1140
if (inst < 0) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1144
dcn35_set_dppclk_src_new(dccg, inst, DPP_REFCLK);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1145
REG_SET_2(DPPCLK_DTO_PARAM[inst], 0,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1148
dccg35_set_dppclk_rcg(dccg, inst, true);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1152
int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1154
dccg35_set_dsc_clk_src_new(dccg, inst, DSC_CLK_REF_CLK);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1155
dccg35_set_dsc_clk_rcg(dccg, inst, true);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1159
int inst,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1162
dccg35_set_dsc_clk_rcg(dccg, inst, false);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1163
dccg35_set_dsc_clk_src_new(dccg, inst, src);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1168
int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1170
dccg35_set_dtbclk_p_rcg(dccg, inst, false);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1171
dccg35_set_dtbclk_p_src_new(dccg, src, inst);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1175
int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1177
dccg35_set_dtbclk_p_src_new(dccg, DTBCLK_REFCLK, inst);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1178
dccg35_set_dtbclk_p_rcg(dccg, inst, true);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1182
int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1184
dccg35_set_dpstreamclk_src_new(dccg, DP_STREAM_REFCLK, inst);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1185
dccg35_set_dpstreamclk_rcg(dccg, inst, true);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1190
int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1192
dccg35_set_dpstreamclk_rcg(dccg, inst, false);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1193
dccg35_set_dpstreamclk_src_new(dccg, src, inst);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1198
int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1200
dccg35_set_hdmistreamclk_src_new(dccg, HDMI_STREAM_REFCLK, inst);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1201
dccg35_set_hdmistreamclk_rcg(dccg, inst, true);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1206
int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1208
dccg35_set_hdmistreamclk_rcg(dccg, inst, false);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1209
dccg35_set_hdmistreamclk_src_new(dccg, src, inst);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1213
int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1215
dccg35_set_hdmi_char_clk_rcg(dccg, inst, false);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1216
dccg35_set_hdmi_char_clk_src_new(dccg, src, inst);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1219
static void dccg35_disable_hdmicharclk_new(struct dccg *dccg, int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1221
dccg35_set_hdmi_char_clk_src_new(dccg, HDMI_CHAR_REFCLK, inst);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1222
dccg35_set_hdmi_char_clk_rcg(dccg, inst, true);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
138
static void dccg35_set_dsc_clk_rcg(struct dccg *dccg, int inst, bool allow_rcg)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
145
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
170
int inst,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
180
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2036
void dccg35_enable_dscclk(struct dccg *dccg, int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2041
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2083
void dccg35_disable_dscclk(struct dccg *dccg, int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2087
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
209
int inst,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
217
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
236
int inst,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
244
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2520
int inst,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2523
dccg35_enable_symclk32_se_new(dccg, inst, (enum symclk32_se_clk_source)phyd32clk);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2526
static void dccg35_disable_symclk32_se_cb(struct dccg *dccg, int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2528
dccg35_disable_symclk32_se_new(dccg, inst);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2533
int inst,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2536
dccg35_enable_symclk32_le_new(dccg, inst, (enum symclk32_le_clk_source) src);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2539
static void dccg35_disable_symclk32_le_cb(struct dccg *dccg, int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2541
dccg35_disable_symclk32_le_new(dccg, inst);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2546
int inst,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2555
dccg35_enable_symclk32_le_new(dccg, inst, SYMCLK32_LE_REFCLK);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2557
dccg35_disable_symclk32_le_new(dccg, inst);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2562
int inst,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2568
dccg35_enable_physymclk_new(dccg, inst, (enum physymclk_source)clk_src);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2570
dccg35_disable_physymclk_new(dccg, inst);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2575
int inst,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2582
dccg35_enable_physymclk_new(dccg, inst, PHYSYMCLK_REFCLK);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2584
dccg35_disable_physymclk_new(dccg, inst);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2589
int inst,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2598
dccg35_enable_symclk32_le_new(dccg, inst, SYMCLK32_LE_REFCLK);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2600
dccg35_disable_symclk32_le_new(dccg, inst);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2606
uint32_t inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2609
dccg35_enable_dtbclk_p_new(dccg, DTBCLK_DTBCLK0, inst);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2611
dccg35_disable_dtbclk_p_new(dccg, inst);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2666
int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2668
dccg35_disable_dscclk_new(dccg, inst);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2671
static void dccg35_enable_dscclk_cb(struct dccg *dccg, int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2673
dccg35_enable_dscclk_new(dccg, inst, DSC_DTO_TUNED_CK_GPU_DISCLK_3);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
273
int inst,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
281
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
320
int inst,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
330
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
367
static void dccg35_set_dtbclk_p_rcg(struct dccg *dccg, int inst, bool enable)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
375
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
394
static void dccg35_set_dppclk_rcg(struct dccg *dccg, int inst, bool allow_rcg)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
401
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
426
int inst,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
434
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
463
int inst,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
471
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
500
int inst,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
508
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
521
int inst,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
530
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
544
int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
552
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
567
int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
571
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
584
static void dccg35_set_dsc_clk_src_new(struct dccg *dccg, int inst, enum dsc_clk_source src)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
590
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
611
int inst,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
617
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
664
int inst,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
669
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
687
int inst, enum dppclk_clock_source src)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
691
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
713
int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
721
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
751
int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
755
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
791
int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
795
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
835
int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
839
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
902
static void dccg35_set_symclk_fe_src_new(struct dccg *dccg, enum symclk_fe_source src, int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
906
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
935
static uint32_t dccg35_is_fe_rcg(struct dccg *dccg, int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
940
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
968
static uint32_t dccg35_is_symclk32_se_rcg(struct dccg *dccg, int inst)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
974
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
267
void dccg35_enable_dscclk(struct dccg *dccg, int inst);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
268
void dccg35_disable_dscclk(struct dccg *dccg, int inst);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
30
#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
31
.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
796
void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst, uint32_t num_slices_h)
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
801
switch (inst) {
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
212
void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst, uint32_t num_slices_h);
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
31
#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
32
.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
1188
if (audio->inst != 0)
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
1235
unsigned int inst,
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
1249
audio->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
632
audio->inst, value);
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
662
audio->inst, value);
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
910
audio->inst, value, audio_info->display_name);
drivers/gpu/drm/amd/display/dc/dce/dce_audio.h
149
unsigned int inst,
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
282
EVENT_LOG_AUX_REQ(engine->inst, EVENT_LOG_AUX_ORIGIN_NATIVE,
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
601
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
612
aux_engine110->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
770
EVENT_LOG_AUX_REP(aux_engine->inst,
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
242
uint32_t inst;
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
289
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1003
REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1007
REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1011
REG_UPDATE(PIXEL_RATE_CNTL[inst],
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1016
REG_UPDATE(PIXEL_RATE_CNTL[inst],
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1079
unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1086
dto_params.otg_inst = inst;
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1213
unsigned int inst,
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1223
clock_hz = REG_READ(PHASE[inst]);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1230
modulo_hz = REG_READ(MODULO[inst]);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1250
static bool dcn401_get_dp_dto_frequency_100hz(const struct clock_source *clock_source, unsigned int inst,
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1260
phase_hz = REG_READ(PHASE[inst]);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1261
modulo_hz = REG_READ(MODULO[inst]);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1263
switch (inst) {
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1360
unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1370
REG_WRITE(MODULO[inst],
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1378
unsigned int inst,
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1384
REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 0);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1385
REG_WRITE(PHASE[inst], pixel_clk);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1386
REG_WRITE(MODULO[inst], ref_clk);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1387
REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1406
unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1415
REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1416
REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1419
REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1420
REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1424
REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1428
REG_UPDATE(PIXEL_RATE_CNTL[inst],
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
970
unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
989
REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
990
REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
993
REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
994
REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
999
REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
275
int inst,
drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
281
ipp_dce->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
293
int inst,
drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
299
ipp_dce->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h
271
int inst,
drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h
279
int inst,
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
1003
int inst,
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
1008
dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask);
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
959
int inst,
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
966
dce_mi->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
978
int inst,
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
983
dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask);
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
991
int inst,
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
996
dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask);
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
436
int inst,
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
445
int inst,
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
454
int inst,
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
462
int inst,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
727
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
736
opp110->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
746
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
755
opp110->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
316
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
324
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
292
dce_panel_cntl->base.inst = init_data->inst;
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1646
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1653
xfm_dce->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1675
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1682
xfm_dce->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dce/dce_transform.h
660
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.h
668
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
102
unsigned int inst)
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
106
feature_support = abm_feature_support(abm, inst);
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
109
dmub_abm_init_config(abm, src, bytes, inst);
drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c
162
unsigned int inst)
drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c
166
uint8_t panel_mask = 0x01 << inst;
drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.h
40
unsigned int inst);
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
344
copy_settings_data->dpp_inst = (uint8_t)pipe_ctx->plane_res.dpp->inst;
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
348
copy_settings_data->opp_inst = (uint8_t)pipe_ctx->stream_res.opp->inst;
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
352
copy_settings_data->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
154
copy_settings_data->dpp_inst = (uint8_t)pipe_ctx->plane_res.dpp->inst;
drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
159
copy_settings_data->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
203
params->inst,
drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
212
compressor->attached_inst = params->inst + CONTROLLER_ID_D0;
drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
267
uint32_t *inst)
drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
274
if (inst != NULL)
drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
275
*inst = compressor->attached_inst;
drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
284
if (inst != NULL)
drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
285
*inst =
drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
304
cp110->offsets = reg_offsets[params->inst];
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
1237
gsl_params->gsl_master == tg->inst,
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
2356
tg110->base.inst = instance;
drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c
396
params->inst,
drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c
402
compressor->attached_inst = params->inst;
drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c
403
cp110->offsets = reg_offsets[params->inst];
drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c
442
uint32_t *inst)
drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c
449
if (inst != NULL)
drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c
450
*inst = compressor->attached_inst;
drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c
459
if (inst != NULL)
drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c
460
*inst =
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
1269
tg110->base.inst = instance;
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
266
FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN), gsl_params->gsl_master == tg->inst,
drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
252
tg110->base.inst = instance;
drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
240
tg110->base.inst = instance;
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
121
int inst)
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
125
dwbc10->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
265
int inst);
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
51
#define DWBC_COMMON_REG_LIST_DCN1_0(inst) \
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
52
SRI(WB_ENABLE, CNV, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
53
SRI(WB_EC_CONFIG, CNV, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
54
SRI(CNV_MODE, CNV, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
55
SRI(WB_SOFT_RESET, CNV, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
56
SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
57
SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
58
SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
59
SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
60
SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
61
SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
62
SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
63
SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
64
SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
65
SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
66
SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
67
SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
68
SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
69
SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
70
SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
71
SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
72
SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
73
SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
74
SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
75
SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
76
SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
77
SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
78
SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
79
SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
80
SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
81
SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
82
SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst)
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
145
hubp->inst,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
164
hubp->inst,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
213
pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
261
pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
312
pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
353
dpp->inst, s.igam_input_format,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
442
tg->inst,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
61
int inst,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
67
ippn10->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
78
int inst,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
84
ippn10->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
211
int inst,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
218
int inst,
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
107
DC_LOG_DWB("%s inst = %d, FAILED!LUMA SCALING NOT SUPPORTED", __func__, dwbc20->base.inst);
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
110
DC_LOG_DWB("%s inst = %d, ENABLED", __func__, dwbc20->base.inst);
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
138
DC_LOG_DWB("%s inst = %d, Disabled", __func__, dwbc20->base.inst);
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
166
DC_LOG_DWB("%s inst = %d, FAILED!LUMA SCALING NOT SUPPORTED", __func__, dwbc20->base.inst);
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
169
DC_LOG_DWB("%s inst = %d, scaling", __func__, dwbc20->base.inst);
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
215
dwbc20->base.inst, stereo_params->stereo_enabled);
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
230
DC_LOG_DWB("%s inst = %d", __func__, dwbc20->base.inst);
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
239
DC_LOG_DWB("%s inst = %d", __func__, dwbc20->base.inst);
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
253
DC_LOG_DWB("%s inst = %d", __func__, dwbc20->base.inst);
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
332
int inst)
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
336
dwbc20->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
64
DC_LOG_DWB("%s SUPPORTED! inst = %d", __func__, dwbc20->base.inst);
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
67
DC_LOG_DWB("%s NOT SUPPORTED! inst = %d", __func__, dwbc20->base.inst);
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
75
DC_LOG_DWB("%s inst = %d", __func__, dwbc20->base.inst);
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
30
#define DWBC_COMMON_REG_LIST_DCN2_0(inst) \
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
31
SRI2_DWB(WB_ENABLE, CNV, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
32
SRI2_DWB(WB_EC_CONFIG, CNV, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
33
SRI2_DWB(CNV_MODE, CNV, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
34
SRI2_DWB(CNV_WINDOW_START, CNV, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
35
SRI2_DWB(CNV_WINDOW_SIZE, CNV, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
36
SRI2_DWB(CNV_UPDATE, CNV, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
37
SRI2_DWB(CNV_SOURCE_SIZE, CNV, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
38
SRI2_DWB(CNV_TEST_CNTL, CNV, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
39
SRI2_DWB(CNV_TEST_CRC_RED, CNV, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
40
SRI2_DWB(CNV_TEST_CRC_GREEN, CNV, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
400
int inst);
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
41
SRI2_DWB(CNV_TEST_CRC_BLUE, CNV, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
42
SRI2_DWB(WBSCL_COEF_RAM_SELECT, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
43
SRI2_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
44
SRI2_DWB(WBSCL_MODE, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
45
SRI2_DWB(WBSCL_TAP_CONTROL, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
46
SRI2_DWB(WBSCL_DEST_SIZE, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
47
SRI2_DWB(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
48
SRI2_DWB(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
49
SRI2_DWB(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
50
SRI2_DWB(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
51
SRI2_DWB(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
52
SRI2_DWB(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
53
SRI2_DWB(WBSCL_ROUND_OFFSET, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
54
SRI2_DWB(WBSCL_OVERFLOW_STATUS, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
55
SRI2_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
56
SRI2_DWB(WBSCL_TEST_CNTL, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
57
SRI2_DWB(WBSCL_TEST_CRC_RED, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
58
SRI2_DWB(WBSCL_TEST_CRC_GREEN, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
59
SRI2_DWB(WBSCL_TEST_CRC_BLUE, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
60
SRI2_DWB(WBSCL_BACKPRESSURE_CNT_EN, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
61
SRI2_DWB(WB_MCIF_BACKPRESSURE_CNT, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
62
SRI2_DWB(WBSCL_CLAMP_Y_RGB, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
63
SRI2_DWB(WBSCL_CLAMP_CBCR, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
64
SRI2_DWB(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
65
SRI2_DWB(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
66
SRI2_DWB(WBSCL_DEBUG, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
67
SRI2_DWB(WBSCL_TEST_DEBUG_INDEX, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
68
SRI2_DWB(WBSCL_TEST_DEBUG_DATA, WBSCL, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
69
SRI2_DWB(WB_DEBUG_CTRL, CNV, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
70
SRI2_DWB(WB_DBG_MODE, CNV, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
71
SRI2_DWB(WB_HW_DEBUG, CNV, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
72
SRI2_DWB(CNV_TEST_DEBUG_INDEX, CNV, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
73
SRI2_DWB(CNV_TEST_DEBUG_DATA, CNV, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
74
SRI2_DWB(WB_SOFT_RESET, CNV, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
75
SRI2_DWB(WB_WARM_UP_MODE_CTL1, CNV, inst),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
76
SRI2_DWB(WB_WARM_UP_MODE_CTL2, CNV, inst)
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.h
33
#define MPC_REG_LIST_DCN201(inst) \
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.h
34
MPC_REG_LIST_DCN2_0(inst)
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.h
36
#define MPC_OUT_MUX_REG_LIST_DCN201(inst) \
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.h
37
MPC_OUT_MUX_REG_LIST_DCN2_0(inst)
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.c
62
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.c
68
oppn201->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.h
68
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c
202
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c
209
afmt3->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.h
135
int inst;
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.h
165
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c
229
int inst)
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c
233
mcif_wb30->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
100
SRI2(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
101
SRI2(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
102
SRI2(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
103
SRI2(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
104
SRI2(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
105
SRI2(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
106
SRI2(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
107
SRI2(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
108
SRI2(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MMHUBBUB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
109
SRI2(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
110
SRI2(MCIF_WB_WATERMARK, MMHUBBUB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
111
SRI2(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
112
SRI2(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
113
SRI2(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
114
SRI2(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
115
SRI2(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
116
SRI2(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
117
SRI2(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
118
SRI2(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
119
SRI2(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
120
SRI2(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
121
SRI2(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
122
SRI2(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
123
SRI2(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
124
SRI2(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
125
SRI2(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
126
SRI2(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
127
SRI2(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
128
SRI2(MMHUBBUB_MEM_PWR_CNTL, MMHUBBUB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
129
SRI2(MMHUBBUB_WARMUP_ADDR_REGION, MMHUBBUB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
130
SRI2(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, MMHUBBUB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
131
SRI2(MMHUBBUB_WARMUP_BASE_ADDR_LOW, MMHUBBUB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
132
SRI2(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
133
SRI2(MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI, MCIF_WB, inst)
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
34
#define MCIF_WB_COMMON_REG_LIST_DCN3_0(inst) \
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
35
SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
36
SRI(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
37
SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
38
SRI(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
39
SRI(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
40
SRI(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
41
SRI(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
42
SRI(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
43
SRI(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
44
SRI(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
446
int inst);
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
45
SRI(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
46
SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
47
SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
48
SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
49
SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
50
SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
51
SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
52
SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
53
SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
54
SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
55
SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
56
SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
57
SRI2(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MMHUBBUB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
58
SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
59
SRI2(MCIF_WB_WATERMARK, MMHUBBUB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
60
SRI(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
61
SRI(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
62
SRI(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
63
SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
64
SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
65
SRI(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
66
SRI(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
67
SRI(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
68
SRI(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
69
SRI(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
70
SRI(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
71
SRI(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
72
SRI(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
73
SRI(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
74
SRI(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
75
SRI(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
76
SRI(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
77
SRI2(MMHUBBUB_MEM_PWR_CNTL, MMHUBBUB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
78
SRI2(MMHUBBUB_WARMUP_ADDR_REGION, MMHUBBUB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
79
SRI2(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, MMHUBBUB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
80
SRI2(MMHUBBUB_WARMUP_BASE_ADDR_LOW, MMHUBBUB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
81
SRI2(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
82
SRI2(MMHUBBUB_WARMUP_P_VMID, MMHUBBUB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
83
SRI(MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI, MCIF_WB, inst)
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
85
#define MCIF_WB_COMMON_REG_LIST_DCN30(inst) \
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
86
SRI2(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
87
SRI2(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
88
SRI2(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
89
SRI2(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
90
SRI2(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
91
SRI2(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
92
SRI2(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
93
SRI2(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
94
SRI2(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
95
SRI2(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
96
SRI2(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
97
SRI2(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
98
SRI2(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
99
SRI2(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c
251
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c
258
vpg3->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.h
151
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
217
dcn301_panel_cntl->base.inst = init_data->inst;
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c
79
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c
86
afmt31->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.h
121
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c
107
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c
114
apg31->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.h
118
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.h
87
int inst;
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
174
dcn31_panel_cntl->base.inst = init_data->inst;
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
198
dcn31_panel_cntl->base.pwrseq_inst = dcn31_panel_cntl->base.inst;
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c
79
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c
86
vpg31->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.h
158
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
901
enc1->base.stream_enc_inst = vpg->inst;
drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
506
enc1->base.stream_enc_inst = vpg->inst;
drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
493
enc1->base.stream_enc_inst = vpg->inst;
drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
519
enc1->base.stream_enc_inst = vpg->inst;
drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
795
enc1->base.stream_enc_inst = vpg->inst;
drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c
583
enc1->base.stream_enc_inst = vpg->inst;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
543
(uint8_t)pool->dpps[secondary_pipe->pipe_idx]->inst;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1415
(unsigned char)res_ctx->pipe_ctx[i].stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1862
sec_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[pipe_idx]->inst;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
1297
dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[current_pipe_context->stream_res.hpo_dp_stream_enc->inst] =
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
1298
current_pipe_context->link_res.hpo_dp_link_enc->inst;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c
260
ASSERT(pipe_ctx->stream_res.tg->inst <= 0xFF);
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c
261
pipe_ctx->pipe_dlg_param.otg_inst = (unsigned char)pipe_ctx->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
589
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
596
dpp->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
1522
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
416
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
423
dpp->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
777
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
300
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
307
dpp->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.h
78
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1539
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1546
dpp->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
582
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c
150
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c
157
dpp->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.h
33
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c
131
uint32_t inst, const struct dcn3_dpp_registers *tf_regs,
drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c
135
bool ret = dpp32_construct(dpp, ctx, inst, tf_regs,
drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h
58
uint32_t inst, const struct dcn3_dpp_registers *tf_regs,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
265
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
272
dpp->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
700
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c
326
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c
333
dpp->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.h
463
uint32_t inst,
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
197
DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
235
DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
240
DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
258
DC_LOG_DSC("disable DSC %d", dsc->inst);
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
262
DC_LOG_DSC("DSC %d already disabled!", dsc->inst);
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
283
DC_LOG_DSC("disconnect DSC %d", dsc->inst);
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
65
int inst,
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
71
dsc->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
596
int inst,
drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
63
int inst,
drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
69
dsc->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
86
DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);
drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
99
DC_LOG_DSC("ERROR: DSC %d at opp pipe %u already enabled!", dsc->inst, enabled_opp_pipe);
drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.h
52
int inst,
drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
136
DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);
drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
152
DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);
drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
157
DC_LOG_DSC("ERROR: DSC %d at opp pipe %u already enabled!", dsc->inst, enabled_opp_pipe);
drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
175
DC_LOG_DSC("disable DSC %d", dsc->inst);
drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
179
DC_LOG_DSC("DSC %d already disabled!", dsc->inst);
drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
200
DC_LOG_DSC("disconnect DSC %d", dsc->inst);
drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
50
int inst,
drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
56
dsc->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
330
int inst,
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
130
DC_LOG_DWB("%s dwb3_disabled at inst = %d", __func__, dwbc->inst);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
152
DC_LOG_DWB("%s dwb3_fc_disabled at inst = %d", __func__, dwbc->inst);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
168
DC_LOG_DWB("%s dwb update, inst = %d", __func__, dwbc->inst);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
263
int inst)
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
267
dwbc30->base.inst = inst;
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
95
DC_LOG_DWB("%s dwb3_enabled at inst = %d", __func__, dwbc->inst);
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
30
#define DWBC_COMMON_REG_LIST_DCN30(inst) \
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
882
int inst);
drivers/gpu/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.c
47
int inst)
drivers/gpu/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.c
51
(const struct dcn30_dwbc_mask *)dwbc_mask, inst);
drivers/gpu/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.h
57
int inst);
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_link_encoder.c
168
cntl.hpo_engine_id = enc3->base.inst + ENGINE_ID_HPO_0;
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_link_encoder.c
273
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_link_encoder.c
280
enc3->base.inst = inst;
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_link_encoder.h
141
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c
1042
enc3->base.stream_enc_inst = vpg->inst;
drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
533
cntl.hpo_engine_id = enc->inst + ENGINE_ID_HPO_DP_0;
drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
613
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
620
enc31->base.inst = inst;
drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h
185
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
715
switch (enc->inst) {
drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
767
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
777
enc3->base.inst = inst;
drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h
290
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.c
74
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.c
81
enc31->base.inst = inst;
drivers/gpu/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.h
60
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c
906
enc401->base.stream_enc_inst = vpg->inst;
drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.c
78
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.c
85
enc31->base.inst = inst;
drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.h
12
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_frl_stream_encoder.c
206
enc42->base.stream_enc_inst = vpg->inst;
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1408
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1418
hubp1->base.inst = inst;
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
933
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1712
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1722
hubp2->base.inst = inst;
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
320
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c
141
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c
151
hubp201->base.inst = inst;
drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
127
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
686
cmd.PLAT_54186_wa.flip.flip_params.hubp_inst = hubp->inst;
drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
847
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
857
hubp21->base.inst = inst;
drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
117
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
665
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
675
hubp2->base.inst = inst;
drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
252
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c
119
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c
129
hubp2->base.inst = inst;
drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
239
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
231
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
241
hubp2->base.inst = inst;
drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h
65
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c
228
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c
238
hubp2->base.inst = inst;
drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h
54
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
1084
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
1094
hubp2->base.inst = inst;
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
320
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
36
#define HUBP_3DLUT_FL_REG_LIST_DCN401(inst)\
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
37
SRI_ARR_US(_3DLUT_FL_CONFIG, HUBP, inst),\
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
38
SRI_ARR_US(_3DLUT_FL_BIAS_SCALE, HUBP, inst),\
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
39
SRI_ARR(HUBP_3DLUT_ADDRESS_HIGH, CURSOR0_, inst),\
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
40
SRI_ARR(HUBP_3DLUT_ADDRESS_LOW, CURSOR0_, inst),\
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
41
SRI_ARR(HUBP_3DLUT_CONTROL, CURSOR0_, inst),\
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
42
SRI_ARR(HUBP_3DLUT_DLG_PARAM, CURSOR0_, inst)
drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c
627
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c
637
hubp2->base.inst = inst;
drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h
75
uint32_t inst,
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c
60
val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst],
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c
71
REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c
76
REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c
82
uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]);
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c
83
REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value);
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
1291
unsigned int inst, bool enable);
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
61
#define HSWEQ_DCN_PIXEL_RATE_REG_LIST(blk, inst) \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
62
SRII(PIXEL_RATE_CNTL, blk, inst), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
63
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, inst)
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1239
dto_params.otg_inst = tg->inst;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1241
dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1244
dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst);
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1332
pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1558
pipe_ctx->stream_res.tg->inst + 1);
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1701
pipe_ctx->stream_res.audio->inst);
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1778
pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1989
dccg->funcs->set_ref_dscclk(dccg, dsc->inst);
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1994
pg_cntl->funcs->dsc_pg_control(pg_cntl, dsc->inst, false);
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2024
DC_LOG_DC("Enable OTG PWA frame sync on TG %d\n", tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2096
pipe_ctx->stream_res.tg->inst,
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2414
params.inst = pipe_ctx->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2802
dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2927
gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
3120
dce_enable_fe_clock(dc->hwseq, mi->inst, true);
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
3268
pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
3397
uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
3413
link->panel_cntl->inst);
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
3425
pipe_ctx->stream->link->panel_cntl->inst);
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
3435
uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
3438
abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst);
drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
128
params.inst = pipe_ctx->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
200
uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;
drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
286
dce_enable_fe_clock(dc->hwseq, mi->inst, true);
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1279
inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1393
pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1491
int dpp_id = pipe_ctx->plane_res.dpp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1544
hws->funcs.dpp_pg_control(hws, dpp->inst, false);
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1547
hws->funcs.hubp_pg_control(hws, hubp->inst, false);
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1555
"Power gated front end %d\n", hubp->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1559
hws->funcs.dpp_root_clock_control(hws, dpp->inst, false);
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1667
hubbub->funcs->program_det_size(hubbub, hubp->inst, 0);
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1669
hubbub->funcs->program_det_segments(hubbub, hubp->inst, 0);
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1720
pipe_ctx->plane_res.mpcc_inst = (uint8_t)dpp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1721
hubp->mpcc_id = dpp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1725
dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1800
hws->funcs.dsc_pg_control(hws, dc->res_pool->dscs[i]->inst, false);
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2301
inst_flags.opp_inst = (uint8_t)pipe->stream_res.opp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2309
pipe->stream_res.opp->inst, lock);
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2465
grouped_pipes[i]->stream_res.tg->inst,
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2500
grouped_pipes[i]->stream_res.tg->inst,
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2504
grouped_pipes[i]->stream_res.tg->inst, &pclk);
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2634
grouped_pipes[0]->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2792
pipe_ctx->plane_res.hubp->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2981
mpcc_id = hubp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3006
hubp->inst,
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3011
hubp->opp_id = pipe_ctx->stream_res.opp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3087
dpp->inst,
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3100
hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
315
hubp->inst,
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3161
pipe_ctx->stream_res.opp->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
349
pool->hubps[i]->inst,
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3601
if (res_pool->hubps[i]->inst == mpcc_inst)
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
385
pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
413
pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
443
pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
482
dpp->inst,
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
661
tg->inst,
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
698
dsc->inst,
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
836
hpo_dp_link_enc->inst,
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1002
int mpcc_id = pipe_ctx->plane_res.hubp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1025
int mpcc_id = pipe_ctx->plane_res.hubp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
104
dpp->inst,
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1190
int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1195
opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1284
hws->funcs.dpp_root_clock_control(hws, pipe_ctx->plane_res.dpp->inst, true);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1293
hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1296
hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1303
"Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1461
inst_flags.otg_inst = (uint8_t)pipe->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1692
dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1700
hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1964
dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1968
dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2136
dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2139
hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2226
is_dsc_ungated = dc->hwseq->funcs.dsc_pg_status(dc->hwseq, dsc->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2238
dccg->funcs->set_ref_dscclk(dccg, dsc->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2620
hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2622
hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2635
hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2637
hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2746
(uint8_t)pipe_ctx->plane_res.hubp->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2787
pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2805
pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2896
dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2914
pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2998
mpcc_id = hubp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3024
hubp->inst,
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3029
hubp->opp_id = pipe_ctx->stream_res.opp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3058
dto_params.otg_inst = tg->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3064
dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3065
dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3092
pipe_ctx->stream_res.tg->inst,
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3146
hubp->inst, mode);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3207
res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3224
pipe_ctx->plane_res.mpcc_inst = (uint8_t)dpp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3225
hubp->mpcc_id = dpp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
844
pipe_ctx->stream_res.tg->inst,
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
859
opp_inst[i] = opp_heads[i]->stream_res.opp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
889
dccg->funcs->set_dtbclk_p_src(dccg, DTBCLK0, tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
891
dto_params.otg_inst = tg->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
301
res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
318
pipe_ctx->plane_res.mpcc_inst = dpp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
319
hubp->mpcc_id = dpp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
384
int dpp_id = pipe_ctx->plane_res.dpp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
484
dpp_id = hubp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
524
hubp->opp_id = pipe_ctx->stream_res.opp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
181
uint32_t otg_inst = pipe_ctx->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
199
panel_cntl->inst, panel_cntl->pwrseq_inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
204
panel_cntl->inst,
drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
222
otg_inst = tg->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
233
panel_cntl->inst,
drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
238
panel_cntl->inst,
drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
257
otg_inst = tg->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
268
panel_cntl->inst,
drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
274
panel_cntl->inst,
drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
280
frame_ramp, 0, panel_cntl->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
282
dmub_abm_set_backlight(dc, backlight_pwm_u16_16, frame_ramp, panel_cntl->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
106
dpp->inst,
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
261
int mpcc_id = pipe_ctx->plane_res.hubp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
363
int mpcc_id = pipe_ctx->plane_res.hubp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
399
int mpcc_id = pipe_ctx->plane_res.hubp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
927
hubp->inst, dmdata_hdmi);
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
933
hubp->inst, mode);
drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
624
pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
655
dc->res_pool->hubbub, pipe_ctx_old->plane_res.hubp->inst, 0);
drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
658
dc->res_pool->hubbub, pipe_ctx_old->plane_res.hubp->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
733
otg_inst = tg->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
738
panel_cntl->inst,
drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
742
dmub_abm_set_backlight(dc, backlight_level_params, panel_cntl->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
114
dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
120
odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
128
DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
161
opp_instances[0] = odm_pipe->stream_res.opp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
166
opp_instances[opp_count] = odm_pipe->stream_res.opp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
393
&& pipe->stream_res.tg->inst == pipe->stream_res.stream_enc->funcs->dig_source_otg(pipe->stream_res.stream_enc)
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
437
int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst };
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
444
opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
90
DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
97
DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1057
DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1064
DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1082
dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1084
dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1092
dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1094
odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1098
DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1133
opp_instances[0] = odm_pipe->stream_res.opp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1138
opp_instances[opp_count] = odm_pipe->stream_res.opp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1295
int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst };
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1302
opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1342
pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1363
pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1548
bool is_dsc_ungated = hws->funcs.dsc_pg_status(hws, dsc->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1552
hws->funcs.dsc_pg_control(hws, dsc->inst, true);
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1556
hws->funcs.dsc_pg_control(hws, dsc->inst, false);
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1689
if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) {
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1703
if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src1) {
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
450
int mpcc_id = pipe_ctx->plane_res.hubp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
487
int mpcc_id = pipe_ctx->plane_res.hubp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
574
int mpcc_id = pipe_ctx->plane_res.hubp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1003
pipe_ctx->plane_res.hubp->inst != pipe_ctx->stream_res.dsc->inst) {
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1013
update_state->pg_pipe_res_update[PG_OPP][pipe_ctx->stream_res.opp->inst] = false;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1016
update_state->pg_pipe_res_update[PG_DPSTREAM][pipe_ctx->stream_res.hpo_dp_stream_enc->inst] = false;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1083
update_state->pg_pipe_res_update[j][new_pipe->plane_res.hubp->inst] = true;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1086
update_state->pg_pipe_res_update[j][new_pipe->plane_res.dpp->inst] = true;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1092
update_state->pg_pipe_res_update[j][new_pipe->stream_res.dsc->inst] = true;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1095
update_state->pg_pipe_res_update[j][new_pipe->stream_res.opp->inst] = true;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1098
update_state->pg_pipe_res_update[j][new_pipe->stream_res.tg->inst] = true;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1101
update_state->pg_pipe_res_update[j][new_pipe->stream_res.hpo_dp_stream_enc->inst] = true;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1110
update_state->pg_pipe_res_update[j][new_pipe->plane_res.hubp->inst] = true;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1115
update_state->pg_pipe_res_update[j][new_pipe->plane_res.dpp->inst] = true;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1120
update_state->pg_pipe_res_update[j][new_pipe->stream_res.opp->inst] = true;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1125
update_state->pg_pipe_res_update[j][new_pipe->stream_res.dsc->inst] = true;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1130
update_state->pg_pipe_res_update[j][new_pipe->stream_res.tg->inst] = true;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1135
update_state->pg_pipe_res_update[j][new_pipe->stream_res.hpo_dp_stream_enc->inst] = true;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1171
update_state->pg_pipe_res_update[PG_DSC][new_pipe->stream_res.dsc->inst]) {
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1172
update_state->pg_pipe_res_update[PG_HUBP][new_pipe->stream_res.dsc->inst] = true;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1173
update_state->pg_pipe_res_update[PG_DPP][new_pipe->stream_res.dsc->inst] = true;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1177
new_pipe->plane_res.hubp->inst != new_pipe->stream_res.dsc->inst) {
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
349
DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
356
DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
372
dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
378
odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
386
DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
419
opp_instances[0] = odm_pipe->stream_res.opp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
424
opp_instances[opp_count] = odm_pipe->stream_res.opp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
692
hubbub->funcs->program_det_size(hubbub, hubp->inst, 0);
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
694
hubbub->funcs->program_det_segments(hubbub, hubp->inst, 0);
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
745
pipe_ctx->plane_res.mpcc_inst = (uint8_t)dpp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
746
hubp->mpcc_id = dpp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
750
dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
828
pg_cntl->funcs->dsc_pg_control(pg_cntl, dc->res_pool->dscs[i]->inst, false);
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
987
update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->plane_res.hubp->inst] = false;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
990
update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->plane_res.hubp->inst] = false;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
996
update_state->pg_pipe_res_update[PG_DSC][pipe_ctx->stream_res.dsc->inst] = false;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
998
update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->stream_res.dsc->inst] = false;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
999
update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->stream_res.dsc->inst] = false;
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1020
dccg->funcs->set_dpstreamclk(dccg, DPREFCLK, tg->inst, dp_hpo_inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1037
pipe_ctx->stream_res.tg->inst,
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1665
opp_inst[i] = opp_heads[i]->stream_res.opp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1734
otg_master->stream_res.dsc->inst, num_slices_h);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1752
odm_pipe->stream_res.dsc->inst, num_slices_h);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1802
opp_inst[i] = opp_heads[i]->stream_res.opp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1851
pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1860
pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1920
hubbub->funcs->wait_for_det_update(hubbub, dpp_pipe->plane_res.hubp->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1924
hubbub->funcs->wait_for_det_update(hubbub, opp_heads[slice_idx]->plane_res.hubp->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2117
dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, REFCLK, pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2131
pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2144
DC_LOG_DC("otg frame sync pwa disabled on otg%d\n", tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2272
dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2275
dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2420
pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2425
pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2605
dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2608
hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3072
hws->funcs.dpp_pg_control(hws, dpp->inst, false);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3075
hws->funcs.hubp_pg_control(hws, hubp->inst, false);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3085
"Power gated front end %d\n", hubp->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3088
hws->funcs.dpp_root_clock_control(hws, dpp->inst, false);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3163
hwss_add_dpp_pg_control(seq_state, hws, dpp->inst, false);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3166
hwss_add_hubp_pg_control(seq_state, hws, hubp->inst, false);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3178
DC_LOG_DEBUG("Power gated front end %d\n", hubp->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3181
hwss_add_dpp_root_clock_control(seq_state, hws, dpp->inst, false);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3191
int dpp_id = pipe_ctx->plane_res.dpp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3602
hwss_add_dsc_pg_status(seq_state, dc->hwseq, dsc->inst, false);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3618
hwss_add_dccg_set_ref_dscclk(seq_state, dccg, dsc->inst, 0);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3646
hwss_add_dpp_root_clock_control(seq_state, hws, pipe_ctx->plane_res.dpp->inst, true);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3654
hwss_add_dpp_pg_control(seq_state, hws, pipe_ctx->plane_res.dpp->inst, true);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3658
hwss_add_hubp_pg_control(seq_state, hws, pipe_ctx->plane_res.hubp->inst, true);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3713
hwss_add_dccg_update_dpp_dto(seq_state, dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3717
hwss_add_hubp_vtg_sel(seq_state, hubp, pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3924
mpcc_id = hubp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3951
hwss_add_mpc_insert_plane(seq_state, mpc, mpc_tree_params, blnd_cfg, NULL, NULL, hubp->inst, mpcc_id);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3957
hubp->opp_id = pipe_ctx->stream_res.opp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
3966
if (res_pool->hubps[i]->inst == mpcc_inst)
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
416
int mpcc_id = pipe_ctx->plane_res.hubp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
448
int mpcc_id = hubp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
626
mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, hubp->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
656
int mpcc_id = pipe_ctx->plane_res.hubp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
710
int mpcc_id = pipe_ctx->plane_res.hubp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
780
opp_inst[i] = opp_heads[i]->stream_res.opp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
831
dc->res_pool->dccg, pipe_ctx->stream_res.tg->inst,
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
849
dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, DPREFCLK, pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
851
dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, DTBCLK0, pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
974
*dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
1006
update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->plane_res.hubp->inst] = false;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
1009
update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->plane_res.hubp->inst] = false;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
1015
update_state->pg_pipe_res_update[PG_DSC][pipe_ctx->stream_res.dsc->inst] = false;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
1017
update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->stream_res.dsc->inst] = false;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
1018
update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->stream_res.dsc->inst] = false;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
1022
update_state->pg_pipe_res_update[PG_OPP][pipe_ctx->stream_res.opp->inst] = false;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
1025
update_state->pg_pipe_res_update[PG_DPSTREAM][pipe_ctx->stream_res.hpo_dp_stream_enc->inst] = false;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
1130
update_state->pg_pipe_res_update[j][new_pipe->plane_res.hubp->inst] = true;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
1133
update_state->pg_pipe_res_update[j][new_pipe->plane_res.dpp->inst] = true;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
1139
update_state->pg_pipe_res_update[j][new_pipe->stream_res.dsc->inst] = true;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
1142
update_state->pg_pipe_res_update[j][new_pipe->stream_res.opp->inst] = true;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
1145
update_state->pg_pipe_res_update[j][new_pipe->stream_res.tg->inst] = true;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
1148
update_state->pg_pipe_res_update[j][new_pipe->stream_res.hpo_dp_stream_enc->inst] = true;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
1157
update_state->pg_pipe_res_update[j][new_pipe->plane_res.hubp->inst] = true;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
1162
update_state->pg_pipe_res_update[j][new_pipe->plane_res.dpp->inst] = true;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
1167
update_state->pg_pipe_res_update[j][new_pipe->stream_res.opp->inst] = true;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
1172
update_state->pg_pipe_res_update[j][new_pipe->stream_res.dsc->inst] = true;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
1177
update_state->pg_pipe_res_update[j][new_pipe->stream_res.tg->inst] = true;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
1182
update_state->pg_pipe_res_update[j][new_pipe->stream_res.hpo_dp_stream_enc->inst] = true;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
348
mpcc_id = hubp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
374
hubp->inst,
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
379
hubp->opp_id = pipe_ctx->stream_res.opp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
482
int mpcc_id = pipe_ctx->plane_res.hubp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
501
int mpcc_id = pipe_ctx->plane_res.hubp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
671
mpc_fl_config.hubp_index = hubp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
701
int mpcc_id = hubp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
878
mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, hubp->inst);
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
897
int mpcc_id = pipe_ctx->plane_res.hubp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c
100
hubbub->funcs->program_det_segments(hubbub, hubp->inst, 0);
drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c
155
pipe_ctx->plane_res.mpcc_inst = (uint8_t)dpp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c
156
hubp->mpcc_id = dpp->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c
160
dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c
235
hws->funcs.dsc_pg_control(hws, dc->res_pool->dscs[i]->inst, false);
drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c
98
hubbub->funcs->program_det_size(hubbub, hubp->inst, 0);
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
2042
struct dccg *dccg, int inst, int num_slices_h);
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
250
int inst;
drivers/gpu/drm/amd/display/dc/inc/clock_source.h
175
unsigned int inst,
drivers/gpu/drm/amd/display/dc/inc/clock_source.h
179
unsigned int inst,
drivers/gpu/drm/amd/display/dc/inc/compressor.h
50
uint32_t inst;
drivers/gpu/drm/amd/display/dc/inc/hw/abm.h
58
unsigned int inst);
drivers/gpu/drm/amd/display/dc/inc/hw/audio.h
62
unsigned int inst;
drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h
91
uint32_t inst;
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
82
#define CLK_BASE(inst) \
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
83
CLK_BASE_INNER(inst)
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
85
#define CLK_SRI(reg_name, block, inst)\
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
86
.reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
87
mm ## block ## _ ## inst ## _ ## reg_name
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
300
int inst);
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
304
int inst);
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
77
int inst;
drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
159
int inst;
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
122
int inst;
drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h
39
unsigned int inst;
drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
269
int inst;
drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
423
int inst;
drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h
71
int inst;
drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
87
int inst;
drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
237
uint32_t inst;
drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h
59
uint32_t inst;
drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h
66
uint32_t inst;
drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
527
uint32_t inst;
drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
325
uint32_t inst;
drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
41
int inst;
drivers/gpu/drm/amd/display/dc/inc/hw/vpg.h
50
int inst;
drivers/gpu/drm/amd/display/dc/inc/resource.h
87
struct dc_context *ctx, unsigned int inst);
drivers/gpu/drm/amd/display/dc/inc/resource.h
99
uint8_t inst,
drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
120
pipes[i]->stream_res.audio->inst);
drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
861
inst_flags.dig_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
909
inst_flags.dig_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
126
pipe_ctx->stream_res.tg->inst,
drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c
123
link_res->hpo_dp_link_enc->inst,
drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c
147
link_res->hpo_dp_link_enc->inst,
drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c
42
hpo_dp_stream_encoder->inst,
drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c
80
stream_enc->funcs->map_stream_to_link(stream_enc, stream_enc->inst, link_enc->inst);
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
1997
pipe_ctx->stream_res.tg->inst,
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
2016
pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
2021
pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
548
config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
572
config.link_enc_idx = (uint8_t)pipe_ctx->link_res.hpo_dp_link_enc->inst;
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
574
config.link_enc_idx = (uint8_t)pipe_ctx->stream->link->hpo_frl_link_enc->inst;
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
761
dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
763
dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
768
dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
770
odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
808
DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
867
dccg->funcs->set_ref_dscclk(dccg, odm_pipe->stream_res.dsc->inst);
drivers/gpu/drm/amd/display/dc/link/link_factory.c
774
panel_cntl_init_data.inst = panel_cntl_init_data.ctx->dc_edp_id_count;
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
133
dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst + 1;
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
222
*inst_out = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
309
cmd.pr_copy_settings.data.dpp_inst = (uint8_t)pipe_ctx->plane_res.dpp->inst;
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
313
cmd.pr_copy_settings.data.otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1038
dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst + 1;
drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1262
link_enc_index = (uint8_t)link_res->hpo_dp_link_enc->inst;
drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
806
pipe_ctx[i].stream_res.tg->inst + 1;
drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c
1020
pipe->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c
1025
pipe->stream_res.tg->inst);
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c
314
int inst)
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c
318
mcif_wb20->base.inst = inst;
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
32
#define MCIF_WB_COMMON_REG_LIST_DCN2_0(inst) \
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
33
SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
34
SRI(MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
35
SRI(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
36
SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
37
SRI(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
38
SRI(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
39
SRI(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
40
SRI(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
41
SRI(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
42
SRI(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
43
SRI(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
44
SRI(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
45
SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
46
SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
47
SRI(MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
48
SRI(MCIF_WB_TEST_DEBUG_DATA, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
49
SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
50
SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
51
SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
515
int inst);
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
52
SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
53
SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
54
SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
55
SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
56
SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
57
SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
58
SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
59
SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
60
SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
61
SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
62
SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
63
SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
64
SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
65
SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
66
SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
67
SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
68
SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
69
SRI(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
70
SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
71
SRI(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
72
SRI(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
73
SRI(MCIF_WB_SECURITY_LEVEL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
74
SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
75
SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
76
SRI(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
77
SRI(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
78
SRI(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
79
SRI(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
80
SRI(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
81
SRI(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
82
SRI(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
83
SRI(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
84
SRI(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
85
SRI(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
86
SRI(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
87
SRI(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
88
SRI(SMU_WM_CONTROL, WBIF, inst)
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c
229
int inst)
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c
233
mcif_wb30->base.inst = inst;
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
209
int inst);
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
32
#define MCIF_WB_COMMON_REG_LIST_DCN32(inst) \
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
33
SRI2(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
34
SRI2(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
35
SRI2(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
36
SRI2(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
37
SRI2(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
38
SRI2(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
39
SRI2(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
40
SRI2(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
41
SRI2(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
42
SRI2(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
43
SRI2(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
44
SRI2(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
45
SRI2(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
46
SRI2(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
47
SRI2(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
48
SRI2(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
49
SRI2(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
50
SRI2(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
51
SRI2(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
52
SRI2(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
53
SRI2(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
54
SRI2(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
55
SRI2(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MMHUBBUB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
56
SRI2(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
57
SRI2(MCIF_WB_WATERMARK, MMHUBBUB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
58
SRI2(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
59
SRI2(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
60
SRI2(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
61
SRI2(MCIF_WB_SECURITY_LEVEL, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
62
SRI2(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
63
SRI2(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
64
SRI2(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
65
SRI2(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
66
SRI2(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
67
SRI2(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
68
SRI2(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
69
SRI2(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
70
SRI2(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
71
SRI2(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
72
SRI2(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
73
SRI2(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
74
SRI2(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
75
SRI2(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
76
SRI2(MMHUBBUB_MEM_PWR_CNTL, MMHUBBUB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
77
SRI2(MMHUBBUB_WARMUP_ADDR_REGION, MMHUBBUB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
78
SRI2(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, MMHUBBUB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
79
SRI2(MMHUBBUB_WARMUP_BASE_ADDR_LOW, MMHUBBUB, inst),\
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
80
SRI2(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB, inst)
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.c
47
const struct dcn35_mmhubbub_mask *mcif_wb_mask, int inst)
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.c
53
(const struct dcn30_mmhubbub_mask *)(mcif_wb_mask), inst);
drivers/gpu/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.h
71
const struct dcn35_mmhubbub_mask *mcif_wb_mask, int inst);
drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
33
#define MPC_COMMON_REG_LIST_DCN1_0(inst) \
drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
34
SRII(MPCC_TOP_SEL, MPCC, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
35
SRII(MPCC_BOT_SEL, MPCC, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
36
SRII(MPCC_CONTROL, MPCC, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
37
SRII(MPCC_STATUS, MPCC, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
38
SRII(MPCC_OPP_ID, MPCC, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
39
SRII(MPCC_BG_G_Y, MPCC, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
40
SRII(MPCC_BG_R_CR, MPCC, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
41
SRII(MPCC_BG_B_CB, MPCC, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
42
SRII(MPCC_SM_CONTROL, MPCC, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
43
SRII(MPCC_UPDATE_LOCK_SEL, MPCC, inst)
drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
45
#define MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst) \
drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
46
SRII(MUX, MPC_OUT, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
47
VUPDATE_SRII(CUR, VUPDATE_LOCK_SET, inst)
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
33
#define MPC_REG_LIST_DCN2_0(inst)\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
34
MPC_COMMON_REG_LIST_DCN1_0(inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
35
SRII(MPCC_TOP_GAIN, MPCC, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
36
SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
37
SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
38
SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
39
SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
40
SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
41
SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
42
SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_G, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
43
SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_R, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
44
SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
45
SRII(MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
46
SRII(MPCC_OGAM_RAMA_END_CNTL1_G, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
47
SRII(MPCC_OGAM_RAMA_END_CNTL2_G, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
48
SRII(MPCC_OGAM_RAMA_END_CNTL1_R, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
49
SRII(MPCC_OGAM_RAMA_END_CNTL2_R, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
50
SRII(MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
51
SRII(MPCC_OGAM_RAMA_REGION_32_33, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
52
SRII(MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
53
SRII(MPCC_OGAM_RAMB_START_CNTL_G, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
54
SRII(MPCC_OGAM_RAMB_START_CNTL_R, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
55
SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_B, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
56
SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_G, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
57
SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_R, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
58
SRII(MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
59
SRII(MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
60
SRII(MPCC_OGAM_RAMB_END_CNTL1_G, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
61
SRII(MPCC_OGAM_RAMB_END_CNTL2_G, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
62
SRII(MPCC_OGAM_RAMB_END_CNTL1_R, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
63
SRII(MPCC_OGAM_RAMB_END_CNTL2_R, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
64
SRII(MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
65
SRII(MPCC_OGAM_RAMB_REGION_32_33, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
66
SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
67
SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
68
SRII(MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
69
SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
70
SRII(MPCC_OGAM_MODE, MPCC_OGAM, inst)
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
72
#define MPC_OUT_MUX_REG_LIST_DCN2_0(inst) \
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
73
MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
74
SRII(CSC_MODE, MPC_OUT, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
75
SRII(CSC_C11_C12_A, MPC_OUT, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
76
SRII(CSC_C33_C34_A, MPC_OUT, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
77
SRII(CSC_C11_C12_B, MPC_OUT, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
78
SRII(CSC_C33_C34_B, MPC_OUT, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
79
SRII(DENORM_CONTROL, MPC_OUT, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
80
SRII(DENORM_CLAMP_G_Y, MPC_OUT, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
81
SRII(DENORM_CLAMP_B_CB, MPC_OUT, inst)
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
100
SRII(MPCC_OGAM_LUT_CONTROL, MPCC_OGAM, inst)
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
102
#define MPC_OUT_MUX_REG_LIST_DCN3_0(inst) \
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
103
MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
104
SRII(CSC_MODE, MPC_OUT, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
105
SRII(CSC_C11_C12_A, MPC_OUT, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
106
SRII(CSC_C33_C34_A, MPC_OUT, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
107
SRII(CSC_C11_C12_B, MPC_OUT, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
108
SRII(CSC_C33_C34_B, MPC_OUT, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
109
SRII(DENORM_CONTROL, MPC_OUT, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
110
SRII(DENORM_CLAMP_G_Y, MPC_OUT, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
111
SRII(DENORM_CLAMP_B_CB, MPC_OUT, inst), \
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
118
#define MPC_RMU_REG_LIST_DCN3AG(inst) \
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
119
SRII(SHAPER_CONTROL, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
120
SRII(SHAPER_OFFSET_R, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
121
SRII(SHAPER_OFFSET_G, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
122
SRII(SHAPER_OFFSET_B, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
123
SRII(SHAPER_SCALE_R, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
124
SRII(SHAPER_SCALE_G_B, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
125
SRII(SHAPER_LUT_INDEX, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
126
SRII(SHAPER_LUT_DATA, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
127
SRII(SHAPER_LUT_WRITE_EN_MASK, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
128
SRII(SHAPER_RAMA_START_CNTL_B, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
129
SRII(SHAPER_RAMA_START_CNTL_G, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
130
SRII(SHAPER_RAMA_START_CNTL_R, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
131
SRII(SHAPER_RAMA_END_CNTL_B, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
132
SRII(SHAPER_RAMA_END_CNTL_G, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
133
SRII(SHAPER_RAMA_END_CNTL_R, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
134
SRII(SHAPER_RAMA_REGION_0_1, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
135
SRII(SHAPER_RAMA_REGION_2_3, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
136
SRII(SHAPER_RAMA_REGION_4_5, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
137
SRII(SHAPER_RAMA_REGION_6_7, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
138
SRII(SHAPER_RAMA_REGION_8_9, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
139
SRII(SHAPER_RAMA_REGION_10_11, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
140
SRII(SHAPER_RAMA_REGION_12_13, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
141
SRII(SHAPER_RAMA_REGION_14_15, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
142
SRII(SHAPER_RAMA_REGION_16_17, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
143
SRII(SHAPER_RAMA_REGION_18_19, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
144
SRII(SHAPER_RAMA_REGION_20_21, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
145
SRII(SHAPER_RAMA_REGION_22_23, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
146
SRII(SHAPER_RAMA_REGION_24_25, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
147
SRII(SHAPER_RAMA_REGION_26_27, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
148
SRII(SHAPER_RAMA_REGION_28_29, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
149
SRII(SHAPER_RAMA_REGION_30_31, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
150
SRII(SHAPER_RAMA_REGION_32_33, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
151
SRII(SHAPER_RAMB_START_CNTL_B, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
152
SRII(SHAPER_RAMB_START_CNTL_G, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
153
SRII(SHAPER_RAMB_START_CNTL_R, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
154
SRII(SHAPER_RAMB_END_CNTL_B, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
155
SRII(SHAPER_RAMB_END_CNTL_G, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
156
SRII(SHAPER_RAMB_END_CNTL_R, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
157
SRII(SHAPER_RAMB_REGION_0_1, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
158
SRII(SHAPER_RAMB_REGION_2_3, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
159
SRII(SHAPER_RAMB_REGION_4_5, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
160
SRII(SHAPER_RAMB_REGION_6_7, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
161
SRII(SHAPER_RAMB_REGION_8_9, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
162
SRII(SHAPER_RAMB_REGION_10_11, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
163
SRII(SHAPER_RAMB_REGION_12_13, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
164
SRII(SHAPER_RAMB_REGION_14_15, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
165
SRII(SHAPER_RAMB_REGION_16_17, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
166
SRII(SHAPER_RAMB_REGION_18_19, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
167
SRII(SHAPER_RAMB_REGION_20_21, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
168
SRII(SHAPER_RAMB_REGION_22_23, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
169
SRII(SHAPER_RAMB_REGION_24_25, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
170
SRII(SHAPER_RAMB_REGION_26_27, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
171
SRII(SHAPER_RAMB_REGION_28_29, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
172
SRII(SHAPER_RAMB_REGION_30_31, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
173
SRII(SHAPER_RAMB_REGION_32_33, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
174
SRII_MPC_RMU(3DLUT_MODE, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
175
SRII_MPC_RMU(3DLUT_INDEX, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
176
SRII_MPC_RMU(3DLUT_DATA, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
177
SRII_MPC_RMU(3DLUT_DATA_30BIT, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
178
SRII_MPC_RMU(3DLUT_READ_WRITE_CONTROL, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
179
SRII_MPC_RMU(3DLUT_OUT_NORM_FACTOR, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
180
SRII_MPC_RMU(3DLUT_OUT_OFFSET_R, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
181
SRII_MPC_RMU(3DLUT_OUT_OFFSET_G, MPC_RMU, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
182
SRII_MPC_RMU(3DLUT_OUT_OFFSET_B, MPC_RMU, inst)
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
185
#define MPC_DWB_MUX_REG_LIST_DCN3_0(inst) \
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
186
SRII_DWB(DWB_MUX, MUX, MPC_DWB, inst)
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
45
#define MPC_REG_LIST_DCN3_0(inst)\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
46
MPC_COMMON_REG_LIST_DCN1_0(inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
47
SRII(MPCC_TOP_GAIN, MPCC, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
48
SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
49
SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
50
SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
51
SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
52
SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
53
SRII(MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
54
SRII(MPCC_GAMUT_REMAP_MODE, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
55
SRII(MPC_GAMUT_REMAP_C11_C12_A, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
56
SRII(MPC_GAMUT_REMAP_C33_C34_A, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
57
SRII(MPC_GAMUT_REMAP_C11_C12_B, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
58
SRII(MPC_GAMUT_REMAP_C33_C34_B, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
59
SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
60
SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
61
SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
62
SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
63
SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_G, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
64
SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_R, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
65
SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
66
SRII(MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
67
SRII(MPCC_OGAM_RAMA_END_CNTL1_G, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
68
SRII(MPCC_OGAM_RAMA_END_CNTL2_G, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
69
SRII(MPCC_OGAM_RAMA_END_CNTL1_R, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
70
SRII(MPCC_OGAM_RAMA_END_CNTL2_R, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
71
SRII(MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
72
SRII(MPCC_OGAM_RAMA_REGION_32_33, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
73
SRII(MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
74
SRII(MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
75
SRII(MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
76
SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
77
SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_G, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
78
SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_R, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
79
SRII(MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
80
SRII(MPCC_OGAM_RAMB_START_CNTL_G, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
81
SRII(MPCC_OGAM_RAMB_START_CNTL_R, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
82
SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_B, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
83
SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_G, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
84
SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_R, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
85
SRII(MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
86
SRII(MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
87
SRII(MPCC_OGAM_RAMB_END_CNTL1_G, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
88
SRII(MPCC_OGAM_RAMB_END_CNTL2_G, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
89
SRII(MPCC_OGAM_RAMB_END_CNTL1_R, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
90
SRII(MPCC_OGAM_RAMB_END_CNTL2_R, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
91
SRII(MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
92
SRII(MPCC_OGAM_RAMB_REGION_32_33, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
93
SRII(MPCC_OGAM_RAMB_OFFSET_B, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
94
SRII(MPCC_OGAM_RAMB_OFFSET_G, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
95
SRII(MPCC_OGAM_RAMB_OFFSET_R, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
96
SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_B, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
97
SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_G, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
98
SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_R, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
99
SRII(MPCC_OGAM_CONTROL, MPCC_OGAM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
100
SRII(MPCC_MCM_3DLUT_OUT_OFFSET_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
101
SRII(MPCC_MCM_1DLUT_CONTROL, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
102
SRII(MPCC_MCM_1DLUT_LUT_INDEX, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
103
SRII(MPCC_MCM_1DLUT_LUT_DATA, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
104
SRII(MPCC_MCM_1DLUT_LUT_CONTROL, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
105
SRII(MPCC_MCM_1DLUT_RAMA_START_CNTL_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
106
SRII(MPCC_MCM_1DLUT_RAMA_START_CNTL_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
107
SRII(MPCC_MCM_1DLUT_RAMA_START_CNTL_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
108
SRII(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
109
SRII(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
110
SRII(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
111
SRII(MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
112
SRII(MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
113
SRII(MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
114
SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL1_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
115
SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL2_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
116
SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL1_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
117
SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL2_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
118
SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL1_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
119
SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL2_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
120
SRII(MPCC_MCM_1DLUT_RAMA_OFFSET_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
121
SRII(MPCC_MCM_1DLUT_RAMA_OFFSET_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
122
SRII(MPCC_MCM_1DLUT_RAMA_OFFSET_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
123
SRII(MPCC_MCM_1DLUT_RAMA_REGION_0_1, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
124
SRII(MPCC_MCM_1DLUT_RAMA_REGION_2_3, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
125
SRII(MPCC_MCM_1DLUT_RAMA_REGION_4_5, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
126
SRII(MPCC_MCM_1DLUT_RAMA_REGION_6_7, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
127
SRII(MPCC_MCM_1DLUT_RAMA_REGION_8_9, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
128
SRII(MPCC_MCM_1DLUT_RAMA_REGION_10_11, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
129
SRII(MPCC_MCM_1DLUT_RAMA_REGION_12_13, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
130
SRII(MPCC_MCM_1DLUT_RAMA_REGION_14_15, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
131
SRII(MPCC_MCM_1DLUT_RAMA_REGION_16_17, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
132
SRII(MPCC_MCM_1DLUT_RAMA_REGION_18_19, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
133
SRII(MPCC_MCM_1DLUT_RAMA_REGION_20_21, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
134
SRII(MPCC_MCM_1DLUT_RAMA_REGION_22_23, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
135
SRII(MPCC_MCM_1DLUT_RAMA_REGION_24_25, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
136
SRII(MPCC_MCM_1DLUT_RAMA_REGION_26_27, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
137
SRII(MPCC_MCM_1DLUT_RAMA_REGION_28_29, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
138
SRII(MPCC_MCM_1DLUT_RAMA_REGION_30_31, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
139
SRII(MPCC_MCM_1DLUT_RAMA_REGION_32_33, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
140
SRII(MPCC_MCM_1DLUT_RAMB_START_CNTL_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
141
SRII(MPCC_MCM_1DLUT_RAMB_START_CNTL_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
142
SRII(MPCC_MCM_1DLUT_RAMB_START_CNTL_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
143
SRII(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
144
SRII(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
145
SRII(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
146
SRII(MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
147
SRII(MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
148
SRII(MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
149
SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL1_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
150
SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL2_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
151
SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL1_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
152
SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL2_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
153
SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL1_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
154
SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL2_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
155
SRII(MPCC_MCM_1DLUT_RAMB_OFFSET_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
156
SRII(MPCC_MCM_1DLUT_RAMB_OFFSET_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
157
SRII(MPCC_MCM_1DLUT_RAMB_OFFSET_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
158
SRII(MPCC_MCM_1DLUT_RAMB_REGION_0_1, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
159
SRII(MPCC_MCM_1DLUT_RAMB_REGION_2_3, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
160
SRII(MPCC_MCM_1DLUT_RAMB_REGION_4_5, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
161
SRII(MPCC_MCM_1DLUT_RAMB_REGION_6_7, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
162
SRII(MPCC_MCM_1DLUT_RAMB_REGION_8_9, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
163
SRII(MPCC_MCM_1DLUT_RAMB_REGION_10_11, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
164
SRII(MPCC_MCM_1DLUT_RAMB_REGION_12_13, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
165
SRII(MPCC_MCM_1DLUT_RAMB_REGION_14_15, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
166
SRII(MPCC_MCM_1DLUT_RAMB_REGION_16_17, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
167
SRII(MPCC_MCM_1DLUT_RAMB_REGION_18_19, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
168
SRII(MPCC_MCM_1DLUT_RAMB_REGION_20_21, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
169
SRII(MPCC_MCM_1DLUT_RAMB_REGION_22_23, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
170
SRII(MPCC_MCM_1DLUT_RAMB_REGION_24_25, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
171
SRII(MPCC_MCM_1DLUT_RAMB_REGION_26_27, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
172
SRII(MPCC_MCM_1DLUT_RAMB_REGION_28_29, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
173
SRII(MPCC_MCM_1DLUT_RAMB_REGION_30_31, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
174
SRII(MPCC_MCM_1DLUT_RAMB_REGION_32_33, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
175
SRII(MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM, inst)
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
34
#define MPC_REG_LIST_DCN3_2(inst) \
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
35
MPC_REG_LIST_DCN3_0(inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
36
SRII(MPCC_MOVABLE_CM_LOCATION_CONTROL, MPCC, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
37
SRII(MPCC_MCM_SHAPER_CONTROL, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
38
SRII(MPCC_MCM_SHAPER_OFFSET_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
39
SRII(MPCC_MCM_SHAPER_OFFSET_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
40
SRII(MPCC_MCM_SHAPER_OFFSET_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
41
SRII(MPCC_MCM_SHAPER_SCALE_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
42
SRII(MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
43
SRII(MPCC_MCM_SHAPER_LUT_INDEX, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
44
SRII(MPCC_MCM_SHAPER_LUT_DATA, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
45
SRII(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
46
SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
47
SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
48
SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
49
SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
50
SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
51
SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
52
SRII(MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
53
SRII(MPCC_MCM_SHAPER_RAMA_REGION_2_3, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
54
SRII(MPCC_MCM_SHAPER_RAMA_REGION_4_5, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
55
SRII(MPCC_MCM_SHAPER_RAMA_REGION_6_7, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
56
SRII(MPCC_MCM_SHAPER_RAMA_REGION_8_9, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
57
SRII(MPCC_MCM_SHAPER_RAMA_REGION_10_11, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
58
SRII(MPCC_MCM_SHAPER_RAMA_REGION_12_13, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
59
SRII(MPCC_MCM_SHAPER_RAMA_REGION_14_15, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
60
SRII(MPCC_MCM_SHAPER_RAMA_REGION_16_17, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
61
SRII(MPCC_MCM_SHAPER_RAMA_REGION_18_19, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
62
SRII(MPCC_MCM_SHAPER_RAMA_REGION_20_21, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
63
SRII(MPCC_MCM_SHAPER_RAMA_REGION_22_23, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
64
SRII(MPCC_MCM_SHAPER_RAMA_REGION_24_25, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
65
SRII(MPCC_MCM_SHAPER_RAMA_REGION_26_27, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
66
SRII(MPCC_MCM_SHAPER_RAMA_REGION_28_29, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
67
SRII(MPCC_MCM_SHAPER_RAMA_REGION_30_31, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
68
SRII(MPCC_MCM_SHAPER_RAMA_REGION_32_33, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
69
SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
70
SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
71
SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
72
SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
73
SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
74
SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
75
SRII(MPCC_MCM_SHAPER_RAMB_REGION_0_1, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
76
SRII(MPCC_MCM_SHAPER_RAMB_REGION_2_3, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
77
SRII(MPCC_MCM_SHAPER_RAMB_REGION_4_5, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
78
SRII(MPCC_MCM_SHAPER_RAMB_REGION_6_7, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
79
SRII(MPCC_MCM_SHAPER_RAMB_REGION_8_9, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
80
SRII(MPCC_MCM_SHAPER_RAMB_REGION_10_11, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
81
SRII(MPCC_MCM_SHAPER_RAMB_REGION_12_13, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
82
SRII(MPCC_MCM_SHAPER_RAMB_REGION_14_15, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
83
SRII(MPCC_MCM_SHAPER_RAMB_REGION_16_17, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
84
SRII(MPCC_MCM_SHAPER_RAMB_REGION_18_19, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
85
SRII(MPCC_MCM_SHAPER_RAMB_REGION_20_21, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
86
SRII(MPCC_MCM_SHAPER_RAMB_REGION_22_23, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
87
SRII(MPCC_MCM_SHAPER_RAMB_REGION_24_25, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
88
SRII(MPCC_MCM_SHAPER_RAMB_REGION_26_27, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
89
SRII(MPCC_MCM_SHAPER_RAMB_REGION_28_29, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
90
SRII(MPCC_MCM_SHAPER_RAMB_REGION_30_31, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
91
SRII(MPCC_MCM_SHAPER_RAMB_REGION_32_33, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
92
SRII(MPCC_MCM_3DLUT_MODE, MPCC_MCM, inst), /*TODO: may need to add other 3DLUT regs*/\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
93
SRII(MPCC_MCM_3DLUT_INDEX, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
94
SRII(MPCC_MCM_3DLUT_DATA, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
95
SRII(MPCC_MCM_3DLUT_DATA_30BIT, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
96
SRII(MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
97
SRII(MPCC_MCM_3DLUT_OUT_NORM_FACTOR, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
98
SRII(MPCC_MCM_3DLUT_OUT_OFFSET_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
99
SRII(MPCC_MCM_3DLUT_OUT_OFFSET_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
106
#define MPC_REG_LIST_DCN4_01_RI(inst) \
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
107
MPC_REG_LIST_DCN3_2_RI(inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
108
SRII(MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
109
SRII(MPCC_MCM_FIRST_GAMUT_REMAP_MODE, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
110
SRII(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
111
SRII(MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
112
SRII(MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
113
SRII(MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
114
SRII(MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
115
SRII(MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
116
SRII(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
117
SRII(MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
118
SRII(MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
119
SRII(MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
120
SRII(MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
121
SRII(MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
122
SRII(MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT, MPCC_MCM, inst), \
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
123
SRII(MPCC_MCM_SECOND_GAMUT_REMAP_MODE, MPCC_MCM, inst), \
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
124
SRII(MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A, MPCC_MCM, inst), \
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
125
SRII(MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A, MPCC_MCM, inst), \
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
126
SRII(MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A, MPCC_MCM, inst), \
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
127
SRII(MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A, MPCC_MCM, inst), \
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
128
SRII(MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A, MPCC_MCM, inst), \
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
129
SRII(MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A, MPCC_MCM, inst), \
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
130
SRII(MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B, MPCC_MCM, inst), \
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
131
SRII(MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B, MPCC_MCM, inst), \
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
132
SRII(MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B, MPCC_MCM, inst), \
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
133
SRII(MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B, MPCC_MCM, inst), \
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
134
SRII(MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B, MPCC_MCM, inst), \
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
135
SRII(MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B, MPCC_MCM, inst), \
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
136
SRII(MPCC_MCM_3DLUT_FAST_LOAD_STATUS, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
137
SRII(MPCC_MCM_3DLUT_FAST_LOAD_SELECT, MPCC_MCM, inst)
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
434
#define MPC_RMCM_REG_LIST_DCN42(inst)\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
435
SRII(MPC_RMCM_SHAPER_CONTROL, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
436
SRII(MPC_RMCM_SHAPER_OFFSET_R, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
437
SRII(MPC_RMCM_SHAPER_OFFSET_G, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
438
SRII(MPC_RMCM_SHAPER_OFFSET_B, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
439
SRII(MPC_RMCM_SHAPER_SCALE_R, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
440
SRII(MPC_RMCM_SHAPER_SCALE_G_B, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
441
SRII(MPC_RMCM_SHAPER_LUT_INDEX, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
442
SRII(MPC_RMCM_SHAPER_LUT_DATA, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
443
SRII(MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
444
SRII(MPC_RMCM_SHAPER_RAMA_START_CNTL_B, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
445
SRII(MPC_RMCM_SHAPER_RAMA_START_CNTL_G, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
446
SRII(MPC_RMCM_SHAPER_RAMA_START_CNTL_R, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
447
SRII(MPC_RMCM_SHAPER_RAMA_END_CNTL_B, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
448
SRII(MPC_RMCM_SHAPER_RAMA_END_CNTL_G, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
449
SRII(MPC_RMCM_SHAPER_RAMA_END_CNTL_R, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
450
SRII(MPC_RMCM_SHAPER_RAMA_REGION_0_1, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
451
SRII(MPC_RMCM_SHAPER_RAMA_REGION_2_3, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
452
SRII(MPC_RMCM_SHAPER_RAMA_REGION_4_5, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
453
SRII(MPC_RMCM_SHAPER_RAMA_REGION_6_7, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
454
SRII(MPC_RMCM_SHAPER_RAMA_REGION_8_9, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
455
SRII(MPC_RMCM_SHAPER_RAMA_REGION_10_11, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
456
SRII(MPC_RMCM_SHAPER_RAMA_REGION_12_13, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
457
SRII(MPC_RMCM_SHAPER_RAMA_REGION_14_15, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
458
SRII(MPC_RMCM_SHAPER_RAMA_REGION_16_17, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
459
SRII(MPC_RMCM_SHAPER_RAMA_REGION_18_19, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
460
SRII(MPC_RMCM_SHAPER_RAMA_REGION_20_21, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
461
SRII(MPC_RMCM_SHAPER_RAMA_REGION_22_23, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
462
SRII(MPC_RMCM_SHAPER_RAMA_REGION_24_25, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
463
SRII(MPC_RMCM_SHAPER_RAMA_REGION_26_27, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
464
SRII(MPC_RMCM_SHAPER_RAMA_REGION_28_29, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
465
SRII(MPC_RMCM_SHAPER_RAMA_REGION_30_31, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
466
SRII(MPC_RMCM_SHAPER_RAMA_REGION_32_33, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
467
SRII(MPC_RMCM_SHAPER_RAMB_START_CNTL_B, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
468
SRII(MPC_RMCM_SHAPER_RAMB_START_CNTL_G, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
469
SRII(MPC_RMCM_SHAPER_RAMB_START_CNTL_R, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
470
SRII(MPC_RMCM_SHAPER_RAMB_END_CNTL_B, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
471
SRII(MPC_RMCM_SHAPER_RAMB_END_CNTL_G, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
472
SRII(MPC_RMCM_SHAPER_RAMB_END_CNTL_R, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
473
SRII(MPC_RMCM_SHAPER_RAMB_REGION_0_1, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
474
SRII(MPC_RMCM_SHAPER_RAMB_REGION_2_3, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
475
SRII(MPC_RMCM_SHAPER_RAMB_REGION_4_5, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
476
SRII(MPC_RMCM_SHAPER_RAMB_REGION_6_7, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
477
SRII(MPC_RMCM_SHAPER_RAMB_REGION_8_9, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
478
SRII(MPC_RMCM_SHAPER_RAMB_REGION_10_11, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
479
SRII(MPC_RMCM_SHAPER_RAMB_REGION_12_13, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
480
SRII(MPC_RMCM_SHAPER_RAMB_REGION_14_15, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
481
SRII(MPC_RMCM_SHAPER_RAMB_REGION_16_17, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
482
SRII(MPC_RMCM_SHAPER_RAMB_REGION_18_19, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
483
SRII(MPC_RMCM_SHAPER_RAMB_REGION_20_21, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
484
SRII(MPC_RMCM_SHAPER_RAMB_REGION_22_23, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
485
SRII(MPC_RMCM_SHAPER_RAMB_REGION_24_25, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
486
SRII(MPC_RMCM_SHAPER_RAMB_REGION_26_27, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
487
SRII(MPC_RMCM_SHAPER_RAMB_REGION_28_29, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
488
SRII(MPC_RMCM_SHAPER_RAMB_REGION_30_31, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
489
SRII(MPC_RMCM_SHAPER_RAMB_REGION_32_33, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
490
SRII(MPC_RMCM_3DLUT_MODE, MPC_RMCM, inst), /*TODO: may need to add other 3DLUT regs*/\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
491
SRII(MPC_RMCM_3DLUT_INDEX, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
492
SRII(MPC_RMCM_3DLUT_DATA, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
493
SRII(MPC_RMCM_3DLUT_DATA_30BIT, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
494
SRII(MPC_RMCM_3DLUT_READ_WRITE_CONTROL, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
495
SRII(MPC_RMCM_3DLUT_OUT_NORM_FACTOR, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
496
SRII(MPC_RMCM_3DLUT_OUT_OFFSET_R, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
497
SRII(MPC_RMCM_3DLUT_OUT_OFFSET_G, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
498
SRII(MPC_RMCM_3DLUT_OUT_OFFSET_B, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
499
SRII(MPC_RMCM_GAMUT_REMAP_COEF_FORMAT, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
500
SRII(MPC_RMCM_GAMUT_REMAP_MODE, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
501
SRII(MPC_RMCM_GAMUT_REMAP_C11_C12_A, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
502
SRII(MPC_RMCM_GAMUT_REMAP_C13_C14_A, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
503
SRII(MPC_RMCM_GAMUT_REMAP_C21_C22_A, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
504
SRII(MPC_RMCM_GAMUT_REMAP_C23_C24_A, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
505
SRII(MPC_RMCM_GAMUT_REMAP_C31_C32_A, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
506
SRII(MPC_RMCM_GAMUT_REMAP_C33_C34_A, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
507
SRII(MPC_RMCM_GAMUT_REMAP_C11_C12_B, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
508
SRII(MPC_RMCM_GAMUT_REMAP_C13_C14_B, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
509
SRII(MPC_RMCM_GAMUT_REMAP_C21_C22_B, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
510
SRII(MPC_RMCM_GAMUT_REMAP_C23_C24_B, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
511
SRII(MPC_RMCM_GAMUT_REMAP_C31_C32_B, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
512
SRII(MPC_RMCM_GAMUT_REMAP_C33_C34_B, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
513
SRII(MPC_RMCM_MEM_PWR_CTRL, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
514
SRII(MPC_RMCM_3DLUT_FAST_LOAD_SELECT, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
515
SRII(MPC_RMCM_3DLUT_FAST_LOAD_STATUS, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
516
SRII(MPC_RMCM_CNTL, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
517
SRII(MPC_RMCM_TEST_DEBUG_INDEX, MPC_RMCM, inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
518
SRII(MPC_RMCM_TEST_DEBUG_DATA, MPC_RMCM, inst)
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
521
#define MPC_REG_LIST_DCN42(inst) \
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
522
MPC_REG_LIST_DCN4_01_RI(inst),\
drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
523
SRII(MPCC_CONTROL2, MPCC, inst)
drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
414
uint32_t inst,
drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
421
oppn10->base.inst = inst;
drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.h
162
uint32_t inst,
drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
415
uint32_t inst,
drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
421
oppn20->base.inst = inst;
drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h
142
uint32_t inst,
drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.c
40
uint32_t inst, const struct dcn35_opp_registers *regs,
drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.c
44
dcn20_opp_construct(oppn20, ctx, inst,
drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.h
61
uint32_t inst,
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
536
OPTC_SRC_SEL, optc->inst);
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
677
OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
685
TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
695
TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, false);
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
896
MANUAL_FLOW_CONTROL_SEL, optc->inst);
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
900
OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
100
TG_COMMON_REG_LIST_DCN(inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
101
SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
102
SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
103
SRI(OTG_TEST_PATTERN_COLOR, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
104
SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst)
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
34
#define TG_COMMON_REG_LIST_DCN(inst) \
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
35
SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
36
SRI(OTG_VUPDATE_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
37
SRI(OTG_VREADY_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
38
SRI(OTG_BLANK_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
39
SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
40
SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
41
SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
42
SRI(OTG_H_TOTAL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
43
SRI(OTG_H_BLANK_START_END, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
44
SRI(OTG_H_SYNC_A, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
45
SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
46
SRI(OTG_H_TIMING_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
47
SRI(OTG_V_TOTAL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
48
SRI(OTG_V_BLANK_START_END, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
49
SRI(OTG_V_SYNC_A, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
50
SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
51
SRI(OTG_INTERLACE_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
52
SRI(OTG_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
53
SRI(OTG_STEREO_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
54
SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
55
SRI(OTG_STEREO_STATUS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
56
SRI(OTG_V_TOTAL_MAX, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
57
SRI(OTG_V_TOTAL_MID, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
58
SRI(OTG_V_TOTAL_MIN, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
59
SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
60
SRI(OTG_TRIGA_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
61
SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
62
SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
63
SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
64
SRI(OTG_STATUS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
65
SRI(OTG_STATUS_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
66
SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
67
SRI(OTG_BLACK_COLOR, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
68
SRI(OTG_CLOCK_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
69
SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
70
SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
71
SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
72
SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
73
SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
74
SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
75
SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
76
SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
77
SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
78
SRI(CONTROL, VTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
79
SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
80
SRI(OTG_MASTER_UPDATE_MODE, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
81
SRI(OTG_GSL_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
82
SRI(OTG_CRC_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
83
SRI(OTG_CRC0_DATA_RG, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
84
SRI(OTG_CRC0_DATA_B, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
85
SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
86
SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
87
SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
88
SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
89
SRI(OTG_CRC1_DATA_RG, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
90
SRI(OTG_CRC1_DATA_B, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
91
SRI(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
92
SRI(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
93
SRI(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
94
SRI(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
96
SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
97
SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst)
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
99
#define TG_COMMON_REG_LIST_DCN1_0(inst) \
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
169
OPTC_SEG0_SRC_SEL, optc->inst,
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
251
OPTC_DWB0_SOURCE_SELECT, optc->inst);
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
254
OPTC_DWB1_SOURCE_SELECT, optc->inst);
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
287
OTG_MASTER_UPDATE_LOCK_SEL, optc_master->inst);
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
377
OTG_MASTER_UPDATE_LOCK_SEL, optc_slave->inst);
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
386
OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
470
OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
60
OPTC_SEG0_SRC_SEL, optc->inst);
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
31
#define TG_COMMON_REG_LIST_DCN2_0(inst) \
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
32
TG_COMMON_REG_LIST_DCN(inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
33
SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
34
SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
35
SRI(OTG_GSL_WINDOW_X, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
36
SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
37
SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
38
SRI(OTG_DSC_START_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
39
SRI(OTG_CRC_CNTL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
40
SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
41
SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
42
SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
43
SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
45
SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
46
SRI(OTG_DRR_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
47
SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst)
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
46
OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
31
#define TG_COMMON_REG_LIST_DCN201(inst) \
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
32
TG_COMMON_REG_LIST_DCN(inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
33
SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
34
SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
35
SRI(OTG_GSL_WINDOW_X, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
36
SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
37
SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
38
SRI(OTG_DSC_START_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
39
SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
40
SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
41
SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
116
TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
124
OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
132
TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
209
OPTC_SEG0_SRC_SEL, optc->inst,
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
356
dc_dmub_srv_drr_update_cmd(dc, optc->inst, vtotal_min, vtotal_max);
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
50
OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
62
TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
99
TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
100
OPTC_COMMON_REG_LIST_DCN3_BASE(inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
101
SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
102
SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
103
SRI(OTG_GSL_WINDOW_X, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
104
SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
105
SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
106
SRI(OTG_DSC_START_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
107
SRI(OTG_CRC_CNTL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
108
SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
109
SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
110
SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
111
SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
112
SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
113
SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
115
SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst)
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
31
#define V_TOTAL_REGS_DCN30_SRI(inst) \
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
32
SRI(OTG_V_TOTAL_MID, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
33
SRI(OTG_DRR_V_TOTAL_REACH_RANGE, OTG, inst),
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
35
#define OPTC_COMMON_REG_LIST_DCN3_BASE(inst) \
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
36
SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
37
SRI(OTG_VUPDATE_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
38
SRI(OTG_VREADY_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
39
SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
40
SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
41
SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
42
SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
43
SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
44
SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
45
SRI(OTG_H_TOTAL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
46
SRI(OTG_H_BLANK_START_END, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
47
SRI(OTG_H_SYNC_A, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
48
SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
49
SRI(OTG_H_TIMING_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
50
SRI(OTG_V_TOTAL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
51
SRI(OTG_V_BLANK_START_END, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
52
SRI(OTG_V_SYNC_A, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
53
SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
54
SRI(OTG_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
55
SRI(OTG_STEREO_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
56
SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
57
SRI(OTG_STEREO_STATUS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
58
SRI(OTG_V_TOTAL_MAX, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
59
SRI(OTG_V_TOTAL_MIN, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
60
SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
61
V_TOTAL_REGS_DCN30_SRI(inst)\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
62
SRI(OTG_TRIGA_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
63
SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
64
SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
65
SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
66
SRI(OTG_STATUS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
67
SRI(OTG_STATUS_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
68
SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
69
SRI(OTG_BLANK_DATA_COLOR, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
70
SRI(OTG_BLANK_DATA_COLOR_EXT, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
71
SRI(OTG_M_CONST_DTO0, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
72
SRI(OTG_M_CONST_DTO1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
73
SRI(OTG_CLOCK_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
74
SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
75
SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
76
SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
77
SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
78
SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
79
SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
80
SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
81
SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
82
SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
83
SRI(CONTROL, VTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
84
SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
85
SRI(OTG_GSL_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
86
SRI(OTG_CRC_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
87
SRI(OTG_CRC_CNTL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
88
SRI(OTG_CRC0_DATA_RG, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
89
SRI(OTG_CRC0_DATA_B, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
90
SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
91
SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
92
SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
93
SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
95
SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
96
SRI(OTG_DRR_CONTROL, OTG, inst)
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
99
#define OPTC_COMMON_REG_LIST_DCN3_0(inst) \
drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c
103
OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
102
OPTC_SEG0_SRC_SEL, optc->inst);
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
235
OPTC_SEG0_SRC_SEL, optc->inst,
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
100
SRI(OTG_CRC_CNTL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
102
SRI(OTG_DRR_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
103
SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
104
SRI(INTERRUPT_DEST, OTG, inst)
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
31
#define OPTC_COMMON_REG_LIST_DCN3_1(inst) \
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
32
SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
33
SRI(OTG_VUPDATE_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
34
SRI(OTG_VREADY_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
35
SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
36
SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
37
SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
38
SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
39
SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
40
SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
41
SRI(OTG_H_TOTAL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
42
SRI(OTG_H_BLANK_START_END, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
43
SRI(OTG_H_SYNC_A, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
44
SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
45
SRI(OTG_H_TIMING_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
46
SRI(OTG_V_TOTAL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
47
SRI(OTG_V_BLANK_START_END, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
48
SRI(OTG_V_SYNC_A, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
49
SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
50
SRI(OTG_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
51
SRI(OTG_STEREO_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
52
SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
53
SRI(OTG_STEREO_STATUS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
54
SRI(OTG_V_TOTAL_MAX, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
55
SRI(OTG_V_TOTAL_MIN, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
56
SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
57
SRI(OTG_TRIGA_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
58
SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
59
SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
60
SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
61
SRI(OTG_STATUS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
62
SRI(OTG_STATUS_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
63
SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
64
SRI(OTG_M_CONST_DTO0, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
65
SRI(OTG_M_CONST_DTO1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
66
SRI(OTG_CLOCK_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
67
SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
68
SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
69
SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
70
SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
71
SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
72
SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
73
SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
74
SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
75
SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
76
SRI(CONTROL, VTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
77
SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
78
SRI(OTG_GSL_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
79
SRI(OTG_CRC_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
80
SRI(OTG_CRC0_DATA_RG, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
81
SRI(OTG_CRC0_DATA_B, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
82
SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
83
SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
84
SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
85
SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
87
SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
88
SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
89
SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
90
SRI(OTG_GSL_WINDOW_X, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
91
SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
92
SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
93
SRI(OTG_DSC_START_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
94
SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
95
SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
96
SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
97
SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
98
SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
99
SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c
112
OPTC_SEG0_SRC_SEL, optc->inst);
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c
172
OPTC_SEG0_SRC_SEL, optc->inst,
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
100
SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
101
SRI(OTG_DRR_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
102
SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
103
SRI(INTERRUPT_DEST, OTG, inst)
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
32
#define OPTC_COMMON_REG_LIST_DCN3_14(inst) \
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
33
SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
34
SRI(OTG_VUPDATE_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
35
SRI(OTG_VREADY_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
36
SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
37
SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
38
SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
39
SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
40
SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
41
SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
42
SRI(OTG_H_TOTAL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
43
SRI(OTG_H_BLANK_START_END, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
44
SRI(OTG_H_SYNC_A, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
45
SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
46
SRI(OTG_H_TIMING_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
47
SRI(OTG_V_TOTAL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
48
SRI(OTG_V_BLANK_START_END, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
49
SRI(OTG_V_SYNC_A, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
50
SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
51
SRI(OTG_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
52
SRI(OTG_STEREO_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
53
SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
54
SRI(OTG_STEREO_STATUS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
55
SRI(OTG_V_TOTAL_MAX, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
56
SRI(OTG_V_TOTAL_MIN, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
57
SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
58
SRI(OTG_TRIGA_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
59
SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
60
SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
61
SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
62
SRI(OTG_STATUS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
63
SRI(OTG_STATUS_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
64
SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
65
SRI(OTG_M_CONST_DTO0, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
66
SRI(OTG_M_CONST_DTO1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
67
SRI(OTG_CLOCK_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
68
SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
69
SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
70
SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
71
SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
72
SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
73
SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
74
SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
75
SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
76
SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
77
SRI(CONTROL, VTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
78
SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
79
SRI(OTG_GSL_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
80
SRI(OTG_CRC_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
81
SRI(OTG_CRC0_DATA_RG, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
82
SRI(OTG_CRC0_DATA_B, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
83
SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
84
SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
85
SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
86
SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
88
SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
89
SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
90
SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
91
SRI(OTG_GSL_WINDOW_X, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
92
SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
93
SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
94
SRI(OTG_DSC_START_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
95
SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
96
SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
97
SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
98
SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
99
SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
152
OPTC_SEG0_SRC_SEL, optc->inst);
drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
236
OPTC_SEG0_SRC_SEL, optc->inst,
drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
257
dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);
drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
119
OPTC_SEG0_SRC_SEL, optc->inst);
drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
376
dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);
drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
186
OPTC_SEG0_SRC_SEL, optc->inst);
drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
275
OPTC_SEG0_SRC_SEL, optc->inst,
drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
298
dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);
drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
336
dc_dmub_srv_fams2_drr_update(dc, optc->inst,
drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
392
dc_dmub_srv_fams2_drr_update(dc, optc->inst,
drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
400
dc_dmub_srv_drr_update_cmd(dc, optc->inst, vtotal_min, vtotal_max);
drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c
194
TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
463
struct dc_context *ctx, unsigned int inst)
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
465
return dce_audio_create(ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
466
&audio_regs[inst], &audio_shift, &audio_mask);
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
574
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
583
dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
596
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
604
dce_transform_construct(transform, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
605
&xfm_regs[inst], &xfm_shift, &xfm_mask);
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
610
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
619
dce_ipp_construct(ipp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
620
&ipp_regs[inst], &ipp_shift, &ipp_mask);
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
677
&panel_cntl_regs[init_data->inst],
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
686
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
695
ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
701
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
709
dce110_aux_engine_construct(aux_engine, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
711
&aux_engine_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
739
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
747
dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
748
&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
1163
(uint8_t)pipe_ctx->stream_res.tg->inst,
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
507
struct dc_context *ctx, unsigned int inst)
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
509
return dce_audio_create(ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
510
&audio_regs[inst], &audio_shift, &audio_mask);
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
609
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
618
dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
631
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
639
dce_transform_construct(transform, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
640
&xfm_regs[inst], &xfm_shift, &xfm_mask);
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
645
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
654
dce_ipp_construct(ipp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
655
&ipp_regs[inst], &ipp_shift, &ipp_mask);
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
701
&panel_cntl_regs[init_data->inst],
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
710
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
719
ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
725
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
733
dce110_aux_engine_construct(aux_engine, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
735
&aux_engine_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
763
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
771
dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
772
&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
902
pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
487
struct dc_context *ctx, unsigned int inst)
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
489
return dce_audio_create(ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
490
&audio_regs[inst], &audio_shift, &audio_mask);
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
581
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
590
dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
602
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
610
dce_transform_construct(transform, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
611
&xfm_regs[inst], &xfm_shift, &xfm_mask);
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
662
&panel_cntl_regs[init_data->inst],
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
670
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
679
dce_ipp_construct(ipp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
680
&ipp_regs[inst], &ipp_shift, &ipp_mask);
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
686
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
695
ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
701
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
709
dce110_aux_engine_construct(aux_engine, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
711
&aux_engine_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
739
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
747
dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
748
&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
428
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
437
ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
442
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
450
dce110_aux_engine_construct(aux_engine, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
452
&aux_engine_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
480
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
488
dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
489
&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
694
struct dc_context *ctx, unsigned int inst)
drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
696
return dce_audio_create(ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
697
&audio_regs[inst], &audio_shift, &audio_mask);
drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
747
&panel_cntl_regs[init_data->inst],
drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
755
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
764
dce_ipp_construct(ipp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
765
&ipp_regs[inst], &ipp_shift, &ipp_mask);
drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
877
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
886
dce120_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
892
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
900
dce_transform_construct(transform, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
901
&xfm_regs[inst], &xfm_shift, &xfm_mask);
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
498
struct dc_context *ctx, unsigned int inst)
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
500
return dce_audio_create(ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
501
&audio_regs[inst], &audio_shift, &audio_mask);
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
521
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
530
ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
536
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
544
dce110_aux_engine_construct(aux_engine, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
546
&aux_engine_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
574
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
582
dce_i2c_hw_construct(dce_i2c_hw, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
583
&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
684
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
693
dce60_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
706
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
714
dce60_transform_construct(transform, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
715
&xfm_regs[inst], &xfm_shift, &xfm_mask);
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
773
&panel_cntl_regs[init_data->inst],
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
811
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
820
dce60_ipp_construct(ipp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
821
&ipp_regs[inst], &ipp_shift, &ipp_mask);
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
504
struct dc_context *ctx, unsigned int inst)
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
506
return dce_audio_create(ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
507
&audio_regs[inst], &audio_shift, &audio_mask);
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
527
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
536
ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
542
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
550
dce110_aux_engine_construct(aux_engine, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
552
&aux_engine_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
580
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
588
dce_i2c_hw_construct(dce_i2c_hw, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
589
&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
690
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
699
dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
712
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
720
dce_transform_construct(transform, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
721
&xfm_regs[inst], &xfm_shift, &xfm_mask);
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
780
&panel_cntl_regs[init_data->inst],
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
818
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
827
dce_ipp_construct(ipp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
828
&ipp_regs[inst], &ipp_shift, &ipp_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1016
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1024
dcn10_hubp_construct(hubp1, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1025
&hubp_regs[inst], &hubp_shift, &hubp_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1037
pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1142
idle_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[idle_pipe->pipe_idx]->inst;
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
602
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
610
dpp1_construct(dpp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
611
&tf_regs[inst], &tf_shift, &tf_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
616
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
626
dcn10_ipp_construct(ipp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
627
&ipp_regs[inst], &ipp_shift, &ipp_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
633
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
643
dcn10_opp_construct(opp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
644
&opp_regs[inst], &opp_shift, &opp_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
649
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
657
dce110_aux_engine_construct(aux_engine, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
659
&aux_engine_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
686
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
694
dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
695
&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
740
tgn10->base.inst = instance;
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
800
&panel_cntl_regs[init_data->inst],
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
840
struct dc_context *ctx, unsigned int inst)
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
842
return dce_audio_create(ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
843
&audio_regs[inst], &audio_shift, &audio_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1020
struct dc_context *ctx, unsigned int inst)
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1022
return dce_audio_create(ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1023
&audio_regs[inst], &audio_shift, &audio_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1091
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1101
dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1234
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1242
if (hubp2_construct(hubp2, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1243
&hubp_regs[inst], &hubp_shift, &hubp_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1274
pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1382
if (dsc_old && !res_ctx->is_dsc_acquired[dsc_old->inst]) {
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1384
res_ctx->is_dsc_acquired[dsc_old->inst] = true;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1532
next_odm_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[next_odm_pipe->pipe_idx]->inst;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1589
secondary_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[secondary_pipe->pipe_idx]->inst;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1973
if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1977
if (dc->debug.force_odm_combine_4to1 & (1 << pipe->stream_res.tg->inst)) {
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2222
sec_dpp_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[sec_dpp_pipe->pipe_idx]->inst;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
764
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
772
if (dpp2_construct(dpp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
773
&tf_regs[inst], &tf_shift, &tf_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
782
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
792
dcn20_ipp_construct(ipp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
793
&ipp_regs[inst], &ipp_shift, &ipp_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
799
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
809
dcn20_opp_construct(opp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
810
&opp_regs[inst], &opp_shift, &opp_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
816
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
824
dce110_aux_engine_construct(aux_engine, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
826
&aux_engine_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
854
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
862
dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
863
&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
919
tgn10->base.inst = instance;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
980
&panel_cntl_regs[init_data->inst],
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h
102
struct dc_context *ctx, uint32_t inst);
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h
107
uint32_t inst);
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h
84
uint32_t inst);
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h
87
struct dc_context *ctx, uint32_t inst);
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h
90
struct dc_context *ctx, uint32_t inst);
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h
93
struct dc_context *ctx, uint32_t inst);
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h
97
uint32_t inst);
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
1017
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
1025
if (dcn201_hubp_construct(hubp201, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
1026
&hubp_regs[inst], &hubp_shift, &hubp_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
1058
idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
633
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
641
if (dpp201_construct(dpp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
642
&tf_regs[inst], &tf_shift, &tf_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
650
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
659
dcn20_ipp_construct(ipp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
660
&ipp_regs[inst], &ipp_shift, &ipp_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
666
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
675
dcn201_opp_construct(opp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
676
&opp_regs[inst], &opp_shift, &opp_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
681
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
689
dce110_aux_engine_construct(aux_engine, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
691
&aux_engine_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
714
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
722
dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
723
&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
796
tgn10->base.inst = instance;
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
877
struct dc_context *ctx, unsigned int inst)
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
879
return dce_audio_create(ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
880
&audio_regs[inst], &audio_shift, &audio_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1014
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1022
if (hubp21_construct(hubp21, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1023
&hubp_regs[inst], &hubp_shift, &hubp_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1060
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1070
dcn20_opp_construct(opp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1071
&opp_regs[inst], &opp_shift, &opp_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1084
tgn10->base.inst = instance;
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1123
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1133
dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1162
struct dc_context *ctx, unsigned int inst)
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1164
return dce_audio_create(ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1165
&audio_regs[inst], &audio_shift, &audio_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1362
&panel_cntl_regs[init_data->inst],
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
504
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
514
dcn20_ipp_construct(ipp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
515
&ipp_regs[inst], &ipp_shift, &ipp_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
521
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
529
if (dpp2_construct(dpp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
530
&tf_regs[inst], &tf_shift, &tf_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
540
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
548
dce110_aux_engine_construct(aux_engine, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
550
&aux_engine_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
577
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
585
dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
586
&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1026
&panel_cntl_regs[init_data->inst],
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1043
struct dc_context *ctx, unsigned int inst)
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1045
return dce_audio_create(ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1046
&audio_regs[inst], &audio_shift, &audio_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1051
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1058
vpg3_construct(vpg3, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1059
&vpg_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1068
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1075
afmt3_construct(afmt3, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1076
&afmt_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1357
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1365
if (hubp3_construct(hubp2, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1366
&hubp_regs[inst], &hubp_shift, &hubp_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1423
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1433
dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1697
sec_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[pipe_idx]->inst;
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
188
#define CLK_SRI(reg_name, block, inst)\
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
189
.reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
190
mm ## block ## _ ## inst ## _ ## reg_name
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
796
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
804
if (dpp3_construct(dpp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
805
&dpp_regs[inst], &tf_shift, &tf_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
814
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
824
dcn20_opp_construct(opp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
825
&opp_regs[inst], &opp_shift, &opp_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
831
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
839
dce110_aux_engine_construct(aux_engine, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
841
&aux_engine_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
870
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
878
dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
879
&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
969
tgn10->base.inst = instance;
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1005
afmt3_construct(afmt3, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1006
&afmt_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1195
static struct hubp *dcn301_hubp_create(struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1203
if (hubp3_construct(hubp2, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1204
&hubp_regs[inst], &hubp_shift, &hubp_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1261
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1271
dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
190
#define CLK_SRI(reg_name, block, inst)\
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
191
.reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
192
mm ## block ## _ ## inst ## _ ## reg_name
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
719
static struct dpp *dcn301_dpp_create(struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
727
if (dpp3_construct(dpp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
728
&dpp_regs[inst], &tf_shift, &tf_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
736
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
746
dcn20_opp_construct(opp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
747
&opp_regs[inst], &opp_shift, &opp_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
751
static struct dce_aux *dcn301_aux_engine_create(struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
759
dce110_aux_engine_construct(aux_engine, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
761
&aux_engine_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
785
static struct dce_i2c_hw *dcn301_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
793
dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
794
&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
884
tgn10->base.inst = instance;
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
941
&panel_cntl_regs[init_data->inst],
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
973
struct dc_context *ctx, unsigned int inst)
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
975
return dce_audio_create(ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
976
&audio_regs[inst], &audio_shift, &audio_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
981
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
988
vpg3_construct(vpg3, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
989
&vpg_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
998
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
1045
dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst],
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
331
static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
338
vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
363
static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
370
afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
401
static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst)
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
403
return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
623
static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
630
if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
657
static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
664
if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
691
static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
700
dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
730
tgn10->base.inst = instance;
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
799
static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
808
dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
906
static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
913
dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
914
&aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
937
static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
944
dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
324
static struct vpg *dcn303_vpg_create(struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
331
vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
353
static struct afmt *dcn303_afmt_create(struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
360
afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
391
static struct audio *dcn303_create_audio(struct dc_context *ctx, unsigned int inst)
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
393
return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
604
static struct hubp *dcn303_hubp_create(struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
611
if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
635
static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
642
if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
666
static struct output_pixel_processor *dcn303_opp_create(struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
675
dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
702
tgn10->base.inst = instance;
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
760
static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
769
dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
864
static struct dce_aux *dcn303_aux_engine_create(struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
871
dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
872
&aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
892
static struct dce_i2c_hw *dcn303_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
899
dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
990
dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst],
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1006
dcn20_opp_construct(opp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1007
&opp_regs[inst], &opp_shift, &opp_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1013
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1021
dce110_aux_engine_construct(aux_engine, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1023
&aux_engine_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1050
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1058
dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1059
&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1136
tgn10->base.inst = instance;
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1232
struct dc_context *ctx, unsigned int inst)
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1234
return dce_audio_create(ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1235
&audio_regs[inst], &audio_shift, &audio_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1240
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1247
vpg31_construct(vpg31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1248
&vpg_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1257
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1264
afmt31_construct(afmt31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1265
&afmt_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1276
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1283
apg31_construct(apg31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1284
&apg_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1441
uint8_t inst,
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1451
hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1452
&hpo_dp_link_enc_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1654
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1662
if (hubp31_construct(hubp2, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1663
&hubp_regs[inst], &hubp_shift, &hubp_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1720
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1730
dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
199
#define CLK_SRI(reg_name, block, inst)\
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
200
.reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
201
reg ## block ## _ ## inst ## _ ## reg_name
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
978
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
986
if (dpp3_construct(dpp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
987
&dpp_regs[inst], &tf_shift, &tf_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
996
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1013
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1021
if (dpp3_construct(dpp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1022
&dpp_regs[inst], &tf_shift, &tf_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1031
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1041
dcn20_opp_construct(opp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1042
&opp_regs[inst], &opp_shift, &opp_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1048
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1056
dce110_aux_engine_construct(aux_engine, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1058
&aux_engine_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1107
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1115
dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1116
&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1193
tgn10->base.inst = instance;
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1289
struct dc_context *ctx, unsigned int inst)
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1291
return dce_audio_create(ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1292
&audio_regs[inst], &audio_shift, &audio_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1297
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1304
vpg31_construct(vpg31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1305
&vpg_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1314
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1321
afmt31_construct(afmt31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1322
&afmt_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1333
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1340
apg31_construct(apg31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1341
&apg_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1501
uint8_t inst,
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1511
hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1512
&hpo_dp_link_enc_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1713
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1721
if (hubp31_construct(hubp2, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1722
&hubp_regs[inst], &hubp_shift, &hubp_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1779
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1789
dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
216
#define CLK_SRI(reg_name, block, inst)\
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
217
.reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
218
reg ## block ## _ ## inst ## _ ## reg_name
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1005
dcn20_opp_construct(opp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1006
&opp_regs[inst], &opp_shift, &opp_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1012
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1020
dce110_aux_engine_construct(aux_engine, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1022
&aux_engine_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1049
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1057
dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1058
&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1135
tgn10->base.inst = instance;
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1231
struct dc_context *ctx, unsigned int inst)
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1233
return dce_audio_create(ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1234
&audio_regs[inst], &audio_shift, &audio_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1239
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1246
vpg31_construct(vpg31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1247
&vpg_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1256
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1263
afmt31_construct(afmt31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1264
&afmt_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1275
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1282
apg31_construct(apg31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1283
&apg_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1443
uint8_t inst,
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1453
hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1454
&hpo_dp_link_enc_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1656
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1664
if (hubp31_construct(hubp2, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1665
&hubp_regs[inst], &hubp_shift, &hubp_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1722
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1732
dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
977
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
985
if (dpp3_construct(dpp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
986
&dpp_regs[inst], &tf_shift, &tf_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
995
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1005
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1013
dce110_aux_engine_construct(aux_engine, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1015
&aux_engine_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1042
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1050
dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1051
&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1128
tgn10->base.inst = instance;
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1224
struct dc_context *ctx, unsigned int inst)
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1226
return dce_audio_create(ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1227
&audio_regs[inst], &audio_shift, &audio_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1232
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1239
vpg31_construct(vpg31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1240
&vpg_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1249
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1256
afmt31_construct(afmt31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1257
&afmt_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1269
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1276
apg31_construct(apg31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1277
&apg_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1437
uint8_t inst,
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1447
hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1448
&hpo_dp_link_enc_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1646
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1654
if (hubp31_construct(hubp2, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1655
&hubp_regs[inst], &hubp_shift, &hubp_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1712
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1722
dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
970
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
978
if (dpp3_construct(dpp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
979
&dpp_regs[inst], &tf_shift, &tf_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
988
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
998
dcn20_opp_construct(opp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
999
&opp_regs[inst], &opp_shift, &opp_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1011
if (dpp32_construct(dpp3, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1012
&dpp_regs[inst], &tf_shift, &tf_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1045
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1062
dcn20_opp_construct(opp2, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1063
&opp_regs[inst], &opp_shift, &opp_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1085
tgn10->base.inst = instance;
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1178
struct dc_context *ctx, unsigned int inst)
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1189
return dce_audio_create(ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1190
&audio_regs[inst], &audio_shift, &audio_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1195
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1215
vpg3_construct(vpg3, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1216
&vpg_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1225
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1241
afmt3_construct(afmt3, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1242
&afmt_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1251
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1265
apg31_construct(apg31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1266
&apg_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1448
uint8_t inst,
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1463
hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1464
&hpo_dp_link_enc_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
172
#define SRII_ARR_2(reg_name, block, id, inst)\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
173
REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1730
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1747
dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2949
idle_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[idle_pipe->pipe_idx]->inst;
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
3009
(uint8_t)pool->dpps[free_pipe->pipe_idx]->inst;
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
3041
free_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[free_pipe_idx]->inst;
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
806
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
822
dce110_aux_engine_construct(aux_engine, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
824
&aux_engine_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
846
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
862
dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
863
&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
964
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
979
if (hubp32_construct(hubp2, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
980
&hubp_regs[inst], &hubp_shift, &hubp_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
996
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1000
SRII(MPCC_MCM_1DLUT_RAMB_REGION_22_23, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1001
SRII(MPCC_MCM_1DLUT_RAMB_REGION_24_25, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1002
SRII(MPCC_MCM_1DLUT_RAMB_REGION_26_27, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1003
SRII(MPCC_MCM_1DLUT_RAMB_REGION_28_29, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1004
SRII(MPCC_MCM_1DLUT_RAMB_REGION_30_31, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1005
SRII(MPCC_MCM_1DLUT_RAMB_REGION_32_33, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1006
SRII(MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM, inst)
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1009
#define OPTC_COMMON_REG_LIST_DCN3_2_RI(inst) \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1010
SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1011
SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1012
SRI_ARR(OTG_VREADY_PARAM, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1013
SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1014
SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1015
SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1016
SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1017
SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1018
SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1019
SRI_ARR(OTG_H_TOTAL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1020
SRI_ARR(OTG_H_BLANK_START_END, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1021
SRI_ARR(OTG_H_SYNC_A, OTG, inst), SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1022
SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), SRI_ARR(OTG_V_TOTAL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1023
SRI_ARR(OTG_V_BLANK_START_END, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1024
SRI_ARR(OTG_V_SYNC_A, OTG, inst), SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1025
SRI_ARR(OTG_CONTROL, OTG, inst), SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1026
SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1027
SRI_ARR(OTG_STEREO_STATUS, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1028
SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1029
SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1030
SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1031
SRI_ARR(OTG_TRIGA_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1032
SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1033
SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1034
SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1035
SRI_ARR(OTG_STATUS, OTG, inst), SRI_ARR(OTG_STATUS_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1036
SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1037
SRI_ARR(OTG_M_CONST_DTO0, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1038
SRI_ARR(OTG_M_CONST_DTO1, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1039
SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1040
SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1041
SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1042
SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1043
SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1044
SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1045
SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1046
SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1047
SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1048
SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1049
SRI_ARR(CONTROL, VTG, inst), SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1050
SRI_ARR(OTG_GSL_CONTROL, OTG, inst), SRI_ARR(OTG_CRC_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1051
SRI_ARR(OTG_CRC0_DATA_RG, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1052
SRI_ARR(OTG_CRC0_DATA_B, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1053
SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1054
SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1055
SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1056
SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1057
SR_ARR(GSL_SOURCE_SELECT, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1058
SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1059
SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1060
SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1061
SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1062
SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1063
SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1064
SRI_ARR(OTG_DSC_START_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1065
SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1066
SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1067
SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1068
SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1069
SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1070
SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1071
SRI_ARR(OTG_DRR_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1072
SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1073
SRI_ARR(INTERRUPT_DEST, OTG, inst)
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
682
#define MCIF_WB_COMMON_REG_LIST_DCN32_RI(inst) \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
683
SRI2_ARR(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
684
SRI2_ARR(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
685
SRI2_ARR(MCIF_WB_BUF_PITCH, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
686
SRI2_ARR(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
687
SRI2_ARR(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
688
SRI2_ARR(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
689
SRI2_ARR(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
690
SRI2_ARR(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
691
SRI2_ARR(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
692
SRI2_ARR(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
693
SRI2_ARR(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
694
SRI2_ARR(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
695
SRI2_ARR(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
696
SRI2_ARR(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
697
SRI2_ARR(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
698
SRI2_ARR(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
699
SRI2_ARR(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
700
SRI2_ARR(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
701
SRI2_ARR(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
702
SRI2_ARR(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
703
SRI2_ARR(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
704
SRI2_ARR(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
705
SRI2_ARR(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MMHUBBUB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
706
SRI2_ARR(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
707
SRI2_ARR(MCIF_WB_WATERMARK, MMHUBBUB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
708
SRI2_ARR(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
709
SRI2_ARR(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
710
SRI2_ARR(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
711
SRI2_ARR(MCIF_WB_SECURITY_LEVEL, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
712
SRI2_ARR(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
713
SRI2_ARR(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
714
SRI2_ARR(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
715
SRI2_ARR(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
716
SRI2_ARR(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
717
SRI2_ARR(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
718
SRI2_ARR(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
719
SRI2_ARR(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
720
SRI2_ARR(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
721
SRI2_ARR(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
722
SRI2_ARR(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
723
SRI2_ARR(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
724
SRI2_ARR(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
725
SRI2_ARR(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
726
SRI2_ARR(MMHUBBUB_MEM_PWR_CNTL, MMHUBBUB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
727
SRI2_ARR(MMHUBBUB_WARMUP_ADDR_REGION, MMHUBBUB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
728
SRI2_ARR(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, MMHUBBUB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
729
SRI2_ARR(MMHUBBUB_WARMUP_BASE_ADDR_LOW, MMHUBBUB, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
730
SRI2_ARR(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB, inst)
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
787
#define MPC_DWB_MUX_REG_LIST_DCN3_0_RI(inst) \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
788
SRII_DWB(DWB_MUX, MUX, MPC_DWB, inst)
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
790
#define MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0_RI(inst) \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
791
SRII(MUX, MPC_OUT, inst), VUPDATE_SRII(CUR, VUPDATE_LOCK_SET, inst)
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
793
#define MPC_OUT_MUX_REG_LIST_DCN3_0_RI(inst) \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
794
MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0_RI(inst), SRII(CSC_MODE, MPC_OUT, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
795
SRII(CSC_C11_C12_A, MPC_OUT, inst), SRII(CSC_C33_C34_A, MPC_OUT, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
796
SRII(CSC_C11_C12_B, MPC_OUT, inst), SRII(CSC_C33_C34_B, MPC_OUT, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
797
SRII(DENORM_CONTROL, MPC_OUT, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
798
SRII(DENORM_CLAMP_G_Y, MPC_OUT, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
799
SRII(DENORM_CLAMP_B_CB, MPC_OUT, inst), SR(MPC_OUT_CSC_COEF_FORMAT)
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
801
#define MPC_COMMON_REG_LIST_DCN1_0_RI(inst) \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
802
SRII(MPCC_TOP_SEL, MPCC, inst), SRII(MPCC_BOT_SEL, MPCC, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
803
SRII(MPCC_CONTROL, MPCC, inst), SRII(MPCC_STATUS, MPCC, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
804
SRII(MPCC_OPP_ID, MPCC, inst), SRII(MPCC_BG_G_Y, MPCC, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
805
SRII(MPCC_BG_R_CR, MPCC, inst), SRII(MPCC_BG_B_CB, MPCC, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
806
SRII(MPCC_SM_CONTROL, MPCC, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
807
SRII(MPCC_UPDATE_LOCK_SEL, MPCC, inst)
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
809
#define MPC_REG_LIST_DCN3_0_RI(inst) \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
810
MPC_COMMON_REG_LIST_DCN1_0_RI(inst), SRII(MPCC_TOP_GAIN, MPCC, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
811
SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
812
SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
813
SRII(MPCC_MEM_PWR_CTRL, MPCC, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
814
SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
815
SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
816
SRII(MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
817
SRII(MPCC_GAMUT_REMAP_MODE, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
818
SRII(MPC_GAMUT_REMAP_C11_C12_A, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
819
SRII(MPC_GAMUT_REMAP_C33_C34_A, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
820
SRII(MPC_GAMUT_REMAP_C11_C12_B, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
821
SRII(MPC_GAMUT_REMAP_C33_C34_B, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
822
SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
823
SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
824
SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
825
SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
826
SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_G, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
827
SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_R, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
828
SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
829
SRII(MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
830
SRII(MPCC_OGAM_RAMA_END_CNTL1_G, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
831
SRII(MPCC_OGAM_RAMA_END_CNTL2_G, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
832
SRII(MPCC_OGAM_RAMA_END_CNTL1_R, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
833
SRII(MPCC_OGAM_RAMA_END_CNTL2_R, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
834
SRII(MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
835
SRII(MPCC_OGAM_RAMA_REGION_32_33, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
836
SRII(MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
837
SRII(MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
838
SRII(MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
839
SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
840
SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_G, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
841
SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_R, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
842
SRII(MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
843
SRII(MPCC_OGAM_RAMB_START_CNTL_G, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
844
SRII(MPCC_OGAM_RAMB_START_CNTL_R, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
845
SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_B, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
846
SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_G, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
847
SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_R, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
848
SRII(MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
849
SRII(MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
850
SRII(MPCC_OGAM_RAMB_END_CNTL1_G, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
851
SRII(MPCC_OGAM_RAMB_END_CNTL2_G, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
852
SRII(MPCC_OGAM_RAMB_END_CNTL1_R, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
853
SRII(MPCC_OGAM_RAMB_END_CNTL2_R, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
854
SRII(MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
855
SRII(MPCC_OGAM_RAMB_REGION_32_33, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
856
SRII(MPCC_OGAM_RAMB_OFFSET_B, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
857
SRII(MPCC_OGAM_RAMB_OFFSET_G, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
858
SRII(MPCC_OGAM_RAMB_OFFSET_R, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
859
SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_B, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
860
SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_G, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
861
SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_R, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
862
SRII(MPCC_OGAM_CONTROL, MPCC_OGAM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
863
SRII(MPCC_OGAM_LUT_CONTROL, MPCC_OGAM, inst)
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
865
#define MPC_REG_LIST_DCN3_2_RI(inst) \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
866
MPC_REG_LIST_DCN3_0_RI(inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
867
SRII(MPCC_MOVABLE_CM_LOCATION_CONTROL, MPCC, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
868
SRII(MPCC_MCM_SHAPER_CONTROL, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
869
SRII(MPCC_MCM_SHAPER_OFFSET_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
870
SRII(MPCC_MCM_SHAPER_OFFSET_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
871
SRII(MPCC_MCM_SHAPER_OFFSET_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
872
SRII(MPCC_MCM_SHAPER_SCALE_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
873
SRII(MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
874
SRII(MPCC_MCM_SHAPER_LUT_INDEX, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
875
SRII(MPCC_MCM_SHAPER_LUT_DATA, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
876
SRII(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
877
SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
878
SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
879
SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
880
SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
881
SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
882
SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
883
SRII(MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
884
SRII(MPCC_MCM_SHAPER_RAMA_REGION_2_3, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
885
SRII(MPCC_MCM_SHAPER_RAMA_REGION_4_5, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
886
SRII(MPCC_MCM_SHAPER_RAMA_REGION_6_7, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
887
SRII(MPCC_MCM_SHAPER_RAMA_REGION_8_9, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
888
SRII(MPCC_MCM_SHAPER_RAMA_REGION_10_11, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
889
SRII(MPCC_MCM_SHAPER_RAMA_REGION_12_13, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
890
SRII(MPCC_MCM_SHAPER_RAMA_REGION_14_15, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
891
SRII(MPCC_MCM_SHAPER_RAMA_REGION_16_17, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
892
SRII(MPCC_MCM_SHAPER_RAMA_REGION_18_19, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
893
SRII(MPCC_MCM_SHAPER_RAMA_REGION_20_21, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
894
SRII(MPCC_MCM_SHAPER_RAMA_REGION_22_23, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
895
SRII(MPCC_MCM_SHAPER_RAMA_REGION_24_25, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
896
SRII(MPCC_MCM_SHAPER_RAMA_REGION_26_27, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
897
SRII(MPCC_MCM_SHAPER_RAMA_REGION_28_29, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
898
SRII(MPCC_MCM_SHAPER_RAMA_REGION_30_31, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
899
SRII(MPCC_MCM_SHAPER_RAMA_REGION_32_33, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
900
SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
901
SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
902
SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
903
SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
904
SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
905
SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
906
SRII(MPCC_MCM_SHAPER_RAMB_REGION_0_1, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
907
SRII(MPCC_MCM_SHAPER_RAMB_REGION_2_3, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
908
SRII(MPCC_MCM_SHAPER_RAMB_REGION_4_5, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
909
SRII(MPCC_MCM_SHAPER_RAMB_REGION_6_7, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
910
SRII(MPCC_MCM_SHAPER_RAMB_REGION_8_9, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
911
SRII(MPCC_MCM_SHAPER_RAMB_REGION_10_11, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
912
SRII(MPCC_MCM_SHAPER_RAMB_REGION_12_13, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
913
SRII(MPCC_MCM_SHAPER_RAMB_REGION_14_15, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
914
SRII(MPCC_MCM_SHAPER_RAMB_REGION_16_17, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
915
SRII(MPCC_MCM_SHAPER_RAMB_REGION_18_19, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
916
SRII(MPCC_MCM_SHAPER_RAMB_REGION_20_21, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
917
SRII(MPCC_MCM_SHAPER_RAMB_REGION_22_23, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
918
SRII(MPCC_MCM_SHAPER_RAMB_REGION_24_25, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
919
SRII(MPCC_MCM_SHAPER_RAMB_REGION_26_27, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
920
SRII(MPCC_MCM_SHAPER_RAMB_REGION_28_29, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
921
SRII(MPCC_MCM_SHAPER_RAMB_REGION_30_31, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
922
SRII(MPCC_MCM_SHAPER_RAMB_REGION_32_33, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
923
SRII(MPCC_MCM_3DLUT_MODE, MPCC_MCM, inst), /*TODO: may need to add other 3DLUT regs*/\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
924
SRII(MPCC_MCM_3DLUT_INDEX, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
925
SRII(MPCC_MCM_3DLUT_DATA, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
926
SRII(MPCC_MCM_3DLUT_DATA_30BIT, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
927
SRII(MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
928
SRII(MPCC_MCM_3DLUT_OUT_NORM_FACTOR, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
929
SRII(MPCC_MCM_3DLUT_OUT_OFFSET_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
930
SRII(MPCC_MCM_3DLUT_OUT_OFFSET_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
931
SRII(MPCC_MCM_3DLUT_OUT_OFFSET_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
932
SRII(MPCC_MCM_1DLUT_CONTROL, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
933
SRII(MPCC_MCM_1DLUT_LUT_INDEX, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
934
SRII(MPCC_MCM_1DLUT_LUT_DATA, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
935
SRII(MPCC_MCM_1DLUT_LUT_CONTROL, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
936
SRII(MPCC_MCM_1DLUT_RAMA_START_CNTL_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
937
SRII(MPCC_MCM_1DLUT_RAMA_START_CNTL_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
938
SRII(MPCC_MCM_1DLUT_RAMA_START_CNTL_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
939
SRII(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
940
SRII(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
941
SRII(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
942
SRII(MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
943
SRII(MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
944
SRII(MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
945
SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL1_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
946
SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL2_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
947
SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL1_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
948
SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL2_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
949
SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL1_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
950
SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL2_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
951
SRII(MPCC_MCM_1DLUT_RAMA_OFFSET_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
952
SRII(MPCC_MCM_1DLUT_RAMA_OFFSET_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
953
SRII(MPCC_MCM_1DLUT_RAMA_OFFSET_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
954
SRII(MPCC_MCM_1DLUT_RAMA_REGION_0_1, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
955
SRII(MPCC_MCM_1DLUT_RAMA_REGION_2_3, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
956
SRII(MPCC_MCM_1DLUT_RAMA_REGION_4_5, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
957
SRII(MPCC_MCM_1DLUT_RAMA_REGION_6_7, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
958
SRII(MPCC_MCM_1DLUT_RAMA_REGION_8_9, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
959
SRII(MPCC_MCM_1DLUT_RAMA_REGION_10_11, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
960
SRII(MPCC_MCM_1DLUT_RAMA_REGION_12_13, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
961
SRII(MPCC_MCM_1DLUT_RAMA_REGION_14_15, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
962
SRII(MPCC_MCM_1DLUT_RAMA_REGION_16_17, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
963
SRII(MPCC_MCM_1DLUT_RAMA_REGION_18_19, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
964
SRII(MPCC_MCM_1DLUT_RAMA_REGION_20_21, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
965
SRII(MPCC_MCM_1DLUT_RAMA_REGION_22_23, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
966
SRII(MPCC_MCM_1DLUT_RAMA_REGION_24_25, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
967
SRII(MPCC_MCM_1DLUT_RAMA_REGION_26_27, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
968
SRII(MPCC_MCM_1DLUT_RAMA_REGION_28_29, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
969
SRII(MPCC_MCM_1DLUT_RAMA_REGION_30_31, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
970
SRII(MPCC_MCM_1DLUT_RAMA_REGION_32_33, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
971
SRII(MPCC_MCM_1DLUT_RAMB_START_CNTL_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
972
SRII(MPCC_MCM_1DLUT_RAMB_START_CNTL_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
973
SRII(MPCC_MCM_1DLUT_RAMB_START_CNTL_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
974
SRII(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
975
SRII(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
976
SRII(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
977
SRII(MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
978
SRII(MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
979
SRII(MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
980
SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL1_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
981
SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL2_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
982
SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL1_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
983
SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL2_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
984
SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL1_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
985
SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL2_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
986
SRII(MPCC_MCM_1DLUT_RAMB_OFFSET_B, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
987
SRII(MPCC_MCM_1DLUT_RAMB_OFFSET_G, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
988
SRII(MPCC_MCM_1DLUT_RAMB_OFFSET_R, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
989
SRII(MPCC_MCM_1DLUT_RAMB_REGION_0_1, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
990
SRII(MPCC_MCM_1DLUT_RAMB_REGION_2_3, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
991
SRII(MPCC_MCM_1DLUT_RAMB_REGION_4_5, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
992
SRII(MPCC_MCM_1DLUT_RAMB_REGION_6_7, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
993
SRII(MPCC_MCM_1DLUT_RAMB_REGION_8_9, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
994
SRII(MPCC_MCM_1DLUT_RAMB_REGION_10_11, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
995
SRII(MPCC_MCM_1DLUT_RAMB_REGION_12_13, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
996
SRII(MPCC_MCM_1DLUT_RAMB_REGION_14_15, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
997
SRII(MPCC_MCM_1DLUT_RAMB_REGION_16_17, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
998
SRII(MPCC_MCM_1DLUT_RAMB_REGION_18_19, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
999
SRII(MPCC_MCM_1DLUT_RAMB_REGION_20_21, MPCC_MCM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1000
&dpp_regs[inst], &tf_shift, &tf_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1033
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1050
dcn20_opp_construct(opp2, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1051
&opp_regs[inst], &opp_shift, &opp_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1073
tgn10->base.inst = instance;
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1153
struct dc_context *ctx, unsigned int inst)
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1164
return dce_audio_create(ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1165
&audio_regs[inst], &audio_shift, &audio_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1170
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1190
vpg3_construct(vpg3, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1191
&vpg_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1200
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1216
afmt3_construct(afmt3, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1217
&afmt_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1226
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1240
apg31_construct(apg31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1241
&apg_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1423
uint8_t inst,
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1438
hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1439
&hpo_dp_link_enc_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
167
#define SRII_ARR_2(reg_name, block, id, inst)\
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
168
REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1704
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1721
dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
794
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
810
dce110_aux_engine_construct(aux_engine, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
812
&aux_engine_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
834
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
850
dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
851
&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
952
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
967
if (hubp32_construct(hubp2, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
968
&hubp_regs[inst], &hubp_shift, &hubp_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
984
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
999
if (dpp32_construct(dpp3, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1113
tgn10->base.inst = instance;
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1232
struct dc_context *ctx, unsigned int inst)
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1245
return dce_audio_create(ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1246
&audio_regs[inst], &audio_shift, &audio_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1251
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1271
vpg31_construct(vpg31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1272
&vpg_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1281
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1297
afmt31_construct(afmt31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1298
&afmt_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1309
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1323
apg31_construct(apg31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1324
&apg_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1499
uint8_t inst,
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1514
hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1515
&hpo_dp_link_enc_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1723
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1738
if (hubp35_construct(hubp2, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1739
&hubp_regs[inst], &hubp_shift, &hubp_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1822
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
183
#define SRII_ARR_2(reg_name, block, id, inst)\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1839
dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
184
REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
861
static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
876
success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
891
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
908
dcn35_opp_construct(opp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
909
&opp_regs[inst], &opp_shift, &opp_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
918
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
934
dce110_aux_engine_construct(aux_engine, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
936
&aux_engine_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
981
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
997
dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
998
&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
158
#define MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(inst) \
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
159
MCIF_WB_COMMON_REG_LIST_DCN32_RI(inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
160
SRI2_ARR(MMHUBBUB_CLOCK_CNTL, MMHUBBUB, inst)
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
218
#define OPTC_COMMON_REG_LIST_DCN3_5_RI(inst) \
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
219
SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
220
SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
221
SRI_ARR(OTG_VREADY_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
222
SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
223
SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
224
SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
225
SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
226
SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
227
SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
228
SRI_ARR(OTG_H_TOTAL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
229
SRI_ARR(OTG_H_BLANK_START_END, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
230
SRI_ARR(OTG_H_SYNC_A, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
231
SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
232
SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
233
SRI_ARR(OTG_V_TOTAL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
234
SRI_ARR(OTG_V_BLANK_START_END, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
235
SRI_ARR(OTG_V_SYNC_A, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
236
SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
237
SRI_ARR(OTG_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
238
SRI_ARR(OTG_STEREO_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
239
SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
240
SRI_ARR(OTG_STEREO_STATUS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
241
SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
242
SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
243
SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
244
SRI_ARR(OTG_V_COUNT_STOP_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
245
SRI_ARR(OTG_V_COUNT_STOP_CONTROL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
246
SRI_ARR(OTG_TRIGA_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
247
SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
248
SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
249
SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
250
SRI_ARR(OTG_STATUS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
251
SRI_ARR(OTG_STATUS_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
252
SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
253
SRI_ARR(OTG_M_CONST_DTO0, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
254
SRI_ARR(OTG_M_CONST_DTO1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
255
SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
256
SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
257
SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
258
SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
259
SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
260
SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
261
SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
262
SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
263
SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
264
SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
265
SRI_ARR(CONTROL, VTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
266
SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
267
SRI_ARR(OTG_GSL_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
268
SRI_ARR(OTG_CRC_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
269
SRI_ARR(OTG_CRC0_DATA_RG, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
270
SRI_ARR(OTG_CRC0_DATA_B, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
271
SRI_ARR(OTG_CRC1_DATA_RG, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
272
SRI_ARR(OTG_CRC1_DATA_B, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
273
SRI_ARR(OTG_CRC2_DATA_RG, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
274
SRI_ARR(OTG_CRC2_DATA_B, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
275
SRI_ARR(OTG_CRC3_DATA_RG, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
276
SRI_ARR(OTG_CRC3_DATA_B, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
277
SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
278
SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
279
SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
280
SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
281
SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
282
SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
283
SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
284
SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
285
SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
286
SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
287
SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
288
SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
289
SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
290
SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
291
SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
292
SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
293
SR_ARR(GSL_SOURCE_SELECT, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
294
SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
295
SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
296
SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
297
SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
298
SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
299
SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
300
SRI_ARR(OTG_DSC_START_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
301
SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
302
SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
303
SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
304
SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
305
SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
306
SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
307
SRI_ARR(OTG_DRR_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
308
SRI2_ARR(OPTC_CLOCK_CONTROL, OPTC, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
309
SRI_ARR(INTERRUPT_DEST, OTG, inst)
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1093
tgn10->base.inst = instance;
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1212
struct dc_context *ctx, unsigned int inst)
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1225
return dce_audio_create(ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1226
&audio_regs[inst], &audio_shift, &audio_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1231
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1251
vpg31_construct(vpg31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1252
&vpg_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1261
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1277
afmt31_construct(afmt31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1278
&afmt_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1289
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1303
apg31_construct(apg31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1304
&apg_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1479
uint8_t inst,
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1494
hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1495
&hpo_dp_link_enc_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
163
#define SRII_ARR_2(reg_name, block, id, inst)\
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
164
REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1703
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1718
if (hubp35_construct(hubp2, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1719
&hubp_regs[inst], &hubp_shift, &hubp_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1802
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1819
dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
841
static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
856
success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
871
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
888
dcn35_opp_construct(opp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
889
&opp_regs[inst], &opp_shift, &opp_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
898
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
914
dce110_aux_engine_construct(aux_engine, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
916
&aux_engine_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
961
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
977
dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
978
&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1100
tgn10->base.inst = instance;
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1219
struct dc_context *ctx, unsigned int inst)
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1232
return dce_audio_create(ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1233
&audio_regs[inst], &audio_shift, &audio_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1238
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1258
vpg31_construct(vpg31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1259
&vpg_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1268
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1284
afmt31_construct(afmt31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1285
&afmt_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1296
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1310
apg31_construct(apg31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1311
&apg_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1486
uint8_t inst,
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1501
hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1502
&hpo_dp_link_enc_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
168
#define SRII_ARR_2(reg_name, block, id, inst)\
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
169
REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1710
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1725
if (hubp35_construct(hubp2, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1726
&hubp_regs[inst], &hubp_shift, &hubp_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1809
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1826
dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
848
static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
863
success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
878
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
895
dcn35_opp_construct(opp, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
896
&opp_regs[inst], &opp_shift, &opp_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
905
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
921
dce110_aux_engine_construct(aux_engine, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
923
&aux_engine_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
968
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
984
dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
985
&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1001
if (dpp401_construct(dpp401, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1002
&dpp_regs[inst], &tf_shift, &tf_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1035
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1052
dcn20_opp_construct(opp4, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1053
&opp_regs[inst], &opp_shift, &opp_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1074
tgn10->base.inst = instance;
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1149
struct dc_context *ctx, unsigned int inst)
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1160
return dce_audio_create(ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1161
&audio_regs[inst], &audio_shift, &audio_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1166
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1186
vpg31_construct(vpg4, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1187
&vpg_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1196
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1211
afmt3_construct(afmt401, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1212
&afmt_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1221
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1235
apg31_construct(apg31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1236
&apg_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1408
uint8_t inst,
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1425
hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1426
&hpo_dp_link_enc_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
154
#define SRII_ARR_2(reg_name, block, id, inst)\
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
155
REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1722
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1739
dsc401_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1879
pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
798
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
813
dce110_aux_engine_construct(aux_engine, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
815
&aux_engine_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
837
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
852
dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
853
&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
954
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
969
if (hubp401_construct(hubp2, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
970
&hubp_regs[inst], &hubp_shift, &hubp_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
986
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
475
#define MPC_DWB_MUX_REG_LIST_DCN4_01_RI(inst) \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
476
MPC_DWB_MUX_REG_LIST_DCN3_0_RI(inst)
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
478
#define MPC_OUT_MUX_COMMON_REG_LIST_DCN4_01_RI(inst) \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
479
MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0_RI(inst)
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
481
#define MPC_OUT_MUX_REG_LIST_DCN4_01_RI(inst) \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
482
MPC_OUT_MUX_REG_LIST_DCN3_0_RI(inst)
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
485
#define OPTC_COMMON_REG_LIST_DCN401_RI(inst) \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
486
SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
487
SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
488
SRI_ARR(OTG_VREADY_PARAM, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
489
SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
490
SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
491
SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
492
SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
493
SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
494
SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
495
SRI_ARR(OTG_H_TOTAL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
496
SRI_ARR(OTG_H_BLANK_START_END, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
497
SRI_ARR(OTG_H_SYNC_A, OTG, inst), SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
498
SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), SRI_ARR(OTG_V_TOTAL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
499
SRI_ARR(OTG_V_BLANK_START_END, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
500
SRI_ARR(OTG_V_SYNC_A, OTG, inst), SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
501
SRI_ARR(OTG_CONTROL, OTG, inst), SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
502
SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
503
SRI_ARR(OTG_STEREO_STATUS, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
504
SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
505
SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
506
SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
507
SRI_ARR(OTG_TRIGA_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
508
SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
509
SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
510
SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
511
SRI_ARR(OTG_STATUS, OTG, inst), SRI_ARR(OTG_STATUS_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
512
SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
513
SRI_ARR(OTG_M_CONST_DTO0, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
514
SRI_ARR(OTG_M_CONST_DTO1, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
515
SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
516
SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
517
SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
518
SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
519
SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
520
SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
521
SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
522
SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
523
SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
524
SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
525
SRI_ARR(CONTROL, VTG, inst), SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
526
SRI_ARR(OTG_GSL_CONTROL, OTG, inst), SRI_ARR(OTG_CRC_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
527
SRI_ARR(OTG_CRC0_DATA_RG, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
528
SRI_ARR(OTG_CRC0_DATA_B, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
529
SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
530
SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
531
SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
532
SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
533
SR_ARR(GSL_SOURCE_SELECT, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
534
SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
535
SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
536
SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
537
SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
538
SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
539
SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
540
SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
541
SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
542
SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
543
SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
544
SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
545
SRI_ARR(OPTC_WIDTH_CONTROL2, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
546
SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
547
SRI_ARR(OTG_DRR_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
548
SRI_ARR(OTG_PSTATE_REGISTER, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
549
SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
550
SRI_ARR(INTERRUPT_DEST, OTG, inst)
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1019
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1034
if (dpp42_construct(dpp42, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1035
&dpp_regs[inst], &tf_shift, &tf_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1069
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1085
dcn20_opp_construct(opp4, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1086
&opp_regs[inst], &opp_shift, &opp_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1105
tgn10->base.inst = instance;
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1180
struct dc_context *ctx, unsigned int inst)
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1191
return dce_audio_create(ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1192
&audio_regs[inst], &audio_shift, &audio_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1197
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1216
vpg31_construct(vpg4, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1217
&vpg_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1226
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1246
apg31_construct(apg31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1247
&apg_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1423
uint8_t inst,
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1440
hpo_dp_link_encoder42_construct(hpo_dp_enc31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1441
&hpo_dp_link_enc_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1673
pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
169
#define SRII_ARR_2(reg_name, block, id, inst) \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
170
REG_STRUCT[inst].reg_name[id] = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1787
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
1804
dsc401_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
812
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
828
dce110_aux_engine_construct(aux_engine, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
830
&aux_engine_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
878
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
893
dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
894
&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
977
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
992
if (hubp42_construct(hubp2, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
993
&hubp_regs[inst], &hubp_shift, &hubp_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
434
#define OPTC_COMMON_REG_LIST_DCN42_RI(inst) \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
435
SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
436
SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
437
SRI_ARR(OTG_VREADY_PARAM, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
438
SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
439
SRI_ARR(OTG_MASTER_UPDATE_MODE, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
440
SRI_ARR(OTG_V_COUNT_STOP_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
441
SRI_ARR(OTG_V_COUNT_STOP_CONTROL2, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
442
SRI_ARR(OTG_GSL_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
443
SRI2_ARR(OPTC_CLOCK_CONTROL, OPTC, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
444
SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
445
SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
446
SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
447
SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
448
SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
449
SRI_ARR(OTG_H_TOTAL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
450
SRI_ARR(OTG_H_BLANK_START_END, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
451
SRI_ARR(OTG_H_SYNC_A, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
452
SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
453
SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
454
SRI_ARR(OTG_V_TOTAL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
455
SRI_ARR(OTG_V_BLANK_START_END, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
456
SRI_ARR(OTG_V_SYNC_A, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
457
SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
458
SRI_ARR(OTG_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
459
SRI_ARR(OTG_MASTER_EN, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
460
SRI_ARR(OTG_LONG_VBLANK_STATUS, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
461
SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
462
SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
463
SRI_ARR(OTG_STEREO_STATUS, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
464
SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
465
SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
466
SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
467
SRI_ARR(OTG_TRIGA_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
468
SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
469
SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
470
SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
471
SRI_ARR(OTG_STATUS, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
472
SRI_ARR(OTG_STATUS_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
473
SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
474
SRI_ARR(OTG_M_CONST_DTO0, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
475
SRI_ARR(OTG_M_CONST_DTO1, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
476
SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
477
SRI_ARR(OTG_COUNT_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
478
SRI_ARR(OTG_COUNT_RESET, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
479
SRI_ARR(OTG_CRC_SIG_BLUE_CONTROL_MASK, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
480
SRI_ARR(OTG_CRC_SIG_RED_GREEN_MASK, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
481
SRI_ARR(OTG_DRR_TIMING_INT_STATUS, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
482
SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
483
SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
484
SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
485
SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
486
SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
487
SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
488
SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
489
SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
490
SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
491
SRI_ARR(OPTC_RSMU_UNDERFLOW, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
492
SRI_ARR(OPTC_UNDERFLOW_THRESHOLD, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
493
SRI_ARR(CONTROL, VTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
494
SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
495
SRI_ARR(OTG_GSL_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
496
SRI_ARR(OTG_CRC_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
497
SRI_ARR(OTG_CRC0_DATA_R, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
498
SRI_ARR(OTG_CRC0_DATA_G, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
499
SRI_ARR(OTG_CRC0_DATA_B, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
500
SRI_ARR(OTG_CRC1_DATA_R, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
501
SRI_ARR(OTG_CRC1_DATA_G, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
502
SRI_ARR(OTG_CRC1_DATA_B, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
503
SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
504
SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
505
SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
506
SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
507
SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
508
SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
509
SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
510
SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
511
SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
512
SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
513
SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
514
SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
515
SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
516
SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
517
SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
518
SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
519
SR_ARR(GSL_SOURCE_SELECT, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
520
SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
521
SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
522
SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
523
SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
524
SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
525
SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
526
SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
527
SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
528
SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
529
SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
530
SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
531
SRI_ARR(OPTC_WIDTH_CONTROL2, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
532
SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
533
SRI_ARR(OTG_DRR_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
534
SRI_ARR(OTG_PSTATE_REGISTER, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
535
SRI_ARR(OTG_PWA_FRAME_SYNC_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
536
SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
537
SRI_ARR(INTERRUPT_DEST, OTG, inst)
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1012
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1027
if (hubp42_construct(hubp2, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1028
&hubp_regs[inst], &hubp_shift, &hubp_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1054
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1069
if (dpp42_construct(dpp42b, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1070
&dpp_regs[inst], &tf_shift, &tf_mask))
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1104
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1121
dcn20_opp_construct(opp4, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1122
&opp_regs[inst], &opp_shift, &opp_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1141
tgn10->base.inst = instance;
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1225
struct dc_context *ctx, unsigned int inst)
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1236
return dce_audio_create(ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1237
&audio_regs[inst], &audio_shift, &audio_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1242
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1261
vpg31_construct(vpg4, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1262
&vpg_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1271
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1291
apg31_construct(apg31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1292
&apg_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1404
uint8_t inst,
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1420
hpo_dp_link_encoder42_construct(hpo_dp_enc31, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1421
&hpo_dp_link_enc_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1638
pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1752
struct dc_context *ctx, uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
1769
dsc401_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
202
#define SRII_ARR_2(reg_name, block, id, inst) \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
203
REG_STRUCT[inst].reg_name[id] = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
840
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
857
dce110_aux_engine_construct(aux_engine, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
859
&aux_engine_regs[inst],
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
910
uint32_t inst)
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
927
dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
928
&i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
396
#define OPTC_COMMON_REG_LIST_DCN42B_RI(inst) \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
397
SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
398
SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
399
SRI_ARR(OTG_VREADY_PARAM, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
400
SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
401
SRI_ARR(OTG_MASTER_UPDATE_MODE, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
402
SRI_ARR(OTG_V_COUNT_STOP_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
403
SRI_ARR(OTG_V_COUNT_STOP_CONTROL2, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
404
SRI_ARR(OTG_GSL_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
405
SRI2_ARR(OPTC_CLOCK_CONTROL, OPTC, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
406
SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
407
SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
408
SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
409
SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
410
SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
411
SRI_ARR(OTG_H_TOTAL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
412
SRI_ARR(OTG_H_BLANK_START_END, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
413
SRI_ARR(OTG_H_SYNC_A, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
414
SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
415
SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
416
SRI_ARR(OTG_V_TOTAL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
417
SRI_ARR(OTG_V_BLANK_START_END, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
418
SRI_ARR(OTG_V_SYNC_A, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
419
SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
420
SRI_ARR(OTG_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
421
SRI_ARR(OTG_MASTER_EN, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
422
SRI_ARR(OTG_LONG_VBLANK_STATUS, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
423
SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
424
SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
425
SRI_ARR(OTG_STEREO_STATUS, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
426
SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
427
SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
428
SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
429
SRI_ARR(OTG_TRIGA_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
430
SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
431
SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
432
SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
433
SRI_ARR(OTG_STATUS, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
434
SRI_ARR(OTG_STATUS_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
435
SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
436
SRI_ARR(OTG_M_CONST_DTO0, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
437
SRI_ARR(OTG_M_CONST_DTO1, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
438
SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
439
SRI_ARR(OTG_COUNT_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
440
SRI_ARR(OTG_COUNT_RESET, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
441
SRI_ARR(OTG_CRC_SIG_BLUE_CONTROL_MASK, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
442
SRI_ARR(OTG_CRC_SIG_RED_GREEN_MASK, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
443
SRI_ARR(OTG_DRR_TIMING_INT_STATUS, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
444
SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
445
SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
446
SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
447
SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
448
SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
449
SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
450
SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
451
SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
452
SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
453
SRI_ARR(OPTC_RSMU_UNDERFLOW, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
454
SRI_ARR(OPTC_UNDERFLOW_THRESHOLD, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
455
SRI_ARR(CONTROL, VTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
456
SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
457
SRI_ARR(OTG_GSL_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
458
SRI_ARR(OTG_CRC_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
459
SRI_ARR(OTG_CRC0_DATA_R, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
460
SRI_ARR(OTG_CRC0_DATA_G, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
461
SRI_ARR(OTG_CRC0_DATA_B, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
462
SRI_ARR(OTG_CRC1_DATA_R, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
463
SRI_ARR(OTG_CRC1_DATA_G, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
464
SRI_ARR(OTG_CRC1_DATA_B, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
465
SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
466
SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
467
SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
468
SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
469
SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
470
SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
471
SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
472
SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
473
SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
474
SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
475
SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
476
SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
477
SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
478
SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
479
SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
480
SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
481
SR_ARR(GSL_SOURCE_SELECT, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
482
SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
483
SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
484
SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
485
SRI_ARR(OTG_GLOBAL_CONTROL3, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
486
SRI_ARR(OTG_GLOBAL_SYNC_STATUS, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
487
SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
488
SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
489
SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
490
SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
491
SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
492
SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
493
SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
494
SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
495
SRI_ARR(OPTC_WIDTH_CONTROL2, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
496
SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
497
SRI_ARR(OTG_DRR_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
498
SRI_ARR(OTG_DRR_CONTOL2, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
499
SRI_ARR(OTG_PSTATE_REGISTER, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
500
SRI_ARR(OTG_PWA_FRAME_SYNC_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
501
SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h
502
SRI_ARR(INTERRUPT_DEST, OTG, inst)
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
3026
uint8_t inst : 6; /**< DOMAIN instance to control */
drivers/gpu/drm/amd/display/modules/inc/mod_power.h
233
unsigned int inst);
drivers/gpu/drm/amd/display/modules/inc/mod_power.h
237
unsigned int inst);
drivers/gpu/drm/amd/display/modules/inc/mod_power.h
241
unsigned int inst);
drivers/gpu/drm/amd/display/modules/inc/mod_power.h
247
unsigned int inst);
drivers/gpu/drm/amd/display/modules/inc/mod_power.h
253
unsigned int inst);
drivers/gpu/drm/amd/display/modules/inc/mod_power.h
269
unsigned int inst);
drivers/gpu/drm/amd/display/modules/inc/mod_power.h
281
unsigned int inst);
drivers/gpu/drm/amd/display/modules/inc/mod_power.h
292
unsigned int inst);
drivers/gpu/drm/amd/display/modules/inc/mod_power.h
296
unsigned int inst);
drivers/gpu/drm/amd/display/modules/inc/mod_power.h
329
unsigned int inst);
drivers/gpu/drm/amd/display/modules/power/power.c
108
unsigned int inst = 0;
drivers/gpu/drm/amd/display/modules/power/power.c
141
for (inst = 0; inst < edp_num; inst++) {
drivers/gpu/drm/amd/display/modules/power/power.c
142
core_power->bl_prop[inst].min_abm_backlight =
drivers/gpu/drm/amd/display/modules/power/power.c
143
init_params[inst].min_abm_backlight;
drivers/gpu/drm/amd/display/modules/power/power.c
144
core_power->bl_prop[inst].disable_fractional_pwm =
drivers/gpu/drm/amd/display/modules/power/power.c
145
init_params[inst].disable_fractional_pwm;
drivers/gpu/drm/amd/display/modules/power/power.c
146
core_power->bl_prop[inst].use_linear_backlight_curve =
drivers/gpu/drm/amd/display/modules/power/power.c
147
init_params[inst].use_linear_backlight_curve;
drivers/gpu/drm/amd/display/modules/power/power.c
148
core_power->bl_prop[inst].use_nits_based_brightness =
drivers/gpu/drm/amd/display/modules/power/power.c
149
init_params[inst].use_nits_based_brightness;
drivers/gpu/drm/amd/display/modules/power/power.c
150
core_power->bl_prop[inst].backlight_ramping_override =
drivers/gpu/drm/amd/display/modules/power/power.c
151
init_params[inst].backlight_ramping_override;
drivers/gpu/drm/amd/display/modules/power/power.c
152
core_power->bl_prop[inst].backlight_ramping_reduction =
drivers/gpu/drm/amd/display/modules/power/power.c
153
init_params[inst].backlight_ramping_reduction;
drivers/gpu/drm/amd/display/modules/power/power.c
154
core_power->bl_prop[inst].backlight_ramping_start =
drivers/gpu/drm/amd/display/modules/power/power.c
155
init_params[inst].backlight_ramping_start;
drivers/gpu/drm/amd/display/modules/power/power.c
156
core_power->bl_prop[inst].use_custom_backlight_caps =
drivers/gpu/drm/amd/display/modules/power/power.c
157
init_params[inst].use_custom_backlight_caps;
drivers/gpu/drm/amd/display/modules/power/power.c
158
core_power->bl_prop[inst].custom_backlight_caps_config_no =
drivers/gpu/drm/amd/display/modules/power/power.c
159
init_params[inst].custom_backlight_caps_config_no;
drivers/gpu/drm/amd/display/modules/power/power.c
162
if (init_params[inst].num_backlight_levels < 101)
drivers/gpu/drm/amd/display/modules/power/power.c
163
core_power->bl_prop[inst].num_backlight_levels = 101;
drivers/gpu/drm/amd/display/modules/power/power.c
165
core_power->bl_prop[inst].num_backlight_levels =
drivers/gpu/drm/amd/display/modules/power/power.c
166
init_params[inst].num_backlight_levels;
drivers/gpu/drm/amd/display/modules/power/power.c
168
core_power->bl_prop[inst].backlight_lut = (unsigned int *)
drivers/gpu/drm/amd/display/modules/power/power.c
170
core_power->bl_prop[inst].num_backlight_levels, GFP_KERNEL));
drivers/gpu/drm/amd/display/modules/power/power.c
171
if (core_power->bl_prop[inst].backlight_lut == NULL)
drivers/gpu/drm/amd/display/modules/power/power.c
207
for (inst = 0; inst < edp_num; inst++) {
drivers/gpu/drm/amd/display/modules/power/power.c
208
core_power->bl_prop[inst].backlight_lut[0] = init_params[inst].min_backlight_pwm;
drivers/gpu/drm/amd/display/modules/power/power.c
209
core_power->bl_prop[inst].backlight_lut[
drivers/gpu/drm/amd/display/modules/power/power.c
210
core_power->bl_prop[inst].num_backlight_levels-1] =
drivers/gpu/drm/amd/display/modules/power/power.c
211
init_params[inst].max_backlight_pwm;
drivers/gpu/drm/amd/display/modules/power/power.c
212
core_power->bl_prop[inst].min_backlight_pwm = init_params[inst].min_backlight_pwm;
drivers/gpu/drm/amd/display/modules/power/power.c
213
core_power->bl_prop[inst].max_backlight_pwm = init_params[inst].max_backlight_pwm;
drivers/gpu/drm/amd/display/modules/power/power.c
214
core_power->bl_prop[inst].ac_backlight_percent =
drivers/gpu/drm/amd/display/modules/power/power.c
216
core_power->bl_prop[inst].dc_backlight_percent =
drivers/gpu/drm/amd/display/modules/power/power.c
218
core_power->bl_prop[inst].backlight_caps_valid = false;
drivers/gpu/drm/amd/display/modules/power/power.c
220
if (core_power->bl_prop[inst].use_nits_based_brightness) {
drivers/gpu/drm/amd/display/modules/power/power.c
221
core_power->bl_prop[inst].min_brightness_millinits =
drivers/gpu/drm/amd/display/modules/power/power.c
222
init_params[inst].panel_min_millinits;
drivers/gpu/drm/amd/display/modules/power/power.c
223
core_power->bl_prop[inst].max_brightness_millinits =
drivers/gpu/drm/amd/display/modules/power/power.c
224
init_params[inst].panel_max_millinits;
drivers/gpu/drm/amd/display/modules/power/power.c
227
core_power->bl_prop[inst].min_brightness_millinits =
drivers/gpu/drm/amd/display/modules/power/power.c
229
core_power->bl_prop[inst].max_brightness_millinits =
drivers/gpu/drm/amd/display/modules/power/power.c
233
core_power->bl_prop[inst].backlight_range =
drivers/gpu/drm/amd/display/modules/power/power.c
234
core_power->bl_prop[inst].max_backlight_pwm-
drivers/gpu/drm/amd/display/modules/power/power.c
235
core_power->bl_prop[inst].min_backlight_pwm;
drivers/gpu/drm/amd/display/modules/power/power.c
237
core_power->bl_prop[inst].nits_range =
drivers/gpu/drm/amd/display/modules/power/power.c
238
core_power->bl_prop[inst].max_brightness_millinits -
drivers/gpu/drm/amd/display/modules/power/power.c
239
core_power->bl_prop[inst].min_brightness_millinits;
drivers/gpu/drm/amd/display/modules/power/power.c
241
core_power->bl_state[inst].smooth_brightness_enabled = true;
drivers/gpu/drm/amd/display/modules/power/power.c
245
for (inst = 0; inst < edp_num; inst++) {
drivers/gpu/drm/amd/display/modules/power/power.c
246
if (core_power->bl_prop[inst].nits_range != 0 && core_power->bl_prop[inst].backlight_range != 0) {
drivers/gpu/drm/amd/display/modules/power/power.c
258
for (inst = 0; inst < edp_num; inst++) {
drivers/gpu/drm/amd/display/modules/power/power.c
259
initialize_backlight_caps(core_power, inst);
drivers/gpu/drm/amd/display/modules/power/power.c
260
core_power->bl_state[inst].backlight_millipercent =
drivers/gpu/drm/amd/display/modules/power/power.c
261
core_power->bl_prop[inst].dc_backlight_percent * 1000;
drivers/gpu/drm/amd/display/modules/power/power.c
262
core_power->bl_state[inst].backlight_pwm = backlight_millipercent_to_pwm(core_power,
drivers/gpu/drm/amd/display/modules/power/power.c
263
core_power->bl_state[inst].backlight_millipercent, inst);
drivers/gpu/drm/amd/display/modules/power/power.c
264
core_power->bl_state[inst].backlight_millinit = backlight_millipercent_to_millinit(core_power,
drivers/gpu/drm/amd/display/modules/power/power.c
265
core_power->bl_state[inst].backlight_millipercent, inst);
drivers/gpu/drm/amd/display/modules/power/power.c
272
for (inst = 0; inst < edp_num; inst++)
drivers/gpu/drm/amd/display/modules/power/power.c
273
if (core_power->bl_prop[inst].backlight_lut)
drivers/gpu/drm/amd/display/modules/power/power.c
274
kfree(core_power->bl_prop[inst].backlight_lut);
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1006
if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst))
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1009
core_power->bl_state[inst].backlight_millinit = backlight_millinit;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1011
core_power->bl_state[inst].backlight_millipercent = backlight_millinit_to_millipercent(
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1012
core_power, backlight_millinit, inst);
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1013
core_power->bl_state[inst].backlight_pwm = backlight_millinit_to_pwm(
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1014
core_power, backlight_millinit, inst);
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1019
unsigned int inst)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1028
*backlight_pwm = core_power->bl_state[inst].backlight_pwm;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1035
unsigned int inst)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1044
*backlight_millinit = core_power->bl_state[inst].backlight_millinit;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1051
unsigned int inst)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1060
*backlight_millipercent = core_power->bl_state[inst].backlight_millipercent;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1068
unsigned int inst)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1082
backlight_u16_16, inst);
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1091
unsigned int inst)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1105
backlight_u16_16, inst);
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1126
unsigned int inst)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1139
backlight_u16_16, inst);
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1184
unsigned int inst)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1197
backlight_u16_16, inst);
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1221
unsigned int inst)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1233
if (core_power->bl_prop[inst].backlight_caps_valid) {
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1234
*out_min_backlight = core_power->bl_prop[inst].backlight_lut[0];
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1236
core_power->bl_prop[inst].backlight_lut[
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1237
core_power->bl_prop[inst].num_backlight_levels - 1];
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1239
core_power->bl_prop[inst].ac_backlight_percent;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1241
core_power->bl_prop[inst].dc_backlight_percent;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1251
unsigned int inst)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1260
core_power->bl_state[inst].smooth_brightness_enabled = enable_brightness;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1441
unsigned int inst)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1450
mod_power_get_backlight_pwm(mod_power, &user_backlight, inst);
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1928
unsigned int inst)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1936
if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1993
if (res_pool->multiple_abms[inst]) {
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1994
result = res_pool->multiple_abms[inst]->funcs->init_abm_config(
drivers/gpu/drm/amd/display/modules/power/power_abm.c
1995
res_pool->multiple_abms[inst], (char *)(&config), sizeof(struct abm_config_table), inst);
drivers/gpu/drm/amd/display/modules/power/power_abm.c
254
struct core_power *core_power, unsigned int millipercent, unsigned int inst)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
263
core_power->bl_prop[inst].nits_range;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
265
core_power->bl_prop[inst].min_brightness_millinits;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
271
struct core_power *core_power, unsigned int millinit, unsigned int inst)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
279
if (millinit <= core_power->bl_prop[inst].min_brightness_millinits)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
282
if (millinit >= core_power->bl_prop[inst].max_brightness_millinits)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
286
core_power->bl_prop[inst].min_brightness_millinits) * 100000;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
288
core_power->bl_prop[inst].nits_range));
drivers/gpu/drm/amd/display/modules/power/power_abm.c
294
struct core_power *core_power, unsigned int pwm, unsigned int inst)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
302
if (!core_power->bl_prop[inst].backlight_caps_valid)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
308
if (core_power->bl_prop[inst].num_backlight_levels < 2)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
311
max_index = core_power->bl_prop[inst].num_backlight_levels - 1;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
313
if (pwm <= core_power->bl_prop[inst].backlight_lut[0])
drivers/gpu/drm/amd/display/modules/power/power_abm.c
316
if (pwm > core_power->bl_prop[inst].backlight_lut[max_index])
drivers/gpu/drm/amd/display/modules/power/power_abm.c
329
if (core_power->bl_prop[inst].backlight_lut[mid] < pwm)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
331
else if (core_power->bl_prop[inst].backlight_lut[mid] > pwm)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
345
min_delta = (core_power->bl_prop[inst].backlight_lut[min] > pwm) ?
drivers/gpu/drm/amd/display/modules/power/power_abm.c
346
core_power->bl_prop[inst].backlight_lut[min] - pwm :
drivers/gpu/drm/amd/display/modules/power/power_abm.c
347
pwm - core_power->bl_prop[inst].backlight_lut[min];
drivers/gpu/drm/amd/display/modules/power/power_abm.c
349
mid_delta = (core_power->bl_prop[inst].backlight_lut[mid] > pwm) ?
drivers/gpu/drm/amd/display/modules/power/power_abm.c
350
core_power->bl_prop[inst].backlight_lut[mid] - pwm :
drivers/gpu/drm/amd/display/modules/power/power_abm.c
351
pwm - core_power->bl_prop[inst].backlight_lut[mid];
drivers/gpu/drm/amd/display/modules/power/power_abm.c
353
max_delta = (core_power->bl_prop[inst].backlight_lut[max] > pwm) ?
drivers/gpu/drm/amd/display/modules/power/power_abm.c
354
core_power->bl_prop[inst].backlight_lut[max] - pwm :
drivers/gpu/drm/amd/display/modules/power/power_abm.c
355
pwm - core_power->bl_prop[inst].backlight_lut[max];
drivers/gpu/drm/amd/display/modules/power/power_abm.c
371
struct core_power *core_power, unsigned int pwm, unsigned int inst)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
378
if (pwm <= core_power->bl_prop[inst].min_backlight_pwm)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
379
return core_power->bl_prop[inst].min_brightness_millinits;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
381
if (pwm >= core_power->bl_prop[inst].max_backlight_pwm)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
382
return core_power->bl_prop[inst].max_brightness_millinits;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
385
core_power->bl_prop[inst].min_backlight_pwm) *
drivers/gpu/drm/amd/display/modules/power/power_abm.c
386
core_power->bl_prop[inst].nits_range,
drivers/gpu/drm/amd/display/modules/power/power_abm.c
387
core_power->bl_prop[inst].backlight_range));
drivers/gpu/drm/amd/display/modules/power/power_abm.c
389
millinit += core_power->bl_prop[inst].min_brightness_millinits;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
391
if (millinit > core_power->bl_prop[inst].max_brightness_millinits)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
392
millinit = core_power->bl_prop[inst].max_brightness_millinits;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
398
struct core_power *core_power, unsigned int millipercent, unsigned int inst)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
408
pwm = core_power->bl_prop[inst].min_backlight_pwm +
drivers/gpu/drm/amd/display/modules/power/power_abm.c
410
core_power->bl_prop[inst].backlight_range,
drivers/gpu/drm/amd/display/modules/power/power_abm.c
413
if (pwm > core_power->bl_prop[inst].max_backlight_pwm)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
414
pwm = core_power->bl_prop[inst].max_backlight_pwm;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
420
return core_power->bl_prop[inst].backlight_lut[core_power->bl_prop[inst].num_backlight_levels - 1];
drivers/gpu/drm/amd/display/modules/power/power_abm.c
423
index = ((core_power->bl_prop[inst].num_backlight_levels - 1) *
drivers/gpu/drm/amd/display/modules/power/power_abm.c
426
if (core_power->bl_prop[inst].backlight_lut == NULL)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
429
pwm = core_power->bl_prop[inst].backlight_lut[index];
drivers/gpu/drm/amd/display/modules/power/power_abm.c
435
struct core_power *core_power, unsigned int millinit, unsigned int inst)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
445
if (millinit >= core_power->bl_prop[inst].max_brightness_millinits)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
446
return core_power->bl_prop[inst].max_backlight_pwm;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
447
else if (millinit <= core_power->bl_prop[inst].min_brightness_millinits)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
448
return core_power->bl_prop[inst].min_backlight_pwm;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
451
core_power->bl_prop[inst].min_brightness_millinits) *
drivers/gpu/drm/amd/display/modules/power/power_abm.c
452
core_power->bl_prop[inst].backlight_range,
drivers/gpu/drm/amd/display/modules/power/power_abm.c
453
core_power->bl_prop[inst].nits_range));
drivers/gpu/drm/amd/display/modules/power/power_abm.c
455
pwm += core_power->bl_prop[inst].min_backlight_pwm;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
457
if (pwm > core_power->bl_prop[inst].max_backlight_pwm)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
458
pwm = core_power->bl_prop[inst].max_backlight_pwm;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
509
void initialize_backlight_caps(struct core_power *core_power, unsigned int inst)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
517
(inst == 0) ? AcpiDisplayType_LCD1 : AcpiDisplayType_LCD2;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
523
num_levels = core_power->bl_prop[inst].num_backlight_levels;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
541
if (core_power->bl_prop[inst].use_custom_backlight_caps &&
drivers/gpu/drm/amd/display/modules/power/power_abm.c
543
core_power->bl_prop[inst].custom_backlight_caps_config_no,
drivers/gpu/drm/amd/display/modules/power/power_abm.c
552
core_power->bl_prop[inst].ac_backlight_percent =
drivers/gpu/drm/amd/display/modules/power/power_abm.c
554
core_power->bl_prop[inst].dc_backlight_percent =
drivers/gpu/drm/amd/display/modules/power/power_abm.c
556
core_power->bl_prop[inst].backlight_lut[0] =
drivers/gpu/drm/amd/display/modules/power/power_abm.c
559
core_power->bl_prop[inst].backlight_lut[num_levels - 1] =
drivers/gpu/drm/amd/display/modules/power/power_abm.c
580
core_power->bl_prop[inst].backlight_lut[index-1];
drivers/gpu/drm/amd/display/modules/power/power_abm.c
588
core_power->bl_prop[inst].backlight_lut[index] =
drivers/gpu/drm/amd/display/modules/power/power_abm.c
597
core_power->bl_prop[inst].backlight_lut[index++] = signal_level;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
605
core_power->bl_prop[inst].backlight_lut[index-1];
drivers/gpu/drm/amd/display/modules/power/power_abm.c
607
core_power->bl_prop[inst].backlight_lut[num_levels - 1] -
drivers/gpu/drm/amd/display/modules/power/power_abm.c
613
core_power->bl_prop[inst].backlight_lut[index] =
drivers/gpu/drm/amd/display/modules/power/power_abm.c
636
core_power->bl_prop[inst].backlight_lut[num_levels - 1] -
drivers/gpu/drm/amd/display/modules/power/power_abm.c
637
core_power->bl_prop[inst].backlight_lut[0];
drivers/gpu/drm/amd/display/modules/power/power_abm.c
638
unsigned int coeffC = core_power->bl_prop[inst].backlight_lut[0];
drivers/gpu/drm/amd/display/modules/power/power_abm.c
649
core_power->bl_prop[inst].backlight_lut[i] = (unsigned int)lut_val;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
657
core_power->bl_prop[inst].backlight_caps_valid = true;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
737
unsigned int inst)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
749
return dc_link_set_backlight_level_nits(link, core_power->bl_state[inst].isHDR,
drivers/gpu/drm/amd/display/modules/power/power_abm.c
756
unsigned int inst)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
769
core_power->bl_state[inst].backlight_pwm = backlight_pwm_u16_16;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
786
if (core_power->bl_state[inst].smooth_brightness_enabled)
drivers/gpu/drm/amd/display/modules/power/power_abm.c
791
core_power->bl_state[inst].frame_ramp = frame_ramp;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
890
unsigned int inst = 0;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
897
if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst))
drivers/gpu/drm/amd/display/modules/power/power_abm.c
901
core_power, backlight_millipercent, inst);
drivers/gpu/drm/amd/display/modules/power/power_abm.c
911
unsigned int inst = 0;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
918
if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst))
drivers/gpu/drm/amd/display/modules/power/power_abm.c
922
core_power, backlight_millinit, inst);
drivers/gpu/drm/amd/display/modules/power/power_abm.c
975
unsigned int inst = 0;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
982
if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst))
drivers/gpu/drm/amd/display/modules/power/power_abm.c
984
core_power->bl_state[inst].backlight_millipercent = backlight_millipercent;
drivers/gpu/drm/amd/display/modules/power/power_abm.c
986
core_power->bl_state[inst].backlight_millinit =
drivers/gpu/drm/amd/display/modules/power/power_abm.c
988
core_power, backlight_millipercent, inst);
drivers/gpu/drm/amd/display/modules/power/power_abm.c
990
core_power->bl_state[inst].backlight_pwm = backlight_millipercent_to_pwm(
drivers/gpu/drm/amd/display/modules/power/power_abm.c
991
core_power, backlight_millipercent, inst);
drivers/gpu/drm/amd/display/modules/power/power_abm.c
999
unsigned int inst = 0;
drivers/gpu/drm/amd/display/modules/power/power_helpers.h
147
unsigned int inst);
drivers/gpu/drm/amd/display/modules/power/power_helpers.h
182
void initialize_backlight_caps(struct core_power *core_power, unsigned int inst);
drivers/gpu/drm/amd/display/modules/power/power_helpers.h
184
struct core_power *core_power, unsigned int millipercent, unsigned int inst);
drivers/gpu/drm/amd/display/modules/power/power_helpers.h
186
struct core_power *core_power, unsigned int millipercent, unsigned int inst);
drivers/gpu/drm/amd/include/kgd_kfd_interface.h
226
uint32_t inst);
drivers/gpu/drm/amd/include/kgd_kfd_interface.h
229
unsigned int vmid, uint32_t inst);
drivers/gpu/drm/amd/include/kgd_kfd_interface.h
232
uint32_t inst);
drivers/gpu/drm/amd/include/kgd_kfd_interface.h
237
struct mm_struct *mm, uint32_t inst);
drivers/gpu/drm/amd/include/kgd_kfd_interface.h
241
uint32_t doorbell_off, uint32_t inst);
drivers/gpu/drm/amd/include/kgd_kfd_interface.h
248
uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst);
drivers/gpu/drm/amd/include/kgd_kfd_interface.h
256
uint32_t queue_id, uint32_t inst);
drivers/gpu/drm/amd/include/kgd_kfd_interface.h
261
uint32_t queue_id, uint32_t inst);
drivers/gpu/drm/amd/include/kgd_kfd_interface.h
270
uint32_t sq_cmd, uint32_t inst);
drivers/gpu/drm/amd/include/kgd_kfd_interface.h
311
uint32_t inst);
drivers/gpu/drm/amd/include/kgd_kfd_interface.h
316
uint32_t inst);
drivers/gpu/drm/amd/include/kgd_kfd_interface.h
325
int *max_waves_per_cu, uint32_t inst);
drivers/gpu/drm/amd/include/kgd_kfd_interface.h
328
uint32_t inst);
drivers/gpu/drm/amd/include/kgd_kfd_interface.h
331
uint32_t inst);
drivers/gpu/drm/amd/include/kgd_kfd_interface.h
334
uint32_t inst, unsigned int utimeout);
drivers/gpu/drm/amd/include/kgd_pp_interface.h
460
int inst);
drivers/gpu/drm/amd/include/kgd_pp_interface.h
693
#define AMDGPU_METRICS_ENC_ATTR(unit, type, id, inst) \
drivers/gpu/drm/amd/include/kgd_pp_interface.h
696
((u64)(id) << AMDGPU_METRICS_ATTR_ID_SHIFT) | (inst))
drivers/gpu/drm/amd/pm/amdgpu_dpm.c
109
(adev)->powerplay.pp_handle, block_type, gate, inst));
drivers/gpu/drm/amd/pm/amdgpu_dpm.c
615
void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable, int inst)
drivers/gpu/drm/amd/pm/amdgpu_dpm.c
619
ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCN, !enable, inst);
drivers/gpu/drm/amd/pm/amdgpu_dpm.c
76
int inst)
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
397
uint32_t block_type, bool gate, int inst);
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
448
void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable, int inst);
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
3295
int inst)
drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
1205
int inst)
drivers/gpu/drm/amd/pm/powerplay/hwmgr/common_baco.c
112
reg = adev->reg_offset[entry[i].hwip][entry[i].inst][entry[i].seg]
drivers/gpu/drm/amd/pm/powerplay/hwmgr/common_baco.h
48
uint32_t inst;
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
2172
adev->vcn.inst[i].cur_state = AMD_PG_STATE_GATE;
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
253
int inst)
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
268
if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable)
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
271
ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, inst);
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
273
atomic_set(&power_gate->vcn_gated[inst], !enable);
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
394
int inst)
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
413
ret = smu_dpm_set_vcn_enable(smu, !gate, inst);
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
416
gate ? "gate" : "ungate", inst);
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
940
int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable, int inst);
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
229
int inst);
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
187
int inst);
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h
197
int inst);
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
1543
int inst)
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1130
int inst)
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1155
int inst)
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1160
if (adev->vcn.harvest_config & (1 << inst))
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1166
0x10000 * inst, NULL);
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
469
int inst)
drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
639
int inst)
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1948
int inst)
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1953
if (adev->vcn.harvest_config & (1 << inst))
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1958
inst << 16U, NULL);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
1000
metrics->GfxclkLowUtilizationAcc[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
1003
metrics->GfxclkBelowHostLimitTotalAcc[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
1007
gpu_metrics->temperature_xcd[i] = metrics->XcdTemperature[inst];
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
793
int inst, j, k, idx;
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
802
inst = GET_INST(VCN, k);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
806
JpegBusy[(inst * num_jpeg_rings) + j]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
809
SMUQ10_ROUND(metrics->VcnBusy[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
811
metrics->VclkFrequency[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
813
metrics->DclkFrequency[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
815
metrics->SocclkFrequency[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
826
inst = GET_INST(GC, k);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
827
xcp_metrics->current_gfxclk[idx] = SMUQ10_ROUND(metrics->GfxclkFrequency[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
828
xcp_metrics->gfx_busy_inst[idx] = SMUQ10_ROUND(metrics->GfxBusy[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
829
xcp_metrics->gfx_busy_acc[idx] = SMUQ10_ROUND(metrics->GfxBusyAcc[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
831
xcp_metrics->gfx_below_host_limit_ppt_acc[idx] = SMUQ10_ROUND(metrics->GfxclkBelowHostLimitPptAcc[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
832
xcp_metrics->gfx_below_host_limit_thm_acc[idx] = SMUQ10_ROUND(metrics->GfxclkBelowHostLimitThmAcc[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
833
xcp_metrics->gfx_low_utilization_acc[idx] = SMUQ10_ROUND(metrics->GfxclkLowUtilizationAcc[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
834
xcp_metrics->gfx_below_host_limit_total_acc[idx] = SMUQ10_ROUND(metrics->GfxclkBelowHostLimitTotalAcc[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
850
int ret = 0, xcc_id, inst, i, j, idx;
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
912
inst = GET_INST(VCN, i);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
913
if (inst >= 0) {
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
915
SMUQ10_ROUND(metrics->VclkFrequency[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
917
SMUQ10_ROUND(metrics->DclkFrequency[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
972
inst = GET_INST(VCN, i);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
978
metrics->JpegBusy[(inst *
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
982
gpu_metrics->vcn_busy[i] = SMUQ10_ROUND(metrics->VcnBusy[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
986
inst = GET_INST(GC, i);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
988
SMUQ10_ROUND(metrics->GfxBusy[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
990
SMUQ10_ROUND(metrics->GfxBusyAcc[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
995
metrics->GfxclkBelowHostLimitPptAcc[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
998
metrics->GfxclkBelowHostLimitThmAcc[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
201
int inst)
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2666
int ret, inst, i, j, k, idx;
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2708
inst = GET_INST(VCN, k);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2714
version)[(inst * num_jpeg_rings) + j]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2717
SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, version)[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2720
GET_METRIC_FIELD(VclkFrequency, version)[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2722
GET_METRIC_FIELD(DclkFrequency, version)[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2724
GET_METRIC_FIELD(SocclkFrequency, version)[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2736
inst = GET_INST(GC, k);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2739
version)[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2742
GET_GPU_METRIC_FIELD(GfxBusy, version)[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2745
version)[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2751
[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2755
[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2759
->GfxclkLowUtilizationAcc[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2763
[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2780
int ret = 0, xcc_id, inst, i, j;
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2837
inst = GET_INST(VCN, i);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2838
if (inst >= 0) {
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2841
version)[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2844
version)[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2930
inst = GET_INST(JPEG, i);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2935
version)[(inst * num_jpeg_rings) + j]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2938
inst = GET_INST(VCN, i);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2940
SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, version)[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2945
inst = GET_INST(GC, i);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2947
GET_GPU_METRIC_FIELD(GfxBusy, version)[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2950
version)[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2956
[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2960
[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2964
->GfxclkLowUtilizationAcc[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2968
[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
228
int inst)
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1500
int inst)
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1505
if (adev->vcn.harvest_config & (1 << inst))
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1509
if (inst == 0)
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1512
inst << 16U, NULL);
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1513
else if (inst == 1)
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1516
inst << 16U, NULL);
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1520
inst << 16U, NULL);
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c
1373
int inst)
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c
1378
if (adev->vcn.harvest_config & (1 << inst))
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c
1384
inst << 16U, NULL);
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
1611
int ret, inst, i, j, k, idx;
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
1638
inst = GET_INST(VCN, k);
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
1641
SMUQ10_ROUND(metrics->JpegBusy[(inst * num_jpeg_rings) + j]);
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
1644
SMUQ10_ROUND(metrics->VcnBusy[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
1646
xcp_metrics->current_vclk[idx] = SMUQ10_ROUND(metrics->VclkFrequency[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
1647
xcp_metrics->current_dclk[idx] = SMUQ10_ROUND(metrics->DclkFrequency[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
1655
inst = GET_INST(GC, k);
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
1657
SMUQ10_ROUND(metrics->GfxclkFrequency[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
1659
xcp_metrics->gfx_busy_inst[idx] = SMUQ10_ROUND(metrics->GfxBusy[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
1660
xcp_metrics->gfx_busy_acc[idx] = SMUQ10_ROUND(metrics->GfxBusyAcc[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
1662
SMUQ10_ROUND(metrics->GfxclkBelowHostLimitPptAcc[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
1664
SMUQ10_ROUND(metrics->GfxclkBelowHostLimitThmAcc[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
1666
SMUQ10_ROUND(metrics->GfxclkLowUtilizationAcc[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
1668
SMUQ10_ROUND(metrics->GfxclkBelowHostLimitTotalAcc[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
1683
int ret = 0, xcc_id, inst, i, j, idx;
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
1771
inst = GET_INST(VCN, i);
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
1772
if (inst >= 0) {
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
1773
gpu_metrics->current_vclk0[i] = SMUQ10_ROUND(metrics->VclkFrequency[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
1774
gpu_metrics->current_dclk0[i] = SMUQ10_ROUND(metrics->DclkFrequency[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
1811
inst = GET_INST(GC, i);
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
1812
gpu_metrics->gfx_busy_inst[i] = SMUQ10_ROUND(metrics->GfxBusy[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
1813
gpu_metrics->gfx_busy_acc[i] = SMUQ10_ROUND(metrics->GfxBusyAcc[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
1815
SMUQ10_ROUND(metrics->GfxclkBelowHostLimitPptAcc[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
1817
SMUQ10_ROUND(metrics->GfxclkBelowHostLimitThmAcc[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
1819
SMUQ10_ROUND(metrics->GfxclkLowUtilizationAcc[inst]);
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
1821
SMUQ10_ROUND(metrics->GfxclkBelowHostLimitTotalAcc[inst]);
drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h
76
#define RAS_DEV_RREG32_SOC15(dev, ip, inst, reg) \
drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h
79
__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h
80
0, ip##_HWIP, inst); \
drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h
83
#define RAS_DEV_WREG32_SOC15(dev, ip, inst, reg, value) \
drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h
86
__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \
drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h
87
value, 0, ip##_HWIP, inst); \
drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h
91
#define RAS_GET_INST(dev, ip, inst) \
drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h
95
adev->ip_map.logical_to_dev_inst(adev, ip##_HWIP, inst) : inst; \
drivers/gpu/drm/etnaviv/etnaviv_flop_reset.c
110
static const u32 inst[PPU_FLOP_RESET_INSTR_DWORD_COUNT] = {
drivers/gpu/drm/etnaviv/etnaviv_flop_reset.c
132
memcpy(dest, inst, sizeof(inst));
drivers/gpu/drm/i915/display/intel_display_power_map.c
1762
static void init_power_well_domains(const struct i915_power_well_instance *inst,
drivers/gpu/drm/i915/display/intel_display_power_map.c
1767
if (!inst->domain_list)
drivers/gpu/drm/i915/display/intel_display_power_map.c
1770
if (inst->domain_list->count == 0) {
drivers/gpu/drm/i915/display/intel_display_power_map.c
1776
for (j = 0; j < inst->domain_list->count; j++)
drivers/gpu/drm/i915/display/intel_display_power_map.c
1777
set_bit(inst->domain_list->list[j], power_well->domains.bits);
drivers/gpu/drm/i915/display/intel_display_power_map.c
1804
const struct i915_power_well_instance *inst;
drivers/gpu/drm/i915/display/intel_display_power_map.c
1808
for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst)
drivers/gpu/drm/i915/display/intel_display_power_map.c
1818
for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) {
drivers/gpu/drm/i915/display/intel_display_power_map.c
1820
enum i915_power_well_id id = inst->id;
drivers/gpu/drm/i915/display/intel_display_power_map.c
1824
overflows_type(inst - desc->instances->list, pw->instance_idx));
drivers/gpu/drm/i915/display/intel_display_power_map.c
1825
pw->instance_idx = inst - desc->instances->list;
drivers/gpu/drm/i915/display/intel_display_power_map.c
1827
init_power_well_domains(inst, pw);
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
709
int inst = 0;
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
724
inst++);
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
1246
int inst = 0;
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
1268
inst++);
drivers/gpu/drm/i915/gt/intel_engine_user.c
266
int class, inst;
drivers/gpu/drm/i915/gt/intel_engine_user.c
270
for (inst = 0; inst < i915->engine_uabi_class_count[class]; inst++) {
drivers/gpu/drm/i915/gt/intel_engine_user.c
272
class, inst);
drivers/gpu/drm/i915/gt/intel_engine_user.c
275
class, inst);
drivers/gpu/drm/i915/gt/intel_engine_user.c
281
engine->uabi_instance != inst) {
drivers/gpu/drm/i915/gt/intel_engine_user.c
286
class, inst);
drivers/gpu/drm/i915/gt/selftest_execlists.c
3845
unsigned int inst;
drivers/gpu/drm/i915/gt/selftest_execlists.c
3847
for (inst = 0; inst <= MAX_ENGINE_INSTANCE; inst++) {
drivers/gpu/drm/i915/gt/selftest_execlists.c
3848
if (!gt->engine_class[class][inst])
drivers/gpu/drm/i915/gt/selftest_execlists.c
3851
if (filter && !filter(gt->engine_class[class][inst]))
drivers/gpu/drm/i915/gt/selftest_execlists.c
3854
siblings[n++] = gt->engine_class[class][inst];
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
353
u8 group, inst;
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
363
intel_gt_mcr_get_nonterminated_steering(gt, reg, &group, &inst);
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
364
flags |= GUC_REGSET_STEERING(group, inst);
drivers/gpu/drm/nouveau/include/nvif/if0020.h
31
__u64 inst;
drivers/gpu/drm/nouveau/include/nvif/ifc00d.h
40
__u64 inst;
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
113
u32 inst; \
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
114
int (*ctor)(struct nvkm_device *, enum nvkm_subdev_type, int inst, data **); \
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
81
struct nvkm_subdev *nvkm_device_subdev(struct nvkm_device *, int type, int inst);
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
82
struct nvkm_engine *nvkm_device_engine(struct nvkm_device *, int type, int inst);
drivers/gpu/drm/nouveau/include/nvkm/core/engine.h
46
enum nvkm_subdev_type, int inst, bool enable, struct nvkm_engine *);
drivers/gpu/drm/nouveau/include/nvkm/core/enum.h
11
int inst;
drivers/gpu/drm/nouveau/include/nvkm/core/falcon.h
133
struct nvkm_memory *inst;
drivers/gpu/drm/nouveau/include/nvkm/core/falcon.h
152
struct nvkm_memory *inst);
drivers/gpu/drm/nouveau/include/nvkm/core/intr.h
30
int inst;
drivers/gpu/drm/nouveau/include/nvkm/core/ramht.h
8
struct nvkm_gpuobj *inst;
drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h
19
int inst;
drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h
49
int inst, struct nvkm_subdev **);
drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h
51
enum nvkm_subdev_type, int inst, struct nvkm_subdev *);
drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h
55
enum nvkm_subdev_type type, int inst, struct nvkm_subdev *subdev)
drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h
57
__nvkm_subdev_ctor(func, device, type, inst, subdev);
drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h
61
void nvkm_subdev_disable(struct nvkm_device *, enum nvkm_subdev_type, int inst);
drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h
5
int g84_bsp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
10
int gm200_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
11
int gp100_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
12
int gp102_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
13
int gv100_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
14
int tu102_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
15
int ga100_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
16
int ga102_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
6
int gt215_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
7
int gf100_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
8
int gk104_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
9
int gm107_ce_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h
5
int g84_cipher_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
61
struct nvkm_gpuobj *inst;
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
72
int nv04_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **);
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
73
int nv50_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **);
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
74
int g84_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **);
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
75
int gt200_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **);
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
76
int g94_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **);
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
77
int mcp77_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **);
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
78
int gt215_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **);
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
79
int mcp89_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **);
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
80
int gf119_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **);
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
81
int gk104_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **);
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
82
int gk110_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **);
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
83
int gm107_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **);
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
84
int gm200_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **);
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
85
int gp100_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **);
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
86
int gp102_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **);
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
87
int gv100_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **);
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
88
int tu102_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **);
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
89
int ga102_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **);
drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h
26
int nv04_dma_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_dma **);
drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h
27
int nv50_dma_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_dma **);
drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h
28
int gf100_dma_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_dma **);
drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h
29
int gf119_dma_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_dma **);
drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h
30
int gv100_dma_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_dma **);
drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h
58
enum nvkm_subdev_type, int inst, bool enable, u32 addr, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
100
int nv50_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
101
int g84_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
102
int g98_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
103
int gf100_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
104
int gk104_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
105
int gk110_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
106
int gk208_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
107
int gk20a_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
108
int gm107_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
109
int gm200_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
110
int gp100_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
111
int gv100_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
112
int tu102_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
113
int ga100_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
114
int ga102_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
18
struct nvkm_gpuobj *inst;
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
53
struct nvkm_chan *nvkm_chan_get_inst(struct nvkm_engine *, u64 inst, unsigned long *irqflags);
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
96
int nv04_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
97
int nv10_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
98
int nv17_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
99
int nv40_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
36
int nv04_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
37
int nv10_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
38
int nv15_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
39
int nv17_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
40
int nv20_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
41
int nv25_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
42
int nv2a_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
43
int nv30_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
44
int nv34_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
45
int nv35_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
46
int nv40_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
47
int nv44_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
48
int nv50_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
49
int g84_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
50
int gt200_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
51
int mcp79_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
52
int gt215_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
53
int mcp89_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
54
int gf100_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
55
int gf104_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
56
int gf108_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
57
int gf110_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
58
int gf117_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
59
int gf119_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
60
int gk104_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
61
int gk110_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
62
int gk110b_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
63
int gk208_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
64
int gk20a_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
65
int gm107_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
66
int gm200_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
67
int gm20b_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
68
int gp100_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
69
int gp102_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
70
int gp104_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
71
int gp107_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
72
int gp108_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
73
int gp10b_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
74
int gv100_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
75
int tu102_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
76
int ga102_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h
5
int nv31_mpeg_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h
6
int nv40_mpeg_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h
7
int nv44_mpeg_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h
8
int nv50_mpeg_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h
9
int g84_mpeg_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h
5
int g98_mspdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h
6
int gt215_mspdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h
7
int gf100_mspdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h
8
int gk104_mspdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h
5
int g98_msppp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h
6
int gt215_msppp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h
7
int gf100_msppp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h
5
int g98_msvld_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h
6
int gt215_msvld_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h
7
int mcp89_msvld_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h
8
int gf100_msvld_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h
9
int gk104_msvld_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/nvdec.h
14
int gm107_nvdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvdec **);
drivers/gpu/drm/nouveau/include/nvkm/engine/nvdec.h
15
int tu102_nvdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvdec **);
drivers/gpu/drm/nouveau/include/nvkm/engine/nvdec.h
16
int ga102_nvdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvdec **);
drivers/gpu/drm/nouveau/include/nvkm/engine/nvenc.h
14
int gm107_nvenc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvenc **);
drivers/gpu/drm/nouveau/include/nvkm/engine/nvenc.h
15
int tu102_nvenc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvenc **);
drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h
5
int g98_sec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h
23
int gp102_sec2_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_sec2 **);
drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h
24
int gp108_sec2_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_sec2 **);
drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h
25
int tu102_sec2_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_sec2 **);
drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h
26
int ga102_sec2_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_sec2 **);
drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h
15
int nv04_sw_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_sw **);
drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h
16
int nv10_sw_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_sw **);
drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h
17
int nv50_sw_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_sw **);
drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h
18
int gf100_sw_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_sw **);
drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h
5
int g84_vp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/acr.h
49
struct nvkm_memory *inst;
drivers/gpu/drm/nouveau/include/nvkm/subdev/acr.h
63
int gm200_acr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_acr **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/acr.h
64
int gm20b_acr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_acr **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/acr.h
65
int gp102_acr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_acr **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/acr.h
66
int gp108_acr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_acr **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/acr.h
67
int gp10b_acr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_acr **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/acr.h
68
int gv100_acr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_acr **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/acr.h
69
int tu102_acr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_acr **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/acr.h
70
int ga102_acr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_acr **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h
30
int nv50_bar_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_bar **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h
31
int g84_bar_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_bar **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h
32
int gf100_bar_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_bar **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h
33
int gk20a_bar_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_bar **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h
34
int gm107_bar_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_bar **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h
35
int gm20b_bar_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_bar **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h
36
int tu102_bar_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_bar **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h
21
int nv04_bus_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_bus **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h
22
int nv31_bus_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_bus **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h
23
int nv50_bus_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_bus **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h
24
int g94_bus_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_bus **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h
25
int gf100_bus_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_bus **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
127
int nv04_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
128
int nv40_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
129
int nv50_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
130
int g84_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
131
int mcp77_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
132
int gt215_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
133
int gf100_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
134
int gk104_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
135
int gk20a_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
136
int gm20b_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
137
int gp10b_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h
26
u64 inst;
drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h
37
int gp100_fault_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fault **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h
38
int gp10b_fault_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fault **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h
39
int gv100_fault_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fault **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h
40
int tu102_fault_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fault **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
100
int gp10b_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
101
int gv100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
102
int tu102_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
103
int ga100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
104
int ga102_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
105
int gh100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
106
int gb100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
107
int gb202_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
70
int nv04_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
71
int nv10_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
72
int nv1a_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
73
int nv20_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
74
int nv25_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
75
int nv30_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
76
int nv35_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
77
int nv36_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
78
int nv40_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
79
int nv41_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
80
int nv44_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
81
int nv46_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
82
int nv47_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
83
int nv49_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
84
int nv4e_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
85
int nv50_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
86
int g84_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
87
int gt215_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
88
int mcp77_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
89
int mcp89_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
90
int gf100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
91
int gf108_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
92
int gk104_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
93
int gk110_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
94
int gk20a_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
95
int gm107_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
96
int gm200_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
97
int gm20b_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
98
int gp100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
99
int gp102_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fsp.h
21
int gh100_fsp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fsp **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fsp.h
22
int gb100_fsp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fsp **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fsp.h
23
int gb202_fsp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fsp **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fuse.h
14
int nv50_fuse_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fuse **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fuse.h
15
int gf100_fuse_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fuse **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/fuse.h
16
int gm107_fuse_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fuse **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h
35
int nv10_gpio_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gpio **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h
36
int nv50_gpio_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gpio **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h
37
int g94_gpio_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gpio **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h
38
int gf119_gpio_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gpio **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h
39
int gk104_gpio_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gpio **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h
40
int ga102_gpio_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gpio **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h
220
int inst;
drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h
79
int nv04_i2c_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_i2c **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h
80
int nv4e_i2c_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_i2c **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h
81
int nv50_i2c_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_i2c **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h
82
int g94_i2c_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_i2c **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h
83
int gf117_i2c_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_i2c **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h
84
int gf119_i2c_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_i2c **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h
85
int gk104_i2c_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_i2c **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h
86
int gk110_i2c_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_i2c **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h
87
int gm200_i2c_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_i2c **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
40
int gf100_ltc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_ltc **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
41
int gk104_ltc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_ltc **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
42
int gm107_ltc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_ltc **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
43
int gm200_ltc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_ltc **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
44
int gp100_ltc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_ltc **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
45
int gp102_ltc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_ltc **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
46
int gp10b_ltc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_ltc **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
47
int ga102_ltc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_ltc **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
20
int nv04_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
21
int nv11_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
22
int nv17_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
23
int nv44_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
24
int nv50_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
25
int g84_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
26
int g98_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
27
int gt215_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
28
int gf100_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
29
int gk104_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
30
int gk20a_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
31
int gp100_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
32
int gp10b_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
33
int ga100_mc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mc **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
154
int nv04_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
155
int nv41_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
156
int nv44_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
157
int nv50_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
158
int g84_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
159
int mcp77_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
160
int gf100_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
161
int gk104_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
162
int gk20a_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
163
int gm200_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
164
int gm20b_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
165
int gp100_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
166
int gp10b_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
167
int gv100_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
168
int tu102_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
169
int gh100_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
85
int nvkm_vmm_join(struct nvkm_vmm *, struct nvkm_memory *inst);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
86
void nvkm_vmm_part(struct nvkm_vmm *, struct nvkm_memory *inst);
drivers/gpu/drm/nouveau/include/nvkm/subdev/mxm.h
6
int nv50_mxm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_subdev **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h
42
int nv04_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h
43
int nv40_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h
44
int nv46_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h
45
int nv4c_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h
46
int g84_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h
47
int g92_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h
48
int g94_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h
49
int gf100_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h
50
int gf106_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h
51
int gk104_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h
52
int gp100_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h
53
int gh100_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h
43
int gt215_pmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h
44
int gf100_pmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h
45
int gf119_pmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h
46
int gk104_pmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h
47
int gk110_pmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h
48
int gk208_pmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h
49
int gk20a_pmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h
50
int gm107_pmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h
51
int gm200_pmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h
52
int gm20b_pmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h
53
int gp102_pmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h
54
int gp10b_pmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pmu **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/privring.h
10
int gm200_privring_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_subdev **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/privring.h
11
int gp10b_privring_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_subdev **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/privring.h
6
int gf100_privring_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_subdev **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/privring.h
7
int gf117_privring_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_subdev **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/privring.h
8
int gk104_privring_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_subdev **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/privring.h
9
int gk20a_privring_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_subdev **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h
110
int nv40_therm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_therm **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h
111
int nv50_therm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_therm **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h
112
int g84_therm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_therm **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h
113
int gt215_therm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_therm **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h
114
int gf119_therm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_therm **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h
115
int gk104_therm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_therm **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h
116
int gm107_therm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_therm **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h
117
int gm200_therm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_therm **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h
118
int gp100_therm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_therm **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h
79
int nv04_timer_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_timer **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h
80
int nv40_timer_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_timer **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h
81
int nv41_timer_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_timer **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h
82
int gk20a_timer_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_timer **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h
14
int inst;
drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h
31
int gk104_top_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_top **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h
32
int ga100_top_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_top **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h
39
int nv40_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_volt **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h
40
int gf100_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_volt **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h
41
int gf117_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_volt **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h
42
int gk104_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_volt **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h
43
int gk20a_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_volt **);
drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h
44
int gm20b_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_volt **);
drivers/gpu/drm/nouveau/nouveau_chan.c
348
chan->inst = args->inst;
drivers/gpu/drm/nouveau/nouveau_chan.c
512
ret = nouveau_svmm_join((*pchan)->vmm->svmm, (*pchan)->inst);
drivers/gpu/drm/nouveau/nouveau_chan.c
97
nouveau_svmm_part(chan->vmm->svmm, chan->inst);
drivers/gpu/drm/nouveau/nouveau_chan.h
20
u64 inst;
drivers/gpu/drm/nouveau/nouveau_svm.c
1071
INIT_LIST_HEAD(&drm->svm->inst);
drivers/gpu/drm/nouveau/nouveau_svm.c
206
nouveau_svmm_part(struct nouveau_svmm *svmm, u64 inst)
drivers/gpu/drm/nouveau/nouveau_svm.c
211
ivmm = nouveau_ivmm_find(svmm->vmm->cli->drm->svm, inst);
drivers/gpu/drm/nouveau/nouveau_svm.c
222
nouveau_svmm_join(struct nouveau_svmm *svmm, u64 inst)
drivers/gpu/drm/nouveau/nouveau_svm.c
229
ivmm->inst = inst;
drivers/gpu/drm/nouveau/nouveau_svm.c
232
list_add(&ivmm->head, &svmm->vmm->cli->drm->svm->inst);
drivers/gpu/drm/nouveau/nouveau_svm.c
397
u64 inst, u8 hub, u8 gpc, u8 client)
drivers/gpu/drm/nouveau/nouveau_svm.c
399
SVM_DBG(svm, "cancel %016llx %d %02x %02x", inst, hub, gpc, client);
drivers/gpu/drm/nouveau/nouveau_svm.c
406
.inst = inst,
drivers/gpu/drm/nouveau/nouveau_svm.c
414
nouveau_svm_fault_cancel(svm, fault->inst,
drivers/gpu/drm/nouveau/nouveau_svm.c
44
struct list_head inst;
drivers/gpu/drm/nouveau/nouveau_svm.c
444
if ((ret = (s64)fa->inst - fb->inst))
drivers/gpu/drm/nouveau/nouveau_svm.c
465
const u64 inst = (u64)insthi << 32 | instlo;
drivers/gpu/drm/nouveau/nouveau_svm.c
480
nouveau_svm_fault_cancel(svm, inst, hub, gpc, client);
drivers/gpu/drm/nouveau/nouveau_svm.c
487
fault->inst = inst;
drivers/gpu/drm/nouveau/nouveau_svm.c
498
fault->inst, fault->addr, fault->access);
drivers/gpu/drm/nouveau/nouveau_svm.c
58
u64 inst;
drivers/gpu/drm/nouveau/nouveau_svm.c
725
u64 inst, start, limit;
drivers/gpu/drm/nouveau/nouveau_svm.c
760
if (!svmm || buffer->fault[fi]->inst != inst) {
drivers/gpu/drm/nouveau/nouveau_svm.c
762
nouveau_ivmm_find(svm, buffer->fault[fi]->inst);
drivers/gpu/drm/nouveau/nouveau_svm.c
764
inst = buffer->fault[fi]->inst;
drivers/gpu/drm/nouveau/nouveau_svm.c
765
SVM_DBG(svm, "inst %016llx -> svm-%p", inst, svmm);
drivers/gpu/drm/nouveau/nouveau_svm.c
89
u64 inst;
drivers/gpu/drm/nouveau/nouveau_svm.c
94
nouveau_ivmm_find(struct nouveau_svm *svm, u64 inst)
drivers/gpu/drm/nouveau/nouveau_svm.c
97
list_for_each_entry(ivmm, &svm->inst, head) {
drivers/gpu/drm/nouveau/nouveau_svm.c
98
if (ivmm->inst == inst)
drivers/gpu/drm/nouveau/nouveau_svm.h
28
int nouveau_svmm_join(struct nouveau_svmm *, u64 inst);
drivers/gpu/drm/nouveau/nouveau_svm.h
29
void nouveau_svmm_part(struct nouveau_svmm *, u64 inst);
drivers/gpu/drm/nouveau/nouveau_svm.h
52
static inline int nouveau_svmm_join(struct nouveau_svmm *svmm, u64 inst)
drivers/gpu/drm/nouveau/nouveau_svm.h
57
static inline void nouveau_svmm_part(struct nouveau_svmm *svmm, u64 inst) {}
drivers/gpu/drm/nouveau/nvkm/core/engine.c
166
enum nvkm_subdev_type type, int inst, bool enable, struct nvkm_engine *engine)
drivers/gpu/drm/nouveau/nvkm/core/engine.c
169
nvkm_subdev_ctor(&nvkm_engine, device, type, inst, &engine->subdev);
drivers/gpu/drm/nouveau/nvkm/core/engine.c
183
enum nvkm_subdev_type type, int inst, bool enable,
drivers/gpu/drm/nouveau/nvkm/core/engine.c
188
return nvkm_engine_ctor(func, device, type, inst, enable, *pengine);
drivers/gpu/drm/nouveau/nvkm/core/intr.c
270
nvkm_intr_subdev_add_dev(struct nvkm_intr *intr, enum nvkm_subdev_type type, int inst)
drivers/gpu/drm/nouveau/nvkm/core/intr.c
276
subdev = nvkm_device_subdev(intr->subdev->device, type, inst);
drivers/gpu/drm/nouveau/nvkm/core/intr.c
306
nvkm_intr_subdev_add_dev(intr, tdev->type, tdev->inst);
drivers/gpu/drm/nouveau/nvkm/core/intr.c
309
nvkm_intr_subdev_add_dev(intr, data->type, data->inst);
drivers/gpu/drm/nouveau/nvkm/core/intr.c
44
tdev->inst == subdev->inst) {
drivers/gpu/drm/nouveau/nvkm/core/intr.c
53
if (data->type == subdev->type && data->inst == subdev->inst) {
drivers/gpu/drm/nouveau/nvkm/core/ramht.c
49
return ramht->data[co].inst;
drivers/gpu/drm/nouveau/nvkm/core/ramht.c
64
u64 inst = 0x00000040; /* just non-zero for <=g8x fifo ramht */
drivers/gpu/drm/nouveau/nvkm/core/ramht.c
67
nvkm_gpuobj_del(&data->inst);
drivers/gpu/drm/nouveau/nvkm/core/ramht.c
72
ret = nvkm_object_bind(object, ramht->parent, 16, &data->inst);
drivers/gpu/drm/nouveau/nvkm/core/ramht.c
78
data->inst = NULL;
drivers/gpu/drm/nouveau/nvkm/core/ramht.c
81
if (data->inst) {
drivers/gpu/drm/nouveau/nvkm/core/ramht.c
83
inst = data->inst->node->offset;
drivers/gpu/drm/nouveau/nvkm/core/ramht.c
85
inst = data->inst->addr;
drivers/gpu/drm/nouveau/nvkm/core/ramht.c
88
if (addr < 0) context |= inst << -addr;
drivers/gpu/drm/nouveau/nvkm/core/ramht.c
89
else context |= inst >> addr;
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
248
nvkm_subdev_disable(struct nvkm_device *device, enum nvkm_subdev_type type, int inst)
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
252
if (subdev->type == type && subdev->inst == inst) {
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
262
enum nvkm_subdev_type type, int inst, struct nvkm_subdev *subdev)
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
267
subdev->inst = inst < 0 ? 0 : inst;
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
269
if (inst >= 0)
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
270
snprintf(subdev->name, sizeof(subdev->name), "%s%d", nvkm_subdev_type[type], inst);
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
281
enum nvkm_subdev_type type, int inst, struct nvkm_subdev **psubdev)
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
285
nvkm_subdev_ctor(func, device, type, inst, *psubdev);
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
85
nvkm_mc_reset(device, subdev->type, subdev->inst);
drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c
39
g84_bsp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c
42
return nvkm_xtensa_new_(&g84_bsp, device, type, inst,
drivers/gpu/drm/nouveau/nvkm/engine/ce/ga100.c
45
return nvkm_rd32(device, 0x104424 + (subdev->inst * 0x80)) & 0x00000fff;
drivers/gpu/drm/nouveau/nvkm/engine/ce/ga100.c
69
vector = nvkm_rd32(device, 0x10442c + (subdev->inst * 0x80)) & 0x00000fff;
drivers/gpu/drm/nouveau/nvkm/engine/ce/ga100.c
89
ga100_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/ce/ga100.c
95
return nvkm_engine_new_(&ga100_ce, device, type, inst, true, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/ce/ga102.c
43
ga102_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/ce/ga102.c
49
return nvkm_engine_new_(&ga102_ce, device, type, inst, true, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c
32
nvkm_wr32(ce->engine.subdev.device, ce->addr + 0x084, ce->engine.subdev.inst);
drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c
64
gf100_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c
67
return nvkm_falcon_new_(inst ? &gf100_ce1 : &gf100_ce0, device, type, inst, true,
drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c
68
0x104000 + (inst * 0x1000), pengine);
drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c
100
return nvkm_engine_new_(&gk104_ce, device, type, inst, true, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c
63
const u32 base = subdev->inst * 0x1000;
drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c
97
gk104_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/ce/gm107.c
39
gm107_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/ce/gm107.c
42
return nvkm_engine_new_(&gm107_ce, device, type, inst, true, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/ce/gm200.c
38
gm200_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/ce/gm200.c
41
return nvkm_engine_new_(&gm200_ce, device, type, inst, true, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c
101
return nvkm_engine_new_(&gp100_ce, device, type, inst, true, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c
64
const u32 base = subdev->inst * 0x80;
drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c
98
gp100_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/ce/gp102.c
40
gp102_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/ce/gp102.c
43
return nvkm_engine_new_(&gp102_ce, device, type, inst, true, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c
47
const u32 base = subdev->inst * 0x1000;
drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c
59
chan ? chan->inst->addr : 0,
drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c
78
gt215_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/ce/gv100.c
60
gv100_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/ce/gv100.c
63
return nvkm_engine_new_(&gv100_ce, device, type, inst, true, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/ce/tu102.c
39
tu102_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/ce/tu102.c
45
return nvkm_engine_new_(&tu102_ce, device, type, inst, true, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c
129
g84_cipher_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c
132
return nvkm_engine_new_(&g84_cipher, device, type, inst, true, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c
88
u32 inst = nvkm_rd32(device, 0x102188) & 0x7fffffff;
drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c
92
chan = nvkm_chan_get_inst(cipher, (u64)inst << 12, &flags);
drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c
97
chan ? chan->id : -1, (u64)inst << 12,
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
2918
nvkm_device_subdev(struct nvkm_device *device, int type, int inst)
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
2923
if (subdev->type == type && subdev->inst == inst)
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
2931
nvkm_device_engine(struct nvkm_device *device, int type, int inst)
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
2933
struct nvkm_subdev *subdev = nvkm_device_subdev(device, type, inst);
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
3408
if (device->chip->ptr.inst) { \
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
3409
WARN_ON(device->chip->ptr.inst != 0x00000001); \
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
3425
WARN_ON(device->chip->ptr.inst & ~((1 << ARRAY_SIZE(device->ptr)) - 1)); \
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
3426
for (j = 0; device->chip->ptr.inst && j < ARRAY_SIZE(device->ptr); j++) { \
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
3427
if (device->chip->ptr.inst & BIT(j)) { \
drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c
179
nvkm_gpuobj_del(&disp->inst);
drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c
230
enum nvkm_subdev_type type, int inst, struct nvkm_disp **pdisp)
drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c
245
ret = nvkm_engine_ctor(&nvkm_disp, device, type, inst, true, &disp->engine);
drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c
345
g84_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c
348
return nvkm_disp_new_(&g84_disp, device, type, inst, pdisp);
drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c
375
g94_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c
378
return nvkm_disp_new_(&g94_disp, device, type, inst, pdisp);
drivers/gpu/drm/nouveau/nvkm/engine/disp/ga102.c
148
ga102_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/disp/ga102.c
152
return r535_disp_new(&ga102_disp, device, type, inst, pdisp);
drivers/gpu/drm/nouveau/nvkm/engine/disp/ga102.c
154
return nvkm_disp_new_(&ga102_disp, device, type, inst, pdisp);
drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c
1212
nvkm_wr32(device, 0x610010, (disp->inst->addr >> 8) | 9);
drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c
1257
gf119_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c
1260
return nvkm_disp_new_(&gf119_disp, device, type, inst, pdisp);
drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c
329
gk104_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c
332
return nvkm_disp_new_(&gk104_disp, device, type, inst, pdisp);
drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c
55
gk110_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c
58
return nvkm_disp_new_(&gk110_disp, device, type, inst, pdisp);
drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c
109
gm107_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c
112
return nvkm_disp_new_(&gm107_disp, device, type, inst, pdisp);
drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c
192
gm200_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c
195
return nvkm_disp_new_(&gm200_disp, device, type, inst, pdisp);
drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.c
81
gp100_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.c
84
return nvkm_disp_new_(&gp100_disp, device, type, inst, pdisp);
drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c
196
gp102_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c
199
return nvkm_disp_new_(&gp102_disp, device, type, inst, pdisp);
drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c
105
gt200_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c
108
return nvkm_disp_new_(>200_disp, device, type, inst, pdisp);
drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c
263
gt215_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c
266
return nvkm_disp_new_(>215_disp, device, type, inst, pdisp);
drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c
1186
switch (nvkm_memory_target(disp->inst->memory)) {
drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c
1194
nvkm_wr32(device, 0x610014, disp->inst->addr >> 16);
drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c
1250
gv100_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c
1253
return nvkm_disp_new_(&gv100_disp, device, type, inst, pdisp);
drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c
69
mcp77_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c
72
return nvkm_disp_new_(&mcp77_disp, device, type, inst, pdisp);
drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.c
83
mcp89_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.c
86
return nvkm_disp_new_(&mcp89_disp, device, type, inst, pdisp);
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c
114
nv04_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c
119
ret = nvkm_disp_new_(&nv04_disp, device, type, inst, pdisp);
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
1572
nvkm_wr32(device, 0x610010, (disp->inst->addr >> 8) | 9);
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
1637
ret = nvkm_gpuobj_new(device, 0x10000, 0x10000, false, NULL, &disp->inst);
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
1641
ret = nvkm_ramht_new(device, func->ramht_size ? func->ramht_size : 0x1000, 0, disp->inst,
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
1791
nv50_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
1794
return nvkm_disp_new_(&nv50_disp, device, type, inst, pdisp);
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
452
const struct nvkm_disp_mthd_list *list, int inst)
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
462
u32 mthd = list->data[i].mthd + (list->mthd * inst);
drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c
170
switch (nvkm_memory_target(disp->inst->memory)) {
drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c
178
nvkm_wr32(device, 0x610014, disp->inst->addr >> 16);
drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c
234
tu102_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c
238
return r535_disp_new(&tu102_disp, device, type, inst, pdisp);
drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c
240
return nvkm_disp_new_(&tu102_disp, device, type, inst, pdisp);
drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c
107
enum nvkm_subdev_type type, int inst, struct nvkm_dma **pdma)
drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c
115
return nvkm_engine_ctor(&nvkm_dma, device, type, inst, true, &dma->engine);
drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.c
33
gf100_dma_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.c
36
return nvkm_dma_new_(&gf100_dma, device, type, inst, pdma);
drivers/gpu/drm/nouveau/nvkm/engine/dma/gf119.c
33
gf119_dma_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/dma/gf119.c
36
return nvkm_dma_new_(&gf119_dma, device, type, inst, pdma);
drivers/gpu/drm/nouveau/nvkm/engine/dma/gv100.c
31
gv100_dma_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/dma/gv100.c
34
return nvkm_dma_new_(&gv100_dma, device, type, inst, pdma);
drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.c
33
nv04_dma_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.c
36
return nvkm_dma_new_(&nv04_dma, device, type, inst, pdma);
drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.c
33
nv50_dma_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.c
36
return nvkm_dma_new_(&nv50_dma, device, type, inst, pdma);
drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
111
if (nvkm_mc_enabled(device, engine->subdev.type, engine->subdev.inst)) {
drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
339
enum nvkm_subdev_type type, int inst, bool enable, u32 addr,
drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
354
return nvkm_engine_ctor(&nvkm_falcon, device, type, inst, enable, &falcon->engine);
drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
67
u32 inst = nvkm_rd32(device, base + 0x050) & 0x3fffffff;
drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
71
chan = nvkm_chan_get_inst(engine, (u64)inst << 12, &flags);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c
376
enum nvkm_subdev_type type, int inst, struct nvkm_fifo **pfifo)
drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c
394
return nvkm_engine_ctor(&nvkm_fifo, device, type, inst, true, &fifo->engine);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/cgrp.c
103
nvkm_gpuobj_del(&vctx->inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/cgrp.c
163
ret = nvkm_object_bind(vctx->ectx->object, NULL, 0, &vctx->inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/cgrp.h
13
struct nvkm_gpuobj *inst;
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
285
nvkm_vmm_part(chan->vmm, chan->inst->memory);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
290
nvkm_gpuobj_del(&chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
307
nvkm_chan_get_inst(struct nvkm_engine *engine, u64 inst, unsigned long *pirqflags)
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
317
chan = nvkm_runl_chan_get_inst(runl, inst, pirqflags);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
357
(!func->inst->vmm != !vmm) ||
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
364
runl->func->runqs, runq, func->inst->vmm, vmm,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
409
ret = nvkm_gpuobj_new(device, func->inst->size, 0x1000, func->inst->zero, NULL,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
410
&chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
417
if (func->inst->vmm) {
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
421
ret = nvkm_vmm_join(vmm, chan->inst->memory);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
432
ret = nvkm_object_bind(&dmaobj->object, chan->inst, -16, &chan->push);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h
24
} *inst;
drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
131
nvkm_wr32(device, 0x0032fc, chan->inst->addr >> 12);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
139
start = cctx->vctx->inst->addr;
drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
140
limit = start + cctx->vctx->inst->size - 1;
drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
227
g84_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
230
return nvkm_fifo_new_(&g84_fifo, device, type, inst, pfifo);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
49
ret = nvkm_gpuobj_new(device, 0x0200, 0, true, chan->inst, &chan->eng);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
53
ret = nvkm_gpuobj_new(device, 0x4000, 0, false, chan->inst, &chan->pgd);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
57
ret = nvkm_gpuobj_new(device, 0x1000, 0x400, true, chan->inst, &chan->cache);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
61
ret = nvkm_gpuobj_new(device, 0x100, 0x100, true, chan->inst, &chan->ramfc);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
65
ret = nvkm_ramht_new(device, 0x8000, 16, chan->inst, &chan->ramht);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
82
nvkm_wo32(chan->ramfc, 0x98, chan->inst->addr >> 12);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
96
.inst = &nv50_chan_inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/g98.c
66
g98_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/g98.c
69
return nvkm_fifo_new_(&g98_fifo, device, type, inst, pfifo);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c
481
tdev->type, tdev->inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c
619
ga100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c
623
return r535_fifo_new(&ga100_fifo, device, type, inst, pfifo);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c
625
return nvkm_fifo_new_(&ga100_fifo, device, type, inst, pfifo);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c
74
nvkm_kmap(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c
75
nvkm_wo32(chan->inst, 0x010, 0x0000face);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c
76
nvkm_wo32(chan->inst, 0x030, 0x7ffff902);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c
77
nvkm_wo32(chan->inst, 0x048, lower_32_bits(offset));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c
78
nvkm_wo32(chan->inst, 0x04c, upper_32_bits(offset) | (limit2 << 16));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c
79
nvkm_wo32(chan->inst, 0x084, 0x20400000);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c
80
nvkm_wo32(chan->inst, 0x094, 0x30000000 | devm);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c
81
nvkm_wo32(chan->inst, 0x0e4, priv ? 0x00000020 : 0x00000000);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c
82
nvkm_wo32(chan->inst, 0x0e8, chan->id);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c
83
nvkm_wo32(chan->inst, 0x0f4, 0x00001000 | (priv ? 0x00000100 : 0x00000000));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c
84
nvkm_wo32(chan->inst, 0x0f8, 0x80000000 | chan->cgrp->runl->nonstall.vector);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c
85
nvkm_mo32(chan->inst, 0x218, 0x00000000, 0x00000000);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c
86
nvkm_done(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c
99
.inst = &gf100_chan_inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga102.c
44
ga102_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga102.c
48
return r535_fifo_new(&ga102_fifo, device, type, inst, pfifo);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga102.c
50
return nvkm_fifo_new_(&ga102_fifo, device, type, inst, pfifo);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
100
nvkm_wo32(chan->inst, 0x9c, 0x00000100);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
101
nvkm_wo32(chan->inst, 0xa4, 0x1f1f1f1f);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
102
nvkm_wo32(chan->inst, 0xa8, 0x1f1f1f1f);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
103
nvkm_wo32(chan->inst, 0xac, 0x0000001f);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
104
nvkm_wo32(chan->inst, 0xb8, 0xf8000000);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
105
nvkm_wo32(chan->inst, 0xf8, 0x10003080); /* 0x002310 */
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
106
nvkm_wo32(chan->inst, 0xfc, 0x10000010); /* 0x002350 */
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
107
nvkm_done(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
150
.inst = &gf100_chan_inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
169
case NVKM_ENGINE_CE : ptr0 = 0x0230 + (engn->engine->subdev.inst * 0x10); break;
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
183
nvkm_kmap(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
184
nvkm_wo32(chan->inst, ptr0 + 0, lower_32_bits(addr));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
185
nvkm_wo32(chan->inst, ptr0 + 4, upper_32_bits(addr));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
186
nvkm_done(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
194
ret = nvkm_vmm_get(vctx->vmm, 12, vctx->inst->size, &vctx->vma);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
198
return nvkm_memory_map(vctx->inst, 0, vctx->vmm, vctx->vma, NULL, 0);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
338
runq->id, show, msg, chid, chan ? chan->inst->addr : 0,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
589
chan = nvkm_chan_get_inst(&fifo->engine, info->inst, &flags);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
598
chan ? chan->id : -1, info->inst, chan ? chan->name : "unknown");
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
699
u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
705
info.inst = (u64)inst << 12;
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
81
nvkm_wr32(device, 0x003000 + (chan->id * 8), 0xc0000000 | chan->inst->addr >> 12);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
90
nvkm_kmap(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
91
nvkm_wo32(chan->inst, 0x08, lower_32_bits(userd));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
92
nvkm_wo32(chan->inst, 0x0c, upper_32_bits(userd));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
93
nvkm_wo32(chan->inst, 0x10, 0x0000face);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
94
nvkm_wo32(chan->inst, 0x30, 0xfffff902);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
95
nvkm_wo32(chan->inst, 0x48, lower_32_bits(offset));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
96
nvkm_wo32(chan->inst, 0x4c, upper_32_bits(offset) | (limit2 << 16));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
965
gf100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
968
return nvkm_fifo_new_(&gf100_fifo, device, type, inst, pfifo);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
97
nvkm_wo32(chan->inst, 0x54, 0x00000002);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
98
nvkm_wo32(chan->inst, 0x84, 0x20400000);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
99
nvkm_wo32(chan->inst, 0x94, 0x30000000 | devm);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
100
nvkm_wo32(chan->inst, 0xb8, 0xf8000000);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
101
nvkm_wo32(chan->inst, 0xf8, 0x10003080); /* 0x002310 */
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
102
nvkm_wo32(chan->inst, 0xfc, 0x10000010); /* 0x002350 */
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
103
nvkm_done(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
123
.inst = &gf100_chan_inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
153
if (!engn->engine->subdev.inst)
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
167
nvkm_kmap(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
168
nvkm_wo32(chan->inst, ptr0 + 0, lower_32_bits(addr));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
169
nvkm_wo32(chan->inst, ptr0 + 4, upper_32_bits(addr));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
171
nvkm_wo32(chan->inst, ptr1 + 0, lower_32_bits(addr));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
172
nvkm_wo32(chan->inst, ptr1 + 4, upper_32_bits(addr));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
174
nvkm_done(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
183
ret = nvkm_vmm_get(vctx->vmm, 12, vctx->inst->size, &vctx->vma);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
187
return nvkm_memory_map(vctx->inst, 0, vctx->vmm, vctx->vma, &args, sizeof(args));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
68
nvkm_wr32(device, 0x800000 + (chan->id * 8), 0x80000000 | chan->inst->addr >> 12);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
795
nvkm_runl_add(runl, tdev->engine, func, tdev->type, tdev->inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
829
gk104_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
832
return nvkm_fifo_new_(&gk104_fifo, device, type, inst, pfifo);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
87
nvkm_kmap(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
88
nvkm_wo32(chan->inst, 0x08, lower_32_bits(userd));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
89
nvkm_wo32(chan->inst, 0x0c, upper_32_bits(userd));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
90
nvkm_wo32(chan->inst, 0x10, 0x0000face);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
91
nvkm_wo32(chan->inst, 0x30, 0xfffff902);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
92
nvkm_wo32(chan->inst, 0x48, lower_32_bits(offset));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
93
nvkm_wo32(chan->inst, 0x4c, upper_32_bits(offset) | (limit2 << 16));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
94
nvkm_wo32(chan->inst, 0x84, 0x20400000);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
95
nvkm_wo32(chan->inst, 0x94, 0x30000000 | devm);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
96
nvkm_wo32(chan->inst, 0x9c, 0x00000100);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
97
nvkm_wo32(chan->inst, 0xac, 0x0000001f);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
98
nvkm_wo32(chan->inst, 0xe4, priv ? 0x00000020 : 0x00000000);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
99
nvkm_wo32(chan->inst, 0xe8, chan->id);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c
128
gk110_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c
131
return nvkm_fifo_new_(&gk110_fifo, device, type, inst, pfifo);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c
50
.inst = &gf100_chan_inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c
73
gk208_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c
76
return nvkm_fifo_new_(&gk208_fifo, device, type, inst, pfifo);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c
48
gk20a_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c
51
return nvkm_fifo_new_(&gk20a_fifo, device, type, inst, pfifo);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c
104
u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c
110
info.inst = (u64)inst << 12;
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c
152
gm107_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c
155
return nvkm_fifo_new_(&gm107_fifo, device, type, inst, pfifo);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c
35
.inst = &gf100_chan_inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c
49
nvkm_wo32(memory, offset + 4, chan->inst->addr >> 12);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c
62
gm200_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c
65
return nvkm_fifo_new_(&gm200_fifo, device, type, inst, pfifo);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c
135
gp100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c
138
return nvkm_fifo_new_(&gp100_fifo, device, type, inst, pfifo);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c
36
nvkm_wo32(memory, offset + 4, chan->inst->addr >> 12);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c
93
u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c
99
info.inst = (u64)inst << 12;
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
100
nvkm_kmap(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
101
nvkm_wo32(chan->inst, 0x210, lower_32_bits(addr));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
102
nvkm_wo32(chan->inst, 0x214, upper_32_bits(addr));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
103
nvkm_mo32(chan->inst, 0x0ac, 0x00010000, cctx ? 0x00010000 : 0x00000000);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
104
nvkm_done(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
118
const u64 bar2 = cctx ? nvkm_memory_bar2(cctx->vctx->inst->memory) : 0ULL;
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
120
nvkm_kmap(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
121
nvkm_wo32(chan->inst, 0x220, lower_32_bits(bar2));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
122
nvkm_wo32(chan->inst, 0x224, upper_32_bits(bar2));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
123
nvkm_mo32(chan->inst, 0x0ac, 0x00020000, cctx ? 0x00020000 : 0x00000000);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
124
nvkm_done(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
130
if (nvkm_memory_bar2(vctx->inst->memory) == ~0ULL)
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
185
const u64 inst = chan->inst->addr;
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
189
nvkm_wo32(memory, offset + 0x8, lower_32_bits(inst) | chan->id);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
190
nvkm_wo32(memory, offset + 0xc, upper_32_bits(inst));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
46
nvkm_kmap(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
47
nvkm_wo32(chan->inst, 0x008, lower_32_bits(userd));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
48
nvkm_wo32(chan->inst, 0x00c, upper_32_bits(userd));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
487
gv100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
49
nvkm_wo32(chan->inst, 0x010, 0x0000face);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
490
return nvkm_fifo_new_(&gv100_fifo, device, type, inst, pfifo);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
50
nvkm_wo32(chan->inst, 0x030, 0x7ffff902);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
51
nvkm_wo32(chan->inst, 0x048, lower_32_bits(offset));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
52
nvkm_wo32(chan->inst, 0x04c, upper_32_bits(offset) | (limit2 << 16));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
53
nvkm_wo32(chan->inst, 0x084, 0x20400000);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
54
nvkm_wo32(chan->inst, 0x094, 0x30000000 | devm);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
55
nvkm_wo32(chan->inst, 0x0e4, priv ? 0x00000020 : 0x00000000);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
56
nvkm_wo32(chan->inst, 0x0e8, chan->id);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
57
nvkm_wo32(chan->inst, 0x0f4, 0x00001000 | (priv ? 0x00000100 : 0x00000000));
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
58
nvkm_wo32(chan->inst, 0x0f8, 0x10003080);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
59
nvkm_mo32(chan->inst, 0x218, 0x00000000, 0x00000000);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
60
nvkm_done(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
79
.inst = &gf100_chan_inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
169
.inst = &nv04_chan_inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
539
nv04_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
542
return nvkm_fifo_new_(&nv04_fifo, device, type, inst, pfifo);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c
109
nv10_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c
112
return nvkm_fifo_new_(&nv10_fifo, device, type, inst, pfifo);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c
79
.inst = &nv04_chan_inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c
138
nv17_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c
141
return nvkm_fifo_new_(&nv17_fifo, device, type, inst, pfifo);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c
85
.inst = &nv04_chan_inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
103
.inst = &nv04_chan_inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
130
u32 inst = 0x00000000, reg, ctx;
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
150
inst = cctx->vctx->inst->addr >> 4;
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
157
nvkm_wr32(device, reg, inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
160
nvkm_wo32(ramfc, chan->ramfc_offset + ctx, inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
248
nv40_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
251
return nvkm_fifo_new_(&nv40_fifo, device, type, inst, pfifo);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
140
.inst = &nv50_chan_inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
181
nvkm_wr32(device, 0x0032fc, chan->inst->addr >> 12);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
189
start = cctx->vctx->inst->addr;
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
190
limit = start + cctx->vctx->inst->size - 1;
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
394
nv50_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
397
return nvkm_fifo_new_(&nv50_fifo, device, type, inst, pfifo);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
86
ret = nvkm_gpuobj_new(device, 0x0200, 0x1000, true, chan->inst, &chan->ramfc);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
90
ret = nvkm_gpuobj_new(device, 0x1200, 0, true, chan->inst, &chan->eng);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
94
ret = nvkm_gpuobj_new(device, 0x4000, 0, false, chan->inst, &chan->pgd);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
98
ret = nvkm_ramht_new(device, 0x8000, 16, chan->inst, &chan->ramht);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/runl.c
183
nvkm_runl_chan_get_inst(struct nvkm_runl *runl, u64 inst, unsigned long *pirqflags)
drivers/gpu/drm/nouveau/nvkm/engine/fifo/runl.c
194
if (chan->inst->addr == inst) {
drivers/gpu/drm/nouveau/nvkm/engine/fifo/runl.c
339
enum nvkm_subdev_type type, int inst)
drivers/gpu/drm/nouveau/nvkm/engine/fifo/runl.c
346
engine = nvkm_device_engine(device, type, inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/runl.c
348
RUNL_DEBUG(runl, "engn %d.%d[%s] not found", engi, inst, nvkm_subdev_type[type]);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/runl.c
364
engn->fault = nvkm_top_fault_id(device, engine->subdev.type, engine->subdev.inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/runl.c
370
if (map->data2 == engine->subdev.type && map->inst == engine->subdev.inst) {
drivers/gpu/drm/nouveau/nvkm/engine/fifo/runl.h
104
enum nvkm_subdev_type, int inst);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/runl.h
118
struct nvkm_chan *nvkm_runl_chan_get_inst(struct nvkm_runl *, u64 inst, unsigned long *irqflags);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c
283
tu102_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c
287
return r535_fifo_new(&tu102_fifo, device, type, inst, pfifo);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c
289
return nvkm_fifo_new_(&tu102_fifo, device, type, inst, pfifo);
drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c
51
.inst = &gf100_chan_inst,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c
402
switch (nvkm_memory_target(chan->inst->memory)) {
drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c
413
args->v0.inst = nvkm_memory_addr(chan->inst->memory);
drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c
205
enum nvkm_subdev_type type, int inst, bool enable, struct nvkm_gr *gr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c
208
return nvkm_engine_ctor(&nvkm_gr, device, type, inst, enable, &gr->engine);
drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c
32
if (gr && gr->func->ctxsw.inst)
drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c
33
return gr->func->ctxsw.inst(gr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
1436
gf100_grctx_generate(struct gf100_gr *gr, struct gf100_gr_chan *chan, struct nvkm_gpuobj *inst)
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
1487
nvkm_kmap(inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
1488
nvkm_wo32(inst, 0x0210, lower_32_bits(ctx->addr + CB_RESERVED) | 4);
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
1489
nvkm_wo32(inst, 0x0214, upper_32_bits(ctx->addr + CB_RESERVED));
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
1490
nvkm_done(inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
1493
addr = inst->addr >> 12;
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
1550
nvkm_kmap(inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
1551
nvkm_wo32(inst, 0x0210, 0);
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
1552
nvkm_wo32(inst, 0x0214, 0);
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
1553
nvkm_done(inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h
76
int gf100_grctx_generate(struct gf100_gr *, struct gf100_gr_chan *, struct nvkm_gpuobj *inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h
25
cp_out(struct nvkm_grctx *ctx, u32 inst)
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h
33
ctxprog[ctx->ctxprog_len++] = inst;
drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c
195
g84_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c
197
return nv50_gr_new_(&g84_gr, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/ga102.c
352
ga102_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/ga102.c
357
return gf100_gr_new_(ga102_gr_fwif, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
1614
u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff;
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
1625
chan = nvkm_chan_get_inst(&gr->base.engine, (u64)inst << 12, &flags);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
1649
chid, inst << 12, name, subc,
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
1659
chid, inst << 12, name, subc, class, mthd, data);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
1669
code, en ? en->name : "", chid, inst << 12,
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
1677
chid, inst << 12, name);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
1764
gf100_gr_init_fw(&gr->fecs.falcon, &gr->fecs.inst,
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
1771
gf100_gr_init_fw(&gr->gpccs.falcon, &gr->gpccs.inst,
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
2143
nvkm_blob_dtor(&gr->fecs.inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
2145
nvkm_blob_dtor(&gr->gpccs.inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
2334
nvkm_mc_disable(device, subdev->type, subdev->inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
2338
nvkm_mc_enable(device, subdev->type, subdev->inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
2523
.ctxsw.inst = gf100_gr_ctxsw_inst,
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
2603
if (gf100_gr_load_fw(gr, "fuc409c", &gr->fecs.inst) ||
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
2605
gf100_gr_load_fw(gr, "fuc41ac", &gr->gpccs.inst) ||
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
2622
enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
2631
ret = nvkm_gr_ctor(&gf100_gr_, device, type, inst, true, &gr->base);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
2657
gf100_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
2659
return gf100_gr_new_(gf100_gr_fwif, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
443
ret = gf100_grctx_generate(gr, chan, fifoch->inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
815
gf100_gr_fecs_wfi_golden_save(struct gf100_gr *gr, u32 inst)
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
820
nvkm_wr32(device, 0x409500, inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
834
gf100_gr_fecs_bind_pointer(struct gf100_gr *gr, u32 inst)
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
839
nvkm_wr32(device, 0x409500, inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
870
gf100_gr_fecs_set_reglist_bind_instance(struct gf100_gr *gr, u32 inst)
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
874
nvkm_wr32(device, 0x409810, inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
138
int gf100_gr_fecs_bind_pointer(struct gf100_gr *, u32 inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
139
int gf100_gr_fecs_wfi_golden_save(struct gf100_gr *, u32 inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
71
struct nvkm_blob inst;
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
80
struct nvkm_blob inst;
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c
158
gf104_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c
160
return gf100_gr_new_(gf104_gr_fwif, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c
157
gf108_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c
159
return gf100_gr_new_(gf108_gr_fwif, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c
133
gf110_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c
135
return gf100_gr_new_(gf110_gr_fwif, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c
200
gf117_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c
202
return gf100_gr_new_(gf117_gr_fwif, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c
224
gf119_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c
226
return gf100_gr_new_(gf119_gr_fwif, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
503
gk104_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
505
return gf100_gr_new_(gk104_gr_fwif, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c
399
gk110_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c
401
return gf100_gr_new_(gk110_gr_fwif, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c
150
gk110b_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c
153
return gf100_gr_new_(gk110b_gr_fwif, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c
208
gk208_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c
210
return gf100_gr_new_(gk208_gr_fwif, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c
322
&gr->fecs.inst) ||
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c
326
&gr->gpccs.inst) ||
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c
343
gk20a_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c
345
return gf100_gr_new_(gk20a_gr_fwif, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
443
gm107_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
445
return gf100_gr_new_(gm107_gr_fwif, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c
293
gm200_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c
295
return gf100_gr_new_(gm200_gr_fwif, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c
154
&gr->gpccs.inst) ||
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c
185
gm20b_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c
187
return gf100_gr_new_(gm20b_gr_fwif, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c
162
gp100_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c
164
return gf100_gr_new_(gp100_gr_fwif, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c
158
gp102_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c
160
return gf100_gr_new_(gp102_gr_fwif, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp104.c
101
return gf100_gr_new_(gp104_gr_fwif, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp104.c
99
gp104_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c
88
gp107_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c
90
return gf100_gr_new_(gp107_gr_fwif, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp108.c
95
gp108_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp108.c
97
return gf100_gr_new_(gp108_gr_fwif, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c
100
gp10b_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c
102
return gf100_gr_new_(gp10b_gr_fwif, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.c
46
gt200_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.c
48
return nv50_gr_new_(>200_gr, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.c
47
gt215_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.c
49
return nv50_gr_new_(>215_gr, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c
339
gv100_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c
341
return gf100_gr_new_(gv100_gr_fwif, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.c
45
mcp79_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.c
47
return nv50_gr_new_(&mcp79_gr, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.c
47
mcp89_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.c
49
return nv50_gr_new_(&mcp89_gr, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
1011
return func(device, inst, data);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
1015
nv04_gr_mthd(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
1018
switch (nvkm_rd32(device, 0x700000 + inst) & 0x000000ff) {
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
1039
return func(device, inst, mthd, data);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
1286
u32 inst = (nvkm_rd32(device, 0x40016c) & 0xffff) << 4;
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
1297
if (!nv04_gr_mthd(device, inst, mthd, data))
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
1416
nv04_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
1425
return nvkm_gr_ctor(&nv04_gr, device, type, inst, true, &gr->base);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
445
nv04_gr_set_ctx1(struct nvkm_device *device, u32 inst, u32 mask, u32 value)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
450
tmp = nvkm_rd32(device, 0x700000 + inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
453
nvkm_wr32(device, 0x700000 + inst, tmp);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
460
nv04_gr_set_ctx_val(struct nvkm_device *device, u32 inst, u32 mask, u32 value)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
465
ctx1 = nvkm_rd32(device, 0x700000 + inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
469
tmp = nvkm_rd32(device, 0x70000c + inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
472
nvkm_wr32(device, 0x70000c + inst, tmp);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
504
nv04_gr_set_ctx1(device, inst, 0x01000000, valid << 24);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
508
nv04_gr_mthd_set_operation(struct nvkm_device *device, u32 inst, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
516
nv04_gr_set_ctx1(device, inst, 0x00038000, data << 15);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
518
nv04_gr_set_ctx_val(device, inst, 0, 0);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
523
nv04_gr_mthd_surf3d_clip_h(struct nvkm_device *device, u32 inst, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
541
nv04_gr_mthd_surf3d_clip_v(struct nvkm_device *device, u32 inst, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
559
nv04_gr_mthd_bind_class(struct nvkm_device *device, u32 inst)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
561
return nvkm_rd32(device, 0x700000 + (inst << 4));
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
565
nv04_gr_mthd_bind_surf2d(struct nvkm_device *device, u32 inst, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
569
nv04_gr_set_ctx1(device, inst, 0x00004000, 0);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
570
nv04_gr_set_ctx_val(device, inst, 0x02000000, 0);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
573
nv04_gr_set_ctx1(device, inst, 0x00004000, 0);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
574
nv04_gr_set_ctx_val(device, inst, 0x02000000, 0x02000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
581
nv04_gr_mthd_bind_surf2d_swzsurf(struct nvkm_device *device, u32 inst, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
585
nv04_gr_set_ctx1(device, inst, 0x00004000, 0);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
586
nv04_gr_set_ctx_val(device, inst, 0x02000000, 0);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
589
nv04_gr_set_ctx1(device, inst, 0x00004000, 0);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
590
nv04_gr_set_ctx_val(device, inst, 0x02000000, 0x02000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
593
nv04_gr_set_ctx1(device, inst, 0x00004000, 0x00004000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
594
nv04_gr_set_ctx_val(device, inst, 0x02000000, 0x02000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
601
nv01_gr_mthd_bind_patt(struct nvkm_device *device, u32 inst, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
605
nv04_gr_set_ctx_val(device, inst, 0x08000000, 0);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
608
nv04_gr_set_ctx_val(device, inst, 0x08000000, 0x08000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
615
nv04_gr_mthd_bind_patt(struct nvkm_device *device, u32 inst, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
619
nv04_gr_set_ctx_val(device, inst, 0x08000000, 0);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
622
nv04_gr_set_ctx_val(device, inst, 0x08000000, 0x08000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
629
nv04_gr_mthd_bind_rop(struct nvkm_device *device, u32 inst, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
633
nv04_gr_set_ctx_val(device, inst, 0x10000000, 0);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
636
nv04_gr_set_ctx_val(device, inst, 0x10000000, 0x10000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
643
nv04_gr_mthd_bind_beta1(struct nvkm_device *device, u32 inst, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
647
nv04_gr_set_ctx_val(device, inst, 0x20000000, 0);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
650
nv04_gr_set_ctx_val(device, inst, 0x20000000, 0x20000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
657
nv04_gr_mthd_bind_beta4(struct nvkm_device *device, u32 inst, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
661
nv04_gr_set_ctx_val(device, inst, 0x40000000, 0);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
664
nv04_gr_set_ctx_val(device, inst, 0x40000000, 0x40000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
671
nv04_gr_mthd_bind_surf_dst(struct nvkm_device *device, u32 inst, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
675
nv04_gr_set_ctx_val(device, inst, 0x02000000, 0);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
678
nv04_gr_set_ctx_val(device, inst, 0x02000000, 0x02000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
685
nv04_gr_mthd_bind_surf_src(struct nvkm_device *device, u32 inst, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
689
nv04_gr_set_ctx_val(device, inst, 0x04000000, 0);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
692
nv04_gr_set_ctx_val(device, inst, 0x04000000, 0x04000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
699
nv04_gr_mthd_bind_surf_color(struct nvkm_device *device, u32 inst, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
703
nv04_gr_set_ctx_val(device, inst, 0x02000000, 0);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
706
nv04_gr_set_ctx_val(device, inst, 0x02000000, 0x02000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
713
nv04_gr_mthd_bind_surf_zeta(struct nvkm_device *device, u32 inst, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
717
nv04_gr_set_ctx_val(device, inst, 0x04000000, 0);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
720
nv04_gr_set_ctx_val(device, inst, 0x04000000, 0x04000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
727
nv01_gr_mthd_bind_clip(struct nvkm_device *device, u32 inst, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
731
nv04_gr_set_ctx1(device, inst, 0x2000, 0);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
734
nv04_gr_set_ctx1(device, inst, 0x2000, 0x2000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
741
nv01_gr_mthd_bind_chroma(struct nvkm_device *device, u32 inst, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
745
nv04_gr_set_ctx1(device, inst, 0x1000, 0);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
751
nv04_gr_set_ctx1(device, inst, 0x1000, 0x1000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
758
nv03_gr_mthd_gdi(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
770
return func(device, inst, data);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
774
nv04_gr_mthd_gdi(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
787
return func(device, inst, data);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
791
nv01_gr_mthd_blit(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
806
return func(device, inst, data);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
810
nv04_gr_mthd_blit(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
825
return func(device, inst, data);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
829
nv04_gr_mthd_iifc(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
844
return func(device, inst, data);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
848
nv01_gr_mthd_ifc(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
862
return func(device, inst, data);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
866
nv04_gr_mthd_ifc(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
881
return func(device, inst, data);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
885
nv03_gr_mthd_sifc(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
898
return func(device, inst, data);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
902
nv04_gr_mthd_sifc(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
916
return func(device, inst, data);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
920
nv03_gr_mthd_sifm(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
932
return func(device, inst, data);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
936
nv04_gr_mthd_sifm(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
949
return func(device, inst, data);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
953
nv04_gr_mthd_surf3d(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
962
return func(device, inst, data);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
966
nv03_gr_mthd_ttri(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
976
return func(device, inst, data);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
980
nv01_gr_mthd_prim(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
993
return func(device, inst, data);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
997
nv04_gr_mthd_prim(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
1176
enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
1185
return nvkm_gr_ctor(func, device, type, inst, true, &gr->base);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
1218
nv10_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
1220
return nv10_gr_new_(&nv10_gr, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
812
nv10_gr_load_dma_vtxbuf(struct nv10_gr_chan *chan, int chid, u32 inst)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
835
if (subchan < 0 || !inst)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
862
nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2_DL, inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
887
u32 inst;
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
900
inst = nvkm_rd32(device, NV10_PGRAPH_GLOBALSTATE1) & 0xffff;
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
901
nv10_gr_load_dma_vtxbuf(chan, chid, inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv15.c
56
nv15_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv15.c
58
return nv10_gr_new_(&nv15_gr, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv17.c
56
nv17_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv17.c
58
return nv10_gr_new_(&nv17_gr, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
100
nvkm_wo32(chan->inst, 0x047c, 0x00000101);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
101
nvkm_wo32(chan->inst, 0x0490, 0x00000111);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
102
nvkm_wo32(chan->inst, 0x04a8, 0x44400000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
104
nvkm_wo32(chan->inst, i, 0x00030303);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
106
nvkm_wo32(chan->inst, i, 0x00080000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
108
nvkm_wo32(chan->inst, i, 0x01012000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
110
nvkm_wo32(chan->inst, i, 0x000105b8);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
112
nvkm_wo32(chan->inst, i, 0x00080008);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
114
nvkm_wo32(chan->inst, i, 0x07ff0000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
115
nvkm_wo32(chan->inst, 0x05a4, 0x4b7fffff);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
116
nvkm_wo32(chan->inst, 0x05fc, 0x00000001);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
117
nvkm_wo32(chan->inst, 0x0604, 0x00004000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
118
nvkm_wo32(chan->inst, 0x0610, 0x00000001);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
119
nvkm_wo32(chan->inst, 0x0618, 0x00040000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
120
nvkm_wo32(chan->inst, 0x061c, 0x00010000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
122
nvkm_wo32(chan->inst, (i + 0), 0x10700ff9);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
123
nvkm_wo32(chan->inst, (i + 4), 0x0436086c);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
124
nvkm_wo32(chan->inst, (i + 8), 0x000c001b);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
126
nvkm_wo32(chan->inst, 0x281c, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
127
nvkm_wo32(chan->inst, 0x2830, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
128
nvkm_wo32(chan->inst, 0x285c, 0x40000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
129
nvkm_wo32(chan->inst, 0x2860, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
130
nvkm_wo32(chan->inst, 0x2864, 0x3f000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
131
nvkm_wo32(chan->inst, 0x286c, 0x40000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
132
nvkm_wo32(chan->inst, 0x2870, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
133
nvkm_wo32(chan->inst, 0x2878, 0xbf800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
134
nvkm_wo32(chan->inst, 0x2880, 0xbf800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
135
nvkm_wo32(chan->inst, 0x34a4, 0x000fe000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
136
nvkm_wo32(chan->inst, 0x3530, 0x000003f8);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
137
nvkm_wo32(chan->inst, 0x3540, 0x002fe000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
139
nvkm_wo32(chan->inst, i, 0x001c527c);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
140
nvkm_done(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
21
u32 inst = nvkm_memory_addr(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
24
nvkm_wo32(gr->ctxtab, chan->chid * 4, inst >> 4);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
333
enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
341
return nvkm_gr_ctor(func, device, type, inst, true, &gr->base);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
35
u32 inst = nvkm_memory_addr(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
373
nv20_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
375
return nv20_gr_new_(&nv20_gr, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
42
nvkm_wr32(device, 0x400784, inst >> 4);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
63
nvkm_memory_unref(&chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
91
&chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
95
nvkm_kmap(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
96
nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24));
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
97
nvkm_wo32(chan->inst, 0x033c, 0xffff0000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
98
nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
99
nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h
29
struct nvkm_memory *inst;
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
132
nv25_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
134
return nv20_gr_new_(&nv25_gr, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
37
&chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
41
nvkm_kmap(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
42
nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24));
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
43
nvkm_wo32(chan->inst, 0x035c, 0xffff0000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
44
nvkm_wo32(chan->inst, 0x03c0, 0x0fff0000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
45
nvkm_wo32(chan->inst, 0x03c4, 0x0fff0000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
46
nvkm_wo32(chan->inst, 0x049c, 0x00000101);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
47
nvkm_wo32(chan->inst, 0x04b0, 0x00000111);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
48
nvkm_wo32(chan->inst, 0x04c8, 0x00000080);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
49
nvkm_wo32(chan->inst, 0x04cc, 0xffff0000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
50
nvkm_wo32(chan->inst, 0x04d0, 0x00000001);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
51
nvkm_wo32(chan->inst, 0x04e4, 0x44400000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
52
nvkm_wo32(chan->inst, 0x04fc, 0x4b800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
54
nvkm_wo32(chan->inst, i, 0x00030303);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
56
nvkm_wo32(chan->inst, i, 0x00080000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
58
nvkm_wo32(chan->inst, i, 0x01012000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
60
nvkm_wo32(chan->inst, i, 0x000105b8);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
62
nvkm_wo32(chan->inst, i, 0x00080008);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
64
nvkm_wo32(chan->inst, i, 0x07ff0000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
65
nvkm_wo32(chan->inst, 0x05e0, 0x4b7fffff);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
66
nvkm_wo32(chan->inst, 0x0620, 0x00000080);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
67
nvkm_wo32(chan->inst, 0x0624, 0x30201000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
68
nvkm_wo32(chan->inst, 0x0628, 0x70605040);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
69
nvkm_wo32(chan->inst, 0x062c, 0xb0a09080);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
70
nvkm_wo32(chan->inst, 0x0630, 0xf0e0d0c0);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
71
nvkm_wo32(chan->inst, 0x0664, 0x00000001);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
72
nvkm_wo32(chan->inst, 0x066c, 0x00004000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
73
nvkm_wo32(chan->inst, 0x0678, 0x00000001);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
74
nvkm_wo32(chan->inst, 0x0680, 0x00040000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
75
nvkm_wo32(chan->inst, 0x0684, 0x00010000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
77
nvkm_wo32(chan->inst, (i + 0), 0x10700ff9);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
78
nvkm_wo32(chan->inst, (i + 4), 0x0436086c);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
79
nvkm_wo32(chan->inst, (i + 8), 0x000c001b);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
81
nvkm_wo32(chan->inst, 0x2704, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
82
nvkm_wo32(chan->inst, 0x2718, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
83
nvkm_wo32(chan->inst, 0x2744, 0x40000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
84
nvkm_wo32(chan->inst, 0x2748, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
85
nvkm_wo32(chan->inst, 0x274c, 0x3f000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
86
nvkm_wo32(chan->inst, 0x2754, 0x40000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
87
nvkm_wo32(chan->inst, 0x2758, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
88
nvkm_wo32(chan->inst, 0x2760, 0xbf800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
89
nvkm_wo32(chan->inst, 0x2768, 0xbf800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
90
nvkm_wo32(chan->inst, 0x308c, 0x000fe000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
91
nvkm_wo32(chan->inst, 0x3108, 0x000003f8);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
92
nvkm_wo32(chan->inst, 0x3468, 0x002fe000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
94
nvkm_wo32(chan->inst, i, 0x001c527c);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
95
nvkm_done(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
123
nv2a_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
125
return nv20_gr_new_(&nv2a_gr, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
37
&chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
41
nvkm_kmap(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
42
nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24));
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
43
nvkm_wo32(chan->inst, 0x033c, 0xffff0000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
44
nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
45
nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
46
nvkm_wo32(chan->inst, 0x047c, 0x00000101);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
47
nvkm_wo32(chan->inst, 0x0490, 0x00000111);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
48
nvkm_wo32(chan->inst, 0x04a8, 0x44400000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
50
nvkm_wo32(chan->inst, i, 0x00030303);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
52
nvkm_wo32(chan->inst, i, 0x00080000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
54
nvkm_wo32(chan->inst, i, 0x01012000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
56
nvkm_wo32(chan->inst, i, 0x000105b8);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
58
nvkm_wo32(chan->inst, i, 0x00080008);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
60
nvkm_wo32(chan->inst, i, 0x07ff0000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
61
nvkm_wo32(chan->inst, 0x05a4, 0x4b7fffff);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
62
nvkm_wo32(chan->inst, 0x05fc, 0x00000001);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
63
nvkm_wo32(chan->inst, 0x0604, 0x00004000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
64
nvkm_wo32(chan->inst, 0x0610, 0x00000001);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
65
nvkm_wo32(chan->inst, 0x0618, 0x00040000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
66
nvkm_wo32(chan->inst, 0x061c, 0x00010000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
68
nvkm_wo32(chan->inst, (i + 0), 0x10700ff9);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
69
nvkm_wo32(chan->inst, (i + 4), 0x0436086c);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
70
nvkm_wo32(chan->inst, (i + 8), 0x000c001b);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
72
nvkm_wo32(chan->inst, 0x269c, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
73
nvkm_wo32(chan->inst, 0x26b0, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
74
nvkm_wo32(chan->inst, 0x26dc, 0x40000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
75
nvkm_wo32(chan->inst, 0x26e0, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
76
nvkm_wo32(chan->inst, 0x26e4, 0x3f000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
77
nvkm_wo32(chan->inst, 0x26ec, 0x40000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
78
nvkm_wo32(chan->inst, 0x26f0, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
79
nvkm_wo32(chan->inst, 0x26f8, 0xbf800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
80
nvkm_wo32(chan->inst, 0x2700, 0xbf800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
81
nvkm_wo32(chan->inst, 0x3024, 0x000fe000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
82
nvkm_wo32(chan->inst, 0x30a0, 0x000003f8);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
83
nvkm_wo32(chan->inst, 0x33fc, 0x002fe000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
85
nvkm_wo32(chan->inst, i, 0x001c527c);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
86
nvkm_done(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
197
nv30_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
199
return nv20_gr_new_(&nv30_gr, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
38
&chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
42
nvkm_kmap(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
43
nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24));
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
44
nvkm_wo32(chan->inst, 0x0410, 0x00000101);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
45
nvkm_wo32(chan->inst, 0x0424, 0x00000111);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
46
nvkm_wo32(chan->inst, 0x0428, 0x00000060);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
47
nvkm_wo32(chan->inst, 0x0444, 0x00000080);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
48
nvkm_wo32(chan->inst, 0x0448, 0xffff0000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
49
nvkm_wo32(chan->inst, 0x044c, 0x00000001);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
50
nvkm_wo32(chan->inst, 0x0460, 0x44400000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
51
nvkm_wo32(chan->inst, 0x048c, 0xffff0000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
53
nvkm_wo32(chan->inst, i, 0x0fff0000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
54
nvkm_wo32(chan->inst, 0x04ec, 0x00011100);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
56
nvkm_wo32(chan->inst, i, 0x07ff0000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
57
nvkm_wo32(chan->inst, 0x0550, 0x4b7fffff);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
58
nvkm_wo32(chan->inst, 0x058c, 0x00000080);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
59
nvkm_wo32(chan->inst, 0x0590, 0x30201000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
60
nvkm_wo32(chan->inst, 0x0594, 0x70605040);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
61
nvkm_wo32(chan->inst, 0x0598, 0xb8a89888);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
62
nvkm_wo32(chan->inst, 0x059c, 0xf8e8d8c8);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
63
nvkm_wo32(chan->inst, 0x05b0, 0xb0000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
65
nvkm_wo32(chan->inst, i, 0x00010588);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
67
nvkm_wo32(chan->inst, i, 0x00030303);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
69
nvkm_wo32(chan->inst, i, 0x0008aae4);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
71
nvkm_wo32(chan->inst, i, 0x01012000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
73
nvkm_wo32(chan->inst, i, 0x00080008);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
74
nvkm_wo32(chan->inst, 0x085c, 0x00040000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
75
nvkm_wo32(chan->inst, 0x0860, 0x00010000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
77
nvkm_wo32(chan->inst, i, 0x00040004);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
79
nvkm_wo32(chan->inst, i + 0, 0x10700ff9);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
80
nvkm_wo32(chan->inst, i + 4, 0x0436086c);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
81
nvkm_wo32(chan->inst, i + 8, 0x000c001b);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
84
nvkm_wo32(chan->inst, i, 0x0000ffff);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
85
nvkm_wo32(chan->inst, 0x344c, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
86
nvkm_wo32(chan->inst, 0x3808, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
87
nvkm_wo32(chan->inst, 0x381c, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
88
nvkm_wo32(chan->inst, 0x3848, 0x40000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
89
nvkm_wo32(chan->inst, 0x384c, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
90
nvkm_wo32(chan->inst, 0x3850, 0x3f000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
91
nvkm_wo32(chan->inst, 0x3858, 0x40000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
92
nvkm_wo32(chan->inst, 0x385c, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
93
nvkm_wo32(chan->inst, 0x3864, 0xbf800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
94
nvkm_wo32(chan->inst, 0x386c, 0xbf800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
95
nvkm_done(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
134
nv34_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
136
return nv20_gr_new_(&nv34_gr, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
37
&chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
41
nvkm_kmap(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
42
nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24));
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
43
nvkm_wo32(chan->inst, 0x040c, 0x01000101);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
44
nvkm_wo32(chan->inst, 0x0420, 0x00000111);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
45
nvkm_wo32(chan->inst, 0x0424, 0x00000060);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
46
nvkm_wo32(chan->inst, 0x0440, 0x00000080);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
47
nvkm_wo32(chan->inst, 0x0444, 0xffff0000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
48
nvkm_wo32(chan->inst, 0x0448, 0x00000001);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
49
nvkm_wo32(chan->inst, 0x045c, 0x44400000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
50
nvkm_wo32(chan->inst, 0x0480, 0xffff0000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
52
nvkm_wo32(chan->inst, i, 0x0fff0000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
53
nvkm_wo32(chan->inst, 0x04e0, 0x00011100);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
55
nvkm_wo32(chan->inst, i, 0x07ff0000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
56
nvkm_wo32(chan->inst, 0x0544, 0x4b7fffff);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
57
nvkm_wo32(chan->inst, 0x057c, 0x00000080);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
58
nvkm_wo32(chan->inst, 0x0580, 0x30201000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
59
nvkm_wo32(chan->inst, 0x0584, 0x70605040);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
60
nvkm_wo32(chan->inst, 0x0588, 0xb8a89888);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
61
nvkm_wo32(chan->inst, 0x058c, 0xf8e8d8c8);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
62
nvkm_wo32(chan->inst, 0x05a0, 0xb0000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
64
nvkm_wo32(chan->inst, i, 0x00010588);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
66
nvkm_wo32(chan->inst, i, 0x00030303);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
68
nvkm_wo32(chan->inst, i, 0x0008aae4);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
70
nvkm_wo32(chan->inst, i, 0x01012000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
72
nvkm_wo32(chan->inst, i, 0x00080008);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
73
nvkm_wo32(chan->inst, 0x0850, 0x00040000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
74
nvkm_wo32(chan->inst, 0x0854, 0x00010000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
76
nvkm_wo32(chan->inst, i, 0x00040004);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
78
nvkm_wo32(chan->inst, i + 0, 0x10700ff9);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
79
nvkm_wo32(chan->inst, i + 4, 0x0436086c);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
80
nvkm_wo32(chan->inst, i + 8, 0x000c001b);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
83
nvkm_wo32(chan->inst, i, 0x0000ffff);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
84
nvkm_wo32(chan->inst, 0x2ae0, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
85
nvkm_wo32(chan->inst, 0x2e9c, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
86
nvkm_wo32(chan->inst, 0x2eb0, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
87
nvkm_wo32(chan->inst, 0x2edc, 0x40000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
88
nvkm_wo32(chan->inst, 0x2ee0, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
89
nvkm_wo32(chan->inst, 0x2ee4, 0x3f000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
90
nvkm_wo32(chan->inst, 0x2eec, 0x40000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
91
nvkm_wo32(chan->inst, 0x2ef0, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
92
nvkm_wo32(chan->inst, 0x2ef8, 0xbf800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
93
nvkm_wo32(chan->inst, 0x2f00, 0xbf800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
94
nvkm_done(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
134
nv35_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
136
return nv20_gr_new_(&nv35_gr, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
37
&chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
41
nvkm_kmap(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
42
nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24));
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
43
nvkm_wo32(chan->inst, 0x040c, 0x00000101);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
44
nvkm_wo32(chan->inst, 0x0420, 0x00000111);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
45
nvkm_wo32(chan->inst, 0x0424, 0x00000060);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
46
nvkm_wo32(chan->inst, 0x0440, 0x00000080);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
47
nvkm_wo32(chan->inst, 0x0444, 0xffff0000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
48
nvkm_wo32(chan->inst, 0x0448, 0x00000001);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
49
nvkm_wo32(chan->inst, 0x045c, 0x44400000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
50
nvkm_wo32(chan->inst, 0x0488, 0xffff0000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
52
nvkm_wo32(chan->inst, i, 0x0fff0000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
53
nvkm_wo32(chan->inst, 0x04e8, 0x00011100);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
55
nvkm_wo32(chan->inst, i, 0x07ff0000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
56
nvkm_wo32(chan->inst, 0x054c, 0x4b7fffff);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
57
nvkm_wo32(chan->inst, 0x0588, 0x00000080);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
58
nvkm_wo32(chan->inst, 0x058c, 0x30201000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
59
nvkm_wo32(chan->inst, 0x0590, 0x70605040);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
60
nvkm_wo32(chan->inst, 0x0594, 0xb8a89888);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
61
nvkm_wo32(chan->inst, 0x0598, 0xf8e8d8c8);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
62
nvkm_wo32(chan->inst, 0x05ac, 0xb0000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
64
nvkm_wo32(chan->inst, i, 0x00010588);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
66
nvkm_wo32(chan->inst, i, 0x00030303);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
68
nvkm_wo32(chan->inst, i, 0x0008aae4);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
70
nvkm_wo32(chan->inst, i, 0x01012000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
72
nvkm_wo32(chan->inst, i, 0x00080008);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
73
nvkm_wo32(chan->inst, 0x0860, 0x00040000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
74
nvkm_wo32(chan->inst, 0x0864, 0x00010000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
76
nvkm_wo32(chan->inst, i, 0x00040004);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
78
nvkm_wo32(chan->inst, i + 0, 0x10700ff9);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
79
nvkm_wo32(chan->inst, i + 4, 0x0436086c);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
80
nvkm_wo32(chan->inst, i + 8, 0x000c001b);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
83
nvkm_wo32(chan->inst, i, 0x0000ffff);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
84
nvkm_wo32(chan->inst, 0x3450, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
85
nvkm_wo32(chan->inst, 0x380c, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
86
nvkm_wo32(chan->inst, 0x3820, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
87
nvkm_wo32(chan->inst, 0x384c, 0x40000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
88
nvkm_wo32(chan->inst, 0x3850, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
89
nvkm_wo32(chan->inst, 0x3854, 0x3f000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
90
nvkm_wo32(chan->inst, 0x385c, 0x40000000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
91
nvkm_wo32(chan->inst, 0x3860, 0x3f800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
92
nvkm_wo32(chan->inst, 0x3868, 0xbf800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
93
nvkm_wo32(chan->inst, 0x3870, 0xbf800000);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
94
nvkm_done(chan->inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
103
if (nvkm_rd32(device, 0x40032c) == inst) {
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
106
nvkm_wr32(device, 0x400784, inst);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
122
if (nvkm_rd32(device, 0x400330) == inst)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
241
u32 inst = nvkm_rd32(device, 0x40032c) & 0x000fffff;
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
253
if (temp->inst >> 4 == inst) {
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
278
chan ? chan->fifo->id : -1, inst << 4,
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
432
enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
441
return nvkm_gr_ctor(func, device, type, inst, true, &gr->base);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
473
nv40_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
475
return nv40_gr_new_(&nv40_gr, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
82
chan->inst = (*pgpuobj)->addr;
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
85
nvkm_wo32(*pgpuobj, 0x00000, chan->inst >> 4);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
98
u32 inst = 0x01000000 | chan->inst >> 4;
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h
26
u32 inst;
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c
105
nv44_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c
107
return nv40_gr_new_(&nv44_gr, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
396
int chid, u64 inst, const char *name)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
436
chid, inst, name, subc, class, mthd,
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
461
"40084c %08x\n", chid, inst, name,
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
627
u32 inst = nvkm_rd32(device, 0x40032c) & 0x0fffffff;
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
640
chan = nvkm_chan_get_inst(&gr->base.engine, (u64)inst << 12, &flags);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
655
if (!nv50_gr_trap_handler(gr, show, chid, (u64)inst << 12, name))
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
668
stat, msg, chid, (u64)inst << 12, name,
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
764
enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
773
return nvkm_gr_ctor(func, device, type, inst, true, &gr->base);
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
793
nv50_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
795
return nv50_gr_new_(&nv50_gr, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h
35
u32 (*inst)(struct nvkm_gr *);
drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c
219
tu102_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c
224
return gf100_gr_new_(tu102_gr_fwif, device, type, inst, pgr);
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/g84.c
40
g84_mpeg_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/g84.c
43
return nvkm_engine_new_(&g84_mpeg, device, type, inst, true, pmpeg);
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
128
u32 inst = data << 4;
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
129
u32 dma0 = nvkm_rd32(device, 0x700000 + inst);
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
130
u32 dma1 = nvkm_rd32(device, 0x700004 + inst);
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
131
u32 dma2 = nvkm_rd32(device, 0x700008 + inst);
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
138
inst, dma0, dma1, dma2);
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
276
enum nvkm_subdev_type type, int inst, struct nvkm_engine **pmpeg)
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
285
return nvkm_engine_ctor(&nv31_mpeg_, device, type, inst, true, &mpeg->engine);
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
294
nv31_mpeg_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
297
return nv31_mpeg_new_(&nv31_mpeg, device, type, inst, pmpeg);
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c
36
u32 inst = data << 4;
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c
37
u32 dma0 = nvkm_instmem_rd32(imem, inst + 0);
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c
38
u32 dma1 = nvkm_instmem_rd32(imem, inst + 4);
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c
39
u32 dma2 = nvkm_instmem_rd32(imem, inst + 8);
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c
46
inst, dma0, dma1, dma2);
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c
79
nv40_mpeg_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c
82
return nv31_mpeg_new_(&nv40_mpeg, device, type, inst, pmpeg);
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
149
u32 inst = nvkm_rd32(device, 0x00b318) & 0x000fffff;
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
158
if (temp->inst >> 4 == inst) {
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
184
chan ? chan->fifo->id : -1, inst << 4,
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
205
nv44_mpeg_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
215
return nvkm_engine_ctor(&nv44_mpeg, device, type, inst, true, &mpeg->engine);
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
48
u32 inst;
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
59
chan->inst = (*pgpuobj)->addr;
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
74
u32 inst = 0x80000000 | (chan->inst >> 4);
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
77
if (nvkm_rd32(device, 0x00b318) == inst)
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c
132
nv50_mpeg_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c
135
return nvkm_engine_new_(&nv50_mpeg, device, type, inst, true, pmpeg);
drivers/gpu/drm/nouveau/nvkm/engine/mspdec/base.c
28
enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine)
drivers/gpu/drm/nouveau/nvkm/engine/mspdec/base.c
30
return nvkm_falcon_new_(func, device, type, inst, true, 0x085000, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c
46
g98_mspdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c
49
return nvkm_mspdec_new_(&g98_mspdec, device, type, inst, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c
46
gf100_mspdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c
49
return nvkm_mspdec_new_(&gf100_mspdec, device, type, inst, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c
38
gk104_mspdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c
41
return nvkm_mspdec_new_(&gk104_mspdec, device, type, inst, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gt215.c
38
gt215_mspdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gt215.c
41
return nvkm_mspdec_new_(>215_mspdec, device, type, inst, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/msppp/base.c
28
enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine)
drivers/gpu/drm/nouveau/nvkm/engine/msppp/base.c
30
return nvkm_falcon_new_(func, device, type, inst, true, 0x086000, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c
46
g98_msppp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c
49
return nvkm_msppp_new_(&g98_msppp, device, type, inst, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c
46
gf100_msppp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c
49
return nvkm_msppp_new_(&gf100_msppp, device, type, inst, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/msppp/gt215.c
38
gt215_msppp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/msppp/gt215.c
41
return nvkm_msppp_new_(>215_msppp, device, type, inst, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/msvld/base.c
28
enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine)
drivers/gpu/drm/nouveau/nvkm/engine/msvld/base.c
30
return nvkm_falcon_new_(func, device, type, inst, true, 0x084000, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c
46
g98_msvld_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c
49
return nvkm_msvld_new_(&g98_msvld, device, type, inst, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c
46
gf100_msvld_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c
49
return nvkm_msvld_new_(&gf100_msvld, device, type, inst, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c
38
gk104_msvld_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c
41
return nvkm_msvld_new_(&gk104_msvld, device, type, inst, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/msvld/gt215.c
38
gt215_msvld_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/msvld/gt215.c
41
return nvkm_msvld_new_(>215_msvld, device, type, inst, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/msvld/mcp89.c
38
mcp89_msvld_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/msvld/mcp89.c
41
return nvkm_msvld_new_(&mcp89_msvld, device, type, inst, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c
41
enum nvkm_subdev_type type, int inst, u32 addr, struct nvkm_nvdec **pnvdec)
drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c
49
ret = nvkm_engine_ctor(&nvkm_nvdec, device, type, inst, true,
drivers/gpu/drm/nouveau/nvkm/engine/nvdec/ga102.c
56
ga102_nvdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/nvdec/ga102.c
62
return nvkm_nvdec_new_(ga102_nvdec_fwif, device, type, inst, 0x848000, pnvdec);
drivers/gpu/drm/nouveau/nvkm/engine/nvdec/gm107.c
54
gm107_nvdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/nvdec/gm107.c
57
return nvkm_nvdec_new_(gm107_nvdec_fwif, device, type, inst, 0, pnvdec);
drivers/gpu/drm/nouveau/nvkm/engine/nvdec/tu102.c
27
tu102_nvdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/nvdec/tu102.c
33
return nvkm_nvdec_new_(gm107_nvdec_fwif, device, type, inst, 0, pnvdec);
drivers/gpu/drm/nouveau/nvkm/engine/nvenc/base.c
42
enum nvkm_subdev_type type, int inst, struct nvkm_nvenc **pnvenc)
drivers/gpu/drm/nouveau/nvkm/engine/nvenc/base.c
50
ret = nvkm_engine_ctor(&nvkm_nvenc, device, type, inst, true,
drivers/gpu/drm/nouveau/nvkm/engine/nvenc/gm107.c
48
gm107_nvenc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/nvenc/gm107.c
51
return nvkm_nvenc_new_(gm107_nvenc_fwif, device, type, inst, pnvenc);
drivers/gpu/drm/nouveau/nvkm/engine/nvenc/tu102.c
27
tu102_nvenc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/nvenc/tu102.c
33
return nvkm_nvenc_new_(gm107_nvenc_fwif, device, type, inst, pnvenc);
drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c
58
chan ? chan->inst->addr : 0,
drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c
77
g98_sec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c
80
return nvkm_falcon_new_(&g98_sec, device, type, inst, true, 0x087000, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c
135
enum nvkm_subdev_type type, int inst, u32 addr, struct nvkm_sec2 **psec2)
drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c
143
ret = nvkm_engine_ctor(&nvkm_sec2, device, type, inst, true, &sec2->engine);
drivers/gpu/drm/nouveau/nvkm/engine/sec2/ga102.c
191
ga102_sec2_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/sec2/ga102.c
200
return r535_sec2_new(&ga102_sec2, device, type, inst, addr, psec2);
drivers/gpu/drm/nouveau/nvkm/engine/sec2/ga102.c
202
return nvkm_sec2_new_(ga102_sec2_fwif, device, type, inst, addr, psec2);
drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c
314
gp102_sec2_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c
317
return nvkm_sec2_new_(gp102_sec2_fwif, device, type, inst, 0, psec2);
drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp108.c
39
gp108_sec2_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp108.c
42
return nvkm_sec2_new_(gp108_sec2_fwif, device, type, inst, 0, psec2);
drivers/gpu/drm/nouveau/nvkm/engine/sec2/r535.c
40
enum nvkm_subdev_type type, int inst, u32 addr, struct nvkm_sec2 **psec2)
drivers/gpu/drm/nouveau/nvkm/engine/sec2/r535.c
48
ret = nvkm_engine_ctor(&r535_sec2, device, type, inst, true, &sec2->engine);
drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c
80
tu102_sec2_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c
89
return r535_sec2_new(&tu102_sec2, device, type, inst, addr, psec2);
drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c
91
return nvkm_sec2_new_(tu102_sec2_fwif, device, type, inst, addr, psec2);
drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c
108
return nvkm_engine_ctor(&nvkm_sw, device, type, inst, true, &sw->engine);
drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c
99
enum nvkm_subdev_type type, int inst, struct nvkm_sw **psw)
drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c
144
gf100_sw_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_sw **psw)
drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c
146
return nvkm_sw_new_(&gf100_sw, device, type, inst, psw);
drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c
45
u32 inst = chan->base.fifo->inst->addr >> 12;
drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c
47
nvkm_wr32(device, 0x001718, 0x80000000 | inst);
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c
136
nv04_sw_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_sw **psw)
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c
138
return nvkm_sw_new_(&nv04_sw, device, type, inst, psw);
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c
65
nv10_sw_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_sw **psw)
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c
67
return nvkm_sw_new_(&nv10_sw, device, type, inst, psw);
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c
139
nv50_sw_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_sw **psw)
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c
141
return nvkm_sw_new_(&nv50_sw, device, type, inst, psw);
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c
46
nvkm_wr32(device, 0x001704, chan->base.fifo->inst->addr >> 12);
drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c
39
g84_vp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c
42
return nvkm_xtensa_new_(&g84_vp, device, type, inst, true, 0x00f000, pengine);
drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c
179
enum nvkm_subdev_type type, int inst, bool enable, u32 addr,
drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c
190
return nvkm_engine_ctor(&nvkm_xtensa, device, type, inst, enable, &xtensa->engine);
drivers/gpu/drm/nouveau/nvkm/falcon/base.c
262
falcon->addr = nvkm_top_addr(subdev->device, subdev->type, subdev->inst);
drivers/gpu/drm/nouveau/nvkm/falcon/fw.c
128
struct nvkm_vmm *vmm, struct nvkm_memory *inst)
drivers/gpu/drm/nouveau/nvkm/falcon/fw.c
134
fw->inst = nvkm_memory_ref(inst);
drivers/gpu/drm/nouveau/nvkm/falcon/fw.c
159
nvkm_memory_unref(&fw->inst);
drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c
173
nvkm_mc_enable(device, falcon->owner->type, falcon->owner->inst);
drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c
205
nvkm_mc_disable(device, falcon->owner->type, falcon->owner->inst);
drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c
254
if (fw->inst) {
drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c
259
switch (nvkm_memory_target(fw->inst)) {
drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c
268
falcon->func->bind_inst(falcon, target, nvkm_memory_addr(fw->inst));
drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c
325
&acr->inst);
drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c
335
ret = nvkm_vmm_join(acr->vmm, acr->inst);
drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c
350
ret = nvkm_falcon_fw_oneinit(&hsfw->fw, falcon, acr->vmm, acr->inst);
drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c
373
nvkm_vmm_part(acr->vmm, acr->inst);
drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c
375
nvkm_memory_unref(&acr->inst);
drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c
421
enum nvkm_subdev_type type, int inst, struct nvkm_acr **pacr)
drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c
428
nvkm_subdev_ctor(&nvkm_acr, device, type, inst, &acr->subdev);
drivers/gpu/drm/nouveau/nvkm/subdev/acr/ga102.c
323
ga102_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/acr/ga102.c
329
return nvkm_acr_new_(ga102_acr_fwif, device, type, inst, pacr);
drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c
370
gm200_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c
373
return nvkm_acr_new_(gm200_acr_fwif, device, type, inst, pacr);
drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm20b.c
136
gm20b_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm20b.c
139
return nvkm_acr_new_(gm20b_acr_fwif, device, type, inst, pacr);
drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.c
284
gp102_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.c
287
return nvkm_acr_new_(gp102_acr_fwif, device, type, inst, pacr);
drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp108.c
108
gp108_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp108.c
111
return nvkm_acr_new_(gp108_acr_fwif, device, type, inst, pacr);
drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp10b.c
55
gp10b_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp10b.c
58
return nvkm_acr_new_(gp10b_acr_fwif, device, type, inst, pacr);
drivers/gpu/drm/nouveau/nvkm/subdev/acr/gv100.c
63
gv100_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/acr/gv100.c
66
return nvkm_acr_new_(gv100_acr_fwif, device, type, inst, pacr);
drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c
257
const struct firmware *bl = NULL, *inst = NULL, *data = NULL;
drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c
274
ret = nvkm_firmware_load_name(subdev, path, "inst", ver, &inst);
drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c
292
lsfw->app_resident_code_size = ALIGN(inst->size, 256);
drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c
306
lsfw->app_resident_code_offset, inst->data, inst->size);
drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c
319
nvkm_firmware_put(inst);
drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c
337
const struct firmware *bl = NULL, *inst = &_inst, *data = &_data;
drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c
368
lsfw->app_resident_code_size = ALIGN(inst->size, 256);
drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c
383
lsfw->app_resident_code_offset, inst->data, inst->size);
drivers/gpu/drm/nouveau/nvkm/subdev/acr/priv.h
104
int inst, struct nvkm_acr **);
drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.c
201
tu102_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.c
207
return nvkm_acr_new_(tu102_acr_fwif, device, type, inst, pacr);
drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c
145
enum nvkm_subdev_type type, int inst, struct nvkm_bar *bar)
drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c
147
nvkm_subdev_ctor(&nvkm_bar, device, type, inst, &bar->subdev);
drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.c
59
g84_bar_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.c
62
return nv50_bar_new_(&g84_bar_func, device, type, inst, 0x200, pbar);
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
119
return nvkm_vmm_join(bar_vm->vmm, bar_vm->inst);
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
153
nvkm_vmm_part(bar->bar[1].vmm, bar->bar[1].inst);
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
155
nvkm_memory_unref(&bar->bar[1].inst);
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
157
nvkm_vmm_part(bar->bar[0].vmm, bar->bar[0].inst);
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
159
nvkm_memory_unref(&bar->bar[0].inst);
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
165
enum nvkm_subdev_type type, int inst, struct nvkm_bar **pbar)
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
170
nvkm_bar_ctor(func, device, type, inst, &bar->base);
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
192
gf100_bar_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
195
return gf100_bar_new_(&gf100_bar_func, device, type, inst, pbar);
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
56
const u32 addr = nvkm_memory_addr(bar->bar[1].inst) >> 12;
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
77
u32 addr = nvkm_memory_addr(bar->bar[0].inst) >> 12;
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
92
&bar_vm->inst);
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h
8
struct nvkm_memory *inst;
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c
35
gk20a_bar_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c
38
int ret = gf100_bar_new_(&gk20a_bar_func, device, type, inst, pbar);
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm107.c
62
gm107_bar_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm107.c
65
return gf100_bar_new_(&gm107_bar_func, device, type, inst, pbar);
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm20b.c
35
gm20b_bar_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm20b.c
38
int ret = gf100_bar_new_(&gm20b_bar_func, device, type, inst, pbar);
drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c
223
enum nvkm_subdev_type type, int inst, u32 pgd_addr, struct nvkm_bar **pbar)
drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c
228
nvkm_bar_ctor(func, device, type, inst, &bar->base);
drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c
251
nv50_bar_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c
254
return nv50_bar_new_(&nv50_bar_func, device, type, inst, 0x1400, pbar);
drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h
8
struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_bar **);
drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.c
100
return r535_bar_new_(&tu102_bar, device, type, inst, pbar);
drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.c
102
return gf100_bar_new_(&tu102_bar, device, type, inst, pbar);
drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.c
49
u32 addr = nvkm_memory_addr(bar->bar[0].inst) >> 12;
drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.c
76
const u32 addr = nvkm_memory_addr(bar->bar[1].inst) >> 12;
drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.c
96
tu102_bar_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.c
151
nvkm_bios_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.c
161
nvkm_subdev_ctor(&nvkm_bios, device, type, inst, &bios->subdev);
drivers/gpu/drm/nouveau/nvkm/subdev/bus/base.c
56
enum nvkm_subdev_type type, int inst, struct nvkm_bus **pbus)
drivers/gpu/drm/nouveau/nvkm/subdev/bus/base.c
61
nvkm_subdev_ctor(&nvkm_bus, device, type, inst, &bus->subdev);
drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.c
61
g94_bus_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.c
64
return nvkm_bus_new_(&g94_bus, device, type, inst, pbus);
drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.c
74
gf100_bus_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.c
80
return nvkm_bus_new_(&gf100_bus, device, type, inst, pbus);
drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c
71
nv04_bus_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c
74
return nvkm_bus_new_(&nv04_bus, device, type, inst, pbus);
drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c
85
nv31_bus_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c
88
return nvkm_bus_new_(&nv31_bus, device, type, inst, pbus);
drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c
102
nv50_bus_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c
105
return nvkm_bus_new_(&nv50_bus, device, type, inst, pbus);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
649
enum nvkm_subdev_type type, int inst, bool allow_reclock, struct nvkm_clk *clk)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
657
nvkm_subdev_ctor(&nvkm_clk, device, type, inst, subdev);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
711
enum nvkm_subdev_type type, int inst, bool allow_reclock, struct nvkm_clk **pclk)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
715
return nvkm_clk_ctor(func, device, type, inst, allow_reclock, *pclk);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.c
44
g84_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.c
47
return nv50_clk_new_(&g84_clk, device, type, inst, (device->chipset >= 0x94), pclk);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
471
gf100_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
480
return nvkm_clk_ctor(&gf100_clk, device, type, inst, false, &clk->base);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
507
gk104_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
516
return nvkm_clk_ctor(&gk104_clk, device, type, inst, true, &clk->base);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
618
gk20a_clk_ctor(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
635
ret = nvkm_clk_ctor(func, device, type, inst, true, &clk->base);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
646
gk20a_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
657
ret = gk20a_clk_ctor(device, type, inst, &gk20a_clk, &gk20a_pllg_params, clk);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
1019
gm20b_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
1030
return gm20b_clk_new_speedo0(device, type, inst, pclk);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
1042
ret = gk20a_clk_ctor(device, type, inst, &gm20b_clk, clk_params, &clk->base);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
1055
return gm20b_clk_new_speedo0(device, type, inst, pclk);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
916
gm20b_clk_new_speedo0(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
927
ret = gk20a_clk_ctor(device, type, inst, &gm20b_clk_speedo0, &gm20b_pllg_params, clk);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gp10b.c
160
gp10b_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gp10b.c
180
ret = nvkm_clk_ctor(func, device, type, inst, true, &clk->base);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
540
gt215_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
549
return nvkm_clk_ctor(>215_clk, device, type, inst, true, &clk->base);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
412
mcp77_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
421
return nvkm_clk_ctor(&mcp77_clk, device, type, inst, true, &clk->base);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c
75
nv04_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c
78
int ret = nvkm_clk_new_(&nv04_clk, device, type, inst, false, pclk);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
221
nv40_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
232
return nvkm_clk_ctor(&nv40_clk, device, type, inst, true, &clk->base);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
511
enum nvkm_subdev_type type, int inst, bool allow_reclock, struct nvkm_clk **pclk)
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
518
ret = nvkm_clk_ctor(func, device, type, inst, allow_reclock, &clk->base);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
559
nv50_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
562
return nv50_clk_new_(&nv50_clk, device, type, inst, false, pclk);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c
131
enum nvkm_subdev_type type, int inst, struct nvkm_devinit *init)
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c
133
nvkm_subdev_ctor(&nvkm_devinit, device, type, inst, &init->subdev);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c
61
g84_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c
64
return nv50_devinit_new_(&g84_devinit, device, type, inst, pinit);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c
60
g98_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c
63
return nv50_devinit_new_(&g98_devinit, device, type, inst, pinit);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ga100.c
85
ga100_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ga100.c
89
return r535_devinit_new(&ga100_devinit, device, type, inst, pinit);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ga100.c
91
return nv50_devinit_new_(&ga100_devinit, device, type, inst, pinit);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c
114
gf100_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c
117
return nv50_devinit_new_(&gf100_devinit, device, type, inst, pinit);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c
58
gm107_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c
61
return nv50_devinit_new_(&gm107_devinit, device, type, inst, pinit);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c
188
gm200_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c
191
return nv50_devinit_new_(&gm200_devinit, device, type, inst, pinit);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c
146
gt215_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c
149
return nv50_devinit_new_(>215_devinit, device, type, inst, pinit);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gv100.c
75
gv100_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gv100.c
78
return nv50_devinit_new_(&gv100_devinit, device, type, inst, pinit);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c
61
mcp89_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c
64
return nv50_devinit_new_(&mcp89_devinit, device, type, inst, pinit);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c
438
enum nvkm_subdev_type type, int inst, struct nvkm_devinit **pinit)
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c
446
nvkm_devinit_ctor(func, device, type, inst, &init->base);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c
461
nv04_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c
464
return nv04_devinit_new_(&nv04_devinit, device, type, inst, pinit);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c
139
nv05_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c
142
return nv04_devinit_new_(&nv05_devinit, device, type, inst, pinit);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c
109
nv10_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c
112
return nv04_devinit_new_(&nv10_devinit, device, type, inst, pinit);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.c
38
nv1a_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.c
41
return nv04_devinit_new_(&nv1a_devinit, device, type, inst, pinit);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c
75
nv20_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c
78
return nv04_devinit_new_(&nv20_devinit, device, type, inst, pinit);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c
149
enum nvkm_subdev_type type, int inst, struct nvkm_devinit **pinit)
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c
157
nvkm_devinit_ctor(func, device, type, inst, &init->base);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c
171
nv50_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c
174
return nv50_devinit_new_(&nv50_devinit, device, type, inst, pinit);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h
22
enum nvkm_subdev_type, int inst, struct nvkm_devinit *);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/r535.c
33
struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/r535.c
46
ret = nv50_devinit_new_(rm, device, type, inst, pdevinit);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.c
101
tu102_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.c
105
return r535_devinit_new(&tu102_devinit, device, type, inst, pinit);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.c
107
return nv50_devinit_new_(&tu102_devinit, device, type, inst, pinit);
drivers/gpu/drm/nouveau/nvkm/subdev/fault/base.c
156
enum nvkm_subdev_type type, int inst, struct nvkm_fault **pfault)
drivers/gpu/drm/nouveau/nvkm/subdev/fault/base.c
161
nvkm_subdev_ctor(&nvkm_fault, device, type, inst, &fault->subdev);
drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp100.c
85
gp100_fault_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp100.c
88
return nvkm_fault_new_(&gp100_fault, device, type, inst, pfault);
drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp10b.c
49
gp10b_fault_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp10b.c
52
return nvkm_fault_new_(&gp10b_fault, device, type, inst, pfault);
drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c
141
info.inst = ((u64)insthi << 32) | (info0 & 0xfffff000);
drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c
237
gv100_fault_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c
240
int ret = nvkm_fault_new_(&gv100_fault, device, type, inst, pfault);
drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c
60
info.inst = ((u64)insthi << 32) | instlo;
drivers/gpu/drm/nouveau/nvkm/subdev/fault/priv.h
24
int inst, struct nvkm_fault **);
drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c
176
tu102_fault_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c
184
ret = nvkm_fault_new_(&tu102_fault, device, type, inst, pfault);
drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c
99
info.inst = ((u64)insthi << 32) | (info0 & 0xfffff000);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c
273
enum nvkm_subdev_type type, int inst, struct nvkm_fb *fb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c
275
nvkm_subdev_ctor(&nvkm_fb, device, type, inst, &fb->subdev);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c
297
enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c
301
return nvkm_fb_ctor(func, device, type, inst, *pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c
35
g84_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c
37
return nv50_fb_new_(&g84_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga100.c
41
ga100_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga100.c
44
return r535_fb_new(&ga100_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga100.c
46
return gf100_fb_new_(&ga100_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga102.c
61
ga102_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga102.c
64
return r535_fb_new(&ga102_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga102.c
66
return gf100_fb_new_(&ga102_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gb100.c
34
gb100_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gb100.c
36
return r535_fb_new(&gb100_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gb202.c
30
gb202_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gb202.c
32
return r535_fb_new(&gb202_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c
111
enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c
117
nvkm_fb_ctor(func, device, type, inst, &fb->base);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c
136
gf100_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c
138
return gf100_fb_new_(&gf100_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf108.c
40
gf108_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf108.c
42
return gf100_fb_new_(&gf108_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gh100.c
30
gh100_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gh100.c
32
return r535_fb_new(&gh100_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c
87
gk104_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c
89
return gf100_fb_new_(&gk104_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk110.c
69
gk110_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk110.c
71
return gf100_fb_new_(&gk110_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c
37
gk20a_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c
39
return gf100_fb_new_(&gk20a_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c
40
gm107_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c
42
return gf100_fb_new_(&gm107_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm200.c
68
gm200_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm200.c
70
return gf100_fb_new_(&gm200_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm20b.c
38
gm20b_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm20b.c
40
return gf100_fb_new_(&gm20b_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.c
60
gp100_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.c
62
return gf100_fb_new_(&gp100_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp102.c
83
gp102_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp102.c
85
return gf100_fb_new_(&gp102_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp10b.c
35
gp10b_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp10b.c
37
return gf100_fb_new_(&gp10b_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c
35
gt215_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c
37
return nv50_fb_new_(>215_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c
47
gv100_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c
49
return gf100_fb_new_(&gv100_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c
34
mcp77_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c
36
return nv50_fb_new_(&mcp77_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c
34
mcp89_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c
36
return nv50_fb_new_(&mcp89_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c
47
nv04_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c
49
return nvkm_fb_new_(&nv04_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c
67
nv10_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c
69
return nvkm_fb_new_(&nv10_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c
39
nv1a_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c
41
return nvkm_fb_new_(&nv1a_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c
101
return nvkm_fb_new_(&nv20_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c
99
nv20_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c
57
nv25_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c
59
return nvkm_fb_new_(&nv25_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c
130
nv30_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c
132
return nvkm_fb_new_(&nv30_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c
59
nv35_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c
61
return nvkm_fb_new_(&nv35_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c
59
nv36_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c
61
return nvkm_fb_new_(&nv36_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c
65
nv40_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c
67
return nvkm_fb_new_(&nv40_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c
59
nv41_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c
61
return nvkm_fb_new_(&nv41_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c
68
nv44_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c
70
return nvkm_fb_new_(&nv44_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c
54
nv46_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c
56
return nvkm_fb_new_(&nv46_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c
42
nv47_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c
44
return nvkm_fb_new_(&nv47_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c
42
nv49_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c
44
return nvkm_fb_new_(&nv49_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c
40
nv4e_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c
42
return nvkm_fb_new_(&nv4e_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
142
u32 trap[6], idx, inst;
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
171
inst = ((trap[2] << 16) | trap[1]) << 12;
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
180
chan = nvkm_chan_get_inst(&device->fifo->engine, inst, &flags);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
186
chan ? chan->id : -1, inst,
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
243
enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
249
nvkm_fb_ctor(&nv50_fb_, device, type, inst, &fb->base);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
263
nv50_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
265
return nv50_fb_new_(&nv50_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h
10
struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h
52
enum nvkm_subdev_type type, int inst, struct nvkm_fb *);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h
54
enum nvkm_subdev_type type, int inst, struct nvkm_fb **);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/r535.c
69
struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/r535.c
82
ret = nvkm_fb_new_(rm, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/tu102.c
49
tu102_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/tu102.c
52
return r535_fb_new(&tu102_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/tu102.c
54
return gf100_fb_new_(&tu102_fb, device, type, inst, pfb);
drivers/gpu/drm/nouveau/nvkm/subdev/fsp/base.c
53
struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/fsp/base.c
63
nvkm_subdev_ctor(&nvkm_fsp, device, type, inst, &fsp->subdev);
drivers/gpu/drm/nouveau/nvkm/subdev/fsp/gb100.c
21
enum nvkm_subdev_type type, int inst, struct nvkm_fsp **pfsp)
drivers/gpu/drm/nouveau/nvkm/subdev/fsp/gb100.c
23
return nvkm_fsp_new_(&gb100_fsp, device, type, inst, pfsp);
drivers/gpu/drm/nouveau/nvkm/subdev/fsp/gb202.c
42
enum nvkm_subdev_type type, int inst, struct nvkm_fsp **pfsp)
drivers/gpu/drm/nouveau/nvkm/subdev/fsp/gb202.c
44
return nvkm_fsp_new_(&gb202_fsp, device, type, inst, pfsp);
drivers/gpu/drm/nouveau/nvkm/subdev/fsp/gh100.c
272
enum nvkm_subdev_type type, int inst, struct nvkm_fsp **pfsp)
drivers/gpu/drm/nouveau/nvkm/subdev/fsp/gh100.c
274
return nvkm_fsp_new_(&gh100_fsp, device, type, inst, pfsp);
drivers/gpu/drm/nouveau/nvkm/subdev/fsp/priv.h
24
struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fsp **);
drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.c
45
enum nvkm_subdev_type type, int inst, struct nvkm_fuse **pfuse)
drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.c
50
nvkm_subdev_ctor(&nvkm_fuse, device, type, inst, &fuse->subdev);
drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c
50
gf100_fuse_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c
53
return nvkm_fuse_new_(&gf100_fuse, device, type, inst, pfuse);
drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.c
41
gm107_fuse_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.c
47
return nvkm_fuse_new_(&gm107_fuse, device, type, inst, pfuse);
drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.c
48
nv50_fuse_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.c
51
return nvkm_fuse_new_(&nv50_fuse, device, type, inst, pfuse);
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c
226
enum nvkm_subdev_type type, int inst, struct nvkm_gpio **pgpio)
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c
233
nvkm_subdev_ctor(&nvkm_gpio, device, type, inst, &gpio->subdev);
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c
71
g94_gpio_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c
74
return nvkm_gpio_new_(&g94_gpio, device, type, inst, pgpio);
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/ga102.c
117
ga102_gpio_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/ga102.c
123
return nvkm_gpio_new_(&ga102_gpio, device, type, inst, pgpio);
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gf119.c
83
gf119_gpio_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gf119.c
86
return nvkm_gpio_new_(&gf119_gpio, device, type, inst, pgpio);
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c
73
gk104_gpio_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c
79
return nvkm_gpio_new_(&gk104_gpio, device, type, inst, pgpio);
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c
115
nv10_gpio_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c
118
return nvkm_gpio_new_(&nv10_gpio, device, type, inst, pgpio);
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c
129
nv50_gpio_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c
132
return nvkm_gpio_new_(&nv50_gpio, device, type, inst, pgpio);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ad102.c
53
ad102_gsp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ad102.c
56
return nvkm_gsp_new_(ad102_gsps, device, type, inst, pgsp);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c
131
enum nvkm_subdev_type type, int inst, struct nvkm_gsp **pgsp)
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c
138
nvkm_subdev_ctor(&nvkm_gsp, device, type, inst, &gsp->subdev);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c
25
nvkm_gsp_intr_nonstall(struct nvkm_gsp *gsp, enum nvkm_subdev_type type, int inst)
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c
28
if (gsp->intr[i].type == type && gsp->intr[i].inst == inst)
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c
36
nvkm_gsp_intr_stall(struct nvkm_gsp *gsp, enum nvkm_subdev_type type, int inst)
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c
39
if (gsp->intr[i].type == type && gsp->intr[i].inst == inst) {
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga100.c
70
ga100_gsp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga100.c
73
return nvkm_gsp_new_(ga100_gsps, device, type, inst, pgsp);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga102.c
187
ga102_gsp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga102.c
190
return nvkm_gsp_new_(ga102_gsps, device, type, inst, pgsp);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gb100.c
28
gb100_gsp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gb100.c
31
return nvkm_gsp_new_(gb100_gsps, device, type, inst, pgsp);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gb202.c
28
gb202_gsp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gb202.c
31
return nvkm_gsp_new_(gb202_gsps, device, type, inst, pgsp);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gh100.c
352
gh100_gsp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gh100.c
355
return nvkm_gsp_new_(gh100_gsps, device, type, inst, pgsp);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.c
55
gv100_gsp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.c
58
return nvkm_gsp_new_(gv100_gsps, device, type, inst, pgsp);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c
104
enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c
122
nvkm_engine_ctor(func, rm->device, type, inst, true, engine);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c
127
nvkm_rm_engine_new_(struct nvkm_rm *rm, enum nvkm_subdev_type type, int inst, u32 class,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c
137
ret = nvkm_rm_engine_ctor(nvkm_rm_engine_dtor, rm, type, inst, &class, 1, engine);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c
148
nvkm_rm_engine_new(struct nvkm_rm *rm, enum nvkm_subdev_type type, int inst)
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c
155
if (WARN_ON(inst >= ARRAY_SIZE(device->ce)))
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c
158
return nvkm_rm_engine_new_(rm, type, inst, gpu->ce.class, &device->ce[inst]);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c
160
if (inst != 0)
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c
165
if (WARN_ON(inst >= ARRAY_SIZE(device->nvdec)))
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c
168
return nvkm_rm_nvdec_new(rm, inst);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c
170
if (WARN_ON(inst >= ARRAY_SIZE(device->nvenc)))
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c
173
return nvkm_rm_nvenc_new(rm, inst);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c
175
if (WARN_ON(inst >= ARRAY_SIZE(device->nvjpg)))
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c
178
return nvkm_rm_engine_new_(rm, type, inst, gpu->nvjpg.class, &device->nvjpg[inst]);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c
180
if (WARN_ON(inst >= ARRAY_SIZE(device->ofa)))
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c
183
return nvkm_rm_engine_new_(rm, type, inst, gpu->ofa.class, &device->ofa[inst]);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c
41
const int inst = oclass->engine->subdev.inst;
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c
53
ret = rm->api->ce->alloc(chan, handle, class, inst, &obj->rm);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c
59
ret = rm->api->nvdec->alloc(chan, handle, class, inst, &obj->rm);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c
62
ret = rm->api->nvenc->alloc(chan, handle, class, inst, &obj->rm);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c
65
ret = rm->api->nvjpg->alloc(chan, handle, class, inst, &obj->rm);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c
68
ret = rm->api->ofa->alloc(chan, handle, class, inst, &obj->rm);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.h
10
enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.h
12
int nvkm_rm_engine_new(struct nvkm_rm *, enum nvkm_subdev_type, int inst);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.h
18
int nvkm_rm_nvdec_new(struct nvkm_rm *, int inst);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.h
19
int nvkm_rm_nvenc_new(struct nvkm_rm *, int inst);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/gr.h
40
struct nvkm_memory *inst;
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/nvdec.c
15
nvkm_rm_nvdec_new(struct nvkm_rm *rm, int inst)
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/nvdec.c
24
ret = nvkm_rm_engine_ctor(nvkm_rm_nvdec_dtor, rm, NVKM_ENGINE_NVDEC, inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/nvdec.c
31
rm->device->nvdec[inst] = nvdec;
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/nvenc.c
15
nvkm_rm_nvenc_new(struct nvkm_rm *rm, int inst)
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/nvenc.c
24
ret = nvkm_rm_engine_ctor(nvkm_rm_nvenc_dtor, rm, NVKM_ENGINE_NVENC, inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/nvenc.c
31
rm->device->nvenc[inst] = nvenc;
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/bar.c
166
enum nvkm_subdev_type type, int inst, struct nvkm_bar **pbar)
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/bar.c
187
ret = gf100_bar_new_(rm, device, type, inst, &bar);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/ce.c
28
r535_ce_alloc(struct nvkm_gsp_object *chan, u32 handle, u32 class, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/ce.c
38
args->engineType = NV2080_ENGINE_TYPE_COPY0 + inst;
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c
107
ctrl->channelInstance = inst;
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c
1517
ret = nvkm_gpuobj_new(device, 0x10000, 0x10000, false, NULL, &disp->inst);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c
1521
if (WARN_ON(nvkm_memory_target(disp->inst->memory) != NVKM_MEM_TARGET_VRAM))
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c
1530
ctrl->instMemPhysAddr = nvkm_memory_addr(disp->inst->memory);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c
1531
ctrl->instMemSize = nvkm_memory_size(disp->inst->memory);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c
168
r535_dmac_alloc(struct nvkm_disp *disp, u32 oclass, int inst, u32 put_offset,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c
1706
0x1000, 0, disp->inst, &disp->ramht);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c
1710
ret = nvkm_gsp_intr_stall(gsp, disp->engine.subdev.type, disp->engine.subdev.inst);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c
173
args = nvkm_gsp_rm_alloc_get(&disp->rm.object, (oclass << 16) | inst, oclass,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c
1731
enum nvkm_subdev_type type, int inst, struct nvkm_disp **pdisp)
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c
1771
ret = nvkm_disp_new_(rm, device, type, inst, pdisp);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c
178
args->channelInstance = inst;
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c
73
r535_disp_chan_set_pushbuf(struct nvkm_disp *disp, s32 oclass, int inst, struct nvkm_memory *memory)
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fbsr.c
306
struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fbsr.c
322
ret = nv50_instmem_new_(rm, device, type, inst, pinstmem);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c
124
args->instanceMem.size = fifo->func->chan.func->inst->size;
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c
184
eT, chan->runq, priv, chan->id, chan->inst->addr,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c
231
.inst = &gf100_chan_inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c
245
ret = nvkm_gsp_intr_nonstall(subdev->device->gsp, subdev->type, subdev->inst);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c
291
ctrl->size = vctx->inst->size;
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c
307
&vctx->inst);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c
311
ret = nvkm_vmm_get(vctx->vmm, 12, vctx->inst->size, &vctx->vma);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c
315
ret = nvkm_memory_map(vctx->inst, 0, vctx->vmm, vctx->vma, NULL, 0);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c
497
int inst, nv2080;
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c
503
inst = rm->api->fifo->xlat_rm_engine_type(rmid, &type, &nv2080);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c
504
if (inst < 0) {
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c
519
(rm->gpu->ce.grce_mask(device) & BIT(inst)) &&
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c
521
RUNL_DEBUG(runl, "skip LCE %d - GRCE without GR", inst);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c
526
ret = nvkm_rm_engine_new(gsp->rm, type, inst);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c
536
engn = nvkm_runl_add(runl, nv2080, &r535_engn_ce, type, inst);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c
539
engn = nvkm_runl_add(runl, nv2080, &r535_engn_gr, type, inst);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c
545
engn = nvkm_runl_add(runl, nv2080, &r535_flcn, type, inst);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c
589
enum nvkm_subdev_type type, int inst, struct nvkm_fifo **pfifo)
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c
606
return nvkm_fifo_new_(rm, device, type, inst, pfifo);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gr.c
283
struct nvkm_memory *inst;
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gr.c
292
ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x12000, 0, true, &golden.inst);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gr.c
306
nvkm_memory_addr(golden.inst),
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gr.c
307
nvkm_memory_addr(golden.inst) + 0x1000,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gr.c
308
nvkm_memory_addr(golden.inst) + 0x2000,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gr.c
339
nvkm_memory_unref(&golden.inst);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c
151
int inst;
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c
158
if (!rmapi->gsp->xlat_mc_engine_idx(ctrl->table[i].engineIdx, &type, &inst))
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c
167
gsp->intr[gsp->intr_nr].inst = inst;
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c
309
ret = nvkm_gsp_intr_stall(gsp, gsp->subdev.type, gsp->subdev.inst);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/nvdec.c
27
r535_nvdec_alloc(struct nvkm_gsp_object *chan, u32 handle, u32 class, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/nvdec.c
37
args->engineInstance = inst;
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/nvenc.c
27
r535_nvenc_alloc(struct nvkm_gsp_object *chan, u32 handle, u32 class, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/nvenc.c
37
args->engineInstance = inst;
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/nvjpg.c
27
r535_nvjpg_alloc(struct nvkm_gsp_object *chan, u32 handle, u32 class, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/nvjpg.c
37
args->engineInstance = inst;
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/ofa.c
27
r535_ofa_alloc(struct nvkm_gsp_object *chan, u32 handle, u32 class, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/vmm.c
168
struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/vmm.c
186
ret = nvkm_mmu_new_(rm, device, type, inst, pmmu);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/disp.c
15
r570_dmac_alloc(struct nvkm_disp *disp, u32 oclass, int inst, u32 put_offset,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/disp.c
20
args = nvkm_gsp_rm_alloc_get(&disp->rm.object, (oclass << 16) | inst, oclass,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/disp.c
25
args->channelInstance = inst;
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/disp.c
33
r570_disp_chan_set_pushbuf(struct nvkm_disp *disp, s32 oclass, int inst, struct nvkm_memory *memory)
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/disp.c
70
ctrl->channelInstance = inst;
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/fifo.c
69
args->instanceMem.size = fifo->func->chan.func->inst->size;
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/gr.c
120
&gr->scrubber.inst);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/gr.c
135
nvkm_memory_addr(gr->scrubber.inst),
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/gr.c
136
nvkm_memory_addr(gr->scrubber.inst) + 0x1000,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/gr.c
137
nvkm_memory_addr(gr->scrubber.inst) + 0x2000,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/gr.c
89
nvkm_memory_unref(&gr->scrubber.inst);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/ofa.c
10
r570_ofa_alloc(struct nvkm_gsp_object *parent, u32 handle, u32 oclass, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/ofa.c
20
args->engineInstance = inst;
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/rm.h
101
int (*dmac_alloc)(struct nvkm_disp *, u32 oclass, int inst, u32 put_offset,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/rm.h
122
int (*alloc)(struct nvkm_gsp_object *chan, u32 handle, u32 class, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/rm.h
38
bool (*xlat_mc_engine_idx)(u32 mc_engine_idx, enum nvkm_subdev_type *, int *inst);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/rm.h
99
int (*set_pushbuf)(struct nvkm_disp *, s32 oclass, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c
505
tu102_gsp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c
508
return nvkm_gsp_new_(tu102_gsps, device, type, inst, pgsp);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu116.c
54
tu116_gsp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu116.c
57
return nvkm_gsp_new_(tu116_gsps, device, type, inst, pgsp);
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c
259
enum nvkm_subdev_type type, int inst, struct nvkm_i2c **pi2c)
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c
272
nvkm_subdev_ctor(&nvkm_i2c, device, type, inst, &i2c->subdev);
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.c
69
g94_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.c
72
return nvkm_i2c_new_(&g94_i2c, device, type, inst, pi2c);
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.c
33
gf117_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.c
36
return nvkm_i2c_new_(&gf117_i2c, device, type, inst, pi2c);
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf119.c
37
gf119_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf119.c
40
return nvkm_i2c_new_(&gf119_i2c, device, type, inst, pi2c);
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.c
69
gk104_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.c
72
return nvkm_i2c_new_(&gk104_i2c, device, type, inst, pi2c);
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk110.c
42
gk110_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk110.c
45
return nvkm_i2c_new_(&gk110_i2c, device, type, inst, pi2c);
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm200.c
46
gm200_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm200.c
52
return nvkm_i2c_new_(&gm200_i2c, device, type, inst, pi2c);
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.c
33
nv04_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.c
36
return nvkm_i2c_new_(&nv04_i2c, device, type, inst, pi2c);
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.c
33
nv4e_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.c
36
return nvkm_i2c_new_(&nv4e_i2c, device, type, inst, pi2c);
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.c
33
nv50_i2c_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.c
36
return nvkm_i2c_new_(&nv50_i2c, device, type, inst, pi2c);
drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.c
315
nvkm_iccsense_ctor(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.c
318
nvkm_subdev_ctor(&iccsense_func, device, type, inst, &iccsense->subdev);
drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.c
322
nvkm_iccsense_new_(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.c
329
nvkm_iccsense_ctor(device, type, inst, *iccsense);
drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/gf100.c
27
gf100_iccsense_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/gf100.c
30
return nvkm_iccsense_new_(device, type, inst, piccsense);
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c
247
enum nvkm_subdev_type type, int inst, struct nvkm_instmem *imem)
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c
249
nvkm_subdev_ctor(&nvkm_instmem, device, type, inst, &imem->subdev);
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gh100.c
24
gh100_instmem_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gh100.c
27
return r535_instmem_new(&gh100_instmem, device, type, inst, pimem);
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c
574
gk20a_instmem_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c
582
nvkm_instmem_ctor(&gk20a_instmem, device, type, inst, &imem->base);
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c
265
nv04_instmem_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c
272
nvkm_instmem_ctor(&nv04_instmem, device, type, inst, &imem->base);
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c
238
nv40_instmem_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c
245
nvkm_instmem_ctor(&nv40_instmem, device, type, inst, &imem->base);
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c
429
struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c
436
nvkm_instmem_ctor(func, device, type, inst, &imem->base);
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c
443
nv50_instmem_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c
447
return r535_instmem_new(&nv50_instmem, device, type, inst, pimem);
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c
449
return nv50_instmem_new_(&nv50_instmem, device, type, inst, pimem);
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c
132
enum nvkm_subdev_type type, int inst, struct nvkm_ltc **pltc)
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c
139
nvkm_subdev_ctor(&nvkm_ltc, device, type, inst, <c->subdev);
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/ga102.c
55
ga102_ltc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/ga102.c
61
return nvkm_ltc_new_(&ga102_ltc, device, type, inst, pltc);
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c
253
gf100_ltc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c
256
return nvkm_ltc_new_(&gf100_ltc, device, type, inst, pltc);
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c
54
gk104_ltc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c
57
return nvkm_ltc_new_(&gk104_ltc, device, type, inst, pltc);
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c
149
gm107_ltc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c
152
return nvkm_ltc_new_(&gm107_ltc, device, type, inst, pltc);
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm200.c
61
gm200_ltc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm200.c
64
return nvkm_ltc_new_(&gm200_ltc, device, type, inst, pltc);
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.c
73
gp100_ltc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.c
76
return nvkm_ltc_new_(&gp100_ltc, device, type, inst, pltc);
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp102.c
51
gp102_ltc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp102.c
57
return nvkm_ltc_new_(&gp102_ltc, device, type, inst, pltc);
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c
58
gp10b_ltc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c
61
return nvkm_ltc_new_(&gp10b_ltc, device, type, inst, pltc);
drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
100
u64 pmc_enable = nvkm_mc_reset_mask(device, false, type, inst);
drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
128
enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc)
drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
136
nvkm_subdev_ctor(&nvkm_mc, device, type, inst, &mc->subdev);
drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
38
nvkm_mc_intr_mask(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, bool en)
drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
40
struct nvkm_subdev *subdev = nvkm_device_subdev(device, type, inst);
drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
51
nvkm_mc_reset_mask(struct nvkm_device *device, bool isauto, enum nvkm_subdev_type type, int inst)
drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
57
if (!(pmc_enable = nvkm_top_reset(device, type, inst))) {
drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
60
if (map->type == type && map->inst == inst) {
drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
72
nvkm_mc_reset(struct nvkm_device *device, enum nvkm_subdev_type type, int inst)
drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
74
u64 pmc_enable = nvkm_mc_reset_mask(device, true, type, inst);
drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
82
nvkm_mc_disable(struct nvkm_device *device, enum nvkm_subdev_type type, int inst)
drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
84
u64 pmc_enable = nvkm_mc_reset_mask(device, false, type, inst);
drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
90
nvkm_mc_enable(struct nvkm_device *device, enum nvkm_subdev_type type, int inst)
drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
92
u64 pmc_enable = nvkm_mc_reset_mask(device, false, type, inst);
drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
98
nvkm_mc_enabled(struct nvkm_device *device, enum nvkm_subdev_type type, int inst)
drivers/gpu/drm/nouveau/nvkm/subdev/mc/g84.c
64
g84_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc)
drivers/gpu/drm/nouveau/nvkm/subdev/mc/g84.c
66
return nvkm_mc_new_(&g84_mc, device, type, inst, pmc);
drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c
64
g98_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc)
drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c
66
return nvkm_mc_new_(&g98_mc, device, type, inst, pmc);
drivers/gpu/drm/nouveau/nvkm/subdev/mc/ga100.c
75
ga100_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc)
drivers/gpu/drm/nouveau/nvkm/subdev/mc/ga100.c
80
return nvkm_mc_new_(&ga100_mc, device, type, inst, pmc);
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c
79
gf100_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc)
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c
81
return nvkm_mc_new_(&gf100_mc, device, type, inst, pmc);
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk104.c
63
gk104_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc)
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk104.c
65
return nvkm_mc_new_(&gk104_mc, device, type, inst, pmc);
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c
37
gk20a_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc)
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c
39
return nvkm_mc_new_(&gk20a_mc, device, type, inst, pmc);
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c
101
gp100_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc)
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c
106
return nvkm_mc_new_(&gp100_mc, device, type, inst, pmc);
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.c
45
gp10b_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc)
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.c
47
return nvkm_mc_new_(&gp10b_mc, device, type, inst, pmc);
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gt215.c
91
gt215_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc)
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gt215.c
93
return nvkm_mc_new_(>215_mc, device, type, inst, pmc);
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c
134
nv04_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc)
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c
136
return nvkm_mc_new_(&nv04_mc, device, type, inst, pmc);
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv11.c
46
nv11_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc)
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv11.c
48
return nvkm_mc_new_(&nv11_mc, device, type, inst, pmc);
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv17.c
55
nv17_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc)
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv17.c
57
return nvkm_mc_new_(&nv17_mc, device, type, inst, pmc);
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c
50
nv44_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc)
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c
52
return nvkm_mc_new_(&nv44_mc, device, type, inst, pmc);
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c
57
nv50_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc)
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c
59
return nvkm_mc_new_(&nv50_mc, device, type, inst, pmc);
drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h
13
int inst;
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c
422
enum nvkm_subdev_type type, int inst, struct nvkm_mmu *mmu)
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c
424
nvkm_subdev_ctor(&nvkm_mmu, device, type, inst, &mmu->subdev);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c
435
enum nvkm_subdev_type type, int inst, struct nvkm_mmu **pmmu)
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c
439
nvkm_mmu_ctor(func, device, type, inst, *pmmu);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/g84.c
38
g84_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/g84.c
41
return nvkm_mmu_new_(&g84_mmu, device, type, inst, pmmu);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c
87
gf100_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c
90
return nvkm_mmu_new_(&gf100_mmu, device, type, inst, pmmu);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gh100.c
21
gh100_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gh100.c
24
return r535_mmu_new(&gh100_mmu, device, type, inst, pmmu);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk104.c
38
gk104_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk104.c
41
return nvkm_mmu_new_(&gk104_mmu, device, type, inst, pmmu);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.c
38
gk20a_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.c
41
return nvkm_mmu_new_(&gk20a_mmu, device, type, inst, pmmu);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm200.c
93
gm200_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm200.c
97
return nvkm_mmu_new_(&gm200_mmu_fixed, device, type, inst, pmmu);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm200.c
98
return nvkm_mmu_new_(&gm200_mmu, device, type, inst, pmmu);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm20b.c
50
gm20b_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm20b.c
54
return nvkm_mmu_new_(&gm20b_mmu_fixed, device, type, inst, pmmu);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm20b.c
55
return nvkm_mmu_new_(&gm20b_mmu, device, type, inst, pmmu);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp100.c
40
gp100_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp100.c
44
return gm200_mmu_new(device, type, inst, pmmu);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp100.c
45
return nvkm_mmu_new_(&gp100_mmu, device, type, inst, pmmu);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp10b.c
40
gp10b_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp10b.c
44
return gm20b_mmu_new(device, type, inst, pmmu);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp10b.c
45
return nvkm_mmu_new_(&gp10b_mmu, device, type, inst, pmmu);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gv100.c
40
gv100_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gv100.c
43
return nvkm_mmu_new_(&gv100_mmu, device, type, inst, pmmu);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mcp77.c
38
mcp77_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mcp77.c
41
return nvkm_mmu_new_(&mcp77_mmu, device, type, inst, pmmu);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c
38
nv04_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c
41
return nvkm_mmu_new_(&nv04_mmu, device, type, inst, pmmu);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c
50
nv41_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c
55
return nv04_mmu_new(device, type, inst, pmmu);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c
57
return nvkm_mmu_new_(&nv41_mmu, device, type, inst, pmmu);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c
65
nv44_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c
70
return nv04_mmu_new(device, type, inst, pmmu);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c
72
return nvkm_mmu_new_(&nv44_mmu, device, type, inst, pmmu);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
74
nv50_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
77
return nvkm_mmu_new_(&nv50_mmu, device, type, inst, pmmu);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/tu102.c
55
tu102_mmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/tu102.c
59
return r535_mmu_new(&tu102_mmu, device, type, inst, pmmu);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/tu102.c
61
return nvkm_mmu_new_(&tu102_mmu, device, type, inst, pmmu);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c
1911
nvkm_vmm_part(struct nvkm_vmm *vmm, struct nvkm_memory *inst)
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c
1913
if (inst && vmm && vmm->func->part) {
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c
1915
vmm->func->part(vmm, inst);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c
1921
nvkm_vmm_join(struct nvkm_vmm *vmm, struct nvkm_memory *inst)
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c
1926
ret = vmm->func->join(vmm, inst);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
148
int (*join)(struct nvkm_vmm *, struct nvkm_memory *inst);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
149
void (*part)(struct nvkm_vmm *, struct nvkm_memory *inst);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
168
struct nvkm_memory *inst;
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c
336
gf100_vmm_part(struct nvkm_vmm *vmm, struct nvkm_memory *inst)
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c
338
nvkm_fo64(inst, 0x0200, 0x00000000, 2);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c
342
gf100_vmm_join_(struct nvkm_vmm *vmm, struct nvkm_memory *inst, u64 base)
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c
358
nvkm_kmap(inst);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c
359
nvkm_wo64(inst, 0x0200, base);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c
360
nvkm_wo64(inst, 0x0208, vmm->limit - 1);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c
361
nvkm_done(inst);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c
366
gf100_vmm_join(struct nvkm_vmm *vmm, struct nvkm_memory *inst)
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c
368
return gf100_vmm_join_(vmm, inst, 0);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.c
100
return gf100_vmm_join_(vmm, inst, base);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.c
104
gm200_vmm_join(struct nvkm_vmm *vmm, struct nvkm_memory *inst)
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.c
106
return gm200_vmm_join_(vmm, inst, 0);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.c
96
gm200_vmm_join_(struct nvkm_vmm *vmm, struct nvkm_memory *inst, u64 base)
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
515
aper = (args->v0.inst >> 8) & 3;
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
516
args->v0.inst >>= 12;
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
517
args->v0.inst |= aper << 28;
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
518
args->v0.inst |= 0x80000000;
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
521
if (nvkm_gr_ctxsw_inst(device) == args->v0.inst) {
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
583
gp100_vmm_join(struct nvkm_vmm *vmm, struct nvkm_memory *inst)
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
590
return gf100_vmm_join_(vmm, inst, base);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.c
31
gv100_vmm_join(struct nvkm_vmm *vmm, struct nvkm_memory *inst)
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.c
34
int ret = gp100_vmm_join(vmm, inst), i;
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.c
38
nvkm_kmap(inst);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.c
39
data[0] = nvkm_ro32(inst, 0x200);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.c
40
data[1] = nvkm_ro32(inst, 0x204);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.c
43
nvkm_wo32(inst, 0x21c, 0x00000000);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.c
47
nvkm_wo32(inst, 0x2a4 + (i * 0x10), data[1]);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.c
48
nvkm_wo32(inst, 0x2a0 + (i * 0x10), data[0]);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.c
50
nvkm_wo32(inst, 0x2a4 + (i * 0x10), 0x00000001);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.c
51
nvkm_wo32(inst, 0x2a0 + (i * 0x10), 0x00000001);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.c
53
nvkm_wo32(inst, 0x2a8 + (i * 0x10), 0x00000000);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.c
56
nvkm_wo32(inst, 0x298, lower_32_bits(mask));
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.c
57
nvkm_wo32(inst, 0x29c, upper_32_bits(mask));
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.c
58
nvkm_done(inst);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c
155
nvkm_kmap(join->inst);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c
156
nvkm_wo64(join->inst, pdeo, data);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c
157
nvkm_done(join->inst);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c
327
nv50_vmm_part(struct nvkm_vmm *vmm, struct nvkm_memory *inst)
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c
332
if (join->inst == inst) {
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c
341
nv50_vmm_join(struct nvkm_vmm *vmm, struct nvkm_memory *inst)
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c
351
join->inst = inst;
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c
354
nvkm_kmap(join->inst);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c
360
nvkm_wo64(join->inst, pd_offset + (pdei * 8), data);
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c
362
nvkm_done(join->inst);
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c
233
nvkm_mxm_new_(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c
244
nvkm_subdev_ctor(&nvkm_mxm, device, type, inst, &mxm->subdev);
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c
204
nv50_mxm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c
210
ret = nvkm_mxm_new_(device, type, inst, &mxm);
drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c
161
enum nvkm_subdev_type type, int inst, struct nvkm_pci **ppci)
drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c
167
nvkm_subdev_ctor(&nvkm_pci_func, device, type, inst, &pci->subdev);
drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c
152
g84_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c
155
return nvkm_pci_new_(&g84_pci_func, device, type, inst, ppci);
drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.c
53
g92_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.c
56
return nvkm_pci_new_(&g92_pci_func, device, type, inst, ppci);
drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c
45
g94_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c
48
return nvkm_pci_new_(&g94_pci_func, device, type, inst, ppci);
drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c
101
return nvkm_pci_new_(&gf100_pci_func, device, type, inst, ppci);
drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c
98
gf100_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf106.c
45
gf106_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf106.c
48
return nvkm_pci_new_(&gf106_pci_func, device, type, inst, ppci);
drivers/gpu/drm/nouveau/nvkm/subdev/pci/gh100.c
26
gh100_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/pci/gh100.c
29
return nvkm_pci_new_(&gh100_pci, device, type, inst, ppci);
drivers/gpu/drm/nouveau/nvkm/subdev/pci/gk104.c
224
gk104_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/pci/gk104.c
227
return nvkm_pci_new_(&gk104_pci_func, device, type, inst, ppci);
drivers/gpu/drm/nouveau/nvkm/subdev/pci/gp100.c
39
gp100_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/pci/gp100.c
42
return nvkm_pci_new_(&gp100_pci_func, device, type, inst, ppci);
drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv04.c
32
nv04_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv04.c
35
return nvkm_pci_new_(&nv04_pci_func, device, type, inst, ppci);
drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv40.c
39
nv40_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv40.c
42
return nvkm_pci_new_(&nv40_pci_func, device, type, inst, ppci);
drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.c
46
nv46_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.c
49
return nvkm_pci_new_(&nv46_pci_func, device, type, inst, ppci);
drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv4c.c
32
nv4c_pci_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv4c.c
35
return nvkm_pci_new_(&nv4c_pci_func, device, type, inst, ppci);
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c
127
enum nvkm_subdev_type type, int inst, struct nvkm_pmu *pmu)
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c
131
nvkm_subdev_ctor(&nvkm_pmu, device, type, inst, &pmu->subdev);
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c
161
enum nvkm_subdev_type type, int inst, struct nvkm_pmu **ppmu)
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c
166
return nvkm_pmu_ctor(fwif, device, type, inst, *ppmu);
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c
72
gf100_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c
75
return nvkm_pmu_new_(gf100_pmu_fwif, device, type, inst, ppmu);
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.c
50
gf119_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.c
53
return nvkm_pmu_new_(gf119_pmu_fwif, device, type, inst, ppmu);
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c
130
gk104_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c
133
return nvkm_pmu_new_(gk104_pmu_fwif, device, type, inst, ppmu);
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c
109
gk110_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c
112
return nvkm_pmu_new_(gk110_pmu_fwif, device, type, inst, ppmu);
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c
51
gk208_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c
54
return nvkm_pmu_new_(gk208_pmu_fwif, device, type, inst, ppmu);
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c
212
gk20a_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c
222
ret = nvkm_pmu_ctor(gk20a_pmu_fwif, device, type, inst, &pmu->base);
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c
52
gm107_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c
55
return nvkm_pmu_new_(gm107_pmu_fwif, device, type, inst, ppmu);
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c
81
gm200_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c
84
return nvkm_pmu_new_(gm200_pmu_fwif, device, type, inst, ppmu);
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c
266
gm20b_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c
269
return nvkm_pmu_new_(gm20b_pmu_fwif, device, type, inst, ppmu);
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c
56
gp102_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c
62
return nvkm_pmu_new_(gp102_pmu_fwif, device, type, inst, ppmu);
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c
92
gp10b_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c
95
return nvkm_pmu_new_(gp10b_pmu_fwif, device, type, inst, ppmu);
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c
290
gt215_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c
293
return nvkm_pmu_new_(gt215_pmu_fwif, device, type, inst, ppmu);
drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf100.c
118
gf100_privring_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf100.c
121
return nvkm_subdev_new_(&gf100_privring, device, type, inst, pprivring);
drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf117.c
43
gf117_privring_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf117.c
46
return nvkm_subdev_new_(&gf117_privring, device, type, inst, pprivring);
drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk104.c
121
gk104_privring_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk104.c
124
return nvkm_subdev_new_(&gk104_privring, device, type, inst, pprivring);
drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk20a.c
81
gk20a_privring_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk20a.c
84
return nvkm_subdev_new_(&gk20a_privring, device, type, inst, pprivring);
drivers/gpu/drm/nouveau/nvkm/subdev/privring/gm200.c
34
gm200_privring_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/privring/gm200.c
40
return nvkm_subdev_new_(&gm200_privring, device, type, inst, pprivring);
drivers/gpu/drm/nouveau/nvkm/subdev/privring/gp10b.c
51
gp10b_privring_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/privring/gp10b.c
54
return nvkm_subdev_new_(&gp10b_privring, device, type, inst, pprivring);
drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
425
int inst, const struct nvkm_therm_func *func)
drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
427
nvkm_subdev_ctor(&nvkm_therm, device, type, inst, &therm->subdev);
drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
446
enum nvkm_subdev_type type, int inst, struct nvkm_therm **ptherm)
drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
453
nvkm_therm_ctor(therm, device, type, inst, func);
drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c
226
g84_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c
232
ret = nvkm_therm_new_(&g84_therm, device, type, inst, &therm);
drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.c
150
gf119_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.c
153
return nvkm_therm_new_(&gf119_therm, device, type, inst, ptherm);
drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c
110
enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c
120
nvkm_therm_ctor(&therm->base, device, type, inst, func);
drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c
128
gk104_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_therm **ptherm)
drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c
130
return gk104_therm_new_(&gk104_therm_func, device, type, inst,
drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c
39
if (!nvkm_device_subdev(dev, order[i].type, order[i].inst))
drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c
51
if (!nvkm_device_subdev(dev, order[i].type, order[i].inst))
drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c
68
if (!nvkm_device_subdev(dev, order[i].type, order[i].inst))
drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.h
35
int inst;
drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c
71
gm107_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c
74
return nvkm_therm_new_(&gm107_therm, device, type, inst, ptherm);
drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm200.c
35
gm200_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm200.c
38
return nvkm_therm_new_(&gm200_therm, device, type, inst, ptherm);
drivers/gpu/drm/nouveau/nvkm/subdev/therm/gp100.c
54
gp100_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/therm/gp100.c
60
return nvkm_therm_new_(&gp100_therm, device, type, inst, ptherm);
drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c
71
gt215_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c
74
return nvkm_therm_new_(>215_therm, device, type, inst, ptherm);
drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c
200
nv40_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c
203
return nvkm_therm_new_(&nv40_therm, device, type, inst, ptherm);
drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c
172
nv50_therm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c
175
return nvkm_therm_new_(&nv50_therm, device, type, inst, ptherm);
drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c
186
enum nvkm_subdev_type type, int inst, struct nvkm_timer **ptmr)
drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c
193
nvkm_subdev_ctor(&nvkm_timer, device, type, inst, &tmr->subdev);
drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c
36
gk20a_timer_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c
39
return nvkm_timer_new_(&gk20a_timer, device, type, inst, ptmr);
drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c
148
nv04_timer_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c
151
return nvkm_timer_new_(&nv04_timer, device, type, inst, ptmr);
drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c
85
nv40_timer_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c
88
return nvkm_timer_new_(&nv40_timer, device, type, inst, ptmr);
drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.c
82
nv41_timer_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.c
85
return nvkm_timer_new_(&nv41_timer, device, type, inst, ptmr);
drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c
114
return nvkm_device_subdev(device, info->type, info->inst);
drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c
152
enum nvkm_subdev_type type, int inst, struct nvkm_top **ptop)
drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c
157
nvkm_subdev_ctor(&nvkm_top, device, type, inst, &top->subdev);
drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c
32
info->inst = -1;
drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c
45
nvkm_top_addr(struct nvkm_device *device, enum nvkm_subdev_type type, int inst)
drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c
52
if (info->type == type && info->inst == inst)
drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c
61
nvkm_top_reset(struct nvkm_device *device, enum nvkm_subdev_type type, int inst)
drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c
68
if (info->type == type && info->inst == inst && info->reset >= 0)
drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c
77
nvkm_top_intr_mask(struct nvkm_device *device, enum nvkm_subdev_type type, int inst)
drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c
84
if (info->type == type && info->inst == inst && info->intr >= 0)
drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c
93
nvkm_top_fault_id(struct nvkm_device *device, enum nvkm_subdev_type type, int inst)
drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c
99
if (info->type == type && info->inst == inst && info->fault >= 0)
drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.c
106
ga100_top_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.c
112
return nvkm_top_new_(&ga100_top, device, type, inst, ptop);
drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.c
32
u32 data, type, inst;
drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.c
40
inst = 0;
drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.c
51
inst = (data & 0x000f0000) >> 16;
drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.c
71
#define I_(T,I) do { info->type = (T); info->inst = (I); } while(0)
drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.c
72
#define O_(T,I) do { WARN_ON(inst); I_(T, I); } while (0)
drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.c
76
case 0x0000000e: I_(NVKM_ENGINE_NVENC , inst); break;
drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.c
77
case 0x00000010: I_(NVKM_ENGINE_NVDEC , inst); break;
drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.c
78
case 0x00000012: I_(NVKM_SUBDEV_IOCTRL, inst); break;
drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.c
79
case 0x00000013: I_(NVKM_ENGINE_CE , inst); break;
drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.c
81
case 0x00000015: I_(NVKM_ENGINE_NVJPG , inst); break;
drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.c
90
"runlist %6x engine %2d reset %2d\n", type, inst,
drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c
101
"reset %2d\n", type, inst,
drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c
117
gk104_top_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c
123
return nvkm_top_new_(&gk104_top, device, type, inst, ptop);
drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c
34
u32 data, type, inst;
drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c
42
inst = 0;
drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c
51
inst = (data & 0x3c000000) >> 26;
drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c
75
#define I_(T,I) do { info->type = (T); info->inst = (I); } while(0)
drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c
76
#define O_(T,I) do { WARN_ON(inst); I_(T, I); } while (0)
drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c
88
case 0x0000000e: I_(NVKM_ENGINE_NVENC , inst); break;
drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c
90
case 0x00000010: I_(NVKM_ENGINE_NVDEC , inst); break;
drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c
91
case 0x00000012: I_(NVKM_SUBDEV_IOCTRL, inst); break;
drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c
92
case 0x00000013: I_(NVKM_ENGINE_CE , inst); break;
drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c
94
case 0x00000015: I_(NVKM_ENGINE_NVJPG , inst); break;
drivers/gpu/drm/nouveau/nvkm/subdev/vfn/base.c
37
enum nvkm_subdev_type type, int inst, u32 addr, struct nvkm_vfn **pvfn)
drivers/gpu/drm/nouveau/nvkm/subdev/vfn/base.c
45
nvkm_subdev_ctor(&nvkm_vfn, device, type, inst, &vfn->subdev);
drivers/gpu/drm/nouveau/nvkm/subdev/vfn/ga100.c
46
enum nvkm_subdev_type type, int inst, struct nvkm_vfn **pvfn)
drivers/gpu/drm/nouveau/nvkm/subdev/vfn/ga100.c
49
return r535_vfn_new(&ga100_vfn, device, type, inst, 0xb80000, pvfn);
drivers/gpu/drm/nouveau/nvkm/subdev/vfn/ga100.c
51
return nvkm_vfn_new_(&ga100_vfn, device, type, inst, 0xb80000, pvfn);
drivers/gpu/drm/nouveau/nvkm/subdev/vfn/gv100.c
33
enum nvkm_subdev_type type, int inst, struct nvkm_vfn **pvfn)
drivers/gpu/drm/nouveau/nvkm/subdev/vfn/gv100.c
35
return nvkm_vfn_new_(&gv100_vfn, device, type, inst, 0, pvfn);
drivers/gpu/drm/nouveau/nvkm/subdev/vfn/r535.c
34
struct nvkm_device *device, enum nvkm_subdev_type type, int inst, u32 addr,
drivers/gpu/drm/nouveau/nvkm/subdev/vfn/r535.c
52
ret = nvkm_vfn_new_(rm, device, type, inst, addr, pvfn);
drivers/gpu/drm/nouveau/nvkm/subdev/vfn/tu102.c
107
enum nvkm_subdev_type type, int inst, struct nvkm_vfn **pvfn)
drivers/gpu/drm/nouveau/nvkm/subdev/vfn/tu102.c
110
return r535_vfn_new(&tu102_vfn, device, type, inst, 0xb80000, pvfn);
drivers/gpu/drm/nouveau/nvkm/subdev/vfn/tu102.c
112
return nvkm_vfn_new_(&tu102_vfn, device, type, inst, 0xb80000, pvfn);
drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c
284
enum nvkm_subdev_type type, int inst, struct nvkm_volt *volt)
drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c
289
nvkm_subdev_ctor(&nvkm_volt, device, type, inst, &volt->subdev);
drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c
322
enum nvkm_subdev_type type, int inst, struct nvkm_volt **pvolt)
drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c
326
nvkm_volt_ctor(func, device, type, inst, *pvolt);
drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf100.c
59
gf100_volt_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf100.c
65
ret = nvkm_volt_new_(&gf100_volt, device, type, inst, &volt);
drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf117.c
49
gf117_volt_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf117.c
55
ret = nvkm_volt_new_(&gf117_volt, device, type, inst, &volt);
drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c
118
nvkm_volt_ctor(volt_func, device, type, inst, &volt->base);
drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c
98
gk104_volt_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c
147
gk20a_volt_ctor(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c
154
nvkm_volt_ctor(&gk20a_volt, device, type, inst, &volt->base);
drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c
175
gk20a_volt_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_volt **pvolt)
drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c
184
return gk20a_volt_ctor(device, type, inst, gk20a_cvb_coef,
drivers/gpu/drm/nouveau/nvkm/subdev/volt/gm20b.c
67
gm20b_volt_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/volt/gm20b.c
88
return gk20a_volt_ctor(device, type, inst, gm20b_na_cvb_coef,
drivers/gpu/drm/nouveau/nvkm/subdev/volt/gm20b.c
91
return gk20a_volt_ctor(device, type, inst, gm20b_cvb_coef,
drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.c
33
nv40_volt_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.c
39
ret = nvkm_volt_new_(&nv40_volt, device, type, inst, &volt);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
118
raddr_add_a_to_live_reg_index(uint64_t inst)
drivers/gpu/drm/vc4/vc4_validate_shaders.c
120
uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
121
uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
122
uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
123
uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
189
uint64_t inst = validation_state->shader[validation_state->ip];
drivers/gpu/drm/vc4/vc4_validate_shaders.c
191
QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
drivers/gpu/drm/vc4/vc4_validate_shaders.c
192
QPU_GET_FIELD(inst, QPU_WADDR_ADD));
drivers/gpu/drm/vc4/vc4_validate_shaders.c
193
uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
194
uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
198
uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
201
uint32_t add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
213
QPU_GET_FIELD(inst, QPU_OP_ADD) != QPU_A_ADD) {
drivers/gpu/drm/vc4/vc4_validate_shaders.c
223
clamp_reg = raddr_add_a_to_live_reg_index(inst);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
314
uint64_t inst = validation_state->shader[validation_state->ip];
drivers/gpu/drm/vc4/vc4_validate_shaders.c
315
u32 add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
316
u32 raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
317
u32 raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
318
u32 add_lri = raddr_add_a_to_live_reg_index(inst);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
334
switch (QPU_GET_FIELD(inst, QPU_SIG)) {
drivers/gpu/drm/vc4/vc4_validate_shaders.c
347
if (is_mul || QPU_GET_FIELD(inst, QPU_OP_ADD) != QPU_A_ADD) {
drivers/gpu/drm/vc4/vc4_validate_shaders.c
352
if (QPU_GET_FIELD(inst, QPU_COND_ADD) != QPU_COND_ALWAYS) {
drivers/gpu/drm/vc4/vc4_validate_shaders.c
357
if (QPU_GET_FIELD(inst, QPU_PACK) != QPU_PACK_A_NOP &&
drivers/gpu/drm/vc4/vc4_validate_shaders.c
358
!(inst & QPU_PM)) {
drivers/gpu/drm/vc4/vc4_validate_shaders.c
393
uint64_t inst = validation_state->shader[validation_state->ip];
drivers/gpu/drm/vc4/vc4_validate_shaders.c
395
QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
drivers/gpu/drm/vc4/vc4_validate_shaders.c
396
QPU_GET_FIELD(inst, QPU_WADDR_ADD));
drivers/gpu/drm/vc4/vc4_validate_shaders.c
397
uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
398
bool ws = inst & QPU_WS;
drivers/gpu/drm/vc4/vc4_validate_shaders.c
403
uint32_t cond_add = QPU_GET_FIELD(inst, QPU_COND_ADD);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
404
uint32_t cond_mul = QPU_GET_FIELD(inst, QPU_COND_MUL);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
407
QPU_GET_FIELD(inst, QPU_PACK) == QPU_PACK_A_NOP &&
drivers/gpu/drm/vc4/vc4_validate_shaders.c
411
QPU_GET_FIELD(inst, QPU_LOAD_IMM);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
484
uint64_t inst = validation_state->shader[validation_state->ip];
drivers/gpu/drm/vc4/vc4_validate_shaders.c
485
uint32_t op_add = QPU_GET_FIELD(inst, QPU_OP_ADD);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
486
uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
487
uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
488
uint32_t cond_add = QPU_GET_FIELD(inst, QPU_COND_ADD);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
489
uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
490
uint32_t add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
491
uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
492
uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
493
uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
494
bool ws = inst & QPU_WS;
drivers/gpu/drm/vc4/vc4_validate_shaders.c
501
lri_add_a = raddr_add_a_to_live_reg_index(inst);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
559
uint64_t inst = validation_state->shader[validation_state->ip];
drivers/gpu/drm/vc4/vc4_validate_shaders.c
560
uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
561
uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
578
check_branch(uint64_t inst,
drivers/gpu/drm/vc4/vc4_validate_shaders.c
583
int32_t branch_imm = QPU_GET_FIELD(inst, QPU_BRANCH_TARGET);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
584
uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
585
uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
606
uint64_t inst = validation_state->shader[validation_state->ip];
drivers/gpu/drm/vc4/vc4_validate_shaders.c
607
uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
608
uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
609
uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
645
uint64_t inst = validation_state->shader[ip];
drivers/gpu/drm/vc4/vc4_validate_shaders.c
646
int32_t branch_imm = QPU_GET_FIELD(inst, QPU_BRANCH_TARGET);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
647
uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
671
if (inst & QPU_BRANCH_REG) {
drivers/gpu/drm/vc4/vc4_validate_shaders.c
677
if (!(inst & QPU_BRANCH_REL)) {
drivers/gpu/drm/vc4/vc4_validate_shaders.c
687
if (branch_imm % sizeof(inst) != 0) {
drivers/gpu/drm/vc4/vc4_validate_shaders.c
815
uint64_t inst = validation_state.shader[ip];
drivers/gpu/drm/vc4/vc4_validate_shaders.c
816
uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
drivers/gpu/drm/vc4/vc4_validate_shaders.c
883
if (!check_branch(inst, validated_shader,
drivers/gpu/drm/xe/xe_memirq.c
156
#define XE_MEMIRQ_STATUS_OFFSET(inst) ((inst) * SZ_4K + 0x0)
drivers/gpu/drm/xe/xe_memirq.c
158
#define XE_MEMIRQ_SOURCE_OFFSET(inst) ((inst) * SZ_4K + 0x400)
drivers/iio/adc/ad4134.c
134
static int ad4134_calc_spi_crc(u8 inst, u8 data)
drivers/iio/adc/ad4134.c
136
u8 buf[] = { inst, data };
drivers/iio/adc/ad4134.c
142
static void ad4134_prepare_spi_tx_buf(u8 inst, u8 data, u8 *buf)
drivers/iio/adc/ad4134.c
144
buf[0] = inst;
drivers/iio/adc/ad4134.c
146
buf[2] = ad4134_calc_spi_crc(inst, data);
drivers/iio/adc/ad4134.c
213
unsigned int inst;
drivers/iio/adc/ad4134.c
216
inst = AD4134_REG_READ_MASK | reg;
drivers/iio/adc/ad4134.c
217
ad4134_prepare_spi_tx_buf(inst, 0, st->tx_buf);
drivers/iio/common/ssp_sensors/ssp.h
231
int ssp_send_instruction(struct ssp_data *data, u8 inst, u8 sensor_type,
drivers/iio/common/ssp_sensors/ssp_spi.c
479
int ssp_send_instruction(struct ssp_data *data, u8 inst, u8 sensor_type,
drivers/iio/common/ssp_sensors/ssp_spi.c
490
(inst <= SSP_MSG2SSP_INST_CHANGE_DELAY)) {
drivers/iio/common/ssp_sensors/ssp_spi.c
496
msg = ssp_create_msg(inst, length + 2, SSP_AP2HUB_WRITE, 0);
drivers/iio/common/ssp_sensors/ssp_spi.c
504
__func__, inst, sensor_type, send_buf[1]);
drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
152
int inst)
drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
155
void __iomem *gr0_base = nvidia_smmu_page(smmu, inst, 0);
drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
177
unsigned int inst;
drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
182
for (inst = 0; inst < nvidia->num_instances; inst++) {
drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
185
irq_ret = nvidia_smmu_global_fault_inst(irq, smmu, inst);
drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
195
int idx, int inst)
drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
199
void __iomem *gr1_base = nvidia_smmu_page(smmu, inst, 1);
drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
200
void __iomem *cb_base = nvidia_smmu_page(smmu, inst, smmu->numpage + idx);
drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
221
unsigned int inst;
drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
230
for (inst = 0; inst < nvidia->num_instances; inst++) {
drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
239
idx, inst);
drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
47
unsigned int inst, int page)
drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
52
return nvidia_smmu->bases[inst] + (page << smmu->pgshift);
drivers/mailbox/mailbox-sti.c
34
#define MBOX_BASE(mdev, inst) ((mdev)->base + ((inst) * 4))
drivers/mailbox/ti-msgmgr.c
246
struct ti_msgmgr_inst *inst = dev_get_drvdata(dev);
drivers/mailbox/ti-msgmgr.c
248
const struct ti_msgmgr_desc *desc = inst->desc;
drivers/mailbox/ti-msgmgr.c
276
struct ti_msgmgr_inst *inst = dev_get_drvdata(dev);
drivers/mailbox/ti-msgmgr.c
281
if (WARN_ON(!inst)) {
drivers/mailbox/ti-msgmgr.c
293
desc = inst->desc;
drivers/mailbox/ti-msgmgr.c
322
struct ti_msgmgr_inst *inst = dev_get_drvdata(dev);
drivers/mailbox/ti-msgmgr.c
323
const struct ti_msgmgr_desc *desc = inst->desc;
drivers/mailbox/ti-msgmgr.c
349
struct ti_msgmgr_inst *inst = dev_get_drvdata(dev);
drivers/mailbox/ti-msgmgr.c
350
const struct ti_msgmgr_desc *desc = inst->desc;
drivers/mailbox/ti-msgmgr.c
393
struct ti_msgmgr_inst *inst = dev_get_drvdata(dev);
drivers/mailbox/ti-msgmgr.c
402
if (WARN_ON(!inst)) {
drivers/mailbox/ti-msgmgr.c
406
desc = inst->desc;
drivers/mailbox/ti-msgmgr.c
512
struct ti_msgmgr_inst *inst = dev_get_drvdata(dev);
drivers/mailbox/ti-msgmgr.c
514
const struct ti_msgmgr_desc *d = inst->desc;
drivers/mailbox/ti-msgmgr.c
576
struct ti_msgmgr_inst *inst;
drivers/mailbox/ti-msgmgr.c
582
inst = container_of(mbox, struct ti_msgmgr_inst, mbox);
drivers/mailbox/ti-msgmgr.c
583
if (WARN_ON(!inst))
drivers/mailbox/ti-msgmgr.c
586
d = inst->desc;
drivers/mailbox/ti-msgmgr.c
593
dev_err(inst->dev, "Invalid arguments in dt[%d]. Must be %d\n",
drivers/mailbox/ti-msgmgr.c
608
qinst = &inst->qinsts[req_pid];
drivers/mailbox/ti-msgmgr.c
612
for (qinst = inst->qinsts, i = 0; i < inst->num_valid_queues;
drivers/mailbox/ti-msgmgr.c
619
dev_err(inst->dev, "Queue ID %d, Proxy ID %d is wrong on %pOFn\n",
drivers/mailbox/ti-msgmgr.c
639
struct ti_msgmgr_inst *inst,
drivers/mailbox/ti-msgmgr.c
657
qinst->queue_buff_start = inst->queue_proxy_region +
drivers/mailbox/ti-msgmgr.c
660
qinst->queue_buff_end = inst->queue_proxy_region +
drivers/mailbox/ti-msgmgr.c
663
qinst->queue_state = inst->queue_state_debug_region +
drivers/mailbox/ti-msgmgr.c
665
qinst->queue_ctrl = inst->queue_ctrl_region +
drivers/mailbox/ti-msgmgr.c
673
qinst->queue_buff_start = inst->queue_proxy_region +
drivers/mailbox/ti-msgmgr.c
676
qinst->queue_buff_end = inst->queue_proxy_region +
drivers/mailbox/ti-msgmgr.c
680
inst->queue_state_debug_region +
drivers/mailbox/ti-msgmgr.c
716
struct ti_msgmgr_inst *inst = dev_get_drvdata(dev);
drivers/mailbox/ti-msgmgr.c
725
for (qinst = inst->qinsts, i = 0; i < inst->num_valid_queues; qinst++, i++) {
drivers/mailbox/ti-msgmgr.c
735
struct ti_msgmgr_inst *inst = dev_get_drvdata(dev);
drivers/mailbox/ti-msgmgr.c
739
for (qinst = inst->qinsts, i = 0; i < inst->num_valid_queues; qinst++, i++) {
drivers/mailbox/ti-msgmgr.c
815
struct ti_msgmgr_inst *inst;
drivers/mailbox/ti-msgmgr.c
830
inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL);
drivers/mailbox/ti-msgmgr.c
831
if (!inst)
drivers/mailbox/ti-msgmgr.c
834
inst->dev = dev;
drivers/mailbox/ti-msgmgr.c
835
inst->desc = desc = device_get_match_data(dev);
drivers/mailbox/ti-msgmgr.c
837
inst->queue_proxy_region =
drivers/mailbox/ti-msgmgr.c
839
if (IS_ERR(inst->queue_proxy_region))
drivers/mailbox/ti-msgmgr.c
840
return PTR_ERR(inst->queue_proxy_region);
drivers/mailbox/ti-msgmgr.c
842
inst->queue_state_debug_region =
drivers/mailbox/ti-msgmgr.c
844
if (IS_ERR(inst->queue_state_debug_region))
drivers/mailbox/ti-msgmgr.c
845
return PTR_ERR(inst->queue_state_debug_region);
drivers/mailbox/ti-msgmgr.c
848
inst->queue_ctrl_region =
drivers/mailbox/ti-msgmgr.c
850
if (IS_ERR(inst->queue_ctrl_region))
drivers/mailbox/ti-msgmgr.c
851
return PTR_ERR(inst->queue_ctrl_region);
drivers/mailbox/ti-msgmgr.c
855
inst->queue_proxy_region, inst->queue_state_debug_region);
drivers/mailbox/ti-msgmgr.c
863
inst->num_valid_queues = queue_count;
drivers/mailbox/ti-msgmgr.c
868
inst->qinsts = qinst;
drivers/mailbox/ti-msgmgr.c
873
inst->chans = chans;
drivers/mailbox/ti-msgmgr.c
882
ret = ti_msgmgr_queue_setup(i, dev, np, inst,
drivers/mailbox/ti-msgmgr.c
892
ret = ti_msgmgr_queue_setup(i, dev, np, inst,
drivers/mailbox/ti-msgmgr.c
900
mbox = &inst->mbox;
drivers/mailbox/ti-msgmgr.c
903
mbox->chans = inst->chans;
drivers/mailbox/ti-msgmgr.c
904
mbox->num_chans = inst->num_valid_queues;
drivers/mailbox/ti-msgmgr.c
911
platform_set_drvdata(pdev, inst);
drivers/mcb/mcb-core.c
238
bus->bus_nr, device_id, dev->inst, dev->group, dev->var);
drivers/mcb/mcb-internal.h
107
unsigned int inst:6;
drivers/mcb/mcb-parse.c
59
mdev->inst = GDD_INS(reg2);
drivers/media/pci/saa7164/saa7164-core.c
716
dev->fw_status.inst = saa7164_readl(SAA_DEVICE_SYSINIT_INST);
drivers/media/pci/saa7164/saa7164-core.c
725
dprintk(1, " .inst = 0x%08x\n", s->inst);
drivers/media/pci/saa7164/saa7164.h
227
u32 inst;
drivers/media/platform/amphion/vdec.c
1003
f.type = inst->cap_format.type;
drivers/media/platform/amphion/vdec.c
1011
vpu_try_fmt_common(inst, &f, &inst->cap_format);
drivers/media/platform/amphion/vdec.c
1013
inst->out_format.width = vdec->codec_info.width;
drivers/media/platform/amphion/vdec.c
1014
inst->out_format.height = vdec->codec_info.height;
drivers/media/platform/amphion/vdec.c
1017
static void vdec_init_crop(struct vpu_inst *inst)
drivers/media/platform/amphion/vdec.c
1019
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
1021
inst->crop.left = vdec->codec_info.offset_x;
drivers/media/platform/amphion/vdec.c
1022
inst->crop.top = vdec->codec_info.offset_y;
drivers/media/platform/amphion/vdec.c
1023
inst->crop.width = vdec->codec_info.width;
drivers/media/platform/amphion/vdec.c
1024
inst->crop.height = vdec->codec_info.height;
drivers/media/platform/amphion/vdec.c
1027
static void vdec_init_mbi(struct vpu_inst *inst)
drivers/media/platform/amphion/vdec.c
1029
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
1038
static void vdec_init_dcp(struct vpu_inst *inst)
drivers/media/platform/amphion/vdec.c
1040
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
1056
static int vdec_alloc_fs_buffer(struct vpu_inst *inst, struct vdec_fs_info *fs)
drivers/media/platform/amphion/vdec.c
1072
return vpu_alloc_dma(inst->core, buffer);
drivers/media/platform/amphion/vdec.c
1075
static void vdec_alloc_fs(struct vpu_inst *inst, struct vdec_fs_info *fs)
drivers/media/platform/amphion/vdec.c
1080
ret = vdec_alloc_fs_buffer(inst, fs);
drivers/media/platform/amphion/vdec.c
1099
static int vdec_response_fs(struct vpu_inst *inst, struct vdec_fs_info *fs)
drivers/media/platform/amphion/vdec.c
1113
ret = vpu_session_alloc_fs(inst, &info);
drivers/media/platform/amphion/vdec.c
1121
static int vdec_response_frame_abnormal(struct vpu_inst *inst)
drivers/media/platform/amphion/vdec.c
1123
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
1133
ret = vpu_session_alloc_fs(inst, &info);
drivers/media/platform/amphion/vdec.c
1141
static int vdec_response_frame(struct vpu_inst *inst, struct vb2_v4l2_buffer *vbuf)
drivers/media/platform/amphion/vdec.c
1143
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
1148
if (inst->state != VPU_CODEC_STATE_ACTIVE)
drivers/media/platform/amphion/vdec.c
1162
dev_err(inst->dev, "invalid fs %d for v4l2 buffer %d\n",
drivers/media/platform/amphion/vdec.c
1174
dev_err(inst->dev, "[%d] repeat alloc fs %d (v4l2 index %d)\n",
drivers/media/platform/amphion/vdec.c
1175
inst->id, vpu_buf->fs_id, vbuf->vb2_buf.index);
drivers/media/platform/amphion/vdec.c
1179
dev_dbg(inst->dev, "[%d] state = %s, alloc fs %d, tag = 0x%x\n",
drivers/media/platform/amphion/vdec.c
1180
inst->id, vpu_codec_state_name(inst->state), vbuf->vb2_buf.index, vdec->seq_tag);
drivers/media/platform/amphion/vdec.c
1187
info.luma_size = inst->cap_format.sizeimage[0];
drivers/media/platform/amphion/vdec.c
1192
info.chromau_size = inst->cap_format.sizeimage[1];
drivers/media/platform/amphion/vdec.c
1193
info.bytesperline = inst->cap_format.bytesperline[0];
drivers/media/platform/amphion/vdec.c
1194
ret = vpu_session_alloc_fs(inst, &info);
drivers/media/platform/amphion/vdec.c
1210
static void vdec_response_fs_request(struct vpu_inst *inst, bool force)
drivers/media/platform/amphion/vdec.c
1212
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
1218
vdec_response_frame_abnormal(inst);
drivers/media/platform/amphion/vdec.c
1223
ret = vpu_process_capture_buffer(inst);
drivers/media/platform/amphion/vdec.c
1231
if (vdec_response_fs(inst, &vdec->mbi))
drivers/media/platform/amphion/vdec.c
1237
if (vdec_response_fs(inst, &vdec->dcp))
drivers/media/platform/amphion/vdec.c
1244
static void vdec_response_fs_release(struct vpu_inst *inst, u32 id, u32 tag)
drivers/media/platform/amphion/vdec.c
1251
vpu_session_release_fs(inst, &info);
drivers/media/platform/amphion/vdec.c
1254
static void vdec_recycle_buffer(struct vpu_inst *inst, struct vb2_v4l2_buffer *vbuf)
drivers/media/platform/amphion/vdec.c
1256
if (!inst->fh.m2m_ctx)
drivers/media/platform/amphion/vdec.c
1260
if (vpu_find_buf_by_idx(inst, vbuf->vb2_buf.type, vbuf->vb2_buf.index))
drivers/media/platform/amphion/vdec.c
1262
v4l2_m2m_buf_queue(inst->fh.m2m_ctx, vbuf);
drivers/media/platform/amphion/vdec.c
1265
static void vdec_release_curr_frame_store(struct vpu_inst *inst, u32 id)
drivers/media/platform/amphion/vdec.c
1267
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
1279
vdec_response_fs_release(inst, id, vdec->slots[id].tag);
drivers/media/platform/amphion/vdec.c
1282
vdec_recycle_buffer(inst, vbuf);
drivers/media/platform/amphion/vdec.c
1295
static void vdec_clear_slots(struct vpu_inst *inst)
drivers/media/platform/amphion/vdec.c
1297
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
1304
vpu_trace(inst->dev, "clear slot %d\n", i);
drivers/media/platform/amphion/vdec.c
1305
vdec_release_curr_frame_store(inst, i);
drivers/media/platform/amphion/vdec.c
1309
static void vdec_update_v4l2_ctrl(struct vpu_inst *inst, u32 id, u32 val)
drivers/media/platform/amphion/vdec.c
1311
struct v4l2_ctrl *ctrl = v4l2_ctrl_find(&inst->ctrl_handler, id);
drivers/media/platform/amphion/vdec.c
1317
static void vdec_update_v4l2_profile_level(struct vpu_inst *inst, struct vpu_dec_codec_info *hdr)
drivers/media/platform/amphion/vdec.c
1319
switch (inst->out_format.pixfmt) {
drivers/media/platform/amphion/vdec.c
1322
vdec_update_v4l2_ctrl(inst, V4L2_CID_MPEG_VIDEO_H264_PROFILE,
drivers/media/platform/amphion/vdec.c
1324
vdec_update_v4l2_ctrl(inst, V4L2_CID_MPEG_VIDEO_H264_LEVEL,
drivers/media/platform/amphion/vdec.c
1328
vdec_update_v4l2_ctrl(inst, V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
drivers/media/platform/amphion/vdec.c
1330
vdec_update_v4l2_ctrl(inst, V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
drivers/media/platform/amphion/vdec.c
1338
static void vdec_event_seq_hdr(struct vpu_inst *inst, struct vpu_dec_codec_info *hdr)
drivers/media/platform/amphion/vdec.c
1340
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
1342
vpu_inst_lock(inst);
drivers/media/platform/amphion/vdec.c
1344
vpu_trace(inst->dev,
drivers/media/platform/amphion/vdec.c
1346
inst->id,
drivers/media/platform/amphion/vdec.c
1359
inst->min_buffer_cap = hdr->num_ref_frms + hdr->num_dpb_frms;
drivers/media/platform/amphion/vdec.c
1360
vdec->is_source_changed = vdec_check_source_change(inst, hdr);
drivers/media/platform/amphion/vdec.c
1362
vdec_init_fmt(inst);
drivers/media/platform/amphion/vdec.c
1363
vdec_init_crop(inst);
drivers/media/platform/amphion/vdec.c
1364
vdec_init_mbi(inst);
drivers/media/platform/amphion/vdec.c
1365
vdec_init_dcp(inst);
drivers/media/platform/amphion/vdec.c
1366
vdec_update_v4l2_profile_level(inst, hdr);
drivers/media/platform/amphion/vdec.c
1370
vdec_update_state(inst, VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE, 0);
drivers/media/platform/amphion/vdec.c
1372
vdec_handle_resolution_change(inst);
drivers/media/platform/amphion/vdec.c
1377
vdec_response_fs_request(inst, true);
drivers/media/platform/amphion/vdec.c
1378
vpu_trace(inst->dev, "[%d] seq tag change: %d -> %d\n",
drivers/media/platform/amphion/vdec.c
1379
inst->id, vdec->seq_tag, vdec->codec_info.tag);
drivers/media/platform/amphion/vdec.c
1383
vpu_inst_unlock(inst);
drivers/media/platform/amphion/vdec.c
1386
static void vdec_event_resolution_change(struct vpu_inst *inst)
drivers/media/platform/amphion/vdec.c
1388
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
1390
vpu_trace(inst->dev, "[%d] input : %d, decoded : %d, display : %d, sequence : %d\n",
drivers/media/platform/amphion/vdec.c
1391
inst->id,
drivers/media/platform/amphion/vdec.c
1396
vpu_inst_lock(inst);
drivers/media/platform/amphion/vdec.c
1400
vdec_clear_slots(inst);
drivers/media/platform/amphion/vdec.c
1401
vdec_init_mbi(inst);
drivers/media/platform/amphion/vdec.c
1402
vdec_init_dcp(inst);
drivers/media/platform/amphion/vdec.c
1404
vdec_update_state(inst, VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE, 0);
drivers/media/platform/amphion/vdec.c
1406
vdec_handle_resolution_change(inst);
drivers/media/platform/amphion/vdec.c
1409
vpu_inst_unlock(inst);
drivers/media/platform/amphion/vdec.c
1412
static void vdec_event_req_fs(struct vpu_inst *inst, struct vpu_fs_info *fs)
drivers/media/platform/amphion/vdec.c
1414
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
1419
vpu_inst_lock(inst);
drivers/media/platform/amphion/vdec.c
1435
vdec_alloc_fs(inst, &vdec->mbi);
drivers/media/platform/amphion/vdec.c
1436
vdec_alloc_fs(inst, &vdec->dcp);
drivers/media/platform/amphion/vdec.c
1438
vdec_response_fs_request(inst, false);
drivers/media/platform/amphion/vdec.c
1440
vpu_inst_unlock(inst);
drivers/media/platform/amphion/vdec.c
1443
static void vdec_evnet_rel_fs(struct vpu_inst *inst, struct vpu_fs_info *fs)
drivers/media/platform/amphion/vdec.c
1445
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
1453
dev_err(inst->dev, "[%d] invalid fs(%d) to release\n", inst->id, fs->id);
drivers/media/platform/amphion/vdec.c
1457
vpu_inst_lock(inst);
drivers/media/platform/amphion/vdec.c
1459
dev_dbg(inst->dev, "[%d] fs[%d] has bee released\n", inst->id, fs->id);
drivers/media/platform/amphion/vdec.c
1464
dev_dbg(inst->dev, "[%d] frame skip\n", inst->id);
drivers/media/platform/amphion/vdec.c
1468
vdec_release_curr_frame_store(inst, fs->id);
drivers/media/platform/amphion/vdec.c
1469
vpu_process_capture_buffer(inst);
drivers/media/platform/amphion/vdec.c
1472
vpu_inst_unlock(inst);
drivers/media/platform/amphion/vdec.c
1475
static void vdec_event_eos(struct vpu_inst *inst)
drivers/media/platform/amphion/vdec.c
1477
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
1479
vpu_trace(inst->dev, "[%d] input : %d, decoded : %d, display : %d, sequence : %d\n",
drivers/media/platform/amphion/vdec.c
1480
inst->id,
drivers/media/platform/amphion/vdec.c
1485
vpu_inst_lock(inst);
drivers/media/platform/amphion/vdec.c
1488
inst->min_buffer_cap = VDEC_MIN_BUFFER_CAP;
drivers/media/platform/amphion/vdec.c
1489
vdec_set_last_buffer_dequeued(inst);
drivers/media/platform/amphion/vdec.c
1490
vpu_inst_unlock(inst);
drivers/media/platform/amphion/vdec.c
1493
static void vdec_event_notify(struct vpu_inst *inst, u32 event, void *data)
drivers/media/platform/amphion/vdec.c
1497
vdec_event_seq_hdr(inst, data);
drivers/media/platform/amphion/vdec.c
1500
vdec_event_resolution_change(inst);
drivers/media/platform/amphion/vdec.c
1503
vdec_event_req_fs(inst, data);
drivers/media/platform/amphion/vdec.c
1506
vdec_evnet_rel_fs(inst, data);
drivers/media/platform/amphion/vdec.c
1509
vdec_event_eos(inst);
drivers/media/platform/amphion/vdec.c
1516
static int vdec_process_output(struct vpu_inst *inst, struct vb2_buffer *vb)
drivers/media/platform/amphion/vdec.c
1518
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
1525
dev_dbg(inst->dev, "[%d] dec output [%d] %d : %ld\n",
drivers/media/platform/amphion/vdec.c
1526
inst->id, vbuf->sequence, vb->index, vb2_get_plane_payload(vb, 0));
drivers/media/platform/amphion/vdec.c
1528
if (inst->state == VPU_CODEC_STATE_DEINIT)
drivers/media/platform/amphion/vdec.c
1533
if (inst->state == VPU_CODEC_STATE_STARTED)
drivers/media/platform/amphion/vdec.c
1534
vdec_update_state(inst, VPU_CODEC_STATE_ACTIVE, 0);
drivers/media/platform/amphion/vdec.c
1536
ret = vpu_iface_get_stream_buffer_desc(inst, &desc);
drivers/media/platform/amphion/vdec.c
1540
free_space = vpu_helper_get_free_space(inst);
drivers/media/platform/amphion/vdec.c
1545
ret = vpu_iface_input_frame(inst, vb);
drivers/media/platform/amphion/vdec.c
1549
dev_dbg(inst->dev, "[%d][INPUT TS]%32lld\n", inst->id, vb->timestamp);
drivers/media/platform/amphion/vdec.c
1553
vdec_drain(inst);
drivers/media/platform/amphion/vdec.c
1558
static int vdec_process_capture(struct vpu_inst *inst, struct vb2_buffer *vb)
drivers/media/platform/amphion/vdec.c
1560
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
1564
if (inst->state == VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE)
drivers/media/platform/amphion/vdec.c
1569
ret = vdec_response_frame(inst, vbuf);
drivers/media/platform/amphion/vdec.c
1572
v4l2_m2m_dst_buf_remove_by_buf(inst->fh.m2m_ctx, vbuf);
drivers/media/platform/amphion/vdec.c
1576
static void vdec_on_queue_empty(struct vpu_inst *inst, u32 type)
drivers/media/platform/amphion/vdec.c
1578
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
1583
vdec_handle_resolution_change(inst);
drivers/media/platform/amphion/vdec.c
1585
vdec_set_last_buffer_dequeued(inst);
drivers/media/platform/amphion/vdec.c
1588
static void vdec_abort(struct vpu_inst *inst)
drivers/media/platform/amphion/vdec.c
1590
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
1594
vpu_trace(inst->dev, "[%d] state = %s\n", inst->id, vpu_codec_state_name(inst->state));
drivers/media/platform/amphion/vdec.c
1597
vpu_iface_add_scode(inst, SCODE_PADDING_ABORT);
drivers/media/platform/amphion/vdec.c
1599
vpu_iface_set_decode_params(inst, &vdec->params, 1);
drivers/media/platform/amphion/vdec.c
1601
vpu_session_abort(inst);
drivers/media/platform/amphion/vdec.c
1603
ret = vpu_iface_get_stream_buffer_desc(inst, &desc);
drivers/media/platform/amphion/vdec.c
1605
vpu_iface_update_stream_buffer(inst, desc.rptr, 1);
drivers/media/platform/amphion/vdec.c
1607
vpu_session_rst_buf(inst);
drivers/media/platform/amphion/vdec.c
1608
vpu_trace(inst->dev, "[%d] input : %d, decoded : %d, display : %d, sequence : %d\n",
drivers/media/platform/amphion/vdec.c
1609
inst->id,
drivers/media/platform/amphion/vdec.c
1623
inst->extra_size = 0;
drivers/media/platform/amphion/vdec.c
1626
static void vdec_stop(struct vpu_inst *inst, bool free)
drivers/media/platform/amphion/vdec.c
1628
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
1630
vdec_clear_slots(inst);
drivers/media/platform/amphion/vdec.c
1631
if (inst->state != VPU_CODEC_STATE_DEINIT)
drivers/media/platform/amphion/vdec.c
1632
vpu_session_stop(inst);
drivers/media/platform/amphion/vdec.c
1637
vpu_free_dma(&inst->stream_buffer);
drivers/media/platform/amphion/vdec.c
1639
vdec_update_state(inst, VPU_CODEC_STATE_DEINIT, 1);
drivers/media/platform/amphion/vdec.c
1643
static void vdec_release(struct vpu_inst *inst)
drivers/media/platform/amphion/vdec.c
1645
if (inst->id != VPU_INST_NULL_ID)
drivers/media/platform/amphion/vdec.c
1646
vpu_trace(inst->dev, "[%d]\n", inst->id);
drivers/media/platform/amphion/vdec.c
1647
vdec_stop(inst, true);
drivers/media/platform/amphion/vdec.c
1650
static void vdec_cleanup(struct vpu_inst *inst)
drivers/media/platform/amphion/vdec.c
1654
if (!inst)
drivers/media/platform/amphion/vdec.c
1657
vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
1664
inst->priv = NULL;
drivers/media/platform/amphion/vdec.c
1665
kfree(inst);
drivers/media/platform/amphion/vdec.c
1674
static int vdec_start(struct vpu_inst *inst)
drivers/media/platform/amphion/vdec.c
1676
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
1680
if (inst->state != VPU_CODEC_STATE_DEINIT)
drivers/media/platform/amphion/vdec.c
1683
vpu_trace(inst->dev, "[%d]\n", inst->id);
drivers/media/platform/amphion/vdec.c
1686
ret = vpu_alloc_dma(inst->core, &vdec->udata);
drivers/media/platform/amphion/vdec.c
1688
dev_err(inst->dev, "[%d] alloc udata fail\n", inst->id);
drivers/media/platform/amphion/vdec.c
1693
if (!inst->stream_buffer.virt) {
drivers/media/platform/amphion/vdec.c
1694
stream_buffer_size = vpu_iface_get_stream_buffer_size(inst->core);
drivers/media/platform/amphion/vdec.c
1696
inst->stream_buffer.length = stream_buffer_size;
drivers/media/platform/amphion/vdec.c
1697
ret = vpu_alloc_dma(inst->core, &inst->stream_buffer);
drivers/media/platform/amphion/vdec.c
1699
dev_err(inst->dev, "[%d] alloc stream buffer fail\n", inst->id);
drivers/media/platform/amphion/vdec.c
1702
inst->use_stream_buffer = true;
drivers/media/platform/amphion/vdec.c
1706
if (inst->use_stream_buffer)
drivers/media/platform/amphion/vdec.c
1707
vpu_iface_config_stream_buffer(inst, &inst->stream_buffer);
drivers/media/platform/amphion/vdec.c
1708
vpu_iface_init_instance(inst);
drivers/media/platform/amphion/vdec.c
1711
ret = vpu_iface_set_decode_params(inst, &vdec->params, 0);
drivers/media/platform/amphion/vdec.c
1713
dev_err(inst->dev, "[%d] set decode params fail\n", inst->id);
drivers/media/platform/amphion/vdec.c
1718
ret = vpu_session_start(inst);
drivers/media/platform/amphion/vdec.c
1720
dev_err(inst->dev, "[%d] start fail\n", inst->id);
drivers/media/platform/amphion/vdec.c
1724
vdec_update_state(inst, VPU_CODEC_STATE_STARTED, 0);
drivers/media/platform/amphion/vdec.c
1729
vpu_free_dma(&inst->stream_buffer);
drivers/media/platform/amphion/vdec.c
1733
static int vdec_start_session(struct vpu_inst *inst, u32 type)
drivers/media/platform/amphion/vdec.c
1735
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
1740
vdec_stop(inst, false);
drivers/media/platform/amphion/vdec.c
1741
if (inst->state == VPU_CODEC_STATE_DEINIT) {
drivers/media/platform/amphion/vdec.c
1742
ret = vdec_start(inst);
drivers/media/platform/amphion/vdec.c
1749
vdec_update_state(inst, vdec->state, 1);
drivers/media/platform/amphion/vdec.c
1751
vpu_process_output_buffer(inst);
drivers/media/platform/amphion/vdec.c
1753
vdec_cmd_start(inst);
drivers/media/platform/amphion/vdec.c
1755
if (inst->state == VPU_CODEC_STATE_ACTIVE)
drivers/media/platform/amphion/vdec.c
1756
vdec_response_fs_request(inst, false);
drivers/media/platform/amphion/vdec.c
1761
static int vdec_stop_session(struct vpu_inst *inst, u32 type)
drivers/media/platform/amphion/vdec.c
1763
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
1765
if (inst->state == VPU_CODEC_STATE_DEINIT)
drivers/media/platform/amphion/vdec.c
1769
vdec_update_state(inst, VPU_CODEC_STATE_SEEK, 0);
drivers/media/platform/amphion/vdec.c
1771
vdec_abort(inst);
drivers/media/platform/amphion/vdec.c
1773
if (inst->state != VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE) {
drivers/media/platform/amphion/vdec.c
1774
if (vb2_is_streaming(v4l2_m2m_get_src_vq(inst->fh.m2m_ctx)))
drivers/media/platform/amphion/vdec.c
1775
vdec_abort(inst);
drivers/media/platform/amphion/vdec.c
1778
vdec_clear_slots(inst);
drivers/media/platform/amphion/vdec.c
1784
static int vdec_get_slot_debug_info(struct vpu_inst *inst, char *str, u32 size, u32 i)
drivers/media/platform/amphion/vdec.c
1786
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
1790
vpu_inst_lock(inst);
drivers/media/platform/amphion/vdec.c
1811
vpu_inst_unlock(inst);
drivers/media/platform/amphion/vdec.c
1816
static int vdec_get_debug_info(struct vpu_inst *inst, char *str, u32 size, u32 i)
drivers/media/platform/amphion/vdec.c
1818
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
1874
num = vdec_get_slot_debug_info(inst, str, size, i - 10);
drivers/media/platform/amphion/vdec.c
1904
struct vpu_inst *inst = to_inst(file);
drivers/media/platform/amphion/vdec.c
1913
vdec_s_fmt(file, &inst->fh, &f);
drivers/media/platform/amphion/vdec.c
1921
vdec_s_fmt(file, &inst->fh, &f);
drivers/media/platform/amphion/vdec.c
1926
struct vpu_inst *inst;
drivers/media/platform/amphion/vdec.c
1930
inst = kzalloc_obj(*inst);
drivers/media/platform/amphion/vdec.c
1931
if (!inst)
drivers/media/platform/amphion/vdec.c
1936
kfree(inst);
drivers/media/platform/amphion/vdec.c
1944
kfree(inst);
drivers/media/platform/amphion/vdec.c
1949
inst->ops = &vdec_inst_ops;
drivers/media/platform/amphion/vdec.c
1950
inst->formats = vdec_formats;
drivers/media/platform/amphion/vdec.c
1951
inst->type = VPU_CORE_TYPE_DEC;
drivers/media/platform/amphion/vdec.c
1952
inst->priv = vdec;
drivers/media/platform/amphion/vdec.c
1954
ret = vpu_v4l2_open(file, inst);
drivers/media/platform/amphion/vdec.c
1960
inst->min_buffer_cap = VDEC_MIN_BUFFER_CAP;
drivers/media/platform/amphion/vdec.c
1961
inst->min_buffer_out = VDEC_MIN_BUFFER_OUT;
drivers/media/platform/amphion/vdec.c
202
struct vpu_inst *inst = ctrl_to_inst(ctrl);
drivers/media/platform/amphion/vdec.c
203
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
226
static int vdec_ctrl_init(struct vpu_inst *inst)
drivers/media/platform/amphion/vdec.c
231
ret = v4l2_ctrl_handler_init(&inst->ctrl_handler, 20);
drivers/media/platform/amphion/vdec.c
235
v4l2_ctrl_new_std(&inst->ctrl_handler, &vdec_ctrl_ops,
drivers/media/platform/amphion/vdec.c
239
v4l2_ctrl_new_std(&inst->ctrl_handler, &vdec_ctrl_ops,
drivers/media/platform/amphion/vdec.c
243
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, NULL,
drivers/media/platform/amphion/vdec.c
253
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, NULL,
drivers/media/platform/amphion/vdec.c
259
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, NULL,
drivers/media/platform/amphion/vdec.c
266
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, NULL,
drivers/media/platform/amphion/vdec.c
272
ctrl = v4l2_ctrl_new_std(&inst->ctrl_handler, &vdec_ctrl_ops,
drivers/media/platform/amphion/vdec.c
277
ctrl = v4l2_ctrl_new_std(&inst->ctrl_handler, &vdec_ctrl_ops,
drivers/media/platform/amphion/vdec.c
282
if (inst->ctrl_handler.error) {
drivers/media/platform/amphion/vdec.c
283
ret = inst->ctrl_handler.error;
drivers/media/platform/amphion/vdec.c
284
v4l2_ctrl_handler_free(&inst->ctrl_handler);
drivers/media/platform/amphion/vdec.c
288
ret = v4l2_ctrl_handler_setup(&inst->ctrl_handler);
drivers/media/platform/amphion/vdec.c
290
dev_err(inst->dev, "[%d] setup ctrls fail, ret = %d\n", inst->id, ret);
drivers/media/platform/amphion/vdec.c
291
v4l2_ctrl_handler_free(&inst->ctrl_handler);
drivers/media/platform/amphion/vdec.c
298
static void vdec_attach_frame_store(struct vpu_inst *inst, struct vb2_buffer *vb)
drivers/media/platform/amphion/vdec.c
302
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
344
static void vdec_reset_frame_store(struct vpu_inst *inst)
drivers/media/platform/amphion/vdec.c
346
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
351
vpu_trace(inst->dev, "inst[%d] reset slots\n", inst->id);
drivers/media/platform/amphion/vdec.c
355
static void vdec_handle_resolution_change(struct vpu_inst *inst)
drivers/media/platform/amphion/vdec.c
357
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
360
if (!inst->fh.m2m_ctx)
drivers/media/platform/amphion/vdec.c
363
if (inst->state != VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE)
drivers/media/platform/amphion/vdec.c
368
q = v4l2_m2m_get_dst_vq(inst->fh.m2m_ctx);
drivers/media/platform/amphion/vdec.c
373
vpu_notify_source_change(inst);
drivers/media/platform/amphion/vdec.c
374
vpu_set_last_buffer_dequeued(inst, false);
drivers/media/platform/amphion/vdec.c
377
static int vdec_update_state(struct vpu_inst *inst, enum vpu_codec_state state, u32 force)
drivers/media/platform/amphion/vdec.c
379
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
380
enum vpu_codec_state pre_state = inst->state;
drivers/media/platform/amphion/vdec.c
383
if (inst->state == VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE)
drivers/media/platform/amphion/vdec.c
384
vdec->state = inst->state;
drivers/media/platform/amphion/vdec.c
388
if (inst->state != VPU_CODEC_STATE_SEEK || force)
drivers/media/platform/amphion/vdec.c
389
inst->state = state;
drivers/media/platform/amphion/vdec.c
393
if (inst->state != pre_state)
drivers/media/platform/amphion/vdec.c
394
vpu_trace(inst->dev, "[%d] %s -> %s\n", inst->id,
drivers/media/platform/amphion/vdec.c
395
vpu_codec_state_name(pre_state), vpu_codec_state_name(inst->state));
drivers/media/platform/amphion/vdec.c
397
if (inst->state == VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE)
drivers/media/platform/amphion/vdec.c
398
vdec_handle_resolution_change(inst);
drivers/media/platform/amphion/vdec.c
403
static void vdec_set_last_buffer_dequeued(struct vpu_inst *inst)
drivers/media/platform/amphion/vdec.c
405
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
407
if (inst->state == VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE)
drivers/media/platform/amphion/vdec.c
411
if (!vpu_set_last_buffer_dequeued(inst, true)) {
drivers/media/platform/amphion/vdec.c
413
vdec_update_state(inst, VPU_CODEC_STATE_DRAIN, 0);
drivers/media/platform/amphion/vdec.c
429
struct vpu_inst *inst = to_inst(file);
drivers/media/platform/amphion/vdec.c
430
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
434
vpu_inst_lock(inst);
drivers/media/platform/amphion/vdec.c
436
fmt = vpu_get_format(inst, f->type);
drivers/media/platform/amphion/vdec.c
438
fmt = vpu_helper_find_sibling(inst, f->type, fmt->pixfmt);
drivers/media/platform/amphion/vdec.c
442
fmt = vpu_helper_enum_format(inst, f->type, f->index);
drivers/media/platform/amphion/vdec.c
452
vpu_inst_unlock(inst);
drivers/media/platform/amphion/vdec.c
458
struct vpu_inst *inst = to_inst(file);
drivers/media/platform/amphion/vdec.c
459
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
464
vpu_inst_lock(inst);
drivers/media/platform/amphion/vdec.c
465
cur_fmt = vpu_get_format(inst, f->type);
drivers/media/platform/amphion/vdec.c
482
vpu_inst_unlock(inst);
drivers/media/platform/amphion/vdec.c
489
struct vpu_inst *inst = to_inst(file);
drivers/media/platform/amphion/vdec.c
490
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
493
vpu_inst_lock(inst);
drivers/media/platform/amphion/vdec.c
495
struct vpu_format *cap_fmt = vpu_get_format(inst, f->type);
drivers/media/platform/amphion/vdec.c
497
if (!vpu_helper_match_format(inst, cap_fmt->type, cap_fmt->pixfmt,
drivers/media/platform/amphion/vdec.c
502
vpu_try_fmt_common(inst, f, &fmt);
drivers/media/platform/amphion/vdec.c
515
vpu_inst_unlock(inst);
drivers/media/platform/amphion/vdec.c
520
static int vdec_s_fmt_common(struct vpu_inst *inst, struct v4l2_format *f)
drivers/media/platform/amphion/vdec.c
526
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
529
if (!inst->fh.m2m_ctx)
drivers/media/platform/amphion/vdec.c
532
q = v4l2_m2m_get_vq(inst->fh.m2m_ctx, f->type);
drivers/media/platform/amphion/vdec.c
536
if (vpu_try_fmt_common(inst, f, &fmt))
drivers/media/platform/amphion/vdec.c
539
cur_fmt = vpu_get_format(inst, f->type);
drivers/media/platform/amphion/vdec.c
540
if (V4L2_TYPE_IS_OUTPUT(f->type) && inst->state != VPU_CODEC_STATE_DEINIT) {
drivers/media/platform/amphion/vdec.c
549
if (vpu_helper_match_format(inst, f->type, cur_fmt->pixfmt, pixmp->pixelformat)) {
drivers/media/platform/amphion/vdec.c
573
inst->crop.left = 0;
drivers/media/platform/amphion/vdec.c
574
inst->crop.top = 0;
drivers/media/platform/amphion/vdec.c
575
inst->crop.width = cur_fmt->width;
drivers/media/platform/amphion/vdec.c
576
inst->crop.height = cur_fmt->height;
drivers/media/platform/amphion/vdec.c
580
vpu_trace(inst->dev, "[%d] %c%c%c%c %dx%d\n", inst->id,
drivers/media/platform/amphion/vdec.c
593
struct vpu_inst *inst = to_inst(file);
drivers/media/platform/amphion/vdec.c
595
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
598
vpu_inst_lock(inst);
drivers/media/platform/amphion/vdec.c
599
ret = vdec_s_fmt_common(inst, f);
drivers/media/platform/amphion/vdec.c
607
fc.type = inst->cap_format.type;
drivers/media/platform/amphion/vdec.c
608
fc.fmt.pix_mp.pixelformat = inst->cap_format.pixfmt;
drivers/media/platform/amphion/vdec.c
611
vdec_s_fmt_common(inst, &fc);
drivers/media/platform/amphion/vdec.c
620
vpu_inst_unlock(inst);
drivers/media/platform/amphion/vdec.c
626
struct vpu_inst *inst = to_inst(file);
drivers/media/platform/amphion/vdec.c
635
s->r = inst->crop;
drivers/media/platform/amphion/vdec.c
640
s->r.width = inst->cap_format.width;
drivers/media/platform/amphion/vdec.c
641
s->r.height = inst->cap_format.height;
drivers/media/platform/amphion/vdec.c
650
static int vdec_drain(struct vpu_inst *inst)
drivers/media/platform/amphion/vdec.c
652
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
654
if (!inst->fh.m2m_ctx)
drivers/media/platform/amphion/vdec.c
660
if (!vpu_is_source_empty(inst))
drivers/media/platform/amphion/vdec.c
664
vpu_set_last_buffer_dequeued(inst, true);
drivers/media/platform/amphion/vdec.c
668
vpu_iface_add_scode(inst, SCODE_PADDING_EOS);
drivers/media/platform/amphion/vdec.c
670
vpu_iface_set_decode_params(inst, &vdec->params, 1);
drivers/media/platform/amphion/vdec.c
672
vpu_trace(inst->dev, "[%d] frame_count = %d\n", inst->id, vdec->params.frame_count);
drivers/media/platform/amphion/vdec.c
677
static int vdec_cmd_start(struct vpu_inst *inst)
drivers/media/platform/amphion/vdec.c
679
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
681
switch (inst->state) {
drivers/media/platform/amphion/vdec.c
685
vdec_update_state(inst, VPU_CODEC_STATE_ACTIVE, 0);
drivers/media/platform/amphion/vdec.c
690
vpu_process_capture_buffer(inst);
drivers/media/platform/amphion/vdec.c
692
vdec_set_last_buffer_dequeued(inst);
drivers/media/platform/amphion/vdec.c
696
static int vdec_cmd_stop(struct vpu_inst *inst)
drivers/media/platform/amphion/vdec.c
698
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
700
vpu_trace(inst->dev, "[%d]\n", inst->id);
drivers/media/platform/amphion/vdec.c
702
if (inst->state == VPU_CODEC_STATE_DEINIT) {
drivers/media/platform/amphion/vdec.c
703
vpu_set_last_buffer_dequeued(inst, true);
drivers/media/platform/amphion/vdec.c
706
vdec_drain(inst);
drivers/media/platform/amphion/vdec.c
714
struct vpu_inst *inst = to_inst(file);
drivers/media/platform/amphion/vdec.c
721
vpu_inst_lock(inst);
drivers/media/platform/amphion/vdec.c
724
vdec_cmd_start(inst);
drivers/media/platform/amphion/vdec.c
725
vb2_clear_last_buffer_dequeued(v4l2_m2m_get_dst_vq(inst->fh.m2m_ctx));
drivers/media/platform/amphion/vdec.c
728
vdec_cmd_stop(inst);
drivers/media/platform/amphion/vdec.c
733
vpu_inst_unlock(inst);
drivers/media/platform/amphion/vdec.c
780
static bool vdec_check_ready(struct vpu_inst *inst, unsigned int type)
drivers/media/platform/amphion/vdec.c
782
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
793
static struct vb2_v4l2_buffer *vdec_get_src_buffer(struct vpu_inst *inst, u32 count)
drivers/media/platform/amphion/vdec.c
796
vpu_skip_frame(inst, count - 1);
drivers/media/platform/amphion/vdec.c
798
return vpu_next_src_buf(inst);
drivers/media/platform/amphion/vdec.c
801
static int vdec_frame_decoded(struct vpu_inst *inst, void *arg)
drivers/media/platform/amphion/vdec.c
803
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
813
vpu_inst_lock(inst);
drivers/media/platform/amphion/vdec.c
816
dev_err(inst->dev, "[%d] decoded invalid frame[%d]\n", inst->id, info->id);
drivers/media/platform/amphion/vdec.c
821
src_buf = vdec_get_src_buffer(inst, info->consumed_count);
drivers/media/platform/amphion/vdec.c
825
v4l2_m2m_src_buf_remove(inst->fh.m2m_ctx);
drivers/media/platform/amphion/vdec.c
833
dev_info(inst->dev, "[%d] buf[%d] has been decoded\n", inst->id, info->id);
drivers/media/platform/amphion/vdec.c
840
cur_fmt = vpu_get_format(inst, inst->cap_format.type);
drivers/media/platform/amphion/vdec.c
848
dev_dbg(inst->dev, "[%d][OUTPUT TS]%32lld\n", inst->id, vbuf->vb2_buf.timestamp);
drivers/media/platform/amphion/vdec.c
854
vpu_inst_unlock(inst);
drivers/media/platform/amphion/vdec.c
859
static struct vpu_vb2_buffer *vdec_find_buffer(struct vpu_inst *inst, u32 luma)
drivers/media/platform/amphion/vdec.c
861
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
874
static void vdec_buf_done(struct vpu_inst *inst, struct vpu_frame_info *frame)
drivers/media/platform/amphion/vdec.c
876
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
885
vpu_inst_lock(inst);
drivers/media/platform/amphion/vdec.c
888
vpu_buf = vdec_find_buffer(inst, frame->luma);
drivers/media/platform/amphion/vdec.c
889
vpu_inst_unlock(inst);
drivers/media/platform/amphion/vdec.c
891
dev_err(inst->dev, "[%d] can't find buffer, id = %d, addr = 0x%x\n",
drivers/media/platform/amphion/vdec.c
892
inst->id, frame->id, frame->luma);
drivers/media/platform/amphion/vdec.c
896
dev_dbg(inst->dev, "[%d] frame skip\n", inst->id);
drivers/media/platform/amphion/vdec.c
900
cur_fmt = vpu_get_format(inst, inst->cap_format.type);
drivers/media/platform/amphion/vdec.c
903
dev_err(inst->dev, "[%d] buffer id(%d(%d), %d) mismatch\n",
drivers/media/platform/amphion/vdec.c
904
inst->id, vpu_buf->fs_id, vbuf->vb2_buf.index, frame->id);
drivers/media/platform/amphion/vdec.c
910
dev_err(inst->dev, "[%d] buffer(%d) ready without decoded\n", inst->id, frame->id);
drivers/media/platform/amphion/vdec.c
917
dev_dbg(inst->dev, "[%d][OUTPUT TS]%32lld\n", inst->id, vbuf->vb2_buf.timestamp);
drivers/media/platform/amphion/vdec.c
919
vpu_inst_lock(inst);
drivers/media/platform/amphion/vdec.c
922
vpu_inst_unlock(inst);
drivers/media/platform/amphion/vdec.c
924
dev_dbg(inst->dev, "[%d] decoded : %d, display : %d, sequence : %d\n",
drivers/media/platform/amphion/vdec.c
925
inst->id, vdec->decoded_frame_count, vdec->display_frame_count, vdec->sequence);
drivers/media/platform/amphion/vdec.c
928
static void vdec_stop_done(struct vpu_inst *inst)
drivers/media/platform/amphion/vdec.c
930
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
932
vpu_inst_lock(inst);
drivers/media/platform/amphion/vdec.c
933
vdec_update_state(inst, VPU_CODEC_STATE_DEINIT, 0);
drivers/media/platform/amphion/vdec.c
947
inst->total_input_count = 0;
drivers/media/platform/amphion/vdec.c
948
vpu_inst_unlock(inst);
drivers/media/platform/amphion/vdec.c
951
static bool vdec_check_source_change(struct vpu_inst *inst, struct vpu_dec_codec_info *hdr)
drivers/media/platform/amphion/vdec.c
953
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/vdec.c
956
if (!inst->fh.m2m_ctx)
drivers/media/platform/amphion/vdec.c
962
sibling = vpu_helper_find_sibling(inst, inst->cap_format.type, inst->cap_format.pixfmt);
drivers/media/platform/amphion/vdec.c
964
hdr->pixfmt = inst->cap_format.pixfmt;
drivers/media/platform/amphion/vdec.c
966
if (!vb2_is_streaming(v4l2_m2m_get_dst_vq(inst->fh.m2m_ctx)))
drivers/media/platform/amphion/vdec.c
968
if (inst->cap_format.pixfmt != hdr->pixfmt)
drivers/media/platform/amphion/vdec.c
970
if (inst->cap_format.width != hdr->decoded_width)
drivers/media/platform/amphion/vdec.c
972
if (inst->cap_format.height != hdr->decoded_height)
drivers/media/platform/amphion/vdec.c
974
if (vpu_get_num_buffers(inst, inst->cap_format.type) < inst->min_buffer_cap)
drivers/media/platform/amphion/vdec.c
976
if (inst->crop.left != hdr->offset_x)
drivers/media/platform/amphion/vdec.c
978
if (inst->crop.top != hdr->offset_y)
drivers/media/platform/amphion/vdec.c
980
if (inst->crop.width != hdr->width)
drivers/media/platform/amphion/vdec.c
982
if (inst->crop.height != hdr->height)
drivers/media/platform/amphion/vdec.c
997
static void vdec_init_fmt(struct vpu_inst *inst)
drivers/media/platform/amphion/vdec.c
999
struct vdec_t *vdec = inst->priv;
drivers/media/platform/amphion/venc.c
1002
static void venc_request_mem_resource(struct vpu_inst *inst,
drivers/media/platform/amphion/venc.c
1014
venc = inst->priv;
drivers/media/platform/amphion/venc.c
1016
dev_err(inst->dev, "[%d] enc num(%d) is out of range\n", inst->id, enc_frame_num);
drivers/media/platform/amphion/venc.c
1020
dev_err(inst->dev, "[%d] ref num(%d) is out of range\n", inst->id, ref_frame_num);
drivers/media/platform/amphion/venc.c
1024
dev_err(inst->dev, "[%d] act num(%d) is out of range\n", inst->id, act_frame_num);
drivers/media/platform/amphion/venc.c
1030
ret = vpu_alloc_dma(inst->core, &venc->enc[i]);
drivers/media/platform/amphion/venc.c
1032
venc_cleanup_mem_resource(inst);
drivers/media/platform/amphion/venc.c
1038
ret = vpu_alloc_dma(inst->core, &venc->ref[i]);
drivers/media/platform/amphion/venc.c
104
struct vpu_inst *inst = to_inst(file);
drivers/media/platform/amphion/venc.c
1040
venc_cleanup_mem_resource(inst);
drivers/media/platform/amphion/venc.c
1044
if (act_frame_num != 1 || act_frame_size > inst->act.length) {
drivers/media/platform/amphion/venc.c
1045
venc_cleanup_mem_resource(inst);
drivers/media/platform/amphion/venc.c
1049
venc->act[0].phys = inst->act.phys;
drivers/media/platform/amphion/venc.c
1050
venc->act[0].virt = inst->act.virt;
drivers/media/platform/amphion/venc.c
1053
vpu_iface_config_memory_resource(inst, MEM_RES_ENC, i, &venc->enc[i]);
drivers/media/platform/amphion/venc.c
1055
vpu_iface_config_memory_resource(inst, MEM_RES_REF, i, &venc->ref[i]);
drivers/media/platform/amphion/venc.c
1057
vpu_iface_config_memory_resource(inst, MEM_RES_ACT, i, &venc->act[i]);
drivers/media/platform/amphion/venc.c
1072
static int venc_stop_session(struct vpu_inst *inst, u32 type)
drivers/media/platform/amphion/venc.c
1074
struct venc_t *venc = inst->priv;
drivers/media/platform/amphion/venc.c
108
fmt = vpu_helper_enum_format(inst, f->type, f->index);
drivers/media/platform/amphion/venc.c
1080
if (inst->state == VPU_CODEC_STATE_DEINIT)
drivers/media/platform/amphion/venc.c
1083
if (inst->state != VPU_CODEC_STATE_STOP)
drivers/media/platform/amphion/venc.c
1084
venc_request_eos(inst);
drivers/media/platform/amphion/venc.c
1086
call_void_vop(inst, wait_prepare);
drivers/media/platform/amphion/venc.c
1088
set_bit(inst->id, &inst->core->hang_mask);
drivers/media/platform/amphion/venc.c
1089
vpu_session_debug(inst);
drivers/media/platform/amphion/venc.c
1091
call_void_vop(inst, wait_finish);
drivers/media/platform/amphion/venc.c
1093
inst->state = VPU_CODEC_STATE_DEINIT;
drivers/media/platform/amphion/venc.c
1094
venc_cleanup_frames(inst->priv);
drivers/media/platform/amphion/venc.c
1095
vpu_free_dma(&inst->stream_buffer);
drivers/media/platform/amphion/venc.c
1096
venc_cleanup_mem_resource(inst);
drivers/media/platform/amphion/venc.c
1101
static int venc_process_output(struct vpu_inst *inst, struct vb2_buffer *vb)
drivers/media/platform/amphion/venc.c
1103
struct venc_t *venc = inst->priv;
drivers/media/platform/amphion/venc.c
1107
if (inst->state == VPU_CODEC_STATE_DEINIT)
drivers/media/platform/amphion/venc.c
1111
if (inst->state == VPU_CODEC_STATE_STARTED)
drivers/media/platform/amphion/venc.c
1112
inst->state = VPU_CODEC_STATE_ACTIVE;
drivers/media/platform/amphion/venc.c
1120
vpu_session_update_parameters(inst, &venc->params);
drivers/media/platform/amphion/venc.c
1123
dev_dbg(inst->dev, "[%d][INPUT TS]%32lld\n", inst->id, vb->timestamp);
drivers/media/platform/amphion/venc.c
1124
vpu_iface_input_frame(inst, vb);
drivers/media/platform/amphion/venc.c
1133
static int venc_process_capture(struct vpu_inst *inst, struct vb2_buffer *vb)
drivers/media/platform/amphion/venc.c
1140
venc = inst->priv;
drivers/media/platform/amphion/venc.c
1146
v4l2_m2m_dst_buf_remove_by_buf(inst->fh.m2m_ctx, vbuf);
drivers/media/platform/amphion/venc.c
1147
ret = venc_get_one_encoded_frame(inst, frame, vbuf);
drivers/media/platform/amphion/venc.c
1156
static void venc_on_queue_empty(struct vpu_inst *inst, u32 type)
drivers/media/platform/amphion/venc.c
1158
struct venc_t *venc = inst->priv;
drivers/media/platform/amphion/venc.c
1164
venc_set_last_buffer_dequeued(inst);
drivers/media/platform/amphion/venc.c
1167
static int venc_get_debug_info(struct vpu_inst *inst, char *str, u32 size, u32 i)
drivers/media/platform/amphion/venc.c
1169
struct venc_t *venc = inst->priv;
drivers/media/platform/amphion/venc.c
120
struct vpu_inst *inst = to_inst(file);
drivers/media/platform/amphion/venc.c
126
if (!vpu_helper_find_format(inst, 0, fsize->pixel_format))
drivers/media/platform/amphion/venc.c
1269
struct vpu_inst *inst = to_inst(file);
drivers/media/platform/amphion/venc.c
1274
venc = inst->priv;
drivers/media/platform/amphion/venc.c
1287
venc_s_fmt(file, &inst->fh, &f);
drivers/media/platform/amphion/venc.c
129
res = vpu_get_resource(inst);
drivers/media/platform/amphion/venc.c
1295
venc_s_fmt(file, &inst->fh, &f);
drivers/media/platform/amphion/venc.c
1301
venc_s_parm(file, &inst->fh, &parm);
drivers/media/platform/amphion/venc.c
1306
struct vpu_inst *inst;
drivers/media/platform/amphion/venc.c
1310
inst = kzalloc_obj(*inst);
drivers/media/platform/amphion/venc.c
1311
if (!inst)
drivers/media/platform/amphion/venc.c
1316
kfree(inst);
drivers/media/platform/amphion/venc.c
1320
inst->ops = &venc_inst_ops;
drivers/media/platform/amphion/venc.c
1321
inst->formats = venc_formats;
drivers/media/platform/amphion/venc.c
1322
inst->type = VPU_CORE_TYPE_ENC;
drivers/media/platform/amphion/venc.c
1323
inst->priv = venc;
drivers/media/platform/amphion/venc.c
1327
ret = vpu_v4l2_open(file, inst);
drivers/media/platform/amphion/venc.c
1331
inst->min_buffer_out = VENC_MIN_BUFFER_OUT;
drivers/media/platform/amphion/venc.c
1332
inst->min_buffer_cap = VENC_MIN_BUFFER_CAP;
drivers/media/platform/amphion/venc.c
145
struct vpu_inst *inst = to_inst(file);
drivers/media/platform/amphion/venc.c
151
if (!vpu_helper_find_format(inst, 0, fival->pixel_format))
drivers/media/platform/amphion/venc.c
157
res = vpu_get_resource(inst);
drivers/media/platform/amphion/venc.c
177
struct vpu_inst *inst = to_inst(file);
drivers/media/platform/amphion/venc.c
178
struct venc_t *venc = inst->priv;
drivers/media/platform/amphion/venc.c
183
cur_fmt = vpu_get_format(inst, f->type);
drivers/media/platform/amphion/venc.c
206
struct vpu_inst *inst = to_inst(file);
drivers/media/platform/amphion/venc.c
209
vpu_try_fmt_common(inst, f, &fmt);
drivers/media/platform/amphion/venc.c
216
struct vpu_inst *inst = to_inst(file);
drivers/media/platform/amphion/venc.c
220
struct venc_t *venc = inst->priv;
drivers/media/platform/amphion/venc.c
223
q = v4l2_m2m_get_vq(inst->fh.m2m_ctx, f->type);
drivers/media/platform/amphion/venc.c
227
if (vpu_try_fmt_common(inst, f, &fmt))
drivers/media/platform/amphion/venc.c
230
cur_fmt = vpu_get_format(inst, f->type);
drivers/media/platform/amphion/venc.c
266
struct vpu_inst *inst = to_inst(file);
drivers/media/platform/amphion/venc.c
267
struct venc_t *venc = inst->priv;
drivers/media/platform/amphion/venc.c
276
if (!vpu_helper_check_type(inst, parm->type))
drivers/media/platform/amphion/venc.c
290
struct vpu_inst *inst = to_inst(file);
drivers/media/platform/amphion/venc.c
291
struct venc_t *venc = inst->priv;
drivers/media/platform/amphion/venc.c
301
if (!vpu_helper_check_type(inst, parm->type))
drivers/media/platform/amphion/venc.c
329
struct vpu_inst *inst = to_inst(file);
drivers/media/platform/amphion/venc.c
330
struct venc_t *venc = inst->priv;
drivers/media/platform/amphion/venc.c
340
s->r.width = inst->out_format.width;
drivers/media/platform/amphion/venc.c
341
s->r.height = inst->out_format.height;
drivers/media/platform/amphion/venc.c
383
struct vpu_inst *inst = to_inst(file);
drivers/media/platform/amphion/venc.c
385
struct venc_t *venc = inst->priv;
drivers/media/platform/amphion/venc.c
387
res = vpu_get_resource(inst);
drivers/media/platform/amphion/venc.c
407
inst->crop = venc->params.crop;
drivers/media/platform/amphion/venc.c
412
static int venc_drain(struct vpu_inst *inst)
drivers/media/platform/amphion/venc.c
414
struct venc_t *venc = inst->priv;
drivers/media/platform/amphion/venc.c
417
if (!inst->fh.m2m_ctx)
drivers/media/platform/amphion/venc.c
420
if (inst->state != VPU_CODEC_STATE_DRAIN)
drivers/media/platform/amphion/venc.c
423
if (!vpu_is_source_empty(inst))
drivers/media/platform/amphion/venc.c
430
vpu_trace(inst->dev, "[%d]\n", inst->id);
drivers/media/platform/amphion/venc.c
431
ret = vpu_session_stop(inst);
drivers/media/platform/amphion/venc.c
434
inst->state = VPU_CODEC_STATE_STOP;
drivers/media/platform/amphion/venc.c
440
static int venc_request_eos(struct vpu_inst *inst)
drivers/media/platform/amphion/venc.c
442
inst->state = VPU_CODEC_STATE_DRAIN;
drivers/media/platform/amphion/venc.c
443
venc_drain(inst);
drivers/media/platform/amphion/venc.c
450
struct vpu_inst *inst = to_inst(file);
drivers/media/platform/amphion/venc.c
457
vpu_inst_lock(inst);
drivers/media/platform/amphion/venc.c
459
if (inst->state == VPU_CODEC_STATE_DEINIT)
drivers/media/platform/amphion/venc.c
460
vpu_set_last_buffer_dequeued(inst, true);
drivers/media/platform/amphion/venc.c
462
venc_request_eos(inst);
drivers/media/platform/amphion/venc.c
464
vpu_inst_unlock(inst);
drivers/media/platform/amphion/venc.c
514
struct vpu_inst *inst = ctrl_to_inst(ctrl);
drivers/media/platform/amphion/venc.c
515
struct venc_t *venc = inst->priv;
drivers/media/platform/amphion/venc.c
587
static int venc_ctrl_init(struct vpu_inst *inst)
drivers/media/platform/amphion/venc.c
592
ret = v4l2_ctrl_handler_init(&inst->ctrl_handler, 20);
drivers/media/platform/amphion/venc.c
596
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/amphion/venc.c
604
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/amphion/venc.c
610
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/amphion/venc.c
613
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/amphion/venc.c
620
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/amphion/venc.c
627
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/amphion/venc.c
633
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/amphion/venc.c
636
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/amphion/venc.c
639
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/amphion/venc.c
641
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/amphion/venc.c
643
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/amphion/venc.c
645
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/amphion/venc.c
647
ctrl = v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/amphion/venc.c
651
ctrl = v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/amphion/venc.c
656
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/amphion/venc.c
659
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/amphion/venc.c
661
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/amphion/venc.c
666
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/amphion/venc.c
669
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/amphion/venc.c
672
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/amphion/venc.c
678
v4l2_ctrl_new_std(&inst->ctrl_handler, NULL,
drivers/media/platform/amphion/venc.c
681
if (inst->ctrl_handler.error) {
drivers/media/platform/amphion/venc.c
682
ret = inst->ctrl_handler.error;
drivers/media/platform/amphion/venc.c
683
v4l2_ctrl_handler_free(&inst->ctrl_handler);
drivers/media/platform/amphion/venc.c
687
ret = v4l2_ctrl_handler_setup(&inst->ctrl_handler);
drivers/media/platform/amphion/venc.c
689
dev_err(inst->dev, "[%d] setup ctrls fail, ret = %d\n", inst->id, ret);
drivers/media/platform/amphion/venc.c
690
v4l2_ctrl_handler_free(&inst->ctrl_handler);
drivers/media/platform/amphion/venc.c
697
static bool venc_check_ready(struct vpu_inst *inst, unsigned int type)
drivers/media/platform/amphion/venc.c
699
struct venc_t *venc = inst->priv;
drivers/media/platform/amphion/venc.c
702
if (vpu_helper_get_free_space(inst) < venc->cpb_size)
drivers/media/platform/amphion/venc.c
735
static void venc_input_done(struct vpu_inst *inst)
drivers/media/platform/amphion/venc.c
737
struct venc_t *venc = inst->priv;
drivers/media/platform/amphion/venc.c
739
vpu_inst_lock(inst);
drivers/media/platform/amphion/venc.c
741
vpu_process_output_buffer(inst);
drivers/media/platform/amphion/venc.c
742
if (inst->state == VPU_CODEC_STATE_DRAIN)
drivers/media/platform/amphion/venc.c
743
venc_drain(inst);
drivers/media/platform/amphion/venc.c
744
vpu_inst_unlock(inst);
drivers/media/platform/amphion/venc.c
753
static int venc_precheck_encoded_frame(struct vpu_inst *inst, struct venc_frame_t *frame)
drivers/media/platform/amphion/venc.c
761
venc = inst->priv;
drivers/media/platform/amphion/venc.c
762
skipped = vpu_helper_find_startcode(&inst->stream_buffer,
drivers/media/platform/amphion/venc.c
763
inst->cap_format.pixfmt,
drivers/media/platform/amphion/venc.c
764
frame->info.wptr - inst->stream_buffer.phys,
drivers/media/platform/amphion/venc.c
768
frame->info.wptr = vpu_helper_step_walk(&inst->stream_buffer,
drivers/media/platform/amphion/venc.c
777
static int venc_get_one_encoded_frame(struct vpu_inst *inst,
drivers/media/platform/amphion/venc.c
781
struct venc_t *venc = inst->priv;
drivers/media/platform/amphion/venc.c
787
src_buf = vpu_find_buf_by_sequence(inst, inst->out_format.type, frame->info.frame_id);
drivers/media/platform/amphion/venc.c
791
v4l2_m2m_src_buf_remove_by_buf(inst->fh.m2m_ctx, src_buf);
drivers/media/platform/amphion/venc.c
796
if (!venc_get_enable(inst->priv, vbuf->vb2_buf.type)) {
drivers/media/platform/amphion/venc.c
805
venc_precheck_encoded_frame(inst, frame);
drivers/media/platform/amphion/venc.c
811
vpu_helper_copy_from_stream_buffer(&inst->stream_buffer,
drivers/media/platform/amphion/venc.c
813
vpu_iface_update_stream_buffer(inst, rptr, 0);
drivers/media/platform/amphion/venc.c
817
vbuf->field = inst->cap_format.field;
drivers/media/platform/amphion/venc.c
821
dev_dbg(inst->dev, "[%d][OUTPUT TS]%32lld\n", inst->id, vbuf->vb2_buf.timestamp);
drivers/media/platform/amphion/venc.c
826
dev_dbg(inst->dev, "[%d][%d]key frame\n", inst->id, frame->info.frame_id);
drivers/media/platform/amphion/venc.c
831
static int venc_get_encoded_frames(struct vpu_inst *inst)
drivers/media/platform/amphion/venc.c
837
if (!inst->fh.m2m_ctx)
drivers/media/platform/amphion/venc.c
839
venc = inst->priv;
drivers/media/platform/amphion/venc.c
841
if (venc_get_one_encoded_frame(inst, frame,
drivers/media/platform/amphion/venc.c
842
v4l2_m2m_dst_buf_remove(inst->fh.m2m_ctx)))
drivers/media/platform/amphion/venc.c
851
static int venc_frame_encoded(struct vpu_inst *inst, void *arg)
drivers/media/platform/amphion/venc.c
860
venc = inst->priv;
drivers/media/platform/amphion/venc.c
868
vpu_inst_lock(inst);
drivers/media/platform/amphion/venc.c
871
venc_get_encoded_frames(inst);
drivers/media/platform/amphion/venc.c
872
vpu_inst_unlock(inst);
drivers/media/platform/amphion/venc.c
877
static void venc_set_last_buffer_dequeued(struct vpu_inst *inst)
drivers/media/platform/amphion/venc.c
879
struct venc_t *venc = inst->priv;
drivers/media/platform/amphion/venc.c
882
vpu_set_last_buffer_dequeued(inst, true);
drivers/media/platform/amphion/venc.c
885
static void venc_stop_done(struct vpu_inst *inst)
drivers/media/platform/amphion/venc.c
887
struct venc_t *venc = inst->priv;
drivers/media/platform/amphion/venc.c
889
vpu_inst_lock(inst);
drivers/media/platform/amphion/venc.c
891
venc_set_last_buffer_dequeued(inst);
drivers/media/platform/amphion/venc.c
892
vpu_inst_unlock(inst);
drivers/media/platform/amphion/venc.c
897
static void venc_event_notify(struct vpu_inst *inst, u32 event, void *data)
drivers/media/platform/amphion/venc.c
901
static void venc_release(struct vpu_inst *inst)
drivers/media/platform/amphion/venc.c
905
static void venc_cleanup(struct vpu_inst *inst)
drivers/media/platform/amphion/venc.c
909
if (!inst)
drivers/media/platform/amphion/venc.c
912
venc = inst->priv;
drivers/media/platform/amphion/venc.c
914
inst->priv = NULL;
drivers/media/platform/amphion/venc.c
915
kfree(inst);
drivers/media/platform/amphion/venc.c
918
static int venc_start_session(struct vpu_inst *inst, u32 type)
drivers/media/platform/amphion/venc.c
920
struct venc_t *venc = inst->priv;
drivers/media/platform/amphion/venc.c
928
vpu_iface_init_instance(inst);
drivers/media/platform/amphion/venc.c
929
stream_buffer_size = vpu_iface_get_stream_buffer_size(inst->core);
drivers/media/platform/amphion/venc.c
931
inst->stream_buffer.length = max_t(u32, stream_buffer_size, venc->cpb_size * 3);
drivers/media/platform/amphion/venc.c
932
ret = vpu_alloc_dma(inst->core, &inst->stream_buffer);
drivers/media/platform/amphion/venc.c
936
inst->use_stream_buffer = true;
drivers/media/platform/amphion/venc.c
937
vpu_iface_config_stream_buffer(inst, &inst->stream_buffer);
drivers/media/platform/amphion/venc.c
940
ret = vpu_iface_set_encode_params(inst, &venc->params, 0);
drivers/media/platform/amphion/venc.c
945
ret = vpu_session_configure_codec(inst);
drivers/media/platform/amphion/venc.c
950
vb2_queue_error(v4l2_m2m_get_src_vq(inst->fh.m2m_ctx));
drivers/media/platform/amphion/venc.c
951
vb2_queue_error(v4l2_m2m_get_dst_vq(inst->fh.m2m_ctx));
drivers/media/platform/amphion/venc.c
956
inst->state = VPU_CODEC_STATE_CONFIGURED;
drivers/media/platform/amphion/venc.c
960
ret = vpu_iface_set_encode_params(inst, &venc->params, 1);
drivers/media/platform/amphion/venc.c
964
ret = vpu_session_start(inst);
drivers/media/platform/amphion/venc.c
967
inst->state = VPU_CODEC_STATE_STARTED;
drivers/media/platform/amphion/venc.c
975
vpu_process_output_buffer(inst);
drivers/media/platform/amphion/venc.c
977
dev_err(inst->dev, "[%d] there is no input when starting\n", inst->id);
drivers/media/platform/amphion/venc.c
982
inst->state = VPU_CODEC_STATE_DEINIT;
drivers/media/platform/amphion/venc.c
984
vpu_free_dma(&inst->stream_buffer);
drivers/media/platform/amphion/venc.c
988
static void venc_cleanup_mem_resource(struct vpu_inst *inst)
drivers/media/platform/amphion/venc.c
993
venc = inst->priv;
drivers/media/platform/amphion/vpu.h
200
int (*ctrl_init)(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu.h
201
int (*start)(struct vpu_inst *inst, u32 type);
drivers/media/platform/amphion/vpu.h
202
int (*stop)(struct vpu_inst *inst, u32 type);
drivers/media/platform/amphion/vpu.h
203
int (*abort)(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu.h
204
bool (*check_ready)(struct vpu_inst *inst, unsigned int type);
drivers/media/platform/amphion/vpu.h
205
void (*buf_done)(struct vpu_inst *inst, struct vpu_frame_info *frame);
drivers/media/platform/amphion/vpu.h
206
void (*event_notify)(struct vpu_inst *inst, u32 event, void *data);
drivers/media/platform/amphion/vpu.h
207
void (*release)(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu.h
208
void (*cleanup)(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu.h
209
void (*mem_request)(struct vpu_inst *inst,
drivers/media/platform/amphion/vpu.h
216
void (*input_done)(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu.h
217
void (*stop_done)(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu.h
218
int (*process_output)(struct vpu_inst *inst, struct vb2_buffer *vb);
drivers/media/platform/amphion/vpu.h
219
int (*process_capture)(struct vpu_inst *inst, struct vb2_buffer *vb);
drivers/media/platform/amphion/vpu.h
220
int (*get_one_frame)(struct vpu_inst *inst, void *info);
drivers/media/platform/amphion/vpu.h
221
void (*on_queue_empty)(struct vpu_inst *inst, u32 type);
drivers/media/platform/amphion/vpu.h
222
int (*get_debug_info)(struct vpu_inst *inst, char *str, u32 size, u32 i);
drivers/media/platform/amphion/vpu.h
223
void (*wait_prepare)(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu.h
224
void (*wait_finish)(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu.h
225
void (*attach_frame_store)(struct vpu_inst *inst, struct vb2_buffer *vb);
drivers/media/platform/amphion/vpu.h
226
void (*reset_frame_store)(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu.h
240
int (*release)(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu.h
285
#define call_vop(inst, op, args...) \
drivers/media/platform/amphion/vpu.h
286
((inst)->ops->op ? (inst)->ops->op(inst, ##args) : 0) \
drivers/media/platform/amphion/vpu.h
288
#define call_void_vop(inst, op, args...) \
drivers/media/platform/amphion/vpu.h
290
if ((inst)->ops->op) \
drivers/media/platform/amphion/vpu.h
291
(inst)->ops->op(inst, ##args); \
drivers/media/platform/amphion/vpu.h
345
struct vpu_inst *vpu_inst_get(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu.h
346
void vpu_inst_put(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu.h
349
int vpu_inst_register(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu.h
350
int vpu_inst_unregister(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu.h
351
const struct vpu_core_resources *vpu_get_resource(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu.h
353
int vpu_inst_create_dbgfs_file(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu.h
354
int vpu_inst_remove_dbgfs_file(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu.h
357
void vpu_inst_record_flow(struct vpu_inst *inst, u32 flow);
drivers/media/platform/amphion/vpu_cmds.c
124
static int vpu_session_process_cmd(struct vpu_inst *inst, struct vpu_cmd_t *cmd)
drivers/media/platform/amphion/vpu_cmds.c
128
dev_dbg(inst->dev, "[%d]send cmd %s\n", inst->id, vpu_id_name(cmd->id));
drivers/media/platform/amphion/vpu_cmds.c
129
vpu_iface_pre_send_cmd(inst);
drivers/media/platform/amphion/vpu_cmds.c
130
ret = vpu_cmd_send(inst->core, cmd->pkt);
drivers/media/platform/amphion/vpu_cmds.c
132
vpu_iface_post_send_cmd(inst);
drivers/media/platform/amphion/vpu_cmds.c
133
vpu_inst_record_flow(inst, cmd->id);
drivers/media/platform/amphion/vpu_cmds.c
135
dev_err(inst->dev, "[%d] iface send cmd %s fail\n", inst->id, vpu_id_name(cmd->id));
drivers/media/platform/amphion/vpu_cmds.c
141
static void vpu_process_cmd_request(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_cmds.c
146
if (!inst || inst->pending)
drivers/media/platform/amphion/vpu_cmds.c
149
list_for_each_entry_safe(cmd, tmp, &inst->cmd_q, list) {
drivers/media/platform/amphion/vpu_cmds.c
151
if (vpu_session_process_cmd(inst, cmd))
drivers/media/platform/amphion/vpu_cmds.c
152
dev_err(inst->dev, "[%d] process cmd %s fail\n",
drivers/media/platform/amphion/vpu_cmds.c
153
inst->id, vpu_id_name(cmd->id));
drivers/media/platform/amphion/vpu_cmds.c
155
inst->pending = (void *)cmd;
drivers/media/platform/amphion/vpu_cmds.c
162
static int vpu_request_cmd(struct vpu_inst *inst, u32 id, void *data,
drivers/media/platform/amphion/vpu_cmds.c
168
if (!inst || !inst->core)
drivers/media/platform/amphion/vpu_cmds.c
171
core = inst->core;
drivers/media/platform/amphion/vpu_cmds.c
172
cmd = vpu_alloc_cmd(inst, id, data);
drivers/media/platform/amphion/vpu_cmds.c
177
cmd->key = ++inst->cmd_seq;
drivers/media/platform/amphion/vpu_cmds.c
178
cmd->last_response_cmd = &inst->last_response_cmd;
drivers/media/platform/amphion/vpu_cmds.c
183
list_add_tail(&cmd->list, &inst->cmd_q);
drivers/media/platform/amphion/vpu_cmds.c
184
vpu_process_cmd_request(inst);
drivers/media/platform/amphion/vpu_cmds.c
190
static void vpu_clear_pending(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_cmds.c
192
if (!inst || !inst->pending)
drivers/media/platform/amphion/vpu_cmds.c
195
vpu_free_cmd(inst->pending);
drivers/media/platform/amphion/vpu_cmds.c
196
wake_up_all(&inst->core->ack_wq);
drivers/media/platform/amphion/vpu_cmds.c
197
inst->pending = NULL;
drivers/media/platform/amphion/vpu_cmds.c
216
int vpu_response_cmd(struct vpu_inst *inst, u32 response, u32 handled)
drivers/media/platform/amphion/vpu_cmds.c
220
if (!inst || !inst->core)
drivers/media/platform/amphion/vpu_cmds.c
223
core = inst->core;
drivers/media/platform/amphion/vpu_cmds.c
225
if (vpu_check_response(inst->pending, response, handled))
drivers/media/platform/amphion/vpu_cmds.c
226
vpu_clear_pending(inst);
drivers/media/platform/amphion/vpu_cmds.c
228
vpu_process_cmd_request(inst);
drivers/media/platform/amphion/vpu_cmds.c
234
void vpu_clear_request(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_cmds.c
239
mutex_lock(&inst->core->cmd_lock);
drivers/media/platform/amphion/vpu_cmds.c
240
if (inst->pending)
drivers/media/platform/amphion/vpu_cmds.c
241
vpu_clear_pending(inst);
drivers/media/platform/amphion/vpu_cmds.c
243
list_for_each_entry_safe(cmd, tmp, &inst->cmd_q, list) {
drivers/media/platform/amphion/vpu_cmds.c
247
mutex_unlock(&inst->core->cmd_lock);
drivers/media/platform/amphion/vpu_cmds.c
250
static bool check_is_responsed(struct vpu_inst *inst, unsigned long key)
drivers/media/platform/amphion/vpu_cmds.c
252
unsigned long last_response = atomic_long_read(&inst->last_response_cmd);
drivers/media/platform/amphion/vpu_cmds.c
260
static int sync_session_response(struct vpu_inst *inst, unsigned long key, long timeout, int try)
drivers/media/platform/amphion/vpu_cmds.c
264
if (!inst || !inst->core)
drivers/media/platform/amphion/vpu_cmds.c
267
core = inst->core;
drivers/media/platform/amphion/vpu_cmds.c
269
call_void_vop(inst, wait_prepare);
drivers/media/platform/amphion/vpu_cmds.c
270
wait_event_timeout(core->ack_wq, check_is_responsed(inst, key), timeout);
drivers/media/platform/amphion/vpu_cmds.c
271
call_void_vop(inst, wait_finish);
drivers/media/platform/amphion/vpu_cmds.c
273
if (!check_is_responsed(inst, key)) {
drivers/media/platform/amphion/vpu_cmds.c
276
dev_err(inst->dev, "[%d] sync session timeout\n", inst->id);
drivers/media/platform/amphion/vpu_cmds.c
277
set_bit(inst->id, &core->hang_mask);
drivers/media/platform/amphion/vpu_cmds.c
278
mutex_lock(&inst->core->cmd_lock);
drivers/media/platform/amphion/vpu_cmds.c
279
vpu_clear_pending(inst);
drivers/media/platform/amphion/vpu_cmds.c
280
mutex_unlock(&inst->core->cmd_lock);
drivers/media/platform/amphion/vpu_cmds.c
301
static int vpu_session_send_cmd(struct vpu_inst *inst, u32 id, void *data)
drivers/media/platform/amphion/vpu_cmds.c
307
if (inst->id < 0)
drivers/media/platform/amphion/vpu_cmds.c
310
ret = vpu_request_cmd(inst, id, data, &key, &sync);
drivers/media/platform/amphion/vpu_cmds.c
320
if (sync_session_response(inst, key, VPU_TIMEOUT_WAKEUP, 1))
drivers/media/platform/amphion/vpu_cmds.c
321
vpu_core_keep_active(inst->core);
drivers/media/platform/amphion/vpu_cmds.c
327
ret = sync_session_response(inst, key, VPU_TIMEOUT, 0);
drivers/media/platform/amphion/vpu_cmds.c
331
dev_err(inst->dev, "[%d] send cmd %s fail\n", inst->id, vpu_id_name(id));
drivers/media/platform/amphion/vpu_cmds.c
336
int vpu_session_configure_codec(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_cmds.c
338
return vpu_session_send_cmd(inst, VPU_CMD_ID_CONFIGURE_CODEC, NULL);
drivers/media/platform/amphion/vpu_cmds.c
341
int vpu_session_start(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_cmds.c
343
vpu_trace(inst->dev, "[%d]\n", inst->id);
drivers/media/platform/amphion/vpu_cmds.c
345
return vpu_session_send_cmd(inst, VPU_CMD_ID_START, NULL);
drivers/media/platform/amphion/vpu_cmds.c
348
int vpu_session_stop(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_cmds.c
352
vpu_trace(inst->dev, "[%d]\n", inst->id);
drivers/media/platform/amphion/vpu_cmds.c
354
ret = vpu_session_send_cmd(inst, VPU_CMD_ID_STOP, NULL);
drivers/media/platform/amphion/vpu_cmds.c
363
int vpu_session_encode_frame(struct vpu_inst *inst, s64 timestamp)
drivers/media/platform/amphion/vpu_cmds.c
365
return vpu_session_send_cmd(inst, VPU_CMD_ID_FRAME_ENCODE, ×tamp);
drivers/media/platform/amphion/vpu_cmds.c
368
int vpu_session_alloc_fs(struct vpu_inst *inst, struct vpu_fs_info *fs)
drivers/media/platform/amphion/vpu_cmds.c
370
return vpu_session_send_cmd(inst, VPU_CMD_ID_FS_ALLOC, fs);
drivers/media/platform/amphion/vpu_cmds.c
373
int vpu_session_release_fs(struct vpu_inst *inst, struct vpu_fs_info *fs)
drivers/media/platform/amphion/vpu_cmds.c
375
return vpu_session_send_cmd(inst, VPU_CMD_ID_FS_RELEASE, fs);
drivers/media/platform/amphion/vpu_cmds.c
378
int vpu_session_abort(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_cmds.c
380
return vpu_session_send_cmd(inst, VPU_CMD_ID_ABORT, NULL);
drivers/media/platform/amphion/vpu_cmds.c
383
int vpu_session_rst_buf(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_cmds.c
385
return vpu_session_send_cmd(inst, VPU_CMD_ID_RST_BUF, NULL);
drivers/media/platform/amphion/vpu_cmds.c
388
int vpu_session_fill_timestamp(struct vpu_inst *inst, struct vpu_ts_info *info)
drivers/media/platform/amphion/vpu_cmds.c
390
return vpu_session_send_cmd(inst, VPU_CMD_ID_TIMESTAMP, info);
drivers/media/platform/amphion/vpu_cmds.c
393
int vpu_session_update_parameters(struct vpu_inst *inst, void *arg)
drivers/media/platform/amphion/vpu_cmds.c
395
if (inst->type & VPU_CORE_TYPE_DEC)
drivers/media/platform/amphion/vpu_cmds.c
396
vpu_iface_set_decode_params(inst, arg, 1);
drivers/media/platform/amphion/vpu_cmds.c
398
vpu_iface_set_encode_params(inst, arg, 1);
drivers/media/platform/amphion/vpu_cmds.c
400
return vpu_session_send_cmd(inst, VPU_CMD_ID_UPDATE_PARAMETER, arg);
drivers/media/platform/amphion/vpu_cmds.c
403
int vpu_session_debug(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_cmds.c
405
return vpu_session_send_cmd(inst, VPU_CMD_ID_DEBUG, NULL);
drivers/media/platform/amphion/vpu_cmds.c
410
struct vpu_inst *inst;
drivers/media/platform/amphion/vpu_cmds.c
416
inst = list_first_entry(&core->instances, struct vpu_inst, list);
drivers/media/platform/amphion/vpu_cmds.c
419
ret = vpu_session_send_cmd(inst, VPU_CMD_ID_SNAPSHOT, NULL);
drivers/media/platform/amphion/vpu_cmds.c
80
static struct vpu_cmd_t *vpu_alloc_cmd(struct vpu_inst *inst, u32 id, void *data)
drivers/media/platform/amphion/vpu_cmds.c
97
ret = vpu_iface_pack_cmd(inst->core, cmd->pkt, inst->id, id, data);
drivers/media/platform/amphion/vpu_cmds.c
99
dev_err(inst->dev, "iface pack cmd %s fail\n", vpu_id_name(id));
drivers/media/platform/amphion/vpu_cmds.h
10
int vpu_session_start(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu_cmds.h
11
int vpu_session_stop(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu_cmds.h
12
int vpu_session_abort(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu_cmds.h
13
int vpu_session_rst_buf(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu_cmds.h
14
int vpu_session_encode_frame(struct vpu_inst *inst, s64 timestamp);
drivers/media/platform/amphion/vpu_cmds.h
15
int vpu_session_alloc_fs(struct vpu_inst *inst, struct vpu_fs_info *fs);
drivers/media/platform/amphion/vpu_cmds.h
16
int vpu_session_release_fs(struct vpu_inst *inst, struct vpu_fs_info *fs);
drivers/media/platform/amphion/vpu_cmds.h
17
int vpu_session_fill_timestamp(struct vpu_inst *inst, struct vpu_ts_info *info);
drivers/media/platform/amphion/vpu_cmds.h
18
int vpu_session_update_parameters(struct vpu_inst *inst, void *arg);
drivers/media/platform/amphion/vpu_cmds.h
21
int vpu_response_cmd(struct vpu_inst *inst, u32 response, u32 handled);
drivers/media/platform/amphion/vpu_cmds.h
22
void vpu_clear_request(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu_cmds.h
23
int vpu_session_debug(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu_cmds.h
9
int vpu_session_configure_codec(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu_core.c
342
struct vpu_inst *vpu_inst_get(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_core.c
344
if (!inst)
drivers/media/platform/amphion/vpu_core.c
347
atomic_inc(&inst->ref_count);
drivers/media/platform/amphion/vpu_core.c
349
return inst;
drivers/media/platform/amphion/vpu_core.c
352
void vpu_inst_put(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_core.c
354
if (!inst)
drivers/media/platform/amphion/vpu_core.c
356
if (atomic_dec_and_test(&inst->ref_count)) {
drivers/media/platform/amphion/vpu_core.c
357
if (inst->release)
drivers/media/platform/amphion/vpu_core.c
358
inst->release(inst);
drivers/media/platform/amphion/vpu_core.c
410
int vpu_inst_register(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_core.c
416
vpu = inst->vpu;
drivers/media/platform/amphion/vpu_core.c
417
core = inst->core;
drivers/media/platform/amphion/vpu_core.c
419
core = vpu_request_core(vpu, inst->type);
drivers/media/platform/amphion/vpu_core.c
422
vpu_core_type_desc(inst->type));
drivers/media/platform/amphion/vpu_core.c
425
inst->core = core;
drivers/media/platform/amphion/vpu_core.c
426
inst->dev = get_device(core->dev);
drivers/media/platform/amphion/vpu_core.c
436
if (inst->id >= 0 && inst->id < core->supported_instance_count)
drivers/media/platform/amphion/vpu_core.c
443
vpu_trace(inst->dev, "[%d] %p\n", ret, inst);
drivers/media/platform/amphion/vpu_core.c
444
inst->id = ret;
drivers/media/platform/amphion/vpu_core.c
445
list_add_tail(&inst->list, &core->instances);
drivers/media/platform/amphion/vpu_core.c
448
inst->act.phys = core->act.phys + core->res->act_size * inst->id;
drivers/media/platform/amphion/vpu_core.c
449
inst->act.virt = core->act.virt + core->res->act_size * inst->id;
drivers/media/platform/amphion/vpu_core.c
450
inst->act.length = core->res->act_size;
drivers/media/platform/amphion/vpu_core.c
452
vpu_inst_create_dbgfs_file(inst);
drivers/media/platform/amphion/vpu_core.c
461
int vpu_inst_unregister(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_core.c
465
if (!inst->core)
drivers/media/platform/amphion/vpu_core.c
468
core = inst->core;
drivers/media/platform/amphion/vpu_core.c
469
vpu_clear_request(inst);
drivers/media/platform/amphion/vpu_core.c
471
if (inst->id >= 0 && inst->id < core->supported_instance_count) {
drivers/media/platform/amphion/vpu_core.c
472
vpu_inst_remove_dbgfs_file(inst);
drivers/media/platform/amphion/vpu_core.c
473
list_del_init(&inst->list);
drivers/media/platform/amphion/vpu_core.c
474
vpu_core_release_instance(core, inst->id);
drivers/media/platform/amphion/vpu_core.c
475
inst->id = VPU_INST_NULL_ID;
drivers/media/platform/amphion/vpu_core.c
497
struct vpu_inst *inst = NULL;
drivers/media/platform/amphion/vpu_core.c
505
inst = vpu_inst_get(tmp);
drivers/media/platform/amphion/vpu_core.c
512
return inst;
drivers/media/platform/amphion/vpu_core.c
515
const struct vpu_core_resources *vpu_get_resource(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_core.c
521
if (!inst || !inst->vpu)
drivers/media/platform/amphion/vpu_core.c
524
if (inst->core && inst->core->res)
drivers/media/platform/amphion/vpu_core.c
525
return inst->core->res;
drivers/media/platform/amphion/vpu_core.c
527
vpu = inst->vpu;
drivers/media/platform/amphion/vpu_core.c
530
if (core->type == inst->type) {
drivers/media/platform/amphion/vpu_core.c
730
struct vpu_inst *inst = NULL;
drivers/media/platform/amphion/vpu_core.c
736
list_for_each_entry(inst, &core->instances, list)
drivers/media/platform/amphion/vpu_core.c
737
cancel_work_sync(&inst->msg_work);
drivers/media/platform/amphion/vpu_core.c
743
struct vpu_inst *inst = NULL;
drivers/media/platform/amphion/vpu_core.c
750
list_for_each_entry(inst, &core->instances, list)
drivers/media/platform/amphion/vpu_core.c
751
queue_work(inst->workqueue, &inst->msg_work);
drivers/media/platform/amphion/vpu_dbg.c
101
for (i = 0; i < inst->out_format.mem_planes; i++) {
drivers/media/platform/amphion/vpu_dbg.c
103
vpu_get_fmt_plane_size(&inst->out_format, i),
drivers/media/platform/amphion/vpu_dbg.c
104
inst->out_format.bytesperline[i]);
drivers/media/platform/amphion/vpu_dbg.c
111
vq = v4l2_m2m_get_dst_vq(inst->fh.m2m_ctx);
drivers/media/platform/amphion/vpu_dbg.c
116
inst->cap_format.pixfmt,
drivers/media/platform/amphion/vpu_dbg.c
117
inst->cap_format.pixfmt >> 8,
drivers/media/platform/amphion/vpu_dbg.c
118
inst->cap_format.pixfmt >> 16,
drivers/media/platform/amphion/vpu_dbg.c
119
inst->cap_format.pixfmt >> 24,
drivers/media/platform/amphion/vpu_dbg.c
120
inst->cap_format.width,
drivers/media/platform/amphion/vpu_dbg.c
121
inst->cap_format.height,
drivers/media/platform/amphion/vpu_dbg.c
125
for (i = 0; i < inst->cap_format.mem_planes; i++) {
drivers/media/platform/amphion/vpu_dbg.c
127
vpu_get_fmt_plane_size(&inst->cap_format, i),
drivers/media/platform/amphion/vpu_dbg.c
128
inst->cap_format.bytesperline[i]);
drivers/media/platform/amphion/vpu_dbg.c
135
inst->crop.left,
drivers/media/platform/amphion/vpu_dbg.c
136
inst->crop.top,
drivers/media/platform/amphion/vpu_dbg.c
137
inst->crop.width,
drivers/media/platform/amphion/vpu_dbg.c
138
inst->crop.height);
drivers/media/platform/amphion/vpu_dbg.c
142
vq = v4l2_m2m_get_src_vq(inst->fh.m2m_ctx);
drivers/media/platform/amphion/vpu_dbg.c
164
vq = v4l2_m2m_get_dst_vq(inst->fh.m2m_ctx);
drivers/media/platform/amphion/vpu_dbg.c
198
num = scnprintf(str, sizeof(str), "sequence = %d\n", inst->sequence);
drivers/media/platform/amphion/vpu_dbg.c
202
if (inst->use_stream_buffer) {
drivers/media/platform/amphion/vpu_dbg.c
204
vpu_helper_get_used_space(inst),
drivers/media/platform/amphion/vpu_dbg.c
205
inst->stream_buffer.length,
drivers/media/platform/amphion/vpu_dbg.c
206
&inst->stream_buffer.phys,
drivers/media/platform/amphion/vpu_dbg.c
207
inst->stream_buffer.length);
drivers/media/platform/amphion/vpu_dbg.c
211
num = scnprintf(str, sizeof(str), "kfifo len = 0x%x\n", kfifo_len(&inst->msg_fifo));
drivers/media/platform/amphion/vpu_dbg.c
219
mutex_lock(&inst->core->cmd_lock);
drivers/media/platform/amphion/vpu_dbg.c
220
for (i = 0; i < ARRAY_SIZE(inst->flows); i++) {
drivers/media/platform/amphion/vpu_dbg.c
221
u32 idx = (inst->flow_idx + i) % (ARRAY_SIZE(inst->flows));
drivers/media/platform/amphion/vpu_dbg.c
223
if (!inst->flows[idx])
drivers/media/platform/amphion/vpu_dbg.c
226
inst->flows[idx] >= VPU_MSG_ID_NOOP ? "M" : "C",
drivers/media/platform/amphion/vpu_dbg.c
227
vpu_id_name(inst->flows[idx]));
drivers/media/platform/amphion/vpu_dbg.c
229
mutex_unlock(&inst->core->cmd_lock);
drivers/media/platform/amphion/vpu_dbg.c
233
mutex_unlock(&inst->core->cmd_lock);
drivers/media/platform/amphion/vpu_dbg.c
237
num = call_vop(inst, get_debug_info, str, sizeof(str), i++);
drivers/media/platform/amphion/vpu_dbg.c
373
struct vpu_inst *inst = s->private;
drivers/media/platform/amphion/vpu_dbg.c
375
vpu_session_debug(inst);
drivers/media/platform/amphion/vpu_dbg.c
434
int vpu_inst_create_dbgfs_file(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_dbg.c
439
if (!inst || !inst->core || !inst->core->vpu)
drivers/media/platform/amphion/vpu_dbg.c
442
vpu = inst->core->vpu;
drivers/media/platform/amphion/vpu_dbg.c
446
if (inst->debugfs)
drivers/media/platform/amphion/vpu_dbg.c
449
scnprintf(name, sizeof(name), "instance.%d.%d", inst->core->id, inst->id);
drivers/media/platform/amphion/vpu_dbg.c
450
inst->debugfs = debugfs_create_file((const char *)name,
drivers/media/platform/amphion/vpu_dbg.c
453
inst,
drivers/media/platform/amphion/vpu_dbg.c
459
int vpu_inst_remove_dbgfs_file(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_dbg.c
461
if (!inst)
drivers/media/platform/amphion/vpu_dbg.c
464
debugfs_remove(inst->debugfs);
drivers/media/platform/amphion/vpu_dbg.c
465
inst->debugfs = NULL;
drivers/media/platform/amphion/vpu_dbg.c
514
void vpu_inst_record_flow(struct vpu_inst *inst, u32 flow)
drivers/media/platform/amphion/vpu_dbg.c
516
if (!inst)
drivers/media/platform/amphion/vpu_dbg.c
519
inst->flows[inst->flow_idx] = flow;
drivers/media/platform/amphion/vpu_dbg.c
520
inst->flow_idx = (inst->flow_idx + 1) % (ARRAY_SIZE(inst->flows));
drivers/media/platform/amphion/vpu_dbg.c
63
struct vpu_inst *inst = s->private;
drivers/media/platform/amphion/vpu_dbg.c
69
if (!inst->fh.m2m_ctx)
drivers/media/platform/amphion/vpu_dbg.c
71
num = scnprintf(str, sizeof(str), "[%s]\n", vpu_core_type_desc(inst->type));
drivers/media/platform/amphion/vpu_dbg.c
75
num = scnprintf(str, sizeof(str), "tgig = %d,pid = %d\n", inst->tgid, inst->pid);
drivers/media/platform/amphion/vpu_dbg.c
78
num = scnprintf(str, sizeof(str), "state = %s\n", vpu_codec_state_name(inst->state));
drivers/media/platform/amphion/vpu_dbg.c
83
inst->min_buffer_out, inst->min_buffer_cap);
drivers/media/platform/amphion/vpu_dbg.c
87
vq = v4l2_m2m_get_src_vq(inst->fh.m2m_ctx);
drivers/media/platform/amphion/vpu_dbg.c
92
inst->out_format.pixfmt,
drivers/media/platform/amphion/vpu_dbg.c
93
inst->out_format.pixfmt >> 8,
drivers/media/platform/amphion/vpu_dbg.c
94
inst->out_format.pixfmt >> 16,
drivers/media/platform/amphion/vpu_dbg.c
95
inst->out_format.pixfmt >> 24,
drivers/media/platform/amphion/vpu_dbg.c
96
inst->out_format.width,
drivers/media/platform/amphion/vpu_dbg.c
97
inst->out_format.height,
drivers/media/platform/amphion/vpu_helpers.c
101
for (pfmt = inst->formats; pfmt->pixfmt; pfmt++) {
drivers/media/platform/amphion/vpu_helpers.c
102
if (!vpu_iface_check_format(inst, pfmt->pixfmt))
drivers/media/platform/amphion/vpu_helpers.c
115
u32 vpu_helper_valid_frame_width(struct vpu_inst *inst, u32 width)
drivers/media/platform/amphion/vpu_helpers.c
119
if (!inst)
drivers/media/platform/amphion/vpu_helpers.c
122
res = vpu_get_resource(inst);
drivers/media/platform/amphion/vpu_helpers.c
133
u32 vpu_helper_valid_frame_height(struct vpu_inst *inst, u32 height)
drivers/media/platform/amphion/vpu_helpers.c
137
if (!inst)
drivers/media/platform/amphion/vpu_helpers.c
140
res = vpu_get_resource(inst);
drivers/media/platform/amphion/vpu_helpers.c
31
bool vpu_helper_check_type(struct vpu_inst *inst, u32 type)
drivers/media/platform/amphion/vpu_helpers.c
340
u32 vpu_helper_get_free_space(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_helpers.c
344
if (vpu_iface_get_stream_buffer_desc(inst, &desc))
drivers/media/platform/amphion/vpu_helpers.c
35
for (pfmt = inst->formats; pfmt->pixfmt; pfmt++) {
drivers/media/platform/amphion/vpu_helpers.c
355
u32 vpu_helper_get_used_space(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_helpers.c
359
if (vpu_iface_get_stream_buffer_desc(inst, &desc))
drivers/media/platform/amphion/vpu_helpers.c
36
if (!vpu_iface_check_format(inst, pfmt->pixfmt))
drivers/media/platform/amphion/vpu_helpers.c
372
struct vpu_inst *inst = ctrl_to_inst(ctrl);
drivers/media/platform/amphion/vpu_helpers.c
376
ctrl->val = inst->min_buffer_cap;
drivers/media/platform/amphion/vpu_helpers.c
379
ctrl->val = inst->min_buffer_out;
drivers/media/platform/amphion/vpu_helpers.c
45
const struct vpu_format *vpu_helper_find_format(struct vpu_inst *inst, u32 type, u32 pixelfmt)
drivers/media/platform/amphion/vpu_helpers.c
49
if (!inst || !inst->formats)
drivers/media/platform/amphion/vpu_helpers.c
52
if (!vpu_iface_check_format(inst, pixelfmt))
drivers/media/platform/amphion/vpu_helpers.c
55
for (pfmt = inst->formats; pfmt->pixfmt; pfmt++) {
drivers/media/platform/amphion/vpu_helpers.c
63
const struct vpu_format *vpu_helper_find_sibling(struct vpu_inst *inst, u32 type, u32 pixelfmt)
drivers/media/platform/amphion/vpu_helpers.c
68
fmt = vpu_helper_find_format(inst, type, pixelfmt);
drivers/media/platform/amphion/vpu_helpers.c
72
sibling = vpu_helper_find_format(inst, type, fmt->sibling);
drivers/media/platform/amphion/vpu_helpers.c
80
bool vpu_helper_match_format(struct vpu_inst *inst, u32 type, u32 fmta, u32 fmtb)
drivers/media/platform/amphion/vpu_helpers.c
87
sibling = vpu_helper_find_sibling(inst, type, fmta);
drivers/media/platform/amphion/vpu_helpers.c
93
const struct vpu_format *vpu_helper_enum_format(struct vpu_inst *inst, u32 type, int index)
drivers/media/platform/amphion/vpu_helpers.c
98
if (!inst || !inst->formats)
drivers/media/platform/amphion/vpu_helpers.h
17
bool vpu_helper_check_type(struct vpu_inst *inst, u32 type);
drivers/media/platform/amphion/vpu_helpers.h
18
const struct vpu_format *vpu_helper_find_format(struct vpu_inst *inst, u32 type, u32 pixelfmt);
drivers/media/platform/amphion/vpu_helpers.h
19
const struct vpu_format *vpu_helper_find_sibling(struct vpu_inst *inst, u32 type, u32 pixelfmt);
drivers/media/platform/amphion/vpu_helpers.h
20
bool vpu_helper_match_format(struct vpu_inst *inst, u32 type, u32 fmta, u32 fmtb);
drivers/media/platform/amphion/vpu_helpers.h
21
const struct vpu_format *vpu_helper_enum_format(struct vpu_inst *inst, u32 type, int index);
drivers/media/platform/amphion/vpu_helpers.h
22
u32 vpu_helper_valid_frame_width(struct vpu_inst *inst, u32 width);
drivers/media/platform/amphion/vpu_helpers.h
23
u32 vpu_helper_valid_frame_height(struct vpu_inst *inst, u32 height);
drivers/media/platform/amphion/vpu_helpers.h
32
u32 vpu_helper_get_free_space(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu_helpers.h
33
u32 vpu_helper_get_used_space(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu_malone.c
1305
scode->inst->out_format.width,
drivers/media/platform/amphion/vpu_malone.c
1306
scode->inst->out_format.height);
drivers/media/platform/amphion/vpu_malone.c
1307
ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
drivers/media/platform/amphion/vpu_malone.c
1325
scode->inst->out_format.width,
drivers/media/platform/amphion/vpu_malone.c
1326
scode->inst->out_format.height);
drivers/media/platform/amphion/vpu_malone.c
1327
ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
drivers/media/platform/amphion/vpu_malone.c
1338
if (!scode->inst->total_input_count)
drivers/media/platform/amphion/vpu_malone.c
1351
if (scode->inst->total_input_count == 0)
drivers/media/platform/amphion/vpu_malone.c
1357
ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
drivers/media/platform/amphion/vpu_malone.c
1372
if (scode->inst->total_input_count)
drivers/media/platform/amphion/vpu_malone.c
1383
scode->inst->out_format.width,
drivers/media/platform/amphion/vpu_malone.c
1384
scode->inst->out_format.height);
drivers/media/platform/amphion/vpu_malone.c
1385
ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
drivers/media/platform/amphion/vpu_malone.c
1409
ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
drivers/media/platform/amphion/vpu_malone.c
1431
scode->inst->out_format.width,
drivers/media/platform/amphion/vpu_malone.c
1432
scode->inst->out_format.height);
drivers/media/platform/amphion/vpu_malone.c
1433
ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
drivers/media/platform/amphion/vpu_malone.c
1456
ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
drivers/media/platform/amphion/vpu_malone.c
1518
if (!scode || !scode->inst || !scode->vb)
drivers/media/platform/amphion/vpu_malone.c
1522
handler = get_scode_handler(scode->inst->out_format.pixfmt);
drivers/media/platform/amphion/vpu_malone.c
1543
struct vpu_inst *inst, struct vb2_buffer *vb,
drivers/media/platform/amphion/vpu_malone.c
1553
scode.inst = inst;
drivers/media/platform/amphion/vpu_malone.c
1575
ret = vpu_helper_copy_to_stream_buffer(&inst->stream_buffer,
drivers/media/platform/amphion/vpu_malone.c
1594
ret = vpu_malone_add_scode(inst->core->iface,
drivers/media/platform/amphion/vpu_malone.c
1595
inst->id,
drivers/media/platform/amphion/vpu_malone.c
1596
&inst->stream_buffer,
drivers/media/platform/amphion/vpu_malone.c
1597
inst->out_format.pixfmt,
drivers/media/platform/amphion/vpu_malone.c
1608
struct vpu_inst *inst, struct vb2_buffer *vb)
drivers/media/platform/amphion/vpu_malone.c
1613
ret = vpu_helper_copy_to_stream_buffer(&inst->stream_buffer,
drivers/media/platform/amphion/vpu_malone.c
1625
static int vpu_malone_input_ts(struct vpu_inst *inst, s64 timestamp, u32 size)
drivers/media/platform/amphion/vpu_malone.c
1633
return vpu_session_fill_timestamp(inst, &info);
drivers/media/platform/amphion/vpu_malone.c
1637
struct vpu_inst *inst, struct vb2_buffer *vb)
drivers/media/platform/amphion/vpu_malone.c
1640
struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[inst->id];
drivers/media/platform/amphion/vpu_malone.c
1641
u32 disp_imm = hc->codec_param[inst->id].disp_imm;
drivers/media/platform/amphion/vpu_malone.c
1645
if (vpu_malone_is_non_frame_mode(shared, inst->id))
drivers/media/platform/amphion/vpu_malone.c
1646
ret = vpu_malone_input_stream_data(str_buf, inst, vb);
drivers/media/platform/amphion/vpu_malone.c
1648
ret = vpu_malone_input_frame_data(str_buf, inst, vb, disp_imm);
drivers/media/platform/amphion/vpu_malone.c
1653
if (inst->extra_size) {
drivers/media/platform/amphion/vpu_malone.c
1654
size += inst->extra_size;
drivers/media/platform/amphion/vpu_malone.c
1655
inst->extra_size = 0;
drivers/media/platform/amphion/vpu_malone.c
1658
ret = vpu_malone_input_ts(inst, vb->timestamp, size);
drivers/media/platform/amphion/vpu_malone.c
322
struct vpu_inst *inst;
drivers/media/platform/amphion/vpu_malone.h
37
struct vpu_inst *inst, struct vb2_buffer *vb);
drivers/media/platform/amphion/vpu_msgs.c
100
static void vpu_session_handle_frame_release(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
drivers/media/platform/amphion/vpu_msgs.c
102
if (inst->core->type == VPU_CORE_TYPE_ENC) {
drivers/media/platform/amphion/vpu_msgs.c
106
vpu_iface_unpack_msg_data(inst->core, pkt, (void *)&info.sequence);
drivers/media/platform/amphion/vpu_msgs.c
107
dev_dbg(inst->dev, "[%d] %d\n", inst->id, info.sequence);
drivers/media/platform/amphion/vpu_msgs.c
108
info.type = inst->out_format.type;
drivers/media/platform/amphion/vpu_msgs.c
109
call_void_vop(inst, buf_done, &info);
drivers/media/platform/amphion/vpu_msgs.c
110
} else if (inst->core->type == VPU_CORE_TYPE_DEC) {
drivers/media/platform/amphion/vpu_msgs.c
113
vpu_iface_unpack_msg_data(inst->core, pkt, &fs);
drivers/media/platform/amphion/vpu_msgs.c
114
call_void_vop(inst, event_notify, VPU_MSG_ID_FRAME_RELEASE, &fs);
drivers/media/platform/amphion/vpu_msgs.c
118
static void vpu_session_handle_input_done(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
drivers/media/platform/amphion/vpu_msgs.c
120
dev_dbg(inst->dev, "[%d]\n", inst->id);
drivers/media/platform/amphion/vpu_msgs.c
121
call_void_vop(inst, input_done);
drivers/media/platform/amphion/vpu_msgs.c
124
static void vpu_session_handle_pic_decoded(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
drivers/media/platform/amphion/vpu_msgs.c
128
vpu_iface_unpack_msg_data(inst->core, pkt, (void *)&info);
drivers/media/platform/amphion/vpu_msgs.c
129
call_void_vop(inst, get_one_frame, &info);
drivers/media/platform/amphion/vpu_msgs.c
132
static void vpu_session_handle_pic_done(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
drivers/media/platform/amphion/vpu_msgs.c
138
vpu_iface_unpack_msg_data(inst->core, pkt, (void *)&info);
drivers/media/platform/amphion/vpu_msgs.c
139
if (inst->core->type == VPU_CORE_TYPE_DEC)
drivers/media/platform/amphion/vpu_msgs.c
140
frame.type = inst->cap_format.type;
drivers/media/platform/amphion/vpu_msgs.c
146
call_void_vop(inst, buf_done, &frame);
drivers/media/platform/amphion/vpu_msgs.c
149
static void vpu_session_handle_eos(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
drivers/media/platform/amphion/vpu_msgs.c
151
call_void_vop(inst, event_notify, VPU_MSG_ID_PIC_EOS, NULL);
drivers/media/platform/amphion/vpu_msgs.c
154
static void vpu_session_handle_error(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
drivers/media/platform/amphion/vpu_msgs.c
159
dev_err(inst->dev, "instance %d firmware error : %s\n", inst->id, str);
drivers/media/platform/amphion/vpu_msgs.c
161
dev_err(inst->dev, "instance %d is unsupported stream\n", inst->id);
drivers/media/platform/amphion/vpu_msgs.c
162
call_void_vop(inst, event_notify, VPU_MSG_ID_UNSUPPORTED, NULL);
drivers/media/platform/amphion/vpu_msgs.c
163
vpu_v4l2_set_error(inst);
drivers/media/platform/amphion/vpu_msgs.c
166
static void vpu_session_handle_firmware_xcpt(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
drivers/media/platform/amphion/vpu_msgs.c
170
dev_err(inst->dev, "%s firmware xcpt: %s\n",
drivers/media/platform/amphion/vpu_msgs.c
171
vpu_core_type_desc(inst->core->type), str);
drivers/media/platform/amphion/vpu_msgs.c
172
call_void_vop(inst, event_notify, VPU_MSG_ID_FIRMWARE_XCPT, NULL);
drivers/media/platform/amphion/vpu_msgs.c
173
set_bit(inst->id, &inst->core->hang_mask);
drivers/media/platform/amphion/vpu_msgs.c
174
vpu_v4l2_set_error(inst);
drivers/media/platform/amphion/vpu_msgs.c
177
static void vpu_session_handle_pic_skipped(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
drivers/media/platform/amphion/vpu_msgs.c
179
vpu_inst_lock(inst);
drivers/media/platform/amphion/vpu_msgs.c
180
vpu_skip_frame(inst, 1);
drivers/media/platform/amphion/vpu_msgs.c
181
vpu_inst_unlock(inst);
drivers/media/platform/amphion/vpu_msgs.c
184
static void vpu_session_handle_dbg_msg(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
drivers/media/platform/amphion/vpu_msgs.c
189
dev_info(inst->dev, "instance %d firmware dbg msg : %s\n", inst->id, str);
drivers/media/platform/amphion/vpu_msgs.c
218
static int vpu_session_handle_msg(struct vpu_inst *inst, struct vpu_rpc_event *msg)
drivers/media/platform/amphion/vpu_msgs.c
225
ret = vpu_iface_convert_msg_id(inst->core, msg->hdr.id);
drivers/media/platform/amphion/vpu_msgs.c
230
dev_dbg(inst->dev, "[%d] receive event(%s)\n", inst->id, vpu_id_name(msg_id));
drivers/media/platform/amphion/vpu_msgs.c
243
handler->done(inst, msg);
drivers/media/platform/amphion/vpu_msgs.c
246
vpu_response_cmd(inst, msg_id, 1);
drivers/media/platform/amphion/vpu_msgs.c
25
void (*done)(struct vpu_inst *inst, struct vpu_rpc_event *pkt);
drivers/media/platform/amphion/vpu_msgs.c
251
static bool vpu_inst_receive_msg(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
drivers/media/platform/amphion/vpu_msgs.c
257
if (kfifo_len(&inst->msg_fifo) < bytes)
drivers/media/platform/amphion/vpu_msgs.c
260
ret = kfifo_out(&inst->msg_fifo, pkt, bytes);
drivers/media/platform/amphion/vpu_msgs.c
266
ret = kfifo_out(&inst->msg_fifo, pkt->data, bytes);
drivers/media/platform/amphion/vpu_msgs.c
276
struct vpu_inst *inst = container_of(work, struct vpu_inst, msg_work);
drivers/media/platform/amphion/vpu_msgs.c
279
while (vpu_inst_receive_msg(inst, &pkt))
drivers/media/platform/amphion/vpu_msgs.c
280
vpu_session_handle_msg(inst, &pkt);
drivers/media/platform/amphion/vpu_msgs.c
283
static void vpu_inst_handle_msg(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
drivers/media/platform/amphion/vpu_msgs.c
289
if (!inst->workqueue)
drivers/media/platform/amphion/vpu_msgs.c
29
static void vpu_session_handle_start_done(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
drivers/media/platform/amphion/vpu_msgs.c
293
ret = kfifo_in(&inst->msg_fifo, pkt, bytes);
drivers/media/platform/amphion/vpu_msgs.c
295
dev_err(inst->dev, "[%d:%d]overflow: %d\n", inst->core->id, inst->id, id);
drivers/media/platform/amphion/vpu_msgs.c
296
queue_work(inst->workqueue, &inst->msg_work);
drivers/media/platform/amphion/vpu_msgs.c
302
struct vpu_inst *inst;
drivers/media/platform/amphion/vpu_msgs.c
31
vpu_trace(inst->dev, "[%d]\n", inst->id);
drivers/media/platform/amphion/vpu_msgs.c
314
inst = vpu_core_find_instance(core, pkt.hdr.index);
drivers/media/platform/amphion/vpu_msgs.c
315
if (inst) {
drivers/media/platform/amphion/vpu_msgs.c
316
vpu_response_cmd(inst, ret, 0);
drivers/media/platform/amphion/vpu_msgs.c
318
vpu_inst_record_flow(inst, ret);
drivers/media/platform/amphion/vpu_msgs.c
321
vpu_inst_handle_msg(inst, &pkt);
drivers/media/platform/amphion/vpu_msgs.c
322
vpu_inst_put(inst);
drivers/media/platform/amphion/vpu_msgs.c
34
static void vpu_session_handle_mem_request(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
drivers/media/platform/amphion/vpu_msgs.c
38
vpu_iface_unpack_msg_data(inst->core, pkt, (void *)&req_data);
drivers/media/platform/amphion/vpu_msgs.c
389
struct vpu_inst *inst = vpu_core_find_instance(core, i);
drivers/media/platform/amphion/vpu_msgs.c
39
vpu_trace(inst->dev, "[%d] %d:%d %d:%d %d:%d\n",
drivers/media/platform/amphion/vpu_msgs.c
391
if (!inst)
drivers/media/platform/amphion/vpu_msgs.c
394
if (inst->workqueue && kfifo_len(&inst->msg_fifo) >= bytes)
drivers/media/platform/amphion/vpu_msgs.c
395
queue_work(inst->workqueue, &inst->msg_work);
drivers/media/platform/amphion/vpu_msgs.c
397
vpu_inst_put(inst);
drivers/media/platform/amphion/vpu_msgs.c
40
inst->id,
drivers/media/platform/amphion/vpu_msgs.c
47
vpu_inst_lock(inst);
drivers/media/platform/amphion/vpu_msgs.c
48
call_void_vop(inst, mem_request,
drivers/media/platform/amphion/vpu_msgs.c
55
vpu_inst_unlock(inst);
drivers/media/platform/amphion/vpu_msgs.c
58
static void vpu_session_handle_stop_done(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
drivers/media/platform/amphion/vpu_msgs.c
60
vpu_trace(inst->dev, "[%d]\n", inst->id);
drivers/media/platform/amphion/vpu_msgs.c
62
call_void_vop(inst, stop_done);
drivers/media/platform/amphion/vpu_msgs.c
65
static void vpu_session_handle_seq_hdr(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
drivers/media/platform/amphion/vpu_msgs.c
71
res = vpu_get_resource(inst);
drivers/media/platform/amphion/vpu_msgs.c
73
vpu_iface_unpack_msg_data(inst->core, pkt, (void *)&info);
drivers/media/platform/amphion/vpu_msgs.c
74
call_void_vop(inst, event_notify, VPU_MSG_ID_SEQ_HDR_FOUND, &info);
drivers/media/platform/amphion/vpu_msgs.c
77
static void vpu_session_handle_resolution_change(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
drivers/media/platform/amphion/vpu_msgs.c
79
call_void_vop(inst, event_notify, VPU_MSG_ID_RES_CHANGE, NULL);
drivers/media/platform/amphion/vpu_msgs.c
82
static void vpu_session_handle_enc_frame_done(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
drivers/media/platform/amphion/vpu_msgs.c
86
vpu_iface_unpack_msg_data(inst->core, pkt, (void *)&info);
drivers/media/platform/amphion/vpu_msgs.c
87
dev_dbg(inst->dev, "[%d] frame id = %d, wptr = 0x%x, size = %d\n",
drivers/media/platform/amphion/vpu_msgs.c
88
inst->id, info.frame_id, info.wptr, info.frame_size);
drivers/media/platform/amphion/vpu_msgs.c
89
call_void_vop(inst, get_one_frame, &info);
drivers/media/platform/amphion/vpu_msgs.c
92
static void vpu_session_handle_frame_request(struct vpu_inst *inst, struct vpu_rpc_event *pkt)
drivers/media/platform/amphion/vpu_msgs.c
96
vpu_iface_unpack_msg_data(inst->core, pkt, &fs);
drivers/media/platform/amphion/vpu_msgs.c
97
call_void_vop(inst, event_notify, VPU_MSG_ID_FRAME_REQ, &fs);
drivers/media/platform/amphion/vpu_rpc.c
251
struct vpu_iface_ops *vpu_inst_get_iface(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_rpc.c
253
if (inst->core)
drivers/media/platform/amphion/vpu_rpc.c
254
return vpu_core_get_iface(inst->core);
drivers/media/platform/amphion/vpu_rpc.c
256
return vpu_get_iface(inst->vpu, inst->type);
drivers/media/platform/amphion/vpu_rpc.h
115
struct vpu_iface_ops *vpu_inst_get_iface(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu_rpc.h
128
static inline bool vpu_iface_check_format(struct vpu_inst *inst, u32 pixelfmt)
drivers/media/platform/amphion/vpu_rpc.h
130
struct vpu_iface_ops *ops = vpu_inst_get_iface(inst);
drivers/media/platform/amphion/vpu_rpc.h
133
return ops->check_fmt(inst->type, pixelfmt);
drivers/media/platform/amphion/vpu_rpc.h
248
static inline int vpu_iface_config_stream(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_rpc.h
250
struct vpu_iface_ops *ops = vpu_core_get_iface(inst->core);
drivers/media/platform/amphion/vpu_rpc.h
252
if (!ops || inst->id < 0)
drivers/media/platform/amphion/vpu_rpc.h
255
ops->set_stream_cfg(inst->core->iface, inst->id);
drivers/media/platform/amphion/vpu_rpc.h
311
static inline int vpu_iface_input_frame(struct vpu_inst *inst,
drivers/media/platform/amphion/vpu_rpc.h
314
struct vpu_iface_ops *ops = vpu_core_get_iface(inst->core);
drivers/media/platform/amphion/vpu_rpc.h
320
ret = ops->input_frame(inst->core->iface, inst, vb);
drivers/media/platform/amphion/vpu_rpc.h
323
inst->total_input_count++;
drivers/media/platform/amphion/vpu_rpc.h
327
static inline int vpu_iface_config_memory_resource(struct vpu_inst *inst,
drivers/media/platform/amphion/vpu_rpc.h
332
struct vpu_iface_ops *ops = vpu_core_get_iface(inst->core);
drivers/media/platform/amphion/vpu_rpc.h
334
if (!ops || !ops->config_memory_resource || inst->id < 0)
drivers/media/platform/amphion/vpu_rpc.h
337
return ops->config_memory_resource(inst->core->iface,
drivers/media/platform/amphion/vpu_rpc.h
338
inst->id,
drivers/media/platform/amphion/vpu_rpc.h
342
static inline int vpu_iface_config_stream_buffer(struct vpu_inst *inst,
drivers/media/platform/amphion/vpu_rpc.h
345
struct vpu_iface_ops *ops = vpu_core_get_iface(inst->core);
drivers/media/platform/amphion/vpu_rpc.h
347
if (!ops || !ops->config_stream_buffer || inst->id < 0)
drivers/media/platform/amphion/vpu_rpc.h
355
return ops->config_stream_buffer(inst->core->iface, inst->id, buf);
drivers/media/platform/amphion/vpu_rpc.h
358
static inline int vpu_iface_update_stream_buffer(struct vpu_inst *inst,
drivers/media/platform/amphion/vpu_rpc.h
361
struct vpu_iface_ops *ops = vpu_core_get_iface(inst->core);
drivers/media/platform/amphion/vpu_rpc.h
363
if (!ops || !ops->update_stream_buffer || inst->id < 0)
drivers/media/platform/amphion/vpu_rpc.h
366
return ops->update_stream_buffer(inst->core->iface, inst->id, ptr, write);
drivers/media/platform/amphion/vpu_rpc.h
369
static inline int vpu_iface_get_stream_buffer_desc(struct vpu_inst *inst,
drivers/media/platform/amphion/vpu_rpc.h
372
struct vpu_iface_ops *ops = vpu_core_get_iface(inst->core);
drivers/media/platform/amphion/vpu_rpc.h
374
if (!ops || !ops->get_stream_buffer_desc || inst->id < 0)
drivers/media/platform/amphion/vpu_rpc.h
380
return ops->get_stream_buffer_desc(inst->core->iface, inst->id, desc);
drivers/media/platform/amphion/vpu_rpc.h
403
static inline int vpu_iface_set_encode_params(struct vpu_inst *inst,
drivers/media/platform/amphion/vpu_rpc.h
406
struct vpu_iface_ops *ops = vpu_core_get_iface(inst->core);
drivers/media/platform/amphion/vpu_rpc.h
408
if (!ops || !ops->set_encode_params || inst->id < 0)
drivers/media/platform/amphion/vpu_rpc.h
411
return ops->set_encode_params(inst->core->iface, inst->id, params, update);
drivers/media/platform/amphion/vpu_rpc.h
414
static inline int vpu_iface_set_decode_params(struct vpu_inst *inst,
drivers/media/platform/amphion/vpu_rpc.h
417
struct vpu_iface_ops *ops = vpu_core_get_iface(inst->core);
drivers/media/platform/amphion/vpu_rpc.h
419
if (!ops || !ops->set_decode_params || inst->id < 0)
drivers/media/platform/amphion/vpu_rpc.h
422
return ops->set_decode_params(inst->core->iface, inst->id, params, update);
drivers/media/platform/amphion/vpu_rpc.h
425
static inline int vpu_iface_add_scode(struct vpu_inst *inst, u32 scode_type)
drivers/media/platform/amphion/vpu_rpc.h
427
struct vpu_iface_ops *ops = vpu_core_get_iface(inst->core);
drivers/media/platform/amphion/vpu_rpc.h
429
if (!ops || !ops->add_scode || inst->id < 0)
drivers/media/platform/amphion/vpu_rpc.h
432
return ops->add_scode(inst->core->iface, inst->id,
drivers/media/platform/amphion/vpu_rpc.h
433
&inst->stream_buffer,
drivers/media/platform/amphion/vpu_rpc.h
434
inst->out_format.pixfmt,
drivers/media/platform/amphion/vpu_rpc.h
438
static inline int vpu_iface_pre_send_cmd(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_rpc.h
440
struct vpu_iface_ops *ops = vpu_core_get_iface(inst->core);
drivers/media/platform/amphion/vpu_rpc.h
442
if (ops && ops->pre_send_cmd && inst->id >= 0)
drivers/media/platform/amphion/vpu_rpc.h
443
return ops->pre_send_cmd(inst->core->iface, inst->id);
drivers/media/platform/amphion/vpu_rpc.h
447
static inline int vpu_iface_post_send_cmd(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_rpc.h
449
struct vpu_iface_ops *ops = vpu_core_get_iface(inst->core);
drivers/media/platform/amphion/vpu_rpc.h
451
if (ops && ops->post_send_cmd && inst->id >= 0)
drivers/media/platform/amphion/vpu_rpc.h
452
return ops->post_send_cmd(inst->core->iface, inst->id);
drivers/media/platform/amphion/vpu_rpc.h
456
static inline int vpu_iface_init_instance(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_rpc.h
458
struct vpu_iface_ops *ops = vpu_core_get_iface(inst->core);
drivers/media/platform/amphion/vpu_rpc.h
460
if (ops && ops->init_instance && inst->id >= 0)
drivers/media/platform/amphion/vpu_rpc.h
461
return ops->init_instance(inst->core->iface, inst->id);
drivers/media/platform/amphion/vpu_rpc.h
70
struct vpu_inst *inst, struct vb2_buffer *vb);
drivers/media/platform/amphion/vpu_v4l2.c
102
int vpu_notify_source_change(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_v4l2.c
109
vpu_trace(inst->dev, "[%d]\n", inst->id);
drivers/media/platform/amphion/vpu_v4l2.c
110
v4l2_event_queue_fh(&inst->fh, &ev);
drivers/media/platform/amphion/vpu_v4l2.c
114
int vpu_set_last_buffer_dequeued(struct vpu_inst *inst, bool eos)
drivers/media/platform/amphion/vpu_v4l2.c
118
if (!inst || !inst->fh.m2m_ctx)
drivers/media/platform/amphion/vpu_v4l2.c
121
q = v4l2_m2m_get_dst_vq(inst->fh.m2m_ctx);
drivers/media/platform/amphion/vpu_v4l2.c
127
vpu_trace(inst->dev, "last buffer dequeued\n");
drivers/media/platform/amphion/vpu_v4l2.c
131
vpu_notify_eos(inst);
drivers/media/platform/amphion/vpu_v4l2.c
135
bool vpu_is_source_empty(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_v4l2.c
139
if (!inst->fh.m2m_ctx)
drivers/media/platform/amphion/vpu_v4l2.c
141
v4l2_m2m_for_each_src_buf(inst->fh.m2m_ctx, buf) {
drivers/media/platform/amphion/vpu_v4l2.c
148
static int vpu_init_format(struct vpu_inst *inst, struct vpu_format *fmt)
drivers/media/platform/amphion/vpu_v4l2.c
152
info = vpu_helper_find_format(inst, fmt->type, fmt->pixfmt);
drivers/media/platform/amphion/vpu_v4l2.c
154
info = vpu_helper_enum_format(inst, fmt->type, 0);
drivers/media/platform/amphion/vpu_v4l2.c
190
static int vpu_calc_fmt_sizeimage(struct vpu_inst *inst, struct vpu_format *fmt)
drivers/media/platform/amphion/vpu_v4l2.c
196
const struct vpu_core_resources *res = vpu_get_resource(inst);
drivers/media/platform/amphion/vpu_v4l2.c
240
int vpu_try_fmt_common(struct vpu_inst *inst, struct v4l2_format *f, struct vpu_format *fmt)
drivers/media/platform/amphion/vpu_v4l2.c
248
ret = vpu_init_format(inst, fmt);
drivers/media/platform/amphion/vpu_v4l2.c
255
fmt->width = vpu_helper_valid_frame_width(inst, fmt->width);
drivers/media/platform/amphion/vpu_v4l2.c
257
fmt->height = vpu_helper_valid_frame_height(inst, fmt->height);
drivers/media/platform/amphion/vpu_v4l2.c
260
vpu_calc_fmt_sizeimage(inst, fmt);
drivers/media/platform/amphion/vpu_v4l2.c
280
static bool vpu_check_ready(struct vpu_inst *inst, u32 type)
drivers/media/platform/amphion/vpu_v4l2.c
282
if (!inst)
drivers/media/platform/amphion/vpu_v4l2.c
284
if (inst->state == VPU_CODEC_STATE_DEINIT || inst->id < 0)
drivers/media/platform/amphion/vpu_v4l2.c
286
if (!inst->ops->check_ready)
drivers/media/platform/amphion/vpu_v4l2.c
288
return call_vop(inst, check_ready, type);
drivers/media/platform/amphion/vpu_v4l2.c
291
int vpu_process_output_buffer(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_v4l2.c
296
if (!inst || !inst->fh.m2m_ctx)
drivers/media/platform/amphion/vpu_v4l2.c
299
if (!vpu_check_ready(inst, inst->out_format.type))
drivers/media/platform/amphion/vpu_v4l2.c
302
v4l2_m2m_for_each_src_buf(inst->fh.m2m_ctx, buf) {
drivers/media/platform/amphion/vpu_v4l2.c
312
dev_dbg(inst->dev, "[%d]frame id = %d / %d\n",
drivers/media/platform/amphion/vpu_v4l2.c
313
inst->id, vbuf->sequence, inst->sequence);
drivers/media/platform/amphion/vpu_v4l2.c
314
return call_vop(inst, process_output, &vbuf->vb2_buf);
drivers/media/platform/amphion/vpu_v4l2.c
317
int vpu_process_capture_buffer(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_v4l2.c
32
void vpu_inst_lock(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_v4l2.c
322
if (!inst || !inst->fh.m2m_ctx)
drivers/media/platform/amphion/vpu_v4l2.c
325
if (!vpu_check_ready(inst, inst->cap_format.type))
drivers/media/platform/amphion/vpu_v4l2.c
328
v4l2_m2m_for_each_dst_buf(inst->fh.m2m_ctx, buf) {
drivers/media/platform/amphion/vpu_v4l2.c
337
return call_vop(inst, process_capture, &vbuf->vb2_buf);
drivers/media/platform/amphion/vpu_v4l2.c
34
mutex_lock(&inst->lock);
drivers/media/platform/amphion/vpu_v4l2.c
340
struct vb2_v4l2_buffer *vpu_next_src_buf(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_v4l2.c
344
if (!inst->fh.m2m_ctx)
drivers/media/platform/amphion/vpu_v4l2.c
347
src_buf = v4l2_m2m_next_src_buf(inst->fh.m2m_ctx);
drivers/media/platform/amphion/vpu_v4l2.c
354
void vpu_skip_frame(struct vpu_inst *inst, int count)
drivers/media/platform/amphion/vpu_v4l2.c
360
if (count <= 0 || !inst->fh.m2m_ctx)
drivers/media/platform/amphion/vpu_v4l2.c
364
src_buf = v4l2_m2m_src_buf_remove(inst->fh.m2m_ctx);
drivers/media/platform/amphion/vpu_v4l2.c
37
void vpu_inst_unlock(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_v4l2.c
377
struct vb2_v4l2_buffer *vpu_find_buf_by_sequence(struct vpu_inst *inst, u32 type, u32 sequence)
drivers/media/platform/amphion/vpu_v4l2.c
382
if (!inst || !inst->fh.m2m_ctx)
drivers/media/platform/amphion/vpu_v4l2.c
386
v4l2_m2m_for_each_src_buf(inst->fh.m2m_ctx, buf) {
drivers/media/platform/amphion/vpu_v4l2.c
39
mutex_unlock(&inst->lock);
drivers/media/platform/amphion/vpu_v4l2.c
393
v4l2_m2m_for_each_dst_buf(inst->fh.m2m_ctx, buf) {
drivers/media/platform/amphion/vpu_v4l2.c
404
struct vb2_v4l2_buffer *vpu_find_buf_by_idx(struct vpu_inst *inst, u32 type, u32 idx)
drivers/media/platform/amphion/vpu_v4l2.c
409
if (!inst || !inst->fh.m2m_ctx)
drivers/media/platform/amphion/vpu_v4l2.c
413
v4l2_m2m_for_each_src_buf(inst->fh.m2m_ctx, buf) {
drivers/media/platform/amphion/vpu_v4l2.c
420
v4l2_m2m_for_each_dst_buf(inst->fh.m2m_ctx, buf) {
drivers/media/platform/amphion/vpu_v4l2.c
431
int vpu_get_num_buffers(struct vpu_inst *inst, u32 type)
drivers/media/platform/amphion/vpu_v4l2.c
435
if (!inst || !inst->fh.m2m_ctx)
drivers/media/platform/amphion/vpu_v4l2.c
439
q = v4l2_m2m_get_src_vq(inst->fh.m2m_ctx);
drivers/media/platform/amphion/vpu_v4l2.c
441
q = v4l2_m2m_get_dst_vq(inst->fh.m2m_ctx);
drivers/media/platform/amphion/vpu_v4l2.c
466
struct vpu_inst *inst = vb2_get_drv_priv(vq);
drivers/media/platform/amphion/vpu_v4l2.c
470
cur_fmt = vpu_get_format(inst, vq->type);
drivers/media/platform/amphion/vpu_v4l2.c
483
*buf_count = max_t(unsigned int, *buf_count, inst->min_buffer_out);
drivers/media/platform/amphion/vpu_v4l2.c
485
*buf_count = max_t(unsigned int, *buf_count, inst->min_buffer_cap);
drivers/media/platform/amphion/vpu_v4l2.c
490
if (V4L2_TYPE_IS_OUTPUT(vq->type) && inst->state == VPU_CODEC_STATE_SEEK) {
drivers/media/platform/amphion/vpu_v4l2.c
491
vpu_trace(inst->dev, "reinit when VIDIOC_REQBUFS(OUTPUT, 0)\n");
drivers/media/platform/amphion/vpu_v4l2.c
492
call_void_vop(inst, release);
drivers/media/platform/amphion/vpu_v4l2.c
496
call_void_vop(inst, reset_frame_store);
drivers/media/platform/amphion/vpu_v4l2.c
505
struct vpu_inst *inst = vb2_get_drv_priv(vb->vb2_queue);
drivers/media/platform/amphion/vpu_v4l2.c
510
if (!inst->ops->attach_frame_store || V4L2_TYPE_IS_OUTPUT(vb->type))
drivers/media/platform/amphion/vpu_v4l2.c
513
call_void_vop(inst, attach_frame_store, vb);
drivers/media/platform/amphion/vpu_v4l2.c
528
struct vpu_inst *inst = vb2_get_drv_priv(vb->vb2_queue);
drivers/media/platform/amphion/vpu_v4l2.c
533
cur_fmt = vpu_get_format(inst, vb->type);
drivers/media/platform/amphion/vpu_v4l2.c
536
dev_dbg(inst->dev, "[%d] %s buf[%d] is invalid\n",
drivers/media/platform/amphion/vpu_v4l2.c
537
inst->id, vpu_type_name(vb->type), vb->index);
drivers/media/platform/amphion/vpu_v4l2.c
548
struct vpu_inst *inst = vb2_get_drv_priv(vb->vb2_queue);
drivers/media/platform/amphion/vpu_v4l2.c
553
struct v4l2_ctrl *ctrl = v4l2_ctrl_find(&inst->ctrl_handler,
drivers/media/platform/amphion/vpu_v4l2.c
561
vpu_notify_eos(inst);
drivers/media/platform/amphion/vpu_v4l2.c
564
call_void_vop(inst, on_queue_empty, q->type);
drivers/media/platform/amphion/vpu_v4l2.c
567
static void vpu_vb2_buffers_return(struct vpu_inst *inst, unsigned int type,
drivers/media/platform/amphion/vpu_v4l2.c
573
while ((buf = v4l2_m2m_src_buf_remove(inst->fh.m2m_ctx))) {
drivers/media/platform/amphion/vpu_v4l2.c
578
while ((buf = v4l2_m2m_dst_buf_remove(inst->fh.m2m_ctx))) {
drivers/media/platform/amphion/vpu_v4l2.c
587
struct vpu_inst *inst = vb2_get_drv_priv(q);
drivers/media/platform/amphion/vpu_v4l2.c
588
struct vpu_format *fmt = vpu_get_format(inst, q->type);
drivers/media/platform/amphion/vpu_v4l2.c
591
vpu_inst_unlock(inst);
drivers/media/platform/amphion/vpu_v4l2.c
592
ret = vpu_inst_register(inst);
drivers/media/platform/amphion/vpu_v4l2.c
593
vpu_inst_lock(inst);
drivers/media/platform/amphion/vpu_v4l2.c
595
vpu_vb2_buffers_return(inst, q->type, VB2_BUF_STATE_QUEUED);
drivers/media/platform/amphion/vpu_v4l2.c
599
vpu_trace(inst->dev, "[%d] %s %c%c%c%c %dx%d %u(%u) %u(%u) %u(%u) %d\n",
drivers/media/platform/amphion/vpu_v4l2.c
600
inst->id, vpu_type_name(q->type),
drivers/media/platform/amphion/vpu_v4l2.c
611
ret = call_vop(inst, start, q->type);
drivers/media/platform/amphion/vpu_v4l2.c
613
vpu_vb2_buffers_return(inst, q->type, VB2_BUF_STATE_QUEUED);
drivers/media/platform/amphion/vpu_v4l2.c
620
struct vpu_inst *inst = vb2_get_drv_priv(q);
drivers/media/platform/amphion/vpu_v4l2.c
622
vpu_trace(inst->dev, "[%d] %s\n", inst->id, vpu_type_name(q->type));
drivers/media/platform/amphion/vpu_v4l2.c
624
call_void_vop(inst, stop, q->type);
drivers/media/platform/amphion/vpu_v4l2.c
625
vpu_vb2_buffers_return(inst, q->type, VB2_BUF_STATE_ERROR);
drivers/media/platform/amphion/vpu_v4l2.c
627
inst->sequence = 0;
drivers/media/platform/amphion/vpu_v4l2.c
633
struct vpu_inst *inst = vb2_get_drv_priv(vb->vb2_queue);
drivers/media/platform/amphion/vpu_v4l2.c
636
vbuf->sequence = inst->sequence++;
drivers/media/platform/amphion/vpu_v4l2.c
638
v4l2_m2m_buf_queue(inst->fh.m2m_ctx, vbuf);
drivers/media/platform/amphion/vpu_v4l2.c
639
vpu_process_output_buffer(inst);
drivers/media/platform/amphion/vpu_v4l2.c
640
vpu_process_capture_buffer(inst);
drivers/media/platform/amphion/vpu_v4l2.c
656
struct vpu_inst *inst = priv;
drivers/media/platform/amphion/vpu_v4l2.c
660
inst->out_format.type = src_vq->type;
drivers/media/platform/amphion/vpu_v4l2.c
665
if (inst->type == VPU_CORE_TYPE_DEC && inst->use_stream_buffer)
drivers/media/platform/amphion/vpu_v4l2.c
667
src_vq->drv_priv = inst;
drivers/media/platform/amphion/vpu_v4l2.c
669
src_vq->dev = inst->vpu->dev;
drivers/media/platform/amphion/vpu_v4l2.c
670
src_vq->lock = &inst->lock;
drivers/media/platform/amphion/vpu_v4l2.c
676
inst->cap_format.type = dst_vq->type;
drivers/media/platform/amphion/vpu_v4l2.c
681
if (inst->type == VPU_CORE_TYPE_ENC && inst->use_stream_buffer)
drivers/media/platform/amphion/vpu_v4l2.c
683
dst_vq->drv_priv = inst;
drivers/media/platform/amphion/vpu_v4l2.c
685
dst_vq->dev = inst->vpu->dev;
drivers/media/platform/amphion/vpu_v4l2.c
686
dst_vq->lock = &inst->lock;
drivers/media/platform/amphion/vpu_v4l2.c
696
static int vpu_v4l2_release(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_v4l2.c
698
vpu_trace(inst->vpu->dev, "%p\n", inst);
drivers/media/platform/amphion/vpu_v4l2.c
700
if (inst->workqueue) {
drivers/media/platform/amphion/vpu_v4l2.c
701
cancel_work_sync(&inst->msg_work);
drivers/media/platform/amphion/vpu_v4l2.c
702
destroy_workqueue(inst->workqueue);
drivers/media/platform/amphion/vpu_v4l2.c
703
inst->workqueue = NULL;
drivers/media/platform/amphion/vpu_v4l2.c
706
vpu_release_core(inst->core);
drivers/media/platform/amphion/vpu_v4l2.c
707
put_device(inst->dev);
drivers/media/platform/amphion/vpu_v4l2.c
709
v4l2_ctrl_handler_free(&inst->ctrl_handler);
drivers/media/platform/amphion/vpu_v4l2.c
710
mutex_destroy(&inst->lock);
drivers/media/platform/amphion/vpu_v4l2.c
712
call_void_vop(inst, cleanup);
drivers/media/platform/amphion/vpu_v4l2.c
717
int vpu_v4l2_open(struct file *file, struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_v4l2.c
723
if (!inst || !inst->ops)
drivers/media/platform/amphion/vpu_v4l2.c
726
if (inst->type == VPU_CORE_TYPE_ENC)
drivers/media/platform/amphion/vpu_v4l2.c
731
atomic_set(&inst->ref_count, 0);
drivers/media/platform/amphion/vpu_v4l2.c
732
atomic_long_set(&inst->last_response_cmd, 0);
drivers/media/platform/amphion/vpu_v4l2.c
733
vpu_inst_get(inst);
drivers/media/platform/amphion/vpu_v4l2.c
734
inst->vpu = vpu;
drivers/media/platform/amphion/vpu_v4l2.c
735
inst->core = vpu_request_core(vpu, inst->type);
drivers/media/platform/amphion/vpu_v4l2.c
736
if (inst->core)
drivers/media/platform/amphion/vpu_v4l2.c
737
inst->dev = get_device(inst->core->dev);
drivers/media/platform/amphion/vpu_v4l2.c
738
mutex_init(&inst->lock);
drivers/media/platform/amphion/vpu_v4l2.c
739
INIT_LIST_HEAD(&inst->cmd_q);
drivers/media/platform/amphion/vpu_v4l2.c
740
inst->id = VPU_INST_NULL_ID;
drivers/media/platform/amphion/vpu_v4l2.c
741
inst->release = vpu_v4l2_release;
drivers/media/platform/amphion/vpu_v4l2.c
742
inst->pid = current->pid;
drivers/media/platform/amphion/vpu_v4l2.c
743
inst->tgid = current->tgid;
drivers/media/platform/amphion/vpu_v4l2.c
744
inst->min_buffer_cap = 2;
drivers/media/platform/amphion/vpu_v4l2.c
745
inst->min_buffer_out = 2;
drivers/media/platform/amphion/vpu_v4l2.c
746
v4l2_fh_init(&inst->fh, func->vfd);
drivers/media/platform/amphion/vpu_v4l2.c
747
v4l2_fh_add(&inst->fh, file);
drivers/media/platform/amphion/vpu_v4l2.c
749
ret = call_vop(inst, ctrl_init);
drivers/media/platform/amphion/vpu_v4l2.c
753
inst->fh.m2m_ctx = v4l2_m2m_ctx_init(func->m2m_dev, inst, vpu_m2m_queue_init);
drivers/media/platform/amphion/vpu_v4l2.c
754
if (IS_ERR(inst->fh.m2m_ctx)) {
drivers/media/platform/amphion/vpu_v4l2.c
756
ret = PTR_ERR(inst->fh.m2m_ctx);
drivers/media/platform/amphion/vpu_v4l2.c
760
inst->fh.ctrl_handler = &inst->ctrl_handler;
drivers/media/platform/amphion/vpu_v4l2.c
761
inst->state = VPU_CODEC_STATE_DEINIT;
drivers/media/platform/amphion/vpu_v4l2.c
762
inst->workqueue = alloc_ordered_workqueue("vpu_inst", WQ_MEM_RECLAIM);
drivers/media/platform/amphion/vpu_v4l2.c
763
if (inst->workqueue) {
drivers/media/platform/amphion/vpu_v4l2.c
764
INIT_WORK(&inst->msg_work, vpu_inst_run_work);
drivers/media/platform/amphion/vpu_v4l2.c
765
ret = kfifo_init(&inst->msg_fifo,
drivers/media/platform/amphion/vpu_v4l2.c
766
inst->msg_buffer,
drivers/media/platform/amphion/vpu_v4l2.c
767
rounddown_pow_of_two(sizeof(inst->msg_buffer)));
drivers/media/platform/amphion/vpu_v4l2.c
769
destroy_workqueue(inst->workqueue);
drivers/media/platform/amphion/vpu_v4l2.c
770
inst->workqueue = NULL;
drivers/media/platform/amphion/vpu_v4l2.c
774
inst->tgid, inst->pid, vpu_core_type_desc(inst->type), inst);
drivers/media/platform/amphion/vpu_v4l2.c
778
v4l2_fh_del(&inst->fh, file);
drivers/media/platform/amphion/vpu_v4l2.c
779
v4l2_fh_exit(&inst->fh);
drivers/media/platform/amphion/vpu_v4l2.c
78
void vpu_v4l2_set_error(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_v4l2.c
780
vpu_inst_put(inst);
drivers/media/platform/amphion/vpu_v4l2.c
787
struct vpu_inst *inst = to_inst(file);
drivers/media/platform/amphion/vpu_v4l2.c
789
vpu_trace(vpu->dev, "tgid = %d, pid = %d, inst = %p\n", inst->tgid, inst->pid, inst);
drivers/media/platform/amphion/vpu_v4l2.c
791
vpu_inst_lock(inst);
drivers/media/platform/amphion/vpu_v4l2.c
792
if (inst->fh.m2m_ctx) {
drivers/media/platform/amphion/vpu_v4l2.c
793
v4l2_m2m_ctx_release(inst->fh.m2m_ctx);
drivers/media/platform/amphion/vpu_v4l2.c
794
inst->fh.m2m_ctx = NULL;
drivers/media/platform/amphion/vpu_v4l2.c
796
call_void_vop(inst, release);
drivers/media/platform/amphion/vpu_v4l2.c
797
vpu_inst_unlock(inst);
drivers/media/platform/amphion/vpu_v4l2.c
799
v4l2_fh_del(&inst->fh, file);
drivers/media/platform/amphion/vpu_v4l2.c
80
vpu_inst_lock(inst);
drivers/media/platform/amphion/vpu_v4l2.c
800
v4l2_fh_exit(&inst->fh);
drivers/media/platform/amphion/vpu_v4l2.c
802
vpu_inst_unregister(inst);
drivers/media/platform/amphion/vpu_v4l2.c
803
vpu_inst_put(inst);
drivers/media/platform/amphion/vpu_v4l2.c
81
dev_err(inst->dev, "some error occurs in codec\n");
drivers/media/platform/amphion/vpu_v4l2.c
82
if (inst->fh.m2m_ctx) {
drivers/media/platform/amphion/vpu_v4l2.c
83
vb2_queue_error(v4l2_m2m_get_src_vq(inst->fh.m2m_ctx));
drivers/media/platform/amphion/vpu_v4l2.c
84
vb2_queue_error(v4l2_m2m_get_dst_vq(inst->fh.m2m_ctx));
drivers/media/platform/amphion/vpu_v4l2.c
86
vpu_inst_unlock(inst);
drivers/media/platform/amphion/vpu_v4l2.c
89
static int vpu_notify_eos(struct vpu_inst *inst)
drivers/media/platform/amphion/vpu_v4l2.c
96
vpu_trace(inst->dev, "[%d]\n", inst->id);
drivers/media/platform/amphion/vpu_v4l2.c
97
v4l2_event_queue_fh(&inst->fh, &ev);
drivers/media/platform/amphion/vpu_v4l2.h
11
void vpu_inst_lock(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu_v4l2.h
12
void vpu_inst_unlock(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu_v4l2.h
17
int vpu_v4l2_open(struct file *file, struct vpu_inst *inst);
drivers/media/platform/amphion/vpu_v4l2.h
21
int vpu_try_fmt_common(struct vpu_inst *inst, struct v4l2_format *f, struct vpu_format *fmt);
drivers/media/platform/amphion/vpu_v4l2.h
22
int vpu_process_output_buffer(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu_v4l2.h
23
int vpu_process_capture_buffer(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu_v4l2.h
24
struct vb2_v4l2_buffer *vpu_next_src_buf(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu_v4l2.h
25
void vpu_skip_frame(struct vpu_inst *inst, int count);
drivers/media/platform/amphion/vpu_v4l2.h
26
struct vb2_v4l2_buffer *vpu_find_buf_by_sequence(struct vpu_inst *inst, u32 type, u32 sequence);
drivers/media/platform/amphion/vpu_v4l2.h
27
struct vb2_v4l2_buffer *vpu_find_buf_by_idx(struct vpu_inst *inst, u32 type, u32 idx);
drivers/media/platform/amphion/vpu_v4l2.h
28
void vpu_v4l2_set_error(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu_v4l2.h
29
int vpu_notify_source_change(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu_v4l2.h
30
int vpu_set_last_buffer_dequeued(struct vpu_inst *inst, bool eos);
drivers/media/platform/amphion/vpu_v4l2.h
31
int vpu_get_num_buffers(struct vpu_inst *inst, u32 type);
drivers/media/platform/amphion/vpu_v4l2.h
32
bool vpu_is_source_empty(struct vpu_inst *inst);
drivers/media/platform/amphion/vpu_v4l2.h
35
static inline struct vpu_format *vpu_get_format(struct vpu_inst *inst, u32 type)
drivers/media/platform/amphion/vpu_v4l2.h
38
return &inst->out_format;
drivers/media/platform/amphion/vpu_v4l2.h
40
return &inst->cap_format;
drivers/media/platform/amphion/vpu_windsor.c
779
struct vpu_inst *inst = vb2_get_drv_priv(vb->vb2_queue);
drivers/media/platform/amphion/vpu_windsor.c
788
out_fmt = vpu_get_format(inst, vb->type);
drivers/media/platform/amphion/vpu_windsor.c
806
struct vpu_inst *inst, struct vb2_buffer *vb)
drivers/media/platform/amphion/vpu_windsor.c
808
vpu_windsor_fill_yuv_frame(shared, inst->id, vb);
drivers/media/platform/amphion/vpu_windsor.c
809
return vpu_session_encode_frame(inst, vb->timestamp);
drivers/media/platform/amphion/vpu_windsor.h
34
struct vpu_inst *inst, struct vb2_buffer *vb);
drivers/media/platform/chips-media/wave5/wave5-helper.c
104
dev_err(inst->dev->dev, "%s close, fail: %d\n", name, ret);
drivers/media/platform/chips-media/wave5/wave5-helper.c
109
wave5_cleanup_instance(inst, filp);
drivers/media/platform/chips-media/wave5/wave5-helper.c
117
struct vpu_instance *inst = priv;
drivers/media/platform/chips-media/wave5/wave5-helper.c
126
src_vq->drv_priv = inst;
drivers/media/platform/chips-media/wave5/wave5-helper.c
127
src_vq->lock = &inst->dev->dev_lock;
drivers/media/platform/chips-media/wave5/wave5-helper.c
128
src_vq->dev = inst->dev->v4l2_dev.dev;
drivers/media/platform/chips-media/wave5/wave5-helper.c
139
dst_vq->drv_priv = inst;
drivers/media/platform/chips-media/wave5/wave5-helper.c
140
dst_vq->lock = &inst->dev->dev_lock;
drivers/media/platform/chips-media/wave5/wave5-helper.c
141
dst_vq->dev = inst->dev->v4l2_dev.dev;
drivers/media/platform/chips-media/wave5/wave5-helper.c
151
struct vpu_instance *inst = wave5_to_vpu_inst(fh);
drivers/media/platform/chips-media/wave5/wave5-helper.c
152
bool is_decoder = inst->type == VPU_INST_TYPE_DEC;
drivers/media/platform/chips-media/wave5/wave5-helper.c
154
dev_dbg(inst->dev->dev, "%s: [%s] type: %u id: %u | flags: %u\n", __func__,
drivers/media/platform/chips-media/wave5/wave5-helper.c
173
struct vpu_instance *inst = file_to_vpu_inst(file);
drivers/media/platform/chips-media/wave5/wave5-helper.c
176
f->fmt.pix_mp.width = inst->src_fmt.width;
drivers/media/platform/chips-media/wave5/wave5-helper.c
177
f->fmt.pix_mp.height = inst->src_fmt.height;
drivers/media/platform/chips-media/wave5/wave5-helper.c
178
f->fmt.pix_mp.pixelformat = inst->src_fmt.pixelformat;
drivers/media/platform/chips-media/wave5/wave5-helper.c
179
f->fmt.pix_mp.field = inst->src_fmt.field;
drivers/media/platform/chips-media/wave5/wave5-helper.c
180
f->fmt.pix_mp.flags = inst->src_fmt.flags;
drivers/media/platform/chips-media/wave5/wave5-helper.c
181
f->fmt.pix_mp.num_planes = inst->src_fmt.num_planes;
drivers/media/platform/chips-media/wave5/wave5-helper.c
183
f->fmt.pix_mp.plane_fmt[i].bytesperline = inst->src_fmt.plane_fmt[i].bytesperline;
drivers/media/platform/chips-media/wave5/wave5-helper.c
184
f->fmt.pix_mp.plane_fmt[i].sizeimage = inst->src_fmt.plane_fmt[i].sizeimage;
drivers/media/platform/chips-media/wave5/wave5-helper.c
187
f->fmt.pix_mp.colorspace = inst->colorspace;
drivers/media/platform/chips-media/wave5/wave5-helper.c
188
f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc;
drivers/media/platform/chips-media/wave5/wave5-helper.c
189
f->fmt.pix_mp.quantization = inst->quantization;
drivers/media/platform/chips-media/wave5/wave5-helper.c
190
f->fmt.pix_mp.xfer_func = inst->xfer_func;
drivers/media/platform/chips-media/wave5/wave5-helper.c
234
struct vpu_instance *inst = vb2_get_drv_priv(q);
drivers/media/platform/chips-media/wave5/wave5-helper.c
235
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-helper.c
236
struct v4l2_ctrl_handler v4l2_ctrl_hdl = inst->v4l2_ctrl_hdl;
drivers/media/platform/chips-media/wave5/wave5-helper.c
30
int wave5_kfifo_alloc(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-helper.c
32
return kfifo_alloc(&inst->irq_status, 16 * sizeof(int), GFP_KERNEL);
drivers/media/platform/chips-media/wave5/wave5-helper.c
35
void wave5_cleanup_instance(struct vpu_instance *inst, struct file *filp)
drivers/media/platform/chips-media/wave5/wave5-helper.c
44
if (list_is_singular(&inst->list) &&
drivers/media/platform/chips-media/wave5/wave5-helper.c
45
inst->dev->product_code != WAVE515_CODE)
drivers/media/platform/chips-media/wave5/wave5-helper.c
46
wave5_vdi_free_sram(inst->dev);
drivers/media/platform/chips-media/wave5/wave5-helper.c
48
for (i = 0; i < inst->fbc_buf_count; i++)
drivers/media/platform/chips-media/wave5/wave5-helper.c
49
wave5_vpu_dec_reset_framebuffer(inst, i);
drivers/media/platform/chips-media/wave5/wave5-helper.c
51
wave5_vdi_free_dma_memory(inst->dev, &inst->bitstream_vbuf);
drivers/media/platform/chips-media/wave5/wave5-helper.c
52
v4l2_ctrl_handler_free(&inst->v4l2_ctrl_hdl);
drivers/media/platform/chips-media/wave5/wave5-helper.c
53
if (inst->v4l2_fh.vdev) {
drivers/media/platform/chips-media/wave5/wave5-helper.c
54
v4l2_fh_del(&inst->v4l2_fh, filp);
drivers/media/platform/chips-media/wave5/wave5-helper.c
55
v4l2_fh_exit(&inst->v4l2_fh);
drivers/media/platform/chips-media/wave5/wave5-helper.c
57
kfifo_free(&inst->irq_status);
drivers/media/platform/chips-media/wave5/wave5-helper.c
58
ida_free(&inst->dev->inst_ida, inst->id);
drivers/media/platform/chips-media/wave5/wave5-helper.c
59
kfree(inst->codec_info);
drivers/media/platform/chips-media/wave5/wave5-helper.c
60
kfree(inst);
drivers/media/platform/chips-media/wave5/wave5-helper.c
64
int (*close_func)(struct vpu_instance *inst, u32 *fail_res),
drivers/media/platform/chips-media/wave5/wave5-helper.c
67
struct vpu_instance *inst = file_to_vpu_inst(filp);
drivers/media/platform/chips-media/wave5/wave5-helper.c
84
ret = mutex_lock_interruptible(&inst->dev->irq_lock);
drivers/media/platform/chips-media/wave5/wave5-helper.c
87
spin_lock_irqsave(&inst->dev->irq_spinlock, flags);
drivers/media/platform/chips-media/wave5/wave5-helper.c
88
list_del_init(&inst->list);
drivers/media/platform/chips-media/wave5/wave5-helper.c
89
spin_unlock_irqrestore(&inst->dev->irq_spinlock, flags);
drivers/media/platform/chips-media/wave5/wave5-helper.c
90
mutex_unlock(&inst->dev->irq_lock);
drivers/media/platform/chips-media/wave5/wave5-helper.c
92
v4l2_m2m_ctx_release(inst->v4l2_fh.m2m_ctx);
drivers/media/platform/chips-media/wave5/wave5-helper.c
94
if (inst->state != VPU_INST_STATE_NONE) {
drivers/media/platform/chips-media/wave5/wave5-helper.c
97
ret = close_func(inst, &fail_res);
drivers/media/platform/chips-media/wave5/wave5-helper.c
99
dev_err(inst->dev->dev, "%s close failed, device is still running\n",
drivers/media/platform/chips-media/wave5/wave5-helper.h
17
void wave5_cleanup_instance(struct vpu_instance *inst, struct file *filp);
drivers/media/platform/chips-media/wave5/wave5-helper.h
19
int (*close_func)(struct vpu_instance *inst, u32 *fail_res),
drivers/media/platform/chips-media/wave5/wave5-helper.h
36
int wave5_kfifo_alloc(struct vpu_instance *inst);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1008
int wave5_vpu_dec_get_result(struct vpu_instance *inst, struct dec_output_info *result)
drivers/media/platform/chips-media/wave5/wave5-hw.c
1012
struct dec_info *p_dec_info = &inst->codec_info->dec_info;
drivers/media/platform/chips-media/wave5/wave5-hw.c
1013
struct vpu_device *vpu_dev = inst->dev;
drivers/media/platform/chips-media/wave5/wave5-hw.c
1015
vpu_write_reg(inst->dev, W5_CMD_DEC_ADDR_REPORT_BASE, p_dec_info->user_data_buf_addr);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1016
vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_SIZE, p_dec_info->user_data_buf_size);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1017
vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_PARAM, REPORT_PARAM_ENDIANNESS_BIG_ENDIAN);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1020
ret = wave5_send_query(vpu_dev, inst, GET_RESULT);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1024
reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1029
dev_dbg(inst->dev->dev, "%s: dec pic complete (queue %u : %u)\n", __func__,
drivers/media/platform/chips-media/wave5/wave5-hw.c
1032
reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_TYPE);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1036
if (inst->std == W_HEVC_DEC) {
drivers/media/platform/chips-media/wave5/wave5-hw.c
1048
} else if (inst->std == W_AVC_DEC) {
drivers/media/platform/chips-media/wave5/wave5-hw.c
1060
index = vpu_read_reg(inst->dev, W5_RET_DEC_DISPLAY_INDEX);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1062
index = vpu_read_reg(inst->dev, W5_RET_DEC_DECODED_INDEX);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1066
sub_layer_info = vpu_read_reg(inst->dev, W5_RET_DEC_SUB_LAYER_INFO);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1069
if (inst->std == W_HEVC_DEC || inst->std == W_AVC_DEC) {
drivers/media/platform/chips-media/wave5/wave5-hw.c
1073
result->decoded_poc = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_POC);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1076
result->sequence_changed = vpu_read_reg(inst->dev, W5_RET_DEC_NOTIFICATION);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1077
reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_SIZE);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1084
wave5_get_dec_seq_result(inst, &p_dec_info->new_seq_info);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1087
result->dec_host_cmd_tick = vpu_read_reg(inst->dev, W5_RET_DEC_HOST_CMD_TICK);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1088
result->dec_decode_end_tick = vpu_read_reg(inst->dev, W5_RET_DEC_DECODING_ENC_TICK);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1467
int wave5_vpu_dec_finish_seq(struct vpu_instance *inst, u32 *fail_res)
drivers/media/platform/chips-media/wave5/wave5-hw.c
1469
return send_firmware_command(inst, W5_DESTROY_INSTANCE, true, NULL, fail_res);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1472
int wave5_vpu_dec_set_bitstream_flag(struct vpu_instance *inst, bool eos)
drivers/media/platform/chips-media/wave5/wave5-hw.c
1474
struct dec_info *p_dec_info = &inst->codec_info->dec_info;
drivers/media/platform/chips-media/wave5/wave5-hw.c
1477
vpu_write_reg(inst->dev, W5_BS_OPTION, get_bitstream_options(p_dec_info));
drivers/media/platform/chips-media/wave5/wave5-hw.c
1478
vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1480
return send_firmware_command(inst, W5_UPDATE_BS, true, NULL, NULL);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1483
int wave5_dec_clr_disp_flag(struct vpu_instance *inst, unsigned int index)
drivers/media/platform/chips-media/wave5/wave5-hw.c
1485
struct dec_info *p_dec_info = &inst->codec_info->dec_info;
drivers/media/platform/chips-media/wave5/wave5-hw.c
1488
vpu_write_reg(inst->dev, W5_CMD_DEC_CLR_DISP_IDC, BIT(index));
drivers/media/platform/chips-media/wave5/wave5-hw.c
1489
vpu_write_reg(inst->dev, W5_CMD_DEC_SET_DISP_IDC, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1491
ret = wave5_send_query(inst->dev, inst, UPDATE_DISP_FLAG);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1495
p_dec_info->frame_display_flag = vpu_read_reg(inst->dev, W5_RET_DEC_DISP_IDC);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1500
int wave5_dec_set_disp_flag(struct vpu_instance *inst, unsigned int index)
drivers/media/platform/chips-media/wave5/wave5-hw.c
1504
vpu_write_reg(inst->dev, W5_CMD_DEC_CLR_DISP_IDC, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1505
vpu_write_reg(inst->dev, W5_CMD_DEC_SET_DISP_IDC, BIT(index));
drivers/media/platform/chips-media/wave5/wave5-hw.c
1507
ret = wave5_send_query(inst->dev, inst, UPDATE_DISP_FLAG);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1514
int wave5_vpu_clear_interrupt(struct vpu_instance *inst, u32 flags)
drivers/media/platform/chips-media/wave5/wave5-hw.c
1518
interrupt_reason = vpu_read_reg(inst->dev, W5_VPU_VINT_REASON_USR);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1520
vpu_write_reg(inst->dev, W5_VPU_VINT_REASON_USR, interrupt_reason);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1525
dma_addr_t wave5_dec_get_rd_ptr(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-hw.c
1529
ret = wave5_send_query(inst->dev, inst, GET_BS_RD_PTR);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1531
return inst->codec_info->dec_info.stream_rd_ptr;
drivers/media/platform/chips-media/wave5/wave5-hw.c
1533
return vpu_read_reg(inst->dev, W5_RET_QUERY_DEC_BS_RD_PTR);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1536
int wave5_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr)
drivers/media/platform/chips-media/wave5/wave5-hw.c
1540
vpu_write_reg(inst->dev, W5_RET_QUERY_DEC_SET_BS_RD_PTR, addr);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1542
ret = wave5_send_query(inst->dev, inst, SET_BS_RD_PTR);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1551
int wave5_vpu_build_up_enc_param(struct device *dev, struct vpu_instance *inst,
drivers/media/platform/chips-media/wave5/wave5-hw.c
1555
struct enc_info *p_enc_info = &inst->codec_info->enc_info;
drivers/media/platform/chips-media/wave5/wave5-hw.c
1576
vpu_write_reg(inst->dev, W5_ADDR_WORK_BASE, p_enc_info->vb_work.daddr);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1577
vpu_write_reg(inst->dev, W5_WORK_SIZE, p_enc_info->vb_work.size);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1579
vpu_write_reg(inst->dev, W5_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1580
vpu_write_reg(inst->dev, W5_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1583
vpu_write_reg(inst->dev, W5_CMD_BS_PARAM, reg_val);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1584
vpu_write_reg(inst->dev, W5_CMD_EXT_ADDR, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1585
vpu_write_reg(inst->dev, W5_CMD_NUM_CQ_DEPTH_M1, WAVE521_COMMAND_QUEUE_DEPTH - 1);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1588
vpu_write_reg(inst->dev, W5_CMD_ENC_SRC_OPTIONS, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1589
vpu_write_reg(inst->dev, W5_CMD_ENC_VCORE_INFO, 1);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1591
ret = send_firmware_command(inst, W5_CREATE_INSTANCE, true, NULL, NULL);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1605
p_enc_info->product_code = vpu_read_reg(inst->dev, W5_PRODUCT_NUMBER);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1701
int wave5_vpu_enc_init_seq(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-hw.c
1704
struct enc_info *p_enc_info = &inst->codec_info->enc_info;
drivers/media/platform/chips-media/wave5/wave5-hw.c
1747
wave5_set_enc_crop_info(inst->std, p_param, rot_mir_mode, p_open_param->pic_width,
drivers/media/platform/chips-media/wave5/wave5-hw.c
1751
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SET_PARAM_OPTION, OPT_COMMON);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1752
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SRC_SIZE, p_open_param->pic_height << 16
drivers/media/platform/chips-media/wave5/wave5-hw.c
1754
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MAP_ENDIAN, VDI_LITTLE_ENDIAN);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1759
if (inst->std == W_HEVC_ENC)
drivers/media/platform/chips-media/wave5/wave5-hw.c
1766
else if (inst->std == W_AVC_ENC)
drivers/media/platform/chips-media/wave5/wave5-hw.c
1769
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SPS_PARAM, reg_val);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1782
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_PPS_PARAM, reg_val);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1784
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_GOP_PARAM, p_param->gop_preset_idx);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1786
if (inst->std == W_AVC_ENC)
drivers/media/platform/chips-media/wave5/wave5-hw.c
1787
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, p_param->intra_qp |
drivers/media/platform/chips-media/wave5/wave5-hw.c
1794
else if (inst->std == W_HEVC_ENC)
drivers/media/platform/chips-media/wave5/wave5-hw.c
1795
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM,
drivers/media/platform/chips-media/wave5/wave5-hw.c
1808
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RDO_PARAM, reg_val);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1810
if (inst->std == W_AVC_ENC)
drivers/media/platform/chips-media/wave5/wave5-hw.c
1811
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_REFRESH,
drivers/media/platform/chips-media/wave5/wave5-hw.c
1813
else if (inst->std == W_HEVC_ENC)
drivers/media/platform/chips-media/wave5/wave5-hw.c
1814
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_REFRESH,
drivers/media/platform/chips-media/wave5/wave5-hw.c
1817
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_FRAME_RATE, p_open_param->frame_rate_info);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1818
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_TARGET_RATE, p_open_param->bit_rate);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1825
if (inst->std == W_AVC_ENC)
drivers/media/platform/chips-media/wave5/wave5-hw.c
1827
else if (inst->std == W_HEVC_ENC)
drivers/media/platform/chips-media/wave5/wave5-hw.c
1829
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_PARAM, reg_val);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1831
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_WEIGHT_PARAM,
drivers/media/platform/chips-media/wave5/wave5-hw.c
1834
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_MIN_MAX_QP, p_param->min_qp_i |
drivers/media/platform/chips-media/wave5/wave5-hw.c
1837
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_INTER_MIN_MAX_QP, p_param->min_qp_p |
drivers/media/platform/chips-media/wave5/wave5-hw.c
1841
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_0_3, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1842
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_4_7, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1843
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_ROT_PARAM, rot_mir_mode);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1845
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_BG_PARAM,
drivers/media/platform/chips-media/wave5/wave5-hw.c
1847
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_LAMBDA_ADDR, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1848
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CONF_WIN_TOP_BOT,
drivers/media/platform/chips-media/wave5/wave5-hw.c
1850
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CONF_WIN_LEFT_RIGHT,
drivers/media/platform/chips-media/wave5/wave5-hw.c
1853
if (inst->std == W_AVC_ENC)
drivers/media/platform/chips-media/wave5/wave5-hw.c
1854
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INDEPENDENT_SLICE,
drivers/media/platform/chips-media/wave5/wave5-hw.c
1856
else if (inst->std == W_HEVC_ENC)
drivers/media/platform/chips-media/wave5/wave5-hw.c
1857
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INDEPENDENT_SLICE,
drivers/media/platform/chips-media/wave5/wave5-hw.c
1861
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_USER_SCALING_LIST_ADDR, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1862
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NUM_UNITS_IN_TICK, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1863
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_TIME_SCALE, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1864
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NUM_TICKS_POC_DIFF_ONE, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1866
if (inst->std == W_HEVC_ENC) {
drivers/media/platform/chips-media/wave5/wave5-hw.c
1867
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU04, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1868
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU08, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1869
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU16, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1870
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU32, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1871
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU08, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1872
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU16, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1873
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU32, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1874
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_DEPENDENT_SLICE,
drivers/media/platform/chips-media/wave5/wave5-hw.c
1877
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NR_PARAM, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1879
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NR_WEIGHT,
drivers/media/platform/chips-media/wave5/wave5-hw.c
1887
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_VUI_HRD_PARAM, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1889
return send_firmware_command(inst, W5_ENC_SET_PARAM, true, NULL, NULL);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1892
int wave5_vpu_enc_get_seq_info(struct vpu_instance *inst, struct enc_initial_info *info)
drivers/media/platform/chips-media/wave5/wave5-hw.c
1896
struct enc_info *p_enc_info = &inst->codec_info->enc_info;
drivers/media/platform/chips-media/wave5/wave5-hw.c
1899
ret = wave5_send_query(inst->dev, inst, GET_RESULT);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1903
dev_dbg(inst->dev->dev, "%s: init seq\n", __func__);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1905
reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1910
if (vpu_read_reg(inst->dev, W5_RET_ENC_ENCODING_SUCCESS) != 1) {
drivers/media/platform/chips-media/wave5/wave5-hw.c
1911
info->seq_init_err_reason = vpu_read_reg(inst->dev, W5_RET_ENC_ERR_INFO);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1914
info->warn_info = vpu_read_reg(inst->dev, W5_RET_ENC_WARN_INFO);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1917
info->min_frame_buffer_count = vpu_read_reg(inst->dev, W5_RET_ENC_NUM_REQUIRED_FB);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1918
info->min_src_frame_count = vpu_read_reg(inst->dev, W5_RET_ENC_MIN_SRC_BUF_NUM);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1919
info->vlc_buf_size = vpu_read_reg(inst->dev, W5_RET_VLC_BUF_SIZE);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1920
info->param_buf_size = vpu_read_reg(inst->dev, W5_RET_PARAM_BUF_SIZE);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1937
int wave5_vpu_enc_register_framebuffer(struct device *dev, struct vpu_instance *inst,
drivers/media/platform/chips-media/wave5/wave5-hw.c
1951
bool avc_encoding = (inst->std == W_AVC_ENC);
drivers/media/platform/chips-media/wave5/wave5-hw.c
1958
struct enc_info *p_enc_info = &inst->codec_info->enc_info;
drivers/media/platform/chips-media/wave5/wave5-hw.c
2059
vpu_write_reg(inst->dev, W5_CMD_SET_FB_ADDR_TASK_BUF,
drivers/media/platform/chips-media/wave5/wave5-hw.c
2061
vpu_write_reg(inst->dev, W5_CMD_SET_FB_TASK_BUF_SIZE, vb_task.size);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2065
vpu_write_reg(inst->dev, W5_ADDR_SUB_SAMPLED_FB_BASE, vb_sub_sam_buf.daddr);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2067
vpu_write_reg(inst->dev, W5_SUB_SAMPLED_ONE_FB_SIZE, sub_sampled_size);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2069
vpu_write_reg(inst->dev, W5_PIC_SIZE, pic_size);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2082
vpu_write_reg(inst->dev, W5_FBC_STRIDE, luma_stride << 16 | chroma_stride);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2083
vpu_write_reg(inst->dev, W5_COMMON_PIC_INFO, stride);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2090
vpu_write_reg(inst->dev, W5_SFB_OPTION, reg_val);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2094
vpu_write_reg(inst->dev, W5_SET_FB_NUM, (start_no << 8) | end_no);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2097
vpu_write_reg(inst->dev, W5_ADDR_LUMA_BASE0 + (i << 4), fb_arr[i +
drivers/media/platform/chips-media/wave5/wave5-hw.c
2099
vpu_write_reg(inst->dev, W5_ADDR_CB_BASE0 + (i << 4),
drivers/media/platform/chips-media/wave5/wave5-hw.c
2102
vpu_write_reg(inst->dev, W5_ADDR_FBC_Y_OFFSET0 + (i << 4),
drivers/media/platform/chips-media/wave5/wave5-hw.c
2105
vpu_write_reg(inst->dev, W5_ADDR_FBC_C_OFFSET0 + (i << 4),
drivers/media/platform/chips-media/wave5/wave5-hw.c
2108
vpu_write_reg(inst->dev, W5_ADDR_MV_COL0 + (i << 2),
drivers/media/platform/chips-media/wave5/wave5-hw.c
2114
ret = send_firmware_command(inst, W5_SET_FB, false, NULL, NULL);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2138
static u32 wave5_vpu_enc_validate_sec_axi(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-hw.c
2140
struct enc_info *p_enc_info = &inst->codec_info->enc_info;
drivers/media/platform/chips-media/wave5/wave5-hw.c
2142
u32 sram_size = inst->dev->sram_size;
drivers/media/platform/chips-media/wave5/wave5-hw.c
2163
int wave5_vpu_encode(struct vpu_instance *inst, struct enc_param *option, u32 *fail_res)
drivers/media/platform/chips-media/wave5/wave5-hw.c
2168
struct enc_info *p_enc_info = &inst->codec_info->enc_info;
drivers/media/platform/chips-media/wave5/wave5-hw.c
2175
vpu_write_reg(inst->dev, W5_CMD_ENC_BS_START_ADDR, option->pic_stream_buffer_addr);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2176
vpu_write_reg(inst->dev, W5_CMD_ENC_BS_SIZE, option->pic_stream_buffer_size);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2182
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_AXI_SEL, DEFAULT_SRC_AXI);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2184
reg_val = wave5_vpu_enc_validate_sec_axi(inst);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2185
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_USE_SEC_AXI, reg_val);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2187
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_REPORT_PARAM, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2194
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CODE_OPTION,
drivers/media/platform/chips-media/wave5/wave5-hw.c
2200
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CODE_OPTION,
drivers/media/platform/chips-media/wave5/wave5-hw.c
2210
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_PIC_PARAM, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2214
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_PIC_IDX, 0xFFFFFFFF);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2216
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_PIC_IDX, option->src_idx);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2218
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_Y, p_src_frame->buf_y);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2219
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_U, p_src_frame->buf_cb);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2220
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_V, p_src_frame->buf_cr);
drivers/media/platform/chips-media/wave5/wave5-hw.c
223
static void wave5_bit_issue_command(struct vpu_device *vpu_dev, struct vpu_instance *inst, u32 cmd)
drivers/media/platform/chips-media/wave5/wave5-hw.c
2231
src_stride_c = inst->cbcr_interleave ? p_src_frame->stride :
drivers/media/platform/chips-media/wave5/wave5-hw.c
2244
src_stride_c = inst->cbcr_interleave ? p_src_frame->stride :
drivers/media/platform/chips-media/wave5/wave5-hw.c
2257
src_stride_c = inst->cbcr_interleave ? p_src_frame->stride :
drivers/media/platform/chips-media/wave5/wave5-hw.c
2270
src_stride_c = inst->cbcr_interleave ? p_src_frame->stride :
drivers/media/platform/chips-media/wave5/wave5-hw.c
2271
ALIGN(p_src_frame->stride / 2, 16) * BIT(inst->cbcr_interleave);
drivers/media/platform/chips-media/wave5/wave5-hw.c
228
if (inst) {
drivers/media/platform/chips-media/wave5/wave5-hw.c
2283
src_stride_c = inst->cbcr_interleave ? p_src_frame->stride :
drivers/media/platform/chips-media/wave5/wave5-hw.c
2284
ALIGN(p_src_frame->stride / 2, 16) * BIT(inst->cbcr_interleave);
drivers/media/platform/chips-media/wave5/wave5-hw.c
229
instance_index = inst->id;
drivers/media/platform/chips-media/wave5/wave5-hw.c
2292
src_frame_format = (inst->cbcr_interleave << 1) | (inst->nv21);
drivers/media/platform/chips-media/wave5/wave5-hw.c
230
codec_mode = inst->std;
drivers/media/platform/chips-media/wave5/wave5-hw.c
2310
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_STRIDE,
drivers/media/platform/chips-media/wave5/wave5-hw.c
2312
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_FORMAT, src_frame_format |
drivers/media/platform/chips-media/wave5/wave5-hw.c
2315
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_ADDR, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2316
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2317
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_LONGTERM_PIC, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2318
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_Y, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2319
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_C, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2320
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_MEAN_Y, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2321
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_MEAN_C, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2322
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_PREFIX_SEI_INFO, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2323
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_PREFIX_SEI_NAL_ADDR, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2324
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SUFFIX_SEI_INFO, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2325
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SUFFIX_SEI_NAL_ADDR, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2327
ret = send_firmware_command(inst, W5_DEC_ENC_PIC, true, ®_val, fail_res);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2340
int wave5_vpu_enc_get_result(struct vpu_instance *inst, struct enc_output_info *result)
drivers/media/platform/chips-media/wave5/wave5-hw.c
2345
struct enc_info *p_enc_info = &inst->codec_info->enc_info;
drivers/media/platform/chips-media/wave5/wave5-hw.c
2346
struct vpu_device *vpu_dev = inst->dev;
drivers/media/platform/chips-media/wave5/wave5-hw.c
2348
ret = wave5_send_query(inst->dev, inst, GET_RESULT);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2352
dev_dbg(inst->dev->dev, "%s: enc pic complete\n", __func__);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2354
reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2359
encoding_success = vpu_read_reg(inst->dev, W5_RET_ENC_ENCODING_SUCCESS);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2361
result->error_reason = vpu_read_reg(inst->dev, W5_RET_ENC_ERR_INFO);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2365
result->warn_info = vpu_read_reg(inst->dev, W5_RET_ENC_WARN_INFO);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2367
reg_val = vpu_read_reg(inst->dev, W5_RET_ENC_PIC_TYPE);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2370
result->enc_vcl_nut = vpu_read_reg(inst->dev, W5_RET_ENC_VCL_NUT);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2375
result->recon_frame_index = vpu_read_reg(inst->dev, W5_RET_ENC_PIC_IDX);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2376
result->enc_pic_byte = vpu_read_reg(inst->dev, W5_RET_ENC_PIC_BYTE);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2377
result->enc_src_idx = vpu_read_reg(inst->dev, W5_RET_ENC_USED_SRC_IDX);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2378
p_enc_info->stream_wr_ptr = vpu_read_reg(inst->dev, W5_RET_ENC_WR_PTR);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2379
p_enc_info->stream_rd_ptr = vpu_read_reg(inst->dev, W5_RET_ENC_RD_PTR);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2381
result->bitstream_buffer = vpu_read_reg(inst->dev, W5_RET_ENC_RD_PTR);
drivers/media/platform/chips-media/wave5/wave5-hw.c
239
if (inst) {
drivers/media/platform/chips-media/wave5/wave5-hw.c
2393
result->enc_host_cmd_tick = vpu_read_reg(inst->dev, W5_RET_ENC_HOST_CMD_TICK);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2394
result->enc_encode_end_tick = vpu_read_reg(inst->dev, W5_RET_ENC_ENCODING_END_TICK);
drivers/media/platform/chips-media/wave5/wave5-hw.c
241
cmd_to_str(cmd, inst->type == VPU_INST_TYPE_DEC));
drivers/media/platform/chips-media/wave5/wave5-hw.c
2413
int wave5_vpu_enc_finish_seq(struct vpu_instance *inst, u32 *fail_res)
drivers/media/platform/chips-media/wave5/wave5-hw.c
2415
return send_firmware_command(inst, W5_DESTROY_INSTANCE, true, NULL, fail_res);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2418
static bool wave5_vpu_enc_check_common_param_valid(struct vpu_instance *inst,
drivers/media/platform/chips-media/wave5/wave5-hw.c
2423
struct vpu_device *vpu_dev = inst->dev;
drivers/media/platform/chips-media/wave5/wave5-hw.c
2429
if (inst->std == W_HEVC_ENC && low_delay &&
drivers/media/platform/chips-media/wave5/wave5-hw.c
2568
int wave5_vpu_enc_check_open_param(struct vpu_instance *inst, struct enc_open_param *open_param)
drivers/media/platform/chips-media/wave5/wave5-hw.c
2572
s32 product_id = inst->dev->product;
drivers/media/platform/chips-media/wave5/wave5-hw.c
2573
struct vpu_attr *p_attr = &inst->dev->attr;
drivers/media/platform/chips-media/wave5/wave5-hw.c
2583
if (inst->id >= MAX_NUM_INSTANCE) {
drivers/media/platform/chips-media/wave5/wave5-hw.c
2584
dev_err(inst->dev->dev, "Too many simultaneous instances: %d (max: %u)\n",
drivers/media/platform/chips-media/wave5/wave5-hw.c
2585
inst->id, MAX_NUM_INSTANCE);
drivers/media/platform/chips-media/wave5/wave5-hw.c
2589
if (inst->std != W_HEVC_ENC &&
drivers/media/platform/chips-media/wave5/wave5-hw.c
2590
!(inst->std == W_AVC_ENC && product_id == PRODUCT_ID_521)) {
drivers/media/platform/chips-media/wave5/wave5-hw.c
2591
dev_err(inst->dev->dev, "Unsupported encoder-codec & product combination\n");
drivers/media/platform/chips-media/wave5/wave5-hw.c
2596
if (inst->std == W_HEVC_ENC && !p_attr->support_hevc10bit_enc) {
drivers/media/platform/chips-media/wave5/wave5-hw.c
2597
dev_err(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-hw.c
2600
} else if (inst->std == W_AVC_ENC && !p_attr->support_avc10bit_enc) {
drivers/media/platform/chips-media/wave5/wave5-hw.c
2601
dev_err(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-hw.c
2608
dev_err(inst->dev->dev, "No frame rate information.\n");
drivers/media/platform/chips-media/wave5/wave5-hw.c
2613
dev_err(inst->dev->dev, "Invalid encoding bit-rate: %u (valid: 0-%u)\n",
drivers/media/platform/chips-media/wave5/wave5-hw.c
2620
dev_err(inst->dev->dev, "Invalid encoding dimension: %ux%u\n",
drivers/media/platform/chips-media/wave5/wave5-hw.c
2626
if (inst->std == W_HEVC_ENC) {
drivers/media/platform/chips-media/wave5/wave5-hw.c
2634
dev_err(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-hw.c
2639
} else if (inst->std == W_AVC_ENC) {
drivers/media/platform/chips-media/wave5/wave5-hw.c
2642
dev_err(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-hw.c
2651
dev_err(inst->dev->dev, "Invalid decoding refresh type: %u (valid: 0-2)\n",
drivers/media/platform/chips-media/wave5/wave5-hw.c
2657
dev_err(inst->dev->dev, "Invalid intra refresh mode: %d (valid: 0-4)\n",
drivers/media/platform/chips-media/wave5/wave5-hw.c
2662
if (inst->std == W_HEVC_ENC && param->independ_slice_mode &&
drivers/media/platform/chips-media/wave5/wave5-hw.c
2664
dev_err(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-hw.c
2671
dev_err(inst->dev->dev, "Invalid beta offset: %d (valid: -6-6)\n",
drivers/media/platform/chips-media/wave5/wave5-hw.c
2677
dev_err(inst->dev->dev, "Invalid tc offset: %d (valid: -6-6)\n",
drivers/media/platform/chips-media/wave5/wave5-hw.c
2684
dev_err(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-hw.c
2694
dev_err(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-hw.c
2703
dev_err(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-hw.c
2711
dev_err(inst->dev->dev, "VBV buffer size: %u (valid: %u-%u)\n",
drivers/media/platform/chips-media/wave5/wave5-hw.c
2718
if (!wave5_vpu_enc_check_common_param_valid(inst, open_param))
drivers/media/platform/chips-media/wave5/wave5-hw.c
2721
if (!wave5_vpu_enc_check_param_valid(inst->dev, open_param))
drivers/media/platform/chips-media/wave5/wave5-hw.c
2725
dev_err(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-hw.c
2732
dev_err(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-hw.c
2739
dev_err(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-hw.c
2744
if (inst->std == W_HEVC_ENC) {
drivers/media/platform/chips-media/wave5/wave5-hw.c
2748
dev_err(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-hw.c
275
static int send_firmware_command(struct vpu_instance *inst, u32 cmd, bool check_success,
drivers/media/platform/chips-media/wave5/wave5-hw.c
2758
dev_err(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-hw.c
280
wave5_bit_issue_command(inst->dev, inst, cmd);
drivers/media/platform/chips-media/wave5/wave5-hw.c
281
ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS);
drivers/media/platform/chips-media/wave5/wave5-hw.c
283
dev_warn(inst->dev->dev, "%s: command: '%s', timed out\n", __func__,
drivers/media/platform/chips-media/wave5/wave5-hw.c
284
cmd_to_str(cmd, inst->type == VPU_INST_TYPE_DEC));
drivers/media/platform/chips-media/wave5/wave5-hw.c
289
*queue_status = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS);
drivers/media/platform/chips-media/wave5/wave5-hw.c
297
return wave5_vpu_firmware_command_queue_error_check(inst->dev, fail_result);
drivers/media/platform/chips-media/wave5/wave5-hw.c
300
static int wave5_send_query(struct vpu_device *vpu_dev, struct vpu_instance *inst,
drivers/media/platform/chips-media/wave5/wave5-hw.c
307
wave5_bit_issue_command(vpu_dev, inst, W5_QUERY);
drivers/media/platform/chips-media/wave5/wave5-hw.c
531
int wave5_vpu_build_up_dec_param(struct vpu_instance *inst,
drivers/media/platform/chips-media/wave5/wave5-hw.c
535
struct dec_info *p_dec_info = &inst->codec_info->dec_info;
drivers/media/platform/chips-media/wave5/wave5-hw.c
536
struct vpu_device *vpu_dev = inst->dev;
drivers/media/platform/chips-media/wave5/wave5-hw.c
544
switch (inst->std) {
drivers/media/platform/chips-media/wave5/wave5-hw.c
560
ret = wave5_vdi_allocate_dma_memory(inst->dev, &p_dec_info->vb_work);
drivers/media/platform/chips-media/wave5/wave5-hw.c
564
if (inst->dev->product_code != WAVE515_CODE)
drivers/media/platform/chips-media/wave5/wave5-hw.c
565
vpu_write_reg(inst->dev, W5_CMD_DEC_VCORE_INFO, 1);
drivers/media/platform/chips-media/wave5/wave5-hw.c
567
wave5_vdi_clear_memory(inst->dev, &p_dec_info->vb_work);
drivers/media/platform/chips-media/wave5/wave5-hw.c
569
vpu_write_reg(inst->dev, W5_ADDR_WORK_BASE, p_dec_info->vb_work.daddr);
drivers/media/platform/chips-media/wave5/wave5-hw.c
570
vpu_write_reg(inst->dev, W5_WORK_SIZE, p_dec_info->vb_work.size);
drivers/media/platform/chips-media/wave5/wave5-hw.c
572
if (inst->dev->product_code != WAVE515_CODE) {
drivers/media/platform/chips-media/wave5/wave5-hw.c
573
vpu_write_reg(inst->dev, W5_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr);
drivers/media/platform/chips-media/wave5/wave5-hw.c
574
vpu_write_reg(inst->dev, W5_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size);
drivers/media/platform/chips-media/wave5/wave5-hw.c
577
vpu_write_reg(inst->dev, W5_CMD_DEC_BS_START_ADDR, p_dec_info->stream_buf_start_addr);
drivers/media/platform/chips-media/wave5/wave5-hw.c
578
vpu_write_reg(inst->dev, W5_CMD_DEC_BS_SIZE, p_dec_info->stream_buf_size);
drivers/media/platform/chips-media/wave5/wave5-hw.c
581
vpu_write_reg(inst->dev, W5_CMD_BS_PARAM, BITSTREAM_ENDIANNESS_BIG_ENDIAN);
drivers/media/platform/chips-media/wave5/wave5-hw.c
583
if (inst->dev->product_code != WAVE515_CODE) {
drivers/media/platform/chips-media/wave5/wave5-hw.c
585
vpu_write_reg(inst->dev, W5_CMD_EXT_ADDR, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
586
vpu_write_reg(inst->dev, W5_CMD_NUM_CQ_DEPTH_M1,
drivers/media/platform/chips-media/wave5/wave5-hw.c
589
vpu_write_reg(inst->dev, W5_CMD_ERR_CONCEAL, 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
590
ret = send_firmware_command(inst, W5_CREATE_INSTANCE, true, NULL, NULL);
drivers/media/platform/chips-media/wave5/wave5-hw.c
596
p_dec_info->product_code = vpu_read_reg(inst->dev, W5_PRODUCT_NUMBER);
drivers/media/platform/chips-media/wave5/wave5-hw.c
601
int wave5_vpu_hw_flush_instance(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-hw.c
603
struct dec_info *p_dec_info = &inst->codec_info->dec_info;
drivers/media/platform/chips-media/wave5/wave5-hw.c
609
ret = send_firmware_command(inst, W5_FLUSH_INSTANCE, true, ®_val, &fail_res);
drivers/media/platform/chips-media/wave5/wave5-hw.c
616
dev_warn(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-hw.c
636
int wave5_vpu_dec_init_seq(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-hw.c
638
struct dec_info *p_dec_info = &inst->codec_info->dec_info;
drivers/media/platform/chips-media/wave5/wave5-hw.c
643
if (!inst->codec_info)
drivers/media/platform/chips-media/wave5/wave5-hw.c
646
vpu_write_reg(inst->dev, W5_BS_RD_PTR, p_dec_info->stream_rd_ptr);
drivers/media/platform/chips-media/wave5/wave5-hw.c
647
vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr);
drivers/media/platform/chips-media/wave5/wave5-hw.c
652
if (inst->dev->product_code == WAVE515_CODE)
drivers/media/platform/chips-media/wave5/wave5-hw.c
655
vpu_write_reg(inst->dev, W5_BS_OPTION, bs_option);
drivers/media/platform/chips-media/wave5/wave5-hw.c
657
vpu_write_reg(inst->dev, W5_COMMAND_OPTION, cmd_option);
drivers/media/platform/chips-media/wave5/wave5-hw.c
658
vpu_write_reg(inst->dev, W5_CMD_DEC_USER_MASK, p_dec_info->user_data_enable);
drivers/media/platform/chips-media/wave5/wave5-hw.c
660
ret = send_firmware_command(inst, W5_INIT_SEQ, true, ®_val, &fail_res);
drivers/media/platform/chips-media/wave5/wave5-hw.c
667
dev_dbg(inst->dev->dev, "%s: init seq sent (queue %u : %u)\n", __func__,
drivers/media/platform/chips-media/wave5/wave5-hw.c
673
static void wave5_get_dec_seq_result(struct vpu_instance *inst, struct dec_initial_info *info)
drivers/media/platform/chips-media/wave5/wave5-hw.c
677
struct dec_info *p_dec_info = &inst->codec_info->dec_info;
drivers/media/platform/chips-media/wave5/wave5-hw.c
679
p_dec_info->stream_rd_ptr = wave5_dec_get_rd_ptr(inst);
drivers/media/platform/chips-media/wave5/wave5-hw.c
682
p_dec_info->frame_display_flag = vpu_read_reg(inst->dev, W5_RET_DEC_DISP_IDC);
drivers/media/platform/chips-media/wave5/wave5-hw.c
684
reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_SIZE);
drivers/media/platform/chips-media/wave5/wave5-hw.c
687
info->min_frame_buffer_count = vpu_read_reg(inst->dev, W5_RET_DEC_NUM_REQUIRED_FB);
drivers/media/platform/chips-media/wave5/wave5-hw.c
689
reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_CROP_LEFT_RIGHT);
drivers/media/platform/chips-media/wave5/wave5-hw.c
692
reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_CROP_TOP_BOTTOM);
drivers/media/platform/chips-media/wave5/wave5-hw.c
696
reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_COLOR_SAMPLE_INFO);
drivers/media/platform/chips-media/wave5/wave5-hw.c
700
reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_SEQ_PARAM);
drivers/media/platform/chips-media/wave5/wave5-hw.c
704
if (inst->std == W_HEVC_DEC) {
drivers/media/platform/chips-media/wave5/wave5-hw.c
717
} else if (inst->std == W_AVC_DEC) {
drivers/media/platform/chips-media/wave5/wave5-hw.c
721
if (inst->dev->product_code != WAVE515_CODE) {
drivers/media/platform/chips-media/wave5/wave5-hw.c
722
info->vlc_buf_size = vpu_read_reg(inst->dev, W5_RET_VLC_BUF_SIZE);
drivers/media/platform/chips-media/wave5/wave5-hw.c
723
info->param_buf_size = vpu_read_reg(inst->dev, W5_RET_PARAM_BUF_SIZE);
drivers/media/platform/chips-media/wave5/wave5-hw.c
729
int wave5_vpu_dec_get_seq_info(struct vpu_instance *inst, struct dec_initial_info *info)
drivers/media/platform/chips-media/wave5/wave5-hw.c
733
struct dec_info *p_dec_info = &inst->codec_info->dec_info;
drivers/media/platform/chips-media/wave5/wave5-hw.c
735
vpu_write_reg(inst->dev, W5_CMD_DEC_ADDR_REPORT_BASE, p_dec_info->user_data_buf_addr);
drivers/media/platform/chips-media/wave5/wave5-hw.c
736
vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_SIZE, p_dec_info->user_data_buf_size);
drivers/media/platform/chips-media/wave5/wave5-hw.c
737
vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_PARAM, REPORT_PARAM_ENDIANNESS_BIG_ENDIAN);
drivers/media/platform/chips-media/wave5/wave5-hw.c
740
ret = wave5_send_query(inst->dev, inst, GET_RESULT);
drivers/media/platform/chips-media/wave5/wave5-hw.c
744
reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS);
drivers/media/platform/chips-media/wave5/wave5-hw.c
749
dev_dbg(inst->dev->dev, "%s: init seq complete (queue %u : %u)\n", __func__,
drivers/media/platform/chips-media/wave5/wave5-hw.c
753
if (vpu_read_reg(inst->dev, W5_RET_DEC_DECODING_SUCCESS) != 1) {
drivers/media/platform/chips-media/wave5/wave5-hw.c
754
info->seq_init_err_reason = vpu_read_reg(inst->dev, W5_RET_DEC_ERR_INFO);
drivers/media/platform/chips-media/wave5/wave5-hw.c
758
wave5_get_dec_seq_result(inst, info);
drivers/media/platform/chips-media/wave5/wave5-hw.c
763
int wave5_vpu_dec_register_framebuffer(struct vpu_instance *inst, struct frame_buffer *fb_arr,
drivers/media/platform/chips-media/wave5/wave5-hw.c
767
struct dec_info *p_dec_info = &inst->codec_info->dec_info;
drivers/media/platform/chips-media/wave5/wave5-hw.c
781
cbcr_interleave = inst->cbcr_interleave;
drivers/media/platform/chips-media/wave5/wave5-hw.c
782
nv21 = inst->nv21;
drivers/media/platform/chips-media/wave5/wave5-hw.c
791
switch (inst->std) {
drivers/media/platform/chips-media/wave5/wave5-hw.c
804
if (inst->std == W_HEVC_DEC || inst->std == W_AVC_DEC) {
drivers/media/platform/chips-media/wave5/wave5-hw.c
806
ret = wave5_vdi_allocate_array(inst->dev, p_dec_info->vb_mv, count, size);
drivers/media/platform/chips-media/wave5/wave5-hw.c
817
ret = wave5_vdi_allocate_array(inst->dev, p_dec_info->vb_fbc_y_tbl, count, size);
drivers/media/platform/chips-media/wave5/wave5-hw.c
822
ret = wave5_vdi_allocate_array(inst->dev, p_dec_info->vb_fbc_c_tbl, count, size);
drivers/media/platform/chips-media/wave5/wave5-hw.c
828
if (inst->dev->product_code != WAVE515_CODE) {
drivers/media/platform/chips-media/wave5/wave5-hw.c
834
wave5_vdi_free_dma_memory(inst->dev,
drivers/media/platform/chips-media/wave5/wave5-hw.c
836
ret = wave5_vdi_allocate_dma_memory(inst->dev,
drivers/media/platform/chips-media/wave5/wave5-hw.c
844
vpu_write_reg(inst->dev, W5_CMD_SET_FB_ADDR_TASK_BUF,
drivers/media/platform/chips-media/wave5/wave5-hw.c
846
vpu_write_reg(inst->dev, W5_CMD_SET_FB_TASK_BUF_SIZE,
drivers/media/platform/chips-media/wave5/wave5-hw.c
852
if (inst->output_format == FORMAT_422)
drivers/media/platform/chips-media/wave5/wave5-hw.c
855
vpu_write_reg(inst->dev, W5_PIC_SIZE, pic_size);
drivers/media/platform/chips-media/wave5/wave5-hw.c
865
vpu_write_reg(inst->dev, W5_COMMON_PIC_INFO, reg_val);
drivers/media/platform/chips-media/wave5/wave5-hw.c
872
vpu_write_reg(inst->dev, W5_SFB_OPTION, reg_val);
drivers/media/platform/chips-media/wave5/wave5-hw.c
876
vpu_write_reg(inst->dev, W5_SET_FB_NUM, (start_no << 8) | end_no);
drivers/media/platform/chips-media/wave5/wave5-hw.c
882
vpu_write_reg(inst->dev, W5_ADDR_LUMA_BASE0 + (i << 4), addr_y);
drivers/media/platform/chips-media/wave5/wave5-hw.c
883
vpu_write_reg(inst->dev, W5_ADDR_CB_BASE0 + (i << 4), addr_cb);
drivers/media/platform/chips-media/wave5/wave5-hw.c
886
vpu_write_reg(inst->dev, W5_ADDR_FBC_Y_OFFSET0 + (i << 4),
drivers/media/platform/chips-media/wave5/wave5-hw.c
889
vpu_write_reg(inst->dev, W5_ADDR_FBC_C_OFFSET0 + (i << 4),
drivers/media/platform/chips-media/wave5/wave5-hw.c
891
vpu_write_reg(inst->dev, W5_ADDR_MV_COL0 + (i << 2),
drivers/media/platform/chips-media/wave5/wave5-hw.c
894
vpu_write_reg(inst->dev, W5_ADDR_CR_BASE0 + (i << 4), addr_cr);
drivers/media/platform/chips-media/wave5/wave5-hw.c
895
vpu_write_reg(inst->dev, W5_ADDR_FBC_C_OFFSET0 + (i << 4), 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
896
vpu_write_reg(inst->dev, W5_ADDR_MV_COL0 + (i << 2), 0);
drivers/media/platform/chips-media/wave5/wave5-hw.c
902
ret = send_firmware_command(inst, W5_SET_FB, false, NULL, NULL);
drivers/media/platform/chips-media/wave5/wave5-hw.c
907
reg_val = vpu_read_reg(inst->dev, W5_RET_SUCCESS);
drivers/media/platform/chips-media/wave5/wave5-hw.c
916
wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_task);
drivers/media/platform/chips-media/wave5/wave5-hw.c
919
wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_fbc_c_tbl[i]);
drivers/media/platform/chips-media/wave5/wave5-hw.c
922
wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_fbc_y_tbl[i]);
drivers/media/platform/chips-media/wave5/wave5-hw.c
925
wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_mv[i]);
drivers/media/platform/chips-media/wave5/wave5-hw.c
929
static u32 wave5_vpu_dec_validate_sec_axi(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-hw.c
931
u32 bitdepth = inst->codec_info->dec_info.initial_info.luma_bitdepth;
drivers/media/platform/chips-media/wave5/wave5-hw.c
932
struct dec_info *p_dec_info = &inst->codec_info->dec_info;
drivers/media/platform/chips-media/wave5/wave5-hw.c
934
u32 sram_size = inst->dev->sram_size;
drivers/media/platform/chips-media/wave5/wave5-hw.c
935
u32 width = inst->src_fmt.width;
drivers/media/platform/chips-media/wave5/wave5-hw.c
944
if (inst->dev->product_code == WAVE515_CODE) {
drivers/media/platform/chips-media/wave5/wave5-hw.c
966
int wave5_vpu_decode(struct vpu_instance *inst, u32 *fail_res)
drivers/media/platform/chips-media/wave5/wave5-hw.c
969
struct dec_info *p_dec_info = &inst->codec_info->dec_info;
drivers/media/platform/chips-media/wave5/wave5-hw.c
972
vpu_write_reg(inst->dev, W5_BS_RD_PTR, p_dec_info->stream_rd_ptr);
drivers/media/platform/chips-media/wave5/wave5-hw.c
973
vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr);
drivers/media/platform/chips-media/wave5/wave5-hw.c
975
vpu_write_reg(inst->dev, W5_BS_OPTION, get_bitstream_options(p_dec_info));
drivers/media/platform/chips-media/wave5/wave5-hw.c
978
reg_val = wave5_vpu_dec_validate_sec_axi(inst);
drivers/media/platform/chips-media/wave5/wave5-hw.c
979
vpu_write_reg(inst->dev, W5_USE_SEC_AXI, reg_val);
drivers/media/platform/chips-media/wave5/wave5-hw.c
982
vpu_write_reg(inst->dev, W5_CMD_DEC_USER_MASK, p_dec_info->user_data_enable);
drivers/media/platform/chips-media/wave5/wave5-hw.c
984
vpu_write_reg(inst->dev, W5_COMMAND_OPTION, DEC_PIC_NORMAL);
drivers/media/platform/chips-media/wave5/wave5-hw.c
985
vpu_write_reg(inst->dev, W5_CMD_DEC_TEMPORAL_ID_PLUS1,
drivers/media/platform/chips-media/wave5/wave5-hw.c
988
vpu_write_reg(inst->dev, W5_CMD_SEQ_CHANGE_ENABLE_FLAG, p_dec_info->seq_change_mask);
drivers/media/platform/chips-media/wave5/wave5-hw.c
990
vpu_write_reg(inst->dev, W5_CMD_DEC_FORCE_FB_LATENCY_PLUS1, !p_dec_info->reorder_enable);
drivers/media/platform/chips-media/wave5/wave5-hw.c
992
ret = send_firmware_command(inst, W5_DEC_ENC_PIC, true, ®_val, fail_res);
drivers/media/platform/chips-media/wave5/wave5-hw.c
999
dev_dbg(inst->dev->dev, "%s: dec pic sent (queue %u : %u)\n", __func__,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1004
if (inst->std == W_HEVC_DEC &&
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1005
inst->dev->attr.support_hevc10bit_dec)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1010
dev_err(inst->dev->dev, "no support for %d bit depth\n", bitdepth);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1016
non_linear_num = inst->fbc_buf_count;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1019
struct frame_buffer *frame = &inst->frame_buf[i];
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1020
struct vpu_buf *vframe = &inst->frame_vbuf[i];
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1022
fb_stride = ALIGN(inst->dst_fmt.width * bitdepth / 8, 32);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1023
fb_height = ALIGN(inst->dst_fmt.height, 32);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1032
wave5_vpu_dec_reset_framebuffer(inst, i);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1035
ret = wave5_vdi_allocate_dma_memory(inst->dev, vframe);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1037
dev_dbg(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1047
frame->width = inst->src_fmt.width;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1054
ret = wave5_vpu_dec_reset_framebuffer(inst, i);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1060
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1063
struct frame_buffer *frame = &inst->frame_buf[non_linear_num + i];
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1066
u32 fb_stride = inst->dst_fmt.width;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1067
u32 luma_size = fb_stride * inst->dst_fmt.height;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1070
if (inst->output_format == FORMAT_422)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1071
chroma_size = fb_stride * inst->dst_fmt.height / 2;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1073
chroma_size = fb_stride * inst->dst_fmt.height / 4;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1075
if (inst->dst_fmt.num_planes == 1) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
108
static int switch_state(struct vpu_instance *inst, enum vpu_instance_state state)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1080
} else if (inst->dst_fmt.num_planes == 2) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1086
} else if (inst->dst_fmt.num_planes == 3) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1099
frame->width = inst->src_fmt.width;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1105
ret = wave5_vpu_dec_register_frame_buffer_ex(inst, non_linear_num, linear_num,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1106
fb_stride, inst->dst_fmt.height);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1108
dev_dbg(inst->dev->dev, "%s: vpu_dec_register_frame_buffer_ex fail: %d",
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1118
ret = wave5_vpu_dec_set_disp_flag(inst, i);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1120
dev_dbg(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1129
ret = wave5_vpu_dec_clr_disp_flag(inst, vbuf->vb2_buf.index);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1131
dev_dbg(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1139
static int write_to_ringbuffer(struct vpu_instance *inst, void *buffer, size_t buffer_size,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
114
if (inst->state != VPU_INST_STATE_NONE)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1148
ret = wave5_vdi_write_memory(inst->dev, ring_buffer, offset, (u8 *)buffer, size);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1152
ret = wave5_vdi_write_memory(inst->dev, ring_buffer, 0, (u8 *)buffer + size,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1157
ret = wave5_vdi_write_memory(inst->dev, ring_buffer, offset, (u8 *)buffer,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1166
static struct vpu_src_buffer *inst_src_buf_remove(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1171
ret = mutex_lock_interruptible(&inst->feed_lock);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1175
if (list_empty(&inst->avail_src_bufs)) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1176
mutex_unlock(&inst->feed_lock);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1179
b = list_first_entry(&inst->avail_src_bufs, struct vpu_src_buffer, list);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
118
if (inst->state != VPU_INST_STATE_OPEN && inst->state != VPU_INST_STATE_STOP)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1181
mutex_unlock(&inst->feed_lock);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1185
static int fill_ringbuffer(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1187
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1195
dev_dbg(inst->dev->dev, "last src buffer already written\n");
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1200
while ((vpu_buf = inst_src_buf_remove(inst)) != NULL) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1202
struct vpu_buf *ring_buffer = &inst->bitstream_vbuf;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1210
dev_dbg(inst->dev->dev, "already copied src buf (%u) to the ring buffer\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1216
dev_dbg(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
122
if (inst->state != VPU_INST_STATE_INIT_SEQ)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1222
ret = wave5_vpu_dec_get_bitstream_buffer(inst, &rd_ptr, &wr_ptr, &remain_size);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1225
dev_err(inst->dev->dev, "Getting the bitstream buffer, fail: %d\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1230
dev_dbg(inst->dev->dev, "%s: rd_ptr %pad wr_ptr %pad", __func__, &rd_ptr, &wr_ptr);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1233
dev_dbg(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1239
ret = write_to_ringbuffer(inst, src_buf, src_size, ring_buffer, wr_ptr);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1241
dev_err(inst->dev->dev, "Write src buf (%u) to ring buffer, fail: %d\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1246
ret = wave5_vpu_dec_update_bitstream_buffer(inst, src_size);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1248
dev_dbg(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1258
dev_dbg(inst->dev->dev, "last src buffer written to the ring buffer\n");
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1262
inst->queuing_num++;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1271
struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1272
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1278
vbuf->sequence = inst->queued_src_buf_num++;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1279
ret = mutex_lock_interruptible(&inst->feed_lock);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1283
list_add_tail(&vpu_buf->list, &inst->avail_src_bufs);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1284
mutex_unlock(&inst->feed_lock);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1291
struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1292
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1294
pm_runtime_resume_and_get(inst->dev->dev);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1295
vbuf->sequence = inst->queued_dst_buf_num++;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1297
if (inst->state == VPU_INST_STATE_PIC_RUN) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
130
state_to_str(inst->state), state_to_str(state));
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1306
ret = wave5_vpu_dec_clr_disp_flag(inst, vb->index);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1308
dev_dbg(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1323
spin_lock_irqsave(&inst->state_spinlock, flags);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1324
send_eos_event(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1325
spin_unlock_irqrestore(&inst->state_spinlock, flags);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
133
dev_dbg(inst->dev->dev, "Switch state from %s to %s.\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1331
pm_runtime_put_autosuspend(inst->dev->dev);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1337
struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1339
dev_dbg(inst->dev->dev, "%s: type: %4u index: %4u size: ([0]=%4lu, [1]=%4lu, [2]=%4lu)\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
134
state_to_str(inst->state), state_to_str(state));
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1345
if (inst->empty_queue)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1346
inst->empty_queue = false;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
135
inst->state = state;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1352
static int wave5_vpu_dec_allocate_ring_buffer(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1355
struct vpu_buf *ring_buffer = &inst->bitstream_vbuf;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1357
ring_buffer->size = ALIGN(inst->src_fmt.plane_fmt[0].sizeimage, 1024) * 4;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1358
ret = wave5_vdi_allocate_dma_memory(inst->dev, ring_buffer);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1360
dev_dbg(inst->dev->dev, "%s: allocate ring buffer of size %zu fail: %d\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1365
inst->last_rd_ptr = ring_buffer->daddr;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1372
struct vpu_instance *inst = vb2_get_drv_priv(q);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1373
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1376
dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1377
pm_runtime_resume_and_get(inst->dev->dev);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1381
if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE && inst->state == VPU_INST_STATE_NONE) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1386
ret = wave5_vpu_dec_allocate_ring_buffer(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
139
static int set_instance_state(struct vpu_instance *inst, enum vpu_instance_state state)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1390
open_param.bitstream_buffer = inst->bitstream_vbuf.daddr;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1391
open_param.bitstream_buffer_size = inst->bitstream_vbuf.size;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1393
ret = wave5_vpu_dec_open(inst, &open_param);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1395
dev_dbg(inst->dev->dev, "%s: decoder opening, fail: %d\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1400
ret = switch_state(inst, VPU_INST_STATE_OPEN);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1405
&inst->codec_info->dec_info.initial_info;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1407
if (inst->state == VPU_INST_STATE_STOP)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1408
ret = switch_state(inst, VPU_INST_STATE_INIT_SEQ);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1412
if (inst->state == VPU_INST_STATE_INIT_SEQ &&
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1413
inst->dev->product_code == WAVE521C_CODE) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1415
dev_info(inst->dev->dev, "%s: no support for %d bit depth",
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1423
pm_runtime_put_autosuspend(inst->dev->dev);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1427
wave5_vdi_free_dma_memory(inst->dev, &inst->bitstream_vbuf);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1430
pm_runtime_put_autosuspend(inst->dev->dev);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1436
struct vpu_instance *inst = vb2_get_drv_priv(q);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1437
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
144
spin_lock_irqsave(&inst->state_spinlock, flags);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1445
inst->retry = false;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1446
inst->queuing_num = 0;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1447
while ((vpu_buf = inst_src_buf_remove(inst)) != NULL)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
145
ret = switch_state(inst, state);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1451
ret = wave5_vpu_dec_set_disp_flag(inst, i);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1453
dev_dbg(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1459
dev_dbg(inst->dev->dev, "%s: (Multiplanar) buf type %4u | index %4u\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
146
spin_unlock_irqrestore(&inst->state_spinlock, flags);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1464
while (wave5_vpu_dec_get_output_info(inst, &dec_info) == 0) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1466
wave5_vpu_dec_set_disp_flag(inst, dec_info.index_frame_display);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1469
ret = wave5_vpu_flush_instance(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1474
new_rd_ptr = wave5_vpu_dec_get_rd_ptr(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1475
inst->last_rd_ptr = new_rd_ptr;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1476
inst->codec_info->dec_info.stream_rd_ptr = new_rd_ptr;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1477
inst->codec_info->dec_info.stream_wr_ptr = new_rd_ptr;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1482
spin_lock_irqsave(&inst->state_spinlock, flags);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1483
send_eos_event(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1484
spin_unlock_irqrestore(&inst->state_spinlock, flags);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1488
inst->eos = false;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1495
struct vpu_instance *inst = vb2_get_drv_priv(q);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1496
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1502
ret = wave5_vpu_dec_set_disp_flag(inst, i);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1504
dev_dbg(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
151
static int wave5_vpu_dec_set_eos_on_firmware(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1512
dev_dbg(inst->dev->dev, "%s: buf type %4u | index %4u\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1515
for (plane = 0; plane < inst->dst_fmt.num_planes; plane++)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1521
if (inst->needs_reallocation) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1522
wave5_vpu_dec_give_command(inst, DEC_RESET_FRAMEBUF_INFO, NULL);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1523
inst->needs_reallocation = false;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1527
ret = switch_state(inst, VPU_INST_STATE_INIT_SEQ);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1537
struct vpu_instance *inst = vb2_get_drv_priv(q);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1538
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1542
dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1543
pm_runtime_resume_and_get(inst->dev->dev);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1544
inst->empty_queue = true;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1549
wave5_vpu_dec_give_command(inst, DEC_GET_QUEUE_STATUS, &q_status);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
155
ret = wave5_vpu_dec_update_bitstream_buffer(inst, 0);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1550
if ((inst->state == VPU_INST_STATE_STOP ||
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1551
inst->state == VPU_INST_STATE_INIT_SEQ ||
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1556
if (wave5_vpu_dec_get_output_info(inst, &dec_output_info))
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1557
dev_dbg(inst->dev->dev, "there is no output info\n");
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1567
inst->empty_queue = false;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1568
inst->sent_eos = false;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1569
pm_runtime_put_autosuspend(inst->dev->dev);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1602
static int initialize_sequence(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
161
dev_err(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1611
ret = wave5_vpu_dec_issue_seq_init(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1613
dev_dbg(inst->dev->dev, "%s: wave5_vpu_dec_issue_seq_init, fail: %d\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1618
if (wave5_vpu_wait_interrupt(inst, VPU_DEC_TIMEOUT) < 0)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1619
dev_dbg(inst->dev->dev, "%s: failed to call vpu_wait_interrupt()\n", __func__);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1621
ret = wave5_vpu_dec_complete_seq_init(inst, &initial_info);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1623
dev_dbg(inst->dev->dev, "%s: vpu_dec_complete_seq_init, fail: %d, reason: %u\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1625
wave5_handle_src_buffer(inst, initial_info.rd_ptr);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1629
spin_lock_irqsave(&inst->state_spinlock, flags);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1630
handle_dynamic_resolution_change(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1631
fbc_buf_count = inst->fbc_buf_count;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1632
spin_unlock_irqrestore(&inst->state_spinlock, flags);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1634
wave5_update_min_bufs_ctrl(inst, fbc_buf_count);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1639
static bool wave5_is_draining_or_eos(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1641
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1643
lockdep_assert_held(&inst->state_spinlock);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1644
return m2m_ctx->is_draining || inst->eos;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1649
struct vpu_instance *inst = priv;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1650
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1655
dev_dbg(inst->dev->dev, "%s: Fill the ring buffer with new bitstream data", __func__);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1656
pm_runtime_resume_and_get(inst->dev->dev);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1657
if (!inst->retry) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1658
ret = fill_ringbuffer(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1660
dev_warn(inst->dev->dev, "Filling ring buffer failed\n");
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1662
} else if (!inst->eos &&
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1663
inst->queuing_num == 0 &&
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1664
inst->state == VPU_INST_STATE_PIC_RUN) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1665
dev_dbg(inst->dev->dev, "%s: no bitstream for feeding, so skip ", __func__);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1666
inst->empty_queue = true;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1671
switch (inst->state) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1673
ret = initialize_sequence(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1678
spin_lock_irqsave(&inst->state_spinlock, flags);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1679
if (wave5_is_draining_or_eos(inst) &&
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1683
switch_state(inst, VPU_INST_STATE_STOP);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1686
send_eos_event(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1688
handle_dynamic_resolution_change(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1689
fbc_buf_count = inst->fbc_buf_count;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1692
flag_last_buffer_done(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1694
spin_unlock_irqrestore(&inst->state_spinlock, flags);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1696
wave5_update_min_bufs_ctrl(inst, fbc_buf_count);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1698
set_instance_state(inst, VPU_INST_STATE_INIT_SEQ);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1709
set_instance_state(inst, VPU_INST_STATE_PIC_RUN);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1714
wave5_vpu_dec_give_command(inst, DEC_GET_QUEUE_STATUS, &q_status);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1720
ret = wave5_prepare_fb(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1722
dev_warn(inst->dev->dev, "Framebuffer preparation, fail: %d\n", ret);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1723
set_instance_state(inst, VPU_INST_STATE_STOP);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1732
ret = start_decode(inst, &fail_res);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1734
dev_err(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1741
inst->retry = true;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1742
inst->queuing_fail = true;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1744
inst->retry = false;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1745
if (!inst->eos)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1746
inst->queuing_num--;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1750
dev_dbg(inst->dev->dev, "Execution of a job in state %s illegal.\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1751
state_to_str(inst->state));
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1755
dev_dbg(inst->dev->dev, "%s: leave and finish job", __func__);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1756
pm_runtime_put_autosuspend(inst->dev->dev);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1765
if (!inst->sent_eos)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1766
v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1771
struct vpu_instance *inst = priv;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1772
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1775
ret = set_instance_state(inst, VPU_INST_STATE_STOP);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1779
ret = wave5_vpu_dec_set_eos_on_firmware(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1781
dev_warn(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1784
v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1789
struct vpu_instance *inst = priv;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
179
static void wave5_handle_src_buffer(struct vpu_instance *inst, dma_addr_t rd_ptr)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1790
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1794
spin_lock_irqsave(&inst->state_spinlock, flags);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1796
switch (inst->state) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1798
dev_dbg(inst->dev->dev, "Decoder must be open to start queueing M2M jobs!\n");
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1801
if (wave5_is_draining_or_eos(inst) || !v4l2_m2m_has_stopped(m2m_ctx) ||
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1807
dev_dbg(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
181
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1813
dev_dbg(inst->dev->dev, "CAPTURE queue must be streaming to queue jobs!\n");
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1815
} else if (v4l2_m2m_num_dst_bufs_ready(m2m_ctx) < (inst->fbc_buf_count - 1)) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1816
dev_dbg(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1819
} else if (!wave5_is_draining_or_eos(inst) &&
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1821
inst->empty_queue)) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1822
dev_dbg(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1825
} else if (inst->state == VPU_INST_STATE_PIC_RUN &&
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1826
!wave5_is_draining_or_eos(inst) &&
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1827
inst->queuing_fail) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1833
dev_dbg(inst->dev->dev, "Decoder is stopped, not running.\n");
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1837
spin_unlock_irqrestore(&inst->state_spinlock, flags);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
185
if (rd_ptr >= inst->last_rd_ptr) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1852
struct vpu_instance *inst = NULL;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1856
inst = kzalloc_obj(*inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1857
if (!inst)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
186
consumed_bytes = rd_ptr - inst->last_rd_ptr;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1860
inst->dev = dev;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1861
inst->type = VPU_INST_TYPE_DEC;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1862
inst->ops = &wave5_vpu_dec_inst_ops;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1864
spin_lock_init(&inst->state_spinlock);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1865
mutex_init(&inst->feed_lock);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1866
INIT_LIST_HEAD(&inst->avail_src_bufs);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1868
inst->codec_info = kzalloc_obj(*inst->codec_info);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1869
if (!inst->codec_info) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1870
kfree(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1874
v4l2_fh_init(&inst->v4l2_fh, vdev);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1875
v4l2_fh_add(&inst->v4l2_fh, filp);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1877
INIT_LIST_HEAD(&inst->list);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1879
inst->v4l2_m2m_dev = inst->dev->v4l2_m2m_dec_dev;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
188
size_t rd_offs = rd_ptr - inst->bitstream_vbuf.daddr;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1880
inst->v4l2_fh.m2m_ctx =
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1881
v4l2_m2m_ctx_init(inst->v4l2_m2m_dev, inst, wave5_vpu_dec_queue_init);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1882
if (IS_ERR(inst->v4l2_fh.m2m_ctx)) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1883
ret = PTR_ERR(inst->v4l2_fh.m2m_ctx);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1886
m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
189
size_t last_rd_offs = inst->last_rd_ptr - inst->bitstream_vbuf.daddr;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1905
v4l2_ctrl_handler_init(&inst->v4l2_ctrl_hdl, 10);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1906
v4l2_ctrl_new_std(&inst->v4l2_ctrl_hdl, NULL,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1909
if (inst->v4l2_ctrl_hdl.error) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
191
consumed_bytes = rd_offs + (inst->bitstream_vbuf.size - last_rd_offs);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1914
inst->v4l2_fh.ctrl_handler = &inst->v4l2_ctrl_hdl;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1915
v4l2_ctrl_handler_setup(&inst->v4l2_ctrl_hdl);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1917
wave5_set_default_format(&inst->src_fmt, &inst->dst_fmt);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1918
inst->colorspace = V4L2_COLORSPACE_REC709;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1919
inst->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1920
inst->quantization = V4L2_QUANTIZATION_DEFAULT;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1921
inst->xfer_func = V4L2_XFER_FUNC_DEFAULT;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1923
init_completion(&inst->irq_done);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1924
ret = wave5_kfifo_alloc(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1926
dev_err(inst->dev->dev, "failed to allocate fifo\n");
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1930
inst->id = ida_alloc(&inst->dev->inst_ida, GFP_KERNEL);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1931
if (inst->id < 0) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1932
dev_warn(inst->dev->dev, "Allocating instance ID, fail: %d\n", inst->id);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1933
ret = inst->id;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
194
inst->last_rd_ptr = rd_ptr;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1941
if (inst->dev->product_code != WAVE515_CODE)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1942
wave5_vdi_allocate_sram(inst->dev);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1948
list_add_tail(&inst->list, &dev->instances);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
195
consumed_bytes += inst->remaining_consumed_bytes;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
1955
wave5_cleanup_instance(inst, filp);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
197
dev_dbg(inst->dev->dev, "%s: %zu bytes of bitstream was consumed", __func__,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
207
dev_dbg(inst->dev->dev, "%s: removing src buffer %i",
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
210
inst->timestamp = src_buf->vb2_buf.timestamp;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
219
ret = wave5_vpu_dec_set_eos_on_firmware(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
221
dev_warn(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
227
inst->remaining_consumed_bytes = consumed_bytes;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
230
static int start_decode(struct vpu_instance *inst, u32 *fail_res)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
232
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
235
ret = wave5_vpu_dec_start_one_frame(inst, fail_res);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
242
set_instance_state(inst, VPU_INST_STATE_STOP);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
244
dev_dbg(inst->dev->dev, "%s: pic run failed / finish job", __func__);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
245
v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
251
static void flag_last_buffer_done(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
253
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
257
lockdep_assert_held(&inst->state_spinlock);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
273
static void send_eos_event(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
279
lockdep_assert_held(&inst->state_spinlock);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
281
v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_eos);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
282
inst->eos = false;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
283
inst->sent_eos = true;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
286
static void wave5_update_min_bufs_ctrl(struct vpu_instance *inst, u32 fbc_buf_count)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
288
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
294
ctrl = v4l2_ctrl_find(&inst->v4l2_ctrl_hdl,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
300
static int handle_dynamic_resolution_change(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
302
struct v4l2_fh *fh = &inst->v4l2_fh;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
308
struct dec_info *p_dec_info = &inst->codec_info->dec_info;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
309
struct dec_initial_info *initial_info = &inst->codec_info->dec_info.initial_info;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
311
lockdep_assert_held(&inst->state_spinlock);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
313
dev_dbg(inst->dev->dev, "%s: rd_ptr %pad", __func__, &initial_info->rd_ptr);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
315
dev_dbg(inst->dev->dev, "%s: width: %u height: %u profile: %u | minbuffer: %u\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
319
inst->needs_reallocation = true;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
320
inst->fbc_buf_count = initial_info->min_frame_buffer_count + 1;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
325
inst->conf_win.left = initial_info->pic_crop_rect.left;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
326
inst->conf_win.top = initial_info->pic_crop_rect.top;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
327
inst->conf_win.width = initial_info->pic_width -
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
329
inst->conf_win.height = initial_info->pic_height -
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
332
vpu_fmt = wave5_find_vpu_fmt(inst->src_fmt.pixelformat,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
337
wave5_update_pix_fmt(&inst->src_fmt,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
343
vpu_fmt = wave5_find_vpu_fmt(inst->dst_fmt.pixelformat,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
348
wave5_update_pix_fmt(&inst->dst_fmt,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
360
static void wave5_vpu_dec_finish_decode(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
362
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
369
dev_dbg(inst->dev->dev, "%s: Fetch output info from firmware.", __func__);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
371
ret = wave5_vpu_dec_get_output_info(inst, &dec_info);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
373
dev_dbg(inst->dev->dev, "%s: could not get output info.", __func__);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
374
v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
378
dev_dbg(inst->dev->dev, "%s: rd_ptr %pad wr_ptr %pad", __func__, &dec_info.rd_ptr,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
380
wave5_handle_src_buffer(inst, dec_info.rd_ptr);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
382
dev_dbg(inst->dev->dev, "%s: dec_info dec_idx %i disp_idx %i", __func__,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
386
dev_dbg(inst->dev->dev, "%s: capture is not streaming..", __func__);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
387
v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
399
dec_buf->vb2_buf.timestamp = inst->timestamp;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
401
dev_warn(inst->dev->dev, "%s: invalid decoded frame index %i",
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
409
dev_warn(inst->dev->dev, "%s: invalid display frame index %i",
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
417
if (inst->dst_fmt.num_planes == 1) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
419
inst->dst_fmt.plane_fmt[0].sizeimage);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
420
} else if (inst->dst_fmt.num_planes == 2) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
422
inst->dst_fmt.plane_fmt[0].sizeimage);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
424
inst->dst_fmt.plane_fmt[1].sizeimage);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
425
} else if (inst->dst_fmt.num_planes == 3) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
427
inst->dst_fmt.plane_fmt[0].sizeimage);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
429
inst->dst_fmt.plane_fmt[1].sizeimage);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
431
inst->dst_fmt.plane_fmt[2].sizeimage);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
439
dev_dbg(inst->dev->dev, "%s: frame_cycle %8u (payload %lu)\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
449
spin_lock_irqsave(&inst->state_spinlock, flags);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
451
switch_state(inst, VPU_INST_STATE_STOP);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
454
handle_dynamic_resolution_change(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
455
fbc_buf_count = inst->fbc_buf_count;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
457
send_eos_event(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
460
flag_last_buffer_done(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
462
spin_unlock_irqrestore(&inst->state_spinlock, flags);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
464
wave5_update_min_bufs_ctrl(inst, fbc_buf_count);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
467
if (inst->sent_eos &&
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
468
v4l2_m2m_get_curr_priv(inst->v4l2_m2m_dev)) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
471
wave5_vpu_dec_give_command(inst, DEC_GET_QUEUE_STATUS, &q_status);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
474
v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
477
inst->queuing_fail = false;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
529
struct vpu_instance *inst = file_to_vpu_inst(file);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
530
struct dec_info *p_dec_info = &inst->codec_info->dec_info;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
535
dev_dbg(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
542
width = inst->dst_fmt.width;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
543
height = inst->dst_fmt.height;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
544
f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
554
width = inst->dst_fmt.width;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
555
height = inst->dst_fmt.height;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
560
f->fmt.pix_mp.colorspace = inst->colorspace;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
561
f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
562
f->fmt.pix_mp.quantization = inst->quantization;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
563
f->fmt.pix_mp.xfer_func = inst->xfer_func;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
570
struct vpu_instance *inst = file_to_vpu_inst(file);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
573
dev_dbg(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
582
inst->dst_fmt.width = f->fmt.pix_mp.width;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
583
inst->dst_fmt.height = f->fmt.pix_mp.height;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
584
inst->dst_fmt.pixelformat = f->fmt.pix_mp.pixelformat;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
585
inst->dst_fmt.field = f->fmt.pix_mp.field;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
586
inst->dst_fmt.flags = f->fmt.pix_mp.flags;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
587
inst->dst_fmt.num_planes = f->fmt.pix_mp.num_planes;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
588
for (i = 0; i < inst->dst_fmt.num_planes; i++) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
589
inst->dst_fmt.plane_fmt[i].bytesperline = f->fmt.pix_mp.plane_fmt[i].bytesperline;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
590
inst->dst_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
593
if (inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV12 ||
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
594
inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV12M) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
595
inst->cbcr_interleave = true;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
596
inst->nv21 = false;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
597
inst->output_format = FORMAT_420;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
598
} else if (inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV21 ||
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
599
inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV21M) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
600
inst->cbcr_interleave = true;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
601
inst->nv21 = true;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
602
inst->output_format = FORMAT_420;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
603
} else if (inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV16 ||
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
604
inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV16M) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
605
inst->cbcr_interleave = true;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
606
inst->nv21 = false;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
607
inst->output_format = FORMAT_422;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
608
} else if (inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV61 ||
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
609
inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV61M) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
610
inst->cbcr_interleave = true;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
611
inst->nv21 = true;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
612
inst->output_format = FORMAT_422;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
613
} else if (inst->dst_fmt.pixelformat == V4L2_PIX_FMT_YUV422P ||
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
614
inst->dst_fmt.pixelformat == V4L2_PIX_FMT_YUV422M) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
615
inst->cbcr_interleave = false;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
616
inst->nv21 = false;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
617
inst->output_format = FORMAT_422;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
619
inst->cbcr_interleave = false;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
620
inst->nv21 = false;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
621
inst->output_format = FORMAT_420;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
629
struct vpu_instance *inst = file_to_vpu_inst(file);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
632
f->fmt.pix_mp.width = inst->dst_fmt.width;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
633
f->fmt.pix_mp.height = inst->dst_fmt.height;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
634
f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
635
f->fmt.pix_mp.field = inst->dst_fmt.field;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
636
f->fmt.pix_mp.flags = inst->dst_fmt.flags;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
637
f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
639
f->fmt.pix_mp.plane_fmt[i].bytesperline = inst->dst_fmt.plane_fmt[i].bytesperline;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
640
f->fmt.pix_mp.plane_fmt[i].sizeimage = inst->dst_fmt.plane_fmt[i].sizeimage;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
643
f->fmt.pix_mp.colorspace = inst->colorspace;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
644
f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
645
f->fmt.pix_mp.quantization = inst->quantization;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
646
f->fmt.pix_mp.xfer_func = inst->xfer_func;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
653
struct vpu_instance *inst = file_to_vpu_inst(file);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
656
dev_dbg(inst->dev->dev, "%s: index: %u\n", __func__, f->index);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
670
struct vpu_instance *inst = file_to_vpu_inst(file);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
675
dev_dbg(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
682
width = inst->src_fmt.width;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
683
height = inst->src_fmt.height;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
684
f->fmt.pix_mp.pixelformat = inst->src_fmt.pixelformat;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
701
struct vpu_instance *inst = file_to_vpu_inst(file);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
705
dev_dbg(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
714
inst->std = wave5_to_vpu_std(f->fmt.pix_mp.pixelformat, inst->type);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
715
if (inst->std == STD_UNKNOWN) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
716
dev_warn(inst->dev->dev, "unsupported pixelformat: %.4s\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
721
inst->src_fmt.width = f->fmt.pix_mp.width;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
722
inst->src_fmt.height = f->fmt.pix_mp.height;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
723
inst->src_fmt.pixelformat = f->fmt.pix_mp.pixelformat;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
724
inst->src_fmt.field = f->fmt.pix_mp.field;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
725
inst->src_fmt.flags = f->fmt.pix_mp.flags;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
726
inst->src_fmt.num_planes = f->fmt.pix_mp.num_planes;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
727
for (i = 0; i < inst->src_fmt.num_planes; i++) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
728
inst->src_fmt.plane_fmt[i].bytesperline = f->fmt.pix_mp.plane_fmt[i].bytesperline;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
729
inst->src_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
732
inst->colorspace = f->fmt.pix_mp.colorspace;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
733
inst->ycbcr_enc = f->fmt.pix_mp.ycbcr_enc;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
734
inst->quantization = f->fmt.pix_mp.quantization;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
735
inst->xfer_func = f->fmt.pix_mp.xfer_func;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
737
vpu_fmt = wave5_find_vpu_fmt(inst->dst_fmt.pixelformat, dec_fmt_list[VPU_FMT_TYPE_RAW]);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
741
wave5_update_pix_fmt(&inst->dst_fmt, VPU_FMT_TYPE_RAW,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
750
struct vpu_instance *inst = file_to_vpu_inst(file);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
752
dev_dbg(inst->dev->dev, "%s: type: %u | target: %u\n", __func__, s->type, s->target);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
761
s->r.width = inst->dst_fmt.width;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
762
s->r.height = inst->dst_fmt.height;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
768
if (inst->state > VPU_INST_STATE_OPEN) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
769
s->r = inst->conf_win;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
771
s->r.width = inst->src_fmt.width;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
772
s->r.height = inst->src_fmt.height;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
784
struct vpu_instance *inst = file_to_vpu_inst(file);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
792
dev_dbg(inst->dev->dev, "V4L2_SEL_TGT_COMPOSE w: %u h: %u\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
797
s->r.width = inst->dst_fmt.width;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
798
s->r.height = inst->dst_fmt.height;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
803
static int wave5_vpu_dec_stop(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
807
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
809
spin_lock_irqsave(&inst->state_spinlock, flags);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
816
if (inst->state != VPU_INST_STATE_NONE) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
821
spin_unlock_irqrestore(&inst->state_spinlock, flags);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
822
ret = wave5_vpu_dec_set_eos_on_firmware(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
826
spin_lock_irqsave(&inst->state_spinlock, flags);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
841
inst->eos = true;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
858
if (inst->state == VPU_INST_STATE_NONE) {
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
859
send_eos_event(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
860
flag_last_buffer_done(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
864
spin_unlock_irqrestore(&inst->state_spinlock, flags);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
868
static int wave5_vpu_dec_start(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
872
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
875
spin_lock_irqsave(&inst->state_spinlock, flags);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
886
inst->eos = false;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
889
spin_unlock_irqrestore(&inst->state_spinlock, flags);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
895
struct vpu_instance *inst = file_to_vpu_inst(file);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
896
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
899
dev_dbg(inst->dev->dev, "decoder command: %u\n", dc->cmd);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
907
ret = wave5_vpu_dec_stop(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
912
ret = wave5_vpu_dec_start(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
963
struct vpu_instance *inst = vb2_get_drv_priv(q);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
965
(q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ? inst->src_fmt : inst->dst_fmt;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
968
dev_dbg(inst->dev->dev, "%s: num_buffers: %u | num_planes: %u | type: %u\n", __func__,
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
975
dev_dbg(inst->dev->dev, "%s: size[0]: %u\n", __func__, sizes[0]);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
977
if (*num_buffers < inst->fbc_buf_count)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
978
*num_buffers = inst->fbc_buf_count;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
982
dev_dbg(inst->dev->dev, "%s: size[%u]: %u\n", __func__, i, sizes[i]);
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
989
static int wave5_prepare_fb(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
997
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
998
u32 bitdepth = inst->codec_info->dec_info.initial_info.luma_bitdepth;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1001
inst->enc_param.level = 32;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1004
inst->enc_param.level = 40;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1007
inst->enc_param.level = 41;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1010
inst->enc_param.level = 42;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1013
inst->enc_param.level = 50;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1016
inst->enc_param.level = 51;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1023
inst->enc_param.min_qp_i = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1024
inst->enc_param.min_qp_p = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1025
inst->enc_param.min_qp_b = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1028
inst->enc_param.max_qp_i = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1029
inst->enc_param.max_qp_p = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1030
inst->enc_param.max_qp_b = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1033
inst->enc_param.intra_qp = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1038
inst->enc_param.disable_deblk = 1;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1039
inst->enc_param.lf_cross_slice_boundary_enable = 1;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1042
inst->enc_param.disable_deblk = 0;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1043
inst->enc_param.lf_cross_slice_boundary_enable = 1;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1046
inst->enc_param.disable_deblk = 0;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1047
inst->enc_param.lf_cross_slice_boundary_enable = 0;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1054
inst->enc_param.beta_offset_div2 = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1057
inst->enc_param.tc_offset_div2 = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1060
inst->enc_param.transform8x8_enable = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1063
inst->enc_param.const_intra_pred_flag = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1066
inst->enc_param.chroma_cb_qp_offset = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1067
inst->enc_param.chroma_cr_qp_offset = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1070
inst->enc_param.intra_period = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1073
inst->enc_param.entropy_coding_mode = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1076
inst->enc_param.forced_idr_header_enable = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1095
struct vpu_instance *inst = vb2_get_drv_priv(q);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1097
(q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ? inst->src_fmt : inst->dst_fmt;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1100
dev_dbg(inst->dev->dev, "%s: num_buffers: %u | num_planes: %u | type: %u\n", __func__,
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1115
dev_dbg(inst->dev->dev, "%s: size[%u]: %u\n", __func__, i, sizes[i]);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1119
dev_dbg(inst->dev->dev, "%s: size: %u\n", __func__, sizes[0]);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
112
static int switch_state(struct vpu_instance *inst, enum vpu_instance_state state)
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1127
struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1128
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1130
dev_dbg(inst->dev->dev, "%s: type: %4u index: %4u size: ([0]=%4lu, [1]=%4lu, [2]=%4lu)\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1135
vbuf->sequence = inst->queued_src_buf_num++;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1137
vbuf->sequence = inst->queued_dst_buf_num++;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1143
struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1145
struct enc_wave_param input = inst->enc_param;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1147
u32 num_ctu_row = ALIGN(inst->dst_fmt.height, 64) / 64;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1148
u32 num_mb_row = ALIGN(inst->dst_fmt.height, 16) / 16;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1150
info = v4l2_format_info(inst->src_fmt.pixelformat);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
118
if (inst->state != VPU_INST_STATE_NONE)
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1190
open_param->pic_width = inst->conf_win.width;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1191
open_param->pic_height = inst->conf_win.height;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1192
open_param->frame_rate_info = inst->frame_rate;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1193
open_param->rc_enable = inst->rc_enable;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1194
if (inst->rc_enable) {
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1202
open_param->bit_rate = inst->bit_rate;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1203
open_param->vbv_buffer_size = inst->vbv_buf_size;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1204
if (inst->rc_mode == 0)
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1209
open_param->wave_param.internal_bit_depth = inst->bit_depth;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
122
if (inst->state != VPU_INST_STATE_OPEN && inst->state != VPU_INST_STATE_STOP)
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1225
if (inst->std == W_HEVC_ENC) {
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
126
if (inst->state != VPU_INST_STATE_INIT_SEQ)
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1269
static int initialize_sequence(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1275
ret = wave5_vpu_enc_issue_seq_init(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1277
dev_err(inst->dev->dev, "%s: wave5_vpu_enc_issue_seq_init, fail: %d\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1282
if (wave5_vpu_wait_interrupt(inst, VPU_ENC_TIMEOUT) < 0) {
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1283
dev_err(inst->dev->dev, "%s: wave5_vpu_wait_interrupt failed\n", __func__);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1287
ret = wave5_vpu_enc_complete_seq_init(inst, &initial_info);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1291
dev_dbg(inst->dev->dev, "%s: min_frame_buffer: %u | min_source_buffer: %u\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1294
inst->min_src_buf_count = initial_info.min_src_frame_count +
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1297
ctrl = v4l2_ctrl_find(&inst->v4l2_ctrl_hdl,
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1300
v4l2_ctrl_s_ctrl(ctrl, inst->min_src_buf_count);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1302
inst->fbc_buf_count = initial_info.min_frame_buffer_count;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1307
static int prepare_fb(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1309
u32 fb_stride = ALIGN(inst->dst_fmt.width, 32);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1310
u32 fb_height = ALIGN(inst->dst_fmt.height, 32);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1313
for (i = 0; i < inst->fbc_buf_count; i++) {
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1317
inst->frame_vbuf[i].size = luma_size + chroma_size;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1318
ret = wave5_vdi_allocate_dma_memory(inst->dev, &inst->frame_vbuf[i]);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1320
dev_err(inst->dev->dev, "%s: failed to allocate FBC buffer %zu\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1321
__func__, inst->frame_vbuf[i].size);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1325
inst->frame_buf[i].buf_y = inst->frame_vbuf[i].daddr;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1326
inst->frame_buf[i].buf_cb = (dma_addr_t)-1;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1327
inst->frame_buf[i].buf_cr = (dma_addr_t)-1;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1328
inst->frame_buf[i].update_fb_info = true;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1329
inst->frame_buf[i].size = inst->frame_vbuf[i].size;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
133
dev_dbg(inst->dev->dev, "Switch state from %s to %s.\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1332
ret = wave5_vpu_enc_register_frame_buffer(inst, inst->fbc_buf_count, fb_stride,
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1335
dev_err(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
134
state_to_str(inst->state), state_to_str(state));
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1343
for (i = 0; i < inst->fbc_buf_count; i++)
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1344
wave5_vpu_dec_reset_framebuffer(inst, i);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
135
inst->state = state;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1350
struct vpu_instance *inst = vb2_get_drv_priv(q);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1351
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1354
pm_runtime_resume_and_get(inst->dev->dev);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1357
if (inst->state == VPU_INST_STATE_NONE && q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1362
ret = wave5_set_enc_openparam(&open_param, inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1364
dev_dbg(inst->dev->dev, "%s: wave5_set_enc_openparam, fail: %d\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1369
ret = wave5_vpu_enc_open(inst, &open_param);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1371
dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_open, fail: %d\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1376
if (inst->mirror_direction) {
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1377
wave5_vpu_enc_give_command(inst, ENABLE_MIRRORING, NULL);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1378
wave5_vpu_enc_give_command(inst, SET_MIRROR_DIRECTION,
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1379
&inst->mirror_direction);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1381
if (inst->rot_angle) {
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1382
wave5_vpu_enc_give_command(inst, ENABLE_ROTATION, NULL);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1383
wave5_vpu_enc_give_command(inst, SET_ROTATION_ANGLE, &inst->rot_angle);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1386
ret = switch_state(inst, VPU_INST_STATE_OPEN);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1390
if (inst->state == VPU_INST_STATE_OPEN &&
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1392
ret = initialize_sequence(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1394
dev_warn(inst->dev->dev, "Sequence not found: %d\n", ret);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1397
ret = switch_state(inst, VPU_INST_STATE_INIT_SEQ);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
140
state_to_str(inst->state), state_to_str(state));
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1404
ret = prepare_fb(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1406
dev_warn(inst->dev->dev, "Framebuffer preparation, fail: %d\n", ret);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1410
ret = switch_state(inst, VPU_INST_STATE_PIC_RUN);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1415
pm_runtime_put_autosuspend(inst->dev->dev);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1419
pm_runtime_put_autosuspend(inst->dev->dev);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1423
static void streamoff_output(struct vpu_instance *inst, struct vb2_queue *q)
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1425
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1429
dev_dbg(inst->dev->dev, "%s: buf type %4u | index %4u\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1435
static void streamoff_capture(struct vpu_instance *inst, struct vb2_queue *q)
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1437
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
144
static int start_encode(struct vpu_instance *inst, u32 *fail_res)
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1441
dev_dbg(inst->dev->dev, "%s: buf type %4u | index %4u\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1452
struct vpu_instance *inst = vb2_get_drv_priv(q);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
146
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1460
dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1461
pm_runtime_resume_and_get(inst->dev->dev);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1463
if (wave5_vpu_both_queues_are_streaming(inst))
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1464
switch_state(inst, VPU_INST_STATE_STOP);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1470
wave5_vpu_enc_give_command(inst, ENC_GET_QUEUE_STATUS, &q_status);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1475
if (wave5_vpu_wait_interrupt(inst, VPU_ENC_TIMEOUT) < 0)
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1478
if (wave5_vpu_enc_get_output_info(inst, &enc_output_info))
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1479
dev_dbg(inst->dev->dev, "Getting encoding results from fw, fail\n");
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1483
streamoff_output(inst, q);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1485
streamoff_capture(inst, q);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1487
pm_runtime_put_autosuspend(inst->dev->dev);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1522
struct vpu_instance *inst = priv;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1523
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1527
pm_runtime_resume_and_get(inst->dev->dev);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1528
switch (inst->state) {
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
153
u32 stride = inst->src_fmt.plane_fmt[0].bytesperline;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1530
ret = start_encode(inst, &fail_res);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1533
dev_err(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1537
dev_dbg(inst->dev->dev, "Missing buffers for encode, try again\n");
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1540
dev_dbg(inst->dev->dev, "%s: leave with active job", __func__);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1541
pm_runtime_put_autosuspend(inst->dev->dev);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1545
state_to_str(inst->state));
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1548
dev_dbg(inst->dev->dev, "%s: leave and finish job", __func__);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1549
pm_runtime_put_autosuspend(inst->dev->dev);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1550
v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1555
struct vpu_instance *inst = priv;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1556
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1558
switch (inst->state) {
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1560
dev_dbg(inst->dev->dev, "Encoder must be open to start queueing M2M jobs!\n");
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1564
dev_dbg(inst->dev->dev, "Encoder ready for a job, state: %s\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1565
state_to_str(inst->state));
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1570
dev_dbg(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1572
state_to_str(inst->state), m2m_ctx->is_draining ? "is" : "is not",
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1588
struct vpu_instance *inst = NULL;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1592
inst = kzalloc_obj(*inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1593
if (!inst)
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1595
v4l2_ctrl_hdl = &inst->v4l2_ctrl_hdl;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1597
inst->dev = dev;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1598
inst->type = VPU_INST_TYPE_ENC;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1599
inst->ops = &wave5_vpu_enc_inst_ops;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
160
info = v4l2_format_info(inst->src_fmt.pixelformat);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1601
inst->codec_info = kzalloc_obj(*inst->codec_info);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1602
if (!inst->codec_info) {
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1603
kfree(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1607
v4l2_fh_init(&inst->v4l2_fh, vdev);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1608
v4l2_fh_add(&inst->v4l2_fh, filp);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1610
INIT_LIST_HEAD(&inst->list);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1612
inst->v4l2_m2m_dev = inst->dev->v4l2_m2m_enc_dev;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1613
inst->v4l2_fh.m2m_ctx =
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1614
v4l2_m2m_ctx_init(inst->v4l2_m2m_dev, inst, wave5_vpu_enc_queue_init);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1615
if (IS_ERR(inst->v4l2_fh.m2m_ctx)) {
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1616
ret = PTR_ERR(inst->v4l2_fh.m2m_ctx);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1619
v4l2_m2m_set_src_buffered(inst->v4l2_fh.m2m_ctx, true);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
165
luma_size = stride * inst->dst_fmt.height;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
168
luma_size = inst->src_fmt.plane_fmt[0].sizeimage;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
169
chroma_size = inst->src_fmt.plane_fmt[1].sizeimage;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
174
dev_dbg(inst->dev->dev, "%s: No destination buffer found\n", __func__);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1770
inst->v4l2_fh.ctrl_handler = v4l2_ctrl_hdl;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1773
wave5_set_default_format(&inst->src_fmt, &inst->dst_fmt);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1774
inst->conf_win.width = inst->dst_fmt.width;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1775
inst->conf_win.height = inst->dst_fmt.height;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1776
inst->colorspace = V4L2_COLORSPACE_REC709;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1777
inst->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1778
inst->quantization = V4L2_QUANTIZATION_DEFAULT;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1779
inst->xfer_func = V4L2_XFER_FUNC_DEFAULT;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1780
inst->frame_rate = 30;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1782
init_completion(&inst->irq_done);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1783
ret = wave5_kfifo_alloc(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1785
dev_err(inst->dev->dev, "failed to allocate fifo\n");
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1789
inst->id = ida_alloc(&inst->dev->inst_ida, GFP_KERNEL);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1790
if (inst->id < 0) {
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1791
dev_warn(inst->dev->dev, "Allocating instance ID, fail: %d\n", inst->id);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1792
ret = inst->id;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1796
wave5_vdi_allocate_sram(inst->dev);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1802
list_add_tail(&inst->list, &dev->instances);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
1809
wave5_cleanup_instance(inst, filp);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
185
dev_dbg(inst->dev->dev, "%s: No source buffer found\n", __func__);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
191
if (inst->src_fmt.num_planes == 1) {
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
196
} else if (inst->src_fmt.num_planes == 2) {
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
202
} else if (inst->src_fmt.num_planes == 3) {
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
216
pic_param.code_option.encode_aud = inst->encode_aud;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
217
ret = wave5_vpu_enc_start_one_frame(inst, &pic_param, fail_res);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
222
dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_start_one_frame fail: %d\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
226
dev_dbg(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
233
dev_dbg(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
238
switch_state(inst, VPU_INST_STATE_STOP);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
243
dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_start_one_frame success\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
250
static void wave5_vpu_enc_finish_encode(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
252
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
258
ret = wave5_vpu_enc_get_output_info(inst, &enc_output_info);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
260
dev_dbg(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
266
dev_dbg(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
274
dev_warn(inst->dev->dev, "%s: no source buffer found\n", __func__);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
276
inst->timestamp = src_buf->vb2_buf.timestamp;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
293
v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_eos);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
295
v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
298
dev_warn(inst->dev->dev, "No bitstream buffer.");
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
299
v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
305
dst_buf->vb2_buf.timestamp = inst->timestamp;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
321
dev_dbg(inst->dev->dev, "%s: frame_cycle %8u\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
324
v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
358
struct vpu_instance *inst = file_to_vpu_inst(file);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
361
dev_dbg(inst->dev->dev, "%s: index: %u\n", __func__, f->index);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
375
struct vpu_instance *inst = file_to_vpu_inst(file);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
380
dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
386
width = inst->dst_fmt.width;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
387
height = inst->dst_fmt.height;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
388
f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
399
f->fmt.pix_mp.colorspace = inst->colorspace;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
400
f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
401
f->fmt.pix_mp.quantization = inst->quantization;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
402
f->fmt.pix_mp.xfer_func = inst->xfer_func;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
409
struct vpu_instance *inst = file_to_vpu_inst(file);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
412
dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
420
inst->std = wave5_to_vpu_std(f->fmt.pix_mp.pixelformat, inst->type);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
421
if (inst->std == STD_UNKNOWN) {
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
422
dev_warn(inst->dev->dev, "unsupported pixelformat: %.4s\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
427
inst->dst_fmt.width = f->fmt.pix_mp.width;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
428
inst->dst_fmt.height = f->fmt.pix_mp.height;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
429
inst->dst_fmt.pixelformat = f->fmt.pix_mp.pixelformat;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
430
inst->dst_fmt.field = f->fmt.pix_mp.field;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
431
inst->dst_fmt.flags = f->fmt.pix_mp.flags;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
432
inst->dst_fmt.num_planes = f->fmt.pix_mp.num_planes;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
433
for (i = 0; i < inst->dst_fmt.num_planes; i++) {
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
434
inst->dst_fmt.plane_fmt[i].bytesperline = f->fmt.pix_mp.plane_fmt[i].bytesperline;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
435
inst->dst_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
443
struct vpu_instance *inst = file_to_vpu_inst(file);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
446
f->fmt.pix_mp.width = inst->dst_fmt.width;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
447
f->fmt.pix_mp.height = inst->dst_fmt.height;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
448
f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
449
f->fmt.pix_mp.field = inst->dst_fmt.field;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
450
f->fmt.pix_mp.flags = inst->dst_fmt.flags;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
451
f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
453
f->fmt.pix_mp.plane_fmt[i].bytesperline = inst->dst_fmt.plane_fmt[i].bytesperline;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
454
f->fmt.pix_mp.plane_fmt[i].sizeimage = inst->dst_fmt.plane_fmt[i].sizeimage;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
457
f->fmt.pix_mp.colorspace = inst->colorspace;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
458
f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
459
f->fmt.pix_mp.quantization = inst->quantization;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
460
f->fmt.pix_mp.xfer_func = inst->xfer_func;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
467
struct vpu_instance *inst = file_to_vpu_inst(file);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
470
dev_dbg(inst->dev->dev, "%s: index: %u\n", __func__, f->index);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
484
struct vpu_instance *inst = file_to_vpu_inst(file);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
489
dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
495
width = inst->src_fmt.width;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
496
height = inst->src_fmt.height;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
497
f->fmt.pix_mp.pixelformat = inst->src_fmt.pixelformat;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
513
struct vpu_instance *inst = file_to_vpu_inst(file);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
518
dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
526
inst->src_fmt.width = f->fmt.pix_mp.width;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
527
inst->src_fmt.height = f->fmt.pix_mp.height;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
528
inst->src_fmt.pixelformat = f->fmt.pix_mp.pixelformat;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
529
inst->src_fmt.field = f->fmt.pix_mp.field;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
530
inst->src_fmt.flags = f->fmt.pix_mp.flags;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
531
inst->src_fmt.num_planes = f->fmt.pix_mp.num_planes;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
532
for (i = 0; i < inst->src_fmt.num_planes; i++) {
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
533
inst->src_fmt.plane_fmt[i].bytesperline = f->fmt.pix_mp.plane_fmt[i].bytesperline;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
534
inst->src_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
537
info = v4l2_format_info(inst->src_fmt.pixelformat);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
541
inst->cbcr_interleave = info->comp_planes == 2;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
543
switch (inst->src_fmt.pixelformat) {
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
548
inst->nv21 = true;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
551
inst->nv21 = false;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
554
inst->colorspace = f->fmt.pix_mp.colorspace;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
555
inst->ycbcr_enc = f->fmt.pix_mp.ycbcr_enc;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
556
inst->quantization = f->fmt.pix_mp.quantization;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
557
inst->xfer_func = f->fmt.pix_mp.xfer_func;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
559
vpu_fmt = wave5_find_vpu_fmt(inst->dst_fmt.pixelformat, enc_fmt_list[VPU_FMT_TYPE_CODEC]);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
563
wave5_update_pix_fmt(&inst->dst_fmt, VPU_FMT_TYPE_CODEC,
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
566
inst->conf_win.width = inst->dst_fmt.width;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
567
inst->conf_win.height = inst->dst_fmt.height;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
574
struct vpu_instance *inst = file_to_vpu_inst(file);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
576
dev_dbg(inst->dev->dev, "%s: type: %u | target: %u\n", __func__, s->type, s->target);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
585
s->r.width = inst->dst_fmt.width;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
586
s->r.height = inst->dst_fmt.height;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
591
s->r.width = inst->conf_win.width;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
592
s->r.height = inst->conf_win.height;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
603
struct vpu_instance *inst = file_to_vpu_inst(file);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
611
dev_dbg(inst->dev->dev, "%s: V4L2_SEL_TGT_CROP width: %u | height: %u\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
616
s->r.width = min(s->r.width, inst->dst_fmt.width);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
617
s->r.height = min(s->r.height, inst->dst_fmt.height);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
619
inst->conf_win = s->r;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
626
struct vpu_instance *inst = file_to_vpu_inst(file);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
627
struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
634
if (!wave5_vpu_both_queues_are_streaming(inst))
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
661
struct vpu_instance *inst = file_to_vpu_inst(file);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
663
dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, a->type);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
670
a->parm.output.timeperframe.denominator = inst->frame_rate;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
672
dev_dbg(inst->dev->dev, "%s: numerator: %u | denominator: %u\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
681
struct vpu_instance *inst = file_to_vpu_inst(file);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
683
dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, a->type);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
690
inst->frame_rate = a->parm.output.timeperframe.denominator /
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
694
a->parm.output.timeperframe.denominator = inst->frame_rate;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
697
dev_dbg(inst->dev->dev, "%s: numerator: %u | denominator: %u\n",
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
743
struct vpu_instance *inst = wave5_ctrl_to_vpu_inst(ctrl);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
745
dev_dbg(inst->dev->dev, "%s: name: %s | value: %d\n", __func__, ctrl->name, ctrl->val);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
749
inst->encode_aud = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
752
inst->mirror_direction |= (ctrl->val << 1);
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
755
inst->mirror_direction |= ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
758
inst->rot_angle = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
761
inst->vbv_buf_size = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
766
inst->rc_mode = 0;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
769
inst->rc_mode = 1;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
776
inst->bit_rate = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
779
inst->enc_param.bg_detection = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
782
inst->enc_param.avc_idr_period = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
785
inst->enc_param.independ_slice_mode = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
786
inst->enc_param.avc_slice_mode = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
789
inst->enc_param.independ_slice_mode_arg = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
790
inst->enc_param.avc_slice_arg = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
793
inst->rc_enable = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
796
inst->enc_param.mb_level_rc_enable = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
797
inst->enc_param.cu_level_rc_enable = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
798
inst->enc_param.hvs_qp_enable = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
803
inst->enc_param.profile = HEVC_PROFILE_MAIN;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
804
inst->bit_depth = 8;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
807
inst->enc_param.profile = HEVC_PROFILE_STILLPICTURE;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
808
inst->enc_param.en_still_picture = 1;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
809
inst->bit_depth = 8;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
812
inst->enc_param.profile = HEVC_PROFILE_MAIN10;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
813
inst->bit_depth = 10;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
822
inst->enc_param.level = 10 * 3;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
825
inst->enc_param.level = 20 * 3;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
828
inst->enc_param.level = 21 * 3;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
831
inst->enc_param.level = 30 * 3;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
834
inst->enc_param.level = 31 * 3;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
837
inst->enc_param.level = 40 * 3;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
840
inst->enc_param.level = 41 * 3;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
843
inst->enc_param.level = 50 * 3;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
846
inst->enc_param.level = 51 * 3;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
849
inst->enc_param.level = 52 * 3;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
856
inst->enc_param.min_qp_i = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
857
inst->enc_param.min_qp_p = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
858
inst->enc_param.min_qp_b = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
861
inst->enc_param.max_qp_i = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
862
inst->enc_param.max_qp_p = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
863
inst->enc_param.max_qp_b = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
866
inst->enc_param.intra_qp = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
871
inst->enc_param.disable_deblk = 1;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
872
inst->enc_param.sao_enable = 0;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
873
inst->enc_param.lf_cross_slice_boundary_enable = 0;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
876
inst->enc_param.disable_deblk = 0;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
877
inst->enc_param.sao_enable = 1;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
878
inst->enc_param.lf_cross_slice_boundary_enable = 1;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
881
inst->enc_param.disable_deblk = 0;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
882
inst->enc_param.sao_enable = 1;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
883
inst->enc_param.lf_cross_slice_boundary_enable = 0;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
890
inst->enc_param.beta_offset_div2 = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
893
inst->enc_param.tc_offset_div2 = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
898
inst->enc_param.decoding_refresh_type = 0;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
901
inst->enc_param.decoding_refresh_type = 1;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
904
inst->enc_param.decoding_refresh_type = 2;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
911
inst->enc_param.intra_period = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
914
inst->enc_param.lossless_enable = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
917
inst->enc_param.const_intra_pred_flag = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
920
inst->enc_param.wpp_enable = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
923
inst->enc_param.strong_intra_smooth_enable = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
926
inst->enc_param.max_num_merge = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
929
inst->enc_param.tmvp_enable = ctrl->val;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
935
inst->enc_param.profile = H264_PROFILE_BP;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
936
inst->bit_depth = 8;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
938
inst->enc_param.constraint_set1_flag = 1;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
941
inst->enc_param.profile = H264_PROFILE_MP;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
942
inst->bit_depth = 8;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
945
inst->enc_param.profile = H264_PROFILE_EXTENDED;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
946
inst->bit_depth = 8;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
949
inst->enc_param.profile = H264_PROFILE_HP;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
950
inst->bit_depth = 8;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
953
inst->enc_param.profile = H264_PROFILE_HIGH10;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
954
inst->bit_depth = 10;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
957
inst->enc_param.profile = H264_PROFILE_HIGH422;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
958
inst->bit_depth = 10;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
961
inst->enc_param.profile = H264_PROFILE_HIGH444;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
962
inst->bit_depth = 10;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
971
inst->enc_param.level = 10;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
974
inst->enc_param.level = 9;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
977
inst->enc_param.level = 11;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
980
inst->enc_param.level = 12;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
983
inst->enc_param.level = 13;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
986
inst->enc_param.level = 20;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
989
inst->enc_param.level = 21;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
992
inst->enc_param.level = 22;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
995
inst->enc_param.level = 30;
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
998
inst->enc_param.level = 31;
drivers/media/platform/chips-media/wave5/wave5-vpu.c
123
struct vpu_instance *inst, *tmp;
drivers/media/platform/chips-media/wave5/wave5-vpu.c
127
list_for_each_entry_safe(inst, tmp, &dev->instances, list) {
drivers/media/platform/chips-media/wave5/wave5-vpu.c
128
while (kfifo_len(&inst->irq_status)) {
drivers/media/platform/chips-media/wave5/wave5-vpu.c
129
ret = kfifo_out(&inst->irq_status, &irq_status, sizeof(int));
drivers/media/platform/chips-media/wave5/wave5-vpu.c
133
inst->ops->finish_process(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu.c
163
struct vpu_instance *inst, *tmp;
drivers/media/platform/chips-media/wave5/wave5-vpu.c
174
list_for_each_entry_safe(inst, tmp, &dev->instances, list) {
drivers/media/platform/chips-media/wave5/wave5-vpu.c
175
while (kfifo_len(&inst->irq_status)) {
drivers/media/platform/chips-media/wave5/wave5-vpu.c
176
ret = kfifo_out(&inst->irq_status, &irq_status, sizeof(int));
drivers/media/platform/chips-media/wave5/wave5-vpu.c
180
inst->ops->finish_process(inst);
drivers/media/platform/chips-media/wave5/wave5-vpu.c
35
int wave5_vpu_wait_interrupt(struct vpu_instance *inst, unsigned int timeout)
drivers/media/platform/chips-media/wave5/wave5-vpu.c
39
ret = wait_for_completion_timeout(&inst->irq_done,
drivers/media/platform/chips-media/wave5/wave5-vpu.c
44
reinit_completion(&inst->irq_done);
drivers/media/platform/chips-media/wave5/wave5-vpu.c
55
struct vpu_instance *inst, *tmp;
drivers/media/platform/chips-media/wave5/wave5-vpu.c
67
list_for_each_entry_safe(inst, tmp, &dev->instances, list) {
drivers/media/platform/chips-media/wave5/wave5-vpu.c
72
(cmd_done & BIT(inst->id))) {
drivers/media/platform/chips-media/wave5/wave5-vpu.c
73
cmd_done &= ~BIT(inst->id);
drivers/media/platform/chips-media/wave5/wave5-vpu.c
76
complete(&inst->irq_done);
drivers/media/platform/chips-media/wave5/wave5-vpu.c
77
} else if (seq_done & BIT(inst->id)) {
drivers/media/platform/chips-media/wave5/wave5-vpu.c
78
seq_done &= ~BIT(inst->id);
drivers/media/platform/chips-media/wave5/wave5-vpu.c
81
complete(&inst->irq_done);
drivers/media/platform/chips-media/wave5/wave5-vpu.c
87
if (cmd_done & BIT(inst->id)) {
drivers/media/platform/chips-media/wave5/wave5-vpu.c
88
cmd_done &= ~BIT(inst->id);
drivers/media/platform/chips-media/wave5/wave5-vpu.c
98
kfifo_in(&inst->irq_status, &val, sizeof(int));
drivers/media/platform/chips-media/wave5/wave5-vpu.h
69
int wave5_vpu_wait_interrupt(struct vpu_instance *inst, unsigned int timeout);
drivers/media/platform/chips-media/wave5/wave5-vpu.h
75
static inline bool wave5_vpu_both_queues_are_streaming(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-vpu.h
78
v4l2_m2m_get_vq(inst->v4l2_fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
drivers/media/platform/chips-media/wave5/wave5-vpu.h
80
v4l2_m2m_get_vq(inst->v4l2_fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
1001
ret = wave5_vpu_enc_get_seq_info(inst, info);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
124
static int wave5_check_dec_open_param(struct vpu_instance *inst, struct dec_open_param *param)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
126
if (inst->id >= MAX_NUM_INSTANCE) {
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
127
dev_err(inst->dev->dev, "Too many simultaneous instances: %d (max: %u)\n",
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
128
inst->id, MAX_NUM_INSTANCE);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
133
dev_err(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
140
dev_err(inst->dev->dev,
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
149
int wave5_vpu_dec_open(struct vpu_instance *inst, struct dec_open_param *open_param)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
153
struct vpu_device *vpu_dev = inst->dev;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
157
ret = wave5_check_dec_open_param(inst, open_param);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
170
p_dec_info = &inst->codec_info->dec_info;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
185
ret = wave5_vpu_build_up_dec_param(inst, open_param);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
191
static int reset_auxiliary_buffers(struct vpu_instance *inst, unsigned int index)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
193
struct dec_info *p_dec_info = &inst->codec_info->dec_info;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
202
wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_mv[index]);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
203
wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_fbc_y_tbl[index]);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
204
wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_fbc_c_tbl[index]);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
209
int wave5_vpu_dec_close(struct vpu_instance *inst, u32 *fail_res)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
211
struct dec_info *p_dec_info = &inst->codec_info->dec_info;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
214
struct vpu_device *vpu_dev = inst->dev;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
220
if (!inst->codec_info)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
223
pm_runtime_resume_and_get(inst->dev->dev);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
227
pm_runtime_put_sync(inst->dev->dev);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
232
ret = wave5_vpu_dec_finish_seq(inst, fail_res);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
234
dev_warn(inst->dev->dev, "dec_finish_seq timed out\n");
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
242
dev_warn(inst->dev->dev, "dec_finish_seq timed out\n");
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
252
wave5_vpu_dec_get_output_info(inst, &dec_info);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
255
pm_runtime_put_sync(inst->dev->dev);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
260
dev_dbg(inst->dev->dev, "%s: dec_finish_seq complete\n", __func__);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
265
ret = reset_auxiliary_buffers(inst, i);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
274
mutex_destroy(&inst->feed_lock);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
278
pm_runtime_put_sync(inst->dev->dev);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
282
int wave5_vpu_dec_issue_seq_init(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
285
struct vpu_device *vpu_dev = inst->dev;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
291
ret = wave5_vpu_dec_init_seq(inst);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
298
int wave5_vpu_dec_complete_seq_init(struct vpu_instance *inst, struct dec_initial_info *info)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
300
struct dec_info *p_dec_info = &inst->codec_info->dec_info;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
302
struct vpu_device *vpu_dev = inst->dev;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
308
ret = wave5_vpu_dec_get_seq_info(inst, info);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
312
info->rd_ptr = wave5_dec_get_rd_ptr(inst);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
322
int wave5_vpu_dec_register_frame_buffer_ex(struct vpu_instance *inst, int num_of_decoding_fbs,
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
327
struct vpu_device *vpu_dev = inst->dev;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
333
p_dec_info = &inst->codec_info->dec_info;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
349
fb = inst->frame_buf;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
350
ret = wave5_vpu_dec_register_framebuffer(inst, &fb[p_dec_info->num_of_decoding_fbs],
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
355
ret = wave5_vpu_dec_register_framebuffer(inst, &fb[0], COMPRESSED_FRAME_MAP,
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
364
int wave5_vpu_dec_get_bitstream_buffer(struct vpu_instance *inst, dma_addr_t *prd_ptr,
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
371
struct vpu_device *vpu_dev = inst->dev;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
374
p_dec_info = &inst->codec_info->dec_info;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
379
rd_ptr = wave5_dec_get_rd_ptr(inst);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
401
int wave5_vpu_dec_update_bitstream_buffer(struct vpu_instance *inst, size_t size)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
407
struct vpu_device *vpu_dev = inst->dev;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
409
if (!inst->codec_info)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
412
p_dec_info = &inst->codec_info->dec_info;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
438
ret = wave5_vpu_dec_set_bitstream_flag(inst, (size == 0));
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
444
int wave5_vpu_dec_start_one_frame(struct vpu_instance *inst, u32 *res_fail)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
446
struct dec_info *p_dec_info = &inst->codec_info->dec_info;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
448
struct vpu_device *vpu_dev = inst->dev;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
457
ret = wave5_vpu_decode(inst, res_fail);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
464
int wave5_vpu_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr, int update_wr_ptr)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
466
struct dec_info *p_dec_info = &inst->codec_info->dec_info;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
468
struct vpu_device *vpu_dev = inst->dev;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
474
ret = wave5_dec_set_rd_ptr(inst, addr);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
485
dma_addr_t wave5_vpu_dec_get_rd_ptr(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
490
ret = mutex_lock_interruptible(&inst->dev->hw_lock);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
494
rd_ptr = wave5_dec_get_rd_ptr(inst);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
496
mutex_unlock(&inst->dev->hw_lock);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
501
int wave5_vpu_dec_get_output_info(struct vpu_instance *inst, struct dec_output_info *info)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
510
struct vpu_device *vpu_dev = inst->dev;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
516
p_dec_info = &inst->codec_info->dec_info;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
52
int wave5_vpu_flush_instance(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
524
ret = wave5_vpu_dec_get_result(inst, info);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
541
if (inst->std == W_HEVC_DEC || inst->std == W_AVC_DEC)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
544
if (inst->std == W_HEVC_DEC)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
578
p_dec_info->stream_rd_ptr = wave5_dec_get_rd_ptr(inst);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
58
mutex_ret = mutex_lock_interruptible(&inst->dev->hw_lock);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
594
info->disp_frame = inst->frame_buf[idx];
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
620
int wave5_vpu_dec_clr_disp_flag(struct vpu_instance *inst, int index)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
622
struct dec_info *p_dec_info = &inst->codec_info->dec_info;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
624
struct vpu_device *vpu_dev = inst->dev;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
632
ret = wave5_dec_clr_disp_flag(inst, index);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
638
int wave5_vpu_dec_set_disp_flag(struct vpu_instance *inst, int index)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
640
struct dec_info *p_dec_info = &inst->codec_info->dec_info;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
642
struct vpu_device *vpu_dev = inst->dev;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
650
ret = wave5_dec_set_disp_flag(inst, index);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
656
int wave5_vpu_dec_reset_framebuffer(struct vpu_instance *inst, unsigned int index)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
66
ret = wave5_vpu_hw_flush_instance(inst);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
661
if (inst->frame_vbuf[index].size == 0)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
664
wave5_vdi_free_dma_memory(inst->dev, &inst->frame_vbuf[index]);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
669
int wave5_vpu_dec_give_command(struct vpu_instance *inst, enum codec_command cmd, void *parameter)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
671
struct dec_info *p_dec_info = &inst->codec_info->dec_info;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
68
dev_warn(inst->dev->dev, "Flush of %s instance with id: %d fail: %d\n",
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
686
ret = wave5_vpu_dec_reset_framebuffer(inst, i);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
69
inst->type == VPU_INST_TYPE_DEC ? "DECODER" : "ENCODER", inst->id,
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
692
ret = reset_auxiliary_buffers(inst, i);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
697
wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_task);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
71
mutex_unlock(&inst->dev->hw_lock);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
714
int wave5_vpu_enc_open(struct vpu_instance *inst, struct enc_open_param *open_param)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
718
struct vpu_device *vpu_dev = inst->dev;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
720
ret = wave5_vpu_enc_check_open_param(inst, open_param);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
733
p_enc_info = &inst->codec_info->enc_info;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
736
ret = wave5_vpu_build_up_enc_param(vpu_dev->dev, inst, open_param);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
742
int wave5_vpu_enc_close(struct vpu_instance *inst, u32 *fail_res)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
744
struct enc_info *p_enc_info = &inst->codec_info->enc_info;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
747
struct vpu_device *vpu_dev = inst->dev;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
75
dev_warn(inst->dev->dev, "Flush of %s instance with id: %d timed out!\n",
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
750
if (!inst->codec_info)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
753
pm_runtime_resume_and_get(inst->dev->dev);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
757
pm_runtime_resume_and_get(inst->dev->dev);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
76
inst->type == VPU_INST_TYPE_DEC ? "DECODER" : "ENCODER", inst->id);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
762
ret = wave5_vpu_enc_finish_seq(inst, fail_res);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
764
dev_warn(inst->dev->dev, "enc_finish_seq timed out\n");
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
765
pm_runtime_resume_and_get(inst->dev->dev);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
77
mutex_unlock(&inst->dev->hw_lock);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
772
pm_runtime_resume_and_get(inst->dev->dev);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
778
dev_dbg(inst->dev->dev, "%s: enc_finish_seq complete\n", __func__);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
782
if (inst->std == W_HEVC_ENC || inst->std == W_AVC_ENC) {
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
791
pm_runtime_put_sync(inst->dev->dev);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
796
int wave5_vpu_enc_register_frame_buffer(struct vpu_instance *inst, unsigned int num,
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
800
struct enc_info *p_enc_info = &inst->codec_info->enc_info;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
802
struct vpu_device *vpu_dev = inst->dev;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
82
mutex_unlock(&inst->dev->hw_lock);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
83
wave5_vpu_dec_get_output_info(inst, &dec_info);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
832
if (!inst->frame_buf[i].update_fb_info)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
835
inst->frame_buf[i].update_fb_info = false;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
836
inst->frame_buf[i].stride = stride;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
837
inst->frame_buf[i].height = height;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
838
inst->frame_buf[i].map_type = COMPRESSED_FRAME_MAP;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
839
inst->frame_buf[i].buf_y_size = size_luma;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
84
mutex_ret = mutex_lock_interruptible(&inst->dev->hw_lock);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
840
inst->frame_buf[i].buf_cb = inst->frame_buf[i].buf_y + size_luma;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
841
inst->frame_buf[i].buf_cb_size = size_chroma;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
842
inst->frame_buf[i].buf_cr_size = 0;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
845
ret = wave5_vpu_enc_register_framebuffer(inst->dev->dev, inst, &inst->frame_buf[0],
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
854
static int wave5_check_enc_param(struct vpu_instance *inst, struct enc_param *param)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
856
struct enc_info *p_enc_info = &inst->codec_info->enc_info;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
864
if (p_enc_info->open_param.bit_rate == 0 && inst->std == W_HEVC_ENC) {
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
874
int wave5_vpu_enc_start_one_frame(struct vpu_instance *inst, struct enc_param *param, u32 *fail_res)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
876
struct enc_info *p_enc_info = &inst->codec_info->enc_info;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
878
struct vpu_device *vpu_dev = inst->dev;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
88
mutex_unlock(&inst->dev->hw_lock);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
885
ret = wave5_check_enc_param(inst, param);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
89
wave5_vpu_dec_set_disp_flag(inst, dec_info.index_frame_display);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
895
ret = wave5_vpu_encode(inst, param, fail_res);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
90
mutex_ret = mutex_lock_interruptible(&inst->dev->hw_lock);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
902
int wave5_vpu_enc_get_output_info(struct vpu_instance *inst, struct enc_output_info *info)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
904
struct enc_info *p_enc_info = &inst->codec_info->enc_info;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
906
struct vpu_device *vpu_dev = inst->dev;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
912
ret = wave5_vpu_enc_get_result(inst, info);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
927
int wave5_vpu_enc_give_command(struct vpu_instance *inst, enum codec_command cmd, void *parameter)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
929
struct enc_info *p_enc_info = &inst->codec_info->enc_info;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
96
mutex_unlock(&inst->dev->hw_lock);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
972
int wave5_vpu_enc_issue_seq_init(struct vpu_instance *inst)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
975
struct vpu_device *vpu_dev = inst->dev;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
981
ret = wave5_vpu_enc_init_seq(inst);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
988
int wave5_vpu_enc_complete_seq_init(struct vpu_instance *inst, struct enc_initial_info *info)
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
990
struct enc_info *p_enc_info = &inst->codec_info->enc_info;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
992
struct vpu_device *vpu_dev = inst->dev;
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
780
void (*finish_process)(struct vpu_instance *inst);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
860
int wave5_vpu_flush_instance(struct vpu_instance *inst);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
862
int wave5_vpu_dec_open(struct vpu_instance *inst, struct dec_open_param *open_param);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
863
int wave5_vpu_dec_close(struct vpu_instance *inst, u32 *fail_res);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
864
int wave5_vpu_dec_issue_seq_init(struct vpu_instance *inst);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
865
int wave5_vpu_dec_complete_seq_init(struct vpu_instance *inst, struct dec_initial_info *info);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
866
int wave5_vpu_dec_register_frame_buffer_ex(struct vpu_instance *inst, int num_of_decoding_fbs,
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
868
int wave5_vpu_dec_start_one_frame(struct vpu_instance *inst, u32 *res_fail);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
869
int wave5_vpu_dec_get_output_info(struct vpu_instance *inst, struct dec_output_info *info);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
870
int wave5_vpu_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr, int update_wr_ptr);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
871
dma_addr_t wave5_vpu_dec_get_rd_ptr(struct vpu_instance *inst);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
872
int wave5_vpu_dec_reset_framebuffer(struct vpu_instance *inst, unsigned int index);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
873
int wave5_vpu_dec_give_command(struct vpu_instance *inst, enum codec_command cmd, void *parameter);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
874
int wave5_vpu_dec_get_bitstream_buffer(struct vpu_instance *inst, dma_addr_t *prd_ptr,
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
876
int wave5_vpu_dec_update_bitstream_buffer(struct vpu_instance *inst, size_t size);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
877
int wave5_vpu_dec_clr_disp_flag(struct vpu_instance *inst, int index);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
878
int wave5_vpu_dec_set_disp_flag(struct vpu_instance *inst, int index);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
880
int wave5_vpu_enc_open(struct vpu_instance *inst, struct enc_open_param *open_param);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
881
int wave5_vpu_enc_close(struct vpu_instance *inst, u32 *fail_res);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
882
int wave5_vpu_enc_issue_seq_init(struct vpu_instance *inst);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
883
int wave5_vpu_enc_complete_seq_init(struct vpu_instance *inst, struct enc_initial_info *info);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
884
int wave5_vpu_enc_register_frame_buffer(struct vpu_instance *inst, unsigned int num,
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
887
int wave5_vpu_enc_start_one_frame(struct vpu_instance *inst, struct enc_param *param,
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
889
int wave5_vpu_enc_get_output_info(struct vpu_instance *inst, struct enc_output_info *info);
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
890
int wave5_vpu_enc_give_command(struct vpu_instance *inst, enum codec_command cmd, void *parameter);
drivers/media/platform/chips-media/wave5/wave5.h
100
int wave5_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr);
drivers/media/platform/chips-media/wave5/wave5.h
104
int wave5_vpu_build_up_enc_param(struct device *dev, struct vpu_instance *inst,
drivers/media/platform/chips-media/wave5/wave5.h
107
int wave5_vpu_enc_init_seq(struct vpu_instance *inst);
drivers/media/platform/chips-media/wave5/wave5.h
109
int wave5_vpu_enc_get_seq_info(struct vpu_instance *inst, struct enc_initial_info *info);
drivers/media/platform/chips-media/wave5/wave5.h
111
int wave5_vpu_enc_register_framebuffer(struct device *dev, struct vpu_instance *inst,
drivers/media/platform/chips-media/wave5/wave5.h
115
int wave5_vpu_encode(struct vpu_instance *inst, struct enc_param *option, u32 *fail_res);
drivers/media/platform/chips-media/wave5/wave5.h
117
int wave5_vpu_enc_get_result(struct vpu_instance *inst, struct enc_output_info *result);
drivers/media/platform/chips-media/wave5/wave5.h
119
int wave5_vpu_enc_finish_seq(struct vpu_instance *inst, u32 *fail_res);
drivers/media/platform/chips-media/wave5/wave5.h
121
int wave5_vpu_enc_check_open_param(struct vpu_instance *inst, struct enc_open_param *open_param);
drivers/media/platform/chips-media/wave5/wave5.h
70
int wave5_vpu_build_up_dec_param(struct vpu_instance *inst, struct dec_open_param *param);
drivers/media/platform/chips-media/wave5/wave5.h
72
int wave5_vpu_dec_set_bitstream_flag(struct vpu_instance *inst, bool eos);
drivers/media/platform/chips-media/wave5/wave5.h
74
int wave5_vpu_hw_flush_instance(struct vpu_instance *inst);
drivers/media/platform/chips-media/wave5/wave5.h
76
int wave5_vpu_dec_register_framebuffer(struct vpu_instance *inst,
drivers/media/platform/chips-media/wave5/wave5.h
82
int wave5_vpu_dec_init_seq(struct vpu_instance *inst);
drivers/media/platform/chips-media/wave5/wave5.h
84
int wave5_vpu_dec_get_seq_info(struct vpu_instance *inst, struct dec_initial_info *info);
drivers/media/platform/chips-media/wave5/wave5.h
86
int wave5_vpu_decode(struct vpu_instance *inst, u32 *fail_res);
drivers/media/platform/chips-media/wave5/wave5.h
88
int wave5_vpu_dec_get_result(struct vpu_instance *inst, struct dec_output_info *result);
drivers/media/platform/chips-media/wave5/wave5.h
90
int wave5_vpu_dec_finish_seq(struct vpu_instance *inst, u32 *fail_res);
drivers/media/platform/chips-media/wave5/wave5.h
92
int wave5_dec_clr_disp_flag(struct vpu_instance *inst, unsigned int index);
drivers/media/platform/chips-media/wave5/wave5.h
94
int wave5_dec_set_disp_flag(struct vpu_instance *inst, unsigned int index);
drivers/media/platform/chips-media/wave5/wave5.h
96
int wave5_vpu_clear_interrupt(struct vpu_instance *inst, u32 flags);
drivers/media/platform/chips-media/wave5/wave5.h
98
dma_addr_t wave5_dec_get_rd_ptr(struct vpu_instance *inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
139
static int allocate_prediction_buf(struct vdec_h264_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
143
inst->pred_buf.size = BUF_PREDICTION_SZ;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
144
err = mtk_vcodec_mem_alloc(inst->ctx, &inst->pred_buf);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
146
mtk_vdec_err(inst->ctx, "failed to allocate ppl buf");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
150
inst->vsi->pred_buf_dma = inst->pred_buf.dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
154
static void free_prediction_buf(struct vdec_h264_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
158
inst->vsi->pred_buf_dma = 0;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
159
mem = &inst->pred_buf;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
161
mtk_vcodec_mem_free(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
164
static int alloc_mv_buf(struct vdec_h264_inst *inst, struct vdec_pic_info *pic)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
172
mem = &inst->mv_buf[i];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
174
mtk_vcodec_mem_free(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
176
err = mtk_vcodec_mem_alloc(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
178
mtk_vdec_err(inst->ctx, "failed to allocate mv buf");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
181
inst->vsi->mv_buf_dma[i] = mem->dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
187
static void free_mv_buf(struct vdec_h264_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
193
inst->vsi->mv_buf_dma[i] = 0;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
194
mem = &inst->mv_buf[i];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
196
mtk_vcodec_mem_free(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
200
static int check_list_validity(struct vdec_h264_inst *inst, bool disp_list)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
204
list = disp_list ? &inst->vsi->list_disp : &inst->vsi->list_free;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
209
mtk_vdec_err(inst->ctx, "%s list err: cnt=%d r_idx=%d w_idx=%d",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
218
static void put_fb_to_free(struct vdec_h264_inst *inst, struct vdec_fb *fb)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
223
if (check_list_validity(inst, false))
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
226
list = &inst->vsi->list_free;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
228
mtk_vdec_err(inst->ctx, "[FB] put fb free_list full");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
232
mtk_vdec_debug(inst->ctx, "[FB] put fb into free_list @(%p, %llx)",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
242
static void get_pic_info(struct vdec_h264_inst *inst,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
245
*pic = inst->vsi->pic;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
246
mtk_vdec_debug(inst->ctx, "pic(%d, %d), buf(%d, %d)",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
248
mtk_vdec_debug(inst->ctx, "fb size: Y(%d), C(%d)", pic->fb_sz[0], pic->fb_sz[1]);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
251
static void get_crop_info(struct vdec_h264_inst *inst, struct v4l2_rect *cr)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
253
cr->left = inst->vsi->crop.left;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
254
cr->top = inst->vsi->crop.top;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
255
cr->width = inst->vsi->crop.width;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
256
cr->height = inst->vsi->crop.height;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
258
mtk_vdec_debug(inst->ctx, "l=%d, t=%d, w=%d, h=%d", cr->left, cr->top,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
262
static void get_dpb_size(struct vdec_h264_inst *inst, unsigned int *dpb_sz)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
264
*dpb_sz = inst->vsi->dec.dpb_sz;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
265
mtk_vdec_debug(inst->ctx, "sz=%d", *dpb_sz);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
270
struct vdec_h264_inst *inst = NULL;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
273
inst = kzalloc_obj(*inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
274
if (!inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
277
inst->ctx = ctx;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
279
inst->vpu.id = IPI_VDEC_H264;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
280
inst->vpu.ctx = ctx;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
282
err = vpu_dec_init(&inst->vpu);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
288
inst->vsi = (struct vdec_h264_vsi *)inst->vpu.vsi;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
289
err = allocate_prediction_buf(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
293
mtk_vdec_debug(ctx, "H264 Instance >> %p", inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
295
ctx->drv_handle = inst;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
299
vpu_dec_deinit(&inst->vpu);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
302
kfree(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
308
struct vdec_h264_inst *inst = (struct vdec_h264_inst *)h_vdec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
310
vpu_dec_deinit(&inst->vpu);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
311
free_prediction_buf(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
312
free_mv_buf(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
314
kfree(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
332
struct vdec_h264_inst *inst = (struct vdec_h264_inst *)h_vdec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
333
struct vdec_vpu_inst *vpu = &inst->vpu;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
345
mtk_vdec_debug(inst->ctx, "+ [%d] FB y_dma=%llx c_dma=%llx va=%p",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
346
++inst->num_nalu, y_fb_dma, c_fb_dma, fb);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
356
mtk_vdec_err(inst->ctx, "invalid nal start code");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
363
mtk_vdec_debug(inst->ctx, "\n + NALU[%d] type %d +\n", inst->num_nalu,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
372
memcpy(inst->vsi->hdr_buf, buf + nal_start_idx, buf_sz);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
375
inst->vsi->dec.bs_dma = (uint64_t)bs->dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
376
inst->vsi->dec.y_fb_dma = y_fb_dma;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
377
inst->vsi->dec.c_fb_dma = c_fb_dma;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
378
inst->vsi->dec.vdec_fb_va = vdec_fb_va;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
385
mtk_vdec_err(inst->ctx, "- error bitstream - err = %d -", err);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
391
*res_chg = inst->vsi->dec.resolution_changed;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
395
mtk_vdec_debug(inst->ctx, "- resolution changed -");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
396
get_pic_info(inst, &pic);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
398
if (inst->vsi->dec.realloc_mv_buf) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
399
err = alloc_mv_buf(inst, &pic);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
407
err = mtk_vcodec_wait_for_done_ctx(inst->ctx,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
416
mtk_vdec_debug(inst->ctx, "\n - NALU[%d] type=%d -\n", inst->num_nalu, nal_type);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
420
put_fb_to_free(inst, fb);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
421
mtk_vdec_err(inst->ctx, "\n - NALU[%d] err=%d -\n", inst->num_nalu, err);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
425
static void vdec_h264_get_fb(struct vdec_h264_inst *inst,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
431
if (check_list_validity(inst, disp_list))
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
435
mtk_vdec_debug(inst->ctx, "[FB] there is no %s fb", disp_list ? "disp" : "free");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
445
mtk_vdec_debug(inst->ctx, "[FB] get %s fb st=%d poc=%d %llx",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
458
struct vdec_h264_inst *inst = (struct vdec_h264_inst *)h_vdec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
462
vdec_h264_get_fb(inst, &inst->vsi->list_disp, true, out);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
466
vdec_h264_get_fb(inst, &inst->vsi->list_free, false, out);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
470
get_pic_info(inst, out);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
474
get_dpb_size(inst, out);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
478
get_crop_info(inst, out);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_if.c
482
mtk_vdec_err(inst->ctx, "invalid get parameter type=%d", type);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
102
struct mtk_h264_dec_slice_param *slice_param = &inst->h264_slice_param;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
112
mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_DECODE_PARAMS);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
116
sps = mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_SPS);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
120
pps = mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_PPS);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
125
mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_SCALING_MATRIX);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
129
mtk_vdec_h264_update_dpb(dec_params, inst->dpb);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
135
dec_params, inst->dpb);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
136
mtk_vdec_h264_fill_dpb_info(inst->ctx, &slice_param->decode_params,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
141
inst->dpb);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
151
memcpy(&inst->vsi_ctx.h264_slice_params, slice_param,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
152
sizeof(inst->vsi_ctx.h264_slice_params));
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
157
static int allocate_prediction_buf(struct vdec_h264_slice_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
161
inst->pred_buf.size = BUF_PREDICTION_SZ;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
162
err = mtk_vcodec_mem_alloc(inst->ctx, &inst->pred_buf);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
164
mtk_vdec_err(inst->ctx, "failed to allocate ppl buf");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
168
inst->vsi_ctx.pred_buf_dma = inst->pred_buf.dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
172
static void free_prediction_buf(struct vdec_h264_slice_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
174
struct mtk_vcodec_mem *mem = &inst->pred_buf;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
176
inst->vsi_ctx.pred_buf_dma = 0;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
178
mtk_vcodec_mem_free(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
181
static int alloc_mv_buf(struct vdec_h264_slice_inst *inst,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
189
mtk_v4l2_vdec_dbg(3, inst->ctx, "size = 0x%x", buf_sz);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
191
mem = &inst->mv_buf[i];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
193
mtk_vcodec_mem_free(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
195
err = mtk_vcodec_mem_alloc(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
197
mtk_vdec_err(inst->ctx, "failed to allocate mv buf");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
200
inst->vsi_ctx.mv_buf_dma[i] = mem->dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
206
static void free_mv_buf(struct vdec_h264_slice_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
212
inst->vsi_ctx.mv_buf_dma[i] = 0;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
213
mem = &inst->mv_buf[i];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
215
mtk_vcodec_mem_free(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
219
static void get_pic_info(struct vdec_h264_slice_inst *inst,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
222
struct mtk_vcodec_dec_ctx *ctx = inst->ctx;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
228
inst->vsi_ctx.dec.cap_num_planes =
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
232
mtk_vdec_debug(inst->ctx, "pic(%d, %d), buf(%d, %d)",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
235
mtk_vdec_debug(inst->ctx, "Y/C(%d, %d)", ctx->picinfo.fb_sz[0],
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
240
inst->vsi_ctx.dec.resolution_changed = true;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
243
inst->vsi_ctx.dec.realloc_mv_buf = true;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
245
mtk_v4l2_vdec_dbg(1, inst->ctx, "ResChg: (%d %d) : old(%d, %d) -> new(%d, %d)",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
246
inst->vsi_ctx.dec.resolution_changed,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
247
inst->vsi_ctx.dec.realloc_mv_buf,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
254
static void get_crop_info(struct vdec_h264_slice_inst *inst, struct v4l2_rect *cr)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
256
cr->left = inst->vsi_ctx.crop.left;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
257
cr->top = inst->vsi_ctx.crop.top;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
258
cr->width = inst->vsi_ctx.crop.width;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
259
cr->height = inst->vsi_ctx.crop.height;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
261
mtk_vdec_debug(inst->ctx, "l=%d, t=%d, w=%d, h=%d",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
265
static void get_dpb_size(struct vdec_h264_slice_inst *inst, unsigned int *dpb_sz)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
267
*dpb_sz = inst->vsi_ctx.dec.dpb_sz;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
268
mtk_vdec_debug(inst->ctx, "sz=%d", *dpb_sz);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
273
struct vdec_h264_slice_inst *inst;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
276
inst = kzalloc_obj(*inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
277
if (!inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
280
inst->ctx = ctx;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
282
inst->vpu.id = SCP_IPI_VDEC_H264;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
283
inst->vpu.ctx = ctx;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
285
err = vpu_dec_init(&inst->vpu);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
291
memcpy(&inst->vsi_ctx, inst->vpu.vsi, sizeof(inst->vsi_ctx));
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
292
inst->vsi_ctx.dec.resolution_changed = true;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
293
inst->vsi_ctx.dec.realloc_mv_buf = true;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
295
err = allocate_prediction_buf(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
305
mtk_vdec_debug(ctx, "H264 Instance >> %p", inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
307
ctx->drv_handle = inst;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
311
vpu_dec_deinit(&inst->vpu);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
314
kfree(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
320
struct vdec_h264_slice_inst *inst = h_vdec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
322
vpu_dec_deinit(&inst->vpu);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
323
free_prediction_buf(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
324
free_mv_buf(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
326
kfree(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
332
struct vdec_h264_slice_inst *inst = h_vdec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
334
mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_DECODE_PARAMS);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
335
struct vdec_vpu_inst *vpu = &inst->vpu;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
344
inst->num_nalu++;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
349
fb = inst->ctx->dev->vdec_pdata->get_cap_buffer(inst->ctx);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
351
mtk_vdec_err(inst->ctx, "fb buffer is NULL");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
361
mtk_vdec_debug(inst->ctx, "+ [%d] FB y_dma=%llx c_dma=%llx va=%p",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
362
inst->num_nalu, y_fb_dma, c_fb_dma, fb);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
364
inst->vsi_ctx.dec.bs_dma = (uint64_t)bs->dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
365
inst->vsi_ctx.dec.y_fb_dma = y_fb_dma;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
366
inst->vsi_ctx.dec.c_fb_dma = c_fb_dma;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
367
inst->vsi_ctx.dec.vdec_fb_va = (u64)(uintptr_t)fb;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
371
err = get_vdec_decode_parameters(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
385
*res_chg = inst->vsi_ctx.dec.resolution_changed;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
387
mtk_vdec_debug(inst->ctx, "- resolution changed -");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
388
if (inst->vsi_ctx.dec.realloc_mv_buf) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
389
err = alloc_mv_buf(inst, &inst->ctx->picinfo);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
390
inst->vsi_ctx.dec.realloc_mv_buf = false;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
397
memcpy(inst->vpu.vsi, &inst->vsi_ctx, sizeof(inst->vsi_ctx));
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
403
err = mtk_vcodec_wait_for_done_ctx(inst->ctx,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
410
memcpy(&inst->vsi_ctx, inst->vpu.vsi, sizeof(inst->vsi_ctx));
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
411
mtk_vdec_debug(inst->ctx, "\n - NALU[%d]", inst->num_nalu);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
415
mtk_vdec_err(inst->ctx, "\n - NALU[%d] err=%d -\n", inst->num_nalu, err);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
421
struct vdec_h264_slice_inst *inst = h_vdec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
425
get_pic_info(inst, out);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
429
get_dpb_size(inst, out);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
433
get_crop_info(inst, out);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
437
mtk_vdec_err(inst->ctx, "invalid get parameter type=%d", type);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_if.c
96
static int get_vdec_decode_parameters(struct vdec_h264_slice_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1001
vdec_msg_queue_qbuf(&inst->ctx->msg_queue.lat_ctx, lat_buf);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1002
mtk_vdec_err(inst->ctx, "slice dec number: %d err: %d", inst->slice_dec_num, err);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1009
struct vdec_h264_slice_inst *inst = h_vdec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1010
struct vdec_vpu_inst *vpu = &inst->vpu;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1022
fb = inst->ctx->dev->vdec_pdata->get_cap_buffer(inst->ctx);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1024
mtk_vdec_err(inst->ctx,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1034
mtk_vdec_debug(inst->ctx, "[h264-dec] [%d] y_dma=%llx c_dma=%llx",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1035
inst->ctx->decoded_frame_cnt, y_fb_dma, c_fb_dma);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1037
inst->vsi_ctx_ext.bs.dma_addr = (u64)bs->dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1038
inst->vsi_ctx_ext.bs.size = bs->size;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1039
inst->vsi_ctx_ext.fb.y.dma_addr = y_fb_dma;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1040
inst->vsi_ctx_ext.fb.c.dma_addr = c_fb_dma;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1041
inst->vsi_ctx_ext.dec.vdec_fb_va = (u64)(uintptr_t)fb;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1045
err = get_vdec_sig_decode_parameters(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1049
memcpy(&inst->vsi_ctx_ext.h264_slice_params, &inst->h264_slice_param,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1050
sizeof(inst->vsi_ctx_ext.h264_slice_params));
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1052
*res_chg = inst->resolution_changed;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1053
if (inst->resolution_changed) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1054
mtk_vdec_debug(inst->ctx, "- resolution changed -");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1055
if (inst->realloc_mv_buf) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1056
err = vdec_h264_slice_alloc_mv_buf(inst, &inst->ctx->picinfo);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1057
inst->realloc_mv_buf = false;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1061
inst->resolution_changed = false;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1064
mem = &inst->mv_buf[i];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1065
inst->vsi_ctx_ext.mv_buf_dma[i].dma_addr = mem->dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1069
memcpy(inst->vpu.vsi, &inst->vsi_ctx_ext, sizeof(inst->vsi_ctx_ext));
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1075
err = mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1078
mtk_vdec_err(inst->ctx, "decode timeout: pic_%d", inst->ctx->decoded_frame_cnt);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1080
inst->vsi_ext->dec.timeout = !!err;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1085
memcpy(&inst->vsi_ctx_ext, inst->vpu.vsi, sizeof(inst->vsi_ctx_ext));
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1086
mtk_vdec_debug(inst->ctx, "pic[%d] crc: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1087
inst->ctx->decoded_frame_cnt,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1088
inst->vsi_ctx_ext.dec.crc[0], inst->vsi_ctx_ext.dec.crc[1],
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1089
inst->vsi_ctx_ext.dec.crc[2], inst->vsi_ctx_ext.dec.crc[3],
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1090
inst->vsi_ctx_ext.dec.crc[4], inst->vsi_ctx_ext.dec.crc[5],
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1091
inst->vsi_ctx_ext.dec.crc[6], inst->vsi_ctx_ext.dec.crc[7]);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1093
inst->ctx->decoded_frame_cnt++;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1097
mtk_vdec_err(inst->ctx, "dec frame number: %d err: %d", inst->ctx->decoded_frame_cnt, err);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1104
struct vdec_h264_slice_inst *inst = h_vdec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1105
struct vdec_vpu_inst *vpu = &inst->vpu;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1118
fb = inst->ctx->dev->vdec_pdata->get_cap_buffer(inst->ctx);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1120
mtk_vdec_err(inst->ctx,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1130
mtk_vdec_debug(inst->ctx, "[h264-dec] [%d] y_dma=%llx c_dma=%llx",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1131
inst->ctx->decoded_frame_cnt, y_fb_dma, c_fb_dma);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1133
inst->vsi_ctx.dec.bs_buf_addr = (u64)bs->dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1134
inst->vsi_ctx.dec.bs_buf_size = bs->size;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1135
inst->vsi_ctx.dec.y_fb_dma = y_fb_dma;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1136
inst->vsi_ctx.dec.c_fb_dma = c_fb_dma;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1137
inst->vsi_ctx.dec.vdec_fb_va = (u64)(uintptr_t)fb;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1141
err = get_vdec_sig_decode_parameters(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1145
memcpy(&inst->vsi_ctx.h264_slice_params, &inst->h264_slice_param,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1146
sizeof(inst->vsi_ctx.h264_slice_params));
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1154
inst->vsi_ctx.dec.nal_info = buf[nal_start_idx];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1156
*res_chg = inst->resolution_changed;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1157
if (inst->resolution_changed) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1158
mtk_vdec_debug(inst->ctx, "- resolution changed -");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1159
if (inst->realloc_mv_buf) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1160
err = vdec_h264_slice_alloc_mv_buf(inst, &inst->ctx->picinfo);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1161
inst->realloc_mv_buf = false;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1165
inst->resolution_changed = false;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1168
mem = &inst->mv_buf[i];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1169
inst->vsi_ctx.mv_buf_dma[i] = mem->dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1173
memcpy(inst->vpu.vsi, &inst->vsi_ctx, sizeof(inst->vsi_ctx));
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1179
err = mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1182
mtk_vdec_err(inst->ctx, "decode timeout: pic_%d", inst->ctx->decoded_frame_cnt);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1184
inst->vsi->dec.timeout = !!err;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1189
memcpy(&inst->vsi_ctx, inst->vpu.vsi, sizeof(inst->vsi_ctx));
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1190
mtk_vdec_debug(inst->ctx, "pic[%d] crc: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1191
inst->ctx->decoded_frame_cnt,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1192
inst->vsi_ctx.dec.crc[0], inst->vsi_ctx.dec.crc[1],
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1193
inst->vsi_ctx.dec.crc[2], inst->vsi_ctx.dec.crc[3],
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1194
inst->vsi_ctx.dec.crc[4], inst->vsi_ctx.dec.crc[5],
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1195
inst->vsi_ctx.dec.crc[6], inst->vsi_ctx.dec.crc[7]);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1197
inst->ctx->decoded_frame_cnt++;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1201
mtk_vdec_err(inst->ctx, "dec frame number: %d err: %d", inst->ctx->decoded_frame_cnt, err);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1207
struct vdec_h264_slice_inst *inst;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1211
inst = kzalloc_obj(*inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1212
if (!inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1215
inst->ctx = ctx;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1217
inst->vpu.id = SCP_IPI_VDEC_LAT;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1218
inst->vpu.core_id = SCP_IPI_VDEC_CORE;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1219
inst->vpu.ctx = ctx;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1220
inst->vpu.codec_type = ctx->current_codec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1221
inst->vpu.capture_type = ctx->capture_fourcc;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1223
err = vpu_dec_init(&inst->vpu);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1233
inst->vsi_ext = inst->vpu.vsi;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1234
temp = (unsigned char *)inst->vsi_ext;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1235
inst->vsi_core_ext = (struct vdec_h264_slice_vsi_ext *)(temp + vsi_size);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1237
if (inst->ctx->dev->vdec_pdata->hw_arch == MTK_VDEC_PURE_SINGLE_CORE)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1238
inst->decode = vdec_h264_slice_single_decode_ext;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1240
inst->decode = vdec_h264_slice_lat_decode_ext;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1245
inst->vsi = inst->vpu.vsi;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1246
temp = (unsigned char *)inst->vsi;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1247
inst->vsi_core = (struct vdec_h264_slice_vsi *)(temp + vsi_size);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1249
if (inst->ctx->dev->vdec_pdata->hw_arch == MTK_VDEC_PURE_SINGLE_CORE)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1250
inst->decode = vdec_h264_slice_single_decode;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1252
inst->decode = vdec_h264_slice_lat_decode;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1254
inst->resolution_changed = true;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1255
inst->realloc_mv_buf = true;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1264
inst, inst->vpu.codec_type);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1266
ctx->drv_handle = inst;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1270
kfree(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1276
struct vdec_h264_slice_inst *inst = h_vdec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1278
vpu_dec_deinit(&inst->vpu);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1279
vdec_h264_slice_free_mv_buf(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1280
vdec_msg_queue_deinit(&inst->ctx->msg_queue, inst->ctx);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1282
kfree(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1288
struct vdec_h264_slice_inst *inst = h_vdec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1293
return inst->decode(h_vdec, bs, unused, res_chg);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1299
struct vdec_h264_slice_inst *inst = h_vdec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1303
vdec_h264_slice_get_pic_info(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1309
vdec_h264_slice_get_crop_info(inst, out);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
1312
mtk_vdec_err(inst->ctx, "invalid get parameter type=%d", type);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
268
static int vdec_h264_slice_fill_decode_parameters(struct vdec_h264_slice_inst *inst,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
278
mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_DECODE_PARAMS);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
283
mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_SCALING_MATRIX);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
287
sps = mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_SPS);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
291
pps = mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_PPS);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
296
mtk_vdec_err(inst->ctx, "No support for H.264 field decoding.");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
297
inst->is_field_bitstream = true;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
311
static int get_vdec_sig_decode_parameters(struct vdec_h264_slice_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
317
struct vdec_h264_slice_lat_dec_param *slice_param = &inst->h264_slice_param;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
327
mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_DECODE_PARAMS);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
331
sps = mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_SPS);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
335
pps = mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_PPS);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
340
mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_SCALING_MATRIX);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
344
mtk_vdec_h264_update_dpb(dec_params, inst->dpb);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
350
mtk_vdec_h264_copy_decode_params(&slice_param->decode_params, dec_params, inst->dpb);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
351
mtk_vdec_h264_fill_dpb_info(inst->ctx, &slice_param->decode_params,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
355
v4l2_h264_init_reflist_builder(&reflist_builder, dec_params, sps, inst->dpb);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
367
static void vdec_h264_slice_fill_decode_reflist(struct vdec_h264_slice_inst *inst,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
381
mtk_vdec_h264_update_dpb(dec_params, inst->dpb);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
384
inst->dpb);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
385
mtk_vdec_h264_fill_dpb_info(inst->ctx, &slice_param->decode_params,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
388
mtk_v4l2_vdec_dbg(3, inst->ctx, "cur poc = %d\n", dec_params->bottom_field_order_cnt);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
391
inst->dpb);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
401
static int vdec_h264_slice_alloc_mv_buf(struct vdec_h264_slice_inst *inst,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
408
mtk_v4l2_vdec_dbg(3, inst->ctx, "size = 0x%x", buf_sz);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
410
mem = &inst->mv_buf[i];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
412
mtk_vcodec_mem_free(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
414
err = mtk_vcodec_mem_alloc(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
416
mtk_vdec_err(inst->ctx, "failed to allocate mv buf");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
424
static void vdec_h264_slice_free_mv_buf(struct vdec_h264_slice_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
430
mem = &inst->mv_buf[i];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
432
mtk_vcodec_mem_free(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
436
static void vdec_h264_slice_get_pic_info(struct vdec_h264_slice_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
438
struct mtk_vcodec_dec_ctx *ctx = inst->ctx;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
444
vpu_dec_get_param(&inst->vpu, data, 3, GET_PARAM_PIC_INFO);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
448
ctx->picinfo.fb_sz[0] = inst->vpu.fb_sz[0];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
449
ctx->picinfo.fb_sz[1] = inst->vpu.fb_sz[1];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
450
inst->cap_num_planes =
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
461
inst->resolution_changed = true;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
464
inst->realloc_mv_buf = true;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
466
mtk_v4l2_vdec_dbg(1, inst->ctx, "resChg: (%d %d) : old(%d, %d) -> new(%d, %d)",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
467
inst->resolution_changed,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
468
inst->realloc_mv_buf,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
475
static void vdec_h264_slice_get_crop_info(struct vdec_h264_slice_inst *inst,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
480
cr->width = inst->ctx->picinfo.pic_w;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
481
cr->height = inst->ctx->picinfo.pic_h;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
483
mtk_vdec_debug(inst->ctx, "l=%d, t=%d, w=%d, h=%d",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
487
static void vdec_h264_slice_setup_lat_buffer_ext(struct vdec_h264_slice_inst *inst,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
494
inst->vsi_ext->bs.dma_addr = (u64)bs->dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
495
inst->vsi_ext->bs.size = bs->size;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
498
mem = &inst->mv_buf[i];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
499
inst->vsi_ext->mv_buf_dma[i].dma_addr = mem->dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
500
inst->vsi_ext->mv_buf_dma[i].size = mem->size;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
502
inst->vsi_ext->ube.dma_addr = lat_buf->ctx->msg_queue.wdma_addr.dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
503
inst->vsi_ext->ube.size = lat_buf->ctx->msg_queue.wdma_addr.size;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
505
inst->vsi_ext->row_info.dma_addr = 0;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
506
inst->vsi_ext->row_info.size = 0;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
508
inst->vsi_ext->err_map.dma_addr = lat_buf->wdma_err_addr.dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
509
inst->vsi_ext->err_map.size = lat_buf->wdma_err_addr.size;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
511
inst->vsi_ext->slice_bc.dma_addr = lat_buf->slice_bc_addr.dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
512
inst->vsi_ext->slice_bc.size = lat_buf->slice_bc_addr.size;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
514
inst->vsi_ext->trans.dma_addr_end = inst->ctx->msg_queue.wdma_rptr_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
515
inst->vsi_ext->trans.dma_addr = inst->ctx->msg_queue.wdma_wptr_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
518
static int vdec_h264_slice_setup_core_buffer_ext(struct vdec_h264_slice_inst *inst,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
523
struct mtk_vcodec_dec_ctx *ctx = inst->ctx;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
543
inst->vsi_core_ext->fb.y.dma_addr = y_fb_dma;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
544
inst->vsi_core_ext->fb.y.size = ctx->picinfo.fb_sz[0];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
545
inst->vsi_core_ext->fb.c.dma_addr = c_fb_dma;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
546
inst->vsi_core_ext->fb.c.size = ctx->picinfo.fb_sz[1];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
548
inst->vsi_core_ext->dec.vdec_fb_va = (unsigned long)fb;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
549
inst->vsi_core_ext->dec.nal_info = share_info->nal_info;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
551
inst->vsi_core_ext->ube.dma_addr = lat_buf->ctx->msg_queue.wdma_addr.dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
552
inst->vsi_core_ext->ube.size = lat_buf->ctx->msg_queue.wdma_addr.size;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
554
inst->vsi_core_ext->err_map.dma_addr = lat_buf->wdma_err_addr.dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
555
inst->vsi_core_ext->err_map.size = lat_buf->wdma_err_addr.size;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
557
inst->vsi_core_ext->slice_bc.dma_addr = lat_buf->slice_bc_addr.dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
558
inst->vsi_core_ext->slice_bc.size = lat_buf->slice_bc_addr.size;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
560
inst->vsi_core_ext->row_info.dma_addr = 0;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
561
inst->vsi_core_ext->row_info.size = 0;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
563
inst->vsi_core_ext->trans.dma_addr = share_info->trans_start;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
564
inst->vsi_core_ext->trans.dma_addr_end = share_info->trans_end;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
567
mem = &inst->mv_buf[i];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
568
inst->vsi_core_ext->mv_buf_dma[i].dma_addr = mem->dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
569
inst->vsi_core_ext->mv_buf_dma[i].size = mem->size;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
582
struct vdec_h264_slice_inst *inst = ctx->drv_handle;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
584
struct vdec_vpu_inst *vpu = &inst->vpu;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
586
memcpy(&inst->vsi_core_ext->h264_slice_params, &share_info->h264_slice_params,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
589
err = vdec_h264_slice_setup_core_buffer_ext(inst, share_info, lat_buf);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
593
vdec_h264_slice_fill_decode_reflist(inst, &inst->vsi_core_ext->h264_slice_params,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
602
timeout = mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
606
inst->vsi_core_ext->dec.timeout = !!timeout;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
613
inst->vsi_core_ext->dec.crc[0], inst->vsi_core_ext->dec.crc[1],
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
614
inst->vsi_core_ext->dec.crc[2], inst->vsi_core_ext->dec.crc[3],
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
615
inst->vsi_core_ext->dec.crc[4], inst->vsi_core_ext->dec.crc[5],
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
616
inst->vsi_core_ext->dec.crc[6], inst->vsi_core_ext->dec.crc[7]);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
632
struct vdec_h264_slice_inst *inst = ctx->drv_handle;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
636
struct vdec_vpu_inst *vpu = &inst->vpu;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
638
memcpy(&inst->vsi_core->h264_slice_params, &share_info->h264_slice_params,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
656
inst->vsi_core->dec.y_fb_dma = y_fb_dma;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
657
inst->vsi_core->dec.c_fb_dma = c_fb_dma;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
658
inst->vsi_core->dec.vdec_fb_va = (unsigned long)fb;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
659
inst->vsi_core->dec.nal_info = share_info->nal_info;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
660
inst->vsi_core->wdma_start_addr =
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
662
inst->vsi_core->wdma_end_addr =
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
665
inst->vsi_core->wdma_err_addr = lat_buf->wdma_err_addr.dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
666
inst->vsi_core->slice_bc_start_addr = lat_buf->slice_bc_addr.dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
667
inst->vsi_core->slice_bc_end_addr = lat_buf->slice_bc_addr.dma_addr +
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
669
inst->vsi_core->trans_start = share_info->trans_start;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
670
inst->vsi_core->trans_end = share_info->trans_end;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
672
mem = &inst->mv_buf[i];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
673
inst->vsi_core->mv_buf_dma[i] = mem->dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
679
vdec_h264_slice_fill_decode_reflist(inst, &inst->vsi_core->h264_slice_params,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
689
timeout = mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
693
inst->vsi_core->dec.timeout = !!timeout;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
700
inst->vsi_core->dec.crc[0], inst->vsi_core->dec.crc[1],
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
701
inst->vsi_core->dec.crc[2], inst->vsi_core->dec.crc[3],
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
702
inst->vsi_core->dec.crc[4], inst->vsi_core->dec.crc[5],
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
703
inst->vsi_core->dec.crc[6], inst->vsi_core->dec.crc[7]);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
740
struct vdec_h264_slice_inst *inst = h_vdec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
741
struct vdec_vpu_inst *vpu = &inst->vpu;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
748
if (vdec_msg_queue_init(&inst->ctx->msg_queue, inst->ctx,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
755
vdec_msg_queue_wait_lat_buf_full(&inst->ctx->msg_queue);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
759
if (inst->is_field_bitstream)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
762
lat_buf = vdec_msg_queue_dqbuf(&inst->ctx->msg_queue.lat_ctx);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
764
mtk_vdec_debug(inst->ctx, "failed to get lat buffer");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
774
err = vdec_h264_slice_fill_decode_parameters(inst, share_info,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
775
&inst->vsi_ext->h264_slice_params);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
779
vdec_h264_insert_startcode(inst->ctx->dev, bs->va, &bs->size,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
782
*res_chg = inst->resolution_changed;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
783
if (inst->resolution_changed) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
784
mtk_vdec_debug(inst->ctx, "- resolution changed -");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
785
if (inst->realloc_mv_buf) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
786
err = vdec_h264_slice_alloc_mv_buf(inst, &inst->ctx->picinfo);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
787
inst->realloc_mv_buf = false;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
791
inst->resolution_changed = false;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
794
vdec_h264_slice_setup_lat_buffer_ext(inst, bs, lat_buf);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
795
mtk_vdec_debug(inst->ctx, "lat:trans(0x%llx 0x%lx) err:0x%llx",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
796
inst->vsi_ext->ube.dma_addr, (unsigned long)inst->vsi_ext->ube.size,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
797
inst->vsi_ext->err_map.dma_addr);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
799
mtk_vdec_debug(inst->ctx, "slice(0x%llx 0x%lx) rprt((0x%llx 0x%llx))",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
800
inst->vsi_ext->slice_bc.dma_addr,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
801
(unsigned long)inst->vsi_ext->slice_bc.size,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
802
inst->vsi_ext->trans.dma_addr, inst->vsi_ext->trans.dma_addr_end);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
806
mtk_vdec_debug(inst->ctx, "lat decode err: %d", err);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
810
share_info->trans_end = inst->ctx->msg_queue.wdma_addr.dma_addr +
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
811
inst->vsi_ext->dec.wdma_end_addr_offset;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
813
share_info->trans_start = inst->ctx->msg_queue.wdma_wptr_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
814
share_info->nal_info = inst->vsi_ext->dec.nal_info;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
816
if (IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability)) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
817
memcpy(&share_info->h264_slice_params, &inst->vsi_ext->h264_slice_params,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
819
vdec_msg_queue_qbuf(&inst->ctx->msg_queue.core_ctx, lat_buf);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
823
timeout = mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
826
mtk_vdec_err(inst->ctx, "lat decode timeout: pic_%d", inst->slice_dec_num);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
827
inst->vsi_ext->dec.timeout = !!timeout;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
831
if (!IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability))
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
832
vdec_msg_queue_qbuf(&inst->ctx->msg_queue.lat_ctx, lat_buf);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
833
inst->slice_dec_num++;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
834
mtk_vdec_err(inst->ctx, "lat dec fail: pic_%d err:%d", inst->slice_dec_num, err);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
838
share_info->trans_end = inst->ctx->msg_queue.wdma_addr.dma_addr +
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
839
inst->vsi_ext->dec.wdma_end_addr_offset;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
843
if (!IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability)) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
844
memcpy(&share_info->h264_slice_params, &inst->vsi_ext->h264_slice_params,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
846
vdec_msg_queue_qbuf(&inst->ctx->msg_queue.core_ctx, lat_buf);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
848
mtk_vdec_debug(inst->ctx, "dec num: %d lat crc: 0x%x 0x%x 0x%x", inst->slice_dec_num,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
849
inst->vsi_ext->dec.crc[0], inst->vsi_ext->dec.crc[1],
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
850
inst->vsi_ext->dec.crc[2]);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
852
inst->slice_dec_num++;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
855
vdec_msg_queue_qbuf(&inst->ctx->msg_queue.lat_ctx, lat_buf);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
856
mtk_vdec_err(inst->ctx, "slice dec number: %d err: %d", inst->slice_dec_num, err);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
863
struct vdec_h264_slice_inst *inst = h_vdec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
864
struct vdec_vpu_inst *vpu = &inst->vpu;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
873
if (vdec_msg_queue_init(&inst->ctx->msg_queue, inst->ctx,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
880
vdec_msg_queue_wait_lat_buf_full(&inst->ctx->msg_queue);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
884
if (inst->is_field_bitstream)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
887
lat_buf = vdec_msg_queue_dqbuf(&inst->ctx->msg_queue.lat_ctx);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
889
mtk_vdec_debug(inst->ctx, "failed to get lat buffer");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
902
inst->vsi->dec.nal_info = buf[nal_start_idx];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
907
err = vdec_h264_slice_fill_decode_parameters(inst, share_info,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
908
&inst->vsi->h264_slice_params);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
912
vdec_h264_insert_startcode(inst->ctx->dev, buf, &bs->size,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
915
inst->vsi->dec.bs_buf_addr = (uint64_t)bs->dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
916
inst->vsi->dec.bs_buf_size = bs->size;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
918
*res_chg = inst->resolution_changed;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
919
if (inst->resolution_changed) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
920
mtk_vdec_debug(inst->ctx, "- resolution changed -");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
921
if (inst->realloc_mv_buf) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
922
err = vdec_h264_slice_alloc_mv_buf(inst, &inst->ctx->picinfo);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
923
inst->realloc_mv_buf = false;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
927
inst->resolution_changed = false;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
930
mem = &inst->mv_buf[i];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
931
inst->vsi->mv_buf_dma[i] = mem->dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
933
inst->vsi->wdma_start_addr = lat_buf->ctx->msg_queue.wdma_addr.dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
934
inst->vsi->wdma_end_addr = lat_buf->ctx->msg_queue.wdma_addr.dma_addr +
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
936
inst->vsi->wdma_err_addr = lat_buf->wdma_err_addr.dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
937
inst->vsi->slice_bc_start_addr = lat_buf->slice_bc_addr.dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
938
inst->vsi->slice_bc_end_addr = lat_buf->slice_bc_addr.dma_addr +
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
941
inst->vsi->trans_end = inst->ctx->msg_queue.wdma_rptr_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
942
inst->vsi->trans_start = inst->ctx->msg_queue.wdma_wptr_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
943
mtk_vdec_debug(inst->ctx, "lat:trans(0x%llx 0x%llx) err:0x%llx",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
944
inst->vsi->wdma_start_addr,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
945
inst->vsi->wdma_end_addr,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
946
inst->vsi->wdma_err_addr);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
948
mtk_vdec_debug(inst->ctx, "slice(0x%llx 0x%llx) rprt((0x%llx 0x%llx))",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
949
inst->vsi->slice_bc_start_addr,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
950
inst->vsi->slice_bc_end_addr,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
951
inst->vsi->trans_start,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
952
inst->vsi->trans_end);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
955
mtk_vdec_debug(inst->ctx, "lat decode err: %d", err);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
959
share_info->trans_end = inst->ctx->msg_queue.wdma_addr.dma_addr +
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
960
inst->vsi->wdma_end_addr_offset;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
961
share_info->trans_start = inst->ctx->msg_queue.wdma_wptr_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
962
share_info->nal_info = inst->vsi->dec.nal_info;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
964
if (IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability)) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
965
memcpy(&share_info->h264_slice_params, &inst->vsi->h264_slice_params,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
967
vdec_msg_queue_qbuf(&inst->ctx->msg_queue.core_ctx, lat_buf);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
971
timeout = mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
974
mtk_vdec_err(inst->ctx, "lat decode timeout: pic_%d", inst->slice_dec_num);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
975
inst->vsi->dec.timeout = !!timeout;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
979
if (!IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability))
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
980
vdec_msg_queue_qbuf(&inst->ctx->msg_queue.lat_ctx, lat_buf);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
981
inst->slice_dec_num++;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
982
mtk_vdec_err(inst->ctx, "lat dec fail: pic_%d err:%d", inst->slice_dec_num, err);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
986
share_info->trans_end = inst->ctx->msg_queue.wdma_addr.dma_addr +
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
987
inst->vsi->wdma_end_addr_offset;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
990
if (!IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability)) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
991
memcpy(&share_info->h264_slice_params, &inst->vsi->h264_slice_params,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
993
vdec_msg_queue_qbuf(&inst->ctx->msg_queue.core_ctx, lat_buf);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
995
mtk_vdec_debug(inst->ctx, "dec num: %d lat crc: 0x%x 0x%x 0x%x", inst->slice_dec_num,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
996
inst->vsi->dec.crc[0], inst->vsi->dec.crc[1], inst->vsi->dec.crc[2]);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
998
inst->slice_dec_num++;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1003
err = vdec_hevc_slice_setup_lat_buffer(inst, bs, lat_buf, res_chg);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1009
mtk_vdec_debug(inst->ctx, "lat decode err: %d", err);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1013
if (IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability)) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1014
memcpy(&share_info->hevc_slice_params, &inst->vsi->hevc_slice_params,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1016
vdec_msg_queue_qbuf(&inst->ctx->msg_queue.core_ctx, lat_buf);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1020
timeout = mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1023
mtk_vdec_err(inst->ctx, "lat decode timeout: pic_%d", inst->slice_dec_num);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1024
inst->vsi->dec.timeout = !!timeout;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1028
if (!IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability))
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1029
vdec_msg_queue_qbuf(&inst->ctx->msg_queue.lat_ctx, lat_buf);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1030
inst->slice_dec_num++;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1031
mtk_vdec_err(inst->ctx, "lat dec fail: pic_%d err:%d", inst->slice_dec_num, err);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1035
share_info->trans.dma_addr_end = inst->ctx->msg_queue.wdma_addr.dma_addr +
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1036
inst->vsi->dec.wdma_end_addr_offset;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1039
if (!IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability)) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1040
memcpy(&share_info->hevc_slice_params, &inst->vsi->hevc_slice_params,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1042
vdec_msg_queue_qbuf(&inst->ctx->msg_queue.core_ctx, lat_buf);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1044
mtk_vdec_debug(inst->ctx, "dec num: %d lat crc: 0x%x 0x%x 0x%x", inst->slice_dec_num,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1045
inst->vsi->dec.crc[0], inst->vsi->dec.crc[1], inst->vsi->dec.crc[2]);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1047
inst->slice_dec_num++;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1050
vdec_msg_queue_qbuf(&inst->ctx->msg_queue.lat_ctx, lat_buf);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1051
mtk_vdec_err(inst->ctx, "slice dec number: %d err: %d", inst->slice_dec_num, err);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1058
struct vdec_hevc_slice_inst *inst = h_vdec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1060
if (!h_vdec || inst->ctx->dev->vdec_pdata->hw_arch == MTK_VDEC_PURE_SINGLE_CORE)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1069
struct vdec_hevc_slice_inst *inst = h_vdec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1073
vdec_hevc_slice_get_pic_info(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1079
vdec_hevc_slice_get_crop_info(inst, out);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
1082
mtk_vdec_err(inst->ctx, "invalid get parameter type=%d", type);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
588
static int vdec_hevc_slice_fill_decode_parameters(struct vdec_hevc_slice_inst *inst,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
591
struct vdec_hevc_slice_lat_dec_param *slice_param = &inst->vsi->hevc_slice_params;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
598
vdec_hevc_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_HEVC_DECODE_PARAMS);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
603
vdec_hevc_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_HEVC_SCALING_MATRIX);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
607
sps = vdec_hevc_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_HEVC_SPS);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
611
pps = vdec_hevc_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_HEVC_PPS);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
631
static void vdec_hevc_slice_fill_decode_reflist(struct vdec_hevc_slice_inst *inst,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
640
vdec_hevc_fill_dpb_info(inst->ctx, &slice_param->decode_params,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
644
static int vdec_hevc_slice_alloc_mv_buf(struct vdec_hevc_slice_inst *inst,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
651
mtk_v4l2_vdec_dbg(3, inst->ctx, "allocate mv buffer size = 0x%x", buf_sz);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
653
mem = &inst->mv_buf[i];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
655
mtk_vcodec_mem_free(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
657
err = mtk_vcodec_mem_alloc(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
659
mtk_vdec_err(inst->ctx, "failed to allocate mv buf");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
667
static void vdec_hevc_slice_free_mv_buf(struct vdec_hevc_slice_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
673
mem = &inst->mv_buf[i];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
675
mtk_vcodec_mem_free(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
679
static void vdec_hevc_slice_get_pic_info(struct vdec_hevc_slice_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
681
struct mtk_vcodec_dec_ctx *ctx = inst->ctx;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
687
vpu_dec_get_param(&inst->vpu, data, 3, GET_PARAM_PIC_INFO);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
691
ctx->picinfo.fb_sz[0] = inst->vpu.fb_sz[0];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
692
ctx->picinfo.fb_sz[1] = inst->vpu.fb_sz[1];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
693
inst->cap_num_planes =
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
704
inst->resolution_changed = true;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
707
inst->realloc_mv_buf = true;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
709
mtk_v4l2_vdec_dbg(1, inst->ctx, "resChg: (%d %d) : old(%d, %d) -> new(%d, %d)",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
710
inst->resolution_changed,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
711
inst->realloc_mv_buf,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
718
static void vdec_hevc_slice_get_crop_info(struct vdec_hevc_slice_inst *inst,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
723
cr->width = inst->ctx->picinfo.pic_w;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
724
cr->height = inst->ctx->picinfo.pic_h;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
726
mtk_vdec_debug(inst->ctx, "l=%d, t=%d, w=%d, h=%d",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
730
static int vdec_hevc_slice_setup_lat_buffer(struct vdec_hevc_slice_inst *inst,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
740
inst->vsi->bs.dma_addr = (u64)bs->dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
741
inst->vsi->bs.size = bs->size;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
748
*res_chg = inst->resolution_changed;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
749
if (inst->resolution_changed) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
750
mtk_vdec_debug(inst->ctx, "- resolution changed -");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
751
if (inst->realloc_mv_buf) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
752
err = vdec_hevc_slice_alloc_mv_buf(inst, &inst->ctx->picinfo);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
753
inst->realloc_mv_buf = false;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
757
inst->resolution_changed = false;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
761
mem = &inst->mv_buf[i];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
762
inst->vsi->mv_buf_dma[i].dma_addr = mem->dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
763
inst->vsi->mv_buf_dma[i].size = mem->size;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
766
inst->vsi->ube.dma_addr = lat_buf->ctx->msg_queue.wdma_addr.dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
767
inst->vsi->ube.size = lat_buf->ctx->msg_queue.wdma_addr.size;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
769
inst->vsi->err_map.dma_addr = lat_buf->wdma_err_addr.dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
770
inst->vsi->err_map.size = lat_buf->wdma_err_addr.size;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
772
inst->vsi->slice_bc.dma_addr = lat_buf->slice_bc_addr.dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
773
inst->vsi->slice_bc.size = lat_buf->slice_bc_addr.size;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
775
inst->vsi->trans.dma_addr_end = inst->ctx->msg_queue.wdma_rptr_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
776
inst->vsi->trans.dma_addr = inst->ctx->msg_queue.wdma_wptr_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
779
share_info->trans.dma_addr = inst->vsi->trans.dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
780
share_info->trans.dma_addr_end = inst->vsi->trans.dma_addr_end;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
782
mtk_vdec_debug(inst->ctx, "lat: ube addr/size(0x%llx 0x%llx) err:0x%llx",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
783
inst->vsi->ube.buf,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
784
inst->vsi->ube.padding,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
785
inst->vsi->err_map.buf);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
787
mtk_vdec_debug(inst->ctx, "slice addr/size(0x%llx 0x%llx) trans start/end((0x%llx 0x%llx))",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
788
inst->vsi->slice_bc.buf,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
789
inst->vsi->slice_bc.padding,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
790
inst->vsi->trans.buf,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
791
inst->vsi->trans.padding);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
796
static int vdec_hevc_slice_setup_core_buffer(struct vdec_hevc_slice_inst *inst,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
801
struct mtk_vcodec_dec_ctx *ctx = inst->ctx;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
809
mtk_vdec_err(inst->ctx, "fb buffer is NULL");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
816
y_fb_dma + inst->ctx->picinfo.buf_w * inst->ctx->picinfo.buf_h;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
820
mtk_vdec_debug(inst->ctx, "[hevc-core] y/c addr = 0x%llx 0x%llx", y_fb_dma, c_fb_dma);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
822
inst->vsi_core->fb.y.dma_addr = y_fb_dma;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
823
inst->vsi_core->fb.y.size = ctx->picinfo.fb_sz[0];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
824
inst->vsi_core->fb.c.dma_addr = c_fb_dma;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
825
inst->vsi_core->fb.c.size = ctx->picinfo.fb_sz[1];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
827
inst->vsi_core->dec.vdec_fb_va = (unsigned long)fb;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
829
inst->vsi_core->ube.dma_addr = lat_buf->ctx->msg_queue.wdma_addr.dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
830
inst->vsi_core->ube.size = lat_buf->ctx->msg_queue.wdma_addr.size;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
832
inst->vsi_core->err_map.dma_addr = lat_buf->wdma_err_addr.dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
833
inst->vsi_core->err_map.size = lat_buf->wdma_err_addr.size;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
835
inst->vsi_core->slice_bc.dma_addr = lat_buf->slice_bc_addr.dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
836
inst->vsi_core->slice_bc.size = lat_buf->slice_bc_addr.size;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
838
inst->vsi_core->trans.dma_addr = share_info->trans.dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
839
inst->vsi_core->trans.dma_addr_end = share_info->trans.dma_addr_end;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
841
inst->vsi_core->wrap.dma_addr = inst->wrap_addr.dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
842
inst->vsi_core->wrap.size = inst->wrap_addr.size;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
845
mem = &inst->mv_buf[i];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
846
inst->vsi_core->mv_buf_dma[i].dma_addr = mem->dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
847
inst->vsi_core->mv_buf_dma[i].size = mem->size;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
858
struct vdec_hevc_slice_inst *inst;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
861
inst = kzalloc_obj(*inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
862
if (!inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
865
inst->ctx = ctx;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
867
inst->vpu.id = SCP_IPI_VDEC_LAT;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
868
inst->vpu.core_id = SCP_IPI_VDEC_CORE;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
869
inst->vpu.ctx = ctx;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
870
inst->vpu.codec_type = ctx->current_codec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
871
inst->vpu.capture_type = ctx->capture_fourcc;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
873
err = vpu_dec_init(&inst->vpu);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
880
inst->vsi = inst->vpu.vsi;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
881
inst->vsi_core =
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
882
(struct vdec_hevc_slice_vsi *)(((char *)inst->vpu.vsi) + vsi_size);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
884
inst->resolution_changed = true;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
885
inst->realloc_mv_buf = true;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
887
inst->wrap_addr.size = VDEC_HEVC_WRAP_SZ;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
888
err = mtk_vcodec_mem_alloc(ctx, &inst->wrap_addr);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
899
inst, inst->vpu.codec_type);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
901
ctx->drv_handle = inst;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
904
kfree(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
910
struct vdec_hevc_slice_inst *inst = h_vdec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
913
vpu_dec_deinit(&inst->vpu);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
914
vdec_hevc_slice_free_mv_buf(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
916
mem = &inst->wrap_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
918
mtk_vcodec_mem_free(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
920
vdec_msg_queue_deinit(&inst->ctx->msg_queue, inst->ctx);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
921
kfree(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
928
struct vdec_hevc_slice_inst *inst = ctx->drv_handle;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
930
struct vdec_vpu_inst *vpu = &inst->vpu;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
933
memcpy(&inst->vsi_core->hevc_slice_params, &share_info->hevc_slice_params,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
936
err = vdec_hevc_slice_setup_core_buffer(inst, share_info, lat_buf);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
940
vdec_hevc_slice_fill_decode_reflist(inst, &inst->vsi_core->hevc_slice_params,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
949
timeout = mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
953
inst->vsi_core->dec.timeout = !!timeout;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
958
inst->vsi_core->dec.crc[0], inst->vsi_core->dec.crc[1],
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
959
inst->vsi_core->dec.crc[2], inst->vsi_core->dec.crc[3],
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
960
inst->vsi_core->dec.crc[4], inst->vsi_core->dec.crc[5],
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
961
inst->vsi_core->dec.crc[6], inst->vsi_core->dec.crc[7]);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
974
struct vdec_hevc_slice_inst *inst = h_vdec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
975
struct vdec_vpu_inst *vpu = &inst->vpu;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
981
if (vdec_msg_queue_init(&inst->ctx->msg_queue, inst->ctx,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
988
vdec_msg_queue_wait_lat_buf_full(&inst->ctx->msg_queue);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
992
lat_buf = vdec_msg_queue_dqbuf(&inst->ctx->msg_queue.lat_ctx);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
994
mtk_vdec_debug(inst->ctx, "failed to get lat buffer");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c
999
err = vdec_hevc_slice_fill_decode_parameters(inst, share_info);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
165
static void get_hw_reg_base(struct vdec_vp8_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
167
void __iomem **reg_base = inst->ctx->dev->reg_base;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
169
inst->reg_base.top = mtk_vcodec_get_reg_addr(reg_base, VDEC_TOP);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
170
inst->reg_base.cm = mtk_vcodec_get_reg_addr(reg_base, VDEC_CM);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
171
inst->reg_base.hwd = mtk_vcodec_get_reg_addr(reg_base, VDEC_HWD);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
172
inst->reg_base.misc = mtk_vcodec_get_reg_addr(reg_base, VDEC_MISC);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
173
inst->reg_base.ld = mtk_vcodec_get_reg_addr(reg_base, VDEC_LD);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
174
inst->reg_base.hwb = mtk_vcodec_get_reg_addr(reg_base, VDEC_HWB);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
177
static void write_hw_segmentation_data(struct vdec_vp8_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
182
void __iomem *cm = inst->reg_base.cm;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
183
struct vdec_vp8_vsi *vsi = inst->vsi;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
185
seg_id_addr = readl(inst->reg_base.top + VP8_SEGID_DRAM_ADDR) >> 4;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
198
static void read_hw_segmentation_data(struct vdec_vp8_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
203
void __iomem *cm = inst->reg_base.cm;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
204
struct vdec_vp8_vsi *vsi = inst->vsi;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
206
seg_id_addr = readl(inst->reg_base.top + VP8_SEGID_DRAM_ADDR) >> 4;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
220
static void enable_hw_rw_function(struct vdec_vp8_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
223
void __iomem *misc = inst->reg_base.misc;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
224
void __iomem *ld = inst->reg_base.ld;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
225
void __iomem *hwb = inst->reg_base.hwb;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
226
void __iomem *hwd = inst->reg_base.hwd;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
228
mtk_vcodec_write_vdecsys(inst->ctx, VP8_RW_CKEN_SET, 0x1);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
232
mtk_vcodec_write_vdecsys(inst->ctx, 0, 0x1);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
241
mtk_vcodec_write_vdecsys(inst->ctx, VP8_RW_DCM_CON, 0x1);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
246
static void store_dec_table(struct vdec_vp8_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
250
void __iomem *hwd = inst->reg_base.hwd;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
251
u32 *p = &inst->vsi->dec_table[VP8_DEC_TABLE_OFFSET];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
263
static void load_dec_table(struct vdec_vp8_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
267
u32 *p = &inst->vsi->dec_table[VP8_DEC_TABLE_OFFSET];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
268
void __iomem *hwd = inst->reg_base.hwd;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
280
static void get_pic_info(struct vdec_vp8_inst *inst, struct vdec_pic_info *pic)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
282
*pic = inst->vsi->pic;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
284
mtk_vdec_debug(inst->ctx, "pic(%d, %d), buf(%d, %d)",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
286
mtk_vdec_debug(inst->ctx, "fb size: Y(%d), C(%d)",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
290
static void vp8_dec_finish(struct vdec_vp8_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
293
uint64_t prev_y_dma = inst->vsi->dec.prev_y_dma;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
295
mtk_vdec_debug(inst->ctx, "prev fb base dma=%llx", prev_y_dma);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
299
list_for_each_entry(node, &inst->fb_use_list, list) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
304
&inst->fb_free_list);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
311
node = list_first_entry(&inst->available_fb_node_list,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
313
node->fb = inst->cur_fb;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
314
list_move_tail(&node->list, &inst->fb_use_list);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
317
if (inst->vsi->dec.show_frame) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
318
node = list_first_entry(&inst->available_fb_node_list,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
320
node->fb = inst->cur_fb;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
321
list_move_tail(&node->list, &inst->fb_disp_list);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
325
static void move_fb_list_use_to_free(struct vdec_vp8_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
329
list_for_each_entry_safe(node, tmp, &inst->fb_use_list, list)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
330
list_move_tail(&node->list, &inst->fb_free_list);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
333
static void init_list(struct vdec_vp8_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
337
INIT_LIST_HEAD(&inst->available_fb_node_list);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
338
INIT_LIST_HEAD(&inst->fb_use_list);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
339
INIT_LIST_HEAD(&inst->fb_free_list);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
340
INIT_LIST_HEAD(&inst->fb_disp_list);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
342
for (i = 0; i < ARRAY_SIZE(inst->dec_fb); i++) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
343
INIT_LIST_HEAD(&inst->dec_fb[i].list);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
344
inst->dec_fb[i].fb = NULL;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
345
list_add_tail(&inst->dec_fb[i].list,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
346
&inst->available_fb_node_list);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
350
static void add_fb_to_free_list(struct vdec_vp8_inst *inst, void *fb)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
355
node = list_first_entry(&inst->available_fb_node_list,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
358
list_move_tail(&node->list, &inst->fb_free_list);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
362
static int alloc_working_buf(struct vdec_vp8_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
365
struct mtk_vcodec_mem *mem = &inst->working_buf;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
368
err = mtk_vcodec_mem_alloc(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
370
mtk_vdec_err(inst->ctx, "Cannot allocate working buffer");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
374
inst->vsi->dec.working_buf_dma = (uint64_t)mem->dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
378
static void free_working_buf(struct vdec_vp8_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
380
struct mtk_vcodec_mem *mem = &inst->working_buf;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
383
mtk_vcodec_mem_free(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
385
inst->vsi->dec.working_buf_dma = 0;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
390
struct vdec_vp8_inst *inst;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
393
inst = kzalloc_obj(*inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
394
if (!inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
397
inst->ctx = ctx;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
399
inst->vpu.id = IPI_VDEC_VP8;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
400
inst->vpu.ctx = ctx;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
402
err = vpu_dec_init(&inst->vpu);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
408
inst->vsi = (struct vdec_vp8_vsi *)inst->vpu.vsi;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
409
init_list(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
410
err = alloc_working_buf(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
414
get_hw_reg_base(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
415
mtk_vdec_debug(ctx, "VP8 Instance >> %p", inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
417
ctx->drv_handle = inst;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
421
vpu_dec_deinit(&inst->vpu);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
423
kfree(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
430
struct vdec_vp8_inst *inst = (struct vdec_vp8_inst *)h_vdec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
431
struct vdec_vp8_dec_info *dec = &inst->vsi->dec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
432
struct vdec_vpu_inst *vpu = &inst->vpu;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
441
move_fb_list_use_to_free(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
448
mtk_vdec_debug(inst->ctx, "+ [%d] FB y_dma=%llx c_dma=%llx fb=%p",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
449
inst->frm_cnt, y_fb_dma, c_fb_dma, fb);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
451
inst->cur_fb = fb;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
457
mtk_vdec_debug(inst->ctx, "\n + FRAME[%d] +\n", inst->frm_cnt);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
459
write_hw_segmentation_data(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
460
enable_hw_rw_function(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
461
store_dec_table(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
470
add_fb_to_free_list(inst, fb);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
472
mtk_vdec_debug(inst->ctx, "wait key frame !");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
480
mtk_vdec_debug(inst->ctx, "- resolution_changed -");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
482
add_fb_to_free_list(inst, fb);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
487
mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
490
if (inst->vsi->load_data)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
491
load_dec_table(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
493
vp8_dec_finish(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
494
read_hw_segmentation_data(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
500
mtk_vdec_debug(inst->ctx, "\n - FRAME[%d] - show=%d\n", inst->frm_cnt, dec->show_frame);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
501
inst->frm_cnt++;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
506
mtk_vdec_err(inst->ctx, "\n - FRAME[%d] - err=%d\n", inst->frm_cnt, err);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
510
static void get_disp_fb(struct vdec_vp8_inst *inst, struct vdec_fb **out_fb)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
515
node = list_first_entry_or_null(&inst->fb_disp_list,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
518
list_move_tail(&node->list, &inst->available_fb_node_list);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
521
mtk_vdec_debug(inst->ctx, "[FB] get disp fb %p st=%d", node->fb, fb->status);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
524
mtk_vdec_debug(inst->ctx, "[FB] there is no disp fb");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
530
static void get_free_fb(struct vdec_vp8_inst *inst, struct vdec_fb **out_fb)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
535
node = list_first_entry_or_null(&inst->fb_free_list,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
538
list_move_tail(&node->list, &inst->available_fb_node_list);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
541
mtk_vdec_debug(inst->ctx, "[FB] get free fb %p st=%d", node->fb, fb->status);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
544
mtk_vdec_debug(inst->ctx, "[FB] there is no free fb");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
550
static void get_crop_info(struct vdec_vp8_inst *inst, struct v4l2_rect *cr)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
554
cr->width = inst->vsi->pic.pic_w;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
555
cr->height = inst->vsi->pic.pic_h;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
556
mtk_vdec_debug(inst->ctx, "get crop info l=%d, t=%d, w=%d, h=%d",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
563
struct vdec_vp8_inst *inst = (struct vdec_vp8_inst *)h_vdec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
567
get_disp_fb(inst, out);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
571
get_free_fb(inst, out);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
575
get_pic_info(inst, out);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
579
get_crop_info(inst, out);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
587
mtk_vdec_err(inst->ctx, "invalid get parameter type=%d", type);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
596
struct vdec_vp8_inst *inst = (struct vdec_vp8_inst *)h_vdec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
598
vpu_dec_deinit(&inst->vpu);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
599
free_working_buf(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
600
kfree(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
117
static void vdec_vp8_slice_get_pic_info(struct vdec_vp8_slice_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
119
struct mtk_vcodec_dec_ctx *ctx = inst->ctx;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
125
vpu_dec_get_param(&inst->vpu, data, 3, GET_PARAM_PIC_INFO);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
129
ctx->picinfo.fb_sz[0] = inst->vpu.fb_sz[0];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
130
ctx->picinfo.fb_sz[1] = inst->vpu.fb_sz[1];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
132
inst->vsi->pic.pic_w = ctx->picinfo.pic_w;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
133
inst->vsi->pic.pic_h = ctx->picinfo.pic_h;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
134
inst->vsi->pic.buf_w = ctx->picinfo.buf_w;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
135
inst->vsi->pic.buf_h = ctx->picinfo.buf_h;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
136
inst->vsi->pic.fb_sz[0] = ctx->picinfo.fb_sz[0];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
137
inst->vsi->pic.fb_sz[1] = ctx->picinfo.fb_sz[1];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
138
mtk_vdec_debug(inst->ctx, "pic(%d, %d), buf(%d, %d)",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
141
mtk_vdec_debug(inst->ctx, "fb size: Y(%d), C(%d)",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
145
static int vdec_vp8_slice_alloc_working_buf(struct vdec_vp8_slice_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
150
mem = &inst->seg_id_buf;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
152
err = mtk_vcodec_mem_alloc(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
154
mtk_vdec_err(inst->ctx, "Cannot allocate working buffer");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
157
inst->vsi->dec.seg_id_buf_dma = (u64)mem->dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
159
mem = &inst->wrap_y_buf;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
161
err = mtk_vcodec_mem_alloc(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
163
mtk_vdec_err(inst->ctx, "cannot allocate WRAP Y buffer");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
166
inst->vsi->dec.wrap_y_dma = (u64)mem->dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
168
mem = &inst->wrap_c_buf;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
170
err = mtk_vcodec_mem_alloc(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
172
mtk_vdec_err(inst->ctx, "cannot allocate WRAP C buffer");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
175
inst->vsi->dec.wrap_c_dma = (u64)mem->dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
177
mem = &inst->vld_wrapper_buf;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
179
err = mtk_vcodec_mem_alloc(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
181
mtk_vdec_err(inst->ctx, "cannot allocate vld wrapper buffer");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
184
inst->vsi->dec.vld_wrapper_dma = (u64)mem->dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
189
static void vdec_vp8_slice_free_working_buf(struct vdec_vp8_slice_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
193
mem = &inst->seg_id_buf;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
195
mtk_vcodec_mem_free(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
196
inst->vsi->dec.seg_id_buf_dma = 0;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
198
mem = &inst->wrap_y_buf;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
200
mtk_vcodec_mem_free(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
201
inst->vsi->dec.wrap_y_dma = 0;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
203
mem = &inst->wrap_c_buf;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
205
mtk_vcodec_mem_free(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
206
inst->vsi->dec.wrap_c_dma = 0;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
208
mem = &inst->vld_wrapper_buf;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
210
mtk_vcodec_mem_free(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
211
inst->vsi->dec.vld_wrapper_dma = 0;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
231
static int vdec_vp8_slice_get_decode_parameters(struct vdec_vp8_slice_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
234
struct mtk_vcodec_dec_ctx *ctx = inst->ctx;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
240
frame_header = vdec_vp8_slice_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_VP8_FRAME);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
250
mtk_vdec_err(inst->ctx, "reference invalid: index(%d) ts(%lld)",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
252
inst->vsi->vp8_dpb_info[index].reference_flag = 0;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
255
inst->vsi->vp8_dpb_info[index].reference_flag = 1;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
257
inst->vsi->vp8_dpb_info[index].y_dma_addr =
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
260
inst->vsi->vp8_dpb_info[index].c_dma_addr =
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
263
inst->vsi->vp8_dpb_info[index].c_dma_addr =
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
264
inst->vsi->vp8_dpb_info[index].y_dma_addr +
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
268
inst->vsi->dec.frame_header_type = frame_header->flags >> 1;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
275
struct vdec_vp8_slice_inst *inst;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
278
inst = kzalloc_obj(*inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
279
if (!inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
282
inst->ctx = ctx;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
284
inst->vpu.id = SCP_IPI_VDEC_LAT;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
285
inst->vpu.core_id = SCP_IPI_VDEC_CORE;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
286
inst->vpu.ctx = ctx;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
287
inst->vpu.codec_type = ctx->current_codec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
288
inst->vpu.capture_type = ctx->capture_fourcc;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
290
err = vpu_dec_init(&inst->vpu);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
296
inst->vsi = inst->vpu.vsi;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
297
err = vdec_vp8_slice_alloc_working_buf(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
305
inst, inst->vpu.codec_type, inst->vpu.vsi);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
307
ctx->drv_handle = inst;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
311
vpu_dec_deinit(&inst->vpu);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
313
kfree(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
320
struct vdec_vp8_slice_inst *inst = h_vdec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
321
struct vdec_vpu_inst *vpu = &inst->vpu;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
336
fb = inst->ctx->dev->vdec_pdata->get_cap_buffer(inst->ctx);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
338
mtk_vdec_err(inst->ctx, "fb buffer is NULL");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
344
if (inst->ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes == 1)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
346
inst->ctx->picinfo.buf_w * inst->ctx->picinfo.buf_h;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
350
inst->vsi->dec.bs_dma = (u64)bs->dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
351
inst->vsi->dec.bs_sz = bs->size;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
352
inst->vsi->dec.cur_y_fb_dma = y_fb_dma;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
353
inst->vsi->dec.cur_c_fb_dma = c_fb_dma;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
355
mtk_vdec_debug(inst->ctx, "frame[%d] bs(%zu 0x%llx) y/c(0x%llx 0x%llx)",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
356
inst->ctx->decoded_frame_cnt,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
363
err = vdec_vp8_slice_get_decode_parameters(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
369
mtk_vdec_debug(inst->ctx, "vp8 dec start err!");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
373
if (inst->vsi->dec.resolution_changed) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
374
mtk_vdec_debug(inst->ctx, "- resolution_changed -");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
380
timeout = mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
385
mtk_vdec_debug(inst->ctx, "vp8 dec error timeout:%d err: %d pic_%d",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
386
timeout, err, inst->ctx->decoded_frame_cnt);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
388
mtk_vdec_debug(inst->ctx, "pic[%d] crc: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
389
inst->ctx->decoded_frame_cnt,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
390
inst->vsi->dec.crc[0], inst->vsi->dec.crc[1],
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
391
inst->vsi->dec.crc[2], inst->vsi->dec.crc[3],
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
392
inst->vsi->dec.crc[4], inst->vsi->dec.crc[5],
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
393
inst->vsi->dec.crc[6], inst->vsi->dec.crc[7]);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
395
inst->ctx->decoded_frame_cnt++;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
402
struct vdec_vp8_slice_inst *inst = h_vdec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
406
vdec_vp8_slice_get_pic_info(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
409
mtk_vdec_debug(inst->ctx, "No need to get vp8 crop information.");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
415
mtk_vdec_err(inst->ctx, "invalid get parameter type=%d", type);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
424
struct vdec_vp8_slice_inst *inst = h_vdec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
426
vpu_dec_deinit(&inst->vpu);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
427
vdec_vp8_slice_free_working_buf(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_req_if.c
428
kfree(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
1001
get_crop_info(inst, out);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
1004
mtk_vdec_err(inst->ctx, "not supported param type %d", type);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
207
static bool vp9_is_sf_ref_fb(struct vdec_vp9_inst *inst, struct vdec_fb *fb)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
210
struct vdec_vp9_vsi *vsi = inst->vsi;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
220
*inst, void *addr)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
225
list_for_each_entry(node, &inst->fb_use_list, list) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
229
&inst->available_fb_node_list);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
237
static void vp9_add_to_fb_free_list(struct vdec_vp9_inst *inst,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
243
node = list_first_entry_or_null(&inst->available_fb_node_list,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
248
list_move_tail(&node->list, &inst->fb_free_list);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
251
mtk_vdec_debug(inst->ctx, "No free fb node");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
263
static void vp9_ref_cnt_fb(struct vdec_vp9_inst *inst, int *idx,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
266
struct vdec_vp9_vsi *vsi = inst->vsi;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
273
if (!vp9_is_sf_ref_fb(inst,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
277
fb = vp9_rm_from_fb_use_list(inst,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
279
vp9_add_to_fb_free_list(inst, fb);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
290
static void vp9_free_all_sf_ref_fb(struct vdec_vp9_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
293
struct vdec_vp9_vsi *vsi = inst->vsi;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
297
mtk_vcodec_mem_free(inst->ctx,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
299
mtk_vcodec_mem_free(inst->ctx,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
311
static int vp9_get_sf_ref_fb(struct vdec_vp9_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
316
struct vdec_vp9_vsi *vsi = inst->vsi;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
335
mtk_vdec_err(inst->ctx, "List Full");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
343
if (mtk_vcodec_mem_alloc(inst->ctx, mem_basy_y)) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
344
mtk_vdec_err(inst->ctx, "Cannot allocate sf_ref_buf y_buf");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
352
if (mtk_vcodec_mem_alloc(inst->ctx, mem_basy_c)) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
353
mtk_vdec_err(inst->ctx, "Cannot allocate sf_ref_fb c_buf");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
361
static bool vp9_alloc_work_buf(struct vdec_vp9_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
363
struct vdec_vp9_vsi *vsi = inst->vsi;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
371
if (!(inst->ctx->dev->dec_capability &
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
382
mtk_vdec_err(inst->ctx, "Invalid w/h %d/%d", vsi->pic_w, vsi->pic_h);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
386
mtk_vdec_debug(inst->ctx, "BUF CHG(%d): w/h/sb_w/sb_h=%d/%d/%d/%d",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
390
mem = &inst->mv_buf;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
392
mtk_vcodec_mem_free(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
396
result = mtk_vcodec_mem_alloc(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
399
mtk_vdec_err(inst->ctx, "Cannot allocate mv_buf");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
408
mem = &inst->seg_id_buf;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
410
mtk_vcodec_mem_free(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
413
result = mtk_vcodec_mem_alloc(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
416
mtk_vdec_err(inst->ctx, "Cannot allocate seg_id_buf");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
425
vp9_free_all_sf_ref_fb(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
426
vsi->sf_next_ref_fb_idx = vp9_get_sf_ref_fb(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
431
static bool vp9_add_to_fb_disp_list(struct vdec_vp9_inst *inst,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
437
mtk_vdec_err(inst->ctx, "fb == NULL");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
441
node = list_first_entry_or_null(&inst->available_fb_node_list,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
445
list_move_tail(&node->list, &inst->fb_disp_list);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
447
mtk_vdec_err(inst->ctx, "No available fb node");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
455
static void vp9_swap_frm_bufs(struct vdec_vp9_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
457
struct vdec_vp9_vsi *vsi = inst->vsi;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
463
vp9_ref_cnt_fb(inst, &vsi->ref_frm_map[ref_index],
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
471
if (frm_to_show->fb != inst->cur_fb) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
477
(inst->cur_fb->base_y.size >=
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
479
(inst->cur_fb->base_c.size >=
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
481
memcpy((void *)inst->cur_fb->base_y.va,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
484
memcpy((void *)inst->cur_fb->base_c.va,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
493
mtk_vdec_err(inst->ctx,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
495
inst->cur_fb->base_y.size,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
498
if (!vp9_is_sf_ref_fb(inst, inst->cur_fb)) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
500
vp9_add_to_fb_disp_list(inst, inst->cur_fb);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
503
if (!vp9_is_sf_ref_fb(inst, inst->cur_fb)) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
505
vp9_add_to_fb_disp_list(inst, frm_to_show->fb);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
514
inst, vsi->frm_bufs[vsi->new_fb_idx].buf.fb)) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
517
fb = vp9_rm_from_fb_use_list(inst,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
520
vp9_add_to_fb_free_list(inst, fb);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
531
vsi->sf_next_ref_fb_idx = vp9_get_sf_ref_fb(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
534
static bool vp9_wait_dec_end(struct vdec_vp9_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
536
struct mtk_vcodec_dec_ctx *ctx = inst->ctx;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
538
mtk_vcodec_wait_for_done_ctx(inst->ctx,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
552
struct vdec_vp9_inst *inst;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
559
inst = mem.va;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
560
inst->mem = mem;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
562
return inst;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
565
static void vp9_free_inst(struct vdec_vp9_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
569
mem = inst->mem;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
571
mtk_vcodec_mem_free(inst->ctx, &mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
574
static bool vp9_decode_end_proc(struct vdec_vp9_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
576
struct vdec_vp9_vsi *vsi = inst->vsi;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
580
ret = vp9_wait_dec_end(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
582
mtk_vdec_err(inst->ctx, "Decode failed, Decode Timeout @[%d]",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
587
if (vpu_dec_end(&inst->vpu)) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
588
mtk_vdec_err(inst->ctx, "vp9_dec_vpu_end failed");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
591
mtk_vdec_debug(inst->ctx, "Decode Ok @%d (%d/%d)", vsi->frm_num,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
594
mtk_vdec_debug(inst->ctx, "Decode Ok @%d (show_existing_frame)", vsi->frm_num);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
597
vp9_swap_frm_bufs(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
602
static bool vp9_is_last_sub_frm(struct vdec_vp9_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
604
struct vdec_vp9_vsi *vsi = inst->vsi;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
612
static struct vdec_fb *vp9_rm_from_fb_disp_list(struct vdec_vp9_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
617
node = list_first_entry_or_null(&inst->fb_disp_list,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
622
list_move_tail(&node->list, &inst->available_fb_node_list);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
623
mtk_vdec_debug(inst->ctx, "[FB] get disp fb %p st=%d", node->fb, fb->status);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
625
mtk_vdec_debug(inst->ctx, "[FB] there is no disp fb");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
630
static bool vp9_add_to_fb_use_list(struct vdec_vp9_inst *inst,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
636
mtk_vdec_debug(inst->ctx, "fb == NULL");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
640
node = list_first_entry_or_null(&inst->available_fb_node_list,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
644
list_move_tail(&node->list, &inst->fb_use_list);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
646
mtk_vdec_err(inst->ctx, "No free fb node");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
652
static void vp9_reset(struct vdec_vp9_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
656
list_for_each_entry_safe(node, tmp, &inst->fb_use_list, list)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
657
list_move_tail(&node->list, &inst->fb_free_list);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
659
vp9_free_all_sf_ref_fb(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
660
inst->vsi->sf_next_ref_fb_idx = vp9_get_sf_ref_fb(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
662
if (vpu_dec_reset(&inst->vpu))
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
663
mtk_vdec_err(inst->ctx, "vp9_dec_vpu_reset failed");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
666
inst->vsi->mv_buf.va = (unsigned long)inst->mv_buf.va;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
667
inst->vsi->mv_buf.pa = (unsigned long)inst->mv_buf.dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
668
inst->vsi->mv_buf.sz = (unsigned long)inst->mv_buf.size;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
671
inst->vsi->seg_id_buf.va = (unsigned long)inst->seg_id_buf.va;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
672
inst->vsi->seg_id_buf.pa = (unsigned long)inst->seg_id_buf.dma_addr;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
673
inst->vsi->seg_id_buf.sz = (unsigned long)inst->seg_id_buf.size;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
677
static void init_all_fb_lists(struct vdec_vp9_inst *inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
681
INIT_LIST_HEAD(&inst->available_fb_node_list);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
682
INIT_LIST_HEAD(&inst->fb_use_list);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
683
INIT_LIST_HEAD(&inst->fb_free_list);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
684
INIT_LIST_HEAD(&inst->fb_disp_list);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
686
for (i = 0; i < ARRAY_SIZE(inst->dec_fb); i++) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
687
INIT_LIST_HEAD(&inst->dec_fb[i].list);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
688
inst->dec_fb[i].fb = NULL;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
689
list_add_tail(&inst->dec_fb[i].list,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
690
&inst->available_fb_node_list);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
694
static void get_pic_info(struct vdec_vp9_inst *inst, struct vdec_pic_info *pic)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
696
pic->fb_sz[0] = inst->vsi->buf_sz_y_bs + inst->vsi->buf_len_sz_y;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
697
pic->fb_sz[1] = inst->vsi->buf_sz_c_bs + inst->vsi->buf_len_sz_c;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
699
pic->pic_w = inst->vsi->pic_w;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
700
pic->pic_h = inst->vsi->pic_h;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
701
pic->buf_w = inst->vsi->buf_w;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
702
pic->buf_h = inst->vsi->buf_h;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
704
mtk_vdec_debug(inst->ctx, "pic(%d, %d), buf(%d, %d)",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
706
mtk_vdec_debug(inst->ctx, "fb size: Y(%d), C(%d)", pic->fb_sz[0], pic->fb_sz[1]);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
709
static void get_disp_fb(struct vdec_vp9_inst *inst, struct vdec_fb **out_fb)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
712
*out_fb = vp9_rm_from_fb_disp_list(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
717
static void get_free_fb(struct vdec_vp9_inst *inst, struct vdec_fb **out_fb)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
722
node = list_first_entry_or_null(&inst->fb_free_list,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
725
list_move_tail(&node->list, &inst->available_fb_node_list);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
728
mtk_vdec_debug(inst->ctx, "[FB] get free fb %p st=%d", node->fb, fb->status);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
730
mtk_vdec_debug(inst->ctx, "[FB] there is no free fb");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
736
static int validate_vsi_array_indexes(struct vdec_vp9_inst *inst,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
739
mtk_vdec_err(inst->ctx, "Invalid vsi->sf_frm_idx=%u.", vsi->sf_frm_idx);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
743
mtk_vdec_err(inst->ctx, "Invalid vsi->frm_to_show_idx=%u.", vsi->frm_to_show_idx);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
747
mtk_vdec_err(inst->ctx, "Invalid vsi->new_fb_idx=%u.", vsi->new_fb_idx);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
755
struct vdec_vp9_inst *inst = (struct vdec_vp9_inst *)h_vdec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
759
ret = vpu_dec_deinit(&inst->vpu);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
761
mtk_vdec_err(inst->ctx, "vpu_dec_deinit failed");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
763
mem = &inst->mv_buf;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
765
mtk_vcodec_mem_free(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
767
mem = &inst->seg_id_buf;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
769
mtk_vcodec_mem_free(inst->ctx, mem);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
771
vp9_free_all_sf_ref_fb(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
772
vp9_free_inst(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
777
struct vdec_vp9_inst *inst;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
779
inst = vp9_alloc_inst(ctx);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
780
if (!inst)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
783
inst->total_frm_cnt = 0;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
784
inst->ctx = ctx;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
786
inst->vpu.id = IPI_VDEC_VP9;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
787
inst->vpu.ctx = ctx;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
789
if (vpu_dec_init(&inst->vpu)) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
790
mtk_vdec_err(inst->ctx, "vp9_dec_vpu_init failed");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
794
inst->vsi = (struct vdec_vp9_vsi *)inst->vpu.vsi;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
796
inst->vsi->show_frame |= BIT(3);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
798
init_all_fb_lists(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
800
ctx->drv_handle = inst;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
804
vp9_free_inst(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
813
struct vdec_vp9_inst *inst = (struct vdec_vp9_inst *)h_vdec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
814
struct vdec_vp9_vsi *vsi = inst->vsi;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
821
mtk_vdec_debug(inst->ctx, "[EOS]");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
822
vp9_reset(inst);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
827
mtk_vdec_err(inst->ctx, "bs == NULL");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
831
mtk_vdec_debug(inst->ctx, "Input BS Size = %zu", bs->size);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
870
memset(inst->seg_id_buf.va, 0, inst->seg_id_buf.size);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
872
ret = vpu_dec_start(&inst->vpu, data, 3);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
874
mtk_vdec_err(inst->ctx, "vpu_dec_start failed");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
879
memset(inst->seg_id_buf.va, 0, inst->seg_id_buf.size);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
882
ret = vpu_dec_start(&inst->vpu, NULL, 0);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
884
mtk_vdec_err(inst->ctx, "vpu trig decoder failed");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
890
ret = validate_vsi_array_indexes(inst, vsi);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
892
mtk_vdec_err(inst->ctx, "Invalid values from VPU.");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
897
if (!vp9_alloc_work_buf(inst)) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
907
inst->cur_fb = cur_fb;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
909
inst->cur_fb = fb;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
911
inst->cur_fb = fb;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
914
vsi->frm_bufs[vsi->new_fb_idx].buf.fb = inst->cur_fb;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
915
if (!vp9_is_sf_ref_fb(inst, inst->cur_fb))
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
916
vp9_add_to_fb_use_list(inst, inst->cur_fb);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
918
mtk_vdec_debug(inst->ctx, "[#pic %d]", vsi->frm_num);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
921
mtk_vdec_debug(inst->ctx,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
927
mtk_vdec_debug(inst->ctx,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
931
vp9_ref_cnt_fb(inst, &vsi->new_fb_idx,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
946
mtk_vdec_debug(inst->ctx, "VDEC_ST_RESOLUTION_CHANGED");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
952
if (!vp9_decode_end_proc(inst)) {
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
953
mtk_vdec_err(inst->ctx, "vp9_decode_end_proc");
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
958
if (vp9_is_last_sub_frm(inst))
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
962
inst->total_frm_cnt++;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
966
vp9_add_to_fb_free_list(inst, fb);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
971
static void get_crop_info(struct vdec_vp9_inst *inst, struct v4l2_rect *cr)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
975
cr->width = inst->vsi->pic_w;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
976
cr->height = inst->vsi->pic_h;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
977
mtk_vdec_debug(inst->ctx, "get crop info l=%d, t=%d, w=%d, h=%d\n",
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
984
struct vdec_vp9_inst *inst = (struct vdec_vp9_inst *)h_vdec;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
989
get_disp_fb(inst, out);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
992
get_free_fb(inst, out);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_if.c
995
get_pic_info(inst, out);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
226
static inline u32 h264_read_reg(struct venc_h264_inst *inst, u32 addr)
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
228
return readl(inst->hw_base + addr);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
231
static unsigned int h264_get_profile(struct venc_h264_inst *inst,
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
242
mtk_venc_err(inst->ctx, "unsupported CONSTRAINED_BASELINE");
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
245
mtk_venc_err(inst->ctx, "unsupported EXTENDED");
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
248
mtk_venc_debug(inst->ctx, "unsupported profile %d", profile);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
253
static unsigned int h264_get_level(struct venc_h264_inst *inst,
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
258
mtk_venc_err(inst->ctx, "unsupported 1B");
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
291
mtk_venc_debug(inst->ctx, "unsupported level %d", level);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
296
static void h264_enc_free_work_buf(struct venc_h264_inst *inst)
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
304
if (i != VENC_H264_VPU_WORK_BUF_SKIP_FRAME && inst->work_bufs[i].va)
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
305
mtk_vcodec_mem_free(inst->ctx, &inst->work_bufs[i]);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
308
if (inst->pps_buf.va)
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
309
mtk_vcodec_mem_free(inst->ctx, &inst->pps_buf);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
312
static int h264_enc_alloc_work_buf(struct venc_h264_inst *inst, bool is_34bit)
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
321
wb_34 = inst->vsi_34->work_bufs;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
323
wb = inst->vsi->work_bufs;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
343
inst->work_bufs[i].size = wb_34[i].size;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
347
inst->work_bufs[i].size = wb[i].size;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
355
handler = inst->vpu_inst.ctx->dev->fw_handler;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
356
inst->work_bufs[i].va =
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
358
inst->work_bufs[i].dma_addr = 0;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
360
ret = mtk_vcodec_mem_alloc(inst->ctx,
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
361
&inst->work_bufs[i]);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
363
mtk_venc_err(inst->ctx, "cannot allocate buf %d", i);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
376
handler = inst->vpu_inst.ctx->dev->fw_handler;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
379
memcpy(inst->work_bufs[i].va, tmp_va, wb_size);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
383
wb_34[i].iova = inst->work_bufs[i].dma_addr;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
385
wb[i].iova = inst->work_bufs[i].dma_addr;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
387
mtk_venc_debug(inst->ctx, "work_buf[%d] va=0x%p iova=%pad size=%zu",
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
388
i, inst->work_bufs[i].va,
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
389
&inst->work_bufs[i].dma_addr,
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
390
inst->work_bufs[i].size);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
394
inst->pps_buf.size = 128;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
395
ret = mtk_vcodec_mem_alloc(inst->ctx, &inst->pps_buf);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
397
mtk_venc_err(inst->ctx, "cannot allocate pps_buf");
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
404
h264_enc_free_work_buf(inst);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
409
static unsigned int h264_enc_wait_venc_done(struct venc_h264_inst *inst)
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
412
struct mtk_vcodec_enc_ctx *ctx = (struct mtk_vcodec_enc_ctx *)inst->ctx;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
438
static int h264_encode_sps(struct venc_h264_inst *inst,
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
445
ret = vpu_enc_encode(&inst->vpu_inst, H264_BS_MODE_SPS, NULL, bs_buf, NULL);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
449
irq_status = h264_enc_wait_venc_done(inst);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
451
mtk_venc_err(inst->ctx, "expect irq status %d", MTK_VENC_IRQ_STATUS_SPS);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
455
*bs_size = h264_read_reg(inst, VENC_PIC_BITSTREAM_BYTE_CNT);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
456
mtk_venc_debug(inst->ctx, "bs size %d <-", *bs_size);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
461
static int h264_encode_pps(struct venc_h264_inst *inst,
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
468
ret = vpu_enc_encode(&inst->vpu_inst, H264_BS_MODE_PPS, NULL, bs_buf, NULL);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
472
irq_status = h264_enc_wait_venc_done(inst);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
474
mtk_venc_err(inst->ctx, "expect irq status %d", MTK_VENC_IRQ_STATUS_PPS);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
478
*bs_size = h264_read_reg(inst, VENC_PIC_BITSTREAM_BYTE_CNT);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
479
mtk_venc_debug(inst->ctx, "bs size %d <-", *bs_size);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
484
static int h264_encode_header(struct venc_h264_inst *inst,
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
492
ret = h264_encode_sps(inst, bs_buf, &bs_size_sps);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
496
ret = h264_encode_pps(inst, &inst->pps_buf, &bs_size_pps);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
500
memcpy(bs_buf->va + bs_size_sps, inst->pps_buf.va, bs_size_pps);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
506
static int h264_encode_frame(struct venc_h264_inst *inst,
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
516
struct mtk_vcodec_enc_ctx *ctx = inst->ctx;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
518
mtk_venc_debug(ctx, "frm_cnt = %d\n", inst->frm_cnt);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
521
gop_size = inst->vsi_34->config.gop_size;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
522
intra_period = inst->vsi_34->config.intra_period;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
524
gop_size = inst->vsi->config.gop_size;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
525
intra_period = inst->vsi->config.intra_period;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
527
frame_info.frm_count = inst->frm_cnt;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
528
frame_info.skip_frm_count = inst->skip_frm_cnt;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
529
frame_info.frm_type = h264_frame_type(inst->frm_cnt, gop_size,
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
535
ret = vpu_enc_encode(&inst->vpu_inst, H264_BS_MODE_FRAME,
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
544
if (inst->vpu_inst.state == VEN_IPI_MSG_ENC_STATE_SKIP) {
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
545
*bs_size = inst->vpu_inst.bs_size;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
547
inst->work_bufs[VENC_H264_VPU_WORK_BUF_SKIP_FRAME].va,
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
549
++inst->frm_cnt;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
550
++inst->skip_frm_cnt;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
554
irq_status = h264_enc_wait_venc_done(inst);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
560
*bs_size = h264_read_reg(inst, VENC_PIC_BITSTREAM_BYTE_CNT);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
562
++inst->frm_cnt;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
564
inst->frm_cnt, *bs_size, inst->vpu_inst.is_key_frm);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
569
static void h264_encode_filler(struct venc_h264_inst *inst, void *buf,
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
575
mtk_venc_err(inst->ctx, "filler size too small %d", size);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
589
struct venc_h264_inst *inst;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
591
inst = kzalloc_obj(*inst);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
592
if (!inst)
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
595
inst->ctx = ctx;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
596
inst->vpu_inst.ctx = ctx;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
598
inst->vpu_inst.id = SCP_IPI_VENC_H264;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
600
inst->vpu_inst.id = IPI_VENC_H264;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
602
inst->hw_base = mtk_vcodec_get_reg_addr(inst->ctx->dev->reg_base, VENC_SYS);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
604
ret = vpu_enc_init(&inst->vpu_inst);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
607
inst->vsi_34 = (struct venc_h264_vsi_34 *)inst->vpu_inst.vsi;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
609
inst->vsi = (struct venc_h264_vsi *)inst->vpu_inst.vsi;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
612
kfree(inst);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
614
ctx->drv_handle = inst;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
626
struct venc_h264_inst *inst = (struct venc_h264_inst *)handle;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
627
struct mtk_vcodec_enc_ctx *ctx = inst->ctx;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
637
ret = h264_encode_header(inst, bs_buf, &bs_size_hdr);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
655
if (!inst->prepend_hdr) {
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
656
ret = h264_encode_frame(inst, frm_buf, bs_buf,
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
660
result->is_key_frm = inst->vpu_inst.is_key_frm;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
666
ret = h264_encode_header(inst, bs_buf, &bs_size_hdr);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
676
h264_encode_filler(inst, bs_buf->va + hdr_sz,
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
684
ret = h264_encode_frame(inst, frm_buf, &tmp_bs_buf,
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
694
inst->prepend_hdr = 0;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
695
result->is_key_frm = inst->vpu_inst.is_key_frm;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
713
static void h264_enc_set_vsi_configs(struct venc_h264_inst *inst,
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
716
inst->vsi->config.input_fourcc = enc_prm->input_yuv_fmt;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
717
inst->vsi->config.bitrate = enc_prm->bitrate;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
718
inst->vsi->config.pic_w = enc_prm->width;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
719
inst->vsi->config.pic_h = enc_prm->height;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
720
inst->vsi->config.buf_w = enc_prm->buf_width;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
721
inst->vsi->config.buf_h = enc_prm->buf_height;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
722
inst->vsi->config.gop_size = enc_prm->gop_size;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
723
inst->vsi->config.framerate = enc_prm->frm_rate;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
724
inst->vsi->config.intra_period = enc_prm->intra_period;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
725
inst->vsi->config.profile =
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
726
h264_get_profile(inst, enc_prm->h264_profile);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
727
inst->vsi->config.level =
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
728
h264_get_level(inst, enc_prm->h264_level);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
729
inst->vsi->config.wfd = 0;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
732
static void h264_enc_set_vsi_34_configs(struct venc_h264_inst *inst,
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
735
inst->vsi_34->config.input_fourcc = enc_prm->input_yuv_fmt;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
736
inst->vsi_34->config.bitrate = enc_prm->bitrate;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
737
inst->vsi_34->config.pic_w = enc_prm->width;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
738
inst->vsi_34->config.pic_h = enc_prm->height;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
739
inst->vsi_34->config.buf_w = enc_prm->buf_width;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
740
inst->vsi_34->config.buf_h = enc_prm->buf_height;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
741
inst->vsi_34->config.gop_size = enc_prm->gop_size;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
742
inst->vsi_34->config.framerate = enc_prm->frm_rate;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
743
inst->vsi_34->config.intra_period = enc_prm->intra_period;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
744
inst->vsi_34->config.profile =
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
745
h264_get_profile(inst, enc_prm->h264_profile);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
746
inst->vsi_34->config.level =
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
747
h264_get_level(inst, enc_prm->h264_level);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
748
inst->vsi_34->config.wfd = 0;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
756
struct venc_h264_inst *inst = (struct venc_h264_inst *)handle;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
757
struct mtk_vcodec_enc_ctx *ctx = inst->ctx;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
765
h264_enc_set_vsi_34_configs(inst, enc_prm);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
767
h264_enc_set_vsi_configs(inst, enc_prm);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
768
ret = vpu_enc_set_param(&inst->vpu_inst, type, enc_prm);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
771
if (inst->work_buf_allocated) {
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
772
h264_enc_free_work_buf(inst);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
773
inst->work_buf_allocated = false;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
775
ret = h264_enc_alloc_work_buf(inst, is_34bit);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
778
inst->work_buf_allocated = true;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
782
inst->prepend_hdr = 1;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
788
inst->frm_cnt = 0;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
789
inst->skip_frm_cnt = 0;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
792
ret = vpu_enc_set_param(&inst->vpu_inst, type, enc_prm);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
802
struct venc_h264_inst *inst = (struct venc_h264_inst *)handle;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
804
ret = vpu_enc_deinit(&inst->vpu_inst);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
806
if (inst->work_buf_allocated)
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
807
h264_enc_free_work_buf(inst);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
809
kfree(inst);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
134
static inline u32 vp8_enc_read_reg(struct venc_vp8_inst *inst, u32 addr)
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
136
return readl(inst->hw_base + addr);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
139
static void vp8_enc_free_work_buf(struct venc_vp8_inst *inst)
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
145
if (inst->work_bufs[i].size == 0)
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
147
mtk_vcodec_mem_free(inst->ctx, &inst->work_bufs[i]);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
151
static int vp8_enc_alloc_work_buf(struct venc_vp8_inst *inst)
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
155
struct venc_vp8_vpu_buf *wb = inst->vsi->work_bufs;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
170
inst->work_bufs[i].size = wb[i].size;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
171
ret = mtk_vcodec_mem_alloc(inst->ctx, &inst->work_bufs[i]);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
173
mtk_venc_err(inst->ctx, "cannot alloc work_bufs[%d]", i);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
187
handler = inst->vpu_inst.ctx->dev->fw_handler;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
190
memcpy(inst->work_bufs[i].va, tmp_va, wb[i].size);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
192
wb[i].iova = inst->work_bufs[i].dma_addr;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
194
mtk_venc_debug(inst->ctx, "work_bufs[%d] va=0x%p,iova=%pad,size=%zu",
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
195
i, inst->work_bufs[i].va,
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
196
&inst->work_bufs[i].dma_addr,
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
197
inst->work_bufs[i].size);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
203
vp8_enc_free_work_buf(inst);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
208
static unsigned int vp8_enc_wait_venc_done(struct venc_vp8_inst *inst)
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
211
struct mtk_vcodec_enc_ctx *ctx = (struct mtk_vcodec_enc_ctx *)inst->ctx;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
225
static int vp8_enc_compose_one_frame(struct venc_vp8_inst *inst,
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
236
bs_frm_size = vp8_enc_read_reg(inst, VENC_BITSTREAM_FRAME_SIZE);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
237
bs_hdr_len = vp8_enc_read_reg(inst, VENC_BITSTREAM_HEADER_LEN);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
240
not_key = !inst->vpu_inst.is_key_frm;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
252
ac_tag[6] = inst->vsi->config.pic_w;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
253
ac_tag[7] = inst->vsi->config.pic_w >> 8;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
254
ac_tag[8] = inst->vsi->config.pic_h;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
255
ac_tag[9] = inst->vsi->config.pic_h >> 8;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
261
mtk_venc_err(inst->ctx, "bitstream buf size is too small(%zu)", bs_buf->size);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
275
inst->work_bufs[VENC_VP8_VPU_WORK_BUF_BS_HEADER].va,
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
283
static int vp8_enc_encode_frame(struct venc_vp8_inst *inst,
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
291
mtk_venc_debug(inst->ctx, "->frm_cnt=%d", inst->frm_cnt);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
293
ret = vpu_enc_encode(&inst->vpu_inst, 0, frm_buf, bs_buf, NULL);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
297
irq_status = vp8_enc_wait_venc_done(inst);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
299
mtk_venc_err(inst->ctx, "irq_status=%d failed", irq_status);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
303
if (vp8_enc_compose_one_frame(inst, bs_buf, bs_size)) {
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
304
mtk_venc_err(inst->ctx, "vp8_enc_compose_one_frame failed");
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
308
inst->frm_cnt++;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
309
mtk_venc_debug(inst->ctx, "<-size=%d key_frm=%d", *bs_size, inst->vpu_inst.is_key_frm);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
317
struct venc_vp8_inst *inst;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
319
inst = kzalloc_obj(*inst);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
320
if (!inst)
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
323
inst->ctx = ctx;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
324
inst->vpu_inst.ctx = ctx;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
325
inst->vpu_inst.id = IPI_VENC_VP8;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
326
inst->hw_base = mtk_vcodec_get_reg_addr(inst->ctx->dev->reg_base, VENC_LT_SYS);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
328
ret = vpu_enc_init(&inst->vpu_inst);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
330
inst->vsi = (struct venc_vp8_vsi *)inst->vpu_inst.vsi;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
333
kfree(inst);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
335
ctx->drv_handle = inst;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
347
struct venc_vp8_inst *inst = (struct venc_vp8_inst *)handle;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
348
struct mtk_vcodec_enc_ctx *ctx = inst->ctx;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
354
ret = vp8_enc_encode_frame(inst, frm_buf, bs_buf,
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
358
result->is_key_frm = inst->vpu_inst.is_key_frm;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
378
struct venc_vp8_inst *inst = (struct venc_vp8_inst *)handle;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
380
mtk_venc_debug(inst->ctx, "->type=%d", type);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
384
inst->vsi->config.input_fourcc = enc_prm->input_yuv_fmt;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
385
inst->vsi->config.bitrate = enc_prm->bitrate;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
386
inst->vsi->config.pic_w = enc_prm->width;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
387
inst->vsi->config.pic_h = enc_prm->height;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
388
inst->vsi->config.buf_w = enc_prm->buf_width;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
389
inst->vsi->config.buf_h = enc_prm->buf_height;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
390
inst->vsi->config.gop_size = enc_prm->gop_size;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
391
inst->vsi->config.framerate = enc_prm->frm_rate;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
392
inst->vsi->config.ts_mode = inst->ts_mode;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
393
ret = vpu_enc_set_param(&inst->vpu_inst, type, enc_prm);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
396
if (inst->work_buf_allocated) {
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
397
vp8_enc_free_work_buf(inst);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
398
inst->work_buf_allocated = false;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
400
ret = vp8_enc_alloc_work_buf(inst);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
403
inst->work_buf_allocated = true;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
410
inst->ts_mode = 1;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
411
mtk_venc_debug(inst->ctx, "set ts_mode");
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
415
ret = vpu_enc_set_param(&inst->vpu_inst, type, enc_prm);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
425
struct venc_vp8_inst *inst = (struct venc_vp8_inst *)handle;
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
427
ret = vpu_enc_deinit(&inst->vpu_inst);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
429
if (inst->work_buf_allocated)
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
430
vp8_enc_free_work_buf(inst);
drivers/media/platform/mediatek/vcodec/encoder/venc/venc_vp8_if.c
432
kfree(inst);
drivers/media/platform/qcom/iris/iris_buffer.c
123
static u32 iris_yuv_buffer_size_p010(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_buffer.c
128
if (inst->domain == DECODER)
drivers/media/platform/qcom/iris/iris_buffer.c
129
f = inst->fmt_dst;
drivers/media/platform/qcom/iris/iris_buffer.c
131
f = inst->fmt_src;
drivers/media/platform/qcom/iris/iris_buffer.c
231
static u32 iris_yuv_buffer_size_qc08c(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_buffer.c
238
if (inst->domain == DECODER)
drivers/media/platform/qcom/iris/iris_buffer.c
239
f = inst->fmt_dst;
drivers/media/platform/qcom/iris/iris_buffer.c
241
f = inst->fmt_src;
drivers/media/platform/qcom/iris/iris_buffer.c
357
static u32 iris_yuv_buffer_size_qc10c(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_buffer.c
364
if (inst->domain == DECODER)
drivers/media/platform/qcom/iris/iris_buffer.c
365
f = inst->fmt_dst;
drivers/media/platform/qcom/iris/iris_buffer.c
367
f = inst->fmt_src;
drivers/media/platform/qcom/iris/iris_buffer.c
393
static u32 iris_dec_bitstream_buffer_size(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_buffer.c
395
struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
drivers/media/platform/qcom/iris/iris_buffer.c
400
num_mbs = iris_get_mbpf(inst);
drivers/media/platform/qcom/iris/iris_buffer.c
405
if (inst->codec == V4L2_PIX_FMT_VP9)
drivers/media/platform/qcom/iris/iris_buffer.c
418
static u32 iris_enc_bitstream_buffer_size(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_buffer.c
424
f = inst->fmt_dst;
drivers/media/platform/qcom/iris/iris_buffer.c
426
bitrate_mode = inst->fw_caps[BITRATE_MODE].value;
drivers/media/platform/qcom/iris/iris_buffer.c
427
frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value;
drivers/media/platform/qcom/iris/iris_buffer.c
447
int iris_get_buffer_size(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_buffer.c
450
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_buffer.c
453
return iris_dec_bitstream_buffer_size(inst);
drivers/media/platform/qcom/iris/iris_buffer.c
455
if (inst->fmt_dst->fmt.pix_mp.pixelformat == V4L2_PIX_FMT_QC08C)
drivers/media/platform/qcom/iris/iris_buffer.c
456
return iris_yuv_buffer_size_qc08c(inst);
drivers/media/platform/qcom/iris/iris_buffer.c
457
else if (inst->fmt_dst->fmt.pix_mp.pixelformat == V4L2_PIX_FMT_QC10C)
drivers/media/platform/qcom/iris/iris_buffer.c
458
return iris_yuv_buffer_size_qc10c(inst);
drivers/media/platform/qcom/iris/iris_buffer.c
459
else if (inst->fmt_dst->fmt.pix_mp.pixelformat == V4L2_PIX_FMT_P010)
drivers/media/platform/qcom/iris/iris_buffer.c
460
return iris_yuv_buffer_size_p010(inst);
drivers/media/platform/qcom/iris/iris_buffer.c
462
return iris_yuv_buffer_size_nv12(inst);
drivers/media/platform/qcom/iris/iris_buffer.c
464
if (iris_fmt_is_10bit(inst->fmt_dst->fmt.pix_mp.pixelformat))
drivers/media/platform/qcom/iris/iris_buffer.c
465
return iris_yuv_buffer_size_qc10c(inst);
drivers/media/platform/qcom/iris/iris_buffer.c
467
return iris_yuv_buffer_size_qc08c(inst);
drivers/media/platform/qcom/iris/iris_buffer.c
474
if (inst->fmt_src->fmt.pix_mp.pixelformat == V4L2_PIX_FMT_QC08C)
drivers/media/platform/qcom/iris/iris_buffer.c
475
return iris_yuv_buffer_size_qc08c(inst);
drivers/media/platform/qcom/iris/iris_buffer.c
477
return iris_yuv_buffer_size_nv12(inst);
drivers/media/platform/qcom/iris/iris_buffer.c
479
return iris_enc_bitstream_buffer_size(inst);
drivers/media/platform/qcom/iris/iris_buffer.c
486
static void iris_fill_internal_buf_info(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_buffer.c
489
struct iris_buffers *buffers = &inst->buffers[buffer_type];
drivers/media/platform/qcom/iris/iris_buffer.c
491
buffers->size = inst->core->iris_firmware_desc->get_vpu_buffer_size(inst, buffer_type);
drivers/media/platform/qcom/iris/iris_buffer.c
492
buffers->min_count = iris_vpu_buf_count(inst, buffer_type);
drivers/media/platform/qcom/iris/iris_buffer.c
495
void iris_get_internal_buffers(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_buffer.c
497
const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data;
drivers/media/platform/qcom/iris/iris_buffer.c
501
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_buffer.c
506
iris_fill_internal_buf_info(inst, internal_buf_type[i]);
drivers/media/platform/qcom/iris/iris_buffer.c
511
iris_fill_internal_buf_info(inst, internal_buf_type[i]);
drivers/media/platform/qcom/iris/iris_buffer.c
518
iris_fill_internal_buf_info(inst, internal_buf_type[i]);
drivers/media/platform/qcom/iris/iris_buffer.c
523
iris_fill_internal_buf_info(inst, internal_buf_type[i]);
drivers/media/platform/qcom/iris/iris_buffer.c
528
static int iris_create_internal_buffer(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_buffer.c
531
struct iris_buffers *buffers = &inst->buffers[buffer_type];
drivers/media/platform/qcom/iris/iris_buffer.c
532
struct iris_core *core = inst->core;
drivers/media/platform/qcom/iris/iris_buffer.c
560
int iris_create_internal_buffers(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_buffer.c
562
const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data;
drivers/media/platform/qcom/iris/iris_buffer.c
568
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_buffer.c
587
buffers = &inst->buffers[internal_buf_type[i]];
drivers/media/platform/qcom/iris/iris_buffer.c
589
ret = iris_create_internal_buffer(inst, internal_buf_type[i], j);
drivers/media/platform/qcom/iris/iris_buffer.c
598
int iris_queue_buffer(struct iris_inst *inst, struct iris_buffer *buf)
drivers/media/platform/qcom/iris/iris_buffer.c
600
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_buffer.c
603
ret = hfi_ops->session_queue_buf(inst, buf);
drivers/media/platform/qcom/iris/iris_buffer.c
613
int iris_queue_internal_deferred_buffers(struct iris_inst *inst, enum iris_buffer_type buffer_type)
drivers/media/platform/qcom/iris/iris_buffer.c
619
buffers = &inst->buffers[buffer_type];
drivers/media/platform/qcom/iris/iris_buffer.c
627
ret = iris_queue_buffer(inst, buffer);
drivers/media/platform/qcom/iris/iris_buffer.c
636
int iris_queue_internal_buffers(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_buffer.c
638
const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data;
drivers/media/platform/qcom/iris/iris_buffer.c
645
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_buffer.c
66
static u32 iris_yuv_buffer_size_nv12(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_buffer.c
664
buffers = &inst->buffers[internal_buf_type[i]];
drivers/media/platform/qcom/iris/iris_buffer.c
670
if (buffer->type == BUF_DPB && inst->state != IRIS_INST_STREAMING) {
drivers/media/platform/qcom/iris/iris_buffer.c
674
ret = iris_queue_buffer(inst, buffer);
drivers/media/platform/qcom/iris/iris_buffer.c
683
int iris_destroy_internal_buffer(struct iris_inst *inst, struct iris_buffer *buffer)
drivers/media/platform/qcom/iris/iris_buffer.c
685
struct iris_core *core = inst->core;
drivers/media/platform/qcom/iris/iris_buffer.c
695
static int iris_destroy_internal_buffers(struct iris_inst *inst, u32 plane, bool force)
drivers/media/platform/qcom/iris/iris_buffer.c
697
const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data;
drivers/media/platform/qcom/iris/iris_buffer.c
704
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_buffer.c
71
if (inst->domain == DECODER)
drivers/media/platform/qcom/iris/iris_buffer.c
72
f = inst->fmt_dst;
drivers/media/platform/qcom/iris/iris_buffer.c
723
buffers = &inst->buffers[internal_buf_type[i]];
drivers/media/platform/qcom/iris/iris_buffer.c
733
ret = iris_destroy_internal_buffer(inst, buf);
drivers/media/platform/qcom/iris/iris_buffer.c
74
f = inst->fmt_src;
drivers/media/platform/qcom/iris/iris_buffer.c
740
if (inst->domain == DECODER)
drivers/media/platform/qcom/iris/iris_buffer.c
741
buffers = &inst->buffers[BUF_PERSIST];
drivers/media/platform/qcom/iris/iris_buffer.c
743
buffers = &inst->buffers[BUF_ARP];
drivers/media/platform/qcom/iris/iris_buffer.c
746
ret = iris_destroy_internal_buffer(inst, buf);
drivers/media/platform/qcom/iris/iris_buffer.c
755
int iris_destroy_all_internal_buffers(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_buffer.c
757
return iris_destroy_internal_buffers(inst, plane, true);
drivers/media/platform/qcom/iris/iris_buffer.c
760
int iris_destroy_dequeued_internal_buffers(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_buffer.c
762
return iris_destroy_internal_buffers(inst, plane, false);
drivers/media/platform/qcom/iris/iris_buffer.c
765
static int iris_release_internal_buffers(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_buffer.c
768
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_buffer.c
769
struct iris_buffers *buffers = &inst->buffers[buffer_type];
drivers/media/platform/qcom/iris/iris_buffer.c
779
ret = hfi_ops->session_release_buf(inst, buffer);
drivers/media/platform/qcom/iris/iris_buffer.c
789
static int iris_release_input_internal_buffers(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_buffer.c
791
const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data;
drivers/media/platform/qcom/iris/iris_buffer.c
796
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_buffer.c
805
ret = iris_release_internal_buffers(inst, internal_buf_type[i]);
drivers/media/platform/qcom/iris/iris_buffer.c
813
int iris_alloc_and_queue_persist_bufs(struct iris_inst *inst, enum iris_buffer_type buffer_type)
drivers/media/platform/qcom/iris/iris_buffer.c
815
struct iris_buffers *buffers = &inst->buffers[buffer_type];
drivers/media/platform/qcom/iris/iris_buffer.c
823
iris_fill_internal_buf_info(inst, buffer_type);
drivers/media/platform/qcom/iris/iris_buffer.c
826
ret = iris_create_internal_buffer(inst, buffer_type, i);
drivers/media/platform/qcom/iris/iris_buffer.c
836
ret = iris_queue_buffer(inst, buffer);
drivers/media/platform/qcom/iris/iris_buffer.c
844
int iris_alloc_and_queue_input_int_bufs(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_buffer.c
848
iris_get_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_buffer.c
850
ret = iris_release_input_internal_buffers(inst);
drivers/media/platform/qcom/iris/iris_buffer.c
854
ret = iris_create_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_buffer.c
858
return iris_queue_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_buffer.c
861
int iris_queue_deferred_buffers(struct iris_inst *inst, enum iris_buffer_type buf_type)
drivers/media/platform/qcom/iris/iris_buffer.c
863
struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
drivers/media/platform/qcom/iris/iris_buffer.c
868
iris_scale_power(inst);
drivers/media/platform/qcom/iris/iris_buffer.c
875
ret = iris_queue_buffer(inst, buf);
drivers/media/platform/qcom/iris/iris_buffer.c
884
ret = iris_queue_buffer(inst, buf);
drivers/media/platform/qcom/iris/iris_buffer.c
893
void iris_vb2_queue_error(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_buffer.c
895
struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
drivers/media/platform/qcom/iris/iris_buffer.c
905
iris_helper_find_buf(struct iris_inst *inst, u32 type, u32 idx)
drivers/media/platform/qcom/iris/iris_buffer.c
907
struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
drivers/media/platform/qcom/iris/iris_buffer.c
915
static void iris_get_ts_metadata(struct iris_inst *inst, u64 timestamp_ns,
drivers/media/platform/qcom/iris/iris_buffer.c
921
for (i = 0; i < ARRAY_SIZE(inst->tss); ++i) {
drivers/media/platform/qcom/iris/iris_buffer.c
922
if (inst->tss[i].ts_ns != timestamp_ns)
drivers/media/platform/qcom/iris/iris_buffer.c
926
vbuf->flags |= inst->tss[i].flags;
drivers/media/platform/qcom/iris/iris_buffer.c
927
vbuf->timecode = inst->tss[i].tc;
drivers/media/platform/qcom/iris/iris_buffer.c
932
vbuf->flags |= inst->tss[inst->metadata_idx].flags;
drivers/media/platform/qcom/iris/iris_buffer.c
933
vbuf->timecode = inst->tss[inst->metadata_idx].tc;
drivers/media/platform/qcom/iris/iris_buffer.c
936
int iris_vb2_buffer_done(struct iris_inst *inst, struct iris_buffer *buf)
drivers/media/platform/qcom/iris/iris_buffer.c
938
struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
drivers/media/platform/qcom/iris/iris_buffer.c
954
vbuf = iris_helper_find_buf(inst, type, buf->index);
drivers/media/platform/qcom/iris/iris_buffer.c
972
vbuf->sequence = inst->sequence_cap++;
drivers/media/platform/qcom/iris/iris_buffer.c
973
iris_get_ts_metadata(inst, buf->timestamp, vbuf);
drivers/media/platform/qcom/iris/iris_buffer.c
975
vbuf->sequence = inst->sequence_out++;
drivers/media/platform/qcom/iris/iris_buffer.c
982
v4l2_event_queue_fh(&inst->fh, &ev);
drivers/media/platform/qcom/iris/iris_buffer.c
985
inst->last_buffer_dequeued = true;
drivers/media/platform/qcom/iris/iris_buffer.h
110
int iris_get_buffer_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
drivers/media/platform/qcom/iris/iris_buffer.h
111
void iris_get_internal_buffers(struct iris_inst *inst, u32 plane);
drivers/media/platform/qcom/iris/iris_buffer.h
112
int iris_create_internal_buffers(struct iris_inst *inst, u32 plane);
drivers/media/platform/qcom/iris/iris_buffer.h
113
int iris_queue_internal_buffers(struct iris_inst *inst, u32 plane);
drivers/media/platform/qcom/iris/iris_buffer.h
114
int iris_queue_internal_deferred_buffers(struct iris_inst *inst, enum iris_buffer_type buffer_type);
drivers/media/platform/qcom/iris/iris_buffer.h
115
int iris_destroy_internal_buffer(struct iris_inst *inst, struct iris_buffer *buffer);
drivers/media/platform/qcom/iris/iris_buffer.h
116
int iris_destroy_all_internal_buffers(struct iris_inst *inst, u32 plane);
drivers/media/platform/qcom/iris/iris_buffer.h
117
int iris_destroy_dequeued_internal_buffers(struct iris_inst *inst, u32 plane);
drivers/media/platform/qcom/iris/iris_buffer.h
118
int iris_alloc_and_queue_persist_bufs(struct iris_inst *inst, enum iris_buffer_type buf_type);
drivers/media/platform/qcom/iris/iris_buffer.h
119
int iris_alloc_and_queue_input_int_bufs(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_buffer.h
120
int iris_queue_buffer(struct iris_inst *inst, struct iris_buffer *buf);
drivers/media/platform/qcom/iris/iris_buffer.h
121
int iris_queue_deferred_buffers(struct iris_inst *inst, enum iris_buffer_type buf_type);
drivers/media/platform/qcom/iris/iris_buffer.h
122
int iris_vb2_buffer_done(struct iris_inst *inst, struct iris_buffer *buf);
drivers/media/platform/qcom/iris/iris_buffer.h
123
void iris_vb2_queue_error(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_buffer.h
89
struct iris_inst *inst;
drivers/media/platform/qcom/iris/iris_common.c
100
first_ipsc = inst->sub_state & IRIS_INST_SUB_FIRST_IPSC;
drivers/media/platform/qcom/iris/iris_common.c
102
drain_active = inst->sub_state & IRIS_INST_SUB_DRAIN &&
drivers/media/platform/qcom/iris/iris_common.c
103
inst->sub_state & IRIS_INST_SUB_DRAIN_LAST;
drivers/media/platform/qcom/iris/iris_common.c
105
drc_active = inst->sub_state & IRIS_INST_SUB_DRC &&
drivers/media/platform/qcom/iris/iris_common.c
106
inst->sub_state & IRIS_INST_SUB_DRC_LAST;
drivers/media/platform/qcom/iris/iris_common.c
115
ret = iris_alloc_and_queue_input_int_bufs(inst);
drivers/media/platform/qcom/iris/iris_common.c
118
ret = iris_set_stage(inst, STAGE);
drivers/media/platform/qcom/iris/iris_common.c
121
ret = iris_set_pipe(inst, PIPE);
drivers/media/platform/qcom/iris/iris_common.c
126
if (inst->state == IRIS_INST_INPUT_STREAMING &&
drivers/media/platform/qcom/iris/iris_common.c
127
inst->sub_state & IRIS_INST_SUB_INPUT_PAUSE) {
drivers/media/platform/qcom/iris/iris_common.c
129
ret = hfi_ops->session_resume_drc(inst,
drivers/media/platform/qcom/iris/iris_common.c
132
ret = hfi_ops->session_resume_drain(inst,
drivers/media/platform/qcom/iris/iris_common.c
139
if (inst->sub_state & IRIS_INST_SUB_FIRST_IPSC)
drivers/media/platform/qcom/iris/iris_common.c
142
ret = hfi_ops->session_start(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
drivers/media/platform/qcom/iris/iris_common.c
146
if (inst->sub_state & IRIS_INST_SUB_OUTPUT_PAUSE)
drivers/media/platform/qcom/iris/iris_common.c
149
ret = iris_inst_state_change_streamon(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
drivers/media/platform/qcom/iris/iris_common.c
153
inst->last_buffer_dequeued = false;
drivers/media/platform/qcom/iris/iris_common.c
155
return iris_inst_change_sub_state(inst, clear_sub_state, 0);
drivers/media/platform/qcom/iris/iris_common.c
158
static void iris_flush_deferred_buffers(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_common.c
161
struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
drivers/media/platform/qcom/iris/iris_common.c
172
iris_vb2_buffer_done(inst, buf);
drivers/media/platform/qcom/iris/iris_common.c
183
iris_vb2_buffer_done(inst, buf);
drivers/media/platform/qcom/iris/iris_common.c
190
static void iris_kill_session(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_common.c
192
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_common.c
194
if (!inst->session_id)
drivers/media/platform/qcom/iris/iris_common.c
197
hfi_ops->session_close(inst);
drivers/media/platform/qcom/iris/iris_common.c
198
iris_inst_change_state(inst, IRIS_INST_ERROR);
drivers/media/platform/qcom/iris/iris_common.c
201
int iris_session_streamoff(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_common.c
203
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_common.c
218
ret = hfi_ops->session_stop(inst, plane);
drivers/media/platform/qcom/iris/iris_common.c
222
ret = iris_inst_state_change_streamoff(inst, plane);
drivers/media/platform/qcom/iris/iris_common.c
226
iris_flush_deferred_buffers(inst, buffer_type);
drivers/media/platform/qcom/iris/iris_common.c
231
iris_kill_session(inst);
drivers/media/platform/qcom/iris/iris_common.c
232
iris_flush_deferred_buffers(inst, buffer_type);
drivers/media/platform/qcom/iris/iris_common.c
30
void iris_set_ts_metadata(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf)
drivers/media/platform/qcom/iris/iris_common.c
36
if (inst->metadata_idx >= ARRAY_SIZE(inst->tss))
drivers/media/platform/qcom/iris/iris_common.c
37
inst->metadata_idx = 0;
drivers/media/platform/qcom/iris/iris_common.c
41
inst->tss[inst->metadata_idx].flags = vbuf->flags & mask;
drivers/media/platform/qcom/iris/iris_common.c
42
inst->tss[inst->metadata_idx].tc = vbuf->timecode;
drivers/media/platform/qcom/iris/iris_common.c
43
inst->tss[inst->metadata_idx].ts_us = ts_us;
drivers/media/platform/qcom/iris/iris_common.c
44
inst->tss[inst->metadata_idx].ts_ns = vb->timestamp;
drivers/media/platform/qcom/iris/iris_common.c
46
inst->metadata_idx++;
drivers/media/platform/qcom/iris/iris_common.c
49
int iris_process_streamon_input(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_common.c
51
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_common.c
55
iris_scale_power(inst);
drivers/media/platform/qcom/iris/iris_common.c
57
ret = hfi_ops->session_start(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_common.c
61
if (inst->sub_state & IRIS_INST_SUB_INPUT_PAUSE) {
drivers/media/platform/qcom/iris/iris_common.c
62
ret = iris_inst_change_sub_state(inst, IRIS_INST_SUB_INPUT_PAUSE, 0);
drivers/media/platform/qcom/iris/iris_common.c
67
if (inst->domain == DECODER &&
drivers/media/platform/qcom/iris/iris_common.c
68
(inst->sub_state & IRIS_INST_SUB_DRC ||
drivers/media/platform/qcom/iris/iris_common.c
69
inst->sub_state & IRIS_INST_SUB_DRAIN ||
drivers/media/platform/qcom/iris/iris_common.c
70
inst->sub_state & IRIS_INST_SUB_FIRST_IPSC)) {
drivers/media/platform/qcom/iris/iris_common.c
71
if (!(inst->sub_state & IRIS_INST_SUB_INPUT_PAUSE)) {
drivers/media/platform/qcom/iris/iris_common.c
73
ret = hfi_ops->session_pause(inst,
drivers/media/platform/qcom/iris/iris_common.c
82
ret = iris_inst_state_change_streamon(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_common.c
86
inst->last_buffer_dequeued = false;
drivers/media/platform/qcom/iris/iris_common.c
88
return iris_inst_change_sub_state(inst, 0, set_sub_state);
drivers/media/platform/qcom/iris/iris_common.c
91
int iris_process_streamon_output(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_common.c
93
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_common.c
98
iris_scale_power(inst);
drivers/media/platform/qcom/iris/iris_common.h
13
void iris_set_ts_metadata(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf);
drivers/media/platform/qcom/iris/iris_common.h
14
int iris_process_streamon_input(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_common.h
15
int iris_process_streamon_output(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_common.h
16
int iris_session_streamoff(struct iris_inst *inst, u32 plane);
drivers/media/platform/qcom/iris/iris_ctrls.c
1003
if (inst->codec == V4L2_PIX_FMT_H264) {
drivers/media/platform/qcom/iris/iris_ctrls.c
1004
if (inst->fw_caps[I_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET)
drivers/media/platform/qcom/iris/iris_ctrls.c
1006
if (inst->fw_caps[P_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET)
drivers/media/platform/qcom/iris/iris_ctrls.c
1008
if (inst->fw_caps[B_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET)
drivers/media/platform/qcom/iris/iris_ctrls.c
1011
if (inst->fw_caps[I_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)
drivers/media/platform/qcom/iris/iris_ctrls.c
1013
if (inst->fw_caps[P_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)
drivers/media/platform/qcom/iris/iris_ctrls.c
1015
if (inst->fw_caps[B_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)
drivers/media/platform/qcom/iris/iris_ctrls.c
1024
if (inst->codec == V4L2_PIX_FMT_H264) {
drivers/media/platform/qcom/iris/iris_ctrls.c
1025
i_frame_qp = inst->fw_caps[I_FRAME_QP_H264].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1026
p_frame_qp = inst->fw_caps[P_FRAME_QP_H264].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1027
b_frame_qp = inst->fw_caps[B_FRAME_QP_H264].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1029
i_frame_qp = inst->fw_caps[I_FRAME_QP_HEVC].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1030
p_frame_qp = inst->fw_caps[P_FRAME_QP_HEVC].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1031
b_frame_qp = inst->fw_caps[B_FRAME_QP_HEVC].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1037
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
1039
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
1044
int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
1046
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
1048
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
1050
if (inst->codec == V4L2_PIX_FMT_HEVC) {
drivers/media/platform/qcom/iris/iris_ctrls.c
1051
range.min_qp.qp_packed = inst->fw_caps[MIN_FRAME_QP_HEVC].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1052
range.max_qp.qp_packed = inst->fw_caps[MAX_FRAME_QP_HEVC].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1054
range.min_qp.qp_packed = inst->fw_caps[MIN_FRAME_QP_H264].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1055
range.max_qp.qp_packed = inst->fw_caps[MAX_FRAME_QP_H264].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1058
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
1060
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
1065
int iris_set_rotation(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
1067
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
1068
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
1071
switch (inst->fw_caps[cap_id].value) {
drivers/media/platform/qcom/iris/iris_ctrls.c
1088
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
1090
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
1095
int iris_set_flip(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
1097
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
1098
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
1101
if (inst->fw_caps[HFLIP].value)
drivers/media/platform/qcom/iris/iris_ctrls.c
1104
if (inst->fw_caps[VFLIP].value)
drivers/media/platform/qcom/iris/iris_ctrls.c
1107
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
1109
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
1114
int iris_set_ir_period_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
1116
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
1117
struct v4l2_pix_format_mplane *fmt = &inst->fmt_dst->fmt.pix_mp;
drivers/media/platform/qcom/iris/iris_ctrls.c
1118
u32 codec_align = inst->codec == V4L2_PIX_FMT_HEVC ? 32 : 16;
drivers/media/platform/qcom/iris/iris_ctrls.c
1119
u32 ir_period = inst->fw_caps[cap_id].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1120
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
1126
if (inst->fw_caps[IR_TYPE].value ==
drivers/media/platform/qcom/iris/iris_ctrls.c
1129
} else if (inst->fw_caps[IR_TYPE].value ==
drivers/media/platform/qcom/iris/iris_ctrls.c
1144
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
1146
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
1151
int iris_set_ir_period_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
1153
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
1154
struct vb2_queue *q = v4l2_m2m_get_dst_vq(inst->m2m_ctx);
drivers/media/platform/qcom/iris/iris_ctrls.c
1155
u32 ir_period = inst->fw_caps[cap_id].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1158
if (inst->fw_caps[IR_TYPE].value ==
drivers/media/platform/qcom/iris/iris_ctrls.c
1163
} else if (inst->fw_caps[IR_TYPE].value ==
drivers/media/platform/qcom/iris/iris_ctrls.c
1170
return hfi_ops->session_set_property(inst, ir_type,
drivers/media/platform/qcom/iris/iris_ctrls.c
1172
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
1177
int iris_set_ltr_count_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
1179
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
1180
u32 ltr_count = inst->fw_caps[cap_id].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1181
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
1191
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
1193
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
1198
int iris_set_use_ltr(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
1200
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
1201
struct vb2_queue *sq = v4l2_m2m_get_src_vq(inst->m2m_ctx);
drivers/media/platform/qcom/iris/iris_ctrls.c
1202
struct vb2_queue *dq = v4l2_m2m_get_dst_vq(inst->m2m_ctx);
drivers/media/platform/qcom/iris/iris_ctrls.c
1203
u32 ltr_count = inst->fw_caps[LTR_COUNT].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1204
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
1213
ltr_use.ref_ltr = inst->fw_caps[cap_id].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1217
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
1219
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
1224
int iris_set_mark_ltr(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
1226
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
1227
struct vb2_queue *sq = v4l2_m2m_get_src_vq(inst->m2m_ctx);
drivers/media/platform/qcom/iris/iris_ctrls.c
1228
struct vb2_queue *dq = v4l2_m2m_get_dst_vq(inst->m2m_ctx);
drivers/media/platform/qcom/iris/iris_ctrls.c
1229
u32 ltr_count = inst->fw_caps[LTR_COUNT].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1230
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
1239
ltr_mark.mark_frame = inst->fw_caps[cap_id].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1241
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
1243
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
1248
int iris_set_ltr_count_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
1250
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
1251
u32 ltr_count = inst->fw_caps[cap_id].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1252
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
1257
if (inst->hfi_rc_type == HFI_RC_CBR_VFR ||
drivers/media/platform/qcom/iris/iris_ctrls.c
1258
inst->hfi_rc_type == HFI_RC_CBR_CFR ||
drivers/media/platform/qcom/iris/iris_ctrls.c
1259
inst->hfi_rc_type == HFI_RC_OFF) {
drivers/media/platform/qcom/iris/iris_ctrls.c
1260
inst->fw_caps[LTR_COUNT].value = 0;
drivers/media/platform/qcom/iris/iris_ctrls.c
1264
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
1266
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
1271
int iris_set_use_and_mark_ltr(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
1273
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
1274
struct vb2_queue *sq = v4l2_m2m_get_src_vq(inst->m2m_ctx);
drivers/media/platform/qcom/iris/iris_ctrls.c
1275
struct vb2_queue *dq = v4l2_m2m_get_dst_vq(inst->m2m_ctx);
drivers/media/platform/qcom/iris/iris_ctrls.c
1276
u32 ltr_count = inst->fw_caps[LTR_COUNT].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1277
u32 hfi_val = inst->fw_caps[cap_id].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1278
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
1286
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
1288
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
1293
int iris_set_intra_period(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
1295
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
1296
u32 gop_size = inst->fw_caps[GOP_SIZE].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1297
u32 b_frame = inst->fw_caps[B_FRAME].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1298
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
1312
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
1314
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
1319
int iris_set_layer_type(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
1321
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
1322
u32 layer_enable = inst->fw_caps[LAYER_ENABLE].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1323
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
1326
if (inst->hfi_rc_type == HFI_RATE_CONTROL_CQ ||
drivers/media/platform/qcom/iris/iris_ctrls.c
1327
inst->hfi_rc_type == HFI_RATE_CONTROL_OFF)
drivers/media/platform/qcom/iris/iris_ctrls.c
1330
if (inst->codec == V4L2_PIX_FMT_H264) {
drivers/media/platform/qcom/iris/iris_ctrls.c
1331
if (!layer_enable || !inst->fw_caps[LAYER_COUNT_H264].value)
drivers/media/platform/qcom/iris/iris_ctrls.c
1334
if (inst->fw_caps[LAYER_TYPE_H264].value ==
drivers/media/platform/qcom/iris/iris_ctrls.c
1336
if (inst->hfi_rc_type == HFI_RC_VBR_CFR)
drivers/media/platform/qcom/iris/iris_ctrls.c
1340
} else if (inst->fw_caps[LAYER_TYPE_H264].value ==
drivers/media/platform/qcom/iris/iris_ctrls.c
1342
if (inst->hfi_rc_type == HFI_RC_VBR_CFR)
drivers/media/platform/qcom/iris/iris_ctrls.c
1349
} else if (inst->codec == V4L2_PIX_FMT_HEVC) {
drivers/media/platform/qcom/iris/iris_ctrls.c
1350
if (!inst->fw_caps[LAYER_COUNT_HEVC].value)
drivers/media/platform/qcom/iris/iris_ctrls.c
1353
if (inst->fw_caps[LAYER_TYPE_HEVC].value ==
drivers/media/platform/qcom/iris/iris_ctrls.c
1356
} else if (inst->fw_caps[LAYER_TYPE_HEVC].value ==
drivers/media/platform/qcom/iris/iris_ctrls.c
1358
if (inst->hfi_rc_type == HFI_RC_VBR_CFR)
drivers/media/platform/qcom/iris/iris_ctrls.c
1369
inst->hfi_layer_type = layer_type;
drivers/media/platform/qcom/iris/iris_ctrls.c
1371
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
1373
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
1378
int iris_set_layer_count_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
1380
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
1381
struct vb2_queue *sq = v4l2_m2m_get_src_vq(inst->m2m_ctx);
drivers/media/platform/qcom/iris/iris_ctrls.c
1382
struct vb2_queue *dq = v4l2_m2m_get_dst_vq(inst->m2m_ctx);
drivers/media/platform/qcom/iris/iris_ctrls.c
1383
u32 layer_enable = inst->fw_caps[LAYER_ENABLE].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1384
u32 layer_count = inst->fw_caps[cap_id].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1390
inst->hfi_layer_count = layer_count;
drivers/media/platform/qcom/iris/iris_ctrls.c
1394
ret = hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
1396
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
1403
hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
1404
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
1406
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
1411
int iris_set_layer_count_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
1413
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
1414
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
1415
u32 layer_type = inst->hfi_layer_type;
drivers/media/platform/qcom/iris/iris_ctrls.c
1418
layer_count = (inst->codec == V4L2_PIX_FMT_H264) ?
drivers/media/platform/qcom/iris/iris_ctrls.c
1419
inst->fw_caps[LAYER_COUNT_H264].value :
drivers/media/platform/qcom/iris/iris_ctrls.c
1420
inst->fw_caps[LAYER_COUNT_HEVC].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1430
if (inst->codec == V4L2_PIX_FMT_H264) {
drivers/media/platform/qcom/iris/iris_ctrls.c
1433
if (inst->hfi_rc_type == HFI_RC_VBR_CFR)
drivers/media/platform/qcom/iris/iris_ctrls.c
1446
inst->hfi_layer_count = layer_count;
drivers/media/platform/qcom/iris/iris_ctrls.c
1448
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
1450
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
1455
int iris_set_layer_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
1457
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
1458
struct vb2_queue *sq = v4l2_m2m_get_src_vq(inst->m2m_ctx);
drivers/media/platform/qcom/iris/iris_ctrls.c
1459
struct vb2_queue *dq = v4l2_m2m_get_dst_vq(inst->m2m_ctx);
drivers/media/platform/qcom/iris/iris_ctrls.c
1460
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
1461
u32 bitrate = inst->fw_caps[cap_id].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
1464
if (inst->fw_caps[BITRATE].flags & CAP_FLAG_CLIENT_SET)
drivers/media/platform/qcom/iris/iris_ctrls.c
1467
if (!(inst->fw_caps[cap_id].flags & CAP_FLAG_CLIENT_SET))
drivers/media/platform/qcom/iris/iris_ctrls.c
1473
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
1475
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
1480
int iris_set_properties(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_ctrls.c
1482
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
1487
ret = hfi_ops->session_set_config_params(inst, plane);
drivers/media/platform/qcom/iris/iris_ctrls.c
1492
cap = &inst->fw_caps[i];
drivers/media/platform/qcom/iris/iris_ctrls.c
1497
cap->set(inst, i);
drivers/media/platform/qcom/iris/iris_ctrls.c
307
struct iris_inst *inst = container_of(ctrl->handler, struct iris_inst, ctrl_handler);
drivers/media/platform/qcom/iris/iris_ctrls.c
312
cap = &inst->fw_caps[0];
drivers/media/platform/qcom/iris/iris_ctrls.c
317
q = v4l2_m2m_get_src_vq(inst->m2m_ctx);
drivers/media/platform/qcom/iris/iris_ctrls.c
319
(!(inst->fw_caps[cap_id].flags & CAP_FLAG_DYNAMIC_ALLOWED)))
drivers/media/platform/qcom/iris/iris_ctrls.c
324
inst->fw_caps[cap_id].value = ctrl->val;
drivers/media/platform/qcom/iris/iris_ctrls.c
328
cap[cap_id].set(inst, cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.c
338
int iris_ctrls_init(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_ctrls.c
340
struct platform_inst_fw_cap *cap = &inst->fw_caps[0];
drivers/media/platform/qcom/iris/iris_ctrls.c
355
ret = v4l2_ctrl_handler_init(&inst->ctrl_handler, num_ctrls + 1);
drivers/media/platform/qcom/iris/iris_ctrls.c
372
ctrl = v4l2_ctrl_new_std_menu(&inst->ctrl_handler,
drivers/media/platform/qcom/iris/iris_ctrls.c
379
ctrl = v4l2_ctrl_new_std(&inst->ctrl_handler,
drivers/media/platform/qcom/iris/iris_ctrls.c
395
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_ctrls.c
396
v4l2_ctrl_new_std(&inst->ctrl_handler, NULL,
drivers/media/platform/qcom/iris/iris_ctrls.c
399
v4l2_ctrl_new_std(&inst->ctrl_handler, NULL,
drivers/media/platform/qcom/iris/iris_ctrls.c
403
ret = inst->ctrl_handler.error;
drivers/media/platform/qcom/iris/iris_ctrls.c
409
v4l2_ctrl_handler_free(&inst->ctrl_handler);
drivers/media/platform/qcom/iris/iris_ctrls.c
466
static u32 iris_get_port_info(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_ctrls.c
469
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_ctrls.c
470
if (inst->fw_caps[cap_id].flags & CAP_FLAG_INPUT_PORT)
drivers/media/platform/qcom/iris/iris_ctrls.c
472
else if (inst->fw_caps[cap_id].flags & CAP_FLAG_OUTPUT_PORT)
drivers/media/platform/qcom/iris/iris_ctrls.c
475
if (inst->fw_caps[cap_id].flags & CAP_FLAG_INPUT_PORT)
drivers/media/platform/qcom/iris/iris_ctrls.c
477
else if (inst->fw_caps[cap_id].flags & CAP_FLAG_OUTPUT_PORT)
drivers/media/platform/qcom/iris/iris_ctrls.c
484
int iris_set_u32_enum(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
486
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
487
u32 hfi_value = inst->fw_caps[cap_id].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
488
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
490
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
492
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
497
int iris_set_u32(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
499
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
500
u32 hfi_value = inst->fw_caps[cap_id].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
501
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
503
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
505
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
510
int iris_set_stage(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
512
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
513
struct v4l2_format *inp_f = inst->fmt_src;
drivers/media/platform/qcom/iris/iris_ctrls.c
514
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
519
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_ctrls.c
524
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
526
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
531
int iris_set_pipe(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
533
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
534
u32 work_route = inst->fw_caps[PIPE].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
535
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
537
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
539
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
544
int iris_set_profile(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
546
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
549
if (inst->codec == V4L2_PIX_FMT_H264) {
drivers/media/platform/qcom/iris/iris_ctrls.c
550
hfi_id = inst->fw_caps[PROFILE_H264].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
551
hfi_value = inst->fw_caps[PROFILE_H264].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
553
hfi_id = inst->fw_caps[PROFILE_HEVC].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
554
hfi_value = inst->fw_caps[PROFILE_HEVC].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
557
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
559
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
564
int iris_set_level(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
566
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
569
if (inst->codec == V4L2_PIX_FMT_H264) {
drivers/media/platform/qcom/iris/iris_ctrls.c
570
hfi_id = inst->fw_caps[LEVEL_H264].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
571
hfi_value = inst->fw_caps[LEVEL_H264].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
573
hfi_id = inst->fw_caps[LEVEL_HEVC].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
574
hfi_value = inst->fw_caps[LEVEL_HEVC].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
577
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
579
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
584
int iris_set_profile_level_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
586
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
587
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
590
if (inst->codec == V4L2_PIX_FMT_H264) {
drivers/media/platform/qcom/iris/iris_ctrls.c
591
pl.profile = inst->fw_caps[PROFILE_H264].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
592
pl.level = inst->fw_caps[LEVEL_H264].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
594
pl.profile = inst->fw_caps[PROFILE_HEVC].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
595
pl.level = inst->fw_caps[LEVEL_HEVC].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
598
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
600
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
605
int iris_set_header_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
607
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
608
u32 header_mode = inst->fw_caps[cap_id].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
609
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
617
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
619
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
624
int iris_set_header_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
626
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
627
u32 prepend_sps_pps = inst->fw_caps[PREPEND_SPSPPS_TO_IDR].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
628
u32 header_mode = inst->fw_caps[cap_id].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
629
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
639
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
641
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
646
int iris_set_bitrate_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
648
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
649
u32 entropy_mode = inst->fw_caps[ENTROPY_MODE].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
650
u32 bitrate = inst->fw_caps[cap_id].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
651
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
655
if (!(inst->fw_caps[cap_id].flags & CAP_FLAG_CLIENT_SET) && cap_id != BITRATE)
drivers/media/platform/qcom/iris/iris_ctrls.c
658
if (inst->codec == V4L2_PIX_FMT_HEVC) {
drivers/media/platform/qcom/iris/iris_ctrls.c
693
if (hfi_val.layer_id > 0 && !inst->fw_caps[LAYER_ENABLE].value)
drivers/media/platform/qcom/iris/iris_ctrls.c
696
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
698
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
703
int iris_set_bitrate_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
705
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
706
u32 entropy_mode = inst->fw_caps[ENTROPY_MODE].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
707
u32 bitrate = inst->fw_caps[cap_id].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
708
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
711
if (inst->codec == V4L2_PIX_FMT_HEVC)
drivers/media/platform/qcom/iris/iris_ctrls.c
721
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
723
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
728
int iris_set_peak_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
730
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
731
u32 rc_mode = inst->fw_caps[BITRATE_MODE].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
732
u32 peak_bitrate = inst->fw_caps[cap_id].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
733
u32 bitrate = inst->fw_caps[BITRATE].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
734
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
739
if (inst->fw_caps[cap_id].flags & CAP_FLAG_CLIENT_SET) {
drivers/media/platform/qcom/iris/iris_ctrls.c
746
inst->fw_caps[cap_id].value = peak_bitrate;
drivers/media/platform/qcom/iris/iris_ctrls.c
748
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
750
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
755
int iris_set_bitrate_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
757
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
758
u32 bitrate_mode = inst->fw_caps[BITRATE_MODE].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
759
u32 frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
760
u32 frame_skip = inst->fw_caps[FRAME_SKIP_MODE].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
761
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
773
inst->hfi_rc_type = rc_mode;
drivers/media/platform/qcom/iris/iris_ctrls.c
775
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
777
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
782
int iris_set_bitrate_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
784
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
785
u32 bitrate_mode = inst->fw_caps[BITRATE_MODE].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
786
u32 frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
787
u32 frame_skip = inst->fw_caps[FRAME_SKIP_MODE].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
788
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
800
inst->hfi_rc_type = rc_mode;
drivers/media/platform/qcom/iris/iris_ctrls.c
802
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
804
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
809
int iris_set_entropy_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
811
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
812
u32 entropy_mode = inst->fw_caps[cap_id].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
813
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
816
if (inst->codec != V4L2_PIX_FMT_H264)
drivers/media/platform/qcom/iris/iris_ctrls.c
822
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
824
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
829
int iris_set_entropy_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
831
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
832
u32 entropy_mode = inst->fw_caps[cap_id].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
833
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
836
if (inst->codec != V4L2_PIX_FMT_H264)
drivers/media/platform/qcom/iris/iris_ctrls.c
839
profile = inst->fw_caps[PROFILE_H264].value;
drivers/media/platform/qcom/iris/iris_ctrls.c
845
inst->fw_caps[cap_id].value = entropy_mode;
drivers/media/platform/qcom/iris/iris_ctrls.c
847
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
849
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
854
int iris_set_min_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
856
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
860
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
863
if (inst->codec == V4L2_PIX_FMT_H264) {
drivers/media/platform/qcom/iris/iris_ctrls.c
864
if (inst->fw_caps[MIN_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET)
drivers/media/platform/qcom/iris/iris_ctrls.c
867
(inst->fw_caps[I_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET))
drivers/media/platform/qcom/iris/iris_ctrls.c
870
(inst->fw_caps[P_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET))
drivers/media/platform/qcom/iris/iris_ctrls.c
873
(inst->fw_caps[B_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET))
drivers/media/platform/qcom/iris/iris_ctrls.c
876
if (inst->fw_caps[MIN_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)
drivers/media/platform/qcom/iris/iris_ctrls.c
879
(inst->fw_caps[I_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET))
drivers/media/platform/qcom/iris/iris_ctrls.c
882
(inst->fw_caps[P_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET))
drivers/media/platform/qcom/iris/iris_ctrls.c
885
(inst->fw_caps[B_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET))
drivers/media/platform/qcom/iris/iris_ctrls.c
893
if (inst->codec == V4L2_PIX_FMT_H264) {
drivers/media/platform/qcom/iris/iris_ctrls.c
894
i_frame_qp = max(inst->fw_caps[I_FRAME_MIN_QP_H264].value,
drivers/media/platform/qcom/iris/iris_ctrls.c
895
inst->fw_caps[MIN_FRAME_QP_H264].value);
drivers/media/platform/qcom/iris/iris_ctrls.c
896
p_frame_qp = max(inst->fw_caps[P_FRAME_MIN_QP_H264].value,
drivers/media/platform/qcom/iris/iris_ctrls.c
897
inst->fw_caps[MIN_FRAME_QP_H264].value);
drivers/media/platform/qcom/iris/iris_ctrls.c
898
b_frame_qp = max(inst->fw_caps[B_FRAME_MIN_QP_H264].value,
drivers/media/platform/qcom/iris/iris_ctrls.c
899
inst->fw_caps[MIN_FRAME_QP_H264].value);
drivers/media/platform/qcom/iris/iris_ctrls.c
901
i_frame_qp = max(inst->fw_caps[I_FRAME_MIN_QP_HEVC].value,
drivers/media/platform/qcom/iris/iris_ctrls.c
902
inst->fw_caps[MIN_FRAME_QP_HEVC].value);
drivers/media/platform/qcom/iris/iris_ctrls.c
903
p_frame_qp = max(inst->fw_caps[P_FRAME_MIN_QP_HEVC].value,
drivers/media/platform/qcom/iris/iris_ctrls.c
904
inst->fw_caps[MIN_FRAME_QP_HEVC].value);
drivers/media/platform/qcom/iris/iris_ctrls.c
905
b_frame_qp = max(inst->fw_caps[B_FRAME_MIN_QP_HEVC].value,
drivers/media/platform/qcom/iris/iris_ctrls.c
906
inst->fw_caps[MIN_FRAME_QP_HEVC].value);
drivers/media/platform/qcom/iris/iris_ctrls.c
911
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
913
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
918
int iris_set_max_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
920
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
924
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
927
if (inst->codec == V4L2_PIX_FMT_H264) {
drivers/media/platform/qcom/iris/iris_ctrls.c
928
if (inst->fw_caps[MAX_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET)
drivers/media/platform/qcom/iris/iris_ctrls.c
931
(inst->fw_caps[I_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET))
drivers/media/platform/qcom/iris/iris_ctrls.c
934
(inst->fw_caps[P_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET))
drivers/media/platform/qcom/iris/iris_ctrls.c
937
(inst->fw_caps[B_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET))
drivers/media/platform/qcom/iris/iris_ctrls.c
940
if (inst->fw_caps[MAX_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)
drivers/media/platform/qcom/iris/iris_ctrls.c
943
(inst->fw_caps[I_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET))
drivers/media/platform/qcom/iris/iris_ctrls.c
946
(inst->fw_caps[P_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET))
drivers/media/platform/qcom/iris/iris_ctrls.c
949
(inst->fw_caps[B_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET))
drivers/media/platform/qcom/iris/iris_ctrls.c
957
if (inst->codec == V4L2_PIX_FMT_H264) {
drivers/media/platform/qcom/iris/iris_ctrls.c
958
i_frame_qp = min(inst->fw_caps[I_FRAME_MAX_QP_H264].value,
drivers/media/platform/qcom/iris/iris_ctrls.c
959
inst->fw_caps[MAX_FRAME_QP_H264].value);
drivers/media/platform/qcom/iris/iris_ctrls.c
960
p_frame_qp = min(inst->fw_caps[P_FRAME_MAX_QP_H264].value,
drivers/media/platform/qcom/iris/iris_ctrls.c
961
inst->fw_caps[MAX_FRAME_QP_H264].value);
drivers/media/platform/qcom/iris/iris_ctrls.c
962
b_frame_qp = min(inst->fw_caps[B_FRAME_MAX_QP_H264].value,
drivers/media/platform/qcom/iris/iris_ctrls.c
963
inst->fw_caps[MAX_FRAME_QP_H264].value);
drivers/media/platform/qcom/iris/iris_ctrls.c
965
i_frame_qp = min(inst->fw_caps[I_FRAME_MAX_QP_HEVC].value,
drivers/media/platform/qcom/iris/iris_ctrls.c
966
inst->fw_caps[MAX_FRAME_QP_HEVC].value);
drivers/media/platform/qcom/iris/iris_ctrls.c
967
p_frame_qp = min(inst->fw_caps[P_FRAME_MAX_QP_HEVC].value,
drivers/media/platform/qcom/iris/iris_ctrls.c
968
inst->fw_caps[MAX_FRAME_QP_HEVC].value);
drivers/media/platform/qcom/iris/iris_ctrls.c
969
b_frame_qp = min(inst->fw_caps[B_FRAME_MAX_QP_HEVC].value,
drivers/media/platform/qcom/iris/iris_ctrls.c
970
inst->fw_caps[MAX_FRAME_QP_HEVC].value);
drivers/media/platform/qcom/iris/iris_ctrls.c
976
return hfi_ops->session_set_property(inst, hfi_id,
drivers/media/platform/qcom/iris/iris_ctrls.c
978
iris_get_port_info(inst, cap_id),
drivers/media/platform/qcom/iris/iris_ctrls.c
983
int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
drivers/media/platform/qcom/iris/iris_ctrls.c
985
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_ctrls.c
988
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
drivers/media/platform/qcom/iris/iris_ctrls.c
992
q = v4l2_m2m_get_dst_vq(inst->m2m_ctx);
drivers/media/platform/qcom/iris/iris_ctrls.c
994
if (inst->hfi_rc_type != HFI_RC_OFF)
drivers/media/platform/qcom/iris/iris_ctrls.c
998
if (inst->hfi_rc_type == HFI_RC_OFF) {
drivers/media/platform/qcom/iris/iris_ctrls.h
14
int iris_ctrls_init(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_ctrls.h
16
int iris_set_u32_enum(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
17
int iris_set_stage(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
18
int iris_set_pipe(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
19
int iris_set_u32(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
20
int iris_set_profile(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
21
int iris_set_level(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
22
int iris_set_profile_level_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
23
int iris_set_header_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
24
int iris_set_header_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
25
int iris_set_bitrate_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
26
int iris_set_bitrate_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
27
int iris_set_peak_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
28
int iris_set_bitrate_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
29
int iris_set_bitrate_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
30
int iris_set_entropy_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
31
int iris_set_entropy_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
32
int iris_set_min_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
33
int iris_set_max_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
34
int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
35
int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
36
int iris_set_rotation(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
37
int iris_set_flip(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
38
int iris_set_ir_period_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
39
int iris_set_ir_period_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
40
int iris_set_ltr_count_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
41
int iris_set_ltr_count_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
42
int iris_set_use_ltr(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
43
int iris_set_mark_ltr(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
44
int iris_set_use_and_mark_ltr(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
45
int iris_set_intra_period(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
46
int iris_set_layer_type(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
47
int iris_set_layer_count_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
48
int iris_set_layer_count_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
49
int iris_set_layer_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
drivers/media/platform/qcom/iris/iris_ctrls.h
50
int iris_set_properties(struct iris_inst *inst, u32 plane);
drivers/media/platform/qcom/iris/iris_hfi_common.h
105
int (*handle)(struct iris_inst *inst, u32 plane);
drivers/media/platform/qcom/iris/iris_hfi_common.h
120
int (*session_set_config_params)(struct iris_inst *inst, u32 plane);
drivers/media/platform/qcom/iris/iris_hfi_common.h
121
int (*session_set_property)(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_hfi_common.h
124
int (*session_open)(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_hfi_common.h
125
int (*session_start)(struct iris_inst *inst, u32 plane);
drivers/media/platform/qcom/iris/iris_hfi_common.h
126
int (*session_queue_buf)(struct iris_inst *inst, struct iris_buffer *buffer);
drivers/media/platform/qcom/iris/iris_hfi_common.h
127
int (*session_release_buf)(struct iris_inst *inst, struct iris_buffer *buffer);
drivers/media/platform/qcom/iris/iris_hfi_common.h
128
int (*session_pause)(struct iris_inst *inst, u32 plane);
drivers/media/platform/qcom/iris/iris_hfi_common.h
129
int (*session_resume_drc)(struct iris_inst *inst, u32 plane);
drivers/media/platform/qcom/iris/iris_hfi_common.h
130
int (*session_stop)(struct iris_inst *inst, u32 plane);
drivers/media/platform/qcom/iris/iris_hfi_common.h
131
int (*session_drain)(struct iris_inst *inst, u32 plane);
drivers/media/platform/qcom/iris/iris_hfi_common.h
132
int (*session_resume_drain)(struct iris_inst *inst, u32 plane);
drivers/media/platform/qcom/iris/iris_hfi_common.h
133
int (*session_close)(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
1002
static int iris_hfi_gen1_set_frame_rate(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
101
switch (inst->codec) {
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
1011
frate.framerate = inst->frame_rate << 16;
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
1013
return hfi_gen1_set_property(inst, ptype, &frate, sizeof(frate));
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
1016
static int iris_hfi_gen1_set_stride(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
1024
ALIGN(inst->fmt_src->fmt.pix_mp.width, 128);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
1026
ALIGN(inst->fmt_src->fmt.pix_mp.height, 32);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
1028
ALIGN(inst->fmt_src->fmt.pix_mp.width, 128);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
1030
(ALIGN(inst->fmt_src->fmt.pix_mp.height, 32)) / 2;
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
1032
return hfi_gen1_set_property(inst, ptype, &plane_actual_info, sizeof(plane_actual_info));
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
1035
static int iris_hfi_gen1_session_set_config_params(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
1039
struct iris_core *core = inst->core;
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
1089
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
1109
ret = handler[j].handle(inst, plane);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
115
packet.shdr.session_id = inst->session_id;
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
117
if (inst->domain == DECODER)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
124
reinit_completion(&inst->completion);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
126
ret = iris_hfi_queue_cmd_write(inst->core, &packet, packet.shdr.hdr.size);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
130
return iris_wait_for_session_response(inst, false);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
133
static void iris_hfi_gen1_packet_session_cmd(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
139
packet->shdr.session_id = inst->session_id;
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
142
static int iris_hfi_gen1_session_close(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
146
iris_hfi_gen1_packet_session_cmd(inst, &packet, HFI_CMD_SYS_SESSION_END);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
148
return iris_hfi_queue_cmd_write(inst->core, &packet, packet.shdr.hdr.size);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
151
static int iris_hfi_gen1_session_start(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
153
struct iris_core *core = inst->core;
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
160
if (inst->sub_state & IRIS_INST_SUB_LOAD_RESOURCES)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
163
reinit_completion(&inst->completion);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
164
iris_hfi_gen1_packet_session_cmd(inst, &packet, HFI_CMD_SESSION_LOAD_RESOURCES);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
170
ret = iris_wait_for_session_response(inst, false);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
174
reinit_completion(&inst->completion);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
175
iris_hfi_gen1_packet_session_cmd(inst, &packet, HFI_CMD_SESSION_START);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
181
ret = iris_wait_for_session_response(inst, false);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
185
return iris_inst_change_sub_state(inst, 0, IRIS_INST_SUB_LOAD_RESOURCES);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
188
static int iris_hfi_gen1_session_stop(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
191
struct iris_core *core = inst->core;
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
196
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
197
if (inst->state == IRIS_INST_STREAMING) {
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
203
reinit_completion(&inst->flush_completion);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
207
flush_pkt.shdr.session_id = inst->session_id;
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
212
inst->flush_responses_pending++;
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
213
ret = iris_wait_for_session_response(inst, true);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
215
} else if (inst->sub_state & IRIS_INST_SUB_LOAD_RESOURCES) {
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
216
reinit_completion(&inst->completion);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
217
iris_hfi_gen1_packet_session_cmd(inst, &pkt, HFI_CMD_SESSION_STOP);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
220
ret = iris_wait_for_session_response(inst, false);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
222
reinit_completion(&inst->completion);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
223
iris_hfi_gen1_packet_session_cmd(inst, &pkt,
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
227
ret = iris_wait_for_session_response(inst, false);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
229
iris_inst_change_sub_state(inst, IRIS_INST_SUB_LOAD_RESOURCES, 0);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
231
iris_helper_buffers_done(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
233
iris_helper_buffers_done(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
237
if (inst->state == IRIS_INST_STREAMING ||
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
238
inst->state == IRIS_INST_INPUT_STREAMING ||
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
239
inst->state == IRIS_INST_ERROR) {
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
240
reinit_completion(&inst->completion);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
241
iris_hfi_gen1_packet_session_cmd(inst, &pkt, HFI_CMD_SESSION_STOP);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
244
ret = iris_wait_for_session_response(inst, false);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
246
reinit_completion(&inst->completion);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
247
iris_hfi_gen1_packet_session_cmd(inst, &pkt,
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
251
ret = iris_wait_for_session_response(inst, false);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
253
iris_inst_change_sub_state(inst, IRIS_INST_SUB_LOAD_RESOURCES, 0);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
256
iris_helper_buffers_done(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
258
iris_helper_buffers_done(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
265
static int iris_hfi_gen1_session_continue(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
269
iris_hfi_gen1_packet_session_cmd(inst, &packet, HFI_CMD_SESSION_CONTINUE);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
271
return iris_hfi_queue_cmd_write(inst->core, &packet, packet.shdr.hdr.size);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
274
static int iris_hfi_gen1_queue_input_buffer(struct iris_inst *inst, struct iris_buffer *buf)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
279
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
282
com_ip_pkt.shdr.session_id = inst->session_id;
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
293
return iris_hfi_queue_cmd_write(inst->core, &com_ip_pkt,
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
299
uncom_ip_pkt.shdr.session_id = inst->session_id;
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
311
return iris_hfi_queue_cmd_write(inst->core, &uncom_ip_pkt,
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
316
static int iris_hfi_gen1_queue_output_buffer(struct iris_inst *inst, struct iris_buffer *buf)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
322
op_pkt.shdr.session_id = inst->session_id;
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
331
if (buf->type == BUF_OUTPUT && iris_split_mode_enabled(inst))
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
336
return iris_hfi_queue_cmd_write(inst->core, &op_pkt, op_pkt.shdr.hdr.size);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
339
static int iris_hfi_gen1_queue_internal_buffer(struct iris_inst *inst, struct iris_buffer *buf)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
352
int_pkt->shdr.session_id = inst->session_id;
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
367
ret = iris_hfi_queue_cmd_write(inst->core, int_pkt, int_pkt->shdr.hdr.size);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
375
static int iris_hfi_gen1_session_queue_buffer(struct iris_inst *inst, struct iris_buffer *buf)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
379
return iris_hfi_gen1_queue_input_buffer(inst, buf);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
382
return iris_hfi_gen1_queue_output_buffer(inst, buf);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
388
return iris_hfi_gen1_queue_internal_buffer(inst, buf);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
394
static int iris_hfi_gen1_session_unset_buffers(struct iris_inst *inst, struct iris_buffer *buf)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
413
pkt->shdr.session_id = inst->session_id;
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
439
ret = iris_hfi_queue_cmd_write(inst->core, pkt, pkt->shdr.hdr.size);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
443
ret = iris_wait_for_session_response(inst, false);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
445
ret = iris_destroy_internal_buffer(inst, buf);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
453
static int iris_hfi_gen1_session_drain(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
455
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
460
ip_pkt.shdr.session_id = inst->session_id;
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
464
return iris_hfi_queue_cmd_write(inst->core, &ip_pkt, ip_pkt.shdr.hdr.size);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
467
if (inst->domain == ENCODER) {
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
472
ip_pkt.shdr.session_id = inst->session_id;
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
476
return iris_hfi_queue_cmd_write(inst->core, &ip_pkt, ip_pkt.shdr.hdr.size);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
484
struct iris_inst *inst, u32 ptype, void *pdata)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
490
packet->shdr.session_id = inst->session_id;
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
751
static int hfi_gen1_set_property(struct iris_inst *inst, u32 packet_type,
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
763
ret = iris_hfi_gen1_packet_session_set_property(pkt, inst, packet_type, payload);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
771
ret = iris_hfi_queue_cmd_write(inst->core, pkt, pkt->shdr.hdr.size);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
779
static int iris_hfi_gen1_session_set_property(struct iris_inst *inst, u32 packet_type,
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
783
return hfi_gen1_set_property(inst, packet_type, payload, payload_size);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
786
static int iris_hfi_gen1_set_resolution(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
792
if (!iris_drc_pending(inst) && !(inst->sub_state & IRIS_INST_SUB_FIRST_IPSC)) {
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
794
fs.width = inst->fmt_src->fmt.pix_mp.width;
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
795
fs.height = inst->fmt_src->fmt.pix_mp.height;
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
797
ret = hfi_gen1_set_property(inst, ptype, &fs, sizeof(fs));
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
801
if (inst->domain == DECODER)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
806
fs.width = inst->fmt_dst->fmt.pix_mp.width;
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
807
fs.height = inst->fmt_dst->fmt.pix_mp.height;
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
809
return hfi_gen1_set_property(inst, ptype, &fs, sizeof(fs));
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
812
static int iris_hfi_gen1_decide_core(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
819
return hfi_gen1_set_property(inst, ptype, &cu, sizeof(cu));
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
822
static int iris_hfi_gen1_set_raw_format(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
829
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
830
pixelformat = inst->fmt_dst->fmt.pix_mp.pixelformat;
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
831
if (iris_split_mode_enabled(inst)) {
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
835
ret = hfi_gen1_set_property(inst, ptype, &fmt, sizeof(fmt));
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
843
ret = hfi_gen1_set_property(inst, ptype, &fmt, sizeof(fmt));
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
849
ret = hfi_gen1_set_property(inst, ptype, &fmt, sizeof(fmt));
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
852
pixelformat = inst->fmt_src->fmt.pix_mp.pixelformat;
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
856
ret = hfi_gen1_set_property(inst, ptype, &fmt, sizeof(fmt));
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
862
static int iris_hfi_gen1_set_format_constraints(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
867
if (inst->fmt_dst->fmt.pix_mp.pixelformat == V4L2_PIX_FMT_QC08C)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
882
return hfi_gen1_set_property(inst, ptype, &pconstraint, sizeof(pconstraint));
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
885
static int iris_hfi_gen1_set_num_bufs(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
895
ret = hfi_gen1_set_property(inst, ptype, &buf_count, sizeof(buf_count));
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
899
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
900
if (iris_split_mode_enabled(inst)) {
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
905
ret = hfi_gen1_set_property(inst, ptype, &buf_count, sizeof(buf_count));
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
910
buf_count.count_actual = iris_vpu_buf_count(inst, BUF_DPB);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
911
buf_count.count_min_host = iris_vpu_buf_count(inst, BUF_DPB);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
913
ret = hfi_gen1_set_property(inst, ptype, &buf_count, sizeof(buf_count));
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
919
ret = hfi_gen1_set_property(inst, ptype, &buf_count, sizeof(buf_count));
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
92
static int iris_hfi_gen1_session_open(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
926
ret = hfi_gen1_set_property(inst, ptype, &buf_count, sizeof(buf_count));
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
932
static int iris_hfi_gen1_set_multistream(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
938
if (iris_split_mode_enabled(inst)) {
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
942
ret = hfi_gen1_set_property(inst, ptype, &multi, sizeof(multi));
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
949
ret = hfi_gen1_set_property(inst, ptype, &multi, sizeof(multi));
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
954
ret = hfi_gen1_set_property(inst, ptype, &multi, sizeof(multi));
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
961
ret = hfi_gen1_set_property(inst, ptype, &multi, sizeof(multi));
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
967
static int iris_hfi_gen1_set_bufsize(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
973
if (iris_split_mode_enabled(inst)) {
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
975
bufsz.size = inst->core->iris_firmware_desc->get_vpu_buffer_size(inst, BUF_DPB);
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
977
ret = hfi_gen1_set_property(inst, ptype, &bufsz, sizeof(bufsz));
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
98
if (inst->state != IRIS_INST_DEINIT)
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
982
bufsz.size = inst->buffers[BUF_OUTPUT].size;
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
984
ret = hfi_gen1_set_property(inst, ptype, &bufsz, sizeof(bufsz));
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
987
bufsz.size = inst->buffers[BUF_OUTPUT].size;
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
989
ret = hfi_gen1_set_property(inst, ptype, &bufsz, sizeof(bufsz));
drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
996
ret = hfi_gen1_set_property(inst, ptype, &bufsz, sizeof(bufsz));
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
112
pixmp_op->plane_fmt[0].sizeimage = iris_get_buffer_size(inst, BUF_OUTPUT);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
147
inst->crop.left = event.input_crop.left;
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
148
inst->crop.top = event.input_crop.top;
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
149
inst->crop.width = event.input_crop.width;
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
15
static void iris_hfi_gen1_read_changed_params(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
150
inst->crop.height = event.input_crop.height;
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
152
inst->crop.left = 0;
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
153
inst->crop.top = 0;
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
154
inst->crop.width = event.width;
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
155
inst->crop.height = event.height;
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
158
inst->fw_min_count = event.buf_count;
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
159
inst->buffers[BUF_OUTPUT].min_count = iris_vpu_buf_count(inst, BUF_OUTPUT);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
160
inst->buffers[BUF_OUTPUT].size = pixmp_op->plane_fmt[0].sizeimage;
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
161
ctrl = v4l2_ctrl_find(&inst->ctrl_handler, V4L2_CID_MIN_BUFFERS_FOR_CAPTURE);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
163
v4l2_ctrl_s_ctrl(ctrl, inst->buffers[BUF_OUTPUT].min_count);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
165
dst_q = v4l2_m2m_get_dst_vq(inst->m2m_ctx);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
166
dst_q->min_reqbufs_allocation = inst->buffers[BUF_OUTPUT].min_count;
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
171
iris_inst_change_state(inst, IRIS_INST_ERROR);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
175
static void iris_hfi_gen1_event_seq_changed(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
18
struct v4l2_pix_format_mplane *pixmp_ip = &inst->fmt_src->fmt.pix_mp;
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
182
ret = iris_inst_sub_state_change_drc(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
19
struct v4l2_pix_format_mplane *pixmp_op = &inst->fmt_dst->fmt.pix_mp;
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
191
iris_inst_change_state(inst, IRIS_INST_ERROR);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
197
iris_inst_change_state(inst, IRIS_INST_ERROR);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
201
iris_hfi_gen1_read_changed_params(inst, pkt);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
203
if (inst->state != IRIS_INST_ERROR && !(inst->sub_state & IRIS_INST_SUB_FIRST_IPSC)) {
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
207
flush_pkt.shdr.session_id = inst->session_id;
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
209
if (!iris_hfi_queue_cmd_write(inst->core, &flush_pkt, flush_pkt.shdr.hdr.size))
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
210
inst->flush_responses_pending++;
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
213
iris_vdec_src_change(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
214
iris_inst_sub_state_change_drc_last(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
239
iris_hfi_gen1_event_session_error(struct iris_inst *inst, struct hfi_msg_event_notify_pkt *pkt)
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
247
dev_dbg(inst->core->dev, "session error: event id:%x, session id:%x\n",
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
256
dev_err(inst->core->dev,
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
260
iris_vb2_queue_error(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
261
iris_inst_change_state(inst, IRIS_INST_ERROR);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
266
static void iris_hfi_gen1_session_event_notify(struct iris_inst *inst, void *packet)
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
272
iris_hfi_gen1_event_session_error(inst, pkt);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
275
iris_hfi_gen1_event_seq_changed(inst, pkt);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
28
struct iris_core *core = inst->core;
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
343
static void iris_hfi_gen1_session_etb_done(struct iris_inst *inst, void *packet)
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
346
struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
367
iris_vb2_queue_error(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
368
iris_inst_change_state(inst, IRIS_INST_ERROR);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
378
iris_vb2_buffer_done(inst, buf);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
384
iris_inst_change_state(inst, IRIS_INST_ERROR);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
385
dev_err(inst->core->dev, "error in etb done\n");
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
388
static void iris_hfi_gen1_session_ftb_done(struct iris_inst *inst, void *packet)
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
392
struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
397
struct iris_core *core = inst->core;
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
409
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
428
reinit_completion(&inst->flush_completion);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
432
flush_pkt.shdr.session_id = inst->session_id;
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
435
inst->flush_responses_pending++;
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
437
iris_inst_sub_state_change_drain_last(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
440
if (iris_split_mode_enabled(inst) && inst->domain == DECODER &&
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
442
buffers = &inst->buffers[BUF_DPB];
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
482
if (inst->domain == DECODER && uncom_pkt->stream_id == 1 &&
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
483
!inst->last_buffer_dequeued) {
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
484
if (iris_drc_pending(inst) || iris_drain_pending(inst)) {
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
486
inst->last_buffer_dequeued = true;
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
488
} else if (inst->domain == ENCODER) {
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
489
if (!inst->last_buffer_dequeued && iris_drain_pending(inst)) {
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
491
inst->last_buffer_dequeued = true;
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
527
iris_vb2_buffer_done(inst, buf);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
532
iris_inst_change_state(inst, IRIS_INST_ERROR);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
602
struct iris_inst *inst;
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
630
inst = iris_get_instance(core, pkt->shdr.session_id);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
631
if (inst) {
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
632
mutex_lock(&inst->lock);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
633
iris_hfi_gen1_session_event_notify(inst, hdr);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
634
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
642
inst = iris_get_instance(core, pkt->shdr.session_id);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
643
if (!inst) {
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
650
mutex_lock(&inst->lock);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
652
iris_hfi_gen1_session_etb_done(inst, hdr);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
654
iris_hfi_gen1_session_ftb_done(inst, hdr);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
660
iris_inst_change_state(inst, IRIS_INST_ERROR);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
663
if (!(--inst->flush_responses_pending))
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
664
complete(&inst->flush_completion);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
666
complete(&inst->completion);
drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
669
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/iris/iris_hfi_gen2.h
14
container_of(ptr, struct iris_inst_hfi_gen2, inst)
drivers/media/platform/qcom/iris/iris_hfi_gen2.h
28
struct iris_inst inst;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1037
ret = iris_hfi_gen2_session_set_property(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1054
static int iris_hfi_gen2_subscribe_property(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1056
struct iris_core *core = inst->core;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1063
if (inst->domain == ENCODER)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1070
switch (inst->codec) {
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1097
return iris_hfi_gen2_session_subscribe_mode(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1105
static int iris_hfi_gen2_session_start(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1107
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1110
ret = iris_hfi_gen2_subscribe_change_param(inst, plane);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1114
ret = iris_hfi_gen2_subscribe_property(inst, plane);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1118
iris_hfi_gen2_packet_session_command(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1122
iris_hfi_gen2_get_port(inst, plane),
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1123
inst->session_id,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1128
return iris_hfi_queue_cmd_write(inst->core, inst_hfi_gen2->packet,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1132
static int iris_hfi_gen2_session_stop(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1134
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
114
static u32 iris_hfi_gen2_get_port_from_buf_type(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1140
reinit_completion(&inst->completion);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1142
iris_hfi_gen2_packet_session_command(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1147
iris_hfi_gen2_get_port(inst, plane),
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1148
inst->session_id,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1153
ret = iris_hfi_queue_cmd_write(inst->core, inst_hfi_gen2->packet,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1158
return iris_wait_for_session_response(inst, false);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1161
static int iris_hfi_gen2_session_pause(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1163
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1165
iris_hfi_gen2_packet_session_command(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1169
iris_hfi_gen2_get_port(inst, plane),
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
117
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1170
inst->session_id,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1175
return iris_hfi_queue_cmd_write(inst->core, inst_hfi_gen2->packet,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1179
static int iris_hfi_gen2_session_resume_drc(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1181
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1184
iris_hfi_gen2_packet_session_command(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1188
iris_hfi_gen2_get_port(inst, plane),
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1189
inst->session_id,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1194
return iris_hfi_queue_cmd_write(inst->core, inst_hfi_gen2->packet,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1198
static int iris_hfi_gen2_session_resume_drain(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1200
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1203
iris_hfi_gen2_packet_session_command(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1207
iris_hfi_gen2_get_port(inst, plane),
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1208
inst->session_id,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1213
return iris_hfi_queue_cmd_write(inst->core, inst_hfi_gen2->packet,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1217
static int iris_hfi_gen2_session_drain(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1219
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1224
iris_hfi_gen2_packet_session_command(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1229
iris_hfi_gen2_get_port(inst, plane),
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1230
inst->session_id,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1235
return iris_hfi_queue_cmd_write(inst->core, inst_hfi_gen2->packet,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1276
static int iris_hfi_gen2_set_num_comv(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1278
u32 num_comv = inst->buffers[BUF_OUTPUT].min_count;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1280
if (inst->fw_min_count)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1281
num_comv = inst->fw_min_count;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1283
return iris_hfi_gen2_session_set_property(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1311
static int iris_hfi_gen2_session_queue_buffer(struct iris_inst *inst, struct iris_buffer *buffer)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1313
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1318
iris_hfi_gen2_get_buffer(inst->domain, buffer, &hfi_buffer);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1320
ret = iris_hfi_gen2_set_num_comv(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1325
port = iris_hfi_gen2_get_port_from_buf_type(inst, buffer->type);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1326
iris_hfi_gen2_packet_session_command(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1330
inst->session_id,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1335
return iris_hfi_queue_cmd_write(inst->core, inst_hfi_gen2->packet,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1339
static int iris_hfi_gen2_session_release_buffer(struct iris_inst *inst, struct iris_buffer *buffer)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1341
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1345
iris_hfi_gen2_get_buffer(inst->domain, buffer, &hfi_buffer);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1347
port = iris_hfi_gen2_get_port_from_buf_type(inst, buffer->type);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1349
iris_hfi_gen2_packet_session_command(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1354
inst->session_id,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1359
return iris_hfi_queue_cmd_write(inst->core, inst_hfi_gen2->packet,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1387
out->inst.hfi_session_ops = &iris_hfi_gen2_session_ops;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
1389
return &out->inst;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
152
static int iris_hfi_gen2_session_set_property(struct iris_inst *inst, u32 packet_type, u32 flag,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
156
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
158
iris_hfi_gen2_packet_session_property(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
166
return iris_hfi_queue_cmd_write(inst->core, inst_hfi_gen2->packet,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
170
static int iris_hfi_gen2_set_raw_resolution(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
172
u32 resolution = inst->enc_raw_width << 16 | inst->enc_raw_height;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
173
u32 port = iris_hfi_gen2_get_port(inst, plane);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
175
return iris_hfi_gen2_session_set_property(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
184
static inline u32 iris_hfi_get_aligned_resolution(struct iris_inst *inst, u32 width, u32 height)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
186
u32 codec_align = inst->codec == V4L2_PIX_FMT_HEVC ? 32 : 16;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
191
static int iris_hfi_gen2_set_bitstream_resolution(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
193
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
194
u32 port = iris_hfi_gen2_get_port(inst, plane);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
199
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
200
width = inst->fmt_src->fmt.pix_mp.width;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
201
height = inst->fmt_src->fmt.pix_mp.height;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
202
resolution = iris_hfi_get_aligned_resolution(inst, width, height);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
206
if (is_rotation_90_or_270(inst)) {
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
207
width = inst->enc_scale_height;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
208
height = inst->enc_scale_width;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
210
width = inst->enc_scale_width;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
211
height = inst->enc_scale_height;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
213
resolution = iris_hfi_get_aligned_resolution(inst, width, height);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
218
return iris_hfi_gen2_session_set_property(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
227
static int iris_hfi_gen2_set_crop_offsets(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
229
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
230
u32 port = iris_hfi_gen2_get_port(inst, plane);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
235
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
237
bottom_offset = (inst->fmt_src->fmt.pix_mp.height - inst->crop.height);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
238
right_offset = (inst->fmt_src->fmt.pix_mp.width - inst->crop.width);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
239
left_offset = inst->crop.left;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
240
top_offset = inst->crop.top;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
242
bottom_offset = (inst->fmt_dst->fmt.pix_mp.height - inst->compose.height);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
243
right_offset = (inst->fmt_dst->fmt.pix_mp.width - inst->compose.width);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
244
left_offset = inst->compose.left;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
245
top_offset = inst->compose.top;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
248
codec_align = inst->codec == V4L2_PIX_FMT_HEVC ? 32 : 16;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
250
bottom_offset = (inst->enc_raw_height - inst->crop.height);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
251
right_offset = (inst->enc_raw_width - inst->crop.width);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
252
left_offset = inst->crop.left;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
253
top_offset = inst->crop.top;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
255
if (is_rotation_90_or_270(inst)) {
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
256
bottom_offset = (ALIGN(inst->enc_scale_width, codec_align) -
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
257
inst->enc_scale_width);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
258
right_offset = (ALIGN(inst->enc_scale_height, codec_align) -
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
259
inst->enc_scale_height);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
261
bottom_offset = (ALIGN(inst->enc_scale_height, codec_align) -
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
262
inst->enc_scale_height);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
263
right_offset = (ALIGN(inst->enc_scale_width, codec_align) -
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
264
inst->enc_scale_width);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
276
return iris_hfi_gen2_session_set_property(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
285
static int iris_hfi_gen2_set_bit_depth(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
287
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
288
u32 port = iris_hfi_gen2_get_port(inst, plane);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
293
return iris_hfi_gen2_session_set_property(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
302
static int iris_hfi_gen2_set_coded_frames(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
304
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
305
u32 port = iris_hfi_gen2_get_port(inst, plane);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
308
if (inst->fw_caps[CODED_FRAMES].value == CODED_FRAMES_PROGRESSIVE)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
312
return iris_hfi_gen2_session_set_property(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
321
static int iris_hfi_gen2_set_min_output_count(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
323
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
324
u32 min_output = inst->buffers[BUF_OUTPUT].min_count;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
325
u32 port = iris_hfi_gen2_get_port(inst, plane);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
329
return iris_hfi_gen2_session_set_property(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
338
static int iris_hfi_gen2_set_picture_order_count(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
340
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
341
u32 port = iris_hfi_gen2_get_port(inst, plane);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
346
return iris_hfi_gen2_session_set_property(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
355
static int iris_hfi_gen2_set_colorspace(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
357
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
358
struct v4l2_pix_format_mplane *pixmp = &inst->fmt_src->fmt.pix_mp;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
364
u32 port = iris_hfi_gen2_get_port(inst, plane);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
389
return iris_hfi_gen2_session_set_property(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
398
static int iris_hfi_gen2_set_profile(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
400
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
401
u32 port = iris_hfi_gen2_get_port(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
404
switch (inst->codec) {
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
406
profile = inst->fw_caps[PROFILE_HEVC].value;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
409
profile = inst->fw_caps[PROFILE_VP9].value;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
412
profile = inst->fw_caps[PROFILE_H264].value;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
415
profile = inst->fw_caps[PROFILE_AV1].value;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
421
return iris_hfi_gen2_session_set_property(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
430
static int iris_hfi_gen2_set_level(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
432
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
433
u32 port = iris_hfi_gen2_get_port(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
436
switch (inst->codec) {
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
438
level = inst->fw_caps[LEVEL_HEVC].value;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
441
level = inst->fw_caps[LEVEL_VP9].value;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
444
level = inst->fw_caps[LEVEL_H264].value;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
447
level = inst->fw_caps[LEVEL_AV1].value;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
453
return iris_hfi_gen2_session_set_property(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
462
static int iris_hfi_gen2_set_opb_enable(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
464
u32 port = iris_hfi_gen2_get_port(inst, plane);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
465
u32 opb_enable = iris_split_mode_enabled(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
467
return iris_hfi_gen2_session_set_property(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
476
static int iris_hfi_gen2_set_colorformat(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
478
u32 port = iris_hfi_gen2_get_port(inst, plane);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
481
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
482
pixelformat = inst->fmt_dst->fmt.pix_mp.pixelformat;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
498
pixelformat = inst->fmt_src->fmt.pix_mp.pixelformat;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
503
return iris_hfi_gen2_session_set_property(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
512
static int iris_hfi_gen2_set_linear_stride_scanline(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
515
u32 port = iris_hfi_gen2_get_port(inst, plane);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
518
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
519
pixelformat = inst->fmt_dst->fmt.pix_mp.pixelformat;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
520
stride_y = inst->fmt_dst->fmt.pix_mp.width;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
521
scanline_y = inst->fmt_dst->fmt.pix_mp.height;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
523
pixelformat = inst->fmt_src->fmt.pix_mp.pixelformat;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
524
stride_y = ALIGN(inst->fmt_src->fmt.pix_mp.width, 128);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
525
scanline_y = ALIGN(inst->fmt_src->fmt.pix_mp.height, 32);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
538
return iris_hfi_gen2_session_set_property(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
547
static int iris_hfi_gen2_set_ubwc_stride_scanline(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
551
u32 port = iris_hfi_gen2_get_port(inst, plane);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
555
if (inst->domain != DECODER ||
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
556
inst->fmt_src->fmt.pix_mp.pixelformat != V4L2_PIX_FMT_AV1)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
559
pixelformat = inst->fmt_dst->fmt.pix_mp.pixelformat;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
560
width = inst->fmt_dst->fmt.pix_mp.width;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
561
height = inst->fmt_dst->fmt.pix_mp.height;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
593
return iris_hfi_gen2_session_set_property(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
602
static int iris_hfi_gen2_set_tier(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
604
u32 port = iris_hfi_gen2_get_port(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
605
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
606
u32 tier = inst->fw_caps[TIER].value;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
608
tier = (inst->codec == V4L2_PIX_FMT_AV1) ? inst->fw_caps[TIER_AV1].value :
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
609
inst->fw_caps[TIER].value;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
612
return iris_hfi_gen2_session_set_property(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
621
static int iris_hfi_gen2_set_frame_rate(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
623
u32 port = iris_hfi_gen2_get_port(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
624
u32 frame_rate = inst->frame_rate << 16;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
626
return iris_hfi_gen2_session_set_property(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
635
static int iris_hfi_gen2_set_film_grain(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
637
u32 port = iris_hfi_gen2_get_port(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
638
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
639
u32 film_grain = inst->fw_caps[FILM_GRAIN].value;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
643
return iris_hfi_gen2_session_set_property(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
652
static int iris_hfi_gen2_set_super_block(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
654
u32 port = iris_hfi_gen2_get_port(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
655
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
656
u32 super_block = inst->fw_caps[SUPER_BLOCK].value;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
660
return iris_hfi_gen2_session_set_property(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
669
static int iris_hfi_gen2_session_set_config_params(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
671
const struct iris_firmware_data *fdata = inst->core->iris_firmware_data;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
698
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
700
if (inst->codec == V4L2_PIX_FMT_H264) {
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
703
} else if (inst->codec == V4L2_PIX_FMT_HEVC) {
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
706
} else if (inst->codec == V4L2_PIX_FMT_VP9) {
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
709
} else if (inst->codec == V4L2_PIX_FMT_AV1) {
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
735
ret = prop_type_handle_arr[j].handle(inst, plane);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
746
static int iris_hfi_gen2_session_set_codec(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
748
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
751
switch (inst->codec) {
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
753
if (inst->domain == ENCODER)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
759
if (inst->domain == ENCODER)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
771
iris_hfi_gen2_packet_session_property(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
779
return iris_hfi_queue_cmd_write(inst->core, inst_hfi_gen2->packet,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
783
static int iris_hfi_gen2_session_set_default_header(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
785
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
788
iris_hfi_gen2_packet_session_property(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
796
return iris_hfi_queue_cmd_write(inst->core, inst_hfi_gen2->packet,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
800
static int iris_hfi_gen2_session_open(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
802
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
805
if (inst->state != IRIS_INST_DEINIT)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
815
iris_hfi_gen2_packet_session_command(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
822
&inst->session_id,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
825
ret = iris_hfi_queue_cmd_write(inst->core, inst_hfi_gen2->packet,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
830
ret = iris_hfi_gen2_session_set_codec(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
834
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
835
ret = iris_hfi_gen2_session_set_default_header(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
849
static int iris_hfi_gen2_session_close(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
851
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
857
iris_hfi_gen2_packet_session_command(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
863
inst->session_id,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
868
ret = iris_hfi_queue_cmd_write(inst->core, inst_hfi_gen2->packet,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
877
static int iris_hfi_gen2_session_subscribe_mode(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
881
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
883
iris_hfi_gen2_packet_session_command(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
887
iris_hfi_gen2_get_port(inst, plane),
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
888
inst->session_id,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
893
return iris_hfi_queue_cmd_write(inst->core, inst_hfi_gen2->packet,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
897
static int iris_hfi_gen2_subscribe_change_param(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
899
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
902
struct iris_core *core = inst->core;
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
909
if (inst->domain == ENCODER)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
91
static u32 iris_hfi_gen2_get_port(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
918
switch (inst->codec) {
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
93
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
946
ret = iris_hfi_gen2_session_subscribe_mode(inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
958
hfi_port = iris_hfi_gen2_get_port(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c
229
void iris_hfi_gen2_packet_session_command(struct iris_inst *inst, u32 pkt_type,
drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c
234
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c
235
struct iris_core *core = inst->core;
drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c
249
void iris_hfi_gen2_packet_session_property(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c
253
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c
254
struct iris_core *core = inst->core;
drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c
256
iris_hfi_gen2_create_header(inst_hfi_gen2->packet, inst->session_id, core->header_id++);
drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.h
114
void iris_hfi_gen2_packet_session_command(struct iris_inst *inst, u32 pkt_type,
drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.h
118
void iris_hfi_gen2_packet_session_property(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
196
static int iris_hfi_gen2_handle_session_info(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
199
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
200
struct iris_core *core = inst->core;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
218
ret = iris_inst_sub_state_change_drain_last(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
222
ret = iris_inst_sub_state_change_drc_last(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
235
static int iris_hfi_gen2_handle_session_error(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
238
struct iris_core *core = inst->core;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
24
int (*handle)(struct iris_inst *inst, struct iris_hfi_packet *pkt);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
269
iris_vb2_queue_error(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
270
iris_inst_change_state(inst, IRIS_INST_ERROR);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
29
int (*handle)(struct iris_inst *inst, struct iris_hfi_packet *pkt);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
308
static void iris_hfi_gen2_handle_session_close(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
312
iris_inst_change_state(inst, IRIS_INST_ERROR);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
316
complete(&inst->completion);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
319
static int iris_hfi_gen2_handle_input_buffer(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
32
static u32 iris_hfi_gen2_buf_type_to_driver(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
322
struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
343
buf->flags = iris_hfi_gen2_get_driver_buffer_flags(inst, buffer->flags);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
348
static int iris_hfi_gen2_handle_output_buffer(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
351
struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
358
ret = iris_inst_sub_state_change_drain_last(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
364
ret = iris_inst_sub_state_change_drc_last(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
391
buf->flags = iris_hfi_gen2_get_driver_buffer_flags(inst, hfi_buffer->flags);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
393
if (!buf->data_size && inst->state == IRIS_INST_STREAMING &&
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
401
static void iris_hfi_gen2_handle_dequeue_buffers(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
403
struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
413
iris_vb2_buffer_done(inst, buf);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
424
iris_vb2_buffer_done(inst, buf);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
430
static int iris_hfi_gen2_handle_release_internal_buffer(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
433
u32 buf_type = iris_hfi_gen2_buf_type_to_driver(inst, buffer->type);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
434
struct iris_buffers *buffers = &inst->buffers[buf_type];
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
450
return iris_destroy_internal_buffer(inst, buf);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
453
static int iris_hfi_gen2_handle_session_stop(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
459
ret = iris_inst_sub_state_change_pause(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
461
ret = iris_inst_sub_state_change_pause(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
463
complete(&inst->completion);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
468
static int iris_hfi_gen2_handle_session_buffer(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
477
iris_inst_change_state(inst, IRIS_INST_ERROR);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
488
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
490
return iris_hfi_gen2_handle_input_buffer(inst, buffer);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
492
return iris_hfi_gen2_handle_output_buffer(inst, buffer);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
494
return iris_hfi_gen2_handle_release_internal_buffer(inst, buffer);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
497
return iris_hfi_gen2_handle_input_buffer(inst, buffer);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
499
return iris_hfi_gen2_handle_output_buffer(inst, buffer);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
501
return iris_hfi_gen2_handle_release_internal_buffer(inst, buffer);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
506
static int iris_hfi_gen2_handle_session_drain(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
51
if (inst->domain == DECODER)
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
512
iris_inst_change_state(inst, IRIS_INST_ERROR);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
516
if (inst->sub_state & IRIS_INST_SUB_DRAIN)
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
517
ret = iris_inst_change_sub_state(inst, 0, IRIS_INST_SUB_INPUT_PAUSE);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
522
static void iris_hfi_gen2_read_input_subcr_params(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
524
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
525
struct v4l2_pix_format_mplane *pixmp_ip = &inst->fmt_src->fmt.pix_mp;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
526
struct v4l2_pix_format_mplane *pixmp_op = &inst->fmt_dst->fmt.pix_mp;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
531
struct iris_core *core = inst->core;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
572
pixmp_op->plane_fmt[0].sizeimage = iris_get_buffer_size(inst, BUF_OUTPUT);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
608
inst->crop.top = subsc_params.crop_offsets[0] & 0xFFFF;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
609
inst->crop.left = (subsc_params.crop_offsets[0] >> 16) & 0xFFFF;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
610
inst->crop.height = pixmp_ip->height -
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
611
(subsc_params.crop_offsets[1] & 0xFFFF) - inst->crop.top;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
612
inst->crop.width = pixmp_ip->width -
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
613
((subsc_params.crop_offsets[1] >> 16) & 0xFFFF) - inst->crop.left;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
615
switch (inst->codec) {
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
617
inst->fw_caps[PROFILE_HEVC].value = subsc_params.profile;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
618
inst->fw_caps[LEVEL_HEVC].value = subsc_params.level;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
621
inst->fw_caps[PROFILE_VP9].value = subsc_params.profile;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
622
inst->fw_caps[LEVEL_VP9].value = subsc_params.level;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
625
inst->fw_caps[PROFILE_H264].value = subsc_params.profile;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
626
inst->fw_caps[LEVEL_H264].value = subsc_params.level;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
629
inst->fw_caps[PROFILE_AV1].value = subsc_params.profile;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
630
inst->fw_caps[LEVEL_AV1].value = subsc_params.level;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
634
inst->fw_caps[POC].value = subsc_params.pic_order_cnt;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
635
inst->fw_caps[TIER].value = subsc_params.tier;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
638
inst->fw_caps[BIT_DEPTH].value = BIT_DEPTH_8;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
640
inst->fw_caps[BIT_DEPTH].value = BIT_DEPTH_10;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
646
iris_inst_change_state(inst, IRIS_INST_ERROR);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
649
if (inst->codec == V4L2_PIX_FMT_AV1) {
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
650
inst->fw_caps[FILM_GRAIN].value = subsc_params.film_grain;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
651
inst->fw_caps[SUPER_BLOCK].value = subsc_params.super_block;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
654
inst->fw_min_count = subsc_params.fw_min_count;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
655
inst->buffers[BUF_OUTPUT].min_count = iris_vpu_buf_count(inst, BUF_OUTPUT);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
656
inst->buffers[BUF_OUTPUT].size = pixmp_op->plane_fmt[0].sizeimage;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
657
ctrl = v4l2_ctrl_find(&inst->ctrl_handler, V4L2_CID_MIN_BUFFERS_FOR_CAPTURE);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
659
v4l2_ctrl_s_ctrl(ctrl, inst->buffers[BUF_OUTPUT].min_count);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
661
dst_q = v4l2_m2m_get_dst_vq(inst->m2m_ctx);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
662
dst_q->min_reqbufs_allocation = inst->buffers[BUF_OUTPUT].min_count;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
665
static int iris_hfi_gen2_handle_src_change(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
673
ret = iris_inst_sub_state_change_drc(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
677
iris_hfi_gen2_read_input_subcr_params(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
678
iris_vdec_src_change(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
683
static int iris_hfi_gen2_handle_session_command(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
690
iris_hfi_gen2_handle_session_close(inst, pkt);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
693
iris_hfi_gen2_handle_session_stop(inst, pkt);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
696
ret = iris_hfi_gen2_handle_session_buffer(inst, pkt);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
699
ret = iris_hfi_gen2_handle_src_change(inst, pkt);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
702
ret = iris_hfi_gen2_handle_session_drain(inst, pkt);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
711
static int iris_hfi_gen2_handle_session_property(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
714
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
846
static void iris_hfi_gen2_init_src_change_param(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
848
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
849
struct v4l2_pix_format_mplane *pixmp_ip = &inst->fmt_src->fmt.pix_mp;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
850
struct v4l2_pix_format_mplane *pixmp_op = &inst->fmt_dst->fmt.pix_mp;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
851
u32 bottom_offset = (pixmp_ip->height - inst->crop.height);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
852
u32 right_offset = (pixmp_ip->width - inst->crop.width);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
858
u32 left_offset = inst->crop.left;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
859
u32 top_offset = inst->crop.top;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
868
subsc_params->fw_min_count = inst->buffers[BUF_OUTPUT].min_count;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
880
switch (inst->codec) {
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
882
subsc_params->profile = inst->fw_caps[PROFILE_HEVC].value;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
883
subsc_params->level = inst->fw_caps[LEVEL_HEVC].value;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
886
subsc_params->profile = inst->fw_caps[PROFILE_VP9].value;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
887
subsc_params->level = inst->fw_caps[LEVEL_VP9].value;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
890
subsc_params->profile = inst->fw_caps[PROFILE_H264].value;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
891
subsc_params->level = inst->fw_caps[LEVEL_H264].value;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
894
subsc_params->profile = inst->fw_caps[PROFILE_AV1].value;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
895
subsc_params->level = inst->fw_caps[LEVEL_AV1].value;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
899
subsc_params->pic_order_cnt = inst->fw_caps[POC].value;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
900
subsc_params->bit_depth = inst->fw_caps[BIT_DEPTH].value;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
901
if (inst->fw_caps[CODED_FRAMES].value ==
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
914
struct iris_inst *inst;
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
929
inst = iris_get_instance(core, hdr->session_id);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
930
if (!inst)
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
933
mutex_lock(&inst->lock);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
934
inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
941
iris_hfi_gen2_init_src_change_param(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
954
iris_hfi_gen2_handle_session_error(inst, packet);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
958
ret = range[i].handle(inst, packet);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
960
iris_inst_change_state(inst, IRIS_INST_ERROR);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
967
iris_hfi_gen2_handle_dequeue_buffers(inst);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
969
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
97
static int iris_hfi_gen2_get_driver_buffer_flags(struct iris_inst *inst, u32 hfi_flags)
drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c
99
struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
drivers/media/platform/qcom/iris/iris_platform_common.h
207
int (*set)(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_platform_common.h
287
u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type buffer_type);
drivers/media/platform/qcom/iris/iris_power.c
100
static int iris_scale_clocks(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_power.c
102
const struct vpu_ops *vpu_ops = inst->core->iris_platform_data->vpu_ops;
drivers/media/platform/qcom/iris/iris_power.c
103
struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
drivers/media/platform/qcom/iris/iris_power.c
113
inst->max_input_data_size = data_size;
drivers/media/platform/qcom/iris/iris_power.c
114
if (!inst->max_input_data_size)
drivers/media/platform/qcom/iris/iris_power.c
117
inst->power.min_freq = vpu_ops->calc_freq(inst, inst->max_input_data_size);
drivers/media/platform/qcom/iris/iris_power.c
119
return iris_set_clocks(inst);
drivers/media/platform/qcom/iris/iris_power.c
122
int iris_scale_power(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_power.c
124
struct iris_core *core = inst->core;
drivers/media/platform/qcom/iris/iris_power.c
135
ret = iris_scale_clocks(inst);
drivers/media/platform/qcom/iris/iris_power.c
139
return iris_vote_interconnects(inst);
drivers/media/platform/qcom/iris/iris_power.c
16
static u32 iris_calc_bw(struct iris_inst *inst, struct icc_vote_data *data)
drivers/media/platform/qcom/iris/iris_power.c
19
struct iris_core *core = inst->core;
drivers/media/platform/qcom/iris/iris_power.c
42
static int iris_set_interconnects(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_power.c
44
struct iris_core *core = inst->core;
drivers/media/platform/qcom/iris/iris_power.c
64
static int iris_vote_interconnects(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_power.c
66
struct icc_vote_data *vote_data = &inst->icc_data;
drivers/media/platform/qcom/iris/iris_power.c
67
struct v4l2_format *inp_f = inst->fmt_src;
drivers/media/platform/qcom/iris/iris_power.c
73
inst->power.icc_bw = iris_calc_bw(inst, vote_data);
drivers/media/platform/qcom/iris/iris_power.c
75
return iris_set_interconnects(inst);
drivers/media/platform/qcom/iris/iris_power.c
78
static int iris_set_clocks(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_power.c
80
struct iris_core *core = inst->core;
drivers/media/platform/qcom/iris/iris_power.h
11
int iris_scale_power(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_state.c
10
static bool iris_allow_inst_state_change(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_state.c
101
else if (inst->state == IRIS_INST_STREAMING)
drivers/media/platform/qcom/iris/iris_state.c
105
return iris_inst_change_state(inst, new_state);
drivers/media/platform/qcom/iris/iris_state.c
108
static bool iris_inst_allow_sub_state(struct iris_inst *inst, enum iris_inst_sub_state sub_state)
drivers/media/platform/qcom/iris/iris_state.c
113
switch (inst->state) {
drivers/media/platform/qcom/iris/iris_state.c
13
switch (inst->state) {
drivers/media/platform/qcom/iris/iris_state.c
146
int iris_inst_change_sub_state(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_state.c
152
if (inst->state == IRIS_INST_ERROR)
drivers/media/platform/qcom/iris/iris_state.c
163
prev_sub_state = inst->sub_state;
drivers/media/platform/qcom/iris/iris_state.c
165
if (!iris_inst_allow_sub_state(inst, set_sub_state))
drivers/media/platform/qcom/iris/iris_state.c
168
inst->sub_state |= set_sub_state;
drivers/media/platform/qcom/iris/iris_state.c
169
inst->sub_state &= ~clear_sub_state;
drivers/media/platform/qcom/iris/iris_state.c
171
if (inst->sub_state != prev_sub_state)
drivers/media/platform/qcom/iris/iris_state.c
172
dev_dbg(inst->core->dev, "sub_state changed from %x to %x\n",
drivers/media/platform/qcom/iris/iris_state.c
173
prev_sub_state, inst->sub_state);
drivers/media/platform/qcom/iris/iris_state.c
178
int iris_inst_sub_state_change_drc(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_state.c
182
if (inst->sub_state & IRIS_INST_SUB_DRC)
drivers/media/platform/qcom/iris/iris_state.c
185
if (inst->state == IRIS_INST_INPUT_STREAMING ||
drivers/media/platform/qcom/iris/iris_state.c
186
inst->state == IRIS_INST_INIT)
drivers/media/platform/qcom/iris/iris_state.c
191
return iris_inst_change_sub_state(inst, 0, set_sub_state);
drivers/media/platform/qcom/iris/iris_state.c
194
int iris_inst_sub_state_change_drain_last(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_state.c
198
if (inst->sub_state & IRIS_INST_SUB_DRAIN_LAST)
drivers/media/platform/qcom/iris/iris_state.c
201
if (!(inst->sub_state & IRIS_INST_SUB_DRAIN))
drivers/media/platform/qcom/iris/iris_state.c
206
return iris_inst_change_sub_state(inst, 0, set_sub_state);
drivers/media/platform/qcom/iris/iris_state.c
209
int iris_inst_sub_state_change_drc_last(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_state.c
213
if (inst->sub_state & IRIS_INST_SUB_DRC_LAST)
drivers/media/platform/qcom/iris/iris_state.c
216
if (!(inst->sub_state & IRIS_INST_SUB_DRC) ||
drivers/media/platform/qcom/iris/iris_state.c
217
!(inst->sub_state & IRIS_INST_SUB_INPUT_PAUSE))
drivers/media/platform/qcom/iris/iris_state.c
220
if (inst->sub_state & IRIS_INST_SUB_FIRST_IPSC)
drivers/media/platform/qcom/iris/iris_state.c
225
return iris_inst_change_sub_state(inst, 0, set_sub_state);
drivers/media/platform/qcom/iris/iris_state.c
228
int iris_inst_sub_state_change_pause(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_state.c
233
if (inst->sub_state & IRIS_INST_SUB_DRC &&
drivers/media/platform/qcom/iris/iris_state.c
234
!(inst->sub_state & IRIS_INST_SUB_DRC_LAST))
drivers/media/platform/qcom/iris/iris_state.c
237
if (inst->sub_state & IRIS_INST_SUB_DRAIN &&
drivers/media/platform/qcom/iris/iris_state.c
238
!(inst->sub_state & IRIS_INST_SUB_DRAIN_LAST))
drivers/media/platform/qcom/iris/iris_state.c
246
return iris_inst_change_sub_state(inst, 0, set_sub_state);
drivers/media/platform/qcom/iris/iris_state.c
249
bool iris_drc_pending(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_state.c
251
return inst->sub_state & IRIS_INST_SUB_DRC &&
drivers/media/platform/qcom/iris/iris_state.c
252
inst->sub_state & IRIS_INST_SUB_DRC_LAST;
drivers/media/platform/qcom/iris/iris_state.c
255
bool iris_drain_pending(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_state.c
257
return inst->sub_state & IRIS_INST_SUB_DRAIN &&
drivers/media/platform/qcom/iris/iris_state.c
258
inst->sub_state & IRIS_INST_SUB_DRAIN_LAST;
drivers/media/platform/qcom/iris/iris_state.c
261
bool iris_allow_cmd(struct iris_inst *inst, u32 cmd)
drivers/media/platform/qcom/iris/iris_state.c
263
struct vb2_queue *src_q = v4l2_m2m_get_src_vq(inst->m2m_ctx);
drivers/media/platform/qcom/iris/iris_state.c
264
struct vb2_queue *dst_q = v4l2_m2m_get_dst_vq(inst->m2m_ctx);
drivers/media/platform/qcom/iris/iris_state.c
268
if (iris_drc_pending(inst) || iris_drain_pending(inst))
drivers/media/platform/qcom/iris/iris_state.c
272
if (inst->sub_state != IRIS_INST_SUB_DRAIN)
drivers/media/platform/qcom/iris/iris_state.c
47
int iris_inst_change_state(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_state.c
50
if (inst->state == IRIS_INST_ERROR)
drivers/media/platform/qcom/iris/iris_state.c
53
if (inst->state == request_state)
drivers/media/platform/qcom/iris/iris_state.c
59
if (!iris_allow_inst_state_change(inst, request_state))
drivers/media/platform/qcom/iris/iris_state.c
63
inst->state = request_state;
drivers/media/platform/qcom/iris/iris_state.c
64
dev_dbg(inst->core->dev, "state changed from %x to %x\n",
drivers/media/platform/qcom/iris/iris_state.c
65
inst->state, request_state);
drivers/media/platform/qcom/iris/iris_state.c
70
int iris_inst_state_change_streamon(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_state.c
75
if (inst->state == IRIS_INST_INIT)
drivers/media/platform/qcom/iris/iris_state.c
77
else if (inst->state == IRIS_INST_OUTPUT_STREAMING)
drivers/media/platform/qcom/iris/iris_state.c
80
if (inst->state == IRIS_INST_INIT)
drivers/media/platform/qcom/iris/iris_state.c
82
else if (inst->state == IRIS_INST_INPUT_STREAMING)
drivers/media/platform/qcom/iris/iris_state.c
86
return iris_inst_change_state(inst, new_state);
drivers/media/platform/qcom/iris/iris_state.c
89
int iris_inst_state_change_streamoff(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_state.c
94
if (inst->state == IRIS_INST_INPUT_STREAMING)
drivers/media/platform/qcom/iris/iris_state.c
96
else if (inst->state == IRIS_INST_STREAMING)
drivers/media/platform/qcom/iris/iris_state.c
99
if (inst->state == IRIS_INST_OUTPUT_STREAMING)
drivers/media/platform/qcom/iris/iris_state.h
130
int iris_inst_change_state(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_state.h
132
int iris_inst_change_sub_state(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_state.h
136
int iris_inst_state_change_streamon(struct iris_inst *inst, u32 plane);
drivers/media/platform/qcom/iris/iris_state.h
137
int iris_inst_state_change_streamoff(struct iris_inst *inst, u32 plane);
drivers/media/platform/qcom/iris/iris_state.h
138
int iris_inst_sub_state_change_drc(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_state.h
139
int iris_inst_sub_state_change_drain_last(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_state.h
140
int iris_inst_sub_state_change_drc_last(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_state.h
141
int iris_inst_sub_state_change_pause(struct iris_inst *inst, u32 plane);
drivers/media/platform/qcom/iris/iris_state.h
142
bool iris_allow_cmd(struct iris_inst *inst, u32 cmd);
drivers/media/platform/qcom/iris/iris_state.h
143
bool iris_drc_pending(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_state.h
144
bool iris_drain_pending(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_utils.c
104
int iris_check_core_mbpf(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_utils.c
106
struct iris_core *core = inst->core;
drivers/media/platform/qcom/iris/iris_utils.c
121
int iris_check_core_mbps(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_utils.c
123
struct iris_core *core = inst->core;
drivers/media/platform/qcom/iris/iris_utils.c
140
bool is_rotation_90_or_270(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_utils.c
142
return inst->fw_caps[ROTATION].value == 90 ||
drivers/media/platform/qcom/iris/iris_utils.c
143
inst->fw_caps[ROTATION].value == 270;
drivers/media/platform/qcom/iris/iris_utils.c
26
int iris_get_mbpf(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_utils.c
28
struct v4l2_format *inp_f = inst->fmt_src;
drivers/media/platform/qcom/iris/iris_utils.c
29
u32 height = max(inp_f->fmt.pix_mp.height, inst->crop.height);
drivers/media/platform/qcom/iris/iris_utils.c
30
u32 width = max(inp_f->fmt.pix_mp.width, inst->crop.width);
drivers/media/platform/qcom/iris/iris_utils.c
35
bool iris_split_mode_enabled(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_utils.c
37
return inst->fmt_dst->fmt.pix_mp.pixelformat == V4L2_PIX_FMT_NV12 ||
drivers/media/platform/qcom/iris/iris_utils.c
38
inst->fmt_dst->fmt.pix_mp.pixelformat == V4L2_PIX_FMT_QC08C ||
drivers/media/platform/qcom/iris/iris_utils.c
39
inst->fmt_dst->fmt.pix_mp.pixelformat == V4L2_PIX_FMT_P010 ||
drivers/media/platform/qcom/iris/iris_utils.c
40
inst->fmt_dst->fmt.pix_mp.pixelformat == V4L2_PIX_FMT_QC10C;
drivers/media/platform/qcom/iris/iris_utils.c
55
void iris_helper_buffers_done(struct iris_inst *inst, unsigned int type,
drivers/media/platform/qcom/iris/iris_utils.c
58
struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
drivers/media/platform/qcom/iris/iris_utils.c
70
int iris_wait_for_session_response(struct iris_inst *inst, bool is_flush)
drivers/media/platform/qcom/iris/iris_utils.c
75
done = is_flush ? &inst->flush_completion : &inst->completion;
drivers/media/platform/qcom/iris/iris_utils.c
77
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/iris/iris_utils.c
79
mutex_lock(&inst->lock);
drivers/media/platform/qcom/iris/iris_utils.c
81
iris_inst_change_state(inst, IRIS_INST_ERROR);
drivers/media/platform/qcom/iris/iris_utils.c
90
struct iris_inst *inst;
drivers/media/platform/qcom/iris/iris_utils.c
93
list_for_each_entry(inst, &core->instances, list) {
drivers/media/platform/qcom/iris/iris_utils.c
94
if (inst->session_id == session_id) {
drivers/media/platform/qcom/iris/iris_utils.c
96
return inst;
drivers/media/platform/qcom/iris/iris_utils.h
46
int iris_get_mbpf(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_utils.h
47
bool iris_split_mode_enabled(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_utils.h
51
void iris_helper_buffers_done(struct iris_inst *inst, unsigned int type,
drivers/media/platform/qcom/iris/iris_utils.h
53
int iris_wait_for_session_response(struct iris_inst *inst, bool is_flush);
drivers/media/platform/qcom/iris/iris_utils.h
54
int iris_check_core_mbpf(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_utils.h
55
int iris_check_core_mbps(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_utils.h
56
bool is_rotation_90_or_270(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_vb2.c
102
struct iris_inst *inst;
drivers/media/platform/qcom/iris/iris_vb2.c
107
inst = vb2_get_drv_priv(q);
drivers/media/platform/qcom/iris/iris_vb2.c
109
mutex_lock(&inst->lock);
drivers/media/platform/qcom/iris/iris_vb2.c
110
if (inst->state == IRIS_INST_ERROR) {
drivers/media/platform/qcom/iris/iris_vb2.c
115
core = inst->core;
drivers/media/platform/qcom/iris/iris_vb2.c
116
f = V4L2_TYPE_IS_OUTPUT(q->type) ? inst->fmt_src : inst->fmt_dst;
drivers/media/platform/qcom/iris/iris_vb2.c
125
ret = iris_check_session_supported(inst);
drivers/media/platform/qcom/iris/iris_vb2.c
129
if (!inst->once_per_session_set) {
drivers/media/platform/qcom/iris/iris_vb2.c
130
inst->once_per_session_set = true;
drivers/media/platform/qcom/iris/iris_vb2.c
132
ret = inst->hfi_session_ops->session_open(inst);
drivers/media/platform/qcom/iris/iris_vb2.c
139
ret = iris_inst_change_state(inst, IRIS_INST_INIT);
drivers/media/platform/qcom/iris/iris_vb2.c
148
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/iris/iris_vb2.c
156
struct iris_inst *inst;
drivers/media/platform/qcom/iris/iris_vb2.c
159
inst = vb2_get_drv_priv(q);
drivers/media/platform/qcom/iris/iris_vb2.c
161
mutex_lock(&inst->lock);
drivers/media/platform/qcom/iris/iris_vb2.c
162
if (inst->state == IRIS_INST_ERROR) {
drivers/media/platform/qcom/iris/iris_vb2.c
17
static int iris_check_inst_mbpf(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vb2.c
173
iris_scale_power(inst);
drivers/media/platform/qcom/iris/iris_vb2.c
175
ret = iris_check_session_supported(inst);
drivers/media/platform/qcom/iris/iris_vb2.c
180
if (inst->domain == DECODER)
drivers/media/platform/qcom/iris/iris_vb2.c
181
ret = iris_vdec_streamon_input(inst);
drivers/media/platform/qcom/iris/iris_vb2.c
183
ret = iris_venc_streamon_input(inst);
drivers/media/platform/qcom/iris/iris_vb2.c
185
if (inst->domain == DECODER)
drivers/media/platform/qcom/iris/iris_vb2.c
186
ret = iris_vdec_streamon_output(inst);
drivers/media/platform/qcom/iris/iris_vb2.c
188
ret = iris_venc_streamon_output(inst);
drivers/media/platform/qcom/iris/iris_vb2.c
195
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_vb2.c
197
ret = iris_queue_deferred_buffers(inst, BUF_INPUT);
drivers/media/platform/qcom/iris/iris_vb2.c
199
if (!ret && inst->state == IRIS_INST_STREAMING) {
drivers/media/platform/qcom/iris/iris_vb2.c
200
ret = iris_queue_internal_deferred_buffers(inst, BUF_DPB);
drivers/media/platform/qcom/iris/iris_vb2.c
202
ret = iris_queue_deferred_buffers(inst, BUF_OUTPUT);
drivers/media/platform/qcom/iris/iris_vb2.c
205
if (inst->state == IRIS_INST_STREAMING) {
drivers/media/platform/qcom/iris/iris_vb2.c
206
ret = iris_queue_deferred_buffers(inst, BUF_INPUT);
drivers/media/platform/qcom/iris/iris_vb2.c
208
ret = iris_queue_deferred_buffers(inst, BUF_OUTPUT);
drivers/media/platform/qcom/iris/iris_vb2.c
215
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/iris/iris_vb2.c
22
caps = inst->core->iris_platform_data->inst_caps;
drivers/media/platform/qcom/iris/iris_vb2.c
220
iris_helper_buffers_done(inst, q->type, VB2_BUF_STATE_QUEUED);
drivers/media/platform/qcom/iris/iris_vb2.c
221
iris_inst_change_state(inst, IRIS_INST_ERROR);
drivers/media/platform/qcom/iris/iris_vb2.c
222
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/iris/iris_vb2.c
229
struct iris_inst *inst;
drivers/media/platform/qcom/iris/iris_vb2.c
232
inst = vb2_get_drv_priv(q);
drivers/media/platform/qcom/iris/iris_vb2.c
234
if (V4L2_TYPE_IS_CAPTURE(q->type) && inst->state == IRIS_INST_INIT)
drivers/media/platform/qcom/iris/iris_vb2.c
237
mutex_lock(&inst->lock);
drivers/media/platform/qcom/iris/iris_vb2.c
24
mbpf = iris_get_mbpf(inst);
drivers/media/platform/qcom/iris/iris_vb2.c
243
ret = iris_session_streamoff(inst, q->type);
drivers/media/platform/qcom/iris/iris_vb2.c
248
iris_helper_buffers_done(inst, q->type, VB2_BUF_STATE_ERROR);
drivers/media/platform/qcom/iris/iris_vb2.c
250
iris_inst_change_state(inst, IRIS_INST_ERROR);
drivers/media/platform/qcom/iris/iris_vb2.c
252
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/iris/iris_vb2.c
257
struct iris_inst *inst = vb2_get_drv_priv(vb->vb2_queue);
drivers/media/platform/qcom/iris/iris_vb2.c
267
if (!(inst->sub_state & IRIS_INST_SUB_DRC)) {
drivers/media/platform/qcom/iris/iris_vb2.c
269
vb2_plane_size(vb, 0) < iris_get_buffer_size(inst, BUF_OUTPUT))
drivers/media/platform/qcom/iris/iris_vb2.c
272
vb2_plane_size(vb, 0) < iris_get_buffer_size(inst, BUF_INPUT))
drivers/media/platform/qcom/iris/iris_vb2.c
292
struct iris_inst *inst;
drivers/media/platform/qcom/iris/iris_vb2.c
295
inst = vb2_get_drv_priv(vb2->vb2_queue);
drivers/media/platform/qcom/iris/iris_vb2.c
297
mutex_lock(&inst->lock);
drivers/media/platform/qcom/iris/iris_vb2.c
298
if (inst->state == IRIS_INST_ERROR) {
drivers/media/platform/qcom/iris/iris_vb2.c
306
m2m_ctx = inst->m2m_ctx;
drivers/media/platform/qcom/iris/iris_vb2.c
31
static int iris_check_resolution_supported(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vb2.c
313
if (!inst->last_buffer_dequeued && V4L2_TYPE_IS_CAPTURE(vb2->vb2_queue->type)) {
drivers/media/platform/qcom/iris/iris_vb2.c
314
if ((inst->sub_state & IRIS_INST_SUB_DRC &&
drivers/media/platform/qcom/iris/iris_vb2.c
315
inst->sub_state & IRIS_INST_SUB_DRC_LAST) ||
drivers/media/platform/qcom/iris/iris_vb2.c
316
(inst->sub_state & IRIS_INST_SUB_DRAIN &&
drivers/media/platform/qcom/iris/iris_vb2.c
317
inst->sub_state & IRIS_INST_SUB_DRAIN_LAST)) {
drivers/media/platform/qcom/iris/iris_vb2.c
319
vbuf->sequence = inst->sequence_cap++;
drivers/media/platform/qcom/iris/iris_vb2.c
324
v4l2_event_queue_fh(&inst->fh, &eos);
drivers/media/platform/qcom/iris/iris_vb2.c
327
inst->last_buffer_dequeued = true;
drivers/media/platform/qcom/iris/iris_vb2.c
334
if (inst->domain == DECODER)
drivers/media/platform/qcom/iris/iris_vb2.c
335
ret = iris_vdec_qbuf(inst, vbuf);
drivers/media/platform/qcom/iris/iris_vb2.c
337
ret = iris_venc_qbuf(inst, vbuf);
drivers/media/platform/qcom/iris/iris_vb2.c
341
iris_inst_change_state(inst, IRIS_INST_ERROR);
drivers/media/platform/qcom/iris/iris_vb2.c
344
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/iris/iris_vb2.c
36
caps = inst->core->iris_platform_data->inst_caps;
drivers/media/platform/qcom/iris/iris_vb2.c
37
width = inst->fmt_src->fmt.pix_mp.width;
drivers/media/platform/qcom/iris/iris_vb2.c
38
height = inst->fmt_src->fmt.pix_mp.height;
drivers/media/platform/qcom/iris/iris_vb2.c
52
static int iris_check_session_supported(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vb2.c
54
struct iris_core *core = inst->core;
drivers/media/platform/qcom/iris/iris_vb2.c
60
if (instance == inst)
drivers/media/platform/qcom/iris/iris_vb2.c
69
ret = iris_check_core_mbpf(inst);
drivers/media/platform/qcom/iris/iris_vb2.c
73
ret = iris_check_inst_mbpf(inst);
drivers/media/platform/qcom/iris/iris_vb2.c
77
ret = iris_check_resolution_supported(inst);
drivers/media/platform/qcom/iris/iris_vb2.c
83
dev_err(inst->core->dev, "current session not supported(%d)\n", ret);
drivers/media/platform/qcom/iris/iris_vdec.c
100
inst->fw_caps[BIT_DEPTH].value == BIT_DEPTH_10)
drivers/media/platform/qcom/iris/iris_vdec.c
104
inst->fw_caps[BIT_DEPTH].value != BIT_DEPTH_10)
drivers/media/platform/qcom/iris/iris_vdec.c
111
static u32 find_format_by_index(struct iris_inst *inst, u32 index, u32 type)
drivers/media/platform/qcom/iris/iris_vdec.c
118
fmt = inst->core->iris_platform_data->inst_iris_fmts;
drivers/media/platform/qcom/iris/iris_vdec.c
119
size = inst->core->iris_platform_data->inst_iris_fmts_size;
drivers/media/platform/qcom/iris/iris_vdec.c
135
int iris_vdec_enum_fmt(struct iris_inst *inst, struct v4l2_fmtdesc *f)
drivers/media/platform/qcom/iris/iris_vdec.c
141
fmt = find_format_by_index(inst, f->index, f->type);
drivers/media/platform/qcom/iris/iris_vdec.c
149
fmt = find_format_by_index(inst, f->index, f->type);
drivers/media/platform/qcom/iris/iris_vdec.c
161
int iris_vdec_try_fmt(struct iris_inst *inst, struct v4l2_format *f)
drivers/media/platform/qcom/iris/iris_vdec.c
164
struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
drivers/media/platform/qcom/iris/iris_vdec.c
170
supported = check_format(inst, pixmp->pixelformat, f->type);
drivers/media/platform/qcom/iris/iris_vdec.c
174
f_inst = inst->fmt_src;
drivers/media/platform/qcom/iris/iris_vdec.c
182
f_inst = inst->fmt_dst;
drivers/media/platform/qcom/iris/iris_vdec.c
19
int iris_vdec_inst_init(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vdec.c
190
f_inst = inst->fmt_src;
drivers/media/platform/qcom/iris/iris_vdec.c
207
int iris_vdec_s_fmt(struct iris_inst *inst, struct v4l2_format *f)
drivers/media/platform/qcom/iris/iris_vdec.c
21
struct iris_core *core = inst->core;
drivers/media/platform/qcom/iris/iris_vdec.c
213
q = v4l2_m2m_get_vq(inst->m2m_ctx, f->type);
drivers/media/platform/qcom/iris/iris_vdec.c
226
iris_vdec_try_fmt(inst, f);
drivers/media/platform/qcom/iris/iris_vdec.c
230
if (!check_format(inst, f->fmt.pix_mp.pixelformat, f->type))
drivers/media/platform/qcom/iris/iris_vdec.c
233
fmt = inst->fmt_src;
drivers/media/platform/qcom/iris/iris_vdec.c
236
inst->codec = fmt->fmt.pix_mp.pixelformat;
drivers/media/platform/qcom/iris/iris_vdec.c
237
codec_align = inst->codec == V4L2_PIX_FMT_HEVC ? 32 : 16;
drivers/media/platform/qcom/iris/iris_vdec.c
24
inst->fmt_src = kzalloc_obj(*inst->fmt_src);
drivers/media/platform/qcom/iris/iris_vdec.c
242
fmt->fmt.pix_mp.plane_fmt[0].sizeimage = iris_get_buffer_size(inst, BUF_INPUT);
drivers/media/platform/qcom/iris/iris_vdec.c
243
inst->buffers[BUF_INPUT].min_count = iris_vpu_buf_count(inst, BUF_INPUT);
drivers/media/platform/qcom/iris/iris_vdec.c
244
inst->buffers[BUF_INPUT].size = fmt->fmt.pix_mp.plane_fmt[0].sizeimage;
drivers/media/platform/qcom/iris/iris_vdec.c
25
inst->fmt_dst = kzalloc_obj(*inst->fmt_dst);
drivers/media/platform/qcom/iris/iris_vdec.c
251
output_fmt = inst->fmt_dst;
drivers/media/platform/qcom/iris/iris_vdec.c
260
inst->buffers[BUF_OUTPUT].min_count = iris_vpu_buf_count(inst, BUF_OUTPUT);
drivers/media/platform/qcom/iris/iris_vdec.c
261
inst->buffers[BUF_OUTPUT].size = iris_get_buffer_size(inst, BUF_OUTPUT);
drivers/media/platform/qcom/iris/iris_vdec.c
263
inst->crop.left = 0;
drivers/media/platform/qcom/iris/iris_vdec.c
264
inst->crop.top = 0;
drivers/media/platform/qcom/iris/iris_vdec.c
265
inst->crop.width = f->fmt.pix_mp.width;
drivers/media/platform/qcom/iris/iris_vdec.c
266
inst->crop.height = f->fmt.pix_mp.height;
drivers/media/platform/qcom/iris/iris_vdec.c
269
if (!check_format(inst, f->fmt.pix_mp.pixelformat, f->type))
drivers/media/platform/qcom/iris/iris_vdec.c
27
inst->fw_min_count = 0;
drivers/media/platform/qcom/iris/iris_vdec.c
272
fmt = inst->fmt_dst;
drivers/media/platform/qcom/iris/iris_vdec.c
29
f = inst->fmt_src;
drivers/media/platform/qcom/iris/iris_vdec.c
297
fmt->fmt.pix_mp.plane_fmt[0].sizeimage = iris_get_buffer_size(inst, BUF_OUTPUT);
drivers/media/platform/qcom/iris/iris_vdec.c
298
inst->buffers[BUF_OUTPUT].min_count = iris_vpu_buf_count(inst, BUF_OUTPUT);
drivers/media/platform/qcom/iris/iris_vdec.c
299
inst->buffers[BUF_OUTPUT].size = fmt->fmt.pix_mp.plane_fmt[0].sizeimage;
drivers/media/platform/qcom/iris/iris_vdec.c
301
inst->crop.top = 0;
drivers/media/platform/qcom/iris/iris_vdec.c
302
inst->crop.left = 0;
drivers/media/platform/qcom/iris/iris_vdec.c
303
inst->crop.width = f->fmt.pix_mp.width;
drivers/media/platform/qcom/iris/iris_vdec.c
304
inst->crop.height = f->fmt.pix_mp.height;
drivers/media/platform/qcom/iris/iris_vdec.c
314
int iris_vdec_validate_format(struct iris_inst *inst, u32 pixelformat)
drivers/media/platform/qcom/iris/iris_vdec.c
318
supported = check_format(inst, pixelformat, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
drivers/media/platform/qcom/iris/iris_vdec.c
320
supported = check_format(inst, pixelformat, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_vdec.c
325
int iris_vdec_subscribe_event(struct iris_inst *inst, const struct v4l2_event_subscription *sub)
drivers/media/platform/qcom/iris/iris_vdec.c
331
ret = v4l2_event_subscribe(&inst->fh, sub, 0, NULL);
drivers/media/platform/qcom/iris/iris_vdec.c
334
ret = v4l2_src_change_event_subscribe(&inst->fh, sub);
drivers/media/platform/qcom/iris/iris_vdec.c
337
ret = v4l2_ctrl_subscribe_event(&inst->fh, sub);
drivers/media/platform/qcom/iris/iris_vdec.c
34
inst->codec = f->fmt.pix_mp.pixelformat;
drivers/media/platform/qcom/iris/iris_vdec.c
346
void iris_vdec_src_change(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vdec.c
348
struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
drivers/media/platform/qcom/iris/iris_vdec.c
358
v4l2_event_queue_fh(&inst->fh, &event);
drivers/media/platform/qcom/iris/iris_vdec.c
361
int iris_vdec_streamon_input(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vdec.c
365
ret = iris_set_properties(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_vdec.c
369
ret = iris_alloc_and_queue_persist_bufs(inst, BUF_PERSIST);
drivers/media/platform/qcom/iris/iris_vdec.c
37
f->fmt.pix_mp.plane_fmt[0].sizeimage = iris_get_buffer_size(inst, BUF_INPUT);
drivers/media/platform/qcom/iris/iris_vdec.c
373
iris_get_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_vdec.c
375
ret = iris_destroy_dequeued_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_vdec.c
379
ret = iris_create_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_vdec.c
383
ret = iris_queue_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_vdec.c
387
inst->frame_counter = 0;
drivers/media/platform/qcom/iris/iris_vdec.c
389
return iris_process_streamon_input(inst);
drivers/media/platform/qcom/iris/iris_vdec.c
39
inst->buffers[BUF_INPUT].min_count = iris_vpu_buf_count(inst, BUF_INPUT);
drivers/media/platform/qcom/iris/iris_vdec.c
392
int iris_vdec_streamon_output(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vdec.c
394
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_vdec.c
397
ret = hfi_ops->session_set_config_params(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
drivers/media/platform/qcom/iris/iris_vdec.c
40
inst->buffers[BUF_INPUT].size = f->fmt.pix_mp.plane_fmt[0].sizeimage;
drivers/media/platform/qcom/iris/iris_vdec.c
401
iris_get_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
drivers/media/platform/qcom/iris/iris_vdec.c
403
ret = iris_destroy_dequeued_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
drivers/media/platform/qcom/iris/iris_vdec.c
407
ret = iris_create_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
drivers/media/platform/qcom/iris/iris_vdec.c
411
ret = iris_process_streamon_output(inst);
drivers/media/platform/qcom/iris/iris_vdec.c
415
ret = iris_queue_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
drivers/media/platform/qcom/iris/iris_vdec.c
42
f = inst->fmt_dst;
drivers/media/platform/qcom/iris/iris_vdec.c
422
iris_session_streamoff(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
drivers/media/platform/qcom/iris/iris_vdec.c
427
int iris_vdec_qbuf(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf)
drivers/media/platform/qcom/iris/iris_vdec.c
440
iris_set_ts_metadata(inst, vbuf);
drivers/media/platform/qcom/iris/iris_vdec.c
442
q = v4l2_m2m_get_vq(inst->m2m_ctx, vb2->type);
drivers/media/platform/qcom/iris/iris_vdec.c
451
if (!inst->frame_counter)
drivers/media/platform/qcom/iris/iris_vdec.c
452
inst->last_buf_ns = cur_buf_ns;
drivers/media/platform/qcom/iris/iris_vdec.c
454
inst->frame_counter++;
drivers/media/platform/qcom/iris/iris_vdec.c
455
delta_ns = cur_buf_ns - inst->last_buf_ns;
drivers/media/platform/qcom/iris/iris_vdec.c
458
inst->frame_rate = clamp_t(u32, inst->frame_counter, DEFAULT_FPS,
drivers/media/platform/qcom/iris/iris_vdec.c
460
inst->frame_counter = 0;
drivers/media/platform/qcom/iris/iris_vdec.c
464
iris_scale_power(inst);
drivers/media/platform/qcom/iris/iris_vdec.c
466
return iris_queue_buffer(inst, buf);
drivers/media/platform/qcom/iris/iris_vdec.c
469
int iris_vdec_start_cmd(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vdec.c
471
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_vdec.c
476
dst_vq = v4l2_m2m_get_dst_vq(inst->m2m_ctx);
drivers/media/platform/qcom/iris/iris_vdec.c
478
if (inst->sub_state & IRIS_INST_SUB_DRC &&
drivers/media/platform/qcom/iris/iris_vdec.c
479
inst->sub_state & IRIS_INST_SUB_DRC_LAST) {
drivers/media/platform/qcom/iris/iris_vdec.c
483
if (inst->sub_state & IRIS_INST_SUB_INPUT_PAUSE) {
drivers/media/platform/qcom/iris/iris_vdec.c
484
ret = hfi_ops->session_resume_drc(inst,
drivers/media/platform/qcom/iris/iris_vdec.c
49
f->fmt.pix_mp.plane_fmt[0].sizeimage = iris_get_buffer_size(inst, BUF_OUTPUT);
drivers/media/platform/qcom/iris/iris_vdec.c
490
if (inst->sub_state & IRIS_INST_SUB_OUTPUT_PAUSE) {
drivers/media/platform/qcom/iris/iris_vdec.c
491
ret = hfi_ops->session_resume_drc(inst,
drivers/media/platform/qcom/iris/iris_vdec.c
497
} else if (inst->sub_state & IRIS_INST_SUB_DRAIN &&
drivers/media/platform/qcom/iris/iris_vdec.c
498
inst->sub_state & IRIS_INST_SUB_DRAIN_LAST) {
drivers/media/platform/qcom/iris/iris_vdec.c
501
if (inst->sub_state & IRIS_INST_SUB_INPUT_PAUSE) {
drivers/media/platform/qcom/iris/iris_vdec.c
504
hfi_ops->session_resume_drain(inst,
drivers/media/platform/qcom/iris/iris_vdec.c
512
if (inst->sub_state & IRIS_INST_SUB_OUTPUT_PAUSE) {
drivers/media/platform/qcom/iris/iris_vdec.c
515
hfi_ops->session_resume_drain(inst,
drivers/media/platform/qcom/iris/iris_vdec.c
524
dev_err(inst->core->dev, "start called before receiving last_flag\n");
drivers/media/platform/qcom/iris/iris_vdec.c
525
iris_inst_change_state(inst, IRIS_INST_ERROR);
drivers/media/platform/qcom/iris/iris_vdec.c
529
return iris_inst_change_sub_state(inst, clear_sub_state, 0);
drivers/media/platform/qcom/iris/iris_vdec.c
532
int iris_vdec_stop_cmd(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vdec.c
534
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_vdec.c
537
ret = hfi_ops->session_drain(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_vdec.c
541
return iris_inst_change_sub_state(inst, 0, IRIS_INST_SUB_DRAIN);
drivers/media/platform/qcom/iris/iris_vdec.c
55
inst->buffers[BUF_OUTPUT].min_count = iris_vpu_buf_count(inst, BUF_OUTPUT);
drivers/media/platform/qcom/iris/iris_vdec.c
56
inst->buffers[BUF_OUTPUT].size = f->fmt.pix_mp.plane_fmt[0].sizeimage;
drivers/media/platform/qcom/iris/iris_vdec.c
57
inst->frame_rate = MAXIMUM_FPS;
drivers/media/platform/qcom/iris/iris_vdec.c
59
memcpy(&inst->fw_caps[0], &core->inst_fw_caps_dec[0],
drivers/media/platform/qcom/iris/iris_vdec.c
62
return iris_ctrls_init(inst);
drivers/media/platform/qcom/iris/iris_vdec.c
72
static bool check_format(struct iris_inst *inst, u32 pixfmt, u32 type)
drivers/media/platform/qcom/iris/iris_vdec.c
79
fmt = inst->core->iris_platform_data->inst_iris_fmts;
drivers/media/platform/qcom/iris/iris_vdec.c
80
size = inst->core->iris_platform_data->inst_iris_fmts_size;
drivers/media/platform/qcom/iris/iris_vdec.h
11
int iris_vdec_inst_init(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_vdec.h
12
int iris_vdec_enum_fmt(struct iris_inst *inst, struct v4l2_fmtdesc *f);
drivers/media/platform/qcom/iris/iris_vdec.h
13
int iris_vdec_try_fmt(struct iris_inst *inst, struct v4l2_format *f);
drivers/media/platform/qcom/iris/iris_vdec.h
14
int iris_vdec_s_fmt(struct iris_inst *inst, struct v4l2_format *f);
drivers/media/platform/qcom/iris/iris_vdec.h
15
int iris_vdec_validate_format(struct iris_inst *inst, u32 pixelformat);
drivers/media/platform/qcom/iris/iris_vdec.h
16
int iris_vdec_subscribe_event(struct iris_inst *inst, const struct v4l2_event_subscription *sub);
drivers/media/platform/qcom/iris/iris_vdec.h
17
void iris_vdec_src_change(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_vdec.h
18
int iris_vdec_streamon_input(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_vdec.h
19
int iris_vdec_streamon_output(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_vdec.h
20
int iris_vdec_qbuf(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf);
drivers/media/platform/qcom/iris/iris_vdec.h
21
int iris_vdec_start_cmd(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_vdec.h
22
int iris_vdec_stop_cmd(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_venc.c
118
static u32 find_format_by_index(struct iris_inst *inst, u32 index, u32 type)
drivers/media/platform/qcom/iris/iris_venc.c
142
int iris_venc_enum_fmt(struct iris_inst *inst, struct v4l2_fmtdesc *f)
drivers/media/platform/qcom/iris/iris_venc.c
148
fmt = find_format_by_index(inst, f->index, f->type);
drivers/media/platform/qcom/iris/iris_venc.c
155
fmt = find_format_by_index(inst, f->index, f->type);
drivers/media/platform/qcom/iris/iris_venc.c
169
int iris_venc_try_fmt(struct iris_inst *inst, struct v4l2_format *f)
drivers/media/platform/qcom/iris/iris_venc.c
17
int iris_venc_inst_init(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_venc.c
176
supported = check_format(inst, pixmp->pixelformat, f->type);
drivers/media/platform/qcom/iris/iris_venc.c
180
f_inst = inst->fmt_src;
drivers/media/platform/qcom/iris/iris_venc.c
188
f_inst = inst->fmt_dst;
drivers/media/platform/qcom/iris/iris_venc.c
19
struct iris_core *core = inst->core;
drivers/media/platform/qcom/iris/iris_venc.c
206
static int iris_venc_s_fmt_output(struct iris_inst *inst, struct v4l2_format *f)
drivers/media/platform/qcom/iris/iris_venc.c
212
iris_venc_try_fmt(inst, f);
drivers/media/platform/qcom/iris/iris_venc.c
214
supported = check_format(inst, f->fmt.pix_mp.pixelformat, f->type);
drivers/media/platform/qcom/iris/iris_venc.c
22
inst->fmt_src = kzalloc_obj(*inst->fmt_src);
drivers/media/platform/qcom/iris/iris_venc.c
220
fmt = inst->fmt_dst;
drivers/media/platform/qcom/iris/iris_venc.c
227
if (f->fmt.pix_mp.width != inst->fmt_src->fmt.pix_mp.width ||
drivers/media/platform/qcom/iris/iris_venc.c
228
f->fmt.pix_mp.height != inst->fmt_src->fmt.pix_mp.height) {
drivers/media/platform/qcom/iris/iris_venc.c
229
inst->enc_scale_width = f->fmt.pix_mp.width;
drivers/media/platform/qcom/iris/iris_venc.c
23
inst->fmt_dst = kzalloc_obj(*inst->fmt_dst);
drivers/media/platform/qcom/iris/iris_venc.c
230
inst->enc_scale_height = f->fmt.pix_mp.height;
drivers/media/platform/qcom/iris/iris_venc.c
236
fmt->fmt.pix_mp.plane_fmt[0].sizeimage = iris_get_buffer_size(inst, BUF_OUTPUT);
drivers/media/platform/qcom/iris/iris_venc.c
24
if (!inst->fmt_src || !inst->fmt_dst) {
drivers/media/platform/qcom/iris/iris_venc.c
246
inst->buffers[BUF_OUTPUT].min_count = iris_vpu_buf_count(inst, BUF_OUTPUT);
drivers/media/platform/qcom/iris/iris_venc.c
247
inst->buffers[BUF_OUTPUT].size = fmt->fmt.pix_mp.plane_fmt[0].sizeimage;
drivers/media/platform/qcom/iris/iris_venc.c
249
inst->codec = f->fmt.pix_mp.pixelformat;
drivers/media/platform/qcom/iris/iris_venc.c
25
kfree(inst->fmt_src);
drivers/media/platform/qcom/iris/iris_venc.c
255
static int iris_venc_s_fmt_input(struct iris_inst *inst, struct v4l2_format *f)
drivers/media/platform/qcom/iris/iris_venc.c
259
iris_venc_try_fmt(inst, f);
drivers/media/platform/qcom/iris/iris_venc.c
26
kfree(inst->fmt_dst);
drivers/media/platform/qcom/iris/iris_venc.c
261
if (!check_format(inst, f->fmt.pix_mp.pixelformat, f->type))
drivers/media/platform/qcom/iris/iris_venc.c
264
fmt = inst->fmt_src;
drivers/media/platform/qcom/iris/iris_venc.c
271
fmt->fmt.pix_mp.plane_fmt[0].sizeimage = iris_get_buffer_size(inst, BUF_INPUT);
drivers/media/platform/qcom/iris/iris_venc.c
278
output_fmt = inst->fmt_dst;
drivers/media/platform/qcom/iris/iris_venc.c
286
inst->buffers[BUF_INPUT].min_count = iris_vpu_buf_count(inst, BUF_INPUT);
drivers/media/platform/qcom/iris/iris_venc.c
287
inst->buffers[BUF_INPUT].size = fmt->fmt.pix_mp.plane_fmt[0].sizeimage;
drivers/media/platform/qcom/iris/iris_venc.c
289
inst->enc_raw_width = f->fmt.pix_mp.width;
drivers/media/platform/qcom/iris/iris_venc.c
290
inst->enc_raw_height = f->fmt.pix_mp.height;
drivers/media/platform/qcom/iris/iris_venc.c
291
inst->enc_scale_width = f->fmt.pix_mp.width;
drivers/media/platform/qcom/iris/iris_venc.c
292
inst->enc_scale_height = f->fmt.pix_mp.height;
drivers/media/platform/qcom/iris/iris_venc.c
294
if (f->fmt.pix_mp.width != inst->crop.width ||
drivers/media/platform/qcom/iris/iris_venc.c
295
f->fmt.pix_mp.height != inst->crop.height) {
drivers/media/platform/qcom/iris/iris_venc.c
296
inst->crop.top = 0;
drivers/media/platform/qcom/iris/iris_venc.c
297
inst->crop.left = 0;
drivers/media/platform/qcom/iris/iris_venc.c
298
inst->crop.width = fmt->fmt.pix_mp.width;
drivers/media/platform/qcom/iris/iris_venc.c
299
inst->crop.height = fmt->fmt.pix_mp.height;
drivers/media/platform/qcom/iris/iris_venc.c
30
f = inst->fmt_dst;
drivers/media/platform/qcom/iris/iris_venc.c
301
iris_venc_s_fmt_output(inst, output_fmt);
drivers/media/platform/qcom/iris/iris_venc.c
309
int iris_venc_s_fmt(struct iris_inst *inst, struct v4l2_format *f)
drivers/media/platform/qcom/iris/iris_venc.c
313
q = v4l2_m2m_get_vq(inst->m2m_ctx, f->type);
drivers/media/platform/qcom/iris/iris_venc.c
320
return iris_venc_s_fmt_input(inst, f);
drivers/media/platform/qcom/iris/iris_venc.c
322
return iris_venc_s_fmt_output(inst, f);
drivers/media/platform/qcom/iris/iris_venc.c
328
int iris_venc_validate_format(struct iris_inst *inst, u32 pixelformat)
drivers/media/platform/qcom/iris/iris_venc.c
332
supported = check_format(inst, pixelformat, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_venc.c
334
supported = check_format(inst, pixelformat, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
drivers/media/platform/qcom/iris/iris_venc.c
339
int iris_venc_subscribe_event(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_venc.c
344
return v4l2_event_subscribe(&inst->fh, sub, 0, NULL);
drivers/media/platform/qcom/iris/iris_venc.c
346
return v4l2_ctrl_subscribe_event(&inst->fh, sub);
drivers/media/platform/qcom/iris/iris_venc.c
35
inst->codec = f->fmt.pix_mp.pixelformat;
drivers/media/platform/qcom/iris/iris_venc.c
352
int iris_venc_s_selection(struct iris_inst *inst, struct v4l2_selection *s)
drivers/media/platform/qcom/iris/iris_venc.c
362
if (s->r.width > inst->fmt_src->fmt.pix_mp.width ||
drivers/media/platform/qcom/iris/iris_venc.c
363
s->r.height > inst->fmt_src->fmt.pix_mp.height)
drivers/media/platform/qcom/iris/iris_venc.c
366
inst->crop.left = s->r.left;
drivers/media/platform/qcom/iris/iris_venc.c
367
inst->crop.top = s->r.top;
drivers/media/platform/qcom/iris/iris_venc.c
368
inst->crop.width = s->r.width;
drivers/media/platform/qcom/iris/iris_venc.c
369
inst->crop.height = s->r.height;
drivers/media/platform/qcom/iris/iris_venc.c
370
inst->fmt_dst->fmt.pix_mp.width = inst->crop.width;
drivers/media/platform/qcom/iris/iris_venc.c
371
inst->fmt_dst->fmt.pix_mp.height = inst->crop.height;
drivers/media/platform/qcom/iris/iris_venc.c
372
return iris_venc_s_fmt_output(inst, inst->fmt_dst);
drivers/media/platform/qcom/iris/iris_venc.c
378
int iris_venc_s_param(struct iris_inst *inst, struct v4l2_streamparm *s_parm)
drivers/media/platform/qcom/iris/iris_venc.c
38
f->fmt.pix_mp.plane_fmt[0].sizeimage = iris_get_buffer_size(inst, BUF_OUTPUT);
drivers/media/platform/qcom/iris/iris_venc.c
380
struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
drivers/media/platform/qcom/iris/iris_venc.c
381
struct vb2_queue *src_q = v4l2_m2m_get_src_vq(inst->m2m_ctx);
drivers/media/platform/qcom/iris/iris_venc.c
382
struct vb2_queue *dst_q = v4l2_m2m_get_dst_vq(inst->m2m_ctx);
drivers/media/platform/qcom/iris/iris_venc.c
418
inst->frame_rate = fps;
drivers/media/platform/qcom/iris/iris_venc.c
420
inst->operating_rate = fps;
drivers/media/platform/qcom/iris/iris_venc.c
424
ret = iris_check_core_mbpf(inst);
drivers/media/platform/qcom/iris/iris_venc.c
427
ret = iris_check_core_mbps(inst);
drivers/media/platform/qcom/iris/iris_venc.c
437
inst->frame_rate = default_rate;
drivers/media/platform/qcom/iris/iris_venc.c
439
inst->operating_rate = default_rate;
drivers/media/platform/qcom/iris/iris_venc.c
44
inst->buffers[BUF_OUTPUT].min_count = iris_vpu_buf_count(inst, BUF_OUTPUT);
drivers/media/platform/qcom/iris/iris_venc.c
445
int iris_venc_g_param(struct iris_inst *inst, struct v4l2_streamparm *s_parm)
drivers/media/platform/qcom/iris/iris_venc.c
45
inst->buffers[BUF_OUTPUT].size = f->fmt.pix_mp.plane_fmt[0].sizeimage;
drivers/media/platform/qcom/iris/iris_venc.c
452
timeperframe->denominator = inst->operating_rate;
drivers/media/platform/qcom/iris/iris_venc.c
457
timeperframe->denominator = inst->frame_rate;
drivers/media/platform/qcom/iris/iris_venc.c
464
int iris_venc_streamon_input(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_venc.c
468
ret = iris_set_properties(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_venc.c
47
f = inst->fmt_src;
drivers/media/platform/qcom/iris/iris_venc.c
472
ret = iris_alloc_and_queue_persist_bufs(inst, BUF_ARP);
drivers/media/platform/qcom/iris/iris_venc.c
476
iris_get_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_venc.c
478
ret = iris_destroy_dequeued_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_venc.c
482
ret = iris_create_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_venc.c
486
ret = iris_queue_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_venc.c
490
return iris_process_streamon_input(inst);
drivers/media/platform/qcom/iris/iris_venc.c
493
int iris_venc_streamon_output(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_venc.c
497
ret = iris_set_properties(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
drivers/media/platform/qcom/iris/iris_venc.c
501
ret = iris_alloc_and_queue_persist_bufs(inst, BUF_ARP);
drivers/media/platform/qcom/iris/iris_venc.c
505
iris_get_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
drivers/media/platform/qcom/iris/iris_venc.c
507
ret = iris_destroy_dequeued_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
drivers/media/platform/qcom/iris/iris_venc.c
511
ret = iris_create_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
drivers/media/platform/qcom/iris/iris_venc.c
515
ret = iris_queue_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
drivers/media/platform/qcom/iris/iris_venc.c
519
ret = iris_process_streamon_output(inst);
drivers/media/platform/qcom/iris/iris_venc.c
526
iris_session_streamoff(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
drivers/media/platform/qcom/iris/iris_venc.c
531
int iris_venc_qbuf(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf)
drivers/media/platform/qcom/iris/iris_venc.c
54
f->fmt.pix_mp.plane_fmt[0].sizeimage = iris_get_buffer_size(inst, BUF_INPUT);
drivers/media/platform/qcom/iris/iris_venc.c
543
iris_set_ts_metadata(inst, vbuf);
drivers/media/platform/qcom/iris/iris_venc.c
545
q = v4l2_m2m_get_vq(inst->m2m_ctx, vb2->type);
drivers/media/platform/qcom/iris/iris_venc.c
551
iris_scale_power(inst);
drivers/media/platform/qcom/iris/iris_venc.c
553
return iris_queue_buffer(inst, buf);
drivers/media/platform/qcom/iris/iris_venc.c
556
int iris_venc_start_cmd(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_venc.c
558
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_venc.c
563
dst_vq = v4l2_m2m_get_dst_vq(inst->m2m_ctx);
drivers/media/platform/qcom/iris/iris_venc.c
565
if (inst->sub_state & IRIS_INST_SUB_DRAIN &&
drivers/media/platform/qcom/iris/iris_venc.c
566
inst->sub_state & IRIS_INST_SUB_DRAIN_LAST) {
drivers/media/platform/qcom/iris/iris_venc.c
569
if (inst->sub_state & IRIS_INST_SUB_INPUT_PAUSE) {
drivers/media/platform/qcom/iris/iris_venc.c
571
ret = hfi_ops->session_resume_drain(inst,
drivers/media/platform/qcom/iris/iris_venc.c
578
if (inst->sub_state & IRIS_INST_SUB_OUTPUT_PAUSE) {
drivers/media/platform/qcom/iris/iris_venc.c
580
ret = hfi_ops->session_resume_drain(inst,
drivers/media/platform/qcom/iris/iris_venc.c
588
dev_err(inst->core->dev, "start called before receiving last_flag\n");
drivers/media/platform/qcom/iris/iris_venc.c
589
iris_inst_change_state(inst, IRIS_INST_ERROR);
drivers/media/platform/qcom/iris/iris_venc.c
593
inst->last_buffer_dequeued = false;
drivers/media/platform/qcom/iris/iris_venc.c
595
return iris_inst_change_sub_state(inst, clear_sub_state, 0);
drivers/media/platform/qcom/iris/iris_venc.c
598
int iris_venc_stop_cmd(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_venc.c
60
inst->buffers[BUF_INPUT].min_count = iris_vpu_buf_count(inst, BUF_INPUT);
drivers/media/platform/qcom/iris/iris_venc.c
600
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_venc.c
603
ret = hfi_ops->session_drain(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_venc.c
607
ret = iris_inst_change_sub_state(inst, 0, IRIS_INST_SUB_DRAIN);
drivers/media/platform/qcom/iris/iris_venc.c
609
iris_scale_power(inst);
drivers/media/platform/qcom/iris/iris_venc.c
61
inst->buffers[BUF_INPUT].size = f->fmt.pix_mp.plane_fmt[0].sizeimage;
drivers/media/platform/qcom/iris/iris_venc.c
63
inst->crop.left = 0;
drivers/media/platform/qcom/iris/iris_venc.c
64
inst->crop.top = 0;
drivers/media/platform/qcom/iris/iris_venc.c
65
inst->crop.width = DEFAULT_WIDTH;
drivers/media/platform/qcom/iris/iris_venc.c
66
inst->crop.height = DEFAULT_HEIGHT;
drivers/media/platform/qcom/iris/iris_venc.c
68
inst->operating_rate = DEFAULT_FPS;
drivers/media/platform/qcom/iris/iris_venc.c
69
inst->frame_rate = DEFAULT_FPS;
drivers/media/platform/qcom/iris/iris_venc.c
71
inst->enc_raw_width = DEFAULT_WIDTH;
drivers/media/platform/qcom/iris/iris_venc.c
72
inst->enc_raw_height = DEFAULT_HEIGHT;
drivers/media/platform/qcom/iris/iris_venc.c
73
inst->enc_scale_width = DEFAULT_WIDTH;
drivers/media/platform/qcom/iris/iris_venc.c
74
inst->enc_scale_height = DEFAULT_HEIGHT;
drivers/media/platform/qcom/iris/iris_venc.c
76
memcpy(&inst->fw_caps[0], &core->inst_fw_caps_enc[0],
drivers/media/platform/qcom/iris/iris_venc.c
79
return iris_ctrls_init(inst);
drivers/media/platform/qcom/iris/iris_venc.c
92
static bool check_format(struct iris_inst *inst, u32 pixfmt, u32 type)
drivers/media/platform/qcom/iris/iris_venc.h
11
int iris_venc_inst_init(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_venc.h
12
int iris_venc_enum_fmt(struct iris_inst *inst, struct v4l2_fmtdesc *f);
drivers/media/platform/qcom/iris/iris_venc.h
13
int iris_venc_try_fmt(struct iris_inst *inst, struct v4l2_format *f);
drivers/media/platform/qcom/iris/iris_venc.h
14
int iris_venc_s_fmt(struct iris_inst *inst, struct v4l2_format *f);
drivers/media/platform/qcom/iris/iris_venc.h
15
int iris_venc_validate_format(struct iris_inst *inst, u32 pixelformat);
drivers/media/platform/qcom/iris/iris_venc.h
16
int iris_venc_subscribe_event(struct iris_inst *inst, const struct v4l2_event_subscription *sub);
drivers/media/platform/qcom/iris/iris_venc.h
17
int iris_venc_s_selection(struct iris_inst *inst, struct v4l2_selection *s);
drivers/media/platform/qcom/iris/iris_venc.h
18
int iris_venc_g_param(struct iris_inst *inst, struct v4l2_streamparm *s_parm);
drivers/media/platform/qcom/iris/iris_venc.h
19
int iris_venc_s_param(struct iris_inst *inst, struct v4l2_streamparm *s_parm);
drivers/media/platform/qcom/iris/iris_venc.h
20
int iris_venc_streamon_input(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_venc.h
21
int iris_venc_streamon_output(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_venc.h
22
int iris_venc_qbuf(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf);
drivers/media/platform/qcom/iris/iris_venc.h
23
int iris_venc_start_cmd(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_venc.h
24
int iris_venc_stop_cmd(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_vidc.c
105
src_vq->ops = inst->core->iris_vb2_ops;
drivers/media/platform/qcom/iris/iris_vidc.c
107
src_vq->drv_priv = inst;
drivers/media/platform/qcom/iris/iris_vidc.c
110
src_vq->dev = inst->core->dev;
drivers/media/platform/qcom/iris/iris_vidc.c
111
src_vq->lock = &inst->ctx_q_lock;
drivers/media/platform/qcom/iris/iris_vidc.c
119
dst_vq->ops = inst->core->iris_vb2_ops;
drivers/media/platform/qcom/iris/iris_vidc.c
121
dst_vq->drv_priv = inst;
drivers/media/platform/qcom/iris/iris_vidc.c
124
dst_vq->dev = inst->core->dev;
drivers/media/platform/qcom/iris/iris_vidc.c
125
dst_vq->lock = &inst->ctx_q_lock;
drivers/media/platform/qcom/iris/iris_vidc.c
134
struct iris_inst *inst;
drivers/media/platform/qcom/iris/iris_vidc.c
159
inst = core->hfi_sys_ops->sys_get_instance();
drivers/media/platform/qcom/iris/iris_vidc.c
160
if (!inst)
drivers/media/platform/qcom/iris/iris_vidc.c
163
inst->core = core;
drivers/media/platform/qcom/iris/iris_vidc.c
164
inst->domain = session_type;
drivers/media/platform/qcom/iris/iris_vidc.c
165
inst->session_id = hash32_ptr(inst);
drivers/media/platform/qcom/iris/iris_vidc.c
166
inst->state = IRIS_INST_DEINIT;
drivers/media/platform/qcom/iris/iris_vidc.c
168
mutex_init(&inst->lock);
drivers/media/platform/qcom/iris/iris_vidc.c
169
mutex_init(&inst->ctx_q_lock);
drivers/media/platform/qcom/iris/iris_vidc.c
171
INIT_LIST_HEAD(&inst->buffers[BUF_BIN].list);
drivers/media/platform/qcom/iris/iris_vidc.c
172
INIT_LIST_HEAD(&inst->buffers[BUF_ARP].list);
drivers/media/platform/qcom/iris/iris_vidc.c
173
INIT_LIST_HEAD(&inst->buffers[BUF_COMV].list);
drivers/media/platform/qcom/iris/iris_vidc.c
174
INIT_LIST_HEAD(&inst->buffers[BUF_NON_COMV].list);
drivers/media/platform/qcom/iris/iris_vidc.c
175
INIT_LIST_HEAD(&inst->buffers[BUF_LINE].list);
drivers/media/platform/qcom/iris/iris_vidc.c
176
INIT_LIST_HEAD(&inst->buffers[BUF_DPB].list);
drivers/media/platform/qcom/iris/iris_vidc.c
177
INIT_LIST_HEAD(&inst->buffers[BUF_PERSIST].list);
drivers/media/platform/qcom/iris/iris_vidc.c
178
INIT_LIST_HEAD(&inst->buffers[BUF_SCRATCH_1].list);
drivers/media/platform/qcom/iris/iris_vidc.c
179
INIT_LIST_HEAD(&inst->buffers[BUF_SCRATCH_2].list);
drivers/media/platform/qcom/iris/iris_vidc.c
180
INIT_LIST_HEAD(&inst->buffers[BUF_VPSS].list);
drivers/media/platform/qcom/iris/iris_vidc.c
181
INIT_LIST_HEAD(&inst->buffers[BUF_PARTIAL].list);
drivers/media/platform/qcom/iris/iris_vidc.c
182
init_completion(&inst->completion);
drivers/media/platform/qcom/iris/iris_vidc.c
183
init_completion(&inst->flush_completion);
drivers/media/platform/qcom/iris/iris_vidc.c
185
iris_v4l2_fh_init(inst, filp);
drivers/media/platform/qcom/iris/iris_vidc.c
187
inst->m2m_dev = v4l2_m2m_init(&iris_m2m_ops);
drivers/media/platform/qcom/iris/iris_vidc.c
188
if (IS_ERR_OR_NULL(inst->m2m_dev)) {
drivers/media/platform/qcom/iris/iris_vidc.c
193
inst->m2m_ctx = v4l2_m2m_ctx_init(inst->m2m_dev, inst, iris_m2m_queue_init);
drivers/media/platform/qcom/iris/iris_vidc.c
194
if (IS_ERR_OR_NULL(inst->m2m_ctx)) {
drivers/media/platform/qcom/iris/iris_vidc.c
199
if (inst->domain == DECODER)
drivers/media/platform/qcom/iris/iris_vidc.c
200
ret = iris_vdec_inst_init(inst);
drivers/media/platform/qcom/iris/iris_vidc.c
201
else if (inst->domain == ENCODER)
drivers/media/platform/qcom/iris/iris_vidc.c
202
ret = iris_venc_inst_init(inst);
drivers/media/platform/qcom/iris/iris_vidc.c
206
iris_add_session(inst);
drivers/media/platform/qcom/iris/iris_vidc.c
208
inst->fh.m2m_ctx = inst->m2m_ctx;
drivers/media/platform/qcom/iris/iris_vidc.c
213
v4l2_m2m_ctx_release(inst->m2m_ctx);
drivers/media/platform/qcom/iris/iris_vidc.c
215
v4l2_m2m_release(inst->m2m_dev);
drivers/media/platform/qcom/iris/iris_vidc.c
217
iris_v4l2_fh_deinit(inst, filp);
drivers/media/platform/qcom/iris/iris_vidc.c
218
mutex_destroy(&inst->ctx_q_lock);
drivers/media/platform/qcom/iris/iris_vidc.c
219
mutex_destroy(&inst->lock);
drivers/media/platform/qcom/iris/iris_vidc.c
220
kfree(inst);
drivers/media/platform/qcom/iris/iris_vidc.c
225
static void iris_session_close(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vidc.c
227
const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
drivers/media/platform/qcom/iris/iris_vidc.c
231
if (inst->state == IRIS_INST_DEINIT)
drivers/media/platform/qcom/iris/iris_vidc.c
234
reinit_completion(&inst->completion);
drivers/media/platform/qcom/iris/iris_vidc.c
236
ret = hfi_ops->session_close(inst);
drivers/media/platform/qcom/iris/iris_vidc.c
241
iris_wait_for_session_response(inst, false);
drivers/media/platform/qcom/iris/iris_vidc.c
244
static void iris_check_num_queued_internal_buffers(struct iris_inst *inst, u32 plane)
drivers/media/platform/qcom/iris/iris_vidc.c
246
const struct iris_firmware_data *firmware_data = inst->core->iris_firmware_data;
drivers/media/platform/qcom/iris/iris_vidc.c
25
static void iris_v4l2_fh_init(struct iris_inst *inst, struct file *filp)
drivers/media/platform/qcom/iris/iris_vidc.c
262
buffers = &inst->buffers[internal_buf_type[i]];
drivers/media/platform/qcom/iris/iris_vidc.c
267
dev_err(inst->core->dev, "%d buffer of type %d not released",
drivers/media/platform/qcom/iris/iris_vidc.c
27
if (inst->domain == ENCODER)
drivers/media/platform/qcom/iris/iris_vidc.c
271
if (inst->domain == DECODER)
drivers/media/platform/qcom/iris/iris_vidc.c
272
buffers = &inst->buffers[BUF_PERSIST];
drivers/media/platform/qcom/iris/iris_vidc.c
274
buffers = &inst->buffers[BUF_ARP];
drivers/media/platform/qcom/iris/iris_vidc.c
28
v4l2_fh_init(&inst->fh, inst->core->vdev_enc);
drivers/media/platform/qcom/iris/iris_vidc.c
280
dev_err(inst->core->dev, "%d buffer of type %d not released",
drivers/media/platform/qcom/iris/iris_vidc.c
281
count, inst->domain == DECODER ? BUF_PERSIST : BUF_ARP);
drivers/media/platform/qcom/iris/iris_vidc.c
286
struct iris_inst *inst = iris_get_inst(filp);
drivers/media/platform/qcom/iris/iris_vidc.c
288
v4l2_ctrl_handler_free(&inst->ctrl_handler);
drivers/media/platform/qcom/iris/iris_vidc.c
289
v4l2_m2m_ctx_release(inst->m2m_ctx);
drivers/media/platform/qcom/iris/iris_vidc.c
29
else if (inst->domain == DECODER)
drivers/media/platform/qcom/iris/iris_vidc.c
290
v4l2_m2m_release(inst->m2m_dev);
drivers/media/platform/qcom/iris/iris_vidc.c
291
mutex_lock(&inst->lock);
drivers/media/platform/qcom/iris/iris_vidc.c
292
iris_session_close(inst);
drivers/media/platform/qcom/iris/iris_vidc.c
293
iris_inst_change_state(inst, IRIS_INST_DEINIT);
drivers/media/platform/qcom/iris/iris_vidc.c
294
iris_v4l2_fh_deinit(inst, filp);
drivers/media/platform/qcom/iris/iris_vidc.c
295
iris_destroy_all_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_vidc.c
296
iris_destroy_all_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
drivers/media/platform/qcom/iris/iris_vidc.c
297
iris_check_num_queued_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
drivers/media/platform/qcom/iris/iris_vidc.c
298
iris_check_num_queued_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
drivers/media/platform/qcom/iris/iris_vidc.c
299
iris_remove_session(inst);
drivers/media/platform/qcom/iris/iris_vidc.c
30
v4l2_fh_init(&inst->fh, inst->core->vdev_dec);
drivers/media/platform/qcom/iris/iris_vidc.c
300
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/iris/iris_vidc.c
301
mutex_destroy(&inst->ctx_q_lock);
drivers/media/platform/qcom/iris/iris_vidc.c
302
mutex_destroy(&inst->lock);
drivers/media/platform/qcom/iris/iris_vidc.c
303
kfree(inst->fmt_src);
drivers/media/platform/qcom/iris/iris_vidc.c
304
kfree(inst->fmt_dst);
drivers/media/platform/qcom/iris/iris_vidc.c
305
kfree(inst);
drivers/media/platform/qcom/iris/iris_vidc.c
31
inst->fh.ctrl_handler = &inst->ctrl_handler;
drivers/media/platform/qcom/iris/iris_vidc.c
312
struct iris_inst *inst = iris_get_inst(filp);
drivers/media/platform/qcom/iris/iris_vidc.c
314
if (inst->domain == DECODER)
drivers/media/platform/qcom/iris/iris_vidc.c
315
return iris_vdec_enum_fmt(inst, f);
drivers/media/platform/qcom/iris/iris_vidc.c
316
else if (inst->domain == ENCODER)
drivers/media/platform/qcom/iris/iris_vidc.c
317
return iris_venc_enum_fmt(inst, f);
drivers/media/platform/qcom/iris/iris_vidc.c
32
v4l2_fh_add(&inst->fh, filp);
drivers/media/platform/qcom/iris/iris_vidc.c
324
struct iris_inst *inst = iris_get_inst(filp);
drivers/media/platform/qcom/iris/iris_vidc.c
327
mutex_lock(&inst->lock);
drivers/media/platform/qcom/iris/iris_vidc.c
329
if (inst->domain == DECODER)
drivers/media/platform/qcom/iris/iris_vidc.c
330
ret = iris_vdec_try_fmt(inst, f);
drivers/media/platform/qcom/iris/iris_vidc.c
331
else if (inst->domain == ENCODER)
drivers/media/platform/qcom/iris/iris_vidc.c
332
ret = iris_venc_try_fmt(inst, f);
drivers/media/platform/qcom/iris/iris_vidc.c
334
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/iris/iris_vidc.c
341
struct iris_inst *inst = iris_get_inst(filp);
drivers/media/platform/qcom/iris/iris_vidc.c
344
mutex_lock(&inst->lock);
drivers/media/platform/qcom/iris/iris_vidc.c
346
if (inst->domain == DECODER)
drivers/media/platform/qcom/iris/iris_vidc.c
347
ret = iris_vdec_s_fmt(inst, f);
drivers/media/platform/qcom/iris/iris_vidc.c
348
else if (inst->domain == ENCODER)
drivers/media/platform/qcom/iris/iris_vidc.c
349
ret = iris_venc_s_fmt(inst, f);
drivers/media/platform/qcom/iris/iris_vidc.c
35
static void iris_v4l2_fh_deinit(struct iris_inst *inst, struct file *filp)
drivers/media/platform/qcom/iris/iris_vidc.c
351
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/iris/iris_vidc.c
358
struct iris_inst *inst = iris_get_inst(filp);
drivers/media/platform/qcom/iris/iris_vidc.c
361
mutex_lock(&inst->lock);
drivers/media/platform/qcom/iris/iris_vidc.c
363
*f = *inst->fmt_src;
drivers/media/platform/qcom/iris/iris_vidc.c
365
*f = *inst->fmt_dst;
drivers/media/platform/qcom/iris/iris_vidc.c
369
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/iris/iris_vidc.c
37
v4l2_fh_del(&inst->fh, filp);
drivers/media/platform/qcom/iris/iris_vidc.c
377
struct iris_inst *inst = iris_get_inst(filp);
drivers/media/platform/qcom/iris/iris_vidc.c
38
inst->fh.ctrl_handler = NULL;
drivers/media/platform/qcom/iris/iris_vidc.c
384
if (inst->domain == DECODER)
drivers/media/platform/qcom/iris/iris_vidc.c
385
ret = iris_vdec_validate_format(inst, fsize->pixel_format);
drivers/media/platform/qcom/iris/iris_vidc.c
387
ret = iris_venc_validate_format(inst, fsize->pixel_format);
drivers/media/platform/qcom/iris/iris_vidc.c
39
v4l2_fh_exit(&inst->fh);
drivers/media/platform/qcom/iris/iris_vidc.c
392
caps = inst->core->iris_platform_data->inst_caps;
drivers/media/platform/qcom/iris/iris_vidc.c
409
struct iris_inst *inst = iris_get_inst(filp);
drivers/media/platform/qcom/iris/iris_vidc.c
410
struct iris_core *core = inst->core;
drivers/media/platform/qcom/iris/iris_vidc.c
415
if (inst->domain == DECODER)
drivers/media/platform/qcom/iris/iris_vidc.c
42
static void iris_add_session(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vidc.c
421
ret = iris_venc_validate_format(inst, fival->pixel_format);
drivers/media/platform/qcom/iris/iris_vidc.c
428
caps = inst->core->iris_platform_data->inst_caps;
drivers/media/platform/qcom/iris/iris_vidc.c
44
struct iris_core *core = inst->core;
drivers/media/platform/qcom/iris/iris_vidc.c
452
struct iris_inst *inst = iris_get_inst(filp);
drivers/media/platform/qcom/iris/iris_vidc.c
456
if (inst->domain == DECODER)
drivers/media/platform/qcom/iris/iris_vidc.c
466
struct iris_inst *inst = iris_get_inst(filp);
drivers/media/platform/qcom/iris/iris_vidc.c
469
inst->domain == DECODER)
drivers/media/platform/qcom/iris/iris_vidc.c
473
inst->domain == ENCODER)
drivers/media/platform/qcom/iris/iris_vidc.c
476
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_vidc.c
485
s->r.left = inst->crop.left;
drivers/media/platform/qcom/iris/iris_vidc.c
486
s->r.top = inst->crop.top;
drivers/media/platform/qcom/iris/iris_vidc.c
487
s->r.width = inst->crop.width;
drivers/media/platform/qcom/iris/iris_vidc.c
488
s->r.height = inst->crop.height;
drivers/media/platform/qcom/iris/iris_vidc.c
493
} else if (inst->domain == ENCODER) {
drivers/media/platform/qcom/iris/iris_vidc.c
497
s->r.width = inst->fmt_src->fmt.pix_mp.width;
drivers/media/platform/qcom/iris/iris_vidc.c
498
s->r.height = inst->fmt_src->fmt.pix_mp.height;
drivers/media/platform/qcom/iris/iris_vidc.c
501
s->r.width = inst->crop.width;
drivers/media/platform/qcom/iris/iris_vidc.c
502
s->r.height = inst->crop.height;
drivers/media/platform/qcom/iris/iris_vidc.c
507
s->r.left = inst->crop.left;
drivers/media/platform/qcom/iris/iris_vidc.c
508
s->r.top = inst->crop.top;
drivers/media/platform/qcom/iris/iris_vidc.c
516
struct iris_inst *inst = iris_get_inst(filp);
drivers/media/platform/qcom/iris/iris_vidc.c
518
if (inst->domain == DECODER)
drivers/media/platform/qcom/iris/iris_vidc.c
520
else if (inst->domain == ENCODER)
drivers/media/platform/qcom/iris/iris_vidc.c
521
return iris_venc_s_selection(inst, s);
drivers/media/platform/qcom/iris/iris_vidc.c
528
struct iris_inst *inst = container_of(fh, struct iris_inst, fh);
drivers/media/platform/qcom/iris/iris_vidc.c
530
if (inst->domain == DECODER)
drivers/media/platform/qcom/iris/iris_vidc.c
531
return iris_vdec_subscribe_event(inst, sub);
drivers/media/platform/qcom/iris/iris_vidc.c
532
else if (inst->domain == ENCODER)
drivers/media/platform/qcom/iris/iris_vidc.c
533
return iris_venc_subscribe_event(inst, sub);
drivers/media/platform/qcom/iris/iris_vidc.c
54
list_add_tail(&inst->list, &core->instances);
drivers/media/platform/qcom/iris/iris_vidc.c
540
struct iris_inst *inst = iris_get_inst(filp);
drivers/media/platform/qcom/iris/iris_vidc.c
546
if (inst->domain == ENCODER)
drivers/media/platform/qcom/iris/iris_vidc.c
547
return iris_venc_s_param(inst, a);
drivers/media/platform/qcom/iris/iris_vidc.c
554
struct iris_inst *inst = iris_get_inst(filp);
drivers/media/platform/qcom/iris/iris_vidc.c
560
if (inst->domain == ENCODER)
drivers/media/platform/qcom/iris/iris_vidc.c
561
return iris_venc_g_param(inst, a);
drivers/media/platform/qcom/iris/iris_vidc.c
569
struct iris_inst *inst = iris_get_inst(filp);
drivers/media/platform/qcom/iris/iris_vidc.c
572
mutex_lock(&inst->lock);
drivers/media/platform/qcom/iris/iris_vidc.c
579
if (inst->state == IRIS_INST_DEINIT)
drivers/media/platform/qcom/iris/iris_vidc.c
582
if (!iris_allow_cmd(inst, dec->cmd)) {
drivers/media/platform/qcom/iris/iris_vidc.c
588
ret = iris_vdec_start_cmd(inst);
drivers/media/platform/qcom/iris/iris_vidc.c
59
static void iris_remove_session(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vidc.c
590
ret = iris_vdec_stop_cmd(inst);
drivers/media/platform/qcom/iris/iris_vidc.c
595
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/iris/iris_vidc.c
603
struct iris_inst *inst = iris_get_inst(filp);
drivers/media/platform/qcom/iris/iris_vidc.c
606
mutex_lock(&inst->lock);
drivers/media/platform/qcom/iris/iris_vidc.c
61
struct iris_core *core = inst->core;
drivers/media/platform/qcom/iris/iris_vidc.c
613
if (inst->state == IRIS_INST_DEINIT)
drivers/media/platform/qcom/iris/iris_vidc.c
616
if (!iris_allow_cmd(inst, enc->cmd)) {
drivers/media/platform/qcom/iris/iris_vidc.c
622
ret = iris_venc_start_cmd(inst);
drivers/media/platform/qcom/iris/iris_vidc.c
624
ret = iris_venc_stop_cmd(inst);
drivers/media/platform/qcom/iris/iris_vidc.c
629
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/iris/iris_vidc.c
66
if (iter->session_id == inst->session_id) {
drivers/media/platform/qcom/iris/iris_vidc.c
85
struct iris_inst *inst = priv;
drivers/media/platform/qcom/iris/iris_vidc.c
86
struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
drivers/media/platform/qcom/iris/iris_vidc.c
88
v4l2_m2m_job_finish(inst->m2m_dev, m2m_ctx);
drivers/media/platform/qcom/iris/iris_vidc.c
99
struct iris_inst *inst = priv;
drivers/media/platform/qcom/iris/iris_vpu2.c
15
static u64 iris_vpu2_calc_freq(struct iris_inst *inst, size_t data_size)
drivers/media/platform/qcom/iris/iris_vpu2.c
17
struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
drivers/media/platform/qcom/iris/iris_vpu2.c
18
struct v4l2_format *inp_f = inst->fmt_src;
drivers/media/platform/qcom/iris/iris_vpu2.c
21
u32 fps = inst->frame_rate;
drivers/media/platform/qcom/iris/iris_vpu2.c
23
width = max(inp_f->fmt.pix_mp.width, inst->crop.width);
drivers/media/platform/qcom/iris/iris_vpu2.c
24
height = max(inp_f->fmt.pix_mp.height, inst->crop.height);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1000
static u32 iris_vpu_dec_partial_size(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1002
struct v4l2_format *f = inst->fmt_src;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1030
static u32 iris_vpu_enc_comv_size(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1032
u32 height = iris_vpu_enc_get_bitstream_height(inst);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1033
u32 width = iris_vpu_enc_get_bitstream_width(inst);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1034
u32 num_recon = hfi_buffer_get_recon_count(inst);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1037
codec = (inst->codec == V4L2_PIX_FMT_HEVC) ?
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1039
lcu_size = (inst->codec == V4L2_PIX_FMT_HEVC) ? 32 : 16;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1307
static u32 iris_vpu_enc_non_comv_size(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1309
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1310
u32 height = iris_vpu_enc_get_bitstream_height(inst);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1311
u32 width = iris_vpu_enc_get_bitstream_width(inst);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1314
if (inst->codec == V4L2_PIX_FMT_HEVC) {
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1399
static u32 iris_vpu_enc_line_size(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1401
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1402
u32 height = iris_vpu_enc_get_bitstream_height(inst);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1403
u32 width = iris_vpu_enc_get_bitstream_width(inst);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1406
if (inst->codec == V4L2_PIX_FMT_HEVC) {
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1416
static u32 iris_vpu33_enc_line_size(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1418
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1419
u32 height = iris_vpu_enc_get_bitstream_height(inst);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1420
u32 width = iris_vpu_enc_get_bitstream_width(inst);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1423
if (inst->codec == V4L2_PIX_FMT_HEVC) {
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1473
static u32 iris_vpu_enc_arp_size(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1478
inline bool is_scaling_enabled(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1480
struct v4l2_pix_format_mplane *dst_fmt = &inst->fmt_dst->fmt.pix_mp;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1481
struct v4l2_pix_format_mplane *src_fmt = &inst->fmt_src->fmt.pix_mp;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1638
static u32 iris_vpu_enc_scratch1_size(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1640
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1641
u32 frame_height = iris_vpu_enc_get_bitstream_height(inst);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1642
u32 frame_width = iris_vpu_enc_get_bitstream_width(inst);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1647
if (inst->codec == V4L2_PIX_FMT_H264) {
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1650
} else if (inst->codec == V4L2_PIX_FMT_HEVC) {
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1736
static u32 iris_vpu_enc_scratch2_size(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1738
u32 frame_height = iris_vpu_enc_get_bitstream_height(inst);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1739
u32 frame_width = iris_vpu_enc_get_bitstream_width(inst);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1740
u32 num_ref = hfi_buffer_get_recon_count(inst);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1745
static u32 iris_vpu_enc_vpss_size(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1747
u32 ds_enable = is_scaling_enabled(inst);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1748
struct v4l2_format *f = inst->fmt_dst;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1817
static u32 iris_vpu4x_dec_line_size(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1819
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1820
u32 out_min_count = inst->buffers[BUF_OUTPUT].min_count;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1821
struct v4l2_format *f = inst->fmt_src;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1826
if (iris_split_mode_enabled(inst))
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1829
if (inst->codec == V4L2_PIX_FMT_H264)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1831
else if (inst->codec == V4L2_PIX_FMT_HEVC)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1833
else if (inst->codec == V4L2_PIX_FMT_VP9)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1859
static u32 iris_vpu4x_dec_persist_size(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1861
if (inst->codec == V4L2_PIX_FMT_H264)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1863
else if (inst->codec == V4L2_PIX_FMT_HEVC)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
1865
else if (inst->codec == V4L2_PIX_FMT_VP9)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2041
static u32 iris_vpu4x_enc_line_size(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2043
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2044
u32 lcu_size = inst->codec == V4L2_PIX_FMT_HEVC ? 32 : 16;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2045
struct v4l2_format *f = inst->fmt_dst;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2050
lcu_size, inst->codec);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2053
static int output_min_count(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2058
if (inst->fw_min_count) {
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2059
if (iris_split_mode_enabled(inst) &&
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2060
(inst->codec == V4L2_PIX_FMT_VP9 ||
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2061
inst->codec == V4L2_PIX_FMT_AV1))
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2062
return min_t(u32, 4, inst->fw_min_count);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2064
return inst->fw_min_count;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2067
if (inst->codec == V4L2_PIX_FMT_VP9)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2069
else if (inst->codec == V4L2_PIX_FMT_AV1)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2077
u32 (*handle)(struct iris_inst *inst);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2080
u32 iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2107
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2110
} else if (inst->domain == ENCODER) {
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2117
size = buf_type_handle_arr[i].handle(inst);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2125
u32 iris_vpu33_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2140
if (inst->domain == DECODER)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2141
return iris_vpu_buf_size(inst, buffer_type);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2145
size = enc_internal_buf_type_handle[i].handle(inst);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2153
u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2179
if (inst->domain == DECODER) {
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2182
} else if (inst->domain == ENCODER) {
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2189
size = buf_type_handle_arr[i].handle(inst);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2197
static u32 internal_buffer_count(struct iris_inst *inst,
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2204
if (inst->codec == V4L2_PIX_FMT_H264 ||
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2205
inst->codec == V4L2_PIX_FMT_HEVC ||
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2206
inst->codec == V4L2_PIX_FMT_AV1)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2213
static inline int iris_vpu_dpb_count(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2215
if (inst->codec == V4L2_PIX_FMT_AV1)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2218
if (iris_split_mode_enabled(inst)) {
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2219
return inst->fw_min_count ?
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2220
inst->fw_min_count : inst->buffers[BUF_OUTPUT].min_count;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2226
int iris_vpu_buf_count(struct iris_inst *inst, enum iris_buffer_type buffer_type)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2232
if (inst->domain == ENCODER)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2235
return output_min_count(inst);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2237
if (inst->codec == V4L2_PIX_FMT_AV1)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2245
return internal_buffer_count(inst, buffer_type);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
2253
return iris_vpu_dpb_count(inst);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
708
static u32 iris_vpu_dec_bin_size(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
710
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
711
struct v4l2_format *f = inst->fmt_src;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
715
if (inst->codec == V4L2_PIX_FMT_H264)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
717
else if (inst->codec == V4L2_PIX_FMT_HEVC)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
719
else if (inst->codec == V4L2_PIX_FMT_VP9)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
721
else if (inst->codec == V4L2_PIX_FMT_AV1)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
727
static u32 iris_vpu_dec_comv_size(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
730
struct v4l2_format *f = inst->fmt_src;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
734
if (inst->codec == V4L2_PIX_FMT_H264)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
736
else if (inst->codec == V4L2_PIX_FMT_HEVC)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
742
static u32 iris_vpu3x_4x_dec_comv_size(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
744
u32 num_comv = inst->buffers[BUF_OUTPUT].min_count;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
745
struct v4l2_format *f = inst->fmt_src;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
749
if (inst->fw_min_count)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
750
num_comv = inst->fw_min_count;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
752
if (inst->codec == V4L2_PIX_FMT_H264)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
754
else if (inst->codec == V4L2_PIX_FMT_HEVC)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
756
else if (inst->codec == V4L2_PIX_FMT_AV1) {
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
757
if (inst->fw_caps[DRAP].value)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
766
static u32 iris_vpu_dec_persist_size(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
770
if (inst->codec == V4L2_PIX_FMT_H264)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
772
else if (inst->codec == V4L2_PIX_FMT_HEVC)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
774
else if (inst->codec == V4L2_PIX_FMT_VP9)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
776
else if (inst->codec == V4L2_PIX_FMT_AV1) {
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
777
caps = inst->core->iris_platform_data->inst_caps;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
778
if (inst->fw_caps[DRAP].value)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
788
static u32 iris_vpu_dec_dpb_size(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
790
if (iris_split_mode_enabled(inst))
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
791
return iris_get_buffer_size(inst, BUF_DPB);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
796
static u32 iris_vpu_dec_non_comv_size(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
798
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
799
struct v4l2_format *f = inst->fmt_src;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
803
if (inst->codec == V4L2_PIX_FMT_H264)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
805
else if (inst->codec == V4L2_PIX_FMT_HEVC)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
811
static u32 iris_vpu_dec_line_size(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
813
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
814
struct v4l2_format *f = inst->fmt_src;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
818
u32 out_min_count = inst->buffers[BUF_OUTPUT].min_count;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
820
if (iris_split_mode_enabled(inst))
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
823
if (inst->codec == V4L2_PIX_FMT_H264)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
825
else if (inst->codec == V4L2_PIX_FMT_HEVC)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
827
else if (inst->codec == V4L2_PIX_FMT_VP9)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
830
else if (inst->codec == V4L2_PIX_FMT_AV1)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
836
static u32 iris_vpu_dec_scratch1_size(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
838
return iris_vpu_dec_comv_size(inst) +
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
839
iris_vpu_dec_non_comv_size(inst) +
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
840
iris_vpu_dec_line_size(inst);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
843
static inline u32 iris_vpu_enc_get_bitstream_width(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
845
if (is_rotation_90_or_270(inst))
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
846
return inst->fmt_dst->fmt.pix_mp.height;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
848
return inst->fmt_dst->fmt.pix_mp.width;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
851
static inline u32 iris_vpu_enc_get_bitstream_height(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
853
if (is_rotation_90_or_270(inst))
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
854
return inst->fmt_dst->fmt.pix_mp.width;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
856
return inst->fmt_dst->fmt.pix_mp.height;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
938
static u32 iris_vpu_enc_bin_size(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
940
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
941
u32 height = iris_vpu_enc_get_bitstream_height(inst);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
942
u32 width = iris_vpu_enc_get_bitstream_width(inst);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
943
u32 stage = inst->fw_caps[STAGE].value;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
946
if (inst->codec == V4L2_PIX_FMT_HEVC)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
952
num_vpp_pipes, inst->hfi_rc_type);
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
955
static inline u32 hfi_buffer_get_recon_count(struct iris_inst *inst)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
957
u32 layer_count = inst->hfi_layer_count;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
958
u32 layer_type = inst->hfi_layer_type;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
962
bframe_count = inst->fw_caps[B_FRAME].value;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
963
ltr_count = inst->fw_caps[LTR_COUNT].value;
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
973
if (inst->codec == V4L2_PIX_FMT_HEVC)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
975
else if (inst->codec == V4L2_PIX_FMT_H264 && layer_count < 4)
drivers/media/platform/qcom/iris/iris_vpu_buffer.c
991
if (inst->codec == V4L2_PIX_FMT_HEVC)
drivers/media/platform/qcom/iris/iris_vpu_buffer.h
288
u32 iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
drivers/media/platform/qcom/iris/iris_vpu_buffer.h
289
u32 iris_vpu33_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
drivers/media/platform/qcom/iris/iris_vpu_buffer.h
290
u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
drivers/media/platform/qcom/iris/iris_vpu_buffer.h
291
int iris_vpu_buf_count(struct iris_inst *inst, enum iris_buffer_type buffer_type);
drivers/media/platform/qcom/iris/iris_vpu_common.c
423
u64 iris_vpu3x_vpu4x_calculate_frequency(struct iris_inst *inst, size_t data_size)
drivers/media/platform/qcom/iris/iris_vpu_common.c
425
struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
drivers/media/platform/qcom/iris/iris_vpu_common.c
426
struct v4l2_format *inp_f = inst->fmt_src;
drivers/media/platform/qcom/iris/iris_vpu_common.c
430
u32 fps = inst->frame_rate;
drivers/media/platform/qcom/iris/iris_vpu_common.c
432
width = max(inp_f->fmt.pix_mp.width, inst->crop.width);
drivers/media/platform/qcom/iris/iris_vpu_common.c
433
height = max(inp_f->fmt.pix_mp.height, inst->crop.height);
drivers/media/platform/qcom/iris/iris_vpu_common.c
441
vpp_cycles = mult_frac(mbs_per_second, caps->mb_cycles_vpp, (u32)inst->fw_caps[PIPE].value);
drivers/media/platform/qcom/iris/iris_vpu_common.c
446
if (inst->fw_caps[PIPE].value > 1)
drivers/media/platform/qcom/iris/iris_vpu_common.c
450
if (inst->fw_caps[STAGE].value == STAGE_2)
drivers/media/platform/qcom/iris/iris_vpu_common.c
458
if (inst->fw_caps[STAGE].value == STAGE_1)
drivers/media/platform/qcom/iris/iris_vpu_common.h
23
u64 (*calc_freq)(struct iris_inst *inst, size_t data_size);
drivers/media/platform/qcom/iris/iris_vpu_common.h
43
u64 iris_vpu3x_vpu4x_calculate_frequency(struct iris_inst *inst, size_t data_size);
drivers/media/platform/qcom/venus/core.c
211
struct venus_inst *inst;
drivers/media/platform/qcom/venus/core.c
219
inst = kzalloc_obj(*inst);
drivers/media/platform/qcom/venus/core.c
220
if (!inst)
drivers/media/platform/qcom/venus/core.c
223
mutex_init(&inst->lock);
drivers/media/platform/qcom/venus/core.c
224
inst->core = core;
drivers/media/platform/qcom/venus/core.c
225
inst->session_type = type;
drivers/media/platform/qcom/venus/core.c
231
ret = hfi_session_create(inst, &dummy_ops);
drivers/media/platform/qcom/venus/core.c
240
ret = hfi_session_init(inst, to_v4l2_codec_type(codec));
drivers/media/platform/qcom/venus/core.c
244
ret = hfi_session_deinit(inst);
drivers/media/platform/qcom/venus/core.c
250
hfi_session_destroy(inst);
drivers/media/platform/qcom/venus/core.c
252
mutex_destroy(&inst->lock);
drivers/media/platform/qcom/venus/core.c
253
kfree(inst);
drivers/media/platform/qcom/venus/core.c
61
struct venus_inst *inst;
drivers/media/platform/qcom/venus/core.c
615
void venus_close_common(struct venus_inst *inst, struct file *filp)
drivers/media/platform/qcom/venus/core.c
621
synchronize_irq(inst->core->irq);
drivers/media/platform/qcom/venus/core.c
623
v4l2_m2m_ctx_release(inst->m2m_ctx);
drivers/media/platform/qcom/venus/core.c
624
v4l2_m2m_release(inst->m2m_dev);
drivers/media/platform/qcom/venus/core.c
625
hfi_session_destroy(inst);
drivers/media/platform/qcom/venus/core.c
626
v4l2_fh_del(&inst->fh, filp);
drivers/media/platform/qcom/venus/core.c
627
v4l2_fh_exit(&inst->fh);
drivers/media/platform/qcom/venus/core.c
628
v4l2_ctrl_handler_free(&inst->ctrl_handler);
drivers/media/platform/qcom/venus/core.c
630
mutex_destroy(&inst->lock);
drivers/media/platform/qcom/venus/core.c
631
mutex_destroy(&inst->ctx_q_lock);
drivers/media/platform/qcom/venus/core.c
74
list_for_each_entry(inst, &core->instances, list)
drivers/media/platform/qcom/venus/core.c
75
inst->ops->event_notify(inst, EVT_SESSION_ERROR, NULL);
drivers/media/platform/qcom/venus/core.h
601
void venus_close_common(struct venus_inst *inst, struct file *filp);
drivers/media/platform/qcom/venus/helpers.c
103
int venus_helper_queue_dpb_bufs(struct venus_inst *inst)
drivers/media/platform/qcom/venus/helpers.c
109
if (inst->dpb_buftype == HFI_BUFFER_OUTPUT)
drivers/media/platform/qcom/venus/helpers.c
110
dpb_size = inst->output_buf_size;
drivers/media/platform/qcom/venus/helpers.c
111
else if (inst->dpb_buftype == HFI_BUFFER_OUTPUT2)
drivers/media/platform/qcom/venus/helpers.c
112
dpb_size = inst->output2_buf_size;
drivers/media/platform/qcom/venus/helpers.c
1123
int venus_helper_set_input_resolution(struct venus_inst *inst,
drivers/media/platform/qcom/venus/helpers.c
1133
return hfi_session_set_property(inst, ptype, &fs);
drivers/media/platform/qcom/venus/helpers.c
1137
int venus_helper_set_output_resolution(struct venus_inst *inst,
drivers/media/platform/qcom/venus/helpers.c
114
list_for_each_entry_safe(buf, next, &inst->dpbbufs, list) {
drivers/media/platform/qcom/venus/helpers.c
1148
return hfi_session_set_property(inst, ptype, &fs);
drivers/media/platform/qcom/venus/helpers.c
1152
static u32 venus_helper_get_work_mode(struct venus_inst *inst)
drivers/media/platform/qcom/venus/helpers.c
1158
if (inst->session_type == VIDC_SESSION_TYPE_DEC) {
drivers/media/platform/qcom/venus/helpers.c
1159
num_mbs = (ALIGN(inst->height, 16) * ALIGN(inst->width, 16)) / 256;
drivers/media/platform/qcom/venus/helpers.c
1160
if (inst->hfi_codec == HFI_VIDEO_CODEC_MPEG2 ||
drivers/media/platform/qcom/venus/helpers.c
1161
inst->pic_struct != HFI_INTERLACE_FRAME_PROGRESSIVE ||
drivers/media/platform/qcom/venus/helpers.c
1165
num_mbs = (ALIGN(inst->out_height, 16) * ALIGN(inst->out_width, 16)) / 256;
drivers/media/platform/qcom/venus/helpers.c
1166
if (inst->hfi_codec == HFI_VIDEO_CODEC_VP8 &&
drivers/media/platform/qcom/venus/helpers.c
1174
int venus_helper_set_work_mode(struct venus_inst *inst)
drivers/media/platform/qcom/venus/helpers.c
1180
if (!IS_V4(inst->core) && !IS_V6(inst->core))
drivers/media/platform/qcom/venus/helpers.c
1183
mode = venus_helper_get_work_mode(inst);
drivers/media/platform/qcom/venus/helpers.c
1185
return hfi_session_set_property(inst, ptype, &wm);
drivers/media/platform/qcom/venus/helpers.c
1189
int venus_helper_set_format_constraints(struct venus_inst *inst)
drivers/media/platform/qcom/venus/helpers.c
1194
if (!IS_V6(inst->core))
drivers/media/platform/qcom/venus/helpers.c
1197
if (inst->opb_fmt == HFI_COLOR_FORMAT_NV12_UBWC ||
drivers/media/platform/qcom/venus/helpers.c
1198
inst->opb_fmt == HFI_COLOR_FORMAT_YUV420_TP10_UBWC)
drivers/media/platform/qcom/venus/helpers.c
1213
return hfi_session_set_property(inst, ptype, &pconstraint);
drivers/media/platform/qcom/venus/helpers.c
1217
int venus_helper_set_num_bufs(struct venus_inst *inst, unsigned int input_bufs,
drivers/media/platform/qcom/venus/helpers.c
1228
ret = hfi_session_set_property(inst, ptype, &buf_count);
drivers/media/platform/qcom/venus/helpers.c
1235
ret = hfi_session_set_property(inst, ptype, &buf_count);
drivers/media/platform/qcom/venus/helpers.c
1243
ret = hfi_session_set_property(inst, ptype, &buf_count);
drivers/media/platform/qcom/venus/helpers.c
1250
int venus_helper_set_raw_format(struct venus_inst *inst, u32 hfi_format,
drivers/media/platform/qcom/venus/helpers.c
1259
return hfi_session_set_property(inst, ptype, &fmt);
drivers/media/platform/qcom/venus/helpers.c
1263
int venus_helper_set_color_format(struct venus_inst *inst, u32 pixfmt)
drivers/media/platform/qcom/venus/helpers.c
1267
if (inst->session_type == VIDC_SESSION_TYPE_DEC)
drivers/media/platform/qcom/venus/helpers.c
1269
else if (inst->session_type == VIDC_SESSION_TYPE_ENC)
drivers/media/platform/qcom/venus/helpers.c
127
free_dpb_buf(inst, buf);
drivers/media/platform/qcom/venus/helpers.c
1278
return venus_helper_set_raw_format(inst, hfi_format, buftype);
drivers/media/platform/qcom/venus/helpers.c
1282
int venus_helper_set_multistream(struct venus_inst *inst, bool out_en,
drivers/media/platform/qcom/venus/helpers.c
1292
ret = hfi_session_set_property(inst, ptype, &multi);
drivers/media/platform/qcom/venus/helpers.c
1299
return hfi_session_set_property(inst, ptype, &multi);
drivers/media/platform/qcom/venus/helpers.c
1303
int venus_helper_set_dyn_bufmode(struct venus_inst *inst)
drivers/media/platform/qcom/venus/helpers.c
1309
if (!is_dynamic_bufmode(inst))
drivers/media/platform/qcom/venus/helpers.c
1315
ret = hfi_session_set_property(inst, ptype, &mode);
drivers/media/platform/qcom/venus/helpers.c
1321
return hfi_session_set_property(inst, ptype, &mode);
drivers/media/platform/qcom/venus/helpers.c
1325
int venus_helper_set_bufsize(struct venus_inst *inst, u32 bufsize, u32 buftype)
drivers/media/platform/qcom/venus/helpers.c
133
ret = hfi_session_process_buf(inst, &fdata);
drivers/media/platform/qcom/venus/helpers.c
1333
return hfi_session_set_property(inst, ptype, &bufsz);
drivers/media/platform/qcom/venus/helpers.c
1337
unsigned int venus_helper_get_opb_size(struct venus_inst *inst)
drivers/media/platform/qcom/venus/helpers.c
1340
if (inst->session_type == VIDC_SESSION_TYPE_ENC)
drivers/media/platform/qcom/venus/helpers.c
1341
return inst->output_buf_size;
drivers/media/platform/qcom/venus/helpers.c
1343
if (inst->opb_buftype == HFI_BUFFER_OUTPUT)
drivers/media/platform/qcom/venus/helpers.c
1344
return inst->output_buf_size;
drivers/media/platform/qcom/venus/helpers.c
1345
else if (inst->opb_buftype == HFI_BUFFER_OUTPUT2)
drivers/media/platform/qcom/venus/helpers.c
1346
return inst->output2_buf_size;
drivers/media/platform/qcom/venus/helpers.c
1355
struct venus_inst *inst;
drivers/media/platform/qcom/venus/helpers.c
1358
inst = container_of(work, struct venus_inst, delayed_process_work);
drivers/media/platform/qcom/venus/helpers.c
1360
mutex_lock(&inst->lock);
drivers/media/platform/qcom/venus/helpers.c
1362
if (!(inst->streamon_out & inst->streamon_cap))
drivers/media/platform/qcom/venus/helpers.c
1365
list_for_each_entry_safe(buf, n, &inst->delayed_process, ref_list) {
drivers/media/platform/qcom/venus/helpers.c
1369
ret = session_process_buf(inst, &buf->vb);
drivers/media/platform/qcom/venus/helpers.c
1371
return_buf_error(inst, &buf->vb);
drivers/media/platform/qcom/venus/helpers.c
1376
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/helpers.c
1379
void venus_helper_release_buf_ref(struct venus_inst *inst, unsigned int idx)
drivers/media/platform/qcom/venus/helpers.c
1383
list_for_each_entry(buf, &inst->registeredbufs, reg_list) {
drivers/media/platform/qcom/venus/helpers.c
1386
schedule_work(&inst->delayed_process_work);
drivers/media/platform/qcom/venus/helpers.c
1401
static int is_buf_refed(struct venus_inst *inst, struct vb2_v4l2_buffer *vbuf)
drivers/media/platform/qcom/venus/helpers.c
1406
list_add_tail(&buf->ref_list, &inst->delayed_process);
drivers/media/platform/qcom/venus/helpers.c
1407
schedule_work(&inst->delayed_process_work);
drivers/media/platform/qcom/venus/helpers.c
1415
venus_helper_find_buf(struct venus_inst *inst, unsigned int type, u32 idx)
drivers/media/platform/qcom/venus/helpers.c
1417
struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
drivers/media/platform/qcom/venus/helpers.c
1426
void venus_helper_change_dpb_owner(struct venus_inst *inst,
drivers/media/platform/qcom/venus/helpers.c
1433
buf_type != inst->dpb_buftype)
drivers/media/platform/qcom/venus/helpers.c
1436
list_for_each_entry(dpb_buf, &inst->dpbbufs, list)
drivers/media/platform/qcom/venus/helpers.c
1446
struct venus_inst *inst = vb2_get_drv_priv(vb->vb2_queue);
drivers/media/platform/qcom/venus/helpers.c
145
int venus_helper_free_dpb_bufs(struct venus_inst *inst)
drivers/media/platform/qcom/venus/helpers.c
1454
list_add_tail(&buf->reg_list, &inst->registeredbufs);
drivers/media/platform/qcom/venus/helpers.c
1462
struct venus_inst *inst = vb2_get_drv_priv(vb->vb2_queue);
drivers/media/platform/qcom/venus/helpers.c
1463
unsigned int out_buf_size = venus_helper_get_opb_size(inst);
drivers/media/platform/qcom/venus/helpers.c
1470
dev_err(inst->core->dev, "%s field isn't supported\n",
drivers/media/platform/qcom/venus/helpers.c
1480
vb2_plane_size(vb, 0) < inst->input_buf_size)
drivers/media/platform/qcom/venus/helpers.c
1487
static void cache_payload(struct venus_inst *inst, struct vb2_buffer *vb)
drivers/media/platform/qcom/venus/helpers.c
149
list_for_each_entry_safe(buf, n, &inst->dpbbufs, list) {
drivers/media/platform/qcom/venus/helpers.c
1493
inst->payloads[idx] = vb2_get_plane_payload(vb, 0);
drivers/media/platform/qcom/venus/helpers.c
1499
struct venus_inst *inst = vb2_get_drv_priv(vb->vb2_queue);
drivers/media/platform/qcom/venus/helpers.c
1500
struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
drivers/media/platform/qcom/venus/helpers.c
1506
if (inst->session_type == VIDC_SESSION_TYPE_DEC &&
drivers/media/platform/qcom/venus/helpers.c
1508
inst->codec_state == VENUS_DEC_STATE_DRC)
drivers/media/platform/qcom/venus/helpers.c
1511
cache_payload(inst, vb);
drivers/media/platform/qcom/venus/helpers.c
1513
if (inst->session_type == VIDC_SESSION_TYPE_ENC &&
drivers/media/platform/qcom/venus/helpers.c
1514
!(inst->streamon_out && inst->streamon_cap))
drivers/media/platform/qcom/venus/helpers.c
1518
ret = is_buf_refed(inst, vbuf);
drivers/media/platform/qcom/venus/helpers.c
152
free_dpb_buf(inst, buf);
drivers/media/platform/qcom/venus/helpers.c
1522
ret = session_process_buf(inst, vbuf);
drivers/media/platform/qcom/venus/helpers.c
1524
return_buf_error(inst, vbuf);
drivers/media/platform/qcom/venus/helpers.c
1529
void venus_helper_buffers_done(struct venus_inst *inst, unsigned int type,
drivers/media/platform/qcom/venus/helpers.c
1535
while ((buf = v4l2_m2m_src_buf_remove(inst->m2m_ctx)))
drivers/media/platform/qcom/venus/helpers.c
1538
while ((buf = v4l2_m2m_dst_buf_remove(inst->m2m_ctx)))
drivers/media/platform/qcom/venus/helpers.c
1546
struct venus_inst *inst = vb2_get_drv_priv(q);
drivers/media/platform/qcom/venus/helpers.c
1547
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/helpers.c
155
if (list_empty(&inst->dpbbufs))
drivers/media/platform/qcom/venus/helpers.c
1550
mutex_lock(&inst->lock);
drivers/media/platform/qcom/venus/helpers.c
1552
if (inst->streamon_out & inst->streamon_cap) {
drivers/media/platform/qcom/venus/helpers.c
1553
ret = hfi_session_stop(inst);
drivers/media/platform/qcom/venus/helpers.c
1554
ret |= hfi_session_unload_res(inst);
drivers/media/platform/qcom/venus/helpers.c
1555
ret |= venus_helper_unregister_bufs(inst);
drivers/media/platform/qcom/venus/helpers.c
1556
ret |= venus_helper_intbufs_free(inst);
drivers/media/platform/qcom/venus/helpers.c
1557
ret |= hfi_session_deinit(inst);
drivers/media/platform/qcom/venus/helpers.c
1559
if (inst->session_error || test_bit(0, &core->sys_error))
drivers/media/platform/qcom/venus/helpers.c
156
INIT_LIST_HEAD(&inst->dpbbufs);
drivers/media/platform/qcom/venus/helpers.c
1563
hfi_session_abort(inst);
drivers/media/platform/qcom/venus/helpers.c
1565
venus_helper_free_dpb_bufs(inst);
drivers/media/platform/qcom/venus/helpers.c
1567
venus_pm_load_scale(inst);
drivers/media/platform/qcom/venus/helpers.c
1568
INIT_LIST_HEAD(&inst->registeredbufs);
drivers/media/platform/qcom/venus/helpers.c
1571
venus_helper_buffers_done(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
drivers/media/platform/qcom/venus/helpers.c
1573
venus_helper_buffers_done(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
drivers/media/platform/qcom/venus/helpers.c
1577
inst->streamon_out = 0;
drivers/media/platform/qcom/venus/helpers.c
1579
inst->streamon_cap = 0;
drivers/media/platform/qcom/venus/helpers.c
1581
venus_pm_release_core(inst);
drivers/media/platform/qcom/venus/helpers.c
1583
inst->session_error = 0;
drivers/media/platform/qcom/venus/helpers.c
1585
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/helpers.c
1589
void venus_helper_vb2_queue_error(struct venus_inst *inst)
drivers/media/platform/qcom/venus/helpers.c
1591
struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
drivers/media/platform/qcom/venus/helpers.c
1601
int venus_helper_process_initial_cap_bufs(struct venus_inst *inst)
drivers/media/platform/qcom/venus/helpers.c
1603
struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
drivers/media/platform/qcom/venus/helpers.c
1608
ret = session_process_buf(inst, &buf->vb);
drivers/media/platform/qcom/venus/helpers.c
1610
return_buf_error(inst, &buf->vb);
drivers/media/platform/qcom/venus/helpers.c
1619
int venus_helper_process_initial_out_bufs(struct venus_inst *inst)
drivers/media/platform/qcom/venus/helpers.c
162
int venus_helper_alloc_dpb_bufs(struct venus_inst *inst)
drivers/media/platform/qcom/venus/helpers.c
1621
struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
drivers/media/platform/qcom/venus/helpers.c
1626
ret = session_process_buf(inst, &buf->vb);
drivers/media/platform/qcom/venus/helpers.c
1628
return_buf_error(inst, &buf->vb);
drivers/media/platform/qcom/venus/helpers.c
1637
int venus_helper_vb2_start_streaming(struct venus_inst *inst)
drivers/media/platform/qcom/venus/helpers.c
164
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/helpers.c
1641
ret = venus_helper_intbufs_alloc(inst);
drivers/media/platform/qcom/venus/helpers.c
1645
ret = session_register_bufs(inst);
drivers/media/platform/qcom/venus/helpers.c
1649
venus_pm_load_scale(inst);
drivers/media/platform/qcom/venus/helpers.c
1651
ret = hfi_session_load_res(inst);
drivers/media/platform/qcom/venus/helpers.c
1655
ret = hfi_session_start(inst);
drivers/media/platform/qcom/venus/helpers.c
1662
hfi_session_unload_res(inst);
drivers/media/platform/qcom/venus/helpers.c
1664
venus_helper_unregister_bufs(inst);
drivers/media/platform/qcom/venus/helpers.c
1666
venus_helper_intbufs_free(inst);
drivers/media/platform/qcom/venus/helpers.c
1673
struct venus_inst *inst = priv;
drivers/media/platform/qcom/venus/helpers.c
1674
struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
drivers/media/platform/qcom/venus/helpers.c
1678
mutex_lock(&inst->lock);
drivers/media/platform/qcom/venus/helpers.c
168
u32 buftype = inst->dpb_buftype;
drivers/media/platform/qcom/venus/helpers.c
1681
ret = session_process_buf(inst, &buf->vb);
drivers/media/platform/qcom/venus/helpers.c
1683
return_buf_error(inst, &buf->vb);
drivers/media/platform/qcom/venus/helpers.c
1687
ret = session_process_buf(inst, &buf->vb);
drivers/media/platform/qcom/venus/helpers.c
1689
return_buf_error(inst, &buf->vb);
drivers/media/platform/qcom/venus/helpers.c
1692
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/helpers.c
1698
struct venus_inst *inst = priv;
drivers/media/platform/qcom/venus/helpers.c
1700
v4l2_m2m_job_finish(inst->m2m_dev, inst->m2m_ctx);
drivers/media/platform/qcom/venus/helpers.c
1704
int venus_helper_session_init(struct venus_inst *inst)
drivers/media/platform/qcom/venus/helpers.c
1706
enum hfi_version version = inst->core->res->hfi_version;
drivers/media/platform/qcom/venus/helpers.c
1707
u32 session_type = inst->session_type;
drivers/media/platform/qcom/venus/helpers.c
1711
codec = inst->session_type == VIDC_SESSION_TYPE_DEC ?
drivers/media/platform/qcom/venus/helpers.c
1712
inst->fmt_out->pixfmt : inst->fmt_cap->pixfmt;
drivers/media/platform/qcom/venus/helpers.c
1714
ret = hfi_session_init(inst, codec);
drivers/media/platform/qcom/venus/helpers.c
1718
inst->clk_data.vpp_freq = hfi_platform_get_codec_vpp_freq(inst->core,
drivers/media/platform/qcom/venus/helpers.c
1722
inst->clk_data.vsp_freq = hfi_platform_get_codec_vsp_freq(inst->core,
drivers/media/platform/qcom/venus/helpers.c
1726
inst->clk_data.low_power_freq = hfi_platform_get_codec_lp_freq(inst->core,
drivers/media/platform/qcom/venus/helpers.c
1735
void venus_helper_init_instance(struct venus_inst *inst)
drivers/media/platform/qcom/venus/helpers.c
1737
if (inst->session_type == VIDC_SESSION_TYPE_DEC) {
drivers/media/platform/qcom/venus/helpers.c
1738
INIT_LIST_HEAD(&inst->delayed_process);
drivers/media/platform/qcom/venus/helpers.c
1739
INIT_WORK(&inst->delayed_process_work,
drivers/media/platform/qcom/venus/helpers.c
1758
int venus_helper_get_out_fmts(struct venus_inst *inst, u32 v4l2_fmt,
drivers/media/platform/qcom/venus/helpers.c
1761
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/helpers.c
177
if (!inst->dpb_fmt)
drivers/media/platform/qcom/venus/helpers.c
1771
caps = venus_caps_by_codec(core, inst->hfi_codec, inst->session_type);
drivers/media/platform/qcom/venus/helpers.c
1775
if (inst->bit_depth == VIDC_BITDEPTH_10 && inst->session_type == VIDC_SESSION_TYPE_DEC) {
drivers/media/platform/qcom/venus/helpers.c
180
if (inst->dpb_buftype == HFI_BUFFER_OUTPUT)
drivers/media/platform/qcom/venus/helpers.c
181
dpb_size = inst->output_buf_size;
drivers/media/platform/qcom/venus/helpers.c
182
else if (inst->dpb_buftype == HFI_BUFFER_OUTPUT2)
drivers/media/platform/qcom/venus/helpers.c
1822
bool venus_helper_check_format(struct venus_inst *inst, u32 v4l2_pixfmt)
drivers/media/platform/qcom/venus/helpers.c
1824
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/helpers.c
183
dpb_size = inst->output2_buf_size;
drivers/media/platform/qcom/venus/helpers.c
1832
caps = venus_caps_by_codec(core, inst->hfi_codec, inst->session_type);
drivers/media/platform/qcom/venus/helpers.c
1846
int venus_helper_set_stride(struct venus_inst *inst,
drivers/media/platform/qcom/venus/helpers.c
1860
return hfi_session_set_property(inst, ptype, &plane_actual_info);
drivers/media/platform/qcom/venus/helpers.c
188
ret = venus_helper_get_bufreq(inst, buftype, &bufreq);
drivers/media/platform/qcom/venus/helpers.c
213
id = ida_alloc_min(&inst->dpb_ids, VB2_MAX_FRAME, GFP_KERNEL);
drivers/media/platform/qcom/venus/helpers.c
221
list_add_tail(&buf->list, &inst->dpbbufs);
drivers/media/platform/qcom/venus/helpers.c
228
venus_helper_free_dpb_bufs(inst);
drivers/media/platform/qcom/venus/helpers.c
233
static int intbufs_set_buffer(struct venus_inst *inst, u32 type)
drivers/media/platform/qcom/venus/helpers.c
235
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/helpers.c
243
ret = venus_helper_get_bufreq(inst, type, &bufreq);
drivers/media/platform/qcom/venus/helpers.c
274
ret = hfi_session_set_buffers(inst, &bd);
drivers/media/platform/qcom/venus/helpers.c
280
list_add_tail(&buf->list, &inst->internalbufs);
drivers/media/platform/qcom/venus/helpers.c
292
static int intbufs_unset_buffers(struct venus_inst *inst)
drivers/media/platform/qcom/venus/helpers.c
298
list_for_each_entry_safe(buf, n, &inst->internalbufs, list) {
drivers/media/platform/qcom/venus/helpers.c
305
ret = hfi_session_unset_buffers(inst, &bd);
drivers/media/platform/qcom/venus/helpers.c
308
dma_free_attrs(inst->core->dev, buf->size, buf->va, buf->da,
drivers/media/platform/qcom/venus/helpers.c
340
int venus_helper_intbufs_alloc(struct venus_inst *inst)
drivers/media/platform/qcom/venus/helpers.c
346
if (IS_V6(inst->core)) {
drivers/media/platform/qcom/venus/helpers.c
349
} else if (IS_V4(inst->core)) {
drivers/media/platform/qcom/venus/helpers.c
358
ret = intbufs_set_buffer(inst, intbuf[i]);
drivers/media/platform/qcom/venus/helpers.c
366
intbufs_unset_buffers(inst);
drivers/media/platform/qcom/venus/helpers.c
371
int venus_helper_intbufs_free(struct venus_inst *inst)
drivers/media/platform/qcom/venus/helpers.c
373
return intbufs_unset_buffers(inst);
drivers/media/platform/qcom/venus/helpers.c
377
int venus_helper_intbufs_realloc(struct venus_inst *inst)
drivers/media/platform/qcom/venus/helpers.c
379
enum hfi_version ver = inst->core->res->hfi_version;
drivers/media/platform/qcom/venus/helpers.c
384
list_for_each_entry_safe(buf, n, &inst->internalbufs, list) {
drivers/media/platform/qcom/venus/helpers.c
396
ret = hfi_session_unset_buffers(inst, &bd);
drivers/media/platform/qcom/venus/helpers.c
398
dma_free_attrs(inst->core->dev, buf->size, buf->va, buf->da,
drivers/media/platform/qcom/venus/helpers.c
405
ret = intbufs_set_buffer(inst, HFI_BUFFER_INTERNAL_SCRATCH(ver));
drivers/media/platform/qcom/venus/helpers.c
409
ret = intbufs_set_buffer(inst, HFI_BUFFER_INTERNAL_SCRATCH_1(ver));
drivers/media/platform/qcom/venus/helpers.c
41
bool venus_helper_check_codec(struct venus_inst *inst, u32 v4l2_pixfmt)
drivers/media/platform/qcom/venus/helpers.c
413
ret = intbufs_set_buffer(inst, HFI_BUFFER_INTERNAL_SCRATCH_2(ver));
drivers/media/platform/qcom/venus/helpers.c
43
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/helpers.c
434
static void return_buf_error(struct venus_inst *inst,
drivers/media/platform/qcom/venus/helpers.c
437
struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
drivers/media/platform/qcom/venus/helpers.c
44
u32 session_type = inst->session_type;
drivers/media/platform/qcom/venus/helpers.c
448
put_ts_metadata(struct venus_inst *inst, struct vb2_v4l2_buffer *vbuf)
drivers/media/platform/qcom/venus/helpers.c
455
for (i = 0; i < ARRAY_SIZE(inst->tss); i++) {
drivers/media/platform/qcom/venus/helpers.c
456
if (!inst->tss[i].used) {
drivers/media/platform/qcom/venus/helpers.c
463
dev_dbg(inst->core->dev, VDBGL "no free slot\n");
drivers/media/platform/qcom/venus/helpers.c
469
inst->tss[slot].used = true;
drivers/media/platform/qcom/venus/helpers.c
470
inst->tss[slot].flags = vbuf->flags;
drivers/media/platform/qcom/venus/helpers.c
471
inst->tss[slot].tc = vbuf->timecode;
drivers/media/platform/qcom/venus/helpers.c
472
inst->tss[slot].ts_us = ts_us;
drivers/media/platform/qcom/venus/helpers.c
473
inst->tss[slot].ts_ns = vb->timestamp;
drivers/media/platform/qcom/venus/helpers.c
476
void venus_helper_get_ts_metadata(struct venus_inst *inst, u64 timestamp_us,
drivers/media/platform/qcom/venus/helpers.c
482
for (i = 0; i < ARRAY_SIZE(inst->tss); ++i) {
drivers/media/platform/qcom/venus/helpers.c
483
if (!inst->tss[i].used)
drivers/media/platform/qcom/venus/helpers.c
486
if (inst->tss[i].ts_us != timestamp_us)
drivers/media/platform/qcom/venus/helpers.c
489
inst->tss[i].used = false;
drivers/media/platform/qcom/venus/helpers.c
490
vbuf->flags |= inst->tss[i].flags;
drivers/media/platform/qcom/venus/helpers.c
491
vbuf->timecode = inst->tss[i].tc;
drivers/media/platform/qcom/venus/helpers.c
492
vb->timestamp = inst->tss[i].ts_ns;
drivers/media/platform/qcom/venus/helpers.c
499
session_process_buf(struct venus_inst *inst, struct vb2_v4l2_buffer *vbuf)
drivers/media/platform/qcom/venus/helpers.c
522
if (inst->session_type == VIDC_SESSION_TYPE_DEC)
drivers/media/platform/qcom/venus/helpers.c
523
put_ts_metadata(inst, vbuf);
drivers/media/platform/qcom/venus/helpers.c
525
venus_pm_load_scale(inst);
drivers/media/platform/qcom/venus/helpers.c
527
if (inst->session_type == VIDC_SESSION_TYPE_ENC)
drivers/media/platform/qcom/venus/helpers.c
530
fdata.buffer_type = inst->opb_buftype;
drivers/media/platform/qcom/venus/helpers.c
535
return hfi_session_process_buf(inst, &fdata);
drivers/media/platform/qcom/venus/helpers.c
538
static bool is_dynamic_bufmode(struct venus_inst *inst)
drivers/media/platform/qcom/venus/helpers.c
540
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/helpers.c
550
caps = venus_caps_by_codec(core, inst->hfi_codec, inst->session_type);
drivers/media/platform/qcom/venus/helpers.c
557
int venus_helper_unregister_bufs(struct venus_inst *inst)
drivers/media/platform/qcom/venus/helpers.c
563
if (is_dynamic_bufmode(inst))
drivers/media/platform/qcom/venus/helpers.c
566
list_for_each_entry_safe(buf, n, &inst->registeredbufs, reg_list) {
drivers/media/platform/qcom/venus/helpers.c
568
ret = hfi_session_unset_buffers(inst, &bd);
drivers/media/platform/qcom/venus/helpers.c
576
static int session_register_bufs(struct venus_inst *inst)
drivers/media/platform/qcom/venus/helpers.c
578
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/helpers.c
584
if (is_dynamic_bufmode(inst))
drivers/media/platform/qcom/venus/helpers.c
587
list_for_each_entry(buf, &inst->registeredbufs, reg_list) {
drivers/media/platform/qcom/venus/helpers.c
589
ret = hfi_session_set_buffers(inst, &bd);
drivers/media/platform/qcom/venus/helpers.c
619
static int platform_get_bufreq(struct venus_inst *inst, u32 buftype,
drivers/media/platform/qcom/venus/helpers.c
622
enum hfi_version version = inst->core->res->hfi_version;
drivers/media/platform/qcom/venus/helpers.c
625
bool is_dec = inst->session_type == VIDC_SESSION_TYPE_DEC;
drivers/media/platform/qcom/venus/helpers.c
626
struct venc_controls *enc_ctr = &inst->controls.enc;
drivers/media/platform/qcom/venus/helpers.c
634
params.num_vpp_pipes = inst->core->res->num_vpp_pipes;
drivers/media/platform/qcom/venus/helpers.c
637
params.width = inst->width;
drivers/media/platform/qcom/venus/helpers.c
638
params.height = inst->height;
drivers/media/platform/qcom/venus/helpers.c
639
params.out_width = inst->out_width;
drivers/media/platform/qcom/venus/helpers.c
640
params.out_height = inst->out_height;
drivers/media/platform/qcom/venus/helpers.c
641
params.codec = inst->fmt_out->pixfmt;
drivers/media/platform/qcom/venus/helpers.c
642
params.hfi_color_fmt = to_hfi_raw_fmt(inst->fmt_cap->pixfmt);
drivers/media/platform/qcom/venus/helpers.c
643
params.dec.max_mbs_per_frame = mbs_per_frame_max(inst);
drivers/media/platform/qcom/venus/helpers.c
646
inst->opb_buftype == HFI_BUFFER_OUTPUT2;
drivers/media/platform/qcom/venus/helpers.c
648
params.hfi_dpb_color_fmt = inst->dpb_fmt;
drivers/media/platform/qcom/venus/helpers.c
650
inst->pic_struct != HFI_INTERLACE_FRAME_PROGRESSIVE;
drivers/media/platform/qcom/venus/helpers.c
652
params.width = inst->out_width;
drivers/media/platform/qcom/venus/helpers.c
653
params.height = inst->out_height;
drivers/media/platform/qcom/venus/helpers.c
654
params.codec = inst->fmt_cap->pixfmt;
drivers/media/platform/qcom/venus/helpers.c
655
params.hfi_color_fmt = to_hfi_raw_fmt(inst->fmt_out->pixfmt);
drivers/media/platform/qcom/venus/helpers.c
661
params.enc.is_tenbit = inst->bit_depth == VIDC_BITDEPTH_10;
drivers/media/platform/qcom/venus/helpers.c
664
return hfi_plat->bufreq(¶ms, inst->session_type, buftype, req);
drivers/media/platform/qcom/venus/helpers.c
667
int venus_helper_get_bufreq(struct venus_inst *inst, u32 type,
drivers/media/platform/qcom/venus/helpers.c
671
enum hfi_version ver = inst->core->res->hfi_version;
drivers/media/platform/qcom/venus/helpers.c
679
hfi_bufreq_set_count_min(req, ver, inst->fw_min_cnt);
drivers/media/platform/qcom/venus/helpers.c
681
ret = platform_get_bufreq(inst, type, req);
drivers/media/platform/qcom/venus/helpers.c
684
inst->fw_min_cnt = hfi_bufreq_get_count_min(req, ver);
drivers/media/platform/qcom/venus/helpers.c
688
ret = hfi_session_get_property(inst, ptype, &hprop);
drivers/media/platform/qcom/venus/helpers.c
918
int venus_helper_get_profile_level(struct venus_inst *inst, u32 *profile, u32 *level)
drivers/media/platform/qcom/venus/helpers.c
924
ret = hfi_session_get_property(inst, ptype, &hprop);
drivers/media/platform/qcom/venus/helpers.c
928
v4l2_id_profile_level(inst->hfi_codec, &hprop.profile_level, profile, level);
drivers/media/platform/qcom/venus/helpers.c
93
static void free_dpb_buf(struct venus_inst *inst, struct intbuf *buf)
drivers/media/platform/qcom/venus/helpers.c
934
int venus_helper_set_profile_level(struct venus_inst *inst, u32 profile, u32 level)
drivers/media/platform/qcom/venus/helpers.c
939
hfi_id_profile_level(inst->hfi_codec, profile, level, &pl);
drivers/media/platform/qcom/venus/helpers.c
941
return hfi_session_set_property(inst, ptype, &pl);
drivers/media/platform/qcom/venus/helpers.c
95
ida_free(&inst->dpb_ids, buf->dpb_out_tag);
drivers/media/platform/qcom/venus/helpers.c
98
dma_free_attrs(inst->core->dev, buf->size, buf->va, buf->da,
drivers/media/platform/qcom/venus/helpers.h
14
bool venus_helper_check_codec(struct venus_inst *inst, u32 v4l2_pixfmt);
drivers/media/platform/qcom/venus/helpers.h
15
struct vb2_v4l2_buffer *venus_helper_find_buf(struct venus_inst *inst,
drivers/media/platform/qcom/venus/helpers.h
17
void venus_helper_change_dpb_owner(struct venus_inst *inst,
drivers/media/platform/qcom/venus/helpers.h
20
void venus_helper_buffers_done(struct venus_inst *inst, unsigned int type,
drivers/media/platform/qcom/venus/helpers.h
26
int venus_helper_vb2_start_streaming(struct venus_inst *inst);
drivers/media/platform/qcom/venus/helpers.h
27
void venus_helper_vb2_queue_error(struct venus_inst *inst);
drivers/media/platform/qcom/venus/helpers.h
30
int venus_helper_get_bufreq(struct venus_inst *inst, u32 type,
drivers/media/platform/qcom/venus/helpers.h
34
int venus_helper_set_input_resolution(struct venus_inst *inst,
drivers/media/platform/qcom/venus/helpers.h
36
int venus_helper_set_output_resolution(struct venus_inst *inst,
drivers/media/platform/qcom/venus/helpers.h
39
int venus_helper_set_work_mode(struct venus_inst *inst);
drivers/media/platform/qcom/venus/helpers.h
40
int venus_helper_set_format_constraints(struct venus_inst *inst);
drivers/media/platform/qcom/venus/helpers.h
41
int venus_helper_set_num_bufs(struct venus_inst *inst, unsigned int input_bufs,
drivers/media/platform/qcom/venus/helpers.h
44
int venus_helper_set_raw_format(struct venus_inst *inst, u32 hfi_format,
drivers/media/platform/qcom/venus/helpers.h
46
int venus_helper_set_color_format(struct venus_inst *inst, u32 fmt);
drivers/media/platform/qcom/venus/helpers.h
47
int venus_helper_set_dyn_bufmode(struct venus_inst *inst);
drivers/media/platform/qcom/venus/helpers.h
48
int venus_helper_set_bufsize(struct venus_inst *inst, u32 bufsize, u32 buftype);
drivers/media/platform/qcom/venus/helpers.h
49
int venus_helper_set_multistream(struct venus_inst *inst, bool out_en,
drivers/media/platform/qcom/venus/helpers.h
51
unsigned int venus_helper_get_opb_size(struct venus_inst *inst);
drivers/media/platform/qcom/venus/helpers.h
53
void venus_helper_release_buf_ref(struct venus_inst *inst, unsigned int idx);
drivers/media/platform/qcom/venus/helpers.h
54
void venus_helper_init_instance(struct venus_inst *inst);
drivers/media/platform/qcom/venus/helpers.h
55
int venus_helper_session_init(struct venus_inst *inst);
drivers/media/platform/qcom/venus/helpers.h
56
int venus_helper_get_out_fmts(struct venus_inst *inst, u32 fmt, u32 *out_fmt,
drivers/media/platform/qcom/venus/helpers.h
58
bool venus_helper_check_format(struct venus_inst *inst, u32 v4l2_pixfmt);
drivers/media/platform/qcom/venus/helpers.h
59
int venus_helper_alloc_dpb_bufs(struct venus_inst *inst);
drivers/media/platform/qcom/venus/helpers.h
60
int venus_helper_free_dpb_bufs(struct venus_inst *inst);
drivers/media/platform/qcom/venus/helpers.h
61
int venus_helper_intbufs_alloc(struct venus_inst *inst);
drivers/media/platform/qcom/venus/helpers.h
62
int venus_helper_intbufs_free(struct venus_inst *inst);
drivers/media/platform/qcom/venus/helpers.h
63
int venus_helper_intbufs_realloc(struct venus_inst *inst);
drivers/media/platform/qcom/venus/helpers.h
64
int venus_helper_queue_dpb_bufs(struct venus_inst *inst);
drivers/media/platform/qcom/venus/helpers.h
65
int venus_helper_unregister_bufs(struct venus_inst *inst);
drivers/media/platform/qcom/venus/helpers.h
66
int venus_helper_process_initial_cap_bufs(struct venus_inst *inst);
drivers/media/platform/qcom/venus/helpers.h
67
int venus_helper_process_initial_out_bufs(struct venus_inst *inst);
drivers/media/platform/qcom/venus/helpers.h
68
void venus_helper_get_ts_metadata(struct venus_inst *inst, u64 timestamp_us,
drivers/media/platform/qcom/venus/helpers.h
70
int venus_helper_get_profile_level(struct venus_inst *inst, u32 *profile, u32 *level);
drivers/media/platform/qcom/venus/helpers.h
71
int venus_helper_set_profile_level(struct venus_inst *inst, u32 profile, u32 level);
drivers/media/platform/qcom/venus/helpers.h
72
int venus_helper_set_stride(struct venus_inst *inst, unsigned int aligned_width,
drivers/media/platform/qcom/venus/hfi.c
141
static int wait_session_msg(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi.c
145
ret = wait_for_completion_timeout(&inst->done, TIMEOUT);
drivers/media/platform/qcom/venus/hfi.c
149
if (inst->error != HFI_ERR_NONE)
drivers/media/platform/qcom/venus/hfi.c
155
int hfi_session_create(struct venus_inst *inst, const struct hfi_inst_ops *ops)
drivers/media/platform/qcom/venus/hfi.c
157
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/hfi.c
164
inst->state = INST_UNINIT;
drivers/media/platform/qcom/venus/hfi.c
165
init_completion(&inst->done);
drivers/media/platform/qcom/venus/hfi.c
166
inst->ops = ops;
drivers/media/platform/qcom/venus/hfi.c
170
if (test_bit(0, &inst->core->sys_error)) {
drivers/media/platform/qcom/venus/hfi.c
180
list_add_tail(&inst->list, &core->instances);
drivers/media/platform/qcom/venus/hfi.c
191
int hfi_session_init(struct venus_inst *inst, u32 pixfmt)
drivers/media/platform/qcom/venus/hfi.c
193
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/hfi.c
203
if (!core->ops || test_bit(0, &inst->core->sys_error)) {
drivers/media/platform/qcom/venus/hfi.c
209
if (inst->state != INST_UNINIT)
drivers/media/platform/qcom/venus/hfi.c
212
inst->hfi_codec = to_codec_type(pixfmt);
drivers/media/platform/qcom/venus/hfi.c
213
reinit_completion(&inst->done);
drivers/media/platform/qcom/venus/hfi.c
215
ret = ops->session_init(inst, inst->session_type, inst->hfi_codec);
drivers/media/platform/qcom/venus/hfi.c
219
ret = wait_session_msg(inst);
drivers/media/platform/qcom/venus/hfi.c
223
inst->state = INST_INIT;
drivers/media/platform/qcom/venus/hfi.c
229
void hfi_session_destroy(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi.c
231
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/hfi.c
234
list_del_init(&inst->list);
drivers/media/platform/qcom/venus/hfi.c
241
int hfi_session_deinit(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi.c
243
const struct hfi_ops *ops = inst->core->ops;
drivers/media/platform/qcom/venus/hfi.c
246
if (inst->state == INST_UNINIT)
drivers/media/platform/qcom/venus/hfi.c
249
if (inst->state < INST_INIT)
drivers/media/platform/qcom/venus/hfi.c
252
if (test_bit(0, &inst->core->sys_error))
drivers/media/platform/qcom/venus/hfi.c
255
reinit_completion(&inst->done);
drivers/media/platform/qcom/venus/hfi.c
257
ret = ops->session_end(inst);
drivers/media/platform/qcom/venus/hfi.c
261
ret = wait_session_msg(inst);
drivers/media/platform/qcom/venus/hfi.c
266
inst->state = INST_UNINIT;
drivers/media/platform/qcom/venus/hfi.c
272
int hfi_session_start(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi.c
274
const struct hfi_ops *ops = inst->core->ops;
drivers/media/platform/qcom/venus/hfi.c
277
if (test_bit(0, &inst->core->sys_error))
drivers/media/platform/qcom/venus/hfi.c
280
if (inst->state != INST_LOAD_RESOURCES)
drivers/media/platform/qcom/venus/hfi.c
283
reinit_completion(&inst->done);
drivers/media/platform/qcom/venus/hfi.c
285
ret = ops->session_start(inst);
drivers/media/platform/qcom/venus/hfi.c
289
ret = wait_session_msg(inst);
drivers/media/platform/qcom/venus/hfi.c
293
inst->state = INST_START;
drivers/media/platform/qcom/venus/hfi.c
299
int hfi_session_stop(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi.c
301
const struct hfi_ops *ops = inst->core->ops;
drivers/media/platform/qcom/venus/hfi.c
304
if (test_bit(0, &inst->core->sys_error))
drivers/media/platform/qcom/venus/hfi.c
307
if (inst->state != INST_START)
drivers/media/platform/qcom/venus/hfi.c
310
reinit_completion(&inst->done);
drivers/media/platform/qcom/venus/hfi.c
312
ret = ops->session_stop(inst);
drivers/media/platform/qcom/venus/hfi.c
316
ret = wait_session_msg(inst);
drivers/media/platform/qcom/venus/hfi.c
320
inst->state = INST_STOP;
drivers/media/platform/qcom/venus/hfi.c
326
int hfi_session_continue(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi.c
328
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/hfi.c
330
if (test_bit(0, &inst->core->sys_error))
drivers/media/platform/qcom/venus/hfi.c
336
return core->ops->session_continue(inst);
drivers/media/platform/qcom/venus/hfi.c
340
int hfi_session_abort(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi.c
342
const struct hfi_ops *ops = inst->core->ops;
drivers/media/platform/qcom/venus/hfi.c
345
if (test_bit(0, &inst->core->sys_error))
drivers/media/platform/qcom/venus/hfi.c
348
reinit_completion(&inst->done);
drivers/media/platform/qcom/venus/hfi.c
350
ret = ops->session_abort(inst);
drivers/media/platform/qcom/venus/hfi.c
354
ret = wait_session_msg(inst);
drivers/media/platform/qcom/venus/hfi.c
362
int hfi_session_load_res(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi.c
364
const struct hfi_ops *ops = inst->core->ops;
drivers/media/platform/qcom/venus/hfi.c
367
if (test_bit(0, &inst->core->sys_error))
drivers/media/platform/qcom/venus/hfi.c
370
if (inst->state != INST_INIT)
drivers/media/platform/qcom/venus/hfi.c
373
reinit_completion(&inst->done);
drivers/media/platform/qcom/venus/hfi.c
375
ret = ops->session_load_res(inst);
drivers/media/platform/qcom/venus/hfi.c
379
ret = wait_session_msg(inst);
drivers/media/platform/qcom/venus/hfi.c
383
inst->state = INST_LOAD_RESOURCES;
drivers/media/platform/qcom/venus/hfi.c
388
int hfi_session_unload_res(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi.c
390
const struct hfi_ops *ops = inst->core->ops;
drivers/media/platform/qcom/venus/hfi.c
393
if (test_bit(0, &inst->core->sys_error))
drivers/media/platform/qcom/venus/hfi.c
396
if (inst->state != INST_STOP)
drivers/media/platform/qcom/venus/hfi.c
399
reinit_completion(&inst->done);
drivers/media/platform/qcom/venus/hfi.c
401
ret = ops->session_release_res(inst);
drivers/media/platform/qcom/venus/hfi.c
405
ret = wait_session_msg(inst);
drivers/media/platform/qcom/venus/hfi.c
409
inst->state = INST_RELEASE_RESOURCES;
drivers/media/platform/qcom/venus/hfi.c
415
int hfi_session_flush(struct venus_inst *inst, u32 type, bool block)
drivers/media/platform/qcom/venus/hfi.c
417
const struct hfi_ops *ops = inst->core->ops;
drivers/media/platform/qcom/venus/hfi.c
420
if (test_bit(0, &inst->core->sys_error))
drivers/media/platform/qcom/venus/hfi.c
423
reinit_completion(&inst->done);
drivers/media/platform/qcom/venus/hfi.c
425
ret = ops->session_flush(inst, type);
drivers/media/platform/qcom/venus/hfi.c
430
ret = wait_session_msg(inst);
drivers/media/platform/qcom/venus/hfi.c
439
int hfi_session_set_buffers(struct venus_inst *inst, struct hfi_buffer_desc *bd)
drivers/media/platform/qcom/venus/hfi.c
441
const struct hfi_ops *ops = inst->core->ops;
drivers/media/platform/qcom/venus/hfi.c
443
if (test_bit(0, &inst->core->sys_error))
drivers/media/platform/qcom/venus/hfi.c
446
return ops->session_set_buffers(inst, bd);
drivers/media/platform/qcom/venus/hfi.c
449
int hfi_session_unset_buffers(struct venus_inst *inst,
drivers/media/platform/qcom/venus/hfi.c
452
const struct hfi_ops *ops = inst->core->ops;
drivers/media/platform/qcom/venus/hfi.c
455
if (test_bit(0, &inst->core->sys_error))
drivers/media/platform/qcom/venus/hfi.c
458
reinit_completion(&inst->done);
drivers/media/platform/qcom/venus/hfi.c
460
ret = ops->session_unset_buffers(inst, bd);
drivers/media/platform/qcom/venus/hfi.c
467
ret = wait_session_msg(inst);
drivers/media/platform/qcom/venus/hfi.c
474
int hfi_session_get_property(struct venus_inst *inst, u32 ptype,
drivers/media/platform/qcom/venus/hfi.c
477
const struct hfi_ops *ops = inst->core->ops;
drivers/media/platform/qcom/venus/hfi.c
480
if (test_bit(0, &inst->core->sys_error))
drivers/media/platform/qcom/venus/hfi.c
483
if (inst->state < INST_INIT || inst->state >= INST_STOP)
drivers/media/platform/qcom/venus/hfi.c
486
reinit_completion(&inst->done);
drivers/media/platform/qcom/venus/hfi.c
488
ret = ops->session_get_property(inst, ptype);
drivers/media/platform/qcom/venus/hfi.c
492
ret = wait_session_msg(inst);
drivers/media/platform/qcom/venus/hfi.c
496
*hprop = inst->hprop;
drivers/media/platform/qcom/venus/hfi.c
502
int hfi_session_set_property(struct venus_inst *inst, u32 ptype, void *pdata)
drivers/media/platform/qcom/venus/hfi.c
504
const struct hfi_ops *ops = inst->core->ops;
drivers/media/platform/qcom/venus/hfi.c
506
if (test_bit(0, &inst->core->sys_error))
drivers/media/platform/qcom/venus/hfi.c
509
if (inst->state < INST_INIT || inst->state >= INST_STOP)
drivers/media/platform/qcom/venus/hfi.c
512
return ops->session_set_property(inst, ptype, pdata);
drivers/media/platform/qcom/venus/hfi.c
516
int hfi_session_process_buf(struct venus_inst *inst, struct hfi_frame_data *fd)
drivers/media/platform/qcom/venus/hfi.c
518
const struct hfi_ops *ops = inst->core->ops;
drivers/media/platform/qcom/venus/hfi.c
520
if (test_bit(0, &inst->core->sys_error))
drivers/media/platform/qcom/venus/hfi.c
524
return ops->session_etb(inst, fd);
drivers/media/platform/qcom/venus/hfi.c
527
return ops->session_ftb(inst, fd);
drivers/media/platform/qcom/venus/hfi.h
100
void (*buf_done)(struct venus_inst *inst, unsigned int buf_type,
drivers/media/platform/qcom/venus/hfi.h
103
void (*event_notify)(struct venus_inst *inst, u32 event,
drivers/media/platform/qcom/venus/hfi.h
105
void (*flush_done)(struct venus_inst *inst);
drivers/media/platform/qcom/venus/hfi.h
113
int (*session_init)(struct venus_inst *inst, u32 session_type,
drivers/media/platform/qcom/venus/hfi.h
115
int (*session_end)(struct venus_inst *inst);
drivers/media/platform/qcom/venus/hfi.h
116
int (*session_abort)(struct venus_inst *inst);
drivers/media/platform/qcom/venus/hfi.h
117
int (*session_flush)(struct venus_inst *inst, u32 flush_mode);
drivers/media/platform/qcom/venus/hfi.h
118
int (*session_start)(struct venus_inst *inst);
drivers/media/platform/qcom/venus/hfi.h
119
int (*session_stop)(struct venus_inst *inst);
drivers/media/platform/qcom/venus/hfi.h
120
int (*session_continue)(struct venus_inst *inst);
drivers/media/platform/qcom/venus/hfi.h
121
int (*session_etb)(struct venus_inst *inst, struct hfi_frame_data *fd);
drivers/media/platform/qcom/venus/hfi.h
122
int (*session_ftb)(struct venus_inst *inst, struct hfi_frame_data *fd);
drivers/media/platform/qcom/venus/hfi.h
123
int (*session_set_buffers)(struct venus_inst *inst,
drivers/media/platform/qcom/venus/hfi.h
125
int (*session_unset_buffers)(struct venus_inst *inst,
drivers/media/platform/qcom/venus/hfi.h
127
int (*session_load_res)(struct venus_inst *inst);
drivers/media/platform/qcom/venus/hfi.h
128
int (*session_release_res)(struct venus_inst *inst);
drivers/media/platform/qcom/venus/hfi.h
129
int (*session_parse_seq_hdr)(struct venus_inst *inst, u32 seq_hdr,
drivers/media/platform/qcom/venus/hfi.h
131
int (*session_get_seq_hdr)(struct venus_inst *inst, u32 seq_hdr,
drivers/media/platform/qcom/venus/hfi.h
133
int (*session_set_property)(struct venus_inst *inst, u32 ptype,
drivers/media/platform/qcom/venus/hfi.h
135
int (*session_get_property)(struct venus_inst *inst, u32 ptype);
drivers/media/platform/qcom/venus/hfi.h
154
int hfi_session_create(struct venus_inst *inst, const struct hfi_inst_ops *ops);
drivers/media/platform/qcom/venus/hfi.h
155
void hfi_session_destroy(struct venus_inst *inst);
drivers/media/platform/qcom/venus/hfi.h
156
int hfi_session_init(struct venus_inst *inst, u32 pixfmt);
drivers/media/platform/qcom/venus/hfi.h
157
int hfi_session_deinit(struct venus_inst *inst);
drivers/media/platform/qcom/venus/hfi.h
158
int hfi_session_start(struct venus_inst *inst);
drivers/media/platform/qcom/venus/hfi.h
159
int hfi_session_stop(struct venus_inst *inst);
drivers/media/platform/qcom/venus/hfi.h
160
int hfi_session_continue(struct venus_inst *inst);
drivers/media/platform/qcom/venus/hfi.h
161
int hfi_session_abort(struct venus_inst *inst);
drivers/media/platform/qcom/venus/hfi.h
162
int hfi_session_load_res(struct venus_inst *inst);
drivers/media/platform/qcom/venus/hfi.h
163
int hfi_session_unload_res(struct venus_inst *inst);
drivers/media/platform/qcom/venus/hfi.h
164
int hfi_session_flush(struct venus_inst *inst, u32 type, bool block);
drivers/media/platform/qcom/venus/hfi.h
165
int hfi_session_set_buffers(struct venus_inst *inst,
drivers/media/platform/qcom/venus/hfi.h
167
int hfi_session_unset_buffers(struct venus_inst *inst,
drivers/media/platform/qcom/venus/hfi.h
169
int hfi_session_get_property(struct venus_inst *inst, u32 ptype,
drivers/media/platform/qcom/venus/hfi.h
171
int hfi_session_set_property(struct venus_inst *inst, u32 ptype, void *pdata);
drivers/media/platform/qcom/venus/hfi.h
172
int hfi_session_process_buf(struct venus_inst *inst, struct hfi_frame_data *f);
drivers/media/platform/qcom/venus/hfi_msgs.c
155
inst->ops->event_notify(inst, EVT_SYS_EVENT_CHANGE, &event);
drivers/media/platform/qcom/venus/hfi_msgs.c
159
inst->error = HFI_ERR_SESSION_INSUFFICIENT_RESOURCES;
drivers/media/platform/qcom/venus/hfi_msgs.c
160
inst->ops->event_notify(inst, EVT_SYS_EVENT_CHANGE, &event);
drivers/media/platform/qcom/venus/hfi_msgs.c
164
struct venus_inst *inst,
drivers/media/platform/qcom/venus/hfi_msgs.c
178
inst->error = HFI_ERR_NONE;
drivers/media/platform/qcom/venus/hfi_msgs.c
179
inst->ops->event_notify(inst, EVT_SYS_EVENT_CHANGE, &event);
drivers/media/platform/qcom/venus/hfi_msgs.c
195
event_session_error(struct venus_core *core, struct venus_inst *inst,
drivers/media/platform/qcom/venus/hfi_msgs.c
203
if (!inst)
drivers/media/platform/qcom/venus/hfi_msgs.c
212
inst->error = HFI_ERR_NONE;
drivers/media/platform/qcom/venus/hfi_msgs.c
219
inst->error = pkt->event_data1;
drivers/media/platform/qcom/venus/hfi_msgs.c
22
static void event_seq_changed(struct venus_core *core, struct venus_inst *inst,
drivers/media/platform/qcom/venus/hfi_msgs.c
220
inst->ops->event_notify(inst, EVT_SESSION_ERROR, NULL);
drivers/media/platform/qcom/venus/hfi_msgs.c
225
static void hfi_event_notify(struct venus_core *core, struct venus_inst *inst,
drivers/media/platform/qcom/venus/hfi_msgs.c
238
event_session_error(core, inst, pkt);
drivers/media/platform/qcom/venus/hfi_msgs.c
241
event_seq_changed(core, inst, pkt);
drivers/media/platform/qcom/venus/hfi_msgs.c
244
event_release_buffer_ref(core, inst, pkt);
drivers/media/platform/qcom/venus/hfi_msgs.c
253
static void hfi_sys_init_done(struct venus_core *core, struct venus_inst *inst,
drivers/media/platform/qcom/venus/hfi_msgs.c
276
error = hfi_parser(core, inst, pkt->data, rem_bytes);
drivers/media/platform/qcom/venus/hfi_msgs.c
343
struct venus_inst *inst, void *packet)
drivers/media/platform/qcom/venus/hfi_msgs.c
364
struct venus_inst *inst,
drivers/media/platform/qcom/venus/hfi_msgs.c
373
static void hfi_sys_ping_done(struct venus_core *core, struct venus_inst *inst,
drivers/media/platform/qcom/venus/hfi_msgs.c
386
static void hfi_sys_idle_done(struct venus_core *core, struct venus_inst *inst,
drivers/media/platform/qcom/venus/hfi_msgs.c
393
struct venus_inst *inst, void *packet)
drivers/media/platform/qcom/venus/hfi_msgs.c
40
inst->error = HFI_ERR_NONE;
drivers/media/platform/qcom/venus/hfi_msgs.c
454
struct venus_inst *inst, void *packet)
drivers/media/platform/qcom/venus/hfi_msgs.c
458
union hfi_get_property *hprop = &inst->hprop;
drivers/media/platform/qcom/venus/hfi_msgs.c
47
inst->error = HFI_ERR_SESSION_INVALID_PARAMETER;
drivers/media/platform/qcom/venus/hfi_msgs.c
48
inst->ops->event_notify(inst, EVT_SYS_EVENT_CHANGE, &event);
drivers/media/platform/qcom/venus/hfi_msgs.c
485
inst->error = error;
drivers/media/platform/qcom/venus/hfi_msgs.c
486
complete(&inst->done);
drivers/media/platform/qcom/venus/hfi_msgs.c
490
struct venus_inst *inst, void *packet)
drivers/media/platform/qcom/venus/hfi_msgs.c
509
error = hfi_parser(core, inst, pkt->data, rem_bytes);
drivers/media/platform/qcom/venus/hfi_msgs.c
511
inst->error = error;
drivers/media/platform/qcom/venus/hfi_msgs.c
512
complete(&inst->done);
drivers/media/platform/qcom/venus/hfi_msgs.c
516
struct venus_inst *inst, void *packet)
drivers/media/platform/qcom/venus/hfi_msgs.c
520
inst->error = pkt->error_type;
drivers/media/platform/qcom/venus/hfi_msgs.c
521
complete(&inst->done);
drivers/media/platform/qcom/venus/hfi_msgs.c
525
struct venus_inst *inst, void *packet)
drivers/media/platform/qcom/venus/hfi_msgs.c
529
inst->error = pkt->error_type;
drivers/media/platform/qcom/venus/hfi_msgs.c
530
complete(&inst->done);
drivers/media/platform/qcom/venus/hfi_msgs.c
531
if (inst->ops->flush_done)
drivers/media/platform/qcom/venus/hfi_msgs.c
532
inst->ops->flush_done(inst);
drivers/media/platform/qcom/venus/hfi_msgs.c
536
struct venus_inst *inst, void *packet)
drivers/media/platform/qcom/venus/hfi_msgs.c
540
inst->error = pkt->error_type;
drivers/media/platform/qcom/venus/hfi_msgs.c
541
inst->ops->buf_done(inst, HFI_BUFFER_INPUT, pkt->input_tag,
drivers/media/platform/qcom/venus/hfi_msgs.c
546
struct venus_inst *inst, void *packet)
drivers/media/platform/qcom/venus/hfi_msgs.c
548
u32 session_type = inst->session_type;
drivers/media/platform/qcom/venus/hfi_msgs.c
621
inst->error = error;
drivers/media/platform/qcom/venus/hfi_msgs.c
622
inst->ops->buf_done(inst, buffer_type, output_tag, filled_len,
drivers/media/platform/qcom/venus/hfi_msgs.c
627
struct venus_inst *inst, void *packet)
drivers/media/platform/qcom/venus/hfi_msgs.c
631
inst->error = pkt->error_type;
drivers/media/platform/qcom/venus/hfi_msgs.c
632
complete(&inst->done);
drivers/media/platform/qcom/venus/hfi_msgs.c
636
struct venus_inst *inst, void *packet)
drivers/media/platform/qcom/venus/hfi_msgs.c
640
inst->error = pkt->error_type;
drivers/media/platform/qcom/venus/hfi_msgs.c
641
complete(&inst->done);
drivers/media/platform/qcom/venus/hfi_msgs.c
645
struct venus_inst *inst, void *packet)
drivers/media/platform/qcom/venus/hfi_msgs.c
649
inst->error = pkt->error_type;
drivers/media/platform/qcom/venus/hfi_msgs.c
650
complete(&inst->done);
drivers/media/platform/qcom/venus/hfi_msgs.c
654
struct venus_inst *inst, void *packet)
drivers/media/platform/qcom/venus/hfi_msgs.c
658
inst->error = pkt->error_type;
drivers/media/platform/qcom/venus/hfi_msgs.c
659
complete(&inst->done);
drivers/media/platform/qcom/venus/hfi_msgs.c
663
struct venus_inst *inst, void *packet)
drivers/media/platform/qcom/venus/hfi_msgs.c
667
inst->error = pkt->error_type;
drivers/media/platform/qcom/venus/hfi_msgs.c
668
complete(&inst->done);
drivers/media/platform/qcom/venus/hfi_msgs.c
672
struct venus_inst *inst, void *packet)
drivers/media/platform/qcom/venus/hfi_msgs.c
676
inst->error = pkt->error_type;
drivers/media/platform/qcom/venus/hfi_msgs.c
677
complete(&inst->done);
drivers/media/platform/qcom/venus/hfi_msgs.c
681
struct venus_inst *inst, void *packet)
drivers/media/platform/qcom/venus/hfi_msgs.c
685
inst->error = pkt->error_type;
drivers/media/platform/qcom/venus/hfi_msgs.c
686
complete(&inst->done);
drivers/media/platform/qcom/venus/hfi_msgs.c
794
struct venus_inst *inst;
drivers/media/platform/qcom/venus/hfi_msgs.c
797
list_for_each_entry(inst, &core->instances, list)
drivers/media/platform/qcom/venus/hfi_msgs.c
798
if (hash32_ptr(inst) == session_id) {
drivers/media/platform/qcom/venus/hfi_msgs.c
800
return inst;
drivers/media/platform/qcom/venus/hfi_msgs.c
811
struct venus_inst *inst;
drivers/media/platform/qcom/venus/hfi_msgs.c
835
inst = NULL;
drivers/media/platform/qcom/venus/hfi_msgs.c
840
inst = to_instance(core, pkt->shdr.session_id);
drivers/media/platform/qcom/venus/hfi_msgs.c
842
if (!inst)
drivers/media/platform/qcom/venus/hfi_msgs.c
851
if (!inst && hdr->pkt_type != HFI_MSG_EVENT_NOTIFY) {
drivers/media/platform/qcom/venus/hfi_msgs.c
858
handler->done(core, inst, hdr);
drivers/media/platform/qcom/venus/hfi_parser.c
237
static void parser_init(struct venus_inst *inst, u32 *codecs, u32 *domain)
drivers/media/platform/qcom/venus/hfi_parser.c
239
if (!inst || !IS_V1(inst->core))
drivers/media/platform/qcom/venus/hfi_parser.c
242
*codecs = inst->hfi_codec;
drivers/media/platform/qcom/venus/hfi_parser.c
243
*domain = inst->session_type;
drivers/media/platform/qcom/venus/hfi_parser.c
246
static void parser_fini(struct venus_inst *inst, u32 codecs, u32 domain)
drivers/media/platform/qcom/venus/hfi_parser.c
252
if (!inst || !IS_V1(inst->core))
drivers/media/platform/qcom/venus/hfi_parser.c
255
caps = inst->core->caps;
drivers/media/platform/qcom/venus/hfi_parser.c
256
dom = inst->session_type;
drivers/media/platform/qcom/venus/hfi_parser.c
265
static int hfi_platform_parser(struct venus_core *core, struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi_parser.c
276
if (inst)
drivers/media/platform/qcom/venus/hfi_parser.c
298
u32 hfi_parser(struct venus_core *core, struct venus_inst *inst, void *buf,
drivers/media/platform/qcom/venus/hfi_parser.c
306
ret = hfi_platform_parser(core, inst);
drivers/media/platform/qcom/venus/hfi_parser.c
313
parser_init(inst, &codecs, &domain);
drivers/media/platform/qcom/venus/hfi_parser.c
385
parser_fini(inst, codecs, domain);
drivers/media/platform/qcom/venus/hfi_parser.h
100
static inline u32 frate_max(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi_parser.h
102
return cap_max(inst, HFI_CAPABILITY_FRAMERATE);
drivers/media/platform/qcom/venus/hfi_parser.h
105
static inline u32 frate_step(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi_parser.h
107
return cap_step(inst, HFI_CAPABILITY_FRAMERATE);
drivers/media/platform/qcom/venus/hfi_parser.h
110
static inline u32 core_num_max(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi_parser.h
112
return cap_max(inst, HFI_CAPABILITY_MAX_VIDEOCORES);
drivers/media/platform/qcom/venus/hfi_parser.h
115
static inline u32 mbs_per_frame_max(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi_parser.h
117
return cap_max(inst, HFI_CAPABILITY_MBS_PER_FRAME);
drivers/media/platform/qcom/venus/hfi_parser.h
15
static inline u32 get_cap(struct venus_inst *inst, u32 type, u32 which)
drivers/media/platform/qcom/venus/hfi_parser.h
17
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/hfi_parser.h
22
caps = venus_caps_by_codec(core, inst->hfi_codec, inst->session_type);
drivers/media/platform/qcom/venus/hfi_parser.h
50
static inline u32 cap_min(struct venus_inst *inst, u32 type)
drivers/media/platform/qcom/venus/hfi_parser.h
52
return get_cap(inst, type, WHICH_CAP_MIN);
drivers/media/platform/qcom/venus/hfi_parser.h
55
static inline u32 cap_max(struct venus_inst *inst, u32 type)
drivers/media/platform/qcom/venus/hfi_parser.h
57
return get_cap(inst, type, WHICH_CAP_MAX);
drivers/media/platform/qcom/venus/hfi_parser.h
60
static inline u32 cap_step(struct venus_inst *inst, u32 type)
drivers/media/platform/qcom/venus/hfi_parser.h
62
return get_cap(inst, type, WHICH_CAP_STEP);
drivers/media/platform/qcom/venus/hfi_parser.h
65
static inline u32 frame_width_min(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi_parser.h
67
return cap_min(inst, HFI_CAPABILITY_FRAME_WIDTH);
drivers/media/platform/qcom/venus/hfi_parser.h
70
static inline u32 frame_width_max(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi_parser.h
72
return cap_max(inst, HFI_CAPABILITY_FRAME_WIDTH);
drivers/media/platform/qcom/venus/hfi_parser.h
75
static inline u32 frame_width_step(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi_parser.h
77
return cap_step(inst, HFI_CAPABILITY_FRAME_WIDTH);
drivers/media/platform/qcom/venus/hfi_parser.h
8
u32 hfi_parser(struct venus_core *core, struct venus_inst *inst,
drivers/media/platform/qcom/venus/hfi_parser.h
80
static inline u32 frame_height_min(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi_parser.h
82
return cap_min(inst, HFI_CAPABILITY_FRAME_HEIGHT);
drivers/media/platform/qcom/venus/hfi_parser.h
85
static inline u32 frame_height_max(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi_parser.h
87
return cap_max(inst, HFI_CAPABILITY_FRAME_HEIGHT);
drivers/media/platform/qcom/venus/hfi_parser.h
90
static inline u32 frame_height_step(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi_parser.h
92
return cap_step(inst, HFI_CAPABILITY_FRAME_HEIGHT);
drivers/media/platform/qcom/venus/hfi_parser.h
95
static inline u32 frate_min(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi_parser.h
97
return cap_min(inst, HFI_CAPABILITY_FRAMERATE);
drivers/media/platform/qcom/venus/hfi_venus.c
1223
static int venus_session_init(struct venus_inst *inst, u32 session_type,
drivers/media/platform/qcom/venus/hfi_venus.c
1226
struct venus_hfi_device *hdev = to_hfi_priv(inst->core);
drivers/media/platform/qcom/venus/hfi_venus.c
1234
ret = pkt_session_init(&pkt, inst, session_type, codec);
drivers/media/platform/qcom/venus/hfi_venus.c
1249
static int venus_session_end(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi_venus.c
1251
struct venus_hfi_device *hdev = to_hfi_priv(inst->core);
drivers/media/platform/qcom/venus/hfi_venus.c
1259
return venus_session_cmd(inst, HFI_CMD_SYS_SESSION_END, true);
drivers/media/platform/qcom/venus/hfi_venus.c
1262
static int venus_session_abort(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi_venus.c
1264
struct venus_hfi_device *hdev = to_hfi_priv(inst->core);
drivers/media/platform/qcom/venus/hfi_venus.c
1268
return venus_session_cmd(inst, HFI_CMD_SYS_SESSION_ABORT, true);
drivers/media/platform/qcom/venus/hfi_venus.c
1271
static int venus_session_flush(struct venus_inst *inst, u32 flush_mode)
drivers/media/platform/qcom/venus/hfi_venus.c
1273
struct venus_hfi_device *hdev = to_hfi_priv(inst->core);
drivers/media/platform/qcom/venus/hfi_venus.c
1277
ret = pkt_session_flush(&pkt, inst, flush_mode);
drivers/media/platform/qcom/venus/hfi_venus.c
1284
static int venus_session_start(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi_venus.c
1286
return venus_session_cmd(inst, HFI_CMD_SESSION_START, true);
drivers/media/platform/qcom/venus/hfi_venus.c
1289
static int venus_session_stop(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi_venus.c
1291
return venus_session_cmd(inst, HFI_CMD_SESSION_STOP, true);
drivers/media/platform/qcom/venus/hfi_venus.c
1294
static int venus_session_continue(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi_venus.c
1296
return venus_session_cmd(inst, HFI_CMD_SESSION_CONTINUE, false);
drivers/media/platform/qcom/venus/hfi_venus.c
1299
static int venus_session_etb(struct venus_inst *inst,
drivers/media/platform/qcom/venus/hfi_venus.c
1302
struct venus_hfi_device *hdev = to_hfi_priv(inst->core);
drivers/media/platform/qcom/venus/hfi_venus.c
1303
u32 session_type = inst->session_type;
drivers/media/platform/qcom/venus/hfi_venus.c
1309
ret = pkt_session_etb_decoder(&pkt, inst, in_frame);
drivers/media/platform/qcom/venus/hfi_venus.c
1317
ret = pkt_session_etb_encoder(&pkt, inst, in_frame);
drivers/media/platform/qcom/venus/hfi_venus.c
1329
static int venus_session_ftb(struct venus_inst *inst,
drivers/media/platform/qcom/venus/hfi_venus.c
1332
struct venus_hfi_device *hdev = to_hfi_priv(inst->core);
drivers/media/platform/qcom/venus/hfi_venus.c
1336
ret = pkt_session_ftb(&pkt, inst, out_frame);
drivers/media/platform/qcom/venus/hfi_venus.c
1343
static int venus_session_set_buffers(struct venus_inst *inst,
drivers/media/platform/qcom/venus/hfi_venus.c
1346
struct venus_hfi_device *hdev = to_hfi_priv(inst->core);
drivers/media/platform/qcom/venus/hfi_venus.c
1356
ret = pkt_session_set_buffers(pkt, inst, bd);
drivers/media/platform/qcom/venus/hfi_venus.c
1363
static int venus_session_unset_buffers(struct venus_inst *inst,
drivers/media/platform/qcom/venus/hfi_venus.c
1366
struct venus_hfi_device *hdev = to_hfi_priv(inst->core);
drivers/media/platform/qcom/venus/hfi_venus.c
1376
ret = pkt_session_unset_buffers(pkt, inst, bd);
drivers/media/platform/qcom/venus/hfi_venus.c
1383
static int venus_session_load_res(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi_venus.c
1385
return venus_session_cmd(inst, HFI_CMD_SESSION_LOAD_RESOURCES, true);
drivers/media/platform/qcom/venus/hfi_venus.c
1388
static int venus_session_release_res(struct venus_inst *inst)
drivers/media/platform/qcom/venus/hfi_venus.c
1390
return venus_session_cmd(inst, HFI_CMD_SESSION_RELEASE_RESOURCES, true);
drivers/media/platform/qcom/venus/hfi_venus.c
1393
static int venus_session_parse_seq_hdr(struct venus_inst *inst, u32 seq_hdr,
drivers/media/platform/qcom/venus/hfi_venus.c
1396
struct venus_hfi_device *hdev = to_hfi_priv(inst->core);
drivers/media/platform/qcom/venus/hfi_venus.c
1403
ret = pkt_session_parse_seq_header(pkt, inst, seq_hdr, seq_hdr_len);
drivers/media/platform/qcom/venus/hfi_venus.c
1414
static int venus_session_get_seq_hdr(struct venus_inst *inst, u32 seq_hdr,
drivers/media/platform/qcom/venus/hfi_venus.c
1417
struct venus_hfi_device *hdev = to_hfi_priv(inst->core);
drivers/media/platform/qcom/venus/hfi_venus.c
1424
ret = pkt_session_get_seq_hdr(pkt, inst, seq_hdr, seq_hdr_len);
drivers/media/platform/qcom/venus/hfi_venus.c
1431
static int venus_session_set_property(struct venus_inst *inst, u32 ptype,
drivers/media/platform/qcom/venus/hfi_venus.c
1434
struct venus_hfi_device *hdev = to_hfi_priv(inst->core);
drivers/media/platform/qcom/venus/hfi_venus.c
1441
ret = pkt_session_set_property(pkt, inst, ptype, pdata);
drivers/media/platform/qcom/venus/hfi_venus.c
1450
static int venus_session_get_property(struct venus_inst *inst, u32 ptype)
drivers/media/platform/qcom/venus/hfi_venus.c
1452
struct venus_hfi_device *hdev = to_hfi_priv(inst->core);
drivers/media/platform/qcom/venus/hfi_venus.c
1456
ret = pkt_session_get_property(&pkt, inst, ptype);
drivers/media/platform/qcom/venus/hfi_venus.c
978
static int venus_session_cmd(struct venus_inst *inst, u32 pkt_type, bool sync)
drivers/media/platform/qcom/venus/hfi_venus.c
980
struct venus_hfi_device *hdev = to_hfi_priv(inst->core);
drivers/media/platform/qcom/venus/hfi_venus.c
983
pkt_session_cmd(&pkt, pkt_type, inst);
drivers/media/platform/qcom/venus/pm_helpers.c
1206
static unsigned long calculate_inst_freq(struct venus_inst *inst,
drivers/media/platform/qcom/venus/pm_helpers.c
1210
u32 fps = (u32)inst->fps;
drivers/media/platform/qcom/venus/pm_helpers.c
1213
mbs_per_sec = load_per_instance(inst);
drivers/media/platform/qcom/venus/pm_helpers.c
1215
if (inst->state != INST_START)
drivers/media/platform/qcom/venus/pm_helpers.c
1218
if (inst->session_type == VIDC_SESSION_TYPE_ENC) {
drivers/media/platform/qcom/venus/pm_helpers.c
1219
vpp_freq_per_mb = inst->flags & VENUS_LOW_POWER ?
drivers/media/platform/qcom/venus/pm_helpers.c
1220
inst->clk_data.low_power_freq :
drivers/media/platform/qcom/venus/pm_helpers.c
1221
inst->clk_data.vpp_freq;
drivers/media/platform/qcom/venus/pm_helpers.c
1225
vpp_freq = mbs_per_sec * inst->clk_data.vpp_freq;
drivers/media/platform/qcom/venus/pm_helpers.c
1230
vsp_freq = mbs_per_sec * inst->clk_data.vsp_freq;
drivers/media/platform/qcom/venus/pm_helpers.c
1233
if (inst->session_type == VIDC_SESSION_TYPE_ENC)
drivers/media/platform/qcom/venus/pm_helpers.c
1234
vsp_freq += (inst->controls.enc.bitrate * 10) / 7;
drivers/media/platform/qcom/venus/pm_helpers.c
1241
static int load_scale_v4(struct venus_inst *inst)
drivers/media/platform/qcom/venus/pm_helpers.c
1243
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/pm_helpers.c
1251
for (i = 0; i < inst->num_input_bufs; i++)
drivers/media/platform/qcom/venus/pm_helpers.c
1252
filled_len = max(filled_len, inst->payloads[i]);
drivers/media/platform/qcom/venus/pm_helpers.c
1254
if (inst->session_type == VIDC_SESSION_TYPE_DEC && !filled_len)
drivers/media/platform/qcom/venus/pm_helpers.c
1257
freq = calculate_inst_freq(inst, filled_len);
drivers/media/platform/qcom/venus/pm_helpers.c
1258
inst->clk_data.freq = freq;
drivers/media/platform/qcom/venus/pm_helpers.c
1261
list_for_each_entry(inst, &core->instances, list) {
drivers/media/platform/qcom/venus/pm_helpers.c
1262
if (inst->clk_data.core_id == VIDC_CORE_ID_1) {
drivers/media/platform/qcom/venus/pm_helpers.c
1263
freq_core1 += inst->clk_data.freq;
drivers/media/platform/qcom/venus/pm_helpers.c
1264
} else if (inst->clk_data.core_id == VIDC_CORE_ID_2) {
drivers/media/platform/qcom/venus/pm_helpers.c
1265
freq_core2 += inst->clk_data.freq;
drivers/media/platform/qcom/venus/pm_helpers.c
1266
} else if (inst->clk_data.core_id == VIDC_CORE_ID_3) {
drivers/media/platform/qcom/venus/pm_helpers.c
1267
freq_core1 += inst->clk_data.freq;
drivers/media/platform/qcom/venus/pm_helpers.c
1268
freq_core2 += inst->clk_data.freq;
drivers/media/platform/qcom/venus/pm_helpers.c
166
static u32 load_per_instance(struct venus_inst *inst)
drivers/media/platform/qcom/venus/pm_helpers.c
170
if (!inst || !(inst->state >= INST_INIT && inst->state < INST_STOP))
drivers/media/platform/qcom/venus/pm_helpers.c
173
mbs = (ALIGN(inst->width, 16) / 16) * (ALIGN(inst->height, 16) / 16);
drivers/media/platform/qcom/venus/pm_helpers.c
175
return mbs * inst->fps;
drivers/media/platform/qcom/venus/pm_helpers.c
180
struct venus_inst *inst = NULL;
drivers/media/platform/qcom/venus/pm_helpers.c
183
list_for_each_entry(inst, &core->instances, list) {
drivers/media/platform/qcom/venus/pm_helpers.c
184
if (inst->session_type != session_type)
drivers/media/platform/qcom/venus/pm_helpers.c
187
mbs_per_sec += load_per_instance(inst);
drivers/media/platform/qcom/venus/pm_helpers.c
193
static void mbs_to_bw(struct venus_inst *inst, u32 mbs, u32 *avg, u32 *peak)
drivers/media/platform/qcom/venus/pm_helpers.c
195
const struct venus_resources *res = inst->core->res;
drivers/media/platform/qcom/venus/pm_helpers.c
205
if (inst->session_type == VIDC_SESSION_TYPE_ENC) {
drivers/media/platform/qcom/venus/pm_helpers.c
208
} else if (inst->session_type == VIDC_SESSION_TYPE_DEC) {
drivers/media/platform/qcom/venus/pm_helpers.c
222
if (inst->dpb_fmt & HFI_COLOR_FORMAT_10_BIT_BASE) {
drivers/media/platform/qcom/venus/pm_helpers.c
234
struct venus_inst *inst = NULL;
drivers/media/platform/qcom/venus/pm_helpers.c
237
list_for_each_entry(inst, &core->instances, list) {
drivers/media/platform/qcom/venus/pm_helpers.c
238
mbs_per_sec = load_per_instance(inst);
drivers/media/platform/qcom/venus/pm_helpers.c
239
mbs_to_bw(inst, mbs_per_sec, &avg, &peak);
drivers/media/platform/qcom/venus/pm_helpers.c
260
static int load_scale_v1(struct venus_inst *inst)
drivers/media/platform/qcom/venus/pm_helpers.c
262
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/pm_helpers.c
678
static inline int power_save_mode_enable(struct venus_inst *inst,
drivers/media/platform/qcom/venus/pm_helpers.c
681
struct venc_controls *enc_ctr = &inst->controls.enc;
drivers/media/platform/qcom/venus/pm_helpers.c
686
if (inst->session_type != VIDC_SESSION_TYPE_ENC)
drivers/media/platform/qcom/venus/pm_helpers.c
695
ret = hfi_session_set_property(inst, ptype, &venc_mode);
drivers/media/platform/qcom/venus/pm_helpers.c
699
inst->flags = enable ? inst->flags | VENUS_LOW_POWER :
drivers/media/platform/qcom/venus/pm_helpers.c
700
inst->flags & ~VENUS_LOW_POWER;
drivers/media/platform/qcom/venus/pm_helpers.c
708
struct venus_inst *inst = NULL;
drivers/media/platform/qcom/venus/pm_helpers.c
711
list_for_each_entry(inst, &core->instances, list) {
drivers/media/platform/qcom/venus/pm_helpers.c
712
if (inst->clk_data.core_id == core_id &&
drivers/media/platform/qcom/venus/pm_helpers.c
713
inst->session_type == VIDC_SESSION_TYPE_ENC)
drivers/media/platform/qcom/venus/pm_helpers.c
714
power_save_mode_enable(inst, true);
drivers/media/platform/qcom/venus/pm_helpers.c
721
min_loaded_core(struct venus_inst *inst, u32 *min_coreid, u32 *min_load, bool low_power)
drivers/media/platform/qcom/venus/pm_helpers.c
724
u32 cores_max = core_num_max(inst);
drivers/media/platform/qcom/venus/pm_helpers.c
725
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/pm_helpers.c
733
if (inst_pos == inst)
drivers/media/platform/qcom/venus/pm_helpers.c
739
if (inst->session_type == VIDC_SESSION_TYPE_DEC)
drivers/media/platform/qcom/venus/pm_helpers.c
741
else if (inst->session_type == VIDC_SESSION_TYPE_ENC)
drivers/media/platform/qcom/venus/pm_helpers.c
774
static int decide_core(struct venus_inst *inst)
drivers/media/platform/qcom/venus/pm_helpers.c
777
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/pm_helpers.c
787
if (inst->session_type == VIDC_SESSION_TYPE_DEC)
drivers/media/platform/qcom/venus/pm_helpers.c
795
if (inst->clk_data.core_id != VIDC_CORE_ID_DEFAULT)
drivers/media/platform/qcom/venus/pm_helpers.c
798
cur_inst_load = load_per_instance(inst);
drivers/media/platform/qcom/venus/pm_helpers.c
799
cur_inst_load *= inst->clk_data.vpp_freq;
drivers/media/platform/qcom/venus/pm_helpers.c
802
cur_inst_lp_load = load_per_instance(inst);
drivers/media/platform/qcom/venus/pm_helpers.c
803
cur_inst_lp_load *= inst->clk_data.low_power_freq;
drivers/media/platform/qcom/venus/pm_helpers.c
810
min_loaded_core(inst, &min_coreid, &min_load, false);
drivers/media/platform/qcom/venus/pm_helpers.c
811
min_loaded_core(inst, &min_lp_coreid, &min_lp_load, true);
drivers/media/platform/qcom/venus/pm_helpers.c
814
inst->clk_data.core_id = min_coreid;
drivers/media/platform/qcom/venus/pm_helpers.c
818
inst->clk_data.core_id = min_coreid;
drivers/media/platform/qcom/venus/pm_helpers.c
820
power_save_mode_enable(inst, true);
drivers/media/platform/qcom/venus/pm_helpers.c
823
inst->clk_data.core_id = min_lp_coreid;
drivers/media/platform/qcom/venus/pm_helpers.c
832
ret = hfi_session_set_property(inst, ptype, &cu);
drivers/media/platform/qcom/venus/pm_helpers.c
839
static int acquire_core(struct venus_inst *inst)
drivers/media/platform/qcom/venus/pm_helpers.c
841
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/pm_helpers.c
844
if (inst->core_acquired)
drivers/media/platform/qcom/venus/pm_helpers.c
847
inst->core_acquired = true;
drivers/media/platform/qcom/venus/pm_helpers.c
849
if (inst->clk_data.core_id & VIDC_CORE_ID_1) {
drivers/media/platform/qcom/venus/pm_helpers.c
856
if (inst->clk_data.core_id & VIDC_CORE_ID_2) {
drivers/media/platform/qcom/venus/pm_helpers.c
866
static int release_core(struct venus_inst *inst)
drivers/media/platform/qcom/venus/pm_helpers.c
868
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/pm_helpers.c
872
if (!inst->core_acquired)
drivers/media/platform/qcom/venus/pm_helpers.c
875
if (inst->clk_data.core_id & VIDC_CORE_ID_1) {
drivers/media/platform/qcom/venus/pm_helpers.c
882
if (inst->clk_data.core_id & VIDC_CORE_ID_2) {
drivers/media/platform/qcom/venus/pm_helpers.c
894
inst->clk_data.core_id = VIDC_CORE_ID_DEFAULT;
drivers/media/platform/qcom/venus/pm_helpers.c
895
inst->core_acquired = false;
drivers/media/platform/qcom/venus/pm_helpers.c
899
static int coreid_power_v4(struct venus_inst *inst, int on)
drivers/media/platform/qcom/venus/pm_helpers.c
901
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/pm_helpers.c
908
ret = decide_core(inst);
drivers/media/platform/qcom/venus/pm_helpers.c
913
ret = acquire_core(inst);
drivers/media/platform/qcom/venus/pm_helpers.c
917
ret = release_core(inst);
drivers/media/platform/qcom/venus/pm_helpers.h
25
int (*coreid_power)(struct venus_inst *inst, int on);
drivers/media/platform/qcom/venus/pm_helpers.h
27
int (*load_scale)(struct venus_inst *inst);
drivers/media/platform/qcom/venus/pm_helpers.h
32
static inline int venus_pm_load_scale(struct venus_inst *inst)
drivers/media/platform/qcom/venus/pm_helpers.h
34
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/pm_helpers.h
39
return core->pm_ops->load_scale(inst);
drivers/media/platform/qcom/venus/pm_helpers.h
42
static inline int venus_pm_acquire_core(struct venus_inst *inst)
drivers/media/platform/qcom/venus/pm_helpers.h
44
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/pm_helpers.h
49
ret = pm_ops->coreid_power(inst, POWER_ON);
drivers/media/platform/qcom/venus/pm_helpers.h
54
static inline int venus_pm_release_core(struct venus_inst *inst)
drivers/media/platform/qcom/venus/pm_helpers.h
56
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/pm_helpers.h
61
ret = pm_ops->coreid_power(inst, POWER_OFF);
drivers/media/platform/qcom/venus/vdec.c
1009
vdec_pm_put(inst, false);
drivers/media/platform/qcom/venus/vdec.c
1013
static int vdec_verify_conf(struct venus_inst *inst)
drivers/media/platform/qcom/venus/vdec.c
1015
enum hfi_version ver = inst->core->res->hfi_version;
drivers/media/platform/qcom/venus/vdec.c
1019
if (!inst->num_input_bufs || !inst->num_output_bufs)
drivers/media/platform/qcom/venus/vdec.c
1022
ret = venus_helper_get_bufreq(inst, HFI_BUFFER_OUTPUT, &bufreq);
drivers/media/platform/qcom/venus/vdec.c
1026
if (inst->num_output_bufs < bufreq.count_actual ||
drivers/media/platform/qcom/venus/vdec.c
1027
inst->num_output_bufs < hfi_bufreq_get_count_min(&bufreq, ver))
drivers/media/platform/qcom/venus/vdec.c
1030
ret = venus_helper_get_bufreq(inst, HFI_BUFFER_INPUT, &bufreq);
drivers/media/platform/qcom/venus/vdec.c
1034
if (inst->num_input_bufs < hfi_bufreq_get_count_min(&bufreq, ver))
drivers/media/platform/qcom/venus/vdec.c
1040
static int vdec_start_capture(struct venus_inst *inst)
drivers/media/platform/qcom/venus/vdec.c
1044
if (!inst->streamon_out)
drivers/media/platform/qcom/venus/vdec.c
1047
if (inst->codec_state == VENUS_DEC_STATE_DECODING) {
drivers/media/platform/qcom/venus/vdec.c
1048
if (inst->reconfig)
drivers/media/platform/qcom/venus/vdec.c
1051
venus_helper_queue_dpb_bufs(inst);
drivers/media/platform/qcom/venus/vdec.c
1052
venus_helper_process_initial_cap_bufs(inst);
drivers/media/platform/qcom/venus/vdec.c
1053
inst->streamon_cap = 1;
drivers/media/platform/qcom/venus/vdec.c
1057
if (inst->codec_state != VENUS_DEC_STATE_STOPPED)
drivers/media/platform/qcom/venus/vdec.c
1061
ret = vdec_output_conf(inst);
drivers/media/platform/qcom/venus/vdec.c
1065
ret = venus_helper_set_num_bufs(inst, inst->num_input_bufs,
drivers/media/platform/qcom/venus/vdec.c
1070
ret = venus_helper_intbufs_realloc(inst);
drivers/media/platform/qcom/venus/vdec.c
1074
venus_pm_load_scale(inst);
drivers/media/platform/qcom/venus/vdec.c
1076
inst->next_buf_last = false;
drivers/media/platform/qcom/venus/vdec.c
1078
ret = venus_helper_alloc_dpb_bufs(inst);
drivers/media/platform/qcom/venus/vdec.c
1082
ret = hfi_session_continue(inst);
drivers/media/platform/qcom/venus/vdec.c
1086
ret = venus_helper_queue_dpb_bufs(inst);
drivers/media/platform/qcom/venus/vdec.c
1090
ret = venus_helper_process_initial_cap_bufs(inst);
drivers/media/platform/qcom/venus/vdec.c
1094
inst->codec_state = VENUS_DEC_STATE_DECODING;
drivers/media/platform/qcom/venus/vdec.c
1096
if (inst->drain_active)
drivers/media/platform/qcom/venus/vdec.c
1097
inst->codec_state = VENUS_DEC_STATE_DRAIN;
drivers/media/platform/qcom/venus/vdec.c
1099
inst->streamon_cap = 1;
drivers/media/platform/qcom/venus/vdec.c
1100
inst->sequence_cap = 0;
drivers/media/platform/qcom/venus/vdec.c
1101
inst->reconfig = false;
drivers/media/platform/qcom/venus/vdec.c
1102
inst->drain_active = false;
drivers/media/platform/qcom/venus/vdec.c
1107
venus_helper_free_dpb_bufs(inst);
drivers/media/platform/qcom/venus/vdec.c
1112
static int vdec_start_output(struct venus_inst *inst)
drivers/media/platform/qcom/venus/vdec.c
1116
if (inst->codec_state == VENUS_DEC_STATE_SEEK) {
drivers/media/platform/qcom/venus/vdec.c
1117
ret = venus_helper_process_initial_out_bufs(inst);
drivers/media/platform/qcom/venus/vdec.c
1121
if (inst->next_buf_last) {
drivers/media/platform/qcom/venus/vdec.c
1122
inst->codec_state = VENUS_DEC_STATE_DRC;
drivers/media/platform/qcom/venus/vdec.c
1124
inst->codec_state = VENUS_DEC_STATE_DECODING;
drivers/media/platform/qcom/venus/vdec.c
1126
if (inst->streamon_cap) {
drivers/media/platform/qcom/venus/vdec.c
1127
ret = venus_helper_queue_dpb_bufs(inst);
drivers/media/platform/qcom/venus/vdec.c
1135
if (inst->codec_state == VENUS_DEC_STATE_INIT ||
drivers/media/platform/qcom/venus/vdec.c
1136
inst->codec_state == VENUS_DEC_STATE_CAPTURE_SETUP) {
drivers/media/platform/qcom/venus/vdec.c
1137
ret = venus_helper_process_initial_out_bufs(inst);
drivers/media/platform/qcom/venus/vdec.c
1141
if (inst->codec_state != VENUS_DEC_STATE_DEINIT)
drivers/media/platform/qcom/venus/vdec.c
1144
venus_helper_init_instance(inst);
drivers/media/platform/qcom/venus/vdec.c
1145
inst->sequence_out = 0;
drivers/media/platform/qcom/venus/vdec.c
1146
inst->reconfig = false;
drivers/media/platform/qcom/venus/vdec.c
1147
inst->next_buf_last = false;
drivers/media/platform/qcom/venus/vdec.c
1149
ret = vdec_set_properties(inst);
drivers/media/platform/qcom/venus/vdec.c
1153
ret = vdec_set_work_route(inst);
drivers/media/platform/qcom/venus/vdec.c
1157
ret = vdec_output_conf(inst);
drivers/media/platform/qcom/venus/vdec.c
116
find_format(struct venus_inst *inst, u32 pixfmt, u32 type)
drivers/media/platform/qcom/venus/vdec.c
1161
ret = vdec_verify_conf(inst);
drivers/media/platform/qcom/venus/vdec.c
1165
ret = venus_helper_set_num_bufs(inst, inst->num_input_bufs,
drivers/media/platform/qcom/venus/vdec.c
1170
ret = venus_helper_vb2_start_streaming(inst);
drivers/media/platform/qcom/venus/vdec.c
1174
ret = venus_helper_process_initial_out_bufs(inst);
drivers/media/platform/qcom/venus/vdec.c
1178
inst->codec_state = VENUS_DEC_STATE_INIT;
drivers/media/platform/qcom/venus/vdec.c
1181
inst->streamon_out = 1;
drivers/media/platform/qcom/venus/vdec.c
1187
struct venus_inst *inst = vb2_get_drv_priv(q);
drivers/media/platform/qcom/venus/vdec.c
1190
mutex_lock(&inst->lock);
drivers/media/platform/qcom/venus/vdec.c
1193
ret = vdec_start_capture(inst);
drivers/media/platform/qcom/venus/vdec.c
1195
ret = vdec_pm_get(inst);
drivers/media/platform/qcom/venus/vdec.c
1199
ret = venus_pm_acquire_core(inst);
drivers/media/platform/qcom/venus/vdec.c
1203
ret = vdec_pm_put(inst, true);
drivers/media/platform/qcom/venus/vdec.c
1207
ret = vdec_start_output(inst);
drivers/media/platform/qcom/venus/vdec.c
1213
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/vdec.c
1217
vdec_pm_put(inst, false);
drivers/media/platform/qcom/venus/vdec.c
1219
venus_helper_buffers_done(inst, q->type, VB2_BUF_STATE_QUEUED);
drivers/media/platform/qcom/venus/vdec.c
1220
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/vdec.c
1224
static void vdec_cancel_dst_buffers(struct venus_inst *inst)
drivers/media/platform/qcom/venus/vdec.c
1228
while ((buf = v4l2_m2m_dst_buf_remove(inst->m2m_ctx)))
drivers/media/platform/qcom/venus/vdec.c
1232
static int vdec_stop_capture(struct venus_inst *inst)
drivers/media/platform/qcom/venus/vdec.c
1236
switch (inst->codec_state) {
drivers/media/platform/qcom/venus/vdec.c
1238
ret = hfi_session_flush(inst, HFI_FLUSH_ALL, true);
drivers/media/platform/qcom/venus/vdec.c
1241
inst->codec_state = VENUS_DEC_STATE_STOPPED;
drivers/media/platform/qcom/venus/vdec.c
1242
inst->drain_active = false;
drivers/media/platform/qcom/venus/vdec.c
1245
vdec_cancel_dst_buffers(inst);
drivers/media/platform/qcom/venus/vdec.c
1248
ret = hfi_session_flush(inst, HFI_FLUSH_OUTPUT, true);
drivers/media/platform/qcom/venus/vdec.c
1249
inst->codec_state = VENUS_DEC_STATE_CAPTURE_SETUP;
drivers/media/platform/qcom/venus/vdec.c
1250
venus_helper_free_dpb_bufs(inst);
drivers/media/platform/qcom/venus/vdec.c
1259
static int vdec_stop_output(struct venus_inst *inst)
drivers/media/platform/qcom/venus/vdec.c
1263
switch (inst->codec_state) {
drivers/media/platform/qcom/venus/vdec.c
1268
ret = hfi_session_flush(inst, HFI_FLUSH_ALL, true);
drivers/media/platform/qcom/venus/vdec.c
1269
inst->codec_state = VENUS_DEC_STATE_SEEK;
drivers/media/platform/qcom/venus/vdec.c
1273
ret = hfi_session_flush(inst, HFI_FLUSH_ALL, true);
drivers/media/platform/qcom/venus/vdec.c
1284
struct venus_inst *inst = vb2_get_drv_priv(q);
drivers/media/platform/qcom/venus/vdec.c
1287
vdec_pm_get_put(inst);
drivers/media/platform/qcom/venus/vdec.c
1289
mutex_lock(&inst->lock);
drivers/media/platform/qcom/venus/vdec.c
1292
ret = vdec_stop_capture(inst);
drivers/media/platform/qcom/venus/vdec.c
1294
ret = vdec_stop_output(inst);
drivers/media/platform/qcom/venus/vdec.c
1296
venus_helper_buffers_done(inst, q->type, VB2_BUF_STATE_ERROR);
drivers/media/platform/qcom/venus/vdec.c
1298
inst->session_error = 0;
drivers/media/platform/qcom/venus/vdec.c
1304
inst->streamon_out = 0;
drivers/media/platform/qcom/venus/vdec.c
1306
inst->streamon_cap = 0;
drivers/media/platform/qcom/venus/vdec.c
1309
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/vdec.c
131
!venus_helper_check_codec(inst, fmt[i].pixfmt))
drivers/media/platform/qcom/venus/vdec.c
1312
static void vdec_session_release(struct venus_inst *inst)
drivers/media/platform/qcom/venus/vdec.c
1314
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/vdec.c
1317
vdec_pm_get(inst);
drivers/media/platform/qcom/venus/vdec.c
1319
mutex_lock(&inst->lock);
drivers/media/platform/qcom/venus/vdec.c
1320
inst->codec_state = VENUS_DEC_STATE_DEINIT;
drivers/media/platform/qcom/venus/vdec.c
1322
ret = hfi_session_stop(inst);
drivers/media/platform/qcom/venus/vdec.c
1324
ret = hfi_session_unload_res(inst);
drivers/media/platform/qcom/venus/vdec.c
1326
ret = venus_helper_unregister_bufs(inst);
drivers/media/platform/qcom/venus/vdec.c
1328
ret = venus_helper_intbufs_free(inst);
drivers/media/platform/qcom/venus/vdec.c
1330
ret = hfi_session_deinit(inst);
drivers/media/platform/qcom/venus/vdec.c
1333
if (inst->session_error || test_bit(0, &core->sys_error))
drivers/media/platform/qcom/venus/vdec.c
1337
hfi_session_abort(inst);
drivers/media/platform/qcom/venus/vdec.c
1339
venus_helper_free_dpb_bufs(inst);
drivers/media/platform/qcom/venus/vdec.c
1340
venus_pm_load_scale(inst);
drivers/media/platform/qcom/venus/vdec.c
1341
INIT_LIST_HEAD(&inst->registeredbufs);
drivers/media/platform/qcom/venus/vdec.c
1342
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/vdec.c
1344
venus_pm_release_core(inst);
drivers/media/platform/qcom/venus/vdec.c
1345
vdec_pm_put(inst, false);
drivers/media/platform/qcom/venus/vdec.c
135
!venus_helper_check_format(inst, fmt[i].pixfmt))
drivers/media/platform/qcom/venus/vdec.c
1350
struct venus_inst *inst = vb2_get_drv_priv(vb->vb2_queue);
drivers/media/platform/qcom/venus/vdec.c
1352
inst->buf_count++;
drivers/media/platform/qcom/venus/vdec.c
1359
struct venus_inst *inst = vb2_get_drv_priv(vb->vb2_queue);
drivers/media/platform/qcom/venus/vdec.c
1363
mutex_lock(&inst->lock);
drivers/media/platform/qcom/venus/vdec.c
1365
if (!list_empty(&inst->registeredbufs))
drivers/media/platform/qcom/venus/vdec.c
1367
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/vdec.c
1369
inst->buf_count--;
drivers/media/platform/qcom/venus/vdec.c
1370
if (!inst->buf_count)
drivers/media/platform/qcom/venus/vdec.c
1371
vdec_session_release(inst);
drivers/media/platform/qcom/venus/vdec.c
1376
struct venus_inst *inst = vb2_get_drv_priv(vb->vb2_queue);
drivers/media/platform/qcom/venus/vdec.c
1380
vdec_pm_get_put(inst);
drivers/media/platform/qcom/venus/vdec.c
1382
mutex_lock(&inst->lock);
drivers/media/platform/qcom/venus/vdec.c
1384
if (inst->next_buf_last && V4L2_TYPE_IS_CAPTURE(vb->vb2_queue->type) &&
drivers/media/platform/qcom/venus/vdec.c
1385
inst->codec_state == VENUS_DEC_STATE_DRC) {
drivers/media/platform/qcom/venus/vdec.c
1387
vbuf->sequence = inst->sequence_cap++;
drivers/media/platform/qcom/venus/vdec.c
139
!(inst->bit_depth == VIDC_BITDEPTH_10))
drivers/media/platform/qcom/venus/vdec.c
1391
v4l2_event_queue_fh(&inst->fh, &eos);
drivers/media/platform/qcom/venus/vdec.c
1392
inst->next_buf_last = false;
drivers/media/platform/qcom/venus/vdec.c
1393
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/vdec.c
1398
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/vdec.c
1411
static void vdec_buf_done(struct venus_inst *inst, unsigned int buf_type,
drivers/media/platform/qcom/venus/vdec.c
1420
vdec_pm_touch(inst);
drivers/media/platform/qcom/venus/vdec.c
1427
vbuf = venus_helper_find_buf(inst, type, tag);
drivers/media/platform/qcom/venus/vdec.c
1429
venus_helper_change_dpb_owner(inst, vbuf, type, buf_type, tag);
drivers/media/platform/qcom/venus/vdec.c
1441
vbuf->sequence = inst->sequence_cap++;
drivers/media/platform/qcom/venus/vdec.c
1446
v4l2_event_queue_fh(&inst->fh, &ev);
drivers/media/platform/qcom/venus/vdec.c
1448
if (inst->codec_state == VENUS_DEC_STATE_DRAIN) {
drivers/media/platform/qcom/venus/vdec.c
1449
inst->drain_active = false;
drivers/media/platform/qcom/venus/vdec.c
1450
inst->codec_state = VENUS_DEC_STATE_STOPPED;
drivers/media/platform/qcom/venus/vdec.c
1457
vbuf->sequence = inst->sequence_out++;
drivers/media/platform/qcom/venus/vdec.c
146
find_format_by_index(struct venus_inst *inst, unsigned int index, u32 type)
drivers/media/platform/qcom/venus/vdec.c
1460
venus_helper_get_ts_metadata(inst, timestamp_us, vbuf);
drivers/media/platform/qcom/venus/vdec.c
1477
static void vdec_event_change(struct venus_inst *inst,
drivers/media/platform/qcom/venus/vdec.c
1483
struct device *dev = inst->core->dev_dec;
drivers/media/platform/qcom/venus/vdec.c
1486
mutex_lock(&inst->lock);
drivers/media/platform/qcom/venus/vdec.c
1489
format.fmt.pix_mp.pixelformat = inst->fmt_cap->pixfmt;
drivers/media/platform/qcom/venus/vdec.c
1493
vdec_try_fmt_common(inst, &format);
drivers/media/platform/qcom/venus/vdec.c
1495
inst->width = format.fmt.pix_mp.width;
drivers/media/platform/qcom/venus/vdec.c
1496
inst->height = format.fmt.pix_mp.height;
drivers/media/platform/qcom/venus/vdec.c
1502
inst->crop.left = ev_data->input_crop.left;
drivers/media/platform/qcom/venus/vdec.c
1503
inst->crop.top = ev_data->input_crop.top;
drivers/media/platform/qcom/venus/vdec.c
1504
inst->crop.width = ev_data->input_crop.width;
drivers/media/platform/qcom/venus/vdec.c
1505
inst->crop.height = ev_data->input_crop.height;
drivers/media/platform/qcom/venus/vdec.c
1507
inst->crop.left = 0;
drivers/media/platform/qcom/venus/vdec.c
1508
inst->crop.top = 0;
drivers/media/platform/qcom/venus/vdec.c
1509
inst->crop.width = ev_data->width;
drivers/media/platform/qcom/venus/vdec.c
1510
inst->crop.height = ev_data->height;
drivers/media/platform/qcom/venus/vdec.c
1513
inst->fw_min_cnt = ev_data->buf_count;
drivers/media/platform/qcom/venus/vdec.c
1515
if (inst->hfi_codec == HFI_VIDEO_CODEC_VP9)
drivers/media/platform/qcom/venus/vdec.c
1516
inst->fw_min_cnt = 11;
drivers/media/platform/qcom/venus/vdec.c
1518
inst->out_width = ev_data->width;
drivers/media/platform/qcom/venus/vdec.c
1519
inst->out_height = ev_data->height;
drivers/media/platform/qcom/venus/vdec.c
1521
if (inst->bit_depth != ev_data->bit_depth) {
drivers/media/platform/qcom/venus/vdec.c
1522
inst->bit_depth = ev_data->bit_depth;
drivers/media/platform/qcom/venus/vdec.c
1523
if (inst->bit_depth == VIDC_BITDEPTH_10)
drivers/media/platform/qcom/venus/vdec.c
1524
inst->fmt_cap = &vdec_formats[VENUS_FMT_P010];
drivers/media/platform/qcom/venus/vdec.c
1526
inst->fmt_cap = &vdec_formats[VENUS_FMT_NV12];
drivers/media/platform/qcom/venus/vdec.c
1529
if (inst->pic_struct != ev_data->pic_struct)
drivers/media/platform/qcom/venus/vdec.c
1530
inst->pic_struct = ev_data->pic_struct;
drivers/media/platform/qcom/venus/vdec.c
1535
switch (inst->codec_state) {
drivers/media/platform/qcom/venus/vdec.c
1537
inst->codec_state = VENUS_DEC_STATE_CAPTURE_SETUP;
drivers/media/platform/qcom/venus/vdec.c
1541
inst->codec_state = VENUS_DEC_STATE_DRC;
drivers/media/platform/qcom/venus/vdec.c
1553
if (inst->codec_state == VENUS_DEC_STATE_DRC) {
drivers/media/platform/qcom/venus/vdec.c
1556
inst->next_buf_last = true;
drivers/media/platform/qcom/venus/vdec.c
1558
ret = hfi_session_flush(inst, HFI_FLUSH_OUTPUT, false);
drivers/media/platform/qcom/venus/vdec.c
1563
inst->next_buf_last = true;
drivers/media/platform/qcom/venus/vdec.c
1564
inst->reconfig = true;
drivers/media/platform/qcom/venus/vdec.c
1565
v4l2_event_queue_fh(&inst->fh, &ev);
drivers/media/platform/qcom/venus/vdec.c
1566
wake_up(&inst->reconf_wait);
drivers/media/platform/qcom/venus/vdec.c
1568
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/vdec.c
1571
static void vdec_event_notify(struct venus_inst *inst, u32 event,
drivers/media/platform/qcom/venus/vdec.c
1574
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/vdec.c
1577
vdec_pm_touch(inst);
drivers/media/platform/qcom/venus/vdec.c
1581
inst->session_error = true;
drivers/media/platform/qcom/venus/vdec.c
1582
venus_helper_vb2_queue_error(inst);
drivers/media/platform/qcom/venus/vdec.c
1583
dev_err(dev, "dec: event session error %x\n", inst->error);
drivers/media/platform/qcom/venus/vdec.c
1588
vdec_event_change(inst, data, true);
drivers/media/platform/qcom/venus/vdec.c
1591
vdec_event_change(inst, data, false);
drivers/media/platform/qcom/venus/vdec.c
1594
venus_helper_release_buf_ref(inst, data->tag);
drivers/media/platform/qcom/venus/vdec.c
1605
static void vdec_flush_done(struct venus_inst *inst)
drivers/media/platform/qcom/venus/vdec.c
1607
dev_dbg(inst->core->dev_dec, VDBGH "flush done\n");
drivers/media/platform/qcom/venus/vdec.c
1616
static void vdec_inst_init(struct venus_inst *inst)
drivers/media/platform/qcom/venus/vdec.c
1618
inst->hfi_codec = HFI_VIDEO_CODEC_H264;
drivers/media/platform/qcom/venus/vdec.c
1619
inst->fmt_out = &vdec_formats[VENUS_FMT_H264];
drivers/media/platform/qcom/venus/vdec.c
162
valid = venus_helper_check_codec(inst, fmt[i].pixfmt);
drivers/media/platform/qcom/venus/vdec.c
1620
inst->fmt_cap = &vdec_formats[VENUS_FMT_NV12];
drivers/media/platform/qcom/venus/vdec.c
1621
inst->width = frame_width_min(inst);
drivers/media/platform/qcom/venus/vdec.c
1622
inst->height = ALIGN(frame_height_min(inst), 32);
drivers/media/platform/qcom/venus/vdec.c
1623
inst->crop.left = 0;
drivers/media/platform/qcom/venus/vdec.c
1624
inst->crop.top = 0;
drivers/media/platform/qcom/venus/vdec.c
1625
inst->crop.width = inst->width;
drivers/media/platform/qcom/venus/vdec.c
1626
inst->crop.height = inst->height;
drivers/media/platform/qcom/venus/vdec.c
1627
inst->fw_min_cnt = 8;
drivers/media/platform/qcom/venus/vdec.c
1628
inst->out_width = frame_width_min(inst);
drivers/media/platform/qcom/venus/vdec.c
1629
inst->out_height = frame_height_min(inst);
drivers/media/platform/qcom/venus/vdec.c
1630
inst->fps = 30;
drivers/media/platform/qcom/venus/vdec.c
1631
inst->timeperframe.numerator = 1;
drivers/media/platform/qcom/venus/vdec.c
1632
inst->timeperframe.denominator = 30;
drivers/media/platform/qcom/venus/vdec.c
1633
inst->opb_buftype = HFI_BUFFER_OUTPUT;
drivers/media/platform/qcom/venus/vdec.c
164
valid = venus_helper_check_format(inst, fmt[i].pixfmt);
drivers/media/platform/qcom/venus/vdec.c
1648
struct venus_inst *inst = priv;
drivers/media/platform/qcom/venus/vdec.c
1656
src_vq->drv_priv = inst;
drivers/media/platform/qcom/venus/vdec.c
1660
src_vq->dev = inst->core->dev;
drivers/media/platform/qcom/venus/vdec.c
1661
src_vq->lock = &inst->ctx_q_lock;
drivers/media/platform/qcom/venus/vdec.c
167
!(inst->bit_depth == VIDC_BITDEPTH_10))
drivers/media/platform/qcom/venus/vdec.c
1671
dst_vq->drv_priv = inst;
drivers/media/platform/qcom/venus/vdec.c
1675
dst_vq->dev = inst->core->dev;
drivers/media/platform/qcom/venus/vdec.c
1676
dst_vq->lock = &inst->ctx_q_lock;
drivers/media/platform/qcom/venus/vdec.c
1683
struct venus_inst *inst;
drivers/media/platform/qcom/venus/vdec.c
1686
inst = kzalloc_obj(*inst);
drivers/media/platform/qcom/venus/vdec.c
1687
if (!inst)
drivers/media/platform/qcom/venus/vdec.c
1690
INIT_LIST_HEAD(&inst->dpbbufs);
drivers/media/platform/qcom/venus/vdec.c
1691
INIT_LIST_HEAD(&inst->registeredbufs);
drivers/media/platform/qcom/venus/vdec.c
1692
INIT_LIST_HEAD(&inst->internalbufs);
drivers/media/platform/qcom/venus/vdec.c
1693
INIT_LIST_HEAD(&inst->list);
drivers/media/platform/qcom/venus/vdec.c
1694
mutex_init(&inst->lock);
drivers/media/platform/qcom/venus/vdec.c
1695
mutex_init(&inst->ctx_q_lock);
drivers/media/platform/qcom/venus/vdec.c
1697
inst->core = core;
drivers/media/platform/qcom/venus/vdec.c
1698
inst->session_type = VIDC_SESSION_TYPE_DEC;
drivers/media/platform/qcom/venus/vdec.c
1699
inst->num_output_bufs = 1;
drivers/media/platform/qcom/venus/vdec.c
1700
inst->codec_state = VENUS_DEC_STATE_DEINIT;
drivers/media/platform/qcom/venus/vdec.c
1701
inst->buf_count = 0;
drivers/media/platform/qcom/venus/vdec.c
1702
inst->clk_data.core_id = VIDC_CORE_ID_DEFAULT;
drivers/media/platform/qcom/venus/vdec.c
1703
inst->core_acquired = false;
drivers/media/platform/qcom/venus/vdec.c
1704
inst->bit_depth = VIDC_BITDEPTH_8;
drivers/media/platform/qcom/venus/vdec.c
1705
inst->pic_struct = HFI_INTERLACE_FRAME_PROGRESSIVE;
drivers/media/platform/qcom/venus/vdec.c
1706
init_waitqueue_head(&inst->reconf_wait);
drivers/media/platform/qcom/venus/vdec.c
1707
inst->nonblock = file->f_flags & O_NONBLOCK;
drivers/media/platform/qcom/venus/vdec.c
1709
venus_helper_init_instance(inst);
drivers/media/platform/qcom/venus/vdec.c
1711
ret = vdec_ctrl_init(inst);
drivers/media/platform/qcom/venus/vdec.c
1715
vdec_inst_init(inst);
drivers/media/platform/qcom/venus/vdec.c
1717
ida_init(&inst->dpb_ids);
drivers/media/platform/qcom/venus/vdec.c
1723
inst->m2m_dev = v4l2_m2m_init(&vdec_m2m_ops);
drivers/media/platform/qcom/venus/vdec.c
1724
if (IS_ERR(inst->m2m_dev)) {
drivers/media/platform/qcom/venus/vdec.c
1725
ret = PTR_ERR(inst->m2m_dev);
drivers/media/platform/qcom/venus/vdec.c
1729
inst->m2m_ctx = v4l2_m2m_ctx_init(inst->m2m_dev, inst, m2m_queue_init);
drivers/media/platform/qcom/venus/vdec.c
1730
if (IS_ERR(inst->m2m_ctx)) {
drivers/media/platform/qcom/venus/vdec.c
1731
ret = PTR_ERR(inst->m2m_ctx);
drivers/media/platform/qcom/venus/vdec.c
1735
ret = hfi_session_create(inst, &vdec_hfi_ops);
drivers/media/platform/qcom/venus/vdec.c
1739
v4l2_fh_init(&inst->fh, core->vdev_dec);
drivers/media/platform/qcom/venus/vdec.c
1741
inst->fh.ctrl_handler = &inst->ctrl_handler;
drivers/media/platform/qcom/venus/vdec.c
1742
v4l2_fh_add(&inst->fh, file);
drivers/media/platform/qcom/venus/vdec.c
1743
inst->fh.m2m_ctx = inst->m2m_ctx;
drivers/media/platform/qcom/venus/vdec.c
1748
v4l2_m2m_ctx_release(inst->m2m_ctx);
drivers/media/platform/qcom/venus/vdec.c
1750
v4l2_m2m_release(inst->m2m_dev);
drivers/media/platform/qcom/venus/vdec.c
1752
v4l2_ctrl_handler_free(&inst->ctrl_handler);
drivers/media/platform/qcom/venus/vdec.c
1754
kfree(inst);
drivers/media/platform/qcom/venus/vdec.c
1760
struct venus_inst *inst = to_inst(file);
drivers/media/platform/qcom/venus/vdec.c
1762
vdec_pm_get(inst);
drivers/media/platform/qcom/venus/vdec.c
1763
cancel_work_sync(&inst->delayed_process_work);
drivers/media/platform/qcom/venus/vdec.c
1764
venus_close_common(inst, file);
drivers/media/platform/qcom/venus/vdec.c
1765
ida_destroy(&inst->dpb_ids);
drivers/media/platform/qcom/venus/vdec.c
1766
vdec_pm_put(inst, false);
drivers/media/platform/qcom/venus/vdec.c
1768
kfree(inst);
drivers/media/platform/qcom/venus/vdec.c
184
vdec_try_fmt_common(struct venus_inst *inst, struct v4l2_format *f)
drivers/media/platform/qcom/venus/vdec.c
194
fmt = find_format(inst, pixmp->pixelformat, f->type);
drivers/media/platform/qcom/venus/vdec.c
202
fmt = find_format(inst, pixmp->pixelformat, f->type);
drivers/media/platform/qcom/venus/vdec.c
207
pixmp->width = clamp(pixmp->width, frame_width_min(inst),
drivers/media/platform/qcom/venus/vdec.c
208
frame_width_max(inst));
drivers/media/platform/qcom/venus/vdec.c
209
pixmp->height = clamp(pixmp->height, frame_height_min(inst),
drivers/media/platform/qcom/venus/vdec.c
210
frame_height_max(inst));
drivers/media/platform/qcom/venus/vdec.c
242
struct venus_inst *inst = to_inst(file);
drivers/media/platform/qcom/venus/vdec.c
244
vdec_try_fmt_common(inst, f);
drivers/media/platform/qcom/venus/vdec.c
249
static int vdec_check_src_change(struct venus_inst *inst)
drivers/media/platform/qcom/venus/vdec.c
253
if (inst->subscriptions & V4L2_EVENT_SOURCE_CHANGE &&
drivers/media/platform/qcom/venus/vdec.c
254
inst->codec_state == VENUS_DEC_STATE_INIT &&
drivers/media/platform/qcom/venus/vdec.c
255
!inst->reconfig)
drivers/media/platform/qcom/venus/vdec.c
258
if (inst->subscriptions & V4L2_EVENT_SOURCE_CHANGE)
drivers/media/platform/qcom/venus/vdec.c
267
if (inst->codec_state != VENUS_DEC_STATE_INIT)
drivers/media/platform/qcom/venus/vdec.c
270
ret = wait_event_timeout(inst->reconf_wait, inst->reconfig,
drivers/media/platform/qcom/venus/vdec.c
275
if (!(inst->codec_state == VENUS_DEC_STATE_CAPTURE_SETUP) ||
drivers/media/platform/qcom/venus/vdec.c
276
!inst->reconfig)
drivers/media/platform/qcom/venus/vdec.c
277
dev_dbg(inst->core->dev, VDBGH "wrong state\n");
drivers/media/platform/qcom/venus/vdec.c
285
struct venus_inst *inst = to_inst(file);
drivers/media/platform/qcom/venus/vdec.c
291
fmt = inst->fmt_cap;
drivers/media/platform/qcom/venus/vdec.c
293
fmt = inst->fmt_out;
drivers/media/platform/qcom/venus/vdec.c
296
ret = vdec_check_src_change(inst);
drivers/media/platform/qcom/venus/vdec.c
304
pixmp->width = inst->width;
drivers/media/platform/qcom/venus/vdec.c
305
pixmp->height = inst->height;
drivers/media/platform/qcom/venus/vdec.c
306
pixmp->colorspace = inst->colorspace;
drivers/media/platform/qcom/venus/vdec.c
307
pixmp->ycbcr_enc = inst->ycbcr_enc;
drivers/media/platform/qcom/venus/vdec.c
308
pixmp->quantization = inst->quantization;
drivers/media/platform/qcom/venus/vdec.c
309
pixmp->xfer_func = inst->xfer_func;
drivers/media/platform/qcom/venus/vdec.c
311
pixmp->width = inst->out_width;
drivers/media/platform/qcom/venus/vdec.c
312
pixmp->height = inst->out_height;
drivers/media/platform/qcom/venus/vdec.c
315
vdec_try_fmt_common(inst, f);
drivers/media/platform/qcom/venus/vdec.c
322
struct venus_inst *inst = to_inst(file);
drivers/media/platform/qcom/venus/vdec.c
330
q = v4l2_m2m_get_vq(inst->m2m_ctx, f->type);
drivers/media/platform/qcom/venus/vdec.c
337
fmt = vdec_try_fmt_common(inst, f);
drivers/media/platform/qcom/venus/vdec.c
341
pixfmt_cap = inst->fmt_cap->pixfmt;
drivers/media/platform/qcom/venus/vdec.c
344
pixfmt_out = inst->fmt_out->pixfmt;
drivers/media/platform/qcom/venus/vdec.c
353
vdec_try_fmt_common(inst, &format);
drivers/media/platform/qcom/venus/vdec.c
356
inst->out_width = format.fmt.pix_mp.width;
drivers/media/platform/qcom/venus/vdec.c
357
inst->out_height = format.fmt.pix_mp.height;
drivers/media/platform/qcom/venus/vdec.c
358
inst->colorspace = pixmp->colorspace;
drivers/media/platform/qcom/venus/vdec.c
359
inst->ycbcr_enc = pixmp->ycbcr_enc;
drivers/media/platform/qcom/venus/vdec.c
360
inst->quantization = pixmp->quantization;
drivers/media/platform/qcom/venus/vdec.c
361
inst->xfer_func = pixmp->xfer_func;
drivers/media/platform/qcom/venus/vdec.c
362
inst->input_buf_size = pixmp->plane_fmt[0].sizeimage;
drivers/media/platform/qcom/venus/vdec.c
371
vdec_try_fmt_common(inst, &format);
drivers/media/platform/qcom/venus/vdec.c
373
inst->width = format.fmt.pix_mp.width;
drivers/media/platform/qcom/venus/vdec.c
374
inst->height = format.fmt.pix_mp.height;
drivers/media/platform/qcom/venus/vdec.c
375
inst->crop.top = 0;
drivers/media/platform/qcom/venus/vdec.c
376
inst->crop.left = 0;
drivers/media/platform/qcom/venus/vdec.c
377
inst->crop.width = inst->width;
drivers/media/platform/qcom/venus/vdec.c
378
inst->crop.height = inst->height;
drivers/media/platform/qcom/venus/vdec.c
381
inst->fmt_out = fmt;
drivers/media/platform/qcom/venus/vdec.c
383
inst->fmt_cap = fmt;
drivers/media/platform/qcom/venus/vdec.c
384
inst->output2_buf_size =
drivers/media/platform/qcom/venus/vdec.c
394
struct venus_inst *inst = to_inst(file);
drivers/media/platform/qcom/venus/vdec.c
409
s->r.width = inst->out_width;
drivers/media/platform/qcom/venus/vdec.c
410
s->r.height = inst->out_height;
drivers/media/platform/qcom/venus/vdec.c
416
s->r.width = inst->width;
drivers/media/platform/qcom/venus/vdec.c
417
s->r.height = inst->height;
drivers/media/platform/qcom/venus/vdec.c
423
s->r = inst->crop;
drivers/media/platform/qcom/venus/vdec.c
435
struct venus_inst *inst = to_inst(file);
drivers/media/platform/qcom/venus/vdec.c
436
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/vdec.c
448
struct venus_inst *inst = to_inst(file);
drivers/media/platform/qcom/venus/vdec.c
453
fmt = find_format_by_index(inst, f->index, f->type);
drivers/media/platform/qcom/venus/vdec.c
465
struct venus_inst *inst = to_inst(file);
drivers/media/platform/qcom/venus/vdec.c
476
timeperframe->denominator = inst->timeperframe.denominator;
drivers/media/platform/qcom/venus/vdec.c
478
timeperframe->numerator = inst->timeperframe.numerator;
drivers/media/platform/qcom/venus/vdec.c
489
inst->fps = fps;
drivers/media/platform/qcom/venus/vdec.c
490
inst->timeperframe = *timeperframe;
drivers/media/platform/qcom/venus/vdec.c
498
struct venus_inst *inst = to_inst(file);
drivers/media/platform/qcom/venus/vdec.c
501
fmt = find_format(inst, fsize->pixel_format,
drivers/media/platform/qcom/venus/vdec.c
504
fmt = find_format(inst, fsize->pixel_format,
drivers/media/platform/qcom/venus/vdec.c
515
fsize->stepwise.min_width = frame_width_min(inst);
drivers/media/platform/qcom/venus/vdec.c
516
fsize->stepwise.max_width = frame_width_max(inst);
drivers/media/platform/qcom/venus/vdec.c
517
fsize->stepwise.step_width = frame_width_step(inst);
drivers/media/platform/qcom/venus/vdec.c
518
fsize->stepwise.min_height = frame_height_min(inst);
drivers/media/platform/qcom/venus/vdec.c
519
fsize->stepwise.max_height = frame_height_max(inst);
drivers/media/platform/qcom/venus/vdec.c
520
fsize->stepwise.step_height = frame_height_step(inst);
drivers/media/platform/qcom/venus/vdec.c
528
struct venus_inst *inst = container_of(fh, struct venus_inst, fh);
drivers/media/platform/qcom/venus/vdec.c
538
inst->subscriptions |= V4L2_EVENT_SOURCE_CHANGE;
drivers/media/platform/qcom/venus/vdec.c
550
struct venus_inst *inst = to_inst(file);
drivers/media/platform/qcom/venus/vdec.c
559
mutex_lock(&inst->lock);
drivers/media/platform/qcom/venus/vdec.c
566
if (!(inst->streamon_out && inst->streamon_cap))
drivers/media/platform/qcom/venus/vdec.c
577
if (IS_IRIS2(inst->core) && is_fw_rev_or_older(inst->core, 1, 0, 87))
drivers/media/platform/qcom/venus/vdec.c
582
ret = hfi_session_process_buf(inst, &fdata);
drivers/media/platform/qcom/venus/vdec.c
584
if (!ret && inst->codec_state == VENUS_DEC_STATE_DECODING) {
drivers/media/platform/qcom/venus/vdec.c
585
inst->codec_state = VENUS_DEC_STATE_DRAIN;
drivers/media/platform/qcom/venus/vdec.c
586
inst->drain_active = true;
drivers/media/platform/qcom/venus/vdec.c
589
inst->codec_state == VENUS_DEC_STATE_STOPPED) {
drivers/media/platform/qcom/venus/vdec.c
590
dst_vq = v4l2_m2m_get_vq(inst->fh.m2m_ctx,
drivers/media/platform/qcom/venus/vdec.c
594
inst->codec_state = VENUS_DEC_STATE_DECODING;
drivers/media/platform/qcom/venus/vdec.c
598
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/vdec.c
630
static int vdec_pm_get(struct venus_inst *inst)
drivers/media/platform/qcom/venus/vdec.c
632
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/vdec.c
643
static int vdec_pm_put(struct venus_inst *inst, bool autosuspend)
drivers/media/platform/qcom/venus/vdec.c
645
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/vdec.c
661
static int vdec_pm_get_put(struct venus_inst *inst)
drivers/media/platform/qcom/venus/vdec.c
663
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/vdec.c
683
static void vdec_pm_touch(struct venus_inst *inst)
drivers/media/platform/qcom/venus/vdec.c
685
pm_runtime_mark_last_busy(inst->core->dev_dec);
drivers/media/platform/qcom/venus/vdec.c
688
static int vdec_set_properties(struct venus_inst *inst)
drivers/media/platform/qcom/venus/vdec.c
690
struct vdec_controls *ctr = &inst->controls.dec;
drivers/media/platform/qcom/venus/vdec.c
697
ret = hfi_session_set_property(inst, ptype, &en);
drivers/media/platform/qcom/venus/vdec.c
705
ret = hfi_session_set_property(inst, ptype, &decode_order);
drivers/media/platform/qcom/venus/vdec.c
711
if (is_fw_rev_or_newer(inst->core, 5, 4, 51)) {
drivers/media/platform/qcom/venus/vdec.c
713
ret = hfi_session_set_property(inst, ptype, &en);
drivers/media/platform/qcom/venus/vdec.c
723
ret = hfi_session_set_property(inst, ptype, &conceal);
drivers/media/platform/qcom/venus/vdec.c
730
static int vdec_set_work_route(struct venus_inst *inst)
drivers/media/platform/qcom/venus/vdec.c
735
if (!(IS_IRIS2(inst->core) || IS_IRIS2_1(inst->core)))
drivers/media/platform/qcom/venus/vdec.c
738
wr.video_work_route = inst->core->res->num_vpp_pipes;
drivers/media/platform/qcom/venus/vdec.c
740
return hfi_session_set_property(inst, ptype, &wr);
drivers/media/platform/qcom/venus/vdec.c
748
static int vdec_output_conf(struct venus_inst *inst)
drivers/media/platform/qcom/venus/vdec.c
750
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/vdec.c
753
u32 width = inst->width;
drivers/media/platform/qcom/venus/vdec.c
754
u32 height = inst->height;
drivers/media/platform/qcom/venus/vdec.c
760
ret = venus_helper_set_work_mode(inst);
drivers/media/platform/qcom/venus/vdec.c
766
ret = hfi_session_set_property(inst, ptype, &en);
drivers/media/platform/qcom/venus/vdec.c
779
ret = venus_helper_get_out_fmts(inst, inst->fmt_cap->pixfmt, &out_fmt,
drivers/media/platform/qcom/venus/vdec.c
784
inst->output_buf_size =
drivers/media/platform/qcom/venus/vdec.c
786
inst->output2_buf_size =
drivers/media/platform/qcom/venus/vdec.c
790
inst->opb_buftype = HFI_BUFFER_OUTPUT2;
drivers/media/platform/qcom/venus/vdec.c
791
inst->opb_fmt = out2_fmt;
drivers/media/platform/qcom/venus/vdec.c
792
inst->dpb_buftype = HFI_BUFFER_OUTPUT;
drivers/media/platform/qcom/venus/vdec.c
793
inst->dpb_fmt = out_fmt;
drivers/media/platform/qcom/venus/vdec.c
795
inst->opb_buftype = HFI_BUFFER_OUTPUT;
drivers/media/platform/qcom/venus/vdec.c
796
inst->opb_fmt = out_fmt;
drivers/media/platform/qcom/venus/vdec.c
797
inst->dpb_buftype = HFI_BUFFER_OUTPUT2;
drivers/media/platform/qcom/venus/vdec.c
798
inst->dpb_fmt = out2_fmt;
drivers/media/platform/qcom/venus/vdec.c
800
inst->opb_buftype = HFI_BUFFER_OUTPUT;
drivers/media/platform/qcom/venus/vdec.c
801
inst->opb_fmt = out_fmt;
drivers/media/platform/qcom/venus/vdec.c
802
inst->dpb_buftype = 0;
drivers/media/platform/qcom/venus/vdec.c
803
inst->dpb_fmt = 0;
drivers/media/platform/qcom/venus/vdec.c
806
ret = venus_helper_set_raw_format(inst, inst->opb_fmt,
drivers/media/platform/qcom/venus/vdec.c
807
inst->opb_buftype);
drivers/media/platform/qcom/venus/vdec.c
811
ret = venus_helper_set_format_constraints(inst);
drivers/media/platform/qcom/venus/vdec.c
815
if (inst->dpb_fmt) {
drivers/media/platform/qcom/venus/vdec.c
816
ret = venus_helper_set_multistream(inst, false, true);
drivers/media/platform/qcom/venus/vdec.c
820
ret = venus_helper_set_raw_format(inst, inst->dpb_fmt,
drivers/media/platform/qcom/venus/vdec.c
821
inst->dpb_buftype);
drivers/media/platform/qcom/venus/vdec.c
825
ret = venus_helper_set_output_resolution(inst, width, height,
drivers/media/platform/qcom/venus/vdec.c
832
ret = venus_helper_get_bufreq(inst, HFI_BUFFER_OUTPUT, &bufreq);
drivers/media/platform/qcom/venus/vdec.c
836
if (bufreq.size > inst->output_buf_size)
drivers/media/platform/qcom/venus/vdec.c
839
if (inst->dpb_fmt) {
drivers/media/platform/qcom/venus/vdec.c
840
ret = venus_helper_get_bufreq(inst, HFI_BUFFER_OUTPUT2,
drivers/media/platform/qcom/venus/vdec.c
845
if (bufreq.size > inst->output2_buf_size)
drivers/media/platform/qcom/venus/vdec.c
849
if (inst->output2_buf_size) {
drivers/media/platform/qcom/venus/vdec.c
850
ret = venus_helper_set_bufsize(inst,
drivers/media/platform/qcom/venus/vdec.c
851
inst->output2_buf_size,
drivers/media/platform/qcom/venus/vdec.c
857
if (inst->output_buf_size) {
drivers/media/platform/qcom/venus/vdec.c
858
ret = venus_helper_set_bufsize(inst,
drivers/media/platform/qcom/venus/vdec.c
859
inst->output_buf_size,
drivers/media/platform/qcom/venus/vdec.c
866
ret = venus_helper_set_dyn_bufmode(inst);
drivers/media/platform/qcom/venus/vdec.c
873
static int vdec_session_init(struct venus_inst *inst)
drivers/media/platform/qcom/venus/vdec.c
877
ret = venus_helper_session_init(inst);
drivers/media/platform/qcom/venus/vdec.c
883
ret = venus_helper_set_input_resolution(inst, frame_width_min(inst),
drivers/media/platform/qcom/venus/vdec.c
884
frame_height_min(inst));
drivers/media/platform/qcom/venus/vdec.c
890
hfi_session_deinit(inst);
drivers/media/platform/qcom/venus/vdec.c
894
static int vdec_num_buffers(struct venus_inst *inst, unsigned int *in_num,
drivers/media/platform/qcom/venus/vdec.c
897
enum hfi_version ver = inst->core->res->hfi_version;
drivers/media/platform/qcom/venus/vdec.c
903
ret = venus_helper_get_bufreq(inst, HFI_BUFFER_INPUT, &bufreq);
drivers/media/platform/qcom/venus/vdec.c
909
ret = venus_helper_get_bufreq(inst, HFI_BUFFER_OUTPUT, &bufreq);
drivers/media/platform/qcom/venus/vdec.c
922
struct venus_inst *inst = vb2_get_drv_priv(q);
drivers/media/platform/qcom/venus/vdec.c
923
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/vdec.c
928
unsigned int output_buf_size = venus_helper_get_opb_size(inst);
drivers/media/platform/qcom/venus/vdec.c
931
*num_planes != inst->fmt_out->num_planes)
drivers/media/platform/qcom/venus/vdec.c
935
*num_planes != inst->fmt_cap->num_planes)
drivers/media/platform/qcom/venus/vdec.c
939
sizes[0] < inst->input_buf_size)
drivers/media/platform/qcom/venus/vdec.c
950
if (inst->nonblock)
drivers/media/platform/qcom/venus/vdec.c
959
ret = vdec_pm_get(inst);
drivers/media/platform/qcom/venus/vdec.c
963
ret = vdec_session_init(inst);
drivers/media/platform/qcom/venus/vdec.c
967
ret = vdec_num_buffers(inst, &in_num, &out_num);
drivers/media/platform/qcom/venus/vdec.c
971
ret = vdec_pm_put(inst, false);
drivers/media/platform/qcom/venus/vdec.c
977
*num_planes = inst->fmt_out->num_planes;
drivers/media/platform/qcom/venus/vdec.c
978
sizes[0] = venus_helper_get_framesz(inst->fmt_out->pixfmt,
drivers/media/platform/qcom/venus/vdec.c
979
inst->out_width,
drivers/media/platform/qcom/venus/vdec.c
980
inst->out_height);
drivers/media/platform/qcom/venus/vdec.c
981
sizes[0] = max(sizes[0], inst->input_buf_size);
drivers/media/platform/qcom/venus/vdec.c
982
inst->input_buf_size = sizes[0];
drivers/media/platform/qcom/venus/vdec.c
984
inst->num_input_bufs = *num_buffers;
drivers/media/platform/qcom/venus/vdec.c
985
inst->num_output_bufs = out_num;
drivers/media/platform/qcom/venus/vdec.c
988
*num_planes = inst->fmt_cap->num_planes;
drivers/media/platform/qcom/venus/vdec.c
989
sizes[0] = venus_helper_get_framesz(inst->fmt_cap->pixfmt,
drivers/media/platform/qcom/venus/vdec.c
990
inst->width,
drivers/media/platform/qcom/venus/vdec.c
991
inst->height);
drivers/media/platform/qcom/venus/vdec.c
992
inst->output_buf_size = sizes[0];
drivers/media/platform/qcom/venus/vdec.c
994
inst->num_output_bufs = *num_buffers;
drivers/media/platform/qcom/venus/vdec.c
996
mutex_lock(&inst->lock);
drivers/media/platform/qcom/venus/vdec.c
997
if (inst->codec_state == VENUS_DEC_STATE_CAPTURE_SETUP)
drivers/media/platform/qcom/venus/vdec.c
998
inst->codec_state = VENUS_DEC_STATE_STOPPED;
drivers/media/platform/qcom/venus/vdec.c
999
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/vdec.h
11
int vdec_ctrl_init(struct venus_inst *inst);
drivers/media/platform/qcom/venus/vdec_ctrls.c
101
ret = v4l2_ctrl_handler_init(&inst->ctrl_handler, 12);
drivers/media/platform/qcom/venus/vdec_ctrls.c
105
ctrl = v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &vdec_ctrl_ops,
drivers/media/platform/qcom/venus/vdec_ctrls.c
114
ctrl = v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &vdec_ctrl_ops,
drivers/media/platform/qcom/venus/vdec_ctrls.c
121
ctrl = v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &vdec_ctrl_ops,
drivers/media/platform/qcom/venus/vdec_ctrls.c
134
ctrl = v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &vdec_ctrl_ops,
drivers/media/platform/qcom/venus/vdec_ctrls.c
141
ctrl = v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &vdec_ctrl_ops,
drivers/media/platform/qcom/venus/vdec_ctrls.c
148
ctrl = v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &vdec_ctrl_ops,
drivers/media/platform/qcom/venus/vdec_ctrls.c
15
struct venus_inst *inst = ctrl_to_inst(ctrl);
drivers/media/platform/qcom/venus/vdec_ctrls.c
155
ctrl = v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &vdec_ctrl_ops,
drivers/media/platform/qcom/venus/vdec_ctrls.c
16
struct vdec_controls *ctr = &inst->controls.dec;
drivers/media/platform/qcom/venus/vdec_ctrls.c
162
v4l2_ctrl_new_std(&inst->ctrl_handler, &vdec_ctrl_ops,
drivers/media/platform/qcom/venus/vdec_ctrls.c
165
ctrl = v4l2_ctrl_new_std(&inst->ctrl_handler, &vdec_ctrl_ops,
drivers/media/platform/qcom/venus/vdec_ctrls.c
170
v4l2_ctrl_new_std(&inst->ctrl_handler, &vdec_ctrl_ops,
drivers/media/platform/qcom/venus/vdec_ctrls.c
174
v4l2_ctrl_new_std(&inst->ctrl_handler, &vdec_ctrl_ops,
drivers/media/platform/qcom/venus/vdec_ctrls.c
178
v4l2_ctrl_new_std(&inst->ctrl_handler, &vdec_ctrl_ops,
drivers/media/platform/qcom/venus/vdec_ctrls.c
182
ret = inst->ctrl_handler.error;
drivers/media/platform/qcom/venus/vdec_ctrls.c
184
v4l2_ctrl_handler_free(&inst->ctrl_handler);
drivers/media/platform/qcom/venus/vdec_ctrls.c
51
struct venus_inst *inst = ctrl_to_inst(ctrl);
drivers/media/platform/qcom/venus/vdec_ctrls.c
52
struct vdec_controls *ctr = &inst->controls.dec;
drivers/media/platform/qcom/venus/vdec_ctrls.c
54
enum hfi_version ver = inst->core->res->hfi_version;
drivers/media/platform/qcom/venus/vdec_ctrls.c
63
ret = venus_helper_get_profile_level(inst, &profile, &level);
drivers/media/platform/qcom/venus/vdec_ctrls.c
71
ret = venus_helper_get_profile_level(inst, &profile, &level);
drivers/media/platform/qcom/venus/vdec_ctrls.c
80
ret = venus_helper_get_bufreq(inst, HFI_BUFFER_OUTPUT, &bufreq);
drivers/media/platform/qcom/venus/vdec_ctrls.c
96
int vdec_ctrl_init(struct venus_inst *inst)
drivers/media/platform/qcom/venus/venc.c
1003
mbs = ALIGN(inst->width, 16) * ALIGN(inst->height, 16);
drivers/media/platform/qcom/venus/venc.c
1019
ret = hfi_session_set_property(inst, ptype, &intra_refresh);
drivers/media/platform/qcom/venus/venc.c
1027
static int venc_init_session(struct venus_inst *inst)
drivers/media/platform/qcom/venus/venc.c
1031
ret = venus_helper_session_init(inst);
drivers/media/platform/qcom/venus/venc.c
1037
ret = venus_helper_set_stride(inst, inst->out_width,
drivers/media/platform/qcom/venus/venc.c
1038
inst->out_height);
drivers/media/platform/qcom/venus/venc.c
104
venus_helper_check_codec(inst, fmt[i].pixfmt);
drivers/media/platform/qcom/venus/venc.c
1042
ret = venus_helper_set_input_resolution(inst, inst->width,
drivers/media/platform/qcom/venus/venc.c
1043
inst->height);
drivers/media/platform/qcom/venus/venc.c
1047
ret = venus_helper_set_output_resolution(inst, inst->width,
drivers/media/platform/qcom/venus/venc.c
1048
inst->height,
drivers/media/platform/qcom/venus/venc.c
1053
ret = venus_helper_set_color_format(inst, inst->fmt_out->pixfmt);
drivers/media/platform/qcom/venus/venc.c
1057
ret = venc_set_properties(inst);
drivers/media/platform/qcom/venus/venc.c
1063
hfi_session_deinit(inst);
drivers/media/platform/qcom/venus/venc.c
1067
static int venc_out_num_buffers(struct venus_inst *inst, unsigned int *num)
drivers/media/platform/qcom/venus/venc.c
1072
ret = venus_helper_get_bufreq(inst, HFI_BUFFER_INPUT, &bufreq);
drivers/media/platform/qcom/venus/venc.c
1085
struct venus_inst *inst = vb2_get_drv_priv(q);
drivers/media/platform/qcom/venus/venc.c
1086
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/venc.c
1092
*num_planes != inst->fmt_out->num_planes)
drivers/media/platform/qcom/venus/venc.c
1096
*num_planes != inst->fmt_cap->num_planes)
drivers/media/platform/qcom/venus/venc.c
1100
sizes[0] < inst->input_buf_size)
drivers/media/platform/qcom/venus/venc.c
1104
sizes[0] < inst->output_buf_size)
drivers/media/platform/qcom/venus/venc.c
1111
if (inst->nonblock)
drivers/media/platform/qcom/venus/venc.c
1120
ret = venc_pm_get(inst);
drivers/media/platform/qcom/venus/venc.c
1124
mutex_lock(&inst->lock);
drivers/media/platform/qcom/venus/venc.c
1125
ret = venc_init_session(inst);
drivers/media/platform/qcom/venus/venc.c
1126
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/venc.c
1131
ret = venc_pm_put(inst, false);
drivers/media/platform/qcom/venus/venc.c
1137
*num_planes = inst->fmt_out->num_planes;
drivers/media/platform/qcom/venus/venc.c
1139
ret = venc_out_num_buffers(inst, &num);
drivers/media/platform/qcom/venus/venc.c
1145
inst->num_input_bufs = *num_buffers;
drivers/media/platform/qcom/venus/venc.c
1147
sizes[0] = venus_helper_get_framesz(inst->fmt_out->pixfmt,
drivers/media/platform/qcom/venus/venc.c
1148
inst->out_width,
drivers/media/platform/qcom/venus/venc.c
1149
inst->out_height);
drivers/media/platform/qcom/venus/venc.c
1150
inst->input_buf_size = sizes[0];
drivers/media/platform/qcom/venus/venc.c
1153
*num_planes = inst->fmt_cap->num_planes;
drivers/media/platform/qcom/venus/venc.c
1155
inst->num_output_bufs = *num_buffers;
drivers/media/platform/qcom/venus/venc.c
1156
sizes[0] = venus_helper_get_framesz(inst->fmt_cap->pixfmt,
drivers/media/platform/qcom/venus/venc.c
1157
inst->width,
drivers/media/platform/qcom/venus/venc.c
1158
inst->height);
drivers/media/platform/qcom/venus/venc.c
1159
sizes[0] = max(sizes[0], inst->output_buf_size);
drivers/media/platform/qcom/venus/venc.c
1160
inst->output_buf_size = sizes[0];
drivers/media/platform/qcom/venus/venc.c
1169
venc_pm_put(inst, false);
drivers/media/platform/qcom/venus/venc.c
1175
struct venus_inst *inst = vb2_get_drv_priv(vb->vb2_queue);
drivers/media/platform/qcom/venus/venc.c
1177
inst->buf_count++;
drivers/media/platform/qcom/venus/venc.c
1182
static void venc_release_session(struct venus_inst *inst)
drivers/media/platform/qcom/venus/venc.c
1186
venc_pm_get(inst);
drivers/media/platform/qcom/venus/venc.c
1188
mutex_lock(&inst->lock);
drivers/media/platform/qcom/venus/venc.c
1190
ret = hfi_session_deinit(inst);
drivers/media/platform/qcom/venus/venc.c
1191
if (ret || inst->session_error)
drivers/media/platform/qcom/venus/venc.c
1192
hfi_session_abort(inst);
drivers/media/platform/qcom/venus/venc.c
1194
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/venc.c
1196
venus_pm_load_scale(inst);
drivers/media/platform/qcom/venus/venc.c
1197
INIT_LIST_HEAD(&inst->registeredbufs);
drivers/media/platform/qcom/venus/venc.c
1198
venus_pm_release_core(inst);
drivers/media/platform/qcom/venus/venc.c
1200
venc_pm_put(inst, false);
drivers/media/platform/qcom/venus/venc.c
1205
struct venus_inst *inst = vb2_get_drv_priv(vb->vb2_queue);
drivers/media/platform/qcom/venus/venc.c
1209
mutex_lock(&inst->lock);
drivers/media/platform/qcom/venus/venc.c
1211
if (!list_empty(&inst->registeredbufs))
drivers/media/platform/qcom/venus/venc.c
1213
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/venc.c
1215
inst->buf_count--;
drivers/media/platform/qcom/venus/venc.c
1216
if (!inst->buf_count)
drivers/media/platform/qcom/venus/venc.c
1217
venc_release_session(inst);
drivers/media/platform/qcom/venus/venc.c
1220
static int venc_verify_conf(struct venus_inst *inst)
drivers/media/platform/qcom/venus/venc.c
1222
enum hfi_version ver = inst->core->res->hfi_version;
drivers/media/platform/qcom/venus/venc.c
1226
if (!inst->num_input_bufs || !inst->num_output_bufs)
drivers/media/platform/qcom/venus/venc.c
1229
ret = venus_helper_get_bufreq(inst, HFI_BUFFER_OUTPUT, &bufreq);
drivers/media/platform/qcom/venus/venc.c
1233
if (inst->num_output_bufs < bufreq.count_actual ||
drivers/media/platform/qcom/venus/venc.c
1234
inst->num_output_bufs < hfi_bufreq_get_count_min(&bufreq, ver))
drivers/media/platform/qcom/venus/venc.c
1237
ret = venus_helper_get_bufreq(inst, HFI_BUFFER_INPUT, &bufreq);
drivers/media/platform/qcom/venus/venc.c
1241
if (inst->num_input_bufs < bufreq.count_actual ||
drivers/media/platform/qcom/venus/venc.c
1242
inst->num_input_bufs < hfi_bufreq_get_count_min(&bufreq, ver))
drivers/media/platform/qcom/venus/venc.c
1250
struct venus_inst *inst = vb2_get_drv_priv(q);
drivers/media/platform/qcom/venus/venc.c
1253
mutex_lock(&inst->lock);
drivers/media/platform/qcom/venus/venc.c
1256
inst->streamon_out = 1;
drivers/media/platform/qcom/venus/venc.c
1258
inst->streamon_cap = 1;
drivers/media/platform/qcom/venus/venc.c
1260
if (!(inst->streamon_out & inst->streamon_cap)) {
drivers/media/platform/qcom/venus/venc.c
1261
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/venc.c
1265
venus_helper_init_instance(inst);
drivers/media/platform/qcom/venus/venc.c
1267
inst->sequence_cap = 0;
drivers/media/platform/qcom/venus/venc.c
1268
inst->sequence_out = 0;
drivers/media/platform/qcom/venus/venc.c
1270
ret = venc_pm_get(inst);
drivers/media/platform/qcom/venus/venc.c
1274
ret = venus_pm_acquire_core(inst);
drivers/media/platform/qcom/venus/venc.c
1278
ret = venc_pm_put(inst, true);
drivers/media/platform/qcom/venus/venc.c
1282
ret = venc_set_properties(inst);
drivers/media/platform/qcom/venus/venc.c
1286
ret = venc_verify_conf(inst);
drivers/media/platform/qcom/venus/venc.c
1290
ret = venus_helper_set_num_bufs(inst, inst->num_input_bufs,
drivers/media/platform/qcom/venus/venc.c
1291
inst->num_output_bufs, 0);
drivers/media/platform/qcom/venus/venc.c
1295
ret = venus_helper_vb2_start_streaming(inst);
drivers/media/platform/qcom/venus/venc.c
1299
inst->enc_state = VENUS_ENC_STATE_ENCODING;
drivers/media/platform/qcom/venus/venc.c
1301
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/venc.c
1306
venc_pm_put(inst, false);
drivers/media/platform/qcom/venus/venc.c
1308
venus_helper_buffers_done(inst, q->type, VB2_BUF_STATE_QUEUED);
drivers/media/platform/qcom/venus/venc.c
1310
inst->streamon_out = 0;
drivers/media/platform/qcom/venus/venc.c
1312
inst->streamon_cap = 0;
drivers/media/platform/qcom/venus/venc.c
1313
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/venc.c
1319
struct venus_inst *inst = vb2_get_drv_priv(vb->vb2_queue);
drivers/media/platform/qcom/venus/venc.c
1322
venc_pm_get_put(inst);
drivers/media/platform/qcom/venus/venc.c
1324
mutex_lock(&inst->lock);
drivers/media/platform/qcom/venus/venc.c
1326
if (inst->enc_state == VENUS_ENC_STATE_STOPPED) {
drivers/media/platform/qcom/venus/venc.c
1327
vbuf->sequence = inst->sequence_cap++;
drivers/media/platform/qcom/venus/venc.c
1331
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/venc.c
1336
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/venc.c
1349
static void venc_buf_done(struct venus_inst *inst, unsigned int buf_type,
drivers/media/platform/qcom/venus/venc.c
1357
venc_pm_touch(inst);
drivers/media/platform/qcom/venus/venc.c
1364
vbuf = venus_helper_find_buf(inst, type, tag);
drivers/media/platform/qcom/venus/venc.c
1375
vbuf->sequence = inst->sequence_cap++;
drivers/media/platform/qcom/venus/venc.c
1377
inst->enc_state == VENUS_ENC_STATE_DRAIN) {
drivers/media/platform/qcom/venus/venc.c
1378
inst->enc_state = VENUS_ENC_STATE_STOPPED;
drivers/media/platform/qcom/venus/venc.c
1381
vbuf->sequence = inst->sequence_out++;
drivers/media/platform/qcom/venus/venc.c
1387
static void venc_event_notify(struct venus_inst *inst, u32 event,
drivers/media/platform/qcom/venus/venc.c
1390
struct device *dev = inst->core->dev_enc;
drivers/media/platform/qcom/venus/venc.c
1392
venc_pm_touch(inst);
drivers/media/platform/qcom/venus/venc.c
1395
inst->session_error = true;
drivers/media/platform/qcom/venus/venc.c
1396
venus_helper_vb2_queue_error(inst);
drivers/media/platform/qcom/venus/venc.c
1397
dev_err(dev, "enc: event session error %x\n", inst->error);
drivers/media/platform/qcom/venus/venc.c
1414
struct venus_inst *inst = priv;
drivers/media/platform/qcom/venus/venc.c
1422
src_vq->drv_priv = inst;
drivers/media/platform/qcom/venus/venc.c
1426
src_vq->dev = inst->core->dev;
drivers/media/platform/qcom/venus/venc.c
1427
src_vq->lock = &inst->ctx_q_lock;
drivers/media/platform/qcom/venus/venc.c
1428
if (inst->core->res->hfi_version == HFI_VERSION_1XX)
drivers/media/platform/qcom/venus/venc.c
1439
dst_vq->drv_priv = inst;
drivers/media/platform/qcom/venus/venc.c
1443
dst_vq->dev = inst->core->dev;
drivers/media/platform/qcom/venus/venc.c
1444
dst_vq->lock = &inst->ctx_q_lock;
drivers/media/platform/qcom/venus/venc.c
1448
static void venc_inst_init(struct venus_inst *inst)
drivers/media/platform/qcom/venus/venc.c
1450
inst->fmt_cap = &venc_formats[VENUS_FMT_H264];
drivers/media/platform/qcom/venus/venc.c
1451
inst->fmt_out = &venc_formats[VENUS_FMT_NV12];
drivers/media/platform/qcom/venus/venc.c
1452
inst->width = 1280;
drivers/media/platform/qcom/venus/venc.c
1453
inst->height = ALIGN(720, 32);
drivers/media/platform/qcom/venus/venc.c
1454
inst->out_width = 1280;
drivers/media/platform/qcom/venus/venc.c
1455
inst->out_height = 720;
drivers/media/platform/qcom/venus/venc.c
1456
inst->fps = 15;
drivers/media/platform/qcom/venus/venc.c
1457
inst->timeperframe.numerator = 1;
drivers/media/platform/qcom/venus/venc.c
1458
inst->timeperframe.denominator = 15;
drivers/media/platform/qcom/venus/venc.c
1459
inst->hfi_codec = HFI_VIDEO_CODEC_H264;
drivers/media/platform/qcom/venus/venc.c
146
struct venus_inst *inst = to_inst(file);
drivers/media/platform/qcom/venus/venc.c
1465
struct venus_inst *inst;
drivers/media/platform/qcom/venus/venc.c
1468
inst = kzalloc_obj(*inst);
drivers/media/platform/qcom/venus/venc.c
1469
if (!inst)
drivers/media/platform/qcom/venus/venc.c
147
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/venc.c
1472
INIT_LIST_HEAD(&inst->dpbbufs);
drivers/media/platform/qcom/venus/venc.c
1473
INIT_LIST_HEAD(&inst->registeredbufs);
drivers/media/platform/qcom/venus/venc.c
1474
INIT_LIST_HEAD(&inst->internalbufs);
drivers/media/platform/qcom/venus/venc.c
1475
INIT_LIST_HEAD(&inst->list);
drivers/media/platform/qcom/venus/venc.c
1476
mutex_init(&inst->lock);
drivers/media/platform/qcom/venus/venc.c
1477
mutex_init(&inst->ctx_q_lock);
drivers/media/platform/qcom/venus/venc.c
1479
inst->core = core;
drivers/media/platform/qcom/venus/venc.c
1480
inst->session_type = VIDC_SESSION_TYPE_ENC;
drivers/media/platform/qcom/venus/venc.c
1481
inst->clk_data.core_id = VIDC_CORE_ID_DEFAULT;
drivers/media/platform/qcom/venus/venc.c
1482
inst->core_acquired = false;
drivers/media/platform/qcom/venus/venc.c
1483
inst->nonblock = file->f_flags & O_NONBLOCK;
drivers/media/platform/qcom/venus/venc.c
1485
if (inst->enc_state == VENUS_ENC_STATE_DEINIT)
drivers/media/platform/qcom/venus/venc.c
1486
inst->enc_state = VENUS_ENC_STATE_INIT;
drivers/media/platform/qcom/venus/venc.c
1488
venus_helper_init_instance(inst);
drivers/media/platform/qcom/venus/venc.c
1490
ret = venc_ctrl_init(inst);
drivers/media/platform/qcom/venus/venc.c
1494
venc_inst_init(inst);
drivers/media/platform/qcom/venus/venc.c
1500
inst->m2m_dev = v4l2_m2m_init(&venc_m2m_ops);
drivers/media/platform/qcom/venus/venc.c
1501
if (IS_ERR(inst->m2m_dev)) {
drivers/media/platform/qcom/venus/venc.c
1502
ret = PTR_ERR(inst->m2m_dev);
drivers/media/platform/qcom/venus/venc.c
1506
inst->m2m_ctx = v4l2_m2m_ctx_init(inst->m2m_dev, inst, m2m_queue_init);
drivers/media/platform/qcom/venus/venc.c
1507
if (IS_ERR(inst->m2m_ctx)) {
drivers/media/platform/qcom/venus/venc.c
1508
ret = PTR_ERR(inst->m2m_ctx);
drivers/media/platform/qcom/venus/venc.c
1512
ret = hfi_session_create(inst, &venc_hfi_ops);
drivers/media/platform/qcom/venus/venc.c
1516
v4l2_fh_init(&inst->fh, core->vdev_enc);
drivers/media/platform/qcom/venus/venc.c
1518
inst->fh.ctrl_handler = &inst->ctrl_handler;
drivers/media/platform/qcom/venus/venc.c
1519
v4l2_fh_add(&inst->fh, file);
drivers/media/platform/qcom/venus/venc.c
1520
inst->fh.m2m_ctx = inst->m2m_ctx;
drivers/media/platform/qcom/venus/venc.c
1525
v4l2_m2m_ctx_release(inst->m2m_ctx);
drivers/media/platform/qcom/venus/venc.c
1527
v4l2_m2m_release(inst->m2m_dev);
drivers/media/platform/qcom/venus/venc.c
1529
v4l2_ctrl_handler_free(&inst->ctrl_handler);
drivers/media/platform/qcom/venus/venc.c
1531
kfree(inst);
drivers/media/platform/qcom/venus/venc.c
1537
struct venus_inst *inst = to_inst(file);
drivers/media/platform/qcom/venus/venc.c
1539
venc_pm_get(inst);
drivers/media/platform/qcom/venus/venc.c
1540
venus_close_common(inst, file);
drivers/media/platform/qcom/venus/venc.c
1541
inst->enc_state = VENUS_ENC_STATE_DEINIT;
drivers/media/platform/qcom/venus/venc.c
1542
venc_pm_put(inst, false);
drivers/media/platform/qcom/venus/venc.c
1544
kfree(inst);
drivers/media/platform/qcom/venus/venc.c
159
struct venus_inst *inst = to_inst(file);
drivers/media/platform/qcom/venus/venc.c
162
fmt = find_format_by_index(inst, f->index, f->type);
drivers/media/platform/qcom/venus/venc.c
175
venc_try_fmt_common(struct venus_inst *inst, struct v4l2_format *f)
drivers/media/platform/qcom/venus/venc.c
185
fmt = find_format(inst, pixmp->pixelformat, f->type);
drivers/media/platform/qcom/venus/venc.c
193
fmt = find_format(inst, pixmp->pixelformat, f->type);
drivers/media/platform/qcom/venus/venc.c
198
pixmp->width = clamp(pixmp->width, frame_width_min(inst),
drivers/media/platform/qcom/venus/venc.c
199
frame_width_max(inst));
drivers/media/platform/qcom/venus/venc.c
200
pixmp->height = clamp(pixmp->height, frame_height_min(inst),
drivers/media/platform/qcom/venus/venc.c
201
frame_height_max(inst));
drivers/media/platform/qcom/venus/venc.c
229
struct venus_inst *inst = to_inst(file);
drivers/media/platform/qcom/venus/venc.c
231
venc_try_fmt_common(inst, f);
drivers/media/platform/qcom/venus/venc.c
238
struct venus_inst *inst = to_inst(file);
drivers/media/platform/qcom/venus/venc.c
246
q = v4l2_m2m_get_vq(inst->m2m_ctx, f->type);
drivers/media/platform/qcom/venus/venc.c
253
fmt = venc_try_fmt_common(inst, f);
drivers/media/platform/qcom/venus/venc.c
259
pixfmt_cap = inst->fmt_cap->pixfmt;
drivers/media/platform/qcom/venus/venc.c
262
pixfmt_out = inst->fmt_out->pixfmt;
drivers/media/platform/qcom/venus/venc.c
271
venc_try_fmt_common(inst, &format);
drivers/media/platform/qcom/venus/venc.c
274
inst->out_width = format.fmt.pix_mp.width;
drivers/media/platform/qcom/venus/venc.c
275
inst->out_height = format.fmt.pix_mp.height;
drivers/media/platform/qcom/venus/venc.c
276
inst->colorspace = pixmp->colorspace;
drivers/media/platform/qcom/venus/venc.c
277
inst->ycbcr_enc = pixmp->ycbcr_enc;
drivers/media/platform/qcom/venus/venc.c
278
inst->quantization = pixmp->quantization;
drivers/media/platform/qcom/venus/venc.c
279
inst->xfer_func = pixmp->xfer_func;
drivers/media/platform/qcom/venus/venc.c
288
venc_try_fmt_common(inst, &format);
drivers/media/platform/qcom/venus/venc.c
290
inst->width = format.fmt.pix_mp.width;
drivers/media/platform/qcom/venus/venc.c
291
inst->height = format.fmt.pix_mp.height;
drivers/media/platform/qcom/venus/venc.c
294
inst->fmt_out = fmt;
drivers/media/platform/qcom/venus/venc.c
296
inst->fmt_cap = fmt;
drivers/media/platform/qcom/venus/venc.c
297
inst->output_buf_size = pixmp->plane_fmt[0].sizeimage;
drivers/media/platform/qcom/venus/venc.c
306
struct venus_inst *inst = to_inst(file);
drivers/media/platform/qcom/venus/venc.c
310
fmt = inst->fmt_cap;
drivers/media/platform/qcom/venus/venc.c
312
fmt = inst->fmt_out;
drivers/media/platform/qcom/venus/venc.c
319
pixmp->width = inst->width;
drivers/media/platform/qcom/venus/venc.c
320
pixmp->height = inst->height;
drivers/media/platform/qcom/venus/venc.c
321
pixmp->colorspace = inst->colorspace;
drivers/media/platform/qcom/venus/venc.c
322
pixmp->ycbcr_enc = inst->ycbcr_enc;
drivers/media/platform/qcom/venus/venc.c
323
pixmp->quantization = inst->quantization;
drivers/media/platform/qcom/venus/venc.c
324
pixmp->xfer_func = inst->xfer_func;
drivers/media/platform/qcom/venus/venc.c
326
pixmp->width = inst->out_width;
drivers/media/platform/qcom/venus/venc.c
327
pixmp->height = inst->out_height;
drivers/media/platform/qcom/venus/venc.c
330
venc_try_fmt_common(inst, f);
drivers/media/platform/qcom/venus/venc.c
338
struct venus_inst *inst = to_inst(file);
drivers/media/platform/qcom/venus/venc.c
346
s->r.width = inst->out_width;
drivers/media/platform/qcom/venus/venc.c
347
s->r.height = inst->out_height;
drivers/media/platform/qcom/venus/venc.c
350
s->r.width = inst->width;
drivers/media/platform/qcom/venus/venc.c
351
s->r.height = inst->height;
drivers/media/platform/qcom/venus/venc.c
366
struct venus_inst *inst = to_inst(file);
drivers/media/platform/qcom/venus/venc.c
371
if (s->r.width > inst->out_width ||
drivers/media/platform/qcom/venus/venc.c
372
s->r.height > inst->out_height)
drivers/media/platform/qcom/venus/venc.c
382
inst->width = s->r.width;
drivers/media/platform/qcom/venus/venc.c
383
inst->height = s->r.height;
drivers/media/platform/qcom/venus/venc.c
394
struct venus_inst *inst = to_inst(file);
drivers/media/platform/qcom/venus/venc.c
406
timeperframe->denominator = inst->timeperframe.denominator;
drivers/media/platform/qcom/venus/venc.c
408
timeperframe->numerator = inst->timeperframe.numerator;
drivers/media/platform/qcom/venus/venc.c
419
inst->timeperframe = *timeperframe;
drivers/media/platform/qcom/venus/venc.c
420
inst->fps = fps;
drivers/media/platform/qcom/venus/venc.c
427
struct venus_inst *inst = to_inst(file);
drivers/media/platform/qcom/venus/venc.c
434
a->parm.output.timeperframe = inst->timeperframe;
drivers/media/platform/qcom/venus/venc.c
442
struct venus_inst *inst = to_inst(file);
drivers/media/platform/qcom/venus/venc.c
447
fmt = find_format(inst, fsize->pixel_format,
drivers/media/platform/qcom/venus/venc.c
450
fmt = find_format(inst, fsize->pixel_format,
drivers/media/platform/qcom/venus/venc.c
459
fsize->stepwise.min_width = frame_width_min(inst);
drivers/media/platform/qcom/venus/venc.c
460
fsize->stepwise.max_width = frame_width_max(inst);
drivers/media/platform/qcom/venus/venc.c
461
fsize->stepwise.step_width = frame_width_step(inst);
drivers/media/platform/qcom/venus/venc.c
462
fsize->stepwise.min_height = frame_height_min(inst);
drivers/media/platform/qcom/venus/venc.c
463
fsize->stepwise.max_height = frame_height_max(inst);
drivers/media/platform/qcom/venus/venc.c
464
fsize->stepwise.step_height = frame_height_step(inst);
drivers/media/platform/qcom/venus/venc.c
472
struct venus_inst *inst = to_inst(file);
drivers/media/platform/qcom/venus/venc.c
478
fmt = find_format(inst, fival->pixel_format,
drivers/media/platform/qcom/venus/venc.c
481
fmt = find_format(inst, fival->pixel_format,
drivers/media/platform/qcom/venus/venc.c
493
if (fival->width > frame_width_max(inst) ||
drivers/media/platform/qcom/venus/venc.c
494
fival->width < frame_width_min(inst) ||
drivers/media/platform/qcom/venus/venc.c
495
fival->height > frame_height_max(inst) ||
drivers/media/platform/qcom/venus/venc.c
496
fival->height < frame_height_min(inst))
drivers/media/platform/qcom/venus/venc.c
499
if (IS_V1(inst->core)) {
drivers/media/platform/qcom/venus/venc.c
505
fival->stepwise.min.denominator = frate_max(inst) / framerate_factor;
drivers/media/platform/qcom/venus/venc.c
507
fival->stepwise.max.denominator = frate_min(inst) / framerate_factor;
drivers/media/platform/qcom/venus/venc.c
509
fival->stepwise.step.denominator = frate_max(inst) / framerate_factor;
drivers/media/platform/qcom/venus/venc.c
530
struct venus_inst *inst = to_inst(file);
drivers/media/platform/qcom/venus/venc.c
538
mutex_lock(&inst->lock);
drivers/media/platform/qcom/venus/venc.c
541
inst->enc_state == VENUS_ENC_STATE_ENCODING) {
drivers/media/platform/qcom/venus/venc.c
546
if (!(inst->streamon_out && inst->streamon_cap))
drivers/media/platform/qcom/venus/venc.c
553
ret = hfi_session_process_buf(inst, &fdata);
drivers/media/platform/qcom/venus/venc.c
555
inst->enc_state = VENUS_ENC_STATE_DRAIN;
drivers/media/platform/qcom/venus/venc.c
557
if (inst->enc_state == VENUS_ENC_STATE_DRAIN) {
drivers/media/platform/qcom/venus/venc.c
561
if (inst->enc_state == VENUS_ENC_STATE_STOPPED) {
drivers/media/platform/qcom/venus/venc.c
562
vb2_clear_last_buffer_dequeued(&inst->fh.m2m_ctx->cap_q_ctx.q);
drivers/media/platform/qcom/venus/venc.c
563
inst->enc_state = VENUS_ENC_STATE_ENCODING;
drivers/media/platform/qcom/venus/venc.c
568
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/venc.c
603
static int venc_pm_get(struct venus_inst *inst)
drivers/media/platform/qcom/venus/venc.c
605
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/venc.c
616
static int venc_pm_put(struct venus_inst *inst, bool autosuspend)
drivers/media/platform/qcom/venus/venc.c
618
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/venc.c
634
static int venc_pm_get_put(struct venus_inst *inst)
drivers/media/platform/qcom/venus/venc.c
636
struct venus_core *core = inst->core;
drivers/media/platform/qcom/venus/venc.c
656
static void venc_pm_touch(struct venus_inst *inst)
drivers/media/platform/qcom/venus/venc.c
658
pm_runtime_mark_last_busy(inst->core->dev_enc);
drivers/media/platform/qcom/venus/venc.c
661
static int venc_set_properties(struct venus_inst *inst)
drivers/media/platform/qcom/venus/venc.c
663
struct venc_controls *ctr = &inst->controls.enc;
drivers/media/platform/qcom/venus/venc.c
67
find_format(struct venus_inst *inst, u32 pixfmt, u32 type)
drivers/media/platform/qcom/venus/venc.c
678
ret = venus_helper_set_work_mode(inst);
drivers/media/platform/qcom/venus/venc.c
684
frate.framerate = inst->fps * (1 << 16);
drivers/media/platform/qcom/venus/venc.c
686
ret = hfi_session_set_property(inst, ptype, &frate);
drivers/media/platform/qcom/venus/venc.c
690
if (inst->fmt_cap->pixfmt == V4L2_PIX_FMT_H264) {
drivers/media/platform/qcom/venus/venc.c
701
ret = hfi_session_set_property(inst, ptype, &info);
drivers/media/platform/qcom/venus/venc.c
711
ret = hfi_session_set_property(inst, ptype, &entropy);
drivers/media/platform/qcom/venus/venc.c
722
ret = hfi_session_set_property(inst, ptype, &deblock);
drivers/media/platform/qcom/venus/venc.c
732
ret = hfi_session_set_property(inst, ptype, &h264_transform);
drivers/media/platform/qcom/venus/venc.c
740
ret = hfi_session_set_property(inst, ptype, &ctr->h264_hier_layers);
drivers/media/platform/qcom/venus/venc.c
745
ret = hfi_session_set_property(inst, ptype, &ctr->layer_bitrate);
drivers/media/platform/qcom/venus/venc.c
754
ret = hfi_session_set_property(inst, ptype, &brate);
drivers/media/platform/qcom/venus/venc.c
761
if (inst->fmt_cap->pixfmt == V4L2_PIX_FMT_H264 ||
drivers/media/platform/qcom/venus/venc.c
762
inst->fmt_cap->pixfmt == V4L2_PIX_FMT_HEVC) {
drivers/media/platform/qcom/venus/venc.c
770
ret = hfi_session_set_property(inst, ptype, &idrp);
drivers/media/platform/qcom/venus/venc.c
775
if (inst->fmt_cap->pixfmt == V4L2_PIX_FMT_HEVC &&
drivers/media/platform/qcom/venus/venc.c
800
ret = hfi_session_set_property(inst, ptype, &hdr10);
drivers/media/platform/qcom/venus/venc.c
809
ret = hfi_session_set_property(inst, ptype, &max_num_b_frames);
drivers/media/platform/qcom/venus/venc.c
818
ret = hfi_session_set_property(inst, ptype, &intra_period);
drivers/media/platform/qcom/venus/venc.c
82
!venus_helper_check_codec(inst, fmt[i].pixfmt))
drivers/media/platform/qcom/venus/venc.c
834
ret = hfi_session_set_property(inst, ptype, &rate_control);
drivers/media/platform/qcom/venus/venc.c
843
ret = hfi_session_set_property(inst, ptype, &quality);
drivers/media/platform/qcom/venus/venc.c
858
ret = hfi_session_set_property(inst, ptype, &brate);
drivers/media/platform/qcom/venus/venc.c
871
ret = hfi_session_set_property(inst, ptype, &brate);
drivers/media/platform/qcom/venus/venc.c
876
if (inst->fmt_cap->pixfmt == V4L2_PIX_FMT_H264 ||
drivers/media/platform/qcom/venus/venc.c
877
inst->fmt_cap->pixfmt == V4L2_PIX_FMT_HEVC) {
drivers/media/platform/qcom/venus/venc.c
884
ret = hfi_session_set_property(inst, ptype, &en);
drivers/media/platform/qcom/venus/venc.c
89
find_format_by_index(struct venus_inst *inst, unsigned int index, u32 type)
drivers/media/platform/qcom/venus/venc.c
890
if (inst->fmt_cap->pixfmt == V4L2_PIX_FMT_HEVC) {
drivers/media/platform/qcom/venus/venc.c
900
ret = hfi_session_set_property(inst, ptype, &quant);
drivers/media/platform/qcom/venus/venc.c
904
if (inst->core->res->hfi_version == HFI_VERSION_4XX ||
drivers/media/platform/qcom/venus/venc.c
905
inst->core->res->hfi_version == HFI_VERSION_6XX) {
drivers/media/platform/qcom/venus/venc.c
908
if (inst->fmt_cap->pixfmt == V4L2_PIX_FMT_HEVC) {
drivers/media/platform/qcom/venus/venc.c
911
} else if (inst->fmt_cap->pixfmt == V4L2_PIX_FMT_VP8) {
drivers/media/platform/qcom/venus/venc.c
919
ret = hfi_session_set_property(inst, ptype, &quant_range_v2);
drivers/media/platform/qcom/venus/venc.c
923
if (inst->fmt_cap->pixfmt == V4L2_PIX_FMT_HEVC) {
drivers/media/platform/qcom/venus/venc.c
926
} else if (inst->fmt_cap->pixfmt == V4L2_PIX_FMT_VP8) {
drivers/media/platform/qcom/venus/venc.c
935
ret = hfi_session_set_property(inst, ptype, &quant_range);
drivers/media/platform/qcom/venus/venc.c
945
ret = hfi_session_set_property(inst, ptype, <r_mode);
drivers/media/platform/qcom/venus/venc.c
949
switch (inst->hfi_codec) {
drivers/media/platform/qcom/venus/venc.c
977
ret = venus_helper_set_profile_level(inst, profile, level);
drivers/media/platform/qcom/venus/venc.c
981
if (inst->fmt_cap->pixfmt == V4L2_PIX_FMT_H264 ||
drivers/media/platform/qcom/venus/venc.c
982
inst->fmt_cap->pixfmt == V4L2_PIX_FMT_HEVC) {
drivers/media/platform/qcom/venus/venc.c
990
ret = hfi_session_set_property(inst, ptype, &en);
drivers/media/platform/qcom/venus/venc.c
993
if ((inst->fmt_cap->pixfmt == V4L2_PIX_FMT_H264 ||
drivers/media/platform/qcom/venus/venc.c
994
inst->fmt_cap->pixfmt == V4L2_PIX_FMT_HEVC) &&
drivers/media/platform/qcom/venus/venc.h
11
int venc_ctrl_init(struct venus_inst *inst);
drivers/media/platform/qcom/venus/venc_ctrls.c
104
ret = dynamic_bitrate_update(inst, ctr->bitrate, 0);
drivers/media/platform/qcom/venus/venc_ctrls.c
221
mutex_lock(&inst->lock);
drivers/media/platform/qcom/venus/venc_ctrls.c
222
if (inst->streamon_out && inst->streamon_cap) {
drivers/media/platform/qcom/venus/venc_ctrls.c
228
ret = hfi_session_set_property(inst, ptype, &en);
drivers/media/platform/qcom/venus/venc_ctrls.c
230
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/venc_ctrls.c
234
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/venc_ctrls.c
262
mutex_lock(&inst->lock);
drivers/media/platform/qcom/venus/venc_ctrls.c
263
if (inst->streamon_out && inst->streamon_cap) {
drivers/media/platform/qcom/venus/venc_ctrls.c
265
ret = hfi_session_set_property(inst, ptype, &en);
drivers/media/platform/qcom/venus/venc_ctrls.c
268
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/venc_ctrls.c
272
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/venc_ctrls.c
293
mutex_lock(&inst->lock);
drivers/media/platform/qcom/venus/venc_ctrls.c
294
if (inst->streamon_out && inst->streamon_cap) {
drivers/media/platform/qcom/venus/venc_ctrls.c
297
ret = hfi_session_set_property(inst, ptype, <r_mark);
drivers/media/platform/qcom/venus/venc_ctrls.c
299
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/venc_ctrls.c
303
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/venc_ctrls.c
306
mutex_lock(&inst->lock);
drivers/media/platform/qcom/venus/venc_ctrls.c
307
if (inst->streamon_out && inst->streamon_cap) {
drivers/media/platform/qcom/venus/venc_ctrls.c
312
ret = hfi_session_set_property(inst, ptype, <r_use);
drivers/media/platform/qcom/venus/venc_ctrls.c
314
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/venc_ctrls.c
318
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/venc_ctrls.c
363
ret = dynamic_bitrate_update(inst, ctr->h264_hier_layer_bitrate[0], 0);
drivers/media/platform/qcom/venus/venc_ctrls.c
369
ret = dynamic_bitrate_update(inst, ctr->h264_hier_layer_bitrate[1], 1);
drivers/media/platform/qcom/venus/venc_ctrls.c
375
ret = dynamic_bitrate_update(inst, ctr->h264_hier_layer_bitrate[2], 2);
drivers/media/platform/qcom/venus/venc_ctrls.c
381
ret = dynamic_bitrate_update(inst, ctr->h264_hier_layer_bitrate[3], 3);
drivers/media/platform/qcom/venus/venc_ctrls.c
387
ret = dynamic_bitrate_update(inst, ctr->h264_hier_layer_bitrate[4], 4);
drivers/media/platform/qcom/venus/venc_ctrls.c
393
ret = dynamic_bitrate_update(inst, ctr->h264_hier_layer_bitrate[5], 5);
drivers/media/platform/qcom/venus/venc_ctrls.c
407
struct venus_inst *inst = ctrl_to_inst(ctrl);
drivers/media/platform/qcom/venus/venc_ctrls.c
409
enum hfi_version ver = inst->core->res->hfi_version;
drivers/media/platform/qcom/venus/venc_ctrls.c
414
ret = venus_helper_get_bufreq(inst, HFI_BUFFER_INPUT, &bufreq);
drivers/media/platform/qcom/venus/venc_ctrls.c
430
int venc_ctrl_init(struct venus_inst *inst)
drivers/media/platform/qcom/venus/venc_ctrls.c
439
ret = v4l2_ctrl_handler_init(&inst->ctrl_handler, 59);
drivers/media/platform/qcom/venus/venc_ctrls.c
443
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
451
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
456
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
463
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
468
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
476
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
481
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
492
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
497
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
502
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
509
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
514
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
519
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
522
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
526
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
530
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
533
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
536
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
539
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
542
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
545
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
548
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
551
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
554
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
557
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
560
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
563
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
566
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
569
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
572
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
575
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
578
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
581
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
584
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
587
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
590
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
593
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
596
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
599
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
603
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
607
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
610
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
613
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
616
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
619
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
622
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
625
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
628
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
631
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
634
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
637
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
644
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
648
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
651
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
655
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
659
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
663
v4l2_ctrl_new_std_compound(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
669
v4l2_ctrl_new_std_compound(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
676
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
681
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
685
if (IS_V4(inst->core) || IS_V6(inst->core)) {
drivers/media/platform/qcom/venus/venc_ctrls.c
686
v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
691
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
694
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
698
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
70
static int dynamic_bitrate_update(struct venus_inst *inst, u32 bitrate,
drivers/media/platform/qcom/venus/venc_ctrls.c
702
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
707
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
712
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
717
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
722
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
drivers/media/platform/qcom/venus/venc_ctrls.c
728
ret = inst->ctrl_handler.error;
drivers/media/platform/qcom/venus/venc_ctrls.c
732
ret = v4l2_ctrl_handler_setup(&inst->ctrl_handler);
drivers/media/platform/qcom/venus/venc_ctrls.c
738
v4l2_ctrl_handler_free(&inst->ctrl_handler);
drivers/media/platform/qcom/venus/venc_ctrls.c
75
mutex_lock(&inst->lock);
drivers/media/platform/qcom/venus/venc_ctrls.c
76
if (inst->streamon_out && inst->streamon_cap) {
drivers/media/platform/qcom/venus/venc_ctrls.c
80
ret = hfi_session_set_property(inst, ptype, &brate);
drivers/media/platform/qcom/venus/venc_ctrls.c
82
mutex_unlock(&inst->lock);
drivers/media/platform/qcom/venus/venc_ctrls.c
89
struct venus_inst *inst = ctrl_to_inst(ctrl);
drivers/media/platform/qcom/venus/venc_ctrls.c
90
struct venc_controls *ctr = &inst->controls.enc;
drivers/media/platform/ti/cal/cal.c
1010
static struct cal_ctx *cal_ctx_create(struct cal_dev *cal, int inst)
drivers/media/platform/ti/cal/cal.c
1020
ctx->dma_ctx = inst;
drivers/media/platform/ti/cal/cal.c
1021
ctx->csi2_ctx = inst;
drivers/media/platform/ti/cal/cal.c
1022
ctx->cport = inst;
drivers/media/test-drivers/vivid/vivid-cec.c
412
dev->inst, is_source ? "out" : "cap", idx);
drivers/media/test-drivers/vivid/vivid-core.c
1422
struct vivid_dev *dev, int inst,
drivers/media/test-drivers/vivid/vivid-core.c
1434
"vivid-%03d-vid-cap", inst);
drivers/media/test-drivers/vivid/vivid-core.c
1471
ret = video_register_device(vfd, VFL_TYPE_VIDEO, vid_cap_nr[inst]);
drivers/media/test-drivers/vivid/vivid-core.c
1484
"vivid-%03d-vid-out", inst);
drivers/media/test-drivers/vivid/vivid-core.c
1523
ret = video_register_device(vfd, VFL_TYPE_VIDEO, vid_out_nr[inst]);
drivers/media/test-drivers/vivid/vivid-core.c
1533
"vivid-%03d-vbi-cap", inst);
drivers/media/test-drivers/vivid/vivid-core.c
1551
ret = video_register_device(vfd, VFL_TYPE_VBI, vbi_cap_nr[inst]);
drivers/media/test-drivers/vivid/vivid-core.c
1564
"vivid-%03d-vbi-out", inst);
drivers/media/test-drivers/vivid/vivid-core.c
1583
ret = video_register_device(vfd, VFL_TYPE_VBI, vbi_out_nr[inst]);
drivers/media/test-drivers/vivid/vivid-core.c
1596
"vivid-%03d-sdr-cap", inst);
drivers/media/test-drivers/vivid/vivid-core.c
1613
ret = video_register_device(vfd, VFL_TYPE_SDR, sdr_cap_nr[inst]);
drivers/media/test-drivers/vivid/vivid-core.c
1623
"vivid-%03d-rad-rx", inst);
drivers/media/test-drivers/vivid/vivid-core.c
1632
ret = video_register_device(vfd, VFL_TYPE_RADIO, radio_rx_nr[inst]);
drivers/media/test-drivers/vivid/vivid-core.c
1642
"vivid-%03d-rad-tx", inst);
drivers/media/test-drivers/vivid/vivid-core.c
1652
ret = video_register_device(vfd, VFL_TYPE_RADIO, radio_tx_nr[inst]);
drivers/media/test-drivers/vivid/vivid-core.c
1662
"vivid-%03d-meta-cap", inst);
drivers/media/test-drivers/vivid/vivid-core.c
1680
meta_cap_nr[inst]);
drivers/media/test-drivers/vivid/vivid-core.c
1691
"vivid-%03d-meta-out", inst);
drivers/media/test-drivers/vivid/vivid-core.c
1710
meta_out_nr[inst]);
drivers/media/test-drivers/vivid/vivid-core.c
1721
"vivid-%03d-touch-cap", inst);
drivers/media/test-drivers/vivid/vivid-core.c
1739
touch_cap_nr[inst]);
drivers/media/test-drivers/vivid/vivid-core.c
1800
static int vivid_create_instance(struct platform_device *pdev, int inst)
drivers/media/test-drivers/vivid/vivid-core.c
1806
int ccs_cap = ccs_cap_mode[inst];
drivers/media/test-drivers/vivid/vivid-core.c
1807
int ccs_out = ccs_out_mode[inst];
drivers/media/test-drivers/vivid/vivid-core.c
1811
unsigned node_type = node_types[inst];
drivers/media/test-drivers/vivid/vivid-core.c
1821
dev->inst = inst;
drivers/media/test-drivers/vivid/vivid-core.c
1829
"platform:%s-%03d", VIVID_MODULE_NAME, inst);
drivers/media/test-drivers/vivid/vivid-core.c
1837
"%s-%03d", VIVID_MODULE_NAME, inst);
drivers/media/test-drivers/vivid/vivid-core.c
1845
ret = vivid_detect_feature_set(dev, inst, node_type,
drivers/media/test-drivers/vivid/vivid-core.c
1977
if (allocators[inst] == 1)
drivers/media/test-drivers/vivid/vivid-core.c
2042
ret = vivid_create_devnodes(pdev, dev, inst,
drivers/media/test-drivers/vivid/vivid-core.c
2049
vivid_devs[inst] = dev;
drivers/media/test-drivers/vivid/vivid-core.c
269
"platform:%s-%03d", VIVID_MODULE_NAME, dev->inst);
drivers/media/test-drivers/vivid/vivid-core.c
921
if (allocators[dev->inst] != 1)
drivers/media/test-drivers/vivid/vivid-core.c
926
q->mem_ops = allocators[dev->inst] == 1 ? &vb2_dma_contig_memops :
drivers/media/test-drivers/vivid/vivid-core.c
932
q->supports_requests = supports_requests[dev->inst];
drivers/media/test-drivers/vivid/vivid-core.c
933
q->requires_requests = supports_requests[dev->inst] >= 2;
drivers/media/test-drivers/vivid/vivid-core.c
934
q->allow_cache_hints = (cache_hints[dev->inst] == 1);
drivers/media/test-drivers/vivid/vivid-core.c
939
static int vivid_detect_feature_set(struct vivid_dev *dev, int inst,
drivers/media/test-drivers/vivid/vivid-core.c
951
dev->multiplanar = multiplanar[inst] > 1;
drivers/media/test-drivers/vivid/vivid-core.c
956
dev->num_inputs = num_inputs[inst];
drivers/media/test-drivers/vivid/vivid-core.c
966
dev->input_type[i] = (input_types[inst] >> (i * 2)) & 0x3;
drivers/media/test-drivers/vivid/vivid-core.c
979
dev->num_outputs = num_outputs[inst];
drivers/media/test-drivers/vivid/vivid-core.c
989
dev->output_type[i] = ((output_types[inst] >> i) & 1) ? HDMI : SVID;
drivers/media/test-drivers/vivid/vivid-core.h
208
u8 inst;
drivers/media/test-drivers/vivid/vivid-ctrls.c
1776
"HDMI %03u-%u Is Connected To", dev->inst, i);
drivers/media/test-drivers/vivid/vivid-ctrls.c
1795
"S-Video %03u-%u Is Connected To", dev->inst, i);
drivers/media/test-drivers/vivid/vivid-ctrls.c
696
hdmi_input_update_outputs_mask |= 1 << dev->inst;
drivers/media/test-drivers/vivid/vivid-vid-cap.c
1088
dev->inst, dev->input_name_counter[inp->index]);
drivers/media/test-drivers/vivid/vivid-vid-cap.c
1093
dev->inst, dev->input_name_counter[inp->index]);
drivers/media/test-drivers/vivid/vivid-vid-cap.c
1102
dev->inst, dev->input_name_counter[inp->index]);
drivers/media/test-drivers/vivid/vivid-vid-cap.c
1110
dev->inst, dev->input_name_counter[inp->index]);
drivers/media/test-drivers/vivid/vivid-vid-out.c
973
dev->inst, dev->output_name_counter[out->index]);
drivers/media/test-drivers/vivid/vivid-vid-out.c
981
dev->inst, dev->output_name_counter[out->index]);
drivers/misc/lkdtm/bugs.c
479
struct lkdtm_cb_fam *inst;
drivers/misc/lkdtm/bugs.c
481
inst = kzalloc_flex(*inst, array, element_count + 1);
drivers/misc/lkdtm/bugs.c
482
if (!inst) {
drivers/misc/lkdtm/bugs.c
487
inst->count = element_count;
drivers/misc/lkdtm/bugs.c
489
inst->array[1] = element_count;
drivers/misc/lkdtm/bugs.c
490
ignored = inst->array[1];
drivers/misc/lkdtm/bugs.c
493
inst->array[element_count] = element_count;
drivers/misc/lkdtm/bugs.c
494
ignored = inst->array[element_count];
drivers/misc/lkdtm/bugs.c
496
kfree(inst);
drivers/misc/lkdtm/bugs.c
535
struct lkdtm_cb_ptr *inst;
drivers/misc/lkdtm/bugs.c
537
inst = kzalloc_obj(*inst);
drivers/misc/lkdtm/bugs.c
538
if (!inst) {
drivers/misc/lkdtm/bugs.c
543
inst->buf = kzalloc(element_count, GFP_KERNEL);
drivers/misc/lkdtm/bugs.c
544
if (!inst->buf) {
drivers/misc/lkdtm/bugs.c
548
inst->len = element_count;
drivers/misc/lkdtm/bugs.c
551
inst->extra = kzalloc_objs(*inst->extra, element_count * 2);
drivers/misc/lkdtm/bugs.c
552
inst->nr_extra = element_count * 2;
drivers/misc/lkdtm/bugs.c
555
check_ptr_len(inst, 4);
drivers/misc/lkdtm/bugs.c
557
inst->buf[0] = 'A';
drivers/misc/lkdtm/bugs.c
558
inst->buf[1] = 'B';
drivers/misc/lkdtm/bugs.c
559
inst->buf[2] = 'C';
drivers/misc/lkdtm/bugs.c
560
inst->buf[3] = 'D';
drivers/misc/lkdtm/bugs.c
562
inst->extra[element_count].biggest = 0x1000;
drivers/misc/lkdtm/bugs.c
565
ignored = inst->extra[inst->nr_extra].b;
drivers/misc/lkdtm/bugs.c
567
kfree(inst->extra);
drivers/misc/lkdtm/bugs.c
568
kfree(inst->buf);
drivers/misc/lkdtm/bugs.c
569
kfree(inst);
drivers/net/ethernet/broadcom/bnx2.c
3905
bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
drivers/net/ethernet/broadcom/bnx2.h
7026
u32 inst;
drivers/net/ethernet/broadcom/bnx2_fw.h
21
.inst = BNX2_COM_CPU_INSTRUCTION,
drivers/net/ethernet/broadcom/bnx2_fw.h
37
.inst = BNX2_CP_CPU_INSTRUCTION,
drivers/net/ethernet/broadcom/bnx2_fw.h
53
.inst = BNX2_RXP_CPU_INSTRUCTION,
drivers/net/ethernet/broadcom/bnx2_fw.h
69
.inst = BNX2_TPAT_CPU_INSTRUCTION,
drivers/net/ethernet/broadcom/bnx2_fw.h
85
.inst = BNX2_TXP_CPU_INSTRUCTION,
drivers/net/ethernet/huawei/hinic/hinic_debugfs.c
96
read_data->inst = TBL_ID_FUNC_CFG_SM_INST;
drivers/net/ethernet/huawei/hinic/hinic_debugfs.h
22
unsigned char inst;
drivers/net/ethernet/marvell/octeontx2/af/common.h
91
struct qmem *inst;
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
2170
u64 inst[8];
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
1231
qmem_free(rvu->dev, aq->inst);
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
1248
err = qmem_alloc(rvu->dev, &aq->inst, qsize, inst_size);
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
1152
u64 *inst;
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
1181
inst = req->inst;
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
1183
inst[0] = 0;
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
1184
inst[1] = res_daddr;
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
1186
inst[2] = 0;
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
1188
inst[3] = 1;
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
1189
inst[4] = 0;
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
1190
inst[5] = 0;
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
1191
inst[6] = 0;
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
1193
inst[7] = CPT_SE_IE_EGRP << 61;
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
1051
struct nix_aq_inst_s inst;
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
1138
memset(&inst, 0, sizeof(struct nix_aq_inst_s));
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
1139
inst.lf = nixlf;
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
1140
inst.cindex = req->qidx;
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
1141
inst.ctype = req->ctype;
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
1142
inst.op = req->op;
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
1146
inst.res_addr = (u64)aq->res->iova;
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
1207
rc = nix_aq_enqueue_wait(rvu, block, &inst);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
4924
NIX_AF_AQ_BASE, (u64)block->aq->inst->iova);
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
973
struct nix_aq_inst_s *inst)
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
987
memcpy((void *)(aq->inst->base + (head * aq->inst->entry_sz)),
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
988
(void *)inst, aq->inst->entry_sz);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
101
inst.res_addr = (u64)aq->res->iova;
drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
158
rc = npa_aq_enqueue_wait(rvu, block, &inst);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
16
struct npa_aq_inst_s *inst)
drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
29
memcpy((void *)(aq->inst->base + (head * aq->inst->entry_sz)),
drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
30
(void *)inst, aq->inst->entry_sz);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
520
NPA_AF_AQ_BASE, (u64)block->aq->inst->iova);
drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
67
struct npa_aq_inst_s inst;
drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
93
memset(&inst, 0, sizeof(struct npa_aq_inst_s));
drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
94
inst.cindex = req->aura_id;
drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
95
inst.lf = npalf;
drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
96
inst.ctype = req->ctype;
drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
97
inst.op = req->op;
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
1002
inst.dlen = dlen + ETH_HLEN - (x->aead->alg_icv_len / 8);
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
1003
inst.opcode_major = CN10K_IPSEC_MAJOR_OP_OUTB_IPSEC;
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
1004
inst.param1 = cn10k_ipsec_get_param1(iv_offset);
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
1006
inst.param2 = encap_offset <<
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
1008
inst.param2 |= (u16)auth_offset <<
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
1017
inst.dptr = dptr_iova | ((u64)gthr_size << 60);
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
1020
inst.rptr = inst.dptr;
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
1023
inst.cptr = sa_info->iova;
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
1024
inst.ctx_val = 1;
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
1025
inst.egrp = CN10K_DEF_CPT_IPSEC_EGRP;
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
1028
inst.nixtxl = (size / 16) - 1;
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
1029
inst.dat_offset = ETH_HLEN;
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
1030
inst.nixtx_offset = sq->sqe_size;
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
1037
cn10k_cpt_inst_flush(pf, &inst, sizeof(struct cpt_inst_s));
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
381
static void cn10k_cpt_inst_flush(struct otx2_nic *pf, struct cpt_inst_s *inst,
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
399
memcpy((u64 *)lmt_info->lmt_addr, inst, size);
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
431
struct cpt_inst_s inst = {};
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
461
inst.res_addr = res_iova;
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
462
inst.dptr = (u64)dptr_iova;
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
463
inst.param2 = sa_size >> 3;
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
464
inst.dlen = sa_size;
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
465
inst.opcode_major = CN10K_IPSEC_MAJOR_OP_WRITE_SA;
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
466
inst.opcode_minor = CN10K_IPSEC_MINOR_OP_WRITE_SA;
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
467
inst.cptr = sa_iova;
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
468
inst.ctx_val = 1;
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
469
inst.egrp = CN10K_DEF_CPT_IPSEC_EGRP;
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
477
cn10k_cpt_inst_flush(pf, &inst, sizeof(struct cpt_inst_s));
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
935
struct cpt_inst_s inst;
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
974
memset(&inst, 0, sizeof(struct cpt_inst_s));
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
990
inst.res_addr = sq->cpt_resp->iova + (64 * sq->head);
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
993
inst.rvu_pf_func = pf->pcifunc;
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.c
998
inst.qord = 1;
drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c
191
u32 inst;
drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c
198
inst = (portno - portno % 4) / 4;
drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c
199
spx5_rmw(BIT(inst), BIT(inst), sparx5, PORT_CONF_QSGMII_ENA);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
1024
void __iomem *inst;
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
1033
inst = spx5_inst_get(sparx5, dev, tinst);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
1034
sparx5_get_dev_misc_stats(portstats, inst, tinst);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
1036
inst = spx5_inst_get(sparx5, TARGET_ASM, 0);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
1037
sparx5_get_asm_misc_stats(portstats, inst, portno);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
239
static void sparx5_get_dev_phy_stats(u64 *portstats, void __iomem *inst, u32
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
243
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
246
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
250
static void sparx5_get_dev_mac_stats(u64 *portstats, void __iomem *inst, u32
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
254
spx5_inst_rd(inst, DEV5G_TX_UC_CNT(tinst)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
256
spx5_inst_rd(inst, DEV5G_PMAC_TX_UC_CNT(tinst)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
258
spx5_inst_rd(inst, DEV5G_TX_MC_CNT(tinst)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
260
spx5_inst_rd(inst, DEV5G_TX_BC_CNT(tinst)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
262
spx5_inst_rd(inst, DEV5G_RX_UC_CNT(tinst)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
264
spx5_inst_rd(inst, DEV5G_PMAC_RX_UC_CNT(tinst)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
266
spx5_inst_rd(inst, DEV5G_RX_MC_CNT(tinst)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
268
spx5_inst_rd(inst, DEV5G_RX_BC_CNT(tinst)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
270
spx5_inst_rd(inst, DEV5G_RX_CRC_ERR_CNT(tinst)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
272
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
275
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
278
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
281
spx5_inst_rd(inst, DEV5G_TX_OK_BYTES_CNT(tinst)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
283
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
286
spx5_inst_rd(inst, DEV5G_RX_OK_BYTES_CNT(tinst)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
288
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
291
spx5_inst_rd(inst, DEV5G_PMAC_TX_MC_CNT(tinst)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
293
spx5_inst_rd(inst, DEV5G_PMAC_TX_BC_CNT(tinst)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
295
spx5_inst_rd(inst, DEV5G_PMAC_RX_MC_CNT(tinst)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
297
spx5_inst_rd(inst, DEV5G_PMAC_RX_BC_CNT(tinst)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
299
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
302
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
305
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
308
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
311
spx5_inst_rd(inst, DEV5G_RX_OVERSIZE_CNT(tinst)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
313
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
317
static void sparx5_get_dev_mac_ctrl_stats(u64 *portstats, void __iomem *inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
321
spx5_inst_rd(inst, DEV5G_TX_PAUSE_CNT(tinst)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
323
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
326
spx5_inst_rd(inst, DEV5G_RX_PAUSE_CNT(tinst)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
328
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
331
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
334
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
338
static void sparx5_get_dev_rmon_stats(u64 *portstats, void __iomem *inst, u32
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
342
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
345
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
348
spx5_inst_rd(inst, DEV5G_RX_OVERSIZE_CNT(tinst)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
350
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
353
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
356
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
359
spx5_inst_rd(inst, DEV5G_RX_JABBERS_CNT(tinst)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
361
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
364
spx5_inst_rd(inst, DEV5G_RX_SIZE64_CNT(tinst)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
366
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
369
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
372
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
375
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
378
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
381
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
384
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
387
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
390
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
393
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
396
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
399
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
402
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
405
spx5_inst_rd(inst, DEV5G_TX_SIZE64_CNT(tinst)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
407
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
410
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
413
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
416
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
419
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
422
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
425
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
428
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
431
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
434
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
437
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
440
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
443
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
447
static void sparx5_get_dev_misc_stats(u64 *portstats, void __iomem *inst, u32
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
451
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
454
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
457
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
460
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
463
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
466
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
469
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
472
spx5_inst_rd(inst, DEV5G_RX_IN_BYTES_CNT(tinst)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
474
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
477
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
480
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
483
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
486
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
489
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
492
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
495
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
498
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
501
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
510
void __iomem *inst;
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
512
inst = spx5_inst_get(sparx5, dev, tinst);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
513
sparx5_get_dev_phy_stats(portstats, inst, tinst);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
514
sparx5_get_dev_mac_stats(portstats, inst, tinst);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
515
sparx5_get_dev_mac_ctrl_stats(portstats, inst, tinst);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
516
sparx5_get_dev_rmon_stats(portstats, inst, tinst);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
517
sparx5_get_dev_misc_stats(portstats, inst, tinst);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
520
static void sparx5_get_asm_phy_stats(u64 *portstats, void __iomem *inst, int
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
524
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
527
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
531
static void sparx5_get_asm_mac_stats(u64 *portstats, void __iomem *inst, int
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
535
spx5_inst_rd(inst, ASM_TX_UC_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
537
spx5_inst_rd(inst, ASM_PMAC_TX_UC_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
539
spx5_inst_rd(inst, ASM_TX_MC_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
541
spx5_inst_rd(inst, ASM_TX_BC_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
543
spx5_inst_rd(inst, ASM_TX_BACKOFF1_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
545
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
548
spx5_inst_rd(inst, ASM_RX_UC_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
550
spx5_inst_rd(inst, ASM_PMAC_RX_UC_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
552
spx5_inst_rd(inst, ASM_RX_MC_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
554
spx5_inst_rd(inst, ASM_RX_BC_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
556
spx5_inst_rd(inst, ASM_RX_CRC_ERR_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
558
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
561
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
564
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
567
spx5_inst_rd(inst, ASM_TX_OK_BYTES_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
569
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
572
spx5_inst_rd(inst, ASM_TX_DEFER_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
574
spx5_inst_rd(inst, ASM_TX_LATE_COLL_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
576
spx5_inst_rd(inst, ASM_TX_XCOLL_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
578
spx5_inst_rd(inst, ASM_TX_CSENSE_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
580
spx5_inst_rd(inst, ASM_RX_OK_BYTES_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
582
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
585
spx5_inst_rd(inst, ASM_PMAC_TX_MC_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
587
spx5_inst_rd(inst, ASM_PMAC_TX_BC_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
589
spx5_inst_rd(inst, ASM_TX_XDEFER_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
591
spx5_inst_rd(inst, ASM_PMAC_RX_MC_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
593
spx5_inst_rd(inst, ASM_PMAC_RX_BC_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
595
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
598
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
601
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
604
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
607
spx5_inst_rd(inst, ASM_RX_OVERSIZE_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
609
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
613
static void sparx5_get_asm_mac_ctrl_stats(u64 *portstats, void __iomem *inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
617
spx5_inst_rd(inst, ASM_TX_PAUSE_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
619
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
622
spx5_inst_rd(inst, ASM_RX_PAUSE_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
624
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
627
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
630
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
634
static void sparx5_get_asm_rmon_stats(u64 *portstats, void __iomem *inst, int
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
638
spx5_inst_rd(inst, ASM_RX_UNDERSIZE_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
640
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
643
spx5_inst_rd(inst, ASM_RX_OVERSIZE_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
645
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
648
spx5_inst_rd(inst, ASM_RX_FRAGMENTS_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
650
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
653
spx5_inst_rd(inst, ASM_RX_JABBERS_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
655
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
658
spx5_inst_rd(inst, ASM_RX_SIZE64_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
660
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
663
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
666
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
669
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
672
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
675
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
678
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
681
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
684
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
687
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
690
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
693
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
696
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
699
spx5_inst_rd(inst, ASM_TX_SIZE64_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
701
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
704
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
707
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
710
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
713
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
716
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
719
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
722
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
725
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
728
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
731
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
734
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
737
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
741
static void sparx5_get_asm_misc_stats(u64 *portstats, void __iomem *inst, int
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
745
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
748
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
751
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
754
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
757
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
760
spx5_inst_rd(inst, ASM_RX_BAD_BYTES_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
762
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
765
spx5_inst_rd(inst, ASM_RX_IN_BYTES_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
767
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
770
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
773
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
776
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
779
spx5_inst_rd(inst, ASM_TX_OUT_BYTES_CNT(portno)));
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
781
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
784
spx5_inst_rd(inst,
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
791
void __iomem *inst = spx5_inst_get(sparx5, TARGET_ASM, 0);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
793
sparx5_get_asm_phy_stats(portstats, inst, portno);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
794
sparx5_get_asm_mac_stats(portstats, inst, portno);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
795
sparx5_get_asm_mac_ctrl_stats(portstats, inst, portno);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
796
sparx5_get_asm_rmon_stats(portstats, inst, portno);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
797
sparx5_get_asm_misc_stats(portstats, inst, portno);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
817
void __iomem *inst;
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
825
inst = spx5_inst_get(sparx5, dev, tinst);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
826
sparx5_get_dev_phy_stats(portstats, inst, tinst);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
828
inst = spx5_inst_get(sparx5, TARGET_ASM, 0);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
829
sparx5_get_asm_phy_stats(portstats, inst, portno);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
842
void __iomem *inst;
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
850
inst = spx5_inst_get(sparx5, dev, tinst);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
851
sparx5_get_dev_mac_stats(portstats, inst, tinst);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
853
inst = spx5_inst_get(sparx5, TARGET_ASM, 0);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
854
sparx5_get_asm_mac_stats(portstats, inst, portno);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
910
void __iomem *inst;
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
918
inst = spx5_inst_get(sparx5, dev, tinst);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
919
sparx5_get_dev_mac_ctrl_stats(portstats, inst, tinst);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
921
inst = spx5_inst_get(sparx5, TARGET_ASM, 0);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
922
sparx5_get_asm_mac_ctrl_stats(portstats, inst, portno);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
942
void __iomem *inst;
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
950
inst = spx5_inst_get(sparx5, dev, tinst);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
951
sparx5_get_dev_rmon_stats(portstats, inst, tinst);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
953
inst = spx5_inst_get(sparx5, TARGET_ASM, 0);
drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c
954
sparx5_get_asm_rmon_stats(portstats, inst, portno);
drivers/net/ethernet/microchip/sparx5/sparx5_port.c
1193
void __iomem *inst;
drivers/net/ethernet/microchip/sparx5/sparx5_port.c
1199
inst = spx5_inst_get(sparx5, dev, tinst);
drivers/net/ethernet/microchip/sparx5/sparx5_port.c
1201
spx5_inst_wr(5, inst,
drivers/net/ethernet/microchip/sparx5/sparx5_port.c
1206
inst = spx5_inst_get(sparx5, dev, tinst);
drivers/net/ethernet/microchip/sparx5/sparx5_port.c
1208
spx5_inst_wr(5, inst,
drivers/net/ethernet/microchip/sparx5/sparx5_port.c
128
void __iomem *inst;
drivers/net/ethernet/microchip/sparx5/sparx5_port.c
137
inst = spx5_inst_get(sparx5, dev, tinst);
drivers/net/ethernet/microchip/sparx5/sparx5_port.c
139
value = spx5_inst_rd(inst, DEV10G_MAC_TX_MONITOR_STICKY(0));
drivers/net/ethernet/microchip/sparx5/sparx5_port.c
143
spx5_inst_wr(0xffffffff, inst, DEV10G_MAC_TX_MONITOR_STICKY(0));
drivers/net/ethernet/microchip/sparx5/sparx5_port.c
144
value = spx5_inst_rd(inst, DEV10G_MAC_TX_MONITOR_STICKY(0));
drivers/net/ethernet/microchip/sparx5/sparx5_port.c
535
u32 inst;
drivers/net/ethernet/microchip/sparx5/sparx5_port.c
542
inst = (portno - portno % 4) / 4;
drivers/net/ethernet/microchip/sparx5/sparx5_port.c
543
spx5_rmw(BIT(inst),
drivers/net/ethernet/microchip/sparx5/sparx5_port.c
544
BIT(inst),
drivers/net/ethernet/microchip/sparx5/sparx5_port.c
577
void __iomem *inst = spx5_inst_get(sparx5, dev, tinst);
drivers/net/ethernet/microchip/sparx5/sparx5_port.c
600
inst,
drivers/net/ethernet/microchip/sparx5/sparx5_port.c
605
inst,
drivers/net/ethernet/microchip/sparx5/sparx5_port.c
610
inst,
drivers/net/ethernet/sun/cassini.c
1146
cas_hp_inst_t *inst;
drivers/net/ethernet/sun/cassini.c
1151
while ((inst = firmware) && inst->note) {
drivers/net/ethernet/sun/cassini.c
1154
val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val);
drivers/net/ethernet/sun/cassini.c
1155
val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask);
drivers/net/ethernet/sun/cassini.c
1158
val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10);
drivers/net/ethernet/sun/cassini.c
1159
val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop);
drivers/net/ethernet/sun/cassini.c
1160
val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext);
drivers/net/ethernet/sun/cassini.c
1161
val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff);
drivers/net/ethernet/sun/cassini.c
1162
val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext);
drivers/net/ethernet/sun/cassini.c
1163
val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff);
drivers/net/ethernet/sun/cassini.c
1164
val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op);
drivers/net/ethernet/sun/cassini.c
1167
val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask);
drivers/net/ethernet/sun/cassini.c
1168
val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift);
drivers/net/ethernet/sun/cassini.c
1169
val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab);
drivers/net/ethernet/sun/cassini.c
1170
val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg);
drivers/net/wireless/intel/iwlegacy/4965-mac.c
4694
const void *inst, *data, *init, *init_data, *boot;
drivers/net/wireless/intel/iwlegacy/4965-mac.c
4738
pieces->inst = src;
drivers/net/wireless/intel/iwlegacy/4965-mac.c
4917
memcpy(il->ucode_code.v_addr, pieces.inst, pieces.inst_size);
drivers/net/wireless/realtek/rtw89/core.c
6725
struct rtw89_vif_link *inst = &rtwvif->links_inst[index];
drivers/net/wireless/realtek/rtw89/core.c
6727
inst->rtwvif = rtwvif;
drivers/net/wireless/realtek/rtw89/core.c
6728
inst->mac_id = mac_id + index * support_mld_num;
drivers/net/wireless/realtek/rtw89/core.c
6729
inst->mac_idx = RTW89_MAC_0 + index;
drivers/net/wireless/realtek/rtw89/core.c
6730
inst->phy_idx = RTW89_PHY_0 + index;
drivers/net/wireless/realtek/rtw89/core.c
6733
inst->port = port;
drivers/net/wireless/realtek/rtw89/core.c
6761
struct rtw89_sta_link *inst = &rtwsta->links_inst[index];
drivers/net/wireless/realtek/rtw89/core.c
6763
inst->rtwvif_link = &rtwvif->links_inst[index];
drivers/net/wireless/realtek/rtw89/core.c
6765
inst->rtwsta = rtwsta;
drivers/net/wireless/realtek/rtw89/core.c
6766
inst->mac_id = mac_id + index * support_mld_num;
drivers/perf/nvidia_t410_cmem_latency_pmu.c
199
unsigned int inst)
drivers/perf/nvidia_t410_cmem_latency_pmu.c
201
return readq(cmem_lat_pmu->base[inst] + CMEM_LAT_STATUS);
drivers/phy/cadence/phy-cadence-sierra.c
941
static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst,
drivers/phy/cadence/phy-cadence-sierra.c
946
if (of_property_read_u32(child, "reg", &inst->mlane))
drivers/phy/cadence/phy-cadence-sierra.c
949
if (of_property_read_u32(child, "cdns,num-lanes", &inst->num_lanes))
drivers/phy/cadence/phy-cadence-sierra.c
957
inst->phy_type = TYPE_PCIE;
drivers/phy/cadence/phy-cadence-sierra.c
960
inst->phy_type = TYPE_USB;
drivers/phy/cadence/phy-cadence-sierra.c
963
inst->phy_type = TYPE_SGMII;
drivers/phy/cadence/phy-cadence-sierra.c
966
inst->phy_type = TYPE_QSGMII;
drivers/phy/cadence/phy-cadence-sierra.c
972
inst->ssc_mode = EXTERNAL_SSC;
drivers/phy/cadence/phy-cadence-sierra.c
973
of_property_read_u32(child, "cdns,ssc-mode", &inst->ssc_mode);
drivers/phy/cadence/phy-cadence-torrent.c
1091
struct cdns_torrent_inst *inst,
drivers/phy/cadence/phy-cadence-torrent.c
1115
pll_bits = ((1 << inst->num_lanes) - 1);
drivers/phy/cadence/phy-cadence-torrent.c
1133
struct cdns_torrent_inst *inst,
drivers/phy/cadence/phy-cadence-torrent.c
1181
struct cdns_torrent_inst *inst, u32 num_lanes)
drivers/phy/cadence/phy-cadence-torrent.c
1202
ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, num_lanes,
drivers/phy/cadence/phy-cadence-torrent.c
1207
ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, num_lanes,
drivers/phy/cadence/phy-cadence-torrent.c
1231
struct cdns_torrent_inst *inst,
drivers/phy/cadence/phy-cadence-torrent.c
1274
cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + i],
drivers/phy/cadence/phy-cadence-torrent.c
1283
struct cdns_torrent_inst *inst,
drivers/phy/cadence/phy-cadence-torrent.c
1334
cdns_torrent_dp_pma_cmn_rate(cdns_phy, inst, dp->link_rate, dp->lanes);
drivers/phy/cadence/phy-cadence-torrent.c
1369
static int cdns_torrent_dp_verify_config(struct cdns_torrent_inst *inst,
drivers/phy/cadence/phy-cadence-torrent.c
1404
if (dp->lanes > inst->num_lanes)
drivers/phy/cadence/phy-cadence-torrent.c
1430
struct cdns_torrent_inst *inst,
drivers/phy/cadence/phy-cadence-torrent.c
1442
<< PHY_POWER_STATE_LN(inst->mlane + i));
drivers/phy/cadence/phy-cadence-torrent.c
1444
pll_clk_en &= ~(0x01U << (inst->mlane + i));
drivers/phy/cadence/phy-cadence-torrent.c
1453
struct cdns_torrent_inst *inst,
drivers/phy/cadence/phy-cadence-torrent.c
1461
u32 clane = inst->mlane;
drivers/phy/cadence/phy-cadence-torrent.c
1467
pma_tx_elec_idle_mask = ((1 << inst->num_lanes) - 1) << clane;
drivers/phy/cadence/phy-cadence-torrent.c
1487
for (i = 0; i < inst->num_lanes; i++)
drivers/phy/cadence/phy-cadence-torrent.c
1490
for (i = 1; i < inst->num_lanes; i++)
drivers/phy/cadence/phy-cadence-torrent.c
1495
cdns_torrent_dp_set_a0_pll(cdns_phy, inst, dp->lanes);
drivers/phy/cadence/phy-cadence-torrent.c
1498
for (i = 0; i < inst->num_lanes; i++)
drivers/phy/cadence/phy-cadence-torrent.c
1501
for (i = 0; i < inst->num_lanes; i++)
drivers/phy/cadence/phy-cadence-torrent.c
1518
ret = cdns_torrent_dp_run(cdns_phy, inst, dp->lanes);
drivers/phy/cadence/phy-cadence-torrent.c
1525
struct cdns_torrent_inst *inst,
drivers/phy/cadence/phy-cadence-torrent.c
1530
ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes,
drivers/phy/cadence/phy-cadence-torrent.c
1534
ret = cdns_torrent_dp_set_pll_en(cdns_phy, inst, dp, false);
drivers/phy/cadence/phy-cadence-torrent.c
1539
ret = cdns_torrent_dp_configure_rate(cdns_phy, inst, dp);
drivers/phy/cadence/phy-cadence-torrent.c
1544
ret = cdns_torrent_dp_set_pll_en(cdns_phy, inst, dp, true);
drivers/phy/cadence/phy-cadence-torrent.c
1547
ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes,
drivers/phy/cadence/phy-cadence-torrent.c
1551
ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes,
drivers/phy/cadence/phy-cadence-torrent.c
1562
struct cdns_torrent_inst *inst,
drivers/phy/cadence/phy-cadence-torrent.c
1569
val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
drivers/phy/cadence/phy-cadence-torrent.c
1576
cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
drivers/phy/cadence/phy-cadence-torrent.c
1579
cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
drivers/phy/cadence/phy-cadence-torrent.c
1582
cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
drivers/phy/cadence/phy-cadence-torrent.c
1585
cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
drivers/phy/cadence/phy-cadence-torrent.c
1589
cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
drivers/phy/cadence/phy-cadence-torrent.c
1593
val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
drivers/phy/cadence/phy-cadence-torrent.c
1600
cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
drivers/phy/cadence/phy-cadence-torrent.c
1608
struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
drivers/phy/cadence/phy-cadence-torrent.c
1615
ret = cdns_torrent_dp_verify_config(inst, &opts->dp);
drivers/phy/cadence/phy-cadence-torrent.c
1622
ret = cdns_torrent_dp_set_lanes(cdns_phy, inst, &opts->dp);
drivers/phy/cadence/phy-cadence-torrent.c
1630
ret = cdns_torrent_dp_set_rate(cdns_phy, inst, &opts->dp);
drivers/phy/cadence/phy-cadence-torrent.c
1638
cdns_torrent_dp_set_voltages(cdns_phy, inst, &opts->dp);
drivers/phy/cadence/phy-cadence-torrent.c
1645
struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
drivers/phy/cadence/phy-cadence-torrent.c
1658
reset_control_deassert(inst->lnk_rst);
drivers/phy/cadence/phy-cadence-torrent.c
1678
if (inst->phy_type == TYPE_PCIE || inst->phy_type == TYPE_USB) {
drivers/phy/cadence/phy-cadence-torrent.c
1679
ret = regmap_field_read_poll_timeout(cdns_phy->phy_pcs_iso_link_ctrl_1[inst->mlane],
drivers/phy/cadence/phy-cadence-torrent.c
1693
struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
drivers/phy/cadence/phy-cadence-torrent.c
1704
return reset_control_assert(inst->lnk_rst);
drivers/phy/cadence/phy-cadence-torrent.c
1708
struct cdns_torrent_inst *inst)
drivers/phy/cadence/phy-cadence-torrent.c
1720
cdns_torrent_dp_set_a0_pll(cdns_phy, inst, inst->num_lanes);
drivers/phy/cadence/phy-cadence-torrent.c
1726
lane_bits = (1 << inst->num_lanes) - 1;
drivers/phy/cadence/phy-cadence-torrent.c
1755
cdns_torrent_dp_pma_cmn_rate(cdns_phy, inst, cdns_phy->max_bit_rate,
drivers/phy/cadence/phy-cadence-torrent.c
1756
inst->num_lanes);
drivers/phy/cadence/phy-cadence-torrent.c
1763
struct cdns_torrent_inst *inst,
drivers/phy/cadence/phy-cadence-torrent.c
1776
ret = cdns_torrent_dp_run(cdns_phy, inst, inst->num_lanes);
drivers/phy/cadence/phy-cadence-torrent.c
1783
struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
drivers/phy/cadence/phy-cadence-torrent.c
1802
cdns_torrent_dp_common_init(cdns_phy, inst);
drivers/phy/cadence/phy-cadence-torrent.c
1804
return cdns_torrent_dp_start(cdns_phy, inst, phy);
drivers/phy/cadence/phy-cadence-torrent.c
1808
struct cdns_torrent_inst *inst,
drivers/phy/cadence/phy-cadence-torrent.c
1816
cdns_torrent_dp_common_init(cdns_phy, inst);
drivers/phy/cadence/phy-cadence-torrent.c
1818
return cdns_torrent_dp_start(cdns_phy, inst, phy);
drivers/phy/cadence/phy-cadence-torrent.c
2324
struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
drivers/phy/cadence/phy-cadence-torrent.c
2325
enum cdns_torrent_phy_type phy_type = inst->phy_type;
drivers/phy/cadence/phy-cadence-torrent.c
2327
enum cdns_torrent_ssc_mode ssc = inst->ssc_mode;
drivers/phy/cadence/phy-cadence-torrent.c
2339
return cdns_torrent_dp_multilink_init(cdns_phy, inst, phy);
drivers/phy/cadence/phy-cadence-torrent.c
2378
for (i = 0; i < inst->num_lanes; i++) {
drivers/phy/cadence/phy-cadence-torrent.c
2379
regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
drivers/phy/cadence/phy-cadence-torrent.c
2436
for (i = 0; i < inst->num_lanes; i++) {
drivers/phy/cadence/phy-cadence-torrent.c
2437
regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
drivers/phy/cadence/phy-cadence-torrent.c
2452
for (i = 0; i < inst->num_lanes; i++) {
drivers/phy/cadence/phy-cadence-torrent.c
2453
regmap = cdns_phy->regmap_rx_lane_cdb[i + inst->mlane];
drivers/phy/canaan/phy-k230-usb.c
161
struct k230_usb_phy_instance *inst = phy_get_drvdata(phy);
drivers/phy/canaan/phy-k230-usb.c
162
struct k230_usb_phy_global *global = inst->global;
drivers/phy/canaan/phy-k230-usb.c
167
writel(K230_PHY_CTL0_VAL, base + inst->ctl_offset + CTL0_OFFSET);
drivers/phy/canaan/phy-k230-usb.c
168
writel(K230_PHY_CTL1_VAL, base + inst->ctl_offset + CTL1_OFFSET);
drivers/phy/canaan/phy-k230-usb.c
171
val = readl(base + inst->test_offset + TEST_CTL3_OFFSET);
drivers/phy/canaan/phy-k230-usb.c
174
if (inst->index == 1)
drivers/phy/canaan/phy-k230-usb.c
179
writel(val, base + inst->test_offset + TEST_CTL3_OFFSET);
drivers/phy/canaan/phy-k230-usb.c
186
struct k230_usb_phy_instance *inst = phy_get_drvdata(phy);
drivers/phy/canaan/phy-k230-usb.c
187
struct k230_usb_phy_global *global = inst->global;
drivers/phy/canaan/phy-k230-usb.c
191
val = readl(base + inst->test_offset + TEST_CTL3_OFFSET);
drivers/phy/canaan/phy-k230-usb.c
193
writel(val, base + inst->test_offset + TEST_CTL3_OFFSET);
drivers/phy/canaan/phy-k230-usb.c
242
struct k230_usb_phy_instance *inst = &global->phys[i];
drivers/phy/canaan/phy-k230-usb.c
245
inst->global = global;
drivers/phy/canaan/phy-k230-usb.c
246
inst->index = i;
drivers/phy/canaan/phy-k230-usb.c
247
inst->test_offset = phy_reg_info[i].test_offset;
drivers/phy/canaan/phy-k230-usb.c
248
inst->ctl_offset = phy_reg_info[i].ctl_offset;
drivers/phy/canaan/phy-k230-usb.c
256
phy_set_drvdata(phy, inst);
drivers/phy/canaan/phy-k230-usb.c
257
inst->phy = phy;
drivers/phy/mediatek/phy-mtk-tphy.c
385
struct mtk_phy_instance *inst = sf->private;
drivers/phy/mediatek/phy-mtk-tphy.c
386
struct u2phy_banks *u2_banks = &inst->u2_banks;
drivers/phy/mediatek/phy-mtk-tphy.c
452
struct mtk_phy_instance *inst = sf->private;
drivers/phy/mediatek/phy-mtk-tphy.c
453
struct u2phy_banks *u2_banks = &inst->u2_banks;
drivers/phy/mediatek/phy-mtk-tphy.c
505
static void u2_phy_dbgfs_files_create(struct mtk_phy_instance *inst)
drivers/phy/mediatek/phy-mtk-tphy.c
511
debugfs_create_file_aux_num(u2_phy_files[i], 0644, inst->phy->debugfs,
drivers/phy/mediatek/phy-mtk-tphy.c
512
inst, i, &u2_phy_fops);
drivers/phy/mediatek/phy-mtk-tphy.c
517
struct mtk_phy_instance *inst = sf->private;
drivers/phy/mediatek/phy-mtk-tphy.c
518
struct u3phy_banks *u3_banks = &inst->u3_banks;
drivers/phy/mediatek/phy-mtk-tphy.c
568
struct mtk_phy_instance *inst = sf->private;
drivers/phy/mediatek/phy-mtk-tphy.c
569
struct u3phy_banks *u3_banks = &inst->u3_banks;
drivers/phy/mediatek/phy-mtk-tphy.c
615
static void u3_phy_dbgfs_files_create(struct mtk_phy_instance *inst)
drivers/phy/mediatek/phy-mtk-tphy.c
621
debugfs_create_file_aux_num(u3_phy_files[i], 0644, inst->phy->debugfs,
drivers/phy/mediatek/phy-mtk-tphy.c
622
inst, i, &u3_phy_fops);
drivers/phy/mediatek/phy-mtk-tphy.c
627
struct mtk_phy_instance *inst = sf->private;
drivers/phy/mediatek/phy-mtk-tphy.c
630
switch (inst->type) {
drivers/phy/mediatek/phy-mtk-tphy.c
657
static void phy_debugfs_init(struct mtk_phy_instance *inst)
drivers/phy/mediatek/phy-mtk-tphy.c
659
debugfs_create_file("type", 0444, inst->phy->debugfs, inst, &phy_type_fops);
drivers/phy/mediatek/phy-mtk-tphy.c
661
switch (inst->type) {
drivers/phy/mediatek/phy-mtk-tphy.c
663
u2_phy_dbgfs_files_create(inst);
drivers/phy/mediatek/phy-mtk-tphy.c
667
u3_phy_dbgfs_files_create(inst);
drivers/phy/mediatek/phy-mtk-tphy.c
676
static void phy_debugfs_init(struct mtk_phy_instance *inst)
drivers/phy/mediatek/phy-mtk-xsphy.c
122
struct xsphy_instance *inst)
drivers/phy/mediatek/phy-mtk-xsphy.c
124
void __iomem *pbase = inst->port_base;
drivers/phy/mediatek/phy-mtk-xsphy.c
130
if (inst->eye_src)
drivers/phy/mediatek/phy-mtk-xsphy.c
169
inst->index, fm_out, calib_val,
drivers/phy/mediatek/phy-mtk-xsphy.c
180
struct xsphy_instance *inst)
drivers/phy/mediatek/phy-mtk-xsphy.c
182
void __iomem *pbase = inst->port_base;
drivers/phy/mediatek/phy-mtk-xsphy.c
191
struct xsphy_instance *inst)
drivers/phy/mediatek/phy-mtk-xsphy.c
193
void __iomem *pbase = inst->port_base;
drivers/phy/mediatek/phy-mtk-xsphy.c
194
u32 index = inst->index;
drivers/phy/mediatek/phy-mtk-xsphy.c
206
struct xsphy_instance *inst)
drivers/phy/mediatek/phy-mtk-xsphy.c
208
void __iomem *pbase = inst->port_base;
drivers/phy/mediatek/phy-mtk-xsphy.c
209
u32 index = inst->index;
drivers/phy/mediatek/phy-mtk-xsphy.c
221
struct xsphy_instance *inst,
drivers/phy/mediatek/phy-mtk-xsphy.c
226
tmp = readl(inst->port_base + XSP_U2PHYDTM1);
drivers/phy/mediatek/phy-mtk-xsphy.c
241
writel(tmp, inst->port_base + XSP_U2PHYDTM1);
drivers/phy/mediatek/phy-mtk-xsphy.c
245
struct xsphy_instance *inst)
drivers/phy/mediatek/phy-mtk-xsphy.c
247
struct device *dev = &inst->phy->dev;
drivers/phy/mediatek/phy-mtk-xsphy.c
249
switch (inst->type) {
drivers/phy/mediatek/phy-mtk-xsphy.c
252
&inst->efuse_intr);
drivers/phy/mediatek/phy-mtk-xsphy.c
254
&inst->eye_src);
drivers/phy/mediatek/phy-mtk-xsphy.c
256
&inst->eye_vrt);
drivers/phy/mediatek/phy-mtk-xsphy.c
258
&inst->eye_term);
drivers/phy/mediatek/phy-mtk-xsphy.c
260
inst->efuse_intr, inst->eye_src,
drivers/phy/mediatek/phy-mtk-xsphy.c
261
inst->eye_vrt, inst->eye_term);
drivers/phy/mediatek/phy-mtk-xsphy.c
265
&inst->efuse_intr);
drivers/phy/mediatek/phy-mtk-xsphy.c
267
&inst->efuse_tx_imp);
drivers/phy/mediatek/phy-mtk-xsphy.c
269
&inst->efuse_rx_imp);
drivers/phy/mediatek/phy-mtk-xsphy.c
271
inst->efuse_intr, inst->efuse_tx_imp,
drivers/phy/mediatek/phy-mtk-xsphy.c
272
inst->efuse_rx_imp);
drivers/phy/mediatek/phy-mtk-xsphy.c
285
struct xsphy_instance *inst)
drivers/phy/mediatek/phy-mtk-xsphy.c
287
void __iomem *pbase = inst->port_base;
drivers/phy/mediatek/phy-mtk-xsphy.c
289
if (inst->efuse_intr)
drivers/phy/mediatek/phy-mtk-xsphy.c
291
inst->efuse_intr);
drivers/phy/mediatek/phy-mtk-xsphy.c
293
if (inst->eye_src)
drivers/phy/mediatek/phy-mtk-xsphy.c
295
inst->eye_src);
drivers/phy/mediatek/phy-mtk-xsphy.c
297
if (inst->eye_vrt)
drivers/phy/mediatek/phy-mtk-xsphy.c
299
inst->eye_vrt);
drivers/phy/mediatek/phy-mtk-xsphy.c
301
if (inst->eye_term)
drivers/phy/mediatek/phy-mtk-xsphy.c
303
inst->eye_term);
drivers/phy/mediatek/phy-mtk-xsphy.c
307
struct xsphy_instance *inst)
drivers/phy/mediatek/phy-mtk-xsphy.c
309
void __iomem *pbase = inst->port_base;
drivers/phy/mediatek/phy-mtk-xsphy.c
311
if (inst->efuse_intr)
drivers/phy/mediatek/phy-mtk-xsphy.c
313
RG_XTP_GLB_BIAS_INTR_CTRL, inst->efuse_intr);
drivers/phy/mediatek/phy-mtk-xsphy.c
315
if (inst->efuse_tx_imp)
drivers/phy/mediatek/phy-mtk-xsphy.c
317
RG_XTP_LN0_TX_IMPSEL, inst->efuse_tx_imp);
drivers/phy/mediatek/phy-mtk-xsphy.c
319
if (inst->efuse_rx_imp)
drivers/phy/mediatek/phy-mtk-xsphy.c
321
RG_XTP_LN0_RX_IMPSEL, inst->efuse_rx_imp);
drivers/phy/mediatek/phy-mtk-xsphy.c
382
struct xsphy_instance *inst = phy_get_drvdata(phy);
drivers/phy/mediatek/phy-mtk-xsphy.c
386
ret = clk_prepare_enable(inst->ref_clk);
drivers/phy/mediatek/phy-mtk-xsphy.c
392
switch (inst->type) {
drivers/phy/mediatek/phy-mtk-xsphy.c
394
u2_phy_instance_init(xsphy, inst);
drivers/phy/mediatek/phy-mtk-xsphy.c
395
u2_phy_props_set(xsphy, inst);
drivers/phy/mediatek/phy-mtk-xsphy.c
398
u3_phy_props_set(xsphy, inst);
drivers/phy/mediatek/phy-mtk-xsphy.c
406
clk_disable_unprepare(inst->ref_clk);
drivers/phy/mediatek/phy-mtk-xsphy.c
415
struct xsphy_instance *inst = phy_get_drvdata(phy);
drivers/phy/mediatek/phy-mtk-xsphy.c
418
if (inst->type == PHY_TYPE_USB2) {
drivers/phy/mediatek/phy-mtk-xsphy.c
419
u2_phy_instance_power_on(xsphy, inst);
drivers/phy/mediatek/phy-mtk-xsphy.c
420
u2_phy_slew_rate_calibrate(xsphy, inst);
drivers/phy/mediatek/phy-mtk-xsphy.c
428
struct xsphy_instance *inst = phy_get_drvdata(phy);
drivers/phy/mediatek/phy-mtk-xsphy.c
431
if (inst->type == PHY_TYPE_USB2)
drivers/phy/mediatek/phy-mtk-xsphy.c
432
u2_phy_instance_power_off(xsphy, inst);
drivers/phy/mediatek/phy-mtk-xsphy.c
439
struct xsphy_instance *inst = phy_get_drvdata(phy);
drivers/phy/mediatek/phy-mtk-xsphy.c
441
clk_disable_unprepare(inst->ref_clk);
drivers/phy/mediatek/phy-mtk-xsphy.c
447
struct xsphy_instance *inst = phy_get_drvdata(phy);
drivers/phy/mediatek/phy-mtk-xsphy.c
450
if (inst->type == PHY_TYPE_USB2)
drivers/phy/mediatek/phy-mtk-xsphy.c
451
u2_phy_instance_set_mode(xsphy, inst, mode);
drivers/phy/mediatek/phy-mtk-xsphy.c
460
struct xsphy_instance *inst = NULL;
drivers/phy/mediatek/phy-mtk-xsphy.c
471
inst = xsphy->phys[index];
drivers/phy/mediatek/phy-mtk-xsphy.c
475
if (!inst) {
drivers/phy/mediatek/phy-mtk-xsphy.c
480
inst->type = args->args[0];
drivers/phy/mediatek/phy-mtk-xsphy.c
481
if (!(inst->type == PHY_TYPE_USB2 ||
drivers/phy/mediatek/phy-mtk-xsphy.c
482
inst->type == PHY_TYPE_USB3 ||
drivers/phy/mediatek/phy-mtk-xsphy.c
483
inst->type == PHY_TYPE_PCIE ||
drivers/phy/mediatek/phy-mtk-xsphy.c
484
inst->type == PHY_TYPE_SGMII)) {
drivers/phy/mediatek/phy-mtk-xsphy.c
485
dev_err(dev, "unsupported phy type: %d\n", inst->type);
drivers/phy/mediatek/phy-mtk-xsphy.c
489
phy_parse_property(xsphy, inst);
drivers/phy/mediatek/phy-mtk-xsphy.c
490
phy_type_set(inst);
drivers/phy/mediatek/phy-mtk-xsphy.c
492
return inst->phy;
drivers/phy/mediatek/phy-mtk-xsphy.c
550
struct xsphy_instance *inst;
drivers/phy/mediatek/phy-mtk-xsphy.c
554
inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL);
drivers/phy/mediatek/phy-mtk-xsphy.c
555
if (!inst)
drivers/phy/mediatek/phy-mtk-xsphy.c
558
xsphy->phys[port] = inst;
drivers/phy/mediatek/phy-mtk-xsphy.c
573
inst->port_base = devm_ioremap_resource(&phy->dev, &res);
drivers/phy/mediatek/phy-mtk-xsphy.c
574
if (IS_ERR(inst->port_base)) {
drivers/phy/mediatek/phy-mtk-xsphy.c
576
return PTR_ERR(inst->port_base);
drivers/phy/mediatek/phy-mtk-xsphy.c
579
inst->phy = phy;
drivers/phy/mediatek/phy-mtk-xsphy.c
580
inst->index = port;
drivers/phy/mediatek/phy-mtk-xsphy.c
581
phy_set_drvdata(phy, inst);
drivers/phy/mediatek/phy-mtk-xsphy.c
584
inst->ref_clk = devm_clk_get(&phy->dev, "ref");
drivers/phy/mediatek/phy-mtk-xsphy.c
585
if (IS_ERR(inst->ref_clk)) {
drivers/phy/mediatek/phy-mtk-xsphy.c
587
return PTR_ERR(inst->ref_clk);
drivers/phy/mediatek/phy-mtk-xsphy.c
590
retval = phy_type_syscon_get(inst, child_np);
drivers/phy/phy-eyeq5-eth.c
100
if (inst->submode == EQ5_PHY_SUBMODE_SGMII) {
drivers/phy/phy-eyeq5-eth.c
101
writel(readl(inst->gp) | EQ5_GP_SGMII_MODE, inst->gp);
drivers/phy/phy-eyeq5-eth.c
104
writel(reg, inst->sgmii);
drivers/phy/phy-eyeq5-eth.c
106
if (readl_poll_timeout(inst->sgmii, reg,
drivers/phy/phy-eyeq5-eth.c
108
dev_err(inst->dev, "PLL timeout\n");
drivers/phy/phy-eyeq5-eth.c
112
reg = readl(inst->sgmii);
drivers/phy/phy-eyeq5-eth.c
114
writel(reg, inst->sgmii);
drivers/phy/phy-eyeq5-eth.c
116
writel(readl(inst->gp) & ~EQ5_GP_SGMII_MODE, inst->gp);
drivers/phy/phy-eyeq5-eth.c
117
writel(0, inst->sgmii);
drivers/phy/phy-eyeq5-eth.c
125
struct eq5_phy_inst *inst = phy_get_drvdata(phy);
drivers/phy/phy-eyeq5-eth.c
127
writel(readl(inst->gp) & ~EQ5_GP_SGMII_MODE, inst->gp);
drivers/phy/phy-eyeq5-eth.c
128
writel(0, inst->sgmii);
drivers/phy/phy-eyeq5-eth.c
136
struct eq5_phy_inst *inst = phy_get_drvdata(phy);
drivers/phy/phy-eyeq5-eth.c
144
if (inst->sgmii_support && submode == PHY_INTERFACE_MODE_SGMII)
drivers/phy/phy-eyeq5-eth.c
152
struct eq5_phy_inst *inst = phy_get_drvdata(phy);
drivers/phy/phy-eyeq5-eth.c
165
if (target_submode == inst->submode)
drivers/phy/phy-eyeq5-eth.c
168
inst->submode = target_submode;
drivers/phy/phy-eyeq5-eth.c
203
struct eq5_phy_inst *inst = &priv->phys[index];
drivers/phy/phy-eyeq5-eth.c
211
inst->dev = dev;
drivers/phy/phy-eyeq5-eth.c
212
inst->phy = phy;
drivers/phy/phy-eyeq5-eth.c
213
inst->gp = base + gp;
drivers/phy/phy-eyeq5-eth.c
214
inst->sgmii = base + sgmii;
drivers/phy/phy-eyeq5-eth.c
215
inst->sgmii_support = sgmii_support;
drivers/phy/phy-eyeq5-eth.c
216
phy_set_drvdata(phy, inst);
drivers/phy/phy-eyeq5-eth.c
222
if (sgmii_support && (readl(inst->gp) & EQ5_GP_SGMII_MODE))
drivers/phy/phy-eyeq5-eth.c
223
inst->submode = EQ5_PHY_SUBMODE_SGMII;
drivers/phy/phy-eyeq5-eth.c
225
inst->submode = EQ5_PHY_SUBMODE_RGMII;
drivers/phy/phy-eyeq5-eth.c
68
struct eq5_phy_inst *inst = phy_get_drvdata(phy);
drivers/phy/phy-eyeq5-eth.c
70
writel(0, inst->gp);
drivers/phy/phy-eyeq5-eth.c
71
writel(0, inst->sgmii);
drivers/phy/phy-eyeq5-eth.c
78
struct eq5_phy_inst *inst = phy_get_drvdata(phy);
drivers/phy/phy-eyeq5-eth.c
90
writel(reg, inst->gp);
drivers/phy/phy-eyeq5-eth.c
97
struct eq5_phy_inst *inst = phy_get_drvdata(phy);
drivers/phy/phy-google-usb.c
100
struct google_usb_phy_instance *inst = phy_get_drvdata(_phy);
drivers/phy/phy-google-usb.c
101
struct google_usb_phy *gphy = inst->parent;
drivers/phy/phy-google-usb.c
122
ret = clk_bulk_prepare_enable(inst->num_clks, inst->clks);
drivers/phy/phy-google-usb.c
126
ret = reset_control_bulk_deassert(inst->num_rsts, inst->rsts);
drivers/phy/phy-google-usb.c
128
clk_bulk_disable_unprepare(inst->num_clks, inst->clks);
drivers/phy/phy-google-usb.c
141
struct google_usb_phy_instance *inst = phy_get_drvdata(_phy);
drivers/phy/phy-google-usb.c
142
struct google_usb_phy *gphy = inst->parent;
drivers/phy/phy-google-usb.c
153
reset_control_bulk_assert(inst->num_rsts, inst->rsts);
drivers/phy/phy-google-usb.c
154
clk_bulk_disable_unprepare(inst->num_clks, inst->clks);
drivers/phy/phy-google-usb.c
179
struct google_usb_phy_instance *inst;
drivers/phy/phy-google-usb.c
219
inst = &gphy->insts[GOOGLE_USB2_PHY];
drivers/phy/phy-google-usb.c
220
inst->parent = gphy;
drivers/phy/phy-google-usb.c
221
inst->index = GOOGLE_USB2_PHY;
drivers/phy/phy-google-usb.c
226
inst->phy = phy;
drivers/phy/phy-google-usb.c
227
phy_set_drvdata(phy, inst);
drivers/phy/phy-google-usb.c
229
inst->num_clks = 2;
drivers/phy/phy-google-usb.c
230
inst->clks = devm_kcalloc(dev, inst->num_clks, sizeof(*inst->clks), GFP_KERNEL);
drivers/phy/phy-google-usb.c
231
if (!inst->clks)
drivers/phy/phy-google-usb.c
233
inst->clks[0].id = "usb2";
drivers/phy/phy-google-usb.c
234
inst->clks[1].id = "usb2_apb";
drivers/phy/phy-google-usb.c
235
ret = devm_clk_bulk_get(dev, inst->num_clks, inst->clks);
drivers/phy/phy-google-usb.c
239
inst->num_rsts = 2;
drivers/phy/phy-google-usb.c
240
inst->rsts = devm_kcalloc(dev, inst->num_rsts, sizeof(*inst->rsts), GFP_KERNEL);
drivers/phy/phy-google-usb.c
241
if (!inst->rsts)
drivers/phy/phy-google-usb.c
243
inst->rsts[0].id = "usb2";
drivers/phy/phy-google-usb.c
244
inst->rsts[1].id = "usb2_apb";
drivers/phy/phy-google-usb.c
245
ret = devm_reset_control_bulk_get_exclusive(dev, inst->num_rsts, inst->rsts);
drivers/phy/rockchip/phy-rockchip-pcie.c
102
struct phy_pcie_instance *inst = phy_get_drvdata(phy);
drivers/phy/rockchip/phy-rockchip-pcie.c
103
struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
drivers/phy/rockchip/phy-rockchip-pcie.c
110
PHY_LANE_IDLE_OFF) << inst->index);
drivers/phy/rockchip/phy-rockchip-pcie.c
122
!PHY_LANE_IDLE_OFF) << inst->index);
drivers/phy/rockchip/phy-rockchip-pcie.c
131
struct phy_pcie_instance *inst = phy_get_drvdata(phy);
drivers/phy/rockchip/phy-rockchip-pcie.c
132
struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
drivers/phy/rockchip/phy-rockchip-pcie.c
140
!PHY_LANE_IDLE_OFF) << inst->index);
drivers/phy/rockchip/phy-rockchip-pcie.c
207
struct phy_pcie_instance *inst = phy_get_drvdata(phy);
drivers/phy/rockchip/phy-rockchip-pcie.c
208
struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
drivers/phy/rockchip/phy-rockchip-pcie.c
229
struct phy_pcie_instance *inst = phy_get_drvdata(phy);
drivers/phy/rockchip/phy-rockchip-pcie.c
230
struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
drivers/phy/rockchip/phy-rockchip-pcie.c
65
static struct rockchip_pcie_phy *to_pcie_phy(struct phy_pcie_instance *inst)
drivers/phy/rockchip/phy-rockchip-pcie.c
67
return container_of(inst, struct rockchip_pcie_phy,
drivers/phy/rockchip/phy-rockchip-pcie.c
68
phys[inst->index]);
drivers/phy/samsung/phy-exynos4210-usb2.c
124
static void exynos4210_isol(struct samsung_usb2_phy_instance *inst, bool on)
drivers/phy/samsung/phy-exynos4210-usb2.c
126
struct samsung_usb2_phy_driver *drv = inst->drv;
drivers/phy/samsung/phy-exynos4210-usb2.c
130
switch (inst->cfg->id) {
drivers/phy/samsung/phy-exynos4210-usb2.c
146
static void exynos4210_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
drivers/phy/samsung/phy-exynos4210-usb2.c
148
struct samsung_usb2_phy_driver *drv = inst->drv;
drivers/phy/samsung/phy-exynos4210-usb2.c
155
switch (inst->cfg->id) {
drivers/phy/samsung/phy-exynos4210-usb2.c
207
static int exynos4210_power_on(struct samsung_usb2_phy_instance *inst)
drivers/phy/samsung/phy-exynos4210-usb2.c
210
exynos4210_phy_pwr(inst, 1);
drivers/phy/samsung/phy-exynos4210-usb2.c
211
exynos4210_isol(inst, 0);
drivers/phy/samsung/phy-exynos4210-usb2.c
216
static int exynos4210_power_off(struct samsung_usb2_phy_instance *inst)
drivers/phy/samsung/phy-exynos4210-usb2.c
218
exynos4210_isol(inst, 1);
drivers/phy/samsung/phy-exynos4210-usb2.c
219
exynos4210_phy_pwr(inst, 0);
drivers/phy/samsung/phy-exynos4x12-usb2.c
165
static void exynos4x12_isol(struct samsung_usb2_phy_instance *inst, bool on)
drivers/phy/samsung/phy-exynos4x12-usb2.c
167
struct samsung_usb2_phy_driver *drv = inst->drv;
drivers/phy/samsung/phy-exynos4x12-usb2.c
171
switch (inst->cfg->id) {
drivers/phy/samsung/phy-exynos4x12-usb2.c
192
static void exynos4x12_setup_clk(struct samsung_usb2_phy_instance *inst)
drivers/phy/samsung/phy-exynos4x12-usb2.c
194
struct samsung_usb2_phy_driver *drv = inst->drv;
drivers/phy/samsung/phy-exynos4x12-usb2.c
208
static void exynos4x12_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
drivers/phy/samsung/phy-exynos4x12-usb2.c
210
struct samsung_usb2_phy_driver *drv = inst->drv;
drivers/phy/samsung/phy-exynos4x12-usb2.c
216
switch (inst->cfg->id) {
drivers/phy/samsung/phy-exynos4x12-usb2.c
260
static void exynos4x12_power_on_int(struct samsung_usb2_phy_instance *inst)
drivers/phy/samsung/phy-exynos4x12-usb2.c
262
if (inst->int_cnt++ > 0)
drivers/phy/samsung/phy-exynos4x12-usb2.c
265
exynos4x12_setup_clk(inst);
drivers/phy/samsung/phy-exynos4x12-usb2.c
266
exynos4x12_isol(inst, 0);
drivers/phy/samsung/phy-exynos4x12-usb2.c
267
exynos4x12_phy_pwr(inst, 1);
drivers/phy/samsung/phy-exynos4x12-usb2.c
270
static int exynos4x12_power_on(struct samsung_usb2_phy_instance *inst)
drivers/phy/samsung/phy-exynos4x12-usb2.c
272
struct samsung_usb2_phy_driver *drv = inst->drv;
drivers/phy/samsung/phy-exynos4x12-usb2.c
274
if (inst->ext_cnt++ > 0)
drivers/phy/samsung/phy-exynos4x12-usb2.c
277
if (inst->cfg->id == EXYNOS4x12_HOST) {
drivers/phy/samsung/phy-exynos4x12-usb2.c
284
if (inst->cfg->id == EXYNOS4x12_DEVICE && drv->cfg->has_mode_switch)
drivers/phy/samsung/phy-exynos4x12-usb2.c
289
if (inst->cfg->id == EXYNOS4x12_HSIC0 ||
drivers/phy/samsung/phy-exynos4x12-usb2.c
290
inst->cfg->id == EXYNOS4x12_HSIC1) {
drivers/phy/samsung/phy-exynos4x12-usb2.c
295
exynos4x12_power_on_int(inst);
drivers/phy/samsung/phy-exynos4x12-usb2.c
300
static void exynos4x12_power_off_int(struct samsung_usb2_phy_instance *inst)
drivers/phy/samsung/phy-exynos4x12-usb2.c
302
if (inst->int_cnt-- > 1)
drivers/phy/samsung/phy-exynos4x12-usb2.c
305
exynos4x12_isol(inst, 1);
drivers/phy/samsung/phy-exynos4x12-usb2.c
306
exynos4x12_phy_pwr(inst, 0);
drivers/phy/samsung/phy-exynos4x12-usb2.c
309
static int exynos4x12_power_off(struct samsung_usb2_phy_instance *inst)
drivers/phy/samsung/phy-exynos4x12-usb2.c
311
struct samsung_usb2_phy_driver *drv = inst->drv;
drivers/phy/samsung/phy-exynos4x12-usb2.c
313
if (inst->ext_cnt-- > 1)
drivers/phy/samsung/phy-exynos4x12-usb2.c
316
if (inst->cfg->id == EXYNOS4x12_DEVICE && drv->cfg->has_mode_switch)
drivers/phy/samsung/phy-exynos4x12-usb2.c
321
if (inst->cfg->id == EXYNOS4x12_HOST)
drivers/phy/samsung/phy-exynos4x12-usb2.c
324
if (inst->cfg->id == EXYNOS4x12_HSIC0 ||
drivers/phy/samsung/phy-exynos4x12-usb2.c
325
inst->cfg->id == EXYNOS4x12_HSIC1) {
drivers/phy/samsung/phy-exynos4x12-usb2.c
330
exynos4x12_power_off_int(inst);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1004
inst->phy_cfg->phy_isol(inst, false);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1017
struct phy_usb_instance *inst = phy_get_drvdata(phy);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1018
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1023
inst->phy_cfg->phy_isol(inst, true);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1175
struct phy_usb_instance *inst = phy_get_drvdata(phy);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1176
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1178
if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI)
drivers/phy/samsung/phy-exynos5-usbdrd.c
1192
static void exynos7870_usbdrd_phy_isol(struct phy_usb_instance *inst,
drivers/phy/samsung/phy-exynos5-usbdrd.c
1197
if (!inst->reg_pmu)
drivers/phy/samsung/phy-exynos5-usbdrd.c
1202
regmap_update_bits(inst->reg_pmu, inst->pmu_offset,
drivers/phy/samsung/phy-exynos5-usbdrd.c
1298
struct phy_usb_instance *inst = phy_get_drvdata(phy);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1299
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1307
inst->phy_cfg->phy_init(phy_drd);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1318
struct phy_usb_instance *inst = phy_get_drvdata(phy);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1319
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1390
exynos2200_usbdrd_link_attach_detach_pipe3_phy(struct phy_usb_instance *inst)
drivers/phy/samsung/phy-exynos5-usbdrd.c
1392
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1397
if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) {
drivers/phy/samsung/phy-exynos5-usbdrd.c
1408
if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) {
drivers/phy/samsung/phy-exynos5-usbdrd.c
1420
if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI)
drivers/phy/samsung/phy-exynos5-usbdrd.c
1430
struct phy_usb_instance *inst = phy_get_drvdata(phy);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1431
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1434
if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) {
drivers/phy/samsung/phy-exynos5-usbdrd.c
1448
exynos5_usbdrd_phy_isol(inst, false);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1458
exynos2200_usbdrd_link_attach_detach_pipe3_phy(inst);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1461
inst->phy_cfg->phy_init(phy_drd);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1470
struct phy_usb_instance *inst = phy_get_drvdata(phy);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1471
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1490
exynos5_usbdrd_phy_isol(inst, true);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1629
struct phy_usb_instance *inst = phy_get_drvdata(phy);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1630
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1639
inst->phy_cfg->phy_init(phy_drd);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1648
struct phy_usb_instance *inst = phy_get_drvdata(phy);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1649
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1724
struct phy_usb_instance *inst = phy_get_drvdata(phy);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1725
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1728
if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) {
drivers/phy/samsung/phy-exynos5-usbdrd.c
1742
exynos5_usbdrd_phy_isol(inst, false);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1749
struct phy_usb_instance *inst = phy_get_drvdata(phy);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1750
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1753
if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) {
drivers/phy/samsung/phy-exynos5-usbdrd.c
1759
exynos5_usbdrd_phy_isol(inst, true);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1761
if (inst->phy_cfg->id != EXYNOS5_DRDPHY_UTMI)
drivers/phy/samsung/phy-exynos5-usbdrd.c
2495
struct phy_usb_instance *inst = phy_get_drvdata(phy);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2496
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2504
inst->phy_cfg->phy_isol(inst, false);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2507
inst->phy_cfg->phy_init(phy_drd);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2516
struct phy_usb_instance *inst = phy_get_drvdata(phy);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2517
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2527
inst->phy_cfg->phy_isol(inst, true);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2536
struct phy_usb_instance *inst = phy_get_drvdata(phy);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2537
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2544
if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI)
drivers/phy/samsung/phy-exynos5-usbdrd.c
2546
else if (inst->phy_cfg->id == EXYNOS5_DRDPHY_PIPE3)
drivers/phy/samsung/phy-exynos5-usbdrd.c
2550
inst->phy_cfg->phy_isol(inst, true);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2559
struct phy_usb_instance *inst = phy_get_drvdata(phy);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2560
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2589
struct phy_usb_instance *inst = phy_get_drvdata(phy);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2590
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
drivers/phy/samsung/phy-exynos5-usbdrd.c
473
void (*phy_isol)(struct phy_usb_instance *inst, bool isolate);
drivers/phy/samsung/phy-exynos5-usbdrd.c
475
unsigned int (*set_refclk)(struct phy_usb_instance *inst);
drivers/phy/samsung/phy-exynos5-usbdrd.c
537
struct exynos5_usbdrd_phy *to_usbdrd_phy(struct phy_usb_instance *inst)
drivers/phy/samsung/phy-exynos5-usbdrd.c
539
return container_of((inst), struct exynos5_usbdrd_phy,
drivers/phy/samsung/phy-exynos5-usbdrd.c
540
phys[(inst)->index]);
drivers/phy/samsung/phy-exynos5-usbdrd.c
583
static void exynos5_usbdrd_phy_isol(struct phy_usb_instance *inst,
drivers/phy/samsung/phy-exynos5-usbdrd.c
588
if (!inst->reg_pmu)
drivers/phy/samsung/phy-exynos5-usbdrd.c
593
regmap_update_bits(inst->reg_pmu, inst->pmu_offset,
drivers/phy/samsung/phy-exynos5-usbdrd.c
603
exynos5_usbdrd_pipe3_set_refclk(struct phy_usb_instance *inst)
drivers/phy/samsung/phy-exynos5-usbdrd.c
606
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
drivers/phy/samsung/phy-exynos5-usbdrd.c
653
exynos5_usbdrd_utmi_set_refclk(struct phy_usb_instance *inst)
drivers/phy/samsung/phy-exynos5-usbdrd.c
656
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
drivers/phy/samsung/phy-exynos5-usbdrd.c
890
struct phy_usb_instance *inst = phy_get_drvdata(phy);
drivers/phy/samsung/phy-exynos5-usbdrd.c
891
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
drivers/phy/samsung/phy-exynos5-usbdrd.c
920
inst->phy_cfg->phy_init(phy_drd);
drivers/phy/samsung/phy-exynos5-usbdrd.c
923
reg = inst->phy_cfg->set_refclk(inst);
drivers/phy/samsung/phy-exynos5-usbdrd.c
952
struct phy_usb_instance *inst = phy_get_drvdata(phy);
drivers/phy/samsung/phy-exynos5-usbdrd.c
953
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
drivers/phy/samsung/phy-exynos5-usbdrd.c
985
struct phy_usb_instance *inst = phy_get_drvdata(phy);
drivers/phy/samsung/phy-exynos5-usbdrd.c
986
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
drivers/phy/samsung/phy-exynos5250-usb2.c
174
static void exynos5250_isol(struct samsung_usb2_phy_instance *inst, bool on)
drivers/phy/samsung/phy-exynos5250-usb2.c
176
struct samsung_usb2_phy_driver *drv = inst->drv;
drivers/phy/samsung/phy-exynos5250-usb2.c
181
inst->cfg->id == EXYNOS5250_DEVICE)
drivers/phy/samsung/phy-exynos5250-usb2.c
184
inst->cfg->id == EXYNOS5250_HOST)
drivers/phy/samsung/phy-exynos5250-usb2.c
187
inst->cfg->id == EXYNOS5250_HOST)
drivers/phy/samsung/phy-exynos5250-usb2.c
195
static int exynos5250_power_on(struct samsung_usb2_phy_instance *inst)
drivers/phy/samsung/phy-exynos5250-usb2.c
197
struct samsung_usb2_phy_driver *drv = inst->drv;
drivers/phy/samsung/phy-exynos5250-usb2.c
204
switch (inst->cfg->id) {
drivers/phy/samsung/phy-exynos5250-usb2.c
316
exynos5250_isol(inst, 0);
drivers/phy/samsung/phy-exynos5250-usb2.c
321
static int exynos5250_power_off(struct samsung_usb2_phy_instance *inst)
drivers/phy/samsung/phy-exynos5250-usb2.c
323
struct samsung_usb2_phy_driver *drv = inst->drv;
drivers/phy/samsung/phy-exynos5250-usb2.c
328
exynos5250_isol(inst, 1);
drivers/phy/samsung/phy-exynos5250-usb2.c
330
switch (inst->cfg->id) {
drivers/phy/samsung/phy-s5pv210-usb2.c
109
static void s5pv210_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
drivers/phy/samsung/phy-s5pv210-usb2.c
111
struct samsung_usb2_phy_driver *drv = inst->drv;
drivers/phy/samsung/phy-s5pv210-usb2.c
117
switch (inst->cfg->id) {
drivers/phy/samsung/phy-s5pv210-usb2.c
153
static int s5pv210_power_on(struct samsung_usb2_phy_instance *inst)
drivers/phy/samsung/phy-s5pv210-usb2.c
155
s5pv210_isol(inst, 0);
drivers/phy/samsung/phy-s5pv210-usb2.c
156
s5pv210_phy_pwr(inst, 1);
drivers/phy/samsung/phy-s5pv210-usb2.c
161
static int s5pv210_power_off(struct samsung_usb2_phy_instance *inst)
drivers/phy/samsung/phy-s5pv210-usb2.c
163
s5pv210_phy_pwr(inst, 0);
drivers/phy/samsung/phy-s5pv210-usb2.c
164
s5pv210_isol(inst, 1);
drivers/phy/samsung/phy-s5pv210-usb2.c
89
static void s5pv210_isol(struct samsung_usb2_phy_instance *inst, bool on)
drivers/phy/samsung/phy-s5pv210-usb2.c
91
struct samsung_usb2_phy_driver *drv = inst->drv;
drivers/phy/samsung/phy-s5pv210-usb2.c
94
switch (inst->cfg->id) {
drivers/phy/samsung/phy-samsung-usb2.c
20
struct samsung_usb2_phy_instance *inst = phy_get_drvdata(phy);
drivers/phy/samsung/phy-samsung-usb2.c
21
struct samsung_usb2_phy_driver *drv = inst->drv;
drivers/phy/samsung/phy-samsung-usb2.c
25
inst->cfg->label);
drivers/phy/samsung/phy-samsung-usb2.c
39
if (inst->cfg->power_on) {
drivers/phy/samsung/phy-samsung-usb2.c
41
ret = inst->cfg->power_on(inst);
drivers/phy/samsung/phy-samsung-usb2.c
62
struct samsung_usb2_phy_instance *inst = phy_get_drvdata(phy);
drivers/phy/samsung/phy-samsung-usb2.c
63
struct samsung_usb2_phy_driver *drv = inst->drv;
drivers/phy/samsung/phy-samsung-usb2.c
67
inst->cfg->label);
drivers/phy/samsung/phy-samsung-usb2.c
68
if (inst->cfg->power_off) {
drivers/phy/samsung/phy-samsung-usb2.c
70
ret = inst->cfg->power_off(inst);
drivers/pinctrl/mediatek/mtk-eint.c
135
unsigned int inst = eint->pins[d->hwirq].instance;
drivers/pinctrl/mediatek/mtk-eint.c
140
eint->cur_mask[inst][idx >> 5] &= ~mask;
drivers/pinctrl/mediatek/mtk-eint.c
149
unsigned int inst = eint->pins[d->hwirq].instance;
drivers/pinctrl/mediatek/mtk-eint.c
154
eint->cur_mask[inst][idx >> 5] |= mask;
drivers/pinctrl/mediatek/mtk-eint.c
236
unsigned int inst = eint->pins[d->hwirq].instance;
drivers/pinctrl/mediatek/mtk-eint.c
241
eint->wake_mask[inst][port] |= BIT(shift);
drivers/pinctrl/mediatek/mtk-eint.c
243
eint->wake_mask[inst][port] &= ~BIT(shift);
drivers/pinctrl/mediatek/mtk-eint.c
251
int inst, port, port_num;
drivers/pinctrl/mediatek/mtk-eint.c
254
for (inst = 0; inst < eint->nbase; inst++) {
drivers/pinctrl/mediatek/mtk-eint.c
255
port_num = DIV_ROUND_UP(eint->base_pin_num[inst], 32);
drivers/pinctrl/mediatek/mtk-eint.c
257
reg = eint->base[inst] + (port << 2);
drivers/pinctrl/mediatek/mtk-eint.c
258
writel_relaxed(~buf[inst][port], reg + eint->regs->mask_set);
drivers/pinctrl/mediatek/mtk-eint.c
259
writel_relaxed(buf[inst][port], reg + eint->regs->mask_clr);
drivers/pinctrl/mediatek/mtk-eint.c
342
unsigned int inst = eint->pins[index].instance;
drivers/pinctrl/mediatek/mtk-eint.c
346
dbnc = readl(eint->base[inst] + ctrl_offset);
drivers/pinctrl/mediatek/mtk-eint.c
351
writel(rst, eint->base[inst] + ctrl_offset);
drivers/pinctrl/mediatek/mtk-eint.c
448
unsigned int inst = eint->pins[eint_num].instance;
drivers/pinctrl/mediatek/mtk-eint.c
481
writel(clr_bit, eint->base[inst] + clr_offset);
drivers/pinctrl/mediatek/mtk-eint.c
486
writel(rst | bit, eint->base[inst] + set_offset);
drivers/pinctrl/mediatek/mtk-eint.c
514
unsigned int size, i, port, virq, inst = 0;
drivers/pinctrl/mediatek/mtk-eint.c
528
inst = eint->pins[i].instance;
drivers/pinctrl/mediatek/mtk-eint.c
529
if (inst >= eint->nbase)
drivers/pinctrl/mediatek/mtk-eint.c
531
eint->base_pin_num[inst]++;
drivers/pinctrl/mediatek/mtk-eint.c
539
eint->base_pin_num[inst] = eint->hw->ap_num;
drivers/pinctrl/mediatek/mtk-eint.c
541
eint->pins[i].instance = inst;
drivers/pinctrl/mediatek/mtk-eint.c
591
inst = eint->pins[i].instance;
drivers/pinctrl/mediatek/mtk-eint.c
592
if (inst >= eint->nbase)
drivers/pinctrl/mediatek/mtk-eint.c
594
eint->pin_list[inst][eint->pins[i].index] = i;
drivers/pinctrl/mediatek/mtk-eint.c
79
unsigned int inst = eint->pins[eint_num].instance;
drivers/pinctrl/mediatek/mtk-eint.c
82
reg = eint->base[inst] + offset + (idx / 32 * 4);
drivers/platform/x86/intel/pmt/telemetry.c
348
int inst = 0;
drivers/platform/x86/intel/pmt/telemetry.c
359
if (inst == pos)
drivers/platform/x86/intel/pmt/telemetry.c
361
++inst;
drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
1563
int ret, pkg = 0, inst = 0;
drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
1675
++inst;
drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
1678
if (!inst) {
drivers/platform/x86/serial-multi-instantiate.c
52
const struct smi_instance *inst)
drivers/platform/x86/serial-multi-instantiate.c
56
switch (inst->flags & IRQ_RESOURCE_TYPE) {
drivers/platform/x86/serial-multi-instantiate.c
58
ret = acpi_dev_gpio_irq_get(adev, inst->irq_idx);
drivers/platform/x86/serial-multi-instantiate.c
63
ret = platform_get_irq(pdev, inst->irq_idx);
drivers/platform/x86/serial-multi-instantiate.c
68
if (inst->flags & IRQ_RESOURCE_OPT) {
drivers/platform/x86/serial-multi-instantiate.c
74
ret = acpi_dev_gpio_irq_get(adev, inst->irq_idx);
drivers/platform/x86/serial-multi-instantiate.c
77
ret = platform_get_irq(pdev, inst->irq_idx);
drivers/platform/x86/serial-multi-instantiate.c
84
inst->irq_idx);
drivers/scsi/arm/fas216.c
158
unsigned char is, stat, inst;
drivers/scsi/arm/fas216.c
162
inst = fas216_readb(info, REG_INST);
drivers/scsi/arm/fas216.c
1638
unsigned char inst, is, stat;
drivers/scsi/arm/fas216.c
1645
inst = fas216_readb(info, REG_INST);
drivers/scsi/arm/fas216.c
1647
add_debug_list(stat, is, inst, info->scsi.phase);
drivers/scsi/arm/fas216.c
1650
if (inst & INST_BUSRESET) {
drivers/scsi/arm/fas216.c
1654
} else if (inst & INST_ILLEGALCMD) {
drivers/scsi/arm/fas216.c
1658
} else if (inst & INST_DISCONNECT)
drivers/scsi/arm/fas216.c
1660
else if (inst & INST_RESELECTED) /* reselected */
drivers/scsi/arm/fas216.c
1662
else if (inst & INST_BUSSERVICE) /* bus service request */
drivers/scsi/arm/fas216.c
1664
else if (inst & INST_FUNCDONE) /* function done */
drivers/scsi/arm/fas216.c
1669
fas216_drv_phase(info), inst, is, stat);
drivers/scsi/arm/fas216.c
168
fas216_readb(info, REG_CMD), stat, inst, is,
drivers/scsi/bfa/bfa_defs.h
794
struct bfa_ablk_cfg_inst_s inst[BFA_ABLK_MAX];
drivers/scsi/bfa/bfa_ioc.c
3240
cfg_inst = &cfg->inst[i];
drivers/scsi/bfa/bfa_ioc.c
4168
int inst, int type)
drivers/scsi/bfa/bfa_ioc.c
4178
aen_entry->aen_data.audit.partition_inst = inst;
drivers/soc/mediatek/mtk-cmdq-helper.c
183
struct cmdq_instruction inst)
drivers/soc/mediatek/mtk-cmdq-helper.c
203
*cmd_ptr = inst;
drivers/soc/mediatek/mtk-cmdq-helper.c
211
struct cmdq_instruction inst = {
drivers/soc/mediatek/mtk-cmdq-helper.c
215
return cmdq_pkt_append_command(pkt, inst);
drivers/soc/mediatek/mtk-cmdq-helper.c
220
struct cmdq_instruction inst = {
drivers/soc/mediatek/mtk-cmdq-helper.c
226
return cmdq_pkt_append_command(pkt, inst);
drivers/soc/mediatek/mtk-cmdq-helper.c
291
struct cmdq_instruction inst = {
drivers/soc/mediatek/mtk-cmdq-helper.c
298
return cmdq_pkt_append_command(pkt, inst);
drivers/soc/mediatek/mtk-cmdq-helper.c
305
struct cmdq_instruction inst = {
drivers/soc/mediatek/mtk-cmdq-helper.c
312
return cmdq_pkt_append_command(pkt, inst);
drivers/soc/mediatek/mtk-cmdq-helper.c
319
struct cmdq_instruction inst = {
drivers/soc/mediatek/mtk-cmdq-helper.c
332
return cmdq_pkt_append_command(pkt, inst);
drivers/soc/mediatek/mtk-cmdq-helper.c
339
struct cmdq_instruction inst = {
drivers/soc/mediatek/mtk-cmdq-helper.c
345
return cmdq_pkt_append_command(pkt, inst);
drivers/soc/mediatek/mtk-cmdq-helper.c
352
struct cmdq_instruction inst = {
drivers/soc/mediatek/mtk-cmdq-helper.c
364
return cmdq_pkt_append_command(pkt, inst);
drivers/soc/mediatek/mtk-cmdq-helper.c
399
struct cmdq_instruction inst = {
drivers/soc/mediatek/mtk-cmdq-helper.c
408
return cmdq_pkt_append_command(pkt, inst);
drivers/soc/mediatek/mtk-cmdq-helper.c
414
struct cmdq_instruction inst = {
drivers/soc/mediatek/mtk-cmdq-helper.c
423
return cmdq_pkt_append_command(pkt, inst);
drivers/soc/mediatek/mtk-cmdq-helper.c
429
struct cmdq_instruction inst = {
drivers/soc/mediatek/mtk-cmdq-helper.c
438
return cmdq_pkt_append_command(pkt, inst);
drivers/soc/mediatek/mtk-cmdq-helper.c
444
struct cmdq_instruction inst = {
drivers/soc/mediatek/mtk-cmdq-helper.c
453
return cmdq_pkt_append_command(pkt, inst);
drivers/soc/mediatek/mtk-cmdq-helper.c
460
struct cmdq_instruction inst = {
drivers/soc/mediatek/mtk-cmdq-helper.c
466
return cmdq_pkt_append_command(pkt, inst);
drivers/soc/mediatek/mtk-cmdq-helper.c
486
struct cmdq_instruction inst = { {0} };
drivers/soc/mediatek/mtk-cmdq-helper.c
507
inst.op = CMDQ_CODE_MASK;
drivers/soc/mediatek/mtk-cmdq-helper.c
508
inst.dst_t = CMDQ_REG_TYPE;
drivers/soc/mediatek/mtk-cmdq-helper.c
509
inst.sop = CMDQ_POLL_ADDR_GPR;
drivers/soc/mediatek/mtk-cmdq-helper.c
510
inst.value = addr + pkt->priv.mminfra_offset;
drivers/soc/mediatek/mtk-cmdq-helper.c
511
ret = cmdq_pkt_append_command(pkt, inst);
drivers/soc/mediatek/mtk-cmdq-helper.c
516
inst.op = CMDQ_CODE_POLL;
drivers/soc/mediatek/mtk-cmdq-helper.c
517
inst.dst_t = CMDQ_REG_TYPE;
drivers/soc/mediatek/mtk-cmdq-helper.c
518
inst.sop = CMDQ_POLL_ADDR_GPR;
drivers/soc/mediatek/mtk-cmdq-helper.c
519
inst.offset = use_mask;
drivers/soc/mediatek/mtk-cmdq-helper.c
520
inst.value = value;
drivers/soc/mediatek/mtk-cmdq-helper.c
521
ret = cmdq_pkt_append_command(pkt, inst);
drivers/soc/mediatek/mtk-cmdq-helper.c
534
struct cmdq_instruction inst;
drivers/soc/mediatek/mtk-cmdq-helper.c
539
inst.value = 0;
drivers/soc/mediatek/mtk-cmdq-helper.c
540
inst.op = CMDQ_CODE_LOGIC;
drivers/soc/mediatek/mtk-cmdq-helper.c
541
inst.dst_t = CMDQ_REG_TYPE;
drivers/soc/mediatek/mtk-cmdq-helper.c
542
inst.src_t = cmdq_operand_get_type(left_operand);
drivers/soc/mediatek/mtk-cmdq-helper.c
543
inst.arg_c_t = cmdq_operand_get_type(right_operand);
drivers/soc/mediatek/mtk-cmdq-helper.c
544
inst.sop = s_op;
drivers/soc/mediatek/mtk-cmdq-helper.c
545
inst.reg_dst = result_reg_idx;
drivers/soc/mediatek/mtk-cmdq-helper.c
546
inst.src_reg = cmdq_operand_get_idx_value(left_operand);
drivers/soc/mediatek/mtk-cmdq-helper.c
547
inst.arg_c = cmdq_operand_get_idx_value(right_operand);
drivers/soc/mediatek/mtk-cmdq-helper.c
549
return cmdq_pkt_append_command(pkt, inst);
drivers/soc/mediatek/mtk-cmdq-helper.c
555
struct cmdq_instruction inst = {
drivers/soc/mediatek/mtk-cmdq-helper.c
561
return cmdq_pkt_append_command(pkt, inst);
drivers/soc/mediatek/mtk-cmdq-helper.c
567
struct cmdq_instruction inst = {
drivers/soc/mediatek/mtk-cmdq-helper.c
572
return cmdq_pkt_append_command(pkt, inst);
drivers/soc/mediatek/mtk-cmdq-helper.c
578
struct cmdq_instruction inst = {
drivers/soc/mediatek/mtk-cmdq-helper.c
582
return cmdq_pkt_append_command(pkt, inst);
drivers/soc/mediatek/mtk-cmdq-helper.c
588
struct cmdq_instruction inst = {
drivers/soc/mediatek/mtk-cmdq-helper.c
592
return cmdq_pkt_append_command(pkt, inst);
drivers/soc/tegra/ari-tegra186.c
27
static void read_uncore_mca(u8 cmd, u8 idx, u8 subidx, u8 inst, u64 *data)
drivers/soc/tegra/ari-tegra186.c
32
((u64)inst << 24) | ((u64)idx << 16) |
drivers/soc/ti/knav_qmss.h
279
struct knav_queue_inst *inst;
drivers/soc/ti/knav_qmss.h
314
struct knav_queue_inst *inst);
drivers/soc/ti/knav_qmss.h
316
struct knav_queue_inst *inst, unsigned flags);
drivers/soc/ti/knav_qmss.h
318
struct knav_queue_inst *inst);
drivers/soc/ti/knav_qmss.h
320
struct knav_queue_inst *inst, bool enabled);
drivers/soc/ti/knav_qmss.h
385
extern void knav_queue_notify(struct knav_queue_inst *inst);
drivers/soc/ti/knav_qmss_acc.c
27
struct knav_queue_inst *inst;
drivers/soc/ti/knav_qmss_acc.c
34
inst = knav_range_offset_to_inst(kdev, range,
drivers/soc/ti/knav_qmss_acc.c
36
if (inst->notify_needed) {
drivers/soc/ti/knav_qmss_acc.c
37
inst->notify_needed = 0;
drivers/soc/ti/knav_qmss_acc.c
40
knav_queue_notify(inst);
drivers/soc/ti/knav_qmss_acc.c
412
struct knav_queue_inst *inst, unsigned flags)
drivers/soc/ti/knav_qmss_acc.c
414
unsigned id = inst->id - range->queue_base;
drivers/soc/ti/knav_qmss_acc.c
420
struct knav_queue_inst *inst)
drivers/soc/ti/knav_qmss_acc.c
422
unsigned id = inst->id - range->queue_base;
drivers/soc/ti/knav_qmss_acc.c
45
inst = knav_range_offset_to_inst(kdev, range, queue);
drivers/soc/ti/knav_qmss_acc.c
48
knav_queue_notify(inst);
drivers/soc/ti/knav_qmss_queue.c
105
struct knav_queue_inst *inst = _instdata;
drivers/soc/ti/knav_qmss_queue.c
107
knav_queue_notify(inst);
drivers/soc/ti/knav_qmss_queue.c
112
struct knav_queue_inst *inst)
drivers/soc/ti/knav_qmss_queue.c
114
unsigned queue = inst->id - range->queue_base;
drivers/soc/ti/knav_qmss_queue.c
120
inst->irq_name, inst);
drivers/soc/ti/knav_qmss_queue.c
135
static void knav_queue_free_irq(struct knav_queue_inst *inst)
drivers/soc/ti/knav_qmss_queue.c
137
struct knav_range_info *range = inst->range;
drivers/soc/ti/knav_qmss_queue.c
138
unsigned queue = inst->id - inst->range->queue_base;
drivers/soc/ti/knav_qmss_queue.c
144
free_irq(irq, inst);
drivers/soc/ti/knav_qmss_queue.c
148
static inline bool knav_queue_is_busy(struct knav_queue_inst *inst)
drivers/soc/ti/knav_qmss_queue.c
150
return !list_empty(&inst->handles);
drivers/soc/ti/knav_qmss_queue.c
153
static inline bool knav_queue_is_reserved(struct knav_queue_inst *inst)
drivers/soc/ti/knav_qmss_queue.c
155
return inst->range->flags & RANGE_RESERVED;
drivers/soc/ti/knav_qmss_queue.c
158
static inline bool knav_queue_is_shared(struct knav_queue_inst *inst)
drivers/soc/ti/knav_qmss_queue.c
163
for_each_handle_rcu(tmp, inst) {
drivers/soc/ti/knav_qmss_queue.c
1694
struct knav_queue_inst *inst,
drivers/soc/ti/knav_qmss_queue.c
1698
inst->qmgr = knav_find_qmgr(id);
drivers/soc/ti/knav_qmss_queue.c
1699
if (!inst->qmgr)
drivers/soc/ti/knav_qmss_queue.c
1702
INIT_LIST_HEAD(&inst->handles);
drivers/soc/ti/knav_qmss_queue.c
1703
inst->kdev = kdev;
drivers/soc/ti/knav_qmss_queue.c
1704
inst->range = range;
drivers/soc/ti/knav_qmss_queue.c
1705
inst->irq_num = -1;
drivers/soc/ti/knav_qmss_queue.c
1706
inst->id = id;
drivers/soc/ti/knav_qmss_queue.c
1708
inst->irq_name = kstrndup(irq_name, sizeof(irq_name), GFP_KERNEL);
drivers/soc/ti/knav_qmss_queue.c
1711
return range->ops->init_queue(range, inst);
drivers/soc/ti/knav_qmss_queue.c
173
static inline bool knav_queue_match_type(struct knav_queue_inst *inst,
drivers/soc/ti/knav_qmss_queue.c
177
(inst->range->flags & RANGE_HAS_IRQ)) {
drivers/soc/ti/knav_qmss_queue.c
180
(inst->range->flags & RANGE_HAS_ACCUMULATOR)) {
drivers/soc/ti/knav_qmss_queue.c
183
!(inst->range->flags &
drivers/soc/ti/knav_qmss_queue.c
193
struct knav_queue_inst *inst;
drivers/soc/ti/knav_qmss_queue.c
196
for_each_instance(idx, inst, kdev) {
drivers/soc/ti/knav_qmss_queue.c
197
if (inst->id == id)
drivers/soc/ti/knav_qmss_queue.c
198
return inst;
drivers/soc/ti/knav_qmss_queue.c
213
static struct knav_queue *__knav_queue_open(struct knav_queue_inst *inst,
drivers/soc/ti/knav_qmss_queue.c
220
qh = devm_kzalloc(inst->kdev->dev, sizeof(*qh), GFP_KERNEL);
drivers/soc/ti/knav_qmss_queue.c
231
qh->inst = inst;
drivers/soc/ti/knav_qmss_queue.c
232
id = inst->id - inst->qmgr->start_queue;
drivers/soc/ti/knav_qmss_queue.c
233
qh->reg_push = &inst->qmgr->reg_push[id];
drivers/soc/ti/knav_qmss_queue.c
234
qh->reg_pop = &inst->qmgr->reg_pop[id];
drivers/soc/ti/knav_qmss_queue.c
235
qh->reg_peek = &inst->qmgr->reg_peek[id];
drivers/soc/ti/knav_qmss_queue.c
238
if (!knav_queue_is_busy(inst)) {
drivers/soc/ti/knav_qmss_queue.c
239
struct knav_range_info *range = inst->range;
drivers/soc/ti/knav_qmss_queue.c
241
inst->name = kstrndup(name, KNAV_NAME_SIZE - 1, GFP_KERNEL);
drivers/soc/ti/knav_qmss_queue.c
243
ret = range->ops->open_queue(range, inst, flags);
drivers/soc/ti/knav_qmss_queue.c
248
list_add_tail_rcu(&qh->list, &inst->handles);
drivers/soc/ti/knav_qmss_queue.c
253
devm_kfree(inst->kdev->dev, qh);
drivers/soc/ti/knav_qmss_queue.c
260
struct knav_queue_inst *inst;
drivers/soc/ti/knav_qmss_queue.c
266
inst = knav_queue_find_by_id(id);
drivers/soc/ti/knav_qmss_queue.c
267
if (!inst)
drivers/soc/ti/knav_qmss_queue.c
271
if (!(flags & KNAV_QUEUE_SHARED) && knav_queue_is_busy(inst))
drivers/soc/ti/knav_qmss_queue.c
276
(knav_queue_is_busy(inst) && !knav_queue_is_shared(inst)))
drivers/soc/ti/knav_qmss_queue.c
279
qh = __knav_queue_open(inst, name, flags);
drivers/soc/ti/knav_qmss_queue.c
290
struct knav_queue_inst *inst;
drivers/soc/ti/knav_qmss_queue.c
296
for_each_instance(idx, inst, knav_qdev) {
drivers/soc/ti/knav_qmss_queue.c
297
if (knav_queue_is_reserved(inst))
drivers/soc/ti/knav_qmss_queue.c
299
if (!knav_queue_match_type(inst, type))
drivers/soc/ti/knav_qmss_queue.c
301
if (knav_queue_is_busy(inst))
drivers/soc/ti/knav_qmss_queue.c
303
qh = __knav_queue_open(inst, name, flags);
drivers/soc/ti/knav_qmss_queue.c
312
static void knav_queue_set_notify(struct knav_queue_inst *inst, bool enabled)
drivers/soc/ti/knav_qmss_queue.c
314
struct knav_range_info *range = inst->range;
drivers/soc/ti/knav_qmss_queue.c
317
range->ops->set_notify(range, inst, enabled);
drivers/soc/ti/knav_qmss_queue.c
322
struct knav_queue_inst *inst = qh->inst;
drivers/soc/ti/knav_qmss_queue.c
334
first = (atomic_inc_return(&inst->num_notifiers) == 1);
drivers/soc/ti/knav_qmss_queue.c
336
knav_queue_set_notify(inst, true);
drivers/soc/ti/knav_qmss_queue.c
343
struct knav_queue_inst *inst = qh->inst;
drivers/soc/ti/knav_qmss_queue.c
350
last = (atomic_dec_return(&inst->num_notifiers) == 0);
drivers/soc/ti/knav_qmss_queue.c
352
knav_queue_set_notify(inst, false);
drivers/soc/ti/knav_qmss_queue.c
365
if (!(qh->inst->range->flags & (RANGE_HAS_ACCUMULATOR | RANGE_HAS_IRQ)))
drivers/soc/ti/knav_qmss_queue.c
381
struct knav_queue_inst *inst,
drivers/soc/ti/knav_qmss_queue.c
387
queue = inst->id - range->queue_base;
drivers/soc/ti/knav_qmss_queue.c
397
struct knav_queue_inst *inst, unsigned flags)
drivers/soc/ti/knav_qmss_queue.c
399
return knav_queue_setup_irq(range, inst);
drivers/soc/ti/knav_qmss_queue.c
403
struct knav_queue_inst *inst)
drivers/soc/ti/knav_qmss_queue.c
405
knav_queue_free_irq(inst);
drivers/soc/ti/knav_qmss_queue.c
419
struct knav_queue_inst *inst = qh->inst;
drivers/soc/ti/knav_qmss_queue.c
422
atomic_read(&inst->desc_count);
drivers/soc/ti/knav_qmss_queue.c
426
struct knav_queue_inst *inst)
drivers/soc/ti/knav_qmss_queue.c
428
struct knav_device *kdev = inst->kdev;
drivers/soc/ti/knav_qmss_queue.c
437
if (!knav_queue_is_busy(inst))
drivers/soc/ti/knav_qmss_queue.c
441
kdev->base_id + inst->id, inst->name);
drivers/soc/ti/knav_qmss_queue.c
442
for_each_handle_rcu(qh, inst) {
drivers/soc/ti/knav_qmss_queue.c
464
struct knav_queue_inst *inst;
drivers/soc/ti/knav_qmss_queue.c
471
for_each_instance(idx, inst, knav_qdev)
drivers/soc/ti/knav_qmss_queue.c
472
knav_queue_debug_show_instance(s, inst);
drivers/soc/ti/knav_qmss_queue.c
501
struct knav_queue_inst *inst = qh->inst;
drivers/soc/ti/knav_qmss_queue.c
502
unsigned id = inst->id - inst->qmgr->start_queue;
drivers/soc/ti/knav_qmss_queue.c
504
atomic_set(&inst->desc_count, 0);
drivers/soc/ti/knav_qmss_queue.c
505
writel_relaxed(0, &inst->qmgr->reg_push[id].ptr_size_thresh);
drivers/soc/ti/knav_qmss_queue.c
550
struct knav_queue_inst *inst = qh->inst;
drivers/soc/ti/knav_qmss_queue.c
559
if (!knav_queue_is_busy(inst)) {
drivers/soc/ti/knav_qmss_queue.c
56
#define for_each_handle_rcu(qh, inst) \
drivers/soc/ti/knav_qmss_queue.c
560
struct knav_range_info *range = inst->range;
drivers/soc/ti/knav_qmss_queue.c
563
range->ops->close_queue(range, inst);
drivers/soc/ti/knav_qmss_queue.c
566
devm_kfree(inst->kdev->dev, qh);
drivers/soc/ti/knav_qmss_queue.c
57
list_for_each_entry_rcu(qh, &inst->handles, list, \
drivers/soc/ti/knav_qmss_queue.c
587
ret = qh->inst->kdev->base_id + qh->inst->id;
drivers/soc/ti/knav_qmss_queue.c
60
#define for_each_instance(idx, inst, kdev) \
drivers/soc/ti/knav_qmss_queue.c
61
for (idx = 0, inst = kdev->instances; \
drivers/soc/ti/knav_qmss_queue.c
63
idx++, inst = knav_queue_idx_to_inst(kdev, idx))
drivers/soc/ti/knav_qmss_queue.c
654
struct knav_queue_inst *inst = qh->inst;
drivers/soc/ti/knav_qmss_queue.c
659
if (inst->descs) {
drivers/soc/ti/knav_qmss_queue.c
660
if (unlikely(atomic_dec_return(&inst->desc_count) < 0)) {
drivers/soc/ti/knav_qmss_queue.c
661
atomic_inc(&inst->desc_count);
drivers/soc/ti/knav_qmss_queue.c
664
idx = atomic_inc_return(&inst->desc_head);
drivers/soc/ti/knav_qmss_queue.c
666
val = inst->descs[idx];
drivers/soc/ti/knav_qmss_queue.c
83
void knav_queue_notify(struct knav_queue_inst *inst)
drivers/soc/ti/knav_qmss_queue.c
87
if (!inst)
drivers/soc/ti/knav_qmss_queue.c
91
for_each_handle_rcu(qh, inst) {
drivers/spi/atmel-quadspi.c
140
#define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
drivers/spi/spi-axi-spi-engine.c
93
#define SPI_ENGINE_CMD(inst, arg1, arg2) \
drivers/spi/spi-axi-spi-engine.c
94
(((inst) << 12) | ((arg1) << 8) | (arg2))
drivers/spi/spi-pci1xxxx.c
947
u8 inst, bool store)
drivers/spi/spi-pci1xxxx.c
961
regval = readl(spi_ptr->reg_base + SPI_MST_CTL_REG_OFFSET(inst));
drivers/spi/spi-pci1xxxx.c
965
spi_ptr->reg_base + SPI_MST_CTL_REG_OFFSET(inst));
drivers/spi/spi-pci1xxxx.c
967
spi_ptr->reg_base + SPI_PCI_CTRL_REG_OFFSET(inst));
drivers/target/iscsi/iscsi_target_stat.c
150
CONFIGFS_ATTR_RO(iscsi_stat_instance_, inst);
drivers/target/iscsi/iscsi_target_stat.c
230
CONFIGFS_ATTR_RO(iscsi_stat_sess_err_, inst);
drivers/target/iscsi/iscsi_target_stat.c
363
CONFIGFS_ATTR_RO(iscsi_stat_tgt_attr_, inst);
drivers/target/iscsi/iscsi_target_stat.c
495
CONFIGFS_ATTR_RO(iscsi_stat_login_, inst);
drivers/target/iscsi/iscsi_target_stat.c
560
CONFIGFS_ATTR_RO(iscsi_stat_logout_, inst);
drivers/target/iscsi/iscsi_target_stat.c
772
CONFIGFS_ATTR_RO(iscsi_stat_sess_, inst);
drivers/target/target_core_stat.c
1088
CONFIGFS_ATTR_RO(target_stat_auth_, inst);
drivers/target/target_core_stat.c
1275
CONFIGFS_ATTR_RO(target_stat_iport_, inst);
drivers/target/target_core_stat.c
159
CONFIGFS_ATTR_RO(target_stat_tgt_, inst);
drivers/target/target_core_stat.c
346
CONFIGFS_ATTR_RO(target_stat_lu_, inst);
drivers/target/target_core_stat.c
498
CONFIGFS_ATTR_RO(target_stat_port_, inst);
drivers/target/target_core_stat.c
651
CONFIGFS_ATTR_RO(target_stat_tgt_port_, inst);
drivers/target/target_core_stat.c
70
CONFIGFS_ATTR_RO(target_stat_, inst);
drivers/target/target_core_stat.c
779
CONFIGFS_ATTR_RO(target_stat_transport_, inst);
drivers/tty/serial/sunsab.c
1017
static int inst;
drivers/tty/serial/sunsab.c
1021
up = &sunsab_ports[inst * 2];
drivers/tty/serial/sunsab.c
1025
(inst * 2) + 0);
drivers/tty/serial/sunsab.c
1031
(inst * 2) + 1);
drivers/tty/serial/sunsab.c
1053
inst++;
drivers/tty/serial/sunzilog.c
1399
int inst;
drivers/tty/serial/sunzilog.c
1410
inst = uart_chip_count + kbm_inst;
drivers/tty/serial/sunzilog.c
1412
inst = uart_inst;
drivers/tty/serial/sunzilog.c
1414
sunzilog_chip_regs[inst] = of_ioremap(&op->resource[0], 0,
drivers/tty/serial/sunzilog.c
1417
if (!sunzilog_chip_regs[inst])
drivers/tty/serial/sunzilog.c
1420
rp = sunzilog_chip_regs[inst];
drivers/tty/serial/sunzilog.c
1425
up = &sunzilog_port_table[inst * 2];
drivers/tty/serial/sunzilog.c
1437
up[0].port.line = (inst * 2) + 0;
drivers/tty/serial/sunzilog.c
1455
up[1].port.line = (inst * 2) + 1;
fs/ceph/debugfs.c
386
struct ceph_entity_inst *inst = &fsc->client->msgr.inst;
fs/ceph/debugfs.c
389
seq_printf(s, "instance: %s.%lld %s/%u\n", ENTITY_NAME(inst->name),
fs/ceph/snap.c
921
ret = ceph_monc_blocklist_add(&client->monc, &client->msgr.inst.addr);
fs/ceph/snap.c
924
ceph_pr_addr(&client->msgr.inst.addr), ret);
fs/ceph/snap.c
928
ret ? "" : ceph_pr_addr(&client->msgr.inst.addr),
include/crypto/algapi.h
148
struct crypto_instance *inst);
include/crypto/algapi.h
149
void crypto_unregister_instance(struct crypto_instance *inst);
include/crypto/algapi.h
151
int crypto_grab_spawn(struct crypto_spawn *spawn, struct crypto_instance *inst,
include/crypto/algapi.h
161
int __crypto_inst_setname(struct crypto_instance *inst, const char *name,
include/crypto/algapi.h
164
#define crypto_inst_setname(inst, name, ...) \
include/crypto/algapi.h
166
inst, name, ##__VA_ARGS__)
include/crypto/algapi.h
167
#define crypto_inst_setname_1(inst, name, alg) \
include/crypto/algapi.h
168
__crypto_inst_setname(inst, name, name, alg)
include/crypto/algapi.h
169
#define crypto_inst_setname_2(inst, name, driver, alg) \
include/crypto/algapi.h
170
__crypto_inst_setname(inst, name, driver, alg)
include/crypto/algapi.h
220
static inline void *crypto_instance_ctx(struct crypto_instance *inst)
include/crypto/algapi.h
222
return inst->__ctx;
include/crypto/algapi.h
92
struct crypto_instance *inst;
include/crypto/internal/aead.h
100
struct crypto_instance *inst,
include/crypto/internal/aead.h
165
struct aead_instance *inst);
include/crypto/internal/aead.h
19
void (*free)(struct aead_instance *inst);
include/crypto/internal/aead.h
48
struct aead_instance *inst)
include/crypto/internal/aead.h
50
return container_of(&inst->alg.base, struct crypto_instance, alg);
include/crypto/internal/aead.h
53
static inline struct aead_instance *aead_instance(struct crypto_instance *inst)
include/crypto/internal/aead.h
55
return container_of(&inst->alg, struct aead_instance, alg.base);
include/crypto/internal/aead.h
63
static inline void *aead_instance_ctx(struct aead_instance *inst)
include/crypto/internal/aead.h
65
return crypto_instance_ctx(aead_crypto_instance(inst));
include/crypto/internal/akcipher.h
100
return crypto_instance_ctx(akcipher_crypto_instance(inst));
include/crypto/internal/akcipher.h
104
struct crypto_instance *inst,
include/crypto/internal/akcipher.h
14
void (*free)(struct akcipher_instance *inst);
include/crypto/internal/akcipher.h
154
struct akcipher_instance *inst);
include/crypto/internal/akcipher.h
81
struct akcipher_instance *inst)
include/crypto/internal/akcipher.h
83
return container_of(&inst->alg.base, struct crypto_instance, alg);
include/crypto/internal/akcipher.h
87
struct crypto_instance *inst)
include/crypto/internal/akcipher.h
89
return container_of(&inst->alg, struct akcipher_instance, alg.base);
include/crypto/internal/akcipher.h
98
static inline void *akcipher_instance_ctx(struct akcipher_instance *inst)
include/crypto/internal/cipher.h
184
struct crypto_instance *inst,
include/crypto/internal/cipher.h
190
return crypto_grab_spawn(&spawn->base, inst, name, type, mask);
include/crypto/internal/hash.h
124
struct crypto_instance *inst,
include/crypto/internal/hash.h
143
struct shash_instance *inst);
include/crypto/internal/hash.h
144
void shash_free_singlespawn_instance(struct shash_instance *inst);
include/crypto/internal/hash.h
147
struct crypto_instance *inst,
include/crypto/internal/hash.h
214
struct ahash_instance *inst)
include/crypto/internal/hash.h
216
return &inst->s.base;
include/crypto/internal/hash.h
220
struct crypto_instance *inst)
include/crypto/internal/hash.h
222
return container_of(inst, struct ahash_instance, s.base);
include/crypto/internal/hash.h
231
static inline void *ahash_instance_ctx(struct ahash_instance *inst)
include/crypto/internal/hash.h
233
return crypto_instance_ctx(ahash_crypto_instance(inst));
include/crypto/internal/hash.h
280
struct shash_instance *inst)
include/crypto/internal/hash.h
282
return &inst->s.base;
include/crypto/internal/hash.h
286
struct crypto_instance *inst)
include/crypto/internal/hash.h
288
return container_of(inst, struct shash_instance, s.base);
include/crypto/internal/hash.h
297
static inline void *shash_instance_ctx(struct shash_instance *inst)
include/crypto/internal/hash.h
299
return crypto_instance_ctx(shash_crypto_instance(inst));
include/crypto/internal/hash.h
49
void (*free)(struct ahash_instance *inst);
include/crypto/internal/hash.h
60
void (*free)(struct shash_instance *inst);
include/crypto/internal/hash.h
92
struct ahash_instance *inst);
include/crypto/internal/hash.h
93
void ahash_free_singlespawn_instance(struct ahash_instance *inst);
include/crypto/internal/kpp.h
106
struct kpp_instance *inst)
include/crypto/internal/kpp.h
108
return &inst->s.base;
include/crypto/internal/kpp.h
117
static inline struct kpp_instance *kpp_instance(struct crypto_instance *inst)
include/crypto/internal/kpp.h
119
return container_of(inst, struct kpp_instance, s.base);
include/crypto/internal/kpp.h
144
static inline void *kpp_instance_ctx(struct kpp_instance *inst)
include/crypto/internal/kpp.h
146
return crypto_instance_ctx(kpp_crypto_instance(inst));
include/crypto/internal/kpp.h
182
struct kpp_instance *inst);
include/crypto/internal/kpp.h
197
struct crypto_instance *inst,
include/crypto/internal/kpp.h
21
void (*free)(struct kpp_instance *inst);
include/crypto/internal/sig.h
14
void (*free)(struct sig_instance *inst);
include/crypto/internal/sig.h
54
struct sig_instance *inst);
include/crypto/internal/sig.h
56
static inline struct sig_instance *sig_instance(struct crypto_instance *inst)
include/crypto/internal/sig.h
58
return container_of(&inst->alg, struct sig_instance, alg.base);
include/crypto/internal/sig.h
67
*inst)
include/crypto/internal/sig.h
69
return container_of(&inst->alg.base, struct crypto_instance, alg);
include/crypto/internal/sig.h
72
static inline void *sig_instance_ctx(struct sig_instance *inst)
include/crypto/internal/sig.h
74
return crypto_instance_ctx(sig_crypto_instance(inst));
include/crypto/internal/sig.h
78
struct crypto_instance *inst,
include/crypto/internal/skcipher.h
101
return &inst->s.base;
include/crypto/internal/skcipher.h
105
struct lskcipher_instance *inst)
include/crypto/internal/skcipher.h
107
return &inst->s.base;
include/crypto/internal/skcipher.h
124
static inline void *skcipher_instance_ctx(struct skcipher_instance *inst)
include/crypto/internal/skcipher.h
126
return crypto_instance_ctx(skcipher_crypto_instance(inst));
include/crypto/internal/skcipher.h
129
static inline void *lskcipher_instance_ctx(struct lskcipher_instance *inst)
include/crypto/internal/skcipher.h
131
return crypto_instance_ctx(lskcipher_crypto_instance(inst));
include/crypto/internal/skcipher.h
140
struct crypto_instance *inst,
include/crypto/internal/skcipher.h
144
struct crypto_instance *inst,
include/crypto/internal/skcipher.h
205
struct skcipher_instance *inst);
include/crypto/internal/skcipher.h
212
struct lskcipher_instance *inst);
include/crypto/internal/skcipher.h
28
void (*free)(struct skcipher_instance *inst);
include/crypto/internal/skcipher.h
288
struct skcipher_instance *inst)
include/crypto/internal/skcipher.h
290
struct crypto_cipher_spawn *spawn = skcipher_instance_ctx(inst);
include/crypto/internal/skcipher.h
307
struct lskcipher_instance *inst)
include/crypto/internal/skcipher.h
309
struct crypto_lskcipher_spawn *spawn = lskcipher_instance_ctx(inst);
include/crypto/internal/skcipher.h
39
void (*free)(struct lskcipher_instance *inst);
include/crypto/internal/skcipher.h
99
struct skcipher_instance *inst)
include/linux/arm-smccc.h
626
#define __arm_smccc_1_1(inst, ...) \
include/linux/arm-smccc.h
634
asm volatile(inst "\n" : \
include/linux/ceph/messenger.h
105
struct ceph_entity_inst inst; /* my name+address */
include/linux/mcb.h
68
int inst;
include/linux/usb/composite.h
576
struct usb_function *(*alloc_func)(struct usb_function_instance *inst);
include/linux/usb/composite.h
583
int (*set_inst_name)(struct usb_function_instance *inst,
include/linux/usb/composite.h
585
void (*free_func_inst)(struct usb_function_instance *inst);
include/sound/opl3.h
256
struct fm_instrument inst;
include/uapi/linux/kcov.h
56
static inline __u64 kcov_remote_handle(__u64 subsys, __u64 inst)
include/uapi/linux/kcov.h
58
if (subsys & ~KCOV_SUBSYSTEM_MASK || inst & ~KCOV_INSTANCE_MASK)
include/uapi/linux/kcov.h
60
return subsys | inst;
kernel/trace/trace_osnoise.c
114
struct osnoise_instance *inst;
kernel/trace/trace_osnoise.c
118
list_for_each_entry_rcu(inst, &osnoise_instances, list) {
kernel/trace/trace_osnoise.c
119
if (inst->tr == tr)
kernel/trace/trace_osnoise.c
1197
struct osnoise_instance *inst;
kernel/trace/trace_osnoise.c
1201
list_for_each_entry_rcu(inst, &osnoise_instances, list) {
kernel/trace/trace_osnoise.c
1202
tr = inst->tr;
kernel/trace/trace_osnoise.c
135
struct osnoise_instance *inst;
kernel/trace/trace_osnoise.c
1370
struct osnoise_instance *inst;
kernel/trace/trace_osnoise.c
1374
list_for_each_entry_rcu(inst, &osnoise_instances, list) {
kernel/trace/trace_osnoise.c
1375
tr = inst->tr;
kernel/trace/trace_osnoise.c
1392
struct osnoise_instance *inst;
kernel/trace/trace_osnoise.c
1396
list_for_each_entry_rcu(inst, &osnoise_instances, list)
kernel/trace/trace_osnoise.c
1397
trace_is_on += tracer_tracing_is_on(inst->tr);
kernel/trace/trace_osnoise.c
1408
struct osnoise_instance *inst;
kernel/trace/trace_osnoise.c
1412
list_for_each_entry_rcu(inst, &osnoise_instances, list) {
kernel/trace/trace_osnoise.c
1413
tr = inst->tr;
kernel/trace/trace_osnoise.c
144
inst = kmalloc_obj(*inst);
kernel/trace/trace_osnoise.c
145
if (!inst)
kernel/trace/trace_osnoise.c
148
INIT_LIST_HEAD_RCU(&inst->list);
kernel/trace/trace_osnoise.c
149
inst->tr = tr;
kernel/trace/trace_osnoise.c
150
list_add_tail_rcu(&inst->list, &osnoise_instances);
kernel/trace/trace_osnoise.c
163
struct osnoise_instance *inst;
kernel/trace/trace_osnoise.c
170
list_for_each_entry_rcu(inst, &osnoise_instances, list,
kernel/trace/trace_osnoise.c
172
if (inst->tr == tr) {
kernel/trace/trace_osnoise.c
173
list_del_rcu(&inst->list);
kernel/trace/trace_osnoise.c
184
kvfree(inst);
kernel/trace/trace_osnoise.c
528
struct osnoise_instance *inst;
kernel/trace/trace_osnoise.c
534
list_for_each_entry_rcu(inst, &osnoise_instances, list) {
kernel/trace/trace_osnoise.c
535
buffer = inst->tr->array_buffer.buffer;
kernel/trace/trace_osnoise.c
602
struct osnoise_instance *inst;
kernel/trace/trace_osnoise.c
608
list_for_each_entry_rcu(inst, &osnoise_instances, list) {
kernel/trace/trace_osnoise.c
609
buffer = inst->tr->array_buffer.buffer;
kernel/trace/trace_osnoise.c
679
struct osnoise_instance *inst;
kernel/trace/trace_osnoise.c
695
list_for_each_entry_rcu(inst, &osnoise_instances, list) {
kernel/trace/trace_osnoise.c
696
buffer = inst->tr->array_buffer.buffer;
kernel/trace/trace_osnoise.c
88
struct osnoise_instance *inst;
kernel/trace/trace_osnoise.c
93
list_for_each_entry_rcu(inst, &osnoise_instances, list) {
kernel/trace/trace_osnoise.c
94
tr = inst->tr;
net/bridge/br_mrp_netlink.c
35
struct br_mrp_instance inst;
net/bridge/br_mrp_netlink.c
51
memset(&inst, 0, sizeof(inst));
net/bridge/br_mrp_netlink.c
53
inst.ring_id = nla_get_u32(tb[IFLA_BRIDGE_MRP_INSTANCE_RING_ID]);
net/bridge/br_mrp_netlink.c
54
inst.p_ifindex = nla_get_u32(tb[IFLA_BRIDGE_MRP_INSTANCE_P_IFINDEX]);
net/bridge/br_mrp_netlink.c
55
inst.s_ifindex = nla_get_u32(tb[IFLA_BRIDGE_MRP_INSTANCE_S_IFINDEX]);
net/bridge/br_mrp_netlink.c
56
inst.prio = MRP_DEFAULT_PRIO;
net/bridge/br_mrp_netlink.c
59
inst.prio = nla_get_u16(tb[IFLA_BRIDGE_MRP_INSTANCE_PRIO]);
net/bridge/br_mrp_netlink.c
62
return br_mrp_add(br, &inst);
net/bridge/br_mrp_netlink.c
64
return br_mrp_del(br, &inst);
net/ceph/ceph_common.c
693
return &client->msgr.inst.addr;
net/ceph/debugfs.c
45
struct ceph_entity_inst *inst =
net/ceph/debugfs.c
49
ENTITY_NAME(inst->name),
net/ceph/debugfs.c
50
ceph_pr_addr(&inst->addr));
net/ceph/messenger.c
1662
u32 nonce = le32_to_cpu(msgr->inst.addr.nonce) + 1000000;
net/ceph/messenger.c
1663
msgr->inst.addr.nonce = cpu_to_le32(nonce);
net/ceph/messenger.c
1676
memcpy(&msgr->inst.addr.in_addr, &myaddr->in_addr,
net/ceph/messenger.c
1677
sizeof(msgr->inst.addr.in_addr));
net/ceph/messenger.c
1678
ceph_addr_set_port(&msgr->inst.addr, 0);
net/ceph/messenger.c
1685
msgr->inst.addr.type = CEPH_ENTITY_ADDR_TYPE_ANY;
net/ceph/messenger.c
1689
get_random_bytes(&msgr->inst.addr.nonce,
net/ceph/messenger.c
1690
sizeof(msgr->inst.addr.nonce));
net/ceph/messenger.c
1691
} while (!msgr->inst.addr.nonce);
net/ceph/messenger.c
1735
msg->hdr.src = con->msgr->inst.name;
net/ceph/messenger.c
200
memcpy(&msgr->my_enc_addr, &msgr->inst.addr,
net/ceph/messenger_v1.c
699
struct ceph_entity_addr *my_addr = &con->msgr->inst.addr;
net/ceph/messenger_v2.c
1448
struct ceph_entity_addr *my_addr = &con->msgr->inst.addr;
net/ceph/messenger_v2.c
1500
struct ceph_entity_addr *my_addr = &con->msgr->inst.addr;
net/ceph/messenger_v2.c
2195
struct ceph_entity_addr *my_addr = &con->msgr->inst.addr;
net/ceph/mon_client.c
1151
struct ceph_entity_inst *inst = &monc->monmap->mon_inst[i];
net/ceph/mon_client.c
1153
memcpy(&inst->addr.in_addr, &opt->mon_addr[i].in_addr,
net/ceph/mon_client.c
1154
sizeof(inst->addr.in_addr));
net/ceph/mon_client.c
1155
inst->addr.type = my_type;
net/ceph/mon_client.c
1156
inst->addr.nonce = 0;
net/ceph/mon_client.c
1157
inst->name.type = CEPH_ENTITY_TYPE_MON;
net/ceph/mon_client.c
1158
inst->name.num = cpu_to_le64(i);
net/ceph/mon_client.c
1302
monc->client->msgr.inst.name.type = CEPH_ENTITY_TYPE_CLIENT;
net/ceph/mon_client.c
1303
monc->client->msgr.inst.name.num =
net/ceph/mon_client.c
131
struct ceph_entity_inst *inst = &monmap->mon_inst[i];
net/ceph/mon_client.c
134
inst->name.type = CEPH_ENTITY_TYPE_MON;
net/ceph/mon_client.c
135
inst->name.num = cpu_to_le64(i);
net/ceph/mon_client.c
138
ret = decode_mon_info(p, end, msgr2, &inst->addr);
net/ceph/mon_client.c
140
ret = ceph_decode_entity_addr(p, end, &inst->addr);
net/ceph/mon_client.c
145
ceph_pr_addr(&inst->addr));
net/netfilter/ipset/ip_set_core.c
1000
for (i = 0; i < inst->ip_set_max; i++) {
net/netfilter/ipset/ip_set_core.c
1001
set = ip_set(inst, i);
net/netfilter/ipset/ip_set_core.c
1011
find_set(struct ip_set_net *inst, const char *name)
net/netfilter/ipset/ip_set_core.c
1015
return find_set_and_id(inst, name, &id);
net/netfilter/ipset/ip_set_core.c
1019
find_free_id(struct ip_set_net *inst, const char *name, ip_set_id_t *index,
net/netfilter/ipset/ip_set_core.c
1026
for (i = 0; i < inst->ip_set_max; i++) {
net/netfilter/ipset/ip_set_core.c
1027
s = ip_set(inst, i);
net/netfilter/ipset/ip_set_core.c
1052
struct ip_set_net *inst = ip_set_pernet(info->net);
net/netfilter/ipset/ip_set_core.c
1119
ret = find_free_id(inst, set->name, &index, &clash);
net/netfilter/ipset/ip_set_core.c
1132
ip_set_id_t i = inst->ip_set_max + IP_SET_INC;
net/netfilter/ipset/ip_set_core.c
1134
if (i < inst->ip_set_max || i == IPSET_INVALID_ID)
net/netfilter/ipset/ip_set_core.c
1142
tmp = ip_set_dereference(inst);
net/netfilter/ipset/ip_set_core.c
1143
memcpy(list, tmp, sizeof(struct ip_set *) * inst->ip_set_max);
net/netfilter/ipset/ip_set_core.c
1144
rcu_assign_pointer(inst->ip_set_list, list);
net/netfilter/ipset/ip_set_core.c
1148
index = inst->ip_set_max;
net/netfilter/ipset/ip_set_core.c
1149
inst->ip_set_max = i;
net/netfilter/ipset/ip_set_core.c
1158
ip_set(inst, index) = set;
net/netfilter/ipset/ip_set_core.c
1198
_destroy_all_sets(struct ip_set_net *inst)
net/netfilter/ipset/ip_set_core.c
1205
for (i = 0; i < inst->ip_set_max; i++) {
net/netfilter/ipset/ip_set_core.c
1206
set = ip_set(inst, i);
net/netfilter/ipset/ip_set_core.c
1216
for (i = 0; i < inst->ip_set_max; i++) {
net/netfilter/ipset/ip_set_core.c
1217
set = ip_set(inst, i);
net/netfilter/ipset/ip_set_core.c
1219
ip_set(inst, i) = NULL;
net/netfilter/ipset/ip_set_core.c
1230
struct ip_set_net *inst = ip_set_pernet(info->net);
net/netfilter/ipset/ip_set_core.c
1250
for (i = 0; i < inst->ip_set_max; i++) {
net/netfilter/ipset/ip_set_core.c
1251
s = ip_set(inst, i);
net/netfilter/ipset/ip_set_core.c
1257
inst->is_destroyed = true;
net/netfilter/ipset/ip_set_core.c
1259
_destroy_all_sets(inst);
net/netfilter/ipset/ip_set_core.c
1261
inst->is_destroyed = false;
net/netfilter/ipset/ip_set_core.c
1267
s = find_set_and_id(inst, nla_data(attr[IPSET_ATTR_SETNAME]),
net/netfilter/ipset/ip_set_core.c
1278
ip_set(inst, i) = NULL;
net/netfilter/ipset/ip_set_core.c
1309
struct ip_set_net *inst = ip_set_pernet(info->net);
net/netfilter/ipset/ip_set_core.c
1317
for (i = 0; i < inst->ip_set_max; i++) {
net/netfilter/ipset/ip_set_core.c
1318
s = ip_set(inst, i);
net/netfilter/ipset/ip_set_core.c
1323
s = find_set(inst, nla_data(attr[IPSET_ATTR_SETNAME]));
net/netfilter/ipset/ip_set_core.c
1347
struct ip_set_net *inst = ip_set_pernet(info->net);
net/netfilter/ipset/ip_set_core.c
1358
set = find_set(inst, nla_data(attr[IPSET_ATTR_SETNAME]));
net/netfilter/ipset/ip_set_core.c
1369
for (i = 0; i < inst->ip_set_max; i++) {
net/netfilter/ipset/ip_set_core.c
1370
s = ip_set(inst, i);
net/netfilter/ipset/ip_set_core.c
1395
struct ip_set_net *inst = ip_set_pernet(info->net);
net/netfilter/ipset/ip_set_core.c
1405
from = find_set_and_id(inst, nla_data(attr[IPSET_ATTR_SETNAME]),
net/netfilter/ipset/ip_set_core.c
1410
to = find_set_and_id(inst, nla_data(attr[IPSET_ATTR_SETNAME2]),
net/netfilter/ipset/ip_set_core.c
1435
ip_set(inst, from_id) = to;
net/netfilter/ipset/ip_set_core.c
1436
ip_set(inst, to_id) = from;
net/netfilter/ipset/ip_set_core.c
1480
struct ip_set_net *inst =
net/netfilter/ipset/ip_set_core.c
1486
set = ip_set_ref_netlink(inst, index);
net/netfilter/ipset/ip_set_core.c
1525
struct ip_set_net *inst = ip_set_pernet(sock_net(skb->sk));
net/netfilter/ipset/ip_set_core.c
1540
set = find_set_and_id(inst, nla_data(cda[IPSET_ATTR_SETNAME]),
net/netfilter/ipset/ip_set_core.c
1557
cb->args[IPSET_CB_NET] = (unsigned long)inst;
net/netfilter/ipset/ip_set_core.c
1577
struct ip_set_net *inst = ip_set_pernet(sock_net(skb->sk));
net/netfilter/ipset/ip_set_core.c
1585
if (cb->args[IPSET_CB_INDEX] >= inst->ip_set_max)
net/netfilter/ipset/ip_set_core.c
1591
: inst->ip_set_max;
net/netfilter/ipset/ip_set_core.c
1598
set = ip_set(inst, index);
net/netfilter/ipset/ip_set_core.c
1599
is_destroyed = inst->is_destroyed;
net/netfilter/ipset/ip_set_core.c
1694
set = ip_set_ref_netlink(inst, index);
net/netfilter/ipset/ip_set_core.c
1819
struct ip_set_net *inst = ip_set_pernet(net);
net/netfilter/ipset/ip_set_core.c
1838
set = find_set(inst, nla_data(attr[IPSET_ATTR_SETNAME]));
net/netfilter/ipset/ip_set_core.c
1885
struct ip_set_net *inst = ip_set_pernet(info->net);
net/netfilter/ipset/ip_set_core.c
1897
set = find_set(inst, nla_data(attr[IPSET_ATTR_SETNAME]));
net/netfilter/ipset/ip_set_core.c
1920
struct ip_set_net *inst = ip_set_pernet(info->net);
net/netfilter/ipset/ip_set_core.c
1929
set = find_set(inst, nla_data(attr[IPSET_ATTR_SETNAME]));
net/netfilter/ipset/ip_set_core.c
2057
struct ip_set_net *inst = ip_set_pernet(info->net);
net/netfilter/ipset/ip_set_core.c
2067
set = find_set_and_id(inst, nla_data(attr[IPSET_ATTR_SETNAME]), &id);
net/netfilter/ipset/ip_set_core.c
2102
struct ip_set_net *inst = ip_set_pernet(info->net);
net/netfilter/ipset/ip_set_core.c
2113
if (id >= inst->ip_set_max)
net/netfilter/ipset/ip_set_core.c
2115
set = ip_set(inst, id);
net/netfilter/ipset/ip_set_core.c
2255
struct ip_set_net *inst = ip_set_pernet(net);
net/netfilter/ipset/ip_set_core.c
2313
find_set_and_id(inst, req_get->set.name, &id);
net/netfilter/ipset/ip_set_core.c
2328
find_set_and_id(inst, req_get->set.name, &id);
net/netfilter/ipset/ip_set_core.c
2331
req_get->family = ip_set(inst, id)->family;
net/netfilter/ipset/ip_set_core.c
2340
req_get->set.index >= inst->ip_set_max) {
net/netfilter/ipset/ip_set_core.c
2345
set = ip_set(inst, req_get->set.index);
net/netfilter/ipset/ip_set_core.c
2380
struct ip_set_net *inst = ip_set_pernet(net);
net/netfilter/ipset/ip_set_core.c
2383
inst->ip_set_max = max_sets ? max_sets : CONFIG_IP_SET_MAX;
net/netfilter/ipset/ip_set_core.c
2384
if (inst->ip_set_max >= IPSET_INVALID_ID)
net/netfilter/ipset/ip_set_core.c
2385
inst->ip_set_max = IPSET_INVALID_ID - 1;
net/netfilter/ipset/ip_set_core.c
2387
list = kvzalloc_objs(struct ip_set *, inst->ip_set_max);
net/netfilter/ipset/ip_set_core.c
2390
inst->is_deleted = false;
net/netfilter/ipset/ip_set_core.c
2391
inst->is_destroyed = false;
net/netfilter/ipset/ip_set_core.c
2392
rcu_assign_pointer(inst->ip_set_list, list);
net/netfilter/ipset/ip_set_core.c
2399
struct ip_set_net *inst = ip_set_pernet(net);
net/netfilter/ipset/ip_set_core.c
2401
inst->is_deleted = true; /* flag for ip_set_nfnl_put */
net/netfilter/ipset/ip_set_core.c
2407
struct ip_set_net *inst = ip_set_pernet(net);
net/netfilter/ipset/ip_set_core.c
2409
_destroy_all_sets(inst);
net/netfilter/ipset/ip_set_core.c
2410
kvfree(rcu_dereference_protected(inst->ip_set_list, 1));
net/netfilter/ipset/ip_set_core.c
56
#define ip_set_dereference(inst) \
net/netfilter/ipset/ip_set_core.c
57
rcu_dereference_protected((inst)->ip_set_list, \
net/netfilter/ipset/ip_set_core.c
60
(inst)->is_deleted)
net/netfilter/ipset/ip_set_core.c
61
#define ip_set(inst, id) \
net/netfilter/ipset/ip_set_core.c
62
ip_set_dereference(inst)[id]
net/netfilter/ipset/ip_set_core.c
63
#define ip_set_ref_netlink(inst,id) \
net/netfilter/ipset/ip_set_core.c
64
rcu_dereference_raw((inst)->ip_set_list)[id]
net/netfilter/ipset/ip_set_core.c
719
struct ip_set_net *inst = ip_set_pernet(net);
net/netfilter/ipset/ip_set_core.c
722
return ip_set_dereference_nfnl(inst->ip_set_list)[index];
net/netfilter/ipset/ip_set_core.c
828
struct ip_set_net *inst = ip_set_pernet(net);
net/netfilter/ipset/ip_set_core.c
831
for (i = 0; i < inst->ip_set_max; i++) {
net/netfilter/ipset/ip_set_core.c
832
s = rcu_dereference(inst->ip_set_list)[i];
net/netfilter/ipset/ip_set_core.c
853
__ip_set_put_byindex(struct ip_set_net *inst, ip_set_id_t index)
net/netfilter/ipset/ip_set_core.c
858
set = rcu_dereference(inst->ip_set_list)[index];
net/netfilter/ipset/ip_set_core.c
867
struct ip_set_net *inst = ip_set_pernet(net);
net/netfilter/ipset/ip_set_core.c
869
__ip_set_put_byindex(inst, index);
net/netfilter/ipset/ip_set_core.c
904
struct ip_set_net *inst = ip_set_pernet(net);
net/netfilter/ipset/ip_set_core.c
906
if (index >= inst->ip_set_max)
net/netfilter/ipset/ip_set_core.c
910
set = ip_set(inst, index);
net/netfilter/ipset/ip_set_core.c
931
struct ip_set_net *inst = ip_set_pernet(net);
net/netfilter/ipset/ip_set_core.c
934
if (!inst->is_deleted) { /* already deleted from ip_set_net_exit() */
net/netfilter/ipset/ip_set_core.c
935
set = ip_set(inst, index);
net/netfilter/ipset/ip_set_core.c
994
find_set_and_id(struct ip_set_net *inst, const char *name, ip_set_id_t *id)
net/netfilter/nfnetlink_log.c
1000
nfulnl_set_mode(inst, params->copy_mode,
net/netfilter/nfnetlink_log.c
1007
nfulnl_set_timeout(inst, ntohl(timeout));
net/netfilter/nfnetlink_log.c
1013
nfulnl_set_nlbufsiz(inst, ntohl(nlbufsiz));
net/netfilter/nfnetlink_log.c
1019
nfulnl_set_qthresh(inst, ntohl(qthresh));
net/netfilter/nfnetlink_log.c
1023
nfulnl_set_flags(inst, flags);
net/netfilter/nfnetlink_log.c
1026
instance_put(inst);
net/netfilter/nfnetlink_log.c
109
struct nfulnl_instance *inst;
net/netfilter/nfnetlink_log.c
112
hlist_for_each_entry_rcu(inst, head, hlist) {
net/netfilter/nfnetlink_log.c
1126
const struct nfulnl_instance *inst = v;
net/netfilter/nfnetlink_log.c
1129
inst->group_num,
net/netfilter/nfnetlink_log.c
113
if (inst->group_num == group_num)
net/netfilter/nfnetlink_log.c
1130
inst->peer_portid, inst->qlen,
net/netfilter/nfnetlink_log.c
1131
inst->copy_mode, inst->copy_range,
net/netfilter/nfnetlink_log.c
1132
inst->flushtimeout, refcount_read(&inst->use));
net/netfilter/nfnetlink_log.c
114
return inst;
net/netfilter/nfnetlink_log.c
120
instance_get(struct nfulnl_instance *inst)
net/netfilter/nfnetlink_log.c
122
refcount_inc(&inst->use);
net/netfilter/nfnetlink_log.c
128
struct nfulnl_instance *inst;
net/netfilter/nfnetlink_log.c
130
inst = __instance_lookup(log, group_num);
net/netfilter/nfnetlink_log.c
131
if (inst && !refcount_inc_not_zero(&inst->use))
net/netfilter/nfnetlink_log.c
132
inst = NULL;
net/netfilter/nfnetlink_log.c
134
return inst;
net/netfilter/nfnetlink_log.c
140
struct nfulnl_instance *inst;
net/netfilter/nfnetlink_log.c
143
inst = instance_lookup_get_rcu(log, group_num);
net/netfilter/nfnetlink_log.c
146
return inst;
net/netfilter/nfnetlink_log.c
151
struct nfulnl_instance *inst =
net/netfilter/nfnetlink_log.c
154
put_net_track(inst->net, &inst->ns_tracker);
net/netfilter/nfnetlink_log.c
155
kfree(inst);
net/netfilter/nfnetlink_log.c
160
instance_put(struct nfulnl_instance *inst)
net/netfilter/nfnetlink_log.c
162
if (inst && refcount_dec_and_test(&inst->use))
net/netfilter/nfnetlink_log.c
163
call_rcu(&inst->rcu, nfulnl_instance_free_rcu);
net/netfilter/nfnetlink_log.c
172
struct nfulnl_instance *inst;
net/netfilter/nfnetlink_log.c
182
inst = kzalloc_obj(*inst, GFP_ATOMIC);
net/netfilter/nfnetlink_log.c
183
if (!inst) {
net/netfilter/nfnetlink_log.c
189
kfree(inst);
net/netfilter/nfnetlink_log.c
194
INIT_HLIST_NODE(&inst->hlist);
net/netfilter/nfnetlink_log.c
195
spin_lock_init(&inst->lock);
net/netfilter/nfnetlink_log.c
197
refcount_set(&inst->use, 2);
net/netfilter/nfnetlink_log.c
199
timer_setup(&inst->timer, nfulnl_timer, 0);
net/netfilter/nfnetlink_log.c
201
inst->net = get_net_track(net, &inst->ns_tracker, GFP_ATOMIC);
net/netfilter/nfnetlink_log.c
202
inst->peer_user_ns = user_ns;
net/netfilter/nfnetlink_log.c
203
inst->peer_portid = portid;
net/netfilter/nfnetlink_log.c
204
inst->group_num = group_num;
net/netfilter/nfnetlink_log.c
206
inst->qthreshold = NFULNL_QTHRESH_DEFAULT;
net/netfilter/nfnetlink_log.c
207
inst->flushtimeout = NFULNL_TIMEOUT_DEFAULT;
net/netfilter/nfnetlink_log.c
208
inst->nlbufsiz = NFULNL_NLBUFSIZ_DEFAULT;
net/netfilter/nfnetlink_log.c
209
inst->copy_mode = NFULNL_COPY_PACKET;
net/netfilter/nfnetlink_log.c
210
inst->copy_range = NFULNL_COPY_RANGE_MAX;
net/netfilter/nfnetlink_log.c
212
hlist_add_head_rcu(&inst->hlist,
net/netfilter/nfnetlink_log.c
218
return inst;
net/netfilter/nfnetlink_log.c
225
static void __nfulnl_flush(struct nfulnl_instance *inst);
net/netfilter/nfnetlink_log.c
229
__instance_destroy(struct nfulnl_instance *inst)
net/netfilter/nfnetlink_log.c
232
hlist_del_rcu(&inst->hlist);
net/netfilter/nfnetlink_log.c
236
spin_lock(&inst->lock);
net/netfilter/nfnetlink_log.c
239
inst->copy_mode = NFULNL_COPY_DISABLED;
net/netfilter/nfnetlink_log.c
241
if (inst->skb)
net/netfilter/nfnetlink_log.c
242
__nfulnl_flush(inst);
net/netfilter/nfnetlink_log.c
243
spin_unlock(&inst->lock);
net/netfilter/nfnetlink_log.c
246
instance_put(inst);
net/netfilter/nfnetlink_log.c
251
struct nfulnl_instance *inst)
net/netfilter/nfnetlink_log.c
254
__instance_destroy(inst);
net/netfilter/nfnetlink_log.c
259
nfulnl_set_mode(struct nfulnl_instance *inst, u_int8_t mode,
net/netfilter/nfnetlink_log.c
264
spin_lock_bh(&inst->lock);
net/netfilter/nfnetlink_log.c
269
inst->copy_mode = mode;
net/netfilter/nfnetlink_log.c
270
inst->copy_range = 0;
net/netfilter/nfnetlink_log.c
274
inst->copy_mode = mode;
net/netfilter/nfnetlink_log.c
277
inst->copy_range = min_t(unsigned int,
net/netfilter/nfnetlink_log.c
286
spin_unlock_bh(&inst->lock);
net/netfilter/nfnetlink_log.c
292
nfulnl_set_nlbufsiz(struct nfulnl_instance *inst, u_int32_t nlbufsiz)
net/netfilter/nfnetlink_log.c
296
spin_lock_bh(&inst->lock);
net/netfilter/nfnetlink_log.c
302
inst->nlbufsiz = nlbufsiz;
net/netfilter/nfnetlink_log.c
305
spin_unlock_bh(&inst->lock);
net/netfilter/nfnetlink_log.c
311
nfulnl_set_timeout(struct nfulnl_instance *inst, u_int32_t timeout)
net/netfilter/nfnetlink_log.c
313
spin_lock_bh(&inst->lock);
net/netfilter/nfnetlink_log.c
314
inst->flushtimeout = timeout;
net/netfilter/nfnetlink_log.c
315
spin_unlock_bh(&inst->lock);
net/netfilter/nfnetlink_log.c
319
nfulnl_set_qthresh(struct nfulnl_instance *inst, u_int32_t qthresh)
net/netfilter/nfnetlink_log.c
321
spin_lock_bh(&inst->lock);
net/netfilter/nfnetlink_log.c
322
inst->qthreshold = qthresh;
net/netfilter/nfnetlink_log.c
323
spin_unlock_bh(&inst->lock);
net/netfilter/nfnetlink_log.c
327
nfulnl_set_flags(struct nfulnl_instance *inst, u_int16_t flags)
net/netfilter/nfnetlink_log.c
329
spin_lock_bh(&inst->lock);
net/netfilter/nfnetlink_log.c
330
inst->flags = flags;
net/netfilter/nfnetlink_log.c
331
spin_unlock_bh(&inst->lock);
net/netfilter/nfnetlink_log.c
361
__nfulnl_send(struct nfulnl_instance *inst)
net/netfilter/nfnetlink_log.c
363
if (inst->qlen > 1) {
net/netfilter/nfnetlink_log.c
364
struct nlmsghdr *nlh = nfnl_msg_put(inst->skb, 0, 0,
net/netfilter/nfnetlink_log.c
367
htons(inst->group_num));
net/netfilter/nfnetlink_log.c
369
inst->skb->len, skb_tailroom(inst->skb))) {
net/netfilter/nfnetlink_log.c
370
kfree_skb(inst->skb);
net/netfilter/nfnetlink_log.c
374
nfnetlink_unicast(inst->skb, inst->net, inst->peer_portid);
net/netfilter/nfnetlink_log.c
376
inst->qlen = 0;
net/netfilter/nfnetlink_log.c
377
inst->skb = NULL;
net/netfilter/nfnetlink_log.c
381
__nfulnl_flush(struct nfulnl_instance *inst)
net/netfilter/nfnetlink_log.c
384
if (timer_delete(&inst->timer))
net/netfilter/nfnetlink_log.c
385
instance_put(inst);
net/netfilter/nfnetlink_log.c
386
if (inst->skb)
net/netfilter/nfnetlink_log.c
387
__nfulnl_send(inst);
net/netfilter/nfnetlink_log.c
393
struct nfulnl_instance *inst = timer_container_of(inst, t, timer);
net/netfilter/nfnetlink_log.c
395
spin_lock_bh(&inst->lock);
net/netfilter/nfnetlink_log.c
396
if (inst->skb)
net/netfilter/nfnetlink_log.c
397
__nfulnl_send(inst);
net/netfilter/nfnetlink_log.c
398
spin_unlock_bh(&inst->lock);
net/netfilter/nfnetlink_log.c
399
instance_put(inst);
net/netfilter/nfnetlink_log.c
422
static int nfulnl_put_bridge(struct nfulnl_instance *inst, const struct sk_buff *skb)
net/netfilter/nfnetlink_log.c
432
nest = nla_nest_start(inst->skb, NFULA_VLAN);
net/netfilter/nfnetlink_log.c
436
if (nla_put_be16(inst->skb, NFULA_VLAN_TCI, htons(skb->vlan_tci)) ||
net/netfilter/nfnetlink_log.c
437
nla_put_be16(inst->skb, NFULA_VLAN_PROTO, skb->vlan_proto))
net/netfilter/nfnetlink_log.c
440
nla_nest_end(inst->skb, nest);
net/netfilter/nfnetlink_log.c
445
nla_put(inst->skb, NFULA_L2HDR, mac_len, skb_mac_header(skb)))
net/netfilter/nfnetlink_log.c
475
struct nfulnl_instance *inst,
net/netfilter/nfnetlink_log.c
488
sk_buff_data_t old_tail = inst->skb->tail;
net/netfilter/nfnetlink_log.c
492
nlh = nfnl_msg_put(inst->skb, 0, 0,
net/netfilter/nfnetlink_log.c
494
0, pf, NFNETLINK_V0, htons(inst->group_num));
net/netfilter/nfnetlink_log.c
502
if (nla_put(inst->skb, NFULA_PACKET_HDR, sizeof(pmsg), &pmsg))
net/netfilter/nfnetlink_log.c
506
nla_put(inst->skb, NFULA_PREFIX, plen, prefix))
net/netfilter/nfnetlink_log.c
511
if (nla_put_be32(inst->skb, NFULA_IFINDEX_INDEV,
net/netfilter/nfnetlink_log.c
519
if (nla_put_be32(inst->skb, NFULA_IFINDEX_PHYSINDEV,
net/netfilter/nfnetlink_log.c
525
nflog_put_master_ifindex(inst->skb, NFULA_IFINDEX_INDEV, indev))
net/netfilter/nfnetlink_log.c
532
if (nla_put_be32(inst->skb, NFULA_IFINDEX_INDEV,
net/netfilter/nfnetlink_log.c
538
nla_put_be32(inst->skb, NFULA_IFINDEX_PHYSINDEV,
net/netfilter/nfnetlink_log.c
547
if (nla_put_be32(inst->skb, NFULA_IFINDEX_OUTDEV,
net/netfilter/nfnetlink_log.c
555
if (nla_put_be32(inst->skb, NFULA_IFINDEX_PHYSOUTDEV,
net/netfilter/nfnetlink_log.c
561
nflog_put_master_ifindex(inst->skb, NFULA_IFINDEX_OUTDEV, outdev))
net/netfilter/nfnetlink_log.c
568
if (nla_put_be32(inst->skb, NFULA_IFINDEX_OUTDEV,
net/netfilter/nfnetlink_log.c
574
nla_put_be32(inst->skb, NFULA_IFINDEX_PHYSOUTDEV,
net/netfilter/nfnetlink_log.c
582
nla_put_be32(inst->skb, NFULA_MARK, htonl(skb->mark)))
net/netfilter/nfnetlink_log.c
595
if (nla_put(inst->skb, NFULA_HWADDR, sizeof(phw), &phw))
net/netfilter/nfnetlink_log.c
601
if (nla_put_be16(inst->skb, NFULA_HWTYPE, htons(skb->dev->type)) ||
net/netfilter/nfnetlink_log.c
602
nla_put_be16(inst->skb, NFULA_HWLEN,
net/netfilter/nfnetlink_log.c
612
nla_put(inst->skb, NFULA_HWHEADER,
net/netfilter/nfnetlink_log.c
623
if (nla_put(inst->skb, NFULA_TIMESTAMP, sizeof(ts), &ts))
net/netfilter/nfnetlink_log.c
643
struct user_namespace *user_ns = inst->peer_user_ns;
net/netfilter/nfnetlink_log.c
646
if (nla_put_be32(inst->skb, NFULA_UID, uid) ||
net/netfilter/nfnetlink_log.c
647
nla_put_be32(inst->skb, NFULA_GID, gid))
net/netfilter/nfnetlink_log.c
653
if ((inst->flags & NFULNL_CFG_F_SEQ) &&
net/netfilter/nfnetlink_log.c
654
nla_put_be32(inst->skb, NFULA_SEQ, htonl(inst->seq++)))
net/netfilter/nfnetlink_log.c
658
if ((inst->flags & NFULNL_CFG_F_SEQ_GLOBAL) &&
net/netfilter/nfnetlink_log.c
659
nla_put_be32(inst->skb, NFULA_SEQ_GLOBAL,
net/netfilter/nfnetlink_log.c
663
if (ct && nfnl_ct->build(inst->skb, ct, ctinfo,
net/netfilter/nfnetlink_log.c
668
nfulnl_put_bridge(inst, skb) < 0)
net/netfilter/nfnetlink_log.c
674
nla = nla_reserve(inst->skb, NFULA_PAYLOAD, data_len);
net/netfilter/nfnetlink_log.c
682
nlh->nlmsg_len = inst->skb->tail - old_tail;
net/netfilter/nfnetlink_log.c
729
struct nfulnl_instance *inst;
net/netfilter/nfnetlink_log.c
743
inst = instance_lookup_get_rcu(log, li->u.ulog.group);
net/netfilter/nfnetlink_log.c
744
if (!inst)
net/netfilter/nfnetlink_log.c
775
spin_lock_bh(&inst->lock);
net/netfilter/nfnetlink_log.c
777
if (inst->flags & NFULNL_CFG_F_SEQ)
net/netfilter/nfnetlink_log.c
779
if (inst->flags & NFULNL_CFG_F_SEQ_GLOBAL)
net/netfilter/nfnetlink_log.c
782
if (inst->flags & NFULNL_CFG_F_CONNTRACK) {
net/netfilter/nfnetlink_log.c
794
qthreshold = inst->qthreshold;
net/netfilter/nfnetlink_log.c
801
switch (inst->copy_mode) {
net/netfilter/nfnetlink_log.c
808
data_len = nfulnl_get_copy_len(li, skb, inst->copy_range);
net/netfilter/nfnetlink_log.c
817
if (inst->skb && size > skb_tailroom(inst->skb)) {
net/netfilter/nfnetlink_log.c
820
__nfulnl_flush(inst);
net/netfilter/nfnetlink_log.c
823
if (!inst->skb) {
net/netfilter/nfnetlink_log.c
824
inst->skb = nfulnl_alloc_skb(net, inst->peer_portid,
net/netfilter/nfnetlink_log.c
825
inst->nlbufsiz, size);
net/netfilter/nfnetlink_log.c
826
if (!inst->skb)
net/netfilter/nfnetlink_log.c
830
inst->qlen++;
net/netfilter/nfnetlink_log.c
832
__build_packet_message(log, inst, skb, data_len, pf,
net/netfilter/nfnetlink_log.c
836
if (inst->qlen >= qthreshold)
net/netfilter/nfnetlink_log.c
837
__nfulnl_flush(inst);
net/netfilter/nfnetlink_log.c
840
else if (!timer_pending(&inst->timer)) {
net/netfilter/nfnetlink_log.c
841
instance_get(inst);
net/netfilter/nfnetlink_log.c
842
inst->timer.expires = jiffies + (inst->flushtimeout*HZ/100);
net/netfilter/nfnetlink_log.c
843
add_timer(&inst->timer);
net/netfilter/nfnetlink_log.c
847
spin_unlock_bh(&inst->lock);
net/netfilter/nfnetlink_log.c
848
instance_put(inst);
net/netfilter/nfnetlink_log.c
870
struct nfulnl_instance *inst;
net/netfilter/nfnetlink_log.c
873
hlist_for_each_entry_safe(inst, t2, head, hlist) {
net/netfilter/nfnetlink_log.c
874
if (n->portid == inst->peer_portid)
net/netfilter/nfnetlink_log.c
875
__instance_destroy(inst);
net/netfilter/nfnetlink_log.c
917
struct nfulnl_instance *inst;
net/netfilter/nfnetlink_log.c
935
inst = instance_lookup_get(log, group_num);
net/netfilter/nfnetlink_log.c
936
if (inst && inst->peer_portid != NETLINK_CB(skb).portid) {
net/netfilter/nfnetlink_log.c
966
if (inst) {
net/netfilter/nfnetlink_log.c
971
inst = instance_create(info->net, group_num,
net/netfilter/nfnetlink_log.c
974
if (IS_ERR(inst)) {
net/netfilter/nfnetlink_log.c
975
ret = PTR_ERR(inst);
net/netfilter/nfnetlink_log.c
980
if (!inst) {
net/netfilter/nfnetlink_log.c
985
instance_destroy(log, inst);
net/netfilter/nfnetlink_log.c
991
} else if (!inst) {
net/netfilter/nfnetlink_queue.c
122
struct nfqnl_instance *inst;
net/netfilter/nfnetlink_queue.c
125
hlist_for_each_entry_rcu(inst, head, hlist) {
net/netfilter/nfnetlink_queue.c
126
if (inst->queue_num == queue_num)
net/netfilter/nfnetlink_queue.c
127
return inst;
net/netfilter/nfnetlink_queue.c
135
struct nfqnl_instance *inst;
net/netfilter/nfnetlink_queue.c
139
inst = kzalloc_obj(*inst, GFP_KERNEL_ACCOUNT);
net/netfilter/nfnetlink_queue.c
140
if (!inst)
net/netfilter/nfnetlink_queue.c
143
inst->queue_num = queue_num;
net/netfilter/nfnetlink_queue.c
144
inst->peer_portid = portid;
net/netfilter/nfnetlink_queue.c
145
inst->queue_maxlen = NFQNL_QMAX_DEFAULT;
net/netfilter/nfnetlink_queue.c
146
inst->copy_range = NFQNL_MAX_COPY_RANGE;
net/netfilter/nfnetlink_queue.c
147
inst->copy_mode = NFQNL_COPY_NONE;
net/netfilter/nfnetlink_queue.c
1470
struct nfqnl_instance *inst;
net/netfilter/nfnetlink_queue.c
1473
hlist_for_each_entry_rcu(inst, head, hlist)
net/netfilter/nfnetlink_queue.c
1474
nfqnl_flush(inst, dev_cmp, ifindex);
net/netfilter/nfnetlink_queue.c
148
spin_lock_init(&inst->lock);
net/netfilter/nfnetlink_queue.c
149
INIT_LIST_HEAD(&inst->queue_list);
net/netfilter/nfnetlink_queue.c
151
err = rhashtable_init(&inst->nfqnl_packet_map, &nfqnl_rhashtable_params);
net/netfilter/nfnetlink_queue.c
1512
struct nfqnl_instance *inst;
net/netfilter/nfnetlink_queue.c
1515
hlist_for_each_entry_rcu(inst, head, hlist)
net/netfilter/nfnetlink_queue.c
1516
nfqnl_flush(inst, NULL, 0);
net/netfilter/nfnetlink_queue.c
1534
struct nfqnl_instance *inst;
net/netfilter/nfnetlink_queue.c
1537
hlist_for_each_entry_safe(inst, t2, head, hlist) {
net/netfilter/nfnetlink_queue.c
1538
if (n->portid == inst->peer_portid)
net/netfilter/nfnetlink_queue.c
1539
__instance_destroy(inst);
net/netfilter/nfnetlink_queue.c
167
hlist_add_head_rcu(&inst->hlist, &q->instance_table[h]);
net/netfilter/nfnetlink_queue.c
171
return inst;
net/netfilter/nfnetlink_queue.c
175
rhashtable_destroy(&inst->nfqnl_packet_map);
net/netfilter/nfnetlink_queue.c
177
kfree(inst);
net/netfilter/nfnetlink_queue.c
186
struct nfqnl_instance *inst;
net/netfilter/nfnetlink_queue.c
188
inst = container_of(to_rcu_work(work), struct nfqnl_instance,
net/netfilter/nfnetlink_queue.c
191
nfqnl_flush(inst, NULL, 0);
net/netfilter/nfnetlink_queue.c
194
rhashtable_destroy(&inst->nfqnl_packet_map);
net/netfilter/nfnetlink_queue.c
196
kfree(inst);
net/netfilter/nfnetlink_queue.c
201
__instance_destroy(struct nfqnl_instance *inst)
net/netfilter/nfnetlink_queue.c
203
hlist_del_rcu(&inst->hlist);
net/netfilter/nfnetlink_queue.c
2032
const struct nfqnl_instance *inst = v;
net/netfilter/nfnetlink_queue.c
2035
inst->queue_num,
net/netfilter/nfnetlink_queue.c
2036
inst->peer_portid, inst->queue_total,
net/netfilter/nfnetlink_queue.c
2037
inst->copy_mode, inst->copy_range,
net/netfilter/nfnetlink_queue.c
2038
inst->queue_dropped, inst->queue_user_dropped,
net/netfilter/nfnetlink_queue.c
2039
inst->id_sequence, 1);
net/netfilter/nfnetlink_queue.c
205
INIT_RCU_WORK(&inst->rwork, instance_destroy_work);
net/netfilter/nfnetlink_queue.c
206
queue_rcu_work(nfq_cleanup_wq, &inst->rwork);
net/netfilter/nfnetlink_queue.c
210
instance_destroy(struct nfnl_queue_net *q, struct nfqnl_instance *inst)
net/netfilter/nfnetlink_queue.c
213
__instance_destroy(inst);
net/rxrpc/rxkad.c
853
name = Z(INST, inst);
net/tipc/msg.c
718
u32 inst = msg_nameinst(msg);
net/tipc/msg.c
735
msg_nametype(msg), inst, inst);
net/tipc/name_table.c
578
u32 inst = ua->sa.instance;
net/tipc/name_table.c
594
service_range_foreach_match(r, sc, inst, inst) {
net/tipc/name_table.c
635
u32 inst = ua->sa.instance;
net/tipc/name_table.c
649
sr = service_range_match_first(sc->ranges.rb_node, inst, inst);
scripts/mod/modpost.c
1195
uint32_t inst, upper, lower, sign, j1, j2;
scripts/mod/modpost.c
1201
inst = get_unaligned_native((uint32_t *)loc);
scripts/mod/modpost.c
1202
return inst + sym->st_value;
scripts/mod/modpost.c
1205
inst = get_unaligned_native((uint32_t *)loc);
scripts/mod/modpost.c
1206
offset = sign_extend32(((inst & 0xf0000) >> 4) | (inst & 0xfff),
scripts/mod/modpost.c
1212
inst = get_unaligned_native((uint32_t *)loc);
scripts/mod/modpost.c
1213
offset = sign_extend32((inst & 0x00ffffff) << 2, 25);
scripts/mod/modpost.c
1279
uint32_t inst;
scripts/mod/modpost.c
1281
inst = get_unaligned_native(location);
scripts/mod/modpost.c
1284
return inst & 0xffff;
scripts/mod/modpost.c
1286
return (inst & 0x03ffffff) << 2;
scripts/mod/modpost.c
1288
return inst;
sound/drivers/opl3/opl3_midi.c
347
fm = &patch->inst;
sound/drivers/opl3/opl3_synth.c
188
struct sbi_patch inst;
sound/drivers/opl3/opl3_synth.c
190
while (count >= sizeof(inst)) {
sound/drivers/opl3/opl3_synth.c
192
if (copy_from_user(&inst, buf, sizeof(inst)))
sound/drivers/opl3/opl3_synth.c
194
if (!memcmp(inst.key, FM_KEY_SBI, 4) ||
sound/drivers/opl3/opl3_synth.c
195
!memcmp(inst.key, FM_KEY_2OP, 4))
sound/drivers/opl3/opl3_synth.c
197
else if (!memcmp(inst.key, FM_KEY_4OP, 4))
sound/drivers/opl3/opl3_synth.c
201
err = snd_opl3_load_patch(opl3, inst.prog, inst.bank, type,
sound/drivers/opl3/opl3_synth.c
202
inst.name, inst.extension,
sound/drivers/opl3/opl3_synth.c
203
inst.data);
sound/drivers/opl3/opl3_synth.c
206
result += sizeof(inst);
sound/drivers/opl3/opl3_synth.c
207
count -= sizeof(inst);
sound/drivers/opl3/opl3_synth.c
255
patch->inst.op[i].am_vib = data[AM_VIB + i];
sound/drivers/opl3/opl3_synth.c
256
patch->inst.op[i].ksl_level = data[KSL_LEVEL + i];
sound/drivers/opl3/opl3_synth.c
257
patch->inst.op[i].attack_decay = data[ATTACK_DECAY + i];
sound/drivers/opl3/opl3_synth.c
258
patch->inst.op[i].sustain_release = data[SUSTAIN_RELEASE + i];
sound/drivers/opl3/opl3_synth.c
259
patch->inst.op[i].wave_select = data[WAVE_SELECT + i];
sound/drivers/opl3/opl3_synth.c
261
patch->inst.feedback_connection[0] = data[CONNECTION];
sound/drivers/opl3/opl3_synth.c
265
patch->inst.op[i+2].am_vib =
sound/drivers/opl3/opl3_synth.c
267
patch->inst.op[i+2].ksl_level =
sound/drivers/opl3/opl3_synth.c
269
patch->inst.op[i+2].attack_decay =
sound/drivers/opl3/opl3_synth.c
271
patch->inst.op[i+2].sustain_release =
sound/drivers/opl3/opl3_synth.c
273
patch->inst.op[i+2].wave_select =
sound/drivers/opl3/opl3_synth.c
276
patch->inst.feedback_connection[1] =
sound/drivers/opl3/opl3_synth.c
281
patch->inst.echo_delay = ext[0];
sound/drivers/opl3/opl3_synth.c
282
patch->inst.echo_atten = ext[1];
sound/drivers/opl3/opl3_synth.c
283
patch->inst.chorus_spread = ext[2];
sound/drivers/opl3/opl3_synth.c
284
patch->inst.trnsps = ext[3];
sound/drivers/opl3/opl3_synth.c
285
patch->inst.fix_dur = ext[4];
sound/drivers/opl3/opl3_synth.c
286
patch->inst.modes = ext[5];
sound/drivers/opl3/opl3_synth.c
287
patch->inst.fix_key = ext[6];
sound/pci/maestro3.c
1066
s->inst.data + CDATA_INSTANCE_READY, 1);
sound/pci/maestro3.c
1075
s->inst.data + CDATA_INSTANCE_READY, 1);
sound/pci/maestro3.c
1089
s->inst.data + CDATA_INSTANCE_READY, 0);
sound/pci/maestro3.c
1156
dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
sound/pci/maestro3.c
1169
s->inst.data + CDATA_HOST_SRC_ADDRL,
sound/pci/maestro3.c
1173
s->inst.data + CDATA_HOST_SRC_ADDRH,
sound/pci/maestro3.c
1177
s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
sound/pci/maestro3.c
1181
s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
sound/pci/maestro3.c
1185
s->inst.data + CDATA_HOST_SRC_CURRENTL,
sound/pci/maestro3.c
1189
s->inst.data + CDATA_HOST_SRC_CURRENTH,
sound/pci/maestro3.c
1197
s->inst.data + CDATA_IN_BUF_BEGIN,
sound/pci/maestro3.c
1201
s->inst.data + CDATA_IN_BUF_END_PLUS_1,
sound/pci/maestro3.c
1205
s->inst.data + CDATA_IN_BUF_HEAD,
sound/pci/maestro3.c
1209
s->inst.data + CDATA_IN_BUF_TAIL,
sound/pci/maestro3.c
1213
s->inst.data + CDATA_OUT_BUF_BEGIN,
sound/pci/maestro3.c
1217
s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
sound/pci/maestro3.c
1221
s->inst.data + CDATA_OUT_BUF_HEAD,
sound/pci/maestro3.c
1225
s->inst.data + CDATA_OUT_BUF_TAIL,
sound/pci/maestro3.c
1239
s->inst.data >> DP_SHIFT_COUNT);
sound/pci/maestro3.c
1241
s->inst.data >> DP_SHIFT_COUNT);
sound/pci/maestro3.c
1243
s->inst.data >> DP_SHIFT_COUNT);
sound/pci/maestro3.c
1249
s->inst.data + SRC3_DIRECTION_OFFSET + 1,
sound/pci/maestro3.c
1253
s->inst.data + SRC3_DIRECTION_OFFSET + 2,
sound/pci/maestro3.c
1262
s->inst.data + CDATA_FREQUENCY,
sound/pci/maestro3.c
1306
s->inst.data + SRC3_DIRECTION_OFFSET + 12,
sound/pci/maestro3.c
1307
s->inst.data + 40 + 8);
sound/pci/maestro3.c
1310
s->inst.data + SRC3_DIRECTION_OFFSET + 19,
sound/pci/maestro3.c
1311
s->inst.code + MINISRC_COEF_LOC);
sound/pci/maestro3.c
1315
s->inst.data + SRC3_DIRECTION_OFFSET + 22,
sound/pci/maestro3.c
1320
s->inst.data + CDATA_DMA_CONTROL,
sound/pci/maestro3.c
1328
s->inst.data + pv[i].addr, pv[i].val);
sound/pci/maestro3.c
1372
s->inst.data + SRC3_DIRECTION_OFFSET + 12,
sound/pci/maestro3.c
1373
s->inst.data + 40 + 8);
sound/pci/maestro3.c
1377
s->inst.data + CDATA_DMA_CONTROL,
sound/pci/maestro3.c
1386
s->inst.data + rv[i].addr, rv[i].val);
sound/pci/maestro3.c
1460
s->inst.data + CDATA_HOST_SRC_CURRENTH);
sound/pci/maestro3.c
1463
s->inst.data + CDATA_HOST_SRC_CURRENTL);
sound/pci/maestro3.c
1466
s->inst.data + CDATA_HOST_SRC_CURRENTH))
sound/pci/maestro3.c
2200
s->inst.code = 0x400;
sound/pci/maestro3.c
2201
s->inst.data = address;
sound/pci/maestro3.c
699
} inst;
sound/pci/ymfpci/ymfpci_main.c
2026
const __le32 *inst;
sound/pci/ymfpci/ymfpci_main.c
2041
inst = (const __le32 *)chip->dsp_microcode->data;
sound/pci/ymfpci/ymfpci_main.c
2044
le32_to_cpu(inst[i]));
sound/pci/ymfpci/ymfpci_main.c
2047
inst = (const __le32 *)chip->controller_microcode->data;
sound/pci/ymfpci/ymfpci_main.c
2050
le32_to_cpu(inst[i]));
tools/arch/arm64/include/asm/sysreg.h
57
#define __emit_inst(x) .inst(x)
tools/arch/x86/include/asm/asm.h
28
#define __ASM_SIZE(inst, ...) __ASM_SEL(inst##l##__VA_ARGS__, \
tools/arch/x86/include/asm/asm.h
29
inst##q##__VA_ARGS__)
tools/build/feature/test-libtracefs.c
6
struct tracefs_instance *inst = tracefs_instance_create("dummy");
tools/build/feature/test-libtracefs.c
8
tracefs_instance_destroy(inst);
tools/objtool/arch/loongarch/decode.c
108
static bool decode_insn_reg1i21_fomat(union loongarch_instruction inst,
tools/objtool/arch/loongarch/decode.c
111
switch (inst.reg1i21_format.opcode) {
tools/objtool/arch/loongarch/decode.c
116
insn->immediate = sign_extend64(inst.reg1i21_format.immediate_h << 16 |
tools/objtool/arch/loongarch/decode.c
117
inst.reg1i21_format.immediate_l, 20);
tools/objtool/arch/loongarch/decode.c
126
static bool decode_insn_reg2i12_fomat(union loongarch_instruction inst,
tools/objtool/arch/loongarch/decode.c
131
switch (inst.reg2i12_format.opcode) {
tools/objtool/arch/loongarch/decode.c
133
if ((inst.reg2i12_format.rd == CFI_SP) || (inst.reg2i12_format.rj == CFI_SP)) {
tools/objtool/arch/loongarch/decode.c
135
insn->immediate = sign_extend64(inst.reg2i12_format.immediate, 11);
tools/objtool/arch/loongarch/decode.c
138
op->src.reg = inst.reg2i12_format.rj;
tools/objtool/arch/loongarch/decode.c
141
op->dest.reg = inst.reg2i12_format.rd;
tools/objtool/arch/loongarch/decode.c
144
if ((inst.reg2i12_format.rd == CFI_SP) && (inst.reg2i12_format.rj == CFI_FP)) {
tools/objtool/arch/loongarch/decode.c
155
if (inst.reg2i12_format.rj == CFI_SP) {
tools/objtool/arch/loongarch/decode.c
157
insn->immediate = sign_extend64(inst.reg2i12_format.immediate, 11);
tools/objtool/arch/loongarch/decode.c
163
op->dest.reg = inst.reg2i12_format.rd;
tools/objtool/arch/loongarch/decode.c
168
if (inst.reg2i12_format.rj == CFI_SP) {
tools/objtool/arch/loongarch/decode.c
170
insn->immediate = sign_extend64(inst.reg2i12_format.immediate, 11);
tools/objtool/arch/loongarch/decode.c
173
op->src.reg = inst.reg2i12_format.rd;
tools/objtool/arch/loongarch/decode.c
181
if (inst.reg2i12_format.rd == 0 &&
tools/objtool/arch/loongarch/decode.c
182
inst.reg2i12_format.rj == 0 &&
tools/objtool/arch/loongarch/decode.c
183
inst.reg2i12_format.immediate == 0)
tools/objtool/arch/loongarch/decode.c
194
static bool decode_insn_reg2i14_fomat(union loongarch_instruction inst,
tools/objtool/arch/loongarch/decode.c
199
switch (inst.reg2i14_format.opcode) {
tools/objtool/arch/loongarch/decode.c
201
if (inst.reg2i14_format.rj == CFI_SP) {
tools/objtool/arch/loongarch/decode.c
203
insn->immediate = sign_extend64(inst.reg2i14_format.immediate, 13);
tools/objtool/arch/loongarch/decode.c
209
op->dest.reg = inst.reg2i14_format.rd;
tools/objtool/arch/loongarch/decode.c
214
if (inst.reg2i14_format.rj == CFI_SP) {
tools/objtool/arch/loongarch/decode.c
216
if (inst.reg2i14_format.rd == LOONGARCH_GPR_RA &&
tools/objtool/arch/loongarch/decode.c
217
inst.reg2i14_format.immediate == 0)
tools/objtool/arch/loongarch/decode.c
221
insn->immediate = sign_extend64(inst.reg2i14_format.immediate, 13);
tools/objtool/arch/loongarch/decode.c
224
op->src.reg = inst.reg2i14_format.rd;
tools/objtool/arch/loongarch/decode.c
238
static bool decode_insn_reg2i16_fomat(union loongarch_instruction inst,
tools/objtool/arch/loongarch/decode.c
241
switch (inst.reg2i16_format.opcode) {
tools/objtool/arch/loongarch/decode.c
243
if (inst.reg2i16_format.rd == 0 &&
tools/objtool/arch/loongarch/decode.c
244
inst.reg2i16_format.rj == CFI_RA &&
tools/objtool/arch/loongarch/decode.c
245
inst.reg2i16_format.immediate == 0) {
tools/objtool/arch/loongarch/decode.c
248
} else if (inst.reg2i16_format.rd == CFI_RA) {
tools/objtool/arch/loongarch/decode.c
251
} else if (inst.reg2i16_format.rd == CFI_A0 &&
tools/objtool/arch/loongarch/decode.c
252
inst.reg2i16_format.immediate == 0) {
tools/objtool/arch/loongarch/decode.c
259
} else if (inst.reg2i16_format.rd == 0 &&
tools/objtool/arch/loongarch/decode.c
260
inst.reg2i16_format.immediate == 0) {
tools/objtool/arch/loongarch/decode.c
263
} else if (inst.reg2i16_format.rd == 0 &&
tools/objtool/arch/loongarch/decode.c
264
inst.reg2i16_format.immediate != 0) {
tools/objtool/arch/loongarch/decode.c
274
insn->immediate = sign_extend64(inst.reg2i16_format.immediate, 15);
tools/objtool/arch/loongarch/decode.c
284
insn->immediate = sign_extend64(inst.reg2i16_format.immediate, 15);
tools/objtool/arch/loongarch/decode.c
293
static bool decode_insn_reg3_fomat(union loongarch_instruction inst,
tools/objtool/arch/loongarch/decode.c
296
switch (inst.reg3_format.opcode) {
tools/objtool/arch/loongarch/decode.c
298
if (inst.reg3_format.rd == LOONGARCH_GPR_ZERO &&
tools/objtool/arch/loongarch/decode.c
299
inst.reg3_format.rk == LOONGARCH_GPR_RA &&
tools/objtool/arch/loongarch/decode.c
300
inst.reg3_format.rj == LOONGARCH_GPR_ZERO) {
tools/objtool/arch/loongarch/decode.c
319
union loongarch_instruction inst;
tools/objtool/arch/loongarch/decode.c
331
inst = *(union loongarch_instruction *)(sec->data->d_buf + offset);
tools/objtool/arch/loongarch/decode.c
333
if (decode_insn_reg0i26_fomat(inst, insn))
tools/objtool/arch/loongarch/decode.c
335
if (decode_insn_reg1i21_fomat(inst, insn))
tools/objtool/arch/loongarch/decode.c
337
if (decode_insn_reg2i12_fomat(inst, insn, ops_list, op))
tools/objtool/arch/loongarch/decode.c
339
if (decode_insn_reg2i14_fomat(inst, insn, ops_list, op))
tools/objtool/arch/loongarch/decode.c
341
if (decode_insn_reg2i16_fomat(inst, insn))
tools/objtool/arch/loongarch/decode.c
343
if (decode_insn_reg3_fomat(inst, insn))
tools/objtool/arch/loongarch/decode.c
346
if (inst.word == 0) {
tools/objtool/arch/loongarch/decode.c
349
} else if (inst.reg0i15_format.opcode == break_op &&
tools/objtool/arch/loongarch/decode.c
350
inst.reg0i15_format.immediate == 0x0) {
tools/objtool/arch/loongarch/decode.c
353
} else if (inst.reg0i15_format.opcode == break_op &&
tools/objtool/arch/loongarch/decode.c
354
inst.reg0i15_format.immediate == 0x1) {
tools/objtool/arch/loongarch/decode.c
357
} else if (inst.reg2_format.opcode == ertn_op) {
tools/objtool/arch/loongarch/decode.c
87
static bool decode_insn_reg0i26_fomat(union loongarch_instruction inst,
tools/objtool/arch/loongarch/decode.c
90
switch (inst.reg0i26_format.opcode) {
tools/objtool/arch/loongarch/decode.c
93
insn->immediate = sign_extend64(inst.reg0i26_format.immediate_h << 16 |
tools/objtool/arch/loongarch/decode.c
94
inst.reg0i26_format.immediate_l, 25);
tools/objtool/arch/loongarch/decode.c
98
insn->immediate = sign_extend64(inst.reg0i26_format.immediate_h << 16 |
tools/objtool/arch/loongarch/decode.c
99
inst.reg0i26_format.immediate_l, 25);
tools/perf/util/dwarf-aux.c
777
static int __die_walk_instances_cb(Dwarf_Die *inst, void *data)
tools/perf/util/dwarf-aux.c
786
if (!die_is_func_instance(inst))
tools/perf/util/dwarf-aux.c
789
attr = dwarf_attr(inst, DW_AT_abstract_origin, &attr_mem);
tools/perf/util/dwarf-aux.c
798
if (dwarf_tag(inst) == DW_TAG_inlined_subroutine) {
tools/perf/util/dwarf-aux.c
799
if (dwarf_decl_line(origin, &tmp) == 0 && die_get_call_lineno(inst) == tmp) {
tools/perf/util/dwarf-aux.c
801
if (die_get_call_fileno(inst) == tmp)
tools/perf/util/dwarf-aux.c
806
iwp->retval = iwp->callback(inst, iwp->data);
tools/testing/selftests/arm64/fp/sme-inst.h
14
.inst 0x4bf5800 \
tools/testing/selftests/arm64/fp/sme-inst.h
36
.inst 0xe1000000 \
tools/testing/selftests/arm64/fp/sme-inst.h
47
.inst 0xe1200000 \
tools/testing/selftests/arm64/fp/sme-inst.h
59
.inst 0xe11f8000 \
tools/testing/selftests/arm64/fp/sme-inst.h
69
.inst 0xe13f8000 \
tools/testing/selftests/bpf/prog_tests/trampoline_count.c
10
static struct bpf_program *load_prog(char *file, char *name, struct inst *inst)
tools/testing/selftests/bpf/prog_tests/trampoline_count.c
20
inst->obj = obj;
tools/testing/selftests/bpf/prog_tests/trampoline_count.c
40
struct inst *inst;
tools/testing/selftests/bpf/prog_tests/trampoline_count.c
45
inst = calloc(bpf_max_tramp_links + 1, sizeof(*inst));
tools/testing/selftests/bpf/prog_tests/trampoline_count.c
46
if (!ASSERT_OK_PTR(inst, "inst"))
tools/testing/selftests/bpf/prog_tests/trampoline_count.c
51
prog = load_prog(file, progs[i % ARRAY_SIZE(progs)], &inst[i]);
tools/testing/selftests/bpf/prog_tests/trampoline_count.c
59
inst[i].link = link;
tools/testing/selftests/bpf/prog_tests/trampoline_count.c
63
prog = load_prog(file, "fmod_ret_test", &inst[i]);
tools/testing/selftests/bpf/prog_tests/trampoline_count.c
70
inst[i].link = link;
tools/testing/selftests/bpf/prog_tests/trampoline_count.c
85
bpf_link__destroy(inst[i].link);
tools/testing/selftests/bpf/prog_tests/trampoline_count.c
86
bpf_object__close(inst[i].obj);
tools/testing/selftests/bpf/prog_tests/trampoline_count.c
88
free(inst);
tools/testing/selftests/powerpc/alignment/alignment_handler.c
71
u32 inst = *(u32 *)ucp->uc_mcontext.gp_regs[PT_NIP];
tools/testing/selftests/powerpc/alignment/alignment_handler.c
72
ucp->uc_mcontext.gp_regs[PT_NIP] += ((inst >> 26 == 1) ? 8 : 4);
tools/thermal/tmon/sysfs.c
400
int inst;
tools/thermal/tmon/sysfs.c
403
inst = get_instance_id(namelist[n]->d_name, 1,
tools/thermal/tmon/sysfs.c
408
if (inst > ptdata.max_cdev_instance)
tools/thermal/tmon/sysfs.c
409
ptdata.max_cdev_instance = inst;
tools/thermal/tmon/sysfs.c
417
inst = get_instance_id(namelist[n]->d_name, 1,
tools/thermal/tmon/sysfs.c
419
if (inst > ptdata.max_tz_instance)
tools/thermal/tmon/sysfs.c
420
ptdata.max_tz_instance = inst;
tools/thermal/tmon/tui.c
624
int inst = ptdata.tzi[i].instance;
tools/thermal/tmon/tui.c
627
TZ_LEFT_ALIGN+TZONE_RECORD_SIZE * inst, "%.9s%02d",
tools/thermal/tmon/tui.c
640
inst * TZONE_RECORD_SIZE + TZ_LEFT_ALIGN +
tools/thermal/tmon/tui.c
643
inst, j, type);
tools/tracing/rtla/src/common.c
183
retval = enable_tracer_by_name(tool->trace.inst, ops->tracer);
tools/tracing/rtla/src/common.c
213
params->threshold_actions.trace_output_inst = tool->record->trace.inst;
tools/tracing/rtla/src/common.c
214
params->end_actions.trace_output_inst = tool->record->trace.inst;
tools/tracing/rtla/src/common.c
25
tracefs_iterate_stop(trace_tool->trace.inst);
tools/tracing/rtla/src/common.c
313
trace->inst,
tools/tracing/rtla/src/common.c
364
trace->inst,
tools/tracing/rtla/src/osnoise.c
1193
retval = tracefs_event_enable(trace->trace.inst, "osnoise", NULL);
tools/tracing/rtla/src/osnoise.c
1199
retval = enable_tracer_by_name(trace->trace.inst, tracer);
tools/tracing/rtla/src/osnoise.c
1217
if (!tracefs_trace_is_on(tool->trace.inst))
tools/tracing/rtla/src/osnoise.c
1224
return record && !tracefs_trace_is_on(record->trace.inst);
tools/tracing/rtla/src/osnoise.c
1311
retval = tracefs_instance_file_write(tool->trace.inst, "trace", "");
tools/tracing/rtla/src/osnoise_hist.c
133
tracefs_hist_pause(tool->trace.inst, data->trace_hist);
tools/tracing/rtla/src/osnoise_hist.c
134
tracefs_hist_destroy(tool->trace.inst, data->trace_hist);
tools/tracing/rtla/src/osnoise_hist.c
163
retval = tracefs_hist_start(tool->trace.inst, data->trace_hist);
tools/tracing/rtla/src/osnoise_hist.c
183
tracefs_hist_pause(tool->trace.inst, data->trace_hist);
tools/tracing/rtla/src/osnoise_hist.c
185
content = tracefs_event_file_read(tool->trace.inst, "osnoise",
tools/tracing/rtla/src/timerlat.c
162
retval = enable_tracer_by_name(tool->aa->trace.inst, "timerlat");
tools/tracing/rtla/src/timerlat.c
225
max_lat = tracefs_instance_file_read(tool->trace.inst, "tracing_max_latency", NULL);
tools/tracing/rtla/src/timerlat_aa.c
1002
retval = tracefs_event_enable(tool->trace.inst, "workqueue", "workqueue_execute_start");
tools/tracing/rtla/src/timerlat_aa.c
730
trace->inst,
tools/tracing/rtla/src/timerlat_aa.c
922
tracefs_event_disable(tool->trace.inst, "osnoise", NULL);
tools/tracing/rtla/src/timerlat_aa.c
941
tracefs_event_disable(tool->trace.inst, "sched", "sched_switch");
tools/tracing/rtla/src/timerlat_aa.c
945
tracefs_event_disable(tool->trace.inst, "workqueue", "workqueue_execute_start");
tools/tracing/rtla/src/timerlat_aa.c
966
retval = tracefs_event_enable(tool->trace.inst, "osnoise", NULL);
tools/tracing/rtla/src/timerlat_aa.c
993
retval = tracefs_event_enable(tool->trace.inst, "sched", "sched_switch");
tools/tracing/rtla/src/trace.c
15
int enable_tracer_by_name(struct tracefs_instance *inst, const char *tracer_name)
tools/tracing/rtla/src/trace.c
181
if (trace->inst) {
tools/tracing/rtla/src/trace.c
182
disable_tracer(trace->inst);
tools/tracing/rtla/src/trace.c
183
destroy_instance(trace->inst);
tools/tracing/rtla/src/trace.c
184
trace->inst = NULL;
tools/tracing/rtla/src/trace.c
215
trace->inst = create_instance(tool_name);
tools/tracing/rtla/src/trace.c
216
if (!trace->inst)
tools/tracing/rtla/src/trace.c
227
tracefs_trace_off(trace->inst);
tools/tracing/rtla/src/trace.c
234
tracefs_follow_missed_events(trace->inst,
tools/tracing/rtla/src/trace.c
24
retval = tracefs_tracer_set(inst, tracer, tracer_name);
tools/tracing/rtla/src/trace.c
252
return tracefs_trace_on(trace->inst);
tools/tracing/rtla/src/trace.c
260
return tracefs_trace_off(trace->inst);
tools/tracing/rtla/src/trace.c
347
retval = tracefs_event_file_write(instance->inst, tevent->system,
tools/tracing/rtla/src/trace.c
389
hist = tracefs_event_file_read(instance->inst, tevent->system, tevent->event, "hist", 0);
tools/tracing/rtla/src/trace.c
39
void disable_tracer(struct tracefs_instance *inst)
tools/tracing/rtla/src/trace.c
436
retval = tracefs_event_file_write(instance->inst, tevent->system,
tools/tracing/rtla/src/trace.c
44
retval = tracefs_tracer_set(inst, t);
tools/tracing/rtla/src/trace.c
459
tracefs_event_disable(instance->inst, tevent->system, tevent->event);
tools/tracing/rtla/src/trace.c
490
retval = tracefs_event_file_write(instance->inst, tevent->system,
tools/tracing/rtla/src/trace.c
525
retval = tracefs_event_file_write(instance->inst, tevent->system,
tools/tracing/rtla/src/trace.c
549
retval = tracefs_event_enable(instance->inst, tevent->system, tevent->event);
tools/tracing/rtla/src/trace.c
592
retval = tracefs_instance_set_buffer_size(trace->inst, size, -1);
tools/tracing/rtla/src/trace.c
60
void destroy_instance(struct tracefs_instance *inst)
tools/tracing/rtla/src/trace.c
62
tracefs_instance_destroy(inst);
tools/tracing/rtla/src/trace.c
63
tracefs_instance_free(inst);
tools/tracing/rtla/src/trace.c
69
int save_trace_to_file(struct tracefs_instance *inst, const char *filename)
tools/tracing/rtla/src/trace.c
79
if (!inst || !filename)
tools/tracing/rtla/src/trace.c
82
in_fd = tracefs_instance_file_open(inst, file, O_RDONLY);
tools/tracing/rtla/src/trace.h
17
struct tracefs_instance *inst;
tools/tracing/rtla/src/trace.h
30
int enable_tracer_by_name(struct tracefs_instance *inst, const char *tracer_name);
tools/tracing/rtla/src/trace.h
31
void disable_tracer(struct tracefs_instance *inst);
tools/tracing/rtla/src/trace.h
34
void destroy_instance(struct tracefs_instance *inst);
tools/tracing/rtla/src/trace.h
36
int save_trace_to_file(struct tracefs_instance *inst, const char *filename);
tools/verification/rv/include/trace.h
6
struct tracefs_instance *inst;
tools/verification/rv/src/in_kernel.c
529
static int ikm_enable_trace_events(char *monitor_name, struct trace_instance *inst)
tools/verification/rv/src/in_kernel.c
535
retval = tracefs_event_enable(inst->inst, "rv", event);
tools/verification/rv/src/in_kernel.c
539
tep_register_event_handler(inst->tep, -1, "rv", event,
tools/verification/rv/src/in_kernel.c
543
retval = tracefs_event_enable(inst->inst, "rv", event);
tools/verification/rv/src/in_kernel.c
547
tep_register_event_handler(inst->tep, -1, "rv", event,
tools/verification/rv/src/in_kernel.c
560
struct trace_instance *inst)
tools/verification/rv/src/in_kernel.c
578
retval = ikm_enable_trace_events(ep->d_name, inst);
tools/verification/rv/src/in_kernel.c
596
struct trace_instance *inst;
tools/verification/rv/src/in_kernel.c
603
inst = calloc(1, sizeof(*inst));
tools/verification/rv/src/in_kernel.c
604
if (!inst) {
tools/verification/rv/src/in_kernel.c
609
retval = trace_instance_init(inst, monitor_name);
tools/verification/rv/src/in_kernel.c
614
retval = ikm_enable_trace_container(monitor_name, inst);
tools/verification/rv/src/in_kernel.c
616
retval = ikm_enable_trace_events(monitor_name, inst);
tools/verification/rv/src/in_kernel.c
621
tracefs_trace_on(inst->inst);
tools/verification/rv/src/in_kernel.c
623
return inst;
tools/verification/rv/src/in_kernel.c
626
trace_instance_destroy(inst);
tools/verification/rv/src/in_kernel.c
628
free(inst);
tools/verification/rv/src/in_kernel.c
636
static void ikm_destroy_trace_instance(struct trace_instance *inst)
tools/verification/rv/src/in_kernel.c
638
if (!inst)
tools/verification/rv/src/in_kernel.c
641
trace_instance_destroy(inst);
tools/verification/rv/src/in_kernel.c
642
free(inst);
tools/verification/rv/src/in_kernel.c
781
struct trace_instance *inst = NULL;
tools/verification/rv/src/in_kernel.c
811
inst = ikm_setup_trace_instance(nested_name);
tools/verification/rv/src/in_kernel.c
812
if (!inst)
tools/verification/rv/src/in_kernel.c
821
ikm_print_header(inst->seq);
tools/verification/rv/src/in_kernel.c
825
retval = tracefs_iterate_raw_events(inst->tep,
tools/verification/rv/src/in_kernel.c
826
inst->inst,
tools/verification/rv/src/in_kernel.c
830
inst);
tools/verification/rv/src/in_kernel.c
841
ikm_destroy_trace_instance(inst);
tools/verification/rv/src/in_kernel.c
849
ikm_destroy_trace_instance(inst);
tools/verification/rv/src/trace.c
104
trace->inst = create_instance(name);
tools/verification/rv/src/trace.c
105
if (!trace->inst)
tools/verification/rv/src/trace.c
116
tracefs_trace_off(trace->inst);
tools/verification/rv/src/trace.c
132
return tracefs_trace_on(trace->inst);
tools/verification/rv/src/trace.c
30
static void destroy_instance(struct tracefs_instance *inst)
tools/verification/rv/src/trace.c
32
tracefs_instance_destroy(inst);
tools/verification/rv/src/trace.c
33
tracefs_instance_free(inst);
tools/verification/rv/src/trace.c
67
if (trace->inst) {
tools/verification/rv/src/trace.c
68
destroy_instance(trace->inst);
tools/verification/rv/src/trace.c
69
trace->inst = NULL;
