root/drivers/gpu/drm/amd/include/asic_reg/thm/thm_15_0_0_offset.h
/*
 * Copyright (C) 2025  Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */
#ifndef _thm_15_0_0_OFFSET_HEADER
#define _thm_15_0_0_OFFSET_HEADER



// addressBlock: thm_thm_SmuThmDec
// base address: 0x59800
#define regTHM_TCON_CUR_TMP                                                                             0x0000
#define regTHM_TCON_CUR_TMP_BASE_IDX                                                                    0
#define regTHM_TCON_HTC                                                                                 0x0001
#define regTHM_TCON_HTC_BASE_IDX                                                                        0
#define regTHM_TCON_THERM_TRIP                                                                          0x0002
#define regTHM_TCON_THERM_TRIP_BASE_IDX                                                                 0
#define regTHM_CTF_DELAY                                                                                0x0004
#define regTHM_CTF_DELAY_BASE_IDX                                                                       0
#define regTHM_GPIO_PROCHOT_CTRL                                                                        0x0005
#define regTHM_GPIO_PROCHOT_CTRL_BASE_IDX                                                               0
#define regTHM_SW_TEMP                                                                                  0x0006
#define regTHM_SW_TEMP_BASE_IDX                                                                         0
#define regCG_MULT_THERMAL_CTRL                                                                         0x0007
#define regCG_MULT_THERMAL_CTRL_BASE_IDX                                                                0
#define regCG_MULT_THERMAL_STATUS                                                                       0x0008
#define regCG_MULT_THERMAL_STATUS_BASE_IDX                                                              0
#define regCG_THERMAL_RANGE                                                                             0x0009
#define regCG_THERMAL_RANGE_BASE_IDX                                                                    0
#define regTHM_TCON_LOCAL2                                                                              0x000a
#define regTHM_TCON_LOCAL2_BASE_IDX                                                                     0
#define regTHM_TCON_LOCAL3                                                                              0x000b
#define regTHM_TCON_LOCAL3_BASE_IDX                                                                     0
#define regTHM_TCON_LOCAL4                                                                              0x000c
#define regTHM_TCON_LOCAL4_BASE_IDX                                                                     0
#define regTHM_TCON_LOCAL5                                                                              0x000d
#define regTHM_TCON_LOCAL5_BASE_IDX                                                                     0
#define regTHM_TCON_LOCAL6                                                                              0x000e
#define regTHM_TCON_LOCAL6_BASE_IDX                                                                     0
#define regTHM_TCON_LOCAL7                                                                              0x000f
#define regTHM_TCON_LOCAL7_BASE_IDX                                                                     0
#define regTHM_TCON_LOCAL8                                                                              0x0010
#define regTHM_TCON_LOCAL8_BASE_IDX                                                                     0
#define regTHM_TCON_LOCAL9                                                                              0x0011
#define regTHM_TCON_LOCAL9_BASE_IDX                                                                     0
#define regTHM_TCON_LOCAL10                                                                             0x0012
#define regTHM_TCON_LOCAL10_BASE_IDX                                                                    0
#define regTHM_TCON_LOCAL11                                                                             0x0013
#define regTHM_TCON_LOCAL11_BASE_IDX                                                                    0
#define regTHM_TCON_LOCAL12                                                                             0x0014
#define regTHM_TCON_LOCAL12_BASE_IDX                                                                    0
#define regTHM_TCON_LOCAL13                                                                             0x0015
#define regTHM_TCON_LOCAL13_BASE_IDX                                                                    0
#define regTHM_TCON_LOCAL14                                                                             0x0016
#define regTHM_TCON_LOCAL14_BASE_IDX                                                                    0
#define regTHM_TCON_LOCAL15                                                                             0x0017
#define regTHM_TCON_LOCAL15_BASE_IDX                                                                    0
#define regTHM_PWRMGT                                                                                   0x001b
#define regTHM_PWRMGT_BASE_IDX                                                                          0
#define regTHM_DIE1_TEMP                                                                                0x001c
#define regTHM_DIE1_TEMP_BASE_IDX                                                                       0
#define regTHM_DIE2_TEMP                                                                                0x001d
#define regTHM_DIE2_TEMP_BASE_IDX                                                                       0
#define regTHM_DIE3_TEMP                                                                                0x001e
#define regTHM_DIE3_TEMP_BASE_IDX                                                                       0
#define regSMUSBI_SBIREGADDR                                                                            0x0124
#define regSMUSBI_SBIREGADDR_BASE_IDX                                                                   0
#define regSMUSBI_SBIREGDATA                                                                            0x0125
#define regSMUSBI_SBIREGDATA_BASE_IDX                                                                   0
#define regSMUSBI_ERRATA_STAT_REG                                                                       0x0129
#define regSMUSBI_ERRATA_STAT_REG_BASE_IDX                                                              0
#define regSMUSBI_SBICTRL                                                                               0x012a
#define regSMUSBI_SBICTRL_BASE_IDX                                                                      0
#define regSMUSBI_CKNBIRESET                                                                            0x012b
#define regSMUSBI_CKNBIRESET_BASE_IDX                                                                   0
#define regSMUSBI_TIMING                                                                                0x012c
#define regSMUSBI_TIMING_BASE_IDX                                                                       0
#define regSMUSBI_HS_TIMING                                                                             0x012d
#define regSMUSBI_HS_TIMING_BASE_IDX                                                                    0
#define regSBTSI_REMOTE_TEMP                                                                            0x012e
#define regSBTSI_REMOTE_TEMP_BASE_IDX                                                                   0
#define regSBRMI_CONTROL                                                                                0x012f
#define regSBRMI_CONTROL_BASE_IDX                                                                       0
#define regSBRMI_COMMAND                                                                                0x0130
#define regSBRMI_COMMAND_BASE_IDX                                                                       0
#define regSBRMI_WRITE_DATA0                                                                            0x0132
#define regSBRMI_WRITE_DATA0_BASE_IDX                                                                   0
#define regSBRMI_WRITE_DATA1                                                                            0x0133
#define regSBRMI_WRITE_DATA1_BASE_IDX                                                                   0
#define regSBRMI_WRITE_DATA2                                                                            0x0134
#define regSBRMI_WRITE_DATA2_BASE_IDX                                                                   0
#define regSBRMI_READ_DATA0                                                                             0x0136
#define regSBRMI_READ_DATA0_BASE_IDX                                                                    0
#define regSBRMI_READ_DATA1                                                                             0x0137
#define regSBRMI_READ_DATA1_BASE_IDX                                                                    0
#define regSBRMI_CORE_EN_NUMBER                                                                         0x0138
#define regSBRMI_CORE_EN_NUMBER_BASE_IDX                                                                0
#define regSBRMI_CORE_EN_STATUS0                                                                        0x0139
#define regSBRMI_CORE_EN_STATUS0_BASE_IDX                                                               0
#define regSBRMI_CORE_EN_STATUS1                                                                        0x013a
#define regSBRMI_CORE_EN_STATUS1_BASE_IDX                                                               0
#define regSBRMI_APIC_STATUS0                                                                           0x013b
#define regSBRMI_APIC_STATUS0_BASE_IDX                                                                  0
#define regSBRMI_APIC_STATUS1                                                                           0x013c
#define regSBRMI_APIC_STATUS1_BASE_IDX                                                                  0
#define regSBRMI_MCE_STATUS0                                                                            0x013d
#define regSBRMI_MCE_STATUS0_BASE_IDX                                                                   0
#define regSBRMI_MCE_STATUS1                                                                            0x013e
#define regSBRMI_MCE_STATUS1_BASE_IDX                                                                   0
#define regSMBUS_CNTL0                                                                                  0x013f
#define regSMBUS_CNTL0_BASE_IDX                                                                         0
#define regSMBUS_CNTL1                                                                                  0x0140
#define regSMBUS_CNTL1_BASE_IDX                                                                         0
#define regSMBUS_BLKWR_CMD_CTRL0                                                                        0x0141
#define regSMBUS_BLKWR_CMD_CTRL0_BASE_IDX                                                               0
#define regSMBUS_BLKWR_CMD_CTRL1                                                                        0x0142
#define regSMBUS_BLKWR_CMD_CTRL1_BASE_IDX                                                               0
#define regSMBUS_BLKRD_CMD_CTRL0                                                                        0x0143
#define regSMBUS_BLKRD_CMD_CTRL0_BASE_IDX                                                               0
#define regSMBUS_BLKRD_CMD_CTRL1                                                                        0x0144
#define regSMBUS_BLKRD_CMD_CTRL1_BASE_IDX                                                               0
#define regSMBUS_TIMING_CNTL0                                                                           0x0145
#define regSMBUS_TIMING_CNTL0_BASE_IDX                                                                  0
#define regSMBUS_TIMING_CNTL1                                                                           0x0146
#define regSMBUS_TIMING_CNTL1_BASE_IDX                                                                  0
#define regSMBUS_TIMING_CNTL2                                                                           0x0147
#define regSMBUS_TIMING_CNTL2_BASE_IDX                                                                  0
#define regSMBUS_TRIGGER_CNTL                                                                           0x0148
#define regSMBUS_TRIGGER_CNTL_BASE_IDX                                                                  0
#define regSMBUS_UDID_CNTL0                                                                             0x0149
#define regSMBUS_UDID_CNTL0_BASE_IDX                                                                    0
#define regSMBUS_UDID_CNTL1                                                                             0x014a
#define regSMBUS_UDID_CNTL1_BASE_IDX                                                                    0
#define regSMBUS_UDID_CNTL2                                                                             0x014b
#define regSMBUS_UDID_CNTL2_BASE_IDX                                                                    0
#define regSMUSBI_SMBUS                                                                                 0x014c
#define regSMUSBI_SMBUS_BASE_IDX                                                                        0
#define regSMUSBI_ALERT                                                                                 0x014d
#define regSMUSBI_ALERT_BASE_IDX                                                                        0

#endif