// SPDX-License-Identifier: MIT
//
// Copyright 2026 Advanced Micro Devices, Inc.

#include "dcn401/dcn401_hubp.h"
#include "dcn42_hubp.h"
#include "reg_helper.h"

#define REG(reg) \
        hubp2->hubp_regs->reg

#define CTX \
        hubp2->base.ctx

#undef FN
#define FN(reg_name, field_name) \
        hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name

static void hubp42_set_fgcg(struct hubp *hubp, bool enable)
{
        struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

        REG_UPDATE(HUBP_CLK_CNTL, HUBP_FGCG_REP_DIS, !enable);
}

static void hubp42_init(struct hubp *hubp)
{
        hubp3_init(hubp);

        hubp42_set_fgcg(hubp, hubp->ctx->dc->debug.enable_fine_grain_clock_gating.bits.dchub);

        /*do nothing for now for dcn3.5 or later*/
}

static void hubp42_program_pixel_format(
        struct hubp *hubp,
        enum surface_pixel_format format)
{
        struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
        uint32_t green_bar = 1;
        uint32_t red_bar = 3;
        uint32_t blue_bar = 2;

        /* swap for ABGR format */
        if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
                        || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
                        || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
                        || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616
                        || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
                red_bar = 2;
                blue_bar = 3;
        }

        REG_UPDATE_3(HUBPRET_CONTROL,
                        CROSSBAR_SRC_Y_G, green_bar,
                        CROSSBAR_SRC_CB_B, blue_bar,
                        CROSSBAR_SRC_CR_R, red_bar);

        /* Mapping is same as ipp programming (cnvc) */

        switch (format) {
        case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
                REG_UPDATE(DCSURF_SURFACE_CONFIG,
                                SURFACE_PIXEL_FORMAT, 1);
                break;
        case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
                REG_UPDATE(DCSURF_SURFACE_CONFIG,
                                SURFACE_PIXEL_FORMAT, 3);
                break;
        case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
        case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
                REG_UPDATE(DCSURF_SURFACE_CONFIG,
                                SURFACE_PIXEL_FORMAT, 8);
                break;
        case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
        case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
        case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
                REG_UPDATE(DCSURF_SURFACE_CONFIG,
                                SURFACE_PIXEL_FORMAT, 10);
                break;
        case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
        case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /* we use crossbar already */
                REG_UPDATE(DCSURF_SURFACE_CONFIG,
                                SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */
                break;
        case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
        case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/
                REG_UPDATE(DCSURF_SURFACE_CONFIG,
                                SURFACE_PIXEL_FORMAT, 24);
                break;

        case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
                REG_UPDATE(DCSURF_SURFACE_CONFIG,
                                SURFACE_PIXEL_FORMAT, 65);
                break;
        case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
                REG_UPDATE(DCSURF_SURFACE_CONFIG,
                                SURFACE_PIXEL_FORMAT, 64);
                break;
        case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
                REG_UPDATE(DCSURF_SURFACE_CONFIG,
                                SURFACE_PIXEL_FORMAT, 67);
                break;
        case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
                REG_UPDATE(DCSURF_SURFACE_CONFIG,
                                SURFACE_PIXEL_FORMAT, 66);
                break;
        case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
                REG_UPDATE(DCSURF_SURFACE_CONFIG,
                                SURFACE_PIXEL_FORMAT, 12);
                break;
        case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
                REG_UPDATE(DCSURF_SURFACE_CONFIG,
                                SURFACE_PIXEL_FORMAT, 112);
                break;
        case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
                REG_UPDATE(DCSURF_SURFACE_CONFIG,
                                SURFACE_PIXEL_FORMAT, 113);
                break;
        case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
                REG_UPDATE(DCSURF_SURFACE_CONFIG,
                                SURFACE_PIXEL_FORMAT, 114);
                break;
        case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
                REG_UPDATE(DCSURF_SURFACE_CONFIG,
                                SURFACE_PIXEL_FORMAT, 118);
                break;
        case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
                REG_UPDATE(DCSURF_SURFACE_CONFIG,
                                SURFACE_PIXEL_FORMAT, 119);
                break;
        case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
                REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
                                SURFACE_PIXEL_FORMAT, 116,
                                ALPHA_PLANE_EN, 0);
                break;
        case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
                REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
                                SURFACE_PIXEL_FORMAT, 116,
                                ALPHA_PLANE_EN, 1);
                break;
        default:
                BREAK_TO_DEBUGGER();
                break;
        }

        /* don't see the need of program the xbar in DCN 1.0 */
}

static void hubp42_program_deadline(
                struct hubp *hubp,
                struct dml2_display_dlg_regs *dlg_attr,
                struct dml2_display_ttu_regs *ttu_attr)
{
        struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

        /* put DLG in mission mode */
        REG_WRITE(HUBPREQ_DEBUG_DB, 0);

        /* DLG - Per hubp */
        REG_SET_2(BLANK_OFFSET_0, 0,
                REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end,
                DLG_V_BLANK_END, dlg_attr->dlg_vblank_end);

        REG_SET(BLANK_OFFSET_1, 0,
                MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start);

        REG_SET(DST_DIMENSIONS, 0,
                REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal);

        REG_SET_2(DST_AFTER_SCALER, 0,
                REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler,
                DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler);

        REG_SET(REF_FREQ_TO_PIX_FREQ, 0,
                REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq);

        /* DLG - Per luma/chroma */
        REG_SET(VBLANK_PARAMETERS_1, 0,
                REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l);

        if (REG(NOM_PARAMETERS_0))
                REG_SET(NOM_PARAMETERS_0, 0,
                        DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);

        if (REG(NOM_PARAMETERS_1))
                REG_SET(NOM_PARAMETERS_1, 0,
                        REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);

        REG_SET(NOM_PARAMETERS_4, 0,
                DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);

        REG_SET(NOM_PARAMETERS_5, 0,
                REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l);

        REG_SET_2(PER_LINE_DELIVERY, 0,
                REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l,
                REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c);

        REG_SET(VBLANK_PARAMETERS_2, 0,
                REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c);

        if (REG(NOM_PARAMETERS_2))
                REG_SET(NOM_PARAMETERS_2, 0,
                        DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);

        if (REG(NOM_PARAMETERS_3))
                REG_SET(NOM_PARAMETERS_3, 0,
                        REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);

        REG_SET(NOM_PARAMETERS_6, 0,
                DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c);

        REG_SET(NOM_PARAMETERS_7, 0,
                REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c);

        /* TTU - per hubp */
        REG_SET_2(DCN_TTU_QOS_WM, 0,
                QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm,
                QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);

        /* TTU - per luma/chroma */
        /* Assumed surf0 is luma and 1 is chroma */

        REG_SET_3(DCN_SURF0_TTU_CNTL0, 0,
                REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l,
                QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l,
                QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l);

        REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,
                REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c,
                QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c,
                QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c);

        REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,
                REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0,
                QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0,
                QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0);

        REG_SET(FLIP_PARAMETERS_1, 0,
                REFCYC_PER_PTE_GROUP_FLIP_L, dlg_attr->refcyc_per_pte_group_flip_l);
        REG_SET(HUBP_3DLUT_DLG_PARAM, 0, REFCYC_PER_3DLUT_GROUP, dlg_attr->refcyc_per_tdlut_group);

        REG_UPDATE(DCN_DMDATA_VM_CNTL,
                        REFCYC_PER_VM_DMDATA, dlg_attr->refcyc_per_vm_dmdata);
}

void hubp42_program_requestor(
                struct hubp *hubp,
                struct dml2_display_rq_regs *rq_regs)
{
        struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

        REG_UPDATE(HUBPRET_CONTROL,
                        DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
        REG_SET_4(DCN_EXPANSION_MODE, 0,
                        DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
                        PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
                        MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
                        CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
        REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,
                CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
                MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
                META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
                MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
                DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
                VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
                SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
                PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
        REG_SET_7(DCHUBP_REQ_SIZE_CONFIG_C, 0,
                CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
                MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
                META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
                MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
                DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
                SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
                PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
}


void hubp42_setup(
                struct hubp *hubp,
            struct dml2_dchub_per_pipe_register_set *pipe_regs,
                union dml2_global_sync_programming *pipe_global_sync,
                struct dc_crtc_timing *timing)
{
        /* otg is locked when this func is called. Register are double buffered.
         * disable the requestors is not needed
         */
        hubp401_vready_at_or_After_vsync(hubp, pipe_global_sync, timing);
        hubp42_program_requestor(hubp, &pipe_regs->rq_regs);
        hubp42_program_deadline(hubp, &pipe_regs->dlg_regs, &pipe_regs->ttu_regs);
}
static void hubp42_program_surface_config(
        struct hubp *hubp,
        enum surface_pixel_format format,
        struct dc_tiling_info *tiling_info,
        struct plane_size *plane_size,
        enum dc_rotation_angle rotation,
        struct dc_plane_dcc_param *dcc,
        bool horizontal_mirror,
        unsigned int compat_level)
{
        (void)compat_level;
        struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

        hubp3_dcc_control_sienna_cichlid(hubp, dcc);
        hubp3_program_tiling(hubp2, tiling_info, format);
        hubp2_program_size(hubp, format, plane_size, dcc);
        hubp2_program_rotation(hubp, rotation, horizontal_mirror);
        hubp42_program_pixel_format(hubp, format);
}

void hubp42_program_3dlut_fl_crossbar(struct hubp *hubp,
        enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_r,
        enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_g,
        enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_b)
{
        struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

        REG_UPDATE_3(HUBP_3DLUT_CONTROL,
                HUBP_3DLUT_CROSSBAR_SEL_R, bit_slice_r,
                HUBP_3DLUT_CROSSBAR_SEL_G, bit_slice_g,
                HUBP_3DLUT_CROSSBAR_SEL_B, bit_slice_b);
}

static bool hubp42_program_surface_flip_and_addr(
        struct hubp *hubp,
        const struct dc_plane_address *address,
        bool flip_immediate)
{
        struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

        //program flip type
        REG_UPDATE(DCSURF_FLIP_CONTROL,
                        SURFACE_FLIP_TYPE, flip_immediate);

        // Program VMID reg
        if (flip_immediate == 0)
                REG_UPDATE(VMID_SETTINGS_0,
                        VMID, address->vmid);

        if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) {
                REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0);
                REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1);

        } else {
                // turn off stereo if not in stereo
                REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0);
                REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0);
        }

        /* HW automatically latch rest of address register on write to
         * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used
         *
         * program high first and then the low addr, order matters!
         */
        switch (address->type) {
        case PLN_ADDR_TYPE_GRAPHICS:
                /* DCN1.0 does not support const color
                 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1
                 * base on address->grph.dcc_const_color
                 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma
                 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma
                 */

                if (address->grph.addr.quad_part == 0)
                        break;

                REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
                                PRIMARY_SURFACE_TMZ, address->tmz_surface,
                                PRIMARY_META_SURFACE_TMZ, address->tmz_surface);

                if (address->grph.meta_addr.quad_part != 0) {
                        REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
                                        PRIMARY_META_SURFACE_ADDRESS_HIGH,
                                        address->grph.meta_addr.high_part);

                        REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
                                        PRIMARY_META_SURFACE_ADDRESS,
                                        address->grph.meta_addr.low_part);
                }

                REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
                                PRIMARY_SURFACE_ADDRESS_HIGH,
                                address->grph.addr.high_part);

                REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
                                PRIMARY_SURFACE_ADDRESS,
                                address->grph.addr.low_part);
                break;
        case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
                if (address->video_progressive.luma_addr.quad_part == 0
                                || address->video_progressive.chroma_addr.quad_part == 0)
                        break;

                REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
                                PRIMARY_SURFACE_TMZ, address->tmz_surface,
                                PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
                                PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
                                PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);

                if (address->video_progressive.luma_meta_addr.quad_part != 0) {
                        REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
                                        PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
                                        address->video_progressive.chroma_meta_addr.high_part);

                        REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
                                        PRIMARY_META_SURFACE_ADDRESS_C,
                                        address->video_progressive.chroma_meta_addr.low_part);

                        REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
                                        PRIMARY_META_SURFACE_ADDRESS_HIGH,
                                        address->video_progressive.luma_meta_addr.high_part);

                        REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
                                        PRIMARY_META_SURFACE_ADDRESS,
                                        address->video_progressive.luma_meta_addr.low_part);
                }

                REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
                                PRIMARY_SURFACE_ADDRESS_HIGH_C,
                                address->video_progressive.chroma_addr.high_part);

                REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
                                PRIMARY_SURFACE_ADDRESS_C,
                                address->video_progressive.chroma_addr.low_part);

                REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
                                PRIMARY_SURFACE_ADDRESS_HIGH,
                                address->video_progressive.luma_addr.high_part);

                REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
                                PRIMARY_SURFACE_ADDRESS,
                                address->video_progressive.luma_addr.low_part);
                break;
        case PLN_ADDR_TYPE_GRPH_STEREO:
                if (address->grph_stereo.left_addr.quad_part == 0)
                        break;
                if (address->grph_stereo.right_addr.quad_part == 0)
                        break;

                REG_UPDATE_8(DCSURF_SURFACE_CONTROL,
                                PRIMARY_SURFACE_TMZ, address->tmz_surface,
                                PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
                                PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
                                PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface,
                                SECONDARY_SURFACE_TMZ, address->tmz_surface,
                                SECONDARY_SURFACE_TMZ_C, address->tmz_surface,
                                SECONDARY_META_SURFACE_TMZ, address->tmz_surface,
                                SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface);

                if (address->grph_stereo.right_meta_addr.quad_part != 0) {

                        REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, 0,
                                SECONDARY_META_SURFACE_ADDRESS_HIGH_C,
                                address->grph_stereo.right_alpha_meta_addr.high_part);

                        REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, 0,
                                SECONDARY_META_SURFACE_ADDRESS_C,
                                address->grph_stereo.right_alpha_meta_addr.low_part);

                        REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,
                                        SECONDARY_META_SURFACE_ADDRESS_HIGH,
                                        address->grph_stereo.right_meta_addr.high_part);

                        REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,
                                        SECONDARY_META_SURFACE_ADDRESS,
                                        address->grph_stereo.right_meta_addr.low_part);
                }
                if (address->grph_stereo.left_meta_addr.quad_part != 0) {

                        REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
                                PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
                                address->grph_stereo.left_alpha_meta_addr.high_part);

                        REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
                                PRIMARY_META_SURFACE_ADDRESS_C,
                                address->grph_stereo.left_alpha_meta_addr.low_part);

                        REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
                                        PRIMARY_META_SURFACE_ADDRESS_HIGH,
                                        address->grph_stereo.left_meta_addr.high_part);

                        REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
                                        PRIMARY_META_SURFACE_ADDRESS,
                                        address->grph_stereo.left_meta_addr.low_part);
                }

                REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, 0,
                                SECONDARY_SURFACE_ADDRESS_HIGH_C,
                                address->grph_stereo.right_alpha_addr.high_part);

                REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_C, 0,
                                SECONDARY_SURFACE_ADDRESS_C,
                                address->grph_stereo.right_alpha_addr.low_part);

                REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
                                SECONDARY_SURFACE_ADDRESS_HIGH,
                                address->grph_stereo.right_addr.high_part);

                REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,
                                SECONDARY_SURFACE_ADDRESS,
                                address->grph_stereo.right_addr.low_part);

                REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
                                PRIMARY_SURFACE_ADDRESS_HIGH_C,
                                address->grph_stereo.left_alpha_addr.high_part);

                REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
                                PRIMARY_SURFACE_ADDRESS_C,
                                address->grph_stereo.left_alpha_addr.low_part);

                REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
                                PRIMARY_SURFACE_ADDRESS_HIGH,
                                address->grph_stereo.left_addr.high_part);

                REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
                                PRIMARY_SURFACE_ADDRESS,
                                address->grph_stereo.left_addr.low_part);
                break;
        case PLN_ADDR_TYPE_RGBEA:
                if (address->rgbea.addr.quad_part == 0
                                || address->rgbea.alpha_addr.quad_part == 0)
                        break;

                REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
                                PRIMARY_SURFACE_TMZ, address->tmz_surface,
                                PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
                                PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
                                PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);

                if (address->rgbea.meta_addr.quad_part != 0) {

                        REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
                                        PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
                                        address->rgbea.alpha_meta_addr.high_part);

                        REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
                                        PRIMARY_META_SURFACE_ADDRESS_C,
                                        address->rgbea.alpha_meta_addr.low_part);

                        REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
                                        PRIMARY_META_SURFACE_ADDRESS_HIGH,
                                        address->rgbea.meta_addr.high_part);

                        REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
                                        PRIMARY_META_SURFACE_ADDRESS,
                                        address->rgbea.meta_addr.low_part);
                }

                REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
                                PRIMARY_SURFACE_ADDRESS_HIGH_C,
                                address->rgbea.alpha_addr.high_part);

                REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
                                PRIMARY_SURFACE_ADDRESS_C,
                                address->rgbea.alpha_addr.low_part);

                REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
                                PRIMARY_SURFACE_ADDRESS_HIGH,
                                address->rgbea.addr.high_part);

                REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
                                PRIMARY_SURFACE_ADDRESS,
                                address->rgbea.addr.low_part);
                break;
        default:
                BREAK_TO_DEBUGGER();
                break;
        }

        hubp->request_address = *address;

        return true;
}

struct hubp_funcs dcn42_hubp_funcs = {
        .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
        .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
        .hubp_program_surface_flip_and_addr = hubp42_program_surface_flip_and_addr,
        .hubp_program_surface_config = hubp42_program_surface_config,
        .hubp_is_flip_pending = hubp2_is_flip_pending,
        .hubp_setup2 = hubp42_setup,
        .hubp_setup_interdependent2 = hubp401_setup_interdependent,
        .hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings,
        .set_blank = hubp2_set_blank,
        .set_blank_regs = hubp2_set_blank_regs,
        .dcc_control = hubp3_dcc_control,
        .hubp_reset = hubp_reset,
        .mem_program_viewport = min_set_viewport,
        .set_cursor_attributes  = hubp32_cursor_set_attributes,
        .set_cursor_position    = hubp401_cursor_set_position,
        .hubp_clk_cntl = hubp2_clk_cntl,
        .hubp_vtg_sel = hubp2_vtg_sel,
        .dmdata_set_attributes = hubp3_dmdata_set_attributes,
        .dmdata_load = hubp2_dmdata_load,
        .dmdata_status_done = hubp2_dmdata_status_done,
        .hubp_read_state = hubp42_read_state,
        .hubp_clear_underflow = hubp2_clear_underflow,
        .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
        .hubp_init = hubp42_init,
        .set_unbounded_requesting = hubp31_set_unbounded_requesting,
        .hubp_soft_reset = hubp31_soft_reset,
        .hubp_set_flip_int = hubp1_set_flip_int,
        .hubp_in_blank = hubp1_in_blank,
        .program_extended_blank = hubp31_program_extended_blank_value,
        .hubp_update_3dlut_fl_bias_scale = hubp401_update_3dlut_fl_bias_scale,
        .hubp_program_3dlut_fl_mode = hubp401_program_3dlut_fl_mode,
        .hubp_program_3dlut_fl_format = hubp401_program_3dlut_fl_format,
        .hubp_program_3dlut_fl_addr = hubp401_program_3dlut_fl_addr,
        .hubp_program_3dlut_fl_dlg_param = hubp401_program_3dlut_fl_dlg_param,
        .hubp_enable_3dlut_fl = hubp401_enable_3dlut_fl,
        .hubp_program_3dlut_fl_addressing_mode = hubp401_program_3dlut_fl_addressing_mode,
        .hubp_program_3dlut_fl_width = hubp401_program_3dlut_fl_width,
        .hubp_program_3dlut_fl_tmz_protected = hubp401_program_3dlut_fl_tmz_protected,
        .hubp_program_3dlut_fl_crossbar = hubp42_program_3dlut_fl_crossbar,
        .hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done,
        .hubp_clear_tiling = hubp3_clear_tiling,
        .hubp_program_3dlut_fl_config = hubp401_program_3dlut_fl_config,
        .hubp_read_reg_state = hubp3_read_reg_state
};

bool hubp42_construct(
        struct dcn20_hubp *hubp2,
        struct dc_context *ctx,
        uint32_t inst,
        const struct dcn_hubp2_registers *hubp_regs,
        const struct dcn_hubp2_shift *hubp_shift,
        const struct dcn_hubp2_mask *hubp_mask)
{
        hubp2->base.funcs = &dcn42_hubp_funcs;
        hubp2->base.ctx = ctx;
        hubp2->hubp_regs = hubp_regs;
        hubp2->hubp_shift = hubp_shift;
        hubp2->hubp_mask = hubp_mask;
        hubp2->base.inst = inst;
        hubp2->base.opp_id = OPP_ID_INVALID;
        hubp2->base.mpcc_id = 0xf;

        return true;
}


void hubp42_read_state(struct hubp *hubp)
{
        struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
        struct dcn_hubp_state *s = &hubp2->state;
        struct dcn_fl_regs_st *fl_regs = &s->fl_regs;

        hubp401_read_state(hubp);

        /* CONTROL */
        REG_GET_5(HUBP_3DLUT_CONTROL,
                        HUBP_3DLUT_ENABLE, &fl_regs->lut_enable,
                        HUBP_3DLUT_DONE, &fl_regs->lut_done,
                        HUBP_3DLUT_ADDRESSING_MODE, &fl_regs->lut_addr_mode,
                        HUBP_3DLUT_WIDTH, &fl_regs->lut_width,
                        HUBP_3DLUT_MPC_WIDTH, &fl_regs->lut_mpc_width);

        REG_GET_4(HUBP_3DLUT_CONTROL,
                        HUBP_3DLUT_TMZ, &fl_regs->lut_tmz,
                        HUBP_3DLUT_CROSSBAR_SEL_R, &fl_regs->lut_crossbar_sel_r,
                        HUBP_3DLUT_CROSSBAR_SEL_G, &fl_regs->lut_crossbar_sel_g,
                        HUBP_3DLUT_CROSSBAR_SEL_B, &fl_regs->lut_crossbar_sel_b);

        /* ADDR */
        REG_GET(HUBP_3DLUT_ADDRESS_HIGH,
                        HUBP_3DLUT_ADDRESS_HIGH, &fl_regs->lut_addr_hi);
        REG_GET(HUBP_3DLUT_ADDRESS_LOW,
                        HUBP_3DLUT_ADDRESS_LOW, &fl_regs->lut_addr_lo);
        /* CLK */
        REG_GET(HUBP_3DLUT_DLG_PARAM,
                        REFCYC_PER_3DLUT_GROUP, &fl_regs->refcyc_3dlut_group);
        /* FL */
        REG_GET_2(_3DLUT_FL_BIAS_SCALE,
                HUBP0_3DLUT_FL_BIAS, &fl_regs->lut_fl_bias,
                HUBP0_3DLUT_FL_SCALE, &fl_regs->lut_fl_scale);
        REG_GET_2(_3DLUT_FL_CONFIG,
                HUBP0_3DLUT_FL_MODE, &fl_regs->lut_fl_mode,
                HUBP0_3DLUT_FL_FORMAT, &fl_regs->lut_fl_format);
}