arch/arm/crypto/ghash-ce-glue.c

293

if (unlikely(len / SZ_4K > (len - n) / SZ_4K)) {

arch/arm/include/asm/thread_info.h

34

#define OVERFLOW_STACK_SIZE SZ_4K

arch/arm/mach-bcm/board_bcmbca.c

12

.length = SZ_4K,

arch/arm/mach-davinci/common.c

33

base = ioremap(soc_info->jtag_id_reg, SZ_4K);

arch/arm/mach-davinci/da850.c

362

da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);

arch/arm/mach-davinci/da850.c

366

da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);

arch/arm/mach-davinci/da8xx.h

35

#define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K)

arch/arm/mach-davinci/mux.c

44

pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K);

arch/arm/mach-davinci/pm.c

133

pm_config.cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);

arch/arm/mach-davinci/pm.c

137

pm_config.ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K);

arch/arm/mach-davinci/pm.c

143

pm_config.ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);

arch/arm/mach-exynos/platsmp.c

179

scu_base = ioremap(scu_a9_get_base(), SZ_4K);

arch/arm/mach-footbridge/ebsa285.c

76

xbus = ioremap(XBUS_CS2, SZ_4K);

arch/arm/mach-gemini/board-dt.c

20

.length = SZ_4K,

arch/arm/mach-highbank/highbank.c

38

scu_base_addr = ioremap(base, SZ_4K);

arch/arm/mach-hisi/platsmp.c

46

scu_base = ioremap(base, SZ_4K);

arch/arm/mach-imx/platsmp.c

25

.length = SZ_4K,

arch/arm/mach-nomadik/cpu-8815.c

64

.length = SZ_4K,

arch/arm/mach-nomadik/cpu-8815.c

76

void __iomem *srcbase = ioremap(NOMADIK_SRC_BASE, SZ_4K);

arch/arm/mach-omap2/iomap.h

89

#define DSP_IPI_2420_SIZE SZ_4K

arch/arm/mach-omap2/iomap.h

93

#define DSP_MMU_2420_SIZE SZ_4K

arch/arm/mach-omap2/omap4-common.c

255

l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);

arch/arm/mach-pxa/spitz.c

903

.end = PXA_CS3_PHYS + SZ_4K - 1,

arch/arm/mach-rockchip/pm.c

55

rkpm_bootdata_cpusp = rk3288_bootram_phy + (SZ_4K - 8);

arch/arm/mach-s3c/devs.c

113

[0] = DEFINE_RES_MEM(S3C_PA_HSMMC1, SZ_4K),

arch/arm/mach-s3c/devs.c

145

[0] = DEFINE_RES_MEM(S3C_PA_HSMMC2, SZ_4K),

arch/arm/mach-s3c/devs.c

175

[0] = DEFINE_RES_MEM(S3C_PA_HSMMC3, SZ_4K),

arch/arm/mach-s3c/devs.c

206

[0] = DEFINE_RES_MEM(S3C_PA_IIC, SZ_4K),

arch/arm/mach-s3c/devs.c

241

[0] = DEFINE_RES_MEM(S3C_PA_IIC1, SZ_4K),

arch/arm/mach-s3c/devs.c

298

DEFINE_RES_MEM(SAMSUNG_PA_TIMER, SZ_4K),

arch/arm/mach-s3c/devs.c

83

[0] = DEFINE_RES_MEM(S3C_PA_HSMMC0, SZ_4K),

arch/arm/mach-s3c/mach-s3c64xx-dt.c

25

.length = SZ_4K,

arch/arm/mach-s3c/map-s3c64xx.h

83

#define S3C64XX_SZ_GPIO SZ_4K

arch/arm/mach-s3c/s3c64xx.c

102

.length = SZ_4K,

arch/arm/mach-s3c/s3c64xx.c

107

.length = SZ_4K,

arch/arm/mach-s3c/s3c64xx.c

112

.length = SZ_4K,

arch/arm/mach-s3c/s3c64xx.c

132

.length = SZ_4K,

arch/arm/mach-s3c/s3c64xx.c

137

.length = SZ_4K,

arch/arm/mach-s3c/s3c64xx.c

142

.length = SZ_4K,

arch/arm/mach-sa1100/collie.c

57

[0] = DEFINE_RES_MEM(0x40800000, SZ_4K),

arch/arm/mach-sa1100/h3xxx.c

203

DEFINE_RES_MEM(0x80010000, SZ_4K),

arch/arm/mach-sa1100/h3xxx.c

204

DEFINE_RES_MEM(0x80020000, SZ_4K),

arch/arm/mach-sa1100/neponset.c

285

d->base = ioremap(nep_res->start, SZ_4K);

arch/arm/mach-shmobile/smp-r8a7779.c

43

if (!request_mem_region(0, SZ_4K, "Boot Area")) {

arch/arm/mach-shmobile/smp-sh73a0.c

49

if (!request_mem_region(0, SZ_4K, "Boot Area")) {

arch/arm/mach-spear/spear13xx.c

77

.length = SZ_4K,

arch/arm/mach-tegra/iomap.h

23

#define TEGRA_ARM_INT_DIST_SIZE SZ_4K

arch/arm/mach-tegra/iomap.h

41

#define TEGRA_CLK_RESET_SIZE SZ_4K

arch/arm/mach-tegra/iomap.h

50

#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K

arch/arm/mach-tegra/iomap.h

53

#define TEGRA_APB_MISC_SIZE SZ_4K

arch/arm/mach-tegra/irammap.h

19

#define TEGRA_IRAM_LPx_RESUME_AREA (TEGRA_IRAM_BASE + SZ_4K)

arch/arm/mach-versatile/integrator_ap.c

48

.length = SZ_4K,

arch/arm/mach-versatile/integrator_ap.c

53

.length = SZ_4K,

arch/arm/mach-versatile/integrator_cp.c

41

.length = SZ_4K,

arch/arm/mach-versatile/integrator_cp.c

46

.length = SZ_4K,

arch/arm/mach-versatile/integrator_cp.c

51

.length = SZ_4K,

arch/arm/mach-versatile/versatile.c

95

.length = SZ_4K * 9,

arch/arm/mm/cache-l2x0.c

1524

.way_size_0 = SZ_4K,

arch/arm/mm/cache-l2x0.c

1545

.way_size_0 = SZ_4K,

arch/arm/plat-orion/common.c

711

fill_resources_irq(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1,

arch/arm/plat-orion/common.c

736

mapbase, SZ_4K - 1, irq);

arch/arm/plat-orion/common.c

760

mapbase, SZ_4K - 1, irq);

arch/arm64/include/asm/kvm_nested.h

256

case SZ_4K: \

arch/arm64/include/asm/memory.h

142

#define OVERFLOW_STACK_SIZE SZ_4K

arch/arm64/include/asm/pgtable.h

1612

return PAGE_SIZE == SZ_4K;

arch/arm64/include/asm/tlbflush.h

72

case SZ_4K:

arch/arm64/kernel/alternative.c

90

target = align_down(altinsnptr, SZ_4K) + orig_offset;

arch/arm64/kernel/alternative.c

91

new_offset = target - align_down(insnptr, SZ_4K);

arch/arm64/kernel/module-plts.c

19

add = aarch64_insn_gen_add_sub_imm(reg, reg, dst % SZ_4K,

arch/arm64/kernel/module-plts.c

229

if (min_align > SZ_4K)

arch/arm64/kernel/module-plts.c

243

ret += DIV_ROUND_UP(ret, (SZ_4K / sizeof(struct plt_entry)));

arch/arm64/kernel/module-plts.c

55

p = ALIGN_DOWN((u64)a, SZ_4K);

arch/arm64/kernel/module-plts.c

56

q = ALIGN_DOWN((u64)b, SZ_4K);

arch/arm64/kernel/static_call.c

15

literal = ALIGN_DOWN((u64)tramp + 4, SZ_4K) +

arch/arm64/kvm/at.c

296

case SZ_4K:

arch/arm64/kvm/at.c

496

case SZ_4K:

arch/arm64/kvm/at.c

50

case SZ_4K:

arch/arm64/kvm/at.c

67

case SZ_4K:

arch/arm64/kvm/hyp/nvhe/ffa.c

749

min_rxtx_sz = SZ_4K;

arch/arm64/kvm/nested.c

1580

case SZ_4K:

arch/arm64/kvm/nested.c

1592

case SZ_4K:

arch/arm64/kvm/nested.c

172

case SZ_4K:

arch/arm64/kvm/nested.c

261

case SZ_4K:

arch/arm64/kvm/nested.c

446

max_size = SZ_4K;

arch/arm64/kvm/nested.c

540

if (sz < SZ_4K) sz = SZ_4K;

arch/arm64/kvm/vgic/vgic-kvm-device.c

116

alignment = SZ_4K;

arch/arm64/kvm/vgic/vgic-kvm-device.c

122

alignment = SZ_4K;

arch/arm64/kvm/vgic/vgic-kvm-device.c

57

SZ_4K, KVM_VGIC_V2_DIST_SIZE);

arch/arm64/kvm/vgic/vgic-kvm-device.c

65

SZ_4K, KVM_VGIC_V2_CPU_SIZE);

arch/arm64/kvm/vgic/vgic-mmio-v2.c

508

return SZ_4K;

arch/arm64/kvm/vgic/vgic-v2.c

460

KVM_VGIC_V2_CPU_SIZE - SZ_4K, true);

arch/arm64/lib/insn.c

1220

offset = (addr - ALIGN_DOWN(pc, SZ_4K)) >> 12;

arch/arm64/lib/insn.c

799

if (imm & ~(SZ_4K - 1)) {

arch/arm64/lib/insn.c

801

if (imm & (SZ_4K - 1))

arch/powerpc/include/asm/nohash/32/pte-8xx.h

154

return SZ_4K;

arch/powerpc/include/asm/nohash/32/pte-8xx.h

178

return PAGE_SIZE / SZ_4K;

arch/powerpc/include/asm/nohash/32/pte-8xx.h

180

return SZ_4M / SZ_4K;

arch/powerpc/include/asm/nohash/32/pte-8xx.h

182

return SZ_16K / SZ_4K;

arch/powerpc/include/asm/nohash/32/pte-8xx.h

184

return SZ_512K / SZ_4K;

arch/powerpc/include/asm/nohash/32/pte-8xx.h

198

for (i = 0; i < num; i += PAGE_SIZE / SZ_4K, new += PAGE_SIZE) {

arch/powerpc/include/uapi/asm/papr-indices.h

10

#define RTAS_GET_INDICES_BUF_SIZE SZ_4K

arch/powerpc/kernel/rtas.c

767

char rtas_data_buf[RTAS_DATA_BUF_SIZE] __aligned(SZ_4K);

arch/powerpc/kvm/book3s_64_vio.c

652

if (tce_list & (SZ_4K - 1))

arch/powerpc/kvm/book3s_hv.c

1014

u64 pg_sz = SZ_4K; /* 4K page size */

arch/powerpc/kvm/book3s_hv.c

1015

u64 pg_mask = SZ_4K - 1;

arch/powerpc/kvm/book3s_hv_rm_mmu.c

945

for (i = 0; i < SZ_4K; i += L1_CACHE_BYTES, pa += L1_CACHE_BYTES)

arch/powerpc/kvm/book3s_hv_rm_mmu.c

976

memcpy((void *)dest_pa, (void *)src_pa, SZ_4K);

arch/powerpc/kvm/book3s_hv_rm_mmu.c

989

u64 pg_mask = SZ_4K - 1; /* 4K page size */

arch/powerpc/mm/book3s64/iommu_api.c

25

#define MM_IOMMU_TABLE_GROUP_PAGE_MASK ~(SZ_4K - 1)

arch/powerpc/mm/pgtable.c

331

for (i = 0; i < num; i++, entry++, val += SZ_4K)

arch/powerpc/platforms/powernv/pci-ioda-tce.c

30

mask = SZ_4K | SZ_64K;

arch/powerpc/platforms/pseries/dlpar.c

151

work_area = rtas_work_area_alloc(SZ_4K);

arch/powerpc/platforms/pseries/iommu.c

1384

__builtin_ctzll(SZ_4K), __builtin_ctzll(SZ_64K), __builtin_ctzll(SZ_16M),

arch/powerpc/platforms/pseries/iommu.c

1786

(SZ_4K), (SZ_64K), (SZ_16M),

arch/powerpc/platforms/pseries/iommu.c

86

table_group->pgsizes = SZ_4K;

arch/powerpc/platforms/pseries/papr-hvpipe.c

187

work_area = rtas_work_area_alloc(SZ_4K);

arch/powerpc/platforms/pseries/papr-hvpipe.c

282

work_area = rtas_work_area_alloc(SZ_4K);

arch/powerpc/platforms/pseries/papr-hvpipe.c

291

work_buf = rtas_work_area_alloc(SZ_4K);

arch/powerpc/platforms/pseries/papr-phy-attest.c

149

param->work_area = rtas_work_area_alloc(SZ_4K);

arch/powerpc/platforms/pseries/papr-platform-dump.c

329

params->work_area = rtas_work_area_alloc(SZ_4K);

arch/powerpc/platforms/pseries/papr-platform-dump.c

330

params->buf_length = SZ_4K;

arch/powerpc/platforms/pseries/papr-vpd.c

147

vpd_params->work_area = rtas_work_area_alloc(SZ_4K);

arch/powerpc/platforms/pseries/rtas-work-area.c

58

static char early_work_area_buf[SZ_4K] __initdata __aligned(SZ_4K);

arch/riscv/include/asm/thread_info.h

36

#define OVERFLOW_STACK_SIZE SZ_4K

arch/riscv/mm/init.c

1164

BUG_ON((kernel_map.virt_addr + kernel_map.size) > ADDRESS_SPACE_END - SZ_4K);

arch/sh/boards/mach-sdk7786/sram.c

44

phys = (area << 26) + SZ_64M - SZ_4K;

arch/x86/virt/svm/sev.c

107

#define RST_SIZE SZ_4K

drivers/accel/amdxdna/aie2_msg_priv.h

364

#define MAX_CHAIN_CMDBUF_SIZE SZ_4K

drivers/accel/amdxdna/aie2_pci.c

1039

if (args->element_size > SZ_4K || args->num_element > SZ_1K) {

drivers/accel/ivpu/ivpu_coredump.c

15

#define CRASH_DUMP_HEADERS_SIZE SZ_4K

drivers/accel/ivpu/ivpu_fw.c

22

#define FW_PREEMPT_BUF_MIN_SIZE SZ_4K

drivers/accel/ivpu/ivpu_fw.c

224

boot_params_size = SZ_4K;

drivers/accel/ivpu/ivpu_fw.c

232

fw_version_size = ALIGN(fw_hdr->firmware_version_size, SZ_4K);

drivers/accel/ivpu/ivpu_fw.c

234

if (fw_version_size != SZ_4K) {

drivers/accel/ivpu/ivpu_fw.c

271

if (!ivpu_is_within_range(fw_hdr->entry_point, SZ_4K, &fw_image_range)) {

drivers/accel/ivpu/ivpu_fw.h

12

#define FW_VERSION_HEADER_SIZE SZ_4K

drivers/accel/ivpu/ivpu_job.c

105

cmdq->mem = ivpu_bo_create_global(vdev, SZ_4K, DRM_IVPU_BO_WC | DRM_IVPU_BO_MAPPABLE);

drivers/accel/ivpu/ivpu_mmu_context.c

33

#define IVPU_MMU_PAGE_SIZE SZ_4K

drivers/accel/qaic/mhi_controller.c

853

mhi_cntrl->reg_len = SZ_4K;

drivers/accel/qaic/qaic.h

23

#define QAIC_DBC_SIZE SZ_4K

drivers/accel/qaic/qaic_control.c

33

#define QAIC_DBC_Q_BUF_ALIGN SZ_4K

drivers/accel/qaic/qaic_control.c

35

#define QAIC_WRAPPER_MAX_SIZE SZ_4K

drivers/acpi/arm64/apmt.c

33

res[num_res].end = node->base_address0 + SZ_4K - 1;

drivers/acpi/arm64/apmt.c

40

res[num_res].end = node->base_address1 + SZ_4K - 1;

drivers/acpi/arm64/gtdt.c

230

timer_mem->size = SZ_4K;

drivers/acpi/arm64/gtdt.c

280

frame->size = SZ_4K;

drivers/acpi/arm64/gtdt.c

320

DEFINE_RES_MEM(wd->control_frame_address, SZ_4K),

drivers/acpi/arm64/gtdt.c

321

DEFINE_RES_MEM(wd->refresh_frame_address, SZ_4K),

drivers/acpi/arm64/iort.c

1816

res[0].end = pmcg->page0_base_address + SZ_4K - 1;

drivers/acpi/arm64/iort.c

1826

res[1].end = pmcg->page1_base_address + SZ_4K - 1;

drivers/block/rnbd/rnbd-clt.c

1375

.virt_boundary_mask = SZ_4K - 1,

drivers/block/zloop.c

863

if (file_inode(zone->file)->i_sb->s_blocksize <= SZ_4K)

drivers/clk/hisilicon/clk-hi3559a.c

678

crg_base = ioremap(CRG_BASE_ADDR, SZ_4K);

drivers/clk/imx/clk-imx35.c

91

base = ioremap(MX35_CCM_BASE_ADDR, SZ_4K);

drivers/clk/ux500/clk-prcc.c

113

clk->base = ioremap(phy_base, SZ_4K);

drivers/clk/ux500/reset-prcc.c

166

ur->base[i] = ioremap(ur->phy_base[i], SZ_4K);

drivers/crypto/ccp/sev-dev-tio.c

24

#define SLA_SZ(s) ((s).page_size == SLA_PAGE_SIZE_2M ? SZ_2M : SZ_4K)

drivers/crypto/ccp/sev-dev-tio.c

319

if (WARN_ON_ONCE(SLA_SZ(scatter[i]) > SZ_4K))

drivers/crypto/ccp/sev-dev-tio.c

441

BUILD_BUG_ON(PAGE_SIZE < SZ_4K);

drivers/crypto/hisilicon/qm.c

1233

case SZ_4K:

drivers/crypto/tegra/tegra-se-main.c

217

se->cmdbuf = tegra_se_host1x_bo_alloc(se, SZ_4K);

drivers/crypto/tegra/tegra-se-main.c

223

se->keybuf = tegra_se_host1x_bo_alloc(se, SZ_4K);

drivers/cxl/core/regs.c

494

if (!request_mem_region(rcrb, SZ_4K, dev_name(dev)))

drivers/cxl/core/regs.c

497

addr = ioremap(rcrb, SZ_4K);

drivers/cxl/core/regs.c

516

release_mem_region(rcrb, SZ_4K);

drivers/cxl/core/regs.c

528

if (!request_mem_region(rcrb, SZ_4K, "CXL RCRB"))

drivers/cxl/core/regs.c

531

addr = ioremap(rcrb, SZ_4K);

drivers/cxl/core/regs.c

534

release_mem_region(rcrb, SZ_4K);

drivers/cxl/core/regs.c

542

if (offset == 0 || offset > SZ_4K) {

drivers/cxl/core/regs.c

550

release_mem_region(rcrb, SZ_4K);

drivers/cxl/core/regs.c

587

rcrb += SZ_4K;

drivers/cxl/core/regs.c

595

if (!request_mem_region(rcrb, SZ_4K, "CXL RCRB"))

drivers/cxl/core/regs.c

597

addr = ioremap(rcrb, SZ_4K);

drivers/cxl/core/regs.c

600

release_mem_region(rcrb, SZ_4K);

drivers/cxl/core/regs.c

608

release_mem_region(rcrb, SZ_4K);

drivers/dma/ste_dma40.c

3151

pid |= (readl(virtbase + SZ_4K - 0x20 + 4 * i)

drivers/dma/ste_dma40.c

3154

cid |= (readl(virtbase + SZ_4K - 0x10 + 4 * i)

drivers/dpll/zl3073x/flash.c

234

*sector_size = SZ_4K;

drivers/firmware/arm_ffa/driver.c

2036

size_t rxtx_bufsz = SZ_4K;

drivers/firmware/arm_ffa/driver.c

2063

rxtx_bufsz = SZ_4K;

drivers/firmware/arm_scmi/transports/smc.c

37

#define SHMEM_SIZE (SZ_4K)

drivers/firmware/efi/efi.c

1143

rc = efi_mem_reserve_iomem(__pa(rsv), SZ_4K);

drivers/firmware/efi/efi.c

1155

rsv->size = EFI_MEMRESERVE_COUNT(SZ_4K);

drivers/firmware/imx/sm-misc.c

54

void *syslog __free(kfree) = kmalloc(SZ_4K, GFP_KERNEL);

drivers/firmware/imx/sm-misc.c

56

u16 size = SZ_4K / 4;

drivers/firmware/meson/meson_sm.c

40

.shmem_size = SZ_4K,

drivers/firmware/qcom/qcom_qseecom_uefisecapp.c

818

pool_config.initial_size = SZ_4K;

drivers/firmware/tegra/bpmp-tegra186.c

216

priv->rx.phys = res.start + SZ_4K;

drivers/firmware/tegra/bpmp-tegra186.c

226

priv->rx.dram = priv->tx.dram + SZ_4K;

drivers/firmware/turris-mox-rwtm.c

34

#define RWTM_DMA_BUFFER_SIZE SZ_4K

drivers/fpga/altera-cvp.c

467

if (altera_cvp_chkcfg && !(done % SZ_4K)) {

drivers/fpga/altera-ps-spi.c

177

size_t stride = min_t(size_t, fw_data_end - fw_data, SZ_4K);

drivers/fpga/xilinx-spi.c

32

stride = min_t(size_t, remaining, SZ_4K);

drivers/gpu/drm/arm/malidp_hw.c

586

hwdev->max_line_size = SZ_4K;

drivers/gpu/drm/arm/malidp_hw.c

922

hwdev->max_line_size = SZ_4K;

drivers/gpu/drm/arm/malidp_planes.c

65

#define MALIDP_MMU_PREFETCH_PARTIAL_PGSIZES (SZ_4K | SZ_64K)

drivers/gpu/drm/drm_buddy.c

307

if (chunk_size < SZ_4K)

drivers/gpu/drm/drm_gpusvm.c

916

if (end - start != SZ_4K) {

drivers/gpu/drm/etnaviv/etnaviv_cmdbuf.c

14

#define SUBALLOC_GRANULE SZ_4K

drivers/gpu/drm/etnaviv/etnaviv_gem.c

599

etnaviv_obj->size = ALIGN(size, SZ_4K);

drivers/gpu/drm/etnaviv/etnaviv_gpu.c

886

ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer, SZ_4K);

drivers/gpu/drm/etnaviv/etnaviv_iommu.c

165

drm_mm_init(&context->mm, GPU_MEM_START, PT_ENTRIES * SZ_4K);

drivers/gpu/drm/etnaviv/etnaviv_iommu.c

52

unsigned int index = (iova - GPU_MEM_START) / SZ_4K;

drivers/gpu/drm/etnaviv/etnaviv_iommu.c

54

if (size != SZ_4K)

drivers/gpu/drm/etnaviv/etnaviv_iommu.c

66

unsigned int index = (iova - GPU_MEM_START) / SZ_4K;

drivers/gpu/drm/etnaviv/etnaviv_iommu.c

68

if (size != SZ_4K)

drivers/gpu/drm/etnaviv/etnaviv_iommu.c

73

return SZ_4K;

drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c

100

if (size != SZ_4K)

drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c

127

if (size != SZ_4K)

drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c

135

return SZ_4K;

drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c

141

size_t dump_size = SZ_4K;

drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c

146

dump_size += SZ_4K;

drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c

156

memcpy(buf, v2_context->mtlb_cpu, SZ_4K);

drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c

157

buf += SZ_4K;

drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c

160

memcpy(buf, v2_context->stlb_cpu[i], SZ_4K);

drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c

161

buf += SZ_4K;

drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c

290

v2_context->mtlb_cpu = dma_alloc_wc(global->dev, SZ_4K,

drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c

305

drm_mm_init(&context->mm, SZ_4K, (u64)SZ_1G * 4 - SZ_4K);

drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c

56

dma_free_wc(context->global->dev, SZ_4K,

drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c

61

dma_free_wc(context->global->dev, SZ_4K, v2_context->mtlb_cpu,

drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c

76

dma_alloc_wc(v2_context->base.global->dev, SZ_4K,

drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c

84

SZ_4K / sizeof(u32));

drivers/gpu/drm/etnaviv/etnaviv_mmu.c

22

size_t pgsize = SZ_4K;

drivers/gpu/drm/etnaviv/etnaviv_mmu.c

40

size_t pgsize = SZ_4K;

drivers/gpu/drm/etnaviv/etnaviv_mmu.c

501

global->bad_page_cpu = dma_alloc_wc(dev, SZ_4K, &global->bad_page_dma,

drivers/gpu/drm/etnaviv/etnaviv_mmu.c

506

memset32(global->bad_page_cpu, 0xdead55aa, SZ_4K / sizeof(u32));

drivers/gpu/drm/etnaviv/etnaviv_mmu.c

530

dma_free_wc(dev, SZ_4K, global->bad_page_cpu, global->bad_page_dma);

drivers/gpu/drm/etnaviv/etnaviv_mmu.c

553

dma_free_wc(global->dev, SZ_4K,

drivers/gpu/drm/etnaviv/etnaviv_mmu.c

81

if (!IS_ALIGNED(iova | pa | bytes, SZ_4K)) {

drivers/gpu/drm/etnaviv/etnaviv_mmu.h

37

#define ETNAVIV_PTA_SIZE SZ_4K

drivers/gpu/drm/i915/gem/selftests/huge_pages.c

1477

{ SZ_2M - SZ_4K, SZ_64K | SZ_4K },

drivers/gpu/drm/i915/gem/selftests/huge_pages.c

1478

{ SZ_2M + SZ_4K, SZ_64K | SZ_4K },

drivers/gpu/drm/i915/gem/selftests/huge_pages.c

1479

{ SZ_2M + SZ_4K, SZ_2M | SZ_4K },

drivers/gpu/drm/i915/gem/selftests/huge_pages.c

1658

sz = max_t(u32, sz, SZ_4K);

drivers/gpu/drm/i915/gem/selftests/huge_pages.c

438

unsigned int combination = SZ_4K; /* Required for ppGTT */

drivers/gpu/drm/i915/gem/selftests/huge_pages.c

877

.size = SZ_64K + SZ_4K,

drivers/gpu/drm/i915/gem/selftests/huge_pages.c

882

.size = SZ_64K - SZ_4K,

drivers/gpu/drm/i915/gem/selftests/huge_pages.c

892

.size = SZ_2M - SZ_4K,

drivers/gpu/drm/i915/gem/selftests/huge_pages.c

897

.size = SZ_2M + SZ_4K,

drivers/gpu/drm/i915/gt/gen2_engine_cs.c

185

#define I830_WA_SIZE max(I830_TLB_ENTRIES * SZ_4K, I830_BATCH_LIMIT)

drivers/gpu/drm/i915/gt/gen6_ppgtt.c

392

I915_PDES * SZ_4K);

drivers/gpu/drm/i915/gt/gen6_ppgtt.c

441

ppgtt->base.vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen6_pte_t));

drivers/gpu/drm/i915/gt/gen7_renderclear.c

388

batch_init(&state, vma, start, bv->state_start, SZ_4K);

drivers/gpu/drm/i915/gt/gen7_renderclear.c

86

bv->state_start = round_up(SZ_1K + num_primitives(bv) * 64, SZ_4K);

drivers/gpu/drm/i915/gt/gen7_renderclear.c

87

bv->surface_start = bv->state_start + SZ_4K;

drivers/gpu/drm/i915/gt/gen8_ppgtt.c

1015

ppgtt->vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen8_pte_t));

drivers/gpu/drm/i915/gt/gen8_ppgtt.c

137

#define GEN8_PAGE_SIZE (SZ_4K) /* page and page-directory sizes are the same */

drivers/gpu/drm/i915/gt/intel_context.c

403

ce->ring_size = SZ_4K;

drivers/gpu/drm/i915/gt/intel_engine_cs.c

1423

return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K,

drivers/gpu/drm/i915/gt/intel_gt.c

701

GRAPHICS_VER(gt->i915) == 2 ? SZ_256K : SZ_4K);

drivers/gpu/drm/i915/gt/intel_wopcm.c

63

#define ICL_WOPCM_HW_CTX_RESERVED (SZ_32K + SZ_4K)

drivers/gpu/drm/i915/gt/selftest_execlists.c

2947

n * SZ_4K / 4, SZ_4K);

drivers/gpu/drm/i915/gt/selftest_migrate.c

15

SZ_4K,

drivers/gpu/drm/i915/gt/selftest_migrate.c

18

CHUNK_SZ - SZ_4K,

drivers/gpu/drm/i915/gt/selftest_migrate.c

20

CHUNK_SZ + SZ_4K,

drivers/gpu/drm/i915/gt/selftest_migrate.c

584

ce->ring_size = SZ_4K; /* Not too big */

drivers/gpu/drm/i915/gt/selftest_migrate.c

895

SZ_4K,

drivers/gpu/drm/i915/gt/selftest_migrate.c

978

SZ_4K,

drivers/gpu/drm/i915/gt/selftest_timeline.c

1036

err = create_watcher(&watcher[0], engine, SZ_4K);

drivers/gpu/drm/i915/gt/selftest_tlb.c

326

NULL, SZ_4K,

drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c

275

*cs++ = (gsc->local->size / SZ_4K) | HECI1_FW_LIMIT_VALID;

drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c

387

#define GSC_VER_PKT_SZ SZ_4K

drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c

226

ce = intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K,

drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c

1015

buf = kmalloc(SZ_4K, GFP_NOWAIT);

drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c

1017

buf, SZ_4K, 0)) {

drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c

85

#define CTB_H2G_BUFFER_SIZE (SZ_4K)

drivers/gpu/drm/i915/gt/uc/intel_guc_log.c

82

log->sizes[i].units = SZ_4K;

drivers/gpu/drm/i915/pxp/intel_pxp.c

102

ce = intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K,

drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h

21

#define PXP43_HUC_AUTH_INOUT_SIZE (SZ_4K)

drivers/gpu/drm/i915/selftests/intel_memory_region.c

1311

SZ_4K,

drivers/gpu/drm/i915/selftests/intel_memory_region.c

561

ps = SZ_4K;

drivers/gpu/drm/imagination/pvr_fw.c

100

if (firmware->size < SZ_4K || (firmware->size % FW_BLOCK_SIZE))

drivers/gpu/drm/imagination/pvr_fw.c

153

fw_offset = (firmware->size - SZ_4K) - header->device_info_size;

drivers/gpu/drm/imagination/pvr_fw.c

176

fw_offset = (firmware->size - SZ_4K) - pvr_dev->fw_dev.header->device_info_size;

drivers/gpu/drm/imagination/pvr_fw.c

45

#define PVR_ROGUE_FAULT_PAGE_SIZE SZ_4K

drivers/gpu/drm/imagination/pvr_fw.c

97

u32 fw_offset = firmware->size - SZ_4K;

drivers/gpu/drm/imagination/pvr_fw_info.h

15

#define FW_BLOCK_SIZE SZ_4K

drivers/gpu/drm/imagination/pvr_mmu.c

218

#define PVR_MMU_BACKING_PAGE_SIZE SZ_4K

drivers/gpu/drm/imagination/pvr_mmu.c

32

#if (PVR_DEVICE_PAGE_SIZE == SZ_4K)

drivers/gpu/drm/imagination/pvr_mmu.c

62

(PVR_DEVICE_PAGE_SHIFT - PVR_SHIFT_FROM_SIZE(SZ_4K)))

drivers/gpu/drm/imagination/pvr_rogue_fwif_client.h

17

#define ROGUE_PM_PAGE_SIZE SZ_4K

drivers/gpu/drm/imagination/pvr_vm_mips.c

40

if (pt_size > ROGUE_MIPSFW_MAX_NUM_PAGETABLE_PAGES * SZ_4K)

drivers/gpu/drm/imx/dcss/dcss-blkctl.c

49

blkctl->base_reg = devm_ioremap(dcss->dev, blkctl_base, SZ_4K);

drivers/gpu/drm/imx/dcss/dcss-ctxld.c

220

ctxld->ctxld_reg = devm_ioremap(dcss->dev, ctxld_base, SZ_4K);

drivers/gpu/drm/imx/dcss/dcss-dpr.c

138

ch->base_reg = devm_ioremap(dpr->dev, ch->base_ofs, SZ_4K);

drivers/gpu/drm/imx/dcss/dcss-dtg.c

161

dtg->base_reg = devm_ioremap(dtg->dev, dtg_base, SZ_4K);

drivers/gpu/drm/imx/dcss/dcss-scaler.c

305

ch->base_reg = devm_ioremap(scl->dev, ch->base_ofs, SZ_4K);

drivers/gpu/drm/imx/dcss/dcss-ss.c

94

ss->base_reg = devm_ioremap(ss->dev, ss_base, SZ_4K);

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

380

.fifo_size = SZ_4K,

drivers/gpu/drm/meson/meson_rdma.c

29

dma_alloc_coherent(priv->dev, SZ_4K,

drivers/gpu/drm/meson/meson_rdma.c

55

dma_free_coherent(priv->dev, SZ_4K,

drivers/gpu/drm/meson/meson_rdma.c

94

if (priv->rdma.offset >= (SZ_4K / RDMA_DESC_SIZE)) {

drivers/gpu/drm/msm/adreno/a2xx_gpummu.c

24

#define GPUMMU_PAGE_SIZE SZ_4K

drivers/gpu/drm/msm/adreno/a6xx_catalog.c

689

.gmem = (SZ_128K + SZ_4K),

drivers/gpu/drm/msm/adreno/a6xx_catalog.c

722

.gmem = (SZ_128K + SZ_4K),

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

2182

gmu->dummy.size = SZ_4K;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

2186

ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_4K * 7,

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

982

((gmu->log.size / SZ_4K - 1) & GENMASK(7, 0)));

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

987

((gmu->log.size / SZ_4K - 1) & GENMASK(7, 0)));

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

992

gmu->log.iova | (gmu->log.size / SZ_4K - 1));

drivers/gpu/drm/msm/adreno/a6xx_hfi.c

1043

header->size = SZ_4K >> 2;

drivers/gpu/drm/msm/adreno/a6xx_hfi.c

1079

offset = SZ_4K;

drivers/gpu/drm/msm/adreno/a6xx_hfi.c

1084

offset += SZ_4K;

drivers/gpu/drm/msm/dsi/dsi_host.c

2011

msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL);

drivers/gpu/drm/msm/dsi/dsi_host.c

2079

ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K);

drivers/gpu/drm/omapdrm/dss/dispc.c

42

#define DISPC_SZ_REGS SZ_4K

drivers/gpu/drm/panfrost/panfrost_mmu.c

375

*count = min_not_zero(blk_offset, size) / SZ_4K;

drivers/gpu/drm/panfrost/panfrost_mmu.c

376

return SZ_4K;

drivers/gpu/drm/panfrost/panfrost_mmu.c

812

.pgsize_bitmap = SZ_4K | SZ_2M,

drivers/gpu/drm/panthor/panthor_fw.c

511

*output = mem->kmap + SZ_4K;

drivers/gpu/drm/panthor/panthor_fw.c

513

*output_fw_va = *input_fw_va + SZ_4K;

drivers/gpu/drm/panthor/panthor_mmu.c

1050

size >= SZ_2M ? SZ_2M : SZ_4K,

drivers/gpu/drm/panthor/panthor_mmu.c

2463

.pgsize_bitmap = SZ_4K | SZ_2M,

drivers/gpu/drm/panthor/panthor_mmu.c

2948

pt_cache = kmem_cache_create("panthor-mmu-pt", SZ_4K, SZ_4K, 0, NULL);

drivers/gpu/drm/panthor/panthor_mmu.c

453

if (drm_WARN_ON(&vm->ptdev->base, size != SZ_4K))

drivers/gpu/drm/panthor/panthor_mmu.c

465

memset(page, 0, SZ_4K);

drivers/gpu/drm/panthor/panthor_mmu.c

495

if (drm_WARN_ON(&vm->ptdev->base, size != SZ_4K))

drivers/gpu/drm/panthor/panthor_mmu.c

846

*count = min_not_zero(blk_offset, size) / SZ_4K;

drivers/gpu/drm/panthor/panthor_mmu.c

847

return SZ_4K;

drivers/gpu/drm/panthor/panthor_mmu.c

898

unmapped_sz += SZ_4K;

drivers/gpu/drm/panthor/panthor_sched.c

3509

if (args->ringbuf_size < SZ_4K || args->ringbuf_size > SZ_64K ||

drivers/gpu/drm/tests/drm_buddy_test.c

140

ps = max(SZ_4K, ps);

drivers/gpu/drm/tests/drm_buddy_test.c

368

const unsigned long ps = SZ_4K;

drivers/gpu/drm/tests/drm_buddy_test.c

378

mm_size = SZ_4K << max_order;

drivers/gpu/drm/tests/drm_buddy_test.c

471

size = SZ_4K << order;

drivers/gpu/drm/tests/drm_buddy_test.c

495

mm_size = (SZ_4K << max_order) + (SZ_4K << (max_order - 2));

drivers/gpu/drm/tests/drm_buddy_test.c

499

KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, 0, SZ_4K << max_order,

drivers/gpu/drm/tests/drm_buddy_test.c

50

KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_init(&mm, mm_size, SZ_4K),

drivers/gpu/drm/tests/drm_buddy_test.c

504

KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, 0, SZ_4K << max_order,

drivers/gpu/drm/tests/drm_buddy_test.c

509

KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, SZ_4K << max_order, mm_size,

drivers/gpu/drm/tests/drm_buddy_test.c

519

const unsigned long ps = SZ_4K, mm_size = 16 * 3 * SZ_4K;

drivers/gpu/drm/tests/drm_buddy_test.c

622

mm_size = SZ_4K << max_order;

drivers/gpu/drm/tests/drm_buddy_test.c

623

KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_init(&mm, mm_size, SZ_4K),

drivers/gpu/drm/tests/drm_buddy_test.c

701

mm_size = SZ_4K << max_order;

drivers/gpu/drm/tests/drm_buddy_test.c

702

KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_init(&mm, mm_size, SZ_4K),

drivers/gpu/drm/tests/drm_buddy_test.c

795

mm_size = SZ_4K * ((1 << (max_order + 1)) - 1);

drivers/gpu/drm/tests/drm_buddy_test.c

797

KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_init(&mm, mm_size, SZ_4K),

drivers/gpu/drm/tests/drm_buddy_test.c

833

KUNIT_EXPECT_FALSE(test, drm_buddy_init(&mm, size, SZ_4K));

drivers/gpu/drm/tests/drm_buddy_test.c

867

KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_init(&mm, mm_size, SZ_4K),

drivers/gpu/drm/tests/drm_buddy_test.c

872

SZ_4K, &blocks,

drivers/gpu/drm/tests/drm_buddy_test.c

887

err = drm_buddy_alloc_blocks(&mm, 0, mm_size, size, SZ_4K, &blocks,

drivers/gpu/drm/tests/drm_buddy_test.c

99

ret = drm_buddy_init(&mm, mm_size, SZ_4K);

drivers/gpu/drm/ttm/tests/ttm_bo_validate_test.c

15

#define BO_SIZE SZ_4K

drivers/gpu/drm/ttm/tests/ttm_resource_test.c

9

#define RES_SIZE SZ_4K

drivers/gpu/drm/ttm/tests/ttm_tt_test.c

10

#define BO_SIZE SZ_4K

drivers/gpu/drm/ttm/tests/ttm_tt_test.c

21

.size = SZ_4K,

drivers/gpu/drm/ttm/tests/ttm_tt_test.c

25

.size = SZ_4K,

drivers/gpu/drm/ttm/tests/ttm_tt_test.c

73

int num_pages = (size + SZ_4K) >> PAGE_SHIFT;

drivers/gpu/drm/v3d/v3d_bo.c

118

align = SZ_4K;

drivers/gpu/drm/v3d/v3d_bo.c

124

align = SZ_4K;

drivers/gpu/drm/v3d/v3d_mmu.c

114

page_size = SZ_4K;

drivers/gpu/drm/xe/display/xe_initial_plane.c

51

u64 page_size = xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K;

drivers/gpu/drm/xe/display/xe_stolen.c

25

if (start < SZ_4K)

drivers/gpu/drm/xe/display/xe_stolen.c

26

start = SZ_4K;

drivers/gpu/drm/xe/tests/xe_gt_sriov_pf_config_kunit.c

99

KUNIT_ASSERT_EQ(test, SZ_4K, pf_profile_fair_ctxs(gt, num_vfs));

drivers/gpu/drm/xe/tests/xe_guc_buf_kunit.c

46

xe_bo_size(bo), SZ_4K));

drivers/gpu/drm/xe/tests/xe_migrate.c

225

2 * SZ_4K,

drivers/gpu/drm/xe/xe_bo.c

2172

aligned_size = ALIGN(size, SZ_4K);

drivers/gpu/drm/xe/xe_bo.c

2174

alignment = SZ_4K >> PAGE_SHIFT;

drivers/gpu/drm/xe/xe_bo.c

3313

if (XE_IOCTL_DBG(xe, PAGE_SIZE > SZ_4K))

drivers/gpu/drm/xe/xe_bo.c

3317

SZ_4K) >= DRM_FILE_PAGE_OFFSET_START);

drivers/gpu/drm/xe/xe_bo.c

3636

xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K);

drivers/gpu/drm/xe/xe_configfs.c

635

return wa_bb_show(dev, dev->config.ctx_restore_mid_bb, page, SZ_4K);

drivers/gpu/drm/xe/xe_configfs.c

642

return wa_bb_show(dev, dev->config.ctx_restore_post_bb, page, SZ_4K);

drivers/gpu/drm/xe/xe_device.c

325

if (vma->vm_end - vma->vm_start > SZ_4K)

drivers/gpu/drm/xe/xe_exec_queue.c

687

bo = xe_bo_create_pin_map_novm(xe, tile, SZ_4K, ttm_bo_type_kernel,

drivers/gpu/drm/xe/xe_exec_queue.c

700

xe_map_memset(xe, &bo->vmap, 0, 0, SZ_4K);

drivers/gpu/drm/xe/xe_gsc.c

126

#define GSC_VER_PKT_SZ SZ_4K /* 4K each for input and output */

drivers/gpu/drm/xe/xe_gsc.c

86

bb->cs[bb->len++] = (xe_bo_size(gsc->private) / SZ_4K) |

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

2763

ret = ret ? 0 : SZ_4K;

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

2765

if (size < SZ_4K) {

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c

434

return IS_DGFX(xe) && xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K;

drivers/gpu/drm/xe/xe_gt_sriov_pf_debugfs.c

752

if (count > SZ_4K)

drivers/gpu/drm/xe/xe_guc.c

111

#define LOG_UNIT SZ_4K

drivers/gpu/drm/xe/xe_guc.c

119

#define CAPTURE_UNIT SZ_4K

drivers/gpu/drm/xe/xe_guc.c

299

FIELD_PREP(XE_G2G_REGISTER_SIZE, size / SZ_4K - 1) |

drivers/gpu/drm/xe/xe_guc.c

308

xe_assert(xe, !(size % SZ_4K));

drivers/gpu/drm/xe/xe_guc.c

331

#define G2G_BUFFER_SIZE (SZ_4K)

drivers/gpu/drm/xe/xe_guc.c

333

#define G2G_DESC_AREA_SIZE (SZ_4K)

drivers/gpu/drm/xe/xe_guc_ads.c

382

return SZ_4K;

drivers/gpu/drm/xe/xe_guc_ads.c

385

#define MAX_GOLDEN_LRC_SIZE (SZ_4K * 64)

drivers/gpu/drm/xe/xe_guc_ct.c

117

char *buf __cleanup(kfree) = kmalloc(SZ_4K, GFP_NOWAIT);

drivers/gpu/drm/xe/xe_guc_ct.c

119

if (buf && stack_depot_snprint(ct->fast_req[slot].stack, buf, SZ_4K, 0))

drivers/gpu/drm/xe/xe_guc_ct.c

257

#define CTB_H2G_BUFFER_SIZE (SZ_4K)

drivers/gpu/drm/xe/xe_guc_ct.c

278

return (CTB_H2G_BUFFER_SIZE / SZ_4K) * HZ;

drivers/gpu/drm/xe/xe_guc_log.h

25

#define GUC_LOG_SIZE (SZ_4K + \

drivers/gpu/drm/xe/xe_guc_log.h

30

#define XE_GUC_LOG_EVENT_DATA_OFFSET SZ_4K

drivers/gpu/drm/xe/xe_guc_tlb_inval.c

144

if (length < SZ_4K)

drivers/gpu/drm/xe/xe_guc_tlb_inval.c

145

length = SZ_4K;

drivers/gpu/drm/xe/xe_guc_tlb_inval.c

171

xe_gt_assert(gt, length >= SZ_4K);

drivers/gpu/drm/xe/xe_guc_tlb_inval.c

182

action[len++] = ilog2(length) - ilog2(SZ_4K);

drivers/gpu/drm/xe/xe_huc.c

45

#define PXP43_HUC_AUTH_INOUT_SIZE SZ_4K

drivers/gpu/drm/xe/xe_hw_engine.c

618

hwe->hwsp = xe_managed_bo_create_pin_map(xe, tile, SZ_4K,

drivers/gpu/drm/xe/xe_late_bind_fw_types.h

15

#define XE_LB_MAX_PAYLOAD_SIZE SZ_4K

drivers/gpu/drm/xe/xe_lrc.c

117

size += 3 * SZ_4K;

drivers/gpu/drm/xe/xe_lrc.c

119

size += 13 * SZ_4K;

drivers/gpu/drm/xe/xe_lrc.c

123

size += 2 * SZ_4K;

drivers/gpu/drm/xe/xe_lrc.c

125

size += 13 * SZ_4K;

drivers/gpu/drm/xe/xe_lrc.c

134

size += 1 * SZ_4K;

drivers/gpu/drm/xe/xe_lrc.c

43

#define LRC_PPHWSP_SIZE SZ_4K

drivers/gpu/drm/xe/xe_lrc.c

44

#define LRC_INDIRECT_CTX_BO_SIZE SZ_4K

drivers/gpu/drm/xe/xe_lrc.c

45

#define LRC_INDIRECT_RING_STATE_SIZE SZ_4K

drivers/gpu/drm/xe/xe_lrc.h

47

#define LRC_WA_BB_SIZE SZ_4K

drivers/gpu/drm/xe/xe_memirq.c

170

XE_HW_ENGINE_MAX_INSTANCE * SZ_4K : SZ_4K;

drivers/gpu/drm/xe/xe_memirq.c

175

BUILD_BUG_ON(!IS_ALIGNED(XE_MEMIRQ_STATUS_OFFSET(0), SZ_4K));

drivers/gpu/drm/xe/xe_memirq_types.h

14

#define XE_MEMIRQ_STATUS_OFFSET(inst) ((inst) * SZ_4K + 0x0)

drivers/gpu/drm/xe/xe_memirq_types.h

16

#define XE_MEMIRQ_SOURCE_OFFSET(inst) ((inst) * SZ_4K + 0x400)

drivers/gpu/drm/xe/xe_migrate.c

1858

xe_tile_assert(tile, xe_bo_size(pt_bo) == SZ_4K);

drivers/gpu/drm/xe/xe_migrate.c

2101

else if (IS_ALIGNED(len, SZ_4K))

drivers/gpu/drm/xe/xe_migrate.c

2102

pitch = SZ_4K;

drivers/gpu/drm/xe/xe_migrate.c

501

m->min_chunk_size = SZ_4K * SZ_64K /

drivers/gpu/drm/xe/xe_page_reclaim.h

17

#define XE_PAGE_RECLAIM_LIST_MAX_SIZE SZ_4K

drivers/gpu/drm/xe/xe_pt.c

130

bo = xe_bo_create_pin_map(vm->xe, tile, vm, SZ_4K,

drivers/gpu/drm/xe/xe_pt.c

1611

reclamation_size = COMPUTE_RECLAIM_ADDRESS_MASK(SZ_4K); /* reclamation_size = 0 */

drivers/gpu/drm/xe/xe_pt.c

1612

xe_tile_assert(tile, phys_addr % SZ_4K == 0);

drivers/gpu/drm/xe/xe_pt.c

175

xe_map_memset(vm->xe, map, 0, 0, SZ_4K);

drivers/gpu/drm/xe/xe_pt.c

240

xe_map_memset(xe, map, 0, 0, SZ_4K);

drivers/gpu/drm/xe/xe_pxp_submit.c

57

bo = xe_bo_create_pin_map_novm(xe, tile, SZ_4K, ttm_bo_type_kernel,

drivers/gpu/drm/xe/xe_query.c

347

xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K;

drivers/gpu/drm/xe/xe_sa.h

24

return __xe_sa_bo_manager_init(tile, size, SZ_4K, align, 0);

drivers/gpu/drm/xe/xe_sriov_vf_ccs.c

153

sa_manager = __xe_sa_bo_manager_init(tile, bb_pool_size, SZ_4K, SZ_16,

drivers/gpu/drm/xe/xe_svm.c

1141

case SZ_4K: \

drivers/gpu/drm/xe/xe_svm.c

1165

case SZ_4K: \

drivers/gpu/drm/xe/xe_svm.c

801

SZ_4K,

drivers/gpu/drm/xe/xe_vm.c

2128

page_addr + SZ_4K - 1 < xe_vma_start(vma))

drivers/gpu/drm/xe/xe_vm.c

2149

vma = xe_vm_find_overlapping_vma(vm, page_addr, SZ_4K);

drivers/gpu/drm/xe/xe_vm.c

2506

return SZ_4K;

drivers/gpu/drm/xe/xe_vm.c

2523

case SZ_4K:

drivers/gpu/drm/xe/xe_vm.c

4550

if (*start >= SZ_4K) {

drivers/gpu/drm/xe/xe_vm.c

4551

prev = xe_vm_find_vma_by_addr(vm, *start - SZ_4K);

drivers/gpu/drm/xe/xe_vm_madvise.c

252

if (XE_IOCTL_DBG(xe, !IS_ALIGNED(args->start, SZ_4K)))

drivers/gpu/drm/xe/xe_vm_madvise.c

255

if (XE_IOCTL_DBG(xe, !IS_ALIGNED(args->range, SZ_4K)))

drivers/gpu/drm/xe/xe_vm_madvise.c

258

if (XE_IOCTL_DBG(xe, args->range < SZ_4K))

drivers/gpu/drm/xe/xe_wopcm.c

72

#define WOPCM_HW_CTX_RESERVED (SZ_32K + SZ_4K)

drivers/hid/intel-ish-hid/ishtp/loader.h

233

#define ISH_MANIFEST_ALIGNMENT SZ_4K

drivers/hid/intel-thc-hid/intel-quicki2c/pci-quicki2c.c

591

max_report_len = max(le16_to_cpu(qcdev->dev_desc.max_input_len), SZ_4K);

drivers/hid/intel-thc-hid/intel-quicki2c/pci-quicki2c.c

598

qcdev->dev_desc.max_output_len = cpu_to_le16(SZ_4K);

drivers/hid/intel-thc-hid/intel-thc/intel-thc-dma.c

181

dma_config->max_packet_size = ALIGN(size, SZ_4K);

drivers/hid/intel-thc-hid/intel-thc/intel-thc-dma.h

17

#define THC_MIN_BYTES_PER_SG_LIST_ENTRY SZ_4K

drivers/hv/hv_common.c

432

header->length > sizeof(*header) + SZ_4K)

drivers/i2c/busses/i2c-tegra.c

1597

.max_read_len = SZ_4K,

drivers/i2c/busses/i2c-tegra.c

1598

.max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE,

drivers/i2c/busses/i2c-usbio.c

211

.max_read_len = SZ_4K,

drivers/i2c/busses/i2c-usbio.c

212

.max_write_len = SZ_4K,

drivers/iio/adc/nxp-sar-adc.c

121

#define NXP_PAGE_SIZE SZ_4K

drivers/infiniband/core/rw.c

791

prot_sgt.nents, NULL, SZ_4K);

drivers/infiniband/hw/erdma/erdma_verbs.c

1253

SZ_2G - SZ_4K, false);

drivers/infiniband/hw/erdma/erdma_verbs.c

1912

ureq->qbuf_len, 0, ureq->qbuf_va, SZ_64M - SZ_4K,

drivers/infiniband/hw/erdma/erdma_verbs.c

951

(SZ_1M - SZ_4K), true);

drivers/infiniband/hw/erdma/erdma_verbs.c

960

(SZ_1M - SZ_4K), true);

drivers/infiniband/hw/irdma/hw.c

16

.qplimit = SZ_4K,

drivers/infiniband/hw/irdma/i40iw_hw.c

247

dev->hw_attrs.page_size_cap = SZ_4K | SZ_2M;

drivers/infiniband/hw/irdma/icrdma_hw.c

193

dev->hw_attrs.page_size_cap = SZ_4K | SZ_2M | SZ_1G;

drivers/infiniband/hw/irdma/ig3rdma_hw.c

128

dev->hw_attrs.page_size_cap = SZ_4K | SZ_2M | SZ_1G;

drivers/infiniband/hw/irdma/verbs.c

3385

iwdev->rf->sc_dev.hw_attrs.page_size_cap : SZ_4K;

drivers/infiniband/hw/irdma/verbs.c

3836

iwmr->page_size = SZ_4K;

drivers/infiniband/hw/mana/mana_ib.h

21

(SZ_4K | SZ_8K | SZ_16K | SZ_32K | SZ_64K | SZ_128K | SZ_256K | \

drivers/infiniband/ulp/iser/iscsi_iser.c

650

shost->virt_boundary_mask = SZ_4K - 1;

drivers/infiniband/ulp/iser/iscsi_iser.h

101

((ISER_DEF_MAX_SECTORS * SECTOR_SIZE) >> ilog2(SZ_4K))

drivers/infiniband/ulp/iser/iscsi_iser.h

103

#define ISCSI_ISER_MAX_SG_TABLESIZE ((32768 * SECTOR_SIZE) >> ilog2(SZ_4K))

drivers/infiniband/ulp/iser/iser_memory.c

273

sig_mem->sg, sig_mem->dma_nents, NULL, SZ_4K);

drivers/infiniband/ulp/iser/iser_memory.c

321

n = ib_map_mr_sg(mr, mem->sg, mem->dma_nents, NULL, SZ_4K);

drivers/infiniband/ulp/iser/iser_verbs.c

512

sg_tablesize = DIV_ROUND_UP(max_sectors * SECTOR_SIZE, SZ_4K);

drivers/infiniband/ulp/rtrs/rtrs-clt.c

1072

nr = ib_map_mr_sg(req->mr, req->sglist, count, NULL, SZ_4K);

drivers/infiniband/ulp/rtrs/rtrs-clt.c

3120

clt->max_segments * SZ_4K);

drivers/input/touchscreen/exc3000.c

62

.max_xy = SZ_4K - 1,

drivers/iommu/amd/init.c

1729

SZ_4K);

drivers/iommu/amd/iommu.c

1976

gcr3_info->gcr3_tbl = iommu_alloc_pages_node_sz(nid, GFP_ATOMIC, SZ_4K);

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c

41

static_assert(PAGE_SIZE == SZ_4K || PAGE_SIZE == SZ_16K ||

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

4531

smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G;

drivers/iommu/arm/arm-smmu/arm-smmu.c

1918

smmu->pgsize_bitmap |= SZ_4K | SZ_64K | SZ_1M | SZ_16M;

drivers/iommu/arm/arm-smmu/arm-smmu.c

1921

smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G;

drivers/iommu/arm/arm-smmu/qcom_iommu.c

338

qcom_domain->domain.pgsize_bitmap = SZ_4K;

drivers/iommu/generic_pt/kunit_iommu_pt.h

402

priv->smallest_pgsz != SZ_4K)

drivers/iommu/intel/dmar.c

1706

SZ_4K);

drivers/iommu/intel/iommu.c

1494

GFP_KERNEL, SZ_4K);

drivers/iommu/intel/iommu.c

2867

dmar_domain->domain.pgsize_bitmap = SZ_4K;

drivers/iommu/intel/iommu.c

2965

dmar_domain->domain.pgsize_bitmap = SZ_4K;

drivers/iommu/intel/iommu.c

371

SZ_4K);

drivers/iommu/intel/iommu.c

676

root = iommu_alloc_pages_node_sz(iommu->node, GFP_ATOMIC, SZ_4K);

drivers/iommu/intel/iommu.h

492

#define PRQ_SIZE (SZ_4K << PRQ_ORDER)

drivers/iommu/intel/pasid.c

152

GFP_ATOMIC, SZ_4K);

drivers/iommu/io-pgtable-arm-selftests.c

157

SZ_4K | SZ_2M | SZ_1G,

drivers/iommu/io-pgtable-arm-v7s.c

726

cfg->pgsize_bitmap &= SZ_4K | SZ_64K | SZ_1M | SZ_16M;

drivers/iommu/io-pgtable-arm-v7s.c

820

.pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M,

drivers/iommu/io-pgtable-arm.c

1101

case SZ_4K:

drivers/iommu/io-pgtable-arm.c

1166

cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);

drivers/iommu/io-pgtable-arm.c

1176

cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);

drivers/iommu/io-pgtable-arm.c

1192

cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);

drivers/iommu/io-pgtable-arm.c

238

if ((ARM_LPAE_GRANULE(data) == SZ_4K) && (data->start_level == 0))

drivers/iommu/io-pgtable-arm.c

895

case SZ_4K:

drivers/iommu/io-pgtable-arm.c

896

page_sizes = (SZ_4K | SZ_2M | SZ_1G);

drivers/iommu/io-pgtable-arm.c

924

if (!(cfg->pgsize_bitmap & (SZ_4K | SZ_16K | SZ_64K)))

drivers/iommu/io-pgtable-arm.c

995

case SZ_4K:

drivers/iommu/io-pgtable-dart.c

371

if (cfg->pgsize_bitmap == SZ_4K)

drivers/iommu/io-pgtable-dart.c

423

if (!(cfg->pgsize_bitmap == SZ_4K || cfg->pgsize_bitmap == SZ_16K))

drivers/iommu/ipmmu-vmsa.c

574

domain->io_domain.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K;

drivers/iommu/msm_iommu.c

34

#define MSM_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M)

drivers/iommu/msm_iommu.c

507

__flush_iotlb_range(iova, size, SZ_4K, false, priv);

drivers/iommu/mtk_iommu.c

711

dom->domain.pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M;

drivers/iommu/omap-iommu.c

40

#define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M)

drivers/iommu/omap-iommu.h

213

((bytes) >= SZ_4K) ? SZ_4K : 0)

drivers/iommu/omap-iommu.h

219

((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)

drivers/iommu/omap-iommu.h

225

((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)

drivers/iommu/riscv/iommu.c

1150

SZ_4K);

drivers/iommu/riscv/iommu.c

1393

GFP_KERNEL_ACCOUNT, SZ_4K);

drivers/iommu/riscv/iommu.c

1422

domain->domain.pgsize_bitmap = va_mask & (SZ_4K | SZ_2M | SZ_1G | SZ_512G);

drivers/iommu/riscv/iommu.c

169

iommu, max(queue_size, SZ_4K));

drivers/iommu/riscv/iommu.c

624

ptr = riscv_iommu_get_pages(iommu, SZ_4K);

drivers/iommu/riscv/iommu.c

704

iommu->ddt_root = riscv_iommu_get_pages(iommu, SZ_4K);

drivers/iommu/s390-iommu.c

560

s390_domain->domain.pgsize_bitmap = SZ_4K;

drivers/iommu/s390-iommu.c

921

if (pgsize != SZ_4K)

drivers/iommu/sprd-iommu.c

22

#define SPRD_IOMMU_PAGE_SIZE SZ_4K

drivers/iommu/sun50i-iommu.c

659

return SZ_4K;

drivers/iommu/sun50i-iommu.c

700

sun50i_domain->domain.pgsize_bitmap = SZ_4K;

drivers/iommu/tegra-smmu.c

321

as->domain.pgsize_bitmap = SZ_4K;

drivers/irqchip/irq-gic-v2m.c

479

res.end = m->base_address + SZ_4K - 1;

drivers/irqchip/irq-gic-v3-its.c

2435

case SZ_4K:

drivers/irqchip/irq-gic-v3-its.c

2633

case SZ_4K:

drivers/irqchip/irq-gic-v3-its.c

2652

psz = SZ_4K;

drivers/irqchip/irq-gic-v3-its.c

2654

case SZ_4K:

drivers/irqchip/irq-gic-v3-its.c

2855

psz = SZ_4K;

drivers/irqchip/irq-gic-v3-its.c

2950

psz = SZ_4K;

drivers/irqchip/irq-gic-v3-its.c

5295

(ITS_CMD_QUEUE_SZ / SZ_4K - 1) |

drivers/irqchip/irq-gic-v3.c

2494

#define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)

drivers/irqchip/irq-gic-v5-irs.c

276

case SZ_4K:

drivers/irqchip/irq-gic-v5-its.c

309

case SZ_4K:

drivers/irqchip/irq-gic.c

1312

if (!gic_check_gicv2(alt + SZ_4K)) {

drivers/irqchip/irq-gic.c

1591

#define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K)

drivers/irqchip/irq-gic.c

1593

#define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)

drivers/irqchip/irq-omap-intc.c

267

omap_irq_base = ioremap(base, SZ_4K);

drivers/mailbox/arm_mhuv3.c

183

u8 pad[SZ_4K];

drivers/mailbox/arm_mhuv3.c

191

u8 pad[SZ_4K * 11];

drivers/mailbox/arm_mhuv3.c

200

u8 pad[SZ_4K * 11];

drivers/media/i2c/s5c73m3/s5c73m3-core.c

42

#define S5C73M3_EMBEDDED_DATA_MAXLEN SZ_4K

drivers/media/pci/intel/ipu6/ipu6-mmu.c

561

mmu_info->pgsize_bitmap = SZ_4K;

drivers/media/pci/intel/ipu6/ipu6-mmu.c

626

init_iova_domain(&dmap->iovad, SZ_4K, 1);

drivers/media/pci/tw686x/tw686x-regs.h

111

#define AUDIO_DMA_SIZE_MAX SZ_4K

drivers/media/platform/mediatek/vcodec/decoder/vdec_msg_queue.c

23

#define VDEC_RD_MV_BUFFER_SZ (((SZ_4K * 2304 >> 4) + SZ_1K) << 1)

drivers/media/platform/nxp/imx-mipi-csis.c

228

#define MIPI_CSIS_PKTDATA_SIZE SZ_4K

drivers/media/platform/qcom/iris/iris_hfi_queue.c

252

queue_size = ALIGN((sizeof(*q_tbl_hdr) + (IFACEQ_QUEUE_SIZE * IFACEQ_NUMQ)), SZ_4K);

drivers/media/platform/qcom/iris/iris_hfi_queue.c

310

(IFACEQ_QUEUE_SIZE * IFACEQ_NUMQ), SZ_4K);

drivers/media/platform/qcom/iris/iris_hfi_queue.h

30

#define SFR_SIZE SZ_4K /* Iris hardware requires 4K queue alignment */

drivers/media/platform/qcom/iris/iris_vpu_buffer.c

1620

return ALIGN(metadata_stride * metadata_buf_height, SZ_4K);

drivers/media/platform/qcom/iris/iris_vpu_buffer.c

1658

luma_size = (luma_size + (SZ_4K - 1)) & (~(SZ_4K - 1));

drivers/media/platform/qcom/iris/iris_vpu_buffer.c

1659

chroma_size = (chroma_size + (SZ_4K - 1)) & (~(SZ_4K - 1));

drivers/media/platform/qcom/iris/iris_vpu_buffer.c

880

return ALIGN(frame_size, SZ_4K);

drivers/media/platform/qcom/iris/iris_vpu_common.c

51

(IFACEQ_QUEUE_SIZE * IFACEQ_NUMQ), SZ_4K);

drivers/media/platform/qcom/venus/helpers.c

1000

return ALIGN((y_plane + uv_plane), SZ_4K);

drivers/media/platform/qcom/venus/helpers.c

1017

y_ubwc_plane = ALIGN(y_stride * y_sclines, SZ_4K);

drivers/media/platform/qcom/venus/helpers.c

1018

uv_ubwc_plane = ALIGN(uv_stride * uv_sclines, SZ_4K);

drivers/media/platform/qcom/venus/helpers.c

1021

y_meta_plane = ALIGN(y_meta_stride * y_meta_scanlines, SZ_4K);

drivers/media/platform/qcom/venus/helpers.c

1024

uv_meta_plane = ALIGN(uv_meta_stride * uv_meta_scanlines, SZ_4K);

drivers/media/platform/qcom/venus/helpers.c

1028

return ALIGN(size, SZ_4K);

drivers/media/platform/qcom/venus/helpers.c

1046

y_ubwc_plane = ALIGN(y_stride * y_sclines, SZ_4K);

drivers/media/platform/qcom/venus/helpers.c

1047

uv_ubwc_plane = ALIGN(uv_stride * uv_sclines, SZ_4K);

drivers/media/platform/qcom/venus/helpers.c

1050

y_meta_plane = ALIGN(y_meta_stride * y_meta_scanlines, SZ_4K);

drivers/media/platform/qcom/venus/helpers.c

1053

uv_meta_plane = ALIGN(uv_meta_stride * uv_meta_scanlines, SZ_4K);

drivers/media/platform/qcom/venus/helpers.c

1058

return ALIGN(size, SZ_4K);

drivers/media/platform/qcom/venus/helpers.c

1112

return ALIGN(sz, SZ_4K);

drivers/media/platform/qcom/venus/helpers.c

957

uv_plane = uv_stride * uv_sclines + SZ_4K;

drivers/media/platform/qcom/venus/helpers.c

960

return ALIGN(size, SZ_4K);

drivers/media/platform/qcom/venus/helpers.c

973

y_meta_plane = ALIGN(y_meta_plane, SZ_4K);

drivers/media/platform/qcom/venus/helpers.c

976

y_plane = ALIGN(y_stride * ALIGN(height, 32), SZ_4K);

drivers/media/platform/qcom/venus/helpers.c

980

uv_meta_plane = ALIGN(uv_meta_plane, SZ_4K);

drivers/media/platform/qcom/venus/helpers.c

983

uv_plane = ALIGN(uv_stride * ALIGN(height / 2, 32), SZ_4K);

drivers/media/platform/qcom/venus/helpers.c

986

max(extradata, y_stride * 48), SZ_4K);

drivers/media/platform/qcom/venus/hfi_plat_bufs_v6.c

1153

return ALIGN(frame_size, SZ_4K);

drivers/media/platform/qcom/venus/hfi_plat_bufs_v6.c

400

return ALIGN(frame_size, SZ_4K);

drivers/media/platform/qcom/venus/hfi_plat_bufs_v6.c

945

return ALIGN(metadata_stride * metadata_buf_height, SZ_4K);

drivers/media/platform/qcom/venus/hfi_plat_bufs_v6.c

988

luma_size = (luma_size + (SZ_4K - 1)) & (~(SZ_4K - 1));

drivers/media/platform/qcom/venus/hfi_plat_bufs_v6.c

989

chroma_size = (chroma_size + (SZ_4K - 1)) & (~(SZ_4K - 1));

drivers/media/platform/qcom/venus/hfi_venus.c

350

desc->size = ALIGN(size, SZ_4K);

drivers/media/platform/qcom/venus/hfi_venus.c

86

#define QDSS_SIZE SZ_4K

drivers/media/platform/qcom/venus/hfi_venus.c

87

#define SFR_SIZE SZ_4K

drivers/media/platform/qcom/venus/hfi_venus.c

91

#define ALIGNED_QDSS_SIZE ALIGN(QDSS_SIZE, SZ_4K)

drivers/media/platform/qcom/venus/hfi_venus.c

92

#define ALIGNED_SFR_SIZE ALIGN(SFR_SIZE, SZ_4K)

drivers/media/platform/qcom/venus/hfi_venus.c

93

#define ALIGNED_QUEUE_SIZE ALIGN(QUEUE_SIZE, SZ_4K)

drivers/media/platform/qcom/venus/venc.c

218

pfmt[0].sizeimage = max(ALIGN(pfmt[0].sizeimage, SZ_4K), sizeimage);

drivers/media/platform/rockchip/rkvdec/rkvdec-rcb.c

120

rcb_size = ALIGN(rcb_size, SZ_4K);

drivers/media/platform/rockchip/rkvdec/rkvdec-rcb.c

125

SZ_4K);

drivers/media/platform/samsung/exynos4-is/mipi-csis.c

112

#define S5PCSIS_PKTDATA_SIZE SZ_4K

drivers/misc/keba/cp500.c

100

.fan = { 0x9000, SZ_4K },

drivers/misc/keba/cp500.c

101

.batt = { 0xA000, SZ_4K },

drivers/misc/keba/cp500.c

102

.uart0_rfb = { 0xB000, SZ_4K, CP500_RFB_UART_MSIX },

drivers/misc/keba/cp500.c

103

.uart2_si1 = { 0xD000, SZ_4K, CP500_SI1_UART_MSIX },

drivers/misc/keba/cp500.c

108

.startup = { 0x0000, SZ_4K },

drivers/misc/keba/cp500.c

109

.spi = { 0x4000, SZ_4K },

drivers/misc/keba/cp500.c

110

.i2c = { 0x5000, SZ_4K },

drivers/misc/keba/cp500.c

111

.fan = { 0x9000, SZ_4K },

drivers/misc/keba/cp500.c

112

.batt = { 0xA000, SZ_4K },

drivers/misc/keba/cp500.c

113

.uart0_rfb = { 0xB000, SZ_4K, CP500_RFB_UART_MSIX },

drivers/misc/keba/cp500.c

114

.uart2_si1 = { 0xD000, SZ_4K, CP500_SI1_UART_MSIX },

drivers/misc/keba/cp500.c

119

.startup = { 0x0000, SZ_4K },

drivers/misc/keba/cp500.c

120

.spi = { 0x4000, SZ_4K },

drivers/misc/keba/cp500.c

121

.i2c = { 0x5000, SZ_4K },

drivers/misc/keba/cp500.c

122

.fan = { 0x8000, SZ_4K },

drivers/misc/keba/cp500.c

123

.batt = { 0x9000, SZ_4K },

drivers/misc/keba/cp500.c

124

.uart0_rfb = { 0xC000, SZ_4K, CP500_RFB_UART_MSIX },

drivers/misc/keba/cp500.c

125

.uart1_dbg = { 0xD000, SZ_4K, CP500_DEBUG_UART_MSIX },

drivers/misc/keba/cp500.c

97

.startup = { 0x0000, SZ_4K },

drivers/misc/keba/cp500.c

98

.spi = { 0x1000, SZ_4K },

drivers/misc/keba/cp500.c

99

.i2c = { 0x4000, SZ_4K },

drivers/misc/mei/gsc-me.c

39

u32 limit = (resource_size(mem) / SZ_4K) | GSC_EXT_OP_MEM_VALID;

drivers/misc/mei/vsc-fw-loader.c

521

ALIGN(last_frag->location + last_frag->size, SZ_4K);

drivers/misc/pci_endpoint_test.c

1361

.alignment = SZ_4K,

drivers/mtd/devices/mtd_intel_dg.c

394

for (i = 0; i < len; i += SZ_4K) {

drivers/mtd/devices/mtd_intel_dg.c

512

if (!IS_ALIGNED(info->addr, SZ_4K) || !IS_ALIGNED(info->len, SZ_4K)) {

drivers/mtd/devices/mtd_intel_dg.c

532

if (!IS_ALIGNED(addr, SZ_4K) || !IS_ALIGNED(total_len, SZ_4K)) {

drivers/mtd/devices/mtd_intel_dg.c

720

nvm->mtd.erasesize = SZ_4K; /* 4K bytes granularity */

drivers/mtd/nand/onenand/onenand_samsung.c

881

onenand->page_buf = devm_kzalloc(&pdev->dev, SZ_4K,

drivers/mtd/nand/raw/arasan-nand-controller.c

1119

case SZ_4K:

drivers/mtd/nand/raw/arasan-nand-controller.c

112

#define ANFC_MAX_PARAM_SIZE SZ_4K

drivers/mtd/nand/raw/loongson-nand-controller.c

701

case SZ_4K:

drivers/mtd/nand/raw/marvell_nand.c

2231

if (mtd->writesize == SZ_4K && lt->data_bytes == SZ_2K)

drivers/mtd/nand/raw/nand_ids.c

34

SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },

drivers/mtd/nand/raw/nand_ids.c

37

SZ_4K, SZ_512, SZ_256K, 0, 8, 256, NAND_ECC_INFO(8, SZ_512) },

drivers/mtd/nand/raw/nand_ids.c

40

SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) },

drivers/mtd/nand/raw/nand_ids.c

43

SZ_8K, SZ_4K, SZ_1M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },

drivers/mtd/nand/raw/nand_ids.c

66

SZ_4K, SZ_1K, SZ_256K, 0, 5, 256, NAND_ECC_INFO(8, SZ_512)},

drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c

752

case SZ_4K:

drivers/mtd/spi-nor/core.c

2621

tested_erase->size == SZ_4K) {

drivers/net/ethernet/amazon/ena/ena_com.c

2988

host_attr->host_info = dma_alloc_coherent(ena_dev->dmadev, SZ_4K,

drivers/net/ethernet/amazon/ena/ena_com.c

3041

dma_free_coherent(ena_dev->dmadev, SZ_4K, host_attr->host_info,

drivers/net/ethernet/atheros/ag71xx.c

1958

.desc_pktlen_mask = SZ_4K - 1,

drivers/net/ethernet/atheros/ag71xx.c

1966

.desc_pktlen_mask = SZ_4K - 1,

drivers/net/ethernet/atheros/ag71xx.c

1974

.desc_pktlen_mask = SZ_4K - 1,

drivers/net/ethernet/atheros/ag71xx.c

1982

.desc_pktlen_mask = SZ_4K - 1,

drivers/net/ethernet/broadcom/bnge/bnge_netdev.c

565

const unsigned int rx_size_fac = PAGE_SIZE / SZ_4K;

drivers/net/ethernet/broadcom/bnxt/bnxt.c

3850

const unsigned int rx_size_fac = PAGE_SIZE / SZ_4K;

drivers/net/ethernet/google/gve/gve_main.c

2080

if (!gve_is_dqo(priv) || priv->max_rx_buffer_size < SZ_4K) {

drivers/net/ethernet/google/gve/gve_main.c

2092

if (rx_buf_len != SZ_2K && rx_buf_len != SZ_4K) {

drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c

65

#define CMDQ_DEPTH SZ_4K

drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c

704

pfn = CMDQ_PFN(wq_first_page_paddr, SZ_4K);

drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h

136

#define HINIC_EQ_PAGE_SIZE SZ_4K

drivers/net/ethernet/huawei/hinic/hinic_hw_io.h

21

#define HINIC_DB_PAGE_SIZE SZ_4K

drivers/net/ethernet/huawei/hinic/hinic_hw_io.h

23

#define HINIC_HW_WQ_PAGE_SIZE SZ_4K

drivers/net/ethernet/huawei/hinic/hinic_hw_mbox.c

1340

if (((1U << page_size_info->page_size) * SZ_4K) !=

drivers/net/ethernet/huawei/hinic/hinic_hw_qp.h

44

#define HINIC_SQ_DEPTH SZ_4K

drivers/net/ethernet/huawei/hinic/hinic_hw_qp.h

45

#define HINIC_RQ_DEPTH SZ_4K

drivers/net/ethernet/huawei/hinic/hinic_hw_qp.h

47

#define HINIC_MAX_QUEUE_DEPTH SZ_4K

drivers/net/ethernet/intel/idpf/idpf_txrx.h

227

#define IDPF_TX_MAX_READ_REQ_SIZE SZ_4K

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

2593

*pointer = (value & ~IXGBE_SR_NVM_PTR_4KB_UNITS) * SZ_4K;

drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c

2625

*size = value * SZ_4K;

drivers/net/ethernet/netronome/nfp/nfdk/nfdk.h

12

#define NFDK_TX_MAX_DATA_PER_HEAD SZ_4K

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c

684

FIELD_GET(NSP_DFLT_BUFFER_SIZE_4KB, reg) * SZ_4K;

drivers/net/ethernet/ti/icssg/icssg_config.c

475

for (i = 0; i < SZ_4K - 1; i++) {

drivers/net/ethernet/ti/icssg/icssg_config.c

498

for (i = 0; i < SZ_4K - 1; i++) {

drivers/net/ethernet/ti/icssg/icssg_config.h

47

#define PRUETH_SW_LI_BUF_POOL_SIZE SZ_4K

drivers/net/mdio/mdio-mux-bcm-iproc.c

225

if (!IS_ALIGNED(res->start, SZ_4K)) {

drivers/net/mdio/mdio-mux-bcm-iproc.c

230

res->start = ALIGN_DOWN(res->start, SZ_4K);

drivers/net/thunderbolt/main.c

41

#define TBNET_FRAME_SIZE SZ_4K

drivers/net/wireless/ti/wlcore/spi.c

61

#define SPI_AGGR_BUFFER_SIZE (13 * SZ_4K)

drivers/ntb/hw/amd/ntb_hw_amd.c

108

*addr_align = SZ_4K;

drivers/ntb/hw/epf/ntb_hw_epf.c

182

*addr_align = SZ_4K;

drivers/ntb/hw/mscc/ntb_hw_switchtec.c

210

*addr_align = lut ? size : SZ_4K;

drivers/ntb/hw/mscc/ntb_hw_switchtec.c

213

*size_align = lut ? size : SZ_4K;

drivers/nvdimm/btt.c

455

size_t chunk_size = SZ_4K, offset = 0;

drivers/nvdimm/btt_devs.c

288

nd_btt->initial_offset = SZ_4K;

drivers/nvdimm/btt_devs.c

291

if (nvdimm_read_bytes(ndns, SZ_4K, btt_sb, sizeof(*btt_sb), 0))

drivers/nvdimm/claim.c

221

BUILD_BUG_ON(sizeof(struct btt_sb) != SZ_4K);

drivers/nvdimm/claim.c

222

BUILD_BUG_ON(sizeof(struct nd_pfn_sb) != SZ_4K);

drivers/nvdimm/claim.c

223

BUILD_BUG_ON(sizeof(struct nd_gen_sb) != SZ_4K);

drivers/nvdimm/nd.h

536

char reserved[SZ_4K - 8];

drivers/nvdimm/pfn_devs.c

368

meta_start = (SZ_4K + sizeof(*pfn_sb)) >> 9;

drivers/nvdimm/pfn_devs.c

458

if (nvdimm_read_bytes(ndns, SZ_4K, pfn_sb, sizeof(*pfn_sb), 0))

drivers/nvdimm/pfn_devs.c

838

return nvdimm_write_bytes(ndns, SZ_4K, pfn_sb, sizeof(*pfn_sb), 0);

drivers/nvme/host/fc.c

3088

(ilog2(SZ_4K) - 9);

drivers/nvme/host/rdma.c

1318

SZ_4K);

drivers/nvme/host/rdma.c

1426

SZ_4K);

drivers/nvme/host/rdma.c

830

ctrl->ctrl.max_hw_sectors = ctrl->max_fr_pages << (ilog2(SZ_4K) - 9);

drivers/pci/controller/dwc/pci-imx6.c

1468

.align = SZ_4K,

drivers/pci/controller/dwc/pci-keystone.c

301

dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);

drivers/pci/controller/dwc/pcie-designware.c

136

pci->dbi_base2 = pci->dbi_base + SZ_4K;

drivers/pci/controller/dwc/pcie-designware.c

156

pci->atu_size = SZ_4K;

drivers/pci/controller/dwc/pcie-qcom-ep.c

851

.align = SZ_4K,

drivers/pci/controller/pci-tegra.c

1465

resource_set_size(&pcie->cs, SZ_4K);

drivers/pci/controller/pci-tegra.c

451

base = 0xfe100000 + ((offset & ~(SZ_4K - 1)) >> 8);

drivers/pci/controller/pci-tegra.c

455

addr = pcie->cfg + (offset & (SZ_4K - 1));

drivers/pci/controller/pcie-iproc-msi.c

33

#define EQ_MEM_REGION_SIZE SZ_4K

drivers/pci/controller/pcie-iproc-msi.c

36

#define MSI_MEM_REGION_SIZE SZ_4K

drivers/pci/controller/pcie-rzg3s-host.c

1291

size = max(size, SZ_4K);

drivers/pci/controller/pcie-rzg3s-host.c

1301

size = ALIGN(size, SZ_4K);

drivers/pci/controller/pcie-rzg3s-host.c

1304

cpu_addr = ALIGN(cpu_addr, SZ_4K);

drivers/pci/controller/pcie-rzg3s-host.c

1305

pci_addr = ALIGN(pci_addr, SZ_4K);

drivers/pci/controller/pcie-rzg3s-host.c

1357

res_start = ALIGN(res_start, SZ_4K);

drivers/pci/controller/pcie-rzg3s-host.c

1359

size = ALIGN(size, SZ_4K);

drivers/pci/controller/pcie-xilinx.c

210

phys_addr_t pa = ALIGN_DOWN(virt_to_phys(pcie), SZ_4K);

drivers/pci/controller/pcie-xilinx.c

481

phys_addr_t pa = ALIGN_DOWN(virt_to_phys(pcie), SZ_4K);

drivers/pci/controller/plda/pcie-microchip-host.c

628

val = ALIGN_DOWN(lower_32_bits(pcie_addr), SZ_4K);

drivers/pci/controller/plda/pcie-plda-host.c

506

val = ALIGN_DOWN(lower_32_bits(axi_addr), SZ_4K);

drivers/pci/endpoint/functions/pci-epf-mhi.c

323

if (buf_info->size < SZ_4K)

drivers/pci/endpoint/functions/pci-epf-mhi.c

394

if (buf_info->size < SZ_4K)

drivers/pci/endpoint/functions/pci-epf-vntb.c

1401

*addr_align = SZ_4K;

drivers/pci/setup-bus.c

1035

#define PCI_P2P_DEFAULT_IO_ALIGN SZ_4K

drivers/pcmcia/omap_cf.c

163

io->start = cf->phys_cf + SZ_4K;

drivers/pcmcia/omap_cf.c

206

struct resource iospace = DEFINE_RES_IO(SZ_64, SZ_4K);

drivers/pcmcia/omap_cf.c

240

status = pci_remap_iospace(&iospace, cf->phys_cf + SZ_4K);

drivers/perf/arm-cci.c

1453

.cntr_size = SZ_4K,

drivers/perf/arm-cci.c

1473

.cntr_size = SZ_4K,

drivers/perf/arm-ni.c

584

if (!devm_request_mem_region(ni->dev, res_start, SZ_4K, dev_name(ni->dev))) {

drivers/platform/x86/intel/ehl_pse_io.c

23

#define EHL_PSE_IO_DEV_SIZE SZ_4K

drivers/pmdomain/imx/gpcv2.c

1457

.max_register = SZ_4K,

drivers/pmdomain/imx/imx93-blk-ctrl.c

207

.max_register = SZ_4K,

drivers/pwm/pwm-dwc.c

32

.size = SZ_4K,

drivers/remoteproc/qcom_q6v5_mss.c

1441

max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K);

drivers/remoteproc/qcom_q6v5_mss.c

41

#define MBA_LOG_SIZE SZ_4K

drivers/remoteproc/qcom_q6v5_mss.c

482

return qcom_scm_assign_mem(addr, ALIGN(size, SZ_4K),

drivers/rpmsg/qcom_smd.c

825

bb_size = min(channel->fifo_size, SZ_4K);

drivers/scsi/elx/libefc_sli/sli4.c

113

page_size = SZ_4K;

drivers/scsi/elx/libefc_sli/sli4.c

324

page_size = SZ_4K;

drivers/scsi/elx/libefc_sli/sli4.h

1993

#define SLI_PAGE_SIZE SZ_4K

drivers/sh/intc/userimask.c

87

uimask = ioremap(addr, SZ_4K);

drivers/soc/qcom/llcc-qcom.c

51

#define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K)

drivers/soc/qcom/llcc-qcom.c

52

#define LLCC_TRP_ACT_CLEARn(n) (8 + n * SZ_4K)

drivers/soc/qcom/llcc-qcom.c

53

#define LLCC_TRP_STATUSn(n) (4 + n * SZ_4K)

drivers/soc/qcom/mdt_loader.c

134

max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K);

drivers/soc/qcom/mdt_loader.c

264

max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K);

drivers/soc/qcom/rmtfs_mem.c

208

rmtfs_mem->addr += SZ_4K;

drivers/soc/qcom/rmtfs_mem.c

209

rmtfs_mem->size -= 2 * SZ_4K;

drivers/soc/qcom/smem.c

1074

region->virt_base = devm_ioremap_wc(smem->dev, region->aux_base, SZ_4K);

drivers/soc/qcom/smem.c

1075

ptable_start = region->aux_base + region->size - SZ_4K;

drivers/soc/qcom/smem.c

1077

smem->ptable = devm_ioremap_wc(smem->dev, ptable_start, SZ_4K);

drivers/soc/ti/pm33xx.c

150

gic_dist_base = ioremap(AM43XX_GIC_DIST_BASE, SZ_4K);

drivers/spi/spi-airoha-snfi.c

207

#define SPI_NAND_CACHE_SIZE (SZ_4K + SZ_256)

drivers/spi/spi-intel.c

573

round_up(addr + 1, SZ_4K)) - addr;

drivers/spi/spi-intel.c

630

round_up(addr + 1, SZ_4K)) - addr;

drivers/spi/spi-mtk-snfi.c

572

case SZ_4K:

drivers/spi/spi-nxp-xspi.c

322

.ahb_buf_size = SZ_4K, /* (1024 * 4 bytes) */

drivers/spi/spi-omap2-mcspi.c

1448

.max_xfer_len = SZ_4K - 1,

drivers/spi/spi-sprd-adi.c

62

#define ADI_10BIT_SLAVE_ADDR_SIZE SZ_4K

drivers/staging/media/ipu7/ipu7-cpd.c

21

#define MAX_MANIFEST_SIZE (SZ_4K * sizeof(u32))

drivers/staging/media/ipu7/ipu7-mmu.c

601

mmu_info->pgsize_bitmap = SZ_4K;

drivers/staging/media/ipu7/ipu7-mmu.c

670

init_iova_domain(&dmap->iovad, SZ_4K, base_pfn);

drivers/staging/media/meson/vdec/codec_h264.c

65

static const u8 eos_sequence[SZ_4K] = {

drivers/staging/media/meson/vdec/esparser.h

34

#define ESPARSER_MIN_PACKET_SIZE SZ_4K

drivers/staging/media/meson/vdec/vdec_helpers.c

59

return SZ_4K * width_64 * height_32;

drivers/tee/qcomtee/shm.c

18

#define MAX_OUTBOUND_BUFFER_SIZE SZ_4K

drivers/thermal/qoriq_thermal.c

288

.max_register = SZ_4K,

drivers/thunderbolt/dma_test.c

18

#define DMA_TEST_FRAME_SIZE SZ_4K

drivers/thunderbolt/nvm.c

107

if (!IS_ALIGNED(hdr_size, SZ_4K))

drivers/thunderbolt/nvm.c

241

if (!IS_ALIGNED(hdr_size, SZ_4K))

drivers/tty/serial/earlycon.c

301

port->membase = earlycon_map(port->mapbase, SZ_4K);

drivers/tty/serial/lpc32xx_hs.c

523

release_mem_region(port->mapbase, SZ_4K);

drivers/tty/serial/lpc32xx_hs.c

534

if (!request_mem_region(port->mapbase, SZ_4K, MODNAME))

drivers/tty/serial/lpc32xx_hs.c

537

port->membase = ioremap(port->mapbase, SZ_4K);

drivers/tty/serial/lpc32xx_hs.c

539

release_mem_region(port->mapbase, SZ_4K);

drivers/usb/cdns3/cdns3-gadget.c

1276

if (ALIGN_DOWN(trb->buffer, SZ_4K) !=

drivers/usb/cdns3/cdns3-gadget.c

1277

ALIGN_DOWN(trb->buffer + length, SZ_4K))

drivers/usb/gadget/udc/renesas_usb3.c

2177

else if (ram_size <= SZ_4K)

drivers/usb/gadget/udc/renesas_usb3.c

2785

.ramsize_per_pipe = SZ_4K,

drivers/usb/gadget/udc/renesas_usb3.c

2791

.ramsize_per_pipe = SZ_4K,

drivers/usb/gadget/udc/renesas_usb3.c

2798

.ramsize_per_pipe = SZ_4K,

drivers/usb/host/ohci-pci.c

182

hcd->regs += SZ_4K; /* SZ_4K = 0x1000 */

drivers/vfio/vfio_main.c

1185

if (report.page_size < SZ_4K || !is_power_of_2(report.page_size))

drivers/video/fbdev/omap2/omapfb/dss/dispc.c

40

#define DISPC_SZ_REGS SZ_4K

drivers/virt/coco/sev-guest/sev-guest.c

368

rep_len = SZ_4K;

drivers/virt/coco/sev-guest/sev-guest.c

369

man_len = SZ_4K;

drivers/virt/coco/sev-guest/sev-guest.c

487

const u32 report_size = SZ_4K;

fs/btrfs/fs.c

151

if (blocksize == PAGE_SIZE || blocksize == SZ_4K || blocksize == BTRFS_MIN_BLOCKSIZE)

fs/btrfs/fs.h

61

#define BTRFS_MIN_BLOCKSIZE (SZ_4K)

fs/btrfs/inode.c

9443

if (fs_info->sectorsize < SZ_4K || fs_info->sectorsize > SZ_64K)

fs/btrfs/scrub.c

64

#define SCRUB_MAX_SECTORS_PER_BLOCK (BTRFS_MAX_METADATA_BLOCKSIZE / SZ_4K)

fs/btrfs/tests/extent-map-tests.c

101

em->len = SZ_4K;

fs/btrfs/tests/extent-map-tests.c

103

em->disk_num_bytes = SZ_4K;

fs/btrfs/tests/extent-map-tests.c

104

em->ram_bytes = SZ_4K;

fs/btrfs/tests/extent-map-tests.c

1141

fs_info = btrfs_alloc_dummy_fs_info(SZ_4K, SZ_4K);

fs/btrfs/tests/extent-map-tests.c

181

em->len = SZ_4K;

fs/btrfs/tests/extent-map-tests.c

202

em->start = SZ_4K;

fs/btrfs/tests/extent-map-tests.c

203

em->len = SZ_4K;

fs/btrfs/tests/extent-map-tests.c

204

em->disk_bytenr = SZ_4K;

fs/btrfs/tests/extent-map-tests.c

205

em->disk_num_bytes = SZ_4K;

fs/btrfs/tests/extent-map-tests.c

206

em->ram_bytes = SZ_4K;

fs/btrfs/tests/extent-map-tests.c

225

em->len = SZ_4K;

fs/btrfs/tests/extent-map-tests.c

241

if (em->start != 0 || btrfs_extent_map_end(em) != SZ_4K ||

fs/btrfs/tests/extent-map-tests.c

262

u64 len = SZ_4K;

fs/btrfs/tests/extent-map-tests.c

273

em->start = SZ_4K;

fs/btrfs/tests/extent-map-tests.c

274

em->len = SZ_4K;

fs/btrfs/tests/extent-map-tests.c

275

em->disk_bytenr = SZ_4K;

fs/btrfs/tests/extent-map-tests.c

276

em->disk_num_bytes = SZ_4K;

fs/btrfs/tests/extent-map-tests.c

277

em->ram_bytes = SZ_4K;

fs/btrfs/tests/extent-map-tests.c

371

u64 len = SZ_4K;

fs/btrfs/tests/extent-map-tests.c

492

ret = __test_case_4(fs_info, inode, SZ_4K);

fs/btrfs/tests/extent-map-tests.c

513

em->disk_num_bytes = SZ_4K;

fs/btrfs/tests/extent-map-tests.c

537

{ .start = SZ_4K * 3, .len = SZ_4K * 3}, /* [12k, 24k) */

fs/btrfs/tests/extent-map-tests.c

538

{ .start = SZ_4K * 6, .len = SZ_4K * 3}, /* [24k, 36k) */

fs/btrfs/tests/extent-map-tests.c

539

{ .start = SZ_32K + SZ_4K, .len = SZ_4K}, /* [36k, 40k) */

fs/btrfs/tests/extent-map-tests.c

540

{ .start = SZ_4K * 10, .len = SZ_4K * 6}, /* [40k, 64k) */

fs/btrfs/tests/extent-map-tests.c

544

{ .start = SZ_4K * 5, .len = SZ_4K}, /* [20k, 24k) */

fs/btrfs/tests/extent-map-tests.c

545

{ .start = SZ_4K * 6, .len = SZ_4K * 3}, /* [24k, 36k) */

fs/btrfs/tests/extent-map-tests.c

546

{ .start = SZ_32K + SZ_4K, .len = SZ_4K}, /* [36k, 40k) */

fs/btrfs/tests/extent-map-tests.c

547

{ .start = SZ_4K * 10, .len = SZ_4K * 6}, /* [40k, 64k) */

fs/btrfs/tests/extent-map-tests.c

551

{ .start = SZ_4K * 5, .len = SZ_4K}, /* [20k, 24k) */

fs/btrfs/tests/extent-map-tests.c

552

{ .start = SZ_4K * 6, .len = SZ_4K}, /* [24k, 28k) */

fs/btrfs/tests/extent-map-tests.c

553

{ .start = SZ_32K, .len = SZ_4K}, /* [32k, 36k) */

fs/btrfs/tests/extent-map-tests.c

554

{ .start = SZ_32K + SZ_4K, .len = SZ_4K}, /* [36k, 40k) */

fs/btrfs/tests/extent-map-tests.c

555

{ .start = SZ_4K * 10, .len = SZ_4K * 6}, /* [40k, 64k) */

fs/btrfs/tests/extent-map-tests.c

559

{ .start = SZ_4K * 5, .len = SZ_4K}, /* [20k, 24k) */

fs/btrfs/tests/extent-map-tests.c

560

{ .start = SZ_4K * 6, .len = SZ_4K}, /* [24k, 28k) */

fs/btrfs/tests/extent-map-tests.c

632

ret = add_compressed_extent(inode, 0, SZ_4K * 3, 0);

fs/btrfs/tests/extent-map-tests.c

639

ret = add_compressed_extent(inode, SZ_4K * 3, SZ_4K * 3, SZ_4K);

fs/btrfs/tests/extent-map-tests.c

646

ret = add_compressed_extent(inode, SZ_4K * 6, SZ_4K * 3, SZ_8K);

fs/btrfs/tests/extent-map-tests.c

653

ret = add_compressed_extent(inode, SZ_32K + SZ_4K, SZ_4K, SZ_4K * 3);

fs/btrfs/tests/extent-map-tests.c

660

ret = add_compressed_extent(inode, SZ_4K * 10, SZ_4K * 6, SZ_16K);

fs/btrfs/tests/extent-map-tests.c

668

end = (3 * SZ_4K) - 1;

fs/btrfs/tests/extent-map-tests.c

675

start = SZ_4K * 3;

fs/btrfs/tests/extent-map-tests.c

676

end = SZ_16K + SZ_4K - 1;

fs/btrfs/tests/extent-map-tests.c

683

start = SZ_32K - SZ_4K;

fs/btrfs/tests/extent-map-tests.c

717

ret = add_compressed_extent(inode, 0, SZ_4K, 0);

fs/btrfs/tests/extent-map-tests.c

721

ret = add_compressed_extent(inode, SZ_4K, SZ_4K, 0);

fs/btrfs/tests/extent-map-tests.c

732

em->start = SZ_4K;

fs/btrfs/tests/extent-map-tests.c

733

em->len = SZ_4K;

fs/btrfs/tests/extent-map-tests.c

751

if (em->len != SZ_4K) {

fs/btrfs/tests/extent-map-tests.c

789

em->disk_num_bytes = SZ_4K;

fs/btrfs/tests/extent-map-tests.c

876

if (btrfs_extent_map_block_start(em) != SZ_32K + SZ_4K) {

fs/btrfs/tests/extent-map-tests.c

928

em->disk_num_bytes = SZ_4K;

fs/btrfs/tests/extent-map-tests.c

953

em->disk_num_bytes = SZ_4K;

fs/btrfs/tests/extent-map-tests.c

971

ret = btrfs_add_extent_mapping(inode, &em, SZ_1K * 140, SZ_4K);

fs/btrfs/tree-checker.c

243

SZ_4K);

fs/tests/exec_kunit.c

106

KUNIT_EXPECT_EQ(test, ARG_MAX, 32 * SZ_4K);

include/linux/amba/bus.h

175

.res = DEFINE_RES_MEM(base, SZ_4K), \

include/linux/amba/bus.h

186

.res = DEFINE_RES_MEM(base, SZ_4K), \

include/linux/arm_ffa.h

122

#define FFA_PAGE_SIZE SZ_4K

include/linux/qed/qed_chain.h

161

#define QED_CHAIN_PAGE_SIZE SZ_4K

include/uapi/drm/qaic_accel.h

17

#define QAIC_MANAGE_MAX_MSG_LENGTH SZ_4K

kernel/trace/trace.c

2575

#define FTRACE_KSTACK_ENTRIES (SZ_4K / FTRACE_KSTACK_NESTING)

kernel/unwind/deferred.c

42

((SZ_4K - sizeof(struct unwind_cache)) / sizeof(long))

lib/crypto/arm/blake2b.h

25

SZ_4K / BLAKE2B_BLOCK_SIZE);

lib/crypto/arm/chacha.h

86

unsigned int todo = min_t(unsigned int, bytes, SZ_4K);

lib/crypto/arm/poly1305.h

32

unsigned int todo = min_t(unsigned int, len, SZ_4K);

lib/crypto/arm64/chacha.h

80

unsigned int todo = min_t(unsigned int, bytes, SZ_4K);

lib/crypto/arm64/poly1305.h

31

unsigned int todo = min_t(unsigned int, len, SZ_4K);

lib/crypto/powerpc/chacha.h

59

unsigned int todo = min_t(unsigned int, bytes, SZ_4K);

lib/crypto/x86/blake2s.h

26

BUILD_BUG_ON(SZ_4K / BLAKE2S_BLOCK_SIZE < 8);

lib/crypto/x86/blake2s.h

35

SZ_4K / BLAKE2S_BLOCK_SIZE);

lib/crypto/x86/chacha.h

147

unsigned int todo = min_t(unsigned int, bytes, SZ_4K);

lib/crypto/x86/poly1305.h

100

SZ_4K % POLY1305_BLOCK_SIZE);

lib/crypto/x86/poly1305.h

118

const unsigned int bytes = min(len, SZ_4K);

lib/crypto/x86/poly1305.h

99

BUILD_BUG_ON(SZ_4K < POLY1305_BLOCK_SIZE ||

mm/memcontrol.c

127

#define SEQ_BUF_SIZE SZ_4K

security/loadpin/loadpin.c

292

data = kzalloc(SZ_4K, GFP_KERNEL);

security/loadpin/loadpin.c

298

rc = kernel_read_file(fd_file(f), 0, (void **)&data, SZ_4K - 1, NULL, READING_POLICY);

sound/soc/amd/acp-pcm-dma.c

217

+ (pte_offset * SZ_4K) + (i * (size / 2));

sound/soc/amd/acp-pcm-dma.c

234

(pte_offset * SZ_4K) + (i * (size / 2));

sound/soc/intel/avs/icl.c

70

u8 rsvd[SZ_4K];

sound/soc/intel/avs/icl.c

72

u8 slot_array[AVS_ICL_MEMWND2_SLOTS_COUNT][SZ_4K];

sound/soc/intel/avs/icl.c

96

return offsetof(struct avs_icl_memwnd2, slot_array) + i * SZ_4K;

sound/soc/intel/avs/messages.h

16

#define AVS_MAILBOX_SIZE SZ_4K

sound/soc/intel/avs/registers.h

119

#define AVS_WINDOW_CHUNK_SIZE SZ_4K

tools/testing/cxl/test/mem.c

1731

cxl_mbox->payload_size = SZ_4K;

tools/testing/cxl/test/mem.c

181

u8 event_buf[SZ_4K];

tools/testing/memblock/tests/basic_api.c

1288

.size = SZ_4K

tools/testing/memblock/tests/basic_api.c

1544

.size = SZ_4K

tools/testing/memblock/tests/basic_api.c

1972

.size = SZ_4K

tools/testing/nvdimm/test/nfit.c

1703

sizeof(struct nd_cmd_ars_status) + SZ_4K, GFP_KERNEL);

tools/testing/nvdimm/test/nfit.c

2965

.max_xfer = SZ_4K,

tools/testing/nvdimm/test/nfit.c

2975

|| cmd.cfg_size.max_xfer != SZ_4K) {

tools/testing/nvdimm/test/nfit.c

459

nd_cmd->max_xfer = SZ_4K;

tools/testing/nvdimm/test/nfit.c

519

ars_recs = SZ_4K / sizeof(struct nd_ars_record);

tools/testing/nvdimm/test/nfit.c

890

int max = SZ_4K / sizeof(struct nd_error_stat_query_record);

tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c

184

cmdq_size = ((cbaser & 0xFF) + 1) * SZ_4K;

tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c

76

cbaser = ((size / SZ_4K) - 1) |

tools/testing/selftests/kvm/lib/arm64/processor.c

62

return (vm->page_size == SZ_4K || vm->page_size == SZ_16K) &&

tools/testing/selftests/vfio/vfio_dma_mapping_test.c

176

case SZ_4K: