bin/ksh/c_ksh.c

1049

if (!evaluate(*wp, &val, KSH_RETURN_ERROR, true)) {

bin/ksh/c_ksh.c

1156

if (!(t = gettrap(p + 1, true))) {

bin/ksh/c_ksh.c

1170

if (!(t = gettrap(builtin_opt.optarg, true))) {

bin/ksh/c_ksh.c

1293

if (!*var || *skip_varname(var, true)) {

bin/ksh/c_ksh.c

711

(fset&UCASEV_AL) ? true : false);

bin/ksh/c_sh.c

505

p = gettrap(*wp++, true);

bin/ksh/c_sh.c

529

warningf(true, "%s: bad number", arg);

bin/ksh/c_sh.c

594

warningf(true, "%s: cannot %s", wp[0], wp[0]);

bin/ksh/c_sh.c

603

warningf(true, "%s: can only %s %d level(s)",

bin/ksh/edit.c

127

x_mode(true);

bin/ksh/edit.c

781

saw_slash = true;

bin/ksh/edit.c

98

x_mode(true);

bin/ksh/emacs.c

1177

x_delete(ndel, true);

bin/ksh/emacs.c

1237

xlp_valid = true;

bin/ksh/emacs.c

1630

x_delete(rsize, true);

bin/ksh/emacs.c

2163

xlp_valid = true;

bin/ksh/emacs.c

285

xlp_valid = true;

bin/ksh/emacs.c

563

x_delete(x_bword(), true);

bin/ksh/emacs.c

584

x_delete(x_fword(), true);

bin/ksh/emacs.c

986

xlp_valid = true;

bin/ksh/eval.c

1127

!gmatch(name, sp, true))

bin/ksh/eval.c

276

KSH_UNWIND_ERROR, true);

bin/ksh/exec.c

1109

warningf(true, "%s: %s",

bin/ksh/exec.c

1121

warningf(true, "%s: restricted", cp);

bin/ksh/exec.c

1129

warningf(true, "cannot %s %s: %s",

bin/ksh/exec.c

1153

if (ksh_dup2(u, iop->unit, true) < 0) {

bin/ksh/exec.c

1154

warningf(true,

bin/ksh/exec.c

1194

warningf(true, "here document missing");

bin/ksh/exec.c

1203

warningf(true, "can't %s temporary file %s: %s",

bin/ksh/exec.c

1236

warningf(true, "error writing %s: %s", h->name,

bin/ksh/exec.c

195

coproc_cleanup(true);

bin/ksh/exec.c

276

volatile bool is_first = true;

bin/ksh/exec.c

477

warningf(true,

bin/ksh/exec.c

534

warningf(true, "%s: restricted", cp);

bin/ksh/exec.c

556

warningf(true,

bin/ksh/exec.c

562

warningf(true,

bin/ksh/exec.c

570

warningf(true,

bin/ksh/exec.c

578

warningf(true,

bin/ksh/exec.c

609

Flag(FXTRACE) = tp->flag & TRACE ? true : false;

bin/ksh/exec.c

663

warningf(true, "%s: cannot execute - %s", cp,

bin/ksh/exec.c

667

warningf(true, "%s: not found", cp);

bin/ksh/exec.c

772

tp = findfunc(name, hash(name), true);

bin/ksh/expr.c

251

warningf(true, "%s: unexpected `%s'", es->expression, s);

bin/ksh/expr.c

255

warningf(true, "%s: bad number `%s'", es->expression, str);

bin/ksh/expr.c

259

warningf(true, "%s: expression recurses on parameter `%s'",

bin/ksh/expr.c

264

warningf(true, "%s: %s requires lvalue",

bin/ksh/expr.c

269

warningf(true, "%s: %s applied to read only variable",

bin/ksh/expr.c

275

warningf(true, "%s: %s", es->expression, str);

bin/ksh/expr.c

309

vl = do_ppmm(es, op, es->val, true);

bin/ksh/history.c

169

hfirst = lflag ? hist_get("-16", true, true) :

bin/ksh/history.c

180

hfirst = hist_get(first, (lflag || last) ? true : false,

bin/ksh/history.c

181

lflag ? true : false);

bin/ksh/history.c

184

hlast = last ? hist_get(last, true, lflag ? true : false) :

bin/ksh/io.c

285

ksh_dup2(ofd, fd, true); /* XXX: what to do if this fails? */

bin/ksh/io.c

34

error_prefix(true);

bin/ksh/io.c

69

error_prefix(true);

bin/ksh/io.c

93

error_prefix(true);

bin/ksh/jobs.c

1037

warningf(true,

bin/ksh/jobs.c

189

tty_init(true);

bin/ksh/jobs.c

239

tty_init(true);

bin/ksh/jobs.c

512

(void) ksh_dup2(fd, 0, true);

bin/ksh/jobs.c

591

warningf(true, "%s: no last job", __func__);

bin/ksh/jobs.c

771

warningf(true,

bin/ksh/lex.c

229

int h = findhist(-1, 0, match, true);

bin/ksh/lex.c

938

error_prefix(true);

bin/ksh/main.c

452

shell(s, true); /* doesn't return */

bin/ksh/syn.c

105

reject = true;

bin/ksh/syn.c

143

reject = true;

bin/ksh/syn.c

185

t = c_list(true);

bin/ksh/syn.c

208

reject = true;

bin/ksh/syn.c

216

reject = true;

bin/ksh/syn.c

319

if (!is_wdvarname(yylval.cp, true))

bin/ksh/syn.c

333

t->left = c_list(true);

bin/ksh/syn.c

352

t->left = c_list(true);

bin/ksh/syn.c

383

t = function_body(yylval.cp, true);

bin/ksh/syn.c

434

list = c_list(true);

bin/ksh/syn.c

446

t->left = c_list(true);

bin/ksh/syn.c

460

if ((t = c_list(true)) == NULL)

bin/ksh/syn.c

466

t->left = c_list(true);

bin/ksh/syn.c

471

reject = true;

bin/ksh/syn.c

513

reject = true;

bin/ksh/syn.c

518

reject = true;

bin/ksh/syn.c

523

t->left = c_list(true);

bin/ksh/syn.c

55

((reject) ? (symbol) : (reject = true, symbol = yylex(cf)))

bin/ksh/syn.c

561

reject = true;

bin/ksh/syn.c

600

reject = true;

bin/ksh/syn.c

633

{ "if", IF, true },

bin/ksh/syn.c

634

{ "then", THEN, true },

bin/ksh/syn.c

635

{ "else", ELSE, true },

bin/ksh/syn.c

636

{ "elif", ELIF, true },

bin/ksh/syn.c

637

{ "fi", FI, true },

bin/ksh/syn.c

638

{ "case", CASE, true },

bin/ksh/syn.c

639

{ "esac", ESAC, true },

bin/ksh/syn.c

640

{ "for", FOR, true },

bin/ksh/syn.c

641

{ "select", SELECT, true },

bin/ksh/syn.c

642

{ "while", WHILE, true },

bin/ksh/syn.c

643

{ "until", UNTIL, true },

bin/ksh/syn.c

644

{ "do", DO, true },

bin/ksh/syn.c

645

{ "done", DONE, true },

bin/ksh/syn.c

646

{ "in", IN, true },

bin/ksh/syn.c

647

{ "function", FUNCTION, true },

bin/ksh/syn.c

648

{ "time", TIME, true },

bin/ksh/syn.c

649

{ "{", '{', true },

bin/ksh/syn.c

650

{ "}", '}', true },

bin/ksh/syn.c

651

{ "!", BANG, true },

bin/ksh/syn.c

652

{ "[[", DBRACKET, true },

bin/ksh/syn.c

691

reject = true;

bin/ksh/syn.c

87

reject = true;

bin/ksh/syn.c

896

reject = true;

bin/ksh/var.c

150

*arrayp = true;

bin/ksh/var.c

155

evaluate(sub, &rval, KSH_UNWIND_ERROR, true);

bin/ksh/var.c

368

warningf(true, "%s: is read only", vq->name);

bin/ksh/var.c

393

if (!v_evaluate(vq, s, error_ok, true))

bin/ksh/var.c

644

vp = (set&LOCAL) ? local(tvar, (set & LOCAL_COPY) ? true : false) :

bin/ksh/var.c

837

char *p = skip_wdvarname(s, true);

games/fortune/fortune/fortune.c

1208

Found_one = true;

games/fortune/fortune/fortune.c

270

All_forts = true;

games/fortune/fortune/fortune.c

278

Equal_probs = true;

games/fortune/fortune/fortune.c

281

Find_files = true;

games/fortune/fortune/fortune.c

284

Long_only = true;

games/fortune/fortune/fortune.c

288

Offend = true;

games/fortune/fortune/fortune.c

291

Short_only = true;

games/fortune/fortune/fortune.c

295

Wait = true;

games/fortune/fortune/fortune.c

298

Match = true;

games/fortune/fortune/fortune.c

404

was_malloc = true;

games/fortune/fortune/fortune.c

421

was_malloc = true;

games/fortune/fortune/fortune.c

441

was_malloc = true;

games/fortune/fortune/fortune.c

917

did_noprobs = true;

games/fortune/strfile/strfile.c

267

Iflag = true;

games/fortune/strfile/strfile.c

270

Oflag = true;

games/fortune/strfile/strfile.c

273

Rflag = true;

games/fortune/strfile/strfile.c

276

Sflag = true;

games/fortune/strfile/strfile.c

279

Xflag = true;

games/hunt/huntd/driver.c

324

int true = 1;

games/hunt/huntd/driver.c

438

if (setsockopt(Server_socket, SOL_SOCKET, SO_REUSEPORT, &true,

games/hunt/huntd/driver.c

439

sizeof true) < 0)

games/phantasia/setup.c

132

Enrgyvoid.ev_active = true;

include/stdbool.h

28

#define true true

include/stdbool.h

39

#define true true

lib/libc/gen/devname.c

87

failure = true;

lib/libc/gen/getpwent.c

258

bool remap = true;

lib/libc/gen/getpwent.c

789

return getpwnam_internal(name, pw, buf, buflen, pwretp, false, true);

lib/libc/gen/getpwent.c

813

my_errno = getpwnam_internal(name, NULL, NULL, 0, &pw, true, false);

lib/libc/gen/getpwent.c

873

return getpwuid_internal(uid, pw, buf, buflen, pwretp, false, true);

lib/libc/gen/getpwent.c

897

my_errno = getpwuid_internal(uid, NULL, NULL, 0, &pw, true, false);

lib/libcbor/src/cbor.c

159

return _cbor_copy_int(item, true);

lib/libcbor/src/cbor/arrays.c

41

return true;

lib/libcbor/src/cbor/arrays.c

79

return true;

lib/libcbor/src/cbor/bytestrings.c

118

return true;

lib/libcbor/src/cbor/common.c

19

bool _cbor_enable_assert = true;

lib/libcbor/src/cbor/common.h

66

block _cbor_enable_assert = true; \

lib/libcbor/src/cbor/internal/builder_callbacks.c

111

ctx->syntax_error = true;

lib/libcbor/src/cbor/internal/builder_callbacks.c

119

ctx->creation_failed = true; \

lib/libcbor/src/cbor/internal/builder_callbacks.c

129

ctx->creation_failed = true; \

lib/libcbor/src/cbor/internal/builder_callbacks.c

138

ctx->creation_failed = true; \

lib/libcbor/src/cbor/internal/builder_callbacks.c

220

ctx->creation_failed = true;

lib/libcbor/src/cbor/internal/builder_callbacks.c

229

ctx->creation_failed = true;

lib/libcbor/src/cbor/internal/builder_callbacks.c

240

ctx->creation_failed = true;

lib/libcbor/src/cbor/internal/builder_callbacks.c

264

ctx->syntax_error = true;

lib/libcbor/src/cbor/internal/builder_callbacks.c

272

ctx->creation_failed = true;

lib/libcbor/src/cbor/internal/builder_callbacks.c

280

ctx->creation_failed = true;

lib/libcbor/src/cbor/internal/builder_callbacks.c

291

ctx->creation_failed = true;

lib/libcbor/src/cbor/internal/builder_callbacks.c

378

ctx->syntax_error = true;

lib/libcbor/src/cbor/internal/builder_callbacks.c

45

ctx->creation_failed = true;

lib/libcbor/src/cbor/internal/builder_callbacks.c

59

ctx->creation_failed = true;

lib/libcbor/src/cbor/internal/builder_callbacks.c

72

ctx->creation_failed = true;

lib/libcbor/src/cbor/internal/builder_callbacks.c

79

ctx->creation_failed = true;

lib/libcbor/src/cbor/internal/memory_utils.c

26

if (a <= 1 || b <= 1) return true;

lib/libcbor/src/cbor/maps.c

103

return true;

lib/libcbor/src/cbor/maps.c

92

return true;

lib/libcbor/src/cbor/streaming.c

21

return true;

lib/libcbor/src/cbor/streaming.c

550

callbacks->boolean(context, true);

lib/libcbor/src/cbor/strings.c

107

return true;

lib/libcurses/tinfo/lib_win32con.c

1177

a = _nc_console_MapColor(true, COLOR_WHITE) |

lib/libcurses/tinfo/lib_win32con.c

865

while (true) {

lib/libexpat/examples/element_declarations.c

175

return true;

lib/libexpat/lib/xmlparse.c

821

bool tolerable = true;

lib/libexpat/lib/xmltok.c

378

output_exhausted = true;

lib/libexpat/lib/xmltok.c

386

input_incomplete = true;

lib/libexpat/tests/alloc_tests.c

2105

bool values[] = {true, false};

lib/libexpat/tests/basic_tests.c

1251

true},

lib/libexpat/tests/basic_tests.c

1265

const bool rejection_expected = true;

lib/libexpat/tests/basic_tests.c

347

bool success = true;

lib/libexpat/tests/basic_tests.c

4905

{true, true, "\x3A"}, // [0011 1010] = ASCII colon ':'

lib/libexpat/tests/basic_tests.c

4907

{true, false, "\x39"}, // [0011 1001] = ASCII nine '9'

lib/libexpat/tests/basic_tests.c

4911

{true, true, "\xDB\xA5"}, // [1101 1011] [1010 0101] =

lib/libexpat/tests/basic_tests.c

4916

{true, false, "\xCC\x81"}, // [1100 1100] [1000 0001] =

lib/libexpat/tests/basic_tests.c

4923

{true, true, "\xE0\xA4\x85"}, // [1110 0000] [1010 0100] [1000 0101] =

lib/libexpat/tests/basic_tests.c

4930

{true, false, "\xE0\xA4\x81"}, // [1110 0000] [1010 0100] [1000 0001] =

lib/libexpat/tests/basic_tests.c

4938

const bool atNameStart[] = {true, false};

lib/libexpat/tests/basic_tests.c

4962

bool success = true;

lib/libfido2/src/cbor.c

940

if (cbor_isa_uint(key) == true &&

lib/libfido2/src/cbor.c

964

} else if (cbor_isa_negint(key) == true &&

lib/libfido2/src/cbor.c

968

if (cbor_isa_uint(val) == true &&

lib/libfido2/src/config.c

164

if (force && (argv[2] = cbor_build_bool(true)) == NULL) {

lib/libfido2/src/config.c

207

return config_pin_minlen(dev, 0, true, NULL, pin, &ms);

lib/libfido2/src/dev.c

376

dev->io_own = true;

lib/libfido2/src/dev.c

390

dev->io_own = true;

lib/libfido2/src/nfc.c

306

d->io_own = true;

lib/libradius/radius_attr.c

355

return (true);

lib/libradius/radius_attr.c

365

return (true);

libexec/tradcpp/directive.c

162

newstate->evertrue = true;

libexec/tradcpp/directive.c

190

expr = macroexpand(p2, line, strlen(line), true);

libexec/tradcpp/directive.c

266

expr = macroexpand(p2, line, strlen(line), true);

libexec/tradcpp/directive.c

302

ifstate->evertrue = true;

libexec/tradcpp/directive.c

303

ifstate->seenelse = true;

libexec/tradcpp/directive.c

425

return true;

libexec/tradcpp/directive.c

433

return true;

libexec/tradcpp/directive.c

478

text = macroexpand(p2, line, strlen(line), true);

libexec/tradcpp/directive.c

581

{ "define", true, d_define },

libexec/tradcpp/directive.c

585

{ "error", true, d_error },

libexec/tradcpp/directive.c

589

{ "include", true, d_include },

libexec/tradcpp/directive.c

590

{ "line", true, d_line },

libexec/tradcpp/directive.c

591

{ "pragma", true, d_pragma },

libexec/tradcpp/directive.c

592

{ "undef", true, d_undef },

libexec/tradcpp/directive.c

593

{ "warning", true, d_warning },

libexec/tradcpp/directive.c

659

incomment = true;

libexec/tradcpp/directive.c

724

ifstate = ifstate_create(NULL, NULL, true);

libexec/tradcpp/directive.c

77

incomment = true;

libexec/tradcpp/directive.c

82

inesc = true;

libexec/tradcpp/directive.c

85

inquote = true;

libexec/tradcpp/eval.c

216

return true;

libexec/tradcpp/eval.c

240

return true;

libexec/tradcpp/eval.c

256

return true;

libexec/tradcpp/eval.c

667

return true;

libexec/tradcpp/eval.c

680

return true;

libexec/tradcpp/eval.c

695

return true;

libexec/tradcpp/files.c

145

inquote = true;

libexec/tradcpp/files.c

238

ateof = true;

libexec/tradcpp/files.c

242

ateof = true;

libexec/tradcpp/files.c

332

needslash = true;

libexec/tradcpp/files.c

375

pf = place_addfile(place, name, true);

libexec/tradcpp/files.c

432

file_read(pf, fd, name, true);

libexec/tradcpp/macro.c

1231

inquote = true;

libexec/tradcpp/macro.c

1249

expstate_init(&es, true, honordefined);

libexec/tradcpp/macro.c

177

return true;

libexec/tradcpp/macro.c

254

return true;

libexec/tradcpp/macro.c

560

return true;

libexec/tradcpp/macro.c

625

m->hasparams = true;

libexec/tradcpp/macro.c

654

m = macrotable_find(macro, true);

libexec/tradcpp/macro.c

901

m->inuse = true;

libexec/tradcpp/macro.c

990

expand_missingargs(es, p, true);

libexec/tradcpp/main.c

316

commandline_addfile(p, name, true);

libexec/tradcpp/main.c

459

files_addquotepath(dir, true);

libexec/tradcpp/main.c

460

files_addbracketpath(dir, true);

libexec/tradcpp/main.c

469

files_addquotepath(dir, true);

libexec/tradcpp/main.c

470

files_addbracketpath(dir, true);

libexec/tradcpp/main.c

476

files_addquotepath(dir, true);

libexec/tradcpp/main.c

477

files_addbracketpath(dir, true);

libexec/tradcpp/main.c

54

.do_stdinc = true,

libexec/tradcpp/main.c

55

.do_stddef = true,

libexec/tradcpp/main.c

57

.do_output = true,

libexec/tradcpp/main.c

58

.output_linenumbers = true,

libexec/tradcpp/main.c

608

mode.do_macrolist = true;

libexec/tradcpp/main.c

610

mode.macrolist_include_expansions = true;

libexec/tradcpp/main.c

617

mode.do_macrolist = true;

libexec/tradcpp/main.c

618

mode.macrolist_include_stddef = true;

libexec/tradcpp/main.c

619

mode.macrolist_include_expansions = true;

libexec/tradcpp/main.c

627

mode.do_macrolist = true;

libexec/tradcpp/main.c

640

mode.do_trace = true;

libexec/tradcpp/main.c

649

mode.do_trace = true;

libexec/tradcpp/main.c

650

mode.trace_namesonly = true;

libexec/tradcpp/main.c

651

mode.trace_indented = true;

libexec/tradcpp/main.c

67

.depend_quote_target = true,

libexec/tradcpp/main.c

673

mode.depend_quote_target = true;

libexec/tradcpp/main.c

688

mode.do_depend = true;

libexec/tradcpp/main.c

689

mode.depend_report_system = true;

libexec/tradcpp/main.c

697

mode.do_depend = true;

libexec/tradcpp/main.c

706

mode.do_depend = true;

libexec/tradcpp/main.c

707

mode.depend_report_system = true;

libexec/tradcpp/main.c

714

mode.do_depend = true;

libexec/tradcpp/main.c

722

warns.nestcomment = true;

libexec/tradcpp/main.c

723

warns.undef = true;

libexec/tradcpp/main.c

724

warns.unused = true;

libexec/tradcpp/main.c

781

{ "C", &mode.output_retain_comments, true },

libexec/tradcpp/main.c

782

{ "CC", &mode.output_retain_comments, true },

libexec/tradcpp/main.c

783

{ "MG", &mode.depend_assume_generated, true },

libexec/tradcpp/main.c

784

{ "MP", &mode.depend_issue_fakerules, true },

libexec/tradcpp/main.c

786

{ "Wcomment", &warns.nestcomment, true },

libexec/tradcpp/main.c

787

{ "Wendif-labels", &warns.endiflabels, true },

libexec/tradcpp/main.c

788

{ "Werror", &mode.werror, true },

libexec/tradcpp/main.c

794

{ "Wundef", &warns.undef, true },

libexec/tradcpp/main.c

795

{ "Wunused-macros", &warns.unused, true },

libexec/tradcpp/main.c

796

{ "fdollars-in-identifiers", &mode.input_allow_dollars, true },

libexec/tradcpp/main.c

799

{ "p", &mode.output_cheaplinenumbers, true },

libexec/tradcpp/main.c

81

.endiflabels = true,

libexec/tradcpp/main.c

858

return true;

libexec/tradcpp/main.c

878

return true;

libexec/tradcpp/main.c

898

return true;

libexec/tradcpp/main.c

919

return true;

libexec/tradcpp/main.c

945

return true;

libexec/tradcpp/output.c

119

incomment = true;

libexec/tradcpp/output.c

143

inesc = true;

libexec/tradcpp/output.c

145

inquote = true;

libexec/tradcpp/place.c

246

return true;

libexec/tradcpp/place.c

258

return true;

libexec/tradcpp/place.c

308

overall_failure = true;

libexec/tradcpp/utils.c

243

return true;

regress/lib/libc/qsort/qsort_test.c

738

dump_table = true;

regress/lib/libc/qsort/qsort_test.c

750

timing = true;

regress/lib/libc/qsort/qsort_test.c

753

verbose = true;

regress/lib/libc/sys/t_dup.c

188

check_mode(false, true, false);

regress/lib/libc/sys/t_dup.c

263

check_mode(false, false, true);

regress/lib/libc/sys/t_dup.c

384

check_mode(true, false, false);

regress/lib/libc/sys/t_fork.c

316

ASSERT_EQ(!!WIFEXITED(status), true);

regress/lib/libc/sys/t_fork.c

327

ATF_REQUIRE_EQ(!!WIFEXITED(status), true);

regress/lib/libc/sys/t_getitimer.c

129

fail = true;

regress/lib/libc/sys/t_kevent.c

182

ATF_REQUIRE_ERRNO(EOPNOTSUPP, true);

regress/lib/libc/sys/t_msgget.c

234

fail = true;

regress/lib/libc/sys/t_sigaction.c

49

handler_called = true;

regress/lib/libc/sys/t_sigaltstack.c

47

handler_called = true;

regress/lib/libc/sys/t_sigaltstack.c

52

handler_use_altstack = true;

regress/lib/libc/sys/t_write.c

120

fail = true;

regress/lib/libm/msun/conj_test.c

82

ATF_REQUIRE(fpequal_cs(libcrealf(in), __real__ in, true));

regress/lib/libm/msun/conj_test.c

83

ATF_REQUIRE(fpequal_cs(libcreal(in), __real__ in, true));

regress/lib/libm/msun/conj_test.c

84

ATF_REQUIRE(fpequal_cs(libcreall(in), __real__ in, true));

regress/lib/libm/msun/conj_test.c

85

ATF_REQUIRE(fpequal_cs(libcimagf(in), __imag__ in, true));

regress/lib/libm/msun/conj_test.c

86

ATF_REQUIRE(fpequal_cs(libcimag(in), __imag__ in, true));

regress/lib/libm/msun/conj_test.c

87

ATF_REQUIRE(fpequal_cs(libcimagl(in), __imag__ in, true));

regress/lib/libm/msun/fmaxmin_test.c

54

ATF_CHECK_MSG(fpequal_cs(__result, (expected), true), \

regress/lib/libm/msun/next_test.c

252

if (!fpequal_cs(actual, expected, true)) {

regress/lib/libm/msun/test-utils.h

150

#define CHECK_FPEQUAL(x, y) CHECK_FPEQUAL_CS(x, y, true)

regress/lib/libm/msun/test-utils.h

172

return (fpequal_cs(creall(d1), creall(d2), true) &&

regress/lib/libm/msun/test-utils.h

173

fpequal_cs(cimagl(d1), cimagl(d2), true));

sbin/mountd/mountd.c

1003

if (!xdr_bool(xdrsp, &true))

sbin/mountd/mountd.c

1018

if (!xdr_bool(xdrsp, &true))

sbin/mountd/mountd.c

1025

if (!xdr_bool(xdrsp, &true))

sbin/mountd/mountd.c

940

int true = 1, false = 0;

sbin/mountd/mountd.c

946

if (!xdr_bool(xdrsp, &true))

sbin/mountd/mountd.c

995

int true = 1, false = 0, gotalldir = 0;

sys/arch/amd64/include/ghcb.h

146

_ghcb_mem_rw(addr, GHCB_SZ8, &val, true);

sys/arch/amd64/include/ghcb.h

155

_ghcb_mem_rw(addr, GHCB_SZ16, &val, true);

sys/arch/amd64/include/ghcb.h

164

_ghcb_mem_rw(addr, GHCB_SZ32, &val, true);

sys/arch/amd64/include/ghcb.h

173

_ghcb_mem_rw(addr, GHCB_SZ64, &val, true);

sys/arch/amd64/include/ghcb.h

206

_ghcb_io_rw(port, GHCB_SZ8, &val, true);

sys/arch/amd64/include/ghcb.h

215

_ghcb_io_rw(port, GHCB_SZ16, &val, true);

sys/arch/amd64/include/ghcb.h

224

_ghcb_io_rw(port, GHCB_SZ32, &val, true);

sys/arch/arm64/arm64/disasm.c

639

return true;

sys/arch/arm64/arm64/disasm.c

675

return true;

sys/arch/arm64/arm64/disasm.c

684

return true;

sys/arch/arm64/arm64/disasm.c

719

return true;

sys/arch/armv7/omap/if_cpsw.c

1106

sc->sc_rxeoq = true;

sys/arch/armv7/omap/if_cpsw.c

1116

sc->sc_rxrun = true;

sys/arch/armv7/omap/if_cpsw.c

1198

handled = true;

sys/arch/armv7/omap/if_cpsw.c

1205

sc->sc_txeoq = true;

sys/arch/armv7/omap/if_cpsw.c

1214

if (sc->sc_txeoq == true)

sys/arch/armv7/omap/if_cpsw.c

933

sc->sc_rxrun = true;

sys/arch/armv7/omap/if_cpsw.c

936

sc->sc_txrun = true;

sys/arch/armv7/omap/if_cpsw.c

937

sc->sc_txeoq = true;

sys/arch/armv7/omap/if_cpsw.c

976

if ((sc->sc_txrun == true) && cpsw_txintr(sc) == 0)

sys/arch/armv7/omap/if_cpsw.c

978

if ((sc->sc_rxrun == true) && cpsw_rxintr(sc) == 0)

sys/arch/luna88k/dev/siotty.c

216

sc->sc_rx_ready = true;

sys/arch/luna88k/dev/siotty.c

228

sc->sc_tx_done = true;

sys/arch/luna88k/dev/siotty.c

328

sc->sc_tx_busy = true;

sys/arch/luna88k/dev/xp.c

133

xp_matched = true;

sys/arch/luna88k/dev/xp.c

166

sc->sc_isopen = true;

sys/ddb/db_dwarf.c

116

return (true);

sys/ddb/db_dwarf.c

125

return (read_leb128(d, (uint64_t *)v, true));

sys/ddb/db_dwarf.c

145

return (true);

sys/ddb/db_dwarf.c

157

return (true);

sys/ddb/db_dwarf.c

167

return (true);

sys/ddb/db_dwarf.c

215

return (true);

sys/ddb/db_dwarf.c

281

emit = true;

sys/ddb/db_dwarf.c

292

emit = true;

sys/ddb/db_dwarf.c

293

end_sequence = true;

sys/ddb/db_dwarf.c

324

emit = true;

sys/ddb/db_dwarf.c

325

reset_basic_block = true;

sys/ddb/db_dwarf.c

353

basic_block = true;

sys/ddb/db_dwarf.c

359

prologue_end = true;

sys/ddb/db_dwarf.c

362

epilogue_begin = true;

sys/ddb/db_dwarf.c

385

have_last = true;

sys/ddb/db_dwarf.c

431

bool showdir = true;

sys/ddb/db_dwarf.c

69

return (true);

sys/dev/fdt/rkvop.c

275

false, true);

sys/dev/fdt/rkvop.c

382

return true;

sys/dev/i2c/ietp.c

206

if (ietp_iic_set_absolute_mode(sc, true) != 0) {

sys/dev/i2c/ietp.c

363

require_wakeup = true;

sys/dev/ic/anxdp.c

727

return true;

sys/dev/ic/dwhdmi.c

409

return true;

sys/dev/ic/qwx.c

12955

intersect = true;

sys/dev/ic/qwx.c

17171

ATH11K_SKB_RXCB(msdu)->is_eapol = true;

sys/dev/ic/qwx.c

20917

.lmac_ring = true,

sys/dev/ic/qwx.c

20925

.lmac_ring = true,

sys/dev/ic/qwx.c

20933

.lmac_ring = true,

sys/dev/ic/qwx.c

20941

.lmac_ring = true,

sys/dev/ic/qwx.c

20949

.lmac_ring = true,

sys/dev/ic/qwx.c

20957

.lmac_ring = true,

sys/dev/ic/qwx.c

20965

.lmac_ring = true,

sys/dev/ic/qwx.c

23040

ch->allow_ht = true;

sys/dev/ic/qwx.c

23042

ch->allow_vht = true;

sys/dev/ic/qwx.c

23043

ch->allow_he = true;

sys/dev/ic/qwx.c

23079

ch->psc_channel = true;

sys/dev/ic/qwx.c

24920

peer->dp_setup_done = true;

sys/dev/ic/qwx.c

25258

ti.enable_mesh = true;

sys/dev/ic/qwx.c

26213

arg->is_pmf_enabled = true;

sys/dev/ic/qwx.c

26325

arg->ht_flag = true;

sys/dev/ic/qwx.c

26337

arg->ldpc_flag = true;

sys/dev/ic/qwx.c

26340

arg->bw_40 = true;

sys/dev/ic/qwx.c

26350

arg->stbc_flag = true;

sys/dev/ic/qwx.c

26358

arg->stbc_flag = true;

sys/dev/ic/qwx.c

3658

.rxdma1_enable = true,

sys/dev/ic/qwx.c

3662

.htt_peer_map_v2 = true,

sys/dev/ic/qwx.c

3673

.fragment_160mhz = true,

sys/dev/ic/qwx.c

3679

.supports_monitor = true,

sys/dev/ic/qwx.c

3685

.cold_boot_calib = true,

sys/dev/ic/qwx.c

3686

.cbcal_restart_fw = true,

sys/dev/ic/qwx.c

3693

.fix_l1ss = true,

sys/dev/ic/qwx.c

3699

.alloc_cacheable_memory = true,

sys/dev/ic/qwx.c

3704

.dbr_debug_support = true,

sys/dev/ic/qwx.c

3710

.fixed_bdf_addr = true,

sys/dev/ic/qwx.c

3711

.fixed_mem_region = true,

sys/dev/ic/qwx.c

3721

.tcl_ring_retry = true,

sys/dev/ic/qwx.c

3750

.rxdma1_enable = true,

sys/dev/ic/qwx.c

3754

.htt_peer_map_v2 = true,

sys/dev/ic/qwx.c

3762

.fragment_160mhz = true,

sys/dev/ic/qwx.c

3768

.supports_monitor = true,

sys/dev/ic/qwx.c

3774

.cold_boot_calib = true,

sys/dev/ic/qwx.c

3775

.cbcal_restart_fw = true,

sys/dev/ic/qwx.c

3782

.fix_l1ss = true,

sys/dev/ic/qwx.c

3788

.alloc_cacheable_memory = true,

sys/dev/ic/qwx.c

3793

.dbr_debug_support = true,

sys/dev/ic/qwx.c

3799

.fixed_bdf_addr = true,

sys/dev/ic/qwx.c

3800

.fixed_mem_region = true,

sys/dev/ic/qwx.c

3810

.tcl_ring_retry = true,

sys/dev/ic/qwx.c

3829

.internal_sleep_clock = true,

sys/dev/ic/qwx.c

3838

.single_pdev_only = true,

sys/dev/ic/qwx.c

3841

.rx_mac_buf_ring = true,

sys/dev/ic/qwx.c

3842

.vdev_start_delay = true,

sys/dev/ic/qwx.c

3859

.supports_shadow_regs = true,

sys/dev/ic/qwx.c

3860

.idle_ps = true,

sys/dev/ic/qwx.c

3861

.supports_sta_ps = true,

sys/dev/ic/qwx.c

3867

.supports_suspend = true,

sys/dev/ic/qwx.c

3870

.fix_l1ss = true,

sys/dev/ic/qwx.c

3871

.credit_flow = true,

sys/dev/ic/qwx.c

3877

.supports_rssi_stats = true,

sys/dev/ic/qwx.c

3879

.fw_wmi_diag_event = true,

sys/dev/ic/qwx.c

3880

.current_cc_support = true,

sys/dev/ic/qwx.c

3882

.global_reset = true,

sys/dev/ic/qwx.c

3886

.m3_fw_support = true,

sys/dev/ic/qwx.c

3893

.support_off_channel_tx = true,

sys/dev/ic/qwx.c

3894

.supports_multi_bssid = true,

sys/dev/ic/qwx.c

3901

.tcl_ring_retry = true,

sys/dev/ic/qwx.c

3931

.rxdma1_enable = true,

sys/dev/ic/qwx.c

3935

.htt_peer_map_v2 = true,

sys/dev/ic/qwx.c

3949

.supports_monitor = true,

sys/dev/ic/qwx.c

3950

.full_monitor_mode = true,

sys/dev/ic/qwx.c

3963

.fix_l1ss = true,

sys/dev/ic/qwx.c

3968

.supports_dynamic_smps_6ghz = true,

sys/dev/ic/qwx.c

3969

.alloc_cacheable_memory = true,

sys/dev/ic/qwx.c

3974

.dbr_debug_support = true,

sys/dev/ic/qwx.c

3979

.m3_fw_support = true,

sys/dev/ic/qwx.c

3982

.static_window_map = true,

sys/dev/ic/qwx.c

3991

.tcl_ring_retry = true,

sys/dev/ic/qwx.c

4010

.internal_sleep_clock = true,

sys/dev/ic/qwx.c

4019

.single_pdev_only = true,

sys/dev/ic/qwx.c

4022

.rx_mac_buf_ring = true,

sys/dev/ic/qwx.c

4023

.vdev_start_delay = true,

sys/dev/ic/qwx.c

4040

.supports_shadow_regs = true,

sys/dev/ic/qwx.c

4041

.idle_ps = true,

sys/dev/ic/qwx.c

4042

.supports_sta_ps = true,

sys/dev/ic/qwx.c

4048

.supports_suspend = true,

sys/dev/ic/qwx.c

4050

.supports_regdb = true,

sys/dev/ic/qwx.c

4052

.credit_flow = true,

sys/dev/ic/qwx.c

4058

.supports_rssi_stats = true,

sys/dev/ic/qwx.c

4060

.fw_wmi_diag_event = true,

sys/dev/ic/qwx.c

4061

.current_cc_support = true,

sys/dev/ic/qwx.c

4063

.global_reset = true,

sys/dev/ic/qwx.c

4067

.m3_fw_support = true,

sys/dev/ic/qwx.c

4074

.support_off_channel_tx = true,

sys/dev/ic/qwx.c

4075

.supports_multi_bssid = true,

sys/dev/ic/qwx.c

4082

.tcl_ring_retry = true,

sys/dev/ic/qwx.c

4101

.internal_sleep_clock = true,

sys/dev/ic/qwx.c

4110

.single_pdev_only = true,

sys/dev/ic/qwx.c

4113

.rx_mac_buf_ring = true,

sys/dev/ic/qwx.c

4114

.vdev_start_delay = true,

sys/dev/ic/qwx.c

4130

.supports_shadow_regs = true,

sys/dev/ic/qwx.c

4131

.idle_ps = true,

sys/dev/ic/qwx.c

4132

.supports_sta_ps = true,

sys/dev/ic/qwx.c

4138

.supports_suspend = true,

sys/dev/ic/qwx.c

4140

.supports_regdb = true,

sys/dev/ic/qwx.c

4142

.credit_flow = true,

sys/dev/ic/qwx.c

4148

.supports_rssi_stats = true,

sys/dev/ic/qwx.c

4150

.fw_wmi_diag_event = true,

sys/dev/ic/qwx.c

4151

.current_cc_support = true,

sys/dev/ic/qwx.c

4153

.global_reset = true,

sys/dev/ic/qwx.c

4157

.m3_fw_support = true,

sys/dev/ic/qwx.c

4164

.support_off_channel_tx = true,

sys/dev/ic/qwx.c

4165

.supports_multi_bssid = true,

sys/dev/ic/qwx.c

4172

.tcl_ring_retry = true,

sys/dev/ic/qwx.c

4200

.single_pdev_only = true,

sys/dev/ic/qwx.c

4203

.rx_mac_buf_ring = true,

sys/dev/ic/qwx.c

4204

.vdev_start_delay = true,

sys/dev/ic/qwx.c

4220

.supports_shadow_regs = true,

sys/dev/ic/qwx.c

4221

.idle_ps = true,

sys/dev/ic/qwx.c

4222

.supports_sta_ps = true,

sys/dev/ic/qwx.c

4223

.cold_boot_calib = true,

sys/dev/ic/qwx.c

4230

.supports_regdb = true,

sys/dev/ic/qwx.c

4232

.credit_flow = true,

sys/dev/ic/qwx.c

4238

.supports_rssi_stats = true,

sys/dev/ic/qwx.c

4241

.current_cc_support = true,

sys/dev/ic/qwx.c

4250

.static_window_map = true,

sys/dev/ic/qwx.c

4251

.hybrid_bus_type = true,

sys/dev/ic/qwx.c

4252

.fixed_fw_mem = true,

sys/dev/ic/qwx.c

4254

.support_off_channel_tx = true,

sys/dev/ic/qwx.c

4255

.supports_multi_bssid = true,

sys/dev/ic/qwx.c

4263

.smp2p_wow_exit = true,

sys/dev/ic/qwx.c

4278

.internal_sleep_clock = true,

sys/dev/ic/qwx.c

4287

.single_pdev_only = true,

sys/dev/ic/qwx.c

4290

.rx_mac_buf_ring = true,

sys/dev/ic/qwx.c

4291

.vdev_start_delay = true,

sys/dev/ic/qwx.c

4308

.supports_shadow_regs = true,

sys/dev/ic/qwx.c

4309

.idle_ps = true,

sys/dev/ic/qwx.c

4310

.supports_sta_ps = true,

sys/dev/ic/qwx.c

4316

.supports_suspend = true,

sys/dev/ic/qwx.c

4318

.supports_regdb = true,

sys/dev/ic/qwx.c

4320

.credit_flow = true,

sys/dev/ic/qwx.c

4326

.supports_rssi_stats = true,

sys/dev/ic/qwx.c

4328

.fw_wmi_diag_event = true,

sys/dev/ic/qwx.c

4329

.current_cc_support = true,

sys/dev/ic/qwx.c

4331

.global_reset = true,

sys/dev/ic/qwx.c

4335

.m3_fw_support = true,

sys/dev/ic/qwx.c

4342

.support_off_channel_tx = true,

sys/dev/ic/qwx.c

4343

.supports_multi_bssid = true,

sys/dev/ic/qwx.c

4350

.tcl_ring_retry = true,

sys/dev/ic/qwx.c

9668

cached = true;

sys/dev/ic/qwz.c

10648

intersect = true;

sys/dev/ic/qwz.c

1289

return true;

sys/dev/ic/qwz.c

14545

ATH12K_SKB_RXCB(msdu)->is_eapol = true;

sys/dev/ic/qwz.c

15194

return true;

sys/dev/ic/qwz.c

1710

.single_pdev_only = true,

sys/dev/ic/qwz.c

1711

.internal_sleep_clock = true,

sys/dev/ic/qwz.c

1725

.rx_mac_buf_ring = true,

sys/dev/ic/qwz.c

1730

.supports_shadow_regs = true,

sys/dev/ic/qwz.c

20260

ch->allow_ht = true;

sys/dev/ic/qwz.c

20261

ch->allow_vht = true;

sys/dev/ic/qwz.c

20262

ch->allow_he = true;

sys/dev/ic/qwz.c

20287

ch->psc_channel = true;

sys/dev/ic/qwz.c

22065

peer->dp_setup_done = true;

sys/dev/ic/qwz.c

22376

ti.enable_mesh = true;

sys/dev/ic/qwz.c

23230

arg->is_pmf_enabled = true;

sys/dev/pci/drm/amd/amdgpu/aldebaran.c

329

adev->ip_blocks[i].status.late_initialized = true;

sys/dev/pci/drm/amd/amdgpu/aldebaran.c

40

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c

224

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c

259

found = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c

393

bool ret = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c

596

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c

890

ret = amdgpu_ras_set_aca_debug_mode(adev, val ? true : false);

sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c

143

amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c

239

amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c

453

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c

472

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c

522

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c

540

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c

578

amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c

584

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

1346

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

1381

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

1416

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

1460

atif->functions.system_params = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

1568

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

324

n->enabled = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

331

n->enabled = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

392

atif->backlight_caps.caps_valid = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

653

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

353

r = amdgpu_bo_reserve(bo, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

403

(void)amdgpu_bo_reserve(*bo, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

141

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

237

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

258

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

323

amdgpu_amdkfd_suspend(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

325

if (suspend_resume_compute_scheduler(adev, true))

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

336

amdgpu_amdkfd_resume(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

354

kgd_gfx_v9_set_wave_launch_stall(adev, vmid, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

356

set_barrier_auto_waitcnt(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

380

kgd_gfx_v9_set_wave_launch_stall(adev, vmid, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_fence.c

127

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_fence.c

131

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_fence.c

134

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_fence.c

178

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

178

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

199

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

77

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

391

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

489

retval = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

508

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

561

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

590

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

610

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

642

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

760

kgd_gfx_v10_set_wave_launch_stall(adev, vmid, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

796

kgd_gfx_v10_set_wave_launch_stall(adev, vmid, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

839

kgd_gfx_v10_set_wave_launch_stall(adev, vmid, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

868

kgd_gfx_v10_set_wave_launch_stall(adev, vmid, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

377

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

475

retval = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

495

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

533

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

566

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

362

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

464

retval = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

483

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

518

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

551

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

254

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

336

retval = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

354

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

396

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

425

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

444

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

475

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

277

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

368

retval = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

386

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

431

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

460

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

479

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

510

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1162

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

402

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

500

retval = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

519

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

560

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

592

while (true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

707

kgd_gfx_v9_set_wave_launch_stall(adev, vmid, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

730

kgd_gfx_v9_set_wave_launch_stall(adev, vmid, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

773

kgd_gfx_v9_set_wave_launch_stall(adev, vmid, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

802

kgd_gfx_v9_set_wave_launch_stall(adev, vmid, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

1059

struct ttm_operation_ctx ctx = { true, false };

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

1101

ret = amdgpu_bo_reserve(bo, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

1430

ret = amdgpu_bo_reserve(vm->root.bo, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

1505

struct ttm_operation_ctx ctx = { true, false };

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

1619

WRITE_ONCE(pinfo->block_mmu_notifications, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

2060

is_invalid_userptr = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

2086

entry->is_mapped = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

2114

ret = amdgpu_bo_reserve(mem->bo, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

2218

ret = amdgpu_bo_reserve(bo, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

2280

ret = amdgpu_bo_reserve(bo, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

2331

(void)amdgpu_bo_reserve(bo, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

2399

(*mem)->is_imported = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

2565

if (amdgpu_bo_reserve(bo, true))

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

2862

struct dma_fence *old_ef = rcu_replace_pointer(*ef, new_ef, true

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

3135

ret = amdgpu_amdkfd_bo_validate(gws_bo, AMDGPU_GEM_DOMAIN_GWS, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

3224

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

452

ret = amdgpu_amdkfd_bo_validate(bo, domain, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

566

struct ttm_operation_ctx ctx = {.interruptible = true};

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

613

struct ttm_operation_ctx ctx = {.interruptible = true};

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

650

struct ttm_operation_ctx ctx = {.interruptible = true};

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

773

struct ttm_operation_ctx ctx = {.interruptible = true};

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

84

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

956

WARN_ONCE(true, "Handling invalid ATTACH request");

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

995

(void)amdgpu_bo_reserve(bo[i], true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1046

ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1048

ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1068

ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1070

ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1364

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1553

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1629

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

207

gpio.valid = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

306

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

468

router.ddc_valid = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

476

router.cd_valid = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

566

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

63

i2c.hw_capable = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

68

i2c.mm_i2c = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

75

i2c.valid = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

941

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

963

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

990

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

571

(umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

576

(umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

583

(umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE)) ? true : false;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

585

(umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

597

(umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE) ? true : false;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

599

(umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

627

return (fw_cap & ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

643

return (fw_cap & ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE) ? true : false;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

693

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

85

return (fw_cap & ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION) ? true : false;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

903

return (fw_cap & ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING) ? true : false;

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

142

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

181

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

211

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

249

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

290

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

321

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

351

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

431

found = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

443

found = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

473

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

538

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

578

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

647

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

709

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

87

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cgs.c

259

info->is_kicker = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cgs.c

267

info->is_kicker = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cgs.c

279

info->is_kicker = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cgs.c

287

info->is_kicker = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cgs.c

298

info->is_kicker = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cgs.c

301

info->is_kicker = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cgs.c

313

info->is_kicker = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cgs.c

316

info->is_kicker = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cgs.c

327

info->is_kicker = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1031

force = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1051

amdgpu_connector->detected_hpd_without_ddc = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1066

broken_edid = true; /* defer use_digital to later */

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1090

if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1127

amdgpu_connector->detected_by_load = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1132

amdgpu_connector->use_digital = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1165

if (amdgpu_connector->use_digital == true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1192

amdgpu_connector->use_digital = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1382

found = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1395

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1459

if (amdgpu_display_ddc_probe(amdgpu_connector, true))

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1635

amdgpu_connector->shared_ddc = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1636

shared_ddc = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1654

is_dp_bridge = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1689

has_aux = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1705

connector->interlace_allowed = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1706

connector->doublescan_allowed = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1707

amdgpu_connector->dac_load_detect = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1752

connector->interlace_allowed = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1754

connector->doublescan_allowed = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1758

amdgpu_connector->dac_load_detect = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1795

amdgpu_connector->dac_load_detect = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1804

connector->interlace_allowed = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1805

connector->doublescan_allowed = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1820

amdgpu_connector->dac_load_detect = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1829

connector->interlace_allowed = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1830

connector->doublescan_allowed = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1877

amdgpu_connector->dac_load_detect = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1882

connector->interlace_allowed = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1884

connector->doublescan_allowed = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1931

connector->interlace_allowed = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1933

connector->doublescan_allowed = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1945

has_aux = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1981

connector->interlace_allowed = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1993

has_aux = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

227

connected = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

383

mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

469

new_coherent_mode = val ? true : false;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

555

amdgpu_connector->dac_load_detect = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

915

amdgpu_connector->detected_by_load = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

959

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

234

amdgpu_cper_entry_fill_section_desc(adev, section_desc, true, false,

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

451

return strcmp(chdr->signature, "CPER") ? false : true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

571

ring->no_scheduler = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

594

adev->cper.enabled = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

1364

p->ctx->preamble_presented = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

1514

r = dma_fence_wait_timeout(fence, true, timeout);

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

1651

r = dma_fence_wait_timeout(fence, true, timeout);

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

1711

r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

295

p->jobs[i]->enforce_isolation = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

296

p->jobs[i]->run_cleaner_shader = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

299

p->jobs[i]->enforce_isolation = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

303

p->jobs[i]->enforce_isolation = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

805

.interruptible = true,

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

859

struct ttm_operation_ctx ctx = { true, false };

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

900

userpage_invalidated = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c

56

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c

721

r = amdgpu_ctx_stable_pstate(adev, fpriv, id, true, &stable_pstate);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c

875

r = dma_fence_wait(other, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

102

use_bank = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

110

use_ring = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1308

amdgpu_set_gfx_off_residency(adev, value ? true : false);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1407

amdgpu_gfx_off_ctrl(adev, value ? true : false);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1793

r = amdgpu_bo_reserve(vm->root.bo, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1880

bool preempted = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

195

return amdgpu_debugfs_process_reg_op(true, f, buf, size, pos);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

2152

r = amdgpu_bo_reserve(root_bo, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1461

ret = amdgpu_atomfirmware_asic_init(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1812

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1817

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1827

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1840

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1856

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1890

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1898

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1908

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1928

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1942

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1973

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2265

amdgpu_device_resume(dev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2272

amdgpu_device_suspend(dev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2606

adev->enable_virtual_display = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2640

adev->enable_virtual_display = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2813

r = amdgpu_virt_request_full_gpu(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2911

total = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2930

adev->ip_blocks[i].status.valid = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2933

adev->ip_blocks[i].status.valid = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3016

adev->ip_blocks[i].status.hw = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3042

adev->ip_blocks[i].status.hw = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3067

if (adev->ip_blocks[i].status.hw == true)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3084

adev->ip_blocks[i].status.hw = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3197

adev->ip_blocks[i].status.sw = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3211

adev->ip_blocks[i].status.hw = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3237

adev->ip_blocks[i].status.hw = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3341

amdgpu_ttm_set_buffer_funcs_status(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3387

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3401

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

347

ip_block->status.hw = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3566

adev->ip_blocks[i].status.late_initialized = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3576

amdgpu_ras_set_error_query_ready(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3591

amdgpu_dpm_handle_passthrough_sbr(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3695

amdgpu_amdkfd_suspend(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3811

if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true, 0))

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3812

adev->gfx.gfx_off_state = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4016

block->status.hw = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4058

block->status.hw = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4189

amdgpu_ttm_set_buffer_funcs_status(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

436

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4426

adev->ram_is_direct_mapped = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4444

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4453

adev->gfx.mcbp = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4458

adev->gfx.mcbp = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

455

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4734

adev->have_atomics_support = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4750

adev->have_atomics_support = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4899

adev->accel_working = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4935

amdgpu_virt_release_full_gpu(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4958

adev->ucode_sysfs_en = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5015

amdgpu_virt_release_full_gpu(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5092

adev->shutdown = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5163

dma_fence_put(rcu_dereference_protected(adev->gang_submit, true));

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5283

adev->in_s4 = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5375

adev->in_suspend = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5459

r = amdgpu_virt_request_full_gpu(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5509

amdgpu_virt_release_full_gpu(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5573

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5576

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5587

asic_hang = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5636

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5648

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5737

r = amdgpu_virt_request_full_gpu(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5786

amdgpu_virt_release_full_gpu(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5822

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5843

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5846

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5871

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5884

amdgpu_atombios_scratch_regs_engine_hung(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

5980

amdgpu_fence_driver_isr_toggle(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

6023

need_full_reset = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

6115

amdgpu_ttm_set_buffer_funcs_status(tmp_adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

6409

tmp_adev->shutdown = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

6411

tmp_adev->pcie_reset_ctx.in_link_reset = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

6469

tmp_adev->pcie_reset_ctx.audio_suspended = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

6534

amdgpu_ras_set_fed(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

6540

amdgpu_virt_release_full_gpu(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

6640

amdgpu_ras_set_error_query_ready(tmp_adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

6739

job_signaled = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

694

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7127

adev->nbio.funcs->enable_doorbell_interrupt(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7181

amdgpu_reset_set_dpc_status(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7306

tmp_adev->pcie_reset_ctx.in_link_reset = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7474

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7499

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7572

adev->no_hw_access = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7785

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7791

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

932

GC_HWIP, true,

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2494

adev->enable_mes = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2495

adev->enable_mes_kiq = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2500

adev->enable_mes = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2501

adev->enable_mes_kiq = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2503

adev->enable_uni_mes = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

2546

adev->enable_umsch_mm = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

277

bool sz_valid = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

113

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1146

block_size_log2 = get_dcc_block_size(modifier, true, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1150

block_size_log2 = get_dcc_block_size(modifier, true, pipe_aligned);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1434

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1511

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1558

bool in_vbl = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1697

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1727

r = amdgpu_bo_reserve(aobj, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1739

r = amdgpu_bo_reserve(robj, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1764

r = amdgpu_bo_reserve(aobj, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

179

r = amdgpu_bo_reserve(work->old_abo, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

333

active = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

342

adev->have_disp_power_ref = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

533

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

590

.has_alpha = true, },

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

593

.has_alpha = true, },

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

596

.has_alpha = true, },

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

603

.has_alpha = true, },

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

606

.has_alpha = true, },

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

618

.has_alpha = true, },

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

621

.has_alpha = true, },

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

624

.has_alpha = true, },

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

631

.has_alpha = true, },

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

634

.has_alpha = true, },

sys/dev/pci/drm/amd/amdgpu/amdgpu_dma_buf.c

283

struct ttm_operation_ctx ctx = { true, false };

sys/dev/pci/drm/amd/amdgpu/amdgpu_dma_buf.c

372

.interruptible = true,

sys/dev/pci/drm/amd/amdgpu/amdgpu_dma_buf.c

373

.no_wait_gpu = true,

sys/dev/pci/drm/amd/amdgpu/amdgpu_dma_buf.c

375

.gfp_retry_mayfail = true,

sys/dev/pci/drm/amd/amdgpu/amdgpu_dma_buf.c

524

.allow_peer2peer = true,

sys/dev/pci/drm/amd/amdgpu/amdgpu_dma_buf.c

612

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

2262

adev->debug_vm = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

2267

adev->debug_largebar = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

2272

adev->debug_disable_soft_recovery = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

2277

adev->debug_use_vram_fw_buf = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

2282

adev->debug_enable_ras_aca = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

2287

adev->debug_exp_resets = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

2292

adev->debug_disable_gpu_ring_reset = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

2300

adev->debug_vm_userptr = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

2305

adev->debug_disable_ce_logs = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

2310

adev->debug_enable_ce_cs = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

2354

supports_atomic = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

2620

adev->in_s0ix = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

2622

adev->in_s3 = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

2641

return amdgpu_device_suspend(drm_dev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

2671

adev->no_hw_access = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

2673

r = amdgpu_device_resume(drm_dev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

2687

r = amdgpu_device_suspend(drm_dev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

2706

return amdgpu_device_resume(drm_dev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

2718

return amdgpu_device_suspend(drm_dev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

2727

return amdgpu_device_resume(drm_dev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

2852

adev->in_runpm = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

2913

adev->no_hw_access = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

2979

fpriv->evf_mgr.fd_closing = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

3500

supports_atomic = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

3532

adev->irq.msi_enabled = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

3554

adev->shutdown = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

3783

dev->registered = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

3994

adev->in_s4 = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

876

bool pcie_p2p = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_eeprom.c

231

true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_encoders.c

227

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_encoders.c

232

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_encoders.c

249

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_encoders.c

254

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_eviction_fence.c

136

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_eviction_fence.c

142

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

283

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

461

ring->fence_drv.initialized = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

549

is_gfx_power_domain = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

555

is_gfx_power_domain = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

893

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

910

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_fru_eeprom.c

102

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_fru_eeprom.c

107

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_fru_eeprom.c

111

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_fru_eeprom.c

73

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_fru_eeprom.c

91

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gart.c

191

ret = amdgpu_bo_reserve(bo, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c

1182

amdgpu_vm_bo_invalidate(robj, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c

437

amdgpu_bo_fence(bo, fence, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c

607

struct ttm_operation_ctx ctx = { true, false };

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c

657

r = amdgpu_bo_reserve(bo, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c

764

true, timeout);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

1490

job->enforce_isolation = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

1492

job->run_cleaner_shader = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

160

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

186

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

200

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2014

adev->gfx.userq_sch_inactive[idx] = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2110

wait = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2166

sched_work = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2203

sched_work = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2208

amdgpu_gfx_kfd_sch_ctrl(adev, idx, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2271

r = amdgpu_dpm_switch_power_profile(adev, profile, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2276

adev->gfx.workload_profile_active = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2382

ring->sched.ready = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2452

ring->sched.ready = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

316

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

329

ring->no_scheduler = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

370

r = amdgpu_bo_reserve(kiq->eop_obj, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

804

AMD_IP_BLOCK_TYPE_GFX, true, 0))

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

805

adev->gfx.gfx_off_state = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

849

bool no_delay = adev->in_s0ix ? true : false;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

868

amdgpu_gfx_do_off_ctrl(adev, enable, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

1001

adev->mman.keep_stolen_vga_memory = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

1014

adev->mman.keep_stolen_vga_memory = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

1024

adev->mman.keep_stolen_vga_memory = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

1564

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

1696

valid = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

428

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

434

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

455

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

706

job->vm_needs_flush = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

886

adev->gmc.tmz_enabled = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

916

adev->gmc.tmz_enabled = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gtt_mgr.c

281

man->use_tt = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gtt_mgr.c

292

ttm_resource_manager_set_used(man, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_hmm.c

114

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_hmm.c

86

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

203

need_pipe_sync = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

216

ring->funcs->emit_wave_limit(ring, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

255

amdgpu_ring_emit_frame_cntl(ring, true, secure);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

265

amdgpu_ring_emit_frame_cntl(ring, true, secure);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

352

adev->ib_pool_ready = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c

251

seqno, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c

300

needs_flush = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c

331

job->spm_update_needed = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c

373

needs_flush = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c

376

needs_flush = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c

443

job->vm_needs_flush = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c

514

id_mgr->reserved_vmid = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c

242

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c

246

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c

302

adev->irq.msi_enabled = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c

323

adev->irq.installed = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c

497

handled = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_isp.c

131

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_job.c

174

adev->virt.tdr_debug = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_job.c

48

amdgpu_coredump(adev, true, false, job);

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

376

ring->sched.ready = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

48

adev->jpeg.indirect_sram = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

553

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1286

r = amdgpu_asic_query_video_codecs(adev, true, &codecs);

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1527

if (!WARN_ON(amdgpu_bo_reserve(pd, true))) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

386

adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

891

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

896

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

925

dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

926

dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c

337

bool ret = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c

365

ret = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c

521

ret = amdgpu_ras_set_mca_debug_mode(adev, val ? true : false);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

374

queue_input.is_kq = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

376

queue_input.legacy_gfx = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

588

op_input.set_shader_debugger.flags.process_ctx_flush = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

627

need_retry = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

735

r |= amdgpu_mes_set_enforce_isolation(adev, i, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.c

64

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

1344

r = amdgpu_fill_buffer(abo, 0, &bo->base._resv, &fence, true,

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

278

free = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

519

if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

550

if (amdgpu_bo_reserve(bo, true) == 0) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

572

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

582

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

618

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

641

.gfp_retry_mayfail = true,

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

97

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_preempt_mgr.c

105

man->use_tt = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_preempt_mgr.c

117

ttm_resource_manager_set_used(man, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

116

psp->pmfw_centralized_cstate_management = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1246

psp->asd_context.initialized = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1460

psp->xgmi_context.context.initialized = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

170

psp->autoload_supported = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

171

psp->boot_time_tmr = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1993

psp->ras_context.context.initialized = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2106

psp->hdcp_context.context.initialized = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2180

psp->dtm_context.context.initialized = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2251

psp->rap_context.context.initialized = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2365

psp->securedisplay_context.context.initialized = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3004

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3007

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3013

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3017

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3023

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3149

ret = psp_xgmi_initialize(psp, false, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3356

ret = psp_xgmi_initialize(psp, false, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3806

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

416

ret = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

427

ret = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

463

adev->scpm_enabled = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

484

mem_training_ctx->enable_mem_training = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

491

mem_training_ctx->enable_mem_training = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

689

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

904

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

60

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rap.c

105

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

1251

blk_name, true, false);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

1274

blk_name, false, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

2115

ret = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

2378

amdgpu_ras_set_fed(obj->adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

2719

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

2754

amdgpu_ras_set_fed_all(adev, hive, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3228

ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3397

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3410

return ret ? true : false;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3660

if (con->update_channel_flag == true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3815

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3829

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3923

con->poison_supported = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3935

con->poison_supported = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

4709

amdgpu_ras_set_fed(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

4837

notifier_registered = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

4968

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

4992

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5053

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5079

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5411

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5539

ret = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

1042

con->update_channel_flag = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

1536

ras->is_rma = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

162

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

166

return (adev->gmc.is_app_apu) ? false : true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

193

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

207

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

210

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

217

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

224

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

230

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

582

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

655

con->update_channel_flag = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

779

ras->is_rma = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_res_cursor.h

191

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

718

prop->kernel_queue = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

788

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

832

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

836

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

840

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

845

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

849

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c

403

mux->pending_trailing_fence_signaled = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c

593

mux->s_resubmit = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c

599

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

51

adev->gfx.rlc.in_safe_mode[xcc_id] = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

532

adev->gfx.rlc.is_rlc_v2_1 = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

183

sdma_inst->burst_nop = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

382

ring->sched.ready = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

388

page->sched.ready = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c

141

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c

146

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c

195

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c

213

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c

233

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1001

gtt->bound = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1357

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1370

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1461

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1517

amdgpu_device_mm_access(adev, aligned_pos, &value, 4, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1803

mem_train_support = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1993

adev->mman.initialized = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2121

adev->apu_prefer_gtt = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2337

(*job)->vm_needs_flush = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2489

&next, true, true,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2540

&next, true, delayed, k_job_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2661

amdgpu_device_mm_access(adev, *pos, &value, 4, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

356

&next, false, true, copy_flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

423

r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

425

r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

454

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

466

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

485

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

629

mem->bus.is_iomem = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

634

mem->bus.is_iomem = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

640

mem->bus.is_iomem = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

931

gtt->bound = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

1409

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

529

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.c

175

if (con->update_channel_flag == true) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.c

110

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.c

111

ring->no_scheduler = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

1088

adev->userq_halt_for_enforce_isolation = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

190

ret = dma_fence_wait_timeout(f, true, msecs_to_jiffies(100));

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

267

r = amdgpu_bo_reserve(userq_obj->obj, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

324

r = amdgpu_bo_reserve(db_obj->obj, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

396

r = amdgpu_bo_reserve(queue->db_obj.obj, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

447

r = amdgpu_bo_reserve(bo, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

588

skip_map_queue = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

702

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

926

ret = dma_fence_wait_timeout(f, true, msecs_to_jiffies(100));

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

344

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

414

r = amdgpu_bo_reserve(bo, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

971

r = dma_fence_wait(fences[i], true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

1182

amdgpu_bo_reserve(bo, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

1225

return amdgpu_uvd_send_msg(ring, bo, true, fence);

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

1303

amdgpu_dpm_enable_uvd(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

1344

r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

144

struct ttm_operation_ctx ctx = { true, false };

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

344

adev->uvd.address_64_bit = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

975

ctx->has_msg_cmd = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

1159

r = amdgpu_vce_get_destroy_msg(ring, 1, true, &fence);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

375

amdgpu_dpm_enable_vce(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1016

ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1414

ring->sched.ready = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

144

adev->vcn.inst[i].indirect_sram = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

303

ret = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

305

ret = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

307

ret = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

420

true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

425

adev->vcn.workload_profile_active = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

431

bool pg = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

949

ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1031

ret = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1037

ret = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1044

ret = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1160

amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1191

bool xnack_mode = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1247

con->poison_supported = true; /* Poison is handled by host */

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1249

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1476

amdgpu_virt_req_ras_err_count_internal(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1494

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1531

*hit = tmp->hit ? true : false;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

300

virt->ras_init_done = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

409

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

413

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

522

adev->virt.is_mm_bw_enabled = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

644

amdgpu_ras_set_fed(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

65

adev->enable_virtual_display = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

789

is_sriov = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

859

return amdgpu_sriov_is_debug(adev) ? true : false;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

864

return amdgpu_sriov_is_normal(adev) ? true : false;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

91

adev->no_hw_access = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

931

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

940

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

965

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

982

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

1216

amdgpu_bo_fence(vm->root.bo, vm->last_unlocked, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

1233

bool contiguous = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

1404

flush_tlb = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

1631

r = amdgpu_vm_update_range(adev, vm, false, false, true, false,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

1699

unlock = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

1706

clear = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

1767

all_hub = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

1815

bo_va->is_xgmi = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

2018

bool valid = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

214

vm_bo->moved = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

2296

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

2312

bo_base->vm->evicting = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

2314

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

2339

bo_base->moved = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

2707

r = amdgpu_bo_reserve(root_bo, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

2782

r = amdgpu_bo_reserve(vm->root.bo, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

2798

AMDGPU_FENCE_OWNER_UNDEFINED, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

281

vm_bo->moved = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

2813

vm->is_compute_context = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

2827

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

2850

amdgpu_bo_reserve(root, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

3056

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

3059

r = amdgpu_bo_reserve(root, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

3098

r = amdgpu_vm_update_range(adev, vm, true, false, false, false,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

3103

r = amdgpu_vm_update_pdes(adev, vm, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

339

vm_bo->moved = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

344

vm_bo->moved = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

768

has_compute_vm_bug = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

771

has_compute_vm_bug = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

804

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

807

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

810

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

847

gds_switch_needed = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

848

vm_flush_needed = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

849

pasid_mapping_needed = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

850

spm_update_needed = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

856

pasid_mapping_needed = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h

681

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_cpu.c

55

return amdgpu_sync_wait(sync, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_cpu.c

81

true, MAX_SCHEDULE_TIMEOUT);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c

193

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c

228

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c

248

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c

364

struct ttm_operation_ctx ctx = { true, false };

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c

935

params->needs_flush = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c

62

r = amdgpu_gmc_flush_gpu_tlb_pasid(f->adev, f->pasid, 2, true, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c

92

amdgpu_gmc_flush_gpu_tlb_pasid(adev, vm->pasid, 2, true, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

279

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

311

vpe->collaborate_mode = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

670

amdgpu_ring_set_preempt_cond_exec(ring, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

696

amdgpu_dpm_enable_vpe(adev, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

891

vpe->context_started = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

966

.support_64bit_ptrs = true,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

79

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

846

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

882

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

955

ttm_resource_manager_set_used(man, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

118

xcp->ip[ip->ip_id].valid = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

120

xcp->valid = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

244

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

248

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

252

return true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1020

ret = psp_xgmi_initialize(&adev->psp, false, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1117

ret = amdgpu_xgmi_initialize_hive_get_data_partition(hive, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1124

&tmp_adev->psp.xgmi_context.top_info, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1442

mask_data, &ue_cnt, &ce_cnt, true, false);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1458

mask_data, &ue_cnt, &ce_cnt, true, false);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1476

mask_data, &ue_cnt, &ce_cnt, true, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1485

mask_data, &ue_cnt, &ce_cnt, false, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1503

mask_data, &ue_cnt, &ce_cnt, true, true);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1728

reset_scheduled = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

950

return true;

sys/dev/pci/drm/amd/amdgpu/atom.c

1636

return true;

sys/dev/pci/drm/amd/amdgpu/atom.c

1653

return true;

sys/dev/pci/drm/amd/amdgpu/atom.c

644

ctx->abort = true;

sys/dev/pci/drm/amd/amdgpu/atom.c

769

ctx->abort = true;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

567

return true;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

571

return true;

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

195

amdgpu_connector->ddc_bus->has_aux = true;

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

466

return true;

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

625

clock_recovery = true;

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

690

channel_eq = true;

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

746

dp_info.tp3_supported = true;

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

77

amdgpu_atombios_copy_swap(base, send, send_bytes, true);

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1175

return true;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1181

return true;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1328

amdgpu_dig_connector->edp_on = true;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1711

return true;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

2033

lvds->linkb = true;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

2095

bad_record = true;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

2116

dig->coherent_mode = true;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

2120

dig->linkb = true;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

272

return true;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

309

return true;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

799

is_dp = true;

sys/dev/pci/drm/amd/amdgpu/cik.c

1040

return true;

sys/dev/pci/drm/amd/amdgpu/cik.c

1114

{mmCC_RB_BACKEND_DISABLE, true},

sys/dev/pci/drm/amd/amdgpu/cik.c

1115

{mmGC_USER_RB_BACKEND_DISABLE, true},

sys/dev/pci/drm/amd/amdgpu/cik.c

1117

{mmPA_SC_RASTER_CONFIG, true},

sys/dev/pci/drm/amd/amdgpu/cik.c

1118

{mmPA_SC_RASTER_CONFIG_1, true},

sys/dev/pci/drm/amd/amdgpu/cik.c

1345

amdgpu_atombios_scratch_regs_engine_hung(adev, true);

sys/dev/pci/drm/amd/amdgpu/cik.c

1362

adev->has_hw_reset = true;

sys/dev/pci/drm/amd/amdgpu/cik.c

1779

clk_req_support = true;

sys/dev/pci/drm/amd/amdgpu/cik.c

1882

return true;

sys/dev/pci/drm/amd/amdgpu/cik.c

1943

return true;

sys/dev/pci/drm/amd/amdgpu/cik.c

2153

return true;

sys/dev/pci/drm/amd/amdgpu/cik_ih.c

356

return true;

sys/dev/pci/drm/amd/amdgpu/cik_ih.c

69

adev->irq.ih.enabled = true;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

1031

return true;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

1191

gate = true;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

494

cik_sdma_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

547

adev->sdma.instance[i].burst_nop = true;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

578

cik_ctx_switch_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

352

return true;

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

69

adev->irq.ih.enabled = true;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1010

return true;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1061

wm_high.interlaced = true;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1086

amdgpu_dpm_get_mclk(adev, true) * 10;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1088

amdgpu_dpm_get_sclk(adev, true) * 10;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1100

wm_low.interlaced = true;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1191

adev->mode_info.audio.pin[i].connected = true;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1441

adev->mode_info.audio.enabled = true;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1739

dce_v10_0_audio_enable(adev, dig->afmt->pin, true);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1950

bypass_lut = true;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1961

bypass_lut = true;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2054

dce_v10_0_grph_enable(crtc, true);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2073

r = amdgpu_bo_reserve(abo, true);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2353

dce_v10_0_lock_cursor(crtc, true);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2409

dce_v10_0_lock_cursor(crtc, true);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2434

ret = amdgpu_bo_reserve(aobj, true);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2451

dce_v10_0_lock_cursor(crtc, true);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2501

amdgpu_crtc->enabled = true;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2503

dce_v10_0_vga_enable(crtc, true);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2519

dce_v10_0_vga_enable(crtc, true);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2559

r = amdgpu_bo_reserve(abo, true);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2656

return true;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2813

adev_to_drm(adev)->mode_config.async_page_flip = true;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2821

adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2853

adev_to_drm(adev)->vblank_disable_immediate = true;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2864

adev->mode_info.mode_config_initialized = true;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

290

connected = true;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2969

return true;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3370

dce_v10_0_afmt_enable(encoder, true);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3393

amdgpu_atombios_scratch_regs_lock(adev, true);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3601

amdgpu_encoder->is_ext_encoder = true;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

440

return true;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

955

return true;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

975

return true;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1163

adev->mode_info.audio.pin[i].connected = true;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1420

adev->mode_info.audio.enabled = true;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1759

dce_v6_0_audio_set_mute(encoder, true);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1781

dce_v6_0_audio_enable(adev, dig->afmt->pin, true);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1979

bypass_lut = true;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1989

bypass_lut = true;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2069

dce_v6_0_grph_enable(crtc, true);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2088

r = amdgpu_bo_reserve(abo, true);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2326

dce_v6_0_lock_cursor(crtc, true);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2382

dce_v6_0_lock_cursor(crtc, true);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2407

ret = amdgpu_bo_reserve(aobj, true);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2424

dce_v6_0_lock_cursor(crtc, true);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2473

amdgpu_crtc->enabled = true;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2527

r = amdgpu_bo_reserve(abo, true);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

254

connected = true;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2623

return true;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2762

adev->mode_info.mode_config_initialized = true;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2765

adev_to_drm(adev)->mode_config.async_page_flip = true;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2770

adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2802

adev_to_drm(adev)->vblank_disable_immediate = true;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2914

return true;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3261

dce_v6_0_afmt_enable(encoder, true);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3284

amdgpu_atombios_scratch_regs_lock(adev, true);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3364

return true;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3497

amdgpu_encoder->is_ext_encoder = true;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

407

return true;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

808

return true;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

828

return true;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

863

return true;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

923

wm_high.interlaced = true;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

936

amdgpu_dpm_get_mclk(adev, true) * 10;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

938

amdgpu_dpm_get_sclk(adev, true) * 10;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

950

wm_low.interlaced = true;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1014

wm_high.interlaced = true;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1039

amdgpu_dpm_get_mclk(adev, true) * 10;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1041

amdgpu_dpm_get_sclk(adev, true) * 10;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1053

wm_low.interlaced = true;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1146

adev->mode_info.audio.pin[i].connected = true;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1413

adev->mode_info.audio.enabled = true;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1686

dce_v8_0_audio_enable(adev, dig->afmt->pin, true);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1891

bypass_lut = true;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1901

bypass_lut = true;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1981

dce_v8_0_grph_enable(crtc, true);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2000

r = amdgpu_bo_reserve(abo, true);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2272

dce_v8_0_lock_cursor(crtc, true);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2328

dce_v8_0_lock_cursor(crtc, true);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2353

ret = amdgpu_bo_reserve(aobj, true);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2370

dce_v8_0_lock_cursor(crtc, true);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

238

connected = true;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2420

amdgpu_crtc->enabled = true;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2422

dce_v8_0_vga_enable(crtc, true);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2438

dce_v8_0_vga_enable(crtc, true);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2478

r = amdgpu_bo_reserve(abo, true);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2582

return true;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2727

adev_to_drm(adev)->mode_config.async_page_flip = true;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2739

adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2771

adev_to_drm(adev)->vblank_disable_immediate = true;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2783

adev->mode_info.mode_config_initialized = true;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2886

return true;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3278

dce_v8_0_afmt_enable(encoder, true);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3301

amdgpu_atombios_scratch_regs_lock(adev, true);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3509

amdgpu_encoder->is_ext_encoder = true;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

391

return true;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

908

return true;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

928

return true;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

963

return true;

sys/dev/pci/drm/amd/amdgpu/df_v1_7.c

85

adev->df.funcs->enable_broadcast_mode(adev, true);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

313

adev->df.funcs->enable_broadcast_mode(adev, true);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

535

true);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

548

counter_idx, true);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

662

return true;

sys/dev/pci/drm/amd/amdgpu/df_v4_3.c

49

return true;

sys/dev/pci/drm/amd/amdgpu/df_v4_6_2.c

29

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4156

adev->gfx.cp_fw_write_wait = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4166

adev->gfx.cp_fw_write_wait = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4183

ret = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4380

adev->gfx.rlc.rlcg_reg_access_supported = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4663

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4694

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4807

adev->gfx.enable_cleaner_shader = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4826

adev->gfx.enable_cleaner_shader = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4840

adev->gfx.enable_cleaner_shader = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4854

adev->gfx.enable_cleaner_shader = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6376

gfx_v10_0_cp_gfx_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7209

gfx_v10_0_cp_compute_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7300

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7308

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7316

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7588

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7860

return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8327

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8346

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8460

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8664

(!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8821

(!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8908

amdgpu_ring_set_preempt_cond_exec(ring, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9557

r = gfx_v10_0_kgq_init_queue(ring, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9628

r = gfx_v10_0_kcq_init_queue(ring, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9730

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9760

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9786

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9834

.support_64bit_ptrs = true,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9835

.secure_submission_supported = true,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9892

.support_64bit_ptrs = true,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9932

.support_64bit_ptrs = true,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1138

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1140

ring->no_scheduler = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1141

ring->no_user_submission = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1174

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1648

adev->gfx.enable_cleaner_shader = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1663

adev->gfx.enable_cleaner_shader = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1677

adev->gfx.enable_cleaner_shader = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1691

adev->gfx.enable_cleaner_shader = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1705

adev->gfx.enable_cleaner_shader = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3615

gfx_v11_0_cp_gfx_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4555

gfx_v11_0_cp_compute_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4591

gfx_v11_0_cp_compute_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4592

gfx_v11_0_cp_gfx_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4783

adev->gfx.is_poweron = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4943

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5037

r = gfx_v11_0_request_gfx_index_mutex(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5138

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5145

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5174

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5227

adev->gfx.disable_uq = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5234

adev->gfx.disable_kq = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5283

r = gfx_v11_0_set_userq_eop_interrupts(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5296

return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5591

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5680

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6203

amdgpu_ring_set_preempt_cond_exec(ring, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6841

r = gfx_v11_0_kgq_init_queue(ring, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6996

r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7004

r = gfx_v11_0_kcq_init_queue(ring, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

704

adev->gfx.cp_gfx_shadow = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7099

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7131

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7157

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7207

.support_64bit_ptrs = true,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7208

.secure_submission_supported = true,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7262

.support_64bit_ptrs = true,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7303

.support_64bit_ptrs = true,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

899

adev->gfx.rlc.rlcg_reg_access_supported = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1008

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1443

adev->gfx.enable_cleaner_shader = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2668

gfx_v12_0_cp_gfx_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3425

adev->gfx.kiq[0].ring.sched.ready = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3434

gfx_v12_0_cp_compute_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3467

gfx_v12_0_cp_compute_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3468

gfx_v12_0_cp_gfx_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3650

adev->gfx.is_poweron = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3801

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3844

adev->gfx.disable_uq = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3851

adev->gfx.disable_kq = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3896

r = gfx_v12_0_set_userq_eop_interrupts(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3909

return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4632

amdgpu_ring_set_preempt_cond_exec(ring, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5178

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5203

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5229

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5314

r = gfx_v12_0_kgq_init_queue(ring, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5422

r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5430

r = gfx_v12_0_kcq_init_queue(ring, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5481

.support_64bit_ptrs = true,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5482

.secure_submission_supported = true,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5529

.support_64bit_ptrs = true,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5567

.support_64bit_ptrs = true,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

742

adev->gfx.rlc.rlcg_reg_access_supported = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

975

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2030

gfx_v6_0_cp_gfx_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2281

gfx_v6_0_enable_gui_idle_interrupt(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2474

gfx_v6_0_enable_gui_idle_interrupt(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2494

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2554

gfx_v6_0_enable_gui_idle_interrupt(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2885

gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2886

gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2889

gfx_v6_0_enable_cp_pg(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2890

gfx_v6_0_enable_gds_pg(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2897

gfx_v6_0_update_gfx_pg(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3176

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3386

gate = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3390

gfx_v6_0_enable_mgcg(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3391

gfx_v6_0_enable_cgcg(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3396

gfx_v6_0_enable_gui_idle_interrupt(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

3408

gate = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2472

gfx_v7_0_cp_gfx_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3032

gfx_v7_0_cp_compute_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3093

gfx_v7_0_enable_gui_idle_interrupt(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3330

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3390

gfx_v7_0_enable_gui_idle_interrupt(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3487

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3497

gfx_v7_0_enable_gui_idle_interrupt(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3529

gfx_v7_0_enable_gui_idle_interrupt(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3624

gfx_v7_0_enable_mgcg(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3625

gfx_v7_0_enable_cgcg(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3630

gfx_v7_0_enable_gui_idle_interrupt(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3913

gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3914

gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3917

gfx_v7_0_enable_cp_pg(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3918

gfx_v7_0_enable_gds_pg(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3921

gfx_v7_0_update_gfx_pg(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4290

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4487

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4824

gate = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4829

gfx_v7_0_enable_mgcg(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4830

gfx_v7_0_enable_cgcg(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4835

gfx_v7_0_enable_gui_idle_interrupt(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4847

gate = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1050

adev->virt.chained_ib_support = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1862

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1973

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3879

bool new_entry = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3891

new_entry = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4064

gfx_v8_0_enable_gui_idle_interrupt(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4142

gfx_v8_0_cp_gfx_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4673

gfx_v8_0_cp_compute_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4733

gfx_v8_0_enable_gui_idle_interrupt(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4806

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4816

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4944

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5319

cz_enable_gfx_cg_power_gating(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5321

cz_enable_gfx_pipeline_power_gating(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5347

cz_enable_sck_slow_down_on_power_up(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5348

cz_enable_sck_slow_down_on_power_down(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5354

cz_enable_cp_power_gating(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5361

gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5366

gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5374

gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5379

gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5384

polaris11_enable_gfx_quick_mg_power_gating(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5497

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5563

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5728

gfx_v8_0_enable_gui_idle_interrupt(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5764

gfx_v8_0_enable_gui_idle_interrupt(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6711

gfx_v8_0_parse_sq_irq(adev, sq_work->ih_data, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1312

adev->gfx.me_fw_write_wait = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1316

adev->gfx.mec_fw_write_wait = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1323

adev->gfx.me_fw_write_wait = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1327

adev->gfx.mec_fw_write_wait = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1334

adev->gfx.me_fw_write_wait = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1338

adev->gfx.mec_fw_write_wait = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1346

adev->gfx.me_fw_write_wait = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1350

adev->gfx.mec_fw_write_wait = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1353

adev->gfx.me_fw_write_wait = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1354

adev->gfx.mec_fw_write_wait = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1393

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1403

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1413

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1545

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1832

adev->gfx.rlc.rlcg_reg_access_supported = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2167

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2248

adev->gfx.enable_cleaner_shader = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2260

adev->gfx.enable_cleaner_shader = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2338

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2357

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2359

ring->is_sw_ring = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2989

pwr_10_0_gfxip_control_over_cgpg(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3145

gfx_v9_0_enable_gui_idle_interrupt(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3221

gfx_v9_0_enable_lbpw(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3226

gfx_v9_0_enable_lbpw(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3329

gfx_v9_0_cp_gfx_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3926

gfx_v9_0_cp_compute_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3988

gfx_v9_0_enable_gui_idle_interrupt(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4118

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4302

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4892

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4926

gfx_v9_0_enable_gfx_cg_power_gating(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4928

gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4945

gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4950

gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5180

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5199

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5242

gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5243

gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5250

gfx_v9_0_enable_cp_power_gating(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5261

amdgpu_gfx_off_ctrl_immediate(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5432

true : false,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5757

amdgpu_ring_set_preempt_cond_exec(ring, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5815

flags & AMDGPU_IB_PREEMPTED) ? true : false);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7227

r = gfx_v9_0_kcq_init_queue(ring, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7306

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7336

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7409

.support_64bit_ptrs = true,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7410

.secure_submission_supported = true,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7465

.support_64bit_ptrs = true,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7466

.secure_submission_supported = true,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7525

.support_64bit_ptrs = true,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7568

.support_64bit_ptrs = true,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

533

true);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

557

true);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

598

true);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1049

adev->gfx.enable_cleaner_shader = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1406

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1451

adev->gfx.rlc.rlcg_reg_access_supported = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1565

gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1717

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2227

gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2274

gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2413

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3499

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3612

r = gfx_v9_4_3_xcc_kcq_init_queue(ring, ring->xcc_id, true);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4739

.support_64bit_ptrs = true,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4783

.support_64bit_ptrs = true,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4928

is_symmetric_cus = true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

901

return true;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

988

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

651

value = true;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

475

hub->sdma_invalidation_workaround = true;

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

1073

return true;

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

82

amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true);

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

90

amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true);

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

1023

return true;

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

82

amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true);

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

90

amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true);

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

1010

return true;

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

72

amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true);

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

80

amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

1105

gate = true;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

427

adev->gmc.prt_warning = true;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

555

gmc_v6_0_set_fault_enable_default(adev, true);

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

970

return true;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

1156

return true;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

1305

info->prot_valid = protections & 0x7 ? true : false;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

1306

info->prot_read = protections & 0x8 ? true : false;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

1307

info->prot_write = protections & 0x10 ? true : false;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

1308

info->prot_exec = protections & 0x20 ? true : false;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

1322

gate = true;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

555

adev->gmc.prt_warning = true;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

699

gmc_v7_0_set_fault_enable_default(adev, true);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1279

return true;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1323

return true;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1493

info->prot_valid = protections & 0x7 ? true : false;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1494

info->prot_read = protections & 0x8 ? true : false;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1495

info->prot_write = protections & 0x10 ? true : false;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1496

info->prot_exec = protections & 0x20 ? true : false;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

772

adev->gmc.prt_warning = true;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

939

gmc_v8_0_set_fault_enable_default(adev, true);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1145

snoop = true;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1152

snoop = true;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1162

snoop = true;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1188

snoop = true;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1216

snoop = true;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1390

return true;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1595

adev->gmc.xgmi.supported = true;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1598

adev->gmc.xgmi.supported = true;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2190

adev->gmc.flush_pasid_uses_kiq = true;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2212

adev->mmhub.funcs->update_power_gating(adev, true);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2222

value = true;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2327

return true;

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

346

return true;

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

69

adev->irq.ih.enabled = true;

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

178

ih->enabled = true;

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

396

ret = ih_v6_0_toggle_interrupts(adev, true);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

400

force_update_wptr_for_self_int(adev, 0, 8, true);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

403

adev->irq.ih_soft.enabled = true;

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

453

ih->overflow = true;

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

595

adev->irq.ih.use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

604

adev->irq.ih1.use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

611

r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, true);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

661

return true;

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

150

ih->enabled = true;

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

367

ret = ih_v6_1_toggle_interrupts(adev, true);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

371

force_update_wptr_for_self_int(adev, 0, 8, true);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

374

adev->irq.ih_soft.enabled = true;

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

570

adev->irq.ih.use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

579

adev->irq.ih1.use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

586

r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

636

return true;

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

150

ih->enabled = true;

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

367

ret = ih_v7_0_toggle_interrupts(adev, true);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

371

force_update_wptr_for_self_int(adev, 0, 8, true);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

374

adev->irq.ih_soft.enabled = true;

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

560

adev->irq.ih.use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

569

adev->irq.ih1.use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

576

r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

626

return true;

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

358

val_h = imu_v12_0_grbm_gfx_index_remap(adev, data, true);

sys/dev/pci/drm/amd/amdgpu/isp_v4_1_1.c

217

r = pm_genpd_init(&isp->ispgpd, NULL, true);

sys/dev/pci/drm/amd/amdgpu/isp_v4_1_1.c

72

return amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ISP, true, 0);

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

559

.no_user_fence = true,

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

104

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

341

amdgpu_dpm_enable_jpeg(adev, true);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

146

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

119

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

357

amdgpu_dpm_enable_jpeg(adev, true);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

125

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

196

ring->sched.ready = true;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

394

amdgpu_dpm_enable_jpeg(adev, true);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1434

return true;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

177

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

387

ring->sched.ready = true;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

160

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

507

amdgpu_dpm_enable_jpeg(adev, true);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

106

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

431

amdgpu_dpm_enable_jpeg(adev, true);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

1049

return true;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

174

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

266

ring->sched.ready = true;

sys/dev/pci/drm/amd/amdgpu/mes_userqueue.c

278

userq_props->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/mes_userqueue.c

315

adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow_info, true);

sys/dev/pci/drm/amd/amdgpu/mes_userqueue.c

38

ret = amdgpu_bo_reserve(bo, true);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

105

.support_64bit_ptrs = true,

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1338

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1341

ring->no_scheduler = true;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1362

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1365

ring->no_scheduler = true;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1577

r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1585

mes_v11_0_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1602

adev->mes.enable_legacy_queue_map = true;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1647

AMDGPU_MES_SCHED_PIPE, true);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1654

mes_v11_0_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1690

adev->mes.ring[0].sched.ready = true;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

402

gfx_v11_0_request_gfx_index_mutex(adev, true);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1526

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1528

ring->no_scheduler = true;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1554

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1557

ring->no_scheduler = true;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1607

adev->mes.enable_legacy_queue_map = true;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1754

r = mes_v12_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1765

mes_v12_0_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1827

AMDGPU_MES_SCHED_PIPE, true);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1841

mes_v12_0_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1845

mes_v12_0_enable_unmapped_doorbell_handling(&adev->mes, true);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1877

adev->mes.ring[0].sched.ready = true;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

427

gfx_v12_0_request_gfx_index_mutex(adev, true);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

86

.support_64bit_ptrs = true,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

831

return true;

sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c

153

xgpu_ai_mailbox_set_valid(adev, true);

sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c

360

ras->is_rma = true;

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

121

ras->is_rma = true;

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

163

xgpu_nv_mailbox_set_valid(adev, true);

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

431

ras->is_rma = true;

sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c

363

xgpu_vi_mailbox_set_valid(adev, true);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

176

ih->enabled = true;

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

367

ret = navi10_ih_toggle_interrupts(adev, true);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

371

force_update_wptr_for_self_int(adev, 0, 8, true);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

374

adev->irq.ih_soft.enabled = true;

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

572

use_bus_addr = true;

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

577

adev->irq.ih.use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

586

r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, true);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

631

return true;

sys/dev/pci/drm/amd/amdgpu/nv.c

1008

adev->nbio.funcs->enable_doorbell_aperture(adev, true);

sys/dev/pci/drm/amd/amdgpu/nv.c

1040

return true;

sys/dev/pci/drm/amd/amdgpu/nv.c

415

amdgpu_atombios_scratch_regs_engine_hung(adev, true);

sys/dev/pci/drm/amd/amdgpu/nv.c

539

return true;

sys/dev/pci/drm/amd/amdgpu/nv.c

554

return true;

sys/dev/pci/drm/amd/amdgpu/nv.c

972

adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

568

amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

657

amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

792

psp->vbflash_done = true;

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

879

con->poison_supported = ((reg_data & GENMASK_ULL(24, 24)) >> 24) ? true : false;

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

880

return true;

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

522

amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

663

psp->vbflash_done = true;

sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c

304

return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false;

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

1119

.secure_submission_supported = true,

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

160

adev->sdma.instance[i].burst_nop = true;

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

470

sdma_v2_4_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

923

return true;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1139

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1142

ring->use_pollmem = true;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1212

return true;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1246

return true;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1561

.secure_submission_supported = true,

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

320

adev->sdma.instance[i].burst_nop = true;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

741

sdma_v3_0_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

743

sdma_v3_0_ctx_switch_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1309

sdma_v4_1_update_power_gating(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1399

sdma_v4_0_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1401

sdma_v4_0_ctx_switch_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1427

sdma_v4_0_ctx_switch_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1428

sdma_v4_0_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1768

adev->sdma.has_page_queue = true;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1851

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1880

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1945

amdgpu_sdma_destroy_inst_ctx(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1986

amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2010

sdma_v4_0_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2011

sdma_v4_0_gfx_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2030

return true;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2417

.support_64bit_ptrs = true,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2418

.secure_submission_supported = true,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2449

.support_64bit_ptrs = true,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2450

.secure_submission_supported = true,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

634

ret = amdgpu_sdma_init_microcode(adev, 0, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1022

sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1023

sdma_v4_4_2_inst_enable(adev, true, inst_mask);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1361

adev->sdma.has_page_queue = true;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1466

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1487

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1544

amdgpu_sdma_destroy_inst_ctx(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1621

return true;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1667

amdgpu_amdkfd_suspend(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1669

amdgpu_amdkfd_resume(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1688

sdma_v4_4_2_is_queue_selected(adev, instance_id, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1732

r = sdma_v4_4_2_inst_start(adev, inst_mask, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

201

ret = amdgpu_sdma_init_microcode(adev, 0, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2114

.support_64bit_ptrs = true,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2146

.support_64bit_ptrs = true,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2577

return true;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

986

sdma_v4_4_2_inst_enable(adev, true, inst_mask);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

988

sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1406

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1508

return true;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1549

amdgpu_amdkfd_suspend(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1550

r = amdgpu_sdma_reset_engine(adev, ring->me, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1551

amdgpu_amdkfd_resume(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1620

r = sdma_v5_0_gfx_resume_instance(adev, inst_id, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1669

amdgpu_ring_set_preempt_cond_exec(ring, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1911

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1937

.support_64bit_ptrs = true,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1938

.secure_submission_supported = true,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

834

sdma_v5_0_ctx_switch_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

835

sdma_v5_0_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

947

sdma_v5_0_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

949

sdma_v5_0_ctx_switch_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1256

r = amdgpu_sdma_init_microcode(adev, 0, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1325

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1372

amdgpu_sdma_destroy_inst_ctx(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1421

return true;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1457

amdgpu_amdkfd_suspend(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1458

r = amdgpu_sdma_reset_engine(adev, ring->me, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1459

amdgpu_amdkfd_resume(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1530

r = sdma_v5_2_gfx_resume_instance(adev, inst_id, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1578

amdgpu_ring_set_preempt_cond_exec(ring, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1716

return true;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1719

return true;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1871

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1913

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1939

.support_64bit_ptrs = true,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1940

.secure_submission_supported = true,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

681

sdma_v5_2_ctx_switch_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

682

sdma_v5_2_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

847

sdma_v5_2_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

849

sdma_v5_2_ctx_switch_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1281

adev->sdma.disable_uq = true;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1288

adev->sdma.no_user_submission = true;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1293

r = amdgpu_sdma_init_microcode(adev, 0, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1332

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1423

amdgpu_sdma_destroy_inst_ctx(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1462

return sdma_v6_0_set_userq_trap_interrupts(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1501

return true;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1562

amdgpu_ring_set_preempt_cond_exec(ring, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1580

r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1584

r = sdma_v6_0_gfx_resume_instance(adev, ring->me, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1724

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1751

.support_64bit_ptrs = true,

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1752

.secure_submission_supported = true,

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

618

sdma_v6_0_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

680

use_broadcast = true;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

806

return true;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

843

sdma_v6_0_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

845

sdma_v6_0_ctxempty_int_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1266

adev->sdma.disable_uq = true;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1273

adev->sdma.no_user_submission = true;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1278

r = amdgpu_sdma_init_microcode(adev, 0, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1318

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1376

amdgpu_sdma_destroy_inst_ctx(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1418

return sdma_v7_0_set_userq_trap_interrupts(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1457

return true;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1522

amdgpu_ring_set_preempt_cond_exec(ring, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1657

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1685

.support_64bit_ptrs = true,

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1686

.secure_submission_supported = true,

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

611

ring->sched.ready = true;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

614

sdma_v7_0_ctx_switch_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

615

sdma_v7_0_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

799

return true;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

819

r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

823

r = sdma_v7_0_gfx_resume_instance(adev, ring->me, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

863

sdma_v7_0_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

865

sdma_v7_0_ctx_switch_enable(adev, true);

sys/dev/pci/drm/amd/amdgpu/si.c

1173

{mmCC_RB_BACKEND_DISABLE, true},

sys/dev/pci/drm/amd/amdgpu/si.c

1174

{mmGC_USER_RB_BACKEND_DISABLE, true},

sys/dev/pci/drm/amd/amdgpu/si.c

1175

{mmPA_SC_RASTER_CONFIG, true},

sys/dev/pci/drm/amd/amdgpu/si.c

1341

return true;

sys/dev/pci/drm/amd/amdgpu/si.c

1398

amdgpu_atombios_scratch_regs_engine_hung(adev, true);

sys/dev/pci/drm/amd/amdgpu/si.c

1416

adev->has_hw_reset = true;

sys/dev/pci/drm/amd/amdgpu/si.c

1522

return true;

sys/dev/pci/drm/amd/amdgpu/si.c

2560

clk_req_support = true;

sys/dev/pci/drm/amd/amdgpu/si.c

2664

return true;

sys/dev/pci/drm/amd/amdgpu/si_dma.c

569

return true;

sys/dev/pci/drm/amd/amdgpu/si_ih.c

222

return true;

sys/dev/pci/drm/amd/amdgpu/si_ih.c

45

adev->irq.ih.enabled = true;

sys/dev/pci/drm/amd/amdgpu/sienna_cichlid.c

207

adev->ip_blocks[i].status.late_initialized = true;

sys/dev/pci/drm/amd/amdgpu/sienna_cichlid.c

41

return true;

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

290

smu_v11_0_i2c_enable(control, true);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

381

smu_v11_0_i2c_enable(control, true);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

479

return true;

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

488

return true;

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

562

if (!amdgpu_dpm_smu_i2c_bus_access(adev, true))

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

563

return true;

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

575

return true;

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

618

adev->pm.bus_locked = true;

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

794

return true;

sys/dev/pci/drm/amd/amdgpu/smu_v13_0_10.c

208

adev->ip_blocks[i].status.late_initialized = true;

sys/dev/pci/drm/amd/amdgpu/smu_v13_0_10.c

36

return true;

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c

128

return data ? true : false;

sys/dev/pci/drm/amd/amdgpu/soc15.c

1246

adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);

sys/dev/pci/drm/amd/amdgpu/soc15.c

1283

true, adev->doorbell_index.sdma_engine[i] << 1,

sys/dev/pci/drm/amd/amdgpu/soc15.c

1305

adev->nbio.funcs->enable_doorbell_aperture(adev, true);

sys/dev/pci/drm/amd/amdgpu/soc15.c

1370

return true;

sys/dev/pci/drm/amd/amdgpu/soc15.c

521

adev->nbio.funcs->enable_doorbell_interrupt(adev, true);

sys/dev/pci/drm/amd/amdgpu/soc15.c

534

connected_to_cpu = true;

sys/dev/pci/drm/amd/amdgpu/soc15.c

612

return true;

sys/dev/pci/drm/amd/amdgpu/soc15.c

753

return true;

sys/dev/pci/drm/amd/amdgpu/soc15.c

858

return true;

sys/dev/pci/drm/amd/amdgpu/soc15.c

861

return true;

sys/dev/pci/drm/amd/amdgpu/soc15.c

863

return true;

sys/dev/pci/drm/amd/amdgpu/soc15.c

878

return true;

sys/dev/pci/drm/amd/amdgpu/soc21.c

337

amdgpu_atombios_scratch_regs_engine_hung(adev, true);

sys/dev/pci/drm/amd/amdgpu/soc21.c

465

return true;

sys/dev/pci/drm/amd/amdgpu/soc21.c

481

return true;

sys/dev/pci/drm/amd/amdgpu/soc21.c

859

adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);

sys/dev/pci/drm/amd/amdgpu/soc21.c

889

adev->nbio.funcs->enable_doorbell_aperture(adev, true);

sys/dev/pci/drm/amd/amdgpu/soc21.c

957

return true;

sys/dev/pci/drm/amd/amdgpu/soc24.c

266

return true;

sys/dev/pci/drm/amd/amdgpu/soc24.c

282

return true;

sys/dev/pci/drm/amd/amdgpu/soc24.c

462

adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);

sys/dev/pci/drm/amd/amdgpu/soc24.c

496

adev->nbio.funcs->enable_doorbell_aperture(adev, true);

sys/dev/pci/drm/amd/amdgpu/soc24.c

536

return true;

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

305

r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, true);

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

309

adev->irq.ih.use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

364

return true;

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

395

return true;

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

67

adev->irq.ih.enabled = true;

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

375

umc_v12_0_convert_error_address(adev, err_data, &addr_in, NULL, true);

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

449

return true;

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

566

MCA_IPID_2_SOCKET_ID(ipid), &addr_out, true);

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

332

return true;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

183

.no_user_fence = true,

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

333

uvd_v3_1_set_dcm(adev, true);

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

651

uvd_v3_1_enable_mgcg(adev, true);

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

657

amdgpu_dpm_enable_uvd(adev, true);

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

161

uvd_v4_2_enable_mgcg(adev, true);

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

295

uvd_v4_2_set_dcm(adev, true);

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

777

.no_user_fence = true,

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

159

uvd_v5_0_enable_mgcg(adev, true);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

803

uvd_v5_0_enable_clock_gating(adev, true);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

884

.no_user_fence = true,

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1181

return true;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1255

bool int_handled = true;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1465

uvd_v6_0_enable_clock_gating(adev, true);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1554

.no_user_fence = true,

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1580

.no_user_fence = true,

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1609

.no_user_fence = true,

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

473

uvd_v6_0_enable_mgcg(adev, true);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1541

.no_user_fence = true,

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1573

.no_user_fence = true,

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

463

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

394

vce_v2_0_set_sw_cg(adev, true);

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

396

vce_v2_0_set_dyn_cg(adev, true);

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

471

vce_v2_0_enable_mgcg(adev, true, false);

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

590

gate = true;

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

591

sw_cg = true;

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

638

.no_user_fence = true,

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

174

vce_v3_0_override_vce_clock_gating(adev, true);

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

473

vce_v3_0_override_vce_clock_gating(adev, true);

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

663

return true;

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

921

.no_user_fence = true,

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

945

.no_user_fence = true,

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

473

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

827

.no_user_fence = true,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1904

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1936

amdgpu_dpm_enable_vcn(adev, true, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

2124

.no_user_fence = true,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

2125

.secure_submission_supported = true,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

2159

.no_user_fence = true,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1011

amdgpu_dpm_enable_vcn(adev, true, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

170

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

202

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2116

.secure_submission_supported = true,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1176

amdgpu_dpm_enable_vcn(adev, true, i);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1787

.secure_submission_supported = true,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

342

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

362

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

478

adev->vcn.inst[j].ring_enc[0].sched.ready = true;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

481

adev->vcn.inst[j].ring_dec.sched.ready = true;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1206

amdgpu_dpm_enable_vcn(adev, true, i);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1859

.secure_submission_supported = true,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2023

.secure_submission_supported = true,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

236

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

260

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

384

ring->no_scheduler = true;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

390

ring->sched.ready = true;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

397

ring->no_scheduler = true;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

403

ring->sched.ready = true;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1149

amdgpu_dpm_enable_vcn(adev, true, i);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2024

vcn_v4_0_unified_ring_vm_funcs.secure_submission_supported = true;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

220

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

337

ring->sched.ready = true;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

202

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

2052

return true;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

341

ring->sched.ready = true;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

871

adev->vcn.inst[inst_idx].aid_id, 0, true);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1061

amdgpu_dpm_enable_vcn(adev, true, i);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

119

adev->vcn.per_inst_fw = true;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1528

vcn_v4_0_5_unified_ring_vm_funcs.secure_submission_supported = true;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

182

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

162

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

818

amdgpu_dpm_enable_vcn(adev, true, i);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1677

return true;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

190

ring->use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

313

ring->sched.ready = true;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

694

adev->vcn.inst[inst_idx].aid_id, 0, true);

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

121

ih->enabled = true;

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

299

ret = vega10_ih_toggle_interrupts(adev, true);

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

304

adev->irq.ih_soft.enabled = true;

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

493

r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, true);

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

497

adev->irq.ih.use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

501

r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true);

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

505

adev->irq.ih1.use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

508

r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true);

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

512

adev->irq.ih2.use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

518

r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, true);

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

561

return true;

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

157

ih->enabled = true;

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

377

adev->irq.retry_cam_enabled = true;

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

380

ret = vega20_ih_toggle_interrupts(adev, true);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

385

adev->irq.ih_soft.enabled = true;

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

444

ih->overflow = true;

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

572

bool use_bus_addr = true;

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

588

adev->irq.ih.use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

595

adev->irq.ih1.use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

600

r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

604

adev->irq.ih2.use_doorbell = true;

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

661

return true;

sys/dev/pci/drm/amd/amdgpu/vi.c

1124

bool bClkReqSupport = true;

sys/dev/pci/drm/amd/amdgpu/vi.c

1163

bL1SS = true;

sys/dev/pci/drm/amd/amdgpu/vi.c

1168

bL1SS = true;

sys/dev/pci/drm/amd/amdgpu/vi.c

1341

return true;

sys/dev/pci/drm/amd/amdgpu/vi.c

1348

return true;

sys/dev/pci/drm/amd/amdgpu/vi.c

1422

return true;

sys/dev/pci/drm/amd/amdgpu/vi.c

1710

vi_enable_doorbell_aperture(adev, true);

sys/dev/pci/drm/amd/amdgpu/vi.c

1740

return true;

sys/dev/pci/drm/amd/amdgpu/vi.c

662

return true;

sys/dev/pci/drm/amd/amdgpu/vi.c

737

{mmCC_RB_BACKEND_DISABLE, true},

sys/dev/pci/drm/amd/amdgpu/vi.c

738

{mmGC_USER_RB_BACKEND_DISABLE, true},

sys/dev/pci/drm/amd/amdgpu/vi.c

740

{mmPA_SC_RASTER_CONFIG, true},

sys/dev/pci/drm/amd/amdgpu/vi.c

741

{mmPA_SC_RASTER_CONFIG_1, true},

sys/dev/pci/drm/amd/amdgpu/vi.c

873

amdgpu_atombios_scratch_regs_engine_hung(adev, true);

sys/dev/pci/drm/amd/amdgpu/vi.c

887

adev->has_hw_reset = true;

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

149

vpe_v6_1_set_collaborate_mode(vpe, true);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

181

vpe_v6_1_halt(vpe, true);

sys/dev/pci/drm/amd/amdkfd/cik_event_interrupt.c

50

*patched_flag = true;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

1015

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

1020

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

1025

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

1327

err = amdgpu_amdkfd_gpuvm_sync_memory(dev->adev, (struct kgd_mem *) mem, true);

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

1422

(struct kgd_mem *) mem, true);

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

1695

if (args->xnack_enabled && !kfd_process_xnack_mode(p, true)) {

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

2173

if (process_priv.xnack_mode && !kfd_process_xnack_mode(p, true)) {

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

2301

const bool criu_resume = true;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

2701

p->queues_paused = true;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

2798

true,

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

2857

amdgpu_gfx_off_ctrl(pdd->dev->adev, true);

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

3286

ptrace_attached = true;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1711

cache_line_size_missing = true;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

2068

found = true;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

2157

amdgpu_amdkfd_get_pcie_bandwidth_mbytes(kdev->adev, true);

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

124

bool is_subscribed = true;

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

215

if (!kfd_dbg_ev_raise(trap_mask, p, dev, doorbell_id, true,

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

235

signaled_to_debugger_or_runtime = true;

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

245

signaled_to_debugger_or_runtime = true;

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

248

signaled_to_debugger_or_runtime = true;

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

449

amdgpu_gfx_off_ctrl(pdd->dev->adev, true);

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

454

r = kfd_dbg_set_mes_debug_mode(pdd, true);

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

494

amdgpu_gfx_off_ctrl(pdd->dev->adev, true);

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

499

r = kfd_dbg_set_mes_debug_mode(pdd, true);

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

551

r = kfd_dbg_set_mes_debug_mode(pdd, true);

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

574

kfd_dbg_set_mes_debug_mode(pdd, true);

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

627

amdgpu_gfx_off_ctrl(pdd->dev->adev, true);

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

701

r = kfd_dbg_set_workaround(target, true);

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

730

pdd->dev->kfd2kgd->enable_debug_trap(pdd->dev->adev, true,

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

739

amdgpu_gfx_off_ctrl(pdd->dev->adev, true);

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

748

kfd_process_set_trap_debug_flag(&pdd->qpd, true);

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

753

r = kfd_dbg_set_mes_debug_mode(pdd, true);

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

768

kfd_dbg_trap_deactivate(target, true, i);

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

812

target->debug_trap_enabled = true;

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

882

amdgpu_gfx_off_ctrl(pdd->dev->adev, true);

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

887

r = kfd_dbg_set_mes_debug_mode(pdd, true);

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

914

amdgpu_gfx_off_ctrl(pdd->dev->adev, true);

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

919

r = kfd_dbg_set_mes_debug_mode(pdd, true);

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

959

found = true;

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

985

found = true;

sys/dev/pci/drm/amd/amdkfd/kfd_debug.h

128

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

1011

kfd_smi_event_update_gpu_reset(node, true, NULL);

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

1026

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

1037

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

1446

amdgpu_amdkfd_set_compute_idle(node->adev, true);

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

1453

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

1688

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

1697

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

1703

p->gpu_page_fault = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

215

kfd->device_info.supports_cwsr = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

234

kfd->device_info.needs_pci_atomics = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

241

kfd->device_info.needs_pci_atomics = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

244

kfd->device_info.needs_pci_atomics = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

247

kfd->device_info.needs_pci_atomics = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

258

kfd->device_info.supports_cwsr = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

261

kfd->device_info.needs_pci_atomics = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

559

kfd->cwsr_enabled = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

921

kfd->init_complete = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

975

kgd2kfd_suspend(kfd, true);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

1018

pdd->qpd.mapped_gws_queue = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

1020

q->properties.is_gws = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

1082

q->properties.is_suspended = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

1131

q->properties.is_active = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

1159

q->properties.is_evicted = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

1219

q->properties.is_evicted = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

1307

q->properties.is_active = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

1370

q->properties.is_active = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

1554

dqm->sched_running = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

1652

is_xgmi = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

1665

free_bit_found = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

170

pdd->has_reset_queue = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

1787

dqm->sched_halt = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

1852

dqm->sched_running = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

1938

qpd->is_debug = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2123

dqm->active_runlist = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2136

pdd->has_reset_queue = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2268

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2289

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2426

if (sdma_has_hang(dqm) && reset_queues_on_hws_hang(dqm, true))

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2443

dqm->is_hws_hang = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2457

pasid, USE_DEFAULT_GRACE_PERIOD, true);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2493

q->properties.is_being_destroyed = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2567

qpd->reset_wavefronts = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2611

bool retval = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2674

found = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2823

found = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3082

q->properties.is_evicted = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3537

WARN_ONCE(true, "queue type not recognized!");

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3628

r = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3750

dqm->active_runlist = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

408

qpd->mapped_gws_queue = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

760

set = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

887

qpd->reset_wavefronts = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

93

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_cik.c

98

bool retval = true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v10.c

76

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v11.c

76

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v12.c

76

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v9.c

88

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_vi.c

99

bool retval = true;

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

1009

while (true) {

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

1126

bool send_signal = true;

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

1226

memory_exception_data.failure.imprecise = true;

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

1276

memory_exception_data.failure.imprecise = true;

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

1371

memory_exception_data.failure.imprecise = true;

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

197

p->signal_event_limit_reached = true;

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

647

WRITE_ONCE(waiter->activated, true);

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

833

waiter->event_age_enabled = true;

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

835

waiter->activated = true;

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

84

page->need_to_free_pages = true;

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c

306

*patched_flag = true;

sys/dev/pci/drm/amd/amdkfd/kfd_interrupt.c

117

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_interrupt.c

78

node->interrupts_active = true;

sys/dev/pci/drm/amd/amdkfd/kfd_kernel_queue.c

177

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

157

NULL, &next, false, true, 0);

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

527

r = svm_range_vram_node_new(node, prange, true);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

308

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

144

(void *)&(mqd_mem_obj->cpu_ptr), true);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c

129

pm->allocated = true;

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c

268

true);

sys/dev/pci/drm/amd/amdkfd/kfd_process.c

1234

amdgpu_gfx_off_ctrl(pdd->dev->adev, true);

sys/dev/pci/drm/amd/amdkfd/kfd_process.c

1376

p->has_cwsr = true;

sys/dev/pci/drm/amd/amdkfd/kfd_process.c

1498

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_process.c

1727

kfd_smi_event_process(pdd, true);

sys/dev/pci/drm/amd/amdkfd/kfd_process.c

1781

pdd->runtime_inuse = true;

sys/dev/pci/drm/amd/amdkfd/kfd_process.c

1995

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_process.c

2166

pdd->process->irq_drain_is_open = true;

sys/dev/pci/drm/amd/amdkfd/kfd_process.c

757

err = amdgpu_amdkfd_gpuvm_sync_memory(kdev->adev, *mem, true);

sys/dev/pci/drm/amd/amdkfd/kfd_process.c

866

process = find_process(thread, true);

sys/dev/pci/drm/amd/amdkfd/kfd_process.c

978

p = find_process(task, true);

sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c

100

pdd->already_dequeued = true;

sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c

671

pqn->q->properties.is_user_cu_masked = true;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

1237

snoop = true;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

1250

snoop = true;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

1255

snoop = true;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

1270

snoop = true;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

1339

return amdgpu_vm_update_range(adev, vm, false, true, true, false, NULL, start,

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

1446

r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb, true,

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

1805

prange->mapped_to_gpu = true;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

1896

MAX_GPU_INSTANCE, false, true, false);

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

1980

mapped = true;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

2110

prange = svm_range_new(svms, start, l, true);

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

2250

svm_range_free(prange, true);

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

2300

svm_range_free(prange, true);

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

2617

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

2645

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

2896

prange = svm_range_new(&p->svms, start, last, true);

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

2903

svm_range_free(prange, true);

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

2943

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

2949

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

3095

write_locked = true;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

3188

migration = true;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

3305

svm_range_free(prange, true);

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

3755

MAX_GPU_INSTANCE, true, true, flush_tlb);

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

377

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

3770

MAX_GPU_INSTANCE, true, true, prange->mapped_to_gpu);

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

3838

get_preferred_loc = true;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

3841

get_prefetch_loc = true;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

3844

get_accessible = true;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

3848

get_flags = true;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

3851

get_granularity = true;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

478

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

520

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

616

r = amdgpu_bo_reserve(bo, true);

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

637

amdgpu_bo_fence(bo, &svm_bo->eviction_fence->base, true);

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

783

*update_mapping = true;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

799

*update_mapping = true;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

803

*update_mapping = true;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

867

return true;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

1127

is_unique = true;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

1710

found = true;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

1933

bool firmware_supported = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10027

amdgpu_dm_psr_disable(acrtc_state->stream, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10050

updated_planes_and_streams = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10318

acrtc->enabled = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10321

mode_set_reset_required = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10322

set_backlight_level = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10331

mode_set_reset_required = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1035

if (dm->dmub_thread_offload[notify.type] == true) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10351

dc_allow_idle_optimizations(dm->dc, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10432

wb_info->wb_enabled = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10485

acrtc->wb_pending = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10560

dm_new_con_state->update_hdcp = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10578

enable_encryption = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10594

enable_encryption = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10658

bool wait_for_vblank = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10708

output_color_space_changed = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10835

acrtc->dm_irq_params.window_param[cnt].update_win = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10889

acrtc->wb_enabled = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10987

crtc_state->mode_changed = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11117

new_crtc_state->stream->ignore_msa_timing_param = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11122

config.vsif_supported = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11123

config.btr = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11175

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11374

*lock_and_validation_needed = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1138

*enabled = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11412

*lock_and_validation_needed = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11453

ret = amdgpu_dm_check_crtc_color_mgmt(dm_new_crtc_state, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11490

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11498

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11502

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11506

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11518

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11529

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11534

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11544

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11547

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11572

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11579

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11583

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11588

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11592

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11597

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11609

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11617

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11625

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11738

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11747

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11834

*lock_and_validation_needed = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11912

*lock_and_validation_needed = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1196

adev->mode_info.audio.enabled = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12121

cursor_changed = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12126

consider_mode_change = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12133

consider_mode_change = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1216

adev->dm.audio_registered = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12192

entire_crtc_covered = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12226

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12272

bool is_top_most_overlay = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12304

new_crtc_state->connectors_changed = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12354

new_crtc_state->mode_changed = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12371

modified = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12471

true,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12484

true,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12600

lock_and_validation_needed = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12825

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12854

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12967

vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12971

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13076

freesync_capable = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13093

freesync_capable = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13107

amdgpu_dm_connector->pack_sdp_v1_3 = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13114

freesync_capable = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13306

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1355

hw_params.load_inst_const = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1370

hw_params.dpia_supported = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1382

hw_params.lower_hbr3_phy_ssc = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1426

adev->dm.dc->debug.sanity_checks = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1432

adev->dm.dc->debug.sanity_checks = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1716

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1931

init_data.flags.disable_dmcu = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1935

init_data.flags.disable_dmcu = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1964

init_data.flags.fbc_support = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1967

init_data.flags.multi_mon_pp_mclk_switch = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1970

init_data.flags.disable_fractional_pwm = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1973

init_data.flags.edp_no_power_sequencing = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1976

init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1978

init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1983

init_data.flags.seamless_boot_edp_requested = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1984

init_data.flags.allow_seamless_boot_optimization = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1988

init_data.flags.enable_mipi_converter_optimization = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2009

init_data.flags.allow_0_dtb_clk = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2017

init_data.flags.support_edp0_on_dp1 = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2041

adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2043

adev->dm.dc->debug.disable_stutter = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2046

adev->dm.dc->debug.disable_stutter = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2049

adev->dm.dc->debug.disable_dsc = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2052

adev->dm.dc->debug.disable_clock_gate = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2055

adev->dm.dc->debug.force_subvp_mclk_switch = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2058

adev->dm.dc->debug.force_disable_subvp = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2063

adev->dm.dc->debug.using_dml2 = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2064

adev->dm.dc->debug.using_dml21 = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2068

adev->dm.dc->debug.hdcp_lc_force_fw_enable = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2071

adev->dm.dc->debug.hdcp_lc_enable_sw_fallback = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2074

adev->dm.dc->debug.skip_detection_link_training = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2079

adev->dm.dc->debug.ignore_cable_id = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2207

adev->dm.secure_display_ctx.support_mul_roi = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2697

ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2954

oem_i2c = create_i2c(oem_ddc_service, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3054

&acrtc->base, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3156

new_crtc_state->active_changed = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3173

dm_new_crtc_state->base.color_mgmt_changed = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3227

s3_handle_hdmi_cec(adev_to_drm(adev), true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3229

s3_handle_mst(adev_to_drm(adev), true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

323

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3238

dc_allow_idle_optimizations(dm->dc, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3373

true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3465

dc_state->streams[i]->mode_changed = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3484

dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

368

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3697

caps->aux_support = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

370

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3702

caps->aux_support = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

372

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3748

if (aconnector->mst_mgr.mst_state == true)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3894

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3931

reallow_idle = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3945

fake_reconnect = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3968

dc_allow_idle_optimizations(dc, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3994

dm_con_state->update_hdcp = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4126

&link_loss, true, &has_left_work);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4149

offload_wq->is_handling_mst_msg_rdy_event = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4166

offload_wq->is_handling_link_loss = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4243

dmub_hpd_callback, true)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4249

dmub_hpd_callback, true)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4255

dmub_hpd_sense_callback, true)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4841

adev->mode_info.mode_config_initialized = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4856

adev_to_drm(adev)->mode_config.async_page_flip = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4938

caps->caps_valid = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4946

caps->caps_valid = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5115

reallow_idle = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5127

rc = dc_link_set_backlight_level_nits(link, true, brightness,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5143

dc_allow_idle_optimizations(dm->dc, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5484

psr_feature_enabled = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5510

replay_feature_enabled = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5972

adev->dc_enabled = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6126

plane_info->visible = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6195

dc_plane_state->flip_int_enabled = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6368

&flip_addrs->dirty_rect_count, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6603

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7004

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7238

native_mode_found = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7565

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7968

aconnector->force_yuv422_output = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7973

aconnector->force_yuv420_output = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8095

out->valid = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8135

new_crtc_state->mode_changed = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8143

new_crtc_state->mode_changed = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8151

new_crtc_state->mode_changed = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8366

vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8512

mode_existed = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8601

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8637

m = get_highest_refresh_rate_mode(aconnector, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8783

link->link_enc->features.hdmi_ycbcr420_supported ? true : false;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8791

link->link_enc->features.dp_ycbcr420_supported ? true : false;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8847

drm_connector_attach_content_protection_property(&aconnector->base, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9147

config.disable_immediate = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9203

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9206

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9209

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9212

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9252

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9261

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9290

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9307

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9315

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9329

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

938

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9534

WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9685

amdgpu_dm_replay_enable(acrtc_state->stream, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9773

cursor_update = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9857

amdgpu_dm_psr_disable(acrtc_state->stream, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1040

stream->gamut_remap_matrix.enable_remap = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1318

dc_plane_state->gamut_remap_matrix.enable_remap = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

375

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

501

__drm_lut_to_dc_gamma(lut, gamma, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

503

res = mod_color_calculate_regamma_params(func, gamma, true, has_rom,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

742

lut->lut_3d.use_12bits = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

963

crtc->cm_is_degamma_srgb = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

156

swap = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

160

swap = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

171

swap = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

198

dm->secure_display_ctx.phy_id_mapping[idx].assigned = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

203

dm->secure_display_ctx.phy_id_mapping[idx].is_mst = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

213

dm->secure_display_ctx.phy_mapping_updated = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

240

found = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

257

found = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

271

found = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

292

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

329

dc_stream_forward_multiple_crc_window(stream, NULL, phy_id, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

331

dc_stream_forward_crc_window(stream, NULL, phy_id, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

519

stream_state, NULL, enable, enable, 0, true)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

765

drm_crtc_add_crc_entry(crtc, true,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

785

bool all_crc_ready = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

855

forward_roi_change = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

859

&crc_window, true, true, i, false);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

861

reset_crc_frame_count[i] = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

879

notify_ta = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

883

&crc_window, true, true, i, false);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

886

crtc_ctx->crc_info.crc[i].crc_ready = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

144

amdgpu_dm_replay_enable(vblank_work->stream, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

173

bool is_headless = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

176

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

200

idle_work->dm->idle_workqueue->running = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

223

dc_allow_idle_optimizations(idle_work->dm->dc, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

280

dc_allow_idle_optimizations(dm->dc, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

334

rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

417

return amdgpu_dm_crtc_set_vblank(crtc, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

649

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

781

true, MAX_COLOR_LUT_ENTRIES);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1021

sink_support_replay = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1022

driver_support_replay = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1382

try_again = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1400

is_fec_supported = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1401

is_dsc_supported = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1523

if (aconnector->mst_mgr.mst_state == true)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1711

dm_crtc_state->dsc_force_changed = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1895

dm_crtc_state->dsc_force_changed = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2079

dm_crtc_state->dsc_force_changed = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2251

dm_crtc_state->dsc_force_changed = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

270

bool valid_input = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3240

aconnector->disallow_edp_enter_psr = val ? true : false;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3443

bool valid_input = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3493

prefer_link_settings.use_link_rate_set = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

356

is_end_device = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3730

amdgpu_dm_psr_disable(acrtc->dm_irq_params.stream, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3734

acrtc->dm_irq_params.window_param[0].enable = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3735

acrtc->dm_irq_params.window_param[0].update_win = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3737

acrtc->dm_irq_params.crc_window_activated = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3903

ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

401

bool valid_input = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4131

adev->dm.dc->debug.skip_detection_link_training = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

471

dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

807

valid_test_pattern = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

816

disable_hpd = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

817

valid_test_pattern = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

45

struct i2c_payload i2c_payloads[] = {{true, address, size, (void *)data} };

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

523

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

57

struct i2c_payload i2c_payloads[] = {{true, address, 1, &offset},

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

652

link_lock(work, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

680

link_lock(work, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1148

panel_config->dsc.disable_dsc_edp = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1316

aconnector->timing_changed = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1380

ret_val = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1396

if (dpcd_caps->adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT == true &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1397

dpcd_caps->allow_invalid_MSA_timing_param == true &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

312

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

389

set_flag, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

419

amdgpu_dm_set_mst_status(&aconnector->mst_status, set_flag, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

527

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

533

ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

542

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

559

if (aconnector->mst_mgr.mst_state == true) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

734

if (!execute_synaptics_rc_command(aux, true, 0x01, 5, 0, data))

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

74

edid_caps->panel_patch.disable_fams = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

742

if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

749

if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220D98, data))

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

756

if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

764

if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

776

if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

780

if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL))

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

83

edid_caps->panel_patch.remove_sink_ext_caps = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

88

edid_caps->panel_patch.disable_colorimetry = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

922

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

168

handler_removed = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

261

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

277

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

532

dc_interrupt_set(adev->dm.dc, src, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

556

dc_interrupt_set(adev->dm.dc, src, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

578

work_queued = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

878

true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

939

true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

946

true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1016

bpp_increased[i] = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1087

bpp_increased[next_index] = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1119

tried[i] = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1171

tried[next_index] = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1241

debugfs_overwrite = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1304

vars[i + k].dsc_enabled = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1429

is_dsc_need_re_compute = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1470

is_dsc_need_re_compute = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1534

computed_streams[j] = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1598

computed_streams[j] = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1633

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1652

ret = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1852

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

247

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

261

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

310

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

330

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

348

if (drm_dp_read_desc(immediate_upstream_aux, &branch_desc, true))

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

358

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

416

MST_REMOTE_EDID, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

653

MST_PROBE, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

105

*pre_multiplied_alpha = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1143

state, new_crtc_state, min_scale, max_scale, true, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

127

*per_pixel_alpha = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1327

position->enable = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1334

position->translate_by_source = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

137

*global_alpha = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1444

dc_plane_force_dcc_and_tiling_disable(dc_plane_state, fb->modifier ? true : false);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1543

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1584

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1826

adev_to_drm(dm->adev)->mode_config.fb_modifiers_not_supported = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1912

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

949

r = amdgpu_bo_reserve(rbo, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

109

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

308

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

358

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

378

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

398

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

415

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

446

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

463

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

151

bool psr_enable = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

170

params.triggers.cursor_update = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

171

params.triggers.overlay_update = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

172

params.triggers.surface_update = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

190

dc_allow_idle_optimizations(link->ctx->dc, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

241

allow_active = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

276

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

88

link->psr_settings.psr_feature_enabled = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_quirks.c

171

dm->aux_hpd_discon_quirk = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_quirks.c

175

dm->edp0_on_dp1_quirk = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_quirks.c

44

quirk_entries.support_edp0_on_dp1 = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_quirks.c

50

quirk_entries.aux_hpd_discon = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

103

pr_config.replay_supported = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

112

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

142

link->replay_settings.replay_feature_enabled = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

144

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

155

bool replay_active = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

168

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

192

link->dc->link_srv->edp_set_replay_allow_active(stream->link, &replay_active, true, false, NULL);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

193

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

70

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

87

return true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c

103

r = amdgpu_bo_reserve(rbo, true);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c

64

found = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/dc_fpu.c

94

TRACE_DCN_FPU(true, function_name, line, depth);

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

155

return true;

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

47

return true;

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

70

return true;

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

97

return true;

sys/dev/pci/drm/amd/display/dc/basics/dc_common.c

38

return true;

sys/dev/pci/drm/amd/display/dc/basics/dc_common.c

56

return true;

sys/dev/pci/drm/amd/display/dc/basics/dc_common.c

58

return true;

sys/dev/pci/drm/amd/display/dc/basics/dc_common.c

65

return true;

sys/dev/pci/drm/amd/display/dc/basics/dc_common.c

67

return true;

sys/dev/pci/drm/amd/display/dc/basics/dc_common.c

74

return true;

sys/dev/pci/drm/amd/display/dc/basics/dc_common.c

76

return true;

sys/dev/pci/drm/amd/display/dc/basics/dc_common.c

78

return true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

173

d0_underlay_enable = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

177

d1_underlay_enable = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2094

vbios->scatter_gather_enable = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2137

dceip->pre_downscaler_enabled = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2138

dceip->underlay_downscale_prefetch_enabled = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2164

dceip->limit_excessive_outstanding_dmif_requests = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2210

vbios->scatter_gather_enable = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2231

dceip->argb_compression_support = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2253

dceip->pre_downscaler_enabled = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2254

dceip->underlay_downscale_prefetch_enabled = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2257

dceip->graphics_lb_nodownscaling_multi_line_prefetching = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2280

dceip->limit_excessive_outstanding_dmif_requests = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2326

vbios->scatter_gather_enable = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2347

dceip->argb_compression_support = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2369

dceip->pre_downscaler_enabled = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2370

dceip->underlay_downscale_prefetch_enabled = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2373

dceip->graphics_lb_nodownscaling_multi_line_prefetching = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2396

dceip->limit_excessive_outstanding_dmif_requests = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2462

dceip->display_write_back_supported = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2463

dceip->argb_compression_support = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2485

dceip->pre_downscaler_enabled = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2486

dceip->underlay_downscale_prefetch_enabled = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2489

dceip->graphics_lb_nodownscaling_multi_line_prefetching = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2512

dceip->limit_excessive_outstanding_dmif_requests = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2555

vbios->scatter_gather_enable = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2576

dceip->argb_compression_support = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2598

dceip->pre_downscaler_enabled = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2599

dceip->underlay_downscale_prefetch_enabled = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2625

dceip->limit_excessive_outstanding_dmif_requests = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2681

dceip->dmif_pipe_en_fbc_chunk_tracker = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2688

dceip->display_write_back_supported = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2689

dceip->argb_compression_support = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2711

dceip->pre_downscaler_enabled = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2715

dceip->graphics_lb_nodownscaling_multi_line_prefetching = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2738

dceip->limit_excessive_outstanding_dmif_requests = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2782

return true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2799

data->increase_voltage_to_support_mclk_switch = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3032

return true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

354

fbc_enabled = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

356

lpt_enabled = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3610

calcs_output->nbp_state_change_enable = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3611

calcs_output->cpuc_state_change_enable = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3612

calcs_output->cpup_state_change_enable = true;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3613

calcs_output->stutter_mode_enable = true;

sys/dev/pci/drm/amd/display/dc/basics/vector.c

176

return true;

sys/dev/pci/drm/amd/display/dc/basics/vector.c

231

return true;

sys/dev/pci/drm/amd/display/dc/basics/vector.c

289

return true;

sys/dev/pci/drm/amd/display/dc/basics/vector.c

298

return true;

sys/dev/pci/drm/amd/display/dc/basics/vector.c

309

return true;

sys/dev/pci/drm/amd/display/dc/basics/vector.c

50

return true;

sys/dev/pci/drm/amd/display/dc/basics/vector.c

88

return true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1056

info->type.EXTERNAL = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1060

info->type.CENTER_MODE = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1151

ss_info->type.EXTERNAL = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1155

ss_info->type.CENTER_MODE = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1157

ss_info->type.STEP_AND_DELAY_INFO = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1316

info->lcd_timing.misc_info.DOUBLE_CLOCK = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1319

info->lcd_timing.misc_info.RGB888 = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1326

info->lcd_timing.misc_info.SPATIAL = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1329

info->lcd_timing.misc_info.TEMPORAL = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1332

info->lcd_timing.misc_info.API_ENABLED = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1450

info->lcd_timing.misc_info.DOUBLE_CLOCK = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1453

info->lcd_timing.misc_info.RGB888 = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1925

bool rc = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1964

return true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

2942

return true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

699

ss_info->type.EXTERNAL = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

702

ss_info->type.CENTER_MODE = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

1006

ss_info->type.CENTER_MODE = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

1016

ss_info->type.CENTER_MODE = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

1033

ss_info->type.CENTER_MODE = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

1827

info->oem_i2c_present = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

1914

info->oem_i2c_present = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

2056

info->oem_i2c_present = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

2086

info->oem_i2c_present = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

3787

return true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

502

find_valid = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

515

info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

840

ss_info->type.CENTER_MODE = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

850

ss_info->type.CENTER_MODE = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

861

ss_info->type.CENTER_MODE = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

883

ss_info->type.CENTER_MODE = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

935

ss_info->type.CENTER_MODE = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

945

ss_info->type.CENTER_MODE = true;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

956

ss_info->type.CENTER_MODE = true;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1329

if ((enable == true) && (bp_params->percentage > 0))

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1380

if ((enable == true) && (bp_params->percentage > 0)) {

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1450

if (enable == true) {

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1580

if (bp_params->ss_enable == true)

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

2230

is_input_signal_dp = true;

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

388

is_phy_transition_interlock_allowed = true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

102

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

105

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

108

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

224

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

227

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

230

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

233

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

236

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

364

result = true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

368

result = true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

372

result = true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

376

result = true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

380

result = true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

384

result = true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

388

result = true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

392

result = true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

44

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

51

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

55

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

59

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

64

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

87

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

90

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

93

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

96

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

99

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c

110

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c

113

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c

116

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c

119

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c

122

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c

125

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c

132

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c

209

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c

212

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c

219

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c

222

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c

45

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c

52

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c

56

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c

60

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c

67

return true;

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c

88

return true;

sys/dev/pci/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c

109

bool result = true;

sys/dev/pci/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c

108

bool result = true;

sys/dev/pci/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c

207

bool retCode = true;

sys/dev/pci/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c

106

bool result = true;

sys/dev/pci/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c

205

bool retCode = true;

sys/dev/pci/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c

65

bool result = true;

sys/dev/pci/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c

65

bool result = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

254

pxl_clk_params.flags.SET_DISPCLK_DFS_BYPASS = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

327

clk_mgr_dce->dfs_bypass_enabled = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

348

clk_mgr_dce->ss_on_dprefclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

372

clk_mgr_dce->ss_on_dprefclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

67

clk_mgr_dce->xgmi_enabled = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

68

clk_mgr_dce->ss_on_dprefclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

172

true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

212

enter_display_off = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

228

send_request_to_increase = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

232

send_request_to_lower = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

241

send_request_to_lower = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

247

send_request_to_lower = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

253

send_request_to_lower = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

276

send_request_to_lower = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

343

clk_mgr->dfs_bypass_enabled = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

170

true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

199

dccg->funcs->set_fifo_errdet_ovr_en(dccg, true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

240

force_reset = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

251

enter_display_off = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

298

dpp_clock_lowered = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

301

update_dppclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

307

update_dispclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

407

clk_mgr->clks.p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

408

clk_mgr->clks.prev_p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

489

return true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

108

force_reset = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

145

dpp_clock_lowered = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

148

update_dppclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

154

update_dispclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

214

clk_mgr->dfs_bypass_enabled = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

78

clk_mgr->clks.p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

79

clk_mgr->clks.prev_p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

201

dpp_clock_lowered = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

203

update_dppclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

210

update_dispclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

449

clk_mgr->clks.p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

450

clk_mgr->clks.prev_p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

540

return true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

67

tmds_present = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

687

bw_params->wm_table.entries[i].valid = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

115

clk_mgr_base->clks.p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

116

clk_mgr_base->clks.prev_p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

123

clk_mgr->smu_present = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

217

force_reset = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

226

enter_display_off = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

256

update_pstate_unsupported_clk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

278

update_uclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

288

dpp_clock_lowered = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

292

update_dppclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

298

update_dispclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

452

return true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

105

return true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

121

return true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

135

return true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

154

return true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

173

return true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c

102

return true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

159

dpp_clock_lowered = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

161

update_dppclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

168

update_dispclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

381

clk_mgr->clks.p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

382

clk_mgr->clks.prev_p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

477

return true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

628

bw_params->wm_table.entries[i].valid = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

727

clk_mgr->base.smu_present = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

76

tmds_present = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

158

dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

189

dcn31_smu_set_dtbclk(clk_mgr, true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

219

dpp_clock_lowered = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

221

update_dppclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

225

dcn31_disable_otg_wa(clk_mgr_base, context, true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

231

update_dispclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

304

clk_mgr->clks.p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

305

clk_mgr->clks.prev_p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

326

return true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

352

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

360

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

368

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

376

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

389

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

397

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

405

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

413

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

629

bw_params->wm_table.entries[i].valid = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

723

clk_mgr->base.smu_present = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

90

tmds_present = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

187

tmds_present = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

257

clk_mgr->clks.p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

258

clk_mgr->clks.prev_p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

299

dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

329

dcn314_smu_set_dtbclk(clk_mgr, true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

360

dpp_clock_lowered = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

362

update_dppclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

369

dcn314_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

380

update_dispclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

462

return true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

543

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

551

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

559

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

567

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

580

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

588

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

596

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

604

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

882

bw_params->wm_table.entries[i].valid = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

909

clk_mgr->ss_on_dprefclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

965

clk_mgr->base.smu_present = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

167

dcn315_smu_set_dtbclk(clk_mgr, true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

199

dpp_clock_lowered = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

201

update_dppclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

208

dcn315_disable_otg_wa(clk_mgr_base, context, true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

218

update_dispclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

312

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

320

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

328

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

336

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

349

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

357

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

365

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

373

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

581

bw_params->wm_table.entries[i].valid = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

653

clk_mgr->base.smu_present = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

71

tmds_present = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

92

bool ret = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

177

dcn316_smu_set_dtbclk(clk_mgr, true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

207

dpp_clock_lowered = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

209

update_dppclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

216

dcn316_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

226

update_dispclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

278

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

286

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

294

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

302

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

315

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

323

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

331

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

339

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

561

bw_params->wm_table.entries[i].valid = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

628

clk_mgr->base.smu_present = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

83

tmds_present = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1087

return true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

175

clk_mgr_base->clks.p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

176

clk_mgr_base->clks.prev_p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

177

clk_mgr_base->clks.fclk_prev_p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

182

clk_mgr->smu_present = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

234

clk_mgr->dpm_present = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

389

true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

441

dccg->funcs->set_fifo_errdet_ovr_en(dccg, true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

500

is_native_scaling = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

644

force_reset = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

655

enter_display_off = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

730

dcn32_smu_wait_for_dmub_ack_mclk(clk_mgr, true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

736

update_fclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

749

update_uclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

773

dpp_clock_lowered = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

788

update_dppclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

794

update_dispclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

954

clk_mgr->ss_on_dprefclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

154

return true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

198

return true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

201

return true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

204

return true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

257

hard_min_done = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

93

return true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1188

bw_params->wm_table.entries[i].valid = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1219

return dcn35_smu_get_ips_supported(clk_mgr) ? true : false;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1291

clk_mgr->clks.dtbclk_en = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1434

clk_mgr->base.smu_present = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

170

tmds_present = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

313

dppclk_active[dpp_inst] = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

408

dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

436

dcn35_smu_set_dtbclk(clk_mgr, true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

476

dpp_clock_lowered = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

478

update_dppclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

485

dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

496

update_dispclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

589

return true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

728

clk_mgr->clks.p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

729

clk_mgr->clks.prev_p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

753

clk_mgr->clks.dtbclk_en = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

773

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

781

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

789

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

797

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

810

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

818

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

826

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

834

.valid = true,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

860

clk_mgr->ss_on_dprefclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1103

force_reset = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1137

dppclk_lowered = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1142

update_dppclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1154

update_dispclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1287

clk_mgr->ss_on_dprefclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

129

ppclk_idle_dpm_enabled = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

132

ppclk_idle_dpm_enabled = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1348

new_clocks.p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1354

true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1446

return true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

189

clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

202

clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

228

clk_mgr_base->clks.p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

229

clk_mgr_base->clks.prev_p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

230

clk_mgr_base->clks.fclk_prev_p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

235

clk_mgr->smu_present = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

289

clk_mgr->dpm_present = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

405

is_native_scaling = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

805

enter_display_off = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

819

update_active_fclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

820

update_idle_fclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

903

update_active_uclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

904

update_idle_uclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

909

block_sequence[num_steps].params.update_pstate_support_params.support = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

935

update_active_uclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

944

update_idle_uclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

951

update_subvp_prefetch_dramclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

961

update_active_fclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

970

update_idle_fclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

977

update_subvp_prefetch_fclk = true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

137

TRACE_SMU_MSG_EXIT(true, param_out ? *param_out : 0, clk_mgr->base.ctx);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

138

return true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

155

return true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

174

return true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

193

return true;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

76

TRACE_SMU_MSG_EXIT(true, param_out ? *param_out : 0, clk_mgr->base.ctx);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

77

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1037

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1123

dc_ctx->created_bios = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1184

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1326

bool should_disable = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1345

should_disable = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1355

should_disable = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1371

dc->hwseq->funcs.blank_pixel_data(dc, pipe, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1377

dc_state_rem_all_phantom_planes_for_stream(dc, old_stream, dangling_context, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1389

apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1398

dc->hwss.interdependent_update_lock(dc, dc->current_state, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1697

status->timing_sync_info.master = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1756

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1760

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1762

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1983

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2094

dc->scratch.pipes_to_unlock_first[i] = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2160

dc->hwss.subvp_pipe_control_lock(dc, context, true, true, NULL, subvp_prev_use);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2162

dc->hwss.fams2_global_control_lock(dc, context, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2175

apply_ctx_interdependent_lock(dc, context, context->streams[i], true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2214

dc->hwss.interdependent_update_lock(dc, context, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2231

dc->hwss.subvp_pipe_control_lock(dc, context, false, true, NULL, subvp_prev_use);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2242

apply_ctx_interdependent_lock(dc, context, context->streams[i], true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2294

dc->hwss.update_dsc_pg(dc, context, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2395

handle_exit_odm2to1 = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2450

status->is_abm_supported = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2483

found_pipe_idx = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2489

found_pipe_idx = true;/*for release pipe_idx is not required*/

sys/dev/pci/drm/amd/display/dc/core/dc.c

2517

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2576

dc->hwss.update_dsc_pg(dc, context, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2622

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2641

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

267

link_init_params.is_dpia_link = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2914

has_flip_immediate_plane = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3053

dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3056

dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

322

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3290

update->crtc_timing_adjust->timing_adjust_pending = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

334

bool res = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3424

dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3578

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3700

dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3717

bool should_program_abm = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3742

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3745

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3748

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3962

should_offload_fams2_flip = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4017

pipe_ctx->plane_state->triplebuffer_flips = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4135

subvp_curr_use = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4160

true,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4177

dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, NULL, subvp_prev_use);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4180

dc->hwss.fams2_global_control_lock(dc, context, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4182

dc->hwss.interdependent_update_lock(dc, context, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4185

dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4188

dc->hwss.fams2_global_control_lock(dc, context, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4194

dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4269

pipe_ctx->plane_state->triplebuffer_flips = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

431

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4543

force_minimal_pipe_splitting = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4545

force_minimal_pipe_splitting = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4546

*is_plane_addition = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4557

force_minimal_pipe_splitting = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4559

force_minimal_pipe_splitting = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4560

*is_plane_addition = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4569

subvp_active = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4586

force_minimal_pipe_splitting = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4588

force_minimal_pipe_splitting = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4589

*is_plane_addition = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4616

dc->debug.force_disable_subvp = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

466

stream->adjust.timing_adjust_pending = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4769

success = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4818

success = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4912

subvp_in_use = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4938

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

496

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4969

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5003

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5012

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5024

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5032

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5067

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5100

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5105

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5108

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5111

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5211

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5315

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

535

status = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5526

allow_active = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5531

if (!dc_link_set_psr_allow_active(link, &allow_active, true, false, NULL))

sys/dev/pci/drm/amd/display/dc/core/dc.c

5537

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5556

allow_active = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5563

true, false, NULL))

sys/dev/pci/drm/amd/display/dc/core/dc.c

5569

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5579

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5671

dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5688

dc->hwss.disable_pixel_data(dc, pipe, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5696

hubp->funcs->set_blank_regs(hubp, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5756

blank_and_force_memclk(dc, true, softMax);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5766

blank_and_force_memclk(dc, true, maxDPM);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5779

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5795

dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5821

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5827

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5935

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5977

bool is_cmd_complete = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

616

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

6335

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

6346

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

6358

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

678

return true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

873

ret = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

898

ret = true;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

128

ret = true;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

139

ret = true;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

150

ret = true;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

160

ret = true;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

171

ret = true;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

181

ret = true;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

191

ret = true;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

295

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

308

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

405

is_sdr = true;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

415

is_sdr = true;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

418

is_sdr = true;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

668

enable_subvp = true;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

752

block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = true;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

760

block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.lock = true;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

767

block_sequence[*num_steps].params.pipe_control_lock_params.lock = true;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

857

block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.power_on = true;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

861

if (current_mpc_pipe->stream->csc_color_matrix.enable_adjustment == true) {

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

139

.valid = true,

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

194

is_avail = true;

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

205

is_avail = true;

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

220

are_equal = true;

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

242

if (assignment.valid == true && are_ep_ids_equal(&assignment.ep_id, &ep_id))

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

371

ASSERT(stream->link->is_dig_mapping_flexible != true);

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

47

is_dig_stream = true;

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

472

if ((assignment.valid == true) && (assignment.eng_id == eng_id)) {

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

513

if (assignment.valid == true && are_ep_ids_equal(&assignment.ep_id, &ep_id)) {

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

589

if (assignment.valid == true && are_ep_ids_equal(&assignment.ep_id, &ep_id)) {

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

600

bool is_avail = true;

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

622

bool valid_entries = true;

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

623

bool valid_stream_ptrs = true;

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

624

bool valid_uniqueness = true;

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

625

bool valid_avail = true;

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

626

bool valid_streams = true;

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

78

if ((assignment.valid == true) && (assignment.eng_id == eng_id)) {

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

82

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1504

res = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1577

res = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1691

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2223

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2230

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2232

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2235

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2237

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2241

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2244

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2247

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2249

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2254

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2256

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2270

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2274

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2277

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2384

slice_count, true);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2488

bool result = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2511

bool result = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2741

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2936

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3015

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3157

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3217

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3278

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3336

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3350

bool result = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3385

bool result = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3413

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3417

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3429

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3443

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3470

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3480

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3495

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3544

if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3759

stream->apply_seamless_boot_optimization = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

378

aud_support->dp_audio = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

384

aud_support->hdmi_audio_on_dongle = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

385

aud_support->hdmi_audio_native = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3871

bool is_dio_encoder = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3886

acquired = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3909

true);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3935

true);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3961

pipe_ctx->stream_res.audio, true);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4022

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4026

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4053

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4099

found = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4116

found = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4134

found = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4143

found = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4186

if (!dc_state_rem_all_phantom_planes_for_stream(dc, del_streams[i], context, true)) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4651

info_packet->valid = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4736

sdp_line_num->adaptive_sync_line_num_valid = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

483

dc->caps.dynamic_audio = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4887

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4890

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4893

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4897

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4900

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4903

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4906

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4910

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4913

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4916

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4918

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4923

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4931

need_reprogram = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

498

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5252

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5485

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5504

true);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5540

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5615

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

595

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

641

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

654

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

686

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

765

*flip_vert_scan_dir = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

766

*flip_horz_scan_dir = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

768

*orthogonal_rotation = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

769

*flip_horz_scan_dir = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

771

*orthogonal_rotation = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

772

*flip_vert_scan_dir = true;

sys/dev/pci/drm/amd/display/dc/core/dc_sink.c

53

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

104

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

1073

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

116

res = true;

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

139

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

542

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

55

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

578

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

621

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

632

bool result = true;

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

67

res = true;

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

728

phantom_stream->is_phantom = true;

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

730

phantom_stream->dpms_off = true;

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

765

phantom_plane->is_phantom = true;

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

815

dc_state_set_stream_subvp_cursor_limit(main_stream, state, true);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

90

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

903

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

932

removed_phantom = true;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

1148

true);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

1200

return dc_stream_get_max_flickerless_instant_vtotal_delta(stream, is_gaming, true);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

129

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

248

dc->hwss.cursor_lock(dc, pipe_to_program, true);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

250

dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, true);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

307

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

324

result = true;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

347

reset_idle_optimizations = true;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

354

dc_allow_idle_optimizations(dc, true);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

356

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

387

dc->hwss.cursor_lock(dc, pipe_to_program, true);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

416

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

441

reset_idle_optimizations = true;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

447

dc_allow_idle_optimizations(dc, true);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

469

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

512

isDrc = true;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

546

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

575

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

639

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

697

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

731

ret = true;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

753

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

800

return true;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

900

dc->res_pool->rmcm_3dlut[i].isInUse = true;

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

44

plane_state->gamma_correction.is_identity = true;

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

54

plane_state->pre_multiplied_alpha = true;

sys/dev/pci/drm/amd/display/dc/core/dc_vm_helper.c

49

dc->vm_pa_config.valid = true;

sys/dev/pci/drm/amd/display/dc/core/dc_vm_helper.c

50

dc->dml2_options.gpuvm_enable = true;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1018

return true;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1021

return true;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1144

return true;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1183

return true;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1186

return true;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1205

return true;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1247

cmd.idle_opt_notify_idle.cntl_data.skip_otg_disable = true;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1341

dc_dmub_srv->needs_idle_wake = true;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1439

if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1470

if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1539

reallow_idle = true;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1547

dc_dmub_srv_apply_idle_power_optimizations(dc_dmub_srv->ctx->dc, true);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1596

dc_dmub_srv->idle_allowed = true;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1618

return true;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1622

reallow_idle = true;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1636

dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, true);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1657

return true;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1665

return true;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1679

reallow_idle = true;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1686

dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, true);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

177

return true;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1957

return true;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1985

return true;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

236

return true;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

280

dmub->debug.timeout_info.timeout_occured = true;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

295

return true;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

504

return true;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

602

pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true;

sys/dev/pci/drm/amd/display/dc/dc_fused_io.c

33

return true;

sys/dev/pci/drm/amd/display/dc/dc_fused_io.c

50

loc->is_aux = true;

sys/dev/pci/drm/amd/display/dc/dc_fused_io.c

56

return true;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

165

return true;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

640

offload->gather_in_progress = true;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

149

spl_in->disable_easf = true;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

156

spl_in->adaptive_sharpness.enable = true;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

173

spl_in->adaptive_sharpness.enable = true;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

179

spl_in->adaptive_sharpness.enable = true;

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

258

dto_params.is_hdmi = true;

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1008

dccg35_set_symclk32_le_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1023

dccg35_set_physymclk_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1060

dccg35_set_dppclk_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1067

dccg35_set_dsc_clk_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1090

dccg35_set_dtbclk_p_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1097

dccg35_set_dpstreamclk_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1174

dcn35_set_dppclk_enable(dccg, dpp_inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1655

dto_params.is_hdmi = true;

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

930

dccg35_set_symclk_fe_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

960

dccg35_set_symclk_be_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

977

dccg35_set_symclk32_se_rcg(dccg, inst, true);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

613

enable = true;

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

97

dcn401_set_dppclk_enable(dccg, dpp_inst, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

204

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

217

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

223

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

227

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

248

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

64

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

83

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

110

found = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

147

limit_freq_to_48_khz = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

153

limit_freq_to_88_2_khz = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

158

limit_freq_to_174_4_khz = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

212

limit_freq_to_48_khz = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

214

limit_freq_to_88_2_khz = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

216

limit_freq_to_96_khz = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

218

limit_freq_to_174_4_khz = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

817

is_ac3_supported = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

421

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

700

bool payload_reply = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

738

(ddc->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? true : false,

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

767

(ddc->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? true : false,

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

807

payload->write_status_update = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

811

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

832

retry_on_defer = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

266

pxl_clk_params.flags.SET_DISPCLK_DFS_BYPASS = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

398

clk_mgr_dce->dfs_bypass_enabled = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

419

clk_mgr_dce->ss_on_dprefclk = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

443

clk_mgr_dce->ss_on_dprefclk = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

480

clk_mgr_dce->xgmi_enabled = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

481

clk_mgr_dce->ss_on_dprefclk = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1064

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1166

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1177

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1224

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1301

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1316

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1362

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1665

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1737

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

174

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1762

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1793

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

246

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

285

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

458

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

711

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

752

true))

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

757

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

915

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

962

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

103

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

153

if (wait == true) {

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

277

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

292

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

444

status = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

451

status = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

516

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

579

if (wait == true) {

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

720

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

75

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

763

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

788

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

811

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

852

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

875

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

900

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

922

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c.c

51

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

141

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

155

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

302

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

310

REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

315

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

376

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

400

REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

433

REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

490

pool->i2c_hw_buffer_in_use = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

620

result = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

639

result = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

113

write_bit_to_ddc(ddc_handle, SCL, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

130

write_bit_to_ddc(ddc_handle, SDA, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

134

write_bit_to_ddc(ddc_handle, SCL, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

168

write_bit_to_ddc(ddc_handle, SCL, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

197

write_bit_to_ddc(ddc_handle, SCL, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

206

write_bit_to_ddc(ddc_handle, SDA, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

210

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

231

write_bit_to_ddc(ddc_handle, SCL, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

236

write_bit_to_ddc(ddc_handle, SDA, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

242

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

268

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

291

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

30

#define SDA true

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

307

write_bit_to_ddc(ddc_handle, SCL, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

312

write_bit_to_ddc(ddc_handle, SDA, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

321

write_bit_to_ddc(ddc_handle, SCL, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

334

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

368

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

464

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

477

result = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

86

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.c

49

REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.c

75

REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

204

disable_prbs_symbols(enc110, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

221

enable_phy_bypass_mode(enc110, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

343

enable_phy_bypass_mode(enc110, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

363

enable_phy_bypass_mode(enc110, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

375

disable_prbs_symbols(enc110, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

380

enable_phy_bypass_mode(enc110, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

408

enable_phy_bypass_mode(enc110, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

454

set_link_training_complete(enc110, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

506

set_link_training_complete(enc110, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

534

set_link_training_complete(enc110, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

562

set_link_training_complete(enc110, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

759

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

794

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

804

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

947

is_valid = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

127

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

850

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

895

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

1009

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

1456

dce110_se_enable_audio_clock(enc, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

1474

dce110_se_enable_audio_clock(enc, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

945

REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1201

scl_data->taps.h_taps_c = decide_taps(scl_data->ratios.horz_c, in_taps->h_taps, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1202

scl_data->taps.v_taps_c = decide_taps(scl_data->ratios.vert_c, in_taps->v_taps, true);

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1227

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1350

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

146

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1650

xfm_dce->prescaler_on = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1679

xfm_dce->prescaler_on = true;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

175

return true;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

478

filter_updated = true;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c

112

return true;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

156

return true;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

204

return true;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

251

return true;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

276

return true;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

298

return true;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

317

return true;

sys/dev/pci/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

71

return true;

sys/dev/pci/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

74

return true;

sys/dev/pci/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

84

return true;

sys/dev/pci/drm/amd/display/dc/dce/dmub_outbox.c

49

cmd.outbox1_enable.enable = true;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

173

return true;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

429

return true;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

208

return true;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

208

compressor->is_enabled = true;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

234

wait_for_fbc_state_changed(cp110, true);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

276

return true;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

287

return true;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

427

compressor->base.options.bits.FBC_SUPPORT = true;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

480

return true;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

499

return true;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

571

const unsigned int *pte_chroma = get_dvmm_hw_setting(tiling_info, format, true);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

376

return true;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

458

return true;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

505

power_on_lut(xfm, true, false, true);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

514

power_on_lut(xfm, false, false, true);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1166

return true;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1406

return true;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

146

result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, true);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1981

return true;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2099

return true;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2135

return true;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2251

return true;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2295

return true;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

346

tg110->base.funcs->enable_advanced_request(tg, true, &patched_crtc_timing);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

187

return true;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

77

return true;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

96

return true;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c

179

is_scaling_needed = true;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c

188

is_scaling_needed = true;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c

518

return true;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c

596

filter_updated = true;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c

712

xfm_dce->prescaler_on = true;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c

716

return true;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

278

return true;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

400

compressor->is_enabled = true;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

410

wait_for_fbc_state_changed(cp110, true);

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

450

return true;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

461

return true;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

794

compressor->base.options.bits.FBC_SUPPORT = true;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

795

compressor->base.options.bits.LPT_SUPPORT = true;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

1077

return true;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

1109

return true;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

1171

return true;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

1213

return true;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

125

return true;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

151

result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, true);

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

726

return true;

sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c

202

return true;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c

234

if (fixpoint == true) {

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c

275

if (hw_points_num == 0 || rgb_resulted == NULL || fixpoint == true)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c

276

return true;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c

279

fmt.sign = true;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c

322

return true;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c

509

if (fixpoint == true) {

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c

534

return true;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c

682

return true;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.c

100

return true;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.c

54

caps->caps.support_dwb = true;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.c

56

caps->caps.support_wbscl = true;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.c

58

return true;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.c

78

return true;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c

132

return true;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c

155

return true;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c

195

return true;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c

60

caps->caps.support_dwb = true;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c

65

return true;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

797

return true;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

875

return true;

sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

177

cfg->use_calibration_setting = true;

sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

181

cfg->lane_en[i] = true;

sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

202

return true;

sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

235

return true;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c

254

if (fixpoint == true) {

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c

301

return true;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c

371

if (fixpoint == true) {

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c

431

if (hw_points_num == 0 || rgb_resulted == NULL || fixpoint == true)

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c

432

return true;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c

459

return true;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c

465

bool ret = true;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

89

REG_SET_3(MMHUBBUB_WARMUP_CONTROL_STATUS, 0, MMHUBBUB_WARMUP_EN, true,

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

90

MMHUBBUB_WARMUP_SW_INT_EN, true,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

175

disable_prbs_symbols(enc10, true);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

192

enable_phy_bypass_mode(enc10, true);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

273

enable_phy_bypass_mode(enc10, true);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

293

enable_phy_bypass_mode(enc10, true);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

305

disable_prbs_symbols(enc10, true);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

310

enable_phy_bypass_mode(enc10, true);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

338

enable_phy_bypass_mode(enc10, true);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

386

set_link_training_complete(enc10, true);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

413

set_link_training_complete(enc10, true);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

611

return true;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

652

return true;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

664

return true;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

818

is_valid = true;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1025

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1447

enc1_se_enable_audio_clock(enc, true);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1465

enc1_se_enable_audio_clock(enc, true);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1566

return true;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

952

REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

221

cfg->lane_en[i] = true;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

242

return true;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

309

pps_sdp.valid = true;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

432

if (info_frame->adaptive_sync.valid == true &&

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

433

info_frame->sdp_line_num.adaptive_sync_line_num_valid == true) {

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

547

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

341

pps_sdp.valid = true;

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

411

if (info_frame->adaptive_sync.valid == true &&

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

412

info_frame->sdp_line_num.adaptive_sync_line_num_valid == true) {

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

434

true);

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

449

true);

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

464

true);

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

471

true);

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

478

true);

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

489

true);

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

62

true);

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

752

enc1_se_enable_audio_clock(enc, true);

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

821

enc1_se_enable_audio_clock(enc, true);

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

108

return true;

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

131

return true;

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

441

return true;

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

376

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

73

enc314_reset_fifo(enc, true);

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

168

return true;

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

344

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

415

enc32_reset_fifo(enc, true);

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

291

return true;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

356

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

419

enc35_reset_fifo(enc, true);

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

371

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1166

if (dc->debug.max_disp_clk == true)

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1310

return true;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

313

input->src.is_hsplit = true;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

315

input->src.is_hsplit = true;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

516

true,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

517

true,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

644

updated = true;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

651

updated = true;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

658

updated = true;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

665

updated = true;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

673

updated = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

142

dc->debug.disable_dmcu = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1004

pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1052

return true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

106

.dcc_supported = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1213

context->bw_ctx.bw.dcn.clk.p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1242

false, false, true);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1320

bool synchronized_vblank = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1375

pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

145

.xfc_supported = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

174

.dcc_supported = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1957

bool duplicate = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

213

.xfc_supported = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2471

bw_params->wm_table.entries[WM_D].valid = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

577

.dcc_supported = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

775

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

783

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

791

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

799

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

812

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

820

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

828

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

836

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

849

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

857

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

865

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

873

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

886

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

894

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

902

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

910

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

923

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

931

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

939

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

947

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

960

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

968

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

976

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

984

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

1070

*PTEBufferSizeNotExceeded = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

1076

*PTEBufferSizeNotExceeded = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

1300

mode_lib->vba.DCCEnabledAnyPlane = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

1337

MainPlaneDoesODMCombine = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

1341

MainPlaneDoesODMCombine = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

1343

if (MainPlaneDoesODMCombine == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

1978

if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

1995

&& mode_lib->vba.WritebackEnable[j] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

2052

bool prefetch_vm_bw_valid = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

2053

bool prefetch_row_bw_valid = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

2061

if (mode_lib->vba.XFCEnabled[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

2216

DestinationLineTimesForPrefetchLessThan2 = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

2219

VRatioPrefetchMoreThan4 = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

2225

mode_lib->vba.PrefetchModeSupported = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

2232

if (mode_lib->vba.PrefetchModeSupported == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

2309

mode_lib->vba.ImmediateFlipSupported = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

2370

mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

2371

mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

2379

mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

2601

if (mode_lib->vba.XFCEnabled[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

2687

bool FirstMainPlane = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

2850

MainPlaneDoesODMCombine = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

2855

MainPlaneDoesODMCombine = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

2859

if (MainPlaneDoesODMCombine == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3053

if (DCCEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3063

if (GPUVMEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3111

*ImmediateFlipSupportedForPipe = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3116

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3153

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3184

*ImmediateFlipSupportedForPipe = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3294

mode_lib->vba.ScaleRatioAndTapsSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3329

mode_lib->vba.SourceFormatPixelAndScanSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3357

== true

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3360

|| (mode_lib->vba.DCCEnable[k] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3407

if (mode_lib->vba.WritebackEnable[k] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3414

} else if (mode_lib->vba.WritebackEnable[k] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3421

} else if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3433

if (mode_lib->vba.DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3434

mode_lib->vba.DCCEnabledInAnyPlane = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3450

if (locals->DCCEnabledInAnyPlane == true && locals->ReturnBWToDCNPerState > locals->DCFCLKPerState[i] * locals->ReturnBusWidth / 4) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3473

if (locals->DCCEnabledInAnyPlane == true && locals->ReturnBWToDCNPerState > locals->DCFCLKPerState[i] * locals->ReturnBusWidth / 4) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3495

mode_lib->vba.WritebackLatencySupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3497

if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3526

locals->ROBSupport[i][0] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3535

if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3543

mode_lib->vba.WritebackModeSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3548

if (mode_lib->vba.WritebackEnable[k] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3549

&& mode_lib->vba.Writeback10bpc420Supported != true

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3556

mode_lib->vba.WritebackScaleRatioAndTapsSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3558

if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3647

if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3880

locals->DISPCLK_DPPCLK_Support[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3955

locals->DISPCLK_DPPCLK_Support[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4000

locals->ViewportSizeSupport[i][0] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4019

locals->TotalAvailablePipesSupport[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4034

mode_lib->vba.NumberOfOTGSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4045

mode_lib->vba.NonsupportedDSCInputBPC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4081

true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4085

if (mode_lib->vba.DSCEnabled[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4086

locals->RequiresDSC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4088

locals->RequiresFEC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4110

true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4114

if (mode_lib->vba.DSCEnabled[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4115

locals->RequiresDSC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4117

locals->RequiresFEC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4141

true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4145

if (mode_lib->vba.DSCEnabled[k] == true || mode_lib->vba.Outbpp == BPP_INVALID) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4146

locals->RequiresDSC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4148

locals->RequiresFEC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4167

locals->DIOSupport[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4172

&& mode_lib->vba.Interlace[k] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4173

&& mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true))) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4191

if (locals->RequiresDSC[i][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4196

true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4202

true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4214

if (locals->RequiresDSC[i][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4225

locals->NotEnoughDSCUnits[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4256

if (locals->RequiresDSC[i][k] == true && mode_lib->vba.bpp != 0.0) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4289

if (mode_lib->vba.BlendingAndTiming[k] == m && locals->RequiresDSC[i][m] == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4386

locals->UrgentLatencySupport[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4400

if (locals->DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4577

locals->PTEBufferSizeNotExceededC[i][j][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4611

if (mode_lib->vba.GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4621

if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4638

== true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4683

if (mode_lib->vba.XFCEnabled[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4776

locals->prefetch_vm_bw_valid = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4777

locals->prefetch_row_bw_valid = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4810

locals->BandwidthWithoutPrefetchSupported[i][0] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4815

locals->PrefetchSupported[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4823

|| mode_lib->vba.IsErrorResult[i][j][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4827

locals->VRatioInPrefetchSupported[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4831

|| mode_lib->vba.IsErrorResult[i][j][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4835

} while ((locals->PrefetchSupported[i][j] != true || locals->VRatioInPrefetchSupported[i][j] != true)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4838

if (mode_lib->vba.PrefetchSupported[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4839

&& mode_lib->vba.VRatioInPrefetchSupported[i][j] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4910

mode_lib->vba.ImmediateFlipSupportedForState[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4935

mode_lib->vba.TotalVerticalActiveBandwidthSupport[i][0] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4944

locals->PTEBufferSizeNotExceeded[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4954

mode_lib->vba.CursorSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4978

mode_lib->vba.PitchSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4986

if (mode_lib->vba.DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

5021

if (mode_lib->vba.ScaleRatioAndTapsSupport != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

5023

} else if (mode_lib->vba.SourceFormatPixelAndScanSupport != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

5025

} else if (locals->ViewportSizeSupport[i][0] != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

5027

} else if (locals->DIOSupport[i] != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

5033

} else if (locals->UrgentLatencySupport[i][j] != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

5035

} else if (locals->ROBSupport[i][0] != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

5037

} else if (locals->DISPCLK_DPPCLK_Support[i][j] != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

5039

} else if (locals->TotalAvailablePipesSupport[i][j] != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

5041

} else if (mode_lib->vba.NumberOfOTGSupport != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

5043

} else if (mode_lib->vba.WritebackModeSupport != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

5045

} else if (mode_lib->vba.WritebackLatencySupport != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

5047

} else if (mode_lib->vba.WritebackScaleRatioAndTapsSupport != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

5049

} else if (mode_lib->vba.CursorSupport != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

5051

} else if (mode_lib->vba.PitchSupport != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

5053

} else if (locals->PrefetchSupported[i][j] != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

5055

} else if (locals->TotalVerticalActiveBandwidthSupport[i][0] != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

5057

} else if (locals->VRatioInPrefetchSupported[i][j] != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

5059

} else if (locals->PTEBufferSizeNotExceeded[i][j] != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

5066

locals->ModeSupport[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

5077

if (locals->ModeSupport[i][0] == true || locals->ModeSupport[i][1] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

5079

if (locals->ModeSupport[i][1] == true && (locals->ModeSupport[i][0] == false

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

529

return true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

574

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

605

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

618

if ((GPUVMEnable == true || DCCEnable == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

680

if ((GPUVMEnable == true || DCCEnable == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

734

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

756

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

776

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

783

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

895

if (DCCEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

922

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

957

if (GPUVMEnable == true && mode_lib->vba.GPUVMMaxPageTableLevels > 1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

998

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

1017

if (GPUVMEnable == true && mode_lib->vba.GPUVMMaxPageTableLevels > 1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

1058

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

1130

*PTEBufferSizeNotExceeded = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

1136

*PTEBufferSizeNotExceeded = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

1360

mode_lib->vba.DCCEnabledAnyPlane = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

1397

MainPlaneDoesODMCombine = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

1401

MainPlaneDoesODMCombine = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

1403

if (MainPlaneDoesODMCombine == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

2014

if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

2031

&& mode_lib->vba.WritebackEnable[j] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

2088

bool prefetch_vm_bw_valid = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

2089

bool prefetch_row_bw_valid = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

2097

if (mode_lib->vba.XFCEnabled[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

2250

DestinationLineTimesForPrefetchLessThan2 = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

2253

VRatioPrefetchMoreThan4 = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

2259

mode_lib->vba.PrefetchModeSupported = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

2266

if (mode_lib->vba.PrefetchModeSupported == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

2343

mode_lib->vba.ImmediateFlipSupported = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

2404

mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

2405

mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

2413

mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

2674

if (mode_lib->vba.XFCEnabled[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

2760

bool FirstMainPlane = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

2923

MainPlaneDoesODMCombine = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

2928

MainPlaneDoesODMCombine = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

2932

if (MainPlaneDoesODMCombine == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3126

if (DCCEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3136

if (GPUVMEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3184

*ImmediateFlipSupportedForPipe = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3189

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3211

if ((GPUVMEnable == true || DCCEnable == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3226

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3257

*ImmediateFlipSupportedForPipe = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3401

mode_lib->vba.ScaleRatioAndTapsSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3436

mode_lib->vba.SourceFormatPixelAndScanSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3464

== true

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3467

|| (mode_lib->vba.DCCEnable[k] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3514

if (mode_lib->vba.WritebackEnable[k] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3521

} else if (mode_lib->vba.WritebackEnable[k] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3528

} else if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3540

if (mode_lib->vba.DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3541

mode_lib->vba.DCCEnabledInAnyPlane = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3557

if (locals->DCCEnabledInAnyPlane == true && locals->ReturnBWToDCNPerState > locals->DCFCLKPerState[i] * locals->ReturnBusWidth / 4) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3580

if (locals->DCCEnabledInAnyPlane == true && locals->ReturnBWToDCNPerState > locals->DCFCLKPerState[i] * locals->ReturnBusWidth / 4) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3602

mode_lib->vba.WritebackLatencySupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3604

if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3633

locals->ROBSupport[i][0] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3642

if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3650

mode_lib->vba.WritebackModeSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3655

if (mode_lib->vba.WritebackEnable[k] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3656

&& mode_lib->vba.Writeback10bpc420Supported != true

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3663

mode_lib->vba.WritebackScaleRatioAndTapsSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3665

if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3754

if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3991

locals->DISPCLK_DPPCLK_Support[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4069

locals->DISPCLK_DPPCLK_Support[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4114

locals->ViewportSizeSupport[i][0] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4133

locals->TotalAvailablePipesSupport[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4148

mode_lib->vba.NumberOfOTGSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4159

mode_lib->vba.NonsupportedDSCInputBPC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4198

true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4202

if (mode_lib->vba.DSCEnabled[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4203

locals->RequiresDSC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4205

locals->RequiresFEC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4229

true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4233

if (mode_lib->vba.DSCEnabled[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4234

locals->RequiresDSC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4236

locals->RequiresFEC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4262

true,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4266

if (mode_lib->vba.DSCEnabled[k] == true || mode_lib->vba.Outbpp == BPP_INVALID) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4267

locals->RequiresDSC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4269

locals->RequiresFEC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4288

locals->DIOSupport[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4293

&& mode_lib->vba.Interlace[k] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4294

&& mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true))) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4312

if (locals->RequiresDSC[i][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4317

true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4323

true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4335

if (locals->RequiresDSC[i][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4346

locals->NotEnoughDSCUnits[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4377

if (locals->RequiresDSC[i][k] == true && mode_lib->vba.bpp != 0.0) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4410

if (mode_lib->vba.BlendingAndTiming[k] == m && locals->RequiresDSC[i][m] == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4503

locals->UrgentLatencySupport[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4517

if (locals->DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4699

locals->PTEBufferSizeNotExceededC[i][j][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4733

if (mode_lib->vba.GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4743

if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4760

== true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4805

if (mode_lib->vba.XFCEnabled[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4895

locals->prefetch_vm_bw_valid = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4896

locals->prefetch_row_bw_valid = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4929

locals->BandwidthWithoutPrefetchSupported[i][0] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4934

locals->PrefetchSupported[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4942

|| mode_lib->vba.IsErrorResult[i][j][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4946

locals->VRatioInPrefetchSupported[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4950

|| mode_lib->vba.IsErrorResult[i][j][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4954

} while ((locals->PrefetchSupported[i][j] != true || locals->VRatioInPrefetchSupported[i][j] != true)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4957

if (mode_lib->vba.PrefetchSupported[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4958

&& mode_lib->vba.VRatioInPrefetchSupported[i][j] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5029

mode_lib->vba.ImmediateFlipSupportedForState[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5051

mode_lib->vba.TotalVerticalActiveBandwidthSupport[i][0] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5060

locals->PTEBufferSizeNotExceeded[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5070

mode_lib->vba.CursorSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5094

mode_lib->vba.PitchSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5102

if (mode_lib->vba.DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5137

if (mode_lib->vba.ScaleRatioAndTapsSupport != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5139

} else if (mode_lib->vba.SourceFormatPixelAndScanSupport != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5141

} else if (locals->ViewportSizeSupport[i][0] != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5143

} else if (locals->DIOSupport[i] != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5149

} else if (locals->UrgentLatencySupport[i][j] != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5151

} else if (locals->ROBSupport[i][0] != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5153

} else if (locals->DISPCLK_DPPCLK_Support[i][j] != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5155

} else if (locals->TotalAvailablePipesSupport[i][j] != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5157

} else if (mode_lib->vba.NumberOfOTGSupport != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5159

} else if (mode_lib->vba.WritebackModeSupport != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5161

} else if (mode_lib->vba.WritebackLatencySupport != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5163

} else if (mode_lib->vba.WritebackScaleRatioAndTapsSupport != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5165

} else if (mode_lib->vba.CursorSupport != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5167

} else if (mode_lib->vba.PitchSupport != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5169

} else if (locals->PrefetchSupported[i][j] != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5171

} else if (locals->TotalVerticalActiveBandwidthSupport[i][0] != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5173

} else if (locals->VRatioInPrefetchSupported[i][j] != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5175

} else if (locals->PTEBufferSizeNotExceeded[i][j] != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5182

locals->ModeSupport[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5193

if (locals->ModeSupport[i][0] == true || locals->ModeSupport[i][1] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

5195

if (locals->ModeSupport[i][1] == true && (locals->ModeSupport[i][0] == false

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

521

return true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

538

return true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

637

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

665

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

678

if ((GPUVMEnable == true || DCCEnable == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

740

if ((GPUVMEnable == true || DCCEnable == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

794

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

816

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

836

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

843

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

955

if (DCCEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

982

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

113

ret_val = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

272

req128_l = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

285

req128_l = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

352

true);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

113

ret_val = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

272

req128_l = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

285

req128_l = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

352

true);

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1009

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1023

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1036

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1044

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1097

if (DCCEnabled == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1098

if (DCCProgrammingAssumesScanDirectionUnknown == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1196

*Independent64ByteBlock = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1301

if (DCCEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1328

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1363

if (GPUVMEnable == true && (mode_lib->vba.GPUVMMaxPageTableLevels + 1) * (mode_lib->vba.HostVMMaxPageTableLevels + 1) > 2) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1378

if (HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1382

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1433

*PTEBufferSizeNotExceeded = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1439

*PTEBufferSizeNotExceeded = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1443

if (HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1447

if (HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1450

} else if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1690

MainPlaneDoesODMCombine = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1694

MainPlaneDoesODMCombine = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1696

if (MainPlaneDoesODMCombine == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

2040

if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

2057

&& mode_lib->vba.WritebackEnable[j] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

2110

if (mode_lib->vba.XFCEnabled[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

2299

DestinationLineTimesForPrefetchLessThan2 = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

2301

VRatioPrefetchMoreThan4 = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

2308

mode_lib->vba.PrefetchModeSupported = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

2315

if (mode_lib->vba.PrefetchModeSupported == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

2384

mode_lib->vba.ImmediateFlipSupported = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

2563

locals->AllowDRAMClockChangeDuringVBlank[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

2564

locals->AllowDRAMSelfRefreshDuringVBlank[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

2572

locals->AllowDRAMSelfRefreshDuringVBlank[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

2607

if (mode_lib->vba.XFCEnabled[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

2774

if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

2948

MainPlaneDoesODMCombine = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

2953

MainPlaneDoesODMCombine = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

2957

if (MainPlaneDoesODMCombine == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3139

if (DCCEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3149

if (GPUVMEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3198

if (GPUVMEnable == true && HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3211

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3221

if ((GPUVMEnable == true || DCCEnable == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3231

if (GPUVMEnable == true && DCCEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3235

} else if (GPUVMEnable != true && DCCEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3247

if (GPUVMEnable == true && DCCEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3249

} else if (GPUVMEnable != true && DCCEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3263

*ImmediateFlipSupportedForPipe = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3407

if (mode_lib->vba.XFCEnabled[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3528

mode_lib->vba.ScaleRatioAndTapsSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3563

mode_lib->vba.SourceFormatPixelAndScanSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3591

== true

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3594

|| (mode_lib->vba.DCCEnable[k] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3641

if (mode_lib->vba.WritebackEnable[k] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3648

} else if (mode_lib->vba.WritebackEnable[k] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3655

} else if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3667

if (mode_lib->vba.DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3668

mode_lib->vba.DCCEnabledInAnyPlane = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3688

mode_lib->vba.WritebackLatencySupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3690

if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3722

locals->ROBSupport[i][0] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3731

if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3739

mode_lib->vba.WritebackModeSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3744

if (mode_lib->vba.WritebackEnable[k] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3745

&& mode_lib->vba.Writeback10bpc420Supported != true

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3752

mode_lib->vba.WritebackScaleRatioAndTapsSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3754

if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3843

if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4080

locals->DISPCLK_DPPCLK_Support[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4163

locals->DISPCLK_DPPCLK_Support[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4208

locals->ViewportSizeSupport[i][0] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4227

locals->TotalAvailablePipesSupport[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4242

mode_lib->vba.NumberOfOTGSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4253

mode_lib->vba.NonsupportedDSCInputBPC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4292

true,

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4296

if (mode_lib->vba.DSCEnabled[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4297

locals->RequiresDSC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4299

locals->RequiresFEC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4323

true,

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4327

if (mode_lib->vba.DSCEnabled[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4328

locals->RequiresDSC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4330

locals->RequiresFEC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4356

true,

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4360

if (mode_lib->vba.DSCEnabled[k] == true || mode_lib->vba.Outbpp == BPP_INVALID) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4361

locals->RequiresDSC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4363

locals->RequiresFEC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4382

locals->DIOSupport[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4387

&& mode_lib->vba.Interlace[k] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4388

&& mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true))) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4406

if (locals->RequiresDSC[i][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4411

true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4417

true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4429

if (locals->RequiresDSC[i][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4440

locals->NotEnoughDSCUnits[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4471

if (locals->RequiresDSC[i][k] == true && mode_lib->vba.bpp != 0.0) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4504

if (mode_lib->vba.BlendingAndTiming[k] == m && locals->RequiresDSC[i][m] == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4516

if (mode_lib->vba.DCCEnable[k] == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4649

locals->PTEBufferSizeNotExceededC[i][j][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4742

if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4759

== true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4862

locals->BandwidthWithoutPrefetchSupported[i][0] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4868

locals->PrefetchSupported[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4878

|| mode_lib->vba.IsErrorResult[i][j][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4882

locals->VRatioInPrefetchSupported[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4886

|| mode_lib->vba.IsErrorResult[i][j][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4893

mode_lib->vba.AnyLinesForVMOrRowTooLarge = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4903

} while ((locals->PrefetchSupported[i][j] != true || locals->VRatioInPrefetchSupported[i][j] != true)

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4907

if (locals->PrefetchSupported[i][j] == true && locals->VRatioInPrefetchSupported[i][j] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4967

locals->ImmediateFlipSupportedForState[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

5061

locals->TotalVerticalActiveBandwidthSupport[i][0] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

5072

locals->PTEBufferSizeNotExceeded[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

5083

mode_lib->vba.CursorSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

5095

mode_lib->vba.PitchSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

5103

if (mode_lib->vba.DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

5184

locals->ModeSupport[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

5195

if (locals->ModeSupport[i][0] == true || locals->ModeSupport[i][1] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

5197

if (locals->ModeSupport[i][1] == true && (locals->ModeSupport[i][0] == false

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

5322

if (DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

5339

if (WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

5436

if (WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

5496

} else if (((mode_lib->vba.SynchronizedVBlank == true

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

5903

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

5914

if (DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

5922

if (DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

5954

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

6013

if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

717

if (GPUVMEnable == true && myHostVM->Enable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

738

return true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

783

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

820

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

827

if ((GPUVMEnable == true || DCCEnable == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

923

if ((GPUVMEnable == true || DCCEnable == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

973

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

995

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

256

req128_l = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

269

req128_l = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

342

true);

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

88

ret_val = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

107

.dynamic_metadata_vm_enabled = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

116

.odm_combine_4to1_supported = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

175

.do_urgent_latency_adjustment = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

343

DC_VALIDATE_MODE_AND_PROGRAMMING, true);

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

635

DC_VALIDATE_MODE_AND_PROGRAMMING, true);

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

669

base->bw_params->wm_table.nv_entries[WM_A].valid = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

691

base->bw_params->wm_table.nv_entries[WM_C].valid = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

710

base->bw_params->wm_table.nv_entries[WM_D].valid = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

73

.dcc_supported = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1059

Case1OK = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1070

Case2OK = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1081

Case3OK = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1155

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1170

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1179

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1199

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1213

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1222

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1463

if (DCCProgrammingAssumesScanDirectionUnknown == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1541

if (DCCEnabled != true || BytePerPixelC == 0) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1547

if (DCCEnabled != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1650

if (GPUVMEnable == true && HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1675

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1683

if (DCCEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1698

if (GPUVMEnable == true && mode_lib->vba.GPUVMMaxPageTableLevels > 1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1713

if (HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1755

*PTEBufferSizeNotExceeded = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1760

if (GPUVMEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1762

*PTEBufferSizeNotExceeded = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1766

if (HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1770

if (HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1773

} else if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1810

if (v->HostVMEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

2297

if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

2311

&& v->WritebackEnable[j] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

2521

DestinationLineTimesForPrefetchLessThan2 = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

2523

VRatioPrefetchMoreThan4 = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

2524

if (v->NoUrgentLatencyHiding[k] == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

2525

v->NotEnoughUrgentLatencyHiding[0][0] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

2527

if (v->NoUrgentLatencyHidingPre[k] == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

2528

v->NotEnoughUrgentLatencyHidingPre = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

2536

v->PrefetchModeSupported = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

2545

if (v->PrefetchModeSupported == true && v->ImmediateFlipSupport == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

2617

v->ImmediateFlipSupported = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

2639

v->PrefetchModeSupported = (v->PrefetchModeSupported == true && ((!v->ImmediateFlipSupport &&

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

2641

v->ImmediateFlipSupported)) ? true : false;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

2709

if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

2842

v->AllowDRAMClockChangeDuringVBlank[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

2843

v->AllowDRAMSelfRefreshDuringVBlank[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

2851

v->AllowDRAMSelfRefreshDuringVBlank[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

2903

v->FirstMainPlane = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

2908

if (v->FirstMainPlane == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3230

if (DCCEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3240

if (GPUVMEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3289

if (GPUVMEnable == true && HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3297

if (GPUVMEnable == true || DCCEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3301

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3309

if ((GPUVMEnable == true || DCCEnable == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3318

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3321

} else if ((GPUVMEnable == true || DCCEnable == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3329

if (GPUVMEnable == true && DCCEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3331

} else if (GPUVMEnable != true && DCCEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3338

if (GPUVMEnable == true && DCCEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3340

} else if (GPUVMEnable != true && DCCEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3351

*ImmediateFlipSupportedForPipe = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3453

bool EnoughWritebackUnits = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3454

bool WritebackModeSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3473

v->ScaleRatioAndTapsSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3516

v->SourceFormatPixelAndScanSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3518

if ((v->SurfaceTiling[k] == dm_sw_linear && (!(v->SourceScan[k] != dm_vert) || v->DCCEnable[k] == true))

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3553

if (v->WritebackEnable[k] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3560

} else if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3573

v->WritebackLatencySupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3575

if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3597

if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3618

v->WritebackScaleRatioAndTapsSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3620

if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3650

if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3726

true,

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3770

v->DISPCLK_DPPCLK_Support[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3838

&& v->SingleDPPViewportSizeSupportPerPlane[k] == true))) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3843

v->MPCCombine[i][j][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3873

v->MPCCombine[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3883

v->DISPCLK_DPPCLK_Support[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3887

v->MPCCombine[i][j][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3924

v->TotalAvailablePipesSupport[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3937

v->NonsupportedDSCInputBPC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3984

if (v->DSCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3985

v->RequiresDSC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3986

v->LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3988

v->RequiresFEC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4057

v->RequiresDSC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4058

v->LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4060

v->RequiresFEC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4089

v->DIOSupport[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4093

|| (v->OutputFormat[k] == dm_420 && v->Interlace[k] == true && v->ProgressiveToInterlaceUnitInOPP == true))) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4100

v->ODMCombine4To1SupportCheckOK[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4115

if (v->RequiresDSC[i][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4126

v->NotEnoughDSCUnits[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4138

if (v->RequiresDSC[i][k] == true && v->BPP != 0.0) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4173

if (v->BlendingAndTiming[k] == m && v->RequiresDSC[i][m] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4262

if (v->DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4333

v->PTEBufferSizeNotExceededC[i][j][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4439

v->NotUrgentLatencyHiding[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4489

if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4504

if (v->BlendingAndTiming[m] == k && v->WritebackEnable[m] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4550

if (v->UseMinimumRequiredDCFCLK == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4571

if (v->HostVMEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4587

v->ROBSupport[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4608

v->TotalVerticalActiveBandwidthSupport[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4623

v->BandwidthWithoutPrefetchSupported[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4772

if (v->NoUrgentLatencyHidingPre[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4773

v->NotEnoughUrgentLatencyHidingPre = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4777

v->PrefetchSupported[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4784

|| v->NoTimeForPrefetch[i][j][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4789

v->DynamicMetadataSupported[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4791

if (v->NoTimeForDynamicMetadata[i][j][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4796

v->VRatioInPrefetchSupported[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4798

if (v->VRatioPreY[i][j][k] > 4.0 || v->VRatioPreC[i][j][k] > 4.0 || v->NoTimeForPrefetch[i][j][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4805

v->AnyLinesForVMOrRowTooLarge = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4809

if (v->PrefetchSupported[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4874

v->ImmediateFlipSupportedForState[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4892

} while (!((v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4894

|| v->ImmediateFlipSupportedForState[i][j] == true))

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4963

v->PTEBufferSizeNotExceeded[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4973

v->CursorSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4983

v->PitchSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4986

if (v->DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4994

if (v->DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

5011

ViewportExceedsSurface = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

5016

ViewportExceedsSurface = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

5035

|| v->ImmediateFlipSupportedForState[i][j] == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

5036

v->ModeSupport[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

5045

if (i == v->soc.num_states || v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

5047

v->ModeIsSupported = v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

5048

if (v->ModeSupport[i][1] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

5151

if (DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

5162

if (WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

5218

if (WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

5267

} else if (((mode_lib->vba.SynchronizedVBlank == true || mode_lib->vba.TotalNumberOfActiveOTG == 1 || SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank > 0) && PrefetchMode == 0)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

5625

if (DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

5677

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

5740

if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

5910

if (DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

5945

if (WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

5957

if (SynchronizedVBlank == true || NumberOfActivePlanes == 1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

5963

if (SynchronizedVBlank == true || NumberOfActivePlanes == 1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

6062

*ViewportSizeSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

6163

ViewportSizeSupportPerPlane[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

6239

if (ForceSingleDPP == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

6335

if (GPUVMEnable == true && HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

6351

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

6372

if (DoUrgentLatencyAdjustment == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

6389

NormalEfficiency = (v->HostVMEnable == true ? v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

6391

PTEEfficiency = (v->HostVMEnable == true ? v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

6421

DPTEBandwidth = (v->HostVMEnable == true || v->ImmediateFlipRequirement[0] == dm_immediate_flip_required) ?

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

6444

DynamicMetadataVMExtraLatency[k] = (v->GPUVMEnable == true && v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true) ?

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

6445

v->UrgLatency[i] * v->GPUVMMaxPageTableLevels * (v->HostVMEnable == true ? v->HostVMMaxNonCachedPageTableLevels + 1 : 1) : 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

6447

: v->GPUVMMaxPageTableLevels - 2) * (v->HostVMEnable == true ? v->HostVMMaxNonCachedPageTableLevels + 1 : 1) - 1) - DynamicMetadataVMExtraLatency[k];

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

6454

if (v->HostVMEnable == true || v->ImmediateFlipRequirement[0] == dm_immediate_flip_required) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

6461

if (v->DynamicMetadataEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

6498

MinimumTvmPlus2Tr0 = v->UrgLatency[i] * (v->GPUVMEnable == true ? (v->HostVMEnable == true ?

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

855

if (v->GPUVMEnable == true && v->HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

884

if (v->DynamicMetadataVMEnabled == true && v->GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

890

if (v->DynamicMetadataEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

892

*NotEnoughTimeForDynamicMetadata = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

905

v->Tdmdl_vm[k] = (v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true && v->GPUVMEnable == true ? TWait + Tvm_trips : 0);

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

917

return true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

959

if (v->GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

966

if ((v->GPUVMEnable == true || myPipe->DCCEnable == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1203

visited[j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

200

req128_l = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

206

req128_c = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

213

req128_l = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

217

req128_l = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

225

req128_c = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

103

.odm_combine_4to1_supported = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

226

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

234

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

242

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

250

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

263

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

271

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

279

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

287

.valid = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

60

.dcc_supported = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

94

.dynamic_metadata_vm_enabled = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

104

.odm_combine_4to1_supported = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

163

.do_urgent_latency_adjustment = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

61

.dcc_supported = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

95

.dynamic_metadata_vm_enabled = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

162

.do_urgent_latency_adjustment = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

60

.dcc_supported = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

94

.dynamic_metadata_vm_enabled = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

117

.dcc_supported = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

224

.is_line_buffer_bpp_fixed = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

262

.dcc_supported = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

323

.is_line_buffer_bpp_fixed = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

361

.dcc_supported = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

571

context->bw_ctx.bw.dcn.clk.p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

79

.is_line_buffer_bpp_fixed = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1079

if (GPUVMEnable == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1084

if ((GPUVMEnable == true || myPipe->DCCEnable == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1199

Case1OK = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1210

Case2OK = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1221

Case3OK = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1247

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1253

if ((GPUVMEnable == true || myPipe->DCCEnable == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1320

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1346

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1372

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1399

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1422

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1439

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1645

if (DCCProgrammingAssumesScanDirectionUnknown == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1720

if (DCCEnabled != true || BytePerPixelC == 0) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1726

if (DCCEnabled != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1837

if (GPUVMEnable == true && HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1859

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1867

if (DCCEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1882

if (GPUVMEnable == true && v->GPUVMMaxPageTableLevels > 1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1912

if (HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1954

*PTEBufferSizeNotExceeded = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1959

if (GPUVMEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1961

*PTEBufferSizeNotExceeded = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1966

if (HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1970

if (HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1973

} else if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1992

bool NoChromaPlanes = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

2008

if (v->HostVMEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

2503

if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

2517

if (v->BlendingAndTiming[j] == k && v->WritebackEnable[j] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

2782

DestinationLineTimesForPrefetchLessThan2 = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

2785

VRatioPrefetchMoreThan4 = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

2787

if (v->NoUrgentLatencyHiding[k] == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

2788

v->NoEnoughUrgentLatencyHiding = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

2790

if (v->NoUrgentLatencyHidingPre[k] == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

2791

v->NoEnoughUrgentLatencyHidingPre = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

2804

v->PrefetchModeSupported = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

2817

if (v->ErrorResult[k] == true || v->NotEnoughTimeForDynamicMetadata[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

2823

if (v->PrefetchModeSupported == true && v->ImmediateFlipSupport == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

2880

v->ImmediateFlipSupported = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

2902

(v->PrefetchModeSupported == true && ((!v->ImmediateFlipSupport && !v->HostVMEnable

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

2904

v->ImmediateFlipSupported)) ? true : false;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

2962

if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3084

v->AllowDRAMClockChangeDuringVBlank[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3085

v->AllowDRAMSelfRefreshDuringVBlank[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3091

v->AllowDRAMSelfRefreshDuringVBlank[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3163

v->VREADY_AT_OR_AFTER_VSYNC[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3188

if (v->WritebackEnable[k] == true && v->WritebackPixelFormat[k] == dm_444_32) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3191

} else if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3464

if (DCCEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3472

if (GPUVMEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3500

if (v->GPUVMEnable == true && v->HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3506

if (v->GPUVMEnable == true || v->DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3510

if (v->GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3520

if ((v->GPUVMEnable == true || v->DCCEnable[k] == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3531

if (v->GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3535

} else if ((v->GPUVMEnable == true || v->DCCEnable[k] == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3542

if (v->GPUVMEnable == true && v->DCCEnable[k] != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3544

} else if (v->GPUVMEnable != true && v->DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3554

if (v->GPUVMEnable == true && v->DCCEnable[k] != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3556

} else if (v->GPUVMEnable != true && v->DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3567

v->ImmediateFlipSupportedForPipe[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3793

bool NoChroma = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3794

bool EnoughWritebackUnits = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3810

v->ScaleRatioAndTapsSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3837

v->SourceFormatPixelAndScanSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3839

if ((v->SurfaceTiling[k] == dm_sw_linear && (!(v->SourceScan[k] != dm_vert) || v->DCCEnable[k] == true))

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3876

if (v->WritebackEnable[k] == true && v->WritebackPixelFormat[k] == dm_444_64) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3879

} else if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3889

v->WritebackLatencySupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3891

if (v->WritebackEnable[k] == true && (v->WriteBandwidth[k] > v->WritebackInterfaceBufferSize * 1024 / v->WritebackLatency)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3900

if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3911

v->WritebackScaleRatioAndTapsSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3913

if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3932

if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4019

true,

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4064

v->DISPCLK_DPPCLK_Support[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4099

FMTBufferExceeded = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4127

FMTBufferExceeded = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4133

FMTBufferExceeded = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4149

<= v->MaxDppclkRoundedDownToDFSGranularity && v->SingleDPPViewportSizeSupportPerPlane[k] == true))) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4154

v->MPCCombine[i][j][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4165

v->MPCCombine[i][j][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4195

v->MPCCombine[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4206

v->DISPCLK_DPPCLK_Support[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4210

v->MPCCombine[i][j][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4251

v->TotalAvailablePipesSupport[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4263

v->NonsupportedDSCInputBPC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4310

if (v->DSCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4311

v->RequiresDSC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4312

v->LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4314

v->RequiresFEC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4322

v->RequiresFEC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4347

v->DSCEnable[k] == true && v->ForcedOutputLinkBPP[k] == 0) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4348

v->RequiresDSC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4349

v->LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4389

v->DSCEnable[k] == true && v->ForcedOutputLinkBPP[k] == 0) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4390

v->RequiresDSC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4391

v->LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4430

if (v->Outbpp == BPP_INVALID && v->DSCEnable[k] == true &&

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4432

v->RequiresDSC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4433

v->LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4525

v->LinkCapacitySupport[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4542

if (v->OutputFormat[k] == dm_420 && v->Interlace[k] == 1 && v->ProgressiveToInterlaceUnitInOPP == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4543

P2IWith420 = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4545

if (v->DSCEnable[k] == true && v->OutputFormat[k] == dm_n422

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4547

DSC422NativeNotSupported = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4553

v->ODMCombine4To1SupportCheckOK[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4569

if (v->RequiresDSC[i][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4580

v->NotEnoughDSCUnits[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4592

if (v->RequiresDSC[i][k] == true && v->BPP != 0.0) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4627

if (v->BlendingAndTiming[k] == m && v->RequiresDSC[i][m] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4743

if (v->DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4816

v->PTEBufferSizeNotExceededC[i][j][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4892

v->DCCMetaBufferSizeSupport[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4932

v->NotEnoughUrgentLatencyHidingA[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4960

if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4975

if (v->BlendingAndTiming[m] == k && v->WritebackEnable[m] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5031

if (v->UseMinimumRequiredDCFCLK == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5047

if (v->HostVMEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5060

v->ROBSupport[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5085

v->TotalVerticalActiveBandwidthSupport[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5112

v->BandwidthWithoutPrefetchSupported[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5222

if (v->NotUrgentLatencyHidingPre[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5223

v->NotEnoughUrgentLatencyHidingPre = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5227

v->PrefetchSupported[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5234

|| v->NoTimeForPrefetch[i][j][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5239

v->DynamicMetadataSupported[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5241

if (v->NoTimeForDynamicMetadata[i][j][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5246

v->VRatioInPrefetchSupported[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5248

if (v->VRatioPreY[i][j][k] > 4.0 || v->VRatioPreC[i][j][k] > 4.0 || v->NoTimeForPrefetch[i][j][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5255

v->AnyLinesForVMOrRowTooLarge = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5261

if (v->PrefetchSupported[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5307

v->ImmediateFlipSupportedForState[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5327

} while (!((v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5330

|| v->ImmediateFlipSupportedForState[i][j] == true))

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5376

v->PTEBufferSizeNotExceeded[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5386

v->CursorSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5396

v->PitchSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5399

if (v->DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5408

if (v->DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5427

ViewportExceedsSurface = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5433

ViewportExceedsSurface = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5442

if (v->ScaleRatioAndTapsSupport == true && v->SourceFormatPixelAndScanSupport == true && v->ViewportSizeSupport[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5443

&& v->LinkCapacitySupport[i] == true && !P2IWith420 && !DSCOnlyIfNecessaryWithBPP

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5444

&& !DSC422NativeNotSupported && v->ODMCombine4To1SupportCheckOK[i] == true && v->NotEnoughDSCUnits[i] == false

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5446

&& v->ROBSupport[i][j] == true && v->DISPCLK_DPPCLK_Support[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5447

&& v->TotalAvailablePipesSupport[i][j] == true && EnoughWritebackUnits == true

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5448

&& v->WritebackLatencySupport == true && v->WritebackScaleRatioAndTapsSupport == true

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5449

&& v->CursorSupport == true && v->PitchSupport == true && ViewportExceedsSurface == false

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5450

&& v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5451

&& v->TotalVerticalActiveBandwidthSupport[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5452

&& v->PTEBufferSizeNotExceeded[i][j] == true && v->NonsupportedDSCInputBPC == false

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5455

|| v->ImmediateFlipSupportedForState[i][j] == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5457

v->ModeSupport[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5471

if (v->NotEnoughDSCUnits[i] == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5473

if (v->DTBCLKRequiredMoreThanSupported[i] == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5491

if (ViewportExceedsSurface == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5503

if (v->NonsupportedDSCInputBPC == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5507

|| v->ImmediateFlipSupportedForState[i][j] == true))

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5509

if (FMTBufferExceeded == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5519

if (i == v->soc.num_states || v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5521

v->ModeIsSupported = v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5522

if (v->ModeSupport[i][0] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5604

if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5680

if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

5728

} else if ((v->SynchronizedVBlank == true || v->TotalNumberOfActiveOTG == 1

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

6106

if (DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

6158

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

6221

if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

6388

if (DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

6465

LinesInDETY = (DETBufferSizeY[k] + (UnboundedRequestEnabled == true ? EffectiveCompressedBufferSize : 0) * ReadBandwidthPlaneLuma[k] / TotalDataReadBandwidth)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

6697

*ViewportSizeSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

6789

ViewportSizeSupportPerPlane[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

6875

if (ForceSingleDPP == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

6985

if (GPUVMEnable == true && HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

6999

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

7019

if (DoUrgentLatencyAdjustment == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

7064

DPTEBandwidth = (v->HostVMEnable == true || v->ImmediateFlipRequirement[0] == dm_immediate_flip_required) ?

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

7102

(v->GPUVMEnable == true && v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true) ?

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

7103

v->UrgLatency[i] * v->GPUVMMaxPageTableLevels * (v->HostVMEnable == true ? v->HostVMMaxNonCachedPageTableLevels + 1 : 1) : 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

7107

* (v->HostVMEnable == true ? v->HostVMMaxNonCachedPageTableLevels + 1 : 1) - 1)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

7116

if (v->HostVMEnable == true || v->ImmediateFlipRequirement[0] == dm_immediate_flip_required) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

7123

if (v->DynamicMetadataEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

7165

* (v->GPUVMEnable == true ?

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

7166

(v->HostVMEnable == true ?

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

7202

*UnboundedRequestEnabled == true ?

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

917

if (GPUVMEnable == true && HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

950

if (DynamicMetadataVMEnabled == true && GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

952

if (DynamicMetadataVMEnabled == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

965

if (DynamicMetadataEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

967

*NotEnoughTimeForDynamicMetadata = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

980

*Tdmdl_vm = (DynamicMetadataEnable == true && DynamicMetadataVMEnabled == true && GPUVMEnable == true ? TWait + Tvm_trips : 0);

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

992

return true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1075

visited[j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

353

upscaled = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

364

pipes[pipe_cnt].pipe.src.immediate_flip = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

399

dc->config.enable_4to1MPC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

403

pipes[0].pipe.src.unbounded_req_mode = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

413

context->bw_ctx.dml.ip.odm_combine_4to1_supported = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

60

.is_line_buffer_bpp_fixed = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

98

.dcc_supported = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1010

return true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1097

if (GPUVMEnable == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1102

if ((GPUVMEnable == true || myPipe->DCCEnable == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1217

Case1OK = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1228

Case2OK = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1239

Case3OK = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1265

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1271

if ((GPUVMEnable == true || myPipe->DCCEnable == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1338

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1364

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1390

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1416

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1439

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1456

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1662

if (DCCProgrammingAssumesScanDirectionUnknown == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1737

if (DCCEnabled != true || BytePerPixelC == 0) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1743

if (DCCEnabled != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1854

if (GPUVMEnable == true && HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1876

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1884

if (DCCEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1899

if (GPUVMEnable == true && v->GPUVMMaxPageTableLevels > 1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1929

if (HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1971

*PTEBufferSizeNotExceeded = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1976

if (GPUVMEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1978

*PTEBufferSizeNotExceeded = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1983

if (HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1987

if (HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1990

} else if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

2009

bool NoChromaPlanes = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

2026

if (v->HostVMEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

2522

if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

2536

if (v->BlendingAndTiming[j] == k && v->WritebackEnable[j] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

2801

DestinationLineTimesForPrefetchLessThan2 = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

2804

VRatioPrefetchMoreThan4 = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

2806

if (v->NoUrgentLatencyHiding[k] == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

2807

v->NoEnoughUrgentLatencyHiding = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

2809

if (v->NoUrgentLatencyHidingPre[k] == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

2810

v->NoEnoughUrgentLatencyHidingPre = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

2823

v->PrefetchModeSupported = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

2836

if (v->ErrorResult[k] == true || v->NotEnoughTimeForDynamicMetadata[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

2842

if (v->PrefetchModeSupported == true && v->ImmediateFlipSupport == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

2899

v->ImmediateFlipSupported = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

2920

(v->PrefetchModeSupported == true && ((!v->ImmediateFlipSupport && !v->HostVMEnable

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

2922

v->ImmediateFlipSupported)) ? true : false;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

2981

if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3103

v->AllowDRAMClockChangeDuringVBlank[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3104

v->AllowDRAMSelfRefreshDuringVBlank[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3110

v->AllowDRAMSelfRefreshDuringVBlank[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3181

v->VREADY_AT_OR_AFTER_VSYNC[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3207

if (v->WritebackEnable[k] == true && v->WritebackPixelFormat[k] == dm_444_32) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3210

} else if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3448

return true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3570

if (DCCEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3578

if (GPUVMEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3606

if (v->GPUVMEnable == true && v->HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3612

if (v->GPUVMEnable == true || v->DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3616

if (v->GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3626

if ((v->GPUVMEnable == true || v->DCCEnable[k] == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3637

if (v->GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3641

} else if ((v->GPUVMEnable == true || v->DCCEnable[k] == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3648

if (v->GPUVMEnable == true && v->DCCEnable[k] != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3650

} else if (v->GPUVMEnable != true && v->DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3660

if (v->GPUVMEnable == true && v->DCCEnable[k] != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3662

} else if (v->GPUVMEnable != true && v->DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3673

v->ImmediateFlipSupportedForPipe[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3886

bool NoChroma = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3887

bool EnoughWritebackUnits = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3903

v->ScaleRatioAndTapsSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3930

v->SourceFormatPixelAndScanSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3932

if (v->SurfaceTiling[k] == dm_sw_linear && (!(v->SourceScan[k] != dm_vert) || v->DCCEnable[k] == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3967

if (v->WritebackEnable[k] == true && v->WritebackPixelFormat[k] == dm_444_64) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3970

} else if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3980

v->WritebackLatencySupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3982

if (v->WritebackEnable[k] == true && (v->WriteBandwidth[k] > v->WritebackInterfaceBufferSize * 1024 / v->WritebackLatency)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3991

if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4002

v->WritebackScaleRatioAndTapsSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4004

if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4023

if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4110

true,

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4154

v->DISPCLK_DPPCLK_Support[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4189

FMTBufferExceeded = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4217

FMTBufferExceeded = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4223

FMTBufferExceeded = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4239

<= v->MaxDppclkRoundedDownToDFSGranularity && v->SingleDPPViewportSizeSupportPerPlane[k] == true))) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4244

v->MPCCombine[i][j][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4282

v->MPCCombine[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4293

v->DISPCLK_DPPCLK_Support[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4297

v->MPCCombine[i][j][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4338

v->TotalAvailablePipesSupport[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4350

v->NonsupportedDSCInputBPC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4397

if (v->DSCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4398

v->RequiresDSC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4399

v->LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4401

v->RequiresFEC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4409

v->RequiresFEC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4434

v->DSCEnable[k] == true && v->ForcedOutputLinkBPP[k] == 0) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4435

v->RequiresDSC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4436

v->LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4476

v->DSCEnable[k] == true && v->ForcedOutputLinkBPP[k] == 0) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4477

v->RequiresDSC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4478

v->LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4517

if (v->Outbpp == BPP_INVALID && v->DSCEnable[k] == true &&

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4519

v->RequiresDSC[i][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4520

v->LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4612

v->LinkCapacitySupport[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4629

if (v->OutputFormat[k] == dm_420 && v->Interlace[k] == 1 && v->ProgressiveToInterlaceUnitInOPP == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4630

P2IWith420 = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4632

if (v->DSCEnable[k] == true && v->OutputFormat[k] == dm_n422

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4634

DSC422NativeNotSupported = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4641

v->ODMCombine4To1SupportCheckOK[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4657

if (v->RequiresDSC[i][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4668

v->NotEnoughDSCUnits[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4680

if (v->RequiresDSC[i][k] == true && v->BPP != 0.0) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4716

if (v->BlendingAndTiming[k] == m && v->RequiresDSC[i][m] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4829

if (v->DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4902

v->PTEBufferSizeNotExceededC[i][j][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4980

v->DCCMetaBufferSizeSupport[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5020

v->NotEnoughUrgentLatencyHidingA[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5048

if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5063

if (v->BlendingAndTiming[m] == k && v->WritebackEnable[m] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5117

if (v->UseMinimumRequiredDCFCLK == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5133

if (v->HostVMEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5146

v->ROBSupport[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5171

v->TotalVerticalActiveBandwidthSupport[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5198

v->BandwidthWithoutPrefetchSupported[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5308

if (v->NotUrgentLatencyHidingPre[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5309

v->NotEnoughUrgentLatencyHidingPre = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5313

v->PrefetchSupported[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5320

|| v->NoTimeForPrefetch[i][j][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5325

v->DynamicMetadataSupported[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5327

if (v->NoTimeForDynamicMetadata[i][j][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5332

v->VRatioInPrefetchSupported[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5334

if (v->VRatioPreY[i][j][k] > 4.0 || v->VRatioPreC[i][j][k] > 4.0 || v->NoTimeForPrefetch[i][j][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5341

v->AnyLinesForVMOrRowTooLarge = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5347

if (v->PrefetchSupported[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5393

v->ImmediateFlipSupportedForState[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5413

} while (!((v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5416

|| v->ImmediateFlipSupportedForState[i][j] == true))

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5462

v->PTEBufferSizeNotExceeded[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5472

v->CursorSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5482

v->PitchSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5485

if (v->DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5494

if (v->DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5513

ViewportExceedsSurface = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5519

ViewportExceedsSurface = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5528

if (v->ScaleRatioAndTapsSupport == true && v->SourceFormatPixelAndScanSupport == true && v->ViewportSizeSupport[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5529

&& v->LinkCapacitySupport[i] == true && !P2IWith420 && !DSCOnlyIfNecessaryWithBPP

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5530

&& !DSC422NativeNotSupported && v->ODMCombine4To1SupportCheckOK[i] == true && v->NotEnoughDSCUnits[i] == false

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5532

&& v->ROBSupport[i][j] == true && v->DISPCLK_DPPCLK_Support[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5533

&& v->TotalAvailablePipesSupport[i][j] == true && EnoughWritebackUnits == true

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5534

&& v->WritebackLatencySupport == true && v->WritebackScaleRatioAndTapsSupport == true

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5535

&& v->CursorSupport == true && v->PitchSupport == true && ViewportExceedsSurface == false

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5536

&& v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5537

&& v->TotalVerticalActiveBandwidthSupport[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5538

&& v->PTEBufferSizeNotExceeded[i][j] == true && v->NonsupportedDSCInputBPC == false

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5541

|| v->ImmediateFlipSupportedForState[i][j] == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5543

v->ModeSupport[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5613

if (i == v->soc.num_states || v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5615

v->ModeIsSupported = v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5616

if (v->ModeSupport[i][0] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5698

if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5774

if (v->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

5822

} else if ((v->SynchronizedVBlank == true || v->TotalNumberOfActiveOTG == 1

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

6201

if (DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

6253

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

6316

if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

6483

if (DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

6560

LinesInDETY = (DETBufferSizeY[k] + (UnboundedRequestEnabled == true ? EffectiveCompressedBufferSize : 0) * ReadBandwidthPlaneLuma[k] / TotalDataReadBandwidth)

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

6791

*ViewportSizeSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

6880

ViewportSizeSupportPerPlane[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

6965

if (ForceSingleDPP == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

7075

if (GPUVMEnable == true && HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

7088

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

7107

if (DoUrgentLatencyAdjustment == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

7150

DPTEBandwidth = (v->HostVMEnable == true || v->ImmediateFlipRequirement[0] == dm_immediate_flip_required) ?

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

7188

(v->GPUVMEnable == true && v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true) ?

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

7189

v->UrgLatency[i] * v->GPUVMMaxPageTableLevels * (v->HostVMEnable == true ? v->HostVMMaxNonCachedPageTableLevels + 1 : 1) : 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

7193

* (v->HostVMEnable == true ? v->HostVMMaxNonCachedPageTableLevels + 1 : 1) - 1)

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

7203

if (v->HostVMEnable == true || v->ImmediateFlipRequirement[0] == dm_immediate_flip_required) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

7210

if (v->DynamicMetadataEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

7252

* (v->GPUVMEnable == true ?

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

7253

(v->HostVMEnable == true ?

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

7290

*UnboundedRequestEnabled == true ?

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

935

if (GPUVMEnable == true && HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

968

if (DynamicMetadataVMEnabled == true && GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

970

if (DynamicMetadataVMEnabled == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

983

if (DynamicMetadataEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

985

*NotEnoughTimeForDynamicMetadata = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

998

*Tdmdl_vm = (DynamicMetadataEnable == true && DynamicMetadataVMEnabled == true && GPUVMEnable == true ? TWait + Tvm_trips : 0);

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1162

visited[j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

117

return true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1018

result = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1077

schedulable = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

121

.dcc_supported = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1248

updated = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1260

updated = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1390

return true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1431

return true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1539

found_supported_config = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1597

return true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1608

return true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1680

context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1735

context->res_ctx.pipe_ctx[i].has_vactive_margin = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1774

context->bw_ctx.bw.dcn.clk.p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1775

context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

178

.do_urgent_latency_adjustment = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1871

return true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1880

return true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1934

return true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1951

*repopulate_pipes = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2010

*repopulate_pipes = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2026

*repopulate_pipes = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2072

newly_split[hsplit_pipe->pipe_idx] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2073

*repopulate_pipes = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2093

newly_split[pipe_4to1->pipe_idx] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

211

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2112

newly_split[pipe_4to1->pipe_idx] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2135

return true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2170

out = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

223

clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2278

flags_valid = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2291

out = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2332

pstate_en = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2333

is_subvp_p_drr = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2342

need_fclk_lat_as_dummy = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

236

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2371

stream_status->fpo_in_use = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2372

context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2390

need_fclk_lat_as_dummy = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2400

pstate_en = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

257

clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3410

allow = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3471

allow = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3564

bool vactive_found = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

652

valid_assignment_found = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

708

subvp_possible = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

778

return true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

82

.dsc422_native_support = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

829

subvp_found = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

83

.is_line_buffer_bpp_fixed = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

845

drr_found = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

879

schedulable = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

937

found = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

968

schedulable = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1001

if (v->PrefetchModeSupported == true && mode_lib->vba.ImmediateFlipSupport == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1137

v->PrefetchAndImmediateFlipSupported = (v->PrefetchModeSupported == true &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1139

v->ImmediateFlipSupported)) ? true : false;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1236

if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1458

v->VREADY_AT_OR_AFTER_VSYNC[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1482

if (mode_lib->vba.WritebackEnable[k] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1488

} else if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1660

if (mode_lib->vba.ScaleRatioAndTapsSupport == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1661

&& mode_lib->vba.SourceFormatPixelAndScanSupport == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1662

&& mode_lib->vba.ViewportSizeSupport[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1670

&& mode_lib->vba.LinkCapacitySupport[i] == true && !mode_lib->vba.P2IWith420

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1674

&& mode_lib->vba.ODMCombine2To1SupportCheckOK[i] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1675

&& mode_lib->vba.ODMCombine4To1SupportCheckOK[i] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1685

&& mode_lib->vba.ROBSupport[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1686

&& mode_lib->vba.DISPCLK_DPPCLK_Support[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1687

&& mode_lib->vba.TotalAvailablePipesSupport[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1688

&& mode_lib->vba.NumberOfOTGSupport == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1689

&& mode_lib->vba.NumberOfHDMIFRLSupport == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1690

&& mode_lib->vba.EnoughWritebackUnits == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1691

&& mode_lib->vba.WritebackLatencySupport == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1692

&& mode_lib->vba.WritebackScaleRatioAndTapsSupport == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1693

&& mode_lib->vba.CursorSupport == true && mode_lib->vba.PitchSupport == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1695

&& mode_lib->vba.PrefetchSupported[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1696

&& mode_lib->vba.VActiveBandwithSupport[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1697

&& mode_lib->vba.DynamicMetadataSupported[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1698

&& mode_lib->vba.TotalVerticalActiveBandwidthSupport[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1699

&& mode_lib->vba.VRatioInPrefetchSupported[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1700

&& mode_lib->vba.PTEBufferSizeNotExceeded[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1701

&& mode_lib->vba.DCCMetaBufferSizeNotExceeded[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1716

mode_lib->vba.ModeSupport[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1747

mode_lib->vba.ScaleRatioAndTapsSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1793

mode_lib->vba.SourceFormatPixelAndScanSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1797

|| mode_lib->vba.DCCEnable[k] == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1840

if (mode_lib->vba.WritebackEnable[k] == true && mode_lib->vba.WritebackPixelFormat[k] == dm_444_64) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1845

} else if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1857

mode_lib->vba.WritebackLatencySupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1859

if (mode_lib->vba.WritebackEnable[k] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1868

mode_lib->vba.EnoughWritebackUnits = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1871

if (mode_lib->vba.WritebackEnable[k] == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1879

mode_lib->vba.WritebackScaleRatioAndTapsSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1881

if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1926

mode_lib->vba.DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2026

v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MPCCombineMethodAsNeededForPStateChangeAndVoltage = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2028

v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MPCCombineMethodAsPossible = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2036

mode_lib->vba.TotalAvailablePipesSupport[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2072

true,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2151

mode_lib->vba.SingleDPPViewportSizeSupportPerSurface[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2155

mode_lib->vba.MPCCombine[i][j][k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2167

v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.NoChroma = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2217

true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2306

mode_lib->vba.NonsupportedDSCInputBPC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2313

if (mode_lib->vba.OutputMultistreamEn[k] == true && mode_lib->vba.OutputMultistreamId[k] == k) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2320

mode_lib->vba.ExceededMultistreamSlots[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2322

mode_lib->vba.ExceededMultistreamSlots[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2325

mode_lib->vba.LinkCapacitySupport[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2358

mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2359

mode_lib->vba.P2IWith420 = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2362

mode_lib->vba.DSCOnlyIfNecessaryWithBPP = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2365

mode_lib->vba.DSC422NativeNotSupported = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2375

mode_lib->vba.LinkRateDoesNotMatchDPVersion = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2377

if (mode_lib->vba.OutputMultistreamEn[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2380

mode_lib->vba.LinkRateForMultistreamNotIndicated = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2382

mode_lib->vba.BPPForMultistreamNotIndicated = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2386

mode_lib->vba.BPPForMultistreamNotIndicated = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2391

if (mode_lib->vba.OutputMultistreamEn[k] == true && mode_lib->vba.OutputMultistreamId[k] == k)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2392

mode_lib->vba.MultistreamWithHDMIOreDP = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2394

if (mode_lib->vba.OutputMultistreamEn[k] == true && mode_lib->vba.OutputMultistreamId[k] == j)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2395

mode_lib->vba.MultistreamWithHDMIOreDP = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2403

mode_lib->vba.MSOOrODMSplitWithNonDPLink = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2409

mode_lib->vba.NotEnoughLanesForMSO = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2425

mode_lib->vba.DTBCLKRequiredMoreThanSupported[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2431

mode_lib->vba.ODMCombine2To1SupportCheckOK[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2432

mode_lib->vba.ODMCombine4To1SupportCheckOK[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2463

if (mode_lib->vba.RequiresDSC[i][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2467

mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2471

mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2474

mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2489

mode_lib->vba.PixelsPerLinePerDSCUnitSupport[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2491

if (mode_lib->vba.RequiresDSC[i][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2498

mode_lib->vba.NotEnoughDSCSlices[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2505

mode_lib->vba.NotEnoughDSCSlices[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2511

mode_lib->vba.NotEnoughDSCSlices[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2516

mode_lib->vba.NotEnoughDSCUnits[i] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2536

mode_lib->vba.RequiresDSC[i][m] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2708

if (mode_lib->vba.DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2841

mode_lib->vba.PTEBufferSizeNotExceeded[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2847

mode_lib->vba.DCCMetaBufferSizeNotExceeded[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2916

if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2934

== k && mode_lib->vba.WritebackEnable[m] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3020

((mode_lib->vba.HostVMEnable == true || mode_lib->vba.ImmediateFlipRequirement[k] !=

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3044

v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.FullFrameMALLPStateMethod = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3046

v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SubViewportMALLPStateMethod = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3048

v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.PhantomPipeMALLPStateMethod = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3053

if (mode_lib->vba.UseMinimumRequiredDCFCLK == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3129

mode_lib->vba.ROBSupport[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3159

mode_lib->vba.TotalVerticalActiveBandwidthSupport[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3407

|| mode_lib->vba.NoTimeForPrefetch[i][j][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3412

mode_lib->vba.DynamicMetadataSupported[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3414

if (mode_lib->vba.NoTimeForDynamicMetadata[i][j][k] == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3418

mode_lib->vba.VRatioInPrefetchSupported[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3422

|| mode_lib->vba.NoTimeForPrefetch[i][j][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3430

mode_lib->vba.AnyLinesForVMOrRowTooLarge = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3434

if (mode_lib->vba.PrefetchSupported[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3435

&& mode_lib->vba.VRatioInPrefetchSupported[i][j] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3554

} while (!((mode_lib->vba.PrefetchSupported[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3555

&& mode_lib->vba.DynamicMetadataSupported[i][j] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3556

&& mode_lib->vba.VRatioInPrefetchSupported[i][j] == true &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3562

|| mode_lib->vba.ImmediateFlipSupportedForState[i][j] == true))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3620

mode_lib->vba.CursorSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3629

mode_lib->vba.PitchSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3634

if (mode_lib->vba.DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3649

if (mode_lib->vba.DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3673

mode_lib->vba.ViewportExceedsSurface = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3682

mode_lib->vba.ViewportExceedsSurface = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3694

if (i == v->soc.num_states || mode_lib->vba.ModeSupport[i][0] == true ||

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3695

mode_lib->vba.ModeSupport[i][1] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3697

mode_lib->vba.ModeIsSupported = mode_lib->vba.ModeSupport[i][0] == true

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3698

|| mode_lib->vba.ModeSupport[i][1] == true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

3700

if (mode_lib->vba.ModeSupport[i][0] == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

601

if (mode_lib->vba.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

616

mode_lib->vba.WritebackEnable[j] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

900

DestinationLineTimesForPrefetchLessThan2 = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

904

VRatioPrefetchMoreThanMax = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

996

if (v->ErrorResult[k] == true || v->NotEnoughTimeForDynamicMetadata[k]) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1038

DETPieceAssignedToThisSurfaceAlready[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1042

DETPieceAssignedToThisSurfaceAlready[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1079

NextPotentialSurfaceToAssignDETPieceFound = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1161

DETPieceAssignedToThisSurfaceAlready[NextSurfaceToAssignDETPiece] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1218

*TotalAvailablePipesSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1386

if (DSCEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1387

*RequiresDSC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1388

LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1390

*RequiresFEC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1397

*RequiresFEC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1410

if (*OutBpp == 0 && PHYCLKD32PerState < 13500.0 / 32 && DSCEnable == true &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1412

*RequiresDSC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1413

LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1433

if (*OutBpp == 0 && PHYCLKD32PerState < 20000 / 32 && DSCEnable == true &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1435

*RequiresDSC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1436

LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1455

if (*OutBpp == 0 && DSCEnable == true && ForcedOutputLinkBPP == 0) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1456

*RequiresDSC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1457

LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1478

if (*OutBpp == 0 && PHYCLKPerState < 540 && DSCEnable == true &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1480

*RequiresDSC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1481

LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1483

*RequiresFEC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1503

if (*OutBpp == 0 && PHYCLKPerState < 810 && DSCEnable == true &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1505

*RequiresDSC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1506

LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1508

*RequiresFEC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1529

if (*OutBpp == 0 && DSCEnable == true && ForcedOutputLinkBPP == 0) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1530

*RequiresDSC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1531

LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1533

*RequiresFEC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1704

if (DSCEnable != true)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1732

if (DSCEnabled == true && OutputBpp != 0) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1832

if (DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1876

if (DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

192

is_vert = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1993

if (HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1996

} else if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

2161

PTEBufferSizeNotExceeded[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

2212

DCCMetaBufferSizeNotExceeded[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

2317

if (GPUVMEnable == true && HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

2363

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

2372

if (DCCEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

2380

if (GPUVMEnable == true && GPUVMMaxPageTableLevels > 1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

2421

if (HostVMEnable == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

2510

if (GPUVMEnable != true)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

2512

if (HostVMEnable == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

2635

CanAddAnotherSurfaceToMALL = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

2645

CanAddAnotherSurfaceToMALL = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

2654

UsesMALLForStaticScreen[SurfaceToAddToMALL] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

2685

if (DCCEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

2695

if (GPUVMEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

2718

if (DoUrgentLatencyAdjustment == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3041

DynamicMetadataVMExtraLatency[k] = (GPUVMEnable == true &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3042

DynamicMetadataEnable[k] == true && DynamicMetadataVMEnabled == true) ?

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3044

(HostVMEnable == true ? HostVMMaxNonCachedPageTableLevels + 1 : 1) : 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3058

GPUVMMaxPageTableLevels - 2) * (HostVMEnable == true ?

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3073

if (HostVMEnable == true || ImmediateFlipRequirement == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3082

if (DynamicMetadataEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3126

MinimumTvmPlus2Tr0 = UrgLatency[i] * (GPUVMEnable == true ?

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3127

(HostVMEnable == true ? (GPUVMMaxPageTableLevels + 2) *

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3170

if (GPUVMEnable == true && HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3184

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3303

if (HostVMEnable != true)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3488

if (v->GPUVMEnable == true && v->HostVMEnable == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3525

if (v->DynamicMetadataVMEnabled == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3535

if (v->DynamicMetadataEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3537

*NotEnoughTimeForDynamicMetadata = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3555

*Tdmdl_vm = (v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3556

v->GPUVMEnable == true ? TWait + Tvm_trips : 0);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3568

return true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3608

if (v->GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3614

} else if (v->GPUVMMaxPageTableLevels == 1 && myPipe->DCCEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3621

} else if (myPipe->DCCEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3649

if (v->GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3657

if ((v->GPUVMEnable == true || myPipe->DCCEnable == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3811

Case1OK = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3824

Case2OK = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3837

Case3OK = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3862

if (v->GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3870

if ((v->GPUVMEnable == true || myPipe->DCCEnable == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3915

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3964

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3991

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

4017

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

4042

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

4070

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

4092

MyError = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

4154

if (GPUVMEnable == true && HostVMEnable == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

4172

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

4181

if ((GPUVMEnable == true || DCCEnable == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

4194

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

4199

} else if ((GPUVMEnable == true || DCCEnable == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

4214

if (GPUVMEnable == true && DCCEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

4217

} else if (GPUVMEnable != true && DCCEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

4226

if (GPUVMEnable == true && DCCEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

4228

} else if (GPUVMEnable != true && DCCEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

4241

*ImmediateFlipSupportedForPipe = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

4355

if (v->WritebackEnable[k] == true)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

4501

SynchronizedSurfaces[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

4512

FoundFirstSurfaceWithMinActiveFCLKChangeMargin = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

4520

SameTimingForFCLKChange = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

4542

*USRRetrainingSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

470

bool NoChromaSurfaces = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

4957

if (DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

5020

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

5192

if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

5488

if (DCCProgrammingAssumesScanDirectionUnknown == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

5564

if (DCCEnabled != true || BytePerPixelC == 0) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

5570

if (DCCEnabled != true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

5661

bool SameTiming = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

5698

if (DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

5838

+ (UnboundedRequestEnabled == true ? EffectiveCompressedBufferSize : 0)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

5864

FoundCriticalSurface = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

595

*ViewportSizeSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

6129

NotEnoughUrgentLatencyHiding = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

6184

NotEnoughUrgentLatencyHiding = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

6343

NotEnoughDETSwathFillLatencyHiding = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

639

ViewportSizeSupportPerSurface[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

782

if (ForceSingleDPP == true) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

324

visited[j] = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

100

.dcc_supported = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

157

.do_urgent_latency_adjustment = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

61

.dsc422_native_support = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

62

.is_line_buffer_bpp_fixed = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

112

.dcc_supported = true,

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

491

upscaled = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

499

pipes[pipe_cnt].pipe.src.immediate_flip = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

537

dc->config.enable_4to1MPC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

545

pipes[0].pipe.src.unbounded_req_mode = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

63

.dsc422_native_support = true,/*delta from false*/

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

64

.is_line_buffer_bpp_fixed = true,/*new*/

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

42

.dsc422_native_support = true,/*delta from false*/

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

43

.is_line_buffer_bpp_fixed = true,/*new*/

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

524

upscaled = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

532

pipes[pipe_cnt].pipe.src.immediate_flip = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

570

dc->config.enable_4to1MPC = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

578

pipes[0].pipe.src.unbounded_req_mode = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

91

.dcc_supported = true,

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

1045

return true;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

1056

&& mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true) {

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

390

mode_lib->vba.WritebackLumaAndChromaScalingSupported = true;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

393

mode_lib->vba.Cursor64BppSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

542

visited[j] = true;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

809

visited[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

828

mode_lib->vba.ImmediateFlipSupport = true;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

847

PlaneVisited[j] = true;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

849

PlaneVisited[k] = true;

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

855

PlaneVisited[j] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1040

if (p->GPUVMEnable == true && p->HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1081

if (p->DynamicMetadataVMEnabled == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1093

if (p->DynamicMetadataEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1095

*p->NotEnoughTimeForDynamicMetadata = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1108

*p->Tdmdl_vm = (p->DynamicMetadataEnable == true && p->DynamicMetadataVMEnabled == true && p->GPUVMEnable == true ? p->TWait + s->Tvm_trips : 0);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1120

return true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1156

if (p->GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1161

} else if (p->GPUVMPageTableLevels == 1 && p->myPipe->DCCEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1167

} else if (p->myPipe->DCCEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1198

if (p->GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1206

if ((p->GPUVMEnable == true || p->myPipe->DCCEnable == true)) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1346

Case1OK = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1356

Case2OK = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1366

Case3OK = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1392

if (p->GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1398

if ((p->GPUVMEnable == true || p->myPipe->DCCEnable == true)) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1457

s->MyError = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1480

s->MyError = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1505

s->MyError = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1523

s->MyError = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1555

s->MyError = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1572

s->MyError = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1925

if (DCCEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1935

if (GPUVMEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1986

if (GPUVMEnable == true && HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2005

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2012

if ((GPUVMEnable == true || DCCEnable == true)) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2021

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2024

} else if ((GPUVMEnable == true || DCCEnable == true)) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2038

if (GPUVMEnable == true && DCCEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2040

} else if (GPUVMEnable != true && DCCEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2046

if (GPUVMEnable == true && DCCEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2048

} else if (GPUVMEnable != true && DCCEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2058

*ImmediateFlipSupportedForPipe = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2277

if (DCCProgrammingAssumesScanDirectionUnknown == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2352

if (DCCEnabled != true || BytePerPixelC == 0) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2358

if (DCCEnabled != true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2535

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2543

if (DCCEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2559

if (GPUVMEnable == true && GPUVMMaxPageTableLevels > 1) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2669

if (GPUVMEnable != true)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2700

if (display_cfg->timing.Interlace[k] == 1 && ptoi_supported == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2854

if (p->WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2960

*p->USRRetrainingSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2971

s->FoundCriticalSurface = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2984

s->SynchronizedSurfaces[i][j] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3508

if (DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3560

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3683

if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3799

dml_bool_t SameTiming = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3815

if (p->DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3905

LinesInDETY = ((dml_float_t)p->DETBufferSizeY[k] + (p->UnboundedRequestEnabled == true ? EffectiveCompressedBufferSize : 0) * p->ReadBandwidthSurfaceLuma[k] / p->TotalDataReadBandwidth) / p->BytePerPixelDETY[k] / p->SwathWidthY[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3926

FoundCriticalSurface = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4098

dml_bool_t NoChromaOrLinearSurfaces = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4214

*p->ViewportSizeSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4249

p->ViewportSizeSupportPerSurface[k] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4369

SwathWidthY[k] = (dml_uint_t)(dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 4.0 * HRatio[k], true)));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4371

SwathWidthY[k] = (dml_uint_t)(dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 2.0 * HRatio[k], true)));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4395

if (ForceSingleDPP == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4549

if (GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4569

if (DoUrgentLatencyAdjustment == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4586

if (DSCEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4630

s->DynamicMetadataVMExtraLatency[k] = (p->GPUVMEnable == true && p->DynamicMetadataEnable[k] == true && p->DynamicMetadataVMEnabled == true) ? p->UrgLatency * p->GPUVMMaxPageTableLevels * (p->HostVMEnable == true ? p->HostVMMaxNonCachedPageTableLevels + 1 : 1) : 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4641

PrefetchTime = (p->MaximumVStartup[j][k] - 1) * p->HTotal[k] / p->PixelClock[k] - s->MinimumTWait - p->UrgLatency * ((p->GPUVMMaxPageTableLevels <= 2 ? p->GPUVMMaxPageTableLevels : p->GPUVMMaxPageTableLevels - 2) * (p->HostVMEnable == true ? p->HostVMMaxNonCachedPageTableLevels + 1 : 1) - 1) - s->DynamicMetadataVMExtraLatency[k];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4647

if (p->HostVMEnable == true || p->ImmediateFlipRequirement == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4653

if (p->DynamicMetadataEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4694

s->MinimumTvmPlus2Tr0 = p->UrgLatency * (p->GPUVMEnable == true ? (p->HostVMEnable == true ? (p->GPUVMMaxPageTableLevels + 2) * (p->HostVMMaxNonCachedPageTableLevels + 1) - 1 : p->GPUVMMaxPageTableLevels + 1) : 0);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4772

if (DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4789

if (DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4931

DETPieceAssignedToThisSurfaceAlready[k] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4933

DETPieceAssignedToThisSurfaceAlready[k] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4959

NextPotentialSurfaceToAssignDETPieceFound = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4980

((ForceSingleDPP ? 1 : DPPPerSurface[NextSurfaceToAssignDETPiece]) * ConfigReturnBufferSegmentSizeInkByte), true)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5000

DETPieceAssignedToThisSurfaceAlready[NextSurfaceToAssignDETPiece] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5060

if (p->HostVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5063

} else if (p->GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5222

p->PTEBufferSizeNotExceeded[k] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5288

p->DCCMetaBufferSizeNotExceeded[k] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5391

*RequiresDSC = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5392

LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5394

*RequiresFEC = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5402

*RequiresFEC = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5413

*RequiresDSC = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5414

LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5427

*RequiresDSC = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5428

LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5440

*RequiresDSC = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5441

LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5455

*RequiresDSC = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5456

LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5458

*RequiresFEC = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5472

*RequiresDSC = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5473

LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5475

*RequiresFEC = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5489

*RequiresDSC = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5490

LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5492

*RequiresFEC = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5538

*TotalAvailablePipesSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5742

CanAddAnotherSurfaceToMALL = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5749

CanAddAnotherSurfaceToMALL = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5755

UsesMALLForStaticScreen[SurfaceToAddToMALL] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5814

if (HostVMEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5851

if (HostVMEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5885

if (DSCEnabled == true && OutputBpp != 0) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5938

NotEnoughUrgentLatencyHiding = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5988

NotEnoughUrgentLatencyHiding = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6342

s->AllPrefetchModeTested = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6350

s->AllPrefetchModeTested = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6481

|| mode_lib->ms.support.NoTimeForPrefetch[j][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6486

mode_lib->ms.support.DynamicMetadataSupported[j] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6488

if (mode_lib->ms.support.NoTimeForDynamicMetadata[j][k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6493

mode_lib->ms.support.VRatioInPrefetchSupported[j] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6495

if (mode_lib->ms.support.NoTimeForPrefetch[j][k] == true ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6507

s->AnyLinesForVMOrRowTooLarge = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6511

if (mode_lib->ms.support.PrefetchSupported[j] == true && mode_lib->ms.support.VRatioInPrefetchSupported[j] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6625

} while (!((mode_lib->ms.support.PrefetchSupported[j] == true && mode_lib->ms.support.DynamicMetadataSupported[j] == true &&

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6626

mode_lib->ms.support.VRatioInPrefetchSupported[j] == true &&

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6629

((s->ImmediateFlipRequiredFinal) || mode_lib->ms.support.ImmediateFlipSupportedForState[j] == true)) ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6746

mode_lib->ms.support.ScaleRatioAndTapsSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6785

mode_lib->ms.support.SourceFormatPixelAndScanSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6787

if (mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[k] == dml_sw_linear && (!(!dml_is_vertical_rotation(mode_lib->ms.cache_display_cfg.plane.SourceScan[k])) || mode_lib->ms.cache_display_cfg.surface.DCCEnable[k] == true)) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6827

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6834

} else if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6846

mode_lib->ms.support.WritebackLatencySupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6848

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true &&

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6857

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6868

mode_lib->ms.support.WritebackScaleRatioAndTapsSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6870

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6917

} else if (dml_is_vertical_rotation(mode_lib->ms.cache_display_cfg.plane.SourceScan[k]) && mode_lib->ms.BytePerPixelY[k] == 8 && mode_lib->ms.cache_display_cfg.surface.DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7037

s->MPCCombineMethodAsNeededForPStateChangeAndVoltage = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7039

s->MPCCombineMethodAsPossible = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7045

mode_lib->ms.support.TotalAvailablePipesSupport[j] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7079

true, // DSCEnable

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7151

mode_lib->ms.SingleDPPViewportSizeSupportPerSurface[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7155

mode_lib->ms.MPCCombine[j][k] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7166

s->NoChromaOrLinear = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7194

mode_lib->ms.MPCCombine[j][s->NumberOfNonCombinedSurfaceOfMaximumBandwidth] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7282

mode_lib->ms.support.NonsupportedDSCInputBPC = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7295

mode_lib->ms.support.ExceededMultistreamSlots = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7297

mode_lib->ms.support.ExceededMultistreamSlots = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7300

mode_lib->ms.support.LinkCapacitySupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7322

if (mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_420 && mode_lib->ms.cache_display_cfg.timing.Interlace[k] == 1 && mode_lib->ms.ip.ptoi_supported == true)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7323

mode_lib->ms.support.P2IWith420 = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7326

mode_lib->ms.support.DSCOnlyIfNecessaryWithBPP = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7328

mode_lib->ms.support.DSC422NativeNotSupported = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7334

mode_lib->ms.support.LinkRateDoesNotMatchDPVersion = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7338

mode_lib->ms.support.LinkRateForMultistreamNotIndicated = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7340

mode_lib->ms.support.BPPForMultistreamNotIndicated = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7343

mode_lib->ms.support.BPPForMultistreamNotIndicated = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7349

mode_lib->ms.support.MultistreamWithHDMIOreDP = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7352

mode_lib->ms.support.MultistreamWithHDMIOreDP = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7357

mode_lib->ms.support.MSOOrODMSplitWithNonDPLink = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7361

mode_lib->ms.support.NotEnoughLanesForMSO = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7379

mode_lib->ms.support.DTBCLKRequiredMoreThanSupported = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7383

mode_lib->ms.support.ODMCombineTwoToOneSupportCheckOK = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7384

mode_lib->ms.support.ODMCombineFourToOneSupportCheckOK = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7414

if (mode_lib->ms.RequiresDSC[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7422

mode_lib->ms.support.DSCCLKRequiredMoreThanSupported = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7426

mode_lib->ms.support.DSCCLKRequiredMoreThanSupported = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7430

mode_lib->ms.support.DSCCLKRequiredMoreThanSupported = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7445

mode_lib->ms.support.PixelsPerLinePerDSCUnitSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7447

if (mode_lib->ms.RequiresDSC[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7453

mode_lib->ms.support.NotEnoughDSCSlices = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7459

mode_lib->ms.support.NotEnoughDSCSlices = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7465

mode_lib->ms.support.NotEnoughDSCSlices = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7470

mode_lib->ms.support.NotEnoughDSCUnits = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7491

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == m && mode_lib->ms.RequiresDSC[m] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7641

if (mode_lib->ms.cache_display_cfg.surface.DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7765

mode_lib->ms.support.PTEBufferSizeNotExceeded[j] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7778

mode_lib->ms.support.DCCMetaBufferSizeNotExceeded[j] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7847

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7861

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[m] == k && mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[m] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7925

mode_lib->ms.support.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe || ((mode_lib->ms.cache_display_cfg.plane.HostVMEnable == true || mode_lib->ms.policy.ImmediateFlipRequirement[k] != dml_immediate_flip_not_required) &&

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7942

s->FullFrameMALLPStateMethod = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7944

s->SubViewportMALLPStateMethod = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7946

s->SubViewportMALLRefreshGreaterThan120Hz = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7949

s->PhantomPipeMALLPStateMethod = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7954

if (mode_lib->ms.policy.UseMinimumRequiredDCFCLK == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8028

mode_lib->ms.support.ROBSupport[j] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8049

mode_lib->ms.support.TotalVerticalActiveBandwidthSupport[j] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8062

mode_lib->ms.support.CursorSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8072

mode_lib->ms.support.PitchSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8077

if (mode_lib->ms.cache_display_cfg.surface.DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8089

if (mode_lib->ms.cache_display_cfg.surface.DCCEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8107

mode_lib->ms.support.ViewportExceedsSurface = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8111

mode_lib->ms.support.ViewportExceedsSurface = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8132

if (mode_lib->ms.support.ScaleRatioAndTapsSupport == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8133

&& mode_lib->ms.support.SourceFormatPixelAndScanSupport == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8134

&& mode_lib->ms.support.ViewportSizeSupport[j] == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8142

&& mode_lib->ms.support.LinkCapacitySupport == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8147

&& mode_lib->ms.support.ODMCombineTwoToOneSupportCheckOK == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8148

&& mode_lib->ms.support.ODMCombineFourToOneSupportCheckOK == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8158

&& mode_lib->ms.support.ROBSupport[j] == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8159

&& mode_lib->ms.support.DISPCLK_DPPCLK_Support[j] == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8160

&& mode_lib->ms.support.TotalAvailablePipesSupport[j] == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8161

&& mode_lib->ms.support.NumberOfOTGSupport == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8162

&& mode_lib->ms.support.NumberOfHDMIFRLSupport == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8163

&& mode_lib->ms.support.NumberOfDP2p0Support == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8164

&& mode_lib->ms.support.EnoughWritebackUnits == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8165

&& mode_lib->ms.support.WritebackLatencySupport == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8166

&& mode_lib->ms.support.WritebackScaleRatioAndTapsSupport == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8167

&& mode_lib->ms.support.CursorSupport == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8168

&& mode_lib->ms.support.PitchSupport == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8170

&& mode_lib->ms.support.PrefetchSupported[j] == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8171

&& mode_lib->ms.support.VActiveBandwithSupport[j] == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8172

&& mode_lib->ms.support.DynamicMetadataSupported[j] == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8173

&& mode_lib->ms.support.TotalVerticalActiveBandwidthSupport[j] == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8174

&& mode_lib->ms.support.VRatioInPrefetchSupported[j] == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8175

&& mode_lib->ms.support.PTEBufferSizeNotExceeded[j] == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8176

&& mode_lib->ms.support.DCCMetaBufferSizeNotExceeded[j] == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8180

&& s->dram_clock_change_support == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8181

&& s->f_clock_change_support == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8184

mode_lib->ms.support.ModeSupport[j] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8194

if (mode_lib->ms.support.ModeSupport[0] == true || mode_lib->ms.support.ModeSupport[1] == true) { // if the mode is supported by either no combine or mpccombine

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8195

mode_lib->ms.support.ModeIsSupported = mode_lib->ms.support.ModeSupport[0] == true || mode_lib->ms.support.ModeSupport[1] == true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8198

if ((mode_lib->ms.support.ModeSupport[0] == false && mode_lib->ms.support.ModeSupport[1] == true) || s->MPCCombineMethodAsPossible ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8827

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8843

&& mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[j] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8948

s->AllPrefetchModeTested = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9110

s->DestinationLineTimesForPrefetchLessThan2 = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9116

s->VRatioPrefetchMoreThanMax = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9204

if (locals->NoTimeToPrefetch[k] == true || locals->NotEnoughTimeForDynamicMetadata[k]) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9212

if (locals->PrefetchModeSupported == true && mode_lib->ms.support.ImmediateFlipSupport == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9356

locals->PrefetchAndImmediateFlipSupported = (locals->PrefetchModeSupported == true &&

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9358

locals->ImmediateFlipSupported)) ? true : false;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9484

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9714

locals->VREADY_AT_OR_AFTER_VSYNC[k] = true;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9739

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true && mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[k] == dml_444_32) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9742

} else if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

358

dml_print("DML: MODE SUPPORT: Mode Supported : %s\n", mode_lib->ms.support.ModeSupport[j] == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

359

dml_print("DML: MODE SUPPORT: Scale Ratio And Taps : %s\n", mode_lib->ms.support.ScaleRatioAndTapsSupport == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

360

dml_print("DML: MODE SUPPORT: Source Format Pixel And Scan : %s\n", mode_lib->ms.support.SourceFormatPixelAndScanSupport == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

361

dml_print("DML: MODE SUPPORT: Viewport Size : %s\n", mode_lib->ms.support.ViewportSizeSupport[j] == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

369

dml_print("DML: MODE SUPPORT: LinkCapacitySupport : %s\n", mode_lib->ms.support.LinkCapacitySupport == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

374

dml_print("DML: MODE SUPPORT: ODMCombineTwoToOneSupportCheckOK : %s\n", mode_lib->ms.support.ODMCombineTwoToOneSupportCheckOK == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

375

dml_print("DML: MODE SUPPORT: ODMCombineFourToOneSupportCheckOK : %s\n", mode_lib->ms.support.ODMCombineFourToOneSupportCheckOK == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

381

dml_print("DML: MODE SUPPORT: PixelsPerLinePerDSCUnitSupport : %s\n", mode_lib->ms.support.PixelsPerLinePerDSCUnitSupport == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

385

dml_print("DML: MODE SUPPORT: ROB Support : %s\n", mode_lib->ms.support.ROBSupport[j] == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

386

dml_print("DML: MODE SUPPORT: DISPCLK DPPCLK Support : %s\n", mode_lib->ms.support.DISPCLK_DPPCLK_Support[j] == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

387

dml_print("DML: MODE SUPPORT: Total Available Pipes Support : %s\n", mode_lib->ms.support.TotalAvailablePipesSupport[j] == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

388

dml_print("DML: MODE SUPPORT: Number Of OTG Support : %s\n", mode_lib->ms.support.NumberOfOTGSupport == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

389

dml_print("DML: MODE SUPPORT: Number Of DP2p0 Support : %s\n", mode_lib->ms.support.NumberOfDP2p0Support == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

390

dml_print("DML: MODE SUPPORT: Writeback Latency Support : %s\n", mode_lib->ms.support.WritebackLatencySupport == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

391

dml_print("DML: MODE SUPPORT: Writeback Scale Ratio And Taps Support : %s\n", mode_lib->ms.support.WritebackScaleRatioAndTapsSupport == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

392

dml_print("DML: MODE SUPPORT: Cursor Support : %s\n", mode_lib->ms.support.CursorSupport == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

393

dml_print("DML: MODE SUPPORT: Pitch Support : %s\n", mode_lib->ms.support.PitchSupport == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

395

dml_print("DML: MODE SUPPORT: Prefetch Supported : %s\n", mode_lib->ms.support.PrefetchSupported[j] == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

396

dml_print("DML: MODE SUPPORT: VActive Bandwith Support : %s\n", mode_lib->ms.support.VActiveBandwithSupport[j] == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

397

dml_print("DML: MODE SUPPORT: Dynamic Metadata Supported : %s\n", mode_lib->ms.support.DynamicMetadataSupported[j] == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

398

dml_print("DML: MODE SUPPORT: Total Vertical Active Bandwidth Support : %s\n", mode_lib->ms.support.TotalVerticalActiveBandwidthSupport[j] == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

399

dml_print("DML: MODE SUPPORT: VRatio In Prefetch Supported : %s\n", mode_lib->ms.support.VRatioInPrefetchSupported[j] == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

400

dml_print("DML: MODE SUPPORT: PTE Buffer Size Not Exceeded : %s\n", mode_lib->ms.support.PTEBufferSizeNotExceeded[j] == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

401

dml_print("DML: MODE SUPPORT: DCC Meta Buffer Size Not Exceeded : %s\n", mode_lib->ms.support.DCCMetaBufferSizeNotExceeded[j] == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

405

dml_print("DML: MODE SUPPORT: dram clock change support : %s\n", mode_lib->scratch.dml_core_mode_support_locals.dram_clock_change_support == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

406

dml_print("DML: MODE SUPPORT: f_clock change support : %s\n", mode_lib->scratch.dml_core_mode_support_locals.f_clock_change_support == true ? "Supported" : "NOT Supported");

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

706

is_vert = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

21

pmo_options->disable_dyn_odm_for_multi_stream = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

22

pmo_options->disable_dyn_odm_for_stream_with_svp = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

246

output->output_disabled = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

279

stream_desc->overrides.disable_dynamic_odm = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

556

} else if ((plane_state->ctx->dc->config.use_spl == true) &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

563

plane->composition.scaler_info.enabled = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

568

if (plane_state->ctx->dc->debug.always_scale == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

569

plane->composition.scaler_info.enabled = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

602

plane->tdlut.setup_for_tdlut = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

656

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

739

dml_dispcfg->minimize_det_reallocation = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

740

dml_dispcfg->overrides.enable_subvp_implicit_pmo = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

743

dml_dispcfg->overrides.hw.force_unbounded_requesting.enable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

763

dml_ctx->v21.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[disp_cfg_stream_location] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

784

dml_ctx->v21.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[disp_cfg_plane_location] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

798

dml_dispcfg->overrides.all_streams_blanked = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

801

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

874

dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[i] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

876

dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[i] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

189

ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

205

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

367

phantoms_added = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

47

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

215

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

219

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

263

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

277

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

294

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

35

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

46

dml_ctx->config.pmo.force_pstate_method_enable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

463

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

78

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c

152

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c

207

svp_expanded_display_cfg->overrides.hw.force_unbounded_requesting.enable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c

295

programming->stream_programming[stream_index].phantom_stream.enabled = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c

369

programming->plane_programming[main_plane_index].phantom_plane.valid = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c

61

.dsc422_native_support = true,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c

62

.dcc_supported = true,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c

642

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c

65

.cursor_64bpp_support = true,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c

659

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10063

bool SameTiming = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10070

if (p->display_cfg->plane_descriptors[k].surface.dcc.enable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10167

l->LinesInDETY = ((double)p->DETBufferSizeY[k] + (p->UnboundedRequestEnabled == true ? l->EffectiveCompressedBufferSize : 0) * p->ReadBandwidthSurfaceLuma[k] / p->TotalDataReadBandwidth) / p->BytePerPixelDETY[k] / p->SwathWidthY[k];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10185

FoundCriticalSurface = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

1096

MinimizeReallocationSuccess = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11312

mode_lib->mp.PrefetchModeSupported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11314

if (mode_lib->mp.NoTimeToPrefetch[k] == true ||

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11323

s->DestinationLineTimesForPrefetchLessThan2 = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11327

s->VRatioPrefetchMoreThanMax = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11339

if (s->VRatioPrefetchMoreThanMax == true || s->DestinationLineTimesForPrefetchLessThan2 == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11349

if (mode_lib->mp.PrefetchModeSupported == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11465

if (mode_lib->mp.PrefetchModeSupported == true) { // prefetch schedule and prefetch bw ok, now check flip bw

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11598

mode_lib->mp.PrefetchAndImmediateFlipSupported = (mode_lib->mp.PrefetchModeSupported == true && (!must_support_iflip || mode_lib->mp.ImmediateFlipSupported));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

1174

DETPieceAssignedToThisSurfaceAlready[k] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

1176

DETPieceAssignedToThisSurfaceAlready[k] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11882

mode_lib->mp.VREADY_AT_OR_AFTER_VSYNC[k] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

1198

NextPotentialSurfaceToAssignDETPieceFound = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12153

ret_val = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

1223

DETPieceAssignedToThisSurfaceAlready[l->NextSurfaceToAssignDETPiece] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12738

fams2_global_config->features.bits.enable_stall_recovery = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12794

base_programming->config.bits.min_ttu_vblank_usable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12815

base_programming->config.bits.clamp_vtotal_min = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12825

base_programming->config.bits.clamp_vtotal_min = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12840

sub_programming->drr.only_stretch_if_required = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12868

base_programming->config.bits.clamp_vtotal_min = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12903

out->valid = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13308

out->informative.misc.ROBUrgencyAvoidance = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13313

out->informative.misc.ROBUrgencyAvoidance = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

1630

if (p->GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

1673

if (p->GPUVMEnable == true && p->GPUVMMaxPageTableLevels > 1) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

1734

if (p->GPUVMEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

1799

if (p->GPUVMEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

1931

if (GPUVMEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

1968

CanAddAnotherSurfaceToMALL = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

1975

CanAddAnotherSurfaceToMALL = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

1981

is_using_mall_for_ss[SurfaceToAddToMALL] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2168

if (DCCProgrammingAssumesScanDirectionUnknown == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2243

if (DCCEnabled != true || BytePerPixelC == 0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2249

if (DCCEnabled != true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

239

is_phantom = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2871

if (p->display_cfg->gpuvm_enable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3048

p->PTEBufferSizeNotExceeded[k] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3097

p->DCCMetaBufferSizeNotExceeded[k] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3118

p->DCCMetaBufferSizeNotExceeded[k] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3204

if (DoUrgentLatencyAdjustment == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3701

bool NoChromaOrLinear = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3803

*p->ViewportSizeSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3874

p->ViewportSizeSupportPerSurface[k] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3928

*p->hw_debug5 = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3935

*p->hw_debug5 = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4057

bool are_odm_segments_symmetrical = (ODMMode == dml2_odm_mode_combine_3to1) ? UseDSC : true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4100

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4263

*RequiresDSC = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4264

LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4266

*RequiresFEC = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4274

*RequiresFEC = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4285

*RequiresDSC = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4286

LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4299

*RequiresDSC = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4300

LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4312

*RequiresDSC = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4313

LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4327

*RequiresDSC = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4328

LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4330

*RequiresFEC = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4344

*RequiresDSC = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4345

LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4347

*RequiresFEC = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

435

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced == 1 && ptoi_supported == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4361

*RequiresDSC = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4362

LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4364

*RequiresFEC = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4376

*RequiresDSC = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4377

LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4378

*RequiresFEC = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4412

*RequiresDSC = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4413

LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4414

*RequiresFEC = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4424

*RequiresDSC = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4425

LinkDSCEnable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4426

*RequiresFEC = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4473

if (DSCEnable != true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4501

if (DSCEnabled == true && OutputBpp != 0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4763

if (display_cfg->gpuvm_enable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

4917

exclude_this_plane = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

5144

if (p->display_cfg->gpuvm_enable == true && p->display_cfg->hostvm_enable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

5198

if (p->DynamicMetadataVMEnabled == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

5206

if (p->DynamicMetadataEnable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

5208

*p->NotEnoughTimeForDynamicMetadata = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

5231

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

5291

if (p->display_cfg->gpuvm_enable == true || p->setup_for_tdlut || dcc_mrq_enable) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

5301

if (p->display_cfg->gpuvm_enable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

5377

if (p->display_cfg->gpuvm_enable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

5392

if ((p->display_cfg->gpuvm_enable == true || p->setup_for_tdlut || dcc_mrq_enable)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

541

is_vert = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

5522

bool tpre_gt_req_latency = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

5635

Case1OK = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

5649

Case2OK = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

5662

Case3OK = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

5687

if (p->display_cfg->gpuvm_enable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

5693

if (p->display_cfg->gpuvm_enable == true || dcc_mrq_enable || p->setup_for_tdlut) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

5784

s->NoTimeToPrefetch = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

5807

s->NoTimeToPrefetch = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

5829

s->NoTimeToPrefetch = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

5850

s->NoTimeToPrefetch = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

5880

s->NoTimeToPrefetch = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

5896

s->NoTimeToPrefetch = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6427

*flip_bandwidth_support_ok = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6771

*p->global_fclk_change_supported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6772

*p->global_dram_clock_change_supported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6928

*p->g6_temp_read_support = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6939

FoundCriticalSurface = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6986

if (p->display_cfg->gpuvm_enable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7120

clk_entry_found = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7386

mode_lib->ms.support.PrefetchSupported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7564

|| mode_lib->ms.NoTimeForPrefetch[k] == true

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7575

mode_lib->ms.support.DynamicMetadataSupported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7577

if (mode_lib->ms.NoTimeForDynamicMetadata[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7582

mode_lib->ms.support.VRatioInPrefetchSupported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7739

if (mode_lib->ms.support.PrefetchSupported == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7851

if (display_cfg->plane_descriptors[k].immediate_flip == true && mode_lib->ms.ImmediateFlipSupportedForPipe[k] == false)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8005

mode_lib->ms.support.ScaleRatioAndTapsSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8035

mode_lib->ms.support.SourceFormatPixelAndScanSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8112

mode_lib->ms.support.WritebackLatencySupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8122

mode_lib->ms.support.WritebackScaleRatioAndTapsSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8172

} else if (dml_is_vertical_rotation(display_cfg->plane_descriptors[k].composition.rotation_angle) && mode_lib->ms.BytePerPixelY[k] == 8 && display_cfg->plane_descriptors[k].surface.dcc.enable == true) { // vert 64bpp

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8218

mode_lib->ms.support.CursorSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8227

mode_lib->ms.support.PitchSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8285

mode_lib->ms.support.ViewportExceedsSurface = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8297

mode_lib->ms.support.ViewportExceedsSurface = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8361

mode_lib->ms.support.TotalAvailablePipesSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8413

true, // DSCEnable

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8478

mode_lib->ms.support.DSCSlicesODMModeSupported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8530

mode_lib->ms.MPCCombine[k] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8541

mode_lib->ms.MPCCombine[k] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8633

mode_lib->ms.support.LinkCapacitySupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8655

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format == dml2_420 && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced == 1 && mode_lib->ip.ptoi_supported == true)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8656

mode_lib->ms.support.P2IWith420 = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8659

mode_lib->ms.support.DSC422NativeNotSupported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8667

mode_lib->ms.support.LinkRateDoesNotMatchDPVersion = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8694

mode_lib->ms.support.MSOOrODMSplitWithNonDPLink = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8698

mode_lib->ms.support.NotEnoughLanesForMSO = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8718

mode_lib->ms.support.DTBCLKRequiredMoreThanSupported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8748

if (mode_lib->ms.RequiresDSC[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8760

mode_lib->ms.support.DSCCLKRequiredMoreThanSupported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8776

mode_lib->ms.support.PixelsPerLinePerDSCUnitSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8780

if (mode_lib->ms.RequiresDSC[k] == true && !s->stream_visited[display_cfg->plane_descriptors[k].stream_index]) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8795

mode_lib->ms.support.NotEnoughDSCSlices = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8802

mode_lib->ms.support.NotEnoughDSCUnits = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8876

if (display_cfg->plane_descriptors[k].surface.dcc.enable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8991

mode_lib->ms.support.PTEBufferSizeNotExceeded = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8992

mode_lib->ms.support.DCCMetaBufferSizeNotExceeded = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

900

if (ForceSingleDPP == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9197

((display_cfg->hostvm_enable == true || display_cfg->plane_descriptors[k].immediate_flip == true) &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9214

s->FullFrameMALLPStateMethod = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9216

s->SubViewportMALLPStateMethod = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9223

s->SubViewportMALLRefreshGreaterThan120Hz = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9227

s->PhantomPipeMALLPStateMethod = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9244

mode_lib->ms.support.OutstandingRequestsSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9245

mode_lib->ms.support.OutstandingRequestsUrgencyAvoidance = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9442

mode_lib->ms.support.AvgBandwidthSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9443

mode_lib->ms.support.EnoughUrgentLatencyHidingSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9470

mode_lib->ms.support.ROBSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9476

mode_lib->ms.support.ROBSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9550

mode_lib->ms.support.ModeSupport = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9582

dml2_print_mode_support_info(&mode_lib->ms.support, true);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9750

if (p->display_cfg->plane_descriptors[k].surface.dcc.enable == true && p->mrq_present) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9835

if (p->display_cfg->gpuvm_enable == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c

29

result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

421

is_phantom = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

475

is_vert = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

542

clk_entry_found = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

561

ret_val = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

626

svp_expanded_display_cfg->overrides.hw.force_unbounded_requesting.enable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

680

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

693

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

707

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

721

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

745

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

761

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

777

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

235

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

255

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

269

result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

273

result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

334

result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

348

result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

372

dcfclk_fine_grained = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

376

fclk_fine_grained = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

381

clock_state_count_identical = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

418

bool identical = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

432

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

445

contains_drr = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

490

in_out->programming->uclk_pstate_supported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

493

in_out->programming->fclk_pstate_supported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

496

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

540

in_out->programming->uclk_pstate_supported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

552

in_out->programming->fclk_pstate_supported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

556

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

571

in_out->programming->uclk_pstate_supported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

573

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

697

in_out->programming->uclk_pstate_supported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

703

in_out->programming->fclk_pstate_supported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

709

in_out->programming->fclk_pstate_supported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

722

in_out->programming->stutter.supported_in_blank = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

729

in_out->programming->z8_stutter.meets_eco = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

735

in_out->programming->z8_stutter.supported_in_blank = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

784

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c

11

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c

16

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c

32

result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c

37

result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c

42

result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c

130

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c

144

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c

162

dcfclk_fine_grained = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c

166

fclk_fine_grained = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c

171

clock_state_count_equal = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c

51

dcfclk_fine_grained = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c

55

fclk_fine_grained = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.c

11

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.c

26

result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.c

31

result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

127

success = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

138

success = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

147

bool result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

200

bool identical = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

214

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

227

contains_drr = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

247

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

272

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

307

in_out->base_display_config->stage4.unoptimizable_streams[display_config->plane_descriptors[i].stream_index] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

311

in_out->base_display_config->stage4.unoptimizable_streams[i] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

314

in_out->base_display_config->stage4.unoptimizable_streams[i] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

320

in_out->base_display_config->stage4.unoptimizable_streams[i] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

326

in_out->base_display_config->stage4.unoptimizable_streams[i] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

329

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

334

bool is_vmin = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

402

optimizable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

417

optimizable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

419

optimizable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

436

optimizable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

438

optimizable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

476

result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

519

result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

536

state->performed = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

647

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

665

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

682

success = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

689

success = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

693

success = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

70

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

82

bool result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1013

bool synchronizable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1073

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

113

.allow_state_increase = true,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1151

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1231

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

131

.allow_state_increase = true,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1364

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1368

schedulable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1387

schedulable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1400

swapped = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1442

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1446

schedulable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1459

swapped = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1481

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

149

.allow_state_increase = true,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1508

schedulable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1521

bool strategy_matches_drr_requirements = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1583

bool strategy_matches_forced_requirements = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1584

bool strategy_matches_drr_requirements = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

167

.allow_state_increase = true,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1680

stream_fams2_meta->valid = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1689

if (stream_descriptor->timing.drr_config.enabled == true) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

17

.allow_state_increase = true,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1825

stream_svp_meta->valid = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

184

bool result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1845

bool build_override_strategy = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1847

state->performed = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1851

display_config->display_config.overrides.enable_subvp_implicit_pmo = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1856

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1893

override_base_strategy.allow_state_increase = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1926

s->pmo_dcn4.pstate_strategy_candidates[s->pmo_dcn4.num_pstate_candidates-1].allow_state_increase = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1928

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2112

bool success = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2127

fams2_required = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2130

fams2_required = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2133

fams2_required = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2136

fams2_required = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2139

fams2_required = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2171

bool p_state_supported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2180

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2241

success = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

225

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2250

success = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2264

bool success = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2266

bool stutter_period_meets_z8_eco = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2291

z8_stutter_optimization_too_expensive = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2296

stutter_optimization_too_expensive = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

23

.allow_state_increase = true,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2308

pmo->scratch.pmo_dcn4.z8_vblank_optimizable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2327

bool success = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2366

success = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

250

bool result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

309

result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

35

.allow_state_increase = true,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

352

result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

477

expanded_strategy_added = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

480

skip_to_next_stream = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

483

skip_iteration = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

519

bool valid = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

53

.allow_state_increase = true,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

585

variant_found = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

636

expand_variant_strategy(&base_strategies_list[i], stream_count, true, expanded_strategy_list, num_expanded_strategies);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

708

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

733

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

77

.allow_state_increase = true,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

770

state->unoptimizable_streams[display_config->plane_descriptors[i].stream_index] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

774

state->unoptimizable_streams[i] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

777

state->unoptimizable_streams[i] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

783

state->unoptimizable_streams[i] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

789

state->unoptimizable_streams[i] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

792

state->performed = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

794

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

799

bool is_vmin = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

83

.allow_state_increase = true,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

867

optimizable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

882

optimizable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

884

optimizable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

89

.allow_state_increase = true,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

901

optimizable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

903

optimizable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

928

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

95

.allow_state_increase = true,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

969

s->pmo_dcn4.group_is_drr_enabled[timing_group_idx] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

994

bool valid = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c

17

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c

38

result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c

57

result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c

75

result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

1020

bool success = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

209

bool optimize_succeeded = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

210

bool candidate_validation_passed = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

318

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

33

state->performed = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

346

success = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

35

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

378

success = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

384

success = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

415

success = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

52

result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

529

bool all_pass = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

573

p0pass = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

578

p1pass = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

738

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

769

result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

895

l->mcache_phase.all_or_nothing = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

906

in_out->programming->informative.failed_mcache_validation = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

922

l->uclk_pstate_phase.all_or_nothing = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

928

l->base_display_config_with_meta.stage3.success = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

969

l->stutter_phase.all_or_nothing = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

975

l->base_display_config_with_meta.stage5.success = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

989

in_out->programming->informative.failed_dpmm = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

999

in_out->programming->informative.failed_mode_programming = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

1019

bool result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

1173

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

224

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

230

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

238

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

334

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

483

sorted = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

494

swapped = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

505

sorted = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

570

pipe_pool->pipe_used[odm_slice][i] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

688

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

73

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

730

pipe_pool->pipe_used[odm_slice][i] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

750

master_pipe, &state->res_ctx.pipe_ctx[scratch->pipe_pool.pipes_assigned_to_plane[odm_slice_index][0]], true);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

784

master_pipe, &state->res_ctx.pipe_ctx[scratch->pipe_pool.pipes_assigned_to_plane[odm_slice_index][i]], true);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

963

bool result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

992

bool result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

159

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

168

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

271

valid_assignment_found = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

279

valid_assignment_found = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

280

current_assignment_freesync = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

337

subvp_possible = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

409

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

486

schedulable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

545

found = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

580

schedulable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

603

bool schedulable = true; // true by default for single display case

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

837

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

856

removed_pipe = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

906

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_policy.c

292

policy->DRAMClockChangeRequirementFinal = true; // TOREVIEW: What does this mean?

sys/dev/pci/drm/amd/display/dc/dml2/dml2_policy.c

293

policy->FCLKChangeRequirementFinal = true; // TOREVIEW: What does this mean?

sys/dev/pci/drm/amd/display/dc/dml2/dml2_policy.c

294

policy->USRRetrainingRequiredFinal = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_policy.c

295

policy->EnhancedPrefetchScheduleAccelerationFinal = true; // TOREVIEW: What does this mean?

sys/dev/pci/drm/amd/display/dc/dml2/dml2_policy.c

298

policy->DCCProgrammingAssumesScanDirectionUnknownFinal = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_policy.c

299

policy->SynchronizeTimingsFinal = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_policy.c

300

policy->SynchronizeDRRDisplaysForUCLKPStateChangeFinal = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_policy.c

301

policy->AssumeModeSupportAtMaxPwrStateEvenDRAMClockChangeNotSupported = true; // TOREVIEW: What does this mean?

sys/dev/pci/drm/amd/display/dc/dml2/dml2_policy.c

302

policy->AssumeModeSupportAtMaxPwrStateEvenFClockChangeNotSupported = true; // TOREVIEW: What does this mean?

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1161

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1216

dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid[pipe_index] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1351

dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[disp_cfg_stream_location] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1362

dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[disp_cfg_plane_location] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1395

dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[disp_cfg_plane_location] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1417

dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[disp_cfg_plane_location] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

229

out->dsc422_native_support = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

230

out->dcc_supported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

235

out->cursor_64bpp_support = true; //false;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

277

out->do_urgent_latency_adjustment = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

380

p->in_states->state_array[0].use_ideal_dram_bw_strobe = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

416

p->in_states->state_array[0].use_ideal_dram_bw_strobe = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

451

p->in_states->state_array[0].use_ideal_dram_bw_strobe = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

743

out->state_array[i].use_ideal_dram_bw_strobe = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

889

out->OutputDisabled[location] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

94

out->dsc422_native_support = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

95

out->dcc_supported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

162

ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

177

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

231

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

291

context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

533

need_recalculation = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

557

is_stereo = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

144

optimization_done = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

147

optimization_done = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

205

dml_result = dml_mode_programming(&dml2->v20.dml_core_ctx, s_global->mode_support_params.out_lowest_state_idx, &s->cur_display_config, true);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

246

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

255

bool pass = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

271

unsigned int optimized_result = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

390

result = dml_mode_programming(&dml2->v20.dml_core_ctx, min_state, &s->cur_display_config, true);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

392

result = dml_mode_programming(&dml2->v20.dml_core_ctx, s->mode_support_params.out_lowest_state_idx, &s->cur_display_config, true);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

411

out_clks.p_state_supported = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

421

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

514

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

640

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

691

return true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

86

dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[num_pipes] = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

88

dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[num_pipes] = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

185

return true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

227

dpp1_cm_power_on_regamma_lut(dpp_base, true);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

317

is_float = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

349

force_disable_cursor = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

355

force_disable_cursor = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

361

force_disable_cursor = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

390

== true) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

392

RGAM_MEM_PWR_FORCE, power_on == true ? 0:1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

428

CM_RGAM_LUT_WRITE_SEL, is_ram_a == true ? 0:1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

714

*ram_a_inuse = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

715

ret = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

718

ret = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

736

is_ram_a == true ? 0:1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

756

bool is_ram_a = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

758

dpp1_power_on_degamma_lut(dpp_base, true);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

761

if (is_ram_a == true)

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

807

*ram_a_inuse = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

808

in_use = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

812

in_use = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

109

return true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

118

return true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

169

dpp->base.ctx->dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

170

dpp->base.deferred_reg_writes.bits.disable_dscl = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

632

dpp1_power_on_dscl(dpp_base, true);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

153

force_disable_cursor = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

159

force_disable_cursor = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

165

force_disable_cursor = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

233

== true) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

255

dpp2_power_on_obuf(dpp_base, true);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

433

return true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

83

REG_UPDATE(CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, power_on == true ? 1:0);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

86

OBUF_MEM_PWR_FORCE, power_on == true ? 0:1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

89

LUT_MEM_PWR_FORCE, power_on == true ? 0:1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1002

*is_17x17x17 = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1031

CM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1044

is_color_channel_12bits == true ? 0:1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1192

return true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

120

bool is_ram_a = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

122

dpp1_power_on_degamma_lut(dpp_base, true);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

125

if (is_ram_a == true)

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

372

BLNDGAM_MEM_PWR_FORCE, power_on == true ? 0:1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

385

CM_BLNDGAM_LUT_WRITE_SEL, is_ram_a == true ? 0:1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

539

dpp20_power_on_blnd_lut(dpp_base, true);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

553

return true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

624

CM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

76

*ram_a_inuse = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

77

ret = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

80

ret = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

963

return true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

97

is_ram_a == true ? 0:1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

997

*is_12bits_color_channel = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

100

force_disable_cursor = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

106

force_disable_cursor = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

112

force_disable_cursor = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

185

dpp2_power_on_obuf(dpp_base, true);

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

262

return true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

323

return true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1208

dpp3_power_on_shaper(dpp_base, true);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1229

return true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1264

*is_12bits_color_channel = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1269

*is_17x17x17 = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1298

CM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1311

is_color_channel_12bits == true ? 0:1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1402

dpp3_power_on_hdr3dlut(dpp_base, true);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1463

return true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1521

return true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1534

return true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

262

force_disable_cursor = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

268

force_disable_cursor = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

274

force_disable_cursor = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

357

if (input_csc_color_matrix.enable_adjustment == true) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

517

return true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

578

dpp_base->ctx->dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

579

dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

595

dpp_base->ctx->dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

596

dpp_base->deferred_reg_writes.bits.disable_3dlut = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

612

dpp_base->ctx->dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

613

dpp_base->deferred_reg_writes.bits.disable_shaper = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

626

CM_BLNDGAM_LUT_HOST_SEL, is_ram_a == true ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

800

dpp3_power_on_blnd_lut(dpp_base, true);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

815

return true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

886

CM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

137

dpp_base->ctx->dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

138

dpp_base->deferred_reg_writes.bits.disable_gamcor = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

142

GAMCOR_MEM_PWR_DIS, power_on == true ? 0:1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

210

CM_GAMCOR_LUT_HOST_SEL, is_ram_a == true ? 0:1);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

231

dpp3_power_on_gamcor_lut(dpp_base, true);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

240

dpp3_power_on_gamcor_lut(dpp_base, true);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

301

return true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

164

return true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

142

dpp->dispclk_r_gate_disable = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

203

if (input_csc_color_matrix.enable_adjustment == true) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

279

return true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

101

return true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1030

*bs_coeffs_updated = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1037

*bs_coeffs_updated = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1089

program_isharp_1dlut = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

110

return true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1106

dpp401_power_on_dscl(dpp_base, true);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

161

dpp->base.ctx->dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

162

dpp->base.deferred_reg_writes.bits.disable_dscl = true;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1373

policy->use_min_slices_h = true;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

219

return true;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

234

return true;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

295

return true;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

326

return true;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

421

return true;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

450

dsc_sink_caps->is_dp = true;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

451

return true;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

765

return true;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

450

return true;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

97

dsc_enc_caps->is_block_pred_supported = true;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

75

dsc_enc_caps->is_block_pred_supported = true;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

116

return true;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

130

return true;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

190

return true;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

55

caps->caps.support_dwb = true;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

56

caps->caps.support_ogam = true;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

57

caps->caps.support_wbscl = true;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

59

caps->caps.support_stereo = true;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

60

return true;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

181

DWB_OGAM_LUT_HOST_SEL, (is_ram_a == true) ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

269

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

109

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

112

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

124

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

127

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

130

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

133

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

145

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

148

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

151

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

154

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

157

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

160

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

163

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

167

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

186

bool result = true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

52

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

55

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

58

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

61

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

64

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

67

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

70

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

82

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

85

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

88

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

91

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

94

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

97

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

104

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

107

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

110

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

113

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

116

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

119

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

131

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

134

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

146

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

149

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

152

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

155

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

167

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

170

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

173

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

176

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

179

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

182

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

185

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

189

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

208

bool result = true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

74

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

77

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

80

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

83

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

86

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

89

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

92

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

106

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

109

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

112

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

115

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

118

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

121

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

133

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

136

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

148

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

151

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

154

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

157

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

174

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

177

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

180

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

183

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

186

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

189

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

192

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

196

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

215

bool result = true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

76

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

79

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

82

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

85

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

88

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

91

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

94

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

106

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

109

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

112

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

115

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

118

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

121

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

133

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

136

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

148

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

151

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

154

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

157

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

174

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

177

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

180

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

183

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

186

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

189

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

192

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

196

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

215

bool result = true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

76

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

79

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

82

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

85

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

88

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

91

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

94

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

104

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

107

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

110

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

113

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

116

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

119

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

131

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

134

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

146

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

149

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

152

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

155

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

167

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

170

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

173

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

176

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

179

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

182

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

185

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

189

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

208

bool result = true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

74

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

77

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

80

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

83

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

86

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

89

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

92

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

108

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

111

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

114

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

117

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

120

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

123

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

135

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

138

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

141

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

144

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

157

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

160

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

163

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

166

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

169

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

172

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

175

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

197

bool result = true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

78

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

81

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

84

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

87

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

90

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

93

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

96

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

107

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

110

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

113

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

116

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

119

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

122

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

134

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

137

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

140

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

143

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

156

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

159

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

162

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

165

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

168

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

171

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

193

bool result = true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

77

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

80

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

83

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

86

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

89

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

92

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

95

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

100

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

103

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

115

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

118

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

121

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

124

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

127

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

130

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

142

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

145

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

148

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

151

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

164

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

167

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

170

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

173

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

176

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

179

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

182

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

204

bool result = true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

85

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

88

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

91

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

94

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

97

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

108

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

111

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

114

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

117

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

120

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

123

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

135

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

138

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

141

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

144

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

157

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

160

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

163

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

166

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

169

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

172

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

194

bool result = true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

78

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

81

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

84

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

87

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

90

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

93

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

96

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

103

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

106

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

109

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

112

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

115

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

127

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

130

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

133

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

136

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

148

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

151

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

154

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

157

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

160

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

163

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

175

bool result = true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

76

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

79

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

82

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

85

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

88

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

91

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

102

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

105

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

108

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

111

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

124

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

127

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

130

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

133

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

136

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

159

bool result = true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

51

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

54

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

57

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

60

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

63

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

66

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

78

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

81

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

84

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

87

return true;

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

90

return true;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

256

service->busyness[id][en] = true;

sys/dev/pci/drm/amd/display/dc/gpio/hw_factory.c

107

return true;

sys/dev/pci/drm/amd/display/dc/gpio/hw_factory.c

110

return true;

sys/dev/pci/drm/amd/display/dc/gpio/hw_factory.c

117

return true;

sys/dev/pci/drm/amd/display/dc/gpio/hw_factory.c

120

return true;

sys/dev/pci/drm/amd/display/dc/gpio/hw_factory.c

68

return true;

sys/dev/pci/drm/amd/display/dc/gpio/hw_factory.c

74

return true;

sys/dev/pci/drm/amd/display/dc/gpio/hw_factory.c

78

return true;

sys/dev/pci/drm/amd/display/dc/gpio/hw_factory.c

83

return true;

sys/dev/pci/drm/amd/display/dc/gpio/hw_factory.c

87

return true;

sys/dev/pci/drm/amd/display/dc/gpio/hw_factory.c

91

return true;

sys/dev/pci/drm/amd/display/dc/gpio/hw_factory.c

94

return true;

sys/dev/pci/drm/amd/display/dc/gpio/hw_factory.c

98

return true;

sys/dev/pci/drm/amd/display/dc/gpio/hw_translate.c

108

return true;

sys/dev/pci/drm/amd/display/dc/gpio/hw_translate.c

111

return true;

sys/dev/pci/drm/amd/display/dc/gpio/hw_translate.c

118

return true;

sys/dev/pci/drm/amd/display/dc/gpio/hw_translate.c

121

return true;

sys/dev/pci/drm/amd/display/dc/gpio/hw_translate.c

72

return true;

sys/dev/pci/drm/amd/display/dc/gpio/hw_translate.c

78

return true;

sys/dev/pci/drm/amd/display/dc/gpio/hw_translate.c

84

return true;

sys/dev/pci/drm/amd/display/dc/gpio/hw_translate.c

88

return true;

sys/dev/pci/drm/amd/display/dc/gpio/hw_translate.c

92

return true;

sys/dev/pci/drm/amd/display/dc/gpio/hw_translate.c

95

return true;

sys/dev/pci/drm/amd/display/dc/gpio/hw_translate.c

99

return true;

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

133

{ true, 0, 1, 0 },

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

190

.supported = true,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

312

return true;

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

333

.supported = true,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

41

[HDCP_MESSAGE_ID_READ_BKSV] = true,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

42

[HDCP_MESSAGE_ID_READ_RI_R0] = true,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

43

[HDCP_MESSAGE_ID_READ_PJ] = true,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

47

[HDCP_MESSAGE_ID_READ_VH_X] = true,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

48

[HDCP_MESSAGE_ID_READ_VH_0] = true,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

49

[HDCP_MESSAGE_ID_READ_VH_1] = true,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

50

[HDCP_MESSAGE_ID_READ_VH_2] = true,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

51

[HDCP_MESSAGE_ID_READ_VH_3] = true,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

52

[HDCP_MESSAGE_ID_READ_VH_4] = true,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

53

[HDCP_MESSAGE_ID_READ_BCAPS] = true,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

54

[HDCP_MESSAGE_ID_READ_BSTATUS] = true,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

55

[HDCP_MESSAGE_ID_READ_KSV_FIFO] = true,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

56

[HDCP_MESSAGE_ID_READ_BINFO] = true,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

57

[HDCP_MESSAGE_ID_HDCP2VERSION] = true,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

58

[HDCP_MESSAGE_ID_RX_CAPS] = true,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

60

[HDCP_MESSAGE_ID_READ_AKE_SEND_CERT] = true,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

63

[HDCP_MESSAGE_ID_READ_AKE_SEND_H_PRIME] = true,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

64

[HDCP_MESSAGE_ID_READ_AKE_SEND_PAIRING_INFO] = true,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

66

[HDCP_MESSAGE_ID_READ_LC_SEND_L_PRIME] = true,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

68

[HDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LIST] = true,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

71

[HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY] = true,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

72

[HDCP_MESSAGE_ID_READ_RXSTATUS] = true,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

440

if (info_frame->adaptive_sync.valid == true &&

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

441

info_frame->sdp_line_num.adaptive_sync_line_num_valid == true) {

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

462

true);

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

469

true);

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

476

true);

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

487

true);

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

565

pps_sdp.valid = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

112

return enable ? true : false;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

196

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

210

forced_pstate_allow = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

266

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

277

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

291

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

302

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

316

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

327

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

341

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

352

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

382

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

398

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

415

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

431

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

448

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

464

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

481

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

497

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

527

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

544

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

561

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

578

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

596

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

599

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

602

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

678

dh_data->dchub_initialzied = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

708

standard_swizzle = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

716

display_swizzle = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

725

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

730

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

735

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

740

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

745

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

760

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

766

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

772

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

818

true; /* half 128b request */

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

822

true; /* half 128b request */

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

901

output->grph.rgb.independent_64b_blks = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

908

output->capable = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

911

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

104

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

109

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

116

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

121

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

126

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

132

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

147

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

159

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

165

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

210

true; /* half 128b request */

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

214

true; /* half 128b request */

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

297

output->grph.rgb.independent_64b_blks = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

303

output->capable = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

304

output->const_color_support = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

306

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

502

dh_data->dchub_initialzied = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

605

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

608

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

615

if (hubbub1->base.ctx->dc->clk_mgr->clks.prev_p_state_change_support == true &&

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

617

safe_to_lower = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

620

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

73

standard_swizzle = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

76

render_swizzle = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

84

display_swizzle = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

94

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

99

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c

63

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c

66

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

103

hubbub->riommu_active = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

165

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

176

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

186

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

195

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

210

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

221

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

231

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

240

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

255

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

266

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

276

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

285

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

300

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

311

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

321

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

330

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

361

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

378

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

396

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

413

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

431

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

448

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

466

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

483

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

515

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

551

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

569

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

584

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

587

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

590

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

106

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

109

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

112

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

155

standard_swizzle = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

163

render_swizzle = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

171

display_swizzle = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

181

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

186

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

191

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

196

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

203

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

208

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

213

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

218

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

224

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

269

true; /* half 128b request */

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

273

true; /* half 128b request */

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

363

output->grph.rgb.independent_64b_blks = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

373

output->capable = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

374

output->const_color_support = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

376

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

1016

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

1030

forced_pstate_allow = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

196

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

207

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

217

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

226

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

240

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

251

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

261

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

270

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

284

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

295

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

305

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

314

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

328

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

339

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

349

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

358

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

388

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

404

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

420

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

436

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

453

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

469

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

485

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

501

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

518

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

534

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

550

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

566

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

583

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

599

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

615

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

631

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

662

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

696

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

713

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

727

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

730

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

733

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

797

true; /* half 128b request */

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

801

true; /* half 128b request */

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

889

output->grph.rgb.independent_64b_blks = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

900

output->capable = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

901

output->const_color_support = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

903

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

1006

hubbub32_set_sdp_control(hubbub, true);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

200

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

211

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

221

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

230

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

244

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

255

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

265

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

274

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

288

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

299

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

309

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

318

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

332

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

343

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

353

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

362

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

392

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

408

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

425

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

441

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

458

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

474

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

491

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

507

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

540

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

557

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

574

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

591

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

609

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

626

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

643

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

660

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

691

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

707

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

724

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

741

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

773

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

779

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

782

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

785

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

788

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

815

hubbub32_set_sdp_control(hubbub, true);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

137

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

153

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

171

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

187

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

204

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

220

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

237

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

253

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

308

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

311

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

314

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

317

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

320

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

105

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

1109

output->capable = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

1110

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

113

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

120

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

1220

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

127

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

139

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

149

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

158

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

166

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

173

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

180

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

214

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

235

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

257

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

278

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

306

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

320

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

334

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

348

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

363

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

377

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

391

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

405

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

431

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

444

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

459

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

462

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

465

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

468

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

613

swizzle_supported = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

617

swizzle_supported = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

628

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

633

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

638

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

643

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

660

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

665

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

678

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

682

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

687

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

693

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

700

return true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

751

true; /* half 128b request */

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

755

true; /* half 128b request */

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

783

true; /* half 128B request */

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

788

true; /* half 128B request */

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

800

true; /* half 128b request */

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

806

true; /* half 128b request */

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

816

true; /* half 128b request */

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

822

true; /* half 128b request */

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

86

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

874

is_dual_plane = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

899

is_dual_plane = true;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

96

wm_pending = true;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1319

return in_blank ? true : false;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

518

return true;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

770

return true;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

774

return true;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1717

return true;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

886

return true;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

942

return true;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

946

return true;

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

155

return true;

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

761

flip_regs.grph_stereo = true;

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

803

return true;

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

863

return true;

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

316

return true;

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

582

return true;

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

135

return true;

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

163

REG_UPDATE(DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, true);

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

231

return true;

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

243

return true;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

1096

return true;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

557

return true;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

726

return in_blank ? true : false;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

215

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

103

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

129

true);

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

170

true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1093

if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1112

pipe_ctx->stream_res.audio->enabled = true;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1217

hws->funcs.edp_backlight_control(link, true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1467

audio_output->pll_info.ss_enabled = true;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1539

pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1567

true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1697

dc->link_srv->set_dsc_enable(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1812

true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1887

se->funcs->dp_set_dsc_pps_info_packet(se, false, NULL, true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1983

keep_edp_vdd_on = true;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1989

can_apply_seamless_boot = true;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2258

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2327

if (dc->caps.dynamic_audio == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2337

pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2475

dcb->funcs->set_scratch_critical_state(dcb, true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

250

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2610

blank_target = true;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2613

blank_target = true;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2628

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2702

rc = true;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2832

true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2855

tg->funcs->set_blank(tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

290

bool result = true;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2913

true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2931

dce_enable_fe_clock(dc->hwseq, mi->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2935

== true) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2947

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3106

if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3194

bool fw_set_brightness = true;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3216

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3292

link->dc->hwss.edp_wait_for_hpd_ready(link, true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

342

fmt.sign = true;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

384

fmt.sign = true;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

427

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

603

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

612

xfm->funcs->opp_power_on_regamma_lut(xfm, true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

628

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

764

edp_hpd_high = true;

sys/dev/pci/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

147

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

187

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

241

dh_data->dchub_initialzied = true;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

108

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

189

blank_target = true;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

286

dce_enable_fe_clock(dc->hwseq, mi->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

290

== true) {

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

302

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1014

hws->funcs.dpp_root_clock_control(hws, plane_id, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1021

hws->funcs.dpp_pg_control(hws, plane_id, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1024

hws->funcs.hubp_pg_control(hws, plane_id, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1041

hubp->funcs->set_blank(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1075

hws->funcs.hubp_pg_control(hws, 0, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1080

hws->wa_state.DEGVIDCN10_253_applied = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1088

bool allow_self_fresh_force_enable = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1146

tg->funcs->set_blank_data_double_buffer(tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1199

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1227

true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1259

pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1311

if (dc->caps.dynamic_audio == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1373

hubp->funcs->set_hubp_blank_en(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1377

hubbub1_soft_reset(dc->res_pool->hubbub, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1386

hubp->funcs->hubp_disable_control(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1396

hubp->funcs->hubp_disable_control(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1408

hubp->funcs->set_hubp_blank_en(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1411

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1463

opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1465

dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1538

hubp->power_gated = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1579

can_apply_seamless_boot = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

159

pipe_ctx->wait_is_required = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1604

tg->funcs->set_blank(tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1658

hubp->power_gated = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1659

tg_enabled[i] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1681

dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1827

link->link_status.link_active = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1838

hws->funcs.enable_power_gating_plane(dc->hwseq, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1992

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2036

bool result = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2063

result = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2076

result = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2144

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

216

pipe_ctx->wait_is_required = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2285

rc = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2336

ret = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2434

phase[i] = div_u64(phase[i], get_clock_divider(grouped_pipes[i], true));

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2440

&modulo[i], true) == false) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2446

grouped_pipes[i]->stream->has_non_synchronizable_pclk = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

245

dc->hwss.pipe_control_lock(dc, pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2523

grouped_pipes[i]->stream->vblank_synchronized = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2525

grouped_pipes[master]->stream->vblank_synchronized = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2747

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2752

true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2777

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2783

pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2806

return true; // MPO in use and front plane not hidden

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2832

if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3032

true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3191

fmt.sign = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3220

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3353

true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3386

true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3391

true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3485

non_stereo_timing = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3524

if (!dc_set_generic_gpio_for_stereo(true, dc->ctx->gpio_service))

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3578

hubp->funcs->set_blank(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3594

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3672

pipe_split_on = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3886

fmt.sign = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4036

hws->funcs.edp_backlight_control(link, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4085

context, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4143

true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

469

is_gamut_remap_available = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

820

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

825

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

834

bool force_on = true; /* disable power gating */

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1012

mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1014

if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1043

mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1066

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1073

bool result = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1093

bool result = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1101

&dpp_base->shaper_params, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1122

bool result = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1134

use_degamma_ram = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1136

if (use_degamma_ram == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1146

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1169

result = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1197

int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1289

hws->funcs.dpp_root_clock_control(hws, pipe_ctx->plane_res.dpp->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1298

hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1301

hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1321

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1329

true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1567

new_pipe->update_flags.bits.plane_changed = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1693

dpp->funcs->dpp_dppclk_control(dpp, false, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1794

viewport_changed = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1802

pipe_ctx->update_flags.bits.scaler || viewport_changed == true) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1921

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2082

dc->res_pool->hubbub, true, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2105

dc->hwseq->funcs.blank_pixel_data(dc, pipe, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2117

hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2368

hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2446

true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2455

hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2459

true, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2460

context->bw_ctx.bw.dcn.clk.p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2461

dc->clk_mgr->clks.fw_based_mclk_switching = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2469

true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2534

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2618

hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2620

hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2715

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2793

hws->funcs.edp_backlight_control(link, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2842

if (dc->caps.dynamic_audio == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

311

bool force_on = true; /* disable power gating */

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3118

enable = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3147

hws->funcs.enable_power_gating_plane(hws, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3215

dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

733

hubp->power_gated = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

784

hblank_halved = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

874

last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

884

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

931

true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

942

true,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

95

is_gamut_remap_available = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

951

true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

958

hws->funcs.blank_pixel_data(dc, pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

323

res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

397

mpcc_removed = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

404

mpcc_removed = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

411

opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

413

dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

613

hws->funcs.edp_backlight_control(link, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

71

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

94

is_in_uma = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

97

is_in_uma = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

115

true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

137

pipe_ctx->stream->dpms_off = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

159

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

262

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

285

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

298

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1083

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1100

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1160

subvp_in_use = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1172

dc->res_pool->hubbub, true, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1191

dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

235

bool result = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

271

&dpp_base->shaper_params, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

320

bool result = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

366

pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

380

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

503

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

521

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

714

link->link_status.link_active = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

725

hws->funcs.enable_power_gating_plane(dc->hwseq, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

896

enable = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

941

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

95

is_gamut_remap_available = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

171

link->link_status.link_active = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

182

hws->funcs.enable_power_gating_plane(dc->hwseq, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

349

bool force_on = true; /* disable power gating */

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

365

force_on = true; /* disable power gating */

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

536

dc->hwseq->wa_state.skip_blank_stream = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

598

if (dc->caps.dynamic_audio == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

729

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

107

dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

178

int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

206

true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

297

bool force_on = true; /* disable power gating */

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

313

force_on = true; /* disable power gating */

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

421

otg_disabled[i] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

436

int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1007

dc->debug.force_disable_subvp = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1008

dc->debug.disable_fpo_optimizations = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1062

dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1137

int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1153

true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1180

dc->hwseq->funcs.blank_pixel_data(dc, pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1266

otg_disabled[i] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1281

int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1340

hws->funcs.edp_backlight_control(link, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1352

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

137

bool force_on = true; /* disable power gating */

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1526

hws->funcs.dsc_pg_control(hws, dsc->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1741

bool is_seamless = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1796

dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1835

dc->hwss.pipe_control_lock(dc, pipe, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1848

hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

210

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

286

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

304

mall_ss_unsupported = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

321

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

337

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

358

enable_subvp = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

389

subvp_in_use = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

397

subvp_immediate_flip = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

456

&dpp_base->shaper_params, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

482

bool result = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

507

&dpp_base->shaper_params, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

531

bool result = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

656

hubp->funcs->hubp_update_force_pstate_disallow(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

658

hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

698

cache_cursor = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

744

hubp->funcs->hubp_prepare_subvp_buffering(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

759

clocks->fclk_p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

760

clocks->p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

775

true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

846

link->link_status.link_active = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

858

hws->funcs.enable_power_gating_plane(dc->hwseq, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

892

dc_allow_idle_optimizations(dc, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

998

dc->debug.fams2_config.bits.enable &= true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1048

update_state->pg_pipe_res_update[j][new_pipe->plane_res.hubp->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1051

update_state->pg_pipe_res_update[j][new_pipe->plane_res.dpp->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1054

update_state->pg_pipe_res_update[j][new_pipe->plane_res.mpcc_inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1057

update_state->pg_pipe_res_update[j][new_pipe->stream_res.dsc->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1060

update_state->pg_pipe_res_update[j][new_pipe->stream_res.opp->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1063

update_state->pg_pipe_res_update[j][new_pipe->stream_res.tg->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1066

update_state->pg_pipe_res_update[j][new_pipe->stream_res.hpo_dp_stream_enc->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1075

update_state->pg_pipe_res_update[j][new_pipe->plane_res.hubp->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1080

update_state->pg_pipe_res_update[j][new_pipe->plane_res.dpp->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1085

update_state->pg_pipe_res_update[j][new_pipe->stream_res.opp->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1090

update_state->pg_pipe_res_update[j][new_pipe->stream_res.dsc->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1095

update_state->pg_pipe_res_update[j][new_pipe->stream_res.tg->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1100

update_state->pg_pipe_res_update[j][new_pipe->stream_res.hpo_dp_stream_enc->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1107

update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1112

hpo_dp_stream_enc_acquired = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1118

update_state->pg_res_update[PG_HPO] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1121

update_state->pg_pipe_res_update[PG_HDMISTREAM][0] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1129

update_state->pg_pipe_res_update[PG_HUBP][new_pipe->stream_res.dsc->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1130

update_state->pg_pipe_res_update[PG_DPP][new_pipe->stream_res.dsc->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1136

update_state->pg_pipe_res_update[PG_HUBP][j] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1137

update_state->pg_pipe_res_update[PG_DPP][j] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1147

update_state->pg_pipe_res_update[PG_HUBP][j] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1148

update_state->pg_pipe_res_update[PG_DPP][j] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1270

pg_cntl->funcs->plane_otg_pg_control(pg_cntl, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1276

pg_cntl->funcs->dsc_pg_control(pg_cntl, i, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1284

pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1290

pg_cntl->funcs->dsc_pg_control(pg_cntl, i, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1296

pg_cntl->funcs->hpo_pg_control(pg_cntl, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1368

dc->hwss.root_clock_control(dc, &pg_update_state, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1557

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1573

update_state->pg_pipe_res_update[j][i] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1575

update_state->pg_res_update[PG_HPO] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1576

update_state->pg_res_update[PG_DWB] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1590

dc->hwss.root_clock_control(dc, &pg_update_state, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

204

link->link_status.link_active = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

363

dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

434

int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

462

true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

560

dc_allow_idle_optimizations(dc, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

566

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

607

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

631

can_apply_seamless_boot = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

656

tg->funcs->set_blank(tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

710

hubp->power_gated = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

711

tg_enabled[i] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

733

dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

823

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

828

dccg->funcs->dccg_root_gate_disable_control(dccg, dpp->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

829

dpp->funcs->dpp_dppclk_control(dpp, false, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

833

true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

883

hubp->power_gated = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

936

hpo_dp_stream_enc_acquired = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

942

update_state->pg_res_update[PG_HPO] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

944

update_state->pg_res_update[PG_DWB] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

950

update_state->pg_pipe_res_update[j][i] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

989

update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

166

pg_cntl->funcs->plane_otg_pg_control(pg_cntl, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

174

pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

179

pg_cntl->funcs->dsc_pg_control(pg_cntl, i, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

69

update_state->pg_pipe_res_update[PG_HUBP][j] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

70

update_state->pg_pipe_res_update[PG_DPP][j] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

104

pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1105

mpc_combine_on = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1237

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

125

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1318

mall_ss_unsupported = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1342

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1357

is_wait_needed = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1379

dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1416

dcn401_fams2_global_control_lock(dc, context, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1437

dcn401_fams2_global_control_lock(dc, context, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1438

dcn401_fams2_update_config(dc, context, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1446

true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1449

hubbub->funcs->program_arbiter(hubbub, &context->bw_ctx.bw.dcn.arb_regs, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1459

hubbub->funcs->program_compbuf_segments(hubbub, context->bw_ctx.bw.dcn.arb_regs.compbuf_size, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1464

true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1569

int last_odm_slice_width = resource_get_odm_slice_dst_width(otg_master, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1590

true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1604

dc->hwseq->funcs.blank_pixel_data(dc, otg_master, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1631

hws->funcs.edp_backlight_control(link, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1648

dc->res_pool->hubbub, true, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1650

dc->current_state->bw_ctx.bw.dcn.clk.p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1651

dc->clk_mgr->funcs->update_clocks(dc->clk_mgr, dc->current_state, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1656

dc->clk_mgr->funcs->update_clocks(dc->clk_mgr, dc->current_state, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1713

dc->hwss.pipe_control_lock(dc, pipe, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1778

pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout(pipe_ctx->stream_res.tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1782

wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl(wa_pipes[i]->plane_res.hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1791

wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl(wa_pipes[i]->plane_res.hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1808

hubbub->funcs->program_compbuf_segments(hubbub, context->bw_ctx.bw.dcn.arb_regs.compbuf_size, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1842

if (dc->caps.dynamic_audio == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1976

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2138

dc->res_pool->hubbub, true, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

215

link->link_status.link_active = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2161

dc->hwseq->funcs.blank_pixel_data(dc, pipe, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2173

hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

227

hws->funcs.enable_power_gating_plane(dc->hwseq, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2392

hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2449

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2537

new_pipe->update_flags.bits.plane_changed = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

261

dc_allow_idle_optimizations(dc, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

336

dcn401_setup_hpo_hw_control(hws, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

458

&dpp_base->regamma_params, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

580

mpc->funcs->mcm.program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, true, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

589

hubp->funcs->hubp_enable_3dlut_fl(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

607

hubp->funcs->hubp_enable_3dlut_fl(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

624

return true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

648

&dpp_base->shaper_params, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

78

clocks->fclk_p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

79

clocks->p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

793

last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

810

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

84

true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

840

true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

845

true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

854

true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

856

hws->funcs.blank_pixel_data(dc, pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

446

return true;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

448

return true;

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

229

return true;

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

61

return true;

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

137

return true;

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

177

return true;

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

215

return true;

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

242

return true;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

703

return true;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

738

link->test_pattern_enabled = true;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

888

true,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

945

link->test_pattern_enabled = true;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

950

return true;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.c

31

link->dp_trace.is_initialized = true;

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

283

pipe_ctx->stream_res.stream_enc, true);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

62

pipe_ctx->stream_res.stream_enc->id, true);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

68

pipe_ctx->stream->signal, true);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

123

return true;

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

122

true);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

156

return true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1007

converter_disable_audio = true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1100

return true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1115

link->ctx->dc->debug.hdmi20_disable = true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1206

link->panel_config.ilr.optimize_edp_link_rate = true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1235

return true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1251

return true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1257

link->dc->hwss.edp_power_control(link, true);

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1258

link->dc->hwss.edp_wait_for_hpd_ready(link, true);

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1268

return true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1287

return true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1342

ret = true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1391

return true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

293

.write = true,

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

365

is_type2_dongle = true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

370

is_valid_hdmi_signature = true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

410

if (is_valid_hdmi_signature == true) {

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

434

if (is_valid_hdmi_signature == true) {

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

449

sink_cap->is_dongle_type_one = true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

568

link->cur_link_settings.use_link_rate_set = true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

620

return true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

658

return true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

664

return true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

679

return true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

701

link->wa_flags.dpia_mst_dsc_always_on = true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

709

link->wa_flags.dpia_mst_dsc_always_on = true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

760

can_apply_seamless_boot = true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

835

destrictive = true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

905

return true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

964

dc->config.edp_no_power_sequencing = true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

967

link->wa_flags.dp_keep_receiver_powered = true;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

999

return true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1000

true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1003

pipe_ctx->stream_res.stream_enc, false, NULL, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1007

return true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1022

link_set_dsc_on_stream(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1023

result = true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1028

result = true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1043

link_set_dsc_on_stream(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1044

link_set_dsc_pps_packet(pipe_ctx, true, false);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1045

return true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

116

link_blank_dp_stream(dc->links[i], true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1214

return true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1452

true))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

157

bool dpms_off = true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1581

return true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1623

result = true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1773

true)) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1845

true)) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1979

is_over_340mhz = true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2062

apply_seamless_boot_optimization = true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2072

do_fallback = true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2081

enable_mst_on_sink(link, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2091

link->dc->hwss.edp_power_control(link, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2092

link->dc->hwss.edp_wait_for_hpd_ready(link, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2115

skip_video_pattern = true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2137

fec_enable = true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2150

edp_backlight_enable_aux(link, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2152

edp_backlight_enable_aux(link, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2209

enable_mst_on_sink(link, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2272

pipe_ctx->stream->link->link_status.link_active = true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2322

return true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2374

set_avmute(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2379

update_psp_stream_config(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2502

pipe_ctx->stream->link->link_state_valid = true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

256

result = true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2579

link_set_dsc_enable(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2630

dp_set_dsc_on_rx(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2631

link_set_dsc_pps_packet(pipe_ctx, true, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2645

update_sst_payload(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

268

result = true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

280

result = true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

292

result = true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

298

if (result == true) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

338

payload.write = true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

343

return true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

779

result = true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

792

result = true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

840

dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

895

true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

902

pipe_ctx->stream_res.stream_enc, false, NULL, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

95

link_blank_dp_stream(dc->links[i], true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

971

dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

981

true,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

987

true,

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

740

return true;

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

793

link->is_dig_mapping_flexible = true;

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

801

ddc_service_init_data.is_dpia_link = true;

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

821

link->wa_flags.dp_mot_reset_segment = true;

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

823

return true;

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

833

if (init_params->is_dpia_link == true)

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

227

return true;

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

293

return true;

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

327

return true;

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

429

is_new_slot = true;

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

67

return true;

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

75

dongle_caps->extendedCapValid == true) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

198

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

300

current_payload.mot = is_end_of_payload ? payload->mot:true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

308

} while (retrieved < payload->length && ret == true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

321

bool success = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

340

payload.i2c_over_aux = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

347

payload.write = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

382

&payloads, address, write_size, write_buf, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

463

.write = true,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

525

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

529

result = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

61

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1232

link->dpcd_caps.dongle_caps.extendedCapValid = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1236

link->dpcd_caps.dongle_caps.extendedCapValid = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1381

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1539

mst = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1571

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2005

link->wa_flags.dpia_forced_tbt3_mode = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2078

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2129

(backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true : false;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2135

(general_edp_cap & DP_EDP_SET_POWER_CAP) ? true : false;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2224

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2250

bool is_uhbr13_5_supported = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2380

success = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2388

success = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2393

dp_trace_lt_total_count_increment(link, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2394

dp_trace_lt_result_update(link, status, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2432

success = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2449

dp_trace_lt_fail_count_update(link, fail_count, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2450

dp_trace_set_lt_end_timestamp(link, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2543

*auxless_support = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2545

*auxless_support = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2550

*auxwake_support = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

307

dpcd_write_rx_power_ctrl(link, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

326

link->wa_flags.dp_keep_receiver_powered = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

365

force_disable = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

371

force_disable = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

379

ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

632

found = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

718

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

742

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

775

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

782

initial_link_setting.use_link_rate_set = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

797

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

853

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

891

initial_link_setting.use_link_rate_set = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

906

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

944

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia.c

162

dp_tunnel_setting->should_use_dp_bw_allocation = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

247

link->dpia_bw_alloc_config.bw_alloc_enabled = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

248

ret = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

370

bool is_success = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

396

router_sets[j].is_valid = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

100

return_code = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

169

edp_set_psr_allow_active(link, &allow_active, true, false, NULL);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

170

allow_active = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

171

edp_set_psr_allow_active(link, &allow_active, true, false, NULL);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

174

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

182

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

258

edp_set_replay_allow_active(link, &allow_active, true, false, NULL);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

259

allow_active = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

260

edp_set_replay_allow_active(link, &allow_active, true, false, NULL);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

405

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

451

link->skip_fallback_on_link_loss = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

461

*has_left_work = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

475

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

485

*has_left_work = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

486

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

492

*has_left_work = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

513

*has_left_work = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

519

*out_link_loss = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

532

status = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

82

sink_status_changed = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

91

sink_status_changed = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

93

sink_status_changed = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c

162

link_enc->funcs->fec_set_ready(link_enc, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c

200

link_enc->funcs->fec_set_enable(link_enc, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c

68

dpcd_write_rx_power_ctrl(link, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1130

lt_settings->link_settings.use_link_rate_set == true) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1417

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1456

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1474

req_drv_setting_changed = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1497

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1504

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1672

edp_set_panel_assr(link, pipe_ctx, &panel_mode, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1678

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1718

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1736

do_fallback = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

471

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

480

bool done = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

494

bool done = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

505

bool locked = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

251

lt_settings->disallow_per_lane_settings = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

139

lt_settings->should_set_fec_ready = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

140

lt_settings->disallow_per_lane_settings = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

141

lt_settings->always_match_dpcd_with_hw_lane_settings = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

151

lt_settings->lttpr_early_tps2 = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_auxless.c

79

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

137

fec_enable = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1080

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1110

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1130

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1151

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1178

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1205

bool fw_set_brightness = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1235

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1256

use_hpo_dp_link_enc = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

165

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

234

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

266

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

278

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

283

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

309

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

323

return edp_set_backlight_level_nits(link, true,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

333

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

370

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

391

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

403

link->dc->hwss.edp_power_control(link, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

405

link->dc->hwss.edp_wait_for_hpd_ready(link, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

407

link->dc->hwss.edp_backlight_control(link, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

415

link->dc->hwss.edp_power_control(link, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

416

link->dc->hwss.edp_wait_for_hpd_ready(link, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

420

link->dc->hwss.edp_backlight_control(link, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

423

dpcd_write_rx_power_ctrl(link, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

443

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

523

alpm_config.bits.ENABLE = (enable ? true : false);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

581

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

598

if ((allow_active != NULL) && (*allow_active == true) && (link->type == dc_connection_none)) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

630

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

64

panel_mode_edp = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

648

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

777

edp_power_alpm_dpcd_enable(link, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

789

vtotal_control.bits.ENABLE = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

823

psr_context->psrSupportedDisplayConfig = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

836

psr_context->rfb_update_auto_en = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

855

psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

858

psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

904

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

933

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

967

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

984

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c

132

return true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c

231

result = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c

71

link->is_hpd_filter_disabled = true;

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

89

REG_SET_3(MMHUBBUB_WARMUP_CONTROL_STATUS, 0, MMHUBBUB_WARMUP_EN, true,

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

90

MMHUBBUB_WARMUP_SW_INT_EN, true,

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

281

found = true;

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

300

found = true;

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

279

MPCC_OGAM_MEM_PWR_DIS, power_on == true ? 1:0);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

291

MPCC_OGAM_LUT_RAM_SEL, is_ram_a == true ? 0:1);

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

455

mpc20_power_on_ogam_lut(mpc, mpcc_id, true);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1237

mpc3_power_on_shaper_3dlut(mpc, rmu_idx, true);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1300

return true;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

196

MPCC_OGAM_LUT_HOST_SEL, is_ram_a == true ? 0:1);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

370

mpc3_power_on_ogam_lut(mpc, mpcc_id, true);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

483

MPC_RMU_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

832

MPC_RMU0_MEM_PWR_DIS, power_on == true ? 1:0);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

844

MPC_RMU1_MEM_PWR_DIS, power_on == true ? 1:0);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

854

if (power_status_shaper != 0 && power_on == true)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

857

if (power_status_3dlut != 0 && power_on == true)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

87

return true;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

879

mpc3_power_on_shaper_3dlut(mpc, rmu_idx, true);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

901

return true;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

923

MPC_RMU_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

959

*is_12bits_color_channel = true;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

964

*is_17x17x17 = true;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

981

MPC_RMU_3DLUT_30BIT_EN, is_color_channel_12bits == true ? 0:1);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

134

MPCC_MCM_1DLUT_LUT_HOST_SEL, is_ram_a == true ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

283

mpc32_power_on_blnd_lut(mpc, mpcc_id, true);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

298

return true;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

338

MPCC_MCM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

693

MPCC_MCM_3DLUT_MEM_PWR_DIS, power_on == true ? 1:0);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

704

if (power_status_shaper != 0 && power_on == true)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

707

if (power_status_3dlut != 0 && power_on == true)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

727

mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

749

return true;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

786

*is_12bits_color_channel = true;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

791

*is_17x17x17 = true;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

809

MPCC_MCM_3DLUT_30BIT_EN, is_color_channel_12bits == true ? 0:1);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

88

MPCC_MCM_1DLUT_MEM_PWR_FORCE, power_on == true ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

903

MPCC_MCM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

926

mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

989

return true;

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

104

*is_17x17x17 = true;

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

131

mpc32_power_on_blnd_lut(mpc, mpcc_id, true);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

147

mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

165

mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

99

*is_12bits_color_channel = true;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1300

ret = true;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1327

return true;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1426

return true;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1438

optc1_set_blank_data_double_buffer(optc, true);

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1439

optc1_set_timing_double_buffer(optc, true);

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1479

return true;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1541

return true;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1597

return true;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

293

optc->funcs->set_vtg_params(optc, dc_crtc_timing, true);

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

505

if (optc->funcs->is_optc_underflow_occurred(optc) == true)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

551

return true;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

574

return true;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

642

return true;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

684

TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

721

return true;

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

76

return true;

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

115

return true;

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

116

TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

132

TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

356

optc3_set_timing_double_buffer(optc, true);

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

62

TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

99

TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

117

return true;

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

150

return true;

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

176

return true;

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

127

return true;

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

149

return true;

sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

167

return true;

sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

199

return true;

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

134

return true;

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

169

return true;

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

196

return true;

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

269

return true;

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

202

return true;

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

239

return true;

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

333

program_manual_trigger = true;

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

464

return true;

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

67

first_preferred_memory_for_opp[opp_id[i]] = true;

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

75

second_preferred_memory_for_opp[opp_id[i]] = true;

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

85

second_preferred_memory_for_opp[i] = true;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

385

bool all_mpcc_disabled = true, all_opp_disabled = true;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

386

bool all_optc_disabled = true, all_stream_disabled = true;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

53

return true;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1018

dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1030

dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1092

dc->caps.dual_link_dvi = true;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1093

dc->caps.disable_dp_clk_share = true;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1171

return true;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

387

.argb8888 = true,

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

389

.fp16 = true

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

406

.enable_legacy_fast_update = true,

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

615

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

616

.flags.bits.IS_TPS3_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

853

at_least_one_pipe = true;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

898

return true;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1089

return true;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1172

true,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1281

return true;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1376

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1388

dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1528

return true;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

407

.argb8888 = true,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

409

.fp16 = true

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

428

.enable_legacy_fast_update = true,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

437

.nv12 = true,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

570

hws->wa.blnd_crtc_trigger = true;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

659

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

660

.flags.bits.IS_TPS3_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

932

return true;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

937

return true;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

981

result = true;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1010

return true;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1247

dc->caps.dual_link_dvi = true;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1289

CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1409

return true;

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

412

.argb8888 = true,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

414

.fp16 = true

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

433

.enable_legacy_fast_update = true,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

616

.hdmi_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

618

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

619

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

620

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

621

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

904

result = true;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1088

dc->caps.dual_link_dvi = true;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1089

dc->caps.psp_setup_panel_mode = true;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1126

&clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1277

return true;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

510

.argb8888 = true,

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

512

.fp16 = true

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

529

.disable_clock_gate = true,

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

530

.enable_legacy_fast_update = true,

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

573

return true;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

700

.hdmi_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

702

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

703

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

704

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

705

.flags.bits.IS_TPS4_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1051

dc->caps.disable_dp_clk_share = true;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1060

return true;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1109

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1119

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1131

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1249

dc->caps.disable_dp_clk_share = true;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1258

return true;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1307

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1317

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1328

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1446

dc->caps.disable_dp_clk_share = true;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1455

return true;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

401

.argb8888 = true,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

709

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

710

.flags.bits.IS_TPS3_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

911

dc->caps.dual_link_dvi = true;

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

922

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

933

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1061

dc->caps.disable_dp_clk_share = true;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1070

return true;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1121

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1131

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1143

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1261

dc->caps.disable_dp_clk_share = true;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1270

return true;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1321

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1332

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1342

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1458

dc->caps.disable_dp_clk_share = true;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1467

return true;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

403

.argb8888 = true,

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

405

.fp16 = true

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

422

.enable_legacy_fast_update = true,

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

715

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

716

.flags.bits.IS_TPS3_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

919

dc->caps.dual_link_dvi = true;

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

931

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

943

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1170

mpo_enabled = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1181

video_down_scaled = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1184

video_large = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1188

desktop_large = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1190

dcc_disabled = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1309

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1357

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1362

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1435

&clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1485

dc->config.is_vmin_only_asic = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1665

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

511

.per_pixel_alpha = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

514

.argb8888 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

515

.nv12 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

516

.fp16 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

534

.sanity_checks = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

537

.clock_trace = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

549

.force_single_disp_pipe_split = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

551

.voltage_align_fclk = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

552

.disable_stereo_support = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

553

.vsr_support = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

555

.az_endpoint_mute_only = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

559

.enable_legacy_fast_update = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

726

.hdmi_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

727

.dp_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

728

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

729

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

730

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

731

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

854

hws->wa.DEGVIDCN10_253 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

855

hws->wa.false_optc_underflow = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

856

hws->wa.DEGVIDCN10_254 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

866

hws->wa.wait_hubpret_read_start_during_mpo_transition = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1340

res_ctx->is_dsc_acquired[pipe_idx] = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1347

res_ctx->is_dsc_acquired[dsc_old->inst] = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1355

res_ctx->is_dsc_acquired[i] = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1530

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1668

dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1675

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1831

avoid_split = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1833

force_split = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1848

avoid_split = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1856

avoid_split = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1869

avoid_split = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1943

merge[i] = true; /* 2 -> 1 MPC */

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1948

merge[i] = true; /* 4 -> 2 MPC */

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1951

merge[i] = true; /* 4 -> 1 MPC */

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1957

merge[i] = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1969

merge[i] = true; /* exit ODM */

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1975

merge[i] = true; /* 4 -> 2 ODM */

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1978

merge[i] = true; /* exit ODM */

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1986

merge[i] = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2030

out = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2083

dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2117

out = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2257

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2284

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2388

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2434

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2435

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2436

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2437

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2474

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2480

dc->work_arounds.dedcn20_305_wa = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2519

&clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2729

dc->debug.disable_dpp_power_gate = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2730

dc->debug.disable_hubp_power_gate = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2754

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

670

.per_pixel_alpha = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

673

.argb8888 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

674

.nv12 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

675

.fp16 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

676

.p010 = true

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

709

.clock_trace = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

710

.disable_pplib_clock_request = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

714

.vsr_support = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

718

.scl_reset_length10 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

721

.enable_legacy_fast_update = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

905

.hdmi_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

906

.dp_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

907

.fec_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

908

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

909

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

910

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

911

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1116

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1117

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1118

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1158

dc->work_arounds.no_connect_phy_config = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1159

dc->work_arounds.dedcn20_305_wa = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1179

&clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1292

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

576

.per_pixel_alpha = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

579

.argb8888 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

581

.fp16 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

601

.disable_dmcu = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

603

.clock_trace = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

604

.disable_pplib_clock_request = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

608

.vsr_support = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

610

.az_endpoint_mute_only = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

612

.disable_pplib_wm_range = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

613

.scl_reset_length10 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

616

.enable_tri_buf = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

617

.enable_legacy_fast_update = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

782

.hdmi_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

783

.dp_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

784

.fec_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

785

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

786

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

787

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

788

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

96

.dcc_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1177

hws->wa.DEGVIDCN21 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1178

hws->wa.disallow_self_refresh_during_multi_plane_transition = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1193

.hdmi_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1194

.dp_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1195

.fec_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1196

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1197

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1198

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1199

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1419

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1420

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1421

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1422

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1423

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1460

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1500

&clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1691

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

586

.per_pixel_alpha = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

589

.argb8888 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

590

.nv12 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

591

.fp16 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

592

.p010 = true

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

613

.clock_trace = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

614

.disable_pplib_clock_request = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

619

.vsr_support = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

623

.scl_reset_length10 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

624

.sanity_checks = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

626

.usbc_combo_phy_reset_wa = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

627

.dmub_command_table = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

628

.use_max_lb = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

629

.enable_legacy_fast_update = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

640

.optimize_edp_link_rate = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

792

out = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

878

dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

911

out = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1237

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1262

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1448

res_ctx->is_mpc_3dlut_acquired[i] = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1457

ret = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1479

ret = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1491

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1517

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1579

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1652

out = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1745

repopulate_pipes = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1760

repopulate_pipes = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1806

newly_split[hsplit_pipe->pipe_idx] = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1807

repopulate_pipes = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1827

newly_split[pipe_4to1->pipe_idx] = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1846

newly_split[pipe_4to1->pipe_idx] = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1873

out = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1956

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2002

stream_status->fpo_in_use = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2004

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2058

out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, true);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2315

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2316

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2317

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2318

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2354

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2356

dc->caps.vtotal_limited_by_fp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2421

&clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2606

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

685

.per_pixel_alpha = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

688

.argb8888 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

689

.nv12 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

690

.fp16 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

691

.p010 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

712

.disable_dmcu = true, //No DMCU on DCN30

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

714

.clock_trace = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

715

.disable_pplib_clock_request = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

719

.vsr_support = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

723

.scl_reset_length10 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

727

.dmub_command_table = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

728

.use_max_lb = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

729

.exit_idle_opt_for_cursor_updates = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

913

.hdmi_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

914

.dp_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

915

.fec_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

916

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

917

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

918

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

919

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1197

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1222

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1284

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1318

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1443

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1444

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1445

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1446

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1447

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1483

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1537

&clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1713

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

656

.per_pixel_alpha = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

659

.argb8888 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

660

.nv12 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

661

.fp16 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

662

.p010 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

683

.disable_dmcu = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

685

.clock_trace = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

688

.disable_clock_gate = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

689

.disable_pplib_clock_request = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

690

.disable_pplib_wm_range = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

694

.vsr_support = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

697

.scl_reset_length10 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

701

.dmub_command_table = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

703

.exit_idle_opt_for_cursor_updates = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

704

.enable_legacy_fast_update = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

869

.hdmi_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

870

.dp_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

871

.fec_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

872

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

873

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

874

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

875

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

100

.exit_idle_opt_for_cursor_updates = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1233

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1234

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1235

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1236

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1238

dc->caps.vtotal_limited_by_fp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1274

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1333

&clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

137

.per_pixel_alpha = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

139

.argb8888 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

140

.nv12 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

141

.fp16 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

142

.p010 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1500

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

725

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

760

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

83

.disable_dmcu = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

833

.hdmi_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

834

.dp_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

835

.fec_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

836

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

837

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

838

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

839

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

85

.clock_trace = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

86

.disable_pplib_clock_request = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

90

.vsr_support = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

94

.scl_reset_length10 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

949

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

98

.dmub_command_table = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

985

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

99

.use_max_lb = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

100

.exit_idle_opt_for_cursor_updates = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1177

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1178

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1179

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1180

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1182

dc->caps.vtotal_limited_by_fp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1218

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1220

dc->config.dc_mode_clk_limit_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1265

&clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

134

.per_pixel_alpha = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

136

.argb8888 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

137

.nv12 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

138

.fp16 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

139

.p010 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1432

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

686

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

721

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

788

.hdmi_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

789

.dp_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

790

.fec_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

791

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

792

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

793

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

794

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

83

.disable_dmcu = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

85

.clock_trace = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

86

.disable_pplib_clock_request = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

894

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

90

.vsr_support = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

929

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

94

.scl_reset_length10 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

98

.dmub_command_table = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

99

.use_max_lb = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1079

.hdmi_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1080

.dp_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1081

.fec_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1082

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1083

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1084

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1085

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1535

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1560

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1636

pipes[i].pipe.src.hostvm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1665

upscaled = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1672

pipes[pipe_cnt].pipe.src.immediate_flip = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1674

pipes[pipe_cnt].pipe.src.gpuvm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1707

dc->config.enable_4to1MPC = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1711

pipes[0].pipe.src.unbounded_req_mode = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1781

out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, true);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1913

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1914

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1917

dc->caps.dp_hpo = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1918

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1919

dc->caps.edp_dsc_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1920

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1921

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1922

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1923

dc->caps.zstate_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1963

dc->config.use_pipe_ctx_sync_logic = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1964

dc->config.disable_hbr_audio_dp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1978

dc->caps.vbios_lttpr_aware = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2034

&clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2213

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

832

.per_pixel_alpha = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

835

.argb8888 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

836

.nv12 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

837

.fp16 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

838

.p010 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

859

.disable_dmcu = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

861

.clock_trace = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

866

.vsr_support = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

870

.scl_reset_length10 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

874

.dmub_command_table = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

875

.pstate_enabled = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

876

.use_max_lb = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

879

.vga = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

880

.i2c = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

882

.dscl = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

883

.cm = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

884

.mpc = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

885

.optc = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

886

.vpg = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

887

.afmt = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

890

.disable_z10 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

891

.enable_legacy_fast_update = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

892

.enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

904

.optimize_edp_link_rate = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1137

.hdmi_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1138

.dp_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1139

.fec_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1140

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1141

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1142

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1143

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1593

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1618

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1842

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1843

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1846

dc->caps.dp_hpo = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1847

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1848

dc->caps.edp_dsc_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1849

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1850

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1851

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1852

dc->caps.seamless_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1854

dc->caps.zstate_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1896

dc->config.use_pipe_ctx_sync_logic = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1910

dc->caps.vbios_lttpr_aware = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1918

dc->debug.disable_dpp_power_gate = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1919

dc->debug.disable_hubp_power_gate = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1960

&clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2130

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

844

.per_pixel_alpha = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

847

.argb8888 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

848

.nv12 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

849

.fp16 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

850

.p010 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

873

.enable_z9_disable_interface = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

875

.psr_skip_crtc_disable = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

876

.replay_skip_crtc_disabled = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

877

.disable_dmcu = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

879

.clock_trace = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

886

.vsr_support = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

890

.scl_reset_length10 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

894

.dmub_command_table = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

895

.pstate_enabled = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

896

.use_max_lb = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

899

.vga = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

900

.i2c = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

902

.dscl = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

903

.cm = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

904

.mpc = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

905

.optc = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

906

.vpg = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

907

.afmt = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

913

.dpp = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

914

.dsc = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

915

.hdmistream = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

916

.hdmichar = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

917

.dpstream = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

919

.symclk32_le = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

920

.symclk_fe = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

921

.physymclk = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

922

.dpiasymclk = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

926

.seamless_boot_odm_combine = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

927

.enable_legacy_fast_update = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

929

.disable_dsc_power_gate = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

940

.optimize_edp_link_rate = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1077

.hdmi_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1078

.dp_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1079

.fec_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1080

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1081

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1082

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1083

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1535

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1560

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1661

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1693

pipes[pipe_cnt].pipe.src.immediate_flip = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1792

dc->config.enable_4to1MPC = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1800

pipes[0].pipe.src.unbounded_req_mode = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1882

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1883

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1886

dc->caps.dp_hpo = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1887

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1888

dc->caps.edp_dsc_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1889

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1890

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1891

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1939

dc->caps.vbios_lttpr_aware = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1982

&clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2151

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

831

.per_pixel_alpha = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

834

.argb8888 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

835

.nv12 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

836

.fp16 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

837

.p010 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

858

.disable_z10 = true, /*hw not support it*/

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

859

.disable_dmcu = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

861

.clock_trace = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

866

.vsr_support = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

870

.scl_reset_length10 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

874

.dmub_command_table = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

875

.pstate_enabled = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

876

.use_max_lb = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

879

.vga = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

880

.i2c = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

882

.dscl = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

883

.cm = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

884

.mpc = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

885

.optc = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

886

.vpg = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

887

.afmt = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

890

.enable_legacy_fast_update = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

902

.optimize_edp_link_rate = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1071

.hdmi_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1072

.dp_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1073

.fec_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1074

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1075

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1076

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1077

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1528

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1553

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1637

pipes[pipe_cnt].pipe.src.immediate_flip = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1677

dc->config.enable_4to1MPC = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1682

pipes[0].pipe.src.unbounded_req_mode = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1758

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1759

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1762

dc->caps.dp_hpo = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1763

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1764

dc->caps.edp_dsc_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1765

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1766

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1767

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1815

dc->caps.vbios_lttpr_aware = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1858

&clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2019

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

826

.per_pixel_alpha = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

829

.argb8888 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

830

.nv12 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

831

.fp16 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

832

.p010 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

853

.disable_z10 = true, /*hw not support it*/

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

854

.disable_dmcu = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

856

.clock_trace = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

861

.vsr_support = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

865

.scl_reset_length10 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

869

.dmub_command_table = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

870

.pstate_enabled = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

871

.use_max_lb = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

874

.vga = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

875

.i2c = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

877

.dscl = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

878

.cm = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

879

.mpc = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

880

.optc = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

881

.vpg = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

882

.afmt = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

885

.enable_legacy_fast_update = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

896

.optimize_edp_link_rate = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1027

.hdmi_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1028

.dp_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1029

.fec_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1030

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1031

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1032

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1033

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1530

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1559

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1612

res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1613

ret = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1633

ret = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1761

context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1847

dc_state_set_stream_cursor_subvp_limit(stream, context, true);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1901

single_display_subvp = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1925

pipes[pipe_cnt].pipe.src.gpuvm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1971

subvp_in_use = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2022

context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2231

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2232

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2235

dc->caps.dp_hpo = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2236

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2237

dc->caps.edp_dsc_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2238

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2239

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2240

dc->caps.seamless_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2242

dc->caps.vtotal_limited_by_fp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2277

dc->caps.color.mpc.preblend = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2280

dc->config.use_pipe_ctx_sync_logic = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2282

dc->config.dc_mode_clk_limit_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2283

dc->config.enable_windowed_mpo_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2284

dc->config.disable_hbr_audio_dp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2297

dc->caps.vbios_lttpr_aware = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2340

&clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2523

dc->dml2_options.use_native_soc_bb_construction = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2524

dc->dml2_options.minimize_dispclk_using_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2549

dc->dml2_options.map_dc_pipes_with_callbacks = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2556

dc->dml2_dc_power_options.use_clock_dc_limits = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2558

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

664

.per_pixel_alpha = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

667

.argb8888 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

668

.nv12 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

669

.fp16 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

670

.p010 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

691

.disable_dmcu = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

693

.clock_trace = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

698

.vsr_support = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

702

.scl_reset_length10 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

706

.dmub_command_table = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

715

.optc = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

718

.use_max_lb = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

720

.exit_idle_opt_for_cursor_updates = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

723

.enable_single_display_2to1_odm_policy = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

726

.enable_double_buffered_dsc_pg_support = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

729

.alloc_extra_way_for_cursor = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

732

.override_dispclk_programming = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

738

.disable_dp_plus_plus_wa = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

742

.disable_stutter_for_wm_program = true

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

167

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

179

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

190

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

207

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

219

is_center_timing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

225

is_center_timing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

238

psr_capable = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

407

pipes[0].pipe.src.unbounded_req_mode = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

481

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

601

is_native_scaling = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

625

disallow = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

675

drr_pipe_found = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

683

result = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

736

drr_pipe_found = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

745

result = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1021

.hdmi_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1022

.dp_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1023

.fec_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1024

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1025

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1026

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1027

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1510

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1539

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1734

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1735

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1736

dc->caps.dp_hpo = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1737

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1738

dc->caps.edp_dsc_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1739

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1740

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1742

dc->caps.vtotal_limited_by_fp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1777

dc->caps.color.mpc.preblend = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1780

dc->config.use_pipe_ctx_sync_logic = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1782

dc->config.dc_mode_clk_limit_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1783

dc->config.enable_windowed_mpo_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1784

dc->config.disable_hbr_audio_dp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1797

dc->caps.vbios_lttpr_aware = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1840

&clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2018

dc->dml2_options.use_native_soc_bb_construction = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2019

dc->dml2_options.minimize_dispclk_using_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2047

dc->dml2_dc_power_options.use_clock_dc_limits = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2049

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

660

.per_pixel_alpha = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

663

.argb8888 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

664

.nv12 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

665

.fp16 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

666

.p010 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

687

.disable_dmcu = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

689

.clock_trace = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

694

.vsr_support = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

698

.scl_reset_length10 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

702

.dmub_command_table = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

711

.optc = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

714

.use_max_lb = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

716

.exit_idle_opt_for_cursor_updates = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

717

.enable_single_display_2to1_odm_policy = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

720

.enable_double_buffered_dsc_pg_support = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

723

.alloc_extra_way_for_cursor = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

726

.override_dispclk_programming = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

735

.disable_dc_mode_overwrite = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1060

.hdmi_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1061

.dp_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1062

.fec_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1063

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1064

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1065

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1066

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1626

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1665

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1861

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1862

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1865

dc->caps.dp_hpo = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1866

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1868

dc->caps.edp_dsc_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1869

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1870

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1871

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1872

dc->caps.seamless_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1874

dc->caps.zstate_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1875

dc->caps.ips_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1877

dc->caps.vtotal_limited_by_fp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1912

dc->caps.color.mpc.preblend = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1927

dc->caps.sequential_ono = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1930

dc->config.use_pipe_ctx_sync_logic = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1933

dc->config.disable_hbr_audio_dp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1946

dc->caps.vbios_lttpr_aware = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1990

&clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2178

dc->dml2_options.use_native_soc_bb_construction = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2181

dc->dml2_options.minimize_dispclk_using_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2189

dc->dml2_options.override_det_buffer_size_kbytes = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2194

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

686

.per_pixel_alpha = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

689

.argb8888 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

690

.nv12 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

691

.fp16 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

692

.p010 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

713

.disable_dmcu = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

715

.clock_trace = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

720

.disable_dpp_power_gate = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

721

.disable_hubp_power_gate = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

722

.disable_optc_power_gate = true, /*should the same as above two*/

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

723

.disable_hpo_power_gate = true, /*dmubfw force domain25 on*/

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

725

.disable_dsc_power_gate = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

726

.vsr_support = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

730

.scl_reset_length10 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

734

.dmub_command_table = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

735

.pstate_enabled = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

736

.use_max_lb = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

740

.i2c = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

742

.dscl = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

743

.cm = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

744

.mpc = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

745

.optc = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

746

.vpg = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

747

.afmt = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

752

.dpp = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

753

.dsc = true,/*dscclk and dsc pg*/

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

754

.hdmistream = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

755

.hdmichar = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

756

.dpstream = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

757

.symclk32_se = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

758

.symclk32_le = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

759

.symclk_fe = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

761

.dpiasymclk = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

765

.enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

767

.using_dml2 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

768

.support_eDP1_5 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

770

.enable_legacy_fast_update = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

771

.enable_single_display_2to1_odm_policy = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

778

.enable_double_buffered_dsc_pg_support = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

781

.ignore_pg = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

782

.psp_disabled_wa = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

787

.disable_timeout = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

798

.optimize_edp_link_rate = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1040

.hdmi_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1041

.dp_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1042

.fec_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1043

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1044

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1045

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1046

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1606

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1645

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1834

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1835

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1838

dc->caps.dp_hpo = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1839

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1841

dc->caps.edp_dsc_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1842

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1843

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1844

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1845

dc->caps.seamless_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1847

dc->caps.zstate_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1848

dc->caps.ips_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1850

dc->caps.vtotal_limited_by_fp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1885

dc->caps.color.mpc.preblend = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1899

dc->config.use_pipe_ctx_sync_logic = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1903

dc->config.use_assr_psp_message = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1917

dc->caps.vbios_lttpr_aware = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1962

&clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2151

dc->dml2_options.use_native_soc_bb_construction = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2154

dc->dml2_options.minimize_dispclk_using_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2162

dc->dml2_options.override_det_buffer_size_kbytes = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2167

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

666

.per_pixel_alpha = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

669

.argb8888 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

670

.nv12 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

671

.fp16 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

672

.p010 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

693

.disable_dmcu = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

695

.clock_trace = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

700

.disable_dpp_power_gate = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

701

.disable_hubp_power_gate = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

702

.disable_optc_power_gate = true, /*should the same as above two*/

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

703

.disable_hpo_power_gate = true, /*dmubfw force domain25 on*/

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

705

.disable_dsc_power_gate = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

706

.vsr_support = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

710

.scl_reset_length10 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

714

.dmub_command_table = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

715

.pstate_enabled = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

716

.use_max_lb = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

720

.i2c = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

722

.dscl = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

723

.cm = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

724

.mpc = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

725

.optc = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

726

.vpg = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

727

.afmt = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

732

.dpp = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

733

.dsc = true,/*dscclk and dsc pg*/

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

734

.hdmistream = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

735

.hdmichar = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

736

.dpstream = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

737

.symclk32_se = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

739

.symclk_fe = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

741

.dpiasymclk = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

745

.enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

747

.using_dml2 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

748

.support_eDP1_5 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

750

.enable_legacy_fast_update = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

751

.enable_single_display_2to1_odm_policy = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

758

.enable_double_buffered_dsc_pg_support = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

761

.ignore_pg = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

762

.psp_disabled_wa = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

767

.notify_dpia_hr_bw = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

778

.optimize_edp_link_rate = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1041

.hdmi_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1042

.dp_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1043

.fec_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1044

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1045

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1046

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1047

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1607

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1646

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1834

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1835

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1838

dc->caps.dp_hpo = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1839

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1841

dc->caps.edp_dsc_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1842

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1843

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1844

dc->caps.is_apu = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1845

dc->caps.seamless_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1847

dc->caps.zstate_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1848

dc->caps.ips_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1850

dc->caps.vtotal_limited_by_fp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1885

dc->caps.color.mpc.preblend = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1900

dc->caps.sequential_ono = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1903

dc->config.use_pipe_ctx_sync_logic = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1905

dc->config.disable_hbr_audio_dp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1918

dc->caps.vbios_lttpr_aware = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1963

&clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2151

dc->dml2_options.use_native_soc_bb_construction = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2154

dc->dml2_options.minimize_dispclk_using_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2162

dc->dml2_options.override_det_buffer_size_kbytes = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2167

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

667

.per_pixel_alpha = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

670

.argb8888 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

671

.nv12 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

672

.fp16 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

673

.p010 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

694

.disable_dmcu = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

696

.clock_trace = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

701

.disable_dpp_power_gate = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

702

.disable_hubp_power_gate = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

703

.disable_optc_power_gate = true, /*should the same as above two*/

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

704

.disable_hpo_power_gate = true, /*dmubfw force domain25 on*/

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

706

.disable_dsc_power_gate = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

707

.vsr_support = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

711

.scl_reset_length10 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

715

.dmub_command_table = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

716

.pstate_enabled = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

717

.use_max_lb = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

721

.i2c = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

723

.dscl = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

724

.cm = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

725

.mpc = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

726

.optc = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

727

.vpg = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

728

.afmt = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

733

.dpp = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

734

.dsc = true,/*dscclk and dsc pg*/

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

735

.hdmistream = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

736

.hdmichar = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

737

.dpstream = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

738

.symclk32_se = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

739

.symclk32_le = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

740

.symclk_fe = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

742

.dpiasymclk = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

746

.enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

748

.using_dml2 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

749

.support_eDP1_5 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

751

.enable_legacy_fast_update = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

752

.enable_single_display_2to1_odm_policy = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

759

.enable_double_buffered_dsc_pg_support = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

762

.ignore_pg = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

763

.psp_disabled_wa = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

768

.disable_timeout = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

779

.optimize_edp_link_rate = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1019

.hdmi_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1020

.dp_ycbcr420_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1021

.fec_supported = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1022

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1023

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1024

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1025

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1535

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1564

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1668

dc_state_set_stream_cursor_subvp_limit(stream, context, true);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1884

dc->caps.cursor_not_scaled = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1909

dc->caps.post_blend_color_processing = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1910

dc->caps.force_dp_tps4_for_cp2520 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1911

dc->caps.dp_hpo = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1912

dc->caps.dp_hdmi21_pcon_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1913

dc->caps.edp_dsc_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1914

dc->caps.extended_aux_timeout_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1915

dc->caps.dmcub_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1917

dc->caps.vtotal_limited_by_fp2 = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1955

dc->caps.color.mpc.preblend = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1956

dc->config.use_spl = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1957

dc->config.prefer_easf = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1979

dc->config.dc_mode_clk_limit_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1980

dc->config.enable_windowed_mpo_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1981

dc->config.set_pipe_unlock_order = true; /* Need to ensure DET gets freed before allocating */

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1995

dc->caps.vbios_lttpr_aware = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2038

&clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2217

dc->dml2_options.use_native_soc_bb_construction = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2218

dc->dml2_options.minimize_dispclk_using_odm = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2219

dc->dml2_options.map_dc_pipes_with_callbacks = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2220

dc->dml2_options.force_tdlut_enable = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2247

dc->caps.scl_caps.sharpener_support = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2251

dc->dml2_dc_power_options.use_clock_dc_limits = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2253

return true;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

655

.per_pixel_alpha = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

658

.argb8888 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

659

.nv12 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

660

.fp16 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

661

.p010 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

682

.disable_dmcu = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

684

.clock_trace = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

689

.vsr_support = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

693

.scl_reset_length10 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

697

.dmub_command_table = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

706

.optc = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

709

.use_max_lb = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

712

.exit_idle_opt_for_cursor_updates = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

713

.using_dml2 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

714

.using_dml21 = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

715

.enable_single_display_2to1_odm_policy = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

718

.enable_double_buffered_dsc_pg_support = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

721

.alloc_extra_way_for_cursor = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

732

.enable = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

733

.enable_offload_flip = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

734

.enable_stall_recovery = true,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1096

*enable_easf_h = true;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1098

*enable_easf_v = true;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1099

*enable_easf_h = true;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1109

*enable_easf_h = true;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1111

*enable_easf_v = true;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1112

*enable_easf_h = true;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1161

return true;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1288

fmt.sign = true;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1307

dscl_prog_data->easf_v_en = true;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1471

dscl_prog_data->easf_h_en = true;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

17

return true;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

25

return true;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

34

return true;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

43

return true;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

521

*flip_vert_scan_dir = true;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

522

*flip_horz_scan_dir = true;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

524

*orthogonal_rotation = true;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

525

*flip_horz_scan_dir = true;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

527

*orthogonal_rotation = true;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

528

*flip_vert_scan_dir = true;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

808

skip_easf = true;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

818

skip_easf = true;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

830

skip_easf = true;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

839

return true;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

885

enable_isharp = true;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

995

return true;

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

134

return true;

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

26

return true;

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

49

return true;

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

76

return true;

sys/dev/pci/drm/amd/display/dc/virtual/virtual_link_encoder.c

129

return true;

sys/dev/pci/drm/amd/display/dc/virtual/virtual_link_encoder.c

33

const struct dc_stream_state *stream) { return true; }

sys/dev/pci/drm/amd/display/dc/virtual/virtual_stream_encoder.c

156

return true;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6563

return true;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6593

return true;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6614

return true;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6657

return true;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6682

return true;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6705

return true;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1141

return true;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1156

return true;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1249

dmub->reg_inbox0.is_pending = true;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

442

return true;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

489

dmub->sw_init = true;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

766

dmub->hw_funcs.enable_reg_inbox0_rsp_int(dmub, true);

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

768

dmub->hw_funcs.enable_reg_outbox0_rdy_int(dmub, true);

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

799

dmub->hw_init = true;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

883

return true;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

888

return true;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

913

bool hw_on = true;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv_stat.c

125

notify->pending_notification = true;

sys/dev/pci/drm/amd/display/include/grph_object_id.h

309

return true;

sys/dev/pci/drm/amd/display/include/logger_interface.h

61

static bool print_not_impl = true; \

sys/dev/pci/drm/amd/display/include/logger_interface.h

62

if (print_not_impl == true) { \

sys/dev/pci/drm/amd/display/include/signal_types.h

114

return true;

sys/dev/pci/drm/amd/display/include/signal_types.h

127

return true;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1086

use_eetf = true;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1121

is_clipped = true;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1177

return true;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1220

ret = true;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1598

return true;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1665

return true;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1694

return true;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1701

return true;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1705

return true;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1710

return true;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1805

true);

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1813

ret = true;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1851

ret = true;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1863

ret = true;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1872

ret = true;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1884

ret = true;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1902

ret = true;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1923

bool do_clamping = true;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1930

if (output_tf->type == TF_TYPE_PREDEFINED && can_rom_be_used == true &&

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1933

return true;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1936

return true;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

403

bool ret = true;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

663

return true;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

672

return true;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

681

return true;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

779

return true;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

861

mod_color_set_table_init_state(type_pq_table, true);

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

906

mod_color_set_table_init_state(type_de_pq_table, true);

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

958

ret = true;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

1058

in_out_vrr->supported = true;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

1111

in_out_vrr->fixed.fixed_active = true;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

1113

in_out_vrr->fixed.fixed_active = true;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

1126

in_out_vrr->adjust.allow_otg_v_count_halt = (in_config->state == VRR_STATE_ACTIVE_FIXED) ? true : false;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

1201

in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup = true;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

258

in_out_vrr->fixed.ramping_done = true;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

271

in_out_vrr->fixed.ramping_done = true;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

316

in_out_vrr->btr.btr_active = true;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

468

update = true;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

480

in_out_vrr->fixed.fixed_active = true;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

483

update = true;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

518

in_vrr->flip_interval.program_flip_interval_workaround = true;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

530

in_vrr->flip_interval.program_flip_interval_workaround = true;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

531

in_vrr->flip_interval.flip_interval_workaround_active = true;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

549

return true;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

553

return true;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

555

return true;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

557

return true;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

690

infopacket->valid = true;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

869

infopacket->valid = true;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

884

infopacket->valid = true;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

902

infopacket->valid = true;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

920

infopacket->valid = true;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

970

if (true == pack_sdp_v1_3 &&

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

971

true == dc_is_dp_signal(stream->signal) &&

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

263

display->adjust.disable == true &&

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.c

272

display->adjust.disable = true;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp2_transition.c

204

adjust->hdcp2.force_sw_locality_check = true;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp2_transition.c

525

adjust->hdcp2.force_sw_locality_check = true;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

157

bool success = true;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

228

bool success = true;

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

146

stereo3dSupport = true;

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

187

info_packet->valid = true;

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

209

info_packet->valid = true;

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

219

info_packet->valid = true;

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

293

info_packet->valid = true;

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

469

hdmi_vic_mode = true;

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

521

info_packet->valid = true;

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

551

info_packet->valid = true;

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

563

info_packet->valid = true;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

1040

return true;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

628

params, ram_table, true);

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

776

return true;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

781

fill_iram_v_2_3((struct iram_table_v_2_2 *)ram_table, params, true);

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

785

fill_iram_v_2_3((struct iram_table_v_2_2 *)ram_table, params, true);

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

825

isPSRSUSupported = true;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

847

isPSRSUSupported = true;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

914

link->psr_settings.psr_frame_capture_indication_req = true;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

956

return true;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

975

return true;

sys/dev/pci/drm/amd/include/amd_pcie_helpers.h

31

return true;

sys/dev/pci/drm/amd/include/amd_pcie_helpers.h

39

return true;

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1117

amdgpu_gfx_off_ctrl(adev, true);

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

502

adev->pm.ac_power = true;

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

598

adev->pm.dpm.uvd_active = true;

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

632

adev->pm.dpm.vce_active = true;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

135

ret = amdgpu_pm_dev_state_check(adev, true);

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

4506

return true;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

4529

return true;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

4758

adev->pm.sysfs_initialized = true;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

5011

ret = amdgpu_pm_dev_state_check(adev, true);

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

529

adev->pm.pp_force_state_enabled = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1253

return true;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1332

ret = kv_enable_ulv(adev, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1338

ret = kv_enable_didt(adev, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1343

ret = kv_enable_smc_cac(adev, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1577

kv_enable_vce_dpm(adev, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1712

kv_enable_vce_dpm(adev, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1730

kv_update_samu_dpm(adev, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1753

kv_update_acp_dpm(adev, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1858

pi->nb_dpm_enabled = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1955

kv_enable_nb_dpm(adev, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1968

kv_freeze_sclk_dpm(adev, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1980

kv_enable_nb_dpm(adev, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1998

sumo_take_smu_control(adev, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2018

kv_freeze_sclk_dpm(adev, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2244

ps->need_dfs_bypass = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2285

pi->battery_state = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2429

kv_dpm_power_level_enabled_for_throttle(adev, i, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2446

kv_dpm_power_level_enabled_for_throttle(adev, i, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2462

kv_dpm_power_level_enable(adev, i, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2586

pi->sys_info.nb_dpm_enable = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2598

pi->caps_enable_dfs_bypass = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2804

pi->enable_nb_dpm = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2806

pi->caps_power_containment = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2807

pi->caps_cac = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2810

pi->caps_sq_ramping = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2811

pi->caps_db_ramping = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2812

pi->caps_td_ramping = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2813

pi->caps_tcp_ramping = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2817

pi->caps_sclk_ds = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2821

pi->enable_auto_thermal_throttling = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2826

pi->bapm_enable = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2830

pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2831

pi->caps_uvd_dpm = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2832

pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2833

pi->caps_samu_pg = (adev->pg_flags & AMD_PG_SUPPORT_SAMU) ? true : false;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2834

pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2848

pi->enable_dpm = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2978

kv_dpm_powergate_acp(adev, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2979

kv_dpm_powergate_samu(adev, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

3053

adev->pm.dpm_enabled = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

3104

adev->pm.dpm_enabled = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

3114

return true;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

3178

queue_thermal = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

3182

adev->pm.dpm.thermal.high_to_low = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

3183

queue_thermal = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

562

pi->cac_enabled = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

722

amdgpu_kv_smc_dpm_enable(adev, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

802

kv_dpm_power_level_enable(adev, i, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

816

kv_dpm_power_level_enable(adev, i, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

1005

adev->pm.dpm.thermal_active = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

236

adev->pm.dpm.fan.ucode_fan_control = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

335

adev->pm.dpm.power_control = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

668

adev->pm.no_fan = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1132

true

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1168

true

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1186

true

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1204

true

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1659

true

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1690

true

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1726

true

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1744

true

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

1841

true

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2006

si_pi->dte_data.enable_dte_by_default = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2016

update_dte_from_pl2 = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2020

update_dte_from_pl2 = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2024

update_dte_from_pl2 = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2027

if (si_pi->dte_data.enable_dte_by_default == true)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2041

update_dte_from_pl2 = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2046

update_dte_from_pl2 = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2051

update_dte_from_pl2 = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2073

update_dte_from_pl2 = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2121

update_dte_from_pl2 = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2128

update_dte_from_pl2 = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2134

update_dte_from_pl2 = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2138

update_dte_from_pl2 = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2154

update_dte_from_pl2 = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2166

ni_pi->enable_power_containment = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2167

ni_pi->enable_cac = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2169

si_pi->enable_dte = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2174

ni_pi->enable_sq_ramping = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2177

ni_pi->driver_calculate_cac_leakage = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2178

ni_pi->cac_configuration_required = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2181

ni_pi->support_cac_long_term_average = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2380

return true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2561

ni_pi->pc_enabled = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2932

ni_pi->cac_enabled = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3089

return true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3091

return true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3398

return true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3400

return true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3402

return true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3404

return true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3406

return true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3437

pi->dynamic_ss = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3514

disable_mclk_switching = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3522

disable_sclk_switching = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3537

disable_mclk_switching = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3540

disable_mclk_switching = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3541

disable_sclk_switching = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

358

true

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3694

ps->dc_compatible = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3746

ret = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3809

want_thermal_protection = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3813

want_thermal_protection = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3818

want_thermal_protection = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3888

si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

394

true

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3988

amdgpu_si_smc_clock(adev, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

412

true

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

430

true

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4382

strobe_mode = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4429

return true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

448

true

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4676

voltage_found = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4691

voltage_found = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5562

if (si_get_mclk_frequency_ratio(pl->mclk, true) >=

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5564

dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5566

dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5574

dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5708

return true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5743

eg_pi->uvd_enabled = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5952

bool result = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6301

si_pi->pspp_notify_required = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

640

true

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6610

si_pi->fan_is_controlled_by_smc = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

676

true

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6798

si_pi->fan_ctrl_is_in_default_mode = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6833

ret = si_thermal_enable_alert(adev, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6871

si_enable_voltage_control(adev, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6887

si_enable_spread_spectrum(adev, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6889

si_enable_thermal_protection(adev, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

694

true

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6967

si_enable_sclk_control(adev, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6970

si_enable_auto_throttle_source(adev, SI_DPM_AUTO_THROTTLE_SRC_THERMAL, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6988

ret = si_thermal_enable_alert(adev, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

712

true

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7157

ret = si_enable_smc_cac(adev, new_ps, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7162

ret = si_enable_power_containment(adev, new_ps, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7520

pi->gfx_clock_gating = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7522

eg_pi->sclk_deep_sleep = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7526

pi->thermal_protection = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7530

eg_pi->dynamic_ac_timing = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7532

eg_pi->light_sleep = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7558

si_pi->fan_ctrl_is_in_default_mode = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7659

queue_thermal = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7663

adev->pm.dpm.thermal.high_to_low = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7664

queue_thermal = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7688

si_dpm_powergate_uvd(adev, true);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7847

adev->pm.dpm_enabled = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7898

adev->pm.dpm_enabled = true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7910

return true;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

165

return true;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

135

orderly_poweroff(true);

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

358

hwmgr->en_umd_pstate = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c

119

return true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c

41

return true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c

49

bool ret = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c

98

return true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr.c

222

? true : false;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr.c

266

((struct amdgpu_device *)hwmgr->adev)->pm.dpm_enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr.c

286

psm_adjust_power_state_dynamic(hwmgr, true, NULL);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr.c

308

ret = psm_adjust_power_state_dynamic(hwmgr, true, NULL);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr.c

396

ret = psm_adjust_power_state_dynamic(hwmgr, true, requested_ps);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr.c

401

ret = psm_adjust_power_state_dynamic(hwmgr, true, NULL);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr.c

463

hwmgr->od_enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr.c

91

hwmgr->fan_ctrl_is_in_default_mode = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

634

return true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

830

return true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

90

voltage_type, voltage_mode)) ? true : false;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

1705

hwmgr->need_pp_table_upload = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

717

ps->display.limitRefreshrate = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

109

smu10_data->need_min_deep_sleep_dcefclk = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1182

latency_required = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1186

latency_required = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1308

has_gfx_busy = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1311

has_gfx_busy = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1380

data->water_marks_exist = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1413

smu10_data->vcn_power_gated = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1489

return true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1513

hwmgr->gfxoff_state_changed_by_workload = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1521

smu10_gfx_off_control(hwmgr, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

299

smu10_data->vcn_power_gated = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

300

smu10_data->isp_tileA_power_gated = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

301

smu10_data->isp_tileB_power_gated = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

306

true,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

343

return true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

502

result = smum_smc_table_manager(hwmgr, (uint8_t *)table, SMU10_CLOCKTABLE, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

961

data->cc6_setting_changed = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c

127

smu7_update_uvd_dpm(hwmgr, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c

155

smu7_update_vce_dpm(hwmgr, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1328

PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1336

PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1368

PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1391

protection = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1395

protection = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1400

protection = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1454

data->pcie_performance_request = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1728

smu7_avfs_control(hwmgr, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1730

smu7_avfs_control(hwmgr, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1824

data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1825

data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1831

data->enable_tdc_limit_feature = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1832

data->enable_pkg_pwr_tracking_feature = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1834

data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1959

data->disable_edc_leakage_controller = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1979

data->disable_edc_leakage_controller = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3307

return true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3397

data->mclk_ignore_signal = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3440

latency_allowed = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3452

data->mclk_ignore_signal = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3724

ps->dc_compatible = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3737

data->use_pcie_performance_levels = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3760

data->use_pcie_power_saving_levels = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3872

ps->dc_compatible = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3885

data->use_pcie_performance_levels = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3910

data->use_pcie_power_saving_levels = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4205

data->pspp_notify_required = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4221

PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4235

PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4311

dpm_table->dpm_levels[i].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4378

PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4392

PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4687

is_update_required = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4690

is_update_required = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4695

is_update_required = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4701

is_update_required = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5356

valid_entry = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5488

return true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

835

data->dpm_table.vddc_table.dpm_levels[i].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

845

data->dpm_table.vddci_table.dpm_levels[i].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

859

data->dpm_table.mvdd_table.dpm_levels[i].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

955

entries[i].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

967

entries[i].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

1012

result = smu7_enable_didt(hwmgr, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c

140

hwmgr->fan_ctrl_is_in_default_mode = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c

186

hwmgr->fan_ctrl_enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c

35

fan_speed_info->supports_percent_read = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c

36

fan_speed_info->supports_percent_write = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c

42

fan_speed_info->supports_rpm_read = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c

43

fan_speed_info->supports_rpm_write = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1089

smu8_ps->need_dfs_bypass = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1109

smu8_nbdpm_pstate_enable_disable(hwmgr, false, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1509

hw_data->cc6_settings.cc6_setting_changed = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1925

smu8_enable_disable_uvd_dpm(hwmgr, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1927

smu8_enable_disable_uvd_dpm(hwmgr, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1992

smu8_dpm_update_uvd_dpm(hwmgr, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

2010

true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

2026

data->vce_power_gated = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

2037

smu8_enable_disable_vce_dpm(hwmgr, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

680

data->acp_power_gated = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

830

smu8_nbdpm_pstate_enable_disable(hwmgr, true, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

860

data->is_nb_dpm_enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

875

disable_switch = hw_data->cc6_settings.nb_pstate_switch_disable ? true : false;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

876

enable_low_mem_state = hw_data->cc6_settings.nb_pstate_switch_disable ? false : true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

881

smu8_nbdpm_pstate_enable_disable(hwmgr, true, disable_switch);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

229

found = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

622

orderly_poweroff(true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

636

orderly_poweroff(true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1047

found = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

120

hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

122

hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

124

hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1253

dpm_table->dpm_levels[dpm_table->count].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

126

hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

129

hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

138

hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

141

hwmgr->feature_mask & PP_ULV_MASK ? true : false;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

144

hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

153

hwmgr->feature_mask & PP_AVFS_MASK ? true : false;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2367

if (0 == vega10_enable_smc_features(hwmgr, true,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2369

data->smu_features[GNLD_DPM_PREFETCHER].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2384

if (0 == vega10_enable_smc_features(hwmgr, true,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2386

data->smu_features[GNLD_ACG].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2455

true,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2459

data->smu_features[GNLD_AVFS].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2481

vega10_avfs_enable(hwmgr, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2483

vega10_avfs_enable(hwmgr, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2690

data->vbios_boot_state.bsoc_vddc_lock = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2726

result = vega10_avfs_enable(hwmgr, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2744

true,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2748

data->smu_features[GNLD_THERMAL].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2782

true,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2786

data->smu_features[GNLD_VR0HOT].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2791

true,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2795

data->smu_features[GNLD_VR1HOT].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2808

true, data->smu_features[GNLD_ULV].smu_feature_bitmap),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2811

data->smu_features[GNLD_ULV].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2838

true, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2841

data->smu_features[GNLD_DS_GFXCLK].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2846

true, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2849

data->smu_features[GNLD_DS_SOCCLK].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2854

true, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2857

data->smu_features[GNLD_DS_LCLK].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2862

true, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2865

data->smu_features[GNLD_DS_DCEFCLK].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2918

if(data->smu_features[GNLD_LED_DISPLAY].supported == true){

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2958

data->smu_features[i].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2965

true, feature_mask)) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2973

if(data->smu_features[GNLD_LED_DISPLAY].supported == true){

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2975

true, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2977

data->smu_features[GNLD_LED_DISPLAY].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2990

true, data->smu_features[GNLD_ACDC].smu_feature_bitmap),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2993

data->smu_features[GNLD_ACDC].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3056

vega10_enable_disable_PCC_limit_feature(hwmgr, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3262

vega10_ps->dc_compatible = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3537

dpm_table->dpm_levels[i].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3556

dpm_table->dpm_levels[i].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3784

data->dpm_table.gfx_table.dpm_levels[i].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3788

data->dpm_table.mem_table.dpm_levels[i].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3791

data->dpm_table.soc_table.dpm_levels[i].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4115

vega10_notify_smc_display_change(hwmgr, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

431

data->smu_features[GNLD_DPM_PREFETCHER].supported = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

434

data->smu_features[GNLD_DPM_GFXCLK].supported = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

437

data->smu_features[GNLD_DPM_UCLK].supported = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

440

data->smu_features[GNLD_DPM_SOCCLK].supported = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

443

data->smu_features[GNLD_DPM_UVD].supported = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

446

data->smu_features[GNLD_DPM_VCE].supported = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

448

data->smu_features[GNLD_DPM_LINK].supported = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

451

data->smu_features[GNLD_DPM_DCEFCLK].supported = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

455

data->smu_features[GNLD_DS_GFXCLK].supported = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

456

data->smu_features[GNLD_DS_SOCCLK].supported = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

457

data->smu_features[GNLD_DS_LCLK].supported = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

458

data->smu_features[GNLD_DS_DCEFCLK].supported = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

462

data->smu_features[GNLD_PPT].supported = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

465

data->smu_features[GNLD_TDC].supported = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4656

ret = vega10_enable_smc_features(hwmgr, true, features_to_enable);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

468

data->smu_features[GNLD_THERMAL].supported = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

471

data->smu_features[GNLD_FAN_CONTROL].supported = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

474

data->smu_features[GNLD_FW_CTF].supported = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

477

data->smu_features[GNLD_AVFS].supported = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

480

data->smu_features[GNLD_LED_DISPLAY].supported = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

483

data->smu_features[GNLD_VR1HOT].supported = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

486

data->smu_features[GNLD_VR0HOT].supported = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

496

data->smu_features[GNLD_ACG].supported = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

498

data->smu_features[GNLD_DIDT].supported = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

508

data->smu_features[GNLD_PCC_LIMIT].supported = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5082

is_update_required = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5086

is_update_required = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5454

return true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5746

data->smu_features[GNLD_ULV].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5747

data->smu_features[GNLD_DS_GFXCLK].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5748

data->smu_features[GNLD_DS_SOCCLK].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5749

data->smu_features[GNLD_DS_LCLK].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5750

data->smu_features[GNLD_DS_DCEFCLK].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1022

vega10_didt_set_mask(hwmgr, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1070

vega10_didt_set_mask(hwmgr, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1181

result = vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_DIDT].smu_feature_bitmap);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1183

data->smu_features[GNLD_DIDT].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1305

true, data->smu_features[GNLD_PPT].smu_feature_bitmap),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1311

true, data->smu_features[GNLD_TDC].smu_feature_bitmap),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

914

vega10_didt_set_mask(hwmgr, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

959

vega10_didt_set_mask(hwmgr, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

168

hwmgr->fan_ctrl_is_in_default_mode = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

186

hwmgr, true,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

191

data->smu_features[GNLD_FAN_CONTROL].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

443

true,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

447

data->smu_features[GNLD_FW_CTF].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

45

fan_speed_info->supports_percent_read = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

46

fan_speed_info->supports_percent_write = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

53

fan_speed_info->supports_rpm_read = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

54

fan_speed_info->supports_rpm_write = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1132

table->dpm_levels[i].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1153

table->dpm_levels[i].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1355

vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true) == 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1378

vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true) == 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1399

true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1628

vega12_notify_smc_display_change(hwmgr, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2226

ret = vega12_enable_smc_features(hwmgr, true, features_to_enable);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2629

is_update_required = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2633

is_update_required = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2888

ret = vega12_get_metrics_table(hwmgr, &metrics, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

363

false : true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

453

data->gfxoff_controlled_by_driver = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

629

dpm_table->dpm_levels[i].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

907

data->uvd_power_gated = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

908

data->vce_power_gated = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

932

enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

958

enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c

49

fan_speed_info->supports_rpm_read = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c

50

fan_speed_info->supports_rpm_write = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c

75

hwmgr, true,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c

80

data->smu_features[GNLD_FAN_CONTROL].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1264

ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1411

ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1689

data->uvd_power_gated = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1690

data->vce_power_gated = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1787

table->dpm_levels[i].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1814

table->dpm_levels[i].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2080

ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2106

ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2129

true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3019

data->gfxclk_overdrive = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3061

data->memclk_overdrive = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3140

TABLE_OVERDRIVE, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3306

ret = vega20_enable_smc_features(hwmgr, true, features_to_enable);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3318

true : false;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3824

disable_fclk_switching = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3924

is_update_required = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3929

is_update_required = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

403

false : true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

4178

data->is_custom_profile_set = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

4334

ret = vega20_get_metrics_table(hwmgr, &metrics, true);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

587

dpm_table->dpm_levels[i].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

990

true : false;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c

129

od_supported = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

173

fan_speed_info->supports_percent_read = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

174

fan_speed_info->supports_percent_write = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

175

fan_speed_info->supports_rpm_read = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

176

fan_speed_info->supports_rpm_write = true;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

68

hwmgr, true,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

74

data->smu_features[GNLD_FAN_CONTROL].enabled = true;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2450

bool result = true;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

784

vol_found = true;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

800

vol_found = true;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1207

mem_level->StutterEnable = true;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

328

return true;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2377

bool result = true;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

556

vol_found = true;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

576

vol_found = true;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1197

mem_level->StutterEnable = true;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

330

return true;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

543

hwmgr->avfs_supported = true;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

400

TASK_TYPE_UCODE_SAVE, true);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

429

TASK_TYPE_UCODE_SAVE, true);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

472

TASK_TYPE_UCODE_LOAD, true);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

485

TASK_TYPE_INITIALIZE, true);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

512

SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_G, true);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

525

TASK_TYPE_INITIALIZE, true);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

882

return true;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

891

return true;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c

48

return true;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smumgr.c

222

return true;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2839

bool result = true;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c

156

return true;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

189

return true;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

59

return true;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

613

return true;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1020

mem_level->StutterEnable = true;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1556

return true;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

1281

orderly_poweroff(true);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

1406

smu->adev->pm.no_fan = true;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

1675

ret = smu_system_features_control(smu, true);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

1757

ret = smu_enable_uclk_shadow(smu, true);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

1811

ret = smu_system_features_control(smu, true);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

1947

smu_dpm_set_vcn_enable(smu, true, i);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

1948

smu_dpm_set_jpeg_enable(smu, true);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

1949

smu_dpm_set_umsch_mm_enable(smu, true);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

1951

smu_set_gfx_cgpg(smu, true);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

1980

adev->pm.dpm_enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2281

smu_set_gfx_cgpg(smu, true);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2285

adev->pm.dpm_enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2354

amdgpu_asic_update_umd_stable_pstate(smu->adev, true);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2362

smu_deep_sleep_control(smu, true);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2363

smu_gfx_ulv_control(smu, true);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2364

smu_gpo_control(smu, true);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

246

return true;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2479

ret = smu_adjust_power_state_dynamic(smu, level, true);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2482

ret = smu_adjust_power_state_dynamic(smu, level, true);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3277

custom = true;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

597

return true;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

609

return true;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

665

smu->uploading_custom_pp_table = true;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

713

smu->od_enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

759

smu->od_enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

770

smu->od_enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

842

ret = smu_dpm_set_vcn_enable(smu, true, i);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

849

ret = smu_dpm_set_jpeg_enable(smu, true);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1696

return true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1040

true,

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1502

true);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1686

r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

381

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

399

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

417

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

435

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

464

(val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :

sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

392

ret = smu_cmn_get_metrics_table(smu, &metrics, true);

sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

603

smu->is_apu = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1004

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1022

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1040

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1058

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1076

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1094

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1112

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1130

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2069

(void *)(&activity_monitor), true);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

265

bool is_secure = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2724

ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2730

smu->user_dpm_profile.user_od = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2821

return true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2969

true);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

3084

r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

3179

true);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

3251

true);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

3326

true);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

3512

true);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

378

(val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

390

smu->dc_controlled_by_gpio = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

986

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1012

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1030

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1052

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1074

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1093

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1111

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1129

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1147

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1770

(void *)(&activity_monitor_external), true);

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2415

ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2421

smu->user_dpm_profile.user_od = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2590

r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2697

use_metrics_v3 = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2699

use_metrics_v2 = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2703

use_metrics_v2 = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2707

use_metrics_v2 = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2711

use_metrics_v2 = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2719

true);

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

3057

true);

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

374

(val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

417

smu->dc_controlled_by_gpio = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

751

use_metrics_v3 = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

753

use_metrics_v2 = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

757

use_metrics_v2 = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

761

use_metrics_v2 = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

765

use_metrics_v2 = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

976

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

994

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1439

orderly_poweroff(true);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1451

adev->pm.ac_power = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1895

auto_level = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

2056

single_dpm_table->dpm_levels[i].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

2173

ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)user_od_table, true);

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1395

ret = vangogh_force_dpm_limit_value(smu, true);

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1667

ret = smu_cmn_get_metrics_table(smu, &metrics, true);

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1724

ret = smu_cmn_get_metrics_table(smu, &metrics, true);

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1781

ret = smu_cmn_get_metrics_table(smu, &metrics, true);

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1852

ret = smu_cmn_get_metrics_table(smu, &metrics, true);

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1932

ret = smu_cmn_get_metrics_table(smu, &metrics, true);

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

2566

smu->is_apu = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

659

cur_value_match_level = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

762

cur_value_match_level = true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

883

return true;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

889

return true;

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1366

return true;

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1379

ret = smu_cmn_get_metrics_table(smu, &metrics, true);

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1501

smu->is_apu = true;

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

599

cur_value_match_level = true;

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

965

ret = renoir_force_dpm_limit_value(smu, true);

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1070

true,

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1586

r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

2031

return true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

418

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

429

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

431

dpm_table->dpm_levels[1].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

437

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

453

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

469

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

559

return true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1300

orderly_poweroff(true);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1312

adev->pm.ac_power = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1643

auto_level = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1948

single_dpm_table->dpm_levels[i].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

2499

ret = smu_cmn_update_table(smu, SMU_TABLE_WIFIBAND, 0, &wifi_bands, true);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1180

true);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1974

smu->user_dpm_profile.user_od = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2117

true);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2622

true);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2717

return true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2776

r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2936

smu->adev->no_hw_access = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

359

smu->dc_controlled_by_gpio = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

362

smu_baco->platform_support = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

365

smu_baco->maco_support = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

588

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

621

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

637

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

653

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

669

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

685

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

701

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

257

ret = smu_v13_0_6_get_metrics_table(smu, NULL, true);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

349

pptable->Init = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

576

return true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

1141

smu->is_apu = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

256

ret = smu_cmn_get_metrics_table(smu, &metrics, true);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

744

return true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

1134

smu->is_apu = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

477

ret = smu_cmn_get_metrics_table(smu, &metrics, true);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

721

return true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1112

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1114

dpm_table->dpm_levels[1].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1120

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1138

dpm_table->dpm_levels[i].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1672

smu, true, FEATURE_MASK(FEATURE_DPM_GFXCLK),

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3133

return true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3142

return true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3189

bool ret = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3470

return true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3474

return true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3540

return true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3670

return true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

797

ret = smu_v13_0_6_get_metrics_table(smu, pm_metrics->data, true);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

875

ret = smu_v13_0_6_get_metrics_table(smu, NULL, true);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

942

pptable->Init = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1169

true);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1963

smu->user_dpm_profile.user_od = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

2102

true);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

2571

(void *)(&activity_monitor_external), true);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

2658

return true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

351

smu->dc_controlled_by_gpio = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

354

smu_baco->platform_support = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

358

smu_baco->maco_support = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

595

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

619

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

635

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

651

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

667

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

683

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

699

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1363

smu->is_apu = true;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

568

ret = smu_cmn_get_metrics_table(smu, &metrics, true);

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

855

return true;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1305

auto_level = true;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1559

single_dpm_table->dpm_levels[i].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1719

smu->is_apu = true;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

549

ret = smu_cmn_get_metrics_table(smu, &metrics, true);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

766

return true;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1877

true);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1901

smu_v14_0_deep_sleep_control(smu, true);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1973

return true;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

2032

r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

2152

smu->adev->no_hw_access = true;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

2207

true);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

2295

true);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

2799

smu->user_dpm_profile.user_od = true;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

331

smu->dc_controlled_by_gpio = true;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

334

smu_baco->platform_support = true;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

337

smu_baco->maco_support = true;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

518

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

551

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

567

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

583

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

599

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

615

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

631

dpm_table->dpm_levels[0].enabled = true;

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

1013

true);

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

1024

true);

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

1111

return true;

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

1113

snd_driver_loaded = pci_is_enabled(p) ? true : false;

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

262

*poll = true;

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

428

bool poll = true;

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

678

return true;

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

684

return true;

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

870

true);

sys/dev/pci/drm/apple/afk.c

177

bfr->ready = true;

sys/dev/pci/drm/apple/afk.c

278

ep->services[ch_idx].enabled = true;

sys/dev/pci/drm/apple/afk.c

363

service->cmds[idx].done = true;

sys/dev/pci/drm/apple/afk.c

459

payload_size, true);

sys/dev/pci/drm/apple/afk.c

535

payload_size, true);

sys/dev/pci/drm/apple/afk.c

629

return true;

sys/dev/pci/drm/apple/afk.c

914

service->cmds[idx].free_on_ack = true;

sys/dev/pci/drm/apple/apple_drv.c

108

true, true);

sys/dev/pci/drm/apple/apple_drv.c

337

drm_crtc_enable_color_mgmt(&crtc->base, 0, true, 0);

sys/dev/pci/drm/apple/dcp.c

140

dcp->crashed = true;

sys/dev/pci/drm/apple/dcp.c

171

bfr->is_mapped = true;

sys/dev/pci/drm/apple/dcp.c

210

true);

sys/dev/pci/drm/apple/dcp.c

285

dcp->dptxport[port].connected = true;

sys/dev/pci/drm/apple/dcp.c

442

WARN_ONCE(true, "Unexpected firmware version: %u\n", dcp->fw_compat);

sys/dev/pci/drm/apple/dcp.c

467

WARN_ONCE(true, "Unexpected firmware version: %u\n", dcp->fw_compat);

sys/dev/pci/drm/apple/dcp.c

485

WARN_ONCE(true, "Unexpected firmware version: %u\n", dcp->fw_compat);

sys/dev/pci/drm/apple/dcp.c

547

ret = of_dma_configure(&dcp->piodma->dev, node, true);

sys/dev/pci/drm/apple/dcp.c

825

dcp->panel.has_mini_led = true;

sys/dev/pci/drm/apple/dcp_backlight.c

163

crtc_state->color_mgmt_changed |= true;

sys/dev/pci/drm/apple/dcp_backlight.c

203

dcp->brightness.update = true;

sys/dev/pci/drm/apple/dptxep.c

366

phy_set_rate = true;

sys/dev/pci/drm/apple/dptxep.c

370

phy_set_rate = true;

sys/dev/pci/drm/apple/dptxep.c

374

phy_set_rate = true;

sys/dev/pci/drm/apple/dptxep.c

378

phy_set_rate = true;

sys/dev/pci/drm/apple/dptxep.c

382

phy_set_rate = true;

sys/dev/pci/drm/apple/dptxep.c

555

service->ep->dcp->dptxport[unit].enabled = true;

sys/dev/pci/drm/apple/iomfb.c

455

WARN_ONCE(true, "Unexpected firmware version: %u\n",

sys/dev/pci/drm/apple/iomfb.c

501

WARN_ONCE(true, "Unexpected firmware version: %u\n", dcp->fw_compat);

sys/dev/pci/drm/apple/iomfb.c

517

WARN_ONCE(true, "Unexpected firmware version: %u\n", dcp->fw_compat);

sys/dev/pci/drm/apple/iomfb.c

569

WARN_ONCE(true, "Unexpected firmware version: %u\n", dcp->fw_compat);

sys/dev/pci/drm/apple/iomfb_internal.h

64

return true; \

sys/dev/pci/drm/apple/iomfb_internal.h

76

return true; \

sys/dev/pci/drm/apple/iomfb_internal.h

89

return true; \

sys/dev/pci/drm/apple/iomfb_internal.h

99

return true; \

sys/dev/pci/drm/apple/iomfb_template.c

107

return true;

sys/dev/pci/drm/apple/iomfb_template.c

1221

dcp->during_modeset = true;

sys/dev/pci/drm/apple/iomfb_template.c

1251

dcp->valid_mode = true;

sys/dev/pci/drm/apple/iomfb_template.c

1270

req->surf_null[l] = true;

sys/dev/pci/drm/apple/iomfb_template.c

1273

req->surf2_null[l] = true;

sys/dev/pci/drm/apple/iomfb_template.c

1274

req->unkU32Ptr_null = true;

sys/dev/pci/drm/apple/iomfb_template.c

1275

req->unkU32out_null = true;

sys/dev/pci/drm/apple/iomfb_template.c

1285

dcp->surfaces_cleared = true;

sys/dev/pci/drm/apple/iomfb_template.c

1339

is_premultiplied = true;

sys/dev/pci/drm/apple/iomfb_template.c

1437

dcp->active = true;

sys/dev/pci/drm/apple/iomfb_template.c

152

*succ = true;

sys/dev/pci/drm/apple/iomfb_template.c

174

*succ = true;

sys/dev/pci/drm/apple/iomfb_template.c

186

*succ = true;

sys/dev/pci/drm/apple/iomfb_template.c

187

return true;

sys/dev/pci/drm/apple/iomfb_template.c

230

resp.ret = true;

sys/dev/pci/drm/apple/iomfb_template.c

411

return true;

sys/dev/pci/drm/apple/iomfb_template.c

499

dcp->brightness.update = true;

sys/dev/pci/drm/apple/iomfb_template.c

519

return true;

sys/dev/pci/drm/apple/iomfb_template.c

536

return true;

sys/dev/pci/drm/apple/iomfb_template.c

585

return true;

sys/dev/pci/drm/apple/iomfb_template.c

607

*succ = true;

sys/dev/pci/drm/apple/iomfb_template.c

628

u32 v_true = true;

sys/dev/pci/drm/apple/iomfb_template.c

827

dcp->brightness.update = true;

sys/dev/pci/drm/apple/iomfb_template.c

899

swap->surf_null[l] = true;

sys/dev/pci/drm/apple/iomfb_template.c

902

swap->surf2_null[l] = true;

sys/dev/pci/drm/apple/iomfb_template.c

903

swap->unkU32Ptr_null = true;

sys/dev/pci/drm/apple/iomfb_template.c

904

swap->unkU32out_null = true;

sys/dev/pci/drm/apple/iomfb_template.c

913

dcp->crashed = true;

sys/dev/pci/drm/apple/parser.c

152

return true;

sys/dev/pci/drm/apple/parser.c

251

for (iterator_begin(handle, &it, true); it.idx < it.len; ++it.idx)

sys/dev/pci/drm/apple/parser.c

355

bool is_virtual = true;

sys/dev/pci/drm/apple/parser.c

660

parsed_name = true;

sys/dev/pci/drm/apple/parser.c

666

parsed_class = true;

sys/dev/pci/drm/apple/parser.c

670

parsed_unit = true;

sys/dev/pci/drm/clients/drm_fbdev_client.c

70

drm_fb_helper_set_suspend(fb_helper, true);

sys/dev/pci/drm/clients/drm_fbdev_client.c

72

drm_fb_helper_set_suspend_unlocked(fb_helper, true);

sys/dev/pci/drm/clients/drm_log.c

242

dlog->probed = true;

sys/dev/pci/drm/display/drm_dp_dual_mode_helper.c

330

*enabled = true;

sys/dev/pci/drm/display/drm_dp_helper.c

107

return true;

sys/dev/pci/drm/display/drm_dp_helper.c

1089

return true;

sys/dev/pci/drm/display/drm_dp_helper.c

1102

return true;

sys/dev/pci/drm/display/drm_dp_helper.c

1165

return true;

sys/dev/pci/drm/display/drm_dp_helper.c

122

return true;

sys/dev/pci/drm/display/drm_dp_helper.c

1511

return true;

sys/dev/pci/drm/display/drm_dp_helper.c

182

return true;

sys/dev/pci/drm/display/drm_dp_helper.c

198

return true;

sys/dev/pci/drm/display/drm_dp_helper.c

2537

{ OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) },

sys/dev/pci/drm/display/drm_dp_helper.c

2545

{ OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },

sys/dev/pci/drm/display/drm_dp_helper.c

2547

{ OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },

sys/dev/pci/drm/display/drm_dp_helper.c

2995

ret = drm_dp_lttpr_set_transparent_mode(aux, true);

sys/dev/pci/drm/display/drm_dp_helper.c

3007

drm_dp_lttpr_set_transparent_mode(aux, true);

sys/dev/pci/drm/display/drm_dp_helper.c

3085

data->enhanced_frame_cap = true;

sys/dev/pci/drm/display/drm_dp_helper.c

345

return __read_delay(aux, dpcd, dp_phy, uhbr, true);

sys/dev/pci/drm/display/drm_dp_helper.c

3526

return true;

sys/dev/pci/drm/display/drm_dp_helper.c

3760

return true;

sys/dev/pci/drm/display/drm_dp_helper.c

4096

ret = drm_edp_backlight_set_enable(aux, bl, true);

sys/dev/pci/drm/display/drm_dp_helper.c

4317

bl->aux_enable = true;

sys/dev/pci/drm/display/drm_dp_helper.c

4319

bl->aux_set = true;

sys/dev/pci/drm/display/drm_dp_helper.c

4321

bl->lsb_reg_used = true;

sys/dev/pci/drm/display/drm_dp_helper.c

4324

bl->luminance_set = true;

sys/dev/pci/drm/display/drm_dp_helper.c

4377

bl->enabled = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

1032

return true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

1062

return true; /* since there's nothing to parse */

sys/dev/pci/drm/display/drm_dp_mst_topology.c

1071

return true; /* since there's nothing to parse */

sys/dev/pci/drm/display/drm_dp_mst_topology.c

1104

return true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

1129

return true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

1181

msg->path_msg = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

1192

msg->path_msg = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

1213

msg->path_msg = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

1228

msg->path_msg = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2057

return true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2061

return true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2065

return true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2342

port->aux.is_remote = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2375

created = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2376

changed = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2387

changed = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2388

created = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2390

changed = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2435

changed = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2442

send_link_addr = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2455

send_link_addr = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2465

changed = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2507

dowork = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2514

create_connector = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2517

dowork = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2536

dowork = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2645

changed = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2656

changed = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2677

mgr->payload_id_table_cleared = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2721

return true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2943

mstb->link_address_sent = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2976

changed = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2995

changed = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

341

return true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

3584

process_single_tx_qlock(mgr, txmsg, true);

sys/dev/pci/drm/display/drm_dp_mst_topology.c

3710

mgr->reset_rx_state = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

3948

return true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

3967

return true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

4095

hotplug = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

4115

while (true) {

sys/dev/pci/drm/display/drm_dp_mst_topology.c

4142

if (!drm_dp_get_one_sb_msg(mgr, true, NULL))

sys/dev/pci/drm/display/drm_dp_mst_topology.c

4252

*handled = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

4259

*handled = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

4265

*handled = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

4285

bool kick = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

4543

bool update_payload = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

4584

payload->delete = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

4896

return true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

5065

wake_tx = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

5105

go_again = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

5123

send_hotplug = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

5124

go_again = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

5202

return true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

5226

return true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

5287

found = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

5469

crtc_state->mode_changed = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

556

failed = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

6036

return true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

6042

return true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

6053

return true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

6166

if (drm_dp_read_desc(immediate_upstream_aux, &desc, true))

sys/dev/pci/drm/display/drm_dp_mst_topology.c

778

msg->have_somt = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

781

msg->have_eomt = true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

783

return true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

806

return true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

857

return true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

878

return true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

893

return true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

912

return true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

936

return true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

959

return true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

978

return true;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

996

return true;

sys/dev/pci/drm/display/drm_dp_tunnel.c

1264

changed = true;

sys/dev/pci/drm/display/drm_dp_tunnel.c

1268

changed = true;

sys/dev/pci/drm/display/drm_dp_tunnel.c

1599

return true;

sys/dev/pci/drm/display/drm_dp_tunnel.c

339

group->active = true;

sys/dev/pci/drm/display/drm_dp_tunnel.c

468

return true;

sys/dev/pci/drm/display/drm_dp_tunnel.c

544

tunnel->has_io_error = true;

sys/dev/pci/drm/display/drm_dp_tunnel.c

556

bool ret = true;

sys/dev/pci/drm/display/drm_dp_tunnel.c

626

bool ret = true;

sys/dev/pci/drm/display/drm_dp_tunnel.c

708

changed = true;

sys/dev/pci/drm/display/drm_dp_tunnel.c

713

changed = true;

sys/dev/pci/drm/display/drm_dp_tunnel.c

820

tunnel->destroyed = true;

sys/dev/pci/drm/display/drm_dp_tunnel.c

961

err = set_bw_alloc_mode(tunnel, true);

sys/dev/pci/drm/display/drm_hdmi_audio_helper.c

170

.no_i2s_capture = true,

sys/dev/pci/drm/display/drm_hdmi_audio_helper.c

171

.no_spdif_capture = true,

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

1076

infoframe->set = true;

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

1147

drm_connector_hdmi_audio_plugged_notify(connector, true);

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

364

return true;

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

370

return true;

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

446

return true;

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

478

return true;

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

501

return true;

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

523

return true;

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

607

return true;

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

705

infoframe->set = true;

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

729

infoframe->set = true;

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

755

infoframe->set = true;

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

781

infoframe->set = true;

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

866

crtc_state->mode_changed = true;

sys/dev/pci/drm/display/drm_scdc_helper.c

210

return true;

sys/dev/pci/drm/display/drm_scdc_helper.c

276

return true;

sys/dev/pci/drm/dma-resv.c

156

dma_resv_list_free(rcu_dereference_protected(obj->fences, true));

sys/dev/pci/drm/dma-resv.c

374

cursor->is_restarted = true;

sys/dev/pci/drm/dma-resv.c

405

} while (true);

sys/dev/pci/drm/dma-resv.c

454

restart = true;

sys/dev/pci/drm/dma-resv.c

481

cursor->is_restarted = true;

sys/dev/pci/drm/dma-resv.c

761

return true;

sys/dev/pci/drm/dma-resv.c

77

resv ? dma_resv_held(resv) : true);

sys/dev/pci/drm/drm_atomic.c

131

state->allow_modeset = true;

sys/dev/pci/drm/drm_atomic.c

1625

return config->funcs->atomic_commit(state->dev, state, true);

sys/dev/pci/drm/drm_atomic.c

1765

crtc_state->active = true;

sys/dev/pci/drm/drm_atomic.c

1926

__drm_state_dump(dev, &p, true);

sys/dev/pci/drm/drm_atomic.c

586

return true;

sys/dev/pci/drm/drm_atomic_helper.c

102

crtc_state->planes_changed = true;

sys/dev/pci/drm/drm_atomic_helper.c

1158

return true;

sys/dev/pci/drm/drm_atomic_helper.c

2276

ret = drm_atomic_helper_wait_for_fences(dev, state, true);

sys/dev/pci/drm/drm_atomic_helper.c

2287

ret = drm_atomic_helper_swap_state(state, true);

sys/dev/pci/drm/drm_atomic_helper.c

2381

bool completed = true;

sys/dev/pci/drm/drm_atomic_helper.c

2571

commit->abort_completion = true;

sys/dev/pci/drm/drm_atomic_helper.c

285

crtc_state->connectors_changed = true;

sys/dev/pci/drm/drm_atomic_helper.c

308

crtc_state->connectors_changed = true;

sys/dev/pci/drm/drm_atomic_helper.c

313

crtc_state->connectors_changed = true;

sys/dev/pci/drm/drm_atomic_helper.c

3428

state->legacy_cursor_update = true;

sys/dev/pci/drm/drm_atomic_helper.c

3466

plane_state->state->legacy_cursor_update = true;

sys/dev/pci/drm/drm_atomic_helper.c

3511

ret = handle_conflicting_encoders(state, true);

sys/dev/pci/drm/drm_atomic_helper.c

3645

crtc_state->connectors_changed = true;

sys/dev/pci/drm/drm_atomic_helper.c

3726

state->duplicated = true;

sys/dev/pci/drm/drm_atomic_helper.c

403

crtc_state->connectors_changed = true;

sys/dev/pci/drm/drm_atomic_helper.c

670

new_crtc_state->mode_changed = true;

sys/dev/pci/drm/drm_atomic_helper.c

685

new_crtc_state->mode_changed = true;

sys/dev/pci/drm/drm_atomic_helper.c

686

new_crtc_state->connectors_changed = true;

sys/dev/pci/drm/drm_atomic_helper.c

692

new_crtc_state->active_changed = true;

sys/dev/pci/drm/drm_atomic_helper.c

706

new_crtc_state->no_vblank = true;

sys/dev/pci/drm/drm_atomic_helper.c

734

new_crtc_state->connectors_changed = true;

sys/dev/pci/drm/drm_atomic_helper.c

738

new_crtc_state->connectors_changed = true;

sys/dev/pci/drm/drm_atomic_helper.c

93

crtc_state->planes_changed = true;

sys/dev/pci/drm/drm_atomic_helper.c

942

drm_rect_debug_print("src: ", &plane_state->src, true);

sys/dev/pci/drm/drm_atomic_state_helper.c

605

crtc_state->mode_changed = true;

sys/dev/pci/drm/drm_atomic_state_helper.c

618

crtc_state->connectors_changed = true;

sys/dev/pci/drm/drm_atomic_uapi.c

1097

ret = plane_funcs->atomic_async_check(plane, state, true);

sys/dev/pci/drm/drm_atomic_uapi.c

1401

crtc_state->async_flip = true;

sys/dev/pci/drm/drm_atomic_uapi.c

1452

async_flip = true;

sys/dev/pci/drm/drm_atomic_uapi.c

159

state->enable = true;

sys/dev/pci/drm/drm_atomic_uapi.c

94

state->enable = true;

sys/dev/pci/drm/drm_atomic_uapi.c

985

active = true;

sys/dev/pci/drm/drm_auth.c

163

fpriv->was_master = true;

sys/dev/pci/drm/drm_auth.c

185

drm_set_master(dev, fpriv, true);

sys/dev/pci/drm/drm_auth.c

447

return true;

sys/dev/pci/drm/drm_blend.c

491

crtc_state->zpos_changed = true;

sys/dev/pci/drm/drm_blend.c

531

new_crtc_state->zpos_changed = true;

sys/dev/pci/drm/drm_buddy.c

286

order = __drm_buddy_free(mm, block, true);

sys/dev/pci/drm/drm_cache.c

197

return true;

sys/dev/pci/drm/drm_cache.c

204

return true;

sys/dev/pci/drm/drm_client_event.c

137

client->suspended = true;

sys/dev/pci/drm/drm_client_event.c

65

client->hotplug_pending = true;

sys/dev/pci/drm/drm_client_event.c

73

client->hotplug_failed = true;

sys/dev/pci/drm/drm_client_modeset.c

1040

return true;

sys/dev/pci/drm/drm_client_modeset.c

1192

ret = drm_client_modeset_commit_atomic(client, true, true);

sys/dev/pci/drm/drm_client_modeset.c

1217

ret = drm_client_modeset_commit_atomic(client, true, false);

sys/dev/pci/drm/drm_client_modeset.c

255

enabled[i] = drm_connector_enabled(connector, true);

sys/dev/pci/drm/drm_client_modeset.c

316

can_clone = true;

sys/dev/pci/drm/drm_client_modeset.c

343

return true;

sys/dev/pci/drm/drm_client_modeset.c

347

can_clone = true;

sys/dev/pci/drm/drm_client_modeset.c

374

return true;

sys/dev/pci/drm/drm_client_modeset.c

528

return true;

sys/dev/pci/drm/drm_client_modeset.c

538

return true;

sys/dev/pci/drm/drm_client_modeset.c

632

bool fallback = true, ret = true;

sys/dev/pci/drm/drm_client_modeset.c

788

fallback = true;

sys/dev/pci/drm/drm_color_mgmt.c

253

return true;

sys/dev/pci/drm/drm_color_mgmt.c

297

use_gamma_lut = true;

sys/dev/pci/drm/drm_connector.c

3180

drm_connector_update_privacy_screen_properties(connector, true);

sys/dev/pci/drm/drm_connector.c

3211

drm_connector_update_privacy_screen_properties(connector, true);

sys/dev/pci/drm/drm_connector.c

3326

return true;

sys/dev/pci/drm/drm_connector.c

3398

mode->expose_to_userspace = true;

sys/dev/pci/drm/drm_crtc_helper.c

129

return true;

sys/dev/pci/drm/drm_crtc_helper.c

164

return true;

sys/dev/pci/drm/drm_crtc_helper.c

295

bool ret = true;

sys/dev/pci/drm/drm_crtc_helper.c

304

return true;

sys/dev/pci/drm/drm_crtc_helper.c

646

mode_changed = true;

sys/dev/pci/drm/drm_crtc_helper.c

648

mode_changed = true;

sys/dev/pci/drm/drm_crtc_helper.c

650

fb_changed = true;

sys/dev/pci/drm/drm_crtc_helper.c

654

fb_changed = true;

sys/dev/pci/drm/drm_crtc_helper.c

661

mode_changed = true;

sys/dev/pci/drm/drm_crtc_helper.c

696

mode_changed = true;

sys/dev/pci/drm/drm_crtc_helper.c

706

mode_changed = true;

sys/dev/pci/drm/drm_crtc_helper.c

748

mode_changed = true;

sys/dev/pci/drm/drm_crtc_helper.c

764

mode_changed = true;

sys/dev/pci/drm/drm_damage_helper.c

250

iter->full_update = true;

sys/dev/pci/drm/drm_damage_helper.c

280

return true;

sys/dev/pci/drm/drm_damage_helper.c

288

ret = true;

sys/dev/pci/drm/drm_damage_helper.c

331

valid = true;

sys/dev/pci/drm/drm_debugfs_crc.c

233

crc->opened = true;

sys/dev/pci/drm/drm_debugfs_crc.c

416

crc->overflow = true;

sys/dev/pci/drm/drm_drv.c

1194

dev->registered = true;

sys/dev/pci/drm/drm_drv.c

1374

drm_core_init_complete = true;

sys/dev/pci/drm/drm_drv.c

533

return true;

sys/dev/pci/drm/drm_drv.c

572

dev->unplugged = true;

sys/dev/pci/drm/drm_edid.c

1851

return true;

sys/dev/pci/drm/drm_edid.c

2015

*edid_corrupt = true;

sys/dev/pci/drm/drm_edid.c

2049

if (!drm_edid_block_valid(block, i, true, NULL))

sys/dev/pci/drm/drm_edid.c

2053

return true;

sys/dev/pci/drm/drm_edid.c

2083

return true;

sys/dev/pci/drm/drm_edid.c

2408

connector->edid_corrupt = true;

sys/dev/pci/drm/drm_edid.c

3194

*res = true;

sys/dev/pci/drm/drm_edid.c

3456

true);

sys/dev/pci/drm/drm_edid.c

3567

mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);

sys/dev/pci/drm/drm_edid.c

3714

return true;

sys/dev/pci/drm/drm_edid.c

3730

ok = true;

sys/dev/pci/drm/drm_edid.c

4174

closure.preferred = true; /* first detailed timing is always preferred */

sys/dev/pci/drm/drm_edid.c

4248

found = true;

sys/dev/pci/drm/drm_edid.c

4255

return true;

sys/dev/pci/drm/drm_edid.c

4261

found = true;

sys/dev/pci/drm/drm_edid.c

4350

return true;

sys/dev/pci/drm/drm_edid.c

5526

connector->latency_present[0] = true;

sys/dev/pci/drm/drm_edid.c

5532

connector->latency_present[1] = true;

sys/dev/pci/drm/drm_edid.c

5571

closure->matched = true;

sys/dev/pci/drm/drm_edid.c

5601

return true;

sys/dev/pci/drm/drm_edid.c

5936

hdmi = true;

sys/dev/pci/drm/drm_edid.c

5996

has_audio = true;

sys/dev/pci/drm/drm_edid.c

6114

return true;

sys/dev/pci/drm/drm_edid.c

6148

info->rgb_quant_range_selectable = true;

sys/dev/pci/drm/drm_edid.c

6278

info->has_hdmi_infoframe = true;

sys/dev/pci/drm/drm_edid.c

6281

hdmi->scdc.supported = true;

sys/dev/pci/drm/drm_edid.c

6283

hdmi->scdc.read_request = true;

sys/dev/pci/drm/drm_edid.c

6306

scdc->scrambling.supported = true;

sys/dev/pci/drm/drm_edid.c

6310

scdc->scrambling.low_rates = true;

sys/dev/pci/drm/drm_edid.c

6324

dsc_support = true;

sys/dev/pci/drm/drm_edid.c

6400

info->is_hdmi = true;

sys/dev/pci/drm/drm_edid.c

6416

info->has_hdmi_infoframe = true;

sys/dev/pci/drm/drm_edid.c

6438

info->non_desktop = true;

sys/dev/pci/drm/drm_edid.c

6476

info->has_audio = true;

sys/dev/pci/drm/drm_edid.c

6504

info->has_audio = true;

sys/dev/pci/drm/drm_edid.c

6704

info->non_desktop = true;

sys/dev/pci/drm/drm_edid.c

6807

info->non_desktop = true;

sys/dev/pci/drm/drm_edid.c

7270

return true;

sys/dev/pci/drm/drm_edid.c

7555

connector->has_tile = true;

sys/dev/pci/drm/drm_edid.c

7557

connector->tile_is_single_monitor = true;

sys/dev/pci/drm/drm_encoder.c

318

uses_atomic = true;

sys/dev/pci/drm/drm_exec.c

133

return true;

sys/dev/pci/drm/drm_exec.c

138

return true;

sys/dev/pci/drm/drm_fb_helper.c

1382

force = true;

sys/dev/pci/drm/drm_fb_helper.c

1594

bool lastv = true, lasth = true;

sys/dev/pci/drm/drm_fb_helper.c

1884

fb_helper->deferred_setup = true;

sys/dev/pci/drm/drm_fb_helper.c

2012

fb_helper->delayed_hotplug = true;

sys/dev/pci/drm/drm_fb_helper.c

230

force = true;

sys/dev/pci/drm/drm_fb_helper.c

48

static bool drm_fbdev_emulation = true;

sys/dev/pci/drm/drm_fb_helper.c

535

info->skip_vt_switch = true;

sys/dev/pci/drm/drm_file.c

66

return true;

sys/dev/pci/drm/drm_file.c

986

if (!dma_resv_test_signaled(obj->resv, dma_resv_usage_rw(true))) {

sys/dev/pci/drm/drm_fourcc.c

179

.char_per_block = { 1, }, .block_w = { 8, }, .block_h = { 1, }, .hsub = 1, .vsub = 1, .is_color_indexed = true },

sys/dev/pci/drm/drm_fourcc.c

181

.char_per_block = { 1, }, .block_w = { 4, }, .block_h = { 1, }, .hsub = 1, .vsub = 1, .is_color_indexed = true },

sys/dev/pci/drm/drm_fourcc.c

183

.char_per_block = { 1, }, .block_w = { 2, }, .block_h = { 1, }, .hsub = 1, .vsub = 1, .is_color_indexed = true },

sys/dev/pci/drm/drm_fourcc.c

184

{ .format = DRM_FORMAT_C8, .depth = 8, .num_planes = 1, .cpp = { 1, 0, 0 }, .hsub = 1, .vsub = 1, .is_color_indexed = true },

sys/dev/pci/drm/drm_fourcc.c

207

{ .format = DRM_FORMAT_ARGB4444, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

208

{ .format = DRM_FORMAT_ABGR4444, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

209

{ .format = DRM_FORMAT_RGBA4444, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

210

{ .format = DRM_FORMAT_BGRA4444, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

215

{ .format = DRM_FORMAT_ARGB1555, .depth = 15, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

216

{ .format = DRM_FORMAT_ABGR1555, .depth = 15, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

217

{ .format = DRM_FORMAT_RGBA5551, .depth = 15, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

218

{ .format = DRM_FORMAT_BGRA5551, .depth = 15, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

231

{ .format = DRM_FORMAT_RGB565_A8, .depth = 24, .num_planes = 2, .cpp = { 2, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

232

{ .format = DRM_FORMAT_BGR565_A8, .depth = 24, .num_planes = 2, .cpp = { 2, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

237

{ .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

238

{ .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

239

{ .format = DRM_FORMAT_RGBA1010102, .depth = 30, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

240

{ .format = DRM_FORMAT_BGRA1010102, .depth = 30, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

249

{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

250

{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

251

{ .format = DRM_FORMAT_RGBA8888, .depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

252

{ .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

255

{ .format = DRM_FORMAT_ARGB16161616F, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

256

{ .format = DRM_FORMAT_ABGR16161616F, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

257

{ .format = DRM_FORMAT_AXBXGXRX106106106106, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

260

{ .format = DRM_FORMAT_ARGB16161616, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

261

{ .format = DRM_FORMAT_ABGR16161616, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

262

{ .format = DRM_FORMAT_RGB888_A8, .depth = 32, .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

263

{ .format = DRM_FORMAT_BGR888_A8, .depth = 32, .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

264

{ .format = DRM_FORMAT_XRGB8888_A8, .depth = 32, .num_planes = 2, .cpp = { 4, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

265

{ .format = DRM_FORMAT_XBGR8888_A8, .depth = 32, .num_planes = 2, .cpp = { 4, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

266

{ .format = DRM_FORMAT_RGBX8888_A8, .depth = 32, .num_planes = 2, .cpp = { 4, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

267

{ .format = DRM_FORMAT_BGRX8888_A8, .depth = 32, .num_planes = 2, .cpp = { 4, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/drm_fourcc.c

268

{ .format = DRM_FORMAT_YUV410, .depth = 0, .num_planes = 3, .cpp = { 1, 1, 1 }, .hsub = 4, .vsub = 4, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

269

{ .format = DRM_FORMAT_YVU410, .depth = 0, .num_planes = 3, .cpp = { 1, 1, 1 }, .hsub = 4, .vsub = 4, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

270

{ .format = DRM_FORMAT_YUV411, .depth = 0, .num_planes = 3, .cpp = { 1, 1, 1 }, .hsub = 4, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

271

{ .format = DRM_FORMAT_YVU411, .depth = 0, .num_planes = 3, .cpp = { 1, 1, 1 }, .hsub = 4, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

272

{ .format = DRM_FORMAT_YUV420, .depth = 0, .num_planes = 3, .cpp = { 1, 1, 1 }, .hsub = 2, .vsub = 2, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

273

{ .format = DRM_FORMAT_YVU420, .depth = 0, .num_planes = 3, .cpp = { 1, 1, 1 }, .hsub = 2, .vsub = 2, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

274

{ .format = DRM_FORMAT_YUV422, .depth = 0, .num_planes = 3, .cpp = { 1, 1, 1 }, .hsub = 2, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

275

{ .format = DRM_FORMAT_YVU422, .depth = 0, .num_planes = 3, .cpp = { 1, 1, 1 }, .hsub = 2, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

276

{ .format = DRM_FORMAT_YUV444, .depth = 0, .num_planes = 3, .cpp = { 1, 1, 1 }, .hsub = 1, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

277

{ .format = DRM_FORMAT_YVU444, .depth = 0, .num_planes = 3, .cpp = { 1, 1, 1 }, .hsub = 1, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

278

{ .format = DRM_FORMAT_NV12, .depth = 0, .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

279

{ .format = DRM_FORMAT_NV21, .depth = 0, .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

280

{ .format = DRM_FORMAT_NV16, .depth = 0, .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

281

{ .format = DRM_FORMAT_NV61, .depth = 0, .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

282

{ .format = DRM_FORMAT_NV24, .depth = 0, .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

283

{ .format = DRM_FORMAT_NV42, .depth = 0, .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

284

{ .format = DRM_FORMAT_YUYV, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

285

{ .format = DRM_FORMAT_YVYU, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

286

{ .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

287

{ .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

288

{ .format = DRM_FORMAT_XYUV8888, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

289

{ .format = DRM_FORMAT_VUY888, .depth = 0, .num_planes = 1, .cpp = { 3, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

290

{ .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

291

{ .format = DRM_FORMAT_Y210, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

292

{ .format = DRM_FORMAT_Y212, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

293

{ .format = DRM_FORMAT_Y216, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

294

{ .format = DRM_FORMAT_Y410, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

295

{ .format = DRM_FORMAT_Y412, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

296

{ .format = DRM_FORMAT_Y416, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

297

{ .format = DRM_FORMAT_XVYU2101010, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

298

{ .format = DRM_FORMAT_XVYU12_16161616, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

299

{ .format = DRM_FORMAT_XVYU16161616, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

302

.hsub = 2, .vsub = 2, .has_alpha = true, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

305

.hsub = 2, .vsub = 2, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

308

.hsub = 2, .vsub = 2, .has_alpha = true, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

311

.hsub = 2, .vsub = 2, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

314

.hsub = 2, .vsub = 2, .is_yuv = true},

sys/dev/pci/drm/drm_fourcc.c

317

.hsub = 2, .vsub = 2, .is_yuv = true},

sys/dev/pci/drm/drm_fourcc.c

320

.hsub = 2, .vsub = 2, .is_yuv = true},

sys/dev/pci/drm/drm_fourcc.c

324

.vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

327

.is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

330

.is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

333

.is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

337

.vsub = 2, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

341

.vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

345

.vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

349

.vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

353

.vsub = 1, .is_yuv = true },

sys/dev/pci/drm/drm_fourcc.c

356

.hsub = 2, .vsub = 2, .is_yuv = true},

sys/dev/pci/drm/drm_fourcc.c

359

.hsub = 2, .vsub = 2, .is_yuv = true},

sys/dev/pci/drm/drm_fourcc.c

362

.hsub = 2, .vsub = 1, .is_yuv = true},

sys/dev/pci/drm/drm_fourcc.c

365

.hsub = 1, .vsub = 1, .is_yuv = true},

sys/dev/pci/drm/drm_fourcc.c

368

.hsub = 2, .vsub = 2, .is_yuv = true},

sys/dev/pci/drm/drm_fourcc.c

371

.hsub = 2, .vsub = 1, .is_yuv = true},

sys/dev/pci/drm/drm_fourcc.c

374

.hsub = 1, .vsub = 1, .is_yuv = true},

sys/dev/pci/drm/drm_fourcc.c

377

.hsub = 2, .vsub = 2, .is_yuv = true},

sys/dev/pci/drm/drm_fourcc.c

380

.hsub = 2, .vsub = 1, .is_yuv = true},

sys/dev/pci/drm/drm_fourcc.c

383

.hsub = 1, .vsub = 1, .is_yuv = true},

sys/dev/pci/drm/drm_framebuffer.c

1100

disable_crtcs = true;

sys/dev/pci/drm/drm_framebuffer.c

408

found = true;

sys/dev/pci/drm/drm_gem.c

1060

true, timeout);

sys/dev/pci/drm/drm_gem.c

438

return true;

sys/dev/pci/drm/drm_gem.c

496

final = true;

sys/dev/pci/drm/drm_gpusvm.c

1305

while (true) {

sys/dev/pci/drm/drm_gpusvm.c

1427

flags.has_dma_mapping = true;

sys/dev/pci/drm/drm_gpusvm.c

1431

flags.has_devmem_pages = true;

sys/dev/pci/drm/drm_gpusvm.c

1605

return true;

sys/dev/pci/drm/drm_gpusvm.c

1625

range->pages.flags.unmapped = true;

sys/dev/pci/drm/drm_gpusvm.c

1628

range->pages.flags.partial_unmap = true;

sys/dev/pci/drm/drm_gpusvm.c

348

return true;

sys/dev/pci/drm/drm_gpusvm.c

495

notifier->flags.removed = true;

sys/dev/pci/drm/drm_gpusvm.c

718

while (true) {

sys/dev/pci/drm/drm_gpusvm.c

743

return err ? false : true;

sys/dev/pci/drm/drm_gpusvm.c

924

notifier_alloc = true;

sys/dev/pci/drm/drm_gpuvm.c

2381

prev_split = true;

sys/dev/pci/drm/drm_gpuvm.c

2390

next_split = true;

sys/dev/pci/drm/drm_gpuvm.c

2811

return __drm_gpuvm_sm_map_ops_create(gpuvm, req, true);

sys/dev/pci/drm/drm_gpuvm.c

921

true)

sys/dev/pci/drm/drm_ioctl.c

1011

return true;

sys/dev/pci/drm/drm_linux.c

1859

return true;

sys/dev/pci/drm/drm_linux.c

1863

return true;

sys/dev/pci/drm/drm_linux.c

1873

return true;

sys/dev/pci/drm/drm_linux.c

1877

return true;

sys/dev/pci/drm/drm_linux.c

2120

return true;

sys/dev/pci/drm/drm_linux.c

2281

return true;

sys/dev/pci/drm/drm_linux.c

2479

return true;

sys/dev/pci/drm/drm_linux.c

249

ret = true;

sys/dev/pci/drm/drm_linux.c

2505

return true;

sys/dev/pci/drm/drm_linux.c

2845

return true;

sys/dev/pci/drm/drm_linux.c

455

return true;

sys/dev/pci/drm/drm_linux.c

460

return true;

sys/dev/pci/drm/drm_linux.c

465

return true;

sys/dev/pci/drm/drm_linux.c

470

return true;

sys/dev/pci/drm/drm_linux.c

474

return true;

sys/dev/pci/drm/drm_linux.c

478

return true;

sys/dev/pci/drm/drm_linux.c

484

return true;

sys/dev/pci/drm/drm_linux.c

489

return true;

sys/dev/pci/drm/drm_linux.c

513

return true;

sys/dev/pci/drm/drm_linux.c

734

return true;

sys/dev/pci/drm/drm_mipi_dsi.c

395

dsi->attached = true;

sys/dev/pci/drm/drm_mipi_dsi.c

505

return true;

sys/dev/pci/drm/drm_mipi_dsi.c

538

return true;

sys/dev/pci/drm/drm_mm.c

218

leftmost = true;

sys/dev/pci/drm/drm_mm.c

270

bool first = true;

sys/dev/pci/drm/drm_mm.c

826

return true;

sys/dev/pci/drm/drm_mode_object.c

132

return true;

sys/dev/pci/drm/drm_mode_object.c

83

return __drm_mode_object_add(dev, obj, obj_type, true, NULL);

sys/dev/pci/drm/drm_modes.c

1536

return true;

sys/dev/pci/drm/drm_modes.c

1561

return true;

sys/dev/pci/drm/drm_modes.c

1902

found_it = true;

sys/dev/pci/drm/drm_modes.c

1954

mode->bpp_specified = true;

sys/dev/pci/drm/drm_modes.c

1973

mode->refresh_specified = true;

sys/dev/pci/drm/drm_modes.c

1991

mode->interlace = true;

sys/dev/pci/drm/drm_modes.c

1997

mode->margins = true;

sys/dev/pci/drm/drm_modes.c

2060

cvt = true;

sys/dev/pci/drm/drm_modes.c

2063

rb = true;

sys/dev/pci/drm/drm_modes.c

2161

mode->tv_mode_specified = true;

sys/dev/pci/drm/drm_modes.c

2334

cmdline_mode->tv_mode_specified = true;

sys/dev/pci/drm/drm_modes.c

2335

cmdline_mode->specified = true;

sys/dev/pci/drm/drm_modes.c

2416

parse_extras = true;

sys/dev/pci/drm/drm_modes.c

2419

parse_extras = true;

sys/dev/pci/drm/drm_modes.c

2445

mode->specified = true;

sys/dev/pci/drm/drm_modes.c

2460

freestanding = true;

sys/dev/pci/drm/drm_modes.c

2468

mode->bpp_specified = true;

sys/dev/pci/drm/drm_modes.c

2477

mode->refresh_specified = true;

sys/dev/pci/drm/drm_modes.c

2511

return true;

sys/dev/pci/drm/drm_modes.c

358

bt601 = true;

sys/dev/pci/drm/drm_modeset_helper.c

164

primary->format_default = true;

sys/dev/pci/drm/drm_modeset_lock.c

260

ctx->interruptible = true;

sys/dev/pci/drm/drm_modeset_lock.c

364

return modeset_lock(contended, ctx, ctx->interruptible, true);

sys/dev/pci/drm/drm_panel.c

134

panel->prepared = true;

sys/dev/pci/drm/drm_panel.c

236

panel->enabled = true;

sys/dev/pci/drm/drm_panic.c

514

draw_txt_rectangle(sb, font, panic_msg, panic_msg_lines, true, &r_msg, fg_color);

sys/dev/pci/drm/drm_panic.c

800

draw_txt_rectangle(sb, font, panic_msg, panic_msg_lines, true, &r_msg, fg_color);

sys/dev/pci/drm/drm_panic.c

972

return true;

sys/dev/pci/drm/drm_plane.c

1003

return true;

sys/dev/pci/drm/drm_plane.c

933

return true;

sys/dev/pci/drm/drm_plane.c

943

return true;

sys/dev/pci/drm/drm_print.c

321

bool first = true;

sys/dev/pci/drm/drm_privacy_screen_x86.c

49

return (output & 0x10000) ? true : false;

sys/dev/pci/drm/drm_probe_helper.c

1014

return true;

sys/dev/pci/drm/drm_probe_helper.c

259

poll = true;

sys/dev/pci/drm/drm_probe_helper.c

315

dev->mode_config.poll_running = true;

sys/dev/pci/drm/drm_probe_helper.c

598

ret = drm_helper_probe_detect(connector, &ctx, true);

sys/dev/pci/drm/drm_probe_helper.c

627

dev->mode_config.delayed_event = true;

sys/dev/pci/drm/drm_probe_helper.c

67

static bool drm_kms_helper_poll = true;

sys/dev/pci/drm/drm_probe_helper.c

672

drm_mode_prune_invalid(dev, &connector->modes, true);

sys/dev/pci/drm/drm_probe_helper.c

689

drm_mode_prune_invalid(dev, &connector->modes, true);

sys/dev/pci/drm/drm_probe_helper.c

782

repoll = true;

sys/dev/pci/drm/drm_probe_helper.c

804

repoll = true;

sys/dev/pci/drm/drm_probe_helper.c

839

changed = true;

sys/dev/pci/drm/drm_probe_helper.c

930

dev->mode_config.poll_enabled = true;

sys/dev/pci/drm/drm_property.c

580

true, drm_property_free_blob);

sys/dev/pci/drm/drm_property.c

751

return true;

sys/dev/pci/drm/drm_property.c

79

return true;

sys/dev/pci/drm/drm_property.c

897

found = true;

sys/dev/pci/drm/drm_property.c

946

return true;

sys/dev/pci/drm/drm_property.c

953

return true;

sys/dev/pci/drm/drm_property.c

964

return true;

sys/dev/pci/drm/drm_property.c

969

return true;

sys/dev/pci/drm/drm_property.c

976

return true;

sys/dev/pci/drm/drm_property.c

985

return true;

sys/dev/pci/drm/drm_self_refresh_helper.c

112

crtc_state->self_refresh_active = true;

sys/dev/pci/drm/drm_self_refresh_helper.c

198

state->allow_modeset = true;

sys/dev/pci/drm/drm_suballoc.c

183

return true;

sys/dev/pci/drm/drm_suballoc.c

196

return true;

sys/dev/pci/drm/drm_suballoc.c

238

return true;

sys/dev/pci/drm/drm_suballoc.c

290

return true;

sys/dev/pci/drm/drm_syncobj.c

1491

NULL, args, syncobjs, true, tp);

sys/dev/pci/drm/drm_vblank.c

1191

WRITE_ONCE(vblank->enabled, true);

sys/dev/pci/drm/drm_vblank.c

1919

high_prec = true;

sys/dev/pci/drm/drm_vblank.c

1961

drm_update_vblank_count(dev, pipe, true);

sys/dev/pci/drm/drm_vblank.c

1984

return true;

sys/dev/pci/drm/drm_vblank.c

794

return true;

sys/dev/pci/drm/drm_vblank.c

806

return true;

sys/dev/pci/drm/drm_vblank_work.c

141

rescheduling = true;

sys/dev/pci/drm/drm_vblank_work.c

158

wake = true;

sys/dev/pci/drm/drm_vblank_work.c

163

ret = true;

sys/dev/pci/drm/drm_vblank_work.c

199

ret = true;

sys/dev/pci/drm/drm_vblank_work.c

208

ret = true;

sys/dev/pci/drm/drm_vblank_work.c

65

wake = true;

sys/dev/pci/drm/drm_vma_manager.c

316

return vma_node_allow(node, tag, true);

sys/dev/pci/drm/hdmi.c

1599

frame->itc = ptr[2] & 0x80 ? true : false;

sys/dev/pci/drm/hdmi.c

1699

frame->downmix_inhibit = ptr[4] & 0x80 ? true : false;

sys/dev/pci/drm/i915/display/dvo_ch7017.c

239

return true;

sys/dev/pci/drm/i915/display/dvo_ch7017.c

374

return true;

sys/dev/pci/drm/i915/display/dvo_ch7xxx.c

176

return true;

sys/dev/pci/drm/i915/display/dvo_ch7xxx.c

203

return true;

sys/dev/pci/drm/i915/display/dvo_ch7xxx.c

227

ch7xxx->quiet = true;

sys/dev/pci/drm/i915/display/dvo_ch7xxx.c

253

return true;

sys/dev/pci/drm/i915/display/dvo_ch7xxx.c

350

return true;

sys/dev/pci/drm/i915/display/dvo_ivch.c

225

return true;

sys/dev/pci/drm/i915/display/dvo_ivch.c

254

return true;

sys/dev/pci/drm/i915/display/dvo_ivch.c

278

priv->quiet = true;

sys/dev/pci/drm/i915/display/dvo_ivch.c

306

return true;

sys/dev/pci/drm/i915/display/dvo_ivch.c

394

return true;

sys/dev/pci/drm/i915/display/dvo_ns2501.c

420

return true;

sys/dev/pci/drm/i915/display/dvo_ns2501.c

455

return true;

sys/dev/pci/drm/i915/display/dvo_ns2501.c

485

ns->quiet = true;

sys/dev/pci/drm/i915/display/dvo_ns2501.c

508

return true;

sys/dev/pci/drm/i915/display/dvo_sil164.c

102

return true;

sys/dev/pci/drm/i915/display/dvo_sil164.c

128

return true;

sys/dev/pci/drm/i915/display/dvo_sil164.c

152

sil->quiet = true;

sys/dev/pci/drm/i915/display/dvo_sil164.c

174

return true;

sys/dev/pci/drm/i915/display/dvo_sil164.c

251

return true;

sys/dev/pci/drm/i915/display/dvo_tfp410.c

123

return true;

sys/dev/pci/drm/i915/display/dvo_tfp410.c

149

return true;

sys/dev/pci/drm/i915/display/dvo_tfp410.c

184

tfp->quiet = true;

sys/dev/pci/drm/i915/display/dvo_tfp410.c

200

return true;

sys/dev/pci/drm/i915/display/dvo_tfp410.c

263

return true;

sys/dev/pci/drm/i915/display/g4x_dp.c

1235

crtc_state->has_pch_encoder = true;

sys/dev/pci/drm/i915/display/g4x_dp.c

1270

intel_dp->reset_link_params = true;

sys/dev/pci/drm/i915/display/g4x_dp.c

1421

return true;

sys/dev/pci/drm/i915/display/g4x_dp.c

192

#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)

sys/dev/pci/drm/i915/display/g4x_dp.c

263

return true;

sys/dev/pci/drm/i915/display/g4x_dp.c

359

pipe_config->enhanced_framing = true;

sys/dev/pci/drm/i915/display/g4x_dp.c

372

pipe_config->enhanced_framing = true;

sys/dev/pci/drm/i915/display/g4x_dp.c

388

pipe_config->limited_color_range = true;

sys/dev/pci/drm/i915/display/g4x_dp.c

456

intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true);

sys/dev/pci/drm/i915/display/g4x_dp.c

457

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);

sys/dev/pci/drm/i915/display/g4x_dp.c

572

chv_data_lane_soft_reset(encoder, old_crtc_state, true);

sys/dev/pci/drm/i915/display/g4x_dp.c

700

intel_pps_vdd_off_unlocked(intel_dp, true);

sys/dev/pci/drm/i915/display/g4x_dp.c

86

pipe_config->clock_set = true;

sys/dev/pci/drm/i915/display/g4x_dp.c

937

uniq_trans_scale = true;

sys/dev/pci/drm/i915/display/g4x_hdmi.c

139

crtc_state->has_pch_encoder = true;

sys/dev/pci/drm/i915/display/g4x_hdmi.c

173

pipe_config->has_hdmi_sink = true;

sys/dev/pci/drm/i915/display/g4x_hdmi.c

179

pipe_config->has_infoframe = true;

sys/dev/pci/drm/i915/display/g4x_hdmi.c

182

pipe_config->has_audio = true;

sys/dev/pci/drm/i915/display/g4x_hdmi.c

186

pipe_config->limited_color_range = true;

sys/dev/pci/drm/i915/display/g4x_hdmi.c

37

intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

422

intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

423

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

537

chv_data_lane_soft_reset(encoder, old_crtc_state, true);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

644

crtc_state->mode_changed = true;

sys/dev/pci/drm/i915/display/g4x_hdmi.c

769

return true;

sys/dev/pci/drm/i915/display/hsw_ips.c

108

return true;

sys/dev/pci/drm/i915/display/hsw_ips.c

119

return true;

sys/dev/pci/drm/i915/display/hsw_ips.c

149

return true;

sys/dev/pci/drm/i915/display/hsw_ips.c

160

return true;

sys/dev/pci/drm/i915/display/hsw_ips.c

167

return true;

sys/dev/pci/drm/i915/display/hsw_ips.c

218

return true;

sys/dev/pci/drm/i915/display/hsw_ips.c

272

crtc_state->ips_enabled = true;

sys/dev/pci/drm/i915/display/hsw_ips.c

293

crtc_state->ips_enabled = true;

sys/dev/pci/drm/i915/display/hsw_ips.c

90

need_vblank_wait = true;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1057

plane->need_async_flip_toggle_wa = true;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1276

return true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1196

return true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1364

new_crtc_state->wm.need_postvbl_update = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1391

wm->cxsr = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1392

wm->hpll_en = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1393

wm->fbc_en = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

1439

if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))

sys/dev/pci/drm/i915/display/i9xx_wm.c

1444

if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))

sys/dev/pci/drm/i915/display/i9xx_wm.c

1445

_intel_set_memory_cxsr(display, true);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1852

crtc_state->fifo_changed = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2007

new_crtc_state->wm.need_postvbl_update = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2035

wm->cxsr = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2087

if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))

sys/dev/pci/drm/i915/display/i9xx_wm.c

2092

if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))

sys/dev/pci/drm/i915/display/i9xx_wm.c

2093

_intel_set_memory_cxsr(display, true);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2096

chv_set_memory_pm5(display, true);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2099

chv_set_memory_dvfs(display, true);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2181

cxsr_enabled = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2206

intel_set_memory_cxsr(display, true);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2365

intel_set_memory_cxsr(display, true);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2649

max->spr = ilk_plane_wm_max(display, level, config, ddb_partitioning, true);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2659

max->spr = ilk_plane_wm_reg_max(display, level, true);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2703

result->enable = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2741

result->enable = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2817

return true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2918

return true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3053

new_crtc_state->wm.need_postvbl_update = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3083

ret_wm->enable = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3332

changed = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3337

changed = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3342

changed = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3519

active->wm[0].enable = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3532

active->wm[level].enable = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3555

crtc_state->inherited = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3606

to_intel_atomic_state(state)->internal = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3615

intel_state->skip_intermediate_wm = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3627

crtc_state->wm.need_postvbl_update = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

712

intel_set_memory_cxsr(display, true);

sys/dev/pci/drm/i915/display/i9xx_wm.c

723

return true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

734

return true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

757

new_crtc_state->update_wm_pre = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

759

new_crtc_state->update_wm_post = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

762

new_crtc_state->update_wm_pre = true;

sys/dev/pci/drm/i915/display/i9xx_wm.c

763

new_crtc_state->update_wm_post = true;

sys/dev/pci/drm/i915/display/icl_dsi.c

103

return true;

sys/dev/pci/drm/i915/display/icl_dsi.c

1155

gen11_dsi_config_util_pin(encoder, true);

sys/dev/pci/drm/i915/display/icl_dsi.c

1286

icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true);

sys/dev/pci/drm/i915/display/icl_dsi.c

1658

crtc_state->dsc.compression_enable = true;

sys/dev/pci/drm/i915/display/icl_dsi.c

1698

pipe_config->clock_set = true;

sys/dev/pci/drm/i915/display/icl_dsi.c

1773

crtc_state->uapi.mode_changed = true;

sys/dev/pci/drm/i915/display/icl_dsi.c

1778

return true;

sys/dev/pci/drm/i915/display/icl_dsi.c

1833

enable_lpdt = true;

sys/dev/pci/drm/i915/display/icl_dsi.c

436

intel_combo_phy_power_up_lanes(display, phy, true,

sys/dev/pci/drm/i915/display/icl_dsi.c

666

clock_enabled = true;

sys/dev/pci/drm/i915/display/icl_dsi.c

87

return true;

sys/dev/pci/drm/i915/display/intel_alpm.c

164

return true;

sys/dev/pci/drm/i915/display/intel_alpm.c

174

return true;

sys/dev/pci/drm/i915/display/intel_alpm.c

191

return true;

sys/dev/pci/drm/i915/display/intel_alpm.c

261

return true;

sys/dev/pci/drm/i915/display/intel_alpm.c

596

return true;

sys/dev/pci/drm/i915/display/intel_alpm.c

604

return true;

sys/dev/pci/drm/i915/display/intel_atomic.c

146

crtc_state->mode_changed = true;

sys/dev/pci/drm/i915/display/intel_atomic.c

207

return true;

sys/dev/pci/drm/i915/display/intel_audio.c

1063

glk_force_audio_cdclk(display, true);

sys/dev/pci/drm/i915/display/intel_audio.c

1382

display->audio.component_registered = true;

sys/dev/pci/drm/i915/display/intel_audio.c

573

intel_audio_sdp_split_update(crtc_state, true);

sys/dev/pci/drm/i915/display/intel_audio.c

725

return true;

sys/dev/pci/drm/i915/display/intel_audio.c

977

to_intel_atomic_state(state)->internal = true;

sys/dev/pci/drm/i915/display/intel_backlight.c

1508

return true;

sys/dev/pci/drm/i915/display/intel_backlight.c

1594

panel->backlight.pwm_enabled = true;

sys/dev/pci/drm/i915/display/intel_backlight.c

1724

panel->backlight.present = true;

sys/dev/pci/drm/i915/display/intel_backlight.c

782

panel->backlight.pwm_state.enabled = true;

sys/dev/pci/drm/i915/display/intel_backlight.c

805

panel->backlight.enabled = true;

sys/dev/pci/drm/i915/display/intel_bios.c

1200

display->vbt.override_afc_startup = true;

sys/dev/pci/drm/i915/display/intel_bios.c

1372

panel->vbt.vrr = true; /* matches Windows behaviour */

sys/dev/pci/drm/i915/display/intel_bios.c

2663

return true;

sys/dev/pci/drm/i915/display/intel_bios.c

2826

return true;

sys/dev/pci/drm/i915/display/intel_bios.c

2926

panel->vbt.backlight.present = true;

sys/dev/pci/drm/i915/display/intel_bios.c

2929

panel->vbt.lvds_dither = true;

sys/dev/pci/drm/i915/display/intel_bios.c

314

return true;

sys/dev/pci/drm/i915/display/intel_bios.c

3283

intel_bios_init_panel(display, panel, devdata, drm_edid, true);

sys/dev/pci/drm/i915/display/intel_bios.c

3339

return true;

sys/dev/pci/drm/i915/display/intel_bios.c

3359

return true;

sys/dev/pci/drm/i915/display/intel_bios.c

3378

return true;

sys/dev/pci/drm/i915/display/intel_bios.c

3400

return true;

sys/dev/pci/drm/i915/display/intel_bios.c

3425

return true;

sys/dev/pci/drm/i915/display/intel_bios.c

3434

return true;

sys/dev/pci/drm/i915/display/intel_bios.c

3452

return true;

sys/dev/pci/drm/i915/display/intel_bios.c

3457

return true;

sys/dev/pci/drm/i915/display/intel_bios.c

3490

return true;

sys/dev/pci/drm/i915/display/intel_bios.c

3583

return true;

sys/dev/pci/drm/i915/display/intel_bios.c

680

drm_edid_print_product_id(&p, &product_id, true);

sys/dev/pci/drm/i915/display/intel_bw.c

1274

return true;

sys/dev/pci/drm/i915/display/intel_bw.c

1293

return true;

sys/dev/pci/drm/i915/display/intel_bw.c

1297

return true;

sys/dev/pci/drm/i915/display/intel_bw.c

1477

*need_cdclk_calc = true;

sys/dev/pci/drm/i915/display/intel_bw.c

1516

*changed = true;

sys/dev/pci/drm/i915/display/intel_bw.c

1637

changed = true;

sys/dev/pci/drm/i915/display/intel_bw.c

1768

return true;

sys/dev/pci/drm/i915/display/intel_bw.c

468

bool is_y_tile = true; /* assume y tile may be used */

sys/dev/pci/drm/i915/display/intel_bw.c

539

bool is_y_tile = true; /* assume y tile may be used */

sys/dev/pci/drm/i915/display/intel_bw.c

686

ret = icl_get_qgv_points(display, dram_info, &qi, true);

sys/dev/pci/drm/i915/display/intel_cdclk.c

2090

return true;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3216

*need_cdclk_calc = true;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3350

new_cdclk_state->disable_pipes = true;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3915

return true;

sys/dev/pci/drm/i915/display/intel_color.c

1073

crtc_state->gamma_enable = true;

sys/dev/pci/drm/i915/display/intel_color.c

1076

crtc_state->csc_enable = true;

sys/dev/pci/drm/i915/display/intel_color.c

1101

crtc_state->gamma_enable = true;

sys/dev/pci/drm/i915/display/intel_color.c

1104

crtc_state->csc_enable = true;

sys/dev/pci/drm/i915/display/intel_color.c

2098

new_crtc_state->uapi.color_mgmt_changed = true;

sys/dev/pci/drm/i915/display/intel_color.c

2130

return true;

sys/dev/pci/drm/i915/display/intel_color.c

2185

new_crtc_state->disable_cxsr = true;

sys/dev/pci/drm/i915/display/intel_color.c

2553

true);

sys/dev/pci/drm/i915/display/intel_color.c

2788

true);

sys/dev/pci/drm/i915/display/intel_color.c

3003

return true;

sys/dev/pci/drm/i915/display/intel_color.c

3084

return true;

sys/dev/pci/drm/i915/display/intel_color.c

3139

return true;

sys/dev/pci/drm/i915/display/intel_color.c

3157

return true;

sys/dev/pci/drm/i915/display/intel_combo_phy.c

109

return true;

sys/dev/pci/drm/i915/display/intel_combo_phy.c

148

return true;

sys/dev/pci/drm/i915/display/intel_combo_phy.c

176

return true;

sys/dev/pci/drm/i915/display/intel_combo_phy.c

209

return true;

sys/dev/pci/drm/i915/display/intel_combo_phy.c

221

bool ret = true;

sys/dev/pci/drm/i915/display/intel_crt.c

1070

connector->base.interlace_allowed = true;

sys/dev/pci/drm/i915/display/intel_crt.c

284

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);

sys/dev/pci/drm/i915/display/intel_crt.c

340

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_crt.c

341

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);

sys/dev/pci/drm/i915/display/intel_crt.c

424

crtc_state->has_pch_encoder = true;

sys/dev/pci/drm/i915/display/intel_crt.c

449

crtc_state->has_pch_encoder = true;

sys/dev/pci/drm/i915/display/intel_crt.c

470

crtc_state->enhanced_framing = true;

sys/dev/pci/drm/i915/display/intel_crt.c

517

ret = true;

sys/dev/pci/drm/i915/display/intel_crt.c

566

ret = true;

sys/dev/pci/drm/i915/display/intel_crt.c

615

ret = true;

sys/dev/pci/drm/i915/display/intel_crt.c

636

intel_gmbus_force_bit(ddc, true);

sys/dev/pci/drm/i915/display/intel_crt.c

682

ret = true;

sys/dev/pci/drm/i915/display/intel_crt.c

764

restore_vblank = true;

sys/dev/pci/drm/i915/display/intel_crt.c

977

crt->force_hotplug_required = true;

sys/dev/pci/drm/i915/display/intel_cursor.c

156

true);

sys/dev/pci/drm/i915/display/intel_cursor.c

467

return true;

sys/dev/pci/drm/i915/display/intel_cursor.c

578

true);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2069

pll_state->use_c10 = true;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2101

crtc_state->dpll_hw_state.cx0pll.use_c10 = true;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2593

return true;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

26

#define MB_WRITE_COMMITTED true

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2606

return true;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3466

pll_state->use_c10 = true;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3484

return true;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3504

return true;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3511

return true;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3653

true, port_clock,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3664

__intel_cx0pll_enable(encoder, &pll_state, true, port_clock, 4);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

50

return true;

sys/dev/pci/drm/i915/display/intel_ddi.c

2421

ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true);

sys/dev/pci/drm/i915/display/intel_ddi.c

2438

ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true);

sys/dev/pci/drm/i915/display/intel_ddi.c

2512

drm_WARN(display->drm, true,

sys/dev/pci/drm/i915/display/intel_ddi.c

2691

intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);

sys/dev/pci/drm/i915/display/intel_ddi.c

2851

intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);

sys/dev/pci/drm/i915/display/intel_ddi.c

2936

intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);

sys/dev/pci/drm/i915/display/intel_ddi.c

2987

intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);

sys/dev/pci/drm/i915/display/intel_ddi.c

3032

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_ddi.c

3381

intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);

sys/dev/pci/drm/i915/display/intel_ddi.c

3548

intel_ddi_wait_for_fec_status(encoder, crtc_state, true);

sys/dev/pci/drm/i915/display/intel_ddi.c

3628

intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);

sys/dev/pci/drm/i915/display/intel_ddi.c

4003

crtc_state->has_hdmi_sink = true;

sys/dev/pci/drm/i915/display/intel_ddi.c

4009

crtc_state->has_infoframe = true;

sys/dev/pci/drm/i915/display/intel_ddi.c

4012

crtc_state->hdmi_scrambling = true;

sys/dev/pci/drm/i915/display/intel_ddi.c

4014

crtc_state->hdmi_high_tmds_clock_ratio = true;

sys/dev/pci/drm/i915/display/intel_ddi.c

4400

bool fastset = true;

sys/dev/pci/drm/i915/display/intel_ddi.c

4405

crtc_state->uapi.mode_changed = true;

sys/dev/pci/drm/i915/display/intel_ddi.c

4609

intel_dp->reset_link_params = true;

sys/dev/pci/drm/i915/display/intel_ddi.c

4875

return true;

sys/dev/pci/drm/i915/display/intel_ddi.c

4906

dig_port->ddi_a_4_lanes = true;

sys/dev/pci/drm/i915/display/intel_ddi.c

5028

return true;

sys/dev/pci/drm/i915/display/intel_ddi.c

5040

return true; /* no strap for DDI-E */

sys/dev/pci/drm/i915/display/intel_ddi.c

5066

return true;

sys/dev/pci/drm/i915/display/intel_ddi.c

5168

init_dp = true;

sys/dev/pci/drm/i915/display/intel_ddi.c

663

intel_ddi_config_transcoder_dp2(crtc_state, true);

sys/dev/pci/drm/i915/display/intel_ddi.c

947

return true;

sys/dev/pci/drm/i915/display/intel_de.h

205

trace_i915_reg_rw(false, reg, val, sizeof(val), true);

sys/dev/pci/drm/i915/display/intel_de.h

213

trace_i915_reg_rw(true, reg, val, sizeof(val), true);

sys/dev/pci/drm/i915/display/intel_display.c

1169

need_vbl_wait = true;

sys/dev/pci/drm/i915/display/intel_display.c

1208

intel_async_flip_vtd_wa(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

1213

skl_wa_827(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

1218

icl_wa_scalerclkgating(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

1223

icl_wa_cursorclkgating(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

1405

intel_opregion_notify_encoder(encoder, true);

sys/dev/pci/drm/i915/display/intel_display.c

1546

crtc->active = true;

sys/dev/pci/drm/i915/display/intel_display.c

1588

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

1589

intel_set_pch_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

1703

pipe_crtc->active = true;

sys/dev/pci/drm/i915/display/intel_display.c

1706

glk_pipe_scaler_clock_gating_wa(pipe_crtc, true);

sys/dev/pci/drm/i915/display/intel_display.c

1786

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

1787

intel_set_pch_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

2058

crtc->active = true;

sys/dev/pci/drm/i915/display/intel_display.c

2060

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

2098

crtc->active = true;

sys/dev/pci/drm/i915/display/intel_display.c

2101

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

2407

crtc_state->double_wide = true;

sys/dev/pci/drm/i915/display/intel_display.c

3062

pipe_config->limited_color_range = true;

sys/dev/pci/drm/i915/display/intel_display.c

3070

pipe_config->wgc_enable = true;

sys/dev/pci/drm/i915/display/intel_display.c

3117

ret = true;

sys/dev/pci/drm/i915/display/intel_display.c

3399

pipe_config->limited_color_range = true;

sys/dev/pci/drm/i915/display/intel_display.c

3430

ret = true;

sys/dev/pci/drm/i915/display/intel_display.c

3859

pipe_config->pch_pfit.force_thru = true;

sys/dev/pci/drm/i915/display/intel_display.c

3944

active = true;

sys/dev/pci/drm/i915/display/intel_display.c

4027

crtc_state->hw.active = true;

sys/dev/pci/drm/i915/display/intel_display.c

4031

return true;

sys/dev/pci/drm/i915/display/intel_display.c

4147

return true;

sys/dev/pci/drm/i915/display/intel_display.c

4239

crtc_state->update_wm_post = true;

sys/dev/pci/drm/i915/display/intel_display.c

437

state = true;

sys/dev/pci/drm/i915/display/intel_display.c

4386

bool ret = true;

sys/dev/pci/drm/i915/display/intel_display.c

4654

crtc_state->bw_constrained = true;

sys/dev/pci/drm/i915/display/intel_display.c

471

#define assert_plane_enabled(p) assert_plane(p, true)

sys/dev/pci/drm/i915/display/intel_display.c

4793

return true;

sys/dev/pci/drm/i915/display/intel_display.c

4801

return true;

sys/dev/pci/drm/i915/display/intel_display.c

5017

bool ret = true;

sys/dev/pci/drm/i915/display/intel_display.c

5339

PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true);

sys/dev/pci/drm/i915/display/intel_display.c

5505

crtc_state->uapi.mode_changed = true;

sys/dev/pci/drm/i915/display/intel_display.c

5551

crtc_state->uapi.mode_changed = true;

sys/dev/pci/drm/i915/display/intel_display.c

5614

to_intel_atomic_state(state)->internal = true;

sys/dev/pci/drm/i915/display/intel_display.c

5625

crtc_state->uapi.connectors_changed = true;

sys/dev/pci/drm/i915/display/intel_display.c

5717

state->modeset = true;

sys/dev/pci/drm/i915/display/intel_display.c

5743

if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) {

sys/dev/pci/drm/i915/display/intel_display.c

5748

new_crtc_state->update_lrr = true;

sys/dev/pci/drm/i915/display/intel_display.c

5763

new_crtc_state->update_pipe = true;

sys/dev/pci/drm/i915/display/intel_display.c

5799

return true;

sys/dev/pci/drm/i915/display/intel_display.c

5816

return true;

sys/dev/pci/drm/i915/display/intel_display.c

6219

crtc_state->uapi.mode_changed = true;

sys/dev/pci/drm/i915/display/intel_display.c

6315

while (true) {

sys/dev/pci/drm/i915/display/intel_display.c

6372

new_crtc_state->uapi.mode_changed = true;

sys/dev/pci/drm/i915/display/intel_display.c

6376

new_crtc_state->uapi.mode_changed = true;

sys/dev/pci/drm/i915/display/intel_display.c

6465

any_ms = true;

sys/dev/pci/drm/i915/display/intel_display.c

6494

any_ms = true;

sys/dev/pci/drm/i915/display/intel_display.c

6574

intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

6580

intel_set_pch_fifo_underrun_reporting(display, pch_transcoder, true);

sys/dev/pci/drm/i915/display/intel_display.c

6711

intel_psr_notify_pipe_change(state, crtc, true);

sys/dev/pci/drm/i915/display/intel_display.c

7313

new_crtc_state->dsb_color, true);

sys/dev/pci/drm/i915/display/intel_display.c

7496

intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

7606

ret = drm_atomic_helper_swap_state(&state->base, true);

sys/dev/pci/drm/i915/display/intel_display.c

7727

return true;

sys/dev/pci/drm/i915/display/intel_display.c

7749

return true;

sys/dev/pci/drm/i915/display/intel_display.c

778

try_wait_for_completion(&commit->cleanup_done) : true;

sys/dev/pci/drm/i915/display/intel_display.c

786

return true;

sys/dev/pci/drm/i915/display/intel_display.c

8172

to_intel_atomic_state(state)->internal = true;

sys/dev/pci/drm/i915/display/intel_display.c

8200

crtc_state->uapi.color_mgmt_changed = true;

sys/dev/pci/drm/i915/display/intel_display.c

843

return true;

sys/dev/pci/drm/i915/display/intel_display.c

854

return true;

sys/dev/pci/drm/i915/display/intel_display.c

867

return true;

sys/dev/pci/drm/i915/display/intel_display.h

540

#define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true)

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

903

try_again = true;

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

917

try_again = true;

sys/dev/pci/drm/i915/display/intel_display_device.c

1355

.__runtime_defaults.has_dbuf_overlap_detection = true,

sys/dev/pci/drm/i915/display/intel_display_driver.c

356

set_display_access(display, true, NULL);

sys/dev/pci/drm/i915/display/intel_display_driver.c

447

return true;

sys/dev/pci/drm/i915/display/intel_display_driver.c

75

return true;

sys/dev/pci/drm/i915/display/intel_display_driver.c

770

crtc_state->mode_changed = true;

sys/dev/pci/drm/i915/display/intel_display_driver.c

775

to_intel_atomic_state(state)->skip_intermediate_wm = true;

sys/dev/pci/drm/i915/display/intel_display_driver.c

81

return true;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1086

return true;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1097

return true;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1108

return true;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1193

found = true;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1205

found = true;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1211

found = true;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1215

found = true;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1235

found = true;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1379

found = true;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1387

found = true;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1394

found = true;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1401

found = true;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1409

found = true;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1702

return true;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1721

if (gen11_dsi_configure_te(crtc, true))

sys/dev/pci/drm/i915/display/intel_display_irq.c

2156

display->irq.vlv_display_irqs_enabled = true;

sys/dev/pci/drm/i915/display/intel_display_irq.c

2375

display->drm->vblank_disable_immediate = true;

sys/dev/pci/drm/i915/display/intel_display_irq.c

373

return true;

sys/dev/pci/drm/i915/display/intel_display_irq.c

376

return true;

sys/dev/pci/drm/i915/display/intel_display_irq.c

430

drm_crtc_add_crc_entry(&crtc->base, true,

sys/dev/pci/drm/i915/display/intel_display_irq.c

591

blc_event = true;

sys/dev/pci/drm/i915/display/intel_display_irq.c

615

blc_event = true;

sys/dev/pci/drm/i915/display/intel_display_irq.c

98

return true;

sys/dev/pci/drm/i915/display/intel_display_params.h

32

param(bool, enable_dpt, true, 0400) \

sys/dev/pci/drm/i915/display/intel_display_params.h

33

param(bool, enable_dsb, true, 0600) \

sys/dev/pci/drm/i915/display/intel_display_params.h

35

param(bool, enable_sagv, true, 0600) \

sys/dev/pci/drm/i915/display/intel_display_params.h

37

param(bool, enable_ips, true, 0600) \

sys/dev/pci/drm/i915/display/intel_display_params.h

44

param(bool, verbose_state_checks, true, 0400) \

sys/dev/pci/drm/i915/display/intel_display_params.h

46

param(bool, enable_dp_mst, true, 0600) \

sys/dev/pci/drm/i915/display/intel_display_params.h

51

param(bool, enable_psr2_sel_fetch, true, 0400) \

sys/dev/pci/drm/i915/display/intel_display_power.c

1417

hsw_disable_lcpll(display, true, true);

sys/dev/pci/drm/i915/display/intel_display_power.c

1836

display->power.chv_phy_assert[DPIO_PHY0] = true;

sys/dev/pci/drm/i915/display/intel_display_power.c

1858

display->power.chv_phy_assert[DPIO_PHY1] = true;

sys/dev/pci/drm/i915/display/intel_display_power.c

1950

power_domains->initializing = true;

sys/dev/pci/drm/i915/display/intel_display_power.c

2147

power_domains->display_core_suspended = true;

sys/dev/pci/drm/i915/display/intel_display_power.c

216

is_enabled = true;

sys/dev/pci/drm/i915/display/intel_display_power.c

2165

intel_power_domains_init_hw(display, true);

sys/dev/pci/drm/i915/display/intel_display_power.c

2240

dump_domain_info = true;

sys/dev/pci/drm/i915/display/intel_display_power.c

2249

dumped = true;

sys/dev/pci/drm/i915/display/intel_display_power.c

2316

icl_display_core_init(display, true);

sys/dev/pci/drm/i915/display/intel_display_power.c

2325

bxt_display_core_init(display, true);

sys/dev/pci/drm/i915/display/intel_display_power.c

503

ret = true;

sys/dev/pci/drm/i915/display/intel_display_power.c

589

is_enabled = true;

sys/dev/pci/drm/i915/display/intel_display_power.c

835

cancel_async_put_work(power_domains, true);

sys/dev/pci/drm/i915/display/intel_display_power.c

916

return true;

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1074

.has_vga = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1075

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1082

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

115

.has_vga = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1160

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1169

.has_vga = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1170

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1177

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1185

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1328

.has_vga = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1329

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1337

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1345

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1353

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1361

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1384

.fixed_enable_delay = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1393

.fixed_enable_delay = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1404

.is_tc_tbt = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1485

.has_vga = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1486

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

149

.has_vga = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1494

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1502

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1510

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1518

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1646

.has_vga = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1647

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1655

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1663

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1671

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1679

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1728

.has_vga = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1729

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1737

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1745

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1753

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

365

.always_on = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

366

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

379

.always_on = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

393

.has_vga = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

395

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

472

.has_vga = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

474

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

575

.has_vga = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

577

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

58

.always_on = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

724

.always_on = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

725

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

743

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

751

.has_vga = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

753

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

782

.is_tc_tbt = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

790

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

909

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

917

.has_vga = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

919

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

939

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

947

.has_fuses = true,

sys/dev/pci/drm/i915/display/intel_display_power_map.c

986

.is_tc_tbt = true,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1087

return true;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1163

vlv_set_power_well(display, power_well, true);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1194

enabled = true;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

120

power_well->hw_enabled = true;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1303

vlv_set_power_well(display, power_well, true);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1322

vlv_set_power_well(display, power_well, true);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1478

vlv_set_power_well(display, power_well, true);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1552

display->power.chv_phy_assert[phy] = true;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1762

chv_set_pipe_power_well(display, power_well, true);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1820

tgl_tc_cold_request(display, true);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

801

intel_dmc_update_dc6_allowed_count(display, true);

sys/dev/pci/drm/i915/display/intel_display_reset.c

62

return true;

sys/dev/pci/drm/i915/display/intel_display_reset.c

70

return true;

sys/dev/pci/drm/i915/display/intel_display_reset.c

76

return true;

sys/dev/pci/drm/i915/display/intel_display_types.h

1958

return true;

sys/dev/pci/drm/i915/display/intel_display_types.h

2026

return true;

sys/dev/pci/drm/i915/display/intel_display_types.h

2039

return true;

sys/dev/pci/drm/i915/display/intel_dmc.c

1019

return true;

sys/dev/pci/drm/i915/display/intel_dmc.c

1581

return true;

sys/dev/pci/drm/i915/display/intel_dmc.c

1721

dmc_configure_event(display, dmc_id, event, true);

sys/dev/pci/drm/i915/display/intel_dmc.c

577

return true;

sys/dev/pci/drm/i915/display/intel_dmc.c

592

return true;

sys/dev/pci/drm/i915/display/intel_dmc.c

597

return true;

sys/dev/pci/drm/i915/display/intel_dmc.c

602

return true;

sys/dev/pci/drm/i915/display/intel_dmc.c

754

return true;

sys/dev/pci/drm/i915/display/intel_dmc.c

893

pipedmc_clock_gating_wa(display, true);

sys/dev/pci/drm/i915/display/intel_dmc.c

928

pipedmc_clock_gating_wa(display, true);

sys/dev/pci/drm/i915/display/intel_dmc.c

948

return true;

sys/dev/pci/drm/i915/display/intel_dmc.c

983

dmc->dmc_info[dmc_id].present = true;

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

225

wl->taken = true;

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

237

return true;

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

250

return true;

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

257

return true;

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

276

return true;

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

365

wl->enabled = true;

sys/dev/pci/drm/i915/display/intel_dp.c

1091

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

1334

8, sink_format, true);

sys/dev/pci/drm/i915/display/intel_dp.c

1343

8, sink_format, true);

sys/dev/pci/drm/i915/display/intel_dp.c

1408

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

1491

true);

sys/dev/pci/drm/i915/display/intel_dp.c

1642

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

1646

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

2010

0, true);

sys/dev/pci/drm/i915/display/intel_dp.c

2141

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

2149

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

2360

crtc_state->fec_enable = true;

sys/dev/pci/drm/i915/display/intel_dp.c

2405

true);

sys/dev/pci/drm/i915/display/intel_dp.c

2453

pipe_config->dsc.compression_enable = true;

sys/dev/pci/drm/i915/display/intel_dp.c

2523

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

2549

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

2705

dsc_needed = true;

sys/dev/pci/drm/i915/display/intel_dp.c

2721

true,

sys/dev/pci/drm/i915/display/intel_dp.c

2785

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

2897

as_sdp->target_rr_divider = true;

sys/dev/pci/drm/i915/display/intel_dp.c

3033

pipe_config->update_m_n = true;

sys/dev/pci/drm/i915/display/intel_dp.c

3045

pipe_config->has_drrs = true;

sys/dev/pci/drm/i915/display/intel_dp.c

3149

intel_dp->needs_modeset_retry = true;

sys/dev/pci/drm/i915/display/intel_dp.c

3292

ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);

sys/dev/pci/drm/i915/display/intel_dp.c

3326

pipe_config->splitter.enable = true;

sys/dev/pci/drm/i915/display/intel_dp.c

3533

bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0;

sys/dev/pci/drm/i915/display/intel_dp.c

3535

connector->dp.dsc_decompression_enabled = true;

sys/dev/pci/drm/i915/display/intel_dp.c

3578

intel_dp_sink_set_dsc_passthrough(connector, true);

sys/dev/pci/drm/i915/display/intel_dp.c

3579

intel_dp_sink_set_dsc_decompression(connector, true);

sys/dev/pci/drm/i915/display/intel_dp.c

3623

WRITE_ONCE(intel_dp->oui_valid, true);

sys/dev/pci/drm/i915/display/intel_dp.c

3734

dpcd_updated = true;

sys/dev/pci/drm/i915/display/intel_dp.c

3742

intel_dp->link.active = true;

sys/dev/pci/drm/i915/display/intel_dp.c

3751

bool fastset = true;

sys/dev/pci/drm/i915/display/intel_dp.c

3762

crtc_state->uapi.connectors_changed = true;

sys/dev/pci/drm/i915/display/intel_dp.c

3777

crtc_state->uapi.mode_changed = true;

sys/dev/pci/drm/i915/display/intel_dp.c

3785

crtc_state->uapi.mode_changed = true;

sys/dev/pci/drm/i915/display/intel_dp.c

3874

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

3940

intel_dp->frl.is_trained = true;

sys/dev/pci/drm/i915/display/intel_dp.c

3952

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

4135

ycbcr444_to_420 = true;

sys/dev/pci/drm/i915/display/intel_dp.c

4138

rgb_to_ycbcr = true;

sys/dev/pci/drm/i915/display/intel_dp.c

4139

ycbcr444_to_420 = true;

sys/dev/pci/drm/i915/display/intel_dp.c

4150

rgb_to_ycbcr = true;

sys/dev/pci/drm/i915/display/intel_dp.c

4408

intel_dp->use_rate_select = true;

sys/dev/pci/drm/i915/display/intel_dp.c

4470

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

4656

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

4672

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

4680

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

4898

as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;

sys/dev/pci/drm/i915/display/intel_dp.c

5130

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

5192

bool link_ok = true;

sys/dev/pci/drm/i915/display/intel_dp.c

5221

reprobe_needed = true;

sys/dev/pci/drm/i915/display/intel_dp.c

5285

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

5307

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

5327

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

5333

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

5525

reprobe_needed = true;

sys/dev/pci/drm/i915/display/intel_dp.c

5584

intel_dp->alpm_parameters.sink_alpm_error = true;

sys/dev/pci/drm/i915/display/intel_dp.c

5588

reprobe_needed = true;

sys/dev/pci/drm/i915/display/intel_dp.c

5776

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

5780

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

5784

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

5885

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

6152

connector->dp.dsc_decompression_enabled = true;

sys/dev/pci/drm/i915/display/intel_dp.c

6228

crtc_state->uapi.mode_changed = true;

sys/dev/pci/drm/i915/display/intel_dp.c

6261

crtc_state->uapi.mode_changed = true;

sys/dev/pci/drm/i915/display/intel_dp.c

6369

need_work = true;

sys/dev/pci/drm/i915/display/intel_dp.c

6436

intel_dp_dpcd_set_probe(intel_dp, true);

sys/dev/pci/drm/i915/display/intel_dp.c

6440

intel_dp->reset_link_params = true;

sys/dev/pci/drm/i915/display/intel_dp.c

6468

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

6491

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

6498

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

6575

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

6692

intel_panel_add_edid_fixed_modes(connector, true);

sys/dev/pci/drm/i915/display/intel_dp.c

6722

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

6748

intel_dp->reset_link_params = true;

sys/dev/pci/drm/i915/display/intel_dp.c

6792

connector->base.interlace_allowed = true;

sys/dev/pci/drm/i915/display/intel_dp.c

6832

return true;

sys/dev/pci/drm/i915/display/intel_dp.c

6883

ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst.mgr, true);

sys/dev/pci/drm/i915/display/intel_dp.c

813

return true;

sys/dev/pci/drm/i915/display/intel_dp_aux.c

319

trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

838

intel_dp_dpcd_set_probe(intel_dp, true);

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

171

return true;

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

613

panel->backlight.edp.vesa.luminance_control_support = true;

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

614

return true;

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

621

return true;

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

659

try_vesa_interface = true;

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

662

try_intel_interface = true;

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

670

try_intel_interface = true;

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

672

try_vesa_interface = true;

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

675

try_vesa_interface = true;

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

678

try_intel_interface = true;

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

684

try_vesa_interface = true;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

315

true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

318

DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

326

DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

378

*msg_ready = true;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

382

*msg_ready = true;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

386

*msg_ready = true;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

671

*capable = true;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1008

max_vswing_reached = true;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1070

channel_eq = true;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

113

return true;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1141

intel_dp->link.active = true;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1177

ret = true;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1202

return true;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1232

return true;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

129

return true;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1290

return true;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1314

intel_dp->use_max_params = true;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1347

return true;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1353

intel_dp->hobl_failed = true;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1361

return true;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1370

bool ret = true;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1469

timeout = true; /* try one last time after deadline */

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1494

timeout = true; /* try one last time after deadline */

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1521

return true;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1548

timeout = true; /* try one last time after deadline */

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1577

return true;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1601

passed = true;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1700

intel_dp->link.retrain_disabled = true;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

182

intel_dp_set_lttpr_transparent_mode(intel_dp, true);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

514

changed = true;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

689

return true;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

709

return true;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

886

return true;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

909

return true;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

977

return true;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1219

drm_dp_send_power_updown_phy(&intel_dp->mst.mgr, connector->mst.port, true);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

126

return true;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1329

intel_ddi_wait_for_fec_status(encoder, pipe_config, true);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1360

return true;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1715

return true;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

173

drm_dp_bw_channel_coding_efficiency(true)),

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1858

return true;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

2066

return true;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

2124

return true;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

2139

return true;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

354

true, dsc_slice_count, link_bpp_x16);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

516

bpp_step_x16, true);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

549

return true;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

564

return true;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

585

return true;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

596

return true;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

609

return true;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

682

dsc_needed = true;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

698

pipe_config, true,

sys/dev/pci/drm/i915/display/intel_dp_mst.c

979

crtc_state->uapi.mode_changed = true;

sys/dev/pci/drm/i915/display/intel_dp_test.c

170

intel_dp->compliance.test_active = true;

sys/dev/pci/drm/i915/display/intel_dp_test.c

215

intel_dp->compliance.test_active = true;

sys/dev/pci/drm/i915/display/intel_dp_test.c

348

intel_dp->compliance.test_active = true;

sys/dev/pci/drm/i915/display/intel_dp_test.c

520

return true;

sys/dev/pci/drm/i915/display/intel_dp_test.c

544

reprobe_needed = true;

sys/dev/pci/drm/i915/display/intel_dp_test.c

596

intel_dp->compliance.test_active = true;

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

284

intel_dp->tunnel_suspended = true;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

171

.dual_channel = true,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

380

return true;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

496

was_enabled = true;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

524

return true;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

556

ok = true;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

886

!chv_phy_powergate_ch(display, DPIO_PHY0, DPIO_CH1, true);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

888

chv_phy_powergate_lanes(encoder, true, lane_mask);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

893

__chv_data_lane_soft_reset(encoder, crtc_state, true);

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

100

return true;

sys/dev/pci/drm/i915/display/intel_dpll.c

2320

assert_pll(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_dpll.c

616

return true;

sys/dev/pci/drm/i915/display/intel_dpll.c

808

found = true;

sys/dev/pci/drm/i915/display/intel_dpll.c

851

return true;

sys/dev/pci/drm/i915/display/intel_dpll.c

905

found = true;

sys/dev/pci/drm/i915/display/intel_dpll.c

969

found = true;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1302

return true;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1317

.always_on = true, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1319

.always_on = true, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1321

.always_on = true, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

144

state->dpll_set = true;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1457

ret = true;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1491

ret = true;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2023

.always_on = true, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2243

ret = true;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

239

pll->on = true;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3609

ret = true;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3681

ret = true;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3742

ret = true;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4164

.is_alt_port_dpll = true, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4212

.is_alt_port_dpll = true, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4290

.is_alt_port_dpll = true, },

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

404

#define assert_dpll_enabled(d, p) assert_dpll(d, p, true)

sys/dev/pci/drm/i915/display/intel_dpt.c

143

for_i915_gem_ww(&ww, err, true) {

sys/dev/pci/drm/i915/display/intel_dpt.c

169

dpt->obj->mm.dirty = true;

sys/dev/pci/drm/i915/display/intel_dpt.c

209

i915_ggtt_resume_vm(fb->dpt_vm, true);

sys/dev/pci/drm/i915/display/intel_dpt.c

237

i915_ggtt_suspend_vm(fb->dpt_vm, true);

sys/dev/pci/drm/i915/display/intel_dpt.c

293

vm->is_dpt = true;

sys/dev/pci/drm/i915/display/intel_dpt.c

308

dpt->obj->is_dpt = true;

sys/dev/pci/drm/i915/display/intel_drrs.c

275

intel_drrs_frontbuffer_update(display, frontbuffer_bits, true);

sys/dev/pci/drm/i915/display/intel_drrs.c

73

return true;

sys/dev/pci/drm/i915/display/intel_dsb_buffer.c

71

return true;

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

872

return true;

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

926

want_panel_gpio = true;

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

931

want_panel_gpio = true;

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

932

want_backlight_gpio = true;

sys/dev/pci/drm/i915/display/intel_dvo.c

216

intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);

sys/dev/pci/drm/i915/display/intel_dvo.c

452

intel_gmbus_force_bit(i2c, true);

sys/dev/pci/drm/i915/display/intel_dvo.c

485

return true;

sys/dev/pci/drm/i915/display/intel_fb.c

101

.hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/i915/display/intel_fb.c

104

.hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/i915/display/intel_fb.c

107

.hsub = 2, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/i915/display/intel_fb.c

110

.hsub = 2, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/i915/display/intel_fb.c

113

.hsub = 2, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/i915/display/intel_fb.c

116

.hsub = 2, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/i915/display/intel_fb.c

119

.hsub = 1, .vsub = 1, .is_yuv = true },

sys/dev/pci/drm/i915/display/intel_fb.c

122

.hsub = 2, .vsub = 2, .is_yuv = true },

sys/dev/pci/drm/i915/display/intel_fb.c

125

.hsub = 2, .vsub = 2, .is_yuv = true },

sys/dev/pci/drm/i915/display/intel_fb.c

1279

return true;

sys/dev/pci/drm/i915/display/intel_fb.c

128

.hsub = 2, .vsub = 2, .is_yuv = true },

sys/dev/pci/drm/i915/display/intel_fb.c

131

.hsub = 2, .vsub = 2, .is_yuv = true },

sys/dev/pci/drm/i915/display/intel_fb.c

147

.hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/i915/display/intel_fb.c

150

.hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/i915/display/intel_fb.c

159

.hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/i915/display/intel_fb.c

162

.hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/i915/display/intel_fb.c

171

.hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/i915/display/intel_fb.c

174

.hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/i915/display/intel_fb.c

186

.hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/i915/display/intel_fb.c

189

.hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/i915/display/intel_fb.c

198

.hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/i915/display/intel_fb.c

201

.hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/i915/display/intel_fb.c

210

.hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/i915/display/intel_fb.c

213

.hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/i915/display/intel_fb.c

48

.cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },

sys/dev/pci/drm/i915/display/intel_fb.c

50

.cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },

sys/dev/pci/drm/i915/display/intel_fb.c

56

.cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },

sys/dev/pci/drm/i915/display/intel_fb.c

574

return true;

sys/dev/pci/drm/i915/display/intel_fb.c

58

.cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },

sys/dev/pci/drm/i915/display/intel_fb.c

626

return true;

sys/dev/pci/drm/i915/display/intel_fb.c

77

.hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/i915/display/intel_fb.c

80

.hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/i915/display/intel_fb.c

89

.hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/i915/display/intel_fb.c

92

.hsub = 1, .vsub = 1, .has_alpha = true },

sys/dev/pci/drm/i915/display/intel_fb_pin.c

158

i915_gem_ww_ctx_init(&ww, true);

sys/dev/pci/drm/i915/display/intel_fb_pin.c

51

for_i915_gem_ww(&ww, ret, true) {

sys/dev/pci/drm/i915/display/intel_fbc.c

1007

return true;

sys/dev/pci/drm/i915/display/intel_fbc.c

1012

return true;

sys/dev/pci/drm/i915/display/intel_fbc.c

1039

return true;

sys/dev/pci/drm/i915/display/intel_fbc.c

1045

return true;

sys/dev/pci/drm/i915/display/intel_fbc.c

1059

return true;

sys/dev/pci/drm/i915/display/intel_fbc.c

1064

return true;

sys/dev/pci/drm/i915/display/intel_fbc.c

1080

return true;

sys/dev/pci/drm/i915/display/intel_fbc.c

1105

return true;

sys/dev/pci/drm/i915/display/intel_fbc.c

1117

return true;

sys/dev/pci/drm/i915/display/intel_fbc.c

1214

return true;

sys/dev/pci/drm/i915/display/intel_fbc.c

1625

return true;

sys/dev/pci/drm/i915/display/intel_fbc.c

1638

fbc->flip_pending = true;

sys/dev/pci/drm/i915/display/intel_fbc.c

1659

need_vblank_wait = true;

sys/dev/pci/drm/i915/display/intel_fbc.c

1964

fbc->underrun_detected = true;

sys/dev/pci/drm/i915/display/intel_fbc.c

727

fbc->active = true;

sys/dev/pci/drm/i915/display/intel_fbc.c

728

fbc->activated = true;

sys/dev/pci/drm/i915/display/intel_fbc.c

943

fbc_compressor_clkgate_disable_wa(fbc, true);

sys/dev/pci/drm/i915/display/intel_fbc.c

994

return true;

sys/dev/pci/drm/i915/display/intel_fbdev.c

288

prealloc = true;

sys/dev/pci/drm/i915/display/intel_fbdev.c

531

return true;

sys/dev/pci/drm/i915/display/intel_fdi.c

113

assert_fdi_rx_pll(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_fdi.c

426

cpt_set_fdi_bc_bifurcation(display, true);

sys/dev/pci/drm/i915/display/intel_fdi.c

430

cpt_set_fdi_bc_bifurcation(display, true);

sys/dev/pci/drm/i915/display/intel_fdi.c

54

assert_fdi_tx(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_fdi.c

75

assert_fdi_rx(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

74

return true;

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

91

return true;

sys/dev/pci/drm/i915/display/intel_flipq.c

122

return true;

sys/dev/pci/drm/i915/display/intel_flipq.c

318

intel_flipq_preempt(crtc, true);

sys/dev/pci/drm/i915/display/intel_flipq.c

435

intel_flipq_preempt(crtc, true);

sys/dev/pci/drm/i915/display/intel_frontbuffer.h

111

return true;

sys/dev/pci/drm/i915/display/intel_global_state.c

154

return true;

sys/dev/pci/drm/i915/display/intel_global_state.c

322

obj_state->changed = true;

sys/dev/pci/drm/i915/display/intel_global_state.c

335

obj_state->serialized = true;

sys/dev/pci/drm/i915/display/intel_global_state.c

349

return true;

sys/dev/pci/drm/i915/display/intel_gmbus.c

350

ptl_handle_mask_bits(bus, true);

sys/dev/pci/drm/i915/display/intel_gmbus.c

368

pnv_gmbus_clock_gating(display, true);

sys/dev/pci/drm/i915/display/intel_gmbus.c

588

extra_byte_added = true;

sys/dev/pci/drm/i915/display/intel_gmbus.c

891

bxt_gmbus_clock_gating(display, true);

sys/dev/pci/drm/i915/display/intel_gmbus.c

893

pch_gmbus_clock_gating(display, true);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1064

intel_hdcp_adjust_hdcp_line_rekeying(connector->encoder, hdcp, true);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1070

hdcp->hdcp_encrypted = true;

sys/dev/pci/drm/i915/display/intel_hdcp.c

1150

true);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1157

DRM_MODE_CONTENT_PROTECTION_ENABLED, true);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1171

true);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1180

true);

sys/dev/pci/drm/i915/display/intel_hdcp.c

129

enforce_type0 = true;

sys/dev/pci/drm/i915/display/intel_hdcp.c

1636

hdcp->is_paired = true;

sys/dev/pci/drm/i915/display/intel_hdcp.c

1892

ret = hdcp->shim->stream_2_2_encryption(connector, true);

sys/dev/pci/drm/i915/display/intel_hdcp.c

1928

true);

sys/dev/pci/drm/i915/display/intel_hdcp.c

194

return true;

sys/dev/pci/drm/i915/display/intel_hdcp.c

1948

dig_port->hdcp.auth_status = true;

sys/dev/pci/drm/i915/display/intel_hdcp.c

2105

hdcp->hdcp2_encrypted = true;

sys/dev/pci/drm/i915/display/intel_hdcp.c

2174

_intel_hdcp2_disable(connector, true);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2177

true);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2186

true);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2202

true);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2216

ret = _intel_hdcp2_disable(connector, true);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2222

DRM_MODE_CONTENT_PROTECTION_DESIRED, true);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2227

DRM_MODE_CONTENT_PROTECTION_DESIRED, true);

sys/dev/pci/drm/i915/display/intel_hdcp.c

2352

return true;

sys/dev/pci/drm/i915/display/intel_hdcp.c

2374

display->hdcp.comp_added = true;

sys/dev/pci/drm/i915/display/intel_hdcp.c

240

capable = true;

sys/dev/pci/drm/i915/display/intel_hdcp.c

2407

hdcp->hdcp2_supported = true;

sys/dev/pci/drm/i915/display/intel_hdcp.c

2506

true);

sys/dev/pci/drm/i915/display/intel_hdcp.c

273

return true;

sys/dev/pci/drm/i915/display/intel_hdcp.c

2735

crtc_state->mode_changed = true;

sys/dev/pci/drm/i915/display/intel_hdcp.c

2788

__intel_hdcp_info(m, connector, true);

sys/dev/pci/drm/i915/display/intel_hdcp.c

899

ret = shim->toggle_signalling(dig_port, cpu_transcoder, true);

sys/dev/pci/drm/i915/display/intel_hdcp.c

966

ret = shim->stream_encryption(connector, true);

sys/dev/pci/drm/i915/display/intel_hdcp_gsc.c

34

return true;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc.c

55

cmd_in = i915_gem_object_pin_map_unlocked(obj, intel_gt_coherent_map_type(gt, obj, true));

sys/dev/pci/drm/i915/display/intel_hdmi.c

1002

return true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

1524

true, TRANS_DDI_HDCP_SIGNALLING);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1595

return true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

1606

return true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

1788

*capable = true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

1934

return true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

1967

return true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

2000

status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2095

return true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

2344

pipe_config->has_infoframe = true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

2360

ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2387

pipe_config->hdmi_scrambling = true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

2390

pipe_config->hdmi_scrambling = true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

2391

pipe_config->hdmi_high_tmds_clock_ratio = true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

2431

intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2518

intel_gmbus_force_bit(ddc, true);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2531

connected = true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

2712

return true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

3081

connector->interlace_allowed = true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

3083

connector->stereo_allowed = true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

3086

connector->ycbcr_420_allowed = true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

3117

return true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

3342

bpp_found = true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

724

return true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

766

return true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

779

return true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

798

return true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

813

return true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

828

return true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

841

return true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

844

return true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

847

return true;

sys/dev/pci/drm/i915/display/intel_hdmi.c

863

return true;

sys/dev/pci/drm/i915/display/intel_hotplug.c

1003

queue_hp_work = true;

sys/dev/pci/drm/i915/display/intel_hotplug.c

1008

queue_hp_work = true;

sys/dev/pci/drm/i915/display/intel_hotplug.c

1043

return true;

sys/dev/pci/drm/i915/display/intel_hotplug.c

1086

do_flush = true;

sys/dev/pci/drm/i915/display/intel_hotplug.c

1150

display->hotplug.detection_work_enabled = true;

sys/dev/pci/drm/i915/display/intel_hotplug.c

176

storm = true;

sys/dev/pci/drm/i915/display/intel_hotplug.c

256

hpd_disabled = true;

sys/dev/pci/drm/i915/display/intel_hotplug.c

327

ret = true;

sys/dev/pci/drm/i915/display/intel_hotplug.c

364

return true;

sys/dev/pci/drm/i915/display/intel_hotplug.c

626

queue_dig = true;

sys/dev/pci/drm/i915/display/intel_hotplug.c

669

long_hpd = true;

sys/dev/pci/drm/i915/display/intel_hotplug.c

672

queue_hp = true;

sys/dev/pci/drm/i915/display/intel_hotplug.c

677

storm_detected = true;

sys/dev/pci/drm/i915/display/intel_hotplug.c

678

queue_hp = true;

sys/dev/pci/drm/i915/display/intel_hotplug.c

870

WRITE_ONCE(display->hotplug.poll_enabled, true);

sys/dev/pci/drm/i915/display/intel_hotplug.c

911

intel_dp_dpcd_set_probe(enc_to_intel_dp(encoder), true);

sys/dev/pci/drm/i915/display/intel_hotplug.c

959

was_pending = true;

sys/dev/pci/drm/i915/display/intel_hotplug.c

961

was_pending = true;

sys/dev/pci/drm/i915/display/intel_hotplug.c

963

was_pending = true;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

1111

_xelpdp_pica_hpd_detection_setup(display, encoder->hpd_pin, true);

sys/dev/pci/drm/i915/display/intel_link_bw.c

162

ret = __intel_link_bw_reduce_bpp(state, limits, pipe_mask, reason, true);

sys/dev/pci/drm/i915/display/intel_link_bw.c

192

return true;

sys/dev/pci/drm/i915/display/intel_link_bw.c

236

return true;

sys/dev/pci/drm/i915/display/intel_link_bw.c

283

bpps_changed = true;

sys/dev/pci/drm/i915/display/intel_link_bw.c

293

return true;

sys/dev/pci/drm/i915/display/intel_load_detect.c

129

to_intel_atomic_state(state)->internal = true;

sys/dev/pci/drm/i915/display/intel_load_detect.c

132

to_intel_atomic_state(restore_state)->internal = true;

sys/dev/pci/drm/i915/display/intel_load_detect.c

150

crtc_state->uapi.active = true;

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

212

lpe_present = true;

sys/dev/pci/drm/i915/display/intel_lspcon.c

121

return true;

sys/dev/pci/drm/i915/display/intel_lspcon.c

148

lspcon->hdr_supported = true;

sys/dev/pci/drm/i915/display/intel_lspcon.c

258

return true;

sys/dev/pci/drm/i915/display/intel_lspcon.c

304

return true;

sys/dev/pci/drm/i915/display/intel_lspcon.c

349

return true;

sys/dev/pci/drm/i915/display/intel_lspcon.c

400

return true;

sys/dev/pci/drm/i915/display/intel_lspcon.c

432

return true;

sys/dev/pci/drm/i915/display/intel_lspcon.c

490

return true;

sys/dev/pci/drm/i915/display/intel_lspcon.c

501

bool ret = true;

sys/dev/pci/drm/i915/display/intel_lspcon.c

704

connector->ycbcr_420_allowed = true;

sys/dev/pci/drm/i915/display/intel_lspcon.c

705

lspcon->active = true;

sys/dev/pci/drm/i915/display/intel_lspcon.c

707

return true;

sys/dev/pci/drm/i915/display/intel_lvds.c

436

crtc_state->has_pch_encoder = true;

sys/dev/pci/drm/i915/display/intel_lvds.c

809

return true;

sys/dev/pci/drm/i915/display/intel_lvds.c

812

return true;

sys/dev/pci/drm/i915/display/intel_lvds.c

977

intel_panel_add_edid_fixed_modes(connector, true);

sys/dev/pci/drm/i915/display/intel_modeset_lock.c

27

return true;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

404

return true;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

418

return true;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

515

return true;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

71

to_intel_atomic_state(state)->internal = true;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

753

true);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

829

crtc_state->inherited = true;

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

131

found = true;

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

136

found = true;

sys/dev/pci/drm/i915/display/intel_modeset_verify.c

137

enabled = true;

sys/dev/pci/drm/i915/display/intel_opregion.c

1179

return true;

sys/dev/pci/drm/i915/display/intel_opregion.c

828

requested_callbacks = true;

sys/dev/pci/drm/i915/display/intel_overlay.c

1183

overlay->pfit_active = true;

sys/dev/pci/drm/i915/display/intel_overlay.c

1252

return true;

sys/dev/pci/drm/i915/display/intel_overlay.c

1264

return true;

sys/dev/pci/drm/i915/display/intel_overlay.c

1422

overlay->color_key_enabled = true;

sys/dev/pci/drm/i915/display/intel_overlay.c

275

overlay->active = true;

sys/dev/pci/drm/i915/display/intel_overlay.c

391

i830_overlay_clock_gating(display, true);

sys/dev/pci/drm/i915/display/intel_overlay.c

660

scale_changed = true;

sys/dev/pci/drm/i915/display/intel_overlay.c

777

i915_gem_ww_ctx_init(&ww, true);

sys/dev/pci/drm/i915/display/intel_panel.c

188

return true;

sys/dev/pci/drm/i915/display/intel_panel.c

68

return true;

sys/dev/pci/drm/i915/display/intel_pch_display.c

509

crtc_state->has_pch_encoder = true;

sys/dev/pci/drm/i915/display/intel_pch_display.c

628

crtc_state->has_pch_encoder = true;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

287

with_spread = true;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

415

return true;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

419

return true;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

433

return true;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

438

return true;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

451

has_fdi = true;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

495

lpt_enable_clkout_dp(display, true, true);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

518

has_panel = true;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

519

has_lvds = true;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

522

has_panel = true;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

524

has_cpu_edp = true;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

536

can_ssc = true;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

550

using_ssc_source = true;

sys/dev/pci/drm/i915/display/intel_pfit.c

254

crtc_state->pch_pfit.enabled = true;

sys/dev/pci/drm/i915/display/intel_pfit.c

635

crtc_state->pch_pfit.enabled = true;

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

144

need_stable_symbols = true;

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

148

need_stable_symbols = true;

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

154

need_stable_symbols = true;

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

302

to_intel_atomic_state(state)->internal = true;

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

317

pipe_config->uapi.mode_changed = true;

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

610

intel_crtc_crc_setup_workarounds(crtc, true);

sys/dev/pci/drm/i915/display/intel_plane.c

1244

intel_display_rps_mark_interactive(display, state, true);

sys/dev/pci/drm/i915/display/intel_plane.c

1477

y_plane_state->is_y_plane = true;

sys/dev/pci/drm/i915/display/intel_plane.c

350

*need_cdclk_calc = true;

sys/dev/pci/drm/i915/display/intel_plane.c

506

return true;

sys/dev/pci/drm/i915/display/intel_plane.c

561

return true;

sys/dev/pci/drm/i915/display/intel_plane.c

641

new_crtc_state->disable_cxsr = true;

sys/dev/pci/drm/i915/display/intel_plane.c

645

new_crtc_state->disable_cxsr = true;

sys/dev/pci/drm/i915/display/intel_plane.c

648

new_crtc_state->do_async_flip = true;

sys/dev/pci/drm/i915/display/intel_plane.c

874

intel_plane_async_flip(dsb, plane, crtc_state, plane_state, true);

sys/dev/pci/drm/i915/display/intel_plane_initial.c

121

return true;

sys/dev/pci/drm/i915/display/intel_plane_initial.c

299

return true;

sys/dev/pci/drm/i915/display/intel_plane_initial.c

376

dev_priv->preserve_bios_swizzle = true;

sys/dev/pci/drm/i915/display/intel_plane_initial.c

49

return true;

sys/dev/pci/drm/i915/display/intel_pmdemand.c

249

new_conn_state, true,

sys/dev/pci/drm/i915/display/intel_pmdemand.c

289

return true;

sys/dev/pci/drm/i915/display/intel_pmdemand.c

302

return true;

sys/dev/pci/drm/i915/display/intel_pmdemand.c

305

return true;

sys/dev/pci/drm/i915/display/intel_pmdemand.c

308

return true;

sys/dev/pci/drm/i915/display/intel_pmdemand.c

313

return true;

sys/dev/pci/drm/i915/display/intel_pmdemand.c

598

changed = true;

sys/dev/pci/drm/i915/display/intel_pmdemand.c

604

changed = true;

sys/dev/pci/drm/i915/display/intel_pps.c

1322

pps_init_registers(intel_dp, true);

sys/dev/pci/drm/i915/display/intel_pps.c

138

!chv_phy_powergate_ch(display, phy, ch, true);

sys/dev/pci/drm/i915/display/intel_pps.c

1721

intel_dp->pps.initializing = true;

sys/dev/pci/drm/i915/display/intel_pps.c

1845

bool locked = true;

sys/dev/pci/drm/i915/display/intel_pps.c

243

pps_init_registers(intel_dp, true);

sys/dev/pci/drm/i915/display/intel_pps.c

293

return true;

sys/dev/pci/drm/i915/display/intel_pps.c

384

return true;

sys/dev/pci/drm/i915/display/intel_pps.c

411

return true;

sys/dev/pci/drm/i915/display/intel_pps.c

487

intel_dp->pps.bxt_pps_reset = true;

sys/dev/pci/drm/i915/display/intel_pps.c

632

10 * 1000, 5000 * 1000, true);

sys/dev/pci/drm/i915/display/intel_pps.c

759

intel_dp->pps.want_panel_vdd = true;

sys/dev/pci/drm/i915/display/intel_psr.c

1265

return crtc_state->enable_psr2_sel_fetch = true;

sys/dev/pci/drm/i915/display/intel_psr.c

1308

return true;

sys/dev/pci/drm/i915/display/intel_psr.c

1325

return true;

sys/dev/pci/drm/i915/display/intel_psr.c

1331

crtc_state->req_psr2_sdp_prior_scanline = true;

sys/dev/pci/drm/i915/display/intel_psr.c

1332

return true;

sys/dev/pci/drm/i915/display/intel_psr.c

1391

return true;

sys/dev/pci/drm/i915/display/intel_psr.c

1412

return true;

sys/dev/pci/drm/i915/display/intel_psr.c

1512

return true;

sys/dev/pci/drm/i915/display/intel_psr.c

1562

return true;

sys/dev/pci/drm/i915/display/intel_psr.c

1595

return true;

sys/dev/pci/drm/i915/display/intel_psr.c

1623

return true;

sys/dev/pci/drm/i915/display/intel_psr.c

1649

if (!alpm_config_valid(intel_dp, crtc_state, true))

sys/dev/pci/drm/i915/display/intel_psr.c

1652

return true;

sys/dev/pci/drm/i915/display/intel_psr.c

1706

crtc_state->has_psr = crtc_state->has_panel_replay ? true :

sys/dev/pci/drm/i915/display/intel_psr.c

1761

pipe_config->has_psr = pipe_config->has_panel_replay = true;

sys/dev/pci/drm/i915/display/intel_psr.c

1767

pipe_config->has_psr = true;

sys/dev/pci/drm/i915/display/intel_psr.c

1780

pipe_config->enable_psr2_sel_fetch = true;

sys/dev/pci/drm/i915/display/intel_psr.c

1820

intel_dp->psr.active = true;

sys/dev/pci/drm/i915/display/intel_psr.c

1836

activate = true;

sys/dev/pci/drm/i915/display/intel_psr.c

1842

activate = true;

sys/dev/pci/drm/i915/display/intel_psr.c

1970

intel_dmc_block_pkgc(display, intel_dp->psr.pipe, true);

sys/dev/pci/drm/i915/display/intel_psr.c

1995

intel_dp->psr.sink_not_reliable = true;

sys/dev/pci/drm/i915/display/intel_psr.c

2002

return true;

sys/dev/pci/drm/i915/display/intel_psr.c

2057

intel_snps_phy_update_psr_power_state(&dig_port->base, true);

sys/dev/pci/drm/i915/display/intel_psr.c

2060

intel_dp->psr.enabled = true;

sys/dev/pci/drm/i915/display/intel_psr.c

2070

intel_dp->psr.link_ok = true;

sys/dev/pci/drm/i915/display/intel_psr.c

2336

return true;

sys/dev/pci/drm/i915/display/intel_psr.c

2341

return true;

sys/dev/pci/drm/i915/display/intel_psr.c

243

connector->panel.vbt.psr.enable : true;

sys/dev/pci/drm/i915/display/intel_psr.c

247

return true;

sys/dev/pci/drm/i915/display/intel_psr.c

258

return true;

sys/dev/pci/drm/i915/display/intel_psr.c

2586

su_area_changed = true;

sys/dev/pci/drm/i915/display/intel_psr.c

2592

su_area_changed = true;

sys/dev/pci/drm/i915/display/intel_psr.c

2633

*cursor_in_su_area = true;

sys/dev/pci/drm/i915/display/intel_psr.c

2654

return true;

sys/dev/pci/drm/i915/display/intel_psr.c

2669

return true;

sys/dev/pci/drm/i915/display/intel_psr.c

2735

full_update = true;

sys/dev/pci/drm/i915/display/intel_psr.c

2763

full_update = true;

sys/dev/pci/drm/i915/display/intel_psr.c

2823

full_update = true;

sys/dev/pci/drm/i915/display/intel_psr.c

2891

full_update = true;

sys/dev/pci/drm/i915/display/intel_psr.c

3069

return true;

sys/dev/pci/drm/i915/display/intel_psr.c

3089

return true;

sys/dev/pci/drm/i915/display/intel_psr.c

3195

to_intel_atomic_state(state)->internal = true;

sys/dev/pci/drm/i915/display/intel_psr.c

3222

crtc_state->mode_changed = true;

sys/dev/pci/drm/i915/display/intel_psr.c

3291

psr->sink_not_reliable = true;

sys/dev/pci/drm/i915/display/intel_psr.c

3362

intel_dp->psr.psr2_sel_fetch_cff_enabled = true;

sys/dev/pci/drm/i915/display/intel_psr.c

3573

intel_dp->psr.source_panel_replay_support = true;

sys/dev/pci/drm/i915/display/intel_psr.c

3576

intel_dp->psr.source_support = true;

sys/dev/pci/drm/i915/display/intel_psr.c

3623

psr->sink_not_reliable = true;

sys/dev/pci/drm/i915/display/intel_psr.c

3642

psr->sink_not_reliable = true;

sys/dev/pci/drm/i915/display/intel_psr.c

3686

psr->sink_not_reliable = true;

sys/dev/pci/drm/i915/display/intel_psr.c

464

intel_dp->psr.irq_aux_error = true;

sys/dev/pci/drm/i915/display/intel_psr.c

617

intel_dp->psr.sink_panel_replay_support = true;

sys/dev/pci/drm/i915/display/intel_psr.c

621

intel_dp->psr.sink_panel_replay_su_support = true;

sys/dev/pci/drm/i915/display/intel_psr.c

657

intel_dp->psr.sink_support = true;

sys/dev/pci/drm/i915/display/intel_psr.c

945

true);

sys/dev/pci/drm/i915/display/intel_sbi.c

71

intel_sbi_rw(display, reg, destination, &result, true);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1109

return true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1131

return true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1144

return true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1248

return true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1279

return true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1310

pipe_config->clock_set = true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1369

pipe_config->has_pch_encoder = true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1396

pipe_config->sdvo_tv_clock = true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1782

pipe_config->limited_color_range = true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1788

pipe_config->has_audio = true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1794

pipe_config->has_hdmi_sink = true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1875

intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1876

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2015

return true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

2447

crtc_state->connectors_changed = true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

2533

crtc_state->connectors_changed = true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

2667

intel_gmbus_force_bit(sdvo->i2c, true);

sys/dev/pci/drm/i915/display/intel_sdvo.c

273

return true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

2749

connector->base.base.interlace_allowed = true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

2834

intel_sdvo_connector->is_hdmi = true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

2845

return true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

2881

return true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

2917

return true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

2972

return true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

3050

return true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

3108

return true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

3239

return true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

3253

return true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

3274

return true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

3282

return true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

3513

return true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

470

int i, ret = true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

536

return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true);

sys/dev/pci/drm/i915/display/intel_sdvo.c

612

return true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

681

return true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

739

return true;

sys/dev/pci/drm/i915/display/intel_sdvo.c

974

return true;

sys/dev/pci/drm/i915/display/intel_sprite.c

1268

return true;

sys/dev/pci/drm/i915/display/intel_sprite.c

1358

min_scale, max_scale, true);

sys/dev/pci/drm/i915/display/intel_sprite.c

1415

true);

sys/dev/pci/drm/i915/display/intel_sprite.c

1502

return true;

sys/dev/pci/drm/i915/display/intel_sprite.c

1528

return true;

sys/dev/pci/drm/i915/display/intel_sprite.c

1558

return true;

sys/dev/pci/drm/i915/display/intel_sprite_uapi.c

89

to_intel_atomic_state(state)->internal = true;

sys/dev/pci/drm/i915/display/intel_tc.c

1069

return true;

sys/dev/pci/drm/i915/display/intel_tc.c

1132

return true;

sys/dev/pci/drm/i915/display/intel_tc.c

1210

return true;

sys/dev/pci/drm/i915/display/intel_tc.c

1213

if (!xelpdp_tc_phy_enable_tcss_power(tc, true))

sys/dev/pci/drm/i915/display/intel_tc.c

1216

xelpdp_tc_phy_take_ownership(tc, true);

sys/dev/pci/drm/i915/display/intel_tc.c

1223

return true;

sys/dev/pci/drm/i915/display/intel_tc.c

1355

return true;

sys/dev/pci/drm/i915/display/intel_tc.c

1617

update_mode = true;

sys/dev/pci/drm/i915/display/intel_tc.c

1623

update_mode = true;

sys/dev/pci/drm/i915/display/intel_tc.c

1783

crtc_state->uapi.connectors_changed = true;

sys/dev/pci/drm/i915/display/intel_tc.c

1805

state->internal = true;

sys/dev/pci/drm/i915/display/intel_tc.c

1845

return true;

sys/dev/pci/drm/i915/display/intel_tc.c

1893

intel_tc_port_update_mode(tc, 1, true);

sys/dev/pci/drm/i915/display/intel_tc.c

607

return true;

sys/dev/pci/drm/i915/display/intel_tc.c

666

return true;

sys/dev/pci/drm/i915/display/intel_tc.c

689

return true;

sys/dev/pci/drm/i915/display/intel_tc.c

702

return true;

sys/dev/pci/drm/i915/display/intel_tc.c

706

!icl_tc_phy_take_ownership(tc, true)) &&

sys/dev/pci/drm/i915/display/intel_tc.c

719

return true;

sys/dev/pci/drm/i915/display/intel_tc.c

880

return true;

sys/dev/pci/drm/i915/display/intel_tc.c

926

return true;

sys/dev/pci/drm/i915/display/intel_tc.c

931

if (!adlp_tc_phy_take_ownership(tc, true) &&

sys/dev/pci/drm/i915/display/intel_tc.c

954

return true;

sys/dev/pci/drm/i915/display/intel_tc.c

993

tc_phy_load_fia_params(tc, true);

sys/dev/pci/drm/i915/display/intel_tv.c

1225

pipe_config->clock_set = true;

sys/dev/pci/drm/i915/display/intel_tv.c

1257

tv_conn_state->bypass_vfilter = true;

sys/dev/pci/drm/i915/display/intel_tv.c

1870

new_crtc_state->connectors_changed = true;

sys/dev/pci/drm/i915/display/intel_tv.c

404

.veq_ena = true, .veq_start_f1 = 0,

sys/dev/pci/drm/i915/display/intel_tv.c

410

.burst_ena = true,

sys/dev/pci/drm/i915/display/intel_tv.c

446

.veq_ena = true, .veq_start_f1 = 0,

sys/dev/pci/drm/i915/display/intel_tv.c

452

.burst_ena = true,

sys/dev/pci/drm/i915/display/intel_tv.c

489

.veq_ena = true, .veq_start_f1 = 0,

sys/dev/pci/drm/i915/display/intel_tv.c

495

.burst_ena = true,

sys/dev/pci/drm/i915/display/intel_tv.c

532

.veq_ena = true, .veq_start_f1 = 0,

sys/dev/pci/drm/i915/display/intel_tv.c

538

.burst_ena = true,

sys/dev/pci/drm/i915/display/intel_tv.c

550

.pal_burst = true,

sys/dev/pci/drm/i915/display/intel_tv.c

576

.veq_ena = true, .veq_start_f1 = 0,

sys/dev/pci/drm/i915/display/intel_tv.c

582

.burst_ena = true,

sys/dev/pci/drm/i915/display/intel_tv.c

595

.pal_burst = true,

sys/dev/pci/drm/i915/display/intel_tv.c

620

.veq_ena = true, .veq_start_f1 = 0,

sys/dev/pci/drm/i915/display/intel_tv.c

626

.burst_ena = true,

sys/dev/pci/drm/i915/display/intel_tv.c

638

.pal_burst = true,

sys/dev/pci/drm/i915/display/intel_tv.c

652

.component_only = true,

sys/dev/pci/drm/i915/display/intel_tv.c

657

.progressive = true, .trilevel_sync = false,

sys/dev/pci/drm/i915/display/intel_tv.c

676

.component_only = true,

sys/dev/pci/drm/i915/display/intel_tv.c

681

.progressive = true, .trilevel_sync = false,

sys/dev/pci/drm/i915/display/intel_tv.c

700

.component_only = true,

sys/dev/pci/drm/i915/display/intel_tv.c

705

.progressive = true, .trilevel_sync = true,

sys/dev/pci/drm/i915/display/intel_tv.c

724

.component_only = true,

sys/dev/pci/drm/i915/display/intel_tv.c

729

.progressive = true, .trilevel_sync = true,

sys/dev/pci/drm/i915/display/intel_tv.c

748

.component_only = true,

sys/dev/pci/drm/i915/display/intel_tv.c

753

.progressive = false, .trilevel_sync = true,

sys/dev/pci/drm/i915/display/intel_tv.c

758

.veq_ena = true, .veq_start_f1 = 4,

sys/dev/pci/drm/i915/display/intel_tv.c

774

.component_only = true,

sys/dev/pci/drm/i915/display/intel_tv.c

779

.progressive = false, .trilevel_sync = true,

sys/dev/pci/drm/i915/display/intel_tv.c

784

.veq_ena = true, .veq_start_f1 = 4,

sys/dev/pci/drm/i915/display/intel_tv.c

801

.component_only = true,

sys/dev/pci/drm/i915/display/intel_tv.c

806

.progressive = true, .trilevel_sync = true,

sys/dev/pci/drm/i915/display/intel_tv.c

827

.component_only = true,

sys/dev/pci/drm/i915/display/intel_tv.c

832

.progressive = true, .trilevel_sync = true,

sys/dev/pci/drm/i915/display/intel_tv.c

853

.component_only = true,

sys/dev/pci/drm/i915/display/intel_tv.c

858

.progressive = true, .trilevel_sync = true,

sys/dev/pci/drm/i915/display/intel_vblank.c

453

return true;

sys/dev/pci/drm/i915/display/intel_vblank.c

518

wait_for_pipe_scanline_moving(crtc, true);

sys/dev/pci/drm/i915/display/intel_vdsc.c

300

vdsc_cfg->native_420 = true;

sys/dev/pci/drm/i915/display/intel_vdsc.c

35

return true;

sys/dev/pci/drm/i915/display/intel_vdsc.c

43

return true;

sys/dev/pci/drm/i915/display/intel_vdsc.c

53

return true;

sys/dev/pci/drm/i915/display/intel_vdsc.c

729

mipi_dsi_compression_mode(dsi, true);

sys/dev/pci/drm/i915/display/intel_vdsc.c

874

*all_equal = true;

sys/dev/pci/drm/i915/display/intel_vga.c

39

return true;

sys/dev/pci/drm/i915/display/intel_vrr.c

190

if (!HAS_CMRR(display) || true)

sys/dev/pci/drm/i915/display/intel_vrr.c

203

return true;

sys/dev/pci/drm/i915/display/intel_vrr.c

233

crtc_state->cmrr.enable = true;

sys/dev/pci/drm/i915/display/intel_vrr.c

249

crtc_state->vrr.enable = true;

sys/dev/pci/drm/i915/display/intel_vrr.c

381

crtc_state->update_lrr = true;

sys/dev/pci/drm/i915/display/intel_vrr.c

589

return true;

sys/dev/pci/drm/i915/display/intel_vrr.c

78

new_crtc_state->uapi.mode_changed = true;

sys/dev/pci/drm/i915/display/intel_wm.c

73

return true;

sys/dev/pci/drm/i915/display/intel_wm_types.h

71

return true;

sys/dev/pci/drm/i915/display/skl_scaler.c

177

need_scaler = true;

sys/dev/pci/drm/i915/display/skl_scaler.c

309

need_scaler = true;

sys/dev/pci/drm/i915/display/skl_scaler.c

332

scaler_state->scalers[i].in_use = true;

sys/dev/pci/drm/i915/display/skl_scaler.c

431

scaler_state->scalers[0].in_use = true;

sys/dev/pci/drm/i915/display/skl_scaler.c

460

drm_rect_debug_print("src: ", src, true);

sys/dev/pci/drm/i915/display/skl_scaler.c

497

drm_rect_debug_print("src: ", &src, true);

sys/dev/pci/drm/i915/display/skl_scaler.c

836

uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true);

sys/dev/pci/drm/i915/display/skl_scaler.c

924

crtc_state->pch_pfit.enabled = true;

sys/dev/pci/drm/i915/display/skl_scaler.c

935

scaler_state->scalers[i].in_use = true;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1701

return true;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1951

return true;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2246

return true;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2323

min_scale, max_scale, true);

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2448

return true;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2507

return true;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2525

return true;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2540

return true;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2565

return true;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2579

return true;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2594

return true;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2623

return true;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2635

return true;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2646

return true;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3200

return true;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

527

return true;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

555

return true;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

569

return true;

sys/dev/pci/drm/i915/display/skl_watermark.c

1043

.join_mbus = true,

sys/dev/pci/drm/i915/display/skl_watermark.c

1050

.join_mbus = true,

sys/dev/pci/drm/i915/display/skl_watermark.c

1777

return true;

sys/dev/pci/drm/i915/display/skl_watermark.c

1929

result->enable = true;

sys/dev/pci/drm/i915/display/skl_watermark.c

2036

trans_wm->enable = true;

sys/dev/pci/drm/i915/display/skl_watermark.c

2076

wm->is_planar = true;

sys/dev/pci/drm/i915/display/skl_watermark.c

2450

return true;

sys/dev/pci/drm/i915/display/skl_watermark.c

313

return true;

sys/dev/pci/drm/i915/display/skl_watermark.c

3164

return true;

sys/dev/pci/drm/i915/display/skl_watermark.c

338

return true;

sys/dev/pci/drm/i915/display/skl_watermark.c

352

return true;

sys/dev/pci/drm/i915/display/skl_watermark.c

361

return true;

sys/dev/pci/drm/i915/display/skl_watermark.c

3676

return true;

sys/dev/pci/drm/i915/display/skl_watermark.c

3682

return true;

sys/dev/pci/drm/i915/display/skl_watermark.c

371

return true;

sys/dev/pci/drm/i915/display/skl_watermark.c

3733

return true;

sys/dev/pci/drm/i915/display/skl_watermark.c

3737

return true;

sys/dev/pci/drm/i915/display/vlv_dsi.c

1000

active = true;

sys/dev/pci/drm/i915/display/vlv_dsi.c

323

pipe_config->clock_set = true;

sys/dev/pci/drm/i915/display/vlv_dsi.c

739

intel_set_cpu_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

617

assert_dsi_pll(display, true);

sys/dev/pci/drm/i915/gem/i915_gem_clflush.c

115

obj->base.resv, true,

sys/dev/pci/drm/i915/gem/i915_gem_clflush.c

136

return true;

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1334

return rcu_dereference_protected(ctx->engines, true);

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1388

found = true;

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1514

kill_engines(engines, true,

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1704

ctx->uses_protected_content = true;

sys/dev/pci/drm/i915/gem/i915_gem_context.c

274

pc->uses_protected_content = true;

sys/dev/pci/drm/i915/gem/i915_gem_context.c

313

pc->single_timeline = true;

sys/dev/pci/drm/i915/gem/i915_gem_create.c

494

obj->pat_set_by_user = true;

sys/dev/pci/drm/i915/gem/i915_gem_dmabuf.c

126

i915_gem_ww_ctx_init(&ww, true);

sys/dev/pci/drm/i915/gem/i915_gem_dmabuf.c

150

i915_gem_ww_ctx_init(&ww, true);

sys/dev/pci/drm/i915/gem/i915_gem_dmabuf.c

178

for_i915_gem_ww(&ww, err, true) {

sys/dev/pci/drm/i915/gem/i915_gem_domain.c

174

obj->mm.dirty = true;

sys/dev/pci/drm/i915/gem/i915_gem_domain.c

238

obj->mm.dirty = true;

sys/dev/pci/drm/i915/gem/i915_gem_domain.c

289

obj->cache_dirty = true;

sys/dev/pci/drm/i915/gem/i915_gem_domain.c

48

return true;

sys/dev/pci/drm/i915/gem/i915_gem_domain.c

736

ret = i915_gem_object_set_to_cpu_domain(obj, true);

sys/dev/pci/drm/i915/gem/i915_gem_domain.c

763

obj->mm.dirty = true;

sys/dev/pci/drm/i915/gem/i915_gem_domain.c

84

obj->cache_dirty = true;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

1274

err = i915_gem_object_set_to_gtt_domain(obj, true);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

1808

i915_gem_ww_ctx_init(&eb->ww, true);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

1892

bool throttle = true;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

3470

eb_release_vmas(&eb, true);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

3474

i915_gem_ww_ctx_init(&eb.ww, true);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

3539

eb_release_vmas(&eb, true);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

386

return true;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

389

return true;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

393

return true;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

397

return true;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

401

return true;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

405

return true;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

638

return true;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

714

unpinned = true;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

917

err = intel_pxp_key_check(intel_bo_to_drm_bo(obj), true);

sys/dev/pci/drm/i915/gem/i915_gem_mman.c

321

obj->mm.dirty = true;

sys/dev/pci/drm/i915/gem/i915_gem_mman.c

397

trace_i915_gem_object_fault(obj, page_offset, true, write);

sys/dev/pci/drm/i915/gem/i915_gem_mman.c

401

i915_gem_ww_ctx_init(&ww, true);

sys/dev/pci/drm/i915/gem/i915_gem_mman.c

519

obj->mm.dirty = true;

sys/dev/pci/drm/i915/gem/i915_gem_mman.c

558

i915_gem_ww_ctx_init(&ww, true);

sys/dev/pci/drm/i915/gem/i915_gem_mman.c

682

obj->mm.dirty = true;

sys/dev/pci/drm/i915/gem/i915_gem_mman.c

771

trace_i915_gem_object_fault(obj, page_offset, true, write);

sys/dev/pci/drm/i915/gem/i915_gem_mman.c

775

i915_gem_ww_ctx_init(&ww, true);

sys/dev/pci/drm/i915/gem/i915_gem_mman.c

892

obj->mm.dirty = true;

sys/dev/pci/drm/i915/gem/i915_gem_object.c

229

return true;

sys/dev/pci/drm/i915/gem/i915_gem_object.c

554

return true;

sys/dev/pci/drm/i915/gem/i915_gem_object.c

607

return true;

sys/dev/pci/drm/i915/gem/i915_gem_object.c

68

return true;

sys/dev/pci/drm/i915/gem/i915_gem_object.c

716

return true;

sys/dev/pci/drm/i915/gem/i915_gem_object.c

725

return true;

sys/dev/pci/drm/i915/gem/i915_gem_object.c

732

return true;

sys/dev/pci/drm/i915/gem/i915_gem_object.c

852

return true;

sys/dev/pci/drm/i915/gem/i915_gem_object.c

876

return true;

sys/dev/pci/drm/i915/gem/i915_gem_object.c

884

lmem_placement = true;

sys/dev/pci/drm/i915/gem/i915_gem_object.h

199

return __i915_gem_object_lock(obj, ww, true);

sys/dev/pci/drm/i915/gem/i915_gem_object.h

30

return true;

sys/dev/pci/drm/i915/gem/i915_gem_object.h

800

obj->cache_dirty = true;

sys/dev/pci/drm/i915/gem/i915_gem_object_frontbuffer.h

93

cur = rcu_dereference_protected(obj->frontbuffer, true);

sys/dev/pci/drm/i915/gem/i915_gem_pages.c

153

i915_gem_ww_ctx_init(&ww, true);

sys/dev/pci/drm/i915/gem/i915_gem_pages.c

564

err = i915_gem_object_wait_moving_fence(obj, true);

sys/dev/pci/drm/i915/gem/i915_gem_pages.c

613

obj->mm.dirty = true;

sys/dev/pci/drm/i915/gem/i915_gem_shmem.c

313

obj->cache_dirty = true;

sys/dev/pci/drm/i915/gem/i915_gem_shmem.c

445

obj->cache_dirty = true;

sys/dev/pci/drm/i915/gem/i915_gem_shmem.c

450

__i915_gem_object_release_shmem(obj, pages, true);

sys/dev/pci/drm/i915/gem/i915_gem_shrinker.c

53

return true;

sys/dev/pci/drm/i915/gem/i915_gem_stolen.c

1036

mem->private = true;

sys/dev/pci/drm/i915/gem/i915_gem_stolen.c

1057

mem->private = true;

sys/dev/pci/drm/i915/gem/i915_gem_tiling.c

126

return true;

sys/dev/pci/drm/i915/gem/i915_gem_tiling.c

157

return true;

sys/dev/pci/drm/i915/gem/i915_gem_tiling.c

167

return true;

sys/dev/pci/drm/i915/gem/i915_gem_tiling.c

177

return true;

sys/dev/pci/drm/i915/gem/i915_gem_tiling.c

302

vma->fence->dirty = true;

sys/dev/pci/drm/i915/gem/i915_gem_ttm.c

1098

.interruptible = true,

sys/dev/pci/drm/i915/gem/i915_gem_ttm.c

1099

.no_wait_gpu = true, /* should be idle already */

sys/dev/pci/drm/i915/gem/i915_gem_ttm.c

1272

.interruptible = true,

sys/dev/pci/drm/i915/gem/i915_gem_ttm.c

1273

.no_wait_gpu = true, /* should be idle already */

sys/dev/pci/drm/i915/gem/i915_gem_ttm.c

1505

.interruptible = true,

sys/dev/pci/drm/i915/gem/i915_gem_ttm.c

1562

obj->ttm.created = true;

sys/dev/pci/drm/i915/gem/i915_gem_ttm.c

298

i915_tt->is_shmem = true;

sys/dev/pci/drm/i915/gem/i915_gem_ttm.c

432

.interruptible = true,

sys/dev/pci/drm/i915/gem/i915_gem_ttm.c

479

.interruptible = true,

sys/dev/pci/drm/i915/gem/i915_gem_ttm.c

632

true, 15 * HZ);

sys/dev/pci/drm/i915/gem/i915_gem_ttm.c

673

return true;

sys/dev/pci/drm/i915/gem/i915_gem_ttm.c

703

mem->bus.is_iomem = true;

sys/dev/pci/drm/i915/gem/i915_gem_ttm.c

807

.interruptible = true,

sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c

207

clear = true;

sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c

383

copy_work->obj->mm.unknown_state = true;

sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c

467

return I915_SELFTEST_ONLY(ban_memcpy) ? false : true;

sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c

652

dst_rsgt, true, &deps);

sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c

667

true, dst_mem);

sys/dev/pci/drm/i915/gem/i915_gem_userptr.c

143

obj->cache_dirty = true;

sys/dev/pci/drm/i915/gem/i915_gem_userptr.c

166

__i915_gem_object_release_shmem(obj, pages, true);

sys/dev/pci/drm/i915/gem/i915_gem_userptr.c

63

return true;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1063

err = i915_gem_object_set_to_gtt_domain(vma->obj, true);

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

39

WRITE_ONCE(vm->scrub_64K, true);

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

603

obj = fake_huge_pages_object(i915, size, true);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

120

return true;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

138

return true;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

694

return true;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

698

return true;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

156

err = i915_gem_object_set_to_wc_domain(ctx->obj, true);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

206

err = i915_gem_object_set_to_gtt_domain(ctx->obj, true);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

254

return true;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

90

err = i915_gem_object_set_to_gtt_domain(ctx->obj, true);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_dmabuf.c

105

force_different_devices = true;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_dmabuf.c

231

force_different_devices = true;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_dmabuf.c

303

true, 5 * HZ);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c

212

for_i915_gem_ww(&ww, err, true) {

sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c

236

err = igt_fill_check_buffer(obj, gt, true);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c

249

for_i915_gem_ww(&ww, err, true)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c

270

err = i915_gem_object_wait_migration(obj, true);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c

390

.interruptible = true

sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c

64

for_i915_gem_ww(&ww, err, true) {

sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c

69

err = igt_fill_check_buffer(obj, gt, true);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c

85

err = i915_gem_object_wait_migration(obj, true);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

119

err = i915_gem_object_set_to_gtt_domain(obj, true);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1245

err = i915_gem_object_wait_moving_fence(obj, true);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1249

i915_ttm_migrate_set_failure_modes(true, false);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1849

unuse_mm = true;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

207

err = i915_gem_object_set_to_gtt_domain(obj, true);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_phys.c

57

err = i915_gem_object_set_to_gtt_domain(obj, true);

sys/dev/pci/drm/i915/gt/gen6_ppgtt.c

204

flush = true;

sys/dev/pci/drm/i915/gt/gen6_ppgtt.c

94

ppgtt->scan_for_unused_pt = true;

sys/dev/pci/drm/i915/gt/gen6_ppgtt.h

60

(pt = i915_pt_entry(pd, iter), true); \

sys/dev/pci/drm/i915/gt/gen6_ppgtt.h

68

(pt = i915_pt_entry(pd, iter), true); \

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

349

*cs++ = preparser_disable(true);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

379

*cs++ = preparser_disable(true);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

43

vf_flush_wa = true;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

47

dc_flush_wa = true;

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

1074

gen8_ppgtt_notify_vgt(ppgtt, true);

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

564

pt->is_compact = true;

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

806

pt->is_compact = true;

sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c

109

return true;

sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c

128

return true;

sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c

418

return true;

sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c

427

return true;

sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c

434

return true;

sys/dev/pci/drm/i915/gt/intel_context.c

144

vma->obj->mm.dirty = true;

sys/dev/pci/drm/i915/gt/intel_context.c

290

handoff = true;

sys/dev/pci/drm/i915/gt/intel_context.c

325

i915_gem_ww_ctx_init(&ww, true);

sys/dev/pci/drm/i915/gt/intel_context.c

532

i915_gem_ww_ctx_init(&ww, true);

sys/dev/pci/drm/i915/gt/intel_context.h

396

return true;

sys/dev/pci/drm/i915/gt/intel_engine.h

257

__intel_engine_flush_submission(engine, true);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1102

i915_gem_ww_ctx_init(&ww, true);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1847

bool idle = true;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1850

return true;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1853

return true;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1902

return true;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1905

return true;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1929

return true;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1933

return true;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1940

return true;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1953

return true;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1994

return true;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2056

skip = true;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

556

DRIVER_CAPS(i915)->has_logical_contexts = true;

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

64

return true;

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

155

bool result = true;

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

168

return true;

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

172

return true;

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

179

return true;

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

42

int type = intel_gt_coherent_map_type(ce->engine->gt, obj, true);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1019

return true;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1170

return true;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1176

return true;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1181

return true;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1470

submit = true;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1494

bool merge = true;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1563

submit = true;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1716

return true;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2274

cap->error->gt->engine->hung = true;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2503

tasklet = true;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2513

tasklet = true;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2517

tasklet = true;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2569

return true;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3113

execlists_reset_active(engine, true);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3171

execlists_reset_csb(engine, true);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

337

return true;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

365

return true;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3867

first = true;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

461

lrc_init_regs(ce, engine, true);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

790

return true;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

806

bool ok = true;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

957

return true;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

980

return true;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

991

return true;

sys/dev/pci/drm/i915/gt/intel_ggtt.c

1116

ggtt->vm.skip_pte_rewrite = true;

sys/dev/pci/drm/i915/gt/intel_ggtt.c

162

vm->skip_pte_rewrite = true;

sys/dev/pci/drm/i915/gt/intel_ggtt.c

241

return true;

sys/dev/pci/drm/i915/gt/intel_ggtt.c

383

return true;

sys/dev/pci/drm/i915/gt/intel_ggtt.c

390

iter = __sgt_iter(pages->sgl, true);

sys/dev/pci/drm/i915/gt/intel_ggtt.c

462

return true;

sys/dev/pci/drm/i915/gt/intel_ggtt.c

585

return true;

sys/dev/pci/drm/i915/gt/intel_ggtt.c

61

ggtt->vm.is_ggtt = true;

sys/dev/pci/drm/i915/gt/intel_ggtt_gmch.c

106

ggtt->do_idle_maps = true;

sys/dev/pci/drm/i915/gt/intel_ggtt_gmch.c

79

return true;

sys/dev/pci/drm/i915/gt/intel_gt.c

1143

__intel_gt_bind_context_set_ready(gt, true);

sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c

136

node->pinned = true;

sys/dev/pci/drm/i915/gt/intel_gt_debugfs.c

69

intel_gt_mcr_report_steering(&p, gt, true);

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

207

return true;

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

577

return true;

sys/dev/pci/drm/i915/gt/intel_gt_pm.c

275

gt_sanitize(gt, true);

sys/dev/pci/drm/i915/gt/intel_gt_pm.c

349

user_forcewake(gt, true);

sys/dev/pci/drm/i915/gt/intel_gt_pm.c

58

gt->stats.active = true;

sys/dev/pci/drm/i915/gt/intel_gt_requests.c

162

true,

sys/dev/pci/drm/i915/gt/intel_gtt.c

104

type = intel_gt_coherent_map_type(vm->gt, obj, true);

sys/dev/pci/drm/i915/gt/intel_gtt.c

128

type = intel_gt_coherent_map_type(vm->gt, obj, true);

sys/dev/pci/drm/i915/gt/intel_gtt.c

174

vma->vm_ddestroy = true;

sys/dev/pci/drm/i915/gt/intel_gtt.c

481

bool can_use_gtt_cache = true;

sys/dev/pci/drm/i915/gt/intel_llc.c

74

return true;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1018

bool inhibit = true;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1190

lrc_init_regs(ce, ce->engine, true);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1455

u32 * const start = context_wabb(ce, true);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1590

bool valid = true;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1880

i915_gem_ww_ctx_init(&ww, true);

sys/dev/pci/drm/i915/gt/intel_migrate.c

195

for_i915_gem_ww(&ww, err, true) {

sys/dev/pci/drm/i915/gt/intel_migrate.c

35

return true;

sys/dev/pci/drm/i915/gt/intel_migrate.c

721

ccs_is_src = true;

sys/dev/pci/drm/i915/gt/intel_mocs.c

439

return true;

sys/dev/pci/drm/i915/gt/intel_ppgtt.c

138

free = true;

sys/dev/pci/drm/i915/gt/intel_ppgtt.c

193

vma_res->allocated = true;

sys/dev/pci/drm/i915/gt/intel_rc6.c

420

rc6->bios_state_captured = true;

sys/dev/pci/drm/i915/gt/intel_rc6.c

431

bool enable_rc6 = true;

sys/dev/pci/drm/i915/gt/intel_rc6.c

522

return true;

sys/dev/pci/drm/i915/gt/intel_rc6.c

529

rc6->wakeref = true;

sys/dev/pci/drm/i915/gt/intel_rc6.c

551

return true;

sys/dev/pci/drm/i915/gt/intel_rc6.c

667

rc6->enabled = true;

sys/dev/pci/drm/i915/gt/intel_region_lmem.c

219

return true;

sys/dev/pci/drm/i915/gt/intel_renderstate.c

167

i915_gem_ww_ctx_init(&so->ww, true);

sys/dev/pci/drm/i915/gt/intel_reset.c

102

banned = true;

sys/dev/pci/drm/i915/gt/intel_reset.c

1072

return true;

sys/dev/pci/drm/i915/gt/intel_reset.c

1145

return true;

sys/dev/pci/drm/i915/gt/intel_reset.c

1372

__intel_engine_reset(engine, true);

sys/dev/pci/drm/i915/gt/intel_reset.c

1616

return _intel_gt_reset_lock(gt, srcu, true);

sys/dev/pci/drm/i915/gt/intel_reset.c

1728

return true;

sys/dev/pci/drm/i915/gt/intel_reset.c

1733

return true;

sys/dev/pci/drm/i915/gt/intel_reset.c

453

lock_to_other = true;

sys/dev/pci/drm/i915/gt/intel_reset.c

71

return true;

sys/dev/pci/drm/i915/gt/intel_ring.h

77

return true;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

752

force_restore = true;

sys/dev/pci/drm/i915/gt/intel_rps.c

1086

err = rps_set(rps, val, true);

sys/dev/pci/drm/i915/gt/intel_rps.c

1230

if (rps_set(rps, rps->min_freq, true)) {

sys/dev/pci/drm/i915/gt/intel_rps.c

1236

return true;

sys/dev/pci/drm/i915/gt/intel_rps.c

1544

return true;

sys/dev/pci/drm/i915/gt/intel_rps.c

2152

return __read_cagf(rps, true);

sys/dev/pci/drm/i915/gt/intel_rps.c

2678

intel_rps_set_manual(rps, true);

sys/dev/pci/drm/i915/gt/intel_rps.c

2703

intel_rps_set_manual(rps, true);

sys/dev/pci/drm/i915/gt/intel_rps.c

2847

return true;

sys/dev/pci/drm/i915/gt/intel_rps.c

2874

return true;

sys/dev/pci/drm/i915/gt/intel_rps.c

626

return true;

sys/dev/pci/drm/i915/gt/intel_sseu_debugfs.c

242

i915_print_sseu_info(m, true, HAS_POOLED_EU(i915), &info->sseu);

sys/dev/pci/drm/i915/gt/intel_timeline.c

89

timeline->has_initial_breadcrumb = true;

sys/dev/pci/drm/i915/gt/intel_wopcm.c

124

return true;

sys/dev/pci/drm/i915/gt/intel_wopcm.c

143

return true;

sys/dev/pci/drm/i915/gt/intel_wopcm.c

158

return true;

sys/dev/pci/drm/i915/gt/intel_wopcm.c

212

return true;

sys/dev/pci/drm/i915/gt/intel_wopcm.c

218

return true;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1133

0 /* XXX does this reg exist? */, true);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1754

return true;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1819

bool ok = true;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1857

return true;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2274

0, true);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2666

IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2682

true);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2882

true);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2983

return true;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

301

wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

307

wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

313

wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

319

wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

326

wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

333

wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

669

true);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

29

timeout = dma_fence_wait_timeout(fence, true, HZ / 2);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

31

return true;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

34

return true;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

37

return true;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1194

WRITE_ONCE(threads[tmp].stop, true);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

850

return __igt_reset_engine(arg, true);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1507

return true;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1510

return true;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1616

return emit_wabb_ctx_canary(ce, cs, true);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1639

return true;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1747

return lrc_wabb_ctx(arg, true);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

190

engine->kernel_context, engine, true);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

42

return true;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

45

return true;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

48

return true;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

721

err = __live_lrc_gpr(engine, scratch, true);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

909

err = __lrc_timestamp(&data, true);

sys/dev/pci/drm/i915/gt/selftest_migrate.c

188

len = emit_pte(rq, &it, pat_index, true, offset, CHUNK_SZ);

sys/dev/pci/drm/i915/gt/selftest_migrate.c

280

ccs_cap = true;

sys/dev/pci/drm/i915/gt/selftest_migrate.c

282

for_i915_gem_ww(&ww, err, true) {

sys/dev/pci/drm/i915/gt/selftest_migrate.c

304

true, &rq);

sys/dev/pci/drm/i915/gt/selftest_migrate.c

61

for_i915_gem_ww(&ww, err, true) {

sys/dev/pci/drm/i915/gt/selftest_migrate.c

899

dst = create_init_lmem_internal(gt, sizes[i], true);

sys/dev/pci/drm/i915/gt/selftest_migrate.c

983

src = create_init_lmem_internal(gt, sizes[i], true);

sys/dev/pci/drm/i915/gt/selftest_rps.c

784

engine->kernel_context->vm, true,

sys/dev/pci/drm/i915/gt/selftest_slpc.c

323

err = intel_guc_slpc_set_ignore_eff_freq(slpc, true);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

230

{ "new", 0, false, true },

sys/dev/pci/drm/i915/gt/selftest_timeline.c

231

{ "0a", 0, true, true },

sys/dev/pci/drm/i915/gt/selftest_timeline.c

232

{ "1a", 1, false, true },

sys/dev/pci/drm/i915/gt/selftest_timeline.c

233

{ "1b", 1, true, true },

sys/dev/pci/drm/i915/gt/selftest_timeline.c

234

{ "0b", 0, true, false },

sys/dev/pci/drm/i915/gt/selftest_timeline.c

235

{ "2a", 2, false, true },

sys/dev/pci/drm/i915/gt/selftest_timeline.c

236

{ "4", 4, false, true },

sys/dev/pci/drm/i915/gt/selftest_timeline.c

237

{ "INT_MAX", INT_MAX, false, true },

sys/dev/pci/drm/i915/gt/selftest_timeline.c

238

{ "INT_MAX-1", INT_MAX-1, true, false },

sys/dev/pci/drm/i915/gt/selftest_timeline.c

239

{ "INT_MAX+1", (u32)INT_MAX+1, false, true },

sys/dev/pci/drm/i915/gt/selftest_timeline.c

240

{ "INT_MAX", INT_MAX, true, false },

sys/dev/pci/drm/i915/gt/selftest_timeline.c

241

{ "UINT_MAX", UINT_MAX, false, true },

sys/dev/pci/drm/i915/gt/selftest_timeline.c

242

{ "wrap", 0, false, true },

sys/dev/pci/drm/i915/gt/selftest_timeline.c

243

{ "unwrap", UINT_MAX, true, false },

sys/dev/pci/drm/i915/gt/selftest_tlb.c

310

for_i915_gem_ww(&ww, err, true)

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1015

return true;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1171

bool ok = true;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

425

return true;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

430

return true;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

443

return true;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

454

return true;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

966

return true;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

993

return true;

sys/dev/pci/drm/i915/gt/shmem_utils.c

170

return __shmem_rw(file, off, src, len, true);

sys/dev/pci/drm/i915/gt/shmem_utils.c

293

return __uao_rw(uao, off, src, len, true);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

128

return __caps_show(engine, engine->uabi_capabilities, buf, true);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

240

too_old = true;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

243

too_old = true;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

246

too_old = true;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

339

intel_gt_coherent_map_type(gt, gsc->fw.obj, true));

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

56

if (!intel_gsc_uc_fw_proxy_init_done(gsc, true))

sys/dev/pci/drm/i915/gt/uc/intel_gsc_proxy.c

421

gsc->proxy.component_added = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

106

guc->interrupts.enabled = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

151

guc->interrupts.enabled = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

184

intel_uc_fw_init_early(&guc->fw, INTEL_UC_FW_TYPE_GUC, true);

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

846

vma->obj, true));

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

201

return intel_guc_send_busy_loop(guc, action, ARRAY_SIZE(action), 0, true);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

403

ret |= GUC_MMIO_REG_ADD(gt, regset, RING_MODE_GEN7(base), true);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

409

ret |= GUC_MMIO_REG_ADD(gt, regset, GEN12_RCU_MODE, true);

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

1556

return true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

549

cache->is_valid = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

573

cache->is_valid = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

637

if (!guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_GLOBAL, 0, &tmp, true))

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

641

engine->class, &tmp, true)) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

645

engine->class, &tmp, true)) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

811

return true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

1015

found = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

1077

found = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

1085

found = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

1189

return true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

1400

ct->dead_ct_reported = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

367

err = ct_register_buffer(ct, true, desc, cmds, size);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

371

err = ct_control_enable(ct, true);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

375

ct->enabled = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

521

ctb->broken = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

592

ct->ctbs.send.broken = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

632

return true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

639

ctb->broken = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

800

send_again = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

998

ctb->broken = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

116

*success = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

117

return true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

130

return true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

145

return true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_hwconfig.c

101

return true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_hwconfig.c

103

return true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c

114

log->sizes_initialised = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c

338

overflow = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c

512

log->relay.buf_in_use = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c

788

log->relay.started = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_log_debugfs.c

80

return intel_guc_log_dump(m->private, &p, true);

sys/dev/pci/drm/i915/gt/uc/intel_guc_rc.c

75

return __guc_rc_control(guc, true);

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

698

return true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

710

slpc->min_is_rpmax = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1795

lrc_init_regs(ce, engine, true);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2176

guc->submission_initialized = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2632

true);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3063

G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, true);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3082

G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, true);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3194

enable = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3225

true);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3242

__guc_context_set_context_policies(guc, &policy, true);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3250

intel_guc_send_busy_loop(guc, action, ARRAY_SIZE(action), 0, true);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3335

return true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3365

return true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3630

__guc_context_set_context_policies(guc, &policy, true);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3638

guc_submission_send_busy_loop(guc, action, ARRAY_SIZE(action), 0, true);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3954

ret = try_context_registration(ce, true);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4474

ret = try_context_registration(ce, true);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4788

guc_route_semaphores(guc, true);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4961

return true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5006

wq->busy = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5017

err = intel_guc_send_busy_loop(guc, action, size, G2H_LEN_DW_INVALIDATE_TLB, true);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5089

register_context(ce, true);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5428

found = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

6009

return true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

690

true, timeout);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

938

submit = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

976

submit = true;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

980

submit = true;

sys/dev/pci/drm/i915/gt/uc/intel_huc.c

298

intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC, true);

sys/dev/pci/drm/i915/gt/uc/intel_huc_fw.c

122

return true;

sys/dev/pci/drm/i915/gt/uc/intel_huc_fw.c

45

intel_gt_coherent_map_type(gt, obj, true));

sys/dev/pci/drm/i915/gt/uc/intel_uc.c

607

uc->reset_in_progress = true;

sys/dev/pci/drm/i915/gt/uc/intel_uc.c

762

return __uc_resume(uc, true);

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

1227

intel_gt_coherent_map_type(gt, vma->obj, true));

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

1429

got_wanted = true;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

223

.legacy = true }

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

241

UC_FW_BLOB_NEW(0, 0, 0, true, MAKE_HUC_FW_PATH_GSC(prefix_))

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

244

UC_FW_BLOB_NEW(major_, minor_, 0, true, \

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

334

found = true;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

359

return true;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

446

return true;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

486

uc_fw->user_overridden = true;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

530

gt->uc.fw_table_invalid = true;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

578

uc_fw->user_overridden = true;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

878

*old_ver = true;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

881

*old_ver = true;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

923

old_ver = true;

sys/dev/pci/drm/i915/gt/uc/selftest_guc.c

338

spinning = true;

sys/dev/pci/drm/i915/gt/uc/selftest_guc.c

76

ce->drop_schedule_enable = true;

sys/dev/pci/drm/i915/gt/uc/selftest_guc.c

79

ce->drop_schedule_disable = true;

sys/dev/pci/drm/i915/gt/uc/selftest_guc.c

82

ce->drop_deregister = true;

sys/dev/pci/drm/i915/gvt/aperture_gm.c

91

ret = alloc_gm(vgpu, true);

sys/dev/pci/drm/i915/gvt/cfg_space.c

101

vgpu->d3_entered = true;

sys/dev/pci/drm/i915/gvt/cfg_space.c

160

trap_gttmmio(vgpu, true);

sys/dev/pci/drm/i915/gvt/cfg_space.c

161

map_aperture(vgpu, true);

sys/dev/pci/drm/i915/gvt/cfg_space.c

343

gvt_aperture_pa_base(gvt), true);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1210

index_mode = true;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1739

index_mode = true;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1858

bb_end = true;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1862

bb_end = true;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

2911

s.is_ctx_wa = true;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

3144

s.is_init_ctx = true;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

3159

gvt->is_reg_whitelist_updated = true;

sys/dev/pci/drm/i915/gvt/display.c

575

port->edid->data_valid = true;

sys/dev/pci/drm/i915/gvt/display.c

578

port->dpcd->data_valid = true;

sys/dev/pci/drm/i915/gvt/dmabuf.c

249

return true;

sys/dev/pci/drm/i915/gvt/dmabuf.c

435

dmabuf_obj->initref = true;

sys/dev/pci/drm/i915/gvt/dmabuf.c

475

dmabuf_obj->initref = true;

sys/dev/pci/drm/i915/gvt/edid.c

174

vgpu->display.i2c_edid.edid_available = true;

sys/dev/pci/drm/i915/gvt/edid.c

220

i2c_edid->target_selected = true;

sys/dev/pci/drm/i915/gvt/edid.c

521

i2c_edid->aux_ch.i2c_over_aux_ch = true;

sys/dev/pci/drm/i915/gvt/edid.c

522

i2c_edid->aux_ch.aux_ch_mot = true;

sys/dev/pci/drm/i915/gvt/edid.c

529

i2c_edid->target_selected = true;

sys/dev/pci/drm/i915/gvt/edid.c

533

i2c_edid->edid_available = true;

sys/dev/pci/drm/i915/gvt/execlist.c

237

emulate_csb_update(execlist, &status, true);

sys/dev/pci/drm/i915/gvt/firmware.c

245

firmware->firmware_loaded = true;

sys/dev/pci/drm/i915/gvt/gtt.c

1357

ops->get_entry(NULL, &new, index, true,

sys/dev/pci/drm/i915/gvt/gtt.c

1736

mm->ppgtt_mm.shadowed = true;

sys/dev/pci/drm/i915/gvt/gtt.c

2193

found = true;

sys/dev/pci/drm/i915/gvt/gtt.c

2213

partial_update = true;

sys/dev/pci/drm/i915/gvt/gtt.c

504

_ppgtt_get_root_entry(mm, entry, index, true);

sys/dev/pci/drm/i915/gvt/gtt.c

636

spt->guest_page.type, e, index, true)

sys/dev/pci/drm/i915/gvt/gtt.c

64

return true;

sys/dev/pci/drm/i915/gvt/gtt.c

640

spt->guest_page.type, e, index, true)

sys/dev/pci/drm/i915/gvt/gtt.c

67

return true;

sys/dev/pci/drm/i915/gvt/gtt.c

999

return true;

sys/dev/pci/drm/i915/gvt/gvt.h

743

return vfio_dma_rw(&vgpu->vfio_device, gpa, buf, len, true);

sys/dev/pci/drm/i915/gvt/handlers.c

1109

drm_WARN_ON(&dev_priv->drm, true);

sys/dev/pci/drm/i915/gvt/handlers.c

1242

dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true);

sys/dev/pci/drm/i915/gvt/handlers.c

1306

true);

sys/dev/pci/drm/i915/gvt/handlers.c

1468

invalid_read = true;

sys/dev/pci/drm/i915/gvt/handlers.c

1474

invalid_read = true;

sys/dev/pci/drm/i915/gvt/handlers.c

1480

invalid_read = true;

sys/dev/pci/drm/i915/gvt/handlers.c

1486

vgpu->pv_notified = true;

sys/dev/pci/drm/i915/gvt/handlers.c

1562

invalid_write = true;

sys/dev/pci/drm/i915/gvt/handlers.c

1566

invalid_write = true;

sys/dev/pci/drm/i915/gvt/handlers.c

1587

drm_WARN_ONCE(&i915->drm, true,

sys/dev/pci/drm/i915/gvt/handlers.c

202

vgpu->failsafe = true;

sys/dev/pci/drm/i915/gvt/handlers.c

723

vgpu_update_vblank_emulation(vgpu, true);

sys/dev/pci/drm/i915/gvt/handlers.c

780

return true;

sys/dev/pci/drm/i915/gvt/interrupt.c

410

down_info->has_upstream_irq = true;

sys/dev/pci/drm/i915/gvt/interrupt.c

488

vgpu->irq.irq_warn_once[event] = true;

sys/dev/pci/drm/i915/gvt/kvmgt.c

462

intel_vgpu_emulate_hotplug(vgpu, true);

sys/dev/pci/drm/i915/gvt/kvmgt.c

653

ret = true;

sys/dev/pci/drm/i915/gvt/kvmgt.c

862

true : false;

sys/dev/pci/drm/i915/gvt/kvmgt.c

959

ppos, true);

sys/dev/pci/drm/i915/gvt/kvmgt.c

971

ppos, true);

sys/dev/pci/drm/i915/gvt/kvmgt.c

983

sizeof(val), ppos, true);

sys/dev/pci/drm/i915/gvt/kvmgt.c

995

ppos, true);

sys/dev/pci/drm/i915/gvt/mmio.c

118

failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, true);

sys/dev/pci/drm/i915/gvt/mmio.c

158

ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, true);

sys/dev/pci/drm/i915/gvt/mmio.c

322

intel_vgpu_reset_mmio(vgpu, true);

sys/dev/pci/drm/i915/gvt/mmio_context.c

108

{RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

109

{RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

110

{RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

111

{RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

112

{RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

113

{RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

117

{RCS0, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

118

{RCS0, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

123

{RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

124

{RCS0, _MMIO(0xe180), 0xffff, true}, /* HALF_SLICE_CHICKEN2 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

125

{RCS0, _MMIO(0xe184), 0xffff, true}, /* GEN8_HALF_SLICE_CHICKEN3 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

126

{RCS0, _MMIO(0xe188), 0xffff, true}, /* GEN9_HALF_SLICE_CHICKEN5 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

127

{RCS0, _MMIO(0xe194), 0xffff, true}, /* GEN9_HALF_SLICE_CHICKEN7 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

128

{RCS0, _MMIO(0xe4f0), 0xffff, true}, /* GEN8_ROW_CHICKEN */

sys/dev/pci/drm/i915/gvt/mmio_context.c

129

{RCS0, TRVATTL3PTRDW(0), 0, true}, /* 0x4de0 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

130

{RCS0, TRVATTL3PTRDW(1), 0, true}, /* 0x4de4 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

131

{RCS0, TRNULLDETCT, 0, true}, /* 0x4de8 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

132

{RCS0, TRINVTILEDETCT, 0, true}, /* 0x4dec */

sys/dev/pci/drm/i915/gvt/mmio_context.c

133

{RCS0, TRVADR, 0, true}, /* 0x4df0 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

134

{RCS0, TRTTE, 0, true}, /* 0x4df4 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

135

{RCS0, _MMIO(0x4dfc), 0, true},

sys/dev/pci/drm/i915/gvt/mmio_context.c

147

{RCS0, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

154

{RCS0, _MMIO(0x20D8), 0xffff, true}, /* 0x20d8 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

207

gen9_render_mocs.initialized = true;

sys/dev/pci/drm/i915/gvt/mmio_context.c

63

{RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

76

{RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

77

{RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

78

{RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

79

{RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

80

{RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

81

{RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

95

{RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */

sys/dev/pci/drm/i915/gvt/opregion.c

180

v->child0.dp_compat = true;

sys/dev/pci/drm/i915/gvt/opregion.c

181

v->child0.integrated_encoder = true;

sys/dev/pci/drm/i915/gvt/opregion.c

188

v->child1.dp_compat = true;

sys/dev/pci/drm/i915/gvt/opregion.c

189

v->child1.integrated_encoder = true;

sys/dev/pci/drm/i915/gvt/opregion.c

196

v->child2.dp_compat = true;

sys/dev/pci/drm/i915/gvt/opregion.c

197

v->child2.integrated_encoder = true;

sys/dev/pci/drm/i915/gvt/opregion.c

204

v->child3.dp_compat = true;

sys/dev/pci/drm/i915/gvt/opregion.c

205

v->child3.integrated_encoder = true;

sys/dev/pci/drm/i915/gvt/opregion.c

401

return true;

sys/dev/pci/drm/i915/gvt/page_track.c

118

track->tracked = true;

sys/dev/pci/drm/i915/gvt/sched_policy.c

152

scheduler->need_reschedule = true;

sys/dev/pci/drm/i915/gvt/sched_policy.c

352

vgpu_data->pri_sched = true;

sys/dev/pci/drm/i915/gvt/sched_policy.c

359

vgpu_data->active = true;

sys/dev/pci/drm/i915/gvt/sched_policy.c

44

return true;

sys/dev/pci/drm/i915/gvt/sched_policy.c

465

scheduler->need_reschedule = true;

sys/dev/pci/drm/i915/gvt/scheduler.c

1503

s->active = true;

sys/dev/pci/drm/i915/gvt/scheduler.c

151

sr_oa_regs(workload, (u32 *)shadow_ring_context, true);

sys/dev/pci/drm/i915/gvt/scheduler.c

206

skip = true;

sys/dev/pci/drm/i915/gvt/scheduler.c

258

s->last_ctx[ring_id].valid = true;

sys/dev/pci/drm/i915/gvt/scheduler.c

512

workload->shadow = true;

sys/dev/pci/drm/i915/gvt/scheduler.c

839

workload->dispatched = true;

sys/dev/pci/drm/i915/gvt/scheduler.c

929

return true;

sys/dev/pci/drm/i915/gvt/vgpu.c

247

intel_vgpu_reset_ggtt(vgpu, true);

sys/dev/pci/drm/i915/gvt/vgpu.c

471

intel_vgpu_reset_ggtt(vgpu, true);

sys/dev/pci/drm/i915/gvt/vgpu.c

509

intel_gvt_reset_vgpu_locked(vgpu, true, 0);

sys/dev/pci/drm/i915/i915_cmd_parser.c

1252

return true;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1347

return true;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1602

active = true;

sys/dev/pci/drm/i915/i915_cmd_parser.c

211

#define F true

sys/dev/pci/drm/i915/i915_cmd_parser.c

807

bool ret = true;

sys/dev/pci/drm/i915/i915_cmd_parser.c

810

return true;

sys/dev/pci/drm/i915/i915_cmd_parser.c

844

bool ret = true;

sys/dev/pci/drm/i915/i915_cmd_parser.c

875

return true;

sys/dev/pci/drm/i915/i915_deps.c

229

dma_resv_for_each_fence(&iter, resv, dma_resv_usage_rw(true), fence) {

sys/dev/pci/drm/i915/i915_driver.c

1047

return true;

sys/dev/pci/drm/i915/i915_driver.c

1423

return i915_drm_suspend_late(&i915->drm, true);

sys/dev/pci/drm/i915/i915_driver.c

1481

ret = i915_drm_suspend_late(&i915->drm, true);

sys/dev/pci/drm/i915/i915_driver.c

1646

ret = vlv_resume_prepare(dev_priv, true);

sys/dev/pci/drm/i915/i915_driver.c

2609

dev->registered = true;

sys/dev/pci/drm/i915/i915_driver.c

2657

dev->registered = true;

sys/dev/pci/drm/i915/i915_driver.c

875

i915->do_release = true;

sys/dev/pci/drm/i915/i915_gem.c

1013

for_i915_gem_ww(&ww, err, true) {

sys/dev/pci/drm/i915/i915_gem.c

311

i915_gem_ww_ctx_init(&ww, true);

sys/dev/pci/drm/i915/i915_gem.c

575

vma = i915_gem_gtt_prepare(obj, &node, true);

sys/dev/pci/drm/i915/i915_gem.c

885

reg->dirty = true;

sys/dev/pci/drm/i915/i915_gem_evict.c

115

return true;

sys/dev/pci/drm/i915/i915_gem_evict.c

118

return true;

sys/dev/pci/drm/i915/i915_gem_evict.c

83

return true;

sys/dev/pci/drm/i915/i915_gpu_error.c

1250

true);

sys/dev/pci/drm/i915/i915_gpu_error.c

1275

true);

sys/dev/pci/drm/i915/i915_gpu_error.c

129

return true;

sys/dev/pci/drm/i915/i915_gpu_error.c

1520

return true;

sys/dev/pci/drm/i915/i915_gpu_error.c

2258

error->gt->uc->guc.is_guc_capture = true;

sys/dev/pci/drm/i915/i915_gpu_error.c

297

return true;

sys/dev/pci/drm/i915/i915_gpu_error.c

420

return true;

sys/dev/pci/drm/i915/i915_gpu_error.c

87

return true;

sys/dev/pci/drm/i915/i915_gpu_error.c

983

print_guc_capture = true;

sys/dev/pci/drm/i915/i915_hwmon.c

554

hwmon->ddat.reset_in_progress = true;

sys/dev/pci/drm/i915/i915_irq.c

1230

dev_priv->irqs_enabled = true;

sys/dev/pci/drm/i915/i915_irq.c

1296

i915->irqs_enabled = true;

sys/dev/pci/drm/i915/i915_memcpy.c

133

return true;

sys/dev/pci/drm/i915/i915_memcpy.c

184

has_movntdqa = true;

sys/dev/pci/drm/i915/i915_mitigations.c

113

enable = true;

sys/dev/pci/drm/i915/i915_mitigations.c

36

bool first = true;

sys/dev/pci/drm/i915/i915_mitigations.c

46

bool enable = true;

sys/dev/pci/drm/i915/i915_module.c

24

bool use_kms = true;

sys/dev/pci/drm/i915/i915_params.h

64

param(bool, enable_hangcheck, true, 0600) \

sys/dev/pci/drm/i915/i915_params.h

65

param(bool, error_capture, true, IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) ? 0600 : 0) \

sys/dev/pci/drm/i915/i915_pci.c

103

.has_snoop = true, \

sys/dev/pci/drm/i915/i915_pci.c

133

.gpu_reset_clobbers_display = true, \

sys/dev/pci/drm/i915/i915_pci.c

136

.has_snoop = true, \

sys/dev/pci/drm/i915/i915_pci.c

137

.has_coherent_ggtt = true, \

sys/dev/pci/drm/i915/i915_pci.c

196

.gpu_reset_clobbers_display = true, \

sys/dev/pci/drm/i915/i915_pci.c

199

.has_snoop = true, \

sys/dev/pci/drm/i915/i915_pci.c

200

.has_coherent_ggtt = true, \

sys/dev/pci/drm/i915/i915_pci.c

241

.has_snoop = true, \

sys/dev/pci/drm/i915/i915_pci.c

242

.has_coherent_ggtt = true, \

sys/dev/pci/drm/i915/i915_pci.c

260

.has_rps = true,

sys/dev/pci/drm/i915/i915_pci.c

267

.has_coherent_ggtt = true, \

sys/dev/pci/drm/i915/i915_pci.c

272

.has_rps = true, \

sys/dev/pci/drm/i915/i915_pci.c

315

.has_coherent_ggtt = true, \

sys/dev/pci/drm/i915/i915_pci.c

319

.has_reset_engine = true, \

sys/dev/pci/drm/i915/i915_pci.c

320

.has_rps = true, \

sys/dev/pci/drm/i915/i915_pci.c

372

.has_reset_engine = true,

sys/dev/pci/drm/i915/i915_pci.c

373

.has_rps = true,

sys/dev/pci/drm/i915/i915_pci.c

378

.has_snoop = true,

sys/dev/pci/drm/i915/i915_pci.c

457

.has_rps = true,

sys/dev/pci/drm/i915/i915_pci.c

464

.has_snoop = true,

sys/dev/pci/drm/i915/i915_pci.c

518

.has_rps = true, \

sys/dev/pci/drm/i915/i915_pci.c

525

.has_snoop = true, \

sys/dev/pci/drm/i915/i915_pci.c

83

.gpu_reset_clobbers_display = true, \

sys/dev/pci/drm/i915/i915_pci.c

88

.has_snoop = true, \

sys/dev/pci/drm/i915/i915_pci.c

900

return true;

sys/dev/pci/drm/i915/i915_pci.c

902

return true;

sys/dev/pci/drm/i915/i915_pci.c

918

ret = true;

sys/dev/pci/drm/i915/i915_pci.c

935

return device_id_in_list(device_id, i915_modparams.force_probe, true);

sys/dev/pci/drm/i915/i915_pci.c

949

return true;

sys/dev/pci/drm/i915/i915_pci.c

99

.gpu_reset_clobbers_display = true, \

sys/dev/pci/drm/i915/i915_perf.c

1313

i915_gem_ww_ctx_init(&ww, true);

sys/dev/pci/drm/i915/i915_perf.c

1465

found = true;

sys/dev/pci/drm/i915/i915_perf.c

1994

i915_gem_ww_ctx_init(&ww, true);

sys/dev/pci/drm/i915/i915_perf.c

2029

stream, cs, true /* save */, CS_GPR(i),

sys/dev/pci/drm/i915/i915_perf.c

2032

stream, cs, true /* save */, mi_predicate_result,

sys/dev/pci/drm/i915/i915_perf.c

2240

i915_gem_ww_ctx_init(&ww, true);

sys/dev/pci/drm/i915/i915_perf.c

2341

i915_gem_ww_ctx_init(&ww, true);

sys/dev/pci/drm/i915/i915_perf.c

273

static u32 i915_perf_stream_paranoid = true;

sys/dev/pci/drm/i915/i915_perf.c

3526

stream->pollin = true;

sys/dev/pci/drm/i915/i915_perf.c

3609

stream->enabled = true;

sys/dev/pci/drm/i915/i915_perf.c

3840

bool privileged_op = true;

sys/dev/pci/drm/i915/i915_perf.c

3890

privileged_op = true;

sys/dev/pci/drm/i915/i915_perf.c

3897

privileged_op = true;

sys/dev/pci/drm/i915/i915_perf.c

4127

props->oa_periodic = true;

sys/dev/pci/drm/i915/i915_perf.c

4148

config_sseu = true;

sys/dev/pci/drm/i915/i915_perf.c

4162

config_class = true;

sys/dev/pci/drm/i915/i915_perf.c

4166

config_instance = true;

sys/dev/pci/drm/i915/i915_perf.c

4227

props->has_sseu = true;

sys/dev/pci/drm/i915/i915_perf.c

4361

return true;

sys/dev/pci/drm/i915/i915_perf.c

4370

return true;

sys/dev/pci/drm/i915/i915_pmu.c

1199

pmu->registered = true;

sys/dev/pci/drm/i915/i915_pmu.c

290

pmu->timer_enabled = true;

sys/dev/pci/drm/i915/i915_pmu.c

944

.global = true, \

sys/dev/pci/drm/i915/i915_query.c

463

return query_perf_config_data(i915, query_item, true);

sys/dev/pci/drm/i915/i915_request.c

1980

return true;

sys/dev/pci/drm/i915/i915_request.c

2019

return true;

sys/dev/pci/drm/i915/i915_request.c

287

ret = true;

sys/dev/pci/drm/i915/i915_request.c

462

return true;

sys/dev/pci/drm/i915/i915_request.c

600

return true;

sys/dev/pci/drm/i915/i915_request.c

637

return true;

sys/dev/pci/drm/i915/i915_request.c

722

result = true;

sys/dev/pci/drm/i915/i915_request.h

556

return true;

sys/dev/pci/drm/i915/i915_request.h

558

result = true;

sys/dev/pci/drm/i915/i915_request.h

621

return true;

sys/dev/pci/drm/i915/i915_request.h

623

result = true;

sys/dev/pci/drm/i915/i915_request.h

682

return rcu_dereference_protected(rq->context->gem_context, true);

sys/dev/pci/drm/i915/i915_scatterlist.c

40

return true;

sys/dev/pci/drm/i915/i915_scatterlist.h

103

(__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)

sys/dev/pci/drm/i915/i915_scatterlist.h

90

for ((__iter) = __sgt_iter((__sgt)->sgl, true); \

sys/dev/pci/drm/i915/i915_scatterlist.h

93

(__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)

sys/dev/pci/drm/i915/i915_scheduler.c

109

sched_engine->no_priolist = true;

sys/dev/pci/drm/i915/i915_scheduler.c

365

ret = true;

sys/dev/pci/drm/i915/i915_scheduler.c

64

bool first = true;

sys/dev/pci/drm/i915/i915_sw_fence.c

236

return true;

sys/dev/pci/drm/i915/i915_sw_fence.c

291

return true;

sys/dev/pci/drm/i915/i915_sw_fence.c

298

return true;

sys/dev/pci/drm/i915/i915_ttm_buddy_manager.c

163

return true;

sys/dev/pci/drm/i915/i915_ttm_buddy_manager.c

184

return true;

sys/dev/pci/drm/i915/i915_ttm_buddy_manager.c

201

return true;

sys/dev/pci/drm/i915/i915_ttm_buddy_manager.c

220

return true;

sys/dev/pci/drm/i915/i915_ttm_buddy_manager.c

312

ttm_resource_manager_set_used(man, true);

sys/dev/pci/drm/i915/i915_utils.c

57

return true;

sys/dev/pci/drm/i915/i915_vgpu.c

100

dev_priv->vgpu.active = true;

sys/dev/pci/drm/i915/i915_vma.c

1637

i915_gem_ww_ctx_init(&ww, true);

sys/dev/pci/drm/i915/i915_vma.c

1711

for_i915_gem_ww(&_ww, err, true) {

sys/dev/pci/drm/i915/i915_vma.c

2057

obj->mm.dirty = true;

sys/dev/pci/drm/i915/i915_vma.c

2202

fence = __i915_vma_evict(vma, true);

sys/dev/pci/drm/i915/i915_vma.c

426

err = dma_fence_wait(fence, true);

sys/dev/pci/drm/i915/i915_vma.c

528

true,

sys/dev/pci/drm/i915/i915_vma.c

534

vma->node.size, true);

sys/dev/pci/drm/i915/i915_vma.c

576

ret = i915_gem_object_wait_moving_fence(vma->obj, true);

sys/dev/pci/drm/i915/i915_vma.c

704

return true;

sys/dev/pci/drm/i915/i915_vma.c

707

return true;

sys/dev/pci/drm/i915/i915_vma.c

711

return true;

sys/dev/pci/drm/i915/i915_vma.c

714

return true;

sys/dev/pci/drm/i915/i915_vma.c

718

return true;

sys/dev/pci/drm/i915/i915_vma.c

722

return true;

sys/dev/pci/drm/i915/i915_vma.c

726

return true;

sys/dev/pci/drm/i915/i915_vma.c

763

return true;

sys/dev/pci/drm/i915/i915_vma.c

779

return true;

sys/dev/pci/drm/i915/i915_vma.c

974

return true;

sys/dev/pci/drm/i915/intel_device_info.c

223

return true;

sys/dev/pci/drm/i915/intel_gvt.c

55

return true;

sys/dev/pci/drm/i915/intel_gvt.c

57

return true;

sys/dev/pci/drm/i915/intel_gvt.c

59

return true;

sys/dev/pci/drm/i915/intel_gvt.c

61

return true;

sys/dev/pci/drm/i915/intel_gvt.c

63

return true;

sys/dev/pci/drm/i915/intel_gvt.c

65

return true;

sys/dev/pci/drm/i915/intel_memory_region.c

183

return true;

sys/dev/pci/drm/i915/intel_pcode.c

101

err = __snb_pcode_rw(uncore, mbox, val, val1, 500, 20, true);

sys/dev/pci/drm/i915/intel_pcode.c

135

*status = __snb_pcode_rw(uncore, mbox, &request, NULL, 500, 0, true);

sys/dev/pci/drm/i915/intel_runtime_pm.c

216

return __intel_runtime_pm_get(rpm, true);

sys/dev/pci/drm/i915/intel_runtime_pm.c

258

intel_runtime_pm_acquire(rpm, true);

sys/dev/pci/drm/i915/intel_runtime_pm.c

270

return __intel_runtime_pm_get_if_active(rpm, true);

sys/dev/pci/drm/i915/intel_runtime_pm.c

293

intel_runtime_pm_acquire(rpm, true);

sys/dev/pci/drm/i915/intel_runtime_pm.c

341

__intel_runtime_pm_put(rpm, INTEL_WAKEREF_DEF, true);

sys/dev/pci/drm/i915/intel_runtime_pm.c

356

__intel_runtime_pm_put(rpm, wref, true);

sys/dev/pci/drm/i915/intel_uncore.c

1834

return true;

sys/dev/pci/drm/i915/intel_uncore.c

1907

unclaimed_reg_debug = unclaimed_reg_debug_header(uncore, reg, true)

sys/dev/pci/drm/i915/intel_uncore.c

1911

unclaimed_reg_debug_footer(uncore, reg, true); \

sys/dev/pci/drm/i915/intel_uncore.c

1971

trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \

sys/dev/pci/drm/i915/intel_uncore.c

2010

trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \

sys/dev/pci/drm/i915/intel_uncore.c

2062

trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \

sys/dev/pci/drm/i915/intel_uncore.c

2848

trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);

sys/dev/pci/drm/i915/intel_uncore.c

2892

ret = true;

sys/dev/pci/drm/i915/intel_uncore.c

578

return true;

sys/dev/pci/drm/i915/intel_uncore.c

592

return true;

sys/dev/pci/drm/i915/intel_uncore.c

705

domain->active = true;

sys/dev/pci/drm/i915/intel_uncore.c

808

domain->active = true;

sys/dev/pci/drm/i915/intel_uncore.c

850

__intel_uncore_forcewake_put(uncore, fw_domains, true);

sys/dev/pci/drm/i915/intel_uncore.h

372

__uncore_read(read8, 8, b, true)

sys/dev/pci/drm/i915/intel_uncore.h

373

__uncore_read(read16, 16, w, true)

sys/dev/pci/drm/i915/intel_uncore.h

374

__uncore_read(read, 32, l, true)

sys/dev/pci/drm/i915/intel_uncore.h

378

__uncore_write(write8, 8, b, true)

sys/dev/pci/drm/i915/intel_uncore.h

379

__uncore_write(write16, 16, w, true)

sys/dev/pci/drm/i915/intel_uncore.h

380

__uncore_write(write, 32, l, true)

sys/dev/pci/drm/i915/intel_uncore.h

397

__uncore_read(read64, 64, q, true)

sys/dev/pci/drm/i915/pxp/intel_pxp.c

211

is_full_feature = true;

sys/dev/pci/drm/i915/pxp/intel_pxp.c

289

bound = true;

sys/dev/pci/drm/i915/pxp/intel_pxp.c

375

return true;

sys/dev/pci/drm/i915/pxp/intel_pxp.c

378

return true;

sys/dev/pci/drm/i915/pxp/intel_pxp.c

75

kcr_pxp_set_status(pxp, true);

sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.c

202

intel_gsc_uc_fw_proxy_init_done(&pxp->ctrl_gt->uc.gsc, true))

sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.c

203

return true;

sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.c

27

pxp->platform_cfg_is_bad = true;

sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.c

28

return true;

sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.c

341

*map = i915_gem_object_pin_map_unlocked(obj, intel_gt_coherent_map_type(gt, obj, true));

sys/dev/pci/drm/i915/pxp/intel_pxp_irq.c

80

pxp->irq_enabled = true;

sys/dev/pci/drm/i915/pxp/intel_pxp_pm.c

62

_pxp_resume(pxp, true);

sys/dev/pci/drm/i915/pxp/intel_pxp_session.c

177

intel_pxp_terminate(pxp, true);

sys/dev/pci/drm/i915/pxp/intel_pxp_session.c

75

ret = pxp_wait_for_session_state(pxp, ARB_SESSION, true);

sys/dev/pci/drm/i915/pxp/intel_pxp_session.c

85

pxp->arb_is_valid = true;

sys/dev/pci/drm/i915/pxp/intel_pxp_tee.c

265

obj, true));

sys/dev/pci/drm/i915/pxp/intel_pxp_tee.c

315

pxp->pxp_component_added = true;

sys/dev/pci/drm/i915/pxp/intel_pxp_tee.c

33

pxp->platform_cfg_is_bad = true;

sys/dev/pci/drm/i915/pxp/intel_pxp_tee.c

34

return true;

sys/dev/pci/drm/i915/selftests/i915_active.c

59

active->retired = true;

sys/dev/pci/drm/i915/selftests/i915_gem.c

227

i915_gem_ww_ctx_init(&ww, true);

sys/dev/pci/drm/i915/selftests/i915_gem_evict.c

464

igt_evict_ctl.fail_if_busy = true;

sys/dev/pci/drm/i915/selftests/i915_request.c

1534

return true;

sys/dev/pci/drm/i915/selftests/i915_request.c

1839

WRITE_ONCE(threads[i].stop, true);

sys/dev/pci/drm/i915/selftests/i915_request.c

2565

smp_store_mb(s->seen, true); /* be safe, be strong */

sys/dev/pci/drm/i915/selftests/i915_request.c

2989

busy = true;

sys/dev/pci/drm/i915/selftests/i915_request.c

3064

busy = true;

sys/dev/pci/drm/i915/selftests/i915_request.c

3140

busy = true;

sys/dev/pci/drm/i915/selftests/i915_request.c

516

WRITE_ONCE(threads[n].stop, true);

sys/dev/pci/drm/i915/selftests/i915_selftest.c

131

st[i].enabled = true;

sys/dev/pci/drm/i915/selftests/i915_selftest.c

324

bool result = true;

sys/dev/pci/drm/i915/selftests/i915_selftest.c

328

bool allow = true;

sys/dev/pci/drm/i915/selftests/i915_selftest.c

474

return true;

sys/dev/pci/drm/i915/selftests/i915_selftest.c

490

skip = true;

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

98

return true;

sys/dev/pci/drm/i915/selftests/i915_vma.c

1014

err = i915_gem_object_set_to_gtt_domain(obj, true);

sys/dev/pci/drm/i915/selftests/i915_vma.c

238

return true;

sys/dev/pci/drm/i915/selftests/i915_vma.c

41

bool ok = true;

sys/dev/pci/drm/i915/selftests/i915_vma.c

69

bool ok = true;

sys/dev/pci/drm/i915/selftests/i915_vma.c

744

return true;

sys/dev/pci/drm/i915/selftests/i915_vma.c

752

bool ok = true;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1068

true, 0xdeadbeaf, &rq);

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1077

err = i915_gem_object_set_to_wc_domain(obj, true);

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

153

return true;

sys/dev/pci/drm/i915/selftests/intel_uncore.c

118

{ __gen9_fw_ranges, ARRAY_SIZE(__gen9_fw_ranges), true },

sys/dev/pci/drm/i915/selftests/intel_uncore.c

119

{ __gen11_fw_ranges, ARRAY_SIZE(__gen11_fw_ranges), true },

sys/dev/pci/drm/i915/selftests/intel_uncore.c

120

{ __gen12_fw_ranges, ARRAY_SIZE(__gen12_fw_ranges), true },

sys/dev/pci/drm/i915/selftests/intel_uncore.c

121

{ __mtl_fw_ranges, ARRAY_SIZE(__mtl_fw_ranges), true },

sys/dev/pci/drm/i915/selftests/intel_uncore.c

122

{ __xelpmp_fw_ranges, ARRAY_SIZE(__xelpmp_fw_ranges), true },

sys/dev/pci/drm/i915/selftests/mock_gem_device.c

200

i915->runtime_pm.no_wakeref_tracking = true;

sys/dev/pci/drm/i915/selftests/mock_gem_device.c

250

i915->do_release = true;

sys/dev/pci/drm/i915/selftests/mock_gtt.c

113

ggtt->vm.is_ggtt = true;

sys/dev/pci/drm/i915/soc/intel_dram.c

410

dram_info->has_16gb_dimms = true;

sys/dev/pci/drm/i915/soc/intel_gmch.c

139

i915->gmch.mchbar_need_disable = true;

sys/dev/pci/drm/i915/vlv_iosf_sb.c

205

opcode = unit_to_opcode(unit, true);

sys/dev/pci/drm/i915/vlv_suspend.c

300

trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);

sys/dev/pci/drm/i915/vlv_suspend.c

403

err = vlv_force_gfx_clock(dev_priv, true);

sys/dev/pci/drm/i915/vlv_suspend.c

421

vlv_allow_gt_wake(dev_priv, true);

sys/dev/pci/drm/i915/vlv_suspend.c

441

ret = vlv_force_gfx_clock(dev_priv, true);

sys/dev/pci/drm/i915/vlv_suspend.c

445

err = vlv_allow_gt_wake(dev_priv, true);

sys/dev/pci/drm/include/acpi/video.h

26

return true;

sys/dev/pci/drm/include/asm/cpufeature.h

24

return true;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

1019

return true;

sys/dev/pci/drm/include/drm/drm_cache.h

79

return true;

sys/dev/pci/drm/include/drm/drm_drv.h

528

return true;

sys/dev/pci/drm/include/drm/drm_format_helper.h

61

__DRM_FORMAT_CONV_STATE_INIT(_mem, _size, true)

sys/dev/pci/drm/include/drm/drm_lease.h

8

#define drm_lease_held(f, id) (true)

sys/dev/pci/drm/include/drm/drm_modes.h

482

return drm_analog_tv_mode(dev, DRM_MODE_TV_MODE_NTSC, 13500000, 720, 480, true);

sys/dev/pci/drm/include/drm/drm_modes.h

487

return drm_analog_tv_mode(dev, DRM_MODE_TV_MODE_PAL, 13500000, 720, 576, true);

sys/dev/pci/drm/include/drm/drm_panic.h

174

return true;

sys/dev/pci/drm/include/drm/drm_print.h

161

#define __drm_debug_enabled(category) true

sys/dev/pci/drm/include/drm/drm_print.h

362

return true;

sys/dev/pci/drm/include/drm/drm_print.h

556

__print_once = true; \

sys/dev/pci/drm/include/drm/drm_util.h

66

return true;

sys/dev/pci/drm/include/linux/bitmap.h

109

return true;

sys/dev/pci/drm/include/linux/bitmap.h

112

return true;

sys/dev/pci/drm/include/linux/cgroup_dmem.h

23

return true;

sys/dev/pci/drm/include/linux/completion.h

162

return true;

sys/dev/pci/drm/include/linux/dma-fence.h

128

return true;

sys/dev/pci/drm/include/linux/dma-fence.h

141

return true;

sys/dev/pci/drm/include/linux/hashtable.h

45

return true;

sys/dev/pci/drm/include/linux/interrupt.h

92

ts->use_callback = true;

sys/dev/pci/drm/include/linux/iosys-map.h

80

ism->is_iomem = true;

sys/dev/pci/drm/include/linux/module.h

25

return true;

sys/dev/pci/drm/include/linux/pci.h

558

return true;

sys/dev/pci/drm/include/linux/pci.h

570

return true;

sys/dev/pci/drm/include/linux/refcount.h

38

return true;

sys/dev/pci/drm/include/linux/scatterlist.h

65

sgl->end = true;

sys/dev/pci/drm/include/linux/suspend.h

38

return true;

sys/dev/pci/drm/include/linux/workqueue.h

197

return true;

sys/dev/pci/drm/include/linux/workqueue.h

207

return true;

sys/dev/pci/drm/include/linux/workqueue.h

215

return true;

sys/dev/pci/drm/include/linux/ww_mutex.h

215

(void)__ww_mutex_lock(lock, ctx, true, false);

sys/dev/pci/drm/include/linux/ww_mutex.h

220

return __ww_mutex_lock(lock, ctx, false, true);

sys/dev/pci/drm/include/linux/ww_mutex.h

225

return __ww_mutex_lock(lock, ctx, true, true);

sys/dev/pci/drm/include/linux/ww_mutex.h

99

if (lock->acquired > 0) res = true;

sys/dev/pci/drm/linux_radix.c

111

return (true);

sys/dev/pci/drm/radeon/atom.c

1398

return true;

sys/dev/pci/drm/radeon/atom.c

1415

return true;

sys/dev/pci/drm/radeon/atom.c

647

ctx->abort = true;

sys/dev/pci/drm/radeon/atom.c

750

ctx->abort = true;

sys/dev/pci/drm/radeon/atombios_crtc.c

102

is_tv = true;

sys/dev/pci/drm/radeon/atombios_crtc.c

1050

return true;

sys/dev/pci/drm/radeon/atombios_crtc.c

1237

bypass_lut = true;

sys/dev/pci/drm/radeon/atombios_crtc.c

1247

bypass_lut = true;

sys/dev/pci/drm/radeon/atombios_crtc.c

1553

bypass_lut = true;

sys/dev/pci/drm/radeon/atombios_crtc.c

2054

is_tvcv = true;

sys/dev/pci/drm/radeon/atombios_crtc.c

2122

return true;

sys/dev/pci/drm/radeon/atombios_crtc.c

275

radeon_crtc->enabled = true;

sys/dev/pci/drm/radeon/atombios_dp.c

105

radeon_atom_copy_swap(base, send, send_bytes, true);

sys/dev/pci/drm/radeon/atombios_dp.c

244

radeon_connector->ddc_bus->has_aux = true;

sys/dev/pci/drm/radeon/atombios_dp.c

398

return true;

sys/dev/pci/drm/radeon/atombios_dp.c

509

return true;

sys/dev/pci/drm/radeon/atombios_dp.c

687

clock_recovery = true;

sys/dev/pci/drm/radeon/atombios_dp.c

750

channel_eq = true;

sys/dev/pci/drm/radeon/atombios_dp.c

809

dp_info.use_dpencoder = true;

sys/dev/pci/drm/radeon/atombios_dp.c

829

dp_info.tp3_supported = true;

sys/dev/pci/drm/radeon/atombios_encoders.c

1052

is_dp = true;

sys/dev/pci/drm/radeon/atombios_encoders.c

1408

return true;

sys/dev/pci/drm/radeon/atombios_encoders.c

1414

return true;

sys/dev/pci/drm/radeon/atombios_encoders.c

1669

travis_quirk = true;

sys/dev/pci/drm/radeon/atombios_encoders.c

1702

radeon_dig_connector->edp_on = true;

sys/dev/pci/drm/radeon/atombios_encoders.c

2224

atombios_yuv_setup(encoder, true);

sys/dev/pci/drm/radeon/atombios_encoders.c

2315

return true;

sys/dev/pci/drm/radeon/atombios_encoders.c

2445

radeon_atom_output_lock(encoder, true);

sys/dev/pci/drm/radeon/atombios_encoders.c

2646

dig->coherent_mode = true;

sys/dev/pci/drm/radeon/atombios_encoders.c

2650

dig->linkb = true;

sys/dev/pci/drm/radeon/atombios_encoders.c

2774

radeon_encoder->is_ext_encoder = true;

sys/dev/pci/drm/radeon/atombios_encoders.c

341

return true;

sys/dev/pci/drm/radeon/btc_dpm.c

1592

return true;

sys/dev/pci/drm/radeon/btc_dpm.c

1693

eg_pi->uvd_enabled = true;

sys/dev/pci/drm/radeon/btc_dpm.c

1776

return true;

sys/dev/pci/drm/radeon/btc_dpm.c

1827

bool result = true;

sys/dev/pci/drm/radeon/btc_dpm.c

2059

return true;

sys/dev/pci/drm/radeon/btc_dpm.c

2076

disable_mclk_switching = true;

sys/dev/pci/drm/radeon/btc_dpm.c

2216

ps->dc_compatible = true;

sys/dev/pci/drm/radeon/btc_dpm.c

2366

rv770_enable_voltage_control(rdev, true);

sys/dev/pci/drm/radeon/btc_dpm.c

2389

rv770_enable_backbias(rdev, true);

sys/dev/pci/drm/radeon/btc_dpm.c

2392

cypress_enable_spread_spectrum(rdev, true);

sys/dev/pci/drm/radeon/btc_dpm.c

2395

rv770_enable_thermal_protection(rdev, true);

sys/dev/pci/drm/radeon/btc_dpm.c

2407

btc_enable_dynamic_pcie_gen2(rdev, true);

sys/dev/pci/drm/radeon/btc_dpm.c

2438

cypress_enable_sclk_control(rdev, true);

sys/dev/pci/drm/radeon/btc_dpm.c

2441

cypress_enable_mclk_control(rdev, true);

sys/dev/pci/drm/radeon/btc_dpm.c

2446

btc_cg_clock_gating_enable(rdev, true);

sys/dev/pci/drm/radeon/btc_dpm.c

2449

btc_mg_clock_gating_enable(rdev, true);

sys/dev/pci/drm/radeon/btc_dpm.c

2452

btc_ls_clock_gating_enable(rdev, true);

sys/dev/pci/drm/radeon/btc_dpm.c

2454

rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);

sys/dev/pci/drm/radeon/btc_dpm.c

2603

eg_pi->smu_uvd_hs = true;

sys/dev/pci/drm/radeon/btc_dpm.c

2622

pi->gfx_clock_gating = true;

sys/dev/pci/drm/radeon/btc_dpm.c

2624

pi->mg_clock_gating = true;

sys/dev/pci/drm/radeon/btc_dpm.c

2625

pi->mgcgtssm = true;

sys/dev/pci/drm/radeon/btc_dpm.c

2629

pi->dynamic_pcie_gen2 = true;

sys/dev/pci/drm/radeon/btc_dpm.c

2632

pi->thermal_protection = true;

sys/dev/pci/drm/radeon/btc_dpm.c

2636

pi->display_gap = true;

sys/dev/pci/drm/radeon/btc_dpm.c

2639

pi->dcodt = true;

sys/dev/pci/drm/radeon/btc_dpm.c

2643

pi->ulps = true;

sys/dev/pci/drm/radeon/btc_dpm.c

2645

eg_pi->dynamic_ac_timing = true;

sys/dev/pci/drm/radeon/btc_dpm.c

2646

eg_pi->abm = true;

sys/dev/pci/drm/radeon/btc_dpm.c

2647

eg_pi->mcls = true;

sys/dev/pci/drm/radeon/btc_dpm.c

2648

eg_pi->light_sleep = true;

sys/dev/pci/drm/radeon/btc_dpm.c

2649

eg_pi->memory_transition = true;

sys/dev/pci/drm/radeon/btc_dpm.c

2658

eg_pi->dll_default_on = true;

sys/dev/pci/drm/radeon/ci_dpm.c

1028

pi->fan_is_controlled_by_smc = true;

sys/dev/pci/drm/radeon/ci_dpm.c

1196

pi->fan_ctrl_is_in_default_mode = true;

sys/dev/pci/drm/radeon/ci_dpm.c

1231

ret = ci_thermal_enable_alert(rdev, true);

sys/dev/pci/drm/radeon/ci_dpm.c

1362

want_thermal_protection = true;

sys/dev/pci/drm/radeon/ci_dpm.c

1365

want_thermal_protection = true;

sys/dev/pci/drm/radeon/ci_dpm.c

1369

want_thermal_protection = true;

sys/dev/pci/drm/radeon/ci_dpm.c

1507

ret = ci_enable_sclk_mclk_dpm(rdev, true);

sys/dev/pci/drm/radeon/ci_dpm.c

223

pi->caps_power_containment = true;

sys/dev/pci/drm/radeon/ci_dpm.c

2300

voltage_found = true;

sys/dev/pci/drm/radeon/ci_dpm.c

231

pi->caps_cac = true;

sys/dev/pci/drm/radeon/ci_dpm.c

2317

voltage_found = true;

sys/dev/pci/drm/radeon/ci_dpm.c

235

pi->enable_bapm_feature = true;

sys/dev/pci/drm/radeon/ci_dpm.c

236

pi->enable_tdc_limit_feature = true;

sys/dev/pci/drm/radeon/ci_dpm.c

237

pi->enable_pkg_pwr_tracking_feature = true;

sys/dev/pci/drm/radeon/ci_dpm.c

2890

memory_level->StutterEnable = true;

sys/dev/pci/drm/radeon/ci_dpm.c

2901

memory_level->EdcReadEnable = true;

sys/dev/pci/drm/radeon/ci_dpm.c

2905

memory_level->EdcWriteEnable = true;

sys/dev/pci/drm/radeon/ci_dpm.c

2908

if (si_get_mclk_frequency_ratio(memory_clock, true) >=

sys/dev/pci/drm/radeon/ci_dpm.c

2910

dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;

sys/dev/pci/drm/radeon/ci_dpm.c

2912

dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;

sys/dev/pci/drm/radeon/ci_dpm.c

2918

dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;

sys/dev/pci/drm/radeon/ci_dpm.c

3348

dpm_table->dpm_levels[index].enabled = true;

sys/dev/pci/drm/radeon/ci_dpm.c

3464

pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;

sys/dev/pci/drm/radeon/ci_dpm.c

3472

pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;

sys/dev/pci/drm/radeon/ci_dpm.c

3480

pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;

sys/dev/pci/drm/radeon/ci_dpm.c

3664

dpm_table->dpm_levels[i].enabled = true;

sys/dev/pci/drm/radeon/ci_dpm.c

3683

pcie_table->dpm_levels[i].enabled = true;

sys/dev/pci/drm/radeon/ci_dpm.c

3909

pi->uvd_enabled = true;

sys/dev/pci/drm/radeon/ci_dpm.c

4083

ret = ci_enable_vce_dpm(rdev, true);

sys/dev/pci/drm/radeon/ci_dpm.c

4086

cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true);

sys/dev/pci/drm/radeon/ci_dpm.c

4359

bool result = true;

sys/dev/pci/drm/radeon/ci_dpm.c

4836

pi->pspp_notify_required = true;

sys/dev/pci/drm/radeon/ci_dpm.c

5046

pi->mem_gddr5 = true;

sys/dev/pci/drm/radeon/ci_dpm.c

5131

ci_enable_spread_spectrum(rdev, true);

sys/dev/pci/drm/radeon/ci_dpm.c

5133

ci_enable_thermal_protection(rdev, true);

sys/dev/pci/drm/radeon/ci_dpm.c

5181

ci_enable_sclk_control(rdev, true);

sys/dev/pci/drm/radeon/ci_dpm.c

5182

ret = ci_enable_ulv(rdev, true);

sys/dev/pci/drm/radeon/ci_dpm.c

5187

ret = ci_enable_ds_master_switch(rdev, true);

sys/dev/pci/drm/radeon/ci_dpm.c

5197

ret = ci_enable_didt(rdev, true);

sys/dev/pci/drm/radeon/ci_dpm.c

5202

ret = ci_enable_smc_cac(rdev, true);

sys/dev/pci/drm/radeon/ci_dpm.c

5207

ret = ci_enable_power_containment(rdev, true);

sys/dev/pci/drm/radeon/ci_dpm.c

5219

ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);

sys/dev/pci/drm/radeon/ci_dpm.c

5221

ret = ci_enable_thermal_based_sclk_dpm(rdev, true);

sys/dev/pci/drm/radeon/ci_dpm.c

5244

ret = ci_thermal_enable_alert(rdev, true);

sys/dev/pci/drm/radeon/ci_dpm.c

5259

ci_dpm_powergate_uvd(rdev, true);

sys/dev/pci/drm/radeon/ci_dpm.c

5446

pi->ulv.supported = true;

sys/dev/pci/drm/radeon/ci_dpm.c

5461

pi->use_pcie_powersaving_levels = true;

sys/dev/pci/drm/radeon/ci_dpm.c

5472

pi->use_pcie_performance_levels = true;

sys/dev/pci/drm/radeon/ci_dpm.c

5723

pi->caps_sclk_ds = true;

sys/dev/pci/drm/radeon/ci_dpm.c

5736

pi->caps_uvd_dpm = true;

sys/dev/pci/drm/radeon/ci_dpm.c

5737

pi->caps_vce_dpm = true;

sys/dev/pci/drm/radeon/ci_dpm.c

5857

pi->vddc_phase_shed_control = true;

sys/dev/pci/drm/radeon/ci_dpm.c

5868

pi->caps_sclk_ss_support = true;

sys/dev/pci/drm/radeon/ci_dpm.c

5869

pi->caps_mclk_ss_support = true;

sys/dev/pci/drm/radeon/ci_dpm.c

5870

pi->dynamic_ss = true;

sys/dev/pci/drm/radeon/ci_dpm.c

5874

pi->dynamic_ss = true;

sys/dev/pci/drm/radeon/ci_dpm.c

5878

pi->thermal_protection = true;

sys/dev/pci/drm/radeon/ci_dpm.c

5882

pi->caps_dynamic_ac_timing = true;

sys/dev/pci/drm/radeon/ci_dpm.c

5892

pi->fan_ctrl_is_in_default_mode = true;

sys/dev/pci/drm/radeon/ci_dpm.c

682

pi->cac_enabled = true;

sys/dev/pci/drm/radeon/ci_dpm.c

756

return true;

sys/dev/pci/drm/radeon/ci_dpm.c

759

return true;

sys/dev/pci/drm/radeon/ci_dpm.c

785

disable_mclk_switching = true;

sys/dev/pci/drm/radeon/ci_dpm.c

790

pi->battery_state = true;

sys/dev/pci/drm/radeon/ci_dpm.c

894

rdev->irq.dpm_thermal = true;

sys/dev/pci/drm/radeon/ci_smc.c

161

return true;

sys/dev/pci/drm/radeon/cik.c

1987

new_smc = true;

sys/dev/pci/drm/radeon/cik.c

2003

new_smc = true;

sys/dev/pci/drm/radeon/cik.c

2276

rdev->new_fw = true;

sys/dev/pci/drm/radeon/cik.c

3429

rdev->scratch.free[i] = true;

sys/dev/pci/drm/radeon/cik.c

3629

return true;

sys/dev/pci/drm/radeon/cik.c

3981

cik_cp_gfx_enable(rdev, true);

sys/dev/pci/drm/radeon/cik.c

4100

rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;

sys/dev/pci/drm/radeon/cik.c

4319

cik_cp_compute_enable(rdev, true);

sys/dev/pci/drm/radeon/cik.c

4395

PAGE_SIZE, true,

sys/dev/pci/drm/radeon/cik.c

4512

bool use_doorbell = true;

sys/dev/pci/drm/radeon/cik.c

4566

PAGE_SIZE, true,

sys/dev/pci/drm/radeon/cik.c

4736

rdev->ring[idx].ready = true;

sys/dev/pci/drm/radeon/cik.c

4788

cik_enable_gui_idle_interrupt(rdev, true);

sys/dev/pci/drm/radeon/cik.c

5221

r600_set_bios_scratch_engine_hung(rdev, true);

sys/dev/pci/drm/radeon/cik.c

5334

rdev->mc.vram_is_ddr = true;

sys/dev/pci/drm/radeon/cik.c

5525

rdev->gart.ready = true;

sys/dev/pci/drm/radeon/cik.c

5895

cik_enable_gui_idle_interrupt(rdev, true);

sys/dev/pci/drm/radeon/cik.c

5997

cik_enable_gui_idle_interrupt(rdev, true);

sys/dev/pci/drm/radeon/cik.c

6286

cik_enable_mgcg(rdev, true);

sys/dev/pci/drm/radeon/cik.c

6287

cik_enable_cgcg(rdev, true);

sys/dev/pci/drm/radeon/cik.c

6292

cik_enable_gui_idle_interrupt(rdev, true);

sys/dev/pci/drm/radeon/cik.c

6329

cik_update_cg(rdev, RADEON_CG_BLOCK_GFX, true);

sys/dev/pci/drm/radeon/cik.c

6338

RADEON_CG_BLOCK_HDP), true);

sys/dev/pci/drm/radeon/cik.c

6767

cik_enable_sck_slowdown_on_pu(rdev, true);

sys/dev/pci/drm/radeon/cik.c

6768

cik_enable_sck_slowdown_on_pd(rdev, true);

sys/dev/pci/drm/radeon/cik.c

6771

cik_enable_cp_pg(rdev, true);

sys/dev/pci/drm/radeon/cik.c

6772

cik_enable_gds_pg(rdev, true);

sys/dev/pci/drm/radeon/cik.c

6775

cik_update_gfx_pg(rdev, true);

sys/dev/pci/drm/radeon/cik.c

6821

rdev->ih.enabled = true;

sys/dev/pci/drm/radeon/cik.c

7591

rdev->pm.vblank_sync = true;

sys/dev/pci/drm/radeon/cik.c

7621

rdev->pm.vblank_sync = true;

sys/dev/pci/drm/radeon/cik.c

7651

rdev->pm.vblank_sync = true;

sys/dev/pci/drm/radeon/cik.c

7681

rdev->pm.vblank_sync = true;

sys/dev/pci/drm/radeon/cik.c

7711

rdev->pm.vblank_sync = true;

sys/dev/pci/drm/radeon/cik.c

7741

rdev->pm.vblank_sync = true;

sys/dev/pci/drm/radeon/cik.c

7780

queue_hotplug = true;

sys/dev/pci/drm/radeon/cik.c

7789

queue_hotplug = true;

sys/dev/pci/drm/radeon/cik.c

7798

queue_hotplug = true;

sys/dev/pci/drm/radeon/cik.c

7807

queue_hotplug = true;

sys/dev/pci/drm/radeon/cik.c

7816

queue_hotplug = true;

sys/dev/pci/drm/radeon/cik.c

7825

queue_hotplug = true;

sys/dev/pci/drm/radeon/cik.c

7834

queue_dp = true;

sys/dev/pci/drm/radeon/cik.c

7843

queue_dp = true;

sys/dev/pci/drm/radeon/cik.c

7852

queue_dp = true;

sys/dev/pci/drm/radeon/cik.c

7861

queue_dp = true;

sys/dev/pci/drm/radeon/cik.c

7870

queue_dp = true;

sys/dev/pci/drm/radeon/cik.c

7879

queue_dp = true;

sys/dev/pci/drm/radeon/cik.c

7958

queue_reset = true;

sys/dev/pci/drm/radeon/cik.c

7962

queue_reset = true;

sys/dev/pci/drm/radeon/cik.c

7966

queue_reset = true;

sys/dev/pci/drm/radeon/cik.c

7979

queue_reset = true;

sys/dev/pci/drm/radeon/cik.c

7983

queue_reset = true;

sys/dev/pci/drm/radeon/cik.c

7987

queue_reset = true;

sys/dev/pci/drm/radeon/cik.c

8028

queue_thermal = true;

sys/dev/pci/drm/radeon/cik.c

8032

rdev->pm.dpm.thermal.high_to_low = true;

sys/dev/pci/drm/radeon/cik.c

8033

queue_thermal = true;

sys/dev/pci/drm/radeon/cik.c

8048

queue_reset = true;

sys/dev/pci/drm/radeon/cik.c

8052

queue_reset = true;

sys/dev/pci/drm/radeon/cik.c

8056

queue_reset = true;

sys/dev/pci/drm/radeon/cik.c

8063

queue_reset = true;

sys/dev/pci/drm/radeon/cik.c

8067

queue_reset = true;

sys/dev/pci/drm/radeon/cik.c

8071

queue_reset = true;

sys/dev/pci/drm/radeon/cik.c

8092

rdev->needs_reset = true;

sys/dev/pci/drm/radeon/cik.c

8493

rdev->accel_working = true;

sys/dev/pci/drm/radeon/cik.c

8663

rdev->accel_working = true;

sys/dev/pci/drm/radeon/cik.c

9178

return true;

sys/dev/pci/drm/radeon/cik.c

9198

return true;

sys/dev/pci/drm/radeon/cik.c

9233

return true;

sys/dev/pci/drm/radeon/cik.c

9285

wm_high.interlaced = true;

sys/dev/pci/drm/radeon/cik.c

9311

radeon_dpm_get_mclk(rdev, true) * 10;

sys/dev/pci/drm/radeon/cik.c

9313

radeon_dpm_get_sclk(rdev, true) * 10;

sys/dev/pci/drm/radeon/cik.c

9325

wm_low.interlaced = true;

sys/dev/pci/drm/radeon/cik.c

9747

clk_req_support = true;

sys/dev/pci/drm/radeon/cik_sdma.c

239

return true;

sys/dev/pci/drm/radeon/cik_sdma.c

423

ring->ready = true;

sys/dev/pci/drm/radeon/cik_sdma.c

536

cik_sdma_enable(rdev, true);

sys/dev/pci/drm/radeon/cypress_dpm.c

1820

rv770_enable_voltage_control(rdev, true);

sys/dev/pci/drm/radeon/cypress_dpm.c

1846

rv770_enable_backbias(rdev, true);

sys/dev/pci/drm/radeon/cypress_dpm.c

1849

cypress_enable_spread_spectrum(rdev, true);

sys/dev/pci/drm/radeon/cypress_dpm.c

1852

rv770_enable_thermal_protection(rdev, true);

sys/dev/pci/drm/radeon/cypress_dpm.c

1864

cypress_enable_dynamic_pcie_gen2(rdev, true);

sys/dev/pci/drm/radeon/cypress_dpm.c

1899

cypress_enable_sclk_control(rdev, true);

sys/dev/pci/drm/radeon/cypress_dpm.c

1902

cypress_enable_mclk_control(rdev, true);

sys/dev/pci/drm/radeon/cypress_dpm.c

1907

cypress_gfx_clock_gating_enable(rdev, true);

sys/dev/pci/drm/radeon/cypress_dpm.c

1910

cypress_mg_clock_gating_enable(rdev, true);

sys/dev/pci/drm/radeon/cypress_dpm.c

1912

rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);

sys/dev/pci/drm/radeon/cypress_dpm.c

2095

pi->gfx_clock_gating = true;

sys/dev/pci/drm/radeon/cypress_dpm.c

2097

pi->mg_clock_gating = true;

sys/dev/pci/drm/radeon/cypress_dpm.c

2098

pi->mgcgtssm = true;

sys/dev/pci/drm/radeon/cypress_dpm.c

2102

pi->dynamic_pcie_gen2 = true;

sys/dev/pci/drm/radeon/cypress_dpm.c

2105

pi->thermal_protection = true;

sys/dev/pci/drm/radeon/cypress_dpm.c

2109

pi->display_gap = true;

sys/dev/pci/drm/radeon/cypress_dpm.c

2112

pi->dcodt = true;

sys/dev/pci/drm/radeon/cypress_dpm.c

2116

pi->ulps = true;

sys/dev/pci/drm/radeon/cypress_dpm.c

2118

eg_pi->dynamic_ac_timing = true;

sys/dev/pci/drm/radeon/cypress_dpm.c

2119

eg_pi->abm = true;

sys/dev/pci/drm/radeon/cypress_dpm.c

2120

eg_pi->mcls = true;

sys/dev/pci/drm/radeon/cypress_dpm.c

2121

eg_pi->light_sleep = true;

sys/dev/pci/drm/radeon/cypress_dpm.c

2122

eg_pi->memory_transition = true;

sys/dev/pci/drm/radeon/cypress_dpm.c

2133

eg_pi->dll_default_on = true;

sys/dev/pci/drm/radeon/cypress_dpm.c

2164

return true;

sys/dev/pci/drm/radeon/cypress_dpm.c

315

eg_pi->pcie_performance_request_registered = true;

sys/dev/pci/drm/radeon/cypress_dpm.c

340

pi->pcie_gen2 = true;

sys/dev/pci/drm/radeon/cypress_dpm.c

345

cypress_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, true);

sys/dev/pci/drm/radeon/cypress_dpm.c

430

strobe_mode = true;

sys/dev/pci/drm/radeon/cypress_dpm.c

719

if (cypress_get_mclk_frequency_ratio(rdev, pl->mclk, true) >=

sys/dev/pci/drm/radeon/cypress_dpm.c

721

dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;

sys/dev/pci/drm/radeon/cypress_dpm.c

723

dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;

sys/dev/pci/drm/radeon/cypress_dpm.c

738

true,

sys/dev/pci/drm/radeon/cypress_dpm.c

739

true);

sys/dev/pci/drm/radeon/dce6_afmt.c

75

rdev->audio.pin[i].connected = true;

sys/dev/pci/drm/radeon/evergreen.c

1351

return true;

sys/dev/pci/drm/radeon/evergreen.c

1364

return true;

sys/dev/pci/drm/radeon/evergreen.c

2115

return true;

sys/dev/pci/drm/radeon/evergreen.c

2124

return true;

sys/dev/pci/drm/radeon/evergreen.c

2150

return true;

sys/dev/pci/drm/radeon/evergreen.c

2199

wm_high.interlaced = true;

sys/dev/pci/drm/radeon/evergreen.c

2212

radeon_dpm_get_mclk(rdev, true) * 10;

sys/dev/pci/drm/radeon/evergreen.c

2214

radeon_dpm_get_sclk(rdev, true) * 10;

sys/dev/pci/drm/radeon/evergreen.c

2226

wm_low.interlaced = true;

sys/dev/pci/drm/radeon/evergreen.c

2454

rdev->gart.ready = true;

sys/dev/pci/drm/radeon/evergreen.c

2583

found_crtc = true;

sys/dev/pci/drm/radeon/evergreen.c

2608

is_enabled = true;

sys/dev/pci/drm/radeon/evergreen.c

2680

save->crtc_enabled[i] = true;

sys/dev/pci/drm/radeon/evergreen.c

3120

ring->ready = true;

sys/dev/pci/drm/radeon/evergreen.c

3715

rdev->mc.vram_is_ddr = true;

sys/dev/pci/drm/radeon/evergreen.c

3822

return true;

sys/dev/pci/drm/radeon/evergreen.c

4062

r600_set_bios_scratch_engine_hung(rdev, true);

sys/dev/pci/drm/radeon/evergreen.c

4172

r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,

sys/dev/pci/drm/radeon/evergreen.c

4251

r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,

sys/dev/pci/drm/radeon/evergreen.c

4328

PAGE_SIZE, true,

sys/dev/pci/drm/radeon/evergreen.c

4759

rdev->pm.vblank_sync = true;

sys/dev/pci/drm/radeon/evergreen.c

4799

queue_hotplug = true;

sys/dev/pci/drm/radeon/evergreen.c

4805

queue_dp = true;

sys/dev/pci/drm/radeon/evergreen.c

4833

queue_hdmi = true;

sys/dev/pci/drm/radeon/evergreen.c

4889

queue_thermal = true;

sys/dev/pci/drm/radeon/evergreen.c

4893

rdev->pm.dpm.thermal.high_to_low = true;

sys/dev/pci/drm/radeon/evergreen.c

4894

queue_thermal = true;

sys/dev/pci/drm/radeon/evergreen.c

5143

rdev->accel_working = true;

sys/dev/pci/drm/radeon/evergreen.c

5270

rdev->accel_working = true;

sys/dev/pci/drm/radeon/evergreen.c

5418

disable_l0s = true;

sys/dev/pci/drm/radeon/evergreen.c

5426

fusion_platform = true; /* XXX also dGPUs in a fusion system */

sys/dev/pci/drm/radeon/evergreen_cs.c

1154

track->db_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1196

track->db_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1200

track->db_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1204

track->db_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1208

track->db_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1212

track->db_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1224

track->db_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1236

track->db_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1248

track->db_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1260

track->db_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1264

track->streamout_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1268

track->streamout_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1284

track->streamout_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1293

track->streamout_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1306

track->cb_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1310

track->cb_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1340

track->cb_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1348

track->cb_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1370

track->cb_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1388

track->cb_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1400

track->cb_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1408

track->cb_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

141

track->cb_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1421

track->cb_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1430

track->cb_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1462

track->cb_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1490

track->cb_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1566

track->cb_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

157

track->db_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1582

track->cb_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1594

track->db_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1601

track->db_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

167

track->streamout_dirty = true;

sys/dev/pci/drm/radeon/evergreen_cs.c

1768

return true;

sys/dev/pci/drm/radeon/evergreen_cs.c

3321

return true;

sys/dev/pci/drm/radeon/evergreen_cs.c

3432

return true;

sys/dev/pci/drm/radeon/kv_dpm.c

1095

ret = kv_enable_ulv(rdev, true);

sys/dev/pci/drm/radeon/kv_dpm.c

1101

ret = kv_enable_didt(rdev, true);

sys/dev/pci/drm/radeon/kv_dpm.c

1106

ret = kv_enable_smc_cac(rdev, true);

sys/dev/pci/drm/radeon/kv_dpm.c

1136

kv_enable_thermal_int(rdev, true);

sys/dev/pci/drm/radeon/kv_dpm.c

1140

kv_dpm_powergate_acp(rdev, true);

sys/dev/pci/drm/radeon/kv_dpm.c

1141

kv_dpm_powergate_samu(rdev, true);

sys/dev/pci/drm/radeon/kv_dpm.c

1142

kv_dpm_powergate_vce(rdev, true);

sys/dev/pci/drm/radeon/kv_dpm.c

1143

kv_dpm_powergate_uvd(rdev, true);

sys/dev/pci/drm/radeon/kv_dpm.c

1325

kv_enable_vce_dpm(rdev, true);

sys/dev/pci/drm/radeon/kv_dpm.c

1329

cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true);

sys/dev/pci/drm/radeon/kv_dpm.c

1330

kv_dpm_powergate_vce(rdev, true);

sys/dev/pci/drm/radeon/kv_dpm.c

1453

cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, true);

sys/dev/pci/drm/radeon/kv_dpm.c

1492

kv_update_samu_dpm(rdev, true);

sys/dev/pci/drm/radeon/kv_dpm.c

1515

kv_update_acp_dpm(rdev, true);

sys/dev/pci/drm/radeon/kv_dpm.c

1620

pi->nb_dpm_enabled = true;

sys/dev/pci/drm/radeon/kv_dpm.c

1714

kv_enable_nb_dpm(rdev, true);

sys/dev/pci/drm/radeon/kv_dpm.c

1727

kv_freeze_sclk_dpm(rdev, true);

sys/dev/pci/drm/radeon/kv_dpm.c

1739

kv_enable_nb_dpm(rdev, true);

sys/dev/pci/drm/radeon/kv_dpm.c

1756

sumo_take_smu_control(rdev, true);

sys/dev/pci/drm/radeon/kv_dpm.c

1982

ps->need_dfs_bypass = true;

sys/dev/pci/drm/radeon/kv_dpm.c

2023

pi->battery_state = true;

sys/dev/pci/drm/radeon/kv_dpm.c

2167

kv_dpm_power_level_enabled_for_throttle(rdev, i, true);

sys/dev/pci/drm/radeon/kv_dpm.c

2184

kv_dpm_power_level_enabled_for_throttle(rdev, i, true);

sys/dev/pci/drm/radeon/kv_dpm.c

2200

kv_dpm_power_level_enable(rdev, i, true);

sys/dev/pci/drm/radeon/kv_dpm.c

2321

pi->sys_info.nb_dpm_enable = true;

sys/dev/pci/drm/radeon/kv_dpm.c

2333

pi->caps_enable_dfs_bypass = true;

sys/dev/pci/drm/radeon/kv_dpm.c

2545

pi->enable_nb_dpm = true;

sys/dev/pci/drm/radeon/kv_dpm.c

2547

pi->caps_power_containment = true;

sys/dev/pci/drm/radeon/kv_dpm.c

2548

pi->caps_cac = true;

sys/dev/pci/drm/radeon/kv_dpm.c

2551

pi->caps_sq_ramping = true;

sys/dev/pci/drm/radeon/kv_dpm.c

2552

pi->caps_db_ramping = true;

sys/dev/pci/drm/radeon/kv_dpm.c

2553

pi->caps_td_ramping = true;

sys/dev/pci/drm/radeon/kv_dpm.c

2554

pi->caps_tcp_ramping = true;

sys/dev/pci/drm/radeon/kv_dpm.c

2557

pi->caps_sclk_ds = true;

sys/dev/pci/drm/radeon/kv_dpm.c

2558

pi->enable_auto_thermal_throttling = true;

sys/dev/pci/drm/radeon/kv_dpm.c

2563

pi->bapm_enable = true;

sys/dev/pci/drm/radeon/kv_dpm.c

2569

pi->bapm_enable = true;

sys/dev/pci/drm/radeon/kv_dpm.c

2574

pi->caps_uvd_pg = true;

sys/dev/pci/drm/radeon/kv_dpm.c

2575

pi->caps_uvd_dpm = true;

sys/dev/pci/drm/radeon/kv_dpm.c

2592

pi->enable_dpm = true;

sys/dev/pci/drm/radeon/kv_dpm.c

286

pi->cac_enabled = true;

sys/dev/pci/drm/radeon/kv_dpm.c

492

kv_smc_dpm_enable(rdev, true);

sys/dev/pci/drm/radeon/kv_dpm.c

570

kv_dpm_power_level_enable(rdev, i, true);

sys/dev/pci/drm/radeon/kv_dpm.c

584

kv_dpm_power_level_enable(rdev, i, true);

sys/dev/pci/drm/radeon/ni.c

1328

rdev->gart.ready = true;

sys/dev/pci/drm/radeon/ni.c

1543

cayman_cp_enable(rdev, true);

sys/dev/pci/drm/radeon/ni.c

1702

rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;

sys/dev/pci/drm/radeon/ni.c

1942

r600_set_bios_scratch_engine_hung(rdev, true);

sys/dev/pci/drm/radeon/ni.c

2295

rdev->accel_working = true;

sys/dev/pci/drm/radeon/ni.c

2417

rdev->accel_working = true;

sys/dev/pci/drm/radeon/ni_dma.c

247

ring->ready = true;

sys/dev/pci/drm/radeon/ni_dpm.c

110

true

sys/dev/pci/drm/radeon/ni_dpm.c

179

true

sys/dev/pci/drm/radeon/ni_dpm.c

2349

if (cypress_get_mclk_frequency_ratio(rdev, pl->mclk, true) >=

sys/dev/pci/drm/radeon/ni_dpm.c

2351

dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;

sys/dev/pci/drm/radeon/ni_dpm.c

2353

dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;

sys/dev/pci/drm/radeon/ni_dpm.c

248

true

sys/dev/pci/drm/radeon/ni_dpm.c

2614

ni_pi->pc_enabled = true;

sys/dev/pci/drm/radeon/ni_dpm.c

2773

bool result = true;

sys/dev/pci/drm/radeon/ni_dpm.c

3428

eg_pi->pcie_performance_request_registered = true;

sys/dev/pci/drm/radeon/ni_dpm.c

3448

pi->pcie_gen2 = true;

sys/dev/pci/drm/radeon/ni_dpm.c

3453

ni_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, true);

sys/dev/pci/drm/radeon/ni_dpm.c

3601

rv770_enable_voltage_control(rdev, true);

sys/dev/pci/drm/radeon/ni_dpm.c

3614

cypress_enable_spread_spectrum(rdev, true);

sys/dev/pci/drm/radeon/ni_dpm.c

3616

rv770_enable_thermal_protection(rdev, true);

sys/dev/pci/drm/radeon/ni_dpm.c

3625

ni_enable_dynamic_pcie_gen2(rdev, true);

sys/dev/pci/drm/radeon/ni_dpm.c

3685

cypress_enable_sclk_control(rdev, true);

sys/dev/pci/drm/radeon/ni_dpm.c

3687

cypress_enable_mclk_control(rdev, true);

sys/dev/pci/drm/radeon/ni_dpm.c

3690

ni_gfx_clockgating_enable(rdev, true);

sys/dev/pci/drm/radeon/ni_dpm.c

3692

ni_mg_clockgating_enable(rdev, true);

sys/dev/pci/drm/radeon/ni_dpm.c

3694

ni_ls_clockgating_enable(rdev, true);

sys/dev/pci/drm/radeon/ni_dpm.c

3696

rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);

sys/dev/pci/drm/radeon/ni_dpm.c

3836

ret = ni_enable_smc_cac(rdev, new_ps, true);

sys/dev/pci/drm/radeon/ni_dpm.c

3841

ret = ni_enable_power_containment(rdev, new_ps, true);

sys/dev/pci/drm/radeon/ni_dpm.c

3950

pi->acpi_pcie_gen2 = true;

sys/dev/pci/drm/radeon/ni_dpm.c

3956

eg_pi->ulv.supported = true;

sys/dev/pci/drm/radeon/ni_dpm.c

4127

eg_pi->smu_uvd_hs = true;

sys/dev/pci/drm/radeon/ni_dpm.c

4157

pi->gfx_clock_gating = true;

sys/dev/pci/drm/radeon/ni_dpm.c

4159

pi->mg_clock_gating = true;

sys/dev/pci/drm/radeon/ni_dpm.c

4160

pi->mgcgtssm = true;

sys/dev/pci/drm/radeon/ni_dpm.c

4164

pi->dynamic_pcie_gen2 = true;

sys/dev/pci/drm/radeon/ni_dpm.c

4167

pi->thermal_protection = true;

sys/dev/pci/drm/radeon/ni_dpm.c

4171

pi->display_gap = true;

sys/dev/pci/drm/radeon/ni_dpm.c

4173

pi->dcodt = true;

sys/dev/pci/drm/radeon/ni_dpm.c

4175

pi->ulps = true;

sys/dev/pci/drm/radeon/ni_dpm.c

4177

eg_pi->dynamic_ac_timing = true;

sys/dev/pci/drm/radeon/ni_dpm.c

4178

eg_pi->abm = true;

sys/dev/pci/drm/radeon/ni_dpm.c

4179

eg_pi->mcls = true;

sys/dev/pci/drm/radeon/ni_dpm.c

4180

eg_pi->light_sleep = true;

sys/dev/pci/drm/radeon/ni_dpm.c

4181

eg_pi->memory_transition = true;

sys/dev/pci/drm/radeon/ni_dpm.c

4236

ni_pi->enable_power_containment = true;

sys/dev/pci/drm/radeon/ni_dpm.c

4237

ni_pi->enable_cac = true;

sys/dev/pci/drm/radeon/ni_dpm.c

4238

ni_pi->enable_sq_ramping = true;

sys/dev/pci/drm/radeon/ni_dpm.c

4246

ni_pi->cac_configuration_required = true;

sys/dev/pci/drm/radeon/ni_dpm.c

4249

ni_pi->support_cac_long_term_average = true;

sys/dev/pci/drm/radeon/ni_dpm.c

4258

ni_pi->use_power_boost_limit = true;

sys/dev/pci/drm/radeon/ni_dpm.c

779

return true;

sys/dev/pci/drm/radeon/ni_dpm.c

797

disable_mclk_switching = true;

sys/dev/pci/drm/radeon/ni_dpm.c

894

ps->dc_compatible = true;

sys/dev/pci/drm/radeon/r100.c

105

return true;

sys/dev/pci/drm/radeon/r100.c

1246

ring->ready = true;

sys/dev/pci/drm/radeon/r100.c

1626

track->zb_dirty = true;

sys/dev/pci/drm/radeon/r100.c

1639

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r100.c

1665

track->tex_dirty = true;

sys/dev/pci/drm/radeon/r100.c

1683

track->tex_dirty = true;

sys/dev/pci/drm/radeon/r100.c

1701

track->tex_dirty = true;

sys/dev/pci/drm/radeon/r100.c

1719

track->tex_dirty = true;

sys/dev/pci/drm/radeon/r100.c

1723

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r100.c

1724

track->zb_dirty = true;

sys/dev/pci/drm/radeon/r100.c

1747

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r100.c

1751

track->zb_dirty = true;

sys/dev/pci/drm/radeon/r100.c

1776

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r100.c

1777

track->zb_dirty = true;

sys/dev/pci/drm/radeon/r100.c

1795

track->zb_dirty = true;

sys/dev/pci/drm/radeon/r100.c

1812

track->tex_dirty = true;

sys/dev/pci/drm/radeon/r100.c

1827

track->tex_dirty = true;

sys/dev/pci/drm/radeon/r100.c

1834

track->tex_dirty = true;

sys/dev/pci/drm/radeon/r100.c

1848

track->tex_dirty = true;

sys/dev/pci/drm/radeon/r100.c

1855

track->textures[i].use_pitch = true;

sys/dev/pci/drm/radeon/r100.c

1901

track->tex_dirty = true;

sys/dev/pci/drm/radeon/r100.c

1912

track->tex_dirty = true;

sys/dev/pci/drm/radeon/r100.c

227

rdev->pm.dynpm_can_upclock = true;

sys/dev/pci/drm/radeon/r100.c

228

rdev->pm.dynpm_can_downclock = true;

sys/dev/pci/drm/radeon/r100.c

2408

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r100.c

2409

track->zb_dirty = true;

sys/dev/pci/drm/radeon/r100.c

2410

track->tex_dirty = true;

sys/dev/pci/drm/radeon/r100.c

2411

track->aa_dirty = true;

sys/dev/pci/drm/radeon/r100.c

2420

track->separate_cube = true;

sys/dev/pci/drm/radeon/r100.c

2436

track->z_enabled = true;

sys/dev/pci/drm/radeon/r100.c

2469

track->textures[i].roundup_w = true;

sys/dev/pci/drm/radeon/r100.c

2470

track->textures[i].roundup_h = true;

sys/dev/pci/drm/radeon/r100.c

2665

force_dac2 = true;

sys/dev/pci/drm/radeon/r100.c

2682

force_dac2 = true;

sys/dev/pci/drm/radeon/r100.c

2734

rdev->mc.vram_is_ddr = true;

sys/dev/pci/drm/radeon/r100.c

2736

rdev->mc.vram_is_ddr = true;

sys/dev/pci/drm/radeon/r100.c

2748

rdev->mc.vram_is_ddr = true;

sys/dev/pci/drm/radeon/r100.c

3977

rdev->accel_working = true;

sys/dev/pci/drm/radeon/r100.c

4106

rdev->accel_working = true;

sys/dev/pci/drm/radeon/r100.c

528

return true;

sys/dev/pci/drm/radeon/r100.c

548

connected = true;

sys/dev/pci/drm/radeon/r100.c

552

connected = true;

sys/dev/pci/drm/radeon/r100.c

689

rdev->gart.ready = true;

sys/dev/pci/drm/radeon/r100.c

802

rdev->pm.vblank_sync = true;

sys/dev/pci/drm/radeon/r100.c

811

rdev->pm.vblank_sync = true;

sys/dev/pci/drm/radeon/r100.c

818

queue_hotplug = true;

sys/dev/pci/drm/radeon/r100.c

82

return true;

sys/dev/pci/drm/radeon/r100.c

822

queue_hotplug = true;

sys/dev/pci/drm/radeon/r100.c

87

return true;

sys/dev/pci/drm/radeon/r200.c

190

track->zb_dirty = true;

sys/dev/pci/drm/radeon/r200.c

203

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r200.c

232

track->tex_dirty = true;

sys/dev/pci/drm/radeon/r200.c

276

track->tex_dirty = true;

sys/dev/pci/drm/radeon/r200.c

280

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r200.c

281

track->zb_dirty = true;

sys/dev/pci/drm/radeon/r200.c

305

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r200.c

309

track->zb_dirty = true;

sys/dev/pci/drm/radeon/r200.c

339

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r200.c

340

track->zb_dirty = true;

sys/dev/pci/drm/radeon/r200.c

358

track->zb_dirty = true;

sys/dev/pci/drm/radeon/r200.c

375

track->tex_dirty = true;

sys/dev/pci/drm/radeon/r200.c

400

track->tex_dirty = true;

sys/dev/pci/drm/radeon/r200.c

410

track->tex_dirty = true;

sys/dev/pci/drm/radeon/r200.c

427

track->tex_dirty = true;

sys/dev/pci/drm/radeon/r200.c

466

track->tex_dirty = true;

sys/dev/pci/drm/radeon/r200.c

483

track->textures[i].lookup_disable = true;

sys/dev/pci/drm/radeon/r200.c

523

track->tex_dirty = true;

sys/dev/pci/drm/radeon/r200.c

537

track->tex_dirty = true;

sys/dev/pci/drm/radeon/r300.c

1009

track->tex_dirty = true;

sys/dev/pci/drm/radeon/r300.c

1047

track->tex_dirty = true;

sys/dev/pci/drm/radeon/r300.c

1077

track->tex_dirty = true;

sys/dev/pci/drm/radeon/r300.c

1092

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r300.c

1106

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r300.c

1107

track->zb_dirty = true;

sys/dev/pci/drm/radeon/r300.c

1119

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r300.c

1131

track->aa_dirty = true;

sys/dev/pci/drm/radeon/r300.c

1136

track->aa_dirty = true;

sys/dev/pci/drm/radeon/r300.c

1140

track->aa_dirty = true;

sys/dev/pci/drm/radeon/r300.c

1462

rdev->accel_working = true;

sys/dev/pci/drm/radeon/r300.c

1573

rdev->accel_working = true;

sys/dev/pci/drm/radeon/r300.c

187

rdev->gart.ready = true;

sys/dev/pci/drm/radeon/r300.c

481

rdev->mc.vram_is_ddr = true;

sys/dev/pci/drm/radeon/r300.c

674

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r300.c

687

track->zb_dirty = true;

sys/dev/pci/drm/radeon/r300.c

731

track->tex_dirty = true;

sys/dev/pci/drm/radeon/r300.c

758

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r300.c

759

track->zb_dirty = true;

sys/dev/pci/drm/radeon/r300.c

769

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r300.c

834

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r300.c

839

track->z_enabled = true;

sys/dev/pci/drm/radeon/r300.c

843

track->zb_dirty = true;

sys/dev/pci/drm/radeon/r300.c

860

track->zb_dirty = true;

sys/dev/pci/drm/radeon/r300.c

885

track->zb_dirty = true;

sys/dev/pci/drm/radeon/r300.c

895

track->tex_dirty = true;

sys/dev/pci/drm/radeon/r300.c

981

track->tex_dirty = true;

sys/dev/pci/drm/radeon/r420.c

332

rdev->accel_working = true;

sys/dev/pci/drm/radeon/r420.c

453

rdev->accel_working = true;

sys/dev/pci/drm/radeon/r520.c

242

rdev->accel_working = true;

sys/dev/pci/drm/radeon/r520.c

315

rdev->accel_working = true;

sys/dev/pci/drm/radeon/r520.c

98

rdev->mc.vram_is_ddr = true;

sys/dev/pci/drm/radeon/r600.c

1182

rdev->gart.ready = true;

sys/dev/pci/drm/radeon/r600.c

1441

rdev->mc.vram_is_ddr = true;

sys/dev/pci/drm/radeon/r600.c

1497

rdev->fastfb_working = true;

sys/dev/pci/drm/radeon/r600.c

1513

PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,

sys/dev/pci/drm/radeon/r600.c

1612

return true;

sys/dev/pci/drm/radeon/r600.c

1893

r600_set_bios_scratch_engine_hung(rdev, true);

sys/dev/pci/drm/radeon/r600.c

2767

ring->ready = true;

sys/dev/pci/drm/radeon/r600.c

2818

rdev->scratch.free[i] = true;

sys/dev/pci/drm/radeon/r600.c

2948

return true;

sys/dev/pci/drm/radeon/r600.c

3218

rdev->accel_working = true;

sys/dev/pci/drm/radeon/r600.c

3322

rdev->accel_working = true;

sys/dev/pci/drm/radeon/r600.c

3485

PAGE_SIZE, true,

sys/dev/pci/drm/radeon/r600.c

3599

rdev->ih.enabled = true;

sys/dev/pci/drm/radeon/r600.c

366

rdev->pm.dynpm_can_upclock = true;

sys/dev/pci/drm/radeon/r600.c

367

rdev->pm.dynpm_can_downclock = true;

sys/dev/pci/drm/radeon/r600.c

4142

rdev->pm.vblank_sync = true;

sys/dev/pci/drm/radeon/r600.c

4172

rdev->pm.vblank_sync = true;

sys/dev/pci/drm/radeon/r600.c

4211

queue_hotplug = true;

sys/dev/pci/drm/radeon/r600.c

4219

queue_hotplug = true;

sys/dev/pci/drm/radeon/r600.c

4227

queue_hotplug = true;

sys/dev/pci/drm/radeon/r600.c

4235

queue_hotplug = true;

sys/dev/pci/drm/radeon/r600.c

4243

queue_hotplug = true;

sys/dev/pci/drm/radeon/r600.c

4251

queue_hotplug = true;

sys/dev/pci/drm/radeon/r600.c

4267

queue_hdmi = true;

sys/dev/pci/drm/radeon/r600.c

4276

queue_hdmi = true;

sys/dev/pci/drm/radeon/r600.c

4306

queue_thermal = true;

sys/dev/pci/drm/radeon/r600.c

4310

rdev->pm.dpm.thermal.high_to_low = true;

sys/dev/pci/drm/radeon/r600.c

4311

queue_thermal = true;

sys/dev/pci/drm/radeon/r600.c

800

return true;

sys/dev/pci/drm/radeon/r600.c

812

connected = true;

sys/dev/pci/drm/radeon/r600.c

816

connected = true;

sys/dev/pci/drm/radeon/r600.c

820

connected = true;

sys/dev/pci/drm/radeon/r600.c

824

connected = true;

sys/dev/pci/drm/radeon/r600.c

829

connected = true;

sys/dev/pci/drm/radeon/r600.c

833

connected = true;

sys/dev/pci/drm/radeon/r600.c

842

connected = true;

sys/dev/pci/drm/radeon/r600.c

846

connected = true;

sys/dev/pci/drm/radeon/r600.c

850

connected = true;

sys/dev/pci/drm/radeon/r600_cs.c

1032

track->db_dirty = true;

sys/dev/pci/drm/radeon/r600_cs.c

1056

track->db_dirty = true;

sys/dev/pci/drm/radeon/r600_cs.c

1060

track->db_dirty = true;

sys/dev/pci/drm/radeon/r600_cs.c

1065

track->db_dirty = true;

sys/dev/pci/drm/radeon/r600_cs.c

1069

track->streamout_dirty = true;

sys/dev/pci/drm/radeon/r600_cs.c

1073

track->streamout_dirty = true;

sys/dev/pci/drm/radeon/r600_cs.c

1090

track->streamout_dirty = true;

sys/dev/pci/drm/radeon/r600_cs.c

1099

track->streamout_dirty = true;

sys/dev/pci/drm/radeon/r600_cs.c

1112

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r600_cs.c

1121

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r600_cs.c

1126

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r600_cs.c

1156

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r600_cs.c

1168

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r600_cs.c

1181

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r600_cs.c

1220

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r600_cs.c

1251

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r600_cs.c

1265

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r600_cs.c

1288

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r600_cs.c

1301

track->db_dirty = true;

sys/dev/pci/drm/radeon/r600_cs.c

1313

track->db_dirty = true;

sys/dev/pci/drm/radeon/r600_cs.c

1319

track->db_dirty = true;

sys/dev/pci/drm/radeon/r600_cs.c

1541

is_array = true;

sys/dev/pci/drm/radeon/r600_cs.c

1544

is_array = true;

sys/dev/pci/drm/radeon/r600_cs.c

1626

return true;

sys/dev/pci/drm/radeon/r600_cs.c

183

return true;

sys/dev/pci/drm/radeon/r600_cs.c

197

return true;

sys/dev/pci/drm/radeon/r600_cs.c

325

track->cb_dirty = true;

sys/dev/pci/drm/radeon/r600_cs.c

334

track->db_dirty = true;

sys/dev/pci/drm/radeon/r600_cs.c

345

track->streamout_dirty = true;

sys/dev/pci/drm/radeon/r600_dma.c

171

ring->ready = true;

sys/dev/pci/drm/radeon/r600_dma.c

324

return true;

sys/dev/pci/drm/radeon/r600_dpm.c

1023

rdev->pm.dpm.power_control = true;

sys/dev/pci/drm/radeon/r600_dpm.c

296

return true;

sys/dev/pci/drm/radeon/r600_dpm.c

688

r600_dynamicpm_enable(rdev, true);

sys/dev/pci/drm/radeon/r600_dpm.c

693

r600_enable_spll_bypass(rdev, true);

sys/dev/pci/drm/radeon/r600_dpm.c

698

r600_enable_spll_bypass(rdev, true);

sys/dev/pci/drm/radeon/r600_dpm.c

703

r600_enable_sclk_control(rdev, true);

sys/dev/pci/drm/radeon/r600_dpm.c

704

r600_enable_mclk_control(rdev, true);

sys/dev/pci/drm/radeon/r600_dpm.c

725

return true;

sys/dev/pci/drm/radeon/r600_dpm.c

727

return true;

sys/dev/pci/drm/radeon/r600_dpm.c

729

return true;

sys/dev/pci/drm/radeon/r600_dpm.c

731

return true;

sys/dev/pci/drm/radeon/r600_dpm.c

733

return true;

sys/dev/pci/drm/radeon/r600_dpm.c

773

return true;

sys/dev/pci/drm/radeon/r600_dpm.c

794

rdev->irq.dpm_thermal = true;

sys/dev/pci/drm/radeon/r600_dpm.c

913

rdev->pm.dpm.fan.ucode_fan_control = true;

sys/dev/pci/drm/radeon/r600_hdmi.c

130

changed = true;

sys/dev/pci/drm/radeon/radeon.h

2551

#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)

sys/dev/pci/drm/radeon/radeon.h

2555

#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)

sys/dev/pci/drm/radeon/radeon.h

441

return true;

sys/dev/pci/drm/radeon/radeon_acpi.c

288

n->enabled = true;

sys/dev/pci/drm/radeon/radeon_acpi.c

295

n->enabled = true;

sys/dev/pci/drm/radeon/radeon_acpi.c

551

return true;

sys/dev/pci/drm/radeon/radeon_acpi.c

769

atif->functions.system_params = true;

sys/dev/pci/drm/radeon/radeon_asic.c

2397

rdev->has_uvd = true;

sys/dev/pci/drm/radeon/radeon_asic.c

2410

rdev->has_uvd = true;

sys/dev/pci/drm/radeon/radeon_asic.c

2417

rdev->has_uvd = true;

sys/dev/pci/drm/radeon/radeon_asic.c

2430

rdev->has_uvd = true;

sys/dev/pci/drm/radeon/radeon_asic.c

2436

rdev->has_uvd = true;

sys/dev/pci/drm/radeon/radeon_asic.c

2447

rdev->has_uvd = true;

sys/dev/pci/drm/radeon/radeon_asic.c

2453

rdev->has_uvd = true;

sys/dev/pci/drm/radeon/radeon_asic.c

2459

rdev->has_uvd = true;

sys/dev/pci/drm/radeon/radeon_asic.c

2460

rdev->has_vce = true;

sys/dev/pci/drm/radeon/radeon_asic.c

2481

rdev->has_uvd = true;

sys/dev/pci/drm/radeon/radeon_asic.c

2484

rdev->has_uvd = true;

sys/dev/pci/drm/radeon/radeon_asic.c

2485

rdev->has_vce = true;

sys/dev/pci/drm/radeon/radeon_asic.c

2590

rdev->has_uvd = true;

sys/dev/pci/drm/radeon/radeon_asic.c

2591

rdev->has_vce = true;

sys/dev/pci/drm/radeon/radeon_asic.c

2691

rdev->has_uvd = true;

sys/dev/pci/drm/radeon/radeon_asic.c

2692

rdev->has_vce = true;

sys/dev/pci/drm/radeon/radeon_atombios.c

1013

bios_connectors[i].valid = true;

sys/dev/pci/drm/radeon/radeon_atombios.c

109

i2c.hw_capable = true;

sys/dev/pci/drm/radeon/radeon_atombios.c

1092

return true;

sys/dev/pci/drm/radeon/radeon_atombios.c

114

i2c.mm_i2c = true;

sys/dev/pci/drm/radeon/radeon_atombios.c

121

i2c.valid = true;

sys/dev/pci/drm/radeon/radeon_atombios.c

1293

return true;

sys/dev/pci/drm/radeon/radeon_atombios.c

1318

return true;

sys/dev/pci/drm/radeon/radeon_atombios.c

1322

return true;

sys/dev/pci/drm/radeon/radeon_atombios.c

1376

return true;

sys/dev/pci/drm/radeon/radeon_atombios.c

1412

return true;

sys/dev/pci/drm/radeon/radeon_atombios.c

1551

return true;

sys/dev/pci/drm/radeon/radeon_atombios.c

1573

return true;

sys/dev/pci/drm/radeon/radeon_atombios.c

1600

return true;

sys/dev/pci/drm/radeon/radeon_atombios.c

1689

lvds->linkb = true;

sys/dev/pci/drm/radeon/radeon_atombios.c

1751

bad_record = true;

sys/dev/pci/drm/radeon/radeon_atombios.c

1887

return true;

sys/dev/pci/drm/radeon/radeon_atombios.c

2165

true;

sys/dev/pci/drm/radeon/radeon_atombios.c

2201

true;

sys/dev/pci/drm/radeon/radeon_atombios.c

2237

true;

sys/dev/pci/drm/radeon/radeon_atombios.c

2248

true;

sys/dev/pci/drm/radeon/radeon_atombios.c

225

gpio.valid = true;

sys/dev/pci/drm/radeon/radeon_atombios.c

2289

rdev->pm.no_fan = true;

sys/dev/pci/drm/radeon/radeon_atombios.c

2577

return true;

sys/dev/pci/drm/radeon/radeon_atombios.c

2869

dividers->enable_post_div = true;

sys/dev/pci/drm/radeon/radeon_atombios.c

2886

true : false;

sys/dev/pci/drm/radeon/radeon_atombios.c

2889

dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;

sys/dev/pci/drm/radeon/radeon_atombios.c

2898

ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;

sys/dev/pci/drm/radeon/radeon_atombios.c

2900

ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;

sys/dev/pci/drm/radeon/radeon_atombios.c

2918

ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;

sys/dev/pci/drm/radeon/radeon_atombios.c

2920

ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;

sys/dev/pci/drm/radeon/radeon_atombios.c

3473

return true;

sys/dev/pci/drm/radeon/radeon_atombios.c

3480

return true;

sys/dev/pci/drm/radeon/radeon_atombios.c

3492

return true;

sys/dev/pci/drm/radeon/radeon_atombios.c

457

return true;

sys/dev/pci/drm/radeon/radeon_atombios.c

730

router.ddc_valid = true;

sys/dev/pci/drm/radeon/radeon_atombios.c

738

router.cd_valid = true;

sys/dev/pci/drm/radeon/radeon_atombios.c

834

return true;

sys/dev/pci/drm/radeon/radeon_audio.c

251

rdev->audio.enabled = true;

sys/dev/pci/drm/radeon/radeon_audio.c

651

radeon_audio_set_mute(encoder, true);

sys/dev/pci/drm/radeon/radeon_audio.c

779

*enabled = true;

sys/dev/pci/drm/radeon/radeon_audio.c

843

rdev->audio.component_registered = true;

sys/dev/pci/drm/radeon/radeon_benchmark.c

109

r = radeon_bo_create(rdev, size, PAGE_SIZE, true, ddomain, 0, NULL, NULL, &dobj);

sys/dev/pci/drm/radeon/radeon_benchmark.c

97

r = radeon_bo_create(rdev, size, PAGE_SIZE, true, sdomain, 0, NULL, NULL, &sobj);

sys/dev/pci/drm/radeon/radeon_bios.c

115

return true;

sys/dev/pci/drm/radeon/radeon_bios.c

146

return true;

sys/dev/pci/drm/radeon/radeon_bios.c

183

return true;

sys/dev/pci/drm/radeon/radeon_bios.c

214

return true;

sys/dev/pci/drm/radeon/radeon_bios.c

260

return true;

sys/dev/pci/drm/radeon/radeon_bios.c

340

found = true;

sys/dev/pci/drm/radeon/radeon_bios.c

352

found = true;

sys/dev/pci/drm/radeon/radeon_bios.c

381

return true;

sys/dev/pci/drm/radeon/radeon_bios.c

795

r = true;

sys/dev/pci/drm/radeon/radeon_bios.c

853

rdev->is_atom_bios = true;

sys/dev/pci/drm/radeon/radeon_bios.c

859

return true;

sys/dev/pci/drm/radeon/radeon_bios.c

87

return true;

sys/dev/pci/drm/radeon/radeon_clocks.c

177

return true;

sys/dev/pci/drm/radeon/radeon_clocks.c

253

return true;

sys/dev/pci/drm/radeon/radeon_combios.c

1152

lvds->use_bios_dividers = true;

sys/dev/pci/drm/radeon/radeon_combios.c

1206

lvds->use_bios_dividers = true;

sys/dev/pci/drm/radeon/radeon_combios.c

1321

return true;

sys/dev/pci/drm/radeon/radeon_combios.c

1374

return true;

sys/dev/pci/drm/radeon/radeon_combios.c

1398

return true;

sys/dev/pci/drm/radeon/radeon_combios.c

1427

i2c_bus.valid = true;

sys/dev/pci/drm/radeon/radeon_combios.c

1428

i2c_bus.hw_capable = true;

sys/dev/pci/drm/radeon/radeon_combios.c

1429

i2c_bus.mm_i2c = true;

sys/dev/pci/drm/radeon/radeon_combios.c

1442

return true;

sys/dev/pci/drm/radeon/radeon_combios.c

2208

return true;

sys/dev/pci/drm/radeon/radeon_combios.c

2237

return true;

sys/dev/pci/drm/radeon/radeon_combios.c

2262

return true;

sys/dev/pci/drm/radeon/radeon_combios.c

2622

return true;

sys/dev/pci/drm/radeon/radeon_combios.c

2686

i2c_bus.valid = true;

sys/dev/pci/drm/radeon/radeon_combios.c

2687

i2c_bus.hw_capable = true;

sys/dev/pci/drm/radeon/radeon_combios.c

2688

i2c_bus.mm_i2c = true;

sys/dev/pci/drm/radeon/radeon_combios.c

2750

true;

sys/dev/pci/drm/radeon/radeon_combios.c

2754

rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;

sys/dev/pci/drm/radeon/radeon_combios.c

2951

return true;

sys/dev/pci/drm/radeon/radeon_combios.c

3006

return true;

sys/dev/pci/drm/radeon/radeon_combios.c

391

return true;

sys/dev/pci/drm/radeon/radeon_combios.c

556

i2c.hw_capable = true;

sys/dev/pci/drm/radeon/radeon_combios.c

567

i2c.hw_capable = true;

sys/dev/pci/drm/radeon/radeon_combios.c

580

i2c.hw_capable = true;

sys/dev/pci/drm/radeon/radeon_combios.c

592

i2c.hw_capable = true;

sys/dev/pci/drm/radeon/radeon_combios.c

606

i2c.hw_capable = true;

sys/dev/pci/drm/radeon/radeon_combios.c

629

i2c.valid = true;

sys/dev/pci/drm/radeon/radeon_combios.c

688

i2c.valid = true;

sys/dev/pci/drm/radeon/radeon_combios.c

689

i2c.hw_capable = true;

sys/dev/pci/drm/radeon/radeon_combios.c

690

i2c.mm_i2c = true;

sys/dev/pci/drm/radeon/radeon_combios.c

801

return true;

sys/dev/pci/drm/radeon/radeon_combios.c

819

return true;

sys/dev/pci/drm/radeon/radeon_connectors.c

1049

radeon_connector->detected_by_load = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

1054

ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, true);

sys/dev/pci/drm/radeon/radeon_connectors.c

1195

return true;

sys/dev/pci/drm/radeon/radeon_connectors.c

1233

force = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

1252

radeon_connector->detected_hpd_without_ddc = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

1276

broken_edid = true; /* defer use_digital to later */

sys/dev/pci/drm/radeon/radeon_connectors.c

1320

if ((ret == connector_status_connected) && (radeon_connector->use_digital == true))

sys/dev/pci/drm/radeon/radeon_connectors.c

1355

radeon_connector->detected_by_load = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

1360

radeon_connector->use_digital = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

1373

ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, true);

sys/dev/pci/drm/radeon/radeon_connectors.c

1386

radeon_connector->use_digital = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

1420

if (radeon_connector->use_digital == true) {

sys/dev/pci/drm/radeon/radeon_connectors.c

1446

radeon_connector->use_digital = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

1602

found = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

1616

return true;

sys/dev/pci/drm/radeon/radeon_connectors.c

1684

if (radeon_ddc_probe(radeon_connector, true)) /* try DDC */

sys/dev/pci/drm/radeon/radeon_connectors.c

1874

radeon_connector->shared_ddc = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

1875

shared_ddc = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

1892

is_dp_bridge = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

1928

has_aux = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

1944

connector->interlace_allowed = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

1945

connector->doublescan_allowed = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

1946

radeon_connector->dac_load_detect = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

1999

connector->interlace_allowed = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2001

connector->doublescan_allowed = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2005

radeon_connector->dac_load_detect = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2042

radeon_connector->dac_load_detect = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2056

connector->interlace_allowed = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2057

connector->doublescan_allowed = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2072

radeon_connector->dac_load_detect = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2086

connector->interlace_allowed = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2087

connector->doublescan_allowed = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2136

radeon_connector->dac_load_detect = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2145

connector->interlace_allowed = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2147

connector->doublescan_allowed = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2201

connector->interlace_allowed = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2203

connector->doublescan_allowed = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2216

has_aux = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2258

connector->interlace_allowed = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2271

has_aux = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2297

radeon_connector->dac_load_detect = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

235

connected = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2417

radeon_connector->dac_load_detect = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2423

connector->interlace_allowed = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2424

connector->doublescan_allowed = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2439

radeon_connector->dac_load_detect = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2445

connector->interlace_allowed = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2446

connector->doublescan_allowed = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2463

radeon_connector->dac_load_detect = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2469

connector->interlace_allowed = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2471

connector->doublescan_allowed = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

2483

radeon_connector->dac_load_detect = true;

sys/dev/pci/drm/radeon/radeon_connectors.c

452

mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);

sys/dev/pci/drm/radeon/radeon_connectors.c

538

new_coherent_mode = val ? true : false;

sys/dev/pci/drm/radeon/radeon_connectors.c

648

radeon_connector->dac_load_detect = true;

sys/dev/pci/drm/radeon/radeon_cs.c

169

need_mmap_lock = true;

sys/dev/pci/drm/radeon/radeon_cs.c

499

r = radeon_ib_schedule(rdev, &parser->ib, NULL, true);

sys/dev/pci/drm/radeon/radeon_cs.c

597

r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib, true);

sys/dev/pci/drm/radeon/radeon_cs.c

599

r = radeon_ib_schedule(rdev, &parser->ib, NULL, true);

sys/dev/pci/drm/radeon/radeon_cs.c

643

parser->const_ib.is_const_ib = true;

sys/dev/pci/drm/radeon/radeon_cs.c

821

return true;

sys/dev/pci/drm/radeon/radeon_cursor.c

259

radeon_crtc->cursor_out_of_bounds = true;

sys/dev/pci/drm/radeon/radeon_cursor.c

269

radeon_lock_cursor(crtc, true);

sys/dev/pci/drm/radeon/radeon_cursor.c

326

radeon_lock_cursor(crtc, true);

sys/dev/pci/drm/radeon/radeon_cursor.c

377

radeon_lock_cursor(crtc, true);

sys/dev/pci/drm/radeon/radeon_device.c

1240

radeon_resume_kms(dev, true, true);

sys/dev/pci/drm/radeon/radeon_device.c

1248

radeon_suspend_kms(dev, true, true, false);

sys/dev/pci/drm/radeon/radeon_device.c

1448

runtime = true;

sys/dev/pci/drm/radeon/radeon_device.c

1536

rdev->shutdown = true;

sys/dev/pci/drm/radeon/radeon_device.c

163

return true;

sys/dev/pci/drm/radeon/radeon_device.c

1670

rdev->asic->asic_reset(rdev, true);

sys/dev/pci/drm/radeon/radeon_device.c

1828

saved = true;

sys/dev/pci/drm/radeon/radeon_device.c

1879

rdev->in_reset = true;

sys/dev/pci/drm/radeon/radeon_device.c

279

rdev->scratch.free[i] = true;

sys/dev/pci/drm/radeon/radeon_device.c

321

rdev->scratch.free[i] = true;

sys/dev/pci/drm/radeon/radeon_device.c

475

r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,

sys/dev/pci/drm/radeon/radeon_device.c

519

rdev->wb.enabled = true;

sys/dev/pci/drm/radeon/radeon_device.c

522

rdev->wb.use_event = true;

sys/dev/pci/drm/radeon/radeon_device.c

528

rdev->wb.enabled = true;

sys/dev/pci/drm/radeon/radeon_device.c

529

rdev->wb.use_event = true;

sys/dev/pci/drm/radeon/radeon_device.c

700

return true;

sys/dev/pci/drm/radeon/radeon_device.c

705

return true;

sys/dev/pci/drm/radeon/radeon_device.c

711

return true;

sys/dev/pci/drm/radeon/radeon_device.c

723

return true;

sys/dev/pci/drm/radeon/radeon_device.c

769

return true;

sys/dev/pci/drm/radeon/radeon_device.c

777

return true;

sys/dev/pci/drm/radeon/radeon_display.c

1584

rdev->mode_info.mode_config_initialized = true;

sys/dev/pci/drm/radeon/radeon_display.c

1589

rdev_to_drm(rdev)->mode_config.async_page_flip = true;

sys/dev/pci/drm/radeon/radeon_display.c

1605

rdev_to_drm(rdev)->mode_config.fb_modifiers_not_supported = true;

sys/dev/pci/drm/radeon/radeon_display.c

1676

return true;

sys/dev/pci/drm/radeon/radeon_display.c

1691

bool first = true;

sys/dev/pci/drm/radeon/radeon_display.c

1769

return true;

sys/dev/pci/drm/radeon/radeon_display.c

1816

bool in_vbl = true;

sys/dev/pci/drm/radeon/radeon_display.c

645

active = true;

sys/dev/pci/drm/radeon/radeon_display.c

653

rdev->have_disp_power_ref = true;

sys/dev/pci/drm/radeon/radeon_dp_auxch.c

77

is_write = true;

sys/dev/pci/drm/radeon/radeon_drv.c

1180

rdev->shutdown = true;

sys/dev/pci/drm/radeon/radeon_drv.c

1348

radeon_suspend_kms(ddev, true, true, false);

sys/dev/pci/drm/radeon/radeon_drv.c

1355

radeon_resume_kms(ddev, true, true);

sys/dev/pci/drm/radeon/radeon_drv.c

357

radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false);

sys/dev/pci/drm/radeon/radeon_drv.c

365

return radeon_suspend_kms(drm_dev, true, true, false);

sys/dev/pci/drm/radeon/radeon_drv.c

379

return radeon_resume_kms(drm_dev, true, true);

sys/dev/pci/drm/radeon/radeon_drv.c

386

return radeon_suspend_kms(drm_dev, false, true, true);

sys/dev/pci/drm/radeon/radeon_drv.c

393

return radeon_resume_kms(drm_dev, false, true);

sys/dev/pci/drm/radeon/radeon_encoders.c

176

use_bl = true;

sys/dev/pci/drm/radeon/radeon_encoders.c

191

use_bl = true;

sys/dev/pci/drm/radeon/radeon_encoders.c

391

return true;

sys/dev/pci/drm/radeon/radeon_encoders.c

396

return true;

sys/dev/pci/drm/radeon/radeon_encoders.c

413

return true;

sys/dev/pci/drm/radeon/radeon_encoders.c

418

return true;

sys/dev/pci/drm/radeon/radeon_encoders.c

445

return true;

sys/dev/pci/drm/radeon/radeon_fbdev.c

339

return true;

sys/dev/pci/drm/radeon/radeon_fbdev.c

82

0, true, &gobj);

sys/dev/pci/drm/radeon/radeon_fence.c

241

wake = true;

sys/dev/pci/drm/radeon/radeon_fence.c

304

rdev->needs_reset = true;

sys/dev/pci/drm/radeon/radeon_fence.c

343

return true;

sys/dev/pci/drm/radeon/radeon_fence.c

348

return true;

sys/dev/pci/drm/radeon/radeon_fence.c

361

return true;

sys/dev/pci/drm/radeon/radeon_fence.c

399

rdev->fence_drv[fence->ring].delayed_irq = true;

sys/dev/pci/drm/radeon/radeon_fence.c

408

return true;

sys/dev/pci/drm/radeon/radeon_fence.c

422

return true;

sys/dev/pci/drm/radeon/radeon_fence.c

426

return true;

sys/dev/pci/drm/radeon/radeon_fence.c

448

return true;

sys/dev/pci/drm/radeon/radeon_fence.c

713

return true;

sys/dev/pci/drm/radeon/radeon_fence.c

793

rdev->fence_drv[ring].initialized = true;

sys/dev/pci/drm/radeon/radeon_fence.c

935

rdev->needs_reset = true;

sys/dev/pci/drm/radeon/radeon_gart.c

180

PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,

sys/dev/pci/drm/radeon/radeon_gem.c

240

true, 30 * HZ);

sys/dev/pci/drm/radeon/radeon_gem.c

316

r = radeon_bo_reserve(rbo, true);

sys/dev/pci/drm/radeon/radeon_gem.c

440

struct ttm_operation_ctx ctx = { true, false };

sys/dev/pci/drm/radeon/radeon_gem.c

494

r = radeon_bo_reserve(bo, true);

sys/dev/pci/drm/radeon/radeon_gem.c

632

true, 30 * HZ);

sys/dev/pci/drm/radeon/radeon_i2c.c

83

return true;

sys/dev/pci/drm/radeon/radeon_ib.c

226

rdev->ib_pool_ready = true;

sys/dev/pci/drm/radeon/radeon_irq_kms.c

269

return true;

sys/dev/pci/drm/radeon/radeon_irq_kms.c

278

return true;

sys/dev/pci/drm/radeon/radeon_irq_kms.c

284

return true;

sys/dev/pci/drm/radeon/radeon_irq_kms.c

290

return true;

sys/dev/pci/drm/radeon/radeon_irq_kms.c

296

return true;

sys/dev/pci/drm/radeon/radeon_irq_kms.c

300

return true;

sys/dev/pci/drm/radeon/radeon_irq_kms.c

311

return true;

sys/dev/pci/drm/radeon/radeon_irq_kms.c

316

return true;

sys/dev/pci/drm/radeon/radeon_irq_kms.c

334

rdev_to_drm(rdev)->vblank_disable_immediate = true;

sys/dev/pci/drm/radeon/radeon_irq_kms.c

356

rdev->irq.installed = true;

sys/dev/pci/drm/radeon/radeon_irq_kms.c

517

rdev->irq.afmt[block] = true;

sys/dev/pci/drm/radeon/radeon_kms.c

607

*value = true;

sys/dev/pci/drm/radeon/radeon_kms.c

844

rdev->irq.crtc_vblank_int[pipe] = true;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

1032

return true;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

327

radeon_crtc->enabled = true;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

57

bool hscale = true, vscale = true;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

595

is_tv = true;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

730

return true;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

790

is_tv = true;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

806

use_bios_divs = true;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1041

is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1127

radeon_atom_output_lock(encoder, true);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1129

radeon_combios_output_lock(encoder, true);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1140

radeon_atom_output_lock(encoder, true);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1142

radeon_combios_output_lock(encoder, true);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1160

is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1354

found = true;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1357

found = true;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1420

found = true;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1423

found = true;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1494

found = true;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1535

bool color = true;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

169

radeon_atom_output_lock(encoder, true);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

171

radeon_combios_output_lock(encoder, true);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

270

return true;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

424

pdata->negative = true;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

559

radeon_atom_output_lock(encoder, true);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

561

radeon_combios_output_lock(encoder, true);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

642

bool color = true;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

756

radeon_atom_output_lock(encoder, true);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

758

radeon_combios_output_lock(encoder, true);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

769

radeon_atom_output_lock(encoder, true);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

771

radeon_combios_output_lock(encoder, true);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

91

is_mac = true;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

922

radeon_atom_output_lock(encoder, true);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

924

radeon_combios_output_lock(encoder, true);

sys/dev/pci/drm/radeon/radeon_mn.c

58

return true;

sys/dev/pci/drm/radeon/radeon_mn.c

63

r = radeon_bo_reserve(bo, true);

sys/dev/pci/drm/radeon/radeon_mn.c

66

return true;

sys/dev/pci/drm/radeon/radeon_mn.c

80

return true;

sys/dev/pci/drm/radeon/radeon_object.c

489

struct ttm_operation_ctx ctx = { true, false };

sys/dev/pci/drm/radeon/radeon_object.c

72

return true;

sys/dev/pci/drm/radeon/radeon_pm.c

1218

rdev->pm.dpm.uvd_active = true;

sys/dev/pci/drm/radeon/radeon_pm.c

1248

rdev->pm.dpm.vce_active = true;

sys/dev/pci/drm/radeon/radeon_pm.c

1341

rdev->pm.dpm_enabled = true;

sys/dev/pci/drm/radeon/radeon_pm.c

1377

rdev->pm.dynpm_can_upclock = true;

sys/dev/pci/drm/radeon/radeon_pm.c

1378

rdev->pm.dynpm_can_downclock = true;

sys/dev/pci/drm/radeon/radeon_pm.c

1469

rdev->pm.dpm_enabled = true;

sys/dev/pci/drm/radeon/radeon_pm.c

1524

disable_dpm = true;

sys/dev/pci/drm/radeon/radeon_pm.c

1625

rdev->pm.sysfs_initialized = true;

sys/dev/pci/drm/radeon/radeon_pm.c

1654

rdev->pm.sysfs_initialized = true;

sys/dev/pci/drm/radeon/radeon_pm.c

1822

rdev->pm.dpm.ac_power = true;

sys/dev/pci/drm/radeon/radeon_pm.c

1843

bool in_vbl = true;

sys/dev/pci/drm/radeon/radeon_pm.c

208

misc_after = true;

sys/dev/pci/drm/radeon/radeon_pm.c

227

radeon_pm_debug_check_in_vbl(rdev, true);

sys/dev/pci/drm/radeon/radeon_pm.c

236

radeon_pm_debug_check_in_vbl(rdev, true);

sys/dev/pci/drm/radeon/radeon_pm.c

80

rdev->pm.dpm.ac_power = true;

sys/dev/pci/drm/radeon/radeon_pm.c

917

rdev->pm.dpm.thermal_active = true;

sys/dev/pci/drm/radeon/radeon_ring.c

270

return true;

sys/dev/pci/drm/radeon/radeon_ring.c

394

r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,

sys/dev/pci/drm/radeon/radeon_ring.c

69

return true;

sys/dev/pci/drm/radeon/radeon_sa.c

54

r = radeon_bo_create(rdev, size, RADEON_GPU_PAGE_SIZE, true,

sys/dev/pci/drm/radeon/radeon_semaphore.c

70

return true;

sys/dev/pci/drm/radeon/radeon_semaphore.c

82

if (radeon_semaphore_ring_emit(rdev, ridx, ring, semaphore, true)) {

sys/dev/pci/drm/radeon/radeon_semaphore.c

87

return true;

sys/dev/pci/drm/radeon/radeon_sync.c

104

r = dma_fence_wait(f, true);

sys/dev/pci/drm/radeon/radeon_test.c

523

return true;

sys/dev/pci/drm/radeon/radeon_test.c

70

r = radeon_bo_create(rdev, size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,

sys/dev/pci/drm/radeon/radeon_test.c

90

r = radeon_bo_create(rdev, size, PAGE_SIZE, true,

sys/dev/pci/drm/radeon/radeon_ttm.c

290

mem->bus.is_iomem = true;

sys/dev/pci/drm/radeon/radeon_ttm.c

467

gtt->bound = true;

sys/dev/pci/drm/radeon/radeon_ttm.c

729

rdev->mman.initialized = true;

sys/dev/pci/drm/radeon/radeon_ttm.c

740

r = radeon_bo_create(rdev, rdev->fb_offset, PAGE_SIZE, true,

sys/dev/pci/drm/radeon/radeon_ttm.c

744

r = radeon_bo_create(rdev, stolen_size, PAGE_SIZE, true,

sys/dev/pci/drm/radeon/radeon_ttm.c

87

true, rdev->mc.gtt_size >> PAGE_SHIFT);

sys/dev/pci/drm/radeon/radeon_uvd.c

153

rdev->uvd.fw_header_present = true;

sys/dev/pci/drm/radeon/radeon_uvd.c

189

r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,

sys/dev/pci/drm/radeon/radeon_uvd.c

625

*has_msg_cmd = true;

sys/dev/pci/drm/radeon/radeon_uvd.c

778

r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true);

sys/dev/pci/drm/radeon/radeon_uvd.c

814

r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true);

sys/dev/pci/drm/radeon/radeon_uvd.c

899

radeon_dpm_enable_uvd(rdev, true);

sys/dev/pci/drm/radeon/radeon_vce.c

171

r = radeon_bo_create(rdev, size, PAGE_SIZE, true,

sys/dev/pci/drm/radeon/radeon_vce.c

330

radeon_dpm_enable_vce(rdev, true);

sys/dev/pci/drm/radeon/radeon_vce.c

571

*allocated = true;

sys/dev/pci/drm/radeon/radeon_vce.c

624

created = true;

sys/dev/pci/drm/radeon/radeon_vce.c

657

destroyed = true;

sys/dev/pci/drm/radeon/radeon_vce.c

738

return true;

sys/dev/pci/drm/radeon/radeon_vm.c

1025

ib.fence->is_vm_update = true;

sys/dev/pci/drm/radeon/radeon_vm.c

1202

r = radeon_bo_create(rdev, pd_size, align, true,

sys/dev/pci/drm/radeon/radeon_vm.c

145

list[0].shared = true;

sys/dev/pci/drm/radeon/radeon_vm.c

156

list[idx].shared = true;

sys/dev/pci/drm/radeon/radeon_vm.c

389

struct ttm_operation_ctx ctx = { true, false };

sys/dev/pci/drm/radeon/radeon_vm.c

420

ib.fence->is_vm_update = true;

sys/dev/pci/drm/radeon/radeon_vm.c

550

RADEON_GPU_PAGE_SIZE, true,

sys/dev/pci/drm/radeon/radeon_vm.c

702

radeon_sync_resv(rdev, &ib.sync, pd->tbo.base.resv, true);

sys/dev/pci/drm/radeon/radeon_vm.c

709

ib.fence->is_vm_update = true;

sys/dev/pci/drm/radeon/radeon_vm.c

831

radeon_sync_resv(rdev, &ib->sync, pt->tbo.base.resv, true);

sys/dev/pci/drm/radeon/radeon_vm.c

894

radeon_bo_fence(vm->page_tables[i].bo, fence, true);

sys/dev/pci/drm/radeon/radeon_vm.c

94

rdev->vm_manager.enabled = true;

sys/dev/pci/drm/radeon/rs400.c

194

rdev->gart.ready = true;

sys/dev/pci/drm/radeon/rs400.c

288

rdev->mc.vram_is_ddr = true;

sys/dev/pci/drm/radeon/rs400.c

497

rdev->accel_working = true;

sys/dev/pci/drm/radeon/rs400.c

586

rdev->accel_working = true;

sys/dev/pci/drm/radeon/rs600.c

1063

rdev->accel_working = true;

sys/dev/pci/drm/radeon/rs600.c

1154

rdev->accel_working = true;

sys/dev/pci/drm/radeon/rs600.c

368

connected = true;

sys/dev/pci/drm/radeon/rs600.c

373

connected = true;

sys/dev/pci/drm/radeon/rs600.c

622

rdev->gart.ready = true;

sys/dev/pci/drm/radeon/rs600.c

65

return true;

sys/dev/pci/drm/radeon/rs600.c

78

return true;

sys/dev/pci/drm/radeon/rs600.c

801

rdev->pm.vblank_sync = true;

sys/dev/pci/drm/radeon/rs600.c

810

rdev->pm.vblank_sync = true;

sys/dev/pci/drm/radeon/rs600.c

817

queue_hotplug = true;

sys/dev/pci/drm/radeon/rs600.c

821

queue_hotplug = true;

sys/dev/pci/drm/radeon/rs600.c

825

queue_hdmi = true;

sys/dev/pci/drm/radeon/rs600.c

885

rdev->mc.vram_is_ddr = true;

sys/dev/pci/drm/radeon/rs690.c

157

rdev->mc.vram_is_ddr = true;

sys/dev/pci/drm/radeon/rs690.c

194

rdev->fastfb_working = true;

sys/dev/pci/drm/radeon/rs690.c

629

rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, true);

sys/dev/pci/drm/radeon/rs690.c

630

rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, true);

sys/dev/pci/drm/radeon/rs690.c

774

rdev->accel_working = true;

sys/dev/pci/drm/radeon/rs690.c

866

rdev->accel_working = true;

sys/dev/pci/drm/radeon/rs780_dpm.c

1065

rs780_clk_scaling_enable(rdev, true);

sys/dev/pci/drm/radeon/rs780_dpm.c

1069

rs780_voltage_scaling_enable(rdev, true);

sys/dev/pci/drm/radeon/rs780_dpm.c

167

r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);

sys/dev/pci/drm/radeon/rs780_dpm.c

181

r600_dynamicpm_enable(rdev, true);

sys/dev/pci/drm/radeon/rs780_dpm.c

186

r600_enable_spll_bypass(rdev, true);

sys/dev/pci/drm/radeon/rs780_dpm.c

191

r600_enable_spll_bypass(rdev, true);

sys/dev/pci/drm/radeon/rs780_dpm.c

196

r600_enable_sclk_control(rdev, true);

sys/dev/pci/drm/radeon/rs780_dpm.c

276

rs780_voltage_scaling_enable(rdev, true);

sys/dev/pci/drm/radeon/rs780_dpm.c

506

rs780_clk_scaling_enable(rdev, true);

sys/dev/pci/drm/radeon/rs780_dpm.c

617

rs780_clk_scaling_enable(rdev, true);

sys/dev/pci/drm/radeon/rs780_dpm.c

625

r600_gfx_clockgating_enable(rdev, true);

sys/dev/pci/drm/radeon/rs780_dpm.c

870

pi->gfx_clock_gating = true;

sys/dev/pci/drm/radeon/rs780_dpm.c

884

(pi->num_of_cycles_in_period & 0x8000) ? true : false;

sys/dev/pci/drm/radeon/rs780_dpm.c

894

pi->voltage_control = true;

sys/dev/pci/drm/radeon/rs780_dpm.c

901

(pi->num_of_cycles_in_period & 0x8000) ? true : false;

sys/dev/pci/drm/radeon/rs780_dpm.c

911

(pi->system_config & 0x4) ? true : false;

sys/dev/pci/drm/radeon/rs780_dpm.c

912

pi->voltage_control = true;

sys/dev/pci/drm/radeon/rs780_dpm.c

92

r600_engine_clock_entry_enable_post_divider(rdev, 0, true);

sys/dev/pci/drm/radeon/rs780_dpm.c

99

r600_engine_clock_entry_enable(rdev, 0, true);

sys/dev/pci/drm/radeon/rv515.c

169

rdev->mc.vram_is_ddr = true;

sys/dev/pci/drm/radeon/rv515.c

282

save->crtc_enabled[i] = true;

sys/dev/pci/drm/radeon/rv515.c

562

rdev->accel_working = true;

sys/dev/pci/drm/radeon/rv515.c

664

rdev->accel_working = true;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1340

r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1348

r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1363

want_thermal_protection = true;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1368

want_thermal_protection = true;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1374

want_thermal_protection = true;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1475

rv6xx_enable_dynamic_spread_spectrum(rdev, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1500

rv6xx_enable_bif_dynamic_pcie_gen2(rdev, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1502

r600_enable_dynamic_pcie_gen2(rdev, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1554

rv6xx_enable_backbias(rdev, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1557

rv6xx_enable_spread_spectrum(rdev, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1570

rv6xx_enable_display_gap(rdev, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1592

r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1593

r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1594

r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1596

rv6xx_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1604

rv6xx_enable_dynamic_pcie_gen2(rdev, boot_ps, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1607

r600_gfx_clockgating_enable(rdev, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1620

r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1621

r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1639

rv6xx_enable_static_voltage_control(rdev, boot_ps, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1668

r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

170

r600_engine_clock_entry_enable(rdev, step_index, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1705

r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1715

r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1725

rv6xx_enable_dynamic_voltage_control(rdev, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1729

rv6xx_enable_dynamic_backbias_control(rdev, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1732

rv6xx_enable_dynamic_pcie_gen2(rdev, new_ps, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1745

rv6xx_enable_thermal_protection(rdev, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

179

r600_engine_clock_entry_enable_post_divider(rdev, step_index, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1979

pi->gfx_clock_gating = true;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1990

pi->dynamic_ss = true;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1994

pi->dynamic_pcie_gen2 = true;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1998

pi->thermal_protection = true;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

2002

pi->display_gap = true;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

2144

r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

491

(state->high.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

493

(state->high.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

495

(state->medium.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

497

(state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

500

(state->high.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? true : false;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

502

(state->medium.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? true : false;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

504

(state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? true : false;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

577

rv6xx_enable_engine_spread_spectrum(rdev, level, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

611

rv6xx_memory_clock_entry_enable_post_divider(rdev, entry, true);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

695

rv6xx_enable_memory_spread_spectrum(rdev, true);

sys/dev/pci/drm/radeon/rv770.c

1648

rdev->mc.vram_is_ddr = true;

sys/dev/pci/drm/radeon/rv770.c

1870

rdev->accel_working = true;

sys/dev/pci/drm/radeon/rv770.c

1981

rdev->accel_working = true;

sys/dev/pci/drm/radeon/rv770.c

940

rdev->gart.ready = true;

sys/dev/pci/drm/radeon/rv770_dpm.c

1600

pi->mem_gddr5 = true;

sys/dev/pci/drm/radeon/rv770_dpm.c

1615

pi->pcie_gen2 = true;

sys/dev/pci/drm/radeon/rv770_dpm.c

1621

pi->boot_in_gen2 = true;

sys/dev/pci/drm/radeon/rv770_dpm.c

173

dpm_en = true;

sys/dev/pci/drm/radeon/rv770_dpm.c

175

cg_en = true;

sys/dev/pci/drm/radeon/rv770_dpm.c

1759

current_use_dc = true;

sys/dev/pci/drm/radeon/rv770_dpm.c

1762

new_use_dc = true;

sys/dev/pci/drm/radeon/rv770_dpm.c

1788

current_use_dc = true;

sys/dev/pci/drm/radeon/rv770_dpm.c

1791

new_use_dc = true;

sys/dev/pci/drm/radeon/rv770_dpm.c

1826

want_thermal_protection = true;

sys/dev/pci/drm/radeon/rv770_dpm.c

1831

want_thermal_protection = true;

sys/dev/pci/drm/radeon/rv770_dpm.c

1837

want_thermal_protection = true;

sys/dev/pci/drm/radeon/rv770_dpm.c

1908

rv770_enable_voltage_control(rdev, true);

sys/dev/pci/drm/radeon/rv770_dpm.c

1928

rv770_enable_backbias(rdev, true);

sys/dev/pci/drm/radeon/rv770_dpm.c

1930

rv770_enable_spread_spectrum(rdev, true);

sys/dev/pci/drm/radeon/rv770_dpm.c

1933

rv770_enable_thermal_protection(rdev, true);

sys/dev/pci/drm/radeon/rv770_dpm.c

1946

rv770_enable_dynamic_pcie_gen2(rdev, true);

sys/dev/pci/drm/radeon/rv770_dpm.c

1968

rv770_gfx_clock_gating_enable(rdev, true);

sys/dev/pci/drm/radeon/rv770_dpm.c

1971

rv770_mg_clock_gating_enable(rdev, true);

sys/dev/pci/drm/radeon/rv770_dpm.c

1973

rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);

sys/dev/pci/drm/radeon/rv770_dpm.c

1989

rdev->irq.dpm_thermal = true;

sys/dev/pci/drm/radeon/rv770_dpm.c

209

return true;

sys/dev/pci/drm/radeon/rv770_dpm.c

2231

pi->acpi_pcie_gen2 = true;

sys/dev/pci/drm/radeon/rv770_dpm.c

2238

eg_pi->ulv.supported = true;

sys/dev/pci/drm/radeon/rv770_dpm.c

2340

pi->dynamic_ss = true;

sys/dev/pci/drm/radeon/rv770_dpm.c

2404

pi->gfx_clock_gating = true;

sys/dev/pci/drm/radeon/rv770_dpm.c

2406

pi->mg_clock_gating = true;

sys/dev/pci/drm/radeon/rv770_dpm.c

2407

pi->mgcgtssm = true;

sys/dev/pci/drm/radeon/rv770_dpm.c

2409

pi->dynamic_pcie_gen2 = true;

sys/dev/pci/drm/radeon/rv770_dpm.c

2412

pi->thermal_protection = true;

sys/dev/pci/drm/radeon/rv770_dpm.c

2416

pi->display_gap = true;

sys/dev/pci/drm/radeon/rv770_dpm.c

2419

pi->dcodt = true;

sys/dev/pci/drm/radeon/rv770_dpm.c

2423

pi->ulps = true;

sys/dev/pci/drm/radeon/rv770_dpm.c

2584

return true;

sys/dev/pci/drm/radeon/rv770_dpm.c

792

rv740_enable_mclk_spread_spectrum(rdev, true);

sys/dev/pci/drm/radeon/rv770_smc.c

407

return true;

sys/dev/pci/drm/radeon/si.c

1681

new_smc = true;

sys/dev/pci/drm/radeon/si.c

1702

new_smc = true;

sys/dev/pci/drm/radeon/si.c

1721

new_smc = true;

sys/dev/pci/drm/radeon/si.c

1739

new_smc = true;

sys/dev/pci/drm/radeon/si.c

1742

banks2_fw = true;

sys/dev/pci/drm/radeon/si.c

1757

si58_fw = true;

sys/dev/pci/drm/radeon/si.c

1923

rdev->new_fw = true;

sys/dev/pci/drm/radeon/si.c

2234

return true;

sys/dev/pci/drm/radeon/si.c

2243

return true;

sys/dev/pci/drm/radeon/si.c

2269

return true;

sys/dev/pci/drm/radeon/si.c

2321

wm_high.interlaced = true;

sys/dev/pci/drm/radeon/si.c

2334

radeon_dpm_get_mclk(rdev, true) * 10;

sys/dev/pci/drm/radeon/si.c

2336

radeon_dpm_get_sclk(rdev, true) * 10;

sys/dev/pci/drm/radeon/si.c

2348

wm_low.interlaced = true;

sys/dev/pci/drm/radeon/si.c

3345

rdev->scratch.free[i] = true;

sys/dev/pci/drm/radeon/si.c

3563

si_cp_enable(rdev, true);

sys/dev/pci/drm/radeon/si.c

3727

rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;

sys/dev/pci/drm/radeon/si.c

3728

rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;

sys/dev/pci/drm/radeon/si.c

3729

rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;

sys/dev/pci/drm/radeon/si.c

3746

si_enable_gui_idle_interrupt(rdev, true);

sys/dev/pci/drm/radeon/si.c

4079

r600_set_bios_scratch_engine_hung(rdev, true);

sys/dev/pci/drm/radeon/si.c

4192

rdev->mc.vram_is_ddr = true;

sys/dev/pci/drm/radeon/si.c

4349

rdev->gart.ready = true;

sys/dev/pci/drm/radeon/si.c

4395

return true;

sys/dev/pci/drm/radeon/si.c

4399

return true;

sys/dev/pci/drm/radeon/si.c

4430

return true;

sys/dev/pci/drm/radeon/si.c

5174

bool hw_mode = true;

sys/dev/pci/drm/radeon/si.c

5343

si_enable_gui_idle_interrupt(rdev, true);

sys/dev/pci/drm/radeon/si.c

5604

si_enable_mgcg(rdev, true);

sys/dev/pci/drm/radeon/si.c

5605

si_enable_cgcg(rdev, true);

sys/dev/pci/drm/radeon/si.c

5610

si_enable_gui_idle_interrupt(rdev, true);

sys/dev/pci/drm/radeon/si.c

5644

RADEON_CG_BLOCK_HDP), true);

sys/dev/pci/drm/radeon/si.c

5646

si_update_cg(rdev, RADEON_CG_BLOCK_UVD, true);

sys/dev/pci/drm/radeon/si.c

5768

si_enable_dma_pg(rdev, true);

sys/dev/pci/drm/radeon/si.c

5769

si_enable_gfx_cgpg(rdev, true);

sys/dev/pci/drm/radeon/si.c

5812

si_enable_gui_idle_interrupt(rdev, true);

sys/dev/pci/drm/radeon/si.c

5824

return true;

sys/dev/pci/drm/radeon/si.c

5909

rdev->ih.enabled = true;

sys/dev/pci/drm/radeon/si.c

6283

rdev->pm.vblank_sync = true;

sys/dev/pci/drm/radeon/si.c

6323

queue_hotplug = true;

sys/dev/pci/drm/radeon/si.c

6329

queue_dp = true;

sys/dev/pci/drm/radeon/si.c

6397

queue_thermal = true;

sys/dev/pci/drm/radeon/si.c

6401

rdev->pm.dpm.thermal.high_to_low = true;

sys/dev/pci/drm/radeon/si.c

6402

queue_thermal = true;

sys/dev/pci/drm/radeon/si.c

6770

rdev->accel_working = true;

sys/dev/pci/drm/radeon/si.c

6900

rdev->accel_working = true;

sys/dev/pci/drm/radeon/si.c

7362

clk_req_support = true;

sys/dev/pci/drm/radeon/si_dpm.c

1022

true

sys/dev/pci/drm/radeon/si_dpm.c

1039

true

sys/dev/pci/drm/radeon/si_dpm.c

1056

true

sys/dev/pci/drm/radeon/si_dpm.c

1502

true

sys/dev/pci/drm/radeon/si_dpm.c

1532

true

sys/dev/pci/drm/radeon/si_dpm.c

1566

true

sys/dev/pci/drm/radeon/si_dpm.c

1583

true

sys/dev/pci/drm/radeon/si_dpm.c

1678

true

sys/dev/pci/drm/radeon/si_dpm.c

1817

si_pi->dte_data.enable_dte_by_default = true;

sys/dev/pci/drm/radeon/si_dpm.c

1827

update_dte_from_pl2 = true;

sys/dev/pci/drm/radeon/si_dpm.c

1831

update_dte_from_pl2 = true;

sys/dev/pci/drm/radeon/si_dpm.c

1835

update_dte_from_pl2 = true;

sys/dev/pci/drm/radeon/si_dpm.c

1838

if (si_pi->dte_data.enable_dte_by_default == true)

sys/dev/pci/drm/radeon/si_dpm.c

1851

update_dte_from_pl2 = true;

sys/dev/pci/drm/radeon/si_dpm.c

1860

update_dte_from_pl2 = true;

sys/dev/pci/drm/radeon/si_dpm.c

1869

update_dte_from_pl2 = true;

sys/dev/pci/drm/radeon/si_dpm.c

1895

update_dte_from_pl2 = true;

sys/dev/pci/drm/radeon/si_dpm.c

1942

update_dte_from_pl2 = true;

sys/dev/pci/drm/radeon/si_dpm.c

1953

update_dte_from_pl2 = true;

sys/dev/pci/drm/radeon/si_dpm.c

1963

update_dte_from_pl2 = true;

sys/dev/pci/drm/radeon/si_dpm.c

1971

update_dte_from_pl2 = true;

sys/dev/pci/drm/radeon/si_dpm.c

1987

update_dte_from_pl2 = true;

sys/dev/pci/drm/radeon/si_dpm.c

1999

ni_pi->enable_power_containment= true;

sys/dev/pci/drm/radeon/si_dpm.c

2000

ni_pi->enable_cac = true;

sys/dev/pci/drm/radeon/si_dpm.c

2002

si_pi->enable_dte = true;

sys/dev/pci/drm/radeon/si_dpm.c

2007

ni_pi->enable_sq_ramping = true;

sys/dev/pci/drm/radeon/si_dpm.c

2010

ni_pi->driver_calculate_cac_leakage = true;

sys/dev/pci/drm/radeon/si_dpm.c

2011

ni_pi->cac_configuration_required = true;

sys/dev/pci/drm/radeon/si_dpm.c

2014

ni_pi->support_cac_long_term_average = true;

sys/dev/pci/drm/radeon/si_dpm.c

2217

return true;

sys/dev/pci/drm/radeon/si_dpm.c

235

true

sys/dev/pci/drm/radeon/si_dpm.c

2389

ni_pi->pc_enabled = true;

sys/dev/pci/drm/radeon/si_dpm.c

269

true

sys/dev/pci/drm/radeon/si_dpm.c

2757

ni_pi->cac_enabled = true;

sys/dev/pci/drm/radeon/si_dpm.c

286

true

sys/dev/pci/drm/radeon/si_dpm.c

2947

disable_sclk_switching = true;

sys/dev/pci/drm/radeon/si_dpm.c

2962

disable_mclk_switching = true;

sys/dev/pci/drm/radeon/si_dpm.c

2965

disable_mclk_switching = true;

sys/dev/pci/drm/radeon/si_dpm.c

2966

disable_sclk_switching = true;

sys/dev/pci/drm/radeon/si_dpm.c

303

true

sys/dev/pci/drm/radeon/si_dpm.c

3119

ps->dc_compatible = true;

sys/dev/pci/drm/radeon/si_dpm.c

3171

ret = true;

sys/dev/pci/drm/radeon/si_dpm.c

320

true

sys/dev/pci/drm/radeon/si_dpm.c

3234

want_thermal_protection = true;

sys/dev/pci/drm/radeon/si_dpm.c

3238

want_thermal_protection = true;

sys/dev/pci/drm/radeon/si_dpm.c

3243

want_thermal_protection = true;

sys/dev/pci/drm/radeon/si_dpm.c

3313

si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);

sys/dev/pci/drm/radeon/si_dpm.c

3809

strobe_mode = true;

sys/dev/pci/drm/radeon/si_dpm.c

3859

return true;

sys/dev/pci/drm/radeon/si_dpm.c

4106

voltage_found = true;

sys/dev/pci/drm/radeon/si_dpm.c

4121

voltage_found = true;

sys/dev/pci/drm/radeon/si_dpm.c

4966

if (si_get_mclk_frequency_ratio(pl->mclk, true) >=

sys/dev/pci/drm/radeon/si_dpm.c

4968

dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;

sys/dev/pci/drm/radeon/si_dpm.c

4970

dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;

sys/dev/pci/drm/radeon/si_dpm.c

4978

dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;

sys/dev/pci/drm/radeon/si_dpm.c

508

true

sys/dev/pci/drm/radeon/si_dpm.c

5116

return true;

sys/dev/pci/drm/radeon/si_dpm.c

5151

eg_pi->uvd_enabled = true;

sys/dev/pci/drm/radeon/si_dpm.c

5371

bool result = true;

sys/dev/pci/drm/radeon/si_dpm.c

542

true

sys/dev/pci/drm/radeon/si_dpm.c

559

true

sys/dev/pci/drm/radeon/si_dpm.c

5723

si_pi->pspp_notify_required = true;

sys/dev/pci/drm/radeon/si_dpm.c

576

true

sys/dev/pci/drm/radeon/si_dpm.c

5884

vce_v1_0_enable_mgcg(rdev, true);

sys/dev/pci/drm/radeon/si_dpm.c

5920

rdev->irq.dpm_thermal = true;

sys/dev/pci/drm/radeon/si_dpm.c

6057

si_pi->fan_is_controlled_by_smc = true;

sys/dev/pci/drm/radeon/si_dpm.c

6230

si_pi->fan_ctrl_is_in_default_mode = true;

sys/dev/pci/drm/radeon/si_dpm.c

6265

ret = si_thermal_enable_alert(rdev, true);

sys/dev/pci/drm/radeon/si_dpm.c

6303

si_enable_voltage_control(rdev, true);

sys/dev/pci/drm/radeon/si_dpm.c

6319

si_enable_spread_spectrum(rdev, true);

sys/dev/pci/drm/radeon/si_dpm.c

6321

si_enable_thermal_protection(rdev, true);

sys/dev/pci/drm/radeon/si_dpm.c

6399

si_enable_sclk_control(rdev, true);

sys/dev/pci/drm/radeon/si_dpm.c

6402

si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);

sys/dev/pci/drm/radeon/si_dpm.c

6421

ret = si_thermal_enable_alert(rdev, true);

sys/dev/pci/drm/radeon/si_dpm.c

6585

ret = si_enable_smc_cac(rdev, new_ps, true);

sys/dev/pci/drm/radeon/si_dpm.c

6590

ret = si_enable_power_containment(rdev, new_ps, true);

sys/dev/pci/drm/radeon/si_dpm.c

6979

pi->gfx_clock_gating = true;

sys/dev/pci/drm/radeon/si_dpm.c

6981

eg_pi->sclk_deep_sleep = true;

sys/dev/pci/drm/radeon/si_dpm.c

6985

pi->thermal_protection = true;

sys/dev/pci/drm/radeon/si_dpm.c

6989

eg_pi->dynamic_ac_timing = true;

sys/dev/pci/drm/radeon/si_dpm.c

6991

eg_pi->light_sleep = true;

sys/dev/pci/drm/radeon/si_dpm.c

7017

si_pi->fan_ctrl_is_in_default_mode = true;

sys/dev/pci/drm/radeon/si_dpm.c

988

true

sys/dev/pci/drm/radeon/si_smc.c

167

return true;

sys/dev/pci/drm/radeon/sumo_dpm.c

1219

sumo_enable_voltage_scaling(rdev, true);

sys/dev/pci/drm/radeon/sumo_dpm.c

1226

sumo_enable_sclk_ds(rdev, true);

sys/dev/pci/drm/radeon/sumo_dpm.c

1248

rdev->irq.dpm_thermal = true;

sys/dev/pci/drm/radeon/sumo_dpm.c

1323

sumo_enable_boost(rdev, new_ps, true);

sys/dev/pci/drm/radeon/sumo_dpm.c

1361

sumo_take_smu_control(rdev, true);

sys/dev/pci/drm/radeon/sumo_dpm.c

1712

pi->sys_info.enable_boost = true;

sys/dev/pci/drm/radeon/sumo_dpm.c

1755

pi->disable_gfx_power_gating_in_uvd = true;

sys/dev/pci/drm/radeon/sumo_dpm.c

1758

pi->enable_alt_vddnb = true;

sys/dev/pci/drm/radeon/sumo_dpm.c

1759

pi->enable_sclk_ds = true;

sys/dev/pci/drm/radeon/sumo_dpm.c

1761

pi->enable_dynamic_patch_ps = true;

sys/dev/pci/drm/radeon/sumo_dpm.c

1768

pi->enable_gfx_power_gating = true;

sys/dev/pci/drm/radeon/sumo_dpm.c

1769

pi->enable_gfx_clock_gating = true;

sys/dev/pci/drm/radeon/sumo_dpm.c

1770

pi->enable_mg_clock_gating = true;

sys/dev/pci/drm/radeon/sumo_dpm.c

1771

pi->enable_auto_thermal_throttling = true;

sys/dev/pci/drm/radeon/sumo_dpm.c

1791

pi->enable_dpm = true;

sys/dev/pci/drm/radeon/sumo_dpm.c

1935

sumo_power_level_enable(rdev, ps->num_levels - 1, true);

sys/dev/pci/drm/radeon/sumo_dpm.c

1947

sumo_power_level_enable(rdev, 0, true);

sys/dev/pci/drm/radeon/sumo_dpm.c

1958

sumo_power_level_enable(rdev, i, true);

sys/dev/pci/drm/radeon/sumo_dpm.c

1961

sumo_enable_boost(rdev, rps, true);

sys/dev/pci/drm/radeon/sumo_dpm.c

291

sumo_mg_clockgating_enable(rdev, true);

sys/dev/pci/drm/radeon/sumo_dpm.c

293

sumo_gfx_clockgating_enable(rdev, true);

sys/dev/pci/drm/radeon/sumo_dpm.c

295

sumo_gfx_powergating_enable(rdev, true);

sys/dev/pci/drm/radeon/sumo_dpm.c

600

return true;

sys/dev/pci/drm/radeon/sumo_dpm.c

627

sumo_set_forced_mode(rdev, true);

sys/dev/pci/drm/radeon/sumo_dpm.c

658

sumo_power_level_enable(rdev, 0, true);

sys/dev/pci/drm/radeon/sumo_dpm.c

719

sumo_boost_state_enable(rdev, true);

sys/dev/pci/drm/radeon/sumo_dpm.c

761

sumo_power_level_enable(rdev, i, true);

sys/dev/pci/drm/radeon/sumo_dpm.c

827

sumo_gfx_powergating_enable(rdev, true);

sys/dev/pci/drm/radeon/sumo_smc.c

100

return_code = true;

sys/dev/pci/drm/radeon/trinity_dpm.c

1095

rdev->irq.dpm_thermal = true;

sys/dev/pci/drm/radeon/trinity_dpm.c

1237

sumo_take_smu_control(rdev, true);

sys/dev/pci/drm/radeon/trinity_dpm.c

1607

trinity_dce_enable_voltage_adjustment(rdev, true);

sys/dev/pci/drm/radeon/trinity_dpm.c

1922

pi->enable_bapm = true;

sys/dev/pci/drm/radeon/trinity_dpm.c

1928

pi->enable_bapm = true;

sys/dev/pci/drm/radeon/trinity_dpm.c

1930

pi->enable_nbps_policy = true;

sys/dev/pci/drm/radeon/trinity_dpm.c

1931

pi->enable_sclk_ds = true;

sys/dev/pci/drm/radeon/trinity_dpm.c

1932

pi->enable_gfx_power_gating = true;

sys/dev/pci/drm/radeon/trinity_dpm.c

1933

pi->enable_gfx_clock_gating = true;

sys/dev/pci/drm/radeon/trinity_dpm.c

1937

pi->enable_auto_thermal_throttling = true;

sys/dev/pci/drm/radeon/trinity_dpm.c

1939

pi->uvd_dpm = true; /* ??? */

sys/dev/pci/drm/radeon/trinity_dpm.c

1960

pi->enable_dpm = true;

sys/dev/pci/drm/radeon/trinity_dpm.c

508

trinity_ls_clockgating_enable(rdev, true);

sys/dev/pci/drm/radeon/trinity_dpm.c

509

trinity_mg_clockgating_enable(rdev, true);

sys/dev/pci/drm/radeon/trinity_dpm.c

512

trinity_gfx_clockgating_enable(rdev, true);

sys/dev/pci/drm/radeon/trinity_dpm.c

514

trinity_gfx_dynamic_mgpg_enable(rdev, true);

sys/dev/pci/drm/radeon/trinity_dpm.c

516

trinity_gfx_powergating_enable(rdev, true);

sys/dev/pci/drm/radeon/trinity_dpm.c

701

return true;

sys/dev/pci/drm/radeon/trinity_dpm.c

717

trinity_dpm_config(rdev, true);

sys/dev/pci/drm/radeon/trinity_dpm.c

778

trinity_power_level_enable_disable(rdev, 0, true);

sys/dev/pci/drm/radeon/trinity_dpm.c

802

trinity_power_level_enable_disable(rdev, i, true);

sys/dev/pci/drm/radeon/trinity_dpm.c

815

trinity_power_level_enable_disable(rdev, 0, true);

sys/dev/pci/drm/radeon/trinity_dpm.c

851

return true;

sys/dev/pci/drm/radeon/trinity_dpm.c

868

return true;

sys/dev/pci/drm/radeon/trinity_dpm.c

910

trinity_gfx_powergating_enable(rdev, true);

sys/dev/pci/drm/radeon/trinity_dpm.c

952

vce_v1_0_enable_mgcg(rdev, true);

sys/dev/pci/drm/radeon/uvd_v1_0.c

173

ring->ready = true;

sys/dev/pci/drm/radeon/uvd_v2_2.c

88

return true;

sys/dev/pci/drm/radeon/uvd_v3_1.c

55

return true;

sys/dev/pci/drm/radeon/vce_v1_0.c

366

ring->ready = true;

sys/dev/pci/drm/radeon/vce_v1_0.c

374

ring->ready = true;

sys/dev/pci/drm/radeon/vce_v2_0.c

118

vce_v2_0_set_sw_cg(rdev, true);

sys/dev/pci/drm/radeon/vce_v2_0.c

120

vce_v2_0_set_dyn_cg(rdev, true);

sys/dev/pci/drm/scheduler/sched_entity.c

154

return true;

sys/dev/pci/drm/scheduler/sched_entity.c

245

entity->stopped = true;

sys/dev/pci/drm/scheduler/sched_entity.c

253

prev = rcu_dereference_check(entity->last_scheduled, true);

sys/dev/pci/drm/scheduler/sched_entity.c

364

dma_fence_put(rcu_dereference_check(entity->last_scheduled, true));

sys/dev/pci/drm/scheduler/sched_entity.c

456

return true;

sys/dev/pci/drm/scheduler/sched_entity.c

502

dma_fence_put(rcu_dereference_check(entity->last_scheduled, true));

sys/dev/pci/drm/scheduler/sched_entity.c

567

fence = rcu_dereference_check(entity->last_scheduled, true);

sys/dev/pci/drm/scheduler/sched_internal.h

88

return true;

sys/dev/pci/drm/scheduler/sched_main.c

1028

return true;

sys/dev/pci/drm/scheduler/sched_main.c

1352

sched->own_submit_wq = true;

sys/dev/pci/drm/scheduler/sched_main.c

1378

sched->ready = true;

sys/dev/pci/drm/scheduler/sched_main.c

1452

s_entity->stopped = true;

sys/dev/pci/drm/scheduler/sched_main.c

1543

WRITE_ONCE(sched->pause_submit, true);

sys/dev/pci/drm/scheduler/sched_main.c

666

sched->free_guilty = true;

sys/dev/pci/drm/scheduler/sched_main.c

752

found_guilty = true;

sys/dev/pci/drm/ttm/tests/ttm_bo_test.c

189

bool interruptible = true;

sys/dev/pci/drm/ttm/tests/ttm_bo_test.c

42

.no_wait = true,

sys/dev/pci/drm/ttm/tests/ttm_bo_test.c

46

.interruptible = true,

sys/dev/pci/drm/ttm/tests/ttm_bo_test.c

77

bool no_wait = true;

sys/dev/pci/drm/ttm/tests/ttm_bo_test.c

96

bool no_wait = true;

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

510

.with_ttm = true,

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

682

.no_gpu_wait = true,

sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c

961

bo_big->deleted = true;

sys/dev/pci/drm/ttm/tests/ttm_device_test.c

128

.use_dma_alloc = true,

sys/dev/pci/drm/ttm/tests/ttm_device_test.c

129

.use_dma32 = true,

sys/dev/pci/drm/ttm/tests/ttm_device_test.c

130

.pools_init_expected = true,

sys/dev/pci/drm/ttm/tests/ttm_device_test.c

135

.use_dma32 = true,

sys/dev/pci/drm/ttm/tests/ttm_device_test.c

140

.use_dma_alloc = true,

sys/dev/pci/drm/ttm/tests/ttm_device_test.c

142

.pools_init_expected = true,

sys/dev/pci/drm/ttm/tests/ttm_mock_manager.c

118

base->use_tt = true;

sys/dev/pci/drm/ttm/tests/ttm_mock_manager.c

122

ttm_resource_manager_set_used(base, true);

sys/dev/pci/drm/ttm/tests/ttm_mock_manager.c

177

return true;

sys/dev/pci/drm/ttm/tests/ttm_mock_manager.c

204

ttm_resource_manager_set_used(man, true);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

116

.use_dma_alloc = true,

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

121

.use_dma_alloc = true,

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

221

ttm_pool_init(pool, devs->dev, NUMA_NO_NODE, true, false);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

26

.interruptible = true,

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

351

ttm_pool_init(pool, devs->dev, NUMA_NO_NODE, true, false);

sys/dev/pci/drm/ttm/tests/ttm_pool_test.c

89

ttm_pool_init(pool, devs->dev, NUMA_NO_NODE, true, false);

sys/dev/pci/drm/ttm/tests/ttm_resource_test.c

77

ttm_resource_manager_set_used(man, true);

sys/dev/pci/drm/ttm/ttm_bo.c

1183

ret = ttm_bo_handle_move_mem(bo, evict_mem, true, ctx, &hop);

sys/dev/pci/drm/ttm/ttm_bo.c

1250

.trylock_only = true,

sys/dev/pci/drm/ttm/ttm_bo.c

282

bo->deleted = true;

sys/dev/pci/drm/ttm/ttm_bo.c

397

ret = ttm_bo_handle_move_mem(bo, evict_mem, true, ctx, &hop);

sys/dev/pci/drm/ttm/ttm_bo.c

429

return true;

sys/dev/pci/drm/ttm/ttm_bo.c

581

evict_walk.walk.arg.trylock_only = true;

sys/dev/pci/drm/ttm/ttm_bo.c

586

evict_walk.try_low = true;

sys/dev/pci/drm/ttm/ttm_bo.c

607

evict_walk.try_low = true;

sys/dev/pci/drm/ttm/ttm_bo.c

887

ret = ttm_tt_create(bo, true);

sys/dev/pci/drm/ttm/ttm_bo_util.c

1008

bo_locked = true;

sys/dev/pci/drm/ttm/ttm_bo_util.c

779

ret = ttm_tt_create(bo, true);

sys/dev/pci/drm/ttm/ttm_bo_util.c

801

ret = ttm_tt_create(bo, true);

sys/dev/pci/drm/ttm/ttm_bo_util.c

835

curs->needs_unlock = true;

sys/dev/pci/drm/ttm/ttm_bo_util.c

836

return true;

sys/dev/pci/drm/ttm/ttm_bo_util.c

841

return true;

sys/dev/pci/drm/ttm/ttm_bo_util.c

860

curs->needs_unlock = true;

sys/dev/pci/drm/ttm/ttm_bo_vm.c

225

.interruptible = true,

sys/dev/pci/drm/ttm/ttm_bo_vm.c

378

(void) dma_fence_wait(bo->moving, true);

sys/dev/pci/drm/ttm/ttm_bo_vm.c

380

DMA_RESV_USAGE_KERNEL, true,

sys/dev/pci/drm/ttm/ttm_bo_vm.c

391

err = dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_KERNEL, true,

sys/dev/pci/drm/ttm/ttm_bo_vm.c

527

.interruptible = true,

sys/dev/pci/drm/ttm/ttm_bo_vm.c

68

DMA_RESV_USAGE_KERNEL, true,

sys/dev/pci/drm/ttm/ttm_bo_vm.c

708

ret = ttm_bo_reserve(bo, true, false, NULL);

sys/dev/pci/drm/ttm/ttm_bo_vm.c

78

err = dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_KERNEL, true,

sys/dev/pci/drm/ttm/ttm_pool.c

887

allow_pools = true;

sys/dev/pci/drm/ttm/ttm_pool.c

914

allow_pools = true;

sys/dev/pci/drm/ttm/ttm_range_manager.c

131

return true;

sys/dev/pci/drm/ttm/ttm_range_manager.c

146

return true;

sys/dev/pci/drm/ttm/ttm_range_manager.c

202

ttm_resource_manager_set_used(man, true);

sys/dev/pci/drm/ttm/ttm_resource.c

453

return true;

sys/dev/pci/drm/ttm/ttm_resource.c

498

return true;

sys/dev/pci/drm/ttm/ttm_resource.c

844

iter_io->needs_unmap = true;

sys/dev/pci/drm/ttm/ttm_sys_manager.c

43

man->use_tt = true;

sys/dev/pci/drm/ttm/ttm_sys_manager.c

48

ttm_resource_manager_set_used(man, true);

sys/dev/pci/drm/ttm/ttm_tt.c

569

.maps_tt = true,

sys/dev/pci/if_aq_pci.c

1726

sc->sc_fast_start_enabled = true;

sys/dev/pci/if_bnxt.c

3115

if (shutdown == true)

sys/dev/pci/if_ice.c

10029

found = true;

sys/dev/pci/if_ice.c

1045

ice_msec_delay(100, true);

sys/dev/pci/if_ice.c

1076

ice_msec_delay(10, true);

sys/dev/pci/if_ice.c

1130

ice_msec_delay(1, true);

sys/dev/pci/if_ice.c

11336

is_tx_fltr = true;

sys/dev/pci/if_ice.c

11343

is_tx_fltr = true;

sys/dev/pci/if_ice.c

11350

is_tx_fltr = true;

sys/dev/pci/if_ice.c

11354

is_rx_lb_fltr = true;

sys/dev/pci/if_ice.c

11362

is_tx_fltr = true;

sys/dev/pci/if_ice.c

11484

is_tx_fltr = true;

sys/dev/pci/if_ice.c

11486

is_rx_lb_fltr = true;

sys/dev/pci/if_ice.c

11555

status = ice_update_vsi_list_rule(hw, &vsi_handle, 1, vsi_list_id, true,

sys/dev/pci/if_ice.c

11577

vsi_list_id, true,

sys/dev/pci/if_ice.c

11655

remove_rule = true;

sys/dev/pci/if_ice.c

11666

remove_rule = true;

sys/dev/pci/if_ice.c

11679

remove_rule = true;

sys/dev/pci/if_ice.c

12287

apply_speed_filter = true;

sys/dev/pci/if_ice.c

13099

err = ice_control_all_rx_queues(&sc->pf_vsi, true);

sys/dev/pci/if_ice.c

13124

ice_set_link(sc, true);

sys/dev/pci/if_ice.c

14537

return true;

sys/dev/pci/if_ice.c

14541

return true;

sys/dev/pci/if_ice.c

14544

return true;

sys/dev/pci/if_ice.c

14987

ice_msec_delay(100, true);

sys/dev/pci/if_ice.c

15069

status = ice_get_set_tx_topo(hw, new_topo, size, NULL, NULL, true);

sys/dev/pci/if_ice.c

15077

ice_msec_delay(100, true);

sys/dev/pci/if_ice.c

15189

return true;

sys/dev/pci/if_ice.c

15386

return seg_hdr ? true : false;

sys/dev/pci/if_ice.c

15503

result = true;

sys/dev/pci/if_ice.c

15525

match = true;

sys/dev/pci/if_ice.c

15599

return true;

sys/dev/pci/if_ice.c

15607

return true;

sys/dev/pci/if_ice.c

16119

hw->tnl.tbl[i].valid = true;

sys/dev/pci/if_ice.c

16375

true);

sys/dev/pci/if_ice.c

16639

return true;

sys/dev/pci/if_ice.c

16665

return true;

sys/dev/pci/if_ice.c

16779

state = ice_dwnld_cfg_bufs_no_lock(hw, bufs, 0, count, true);

sys/dev/pci/if_ice.c

16856

hw->dvm_ena = ice_aq_is_dvm_ena(hw) ? true : false;

sys/dev/pci/if_ice.c

17020

hw->blk[blk].xlt1.ptg_tbl[ptg].in_use = true;

sys/dev/pci/if_ice.c

1706

return true;

sys/dev/pci/if_ice.c

17180

hw->blk[blk].xlt2.vsig_tbl[idx].in_use = true;

sys/dev/pci/if_ice.c

17601

flag = true;

sys/dev/pci/if_ice.c

17683

already_loaded = true;

sys/dev/pci/if_ice.c

17893

status = ice_aq_get_link_info(hw->port_info, true, NULL, NULL);

sys/dev/pci/if_ice.c

18052

resmgr->contig_only = true;

sys/dev/pci/if_ice.c

18504

return true;

sys/dev/pci/if_ice.c

18667

return true;

sys/dev/pci/if_ice.c

18989

status = ice_alloc_tcam_ent(hw, blk, true, &tcam->tcam_idx);

sys/dev/pci/if_ice.c

19007

p->add_tcam_idx = true;

sys/dev/pci/if_ice.c

19077

status = ice_prof_tcam_ena_dis(hw, blk, true,

sys/dev/pci/if_ice.c

19229

return true;

sys/dev/pci/if_ice.c

19321

status = ice_alloc_tcam_ent(hw, blk, true, &tcam_idx);

sys/dev/pci/if_ice.c

19330

t->tcam[i].in_use = true;

sys/dev/pci/if_ice.c

19333

p->add_tcam_idx = true;

sys/dev/pci/if_ice.c

19404

true, chg);

sys/dev/pci/if_ice.c

20065

return true;

sys/dev/pci/if_ice.c

20378

return true;

sys/dev/pci/if_ice.c

2044

cmd_completed = true;

sys/dev/pci/if_ice.c

2051

ice_debug_cq(hw, cq, (void *)desc, buf, buf_size, true);

sys/dev/pci/if_ice.c

20703

return true;

sys/dev/pci/if_ice.c

21420

ctx->alloc_from_pool = true;

sys/dev/pci/if_ice.c

22338

true);

sys/dev/pci/if_ice.c

22356

vsi_node->in_use = true;

sys/dev/pci/if_ice.c

22377

vsi_node->in_use = true;

sys/dev/pci/if_ice.c

23356

status = ice_lldp_fltr_add_remove(hw, vsi_num, true);

sys/dev/pci/if_ice.c

23411

status = ice_aq_get_link_info(pi, true, NULL, NULL);

sys/dev/pci/if_ice.c

24142

update_media = true;

sys/dev/pci/if_ice.c

24207

keys, true);

sys/dev/pci/if_ice.c

25396

hw->blk[blk].es.written[map->prof_id] = true;

sys/dev/pci/if_ice.c

26299

return ice_aq_get_set_rss_lut(hw, set_params, true);

sys/dev/pci/if_ice.c

2646

ice_msec_delay(delay, true);

sys/dev/pci/if_ice.c

26561

sc->hw.port_info->phy.get_link_info = true;

sys/dev/pci/if_ice.c

26563

ice_update_link_status(sc, true);

sys/dev/pci/if_ice.c

26763

mdd_detected = true;

sys/dev/pci/if_ice.c

26789

mdd_detected = true;

sys/dev/pci/if_ice.c

26813

mdd_detected = true;

sys/dev/pci/if_ice.c

26826

request_reinit = true;

sys/dev/pci/if_ice.c

26835

request_reinit = true;

sys/dev/pci/if_ice.c

26844

request_reinit = true;

sys/dev/pci/if_ice.c

26933

pi->phy.get_link_info = true;

sys/dev/pci/if_ice.c

2694

ice_msec_delay(1, true);

sys/dev/pci/if_ice.c

2718

return true;

sys/dev/pci/if_ice.c

27953

needs_reconfig = true;

sys/dev/pci/if_ice.c

27962

needs_reconfig = true;

sys/dev/pci/if_ice.c

27970

needs_reconfig = true;

sys/dev/pci/if_ice.c

27977

needs_reconfig = true;

sys/dev/pci/if_ice.c

28441

ice_debug_cq(hw, cq, (void *)desc, e->msg_buf, cq->rq_buf_size, true);

sys/dev/pci/if_ice.c

28577

pi->phy.get_link_info = true;

sys/dev/pci/if_ice.c

28829

sc->stats.offsets_loaded = true;

sys/dev/pci/if_ice.c

28881

vsi->hw_stats.offsets_loaded = true;

sys/dev/pci/if_ice.c

28973

reschedule = true;

sys/dev/pci/if_ice.c

28977

reschedule = true;

sys/dev/pci/if_ice.c

29203

hw->reset_ongoing = true;

sys/dev/pci/if_ice.c

2979

ice_shutdown_ctrlq(hw, ICE_CTL_Q_ADMIN, true);

sys/dev/pci/if_ice.c

2980

ice_msec_delay(ICE_CTL_Q_ADMIN_INIT_MSEC, true);

sys/dev/pci/if_ice.c

29997

*dcbx_agent_status = true;

sys/dev/pci/if_ice.c

30043

status = ice_aq_start_stop_dcbx(hw, true, &dcbx_agent_status,

sys/dev/pci/if_ice.c

30097

qos_cfg->is_sw_lldp = true;

sys/dev/pci/if_ice.c

30116

ret = ice_aq_cfg_lldp_mib_change(hw, true, NULL);

sys/dev/pci/if_ice.c

30118

qos_cfg->is_sw_lldp = true;

sys/dev/pci/if_ice.c

30181

status = ice_init_dcb(hw, true);

sys/dev/pci/if_ice.c

3040

ice_shutdown_all_ctrlq(hw, true);

sys/dev/pci/if_ice.c

30450

pi->phy.get_link_info = true;

sys/dev/pci/if_ice.c

30709

ice_update_link_status(sc, true);

sys/dev/pci/if_ice.c

3147

hw->fwlog_support_ena = true;

sys/dev/pci/if_ice.c

3255

return true;

sys/dev/pci/if_ice.c

3284

return true;

sys/dev/pci/if_ice.c

3353

status = ice_aq_fwlog_register(hw, true);

sys/dev/pci/if_ice.c

3466

second_bank_active = true;

sys/dev/pci/if_ice.c

3679

(uint8_t *)&data_local, true);

sys/dev/pci/if_ice.c

4406

flash->blank_nvm_mode = true;

sys/dev/pci/if_ice.c

4626

bool found = true;

sys/dev/pci/if_ice.c

4719

true : false;

sys/dev/pci/if_ice.c

4724

true : false;

sys/dev/pci/if_ice.c

4729

true : false;

sys/dev/pci/if_ice.c

4734

true : false;

sys/dev/pci/if_ice.c

4754

caps->led[phys_id] = true;

sys/dev/pci/if_ice.c

4762

caps->sdp[phys_id] = true;

sys/dev/pci/if_ice.c

4994

ice_print_led_caps(hw, &func_p->common_cap, "func caps", true);

sys/dev/pci/if_ice.c

4995

ice_print_sdp_caps(hw, &func_p->common_cap, "func caps", true);

sys/dev/pci/if_ice.c

5176

ice_print_led_caps(hw, &dev_p->common_cap, "dev caps", true);

sys/dev/pci/if_ice.c

5177

ice_print_sdp_caps(hw, &dev_p->common_cap, "dev caps", true);

sys/dev/pci/if_ice.c

5493

is_vf = true;

sys/dev/pci/if_ice.c

5902

node->in_use = true;

sys/dev/pci/if_ice.c

6424

return true;

sys/dev/pci/if_ice.c

6427

return true;

sys/dev/pci/if_ice.c

6429

return true;

sys/dev/pci/if_ice.c

6451

return true;

sys/dev/pci/if_ice.c

6453

return true;

sys/dev/pci/if_ice.c

6455

return true;

sys/dev/pci/if_ice.c

6626

return true;

sys/dev/pci/if_ice.c

7177

return true;

sys/dev/pci/if_ice.c

7475

false, true },

sys/dev/pci/if_ice.c

7477

true, true },

sys/dev/pci/if_ice.c

7560

hw->blk[i].is_list_init = true;

sys/dev/pci/if_ice.c

7736

hw->evb_veb = true;

sys/dev/pci/if_ice.c

8115

fi->lb_en = true;

sys/dev/pci/if_ice.c

8145

fi->lan_en = true;

sys/dev/pci/if_ice.c

8147

fi->lan_en = true;

sys/dev/pci/if_ice.c

8156

fi->lan_en = true;

sys/dev/pci/if_ice.c

9319

return true;

sys/dev/pci/if_ice.c

9328

return true;

sys/dev/pci/if_icevar.h

175

return true;

sys/dev/pci/if_icevar.h

183

return true;

sys/dev/pci/if_icevar.h

561

return true;

sys/dev/pci/if_igc.c

1630

if (hw->mac.get_link_status == true)

sys/dev/pci/if_igc.c

1800

sc->hw.mac.get_link_status = true;

sys/dev/pci/if_igc.c

219

if (igc_setup_init_funcs(hw, true)) {

sys/dev/pci/if_igc.c

248

sc->hw.dev_spec._i225.eee_disable = true;

sys/dev/pci/if_igc.c

285

hw->mac.get_link_status = true;

sys/dev/pci/if_igc.c

544

hw->fc.send_xon = true;

sys/dev/pci/if_igc.c

917

igc_set_eee_i225(&sc->hw, true, true, true);

sys/dev/pci/if_igc.h

138

#define DO_AUTO_NEG true

sys/dev/pci/if_iwx.c

12390

sc->sc_low_latency_xtal = true;

sys/dev/pci/if_iwx.c

1463

fw->dbg_dest_tlv_init = true;

sys/dev/pci/if_iwxvar.h

502

.tx_with_siso_diversity = true,

sys/dev/pci/if_iwxvar.h

515

.tx_with_siso_diversity = true,

sys/dev/pci/if_mwx.c

4065

rv = mt7921_mcu_uni_bss_bcnft(dev, vif, true);

sys/dev/pci/if_mwx.c

4425

cck = true;

sys/dev/pci/if_ngbe.c

583

hw->mac.autotry_restart = true;

sys/dev/pci/if_qwx_pci.c

2141

qwx_pci_msi_config(sc, true);

sys/dev/pci/if_qwx_pci.c

2190

qwx_pci_sw_reset(sc, true);

sys/dev/pci/if_qwz_pci.c

2008

qwz_pci_msi_config(sc, true);

sys/dev/pci/if_qwz_pci.c

2057

qwz_pci_sw_reset(sc, true);

sys/dev/pci/igc_i225.c

114

dev_spec->clear_semaphore_once = true;

sys/dev/pci/igc_i225.c

118

mac->asf_firmware_present = true;

sys/dev/pci/igc_i225.c

687

ret_val = true;

sys/dev/pci/igc_phy.c

511

hw->mac.get_link_status = true;

sys/dev/pci/igc_phy.c

910

return __igc_access_xmdio_reg(hw, addr, dev_addr, data, true);

sys/dev/usb/dwc2/dwc2.c

1205

qh_allocated = true;

sys/dev/usb/dwc2/dwc2.c

1344

sc->sc_hcdenabled = true;

sys/dev/usb/dwc2/dwc2_core.c

388

return true;

sys/dev/usb/dwc2/dwc2_core.c

453

wait_for_host_mode = true;

sys/dev/usb/dwc2/dwc2_core.c

507

dwc2_wait_for_mode(hsotg, true);

sys/dev/usb/dwc2/dwc2_core.c

875

return true;

sys/dev/usb/dwc2/dwc2_core.c

95

gr->valid = true;

sys/dev/usb/dwc2/dwc2_coreintr.c

330

true);

sys/dev/usb/dwc2/dwc2_coreintr.c

440

true);

sys/dev/usb/dwc2/dwc2_coreintr.c

459

true);

sys/dev/usb/dwc2/dwc2_coreintr.c

554

usb_phy_set_suspend(hsotg->uphy, true);

sys/dev/usb/dwc2/dwc2_hcd.c

2962

no_queue_space = true;

sys/dev/usb/dwc2/dwc2_hcd.c

2991

no_fifo_space = true;

sys/dev/usb/dwc2/dwc2_hcd.c

3431

ret = dwc2_exit_partial_power_down(hsotg, 0, true);

sys/dev/usb/dwc2/dwc2_hcd.c

3683

hsotg->params.dma_desc_enable = true;

sys/dev/usb/dwc2/dwc2_hcd.c

3752

true);

sys/dev/usb/dwc2/dwc2_hcd.c

4472

dwc2_hcd_disconnect(hsotg, true);

sys/dev/usb/dwc2/dwc2_hcd.c

4556

usb_phy_set_suspend(hsotg->uphy, true);

sys/dev/usb/dwc2/dwc2_hcd.c

4597

ret = dwc2_exit_partial_power_down(hsotg, 0, true);

sys/dev/usb/dwc2/dwc2_hcd.c

4810

retval = dwc2_exit_partial_power_down(hsotg, 0, true);

sys/dev/usb/dwc2/dwc2_hcd.c

4903

qh_allocated = true;

sys/dev/usb/dwc2/dwc2_hcd.c

5301

retval = dwc2_core_init(hsotg, true);

sys/dev/usb/dwc2/dwc2_hcd.c

5467

hr->valid = true;

sys/dev/usb/dwc2/dwc2_hcd.c

5749

return true;

sys/dev/usb/dwc2/dwc2_hcd.c

5760

return true;

sys/dev/usb/dwc2/dwc2_hcd.c

5829

hsotg->bus_suspended = true;

sys/dev/usb/dwc2/dwc2_hcd.c

5953

hsotg->bus_suspended = true;

sys/dev/usb/dwc2/dwc2_hcd.h

618

static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; }

sys/dev/usb/dwc2/dwc2_hcd.h

619

static inline bool dbg_qh(struct dwc2_qh *qh) { return true; }

sys/dev/usb/dwc2/dwc2_hcd.h

620

static inline bool dbg_urb(struct urb *urb) { return true; }

sys/dev/usb/dwc2/dwc2_hcd.h

621

static inline bool dbg_perio(void) { return true; }

sys/dev/usb/dwc2/dwc2_hcdintr.c

1847

return true;

sys/dev/usb/dwc2/dwc2_hcdintr.c

412

hsotg->new_connection = true;

sys/dev/usb/dwc2/dwc2_hcdqueue.c

1788

qh->wait_timer_cancel = true;

sys/dev/usb/dwc2/dwc2_hcdqueue.c

488

printed = true;

sys/dev/usb/dwc2/dwc2_hcdqueue.c

965

err = dwc2_hs_pmap_schedule(hsotg, qh, true, i);

sys/dev/usb/dwc2/dwc2_params.c

121

p->change_speed_quirk = true;

sys/dev/usb/dwc2/dwc2_params.c

171

p->no_clock_gating = true;

sys/dev/usb/dwc2/dwc2_params.c

180

p->no_clock_gating = true;

sys/dev/usb/dwc2/dwc2_params.c

259

p->activate_stm_fs_transceiver = true;

sys/dev/usb/dwc2/dwc2_params.c

285

p->activate_stm_fs_transceiver = true;

sys/dev/usb/dwc2/dwc2_params.c

286

p->activate_stm_id_vb_detection = true;

sys/dev/usb/dwc2/dwc2_params.c

289

p->host_support_fs_ls_low_power = true;

sys/dev/usb/dwc2/dwc2_params.c

290

p->host_ls_low_power_phy_clk = true;

sys/dev/usb/dwc2/dwc2_params.c

364

hsotg->params.otg_caps.hnp_support = true;

sys/dev/usb/dwc2/dwc2_params.c

365

hsotg->params.otg_caps.srp_support = true;

sys/dev/usb/dwc2/dwc2_params.c

371

hsotg->params.otg_caps.srp_support = true;

sys/dev/usb/dwc2/dwc2_params.c

473

p->lpm_clock_gating = true;

sys/dev/usb/dwc2/dwc2_params.c

474

p->besl = true;

sys/dev/usb/dwc2/dwc2_params.c

475

p->hird_threshold_en = true;

sys/dev/usb/dwc2/dwc2_params.c

513

p->uframe_sched = true;

sys/dev/usb/dwc2/dwc2_params.c

592

p->oc_disable = true;

sys/dev/usb/dwc2/dwc2_params.c

868

dwc2_force_mode(hsotg, true);

sys/dev/usb/ukspan.c

558

ukspan_cmsg_init(true, &sc->cmsg);

sys/kern/kern_rwlock.c

768

return true;

sys/net/pfvar.h

1796

#define PF_HI (true)

sys/sys/types.h

252

#define true true

usr.bin/awk/awkgram.y

186

| FUNC funcname '(' varlist rparen {infunc = true;} lbrace stmtlist '}'

usr.bin/awk/b.c

1470

digitfound = true;

usr.bin/awk/b.c

1476

commafound = true;

usr.bin/awk/b.c

960

return true;

usr.bin/awk/lex.c

348

sc = true;

usr.bin/awk/lex.c

557

reg = true;

usr.bin/awk/lib.c

112

innew = true;

usr.bin/awk/lib.c

137

static bool firsttime = true;

usr.bin/awk/lib.c

173

innew = true;

usr.bin/awk/lib.c

192

donerec = true;

usr.bin/awk/lib.c

232

isrec = (c == EOF && rr == buf) ? false : true;

usr.bin/awk/lib.c

248

isrec = (found == 0 && *buf == '\0') ? false : true;

usr.bin/awk/lib.c

278

isrec = (c == EOF && rr == buf) ? false : true;

usr.bin/awk/lib.c

498

donefld = true;

usr.bin/awk/lib.c

509

donerec = true; /* restore */

usr.bin/awk/lib.c

669

donerec = true;

usr.bin/awk/main.c

196

CSV = true;

usr.bin/awk/main.c

204

safe = true;

usr.bin/awk/run.c

1088

static bool first = true;

usr.bin/awk/run.c

199

while (getrec(&record, &recsize, true) > 0) {

usr.bin/awk/run.c

2425

*pnewflag = true;

usr.bin/awk/run.c

2450

stat = true;

usr.bin/awk/run.c

450

n = getrec(&record, &recsize, true);

usr.bin/awk/tran.c

317

donerec = true;

usr.bin/awk/tran.c

366

donerec = true;

usr.bin/awk/tran.c

403

if (is_valid_number(vp->sval, true, & no_trailing, & fval)) {

usr.bin/bc/bc.y

103

static bool do_fork = true;

usr.bin/bc/bc.y

273

st_has_continue = true;

usr.bin/chpass/getpwent.c

233

return getpwnam_internal(name, pw, buf, buflen, pwretp, false, true);

usr.bin/chpass/getpwent.c

256

my_errno = getpwnam_internal(name, NULL, NULL, 0, &pw, true, false);

usr.bin/chpass/getpwent.c

308

return getpwuid_internal(uid, pw, buf, buflen, pwretp, false, true);

usr.bin/chpass/getpwent.c

331

my_errno = getpwuid_internal(uid, NULL, NULL, 0, &pw, true, false);

usr.bin/chpass/getpwent.c

77

bool remap = true;

usr.bin/dc/bcode.c

222

bmachine.interrupted = true;

usr.bin/dc/dc.c

63

extended_regs = true;

usr.bin/dc/inout.c

197

sign = true;

usr.bin/dc/inout.c

202

dot = true;

usr.bin/dc/inout.c

252

escape = true;

usr.bin/grep/util.c

639

return true;

usr.bin/indent/args.c

102

{"ei", PRO_BOOL, true, ON, &ps.else_if },

usr.bin/indent/args.c

106

{"fc1", PRO_BOOL, true, ON, &format_col1_comments },

usr.bin/indent/args.c

110

{"ip", PRO_BOOL, true, ON, &ps.indent_parameters },

usr.bin/indent/args.c

113

{"lp", PRO_BOOL, true, ON, &lineup_to_parens },

usr.bin/indent/args.c

122

{"nbc", PRO_BOOL, true, ON, &ps.leave_comma },

usr.bin/indent/args.c

124

{"ncdb", PRO_BOOL, true, OFF, &comment_delimiter_on_blankline },

usr.bin/indent/args.c

125

{"nce", PRO_BOOL, true, OFF, &cuddle_else },

usr.bin/indent/args.c

128

{"nei", PRO_BOOL, true, OFF, &ps.else_if },

usr.bin/indent/args.c

129

{"nfc1", PRO_BOOL, true, OFF, &format_col1_comments },

usr.bin/indent/args.c

130

{"nip", PRO_BOOL, true, OFF, &ps.indent_parameters },

usr.bin/indent/args.c

131

{"nlp", PRO_BOOL, true, OFF, &lineup_to_parens },

usr.bin/indent/args.c

134

{"npsl", PRO_BOOL, true, OFF, &procnames_start_line },

usr.bin/indent/args.c

136

{"nsc", PRO_BOOL, true, OFF, &star_comment_cont },

usr.bin/indent/args.c

138

{"nut", PRO_BOOL, true, OFF, &use_tabs},

usr.bin/indent/args.c

141

{"psl", PRO_BOOL, true, ON, &procnames_start_line },

usr.bin/indent/args.c

143

{"sc", PRO_BOOL, true, ON, &star_comment_cont },

usr.bin/indent/args.c

147

{"ut", PRO_BOOL, true, ON, &use_tabs},

usr.bin/indent/args.c

219

return (true);

usr.bin/indent/args.c

292

*p->p_obj = true;

usr.bin/indent/args.c

88

{"bc", PRO_BOOL, true, OFF, &ps.leave_comma },

usr.bin/indent/args.c

89

{"bl", PRO_BOOL, true, OFF, &btype_2 },

usr.bin/indent/args.c

90

{"br", PRO_BOOL, true, ON, &btype_2 },

usr.bin/indent/args.c

92

{"cdb", PRO_BOOL, true, ON, &comment_delimiter_on_blankline },

usr.bin/indent/args.c

94

{"ce", PRO_BOOL, true, ON, &cuddle_else },

usr.bin/indent/indent.c

1007

ps.in_or_st = true; /* this might be a structure or initialization

usr.bin/indent/indent.c

1009

ps.in_decl = ps.decl_on_line = true;

usr.bin/indent/indent.c

1085

force_nl = true;

usr.bin/indent/indent.c

1086

ps.last_u_d = true;

usr.bin/indent/indent.c

1108

ps.want_blank = true;

usr.bin/indent/indent.c

1132

force_nl = true;

usr.bin/indent/indent.c

215

ps.last_nl = true; /* this is true if the last thing scanned was

usr.bin/indent/indent.c

247

ps.bl_line = true;

usr.bin/indent/indent.c

422

flushed_nl = true;

usr.bin/indent/indent.c

480

force_nl = true;

usr.bin/indent/indent.c

564

ps.in_stmt = true; /* turn on flag which causes an extra level of

usr.bin/indent/indent.c

593

ps.use_ff = true; /* a form feed is treated much like a newline */

usr.bin/indent/indent.c

652

ps.last_u_d = true;

usr.bin/indent/indent.c

664

ps.want_blank = true;

usr.bin/indent/indent.c

669

force_nl = true;/* must force newline after if */

usr.bin/indent/indent.c

670

ps.last_u_d = true; /* inform lexi that a following

usr.bin/indent/indent.c

749

ps.want_blank = true;

usr.bin/indent/indent.c

755

ps.want_blank = true;

usr.bin/indent/indent.c

765

ps.want_blank = true;

usr.bin/indent/indent.c

769

scase = true; /* so we can process the later colon properly */

usr.bin/indent/indent.c

778

ps.want_blank = true;

usr.bin/indent/indent.c

843

ps.want_blank = true;

usr.bin/indent/indent.c

849

force_nl = true;/* force newline after a end of stmt */

usr.bin/indent/indent.c

856

force_nl = true;/* force other stuff on same line as '{' onto

usr.bin/indent/indent.c

933

ps.want_blank = true;

usr.bin/indent/indent.c

940

ps.in_decl = true;

usr.bin/indent/indent.c

951

sp_sw = true;

usr.bin/indent/indent.c

957

sp_sw = true; /* the interesting stuff is done after the

usr.bin/indent/indent.c

976

force_nl = true;/* also, following stuff must go onto new line */

usr.bin/indent/indent.c

987

force_nl = true;/* also, following stuff must go onto new line */

usr.bin/indent/io.c

361

had_eof = true;

usr.bin/indent/io.c

71

ps.bl_line = true;

usr.bin/indent/lexi.c

230

ps.last_u_d = true;

usr.bin/indent/lexi.c

257

ps.its_a_keyword = true;

usr.bin/indent/lexi.c

258

ps.last_u_d = true;

usr.bin/indent/lexi.c

268

l_struct = true;

usr.bin/indent/lexi.c

289

ps.sizeof_keyword = true;

usr.bin/indent/lexi.c

317

ps.its_a_keyword = true;

usr.bin/indent/lexi.c

318

ps.last_u_d = true;

usr.bin/indent/lexi.c

324

ps.last_u_d = true; /* will make "int a -1" work */

usr.bin/indent/lexi.c

340

ps.last_nl = true; /* remember that we just had a newline */

usr.bin/indent/lexi.c

399

unary_delim = true;

usr.bin/indent/lexi.c

414

unary_delim = true;

usr.bin/indent/lexi.c

420

unary_delim = true;

usr.bin/indent/lexi.c

424

unary_delim = true;

usr.bin/indent/lexi.c

429

unary_delim = true;

usr.bin/indent/lexi.c

439

unary_delim = true;

usr.bin/indent/lexi.c

446

ps.last_nl = true; /* remember this so we can set 'ps.col_1'

usr.bin/indent/lexi.c

452

unary_delim = true;

usr.bin/indent/lexi.c

464

unary_delim = true;

usr.bin/indent/lexi.c

510

unary_delim = true;

usr.bin/indent/lexi.c

525

unary_delim = true;

usr.bin/indent/lexi.c

549

unary_delim = true;

usr.bin/indent/parse.c

66

break_comma = true; /* while in declaration, newline should be

usr.bin/indent/pr_comment.c

106

ps.box_com = true;

usr.bin/indent/pr_comment.c

111

ps.box_com = true; /* a comment with a '-', '*' or newline

usr.bin/indent/pr_comment.c

181

ps.use_ff = true;

usr.bin/jot/jot.c

102

chardata = true;

usr.bin/jot/jot.c

116

randomize = true;

usr.bin/jot/jot.c

122

word = true;

usr.bin/jot/jot.c

168

infinity = true;

usr.bin/jot/jot.c

223

infinity = true;

usr.bin/jot/jot.c

395

longdata = true;

usr.bin/jot/jot.c

404

intdata = true;

usr.bin/jot/jot.c

410

intdata = nosign = true;

usr.bin/jot/jot.c

415

longdata = intdata = true; /* same as %ld */

usr.bin/jot/jot.c

421

longdata = intdata = nosign = true; /* same as %l[ou] */

usr.bin/jot/jot.c

426

chardata = true;

usr.bin/jot/jot.c

67

static bool finalnl = true;

usr.bin/jot/jot.c

97

boring = true;

usr.bin/lex/ccl.c

298

return true;

usr.bin/lex/ccl.c

314

return (isupper(c) || islower(c)) ? true : false;

usr.bin/lex/ccl.c

75

ccl_has_nl[cclp] = true;

usr.bin/lex/dfa.c

290

did_stk_init = true;

usr.bin/lex/dfa.c

475

use_NUL_table = true;

usr.bin/lex/dfa.c

904

rule_useful[accset[i]] = true;

usr.bin/lex/dfa.c

923

rule_useful[j] = true;

usr.bin/lex/filter.c

141

return true;

usr.bin/lex/filter.c

196

return true;

usr.bin/lex/filter.c

346

bool in_gen = true; /* in generated code */

usr.bin/lex/filter.c

395

in_gen = true;

usr.bin/lex/filter.c

415

last_was_blank = true;

usr.bin/lex/flexdef.h

1099

#define b_isalnum(c) (isalnum(c)?true:false)

usr.bin/lex/flexdef.h

1100

#define b_isalpha(c) (isalpha(c)?true:false)

usr.bin/lex/flexdef.h

1101

#define b_isascii(c) (isascii(c)?true:false)

usr.bin/lex/flexdef.h

1102

#define b_isblank(c) (isblank(c)?true:false)

usr.bin/lex/flexdef.h

1103

#define b_iscntrl(c) (iscntrl(c)?true:false)

usr.bin/lex/flexdef.h

1104

#define b_isdigit(c) (isdigit(c)?true:false)

usr.bin/lex/flexdef.h

1105

#define b_isgraph(c) (isgraph(c)?true:false)

usr.bin/lex/flexdef.h

1106

#define b_islower(c) (islower(c)?true:false)

usr.bin/lex/flexdef.h

1107

#define b_isprint(c) (isprint(c)?true:false)

usr.bin/lex/flexdef.h

1108

#define b_ispunct(c) (ispunct(c)?true:false)

usr.bin/lex/flexdef.h

1109

#define b_isspace(c) (isspace(c)?true:false)

usr.bin/lex/flexdef.h

1110

#define b_isupper(c) (isupper(c)?true:false)

usr.bin/lex/flexdef.h

1111

#define b_isxdigit(c) (isxdigit(c)?true:false)

usr.bin/lex/gen.c

2049

did_eof_rule = true;

usr.bin/lex/gen.c

2096

gen_next_state(true);

usr.bin/lex/main.c

1001

long_align = true;

usr.bin/lex/main.c

1005

useecs = true;

usr.bin/lex/main.c

1009

fullspd = true;

usr.bin/lex/main.c

1013

fulltbl = true;

usr.bin/lex/main.c

1017

usemecs = true;

usr.bin/lex/main.c

1021

use_read = true;

usr.bin/lex/main.c

1033

ddebug = true;

usr.bin/lex/main.c

1042

use_read = fulltbl = true;

usr.bin/lex/main.c

1047

use_read = fullspd = true;

usr.bin/lex/main.c

1055

interactive = true;

usr.bin/lex/main.c

1059

sf_set_case_ins(true);

usr.bin/lex/main.c

1063

lex_compat = true;

usr.bin/lex/main.c

1067

posix_compat = true;

usr.bin/lex/main.c

1101

bison_bridge_lval = true;

usr.bin/lex/main.c

1105

bison_bridge_lval = bison_bridge_lloc = true;

usr.bin/lex/main.c

1109

reentrant = true;

usr.bin/lex/main.c

1125

spprdflt = true;

usr.bin/lex/main.c

1129

use_stdout = true;

usr.bin/lex/main.c

1138

tablesext = true;

usr.bin/lex/main.c

1143

tablesverify = true;

usr.bin/lex/main.c

1147

trace = true;

usr.bin/lex/main.c

1151

printstats = true;

usr.bin/lex/main.c

1163

nowarn = true;

usr.bin/lex/main.c

1175

long_align = true;

usr.bin/lex/main.c

1191

yytext_is_array = true;

usr.bin/lex/main.c

1199

useecs = true;

usr.bin/lex/main.c

1211

usemecs = true;

usr.bin/lex/main.c

1243

use_read = true;

usr.bin/lex/main.c

1252

do_stdinit = true;

usr.bin/lex/main.c

1264

do_yylineno = true;

usr.bin/lex/main.c

1272

do_yywrap = true;

usr.bin/lex/main.c

1280

yymore_really_used = true;

usr.bin/lex/main.c

1288

reject_really_used = true;

usr.bin/lex/main.c

1461

posix_compat = true;

usr.bin/lex/main.c

1472

if (yymore_really_used == true)

usr.bin/lex/main.c

1473

yymore_used = true;

usr.bin/lex/main.c

1477

if (reject_really_used == true)

usr.bin/lex/main.c

1478

reject = true;

usr.bin/lex/main.c

1517

real_reject = true;

usr.bin/lex/main.c

1520

reject = true;

usr.bin/lex/main.c

240

yytext_is_array = true;

usr.bin/lex/main.c

241

do_yylineno = true;

usr.bin/lex/main.c

248

reject_really_used = true;

usr.bin/lex/main.c

261

interactive = true;

usr.bin/lex/main.c

368

gentables = true;

usr.bin/lex/main.c

749

if (interactive == true)

usr.bin/lex/main.c

916

do_yywrap = gen_line_dirs = usemecs = useecs = true;

usr.bin/lex/main.c

924

gentables = true;

usr.bin/lex/main.c

926

ansi_func_defs = ansi_func_protos = true;

usr.bin/lex/main.c

959

C_plus_plus = true;

usr.bin/lex/main.c

977

C_plus_plus = true;

usr.bin/lex/main.c

985

backing_up_report = true;

usr.bin/lex/main.c

996

sawcmpflag = true;

usr.bin/lex/misc.c

798

bool do_copy = true;

usr.bin/lex/misc.c

804

sko_push(do_copy = true);

usr.bin/lex/misc.c

884

do_copy = true;

usr.bin/lex/nfa.c

228

rule_has_nl[num_rules] = true;

usr.bin/lex/nfa.c

246

variable_trailing_context_rules = true;

usr.bin/lex/parse.y

1005

syntaxerror = true;

usr.bin/lex/parse.y

173

{ xcluflg = true; }

usr.bin/lex/parse.y

207

{ tablesext = true; tablesfilename = copy_string( nmstr ); }

usr.bin/lex/parse.y

224

in_rule = true;

usr.bin/lex/parse.y

258

bol_needed = true;

usr.bin/lex/parse.y

404

varlength = true;

usr.bin/lex/parse.y

423

variable_trail_rule = true;

usr.bin/lex/parse.y

458

varlength = true;

usr.bin/lex/parse.y

468

variable_trail_rule = true;

usr.bin/lex/parse.y

471

trlcontxt = true;

usr.bin/lex/parse.y

488

variable_trail_rule = true;

usr.bin/lex/parse.y

498

varlength = true;

usr.bin/lex/parse.y

517

trlcontxt = true;

usr.bin/lex/parse.y

547

varlength = true;

usr.bin/lex/parse.y

575

varlength = true;

usr.bin/lex/parse.y

593

varlength = true;

usr.bin/lex/parse.y

611

varlength = true;

usr.bin/lex/parse.y

618

varlength = true;

usr.bin/lex/parse.y

624

varlength = true;

usr.bin/lex/parse.y

630

varlength = true;

usr.bin/lex/parse.y

658

varlength = true;

usr.bin/lex/parse.y

676

varlength = true;

usr.bin/lex/parse.y

712

madeany = true;

usr.bin/lex/parse.y

736

rule_has_nl[num_rules] = true;

usr.bin/lex/parse.y

746

rule_has_nl[num_rules] = true;

usr.bin/lex/parse.y

762

rule_has_nl[num_rules] = true;

usr.bin/lex/parse.y

875

cclsorted = true;

usr.bin/lex/parse.y

930

rule_has_nl[num_rules] = true;

usr.bin/lex/parse.y

967

sceof[scon_stk[i]] = true;

usr.bin/lex/regex.c

44

return true;

usr.bin/make/arch.c

230

subst_lib = true;

usr.bin/make/arch.c

237

lib = Var_Substi(lib, elib, ctxt, true);

usr.bin/make/arch.c

260

subst_member = true;

usr.bin/make/arch.c

294

member = Var_Substi(member, emember, ctxt, true);

usr.bin/make/arch.c

356

return true;

usr.bin/make/arch.c

865

Var(MEMBER_INDEX, gn), true);

usr.bin/make/compat.c

110

gn->must_make = true;

usr.bin/make/compat.c

218

pgn->child_rebuilt = true;

usr.bin/make/compat.c

238

pgn->child_rebuilt = true;

usr.bin/make/compat.c

282

*out_of_date = true;

usr.bin/make/compat.c

283

*has_errors = true;

usr.bin/make/compat.c

285

*out_of_date = true;

usr.bin/make/cond.c

1101

skipLine = true;

usr.bin/make/cond.c

1134

switch (CondE(true)) {

usr.bin/make/cond.c

1136

if (CondToken(true) == EndOfFile) {

usr.bin/make/cond.c

1137

value = true;

usr.bin/make/cond.c

1143

if (CondToken(true) == EndOfFile) {

usr.bin/make/cond.c

130

{ false,true, CondDoDefined }, /* ifndef */

usr.bin/make/cond.c

132

{ false,true, CondDoMake }, /* ifnmake */

usr.bin/make/cond.c

133

{ true, false, CondDoDefined }, /* elif, elifdef */

usr.bin/make/cond.c

134

{ true, true, CondDoDefined }, /* elifndef */

usr.bin/make/cond.c

135

{ true, false, CondDoMake }, /* elifmake */

usr.bin/make/cond.c

136

{ true, true, CondDoMake }, /* elifnmake */

usr.bin/make/cond.c

137

{ true, false, NULL }

usr.bin/make/cond.c

223

cp = VarName_Get(cp, arg, NULL, true, find_cond);

usr.bin/make/cond.c

238

return true;

usr.bin/make/cond.c

275

return true;

usr.bin/make/cond.c

301

result = true;

usr.bin/make/cond.c

325

return true;

usr.bin/make/cond.c

346

return true;

usr.bin/make/cond.c

385

return true;

usr.bin/make/cond.c

406

return CondHandleComparison(lhs, true, doEval);

usr.bin/make/cond.c

441

doFree = true;

usr.bin/make/cond.c

466

return CondHandleComparison(lhs, true, doEval);

usr.bin/make/cond.c

704

if (CondGetArg(&condExpr, &arg, op->s, true))

usr.bin/make/dir.c

321

return true;

usr.bin/make/dir.c

433

hasSlash = true;

usr.bin/make/dir.c

543

checkedDot = true;

usr.bin/make/dir.h

104

#define Dir_FindFilei(n, e, p) Dir_FindFileComplexi(n, e, p, true)

usr.bin/make/direxpand.c

194

dowild = true;

usr.bin/make/direxpand.c

316

wild = true;

usr.bin/make/direxpand.c

325

wild = true;

usr.bin/make/direxpand.c

334

wild = true;

usr.bin/make/dump.c

167

bool first = true;

usr.bin/make/dump.c

211

dumped_once = true;

usr.bin/make/dump.c

221

targ_dump(true);

usr.bin/make/engine.c

110

return true;

usr.bin/make/engine.c

114

return true;

usr.bin/make/engine.c

129

return true;

usr.bin/make/engine.c

159

return true;

usr.bin/make/engine.c

166

bool first = true;

usr.bin/make/engine.c

375

do_oodate = true;

usr.bin/make/engine.c

470

oodate = true;

usr.bin/make/engine.c

489

oodate = true;

usr.bin/make/engine.c

625

doExecute = true;

usr.bin/make/engine.c

640

silent = DEBUG(LOUD) ? false : true;

usr.bin/make/engine.c

644

doExecute = true;

usr.bin/make/engine.c

695

return true;

usr.bin/make/engine.c

722

return true;

usr.bin/make/error.c

148

static bool first = true;

usr.bin/make/expandchildren.c

70

pgn->child_rebuilt = true;

usr.bin/make/expandchildren.c

86

cp = Var_Subst(cgn->name, &pgn->localvars, true);

usr.bin/make/for.c

241

return true;

usr.bin/make/for.c

269

arg->freeold = true;

usr.bin/make/job.c

211

static bool first = true;

usr.bin/make/job.c

236

static bool first = true;

usr.bin/make/job.c

280

bool first = true;

usr.bin/make/job.c

410

bool first = true;

usr.bin/make/job.c

579

no_new_jobs = true;

usr.bin/make/job.c

594

return true;

usr.bin/make/job.c

610

return true;

usr.bin/make/job.c

616

include = true;

usr.bin/make/job.c

634

expensive = true;

usr.bin/make/job.c

643

return true;

usr.bin/make/job.c

759

reaped = true;

usr.bin/make/job.c

852

return true;

usr.bin/make/lst.lib/lstAddNew.c

45

return true;

usr.bin/make/main.c

132

compatMake = true;

usr.bin/make/main.c

140

compatMake = true;

usr.bin/make/main.c

146

Var_setCheckEnvFirst(true);

usr.bin/make/main.c

149

ignoreErrors = true;

usr.bin/make/main.c

152

keepgoing = true;

usr.bin/make/main.c

155

noExecute = true;

usr.bin/make/main.c

158

dumpData = true;

usr.bin/make/main.c

161

queryFlag = true;

usr.bin/make/main.c

165

noBuiltins = true;

usr.bin/make/main.c

168

beSilent = true;

usr.bin/make/main.c

171

touchFlag = true;

usr.bin/make/main.c

320

forceJobs = true;

usr.bin/make/main.c

656

bool read_depend = true;/* false if we don't want to read .depend */

usr.bin/make/main.c

725

compatMake = true;

usr.bin/make/main.c

930

return true;

usr.bin/make/make.c

175

return true;

usr.bin/make/make.c

283

pgn->child_rebuilt = true;

usr.bin/make/make.c

376

return true;

usr.bin/make/make.c

418

return true;

usr.bin/make/make.c

470

gn->must_make = true;

usr.bin/make/make.c

547

*out_of_date = true;

usr.bin/make/make.c

575

*has_errors = true;

usr.bin/make/make.c

583

*has_errors = true;

usr.bin/make/make.c

598

bool first = true;

usr.bin/make/make.c

604

cycle = true;

usr.bin/make/make.c

685

gn->in_cycle = true;

usr.bin/make/parse.c

1180

isSystem = true;

usr.bin/make/parse.c

1202

handle_include_file(file2, strchr(file2, '\0'), isSystem, true);

usr.bin/make/parse.c

1204

return true;

usr.bin/make/parse.c

1231

handle_include_file(name, ename, true, errIfMissing);

usr.bin/make/parse.c

1232

okay = true;

usr.bin/make/parse.c

1248

lookup_sysv_style_include(file, directive, true);

usr.bin/make/parse.c

1280

not = true;

usr.bin/make/parse.c

1295

paren_to_match = true;

usr.bin/make/parse.c

1331

return true;

usr.bin/make/parse.c

1355

return true;

usr.bin/make/parse.c

1370

return true;

usr.bin/make/parse.c

1396

return true;

usr.bin/make/parse.c

1428

return true;

usr.bin/make/parse.c

1454

seen_target = true;

usr.bin/make/parse.c

1496

htargets_setup = true;

usr.bin/make/parse.c

1556

return true;

usr.bin/make/parse.c

1562

return true;

usr.bin/make/parse.c

1568

return true;

usr.bin/make/parse.c

1574

return true;

usr.bin/make/parse.c

1621

*pcommands_seen = true;

usr.bin/make/parse.c

1645

commands_seen = true;

usr.bin/make/parse.c

1665

expectingCommands = true;

usr.bin/make/parse.c

595

return true;

usr.bin/make/parse.c

609

return true;

usr.bin/make/parse.c

877

allPrecious = true;

usr.bin/make/parse.c

880

ignoreErrors = true;

usr.bin/make/parse.c

883

beSilent = true;

usr.bin/make/parsevar.c

142

return true;

usr.bin/make/parsevar.c

151

sub = Var_Subst(arg, NULL, true);

usr.bin/make/parsevar.c

165

arg = Var_Subst(arg, NULL, true);

usr.bin/make/parsevar.c

205

return true;

usr.bin/make/parsevar.c

73

arg = VarName_Get(line, &name, NULL, true, find_op1);

usr.bin/make/regress.c

53

CHECK(Str_Match("string", "string") == true);

usr.bin/make/regress.c

55

CHECK(Str_Match("string", "string*") == true);

usr.bin/make/regress.c

56

CHECK(Str_Match("Long string", "Lo*ng") == true);

usr.bin/make/regress.c

58

CHECK(Str_Match("Long string", "Lo*ng *") == true);

usr.bin/make/regress.c

59

CHECK(Str_Match("string", "stri?g") == true);

usr.bin/make/regress.c

60

CHECK(Str_Match("str?ng", "str\\?ng") == true);

usr.bin/make/regress.c

61

CHECK(Str_Match("striiiing", "str?*ng") == true);

usr.bin/make/regress.c

63

CHECK(Str_Match("d[abc?", "d\\[abc\\?") == true);

usr.bin/make/regress.c

66

CHECK(Str_Match("da0", "d[bcda]0") == true);

usr.bin/make/regress.c

67

CHECK(Str_Match("da0", "d[z-a]0") == true);

usr.bin/make/regress.c

68

CHECK(Str_Match("d-0", "d[-a-z]0") == true);

usr.bin/make/regress.c

70

CHECK(Str_Match("d-0", "d[a\\-z]0") == true);

usr.bin/make/regress.c

71

CHECK(Str_Match("dz0", "d[a\\]z]0") == true);

usr.bin/make/stats.c

166

mmapped = true;

usr.bin/make/str.c

258

return true;

usr.bin/make/str.c

262

return true;

usr.bin/make/str.c

271

return true;

usr.bin/make/str.c

313

return true;

usr.bin/make/str.c

353

return true;

usr.bin/make/suff.c

1521

bool first = true;

usr.bin/make/suff.c

1571

reprint = true;

usr.bin/make/suff.c

413

return true;

usr.bin/make/suff.c

740

return true;

usr.bin/make/suff.c

963

return true;

usr.bin/make/targ.c

251

return true;

usr.bin/make/targ.c

260

return true;

usr.bin/make/targ.c

269

return true;

usr.bin/make/targequiv.c

293

free_a = true;

usr.bin/make/targequiv.c

300

free_b = true;

usr.bin/make/targequiv.c

325

free_a = true;

usr.bin/make/targequiv.c

332

free_b = true;

usr.bin/make/targequiv.c

436

equiv_was_built = true;

usr.bin/make/targequiv.c

453

return true;

usr.bin/make/var.c

1024

*freePtr = true;

usr.bin/make/var.c

107

static bool varname_list_changed = true;

usr.bin/make/var.c

1088

errorReported = true;

usr.bin/make/var.c

1147

seen_target = true;

usr.bin/make/var.c

1346

errorIsOkay = true;

usr.bin/make/var.c

1379

bool first = true;

usr.bin/make/var.c

159

true, /* $@ */

usr.bin/make/var.c

162

true, /* $% */

usr.bin/make/var.c

163

true, /* $< */

usr.bin/make/var.c

365

varname_list_changed = true;

usr.bin/make/var.c

583

varname_list_changed = true;

usr.bin/make/var.c

641

var_set_append(name, ename, val, ctxt, true);

usr.bin/make/var.c

663

bool first = true;

usr.bin/make/var.c

729

return true;

usr.bin/make/var.c

793

has_modifier = true;

usr.bin/make/var.c

823

result = true;

usr.bin/make/var.c

826

char *s = VarModifiers_Apply(NULL, NULL, ctxt, true, &freePtr,

usr.bin/make/var.c

854

return true;

usr.bin/make/var.c

922

*freePtr = true;

usr.bin/make/var.c

934

*freePtr = true;

usr.bin/make/var.c

937

*freePtr = true;

usr.bin/make/varmodifiers.c

1137

*freePtr = true;

usr.bin/make/varmodifiers.c

221

return true;

usr.bin/make/varmodifiers.c

243

return true;

usr.bin/make/varmodifiers.c

262

addSpace = true;

usr.bin/make/varmodifiers.c

286

return true;

usr.bin/make/varmodifiers.c

304

return true;

usr.bin/make/varmodifiers.c

324

return true;

usr.bin/make/varmodifiers.c

350

return true;

usr.bin/make/varmodifiers.c

469

addSpace = true;

usr.bin/make/varmodifiers.c

483

addSpace = true;

usr.bin/make/varmodifiers.c

508

addSpace = true;

usr.bin/make/varmodifiers.c

544

done = true;

usr.bin/make/varmodifiers.c

547

done = true;

usr.bin/make/varmodifiers.c

565

return true;

usr.bin/make/varmodifiers.c

972

return common_get_patternarg(p, ctxt, err, endc, true);

usr.bin/make/varname.c

54

name->tofree = true;

usr.bin/patch/ed.c

150

toutkeep = true;

usr.bin/patch/inp.c

124

return true;

usr.bin/patch/inp.c

160

return true;

usr.bin/patch/inp.c

161

makedirs(filename, true);

usr.bin/patch/inp.c

225

last_line_missing_eol = true;

usr.bin/patch/inp.c

271

return true; /* plan a will work */

usr.bin/patch/inp.c

301

last_line_missing_eol = true;

usr.bin/patch/inp.c

305

found_revision = true;

usr.bin/patch/inp.c

418

return true;

usr.bin/patch/inp.c

422

return true;

usr.bin/patch/inp.c

426

return true;

usr.bin/patch/inp.c

82

using_plan_a = true; /* maybe the next one is smaller */

usr.bin/patch/patch.c

1035

dump_line(last_frozen_line, true);

usr.bin/patch/patch.c

1050

copy_till(input_lines, true); /* dump remainder of file */

usr.bin/patch/patch.c

1113

return true;

usr.bin/patch/patch.c

1137

return true; /* actually, this is not reached */

usr.bin/patch/patch.c

275

patch_seen = true;

usr.bin/patch/patch.c

277

warn_on_invalid_line = true;

usr.bin/patch/patch.c

348

skip_rest_of_patch = true;

usr.bin/patch/patch.c

361

skip_rest_of_patch = true;

usr.bin/patch/patch.c

434

toutkeep = true;

usr.bin/patch/patch.c

469

trejkeep = true;

usr.bin/patch/patch.c

54

bool using_plan_a = true; /* try to keep everything in memory */

usr.bin/patch/patch.c

581

check_only = true;

usr.bin/patch/patch.c

588

do_defines = true;

usr.bin/patch/patch.c

602

remove_empty_files = true;

usr.bin/patch/patch.c

605

force = true;

usr.bin/patch/patch.c

619

canonicalize = true;

usr.bin/patch/patch.c

625

noreverse = true;

usr.bin/patch/patch.c

642

reverse = true;

usr.bin/patch/patch.c

643

reverse_flag_specified = true;

usr.bin/patch/patch.c

649

batch = true;

usr.bin/patch/patch.c

659

Vflag = true;

usr.bin/patch/patch.c

78

bool verbose = true;

usr.bin/patch/pch.c

1158

return true;

usr.bin/patch/pch.c

1229

blankline = true;

usr.bin/patch/pch.c

1292

return true;

usr.bin/patch/pch.c

174

out_of_mem = true; /* whatever is null will be allocated again */

usr.bin/patch/pch.c

217

skip_rest_of_patch = true;

usr.bin/patch/pch.c

218

return true;

usr.bin/patch/pch.c

236

skip_rest_of_patch = true;

usr.bin/patch/pch.c

237

return true;

usr.bin/patch/pch.c

240

return true;

usr.bin/patch/pch.c

344

ok_to_create_file = true;

usr.bin/patch/pch.c

355

ok_to_create_file = true;

usr.bin/patch/pch.c

410

bestguess = posix_name(names, true);

usr.bin/patch/pch.c

412

bestguess = best_name(names, true);

usr.bin/patch/pch.c

479

return true;

usr.bin/patch/pch.c

524

repl_could_be_missing = true;

usr.bin/patch/pch.c

548

repl_missing = true;

usr.bin/patch/pch.c

564

repl_missing = true;

usr.bin/patch/pch.c

573

repl_missing = true;

usr.bin/patch/pch.c

635

repl_missing = true;

usr.bin/patch/pch.c

703

repl_missing = true;

usr.bin/patch/pch.c

730

repl_missing = true;

usr.bin/patch/pch.c

749

repl_missing = true;

usr.bin/patch/pch.c

763

repl_missing = true;

usr.bin/patch/util.c

184

out_of_mem = true;

usr.bin/pkgconf/cli/main.c

1188

pkgconf_path_prepend(pkg_optarg, &dir_list, true);

usr.bin/pkgconf/cli/main.c

1309

opened_error_msgout = true;

usr.bin/pkgconf/cli/main.c

254

return true;

usr.bin/pkgconf/cli/main.c

329

return true;

usr.bin/pkgconf/cli/main.c

389

return true;

usr.bin/pkgconf/cli/main.c

408

return true;

usr.bin/pkgconf/cli/main.c

429

return true;

usr.bin/pkgconf/cli/main.c

452

return true;

usr.bin/pkgconf/cli/main.c

478

render_buf = pkgconf_fragment_render(&filtered_list, true, want_render_ops);

usr.bin/pkgconf/cli/main.c

486

return true;

usr.bin/pkgconf/cli/main.c

599

return true;

usr.bin/pkgconf/cli/main.c

621

render_buf = pkgconf_fragment_render(&filtered_list, true, want_render_ops);

usr.bin/pkgconf/cli/main.c

629

return true;

usr.bin/pkgconf/cli/main.c

650

render_buf = pkgconf_fragment_render(&filtered_list, true, want_render_ops);

usr.bin/pkgconf/cli/main.c

658

return true;

usr.bin/pkgconf/cli/main.c

677

return true;

usr.bin/pkgconf/cli/main.c

695

return true;

usr.bin/pkgconf/cli/main.c

718

return true;

usr.bin/pkgconf/cli/main.c

763

return true;

usr.bin/pkgconf/cli/main.c

807

return true;

usr.bin/pkgconf/cli/main.c

833

return true;

usr.bin/pkgconf/cli/main.c

98

return true;

usr.bin/pkgconf/libpkgconf/argvsplit.c

102

escaped = true;

usr.bin/pkgconf/libpkgconf/argvsplit.c

124

escaped = true;

usr.bin/pkgconf/libpkgconf/client.c

412

return true;

usr.bin/pkgconf/libpkgconf/client.c

63

pkgconf_path_build_from_environ("PKG_CONFIG_PATH", NULL, &client->dir_list, true);

usr.bin/pkgconf/libpkgconf/client.c

73

(void) pkgconf_path_build_from_environ("PKG_CONFIG_LIBDIR", NULL, &dir_list, true);

usr.bin/pkgconf/libpkgconf/fileio.c

29

quoted = true;

usr.bin/pkgconf/libpkgconf/fragment.c

111

return true;

usr.bin/pkgconf/libpkgconf/fragment.c

120

return true;

usr.bin/pkgconf/libpkgconf/fragment.c

123

return true;

usr.bin/pkgconf/libpkgconf/fragment.c

281

return true;

usr.bin/pkgconf/libpkgconf/fragment.c

291

return true;

usr.bin/pkgconf/libpkgconf/fragment.c

327

return true;

usr.bin/pkgconf/libpkgconf/fragment.c

332

return true;

usr.bin/pkgconf/libpkgconf/fragment.c

339

return true;

usr.bin/pkgconf/libpkgconf/fragment.c

437

pkgconf_fragment_copy(client, list, frag, true);

usr.bin/pkgconf/libpkgconf/fragment.c

465

pkgconf_fragment_copy(client, dest, frag, true);

usr.bin/pkgconf/libpkgconf/fragment.c

59

return true;

usr.bin/pkgconf/libpkgconf/fragment.c

63

return true;

usr.bin/pkgconf/libpkgconf/fragment.c

640

return ops->render_len(list, true);

usr.bin/pkgconf/libpkgconf/fragment.c

663

ops->render_buf(list, buf, buflen, true);

usr.bin/pkgconf/libpkgconf/fragment.c

684

size_t buflen = pkgconf_fragment_render_len(list, true, ops);

usr.bin/pkgconf/libpkgconf/fragment.c

687

pkgconf_fragment_render_buf(list, buf, buflen, true, ops);

usr.bin/pkgconf/libpkgconf/fragment.c

786

return true;

usr.bin/pkgconf/libpkgconf/fragment.c

79

return true;

usr.bin/pkgconf/libpkgconf/fragment.c

97

return true;

usr.bin/pkgconf/libpkgconf/parser.c

102

warned_value_whitespace = true;

usr.bin/pkgconf/libpkgconf/parser.c

38

bool continue_reading = true;

usr.bin/pkgconf/libpkgconf/parser.c

57

warned_key_whitespace = true;

usr.bin/pkgconf/libpkgconf/parser.c

76

warned_key_whitespace = true;

usr.bin/pkgconf/libpkgconf/path.c

243

return true;

usr.bin/pkgconf/libpkgconf/path.c

364

return true;

usr.bin/pkgconf/libpkgconf/path.c

40

return true;

usr.bin/pkgconf/libpkgconf/path.c

44

return true;

usr.bin/pkgconf/libpkgconf/personality.c

159

return true;

usr.bin/pkgconf/libpkgconf/personality.c

306

pkgconf_path_add(envvar, &plist, true);

usr.bin/pkgconf/libpkgconf/personality.c

312

pkgconf_path_add(pathbuf, &plist, true);

usr.bin/pkgconf/libpkgconf/personality.c

316

pkgconf_path_build_from_environ("XDG_DATA_DIRS", "/usr/local/share" PKG_CONFIG_PATH_SEP_S "/usr/share", &plist, true);

usr.bin/pkgconf/libpkgconf/personality.c

322

out = load_personality_with_path(pn->path, triplet, true);

usr.bin/pkgconf/libpkgconf/personality.c

329

pkgconf_path_split(PERSONALITY_PATH, &plist, true);

usr.bin/pkgconf/libpkgconf/personality.c

47

.want_default_static = true,

usr.bin/pkgconf/libpkgconf/personality.c

68

pkgconf_path_split(PKG_DEFAULT_PATH, dirlist, true);

usr.bin/pkgconf/libpkgconf/personality.c

74

pkgconf_path_add(outbuf, dirlist, true);

usr.bin/pkgconf/libpkgconf/personality.c

78

pkgconf_path_add(outbuf, dirlist, true);

usr.bin/pkgconf/libpkgconf/personality.c

84

pkgconf_path_add(paths[i], dirlist, true);

usr.bin/pkgconf/libpkgconf/personality.c

90

pkgconf_path_add(paths[i], dirlist, true);

usr.bin/pkgconf/libpkgconf/personality.c

95

pkgconf_path_split(PKG_DEFAULT_PATH, dirlist, true);

usr.bin/pkgconf/libpkgconf/pkg.c

1196

return true;

usr.bin/pkgconf/libpkgconf/pkg.c

1387

return true;

usr.bin/pkgconf/libpkgconf/pkg.c

1485

if (pkgconf_pkg_comparator_impls[pkgdep->compare](pkg->version, pkgdep->version) != true)

usr.bin/pkgconf/libpkgconf/pkg.c

1530

client->already_sent_notice = true;

usr.bin/pkgconf/libpkgconf/pkg.c

1789

pkgconf_fragment_copy(client, list, frag, true);

usr.bin/pkgconf/libpkgconf/pkg.c

1851

pkgconf_fragment_copy(client, list, frag, true);

usr.bin/pkgconf/libpkgconf/pkg.c

409

pkgconf_tuple_add(pkg->owner, &pkg->vars, keyword, value, true, pkg->flags);

usr.bin/pkgconf/libpkgconf/pkg.c

418

pkg->orig_prefix = pkgconf_tuple_add(pkg->owner, &pkg->vars, "orig_prefix", canonicalized_value, true, pkg->flags);

usr.bin/pkgconf/libpkgconf/pkg.c

423

pkgconf_tuple_add(pkg->owner, &pkg->vars, keyword, value, true, pkg->flags);

usr.bin/pkgconf/libpkgconf/pkg.c

462

bool valid = true;

usr.bin/pkgconf/libpkgconf/pkg.c

505

pkgconf_tuple_add(client, &pkg->vars, "pcfiledir", pc_filedir_value, true, pkg->flags);

usr.bin/pkgconf/libpkgconf/pkg.c

859

pkgconf_path_add(pkg->pc_filedir, &client->dir_list, true);

usr.bin/pkgconf/libpkgconf/pkg.c

975

isnum = true;

usr.bin/pkgconf/libpkgconf/queue.c

368

ret = true;

usr.bin/pkgconf/libpkgconf/queue.c

391

bool retval = true;

usr.bin/pkgconf/libpkgconf/tuple.c

217

return true;

usr.bin/sort/bwstring.c

793

*empty = true;

usr.bin/sort/bwstring.c

799

*empty = true;

usr.bin/sort/bwstring.c

813

*empty = true;

usr.bin/sort/bwstring.c

819

*empty = true;

usr.bin/sort/coll.c

1096

kv1->hint->v.gh.notnum = true;

usr.bin/sort/coll.c

1105

key1_read = true;

usr.bin/sort/coll.c

1114

kv2->hint->v.gh.notnum = true;

usr.bin/sort/coll.c

1123

key2_read = true;

usr.bin/sort/coll.c

1246

key1_read = true;

usr.bin/sort/coll.c

1252

key2_read = true;

usr.bin/sort/coll.c

1258

key1_read = true;

usr.bin/sort/coll.c

1263

key2_read = true;

usr.bin/sort/coll.c

226

*empty_key = true;

usr.bin/sort/coll.c

239

*empty_field = true;

usr.bin/sort/coll.c

243

bool pb = true;

usr.bin/sort/coll.c

259

*empty_field = true;

usr.bin/sort/coll.c

273

*empty_field = true;

usr.bin/sort/coll.c

290

*empty_key = true;

usr.bin/sort/coll.c

805

key1_read = true;

usr.bin/sort/coll.c

808

kv1->hint->v.nh.empty=true;

usr.bin/sort/coll.c

812

kv1->hint->v.nh.neg = (sign1 < 0) ? true : false;

usr.bin/sort/coll.c

818

key2_read = true;

usr.bin/sort/coll.c

821

kv2->hint->v.nh.empty=true;

usr.bin/sort/coll.c

825

kv2->hint->v.nh.neg = (sign2 < 0) ? true : false;

usr.bin/sort/coll.c

941

return numcoll_impl(kv1, kv2, offset, true);

usr.bin/sort/file.c

1016

file_list_init(&new_fl, true);

usr.bin/sort/file.c

153

return true;

usr.bin/sort/sort.c

1097

file_list_init(&fl, true);

usr.bin/sort/sort.c

1135

file_list_add(&fl, "-", true);

usr.bin/sort/sort.c

1137

file_list_populate(&fl, argc, argv, true);

usr.bin/sort/sort.c

391

found_others = true;

usr.bin/sort/sort.c

400

mef_flags[i] = true;

usr.bin/sort/sort.c

401

found_this = true;

usr.bin/sort/sort.c

427

sm->bflag = true;

usr.bin/sort/sort.c

430

sm->dflag = true;

usr.bin/sort/sort.c

433

sm->fflag = true;

usr.bin/sort/sort.c

436

sm->gflag = true;

usr.bin/sort/sort.c

437

need_hint = true;

usr.bin/sort/sort.c

440

sm->iflag = true;

usr.bin/sort/sort.c

443

sm->Rflag = true;

usr.bin/sort/sort.c

444

need_random = true;

usr.bin/sort/sort.c

448

sm->Mflag = true;

usr.bin/sort/sort.c

449

need_hint = true;

usr.bin/sort/sort.c

452

sm->nflag = true;

usr.bin/sort/sort.c

453

need_hint = true;

usr.bin/sort/sort.c

456

sm->rflag = true;

usr.bin/sort/sort.c

459

sm->Vflag = true;

usr.bin/sort/sort.c

462

sm->hflag = true;

usr.bin/sort/sort.c

463

need_hint = true;

usr.bin/sort/sort.c

468

sort_opts_vals.complex_sort = true;

usr.bin/sort/sort.c

471

return true;

usr.bin/sort/sort.c

565

ks->pos2b = true;

usr.bin/sort/sort.c

567

ks->pos1b = true;

usr.bin/sort/sort.c

617

ret = parse_pos(pos2, ks, mef_flags, true);

usr.bin/sort/sort.c

830

sort_opts_vals.cflag = true;

usr.bin/sort/sort.c

836

sort_opts_vals.csilentflag = true;

usr.bin/sort/sort.c

842

sort_opts_vals.cflag = true;

usr.bin/sort/sort.c

843

sort_opts_vals.csilentflag = true;

usr.bin/sort/sort.c

847

sort_opts_vals.complex_sort = true;

usr.bin/sort/sort.c

848

sort_opts_vals.kflag = true;

usr.bin/sort/sort.c

865

sort_opts_vals.mflag = true;

usr.bin/sort/sort.c

871

sort_opts_vals.sflag = true;

usr.bin/sort/sort.c

890

sort_opts_vals.tflag = true;

usr.bin/sort/sort.c

898

sort_opts_vals.uflag = true;

usr.bin/sort/sort.c

900

sort_opts_vals.sflag = true;

usr.bin/sort/sort.c

903

sort_opts_vals.zflag = true;

usr.bin/sort/sort.c

926

use_mmap = true;

usr.bin/sort/sort.c

960

debug_sort = true;

usr.bin/sort/vsort.c

80

expect_alpha = true;

usr.bin/sort/vsort.c

82

sfx = true;

usr.bin/ssh/libcrux_mlkem768_sha3.h

10174

libcrux_ml_kem_matrix_sample_matrix_A_2b(uu____1, ret, true);

usr.bin/ssh/libcrux_mlkem768_sha3.h

5060

self->sponge = true;

usr.bin/ssh/libcrux_mlkem768_sha3.h

5358

self->sponge = true;

usr.bin/ssh/libcrux_mlkem768_sha3.h

8355

bool done = true;

usr.bin/ssh/libcrux_mlkem768_sha3.h

8477

bool done = true;

usr.bin/ssh/libcrux_mlkem768_sha3.h

8572

while (true) {

usr.bin/timeout/timeout.c

199

do_second_kill = true;

usr.bin/timeout/timeout.c

293

timedout = true;

usr.bin/top/commands.c

161

int cnt = 0, first = true, currerr = -1;

usr.bin/top/commands.c

189

first = true;

usr.bin/top/display.c

107

int header_status = true;

usr.bin/top/screen.c

155

is_a_terminal = true;

usr.bin/top/screen.c

77

smart_terminal = true;

usr.bin/top/top.c

1009

} else if (filterpid(tempbuf, true) == -1) {

usr.bin/top/top.c

1012

no_command = true;

usr.bin/top/top.c

1061

no_command = true;

usr.bin/top/top.c

207

ps.system = true;

usr.bin/top/top.c

251

show_args = true;

usr.bin/top/top.c

275

ps.threads = true;

usr.bin/top/top.c

276

old_threads = true;

usr.bin/top/top.c

284

interactive = true;

usr.bin/top/top.c

344

ps.rtable = true;

usr.bin/top/top.c

370

topn_specified = true;

usr.bin/top/top.c

396

ps.idle = true;

usr.bin/top/top.c

644

no_command = true;

usr.bin/top/top.c

757

no_command = true;

usr.bin/top/top.c

797

no_command = true;

usr.bin/top/top.c

82

int do_unames = true;

usr.bin/top/top.c

824

display_header(true);

usr.bin/top/top.c

833

no_command = true;

usr.bin/top/top.c

852

no_command = true;

usr.bin/top/top.c

874

no_command = true;

usr.bin/top/top.c

88

int no_command = true;

usr.bin/top/top.c

886

no_command = true;

usr.bin/top/top.c

898

no_command = true;

usr.bin/top/top.c

926

no_command = true;

usr.bin/top/top.c

950

no_command = true;

usr.bin/top/top.c

968

no_command = true;

usr.bin/unexpand/unexpand.c

64

all = true;

usr.bin/unifdef/unifdef.c

1004

defparen = true;

usr.bin/unifdef/unifdef.c

1099

constexpr = killconsts ? false : true;

usr.bin/unifdef/unifdef.c

1523

return (true);

usr.bin/unifdef/unifdef.c

281

addsym1(true, true, optarg);

usr.bin/unifdef/unifdef.c

283

addsym1(true, false, optarg);

usr.bin/unifdef/unifdef.c

288

addsym1(false, true, optarg);

usr.bin/unifdef/unifdef.c

297

lnblank = true;

usr.bin/unifdef/unifdef.c

300

compblank = true;

usr.bin/unifdef/unifdef.c

303

complement = true;

usr.bin/unifdef/unifdef.c

306

debugging = true;

usr.bin/unifdef/unifdef.c

309

iocccok = true;

usr.bin/unifdef/unifdef.c

318

strictlogic = true;

usr.bin/unifdef/unifdef.c

321

killconsts = true;

usr.bin/unifdef/unifdef.c

324

inplace = true;

usr.bin/unifdef/unifdef.c

327

inplace = true;

usr.bin/unifdef/unifdef.c

331

lnnum = true;

usr.bin/unifdef/unifdef.c

337

symlist = true;

usr.bin/unifdef/unifdef.c

340

symlist = symdepth = true;

usr.bin/unifdef/unifdef.c

343

text = true;

usr.bin/unifdef/unifdef.c

556

static void print (void) { flushline(true); }

usr.bin/unifdef/unifdef.c

649

ignoring[depth] = true;

usr.bin/unifdef/unifdef.c

767

zerosyms = true;

usr.sbin/btrace/btrace.c

1255

return true;

usr.sbin/btrace/btrace.c

916

if (stmt_test(bs, dtev) == true)

usr.sbin/ldomctl/mdesc.c

258

return true;

usr.sbin/ldomctl/mdesc.c

272

return true;

usr.sbin/ldomctl/mdesc.c

286

return true;

usr.sbin/ldomctl/mdesc.c

301

return true;

usr.sbin/ldomctl/mdesc.c

316

return true;

usr.sbin/npppctl/npppctl.c

242

} while (true);

usr.sbin/npppctl/npppctl.c

417

return (true);

usr.sbin/npppd/l2tp/l2tp_ctrl.c

1061

return ((off < winsz)? true : false);

usr.sbin/npppd/l2tp/l2tp_ctrl.c

1071

return ((off < _this->winsz)? true : false);

usr.sbin/npppd/l2tp/l2tp_ctrl.c

483

l2tp_ctrl_resend_una_packets(_this, true);

usr.sbin/npppd/l2tp/l2tp_ctrl.c

884

if (l2tp_ctrl_resend_una_packets(ctrl, true) <= 0) {

usr.sbin/npppd/npppd/npppd_ctl.c

106

return (npppd_ctl_who0(_this, true));

usr.sbin/npppd/npppd/npppd_ctl.c

113

_this->responding = true;

usr.sbin/npppd/npppd/npppd_ctl.c

99

_this->is_monitoring = true;

usr.sbin/npppd/npppd/parse.y

1029

yesno : YES { $$ = true; }

usr.sbin/npppd/npppd/parse.y

1643

auth->eap_capable = true;

usr.sbin/npppd/npppd/parse.y

1644

auth->strip_nt_domain = true;

usr.sbin/npppd/npppd/parse.y

892

curr_ipcpconf->dns_use_resolver = true;

usr.sbin/npppd/npppd/parse.y

898

curr_ipcpconf->dns_configured = true;

usr.sbin/npppd/npppd/parse.y

904

curr_ipcpconf->dns_configured = true;

usr.sbin/npppd/npppd/parse.y

909

curr_ipcpconf->nbns_configured = true;

usr.sbin/npppd/npppd/parse.y

914

curr_ipcpconf->nbns_configured = true;

usr.sbin/npppd/npppd/parse.y

970

n->is_pppx = true;

usr.sbin/npppd/npppd/ppp.c

1121

.pipex = true,

usr.sbin/npppd/npppd/ppp.c

1128

.mppe_yesno = true,

usr.sbin/npppd/npppd/ppp.c

1141

.data_use_seq = true,

usr.sbin/npppd/npppd/ppp.c

1144

.lcp_renegotiation = true,

usr.sbin/npppd/npppd/ppp.c

1156

.pipex = true,

usr.sbin/npppd/npppd/ppp.c

1158

.lcp_keepalive = true,

usr.sbin/npppd/npppd/ppp.c

1163

.mppe_yesno = true,

usr.sbin/npppd/npppd/ppp.c

1164

.mppe_required = true,

usr.sbin/npppd/npppd/ppp.c

1182

.pipex = true,

usr.sbin/npppd/npppd/ppp.c

1184

.lcp_keepalive = true,

usr.sbin/npppd/npppd/ppp.c

1189

.mppe_yesno = true,

usr.sbin/npppd/npppd/ppp.c

1197

.accept_any_service = true,

usr.sbin/nsd/ixfr.c

2609

options.no_includes = true;

usr.sbin/nsd/simdzone/src/bench.c

218

options.pretty_ttls = true;

usr.sbin/nsd/simdzone/src/generic/eui.h

27

return true;

usr.sbin/nsd/simdzone/src/generic/eui.h

43

eui_base16_dec_loop_generic_32_inner(input+12, rdata->octets+4, true))

usr.sbin/nsd/simdzone/src/generic/eui.h

62

eui_base16_dec_loop_generic_32_inner(input+18, rdata->octets+6, true))

usr.sbin/nsd/simdzone/src/generic/parser.h

483

parser->file->grouped = true;

usr.sbin/nsd/simdzone/src/generic/parser.h

614

parser->file->grouped = true;

usr.sbin/nsd/simdzone/src/generic/parser.h

715

parser->file->grouped = true;

usr.sbin/nsd/simdzone/src/generic/parser.h

820

parser->file->grouped = true;

usr.sbin/nsd/simdzone/src/generic/parser.h

947

parser->file->grouped = true;

usr.sbin/nsd/simdzone/src/generic/svcb.h

733

out_of_order = true;

usr.sbin/nsd/simdzone/src/generic/svcb.h

884

out_of_order = true;

usr.sbin/nsd/simdzone/src/haswell/base32.h

26

bool valid = true;

usr.sbin/nsd/simdzone/src/westmere/base32.h

25

bool valid = true;

usr.sbin/nsd/simdzone/src/westmere/time.h

120

return true;

usr.sbin/nsd/simdzone/src/zone.c

220

file->start_of_line = true;

usr.sbin/nsd/zonec.c

456

options.pretty_ttls = true; /* non-standard, for backwards compatibility */

usr.sbin/radiusctl/radiusctl.c

465

radius_dump(stdout, respkt, true, test->res->secret);

usr.sbin/radiusd/parse.y

1028

clnt->msgauth_required = true;

usr.sbin/radiusd/parse.y

412

auth->isfilter = true;

usr.sbin/radiusd/parse.y

565

yesno : YES { $$ = true; }

usr.sbin/radiusd/radiusd.c

1288

module->stopped = true;

usr.sbin/radiusd/radiusd.c

1327

module->writeready = true;

usr.sbin/radiusd/radiusd.c

139

noaction = true;

usr.sbin/radiusd/radiusd.c

1742

userpass.has_pass = true;

usr.sbin/radiusd/radiusd.c

1894

arg.final = true;

usr.sbin/radiusd/radiusd.c

869

q->hasnext = true;

usr.sbin/radiusd/radiusd_bsdauth.c

161

authok = true;

usr.sbin/radiusd/radiusd_bsdauth.c

210

group_ok = true;

usr.sbin/radiusd/radiusd_bsdauth.c

216

group_ok = true;

usr.sbin/radiusd/radiusd_eap2mschap.c

505

reset_username = true;

usr.sbin/radiusd/radiusd_eap2mschap.c

641

accept = true;

usr.sbin/radiusd/radiusd_ipcp.c

1055

is_mschap = true;

usr.sbin/radiusd/radiusd_ipcp.c

1058

is_mschap2 = true;

usr.sbin/radiusd/radiusd_ipcp.c

281

self->no_session_timeout = true;

usr.sbin/radiusd/radiusd_ipcp.c

877

found = true;

usr.sbin/radiusd/radiusd_ipcp.c

903

found = true;

usr.sbin/radiusd/radiusd_module.c

199

base->priv_dropped = true;

usr.sbin/radiusd/radiusd_module.c

336

ans.final = true;

usr.sbin/radiusd/radiusd_module.c

624

base->stopped = true;

usr.sbin/radiusd/radiusd_module.c

636

base->ev_onhandler = true;

usr.sbin/radiusd/radiusd_module.c

638

base->writeready = true;

usr.sbin/radiusd/radiusd_standard.c

140

module->strip_atmark_realm = true;

usr.sbin/radiusd/radiusd_standard.c

150

module->strip_nt_domain = true;