/* SPDX-License-Identifier: MIT */
/* Copyright © 2025 Intel Corporation */

#ifndef __INTEL_PFIT_REGS_H__
#define __INTEL_PFIT_REGS_H__

#include "intel_display_reg_defs.h"

/* Panel fitting */
#define PFIT_CONTROL(dev_priv)  _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
#define   PFIT_ENABLE                   REG_BIT(31)
#define   PFIT_PIPE_MASK                REG_GENMASK(30, 29) /* 965+ */
#define   PFIT_PIPE(pipe)               REG_FIELD_PREP(PFIT_PIPE_MASK, (pipe))
#define   PFIT_SCALING_MASK             REG_GENMASK(28, 26) /* 965+ */
#define   PFIT_SCALING_AUTO             REG_FIELD_PREP(PFIT_SCALING_MASK, 0)
#define   PFIT_SCALING_PROGRAMMED       REG_FIELD_PREP(PFIT_SCALING_MASK, 1)
#define   PFIT_SCALING_PILLAR           REG_FIELD_PREP(PFIT_SCALING_MASK, 2)
#define   PFIT_SCALING_LETTER           REG_FIELD_PREP(PFIT_SCALING_MASK, 3)
#define   PFIT_FILTER_MASK              REG_GENMASK(25, 24) /* 965+ */
#define   PFIT_FILTER_FUZZY             REG_FIELD_PREP(PFIT_FILTER_MASK, 0)
#define   PFIT_FILTER_CRISP             REG_FIELD_PREP(PFIT_FILTER_MASK, 1)
#define   PFIT_FILTER_MEDIAN            REG_FIELD_PREP(PFIT_FILTER_MASK, 2)
#define   PFIT_VERT_INTERP_MASK         REG_GENMASK(11, 10) /* pre-965 */
#define   PFIT_VERT_INTERP_BILINEAR     REG_FIELD_PREP(PFIT_VERT_INTERP_MASK, 1)
#define   PFIT_VERT_AUTO_SCALE          REG_BIT(9) /* pre-965 */
#define   PFIT_HORIZ_INTERP_MASK        REG_GENMASK(7, 6) /* pre-965 */
#define   PFIT_HORIZ_INTERP_BILINEAR    REG_FIELD_PREP(PFIT_HORIZ_INTERP_MASK, 1)
#define   PFIT_HORIZ_AUTO_SCALE         REG_BIT(5) /* pre-965 */
#define   PFIT_PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */

#define PFIT_PGM_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
#define   PFIT_VERT_SCALE_MASK          REG_GENMASK(31, 20) /* pre-965 */
#define   PFIT_VERT_SCALE(x)            REG_FIELD_PREP(PFIT_VERT_SCALE_MASK, (x))
#define   PFIT_HORIZ_SCALE_MASK         REG_GENMASK(15, 4) /* pre-965 */
#define   PFIT_HORIZ_SCALE(x)           REG_FIELD_PREP(PFIT_HORIZ_SCALE_MASK, (x))
#define   PFIT_VERT_SCALE_MASK_965      REG_GENMASK(28, 16) /* 965+ */
#define   PFIT_HORIZ_SCALE_MASK_965     REG_GENMASK(12, 0) /* 965+ */

#define PFIT_AUTO_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)

/* CPU panel fitter */
/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
#define _PFA_CTL_1              0x68080
#define _PFB_CTL_1              0x68880
#define PF_CTL(pipe)            _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
#define   PF_ENABLE                     REG_BIT(31)
#define   PF_PIPE_SEL_MASK_IVB          REG_GENMASK(30, 29) /* ivb/hsw */
#define   PF_PIPE_SEL_IVB(pipe)         REG_FIELD_PREP(PF_PIPE_SEL_MASK_IVB, (pipe))
#define   PF_FILTER_MASK                REG_GENMASK(24, 23)
#define   PF_FILTER_PROGRAMMED          REG_FIELD_PREP(PF_FILTER_MASK, 0)
#define   PF_FILTER_MED_3x3             REG_FIELD_PREP(PF_FILTER_MASK, 1)
#define   PF_FILTER_EDGE_ENHANCE        REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 2)
#define   PF_FILTER_EDGE_SOFTEN         REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3)

#define _PFA_WIN_SZ             0x68074
#define _PFB_WIN_SZ             0x68874
#define PF_WIN_SZ(pipe)         _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
#define   PF_WIN_XSIZE_MASK     REG_GENMASK(31, 16)
#define   PF_WIN_XSIZE(w)       REG_FIELD_PREP(PF_WIN_XSIZE_MASK, (w))
#define   PF_WIN_YSIZE_MASK     REG_GENMASK(15, 0)
#define   PF_WIN_YSIZE(h)       REG_FIELD_PREP(PF_WIN_YSIZE_MASK, (h))

#define _PFA_WIN_POS            0x68070
#define _PFB_WIN_POS            0x68870
#define PF_WIN_POS(pipe)        _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
#define   PF_WIN_XPOS_MASK      REG_GENMASK(31, 16)
#define   PF_WIN_XPOS(x)        REG_FIELD_PREP(PF_WIN_XPOS_MASK, (x))
#define   PF_WIN_YPOS_MASK      REG_GENMASK(15, 0)
#define   PF_WIN_YPOS(y)        REG_FIELD_PREP(PF_WIN_YPOS_MASK, (y))

#define _PFA_VSCALE             0x68084
#define _PFB_VSCALE             0x68884
#define PF_VSCALE(pipe)         _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)

#define _PFA_HSCALE             0x68090
#define _PFB_HSCALE             0x68890
#define PF_HSCALE(pipe)         _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)

#endif /* __INTEL_PFIT_REGS_H__ */