sys/arch/acorn32/include/irqhandler.h

199

extern u_int irqmasks[NIPL];

sys/arch/arm/arm32/intr.c

52

u_int spl_masks[NIPL];

sys/arch/arm/arm32/intr.c

61

for (loop = 0; loop < NIPL; ++loop) {

sys/arch/arm/arm32/intr.c

82

for (loop = 0; loop < NIPL; ++loop)

sys/arch/arm/at91/at91aic.c

145

for (ipl = 0; ipl < NIPL; ipl++) {

sys/arch/arm/at91/at91aic.c

289

if (ipl < 0 || ipl >= NIPL)

sys/arch/arm/at91/at91aic.c

336

for (i = 0; i < NIPL; i++) {

sys/arch/arm/at91/at91aic.c

68

static uint32_t aic_imask[NIPL];

sys/arch/arm/cortex/gic.c

124

__CTASSERT(NIPL == 8);

sys/arch/arm/cortex/gic.c

185

| ((IPL_HIGH - ipl) * GICC_PMR_NS_PRIORITIES / NIPL);

sys/arch/arm/cortex/gic.c

193

- (priority & ~GICC_PMR_NONSECURE) * NIPL / GICC_PMR_NS_PRIORITIES;

sys/arch/arm/ep93xx/ep93xx_intr.c

132

for (ipl = 0; ipl < NIPL; ipl++) {

sys/arch/arm/ep93xx/ep93xx_intr.c

298

if (ipl < 0 || ipl > NIPL)

sys/arch/arm/ep93xx/ep93xx_intr.c

60

static uint32_t vic1_imask[NIPL];

sys/arch/arm/ep93xx/ep93xx_intr.c

61

static uint32_t vic2_imask[NIPL];

sys/arch/arm/footbridge/footbridge_irqhandler.c

127

for (ipl = 0; ipl < NIPL; ipl++) {

sys/arch/arm/footbridge/footbridge_irqhandler.c

67

int footbridge_imask[NIPL];

sys/arch/arm/footbridge/isa/isa_machdep.c

111

u_int imask[NIPL];

sys/arch/arm/footbridge/isa/isa_machdep.c

198

for (level = 0; level < NIPL; level++) {

sys/arch/arm/iomd/iomd_irqhandler.c

111

for (loop = 0; loop < NIPL; ++loop)

sys/arch/arm/iomd/iomd_irqhandler.c

157

if (handler->ih_level < 0 || handler->ih_level >= NIPL)

sys/arch/arm/iomd/iomd_irqhandler.c

196

if (handler->ih_level >= 0 && handler->ih_level < NIPL) {

sys/arch/arm/iomd/iomd_irqhandler.c

304

if (handler->ih_level >= 0 && handler->ih_level < NIPL) {

sys/arch/arm/iomd/iomd_irqhandler.c

308

for (level = 0; level < NIPL; ++level)

sys/arch/arm/iomd/iomd_irqhandler.c

64

u_int irqmasks[NIPL];

sys/arch/arm/ixp12x0/ixp12x0_intr.c

186

for (ipl = 0; ipl < NIPL; ipl++) {

sys/arch/arm/ixp12x0/ixp12x0_intr.c

342

if (ipl < 0 || ipl > NIPL)

sys/arch/arm/ixp12x0/ixp12x0_intr.c

63

static uint32_t imask[NIPL];

sys/arch/arm/ixp12x0/ixp12x0_intr.c

64

static uint32_t pci_imask[NIPL];

sys/arch/arm/ofw/ofw_irqhandler.c

134

if (handler->ih_level < 0 || handler->ih_level >= NIPL)

sys/arch/arm/ofw/ofw_irqhandler.c

164

if (handler->ih_level >= 0 && handler->ih_level < NIPL) {

sys/arch/arm/ofw/ofw_irqhandler.c

251

if (handler->ih_level >= 0 && handler->ih_level < NIPL) {

sys/arch/arm/ofw/ofw_irqhandler.c

255

for (level = 0; level < NIPL; ++level)

sys/arch/arm/ofw/ofw_irqhandler.c

61

u_int irqmasks[NIPL];

sys/arch/arm/ofw/ofw_irqhandler.c

89

for (loop = 0; loop < NIPL; ++loop)

sys/arch/arm/pic/pic.c

571

KASSERT(ci->ci_pending_ipls < __BIT(NIPL));

sys/arch/arm/pic/pic.c

574

KASSERT(ipl < NIPL);

sys/arch/arm/pic/pic.c

795

if (ipl < NIPL) {

sys/arch/arm/pic/pic.c

798

sizeof(pic__iplsources[0]) * (pic_ipl_offset[NIPL] - off));

sys/arch/arm/pic/pic.c

806

for (nipl = ipl + 1; nipl <= NIPL; nipl++)

sys/arch/arm/pic/pic.c

87

size_t pic_ipl_offset[NIPL + 1];

sys/arch/arm/pic/pic_splfuncs.c

57

KASSERT(newipl < NIPL);

sys/arch/arm/pic/pic_splfuncs.c

86

KASSERT(savedipl < NIPL);

sys/arch/arm/s3c2xx0/s3c2410_intr.c

260

for (i=0; i < NIPL; ++i)

sys/arch/arm/s3c2xx0/s3c2410_intr.c

66

int s3c2xx0_imask[NIPL];

sys/arch/arm/s3c2xx0/s3c2410_intr.c

69

int s3c24x0_soft_imask[NIPL];

sys/arch/arm/s3c2xx0/s3c2440_intr.c

290

for (i=0; i < NIPL; ++i)

sys/arch/arm/s3c2xx0/s3c2440_intr.c

93

int s3c2xx0_imask[NIPL];

sys/arch/arm/s3c2xx0/s3c2440_intr.c

96

int s3c24x0_soft_imask[NIPL];

sys/arch/arm/s3c2xx0/s3c2800_intr.c

186

for (i = 0; i < NIPL; i++)

sys/arch/arm/s3c2xx0/s3c2800_intr.c

64

int s3c2xx0_imask[NIPL];

sys/arch/arm/s3c2xx0/s3c2xx0_intr.c

106

for (; i < NIPL - 1; ++i)

sys/arch/arm/sa11x0/sa11x0_irqhandler.c

129

for (ipl = 0; ipl < NIPL; ipl++) {

sys/arch/arm/sa11x0/sa11x0_irqhandler.c

140

for( ; i < NIPL-1; ++i)

sys/arch/arm/sa11x0/sa11x0_irqhandler.c

149

for (ipl = 0; ipl < NIPL - 1; ipl++)

sys/arch/arm/sa11x0/sa11x0_irqhandler.c

93

u_int irqmasks[NIPL];

sys/arch/arm/xscale/becc_icu.c

183

for (ipl = 0; ipl < NIPL; ipl++) {

sys/arch/arm/xscale/becc_icu.c

69

uint32_t becc_imask[NIPL];

sys/arch/arm/xscale/i80321_icu.c

174

for (ipl = 0; ipl < NIPL; ipl++)

sys/arch/arm/xscale/i80321_icu.c

183

for (ipl = 1; ipl < NIPL; ipl++)

sys/arch/arm/xscale/i80321_icu.c

67

int i80321_imask[NIPL];

sys/arch/arm/xscale/ixp425_intr.c

208

for (ipl = 0; ipl < NIPL; ipl++) {

sys/arch/arm/xscale/ixp425_intr.c

91

int ixp425_imask[NIPL];

sys/arch/arm/xscale/pxa2x0_intr.c

234

for( ; i < NIPL-1; ++i)

sys/arch/arm/xscale/pxa2x0_intr.c

98

int pxa2x0_imask[NIPL];

sys/arch/atari/atari/intr.c

316

const uint16_t ipl2psl_table[NIPL] = {

sys/arch/atari/include/intr.h

73

extern const uint16_t ipl2psl_table[NIPL];

sys/arch/cats/cats/autoconf.c

133

extern int footbridge_imask[NIPL];

sys/arch/evbarm/ifpga/ifpga_intr.c

159

for (ipl = 0; ipl < NIPL; ipl++) {

sys/arch/evbarm/ifpga/ifpga_intr.c

61

int ifpga_imask[NIPL];

sys/arch/evbarm/iq80310/iq80310_intr.c

163

for (ipl = 0; ipl < NIPL; ipl++) {

sys/arch/evbarm/iq80310/iq80310_intr.c

69

int iq80310_imask[NIPL];

sys/arch/evbcf/include/intr.h

59

extern const uint16_t ipl2psl_table[NIPL];

sys/arch/hpcarm/include/irqhandler.h

76

extern u_int irqmasks[NIPL];

sys/arch/hppa/hppa/intr.c

104

for (i = 0; i < NIPL; i++)

sys/arch/hppa/hppa/intr.c

281

for (ipl = NIPL - 1; ipl > 0; ipl--)

sys/arch/hppa/include/cpu.h

306

u_int ci_imask[NIPL];

sys/arch/m68k/include/intr.h

74

extern const uint16_t ipl2psl_table[NIPL];

sys/arch/m68k/m68k/m68k_intr.c

102

const uint16_t ipl2psl_table[NIPL] = {

sys/arch/mac68k/include/intr.h

57

extern uint16_t ipl2psl_table[NIPL];

sys/arch/mac68k/mac68k/intr.c

85

uint16_t ipl2psl_table[NIPL];

sys/arch/macppc/macppc/pic_ohare.c

143

for (i = 0; i < NIPL; i++)

sys/arch/macppc/macppc/pic_ohare.c

294

int realpri = uimin(NIPL, uimax(0, pri)), i;

sys/arch/macppc/macppc/pic_ohare.c

308

for (i = 0; i < NIPL; i++)

sys/arch/macppc/macppc/pic_ohare.c

59

uint32_t irqs[NIPL]; /* per priority level */

sys/arch/netwinder/netwinder/autoconf.c

62

extern int footbridge_imask[NIPL];

sys/arch/powerpc/booke/booke_machdep.c

667

uint64_t tbs[NIPL*NIPL];

sys/arch/powerpc/booke/booke_machdep.c

669

for (size_t to = 0; to < NIPL; to++) {

sys/arch/powerpc/booke/booke_machdep.c

670

for (size_t from = 0; from < NIPL; from++) {

sys/arch/powerpc/include/booke/cpuvar.h

70

uint64_t cpu_spl_tb[NIPL][NIPL];

sys/arch/powerpc/include/booke/intr.h

52

#define IST_NONE (NIPL+0) /* none */

sys/arch/powerpc/include/booke/intr.h

53

#define IST_EDGE (NIPL+1) /* edge-triggered */

sys/arch/powerpc/include/booke/intr.h

54

#define IST_LEVEL (NIPL+2) /* level-triggered active-low */

sys/arch/powerpc/include/booke/intr.h

56

#define IST_LEVEL_HIGH (NIPL+3) /* level-triggered active-high */

sys/arch/powerpc/include/booke/intr.h

57

#define IST_PULSE (NIPL+4) /* pulsed */

sys/arch/powerpc/include/booke/intr.h

58

#define IST_MSI (NIPL+5) /* message signaling interrupt (PCI) */

sys/arch/powerpc/include/booke/intr.h

59

#define IST_ONCHIP (NIPL+6) /* on-chip device */

sys/arch/powerpc/include/booke/intr.h

61

#define IST_MSIGROUP (NIPL+7) /* openpic msi groups */

sys/arch/powerpc/include/booke/intr.h

62

#define IST_TIMER (NIPL+8) /* openpic timers */

sys/arch/powerpc/include/booke/intr.h

63

#define IST_IPI (NIPL+9) /* openpic ipi */

sys/arch/powerpc/include/booke/intr.h

64

#define IST_MI (NIPL+10) /* openpic message */

sys/arch/powerpc/include/booke/intr.h

65

#define IST_MAX (NIPL+11)

sys/arch/powerpc/pic/intr.c

394

imask_t newmask[NIPL];

sys/arch/powerpc/pic/intr.c

399

for (u_int ipl = IPL_NONE; ipl < NIPL; ipl++) {

sys/arch/powerpc/pic/intr.c

420

for (u_int ipl = 1; ipl < NIPL; ipl++) {

sys/arch/powerpc/pic/intr.c

425

for (u_int ipl = 0; ipl < NIPL; ipl++) {

sys/arch/powerpc/pic/intr.c

443

for (u_int ipl = 0; ipl < NIPL; ipl++) {

sys/arch/powerpc/pic/intr.c

658

KASSERT(ncpl < NIPL);

sys/arch/powerpc/pic/intr.c

78

static imask_t imask[NIPL];

sys/arch/shark/include/irqhandler.h

137

extern u_int irqmasks[NIPL];

sys/arch/shark/isa/isa_irqhandler.c

126

for (loop = 0; loop < NIPL; ++loop)

sys/arch/shark/isa/isa_irqhandler.c

170

if (handler->ih_level < 0 || handler->ih_level >= NIPL)

sys/arch/shark/isa/isa_irqhandler.c

286

for (level = 0; level < NIPL; level++) {

sys/arch/shark/isa/isa_irqhandler.c

95

u_int irqmasks[NIPL];

sys/arch/virt68k/include/intr.h

123

extern const uint16_t ipl2psl_table[NIPL];

sys/arch/virt68k/virt68k/machdep.c

286

const uint16_t ipl2psl_table[NIPL] = {

sys/arch/x68k/include/intr.h

60

extern const uint16_t ipl2psl_table[NIPL];

sys/arch/x68k/x68k/machdep.c

384

const uint16_t ipl2psl_table[NIPL] = {

sys/arch/x86/include/cpu.h

157

uint64_t ci_imask[NIPL];

sys/arch/x86/include/cpu.h

158

uint64_t ci_iunmask[NIPL];

sys/arch/x86/x86/hyperv.c

780

APIC_LEVEL(NIPL), IDT_INTR_HIGH);

sys/arch/x86/x86/intr.c

1511

for (i = 0; i < NIPL; i++)

sys/arch/x86/x86/x86_softintr.c

186

for (level = 0; level < NIPL; level++) {

sys/arch/x86/x86/x86_softintr.c

194

for (level = 0; level<(NIPL-1); level++)

sys/arch/x86/x86/x86_softintr.c

214

for (level = 0; level < NIPL; level++)