Symbol: div
common/lib/libx86emu/x86emu.c
7780
int32_t dvd, div, mod;
common/lib/libx86emu/x86emu.c
7787
div = dvd / (int8_t) s;
common/lib/libx86emu/x86emu.c
7789
if (div > 0x7f || div < -0x7f) {
common/lib/libx86emu/x86emu.c
7793
emu->x86.R_AL = (int8_t) div;
common/lib/libx86emu/x86emu.c
7803
int32_t dvd, div, mod;
common/lib/libx86emu/x86emu.c
7810
div = dvd / (int16_t) s;
common/lib/libx86emu/x86emu.c
7812
if (div > 0x7fff || div < -0x7fff) {
common/lib/libx86emu/x86emu.c
7818
CONDITIONAL_SET_FLAG(div == 0, F_ZF);
common/lib/libx86emu/x86emu.c
7821
emu->x86.R_AX = (uint16_t) div;
common/lib/libx86emu/x86emu.c
7831
int64_t dvd, div, mod;
common/lib/libx86emu/x86emu.c
7838
div = dvd / (int32_t) s;
common/lib/libx86emu/x86emu.c
7840
if (div > 0x7fffffff || div < -0x7fffffff) {
common/lib/libx86emu/x86emu.c
7850
emu->x86.R_EAX = (uint32_t) div;
common/lib/libx86emu/x86emu.c
7860
uint32_t dvd, div, mod;
common/lib/libx86emu/x86emu.c
7867
div = dvd / (uint8_t) s;
common/lib/libx86emu/x86emu.c
7869
if (div > 0xff) {
common/lib/libx86emu/x86emu.c
7873
emu->x86.R_AL = (uint8_t) div;
common/lib/libx86emu/x86emu.c
7883
uint32_t dvd, div, mod;
common/lib/libx86emu/x86emu.c
7890
div = dvd / (uint16_t) s;
common/lib/libx86emu/x86emu.c
7892
if (div > 0xffff) {
common/lib/libx86emu/x86emu.c
7898
CONDITIONAL_SET_FLAG(div == 0, F_ZF);
common/lib/libx86emu/x86emu.c
7901
emu->x86.R_AX = (uint16_t) div;
common/lib/libx86emu/x86emu.c
7911
uint64_t dvd, div, mod;
common/lib/libx86emu/x86emu.c
7918
div = dvd / (uint32_t) s;
common/lib/libx86emu/x86emu.c
7920
if (div > 0xffffffff) {
common/lib/libx86emu/x86emu.c
7930
emu->x86.R_EAX = (uint32_t) div;
include/stdlib.h
109
div_t div(int, int);
lib/libc/cdb/cdbw.c
102
fast_divide32(uint32_t v, uint32_t div, uint32_t m, uint8_t s1,
lib/libc/cdb/cdbw.c
112
fast_remainder32(uint32_t v, uint32_t div, uint32_t m, uint8_t s1,
lib/libc/cdb/cdbw.c
116
return v - div * fast_divide32(v, div, m, s1, s2);
lib/libc/cdb/cdbw.c
88
fast_divide32_prepare(uint32_t div, uint32_t * m,
lib/libc/cdb/cdbw.c
94
l = my_fls32(div - 1);
lib/libc/cdb/cdbw.c
95
mt = (uint64_t)(0x100000000ULL * ((1ULL << l) - div));
lib/libc/cdb/cdbw.c
96
*m = (uint32_t)(mt / div + 1);
sys/arch/arm/altera/cycv_clkmgr.c
260
} else if (fdtbus_get_reg(handle, 0, &clk->u.div.addr, NULL) ==
sys/arch/arm/altera/cycv_clkmgr.c
263
clk->u.div.shift = 0;
sys/arch/arm/altera/cycv_clkmgr.c
264
clk->u.div.mask = 0xff;
sys/arch/arm/altera/cycv_clkmgr.c
271
clk->u.div.addr = of_decode_int(buf);
sys/arch/arm/altera/cycv_clkmgr.c
272
clk->u.div.shift = of_decode_int(buf + 4);
sys/arch/arm/altera/cycv_clkmgr.c
273
clk->u.div.mask = ((1 << of_decode_int(buf + 8)) - 1) <<
sys/arch/arm/altera/cycv_clkmgr.c
274
clk->u.div.shift;
sys/arch/arm/altera/cycv_clkmgr.c
396
tmp = bus_space_read_4(sc->sc_bst, sc->sc_bsh, clk->u.div.addr);
sys/arch/arm/altera/cycv_clkmgr.c
397
tmp = (tmp & clk->u.div.mask) >> clk->u.div.shift;
sys/arch/arm/altera/cycv_clkmgr.c
398
if (__SHIFTOUT_MASK(clk->u.div.mask) > 0xf)
sys/arch/arm/altera/cycv_clkmgr.c
487
clk->u.div.addr);
sys/arch/arm/altera/cycv_clkmgr.c
488
divisor = (divisor & clk->u.div.mask) >> clk->u.div.shift;
sys/arch/arm/altera/cycv_clkmgr.c
489
if (__SHIFTOUT_MASK(clk->u.div.mask) > 0xf)
sys/arch/arm/altera/cycv_clkmgr.c
85
} div;
sys/arch/arm/amlogic/meson_clk.h
128
uint32_t div;
sys/arch/arm/amlogic/meson_clk.h
146
.u.div.reg = (_reg), \
sys/arch/arm/amlogic/meson_clk.h
147
.u.div.parent = (_parent), \
sys/arch/arm/amlogic/meson_clk.h
148
.u.div.div = (_div), \
sys/arch/arm/amlogic/meson_clk.h
149
.u.div.flags = (_flags), \
sys/arch/arm/amlogic/meson_clk.h
161
u_int div;
sys/arch/arm/amlogic/meson_clk.h
177
.u.fixed_factor.div = (_div), \
sys/arch/arm/amlogic/meson_clk.h
338
struct meson_clk_div div;
sys/arch/arm/amlogic/meson_clk_div.c
104
val = CLK_READ(sc, div->reg);
sys/arch/arm/amlogic/meson_clk_div.c
113
if ((div->flags & MESON_CLK_DIV_POWER_OF_TWO) != 0) {
sys/arch/arm/amlogic/meson_clk_div.c
116
} else if ((div->flags & MESON_CLK_DIV_CPU_SCALE_TABLE) != 0) {
sys/arch/arm/amlogic/meson_clk_div.c
122
if (raw_div > __SHIFTOUT_MASK(div->div)) {
sys/arch/arm/amlogic/meson_clk_div.c
127
val &= ~div->div;
sys/arch/arm/amlogic/meson_clk_div.c
128
val |= __SHIFTIN(raw_div, div->div);
sys/arch/arm/amlogic/meson_clk_div.c
129
CLK_WRITE(sc, div->reg, val);
sys/arch/arm/amlogic/meson_clk_div.c
143
struct meson_clk_div *div = &clk->u.div;
sys/arch/arm/amlogic/meson_clk_div.c
147
return div->parent;
sys/arch/arm/amlogic/meson_clk_div.c
43
struct meson_clk_div *div = &clk->u.div;
sys/arch/arm/amlogic/meson_clk_div.c
60
val = CLK_READ(sc, div->reg);
sys/arch/arm/amlogic/meson_clk_div.c
63
if (div->div)
sys/arch/arm/amlogic/meson_clk_div.c
64
ratio = __SHIFTOUT(val, div->div);
sys/arch/arm/amlogic/meson_clk_div.c
68
if (div->flags & MESON_CLK_DIV_POWER_OF_TWO) {
sys/arch/arm/amlogic/meson_clk_div.c
70
} else if (div->flags & MESON_CLK_DIV_CPU_SCALE_TABLE) {
sys/arch/arm/amlogic/meson_clk_div.c
83
struct meson_clk_div *div = &clk->u.div;
sys/arch/arm/amlogic/meson_clk_div.c
96
if ((div->flags & MESON_CLK_DIV_SET_RATE_PARENT) != 0)
sys/arch/arm/amlogic/meson_clk_div.c
99
if (div->div == 0)
sys/arch/arm/amlogic/meson_clk_fixed_factor.c
64
return (u_int)(((uint64_t)p_rate * fixed_factor->mult) / fixed_factor->div);
sys/arch/arm/amlogic/meson_clk_fixed_factor.c
88
rate *= fixed_factor->div;
sys/arch/arm/amlogic/meson_clk_mpll.c
71
const uint64_t div = (SDM_DEN * n2) + sdm;
sys/arch/arm/amlogic/meson_clk_mpll.c
72
if (div == 0)
sys/arch/arm/amlogic/meson_clk_mpll.c
75
return (u_int)howmany(parent_rate * SDM_DEN, div);
sys/arch/arm/amlogic/meson_dwmac.c
143
const u_int div = DIV_ROUND_OFF(clk_get_rate(clkin), 250000000);
sys/arch/arm/amlogic/meson_dwmac.c
153
val |= __SHIFTIN(div, MP2_CLK_OUT_DIV);
sys/arch/arm/amlogic/meson_i2c.c
385
u_int div = howmany(rate, sc->sc_clkfreq) - FILTER_DELAY;
sys/arch/arm/amlogic/meson_i2c.c
386
div = howmany(div, 4);
sys/arch/arm/amlogic/meson_i2c.c
389
mesoni2c_set_mask(sc, MESONI2C_CTRL_REG, MESONI2C_CTRL_CLKDIV_MASK, (div & __BITS(9, 0)) << MESONI2C_CTRL_CLKDIV_SHIFT);
sys/arch/arm/amlogic/meson_i2c.c
390
mesoni2c_set_mask(sc, MESONI2C_CTRL_REG, MESONI2C_CTRL_CLKDIVEXT_MASK, (div >> 10) << MESONI2C_CTRL_CLKDIVEXT_SHIFT);
sys/arch/arm/amlogic/mesong12_clkc.c
1258
uint32_t val, m, n, div_shift, div;
sys/arch/arm/amlogic/mesong12_clkc.c
1305
div = 1 << div_shift;
sys/arch/arm/amlogic/mesong12_clkc.c
1308
freq = xtal_clock * m / n / div;
sys/arch/arm/amlogic/mesongx_mmc.c
470
int best_diff, best_sel, best_div, sel, div;
sys/arch/arm/amlogic/mesongx_mmc.c
483
for (div = 1; div <= 63; div++) {
sys/arch/arm/amlogic/mesongx_mmc.c
484
const u_int rate = parent_rate / div;
sys/arch/arm/amlogic/mesongx_mmc.c
491
best_div = div;
sys/arch/arm/broadcom/bcm2835_cm.c
137
bcm_cm_set(enum bcm_cm_clock clk, uint32_t ctl, uint32_t div)
sys/arch/arm/broadcom/bcm2835_cm.c
176
div &= ~CM_DIV_PASSWD;
sys/arch/arm/broadcom/bcm2835_cm.c
177
div |= __SHIFTIN(CM_PASSWD, CM_DIV_PASSWD);
sys/arch/arm/broadcom/bcm2835_cm.c
194
CM_WRITE(sc, divreg, div);
sys/arch/arm/broadcom/bcm2835_sdhost.c
552
int div;
sys/arch/arm/broadcom/bcm2835_sdhost.c
555
div = SDCDIV_MASK;
sys/arch/arm/broadcom/bcm2835_sdhost.c
557
div = sc->sc_rate / target_rate;
sys/arch/arm/broadcom/bcm2835_sdhost.c
558
if (div < 2)
sys/arch/arm/broadcom/bcm2835_sdhost.c
559
div = 2;
sys/arch/arm/broadcom/bcm2835_sdhost.c
560
if ((sc->sc_rate / div) > target_rate)
sys/arch/arm/broadcom/bcm2835_sdhost.c
561
div++;
sys/arch/arm/broadcom/bcm2835_sdhost.c
562
div -= 2;
sys/arch/arm/broadcom/bcm2835_sdhost.c
563
if (div > SDCDIV_MASK)
sys/arch/arm/broadcom/bcm2835_sdhost.c
564
div = SDCDIV_MASK;
sys/arch/arm/broadcom/bcm2835_sdhost.c
567
SDHOST_WRITE(sc, SDCDIV, div);
sys/arch/arm/broadcom/bcm53xx_mdio.c
102
uint32_t freq = 66000000 / div;
sys/arch/arm/broadcom/bcm53xx_mdio.c
95
uint32_t div = __SHIFTOUT(miimgt, MIIMGT_MDCDIV);
sys/arch/arm/broadcom/bcm53xx_mdio.c
96
if (div == 0) {
sys/arch/arm/broadcom/bcm53xx_mdio.c
97
div = 33; // divisor to get 2MHz
sys/arch/arm/broadcom/bcm53xx_mdio.c
99
miimgt |= __SHIFTIN(div, MIIMGT_MDCDIV);
sys/arch/arm/cortex/a9ptmr.c
152
for (size_t div = 256; div >= 2; div--) {
sys/arch/arm/cortex/a9ptmr.c
153
if (sc->sc_freq % div == 0) {
sys/arch/arm/cortex/a9ptmr.c
154
sc->sc_prescaler = div;
sys/arch/arm/cortex/a9wdt.c
217
for (size_t div = 256; div >= 2; div--) {
sys/arch/arm/cortex/a9wdt.c
218
if (sc->sc_freq % div == 0) {
sys/arch/arm/cortex/a9wdt.c
219
sc->sc_wdog_prescaler = div;
sys/arch/arm/imx/imx23_mmc.c
560
uint8_t div, rate, d, r;
sys/arch/arm/imx/imx23_mmc.c
562
found = div = rate = 0;
sys/arch/arm/imx/imx23_mmc.c
569
div = d;
sys/arch/arm/imx/imx23_mmc.c
575
div = d;
sys/arch/arm/imx/imx23_mmc.c
583
reg |= __SHIFTIN(div, HW_SSP_TIMING_CLOCK_DIVIDE) |
sys/arch/arm/imx/imx23_mmc.c
587
return SSP_CLK / (div * (1 + rate));
sys/arch/arm/imx/imx51_ccm.c
625
int div;
sys/arch/arm/imx/imx51_ccm.c
647
div = uimax(1, freq / rate);
sys/arch/arm/imx/imx51_ccm.c
651
reg |= __SHIFTIN(div, EPDC_AXI_DIV);
sys/arch/arm/imx/imx51_ccm.c
678
div = freq / rate;
sys/arch/arm/imx/imx51_ccm.c
681
reg |= __SHIFTIN(div, EPDC_PIX_CLK_PRED);
sys/arch/arm/imx/imx51_ipuv3.c
363
uint32_t div;
sys/arch/arm/imx/imx51_ipuv3.c
375
div = (ipuclk * 16) / geom->pixel_clk;
sys/arch/arm/imx/imx51_ipuv3.c
376
div = div < 16 ? 16 : div & 0xff8;
sys/arch/arm/imx/imx51_ipuv3.c
384
IPUV3_WRITE(sc, di0, IPU_DI_BS_CLKGEN0, div);
sys/arch/arm/imx/imx51_ipuv3.c
386
__SHIFTIN(div / 16, DI_BS_CLKGEN1_DOWN));
sys/arch/arm/imx/imx51_ipuv3.c
394
reg = __SHIFTIN(div / 16 - 1, DI_DW_GEN_ACCESS_SIZE) |
sys/arch/arm/imx/imx51_ipuv3.c
395
__SHIFTIN(div / 16 - 1, DI_DW_GEN_COMPONNENT_SIZE) |
sys/arch/arm/imx/imx51_ipuv3.c
399
printf("%s: div = %d\n", __func__, div);
sys/arch/arm/imx/imx51_ipuv3.c
405
reg = __SHIFTIN(div / 16 * 2, DI_DW_SET_DOWN);
sys/arch/arm/imx/imxi2c.c
42
int div;
sys/arch/arm/imx/imxi2c.c
88
if (freq / imxi2c_clk_div[index].div < speed) {
sys/arch/arm/imx/imxpwm.c
117
int div = 0;
sys/arch/arm/imx/imxpwm.c
119
div++;
sys/arch/arm/imx/imxpwm.c
120
rate = sc->sc_freq / div;
sys/arch/arm/imx/imxpwm.c
127
cr |= __SHIFTIN(div - 1, PWM_CR_PRESCALER);
sys/arch/arm/imx/imxpwm.c
94
const int div = __SHIFTOUT(cr, PWM_CR_PRESCALER) + 1;
sys/arch/arm/imx/imxpwm.c
96
const uint64_t rate = sc->sc_freq / div;
sys/arch/arm/imx/imxspi.c
131
uint32_t div;
sys/arch/arm/imx/imxspi.c
134
div = (sc->sc_freq + (speed - 1)) / speed;
sys/arch/arm/imx/imxspi.c
135
div = div - 1;
sys/arch/arm/imx/imxspi.c
136
for (div_cnt = 0; div > 0; div_cnt++)
sys/arch/arm/imx/imxspi.c
137
div >>= 1;
sys/arch/arm/imx/imxspi.c
181
uint32_t div;
sys/arch/arm/imx/imxspi.c
185
div = (sc->sc_freq + (speed - 1)) / speed;
sys/arch/arm/imx/imxspi.c
186
for (div_cnt = 0; div > 0; div_cnt++)
sys/arch/arm/imx/imxspi.c
187
div >>= 1;
sys/arch/arm/imx/imxuart.c
2446
imxuart_set_frequency(u_int freq, u_int div)
sys/arch/arm/imx/imxuart.c
2449
imxuart_freqdiv = div;
sys/arch/arm/imx/imxuartreg.h
164
#define IMX_UFCR_DIVIDER_TO_RFDIV(div) \
sys/arch/arm/imx/imxuartreg.h
165
(((6 - div) % 7) & 0x7)
sys/arch/arm/nvidia/tegra124_car.c
1218
return parent_rate / tfixed_div->div;
sys/arch/arm/nvidia/tegra124_car.c
1235
struct tegra_div_clk *tdiv = &tclk->u.div;
sys/arch/arm/nvidia/tegra124_car.c
1282
struct tegra_div_clk *tdiv = &tclk->u.div;
sys/arch/arm/nvidia/tegra124_car.c
1443
rate * tclk->u.fixed_div.div);
sys/arch/arm/nvidia/tegra124_car.c
327
.div = (_div) \
sys/arch/arm/nvidia/tegra124_car.c
336
.div = { \
sys/arch/arm/nvidia/tegra210_car.c
1324
return parent_rate / tfixed_div->div;
sys/arch/arm/nvidia/tegra210_car.c
1331
struct tegra_div_clk *tdiv = &tclk->u.div;
sys/arch/arm/nvidia/tegra210_car.c
1386
struct tegra_div_clk *tdiv = &tclk->u.div;
sys/arch/arm/nvidia/tegra210_car.c
1533
rate * tclk->u.fixed_div.div);
sys/arch/arm/nvidia/tegra210_car.c
339
.div = (_div) \
sys/arch/arm/nvidia/tegra210_car.c
348
.div = { \
sys/arch/arm/nvidia/tegra_clock.h
46
u_int div;
sys/arch/arm/nvidia/tegra_clock.h
85
struct tegra_div_clk div;
sys/arch/arm/nvidia/tegra_drm_mode.c
639
const u_int div = (parent_rate * 2) / (mode->crtc_clock * 1000) - 2;
sys/arch/arm/nvidia/tegra_drm_mode.c
642
__SHIFTIN(div, DC_DISP_DISP_CLOCK_CONTROL_SHIFT_CLK_DIVIDER));
sys/arch/arm/nvidia/tegra_drm_mode.c
944
const u_int div = (mode->crtc_clock / 1000) * 4;
sys/arch/arm/nvidia/tegra_drm_mode.c
946
__SHIFTIN(div >> 2, HDMI_NV_PDISP_SOR_REFCLK_DIV_INT) |
sys/arch/arm/nvidia/tegra_drm_mode.c
947
__SHIFTIN(div & 3, HDMI_NV_PDISP_SOR_REFCLK_DIV_FRAC));
sys/arch/arm/nvidia/tegra_soctherm.c
328
const int div = config->tsample * config->pdiv_ate;
sys/arch/arm/nvidia/tegra_soctherm.c
331
d_sensor * div);
sys/arch/arm/nxp/imx6_ccm.c
168
uint32_t div = __SHIFTOUT(v, pll->mask);
sys/arch/arm/nxp/imx6_ccm.c
170
return freq * ((div == 1) ? 22 : 20);
sys/arch/arm/nxp/imx6_ccm.c
183
uint32_t div = __SHIFTOUT(v, pll->mask);
sys/arch/arm/nxp/imx6_ccm.c
185
return freq * div / 2;
sys/arch/arm/nxp/imx6_ccm.c
201
uint32_t div = __SHIFTOUT(v, pll->mask);
sys/arch/arm/nxp/imx6_ccm.c
209
return freq * div + tmp;
sys/arch/arm/nxp/imx6_ccm.c
236
return rate_parent * fixed_factor->mult / fixed_factor->div;
sys/arch/arm/nxp/imx6_ccm.c
271
struct imx6_clk_div *div = &iclk->clk.div;
sys/arch/arm/nxp/imx6_ccm.c
282
if (div->base == IMX6_CLK_REG_CCM_ANALOG)
sys/arch/arm/nxp/imx6_ccm.c
287
uint32_t v = bus_space_read_4(sc->sc_iot, ioh, div->reg);
sys/arch/arm/nxp/imx6_ccm.c
288
uint32_t n = __SHIFTOUT(v, div->mask);
sys/arch/arm/nxp/imx6_ccm.c
290
if (div->type == IMX6_CLK_DIV_TABLE) {
sys/arch/arm/nxp/imx6_ccm.c
291
KASSERT(div->tbl != NULL);
sys/arch/arm/nxp/imx6_ccm.c
293
for (int i = 0; div->tbl[i] != 0; i++)
sys/arch/arm/nxp/imx6_ccm.c
295
rate /= div->tbl[i];
sys/arch/arm/nxp/imx6_ccm.c
416
struct imx6_clk_div *div = &iclk->clk.div;
sys/arch/arm/nxp/imx6_ccm.c
428
if (div->base == IMX6_CLK_REG_CCM_ANALOG)
sys/arch/arm/nxp/imx6_ccm.c
433
uint32_t v = bus_space_read_4(sc->sc_iot, ioh, div->reg);
sys/arch/arm/nxp/imx6_ccm.c
434
v &= ~div->mask;
sys/arch/arm/nxp/imx6_ccm.c
435
if (div->type == IMX6_CLK_DIV_TABLE) {
sys/arch/arm/nxp/imx6_ccm.c
438
KASSERT(div->tbl != NULL);
sys/arch/arm/nxp/imx6_ccm.c
439
for (int i = 0; div->tbl[i] != 0; i++)
sys/arch/arm/nxp/imx6_ccm.c
440
if (div->tbl[i] == divider)
sys/arch/arm/nxp/imx6_ccm.c
444
v |= __SHIFTIN(n, div->mask);
sys/arch/arm/nxp/imx6_ccm.c
448
v |= __SHIFTIN(divider - 1, div->mask);
sys/arch/arm/nxp/imx6_ccm.c
450
bus_space_write_4(sc->sc_iot, ioh, div->reg, v);
sys/arch/arm/nxp/imx6_ccmvar.h
155
struct imx6_clk_div div;
sys/arch/arm/nxp/imx6_ccmvar.h
177
.div = (_div), \
sys/arch/arm/nxp/imx6_ccmvar.h
215
.div = { \
sys/arch/arm/nxp/imx6_ccmvar.h
229
.div = { \
sys/arch/arm/nxp/imx6_ccmvar.h
245
.div = { \
sys/arch/arm/nxp/imx6_ccmvar.h
98
u_int div;
sys/arch/arm/nxp/imx_ccm.h
202
u_int div;
sys/arch/arm/nxp/imx_ccm.h
217
.u.fixed_factor.div = (_div), \
sys/arch/arm/nxp/imx_ccm.h
277
.u.div.parent = (_parent), \
sys/arch/arm/nxp/imx_ccm.h
278
.u.div.reg = (_reg), \
sys/arch/arm/nxp/imx_ccm.h
279
.u.div.mask = (_mask), \
sys/arch/arm/nxp/imx_ccm.h
280
.u.div.flags = (_flags), \
sys/arch/arm/nxp/imx_ccm.h
302
struct imx_ccm_div div;
sys/arch/arm/nxp/imx_ccm_div.c
107
val = CCM_READ(sc, clk->regidx, div->reg);
sys/arch/arm/nxp/imx_ccm_div.c
108
val &= ~div->mask;
sys/arch/arm/nxp/imx_ccm_div.c
109
val |= __SHIFTIN(best_n, div->mask);
sys/arch/arm/nxp/imx_ccm_div.c
110
CCM_WRITE(sc, clk->regidx, div->reg, val);
sys/arch/arm/nxp/imx_ccm_div.c
119
struct imx_ccm_div *div = &clk->u.div;
sys/arch/arm/nxp/imx_ccm_div.c
123
return div->parent;
sys/arch/arm/nxp/imx_ccm_div.c
45
struct imx_ccm_div *div = &clk->u.div;
sys/arch/arm/nxp/imx_ccm_div.c
59
const uint32_t val = CCM_READ(sc, clk->regidx, div->reg);
sys/arch/arm/nxp/imx_ccm_div.c
60
const u_int n = __SHIFTOUT(val, div->mask);
sys/arch/arm/nxp/imx_ccm_div.c
69
struct imx_ccm_div *div = &clk->u.div;
sys/arch/arm/nxp/imx_ccm_div.c
82
if ((div->flags & IMX_DIV_SET_RATE_PARENT) != 0)
sys/arch/arm/nxp/imx_ccm_div.c
89
for (n = 0; n < __SHIFTOUT_MASK(div->mask); n++) {
sys/arch/arm/nxp/imx_ccm_div.c
92
if ((div->flags & IMX_DIV_ROUND_DOWN) != 0) {
sys/arch/arm/nxp/imx_ccm_fixed_factor.c
64
return (u_int)(((uint64_t)p_rate * fixed_factor->mult) / fixed_factor->div);
sys/arch/arm/nxp/imx_ccm_fixed_factor.c
88
rate *= fixed_factor->div;
sys/arch/arm/nxp/imx_ccm_pll.c
92
const u_int div = __SHIFTOUT(val, pll->div_mask);
sys/arch/arm/nxp/imx_ccm_pll.c
95
return prate * div / 2;
sys/arch/arm/nxp/imx_ccm_pll.c
99
return div == 1 ? 528000000 : 480000000;
sys/arch/arm/nxp/imxpcie.c
338
int div;
sys/arch/arm/nxp/imxpcie.c
341
div = 0;
sys/arch/arm/nxp/imxpcie.c
344
div = 1;
sys/arch/arm/nxp/imxpcie.c
347
div = 1;
sys/arch/arm/nxp/imxpcie.c
361
val |= __SHIFTIN(div, REF_CLKDIV2);
sys/arch/arm/rockchip/rk_cru.h
144
u_int div;
sys/arch/arm/rockchip/rk_cru.h
150
.div = (_div), \
sys/arch/arm/rockchip/rk_cru_arm.c
107
const uint32_t write_val = __SHIFTIN(arm_rate->div - 1,
sys/arch/arm/rockchip/rk_cru_arm.c
58
const u_int div = __SHIFTOUT(val, arm->divs[0].mask) + 1;
sys/arch/arm/rockchip/rk_cru_arm.c
60
return fref / div;
sys/arch/arm/rockchip/rk_cru_arm.c
96
const u_int parent_rate = arm_rate->rate / arm_rate->div;
sys/arch/arm/rockchip/rk_cru_composite.c
183
for (u_int div = 1; div <= __SHIFTOUT_MASK(composite->div_mask) + 1; div++) {
sys/arch/arm/rockchip/rk_cru_composite.c
184
const u_int cur_rate = prate / div;
sys/arch/arm/rockchip/rk_cru_composite.c
190
best_div = div;
sys/arch/arm/rockchip/rk_cru_composite.c
196
best_div = div;
sys/arch/arm/rockchip/rk_cru_composite.c
86
u_int div;
sys/arch/arm/rockchip/rk_cru_composite.c
89
div = 1U << __SHIFTOUT(val, composite->div_mask);
sys/arch/arm/rockchip/rk_cru_composite.c
91
div = __SHIFTOUT(val, composite->div_mask) * 2 + 3;
sys/arch/arm/rockchip/rk_cru_composite.c
92
return ((uint64_t)prate * 2 + div - 1) / div;
sys/arch/arm/rockchip/rk_cru_composite.c
94
div = (composite->div_mask != 0)
sys/arch/arm/rockchip/rk_cru_composite.c
97
return prate / div;
sys/arch/arm/rockchip/rk_i2c.c
132
int div, divl, divh;
sys/arch/arm/rockchip/rk_i2c.c
143
div = howmany(rate, sc->sc_clkfreq * 8) - 2;
sys/arch/arm/rockchip/rk_i2c.c
144
if (div >= 0) {
sys/arch/arm/rockchip/rk_i2c.c
145
divl = div / 2;
sys/arch/arm/rockchip/rk_i2c.c
146
if (div % 2 == 0)
sys/arch/arm/rockchip/rk_i2c.c
149
divh = howmany(div, 2);
sys/arch/arm/rockchip/rk_pwm.c
140
u_int div;
sys/arch/arm/rockchip/rk_pwm.c
147
div = __SHIFTOUT(ctrl, CTRL_SCALE) * 2;
sys/arch/arm/rockchip/rk_pwm.c
148
if (div == 0)
sys/arch/arm/rockchip/rk_pwm.c
149
div = 512;
sys/arch/arm/rockchip/rk_pwm.c
151
div = 1;
sys/arch/arm/rockchip/rk_pwm.c
153
div /= (1 << __SHIFTOUT(ctrl, CTRL_PRESCALE));
sys/arch/arm/rockchip/rk_pwm.c
155
const uint64_t rate = sc->sc_clkfreq / div;
sys/arch/arm/s3c2xx0/s3c2440_sdi.c
321
int div;
sys/arch/arm/s3c2xx0/s3c2440_sdi.c
338
for (div = 1; div <= 256; div++) {
sys/arch/arm/s3c2xx0/s3c2440_sdi.c
339
if ( pclk / div <= freq) {
sys/arch/arm/s3c2xx0/s3c2440_sdi.c
340
DPRINTF(("Using divisor %d: %d/%d = %d\n", div, pclk,
sys/arch/arm/s3c2xx0/s3c2440_sdi.c
341
div, pclk/div));
sys/arch/arm/s3c2xx0/s3c2440_sdi.c
343
bus_space_write_1(sc->iot, sc->ioh, SDI_PRE, div-1);
sys/arch/arm/s3c2xx0/s3c2440_sdi.c
351
if (div-1 == bus_space_read_4(sc->iot, sc->ioh, SDI_PRE)) {
sys/arch/arm/samsung/exynos5410_clock.c
214
.div = { \
sys/arch/arm/samsung/exynos5410_clock.c
781
struct exynos_div_clk *ediv = &eclk->u.div;
sys/arch/arm/samsung/exynos5410_clock.c
790
const u_int div = __SHIFTOUT(v, ediv->bits);
sys/arch/arm/samsung/exynos5410_clock.c
792
return parent_rate / (div + 1);
sys/arch/arm/samsung/exynos5410_clock.c
799
struct exynos_div_clk *ediv = &eclk->u.div;
sys/arch/arm/samsung/exynos5422_clock.c
316
.div = { \
sys/arch/arm/samsung/exynos5422_clock.c
828
struct exynos_div_clk *ediv = &eclk->u.div;
sys/arch/arm/samsung/exynos5422_clock.c
837
const u_int div = __SHIFTOUT(v, ediv->bits);
sys/arch/arm/samsung/exynos5422_clock.c
839
return parent_rate / (div + 1);
sys/arch/arm/samsung/exynos5422_clock.c
846
struct exynos_div_clk *ediv = &eclk->u.div;
sys/arch/arm/samsung/exynos_clock.h
80
struct exynos_div_clk div;
sys/arch/arm/samsung/exynos_wdt.c
242
for (size_t div = 256; UINT16_MAX > div * max_period; div++) {
sys/arch/arm/samsung/exynos_wdt.c
243
u_int remainder = sc->sc_freq % div;
sys/arch/arm/samsung/exynos_wdt.c
245
sc->sc_wdog_prescaler = div;
sys/arch/arm/samsung/exynos_wdt.c
249
sc->sc_wdog_prescaler = div;
sys/arch/arm/sunxi/sun4i_a10_ccu.c
419
.u.div.reg = LCD0CH0_CFG_REG,
sys/arch/arm/sunxi/sun4i_a10_ccu.c
420
.u.div.parents = lcd_parents,
sys/arch/arm/sunxi/sun4i_a10_ccu.c
421
.u.div.nparents = __arraycount(lcd_parents),
sys/arch/arm/sunxi/sun4i_a10_ccu.c
422
.u.div.div = 0,
sys/arch/arm/sunxi/sun4i_a10_ccu.c
423
.u.div.sel = __BITS(25,24),
sys/arch/arm/sunxi/sun4i_a10_ccu.c
424
.u.div.enable = __BIT(31),
sys/arch/arm/sunxi/sun4i_a10_ccu.c
425
.u.div.flags = 0,
sys/arch/arm/sunxi/sun4i_a10_ccu.c
436
.u.div.reg = LCD1CH0_CFG_REG,
sys/arch/arm/sunxi/sun4i_a10_ccu.c
437
.u.div.parents = lcd_parents,
sys/arch/arm/sunxi/sun4i_a10_ccu.c
438
.u.div.nparents = __arraycount(lcd_parents),
sys/arch/arm/sunxi/sun4i_a10_ccu.c
439
.u.div.div = 0,
sys/arch/arm/sunxi/sun4i_a10_ccu.c
440
.u.div.sel = __BITS(25,24),
sys/arch/arm/sunxi/sun4i_a10_ccu.c
441
.u.div.enable = __BIT(31),
sys/arch/arm/sunxi/sun4i_a10_ccu.c
442
.u.div.flags = 0,
sys/arch/arm/sunxi/sun4i_a10_ccu.c
453
.u.div.reg = LCD0CH1_CFG_REG,
sys/arch/arm/sunxi/sun4i_a10_ccu.c
454
.u.div.parents = lcd_parents,
sys/arch/arm/sunxi/sun4i_a10_ccu.c
455
.u.div.nparents = __arraycount(lcd_parents),
sys/arch/arm/sunxi/sun4i_a10_ccu.c
456
.u.div.div = __BITS(3,0),
sys/arch/arm/sunxi/sun4i_a10_ccu.c
457
.u.div.sel = __BITS(25,24),
sys/arch/arm/sunxi/sun4i_a10_ccu.c
458
.u.div.enable = __BIT(15) | __BIT(31),
sys/arch/arm/sunxi/sun4i_a10_ccu.c
459
.u.div.flags = 0,
sys/arch/arm/sunxi/sun4i_a10_ccu.c
469
.u.div.reg = LCD1CH1_CFG_REG,
sys/arch/arm/sunxi/sun4i_a10_ccu.c
470
.u.div.parents = lcd_parents,
sys/arch/arm/sunxi/sun4i_a10_ccu.c
471
.u.div.nparents = __arraycount(lcd_parents),
sys/arch/arm/sunxi/sun4i_a10_ccu.c
472
.u.div.div = __BITS(3,0),
sys/arch/arm/sunxi/sun4i_a10_ccu.c
473
.u.div.sel = __BITS(25,24),
sys/arch/arm/sunxi/sun4i_a10_ccu.c
474
.u.div.enable = __BIT(15) | __BIT(31),
sys/arch/arm/sunxi/sun4i_a10_ccu.c
475
.u.div.flags = 0,
sys/arch/arm/sunxi/sun8i_a23_apbclk.c
175
const u_int div = __SHIFTOUT(val, APB0_DIV);
sys/arch/arm/sunxi/sun8i_a23_apbclk.c
177
return clk_get_rate(clk_parent) / (div + 1);
sys/arch/arm/sunxi/sunxi_ccu.h
206
uint32_t div;
sys/arch/arm/sunxi/sunxi_ccu.h
238
.u.div.reg = (_reg), \
sys/arch/arm/sunxi/sunxi_ccu.h
239
.u.div.parents = (_parents), \
sys/arch/arm/sunxi/sunxi_ccu.h
240
.u.div.nparents = __arraycount(_parents), \
sys/arch/arm/sunxi/sunxi_ccu.h
241
.u.div.div = (_div), \
sys/arch/arm/sunxi/sunxi_ccu.h
242
.u.div.sel = (_sel), \
sys/arch/arm/sunxi/sunxi_ccu.h
243
.u.div.enable = (_enable), \
sys/arch/arm/sunxi/sunxi_ccu.h
244
.u.div.flags = (_flags), \
sys/arch/arm/sunxi/sunxi_ccu.h
271
uint32_t div;
sys/arch/arm/sunxi/sunxi_ccu.h
304
.u.prediv.div = (_div), \
sys/arch/arm/sunxi/sunxi_ccu.h
340
u_int div;
sys/arch/arm/sunxi/sunxi_ccu.h
356
.u.fixed_factor.div = (_div), \
sys/arch/arm/sunxi/sunxi_ccu.h
454
struct sunxi_ccu_div div;
sys/arch/arm/sunxi/sunxi_ccu_div.c
105
struct sunxi_ccu_div *div = &clk->u.div;
sys/arch/arm/sunxi/sunxi_ccu_div.c
113
for (index = 0; index < div->nparents; index++) {
sys/arch/arm/sunxi/sunxi_ccu_div.c
114
pname = div->parents[index];
sys/arch/arm/sunxi/sunxi_ccu_div.c
137
struct sunxi_ccu_div *div = &clk->u.div;
sys/arch/arm/sunxi/sunxi_ccu_div.c
150
if (div->div == 0) {
sys/arch/arm/sunxi/sunxi_ccu_div.c
151
if ((div->flags & SUNXI_CCU_DIV_SET_RATE_PARENT) != 0)
sys/arch/arm/sunxi/sunxi_ccu_div.c
157
val = CCU_READ(sc, div->reg);
sys/arch/arm/sunxi/sunxi_ccu_div.c
164
if ((div->flags & SUNXI_CCU_DIV_TIMES_TWO) != 0) {
sys/arch/arm/sunxi/sunxi_ccu_div.c
168
} else if ((div->flags & SUNXI_CCU_DIV_POWER_OF_TWO) != 0) {
sys/arch/arm/sunxi/sunxi_ccu_div.c
173
if (raw_div > __SHIFTOUT_MASK(div->div))
sys/arch/arm/sunxi/sunxi_ccu_div.c
176
val &= ~div->div;
sys/arch/arm/sunxi/sunxi_ccu_div.c
177
val |= __SHIFTIN(raw_div, div->div);
sys/arch/arm/sunxi/sunxi_ccu_div.c
178
CCU_WRITE(sc, div->reg, val);
sys/arch/arm/sunxi/sunxi_ccu_div.c
187
struct sunxi_ccu_div *div = &clk->u.div;
sys/arch/arm/sunxi/sunxi_ccu_div.c
193
if (div->sel == 0)
sys/arch/arm/sunxi/sunxi_ccu_div.c
196
for (index = 0; index < div->nparents; index++) {
sys/arch/arm/sunxi/sunxi_ccu_div.c
197
if (div->parents[index] != NULL &&
sys/arch/arm/sunxi/sunxi_ccu_div.c
198
strcmp(div->parents[index], name) == 0)
sys/arch/arm/sunxi/sunxi_ccu_div.c
201
if (index == div->nparents)
sys/arch/arm/sunxi/sunxi_ccu_div.c
204
val = CCU_READ(sc, div->reg);
sys/arch/arm/sunxi/sunxi_ccu_div.c
205
val &= ~div->sel;
sys/arch/arm/sunxi/sunxi_ccu_div.c
206
val |= __SHIFTIN(index, div->sel);
sys/arch/arm/sunxi/sunxi_ccu_div.c
207
CCU_WRITE(sc, div->reg, val);
sys/arch/arm/sunxi/sunxi_ccu_div.c
216
struct sunxi_ccu_div *div = &clk->u.div;
sys/arch/arm/sunxi/sunxi_ccu_div.c
222
if (div->sel == 0)
sys/arch/arm/sunxi/sunxi_ccu_div.c
223
return div->parents[0];
sys/arch/arm/sunxi/sunxi_ccu_div.c
225
val = CCU_READ(sc, div->reg);
sys/arch/arm/sunxi/sunxi_ccu_div.c
226
index = __SHIFTOUT(val, div->sel);
sys/arch/arm/sunxi/sunxi_ccu_div.c
228
return div->parents[index];
sys/arch/arm/sunxi/sunxi_ccu_div.c
43
struct sunxi_ccu_div *div = &clk->u.div;
sys/arch/arm/sunxi/sunxi_ccu_div.c
48
if (!div->enable)
sys/arch/arm/sunxi/sunxi_ccu_div.c
51
val = CCU_READ(sc, div->reg);
sys/arch/arm/sunxi/sunxi_ccu_div.c
53
val |= div->enable;
sys/arch/arm/sunxi/sunxi_ccu_div.c
55
val &= ~div->enable;
sys/arch/arm/sunxi/sunxi_ccu_div.c
56
CCU_WRITE(sc, div->reg, val);
sys/arch/arm/sunxi/sunxi_ccu_div.c
65
struct sunxi_ccu_div *div = &clk->u.div;
sys/arch/arm/sunxi/sunxi_ccu_div.c
81
val = CCU_READ(sc, div->reg);
sys/arch/arm/sunxi/sunxi_ccu_div.c
82
if (div->div)
sys/arch/arm/sunxi/sunxi_ccu_div.c
83
ratio = __SHIFTOUT(val, div->div);
sys/arch/arm/sunxi/sunxi_ccu_div.c
87
if ((div->flags & SUNXI_CCU_DIV_ZERO_IS_ONE) != 0 && ratio == 0)
sys/arch/arm/sunxi/sunxi_ccu_div.c
89
if (div->flags & SUNXI_CCU_DIV_POWER_OF_TWO)
sys/arch/arm/sunxi/sunxi_ccu_div.c
91
else if (div->flags & SUNXI_CCU_DIV_TIMES_TWO) {
sys/arch/arm/sunxi/sunxi_ccu_fixed_factor.c
64
return (u_int)(((uint64_t)p_rate * fixed_factor->mult) / fixed_factor->div);
sys/arch/arm/sunxi/sunxi_ccu_fixed_factor.c
88
rate *= fixed_factor->div;
sys/arch/arm/sunxi/sunxi_ccu_prediv.c
45
u_int rate, pre, div, sel;
sys/arch/arm/sunxi/sunxi_ccu_prediv.c
64
if (prediv->div)
sys/arch/arm/sunxi/sunxi_ccu_prediv.c
65
div = __SHIFTOUT(val, prediv->div);
sys/arch/arm/sunxi/sunxi_ccu_prediv.c
67
div = 0;
sys/arch/arm/sunxi/sunxi_ccu_prediv.c
71
div = 1 << div;
sys/arch/arm/sunxi/sunxi_ccu_prediv.c
73
div++;
sys/arch/arm/sunxi/sunxi_ccu_prediv.c
84
return rate / pre / div;
sys/arch/arm/sunxi/sunxi_ccu_prediv.c
86
return rate / div;
sys/arch/arm/sunxi/sunxi_emac.c
1050
int error, div;
sys/arch/arm/sunxi/sunxi_emac.c
1102
div = freq / MDIO_FREQ;
sys/arch/arm/sunxi/sunxi_emac.c
1103
if (div <= 16)
sys/arch/arm/sunxi/sunxi_emac.c
1105
else if (div <= 32)
sys/arch/arm/sunxi/sunxi_emac.c
1107
else if (div <= 64)
sys/arch/arm/sunxi/sunxi_emac.c
1109
else if (div <= 128)
sys/arch/arm/sunxi/sunxi_i2s.c
250
sunxi_i2s_div_to_regval(const u_int *divmap, u_int divmaplen, u_int div)
sys/arch/arm/sunxi/sunxi_i2s.c
255
if (divmap[n] == div)
sys/arch/arm/sunxi/sunxi_tcon.c
478
for (u_int div = 7; div <= 15; div++) {
sys/arch/arm/sunxi/sunxi_tcon.c
480
clk_freq = clk_round_rate(sc->sc_clk_ch0, lcd_dclk_freq * div);
sys/arch/arm/sunxi/sunxi_tcon.c
483
dot_freq = clk_freq / div;
sys/arch/arm/sunxi/sunxi_tcon.c
487
best_div = div;
sys/arch/arm/ti/ti_div_clock.c
171
u_int div, max_div, bit_shift;
sys/arch/arm/ti/ti_div_clock.c
198
div = __SHIFTOUT(val, mask) + (start_index ? 0 : 1);
sys/arch/arm/ti/ti_div_clock.c
199
if (div == 0)
sys/arch/arm/ti/ti_div_clock.c
204
return (u_int)(parent_rate / div);
sys/arch/arm/ti/ti_dpll_clock.c
260
const u_int div = __SHIFTOUT(val, DPLL_DIV) + 1;
sys/arch/arm/ti/ti_dpll_clock.c
264
return (u_int)((mult * parent_rate) / div);
sys/arch/arm/ti/ti_dpll_clock.c
291
const u_int div = (parent_rate / 1000000) - 1;
sys/arch/arm/ti/ti_dpll_clock.c
292
const u_int mult = rate / (parent_rate / (div + 1));
sys/arch/arm/ti/ti_dpll_clock.c
305
mult_div1 |= __SHIFTIN(div, DPLL_DIV);
sys/arch/arm/ti/ti_dpll_clock.c
331
const u_int div = (parent_rate / 1000000) - 1;
sys/arch/arm/ti/ti_dpll_clock.c
332
const u_int mult = rate / (parent_rate / (div + 1));
sys/arch/arm/ti/ti_dpll_clock.c
344
mult_div1 |= __SHIFTIN(div, DPLL_DIV);
sys/arch/arm/ti/ti_dpll_clock.c
370
const u_int div = __SHIFTOUT(val, OMAP3_CORE_DPLL_DIV) + 1;
sys/arch/arm/ti/ti_dpll_clock.c
375
return (u_int)((mult * parent_rate) / div) / postdiv;
sys/arch/arm/ti/ti_dpll_clock.c
391
const u_int div = __SHIFTOUT(val, DPLL_DIV) + 1;
sys/arch/arm/ti/ti_dpll_clock.c
396
return (u_int)((mult * parent_rate) / div) / postdiv;
sys/arch/arm/ti/ti_lcdc.c
160
int clk_div, div, diff, best_diff;
sys/arch/arm/ti/ti_lcdc.c
174
for (div = 2; div < 255; div++) {
sys/arch/arm/ti/ti_lcdc.c
175
const int pixel_clock = (rate / div) / 1000;
sys/arch/arm/ti/ti_lcdc.c
179
clk_div = div;
sys/arch/arm/ti/ti_prcm.h
114
const u_int div = tc->u.fixed_factor.div;
sys/arch/arm/ti/ti_prcm.h
116
return (clk_get_rate(&tc_parent->base) * mult) / div;
sys/arch/arm/ti/ti_prcm.h
130
.u.fixed_factor.div = (_div), \
sys/arch/arm/ti/ti_prcm.h
52
u_int div;
sys/arch/arm/xilinx/zynq_uart.c
2159
zynquart_set_frequency(u_int freq, u_int div)
sys/arch/arm/xilinx/zynq_uart.c
2162
zynquart_freqdiv = div;
sys/arch/arm/xscale/pxa2x0_i2s.c
150
int div;
sys/arch/arm/xscale/pxa2x0_i2s.c
174
sc->sc_sadiv = speed_table[selected].div;
sys/arch/arm/xscale/pxa2x0_mci.c
454
int div;
sys/arch/arm/xscale/pxa2x0_mci.c
494
for (div = 0; div < 7; actfreq /= 2, div++) {
sys/arch/arm/xscale/pxa2x0_mci.c
498
if (div == 7) {
sys/arch/arm/xscale/pxa2x0_mci.c
506
device_xname(sc->sc_dev), freq, actfreq, div));
sys/arch/arm/xscale/pxa2x0_mci.c
509
sc->sc_clkrt = div;
sys/arch/atari/dev/ser.c
1315
int div, x, err;
sys/arch/atari/dev/ser.c
1320
for (div = 4; div <= 64; div *= 4) {
sys/arch/atari/dev/ser.c
1321
x = divrnd((SER_FREQ / div), speed);
sys/arch/atari/dev/ser.c
1337
err = divrnd((SER_FREQ / div) * 1000, speed * x) - 1000;
sys/arch/atari/dev/ser.c
1346
if (div == 4)
sys/arch/atari/dev/ser.c
1347
div = 1;
sys/arch/atari/dev/ser.c
1348
else if (div == 16)
sys/arch/atari/dev/ser.c
1349
div = 3;
sys/arch/atari/dev/ser.c
1350
else if (div == 64)
sys/arch/atari/dev/ser.c
1351
div = 5;
sys/arch/atari/dev/ser.c
1353
return (x / 2) | (div << 8);
sys/arch/atari/dev/zs.c
1202
int diff, bps, div, clkm, brgm, tcon;
sys/arch/atari/dev/zs.c
1204
bps = div = clkm = brgm = tcon = 0;
sys/arch/atari/dev/zs.c
1222
div = ZSWR4_CLK_X16;
sys/arch/atari/dev/zs.c
1237
div = ZSWR4_CLK_X16;
sys/arch/atari/dev/zs.c
1240
div = ZSWR4_CLK_X32;
sys/arch/atari/dev/zs.c
1243
div = ZSWR4_CLK_X64;
sys/arch/atari/dev/zs.c
1252
*divisor = div;
sys/arch/evbarm/dev/plcom.c
368
int div = frequency / denom;
sys/arch/evbarm/dev/plcom.c
371
int ibrd = div << 6;
sys/arch/evbarm/stand/board/sscom.c
195
uint32_t div = read_reg(S3C2800_CLKMAN_BASE+CLKMAN_CLKCON);
sys/arch/evbarm/stand/board/sscom.c
201
uint32_t div = read_reg(S3C2410_CLKMAN_BASE+CLKMAN_CLKDIVN);
sys/arch/evbarm/stand/board/sscom.c
218
if (div & HDIV)
sys/arch/evbarm/stand/board/sscom.c
220
if (div & PDIV)
sys/arch/evbarm/stand/boot2440/s3csdi.c
109
int div;
sys/arch/evbarm/stand/boot2440/s3csdi.c
125
for (div = 1; div <= 256; div++) {
sys/arch/evbarm/stand/boot2440/s3csdi.c
126
if ( clk / div <= freq) {
sys/arch/evbarm/stand/boot2440/s3csdi.c
127
DPRINTF(("Using divisor %d: %d/%d = %d\n", div, clk,
sys/arch/evbarm/stand/boot2440/s3csdi.c
128
div, clk/div));
sys/arch/evbarm/stand/boot2440/s3csdi.c
130
SDI_REG(SDI_PRE) = div-1;
sys/arch/evbarm/stand/boot2440/s3csdi.c
137
if (div-1 != SDI_REG(SDI_PRE)) {
sys/arch/hpcarm/dev/ipaq_lcdreg.h
69
#define CR3_PCD(div) (((div) - 4)/2) /* PCD ; Pixel clock divisor */
sys/arch/hpcarm/dev/ipaq_lcdreg.h
70
#define CR3_ACB(div) (((div) - 2)/2) /* ACB ; */
sys/arch/hpcarm/dev/ipaq_lcdreg.h
71
#define CR3_API(div) ((div) << 16) /* API ; AC Bias */
sys/arch/hpcmips/tx/tx3912video.c
618
int mul, div;
sys/arch/hpcmips/tx/tx3912video.c
662
return ((0xff * dlp->mul) / dlp->div);
sys/arch/hpcmips/tx/tx3912video.c
671
return ((0xff * dlp->mul) / dlp->div);
sys/arch/powerpc/mpc5200/fec.c
207
uint32_t div;
sys/arch/powerpc/mpc5200/fec.c
219
div = howmany(sc->sc_ipb_freq, 2 * FEC_MII_MAX_CLK);
sys/arch/powerpc/mpc5200/fec.c
220
if (div > 0x3f)
sys/arch/powerpc/mpc5200/fec.c
221
div = 0x3f;
sys/arch/powerpc/mpc5200/fec.c
222
FEC_WRITE(sc, FEC_MII_SPEED, FEC_MII_SPEED_DIV(div));
sys/arch/powerpc/mpc5200/fecreg.h
152
#define FEC_MII_SPEED_DIV(div) (((div) & 0x3f) << 1)
sys/arch/powerpc/mpc5200/psc.c
196
u_int div = psc_baud_divisor(ipb, PSC_CONSOLE_SPEED);
sys/arch/powerpc/mpc5200/psc.c
203
ipb / 1000000, (ipb / 100000) % 10, PSC_CONSOLE_SPEED, div);
sys/arch/powerpc/mpc5200/psc.c
273
u_int div;
sys/arch/powerpc/mpc5200/psc.c
278
div = (ipb + (PSC_BAUD_PRESCALE / 2) * baud) /
sys/arch/powerpc/mpc5200/psc.c
280
if (div < 1)
sys/arch/powerpc/mpc5200/psc.c
281
div = 1;
sys/arch/powerpc/mpc5200/psc.c
282
if (div > 0xffff)
sys/arch/powerpc/mpc5200/psc.c
283
div = 0xffff;
sys/arch/powerpc/mpc5200/psc.c
284
return div;
sys/arch/powerpc/mpc5200/psc.c
293
u_int div = psc_baud_divisor(mpc5200_cdm_get_ipb_freq(), baud);
sys/arch/powerpc/mpc5200/psc.c
304
bus_space_write_1(iot, ioh, PSC_CTUR, (div >> 8) & 0xff);
sys/arch/powerpc/mpc5200/psc.c
305
bus_space_write_1(iot, ioh, PSC_CTLR, div & 0xff);
sys/arch/powerpc/oea/cpu_subr.c
1303
cpu_set_dfs(int div)
sys/arch/powerpc/oea/cpu_subr.c
1325
where = xc_broadcast(0, (xcfunc_t)cpu_set_dfs_xcall, &div, &dfs_mask);
sys/arch/powerpc/oea/cpu_subr.c
1328
cpu_set_dfs_xcall(&div, &dfs_mask);
sys/arch/riscv/starfive/jh71x0_clkc.c
232
uint32_t div = __SHIFTOUT(val, JH71X0_CLK_DIV_MASK);
sys/arch/riscv/starfive/jh71x0_clkc.c
234
return rate / div;
sys/arch/riscv/starfive/jh71x0_clkc.c
258
u_int div = uimin(ratio, jcc_div->jcd_maxdiv);
sys/arch/riscv/starfive/jh71x0_clkc.c
260
KASSERT(div <= __SHIFTOUT_MASK(JH71X0_CLK_DIV_MASK));
sys/arch/riscv/starfive/jh71x0_clkc.c
263
__SHIFTIN(div, JH71X0_CLK_DIV_MASK), JH71X0_CLK_DIV_MASK);
sys/arch/riscv/starfive/jh71x0_clkc.c
331
u_int div = uimin(ratio, jcc_div->jcd_maxdiv);
sys/arch/riscv/starfive/jh71x0_clkc.c
333
KASSERT(div <= __SHIFTOUT_MASK(JH71X0_CLK_DIV_MASK));
sys/arch/riscv/starfive/jh71x0_clkc.c
336
__SHIFTIN(div, JH71X0_CLK_DIV_MASK), JH71X0_CLK_DIV_MASK);
sys/arch/riscv/starfive/jh71x0_clkc.c
421
uint32_t div = __SHIFTOUT(val, JH71X0_CLK_DIV_MASK);
sys/arch/riscv/starfive/jh71x0_clkc.c
423
return rate / div;
sys/arch/riscv/starfive/jh71x0_clkc.c
447
u_int div = uimin(ratio, jcc_muxdiv->jcmd_maxdiv);
sys/arch/riscv/starfive/jh71x0_clkc.c
449
KASSERT(div <= __SHIFTOUT_MASK(JH71X0_CLK_DIV_MASK));
sys/arch/riscv/starfive/jh71x0_clkc.c
452
__SHIFTIN(div, JH71X0_CLK_DIV_MASK), JH71X0_CLK_DIV_MASK);
sys/arch/sandpoint/stand/altboot/brdsetup.c
1151
unsigned div;
sys/arch/sandpoint/stand/altboot/brdsetup.c
1153
div = busclock / speed / 16;
sys/arch/sandpoint/stand/altboot/brdsetup.c
1156
UART_WRITE(base, DMB, div >> 8); /* set speed */
sys/arch/sandpoint/stand/altboot/brdsetup.c
1157
UART_WRITE(base, DLB, div & 0xff);
sys/arch/sgimips/dev/crmfb.c
1703
int error, div, best = 9999999;
sys/arch/sgimips/dev/crmfb.c
1711
div = N * (1 << P);
sys/arch/sgimips/dev/crmfb.c
1712
M = f_out * div / f_in;
sys/arch/sgimips/dev/crmfb.c
1714
ff1 = M * f_in / div;
sys/arch/sgimips/dev/crmfb.c
1715
ff2 = (M + 1) * f_in / div;
sys/arch/sgimips/dev/scn.c
357
uint16_t div;
sys/arch/sgimips/dev/scn.c
491
uint16_t div;
sys/arch/sgimips/dev/scn.c
498
div = divs[i].div;
sys/arch/sgimips/dev/scn.c
505
div = ((long)SCN_CLOCK/16/2 + dp->counter/2) / dp->counter;
sys/arch/sgimips/dev/scn.c
511
dp->base[DU_CTUR] = div >> 8;
sys/arch/sgimips/dev/scn.c
512
dp->base[DU_CTLR] = div & 255;
sys/arch/sparc/sparc/emul.c
149
unsigned div:1; /* one if divide */
sys/arch/sparc/sparc/emul.c
160
"us"[op.bits.sgn], op.bits.div ? "div" : "mul",
sys/arch/sparc/sparc/emul.c
169
if (op.bits.div) {
sys/arch/sparc/sparc/emul.c
197
if (op.bits.div) {
sys/arch/sparc64/sparc64/emul.c
148
unsigned div:1; /* one if divide */
sys/arch/sparc64/sparc64/emul.c
159
"us"[op.bits.sgn], op.bits.div ? "div" : "mul",
sys/arch/sparc64/sparc64/emul.c
168
if (op.bits.div) {
sys/arch/sparc64/sparc64/emul.c
196
if (op.bits.div) {
sys/compat/linux/common/linux_statfs.h
113
div = bsp->f_frsize ? (bsp->f_bsize / bsp->f_frsize) : 1;
sys/compat/linux/common/linux_statfs.h
114
if (div == 0)
sys/compat/linux/common/linux_statfs.h
115
div = 1;
sys/compat/linux/common/linux_statfs.h
118
lsp->l_fblocks = bsp->f_blocks / div;
sys/compat/linux/common/linux_statfs.h
119
lsp->l_fbfree = bsp->f_bfree / div;
sys/compat/linux/common/linux_statfs.h
120
lsp->l_fbavail = bsp->f_bavail / div;
sys/compat/linux/common/linux_statfs.h
122
lsp->l_fffree = bsp->f_ffree / div;
sys/compat/linux/common/linux_statfs.h
98
int i, div;
sys/dev/dec/lk201.h
110
#define LK_CMD_MODE(m,div) ((m)|((div)<<3))
sys/dev/dec/lk201reg.h
63
#define LK_CMD_MODE(m,div) ((m)|((div)<<3))
sys/dev/fdt/fixedfactorclock.c
106
of_getprop_uint32(phandle, "clock-div", &sc->sc_clk.div);
sys/dev/fdt/fixedfactorclock.c
109
if (sc->sc_clk.div == 0 || sc->sc_clk.mult == 0) {
sys/dev/fdt/fixedfactorclock.c
124
sc->sc_clk.mult, sc->sc_clk.div);
sys/dev/fdt/fixedfactorclock.c
170
return (clk_get_rate(clkp_parent) * fclk->mult) / fclk->div;
sys/dev/fdt/fixedfactorclock.c
64
u_int div;
sys/dev/i2c/adm1026.c
123
#define VAL_TO_SPEED(val, div) (1350000 / (val * div))
sys/dev/i2c/adm1026.c
124
#define SPEED_TO_VAL(spd, div) ((1350000 / (spd * div)) & 0xff)
sys/dev/i2c/tda19988.c
405
uint8_t reg, div;
sys/dev/i2c/tda19988.c
449
div = 148500 / mode->crtc_clock;
sys/dev/i2c/tda19988.c
450
if (div != 0) {
sys/dev/i2c/tda19988.c
451
div--;
sys/dev/i2c/tda19988.c
452
if (div > 3)
sys/dev/i2c/tda19988.c
453
div = 3;
sys/dev/i2c/tda19988.c
478
tda19988_reg_write(sc, TDA_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
sys/dev/i2c/xc3028.c
533
uint32_t div, offset = 0;
sys/dev/i2c/xc3028.c
542
div = (params->frequency - offset + 15625 / 2) / 15625;
sys/dev/i2c/xc3028.c
549
freq_buf[0] = (div >> 24) & 0xff;
sys/dev/i2c/xc3028.c
550
freq_buf[1] = (div >> 16) & 0xff;
sys/dev/i2c/xc3028.c
551
freq_buf[2] = (div >> 8) & 0xff;
sys/dev/i2c/xc3028.c
552
freq_buf[3] = (div >> 0) & 0xff;
sys/dev/ic/arn9003.c
2323
int32_t div, f1, f2, f3, m, p, c;
sys/dev/ic/arn9003.c
2363
div = ymax - (ymax / 32) + (ymin / 8) + (ymin / 4);
sys/dev/ic/arn9003.c
2364
if (div == 0)
sys/dev/ic/arn9003.c
2367
sin[i] = (sin[i] * SCALE) / div;
sys/dev/ic/arn9003.c
2368
cos[i] = (cos[i] * SCALE) / div;
sys/dev/ic/bwi.c
7123
uint div;
sys/dev/ic/bwi.c
7137
div = 0;
sys/dev/ic/bwi.c
7143
div = 64;
sys/dev/ic/bwi.c
7146
div = 32;
sys/dev/ic/bwi.c
7153
div = 1;
sys/dev/ic/bwi.c
7155
div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2;
sys/dev/ic/bwi.c
7165
div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2;
sys/dev/ic/bwi.c
7169
KASSERT(div != 0);
sys/dev/ic/bwi.c
7175
freq->clkfreq_min = bwi_clkfreq[src].freq_min / div;
sys/dev/ic/bwi.c
7176
freq->clkfreq_max = bwi_clkfreq[src].freq_max / div;
sys/dev/ic/hd64570.c
2076
u_int32_t mhz, div;
sys/dev/ic/hd64570.c
2086
div = scp->sp_rxs & SCA_RXS_DIV_MASK;
sys/dev/ic/hd64570.c
2097
printf("internal %d Hz", (mhz >> div));
sys/dev/ic/hd64570.c
2100
printf("adpll using internal %d Hz", (mhz >> div));
sys/dev/ic/hd64570.c
2107
div = scp->sp_txs & SCA_TXS_DIV_MASK;
sys/dev/ic/hd64570.c
2113
printf("internal %d Hz\n", (mhz >> div));
sys/dev/ic/hd64570.c
483
u_int32_t tmc, div;
sys/dev/ic/hd64570.c
509
div = 0;
sys/dev/ic/hd64570.c
512
div++;
sys/dev/ic/hd64570.c
519
if (div > SCA_RXS_DIV_512) {
sys/dev/ic/hd64570.c
521
div = SCA_RXS_DIV_512;
sys/dev/ic/hd64570.c
526
return (div & 0xFF);
sys/dev/ic/rtsx.c
756
rtsx_switch_sd_clock(struct rtsx_softc *sc, uint8_t n, int div, int mcu)
sys/dev/ic/rtsx.c
768
RTSX_WRITE(sc, RTSX_CLK_DIV, (div << 4) | mcu);
sys/dev/ic/rtsx.c
838
int div;
sys/dev/ic/rtsx.c
857
div = RTSX_CLK_DIV_8;
sys/dev/ic/rtsx.c
865
div = RTSX_CLK_DIV_4;
sys/dev/ic/rtsx.c
873
div = RTSX_CLK_DIV_4;
sys/dev/ic/rtsx.c
881
div = RTSX_CLK_DIV_4;
sys/dev/ic/rtsx.c
889
div = RTSX_CLK_DIV_2;
sys/dev/ic/rtsx.c
897
div = RTSX_CLK_DIV_2;
sys/dev/ic/rtsx.c
911
error = rtsx_switch_sd_clock(sc, n, div, mcu);
sys/dev/ic/wd33c93.c
294
u_int my_id, s, div, i;
sys/dev/ic/wd33c93.c
346
div = 2;
sys/dev/ic/wd33c93.c
349
div = 3;
sys/dev/ic/wd33c93.c
352
div = 4;
sys/dev/ic/wd33c93.c
358
(i + 2) * div * 1250 / sc->sc_clkfreq;
sys/dev/pci/eap.c
1003
div |= EAP_SET_PCLKDIV(EAP_XTAL_FREQ / play->sample_rate - 2);
sys/dev/pci/eap.c
1005
div |= EAP_CCB_INTRM;
sys/dev/pci/eap.c
1012
EWRITE4(sc, EAP_ICSC, div);
sys/dev/pci/eap.c
1013
DPRINTFN(2, ("%s: set ICSC = 0x%08x\n", __func__, div));
sys/dev/pci/eap.c
1019
div = EREAD4(sc, EAP_ICSC);
sys/dev/pci/eap.c
1020
DPRINTFN(2, ("%s: old ICSC = 0x%08x\n", __func__, div));
sys/dev/pci/eap.c
1022
div &= ~EAP_WTSRSEL;
sys/dev/pci/eap.c
1024
div |= EAP_WTSRSEL_5;
sys/dev/pci/eap.c
1026
div |= EAP_WTSRSEL_11;
sys/dev/pci/eap.c
1028
div |= EAP_WTSRSEL_22;
sys/dev/pci/eap.c
1030
div |= EAP_WTSRSEL_44;
sys/dev/pci/eap.c
1032
EWRITE4(sc, EAP_ICSC, div);
sys/dev/pci/eap.c
1033
DPRINTFN(2, ("%s: set ICSC = 0x%08x\n", __func__, div));
sys/dev/pci/eap.c
979
uint32_t div;
sys/dev/pci/eap.c
991
div = EREAD4(sc, EAP_ICSC) & ~EAP_PCLKBITS;
sys/dev/pci/if_iwmreg.h
3378
struct iwm_statistics_div div;
sys/dev/pci/if_iwn.c
4129
int i, ant, div, delta;
sys/dev/pci/if_iwn.c
4132
div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30;
sys/dev/pci/if_iwn.c
4145
(int32_t)calib->noise[i]) / div;
sys/dev/pci/qat/qat.c
1131
u_int div = data >> shift;
sys/dev/pci/qat/qat.c
1132
u_int mult = div << shift;
sys/dev/pci/radeonfb.c
1744
int div;
sys/dev/pci/radeonfb.c
1747
for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) {
sys/dev/pci/radeonfb.c
1749
if ((flags & NO_ODD_FBDIV) && ((div & 1) != 0))
sys/dev/pci/radeonfb.c
1758
if ((sc->sc_family == RADEON_RV350) && (div > 4))
sys/dev/pci/radeonfb.c
1761
outfreq = div * dotclock;
sys/dev/pci/radeonfb.c
1767
DPRINTF(("post divider: %d (mask %x)\n", div,
sys/dev/pci/radeonfb.c
1773
if (div == 0)
sys/dev/pci/viaenv.c
170
val_to_rpm(unsigned int val, int div)
sys/dev/pci/viaenv.c
176
return 1350000 / val / div;
sys/dev/sdmmc/sdhc.c
1021
u_int div;
sys/dev/sdmmc/sdhc.c
1024
for (div = hp->clkbase / freq; div <= 0x3ff; div++) {
sys/dev/sdmmc/sdhc.c
1025
if ((hp->clkbase / div) <= freq) {
sys/dev/sdmmc/sdhc.c
1027
| ((div & 0x300) << SDHC_SDCLK_XDIV_SHIFT)
sys/dev/sdmmc/sdhc.c
1028
| ((div & 0x0ff) << SDHC_SDCLK_DIV_SHIFT);
sys/dev/sdmmc/sdhc.c
1039
for (dvs >>= 1, div = 1; div <= 256; div <<= 1, dvs >>= 1) {
sys/dev/sdmmc/sdhc.c
1042
*divp = (div << SDHC_SDCLK_DIV_SHIFT)
sys/dev/sdmmc/sdhc.c
1046
HDEVNAME(hp), freq, div * 2, dvs + 1));
sys/dev/sdmmc/sdhc.c
1059
div = howmany(hp->clkbase, freq);
sys/dev/sdmmc/sdhc.c
1060
if (div > (hp->sc->sc_clkmsk >> (ffs(hp->sc->sc_clkmsk) - 1)))
sys/dev/sdmmc/sdhc.c
1062
*divp = div << (ffs(hp->sc->sc_clkmsk) - 1);
sys/dev/sdmmc/sdhc.c
1067
div = howmany(hp->clkbase, freq);
sys/dev/sdmmc/sdhc.c
1068
div = div > 1 ? howmany(div, 2) : 0;
sys/dev/sdmmc/sdhc.c
1069
if (div > 0x3ff)
sys/dev/sdmmc/sdhc.c
1071
*divp = (((div >> 8) & SDHC_SDCLK_XDIV_MASK)
sys/dev/sdmmc/sdhc.c
1073
(((div >> 0) & SDHC_SDCLK_DIV_MASK)
sys/dev/sdmmc/sdhc.c
1078
for (div = 1; div <= 256; div *= 2) {
sys/dev/sdmmc/sdhc.c
1079
if ((hp->clkbase / div) <= freq) {
sys/dev/sdmmc/sdhc.c
1080
*divp = (div / 2) << SDHC_SDCLK_DIV_SHIFT;
sys/dev/sdmmc/sdhc.c
1100
u_int div;
sys/dev/sdmmc/sdhc.c
1190
if (!sdhc_clock_divisor(hp, freq, &div)) {
sys/dev/sdmmc/sdhc.c
1200
div = ((div >> 1) & (SDHC_SDCLK_DIV_MASK <<
sys/dev/sdmmc/sdhc.c
1202
(div & (SDHC_SDCLK_DVS_MASK <<
sys/dev/sdmmc/sdhc.c
1211
div | (SDHC_TIMEOUT_MAX << 16) | 0x0f);
sys/dev/sdmmc/sdhc.c
1214
div | (SDHC_TIMEOUT_MAX << 16));
sys/dev/sdmmc/sdhc.c
1218
HWRITE2(hp, SDHC_CLOCK_CTL, reg | div);
sys/dev/usb/uchcom.c
637
uint32_t best, div, pre;
sys/dev/usb/uchcom.c
658
div = try;
sys/dev/usb/uchcom.c
664
if ((rates4x[pre] / div / 4) < (rate * 99 / 100))
sys/dev/usb/uchcom.c
666
if ((rates4x[pre] / div / 4) > (rate * 101 / 100))
sys/dev/usb/uchcom.c
670
dp->dv_div = 256 - div;
sys/kern/kern_tc.c
1408
uint64_t div;
sys/kern/kern_tc.c
1446
div = (uint64_t)btd.sec << 30;
sys/kern/kern_tc.c
1447
div |= (btd.frac >> 34) & (((uint64_t)1 << 30) - 1);
sys/kern/kern_tc.c
1448
div *= pps->capth->th_counter->tc_frequency;
sys/kern/kern_tc.c
1449
div >>= 30;
sys/kern/kern_tc.c
1451
if (div == 0) /* safeguard */
sys/kern/kern_tc.c
1455
scale /= div;
tests/lib/libc/stdlib/t_div.c
50
d = div(NUM, DENOM);
usr.bin/sdiff/sdiff.c
42
char div;
usr.bin/sdiff/sdiff.c
757
diffp->div = divc;
usr.bin/sdiff/sdiff.c
854
divc = SIMPLEQ_FIRST(&diffhead)->div;
usr.bin/sdiff/sdiff.c
867
if (!sflag || diffp->div == '|' || diffp->div == '<' ||
usr.bin/sdiff/sdiff.c
868
diffp->div == '>')
usr.bin/sdiff/sdiff.c
869
println(diffp->left, diffp->div, diffp->right);