arch/arc/include/asm/arcregs.h

324

unsigned int pad3:5, mmu:3, pad2:4, ic:3, dc:3, pad1:6, ver:8;

arch/arc/include/asm/arcregs.h

326

unsigned int ver:8, pad1:6, dc:3, ic:3, pad2:4, mmu:3, pad3:5;

arch/arc/kernel/setup.c

276

IS_AVAIL3(erp.dc, !ctl.dpd, "DC "),

arch/arc/mm/cache.c

1018

struct cpuinfo_arc_cache *dc = &dc_info;

arch/arc/mm/cache.c

1020

if (!dc->line_len)

arch/arc/mm/cache.c

1023

if (dc->line_len != L1_CACHE_BYTES)

arch/arc/mm/cache.c

1025

dc->line_len, L1_CACHE_BYTES);

arch/arc/mm/cache.c

1028

if (is_isa_arcompact() && dc->colors > 1) {

arch/arm64/include/asm/assembler.h

363

dc \op, \addr

arch/arm64/include/asm/assembler.h

365

dc civac, \addr

arch/arm64/include/asm/assembler.h

399

dc \op, \start

arch/mips/include/asm/octeon/cvmx-pci-defs.h

619

uint32_t dc:1;

arch/mips/include/asm/octeon/cvmx-pci-defs.h

635

uint32_t dc:1;

arch/mips/kvm/emulate.c

653

int dc;

arch/mips/kvm/emulate.c

665

dc = kvm_mips_count_disabled(vcpu);

arch/mips/kvm/emulate.c

666

if (dc) {

arch/mips/kvm/emulate.c

682

if (!dc)

arch/mips/kvm/emulate.c

700

int dc;

arch/mips/kvm/emulate.c

732

dc = kvm_mips_count_disabled(vcpu);

arch/mips/kvm/emulate.c

733

if (!dc)

arch/mips/kvm/emulate.c

756

if (!dc)

arch/powerpc/platforms/powermac/setup.c

136

const unsigned int *dc =

arch/powerpc/platforms/powermac/setup.c

140

if (of_property_read_bool(np, "cache-unified") && dc) {

arch/powerpc/platforms/powermac/setup.c

141

seq_printf(m, " %dK unified", *dc / 1024);

arch/powerpc/platforms/powermac/setup.c

145

if (dc)

arch/powerpc/platforms/powermac/setup.c

147

(ic? " +": ""), *dc / 1024);

arch/s390/include/uapi/asm/runtime_instr.h

54

__u32 dc : 4;

arch/x86/kernel/cpu/resctrl/core.c

371

static void setup_default_ctrlval(struct rdt_resource *r, u32 *dc)

arch/x86/kernel/cpu/resctrl/core.c

381

for (i = 0; i < hw_res->num_closid; i++, dc++)

arch/x86/kernel/cpu/resctrl/core.c

382

*dc = resctrl_get_default_ctrl(r);

arch/x86/kernel/cpu/resctrl/core.c

405

u32 *dc;

arch/x86/kernel/cpu/resctrl/core.c

407

dc = kmalloc_array(hw_res->num_closid, sizeof(*hw_dom->ctrl_val),

arch/x86/kernel/cpu/resctrl/core.c

409

if (!dc)

arch/x86/kernel/cpu/resctrl/core.c

412

hw_dom->ctrl_val = dc;

arch/x86/kernel/cpu/resctrl/core.c

413

setup_default_ctrlval(r, dc);

crypto/testmgr.h

1059

be64_to_cpua(8a, 51, 84, ce, 13, 1e, d2, dc),

crypto/testmgr.h

1163

be64_to_cpua(dc, 2b, 43, 0e, 6a, b3, 53, 6f),

crypto/testmgr.h

1174

be64_to_cpua(ec, 63, e3, 0c, ec, 50, dc, cc),

crypto/testmgr.h

1209

be64_to_cpua(35, f6, dc, 6d, 02, 7b, 22, ac),

crypto/testmgr.h

1286

be64_to_cpua(ec, 51, dc, e8, 35, 5e, ae, 16),

crypto/testmgr.h

710

be64_to_cpua(14, f8, 11, 2b, 55, dc, ae, 37),

crypto/testmgr.h

911

be64_to_cpua(91, dc, 02, 67, dc, 0c, d0, 82),

crypto/testmgr.h

913

be64_to_cpua(09, dc, 29, 63, a8, 1a, ad, fc),

crypto/testmgr.h

948

be64_to_cpua(8e, f3, 6f, dc, f8, 69, a6, 2e),

crypto/testmgr.h

954

be64_to_cpua(c0, 60, 11, 92, dc, 17, 89, 12),

crypto/testmgr.h

957

be64_to_cpua(eb, a7, 80, 26, dc, f9, 3a, 44),

drivers/block/drbd/drbd_main.c

697

struct disk_conf *dc;

drivers/block/drbd/drbd_main.c

720

dc = rcu_dereference(peer_device->device->ldev->disk_conf);

drivers/block/drbd/drbd_main.c

721

p->resync_rate = cpu_to_be32(dc->resync_rate);

drivers/block/drbd/drbd_main.c

722

p->c_plan_ahead = cpu_to_be32(dc->c_plan_ahead);

drivers/block/drbd/drbd_main.c

723

p->c_delay_target = cpu_to_be32(dc->c_delay_target);

drivers/block/drbd/drbd_main.c

724

p->c_fill_target = cpu_to_be32(dc->c_fill_target);

drivers/block/drbd/drbd_main.c

725

p->c_max_rate = cpu_to_be32(dc->c_max_rate);

drivers/block/drbd/drbd_nl.c

1190

static int drbd_check_al_size(struct drbd_device *device, struct disk_conf *dc)

drivers/block/drbd/drbd_nl.c

1198

device->act_log->nr_elements == dc->al_extents)

drivers/block/drbd/drbd_nl.c

1204

dc->al_extents, sizeof(struct lc_element), 0);

drivers/block/drbd/drbd_nl.c

1531

static int disk_opts_check_al_size(struct drbd_device *device, struct disk_conf *dc)

drivers/block/drbd/drbd_nl.c

1536

device->act_log->nr_elements == dc->al_extents)

drivers/block/drbd/drbd_nl.c

1547

err = drbd_check_al_size(device, dc);

drivers/block/drbd/drbd_receiver.c

1244

struct disk_conf *dc;

drivers/block/drbd/drbd_receiver.c

1246

dc = rcu_dereference(bdev->disk_conf);

drivers/block/drbd/drbd_receiver.c

1248

if (wo == WO_BDEV_FLUSH && !dc->disk_flushes)

drivers/block/drbd/drbd_receiver.c

1250

if (wo == WO_DRAIN_IO && !dc->disk_drain)

drivers/block/drbd/drbd_receiver.c

1392

struct disk_conf *dc;

drivers/block/drbd/drbd_receiver.c

1399

dc = rcu_dereference(device->ldev->disk_conf);

drivers/block/drbd/drbd_receiver.c

1400

can_do = dc->discard_zeroes_if_aligned;

drivers/block/drbd/drbd_receiver.c

3077

int rct, dc; /* roles at crash time */

drivers/block/drbd/drbd_receiver.c

3168

dc = test_bit(RESOLVE_CONFLICTS, &connection->flags);

drivers/block/drbd/drbd_receiver.c

3169

return dc ? -1 : 1;

drivers/block/drbd/drbd_worker.c

500

struct disk_conf *dc;

drivers/block/drbd/drbd_worker.c

510

dc = rcu_dereference(device->ldev->disk_conf);

drivers/block/drbd/drbd_worker.c

516

want = ((dc->resync_rate * 2 * SLEEP_TIME) / HZ) * steps;

drivers/block/drbd/drbd_worker.c

518

want = dc->c_fill_target ? dc->c_fill_target :

drivers/block/drbd/drbd_worker.c

519

sect_in * dc->c_delay_target * HZ / (SLEEP_TIME * 10);

drivers/block/drbd/drbd_worker.c

537

max_sect = (dc->c_max_rate * 2 * SLEEP_TIME) / HZ;

drivers/block/rnbd/rnbd-srv.c

221

DECLARE_COMPLETION_ONSTACK(dc);

drivers/block/rnbd/rnbd-srv.c

233

sess_dev->destroy_comp = &dc;

drivers/block/rnbd/rnbd-srv.c

235

wait_for_completion(&dc); /* wait for inflights to drop to zero */

drivers/clk/clk-asm9260.c

302

const struct asm9260_div_clk *dc = &asm9260_div_clks[n];

drivers/clk/clk-asm9260.c

304

hws[dc->idx] = clk_hw_register_divider(NULL, dc->name,

drivers/clk/clk-asm9260.c

305

dc->parent_name, CLK_SET_RATE_PARENT,

drivers/clk/clk-asm9260.c

306

base + dc->reg, 0, 8, CLK_DIVIDER_ONE_BASED,

drivers/clk/mvebu/dove-divider.c

101

struct dove_clk *dc = to_dove_clk(hw);

drivers/clk/mvebu/dove-divider.c

102

unsigned int divider = dove_get_divider(dc);

drivers/clk/mvebu/dove-divider.c

106

__func__, dc->name, divider, parent, rate);

drivers/clk/mvebu/dove-divider.c

114

struct dove_clk *dc = to_dove_clk(hw);

drivers/clk/mvebu/dove-divider.c

118

divider = dove_calc_divider(dc, req->rate, parent_rate, false);

drivers/clk/mvebu/dove-divider.c

125

__func__, dc->name, divider, parent_rate, req->rate);

drivers/clk/mvebu/dove-divider.c

133

struct dove_clk *dc = to_dove_clk(hw);

drivers/clk/mvebu/dove-divider.c

137

divider = dove_calc_divider(dc, rate, parent_rate, true);

drivers/clk/mvebu/dove-divider.c

142

__func__, dc->name, divider, parent_rate, rate);

drivers/clk/mvebu/dove-divider.c

144

div = (u32)divider << dc->div_bit_start;

drivers/clk/mvebu/dove-divider.c

145

mask = ~(~0 << dc->div_bit_size) << dc->div_bit_start;

drivers/clk/mvebu/dove-divider.c

146

load = BIT(dc->div_bit_load);

drivers/clk/mvebu/dove-divider.c

148

spin_lock(dc->lock);

drivers/clk/mvebu/dove-divider.c

149

dove_load_divider(dc->base, div, mask, load);

drivers/clk/mvebu/dove-divider.c

150

spin_unlock(dc->lock);

drivers/clk/mvebu/dove-divider.c

162

struct dove_clk *dc, const char **parent_names, size_t num_parents,

drivers/clk/mvebu/dove-divider.c

173

strscpy(name, dc->name, sizeof(name));

drivers/clk/mvebu/dove-divider.c

175

dc->hw.init = &init;

drivers/clk/mvebu/dove-divider.c

176

dc->base = base;

drivers/clk/mvebu/dove-divider.c

177

dc->div_bit_size = dc->div_bit_end - dc->div_bit_start + 1;

drivers/clk/mvebu/dove-divider.c

179

return clk_register(dev, &dc->hw);

drivers/clk/mvebu/dove-divider.c

51

static unsigned int dove_get_divider(struct dove_clk *dc)

drivers/clk/mvebu/dove-divider.c

56

val = readl_relaxed(dc->base + DIV_CTRL0);

drivers/clk/mvebu/dove-divider.c

57

val >>= dc->div_bit_start;

drivers/clk/mvebu/dove-divider.c

59

divider = val & ~(~0 << dc->div_bit_size);

drivers/clk/mvebu/dove-divider.c

61

if (dc->divider_table)

drivers/clk/mvebu/dove-divider.c

62

divider = dc->divider_table[divider];

drivers/clk/mvebu/dove-divider.c

67

static int dove_calc_divider(const struct dove_clk *dc, unsigned long rate,

drivers/clk/mvebu/dove-divider.c

74

if (dc->divider_table) {

drivers/clk/mvebu/dove-divider.c

77

for (i = 0; dc->divider_table[i]; i++)

drivers/clk/mvebu/dove-divider.c

78

if (divider == dc->divider_table[i]) {

drivers/clk/mvebu/dove-divider.c

83

if (!dc->divider_table[i])

drivers/clk/mvebu/dove-divider.c

86

max = 1 << dc->div_bit_size;

drivers/crypto/ccp/sev-dev-tio.c

838

struct sev_data_tio_dev_disconnect dc = {

drivers/crypto/ccp/sev-dev-tio.c

839

.length = sizeof(dc),

drivers/crypto/ccp/sev-dev-tio.c

847

spdm_ctrl_init(&dc.spdm_ctrl, dev_data);

drivers/crypto/ccp/sev-dev-tio.c

849

return sev_tio_do_cmd(SEV_CMD_TIO_DEV_DISCONNECT, &dc, sizeof(dc),

drivers/dma/dw-edma/dw-edma-core.c

558

struct data_chunk *dc = &il->sgl[i % fsz];

drivers/dma/dw-edma/dw-edma-core.c

562

src_addr += dmaengine_get_src_icg(il, dc);

drivers/dma/dw-edma/dw-edma-core.c

566

dst_addr += dmaengine_get_dst_icg(il, dc);

drivers/dma/tegra186-gpc-dma.c

1018

tegra_dma_prep_slave_sg(struct dma_chan *dc, struct scatterlist *sgl,

drivers/dma/tegra186-gpc-dma.c

1022

struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);

drivers/dma/tegra186-gpc-dma.c

1135

tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,

drivers/dma/tegra186-gpc-dma.c

1143

struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);

drivers/dma/tegra186-gpc-dma.c

1254

static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)

drivers/dma/tegra186-gpc-dma.c

1256

struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);

drivers/dma/tegra186-gpc-dma.c

1270

static void tegra_dma_chan_synchronize(struct dma_chan *dc)

drivers/dma/tegra186-gpc-dma.c

1272

struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);

drivers/dma/tegra186-gpc-dma.c

1278

static void tegra_dma_free_chan_resources(struct dma_chan *dc)

drivers/dma/tegra186-gpc-dma.c

1280

struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);

drivers/dma/tegra186-gpc-dma.c

1284

tegra_dma_terminate_all(dc);

drivers/dma/tegra186-gpc-dma.c

257

static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)

drivers/dma/tegra186-gpc-dma.c

259

return container_of(dc, struct tegra_dma_channel, vc.chan);

drivers/dma/tegra186-gpc-dma.c

378

static int tegra_dma_slave_config(struct dma_chan *dc,

drivers/dma/tegra186-gpc-dma.c

381

struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);

drivers/dma/tegra186-gpc-dma.c

416

static int tegra_dma_device_pause(struct dma_chan *dc)

drivers/dma/tegra186-gpc-dma.c

418

struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);

drivers/dma/tegra186-gpc-dma.c

443

static int tegra_dma_device_resume(struct dma_chan *dc)

drivers/dma/tegra186-gpc-dma.c

445

struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);

drivers/dma/tegra186-gpc-dma.c

651

static void tegra_dma_issue_pending(struct dma_chan *dc)

drivers/dma/tegra186-gpc-dma.c

653

struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);

drivers/dma/tegra186-gpc-dma.c

714

static int tegra_dma_terminate_all(struct dma_chan *dc)

drivers/dma/tegra186-gpc-dma.c

716

struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);

drivers/dma/tegra186-gpc-dma.c

774

static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,

drivers/dma/tegra186-gpc-dma.c

778

struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);

drivers/dma/tegra186-gpc-dma.c

785

ret = dma_cookie_status(dc, cookie, txstate);

drivers/dma/tegra186-gpc-dma.c

886

tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_addr_t dest, int value,

drivers/dma/tegra186-gpc-dma.c

889

struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);

drivers/dma/tegra186-gpc-dma.c

951

tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_addr_t dest,

drivers/dma/tegra186-gpc-dma.c

954

struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);

drivers/dma/tegra20-apb-dma.c

1035

tegra_dma_prep_slave_sg(struct dma_chan *dc,

drivers/dma/tegra20-apb-dma.c

1042

struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);

drivers/dma/tegra20-apb-dma.c

1161

tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_addr_t buf_addr,

drivers/dma/tegra20-apb-dma.c

1167

struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);

drivers/dma/tegra20-apb-dma.c

1297

static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)

drivers/dma/tegra20-apb-dma.c

1299

struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);

drivers/dma/tegra20-apb-dma.c

1306

static void tegra_dma_free_chan_resources(struct dma_chan *dc)

drivers/dma/tegra20-apb-dma.c

1308

struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);

drivers/dma/tegra20-apb-dma.c

1319

tegra_dma_terminate_all(dc);

drivers/dma/tegra20-apb-dma.c

246

static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)

drivers/dma/tegra20-apb-dma.c

248

return container_of(dc, struct tegra_dma_channel, dma_chan);

drivers/dma/tegra20-apb-dma.c

329

static int tegra_dma_slave_config(struct dma_chan *dc,

drivers/dma/tegra20-apb-dma.c

332

struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);

drivers/dma/tegra20-apb-dma.c

702

static void tegra_dma_issue_pending(struct dma_chan *dc)

drivers/dma/tegra20-apb-dma.c

704

struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);

drivers/dma/tegra20-apb-dma.c

736

static int tegra_dma_terminate_all(struct dma_chan *dc)

drivers/dma/tegra20-apb-dma.c

738

struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);

drivers/dma/tegra20-apb-dma.c

804

static void tegra_dma_synchronize(struct dma_chan *dc)

drivers/dma/tegra20-apb-dma.c

806

struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);

drivers/dma/tegra20-apb-dma.c

886

static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,

drivers/dma/tegra20-apb-dma.c

890

struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);

drivers/dma/tegra20-apb-dma.c

898

ret = dma_cookie_status(dc, cookie, txstate);

drivers/dma/tegra210-adma.c

232

static inline struct tegra_adma_chan *to_tegra_adma_chan(struct dma_chan *dc)

drivers/dma/tegra210-adma.c

234

return container_of(dc, struct tegra_adma_chan, vc.chan);

drivers/dma/tegra210-adma.c

253

static int tegra_adma_slave_config(struct dma_chan *dc,

drivers/dma/tegra210-adma.c

256

struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);

drivers/dma/tegra210-adma.c

444

static void tegra_adma_synchronize(struct dma_chan *dc)

drivers/dma/tegra210-adma.c

446

struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);

drivers/dma/tegra210-adma.c

538

static void tegra_adma_issue_pending(struct dma_chan *dc)

drivers/dma/tegra210-adma.c

540

struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);

drivers/dma/tegra210-adma.c

563

static int tegra_adma_pause(struct dma_chan *dc)

drivers/dma/tegra210-adma.c

565

struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);

drivers/dma/tegra210-adma.c

585

static int tegra_adma_resume(struct dma_chan *dc)

drivers/dma/tegra210-adma.c

587

struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);

drivers/dma/tegra210-adma.c

598

static int tegra_adma_terminate_all(struct dma_chan *dc)

drivers/dma/tegra210-adma.c

600

struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);

drivers/dma/tegra210-adma.c

617

static enum dma_status tegra_adma_tx_status(struct dma_chan *dc,

drivers/dma/tegra210-adma.c

621

struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);

drivers/dma/tegra210-adma.c

628

ret = dma_cookie_status(dc, cookie, txstate);

drivers/dma/tegra210-adma.c

747

struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,

drivers/dma/tegra210-adma.c

751

struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);

drivers/dma/tegra210-adma.c

785

static int tegra_adma_alloc_chan_resources(struct dma_chan *dc)

drivers/dma/tegra210-adma.c

787

struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);

drivers/dma/tegra210-adma.c

790

ret = request_irq(tdc->irq, tegra_adma_isr, 0, dma_chan_name(dc), tdc);

drivers/dma/tegra210-adma.c

793

dma_chan_name(dc));

drivers/dma/tegra210-adma.c

808

static void tegra_adma_free_chan_resources(struct dma_chan *dc)

drivers/dma/tegra210-adma.c

810

struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);

drivers/dma/tegra210-adma.c

812

tegra_adma_terminate_all(dc);

drivers/dma/txx9dmac.c

1001

dc->ccr = TXX9_DMA_CCR_IMMCHN | TXX9_DMA_CCR_INTENE | CCR_LE;

drivers/dma/txx9dmac.c

1002

txx9dmac_chan_set_SMPCHN(dc);

drivers/dma/txx9dmac.c

1003

if (!txx9_dma_have_SMPCHN() || (dc->ccr & TXX9_DMA_CCR_SMPCHN))

drivers/dma/txx9dmac.c

1004

dc->ccr |= TXX9_DMA_CCR_INTENC;

drivers/dma/txx9dmac.c

1008

dc->ccr |= TXX9_DMA_CCR_XFSZ_X8;

drivers/dma/txx9dmac.c

1013

dc->ccr |= TXX9_DMA_CCR_EXTRQ |

drivers/dma/txx9dmac.c

1015

txx9dmac_chan_set_INTENT(dc);

drivers/dma/txx9dmac.c

1018

spin_lock_bh(&dc->lock);

drivers/dma/txx9dmac.c

1019

i = dc->descs_allocated;

drivers/dma/txx9dmac.c

1020

while (dc->descs_allocated < TXX9_DMA_INITIAL_DESC_COUNT) {

drivers/dma/txx9dmac.c

1021

spin_unlock_bh(&dc->lock);

drivers/dma/txx9dmac.c

1023

desc = txx9dmac_desc_alloc(dc, GFP_KERNEL);

drivers/dma/txx9dmac.c

1027

spin_lock_bh(&dc->lock);

drivers/dma/txx9dmac.c

1030

txx9dmac_desc_put(dc, desc);

drivers/dma/txx9dmac.c

1032

spin_lock_bh(&dc->lock);

drivers/dma/txx9dmac.c

1033

i = ++dc->descs_allocated;

drivers/dma/txx9dmac.c

1035

spin_unlock_bh(&dc->lock);

drivers/dma/txx9dmac.c

1045

struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);

drivers/dma/txx9dmac.c

1046

struct txx9dmac_dev *ddev = dc->ddev;

drivers/dma/txx9dmac.c

1051

dc->descs_allocated);

drivers/dma/txx9dmac.c

1054

BUG_ON(!list_empty(&dc->active_list));

drivers/dma/txx9dmac.c

1055

BUG_ON(!list_empty(&dc->queue));

drivers/dma/txx9dmac.c

1056

BUG_ON(channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT);

drivers/dma/txx9dmac.c

1058

spin_lock_bh(&dc->lock);

drivers/dma/txx9dmac.c

1059

list_splice_init(&dc->free_list, &list);

drivers/dma/txx9dmac.c

1060

dc->descs_allocated = 0;

drivers/dma/txx9dmac.c

1061

spin_unlock_bh(&dc->lock);

drivers/dma/txx9dmac.c

1086

struct txx9dmac_chan *dc;

drivers/dma/txx9dmac.c

1091

dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);

drivers/dma/txx9dmac.c

1092

if (!dc)

drivers/dma/txx9dmac.c

1095

dc->dma.dev = &pdev->dev;

drivers/dma/txx9dmac.c

1096

dc->dma.device_alloc_chan_resources = txx9dmac_alloc_chan_resources;

drivers/dma/txx9dmac.c

1097

dc->dma.device_free_chan_resources = txx9dmac_free_chan_resources;

drivers/dma/txx9dmac.c

1098

dc->dma.device_terminate_all = txx9dmac_terminate_all;

drivers/dma/txx9dmac.c

1099

dc->dma.device_tx_status = txx9dmac_tx_status;

drivers/dma/txx9dmac.c

1100

dc->dma.device_issue_pending = txx9dmac_issue_pending;

drivers/dma/txx9dmac.c

1102

dc->dma.device_prep_dma_memcpy = txx9dmac_prep_dma_memcpy;

drivers/dma/txx9dmac.c

1103

dma_cap_set(DMA_MEMCPY, dc->dma.cap_mask);

drivers/dma/txx9dmac.c

1105

dc->dma.device_prep_slave_sg = txx9dmac_prep_slave_sg;

drivers/dma/txx9dmac.c

1106

dma_cap_set(DMA_SLAVE, dc->dma.cap_mask);

drivers/dma/txx9dmac.c

1107

dma_cap_set(DMA_PRIVATE, dc->dma.cap_mask);

drivers/dma/txx9dmac.c

1110

INIT_LIST_HEAD(&dc->dma.channels);

drivers/dma/txx9dmac.c

1111

dc->ddev = platform_get_drvdata(dmac_dev);

drivers/dma/txx9dmac.c

1112

if (dc->ddev->irq < 0) {

drivers/dma/txx9dmac.c

1116

tasklet_setup(&dc->tasklet, txx9dmac_chan_tasklet);

drivers/dma/txx9dmac.c

1117

dc->irq = irq;

drivers/dma/txx9dmac.c

1118

err = devm_request_irq(&pdev->dev, dc->irq,

drivers/dma/txx9dmac.c

1119

txx9dmac_chan_interrupt, 0, dev_name(&pdev->dev), dc);

drivers/dma/txx9dmac.c

1123

dc->irq = -1;

drivers/dma/txx9dmac.c

1124

dc->ddev->chan[ch] = dc;

drivers/dma/txx9dmac.c

1125

dc->chan.device = &dc->dma;

drivers/dma/txx9dmac.c

1126

list_add_tail(&dc->chan.device_node, &dc->chan.device->channels);

drivers/dma/txx9dmac.c

1127

dma_cookie_init(&dc->chan);

drivers/dma/txx9dmac.c

1129

if (is_dmac64(dc))

drivers/dma/txx9dmac.c

1130

dc->ch_regs = &__txx9dmac_regs(dc->ddev)->CHAN[ch];

drivers/dma/txx9dmac.c

1132

dc->ch_regs = &__txx9dmac_regs32(dc->ddev)->CHAN[ch];

drivers/dma/txx9dmac.c

1133

spin_lock_init(&dc->lock);

drivers/dma/txx9dmac.c

1135

INIT_LIST_HEAD(&dc->active_list);

drivers/dma/txx9dmac.c

1136

INIT_LIST_HEAD(&dc->queue);

drivers/dma/txx9dmac.c

1137

INIT_LIST_HEAD(&dc->free_list);

drivers/dma/txx9dmac.c

1139

txx9dmac_reset_chan(dc);

drivers/dma/txx9dmac.c

1141

platform_set_drvdata(pdev, dc);

drivers/dma/txx9dmac.c

1143

err = dma_async_device_register(&dc->dma);

drivers/dma/txx9dmac.c

1147

dc->dma.dev_id,

drivers/dma/txx9dmac.c

1148

dma_has_cap(DMA_MEMCPY, dc->dma.cap_mask) ? " memcpy" : "",

drivers/dma/txx9dmac.c

1149

dma_has_cap(DMA_SLAVE, dc->dma.cap_mask) ? " slave" : "");

drivers/dma/txx9dmac.c

1156

struct txx9dmac_chan *dc = platform_get_drvdata(pdev);

drivers/dma/txx9dmac.c

1159

dma_async_device_unregister(&dc->dma);

drivers/dma/txx9dmac.c

1160

if (dc->irq >= 0) {

drivers/dma/txx9dmac.c

1161

devm_free_irq(&pdev->dev, dc->irq, dc);

drivers/dma/txx9dmac.c

1162

tasklet_kill(&dc->tasklet);

drivers/dma/txx9dmac.c

1164

dc->ddev->chan[pdev->id % TXX9_DMA_MAX_NR_CHANNELS] = NULL;

drivers/dma/txx9dmac.c

144

static dma_addr_t desc_read_CHAR(const struct txx9dmac_chan *dc,

drivers/dma/txx9dmac.c

147

return is_dmac64(dc) ? desc->hwdesc.CHAR : desc->hwdesc32.CHAR;

drivers/dma/txx9dmac.c

150

static void desc_write_CHAR(const struct txx9dmac_chan *dc,

drivers/dma/txx9dmac.c

153

if (is_dmac64(dc))

drivers/dma/txx9dmac.c

163

static struct txx9dmac_desc *txx9dmac_first_active(struct txx9dmac_chan *dc)

drivers/dma/txx9dmac.c

165

return list_entry(dc->active_list.next,

drivers/dma/txx9dmac.c

169

static struct txx9dmac_desc *txx9dmac_last_active(struct txx9dmac_chan *dc)

drivers/dma/txx9dmac.c

171

return list_entry(dc->active_list.prev,

drivers/dma/txx9dmac.c

175

static struct txx9dmac_desc *txx9dmac_first_queued(struct txx9dmac_chan *dc)

drivers/dma/txx9dmac.c

177

return list_entry(dc->queue.next, struct txx9dmac_desc, desc_node);

drivers/dma/txx9dmac.c

189

static struct txx9dmac_desc *txx9dmac_desc_alloc(struct txx9dmac_chan *dc,

drivers/dma/txx9dmac.c

192

struct txx9dmac_dev *ddev = dc->ddev;

drivers/dma/txx9dmac.c

199

dma_async_tx_descriptor_init(&desc->txd, &dc->chan);

drivers/dma/txx9dmac.c

203

desc->txd.phys = dma_map_single(chan2parent(&dc->chan), &desc->hwdesc,

drivers/dma/txx9dmac.c

208

static struct txx9dmac_desc *txx9dmac_desc_get(struct txx9dmac_chan *dc)

drivers/dma/txx9dmac.c

214

spin_lock_bh(&dc->lock);

drivers/dma/txx9dmac.c

215

list_for_each_entry_safe(desc, _desc, &dc->free_list, desc_node) {

drivers/dma/txx9dmac.c

221

dev_dbg(chan2dev(&dc->chan), "desc %p not ACKed\n", desc);

drivers/dma/txx9dmac.c

224

spin_unlock_bh(&dc->lock);

drivers/dma/txx9dmac.c

226

dev_vdbg(chan2dev(&dc->chan), "scanned %u descriptors on freelist\n",

drivers/dma/txx9dmac.c

229

ret = txx9dmac_desc_alloc(dc, GFP_ATOMIC);

drivers/dma/txx9dmac.c

231

spin_lock_bh(&dc->lock);

drivers/dma/txx9dmac.c

232

dc->descs_allocated++;

drivers/dma/txx9dmac.c

233

spin_unlock_bh(&dc->lock);

drivers/dma/txx9dmac.c

235

dev_err(chan2dev(&dc->chan),

drivers/dma/txx9dmac.c

24

static struct txx9dmac_cregs __iomem *__dma_regs(const struct txx9dmac_chan *dc)

drivers/dma/txx9dmac.c

241

static void txx9dmac_sync_desc_for_cpu(struct txx9dmac_chan *dc,

drivers/dma/txx9dmac.c

244

struct txx9dmac_dev *ddev = dc->ddev;

drivers/dma/txx9dmac.c

248

dma_sync_single_for_cpu(chan2parent(&dc->chan),

drivers/dma/txx9dmac.c

251

dma_sync_single_for_cpu(chan2parent(&dc->chan),

drivers/dma/txx9dmac.c

26

return dc->ch_regs;

drivers/dma/txx9dmac.c

260

static void txx9dmac_desc_put(struct txx9dmac_chan *dc,

drivers/dma/txx9dmac.c

266

txx9dmac_sync_desc_for_cpu(dc, desc);

drivers/dma/txx9dmac.c

268

spin_lock_bh(&dc->lock);

drivers/dma/txx9dmac.c

270

dev_vdbg(chan2dev(&dc->chan),

drivers/dma/txx9dmac.c

273

list_splice_init(&desc->tx_list, &dc->free_list);

drivers/dma/txx9dmac.c

274

dev_vdbg(chan2dev(&dc->chan), "moving desc %p to freelist\n",

drivers/dma/txx9dmac.c

276

list_add(&desc->desc_node, &dc->free_list);

drivers/dma/txx9dmac.c

277

spin_unlock_bh(&dc->lock);

drivers/dma/txx9dmac.c

283

static void txx9dmac_dump_regs(struct txx9dmac_chan *dc)

drivers/dma/txx9dmac.c

285

if (is_dmac64(dc))

drivers/dma/txx9dmac.c

286

dev_err(chan2dev(&dc->chan),

drivers/dma/txx9dmac.c

289

(u64)channel64_read_CHAR(dc),

drivers/dma/txx9dmac.c

290

channel64_readq(dc, SAR),

drivers/dma/txx9dmac.c

291

channel64_readq(dc, DAR),

drivers/dma/txx9dmac.c

292

channel64_readl(dc, CNTR),

drivers/dma/txx9dmac.c

293

channel64_readl(dc, SAIR),

drivers/dma/txx9dmac.c

294

channel64_readl(dc, DAIR),

drivers/dma/txx9dmac.c

295

channel64_readl(dc, CCR),

drivers/dma/txx9dmac.c

296

channel64_readl(dc, CSR));

drivers/dma/txx9dmac.c

298

dev_err(chan2dev(&dc->chan),

drivers/dma/txx9dmac.c

30

const struct txx9dmac_chan *dc)

drivers/dma/txx9dmac.c

301

channel32_readl(dc, CHAR),

drivers/dma/txx9dmac.c

302

channel32_readl(dc, SAR),

drivers/dma/txx9dmac.c

303

channel32_readl(dc, DAR),

drivers/dma/txx9dmac.c

304

channel32_readl(dc, CNTR),

drivers/dma/txx9dmac.c

305

channel32_readl(dc, SAIR),

drivers/dma/txx9dmac.c

306

channel32_readl(dc, DAIR),

drivers/dma/txx9dmac.c

307

channel32_readl(dc, CCR),

drivers/dma/txx9dmac.c

308

channel32_readl(dc, CSR));

drivers/dma/txx9dmac.c

311

static void txx9dmac_reset_chan(struct txx9dmac_chan *dc)

drivers/dma/txx9dmac.c

313

channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST);

drivers/dma/txx9dmac.c

314

if (is_dmac64(dc)) {

drivers/dma/txx9dmac.c

315

channel64_clear_CHAR(dc);

drivers/dma/txx9dmac.c

316

channel_writeq(dc, SAR, 0);

drivers/dma/txx9dmac.c

317

channel_writeq(dc, DAR, 0);

drivers/dma/txx9dmac.c

319

channel_writel(dc, CHAR, 0);

drivers/dma/txx9dmac.c

32

return dc->ch_regs;

drivers/dma/txx9dmac.c

320

channel_writel(dc, SAR, 0);

drivers/dma/txx9dmac.c

321

channel_writel(dc, DAR, 0);

drivers/dma/txx9dmac.c

323

channel_writel(dc, CNTR, 0);

drivers/dma/txx9dmac.c

324

channel_writel(dc, SAIR, 0);

drivers/dma/txx9dmac.c

325

channel_writel(dc, DAIR, 0);

drivers/dma/txx9dmac.c

326

channel_writel(dc, CCR, 0);

drivers/dma/txx9dmac.c

330

static void txx9dmac_dostart(struct txx9dmac_chan *dc,

drivers/dma/txx9dmac.c

333

struct txx9dmac_slave *ds = dc->chan.private;

drivers/dma/txx9dmac.c

336

dev_vdbg(chan2dev(&dc->chan), "dostart %u %p\n",

drivers/dma/txx9dmac.c

339

if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {

drivers/dma/txx9dmac.c

340

dev_err(chan2dev(&dc->chan),

drivers/dma/txx9dmac.c

342

txx9dmac_dump_regs(dc);

drivers/dma/txx9dmac.c

347

if (is_dmac64(dc)) {

drivers/dma/txx9dmac.c

348

channel64_writel(dc, CNTR, 0);

drivers/dma/txx9dmac.c

349

channel64_writel(dc, CSR, 0xffffffff);

drivers/dma/txx9dmac.c

35

#define channel64_readq(dc, name) \

drivers/dma/txx9dmac.c

36

__raw_readq(&(__dma_regs(dc)->name))

drivers/dma/txx9dmac.c

362

channel64_writel(dc, SAIR, sai);

drivers/dma/txx9dmac.c

363

channel64_writel(dc, DAIR, dai);

drivers/dma/txx9dmac.c

365

channel64_writel(dc, CCR, dc->ccr);

drivers/dma/txx9dmac.c

367

channel64_write_CHAR(dc, first->txd.phys);

drivers/dma/txx9dmac.c

369

channel32_writel(dc, CNTR, 0);

drivers/dma/txx9dmac.c

37

#define channel64_writeq(dc, name, val) \

drivers/dma/txx9dmac.c

370

channel32_writel(dc, CSR, 0xffffffff);

drivers/dma/txx9dmac.c

38

__raw_writeq((val), &(__dma_regs(dc)->name))

drivers/dma/txx9dmac.c

383

channel32_writel(dc, SAIR, sai);

drivers/dma/txx9dmac.c

384

channel32_writel(dc, DAIR, dai);

drivers/dma/txx9dmac.c

386

channel32_writel(dc, CCR, dc->ccr);

drivers/dma/txx9dmac.c

388

channel32_writel(dc, CHAR, first->txd.phys);

drivers/dma/txx9dmac.c

39

#define channel64_readl(dc, name) \

drivers/dma/txx9dmac.c

390

channel32_writel(dc, CHAR, first->txd.phys);

drivers/dma/txx9dmac.c

391

channel32_writel(dc, CCR, dc->ccr);

drivers/dma/txx9dmac.c

399

txx9dmac_descriptor_complete(struct txx9dmac_chan *dc,

drivers/dma/txx9dmac.c

40

__raw_readl(&(__dma_regs(dc)->name))

drivers/dma/txx9dmac.c

405

dev_vdbg(chan2dev(&dc->chan), "descriptor %u %p complete\n",

drivers/dma/txx9dmac.c

41

#define channel64_writel(dc, name, val) \

drivers/dma/txx9dmac.c

411

txx9dmac_sync_desc_for_cpu(dc, desc);

drivers/dma/txx9dmac.c

412

list_splice_init(&desc->tx_list, &dc->free_list);

drivers/dma/txx9dmac.c

413

list_move(&desc->desc_node, &dc->free_list);

drivers/dma/txx9dmac.c

42

__raw_writel((val), &(__dma_regs(dc)->name))

drivers/dma/txx9dmac.c

424

static void txx9dmac_dequeue(struct txx9dmac_chan *dc, struct list_head *list)

drivers/dma/txx9dmac.c

426

struct txx9dmac_dev *ddev = dc->ddev;

drivers/dma/txx9dmac.c

432

desc = txx9dmac_first_queued(dc);

drivers/dma/txx9dmac.c

434

desc_write_CHAR(dc, prev, desc->txd.phys);

drivers/dma/txx9dmac.c

435

dma_sync_single_for_device(chan2parent(&dc->chan),

drivers/dma/txx9dmac.c

44

#define channel32_readl(dc, name) \

drivers/dma/txx9dmac.c

443

!txx9dmac_chan_INTENT(dc))

drivers/dma/txx9dmac.c

445

} while (!list_empty(&dc->queue));

drivers/dma/txx9dmac.c

448

static void txx9dmac_complete_all(struct txx9dmac_chan *dc)

drivers/dma/txx9dmac.c

45

__raw_readl(&(__dma_regs32(dc)->name))

drivers/dma/txx9dmac.c

457

list_splice_init(&dc->active_list, &list);

drivers/dma/txx9dmac.c

458

if (!list_empty(&dc->queue)) {

drivers/dma/txx9dmac.c

459

txx9dmac_dequeue(dc, &dc->active_list);

drivers/dma/txx9dmac.c

46

#define channel32_writel(dc, name, val) \

drivers/dma/txx9dmac.c

460

txx9dmac_dostart(dc, txx9dmac_first_active(dc));

drivers/dma/txx9dmac.c

464

txx9dmac_descriptor_complete(dc, desc);

drivers/dma/txx9dmac.c

467

static void txx9dmac_dump_desc(struct txx9dmac_chan *dc,

drivers/dma/txx9dmac.c

47

__raw_writel((val), &(__dma_regs32(dc)->name))

drivers/dma/txx9dmac.c

470

if (is_dmac64(dc)) {

drivers/dma/txx9dmac.c

472

dev_crit(chan2dev(&dc->chan),

drivers/dma/txx9dmac.c

476

dev_crit(chan2dev(&dc->chan),

drivers/dma/txx9dmac.c

485

dev_crit(chan2dev(&dc->chan),

drivers/dma/txx9dmac.c

489

dev_crit(chan2dev(&dc->chan),

drivers/dma/txx9dmac.c

49

#define channel_readq(dc, name) channel64_readq(dc, name)

drivers/dma/txx9dmac.c

498

static void txx9dmac_handle_error(struct txx9dmac_chan *dc, u32 csr)

drivers/dma/txx9dmac.c

50

#define channel_writeq(dc, name, val) channel64_writeq(dc, name, val)

drivers/dma/txx9dmac.c

509

dev_crit(chan2dev(&dc->chan), "Abnormal Chain Completion\n");

drivers/dma/txx9dmac.c

51

#define channel_readl(dc, name) \

drivers/dma/txx9dmac.c

510

txx9dmac_dump_regs(dc);

drivers/dma/txx9dmac.c

512

bad_desc = txx9dmac_first_active(dc);

drivers/dma/txx9dmac.c

519

channel_writel(dc, CSR, errors);

drivers/dma/txx9dmac.c

52

(is_dmac64(dc) ? \

drivers/dma/txx9dmac.c

521

if (list_empty(&dc->active_list) && !list_empty(&dc->queue))

drivers/dma/txx9dmac.c

522

txx9dmac_dequeue(dc, &dc->active_list);

drivers/dma/txx9dmac.c

523

if (!list_empty(&dc->active_list))

drivers/dma/txx9dmac.c

524

txx9dmac_dostart(dc, txx9dmac_first_active(dc));

drivers/dma/txx9dmac.c

526

dev_crit(chan2dev(&dc->chan),

drivers/dma/txx9dmac.c

529

txx9dmac_dump_desc(dc, &bad_desc->hwdesc);

drivers/dma/txx9dmac.c

53

channel64_readl(dc, name) : channel32_readl(dc, name))

drivers/dma/txx9dmac.c

531

txx9dmac_dump_desc(dc, &child->hwdesc);

drivers/dma/txx9dmac.c

533

txx9dmac_descriptor_complete(dc, bad_desc);

drivers/dma/txx9dmac.c

536

static void txx9dmac_scan_descriptors(struct txx9dmac_chan *dc)

drivers/dma/txx9dmac.c

54

#define channel_writel(dc, name, val) \

drivers/dma/txx9dmac.c

543

if (is_dmac64(dc)) {

drivers/dma/txx9dmac.c

544

chain = channel64_read_CHAR(dc);

drivers/dma/txx9dmac.c

545

csr = channel64_readl(dc, CSR);

drivers/dma/txx9dmac.c

546

channel64_writel(dc, CSR, csr);

drivers/dma/txx9dmac.c

548

chain = channel32_readl(dc, CHAR);

drivers/dma/txx9dmac.c

549

csr = channel32_readl(dc, CSR);

drivers/dma/txx9dmac.c

55

(is_dmac64(dc) ? \

drivers/dma/txx9dmac.c

550

channel32_writel(dc, CSR, csr);

drivers/dma/txx9dmac.c

555

txx9dmac_complete_all(dc);

drivers/dma/txx9dmac.c

56

channel64_writel(dc, name, val) : channel32_writel(dc, name, val))

drivers/dma/txx9dmac.c

561

dev_vdbg(chan2dev(&dc->chan), "scan_descriptors: char=%#llx\n",

drivers/dma/txx9dmac.c

564

list_for_each_entry_safe(desc, _desc, &dc->active_list, desc_node) {

drivers/dma/txx9dmac.c

565

if (desc_read_CHAR(dc, desc) == chain) {

drivers/dma/txx9dmac.c

573

if (desc_read_CHAR(dc, child) == chain) {

drivers/dma/txx9dmac.c

58

static dma_addr_t channel64_read_CHAR(const struct txx9dmac_chan *dc)

drivers/dma/txx9dmac.c

584

txx9dmac_descriptor_complete(dc, desc);

drivers/dma/txx9dmac.c

588

txx9dmac_handle_error(dc, csr);

drivers/dma/txx9dmac.c

592

dev_err(chan2dev(&dc->chan),

drivers/dma/txx9dmac.c

596

txx9dmac_reset_chan(dc);

drivers/dma/txx9dmac.c

598

if (!list_empty(&dc->queue)) {

drivers/dma/txx9dmac.c

599

txx9dmac_dequeue(dc, &dc->active_list);

drivers/dma/txx9dmac.c

60

if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))

drivers/dma/txx9dmac.c

600

txx9dmac_dostart(dc, txx9dmac_first_active(dc));

drivers/dma/txx9dmac.c

608

struct txx9dmac_chan *dc;

drivers/dma/txx9dmac.c

61

return channel64_readq(dc, CHAR);

drivers/dma/txx9dmac.c

610

dc = from_tasklet(dc, t, tasklet);

drivers/dma/txx9dmac.c

611

csr = channel_readl(dc, CSR);

drivers/dma/txx9dmac.c

612

dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n", csr);

drivers/dma/txx9dmac.c

614

spin_lock(&dc->lock);

drivers/dma/txx9dmac.c

617

txx9dmac_scan_descriptors(dc);

drivers/dma/txx9dmac.c

618

spin_unlock(&dc->lock);

drivers/dma/txx9dmac.c

619

irq = dc->irq;

drivers/dma/txx9dmac.c

626

struct txx9dmac_chan *dc = dev_id;

drivers/dma/txx9dmac.c

628

dev_vdbg(chan2dev(&dc->chan), "interrupt: status=%#x\n",

drivers/dma/txx9dmac.c

629

channel_readl(dc, CSR));

drivers/dma/txx9dmac.c

63

return channel64_readl(dc, CHAR);

drivers/dma/txx9dmac.c

631

tasklet_schedule(&dc->tasklet);

drivers/dma/txx9dmac.c

645

struct txx9dmac_chan *dc;

drivers/dma/txx9dmac.c

655

dc = ddev->chan[i];

drivers/dma/txx9dmac.c

656

csr = channel_readl(dc, CSR);

drivers/dma/txx9dmac.c

657

dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n",

drivers/dma/txx9dmac.c

659

spin_lock(&dc->lock);

drivers/dma/txx9dmac.c

66

static void channel64_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)

drivers/dma/txx9dmac.c

662

txx9dmac_scan_descriptors(dc);

drivers/dma/txx9dmac.c

663

spin_unlock(&dc->lock);

drivers/dma/txx9dmac.c

68

if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))

drivers/dma/txx9dmac.c

69

channel64_writeq(dc, CHAR, val);

drivers/dma/txx9dmac.c

693

struct txx9dmac_chan *dc = to_txx9dmac_chan(tx->chan);

drivers/dma/txx9dmac.c

696

spin_lock_bh(&dc->lock);

drivers/dma/txx9dmac.c

702

list_add_tail(&desc->desc_node, &dc->queue);

drivers/dma/txx9dmac.c

703

spin_unlock_bh(&dc->lock);

drivers/dma/txx9dmac.c

71

channel64_writel(dc, CHAR, val);

drivers/dma/txx9dmac.c

712

struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);

drivers/dma/txx9dmac.c

713

struct txx9dmac_dev *ddev = dc->ddev;

drivers/dma/txx9dmac.c

74

static void channel64_clear_CHAR(const struct txx9dmac_chan *dc)

drivers/dma/txx9dmac.c

748

desc = txx9dmac_desc_get(dc);

drivers/dma/txx9dmac.c

750

txx9dmac_desc_put(dc, first);

drivers/dma/txx9dmac.c

759

dc->ccr | TXX9_DMA_CCR_XFACT);

drivers/dma/txx9dmac.c

765

dc->ccr | TXX9_DMA_CCR_XFACT);

drivers/dma/txx9dmac.c

77

channel64_writel(dc, CHAR, 0);

drivers/dma/txx9dmac.c

778

desc_write_CHAR(dc, prev, desc->txd.phys);

drivers/dma/txx9dmac.c

779

dma_sync_single_for_device(chan2parent(&dc->chan),

drivers/dma/txx9dmac.c

78

channel64_writel(dc, __pad_CHAR, 0);

drivers/dma/txx9dmac.c

791

desc_write_CHAR(dc, prev, 0);

drivers/dma/txx9dmac.c

792

dma_sync_single_for_device(chan2parent(&dc->chan),

drivers/dma/txx9dmac.c

80

channel64_writeq(dc, CHAR, 0);

drivers/dma/txx9dmac.c

807

struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);

drivers/dma/txx9dmac.c

808

struct txx9dmac_dev *ddev = dc->ddev;

drivers/dma/txx9dmac.c

832

desc = txx9dmac_desc_get(dc);

drivers/dma/txx9dmac.c

834

txx9dmac_desc_put(dc, first);

drivers/dma/txx9dmac.c

84

static dma_addr_t channel_read_CHAR(const struct txx9dmac_chan *dc)

drivers/dma/txx9dmac.c

86

if (is_dmac64(dc))

drivers/dma/txx9dmac.c

867

dc->ccr | TXX9_DMA_CCR_XFACT);

drivers/dma/txx9dmac.c

87

return channel64_read_CHAR(dc);

drivers/dma/txx9dmac.c

872

desc_write_CHAR(dc, prev, desc->txd.phys);

drivers/dma/txx9dmac.c

873

dma_sync_single_for_device(chan2parent(&dc->chan),

drivers/dma/txx9dmac.c

886

desc_write_CHAR(dc, prev, 0);

drivers/dma/txx9dmac.c

887

dma_sync_single_for_device(chan2parent(&dc->chan),

drivers/dma/txx9dmac.c

89

return channel32_readl(dc, CHAR);

drivers/dma/txx9dmac.c

899

struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);

drivers/dma/txx9dmac.c

904

spin_lock_bh(&dc->lock);

drivers/dma/txx9dmac.c

906

txx9dmac_reset_chan(dc);

drivers/dma/txx9dmac.c

909

list_splice_init(&dc->queue, &list);

drivers/dma/txx9dmac.c

910

list_splice_init(&dc->active_list, &list);

drivers/dma/txx9dmac.c

912

spin_unlock_bh(&dc->lock);

drivers/dma/txx9dmac.c

916

txx9dmac_descriptor_complete(dc, desc);

drivers/dma/txx9dmac.c

92

static void channel_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)

drivers/dma/txx9dmac.c

925

struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);

drivers/dma/txx9dmac.c

932

spin_lock_bh(&dc->lock);

drivers/dma/txx9dmac.c

933

txx9dmac_scan_descriptors(dc);

drivers/dma/txx9dmac.c

934

spin_unlock_bh(&dc->lock);

drivers/dma/txx9dmac.c

939

static void txx9dmac_chain_dynamic(struct txx9dmac_chan *dc,

drivers/dma/txx9dmac.c

94

if (is_dmac64(dc))

drivers/dma/txx9dmac.c

942

struct txx9dmac_dev *ddev = dc->ddev;

drivers/dma/txx9dmac.c

947

txx9dmac_dequeue(dc, &list);

drivers/dma/txx9dmac.c

949

desc_write_CHAR(dc, prev, desc->txd.phys);

drivers/dma/txx9dmac.c

95

channel64_write_CHAR(dc, val);

drivers/dma/txx9dmac.c

950

dma_sync_single_for_device(chan2parent(&dc->chan),

drivers/dma/txx9dmac.c

953

if (!(channel_readl(dc, CSR) & TXX9_DMA_CSR_CHNEN) &&

drivers/dma/txx9dmac.c

954

channel_read_CHAR(dc) == prev->txd.phys)

drivers/dma/txx9dmac.c

956

channel_write_CHAR(dc, desc->txd.phys);

drivers/dma/txx9dmac.c

957

list_splice_tail(&list, &dc->active_list);

drivers/dma/txx9dmac.c

962

struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);

drivers/dma/txx9dmac.c

964

spin_lock_bh(&dc->lock);

drivers/dma/txx9dmac.c

966

if (!list_empty(&dc->active_list))

drivers/dma/txx9dmac.c

967

txx9dmac_scan_descriptors(dc);

drivers/dma/txx9dmac.c

968

if (!list_empty(&dc->queue)) {

drivers/dma/txx9dmac.c

969

if (list_empty(&dc->active_list)) {

drivers/dma/txx9dmac.c

97

channel32_writel(dc, CHAR, val);

drivers/dma/txx9dmac.c

970

txx9dmac_dequeue(dc, &dc->active_list);

drivers/dma/txx9dmac.c

971

txx9dmac_dostart(dc, txx9dmac_first_active(dc));

drivers/dma/txx9dmac.c

973

struct txx9dmac_desc *prev = txx9dmac_last_active(dc);

drivers/dma/txx9dmac.c

976

txx9dmac_chan_INTENT(dc))

drivers/dma/txx9dmac.c

977

txx9dmac_chain_dynamic(dc, prev);

drivers/dma/txx9dmac.c

981

spin_unlock_bh(&dc->lock);

drivers/dma/txx9dmac.c

986

struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);

drivers/dma/txx9dmac.c

994

if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {

drivers/dma/txx9dmac.h

193

static inline bool is_dmac64(const struct txx9dmac_chan *dc)

drivers/dma/txx9dmac.h

195

return __is_dmac64(dc->ddev);

drivers/dma/txx9dmac.h

237

static inline bool txx9dmac_chan_INTENT(struct txx9dmac_chan *dc)

drivers/dma/txx9dmac.h

239

return (dc->ccr & TXX9_DMA_CCR_INTENT) != 0;

drivers/dma/txx9dmac.h

242

static inline void txx9dmac_chan_set_INTENT(struct txx9dmac_chan *dc)

drivers/dma/txx9dmac.h

244

dc->ccr |= TXX9_DMA_CCR_INTENT;

drivers/dma/txx9dmac.h

252

static inline void txx9dmac_chan_set_SMPCHN(struct txx9dmac_chan *dc)

drivers/dma/txx9dmac.h

254

dc->ccr |= TXX9_DMA_CCR_SMPCHN;

drivers/dma/txx9dmac.h

265

static inline bool txx9dmac_chan_INTENT(struct txx9dmac_chan *dc)

drivers/dma/txx9dmac.h

270

static void txx9dmac_chan_set_INTENT(struct txx9dmac_chan *dc)

drivers/dma/txx9dmac.h

283

static inline void txx9dmac_chan_set_SMPCHN(struct txx9dmac_chan *dc)

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

477

MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

478

module_param_named(dc, amdgpu_dc, int, 0444);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10087

dc_exit_ips_for_hw_access(dm->dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10104

dc_exit_ips_for_hw_access(dm->dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10186

adev->dm.dc->caps.color.dpp.gamma_corr)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10460

dc_exit_ips_for_hw_access(dm->dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1060

if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10625

dm->dc, acrtc_state->stream,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10630

update_planes_and_stream_adapter(dm->dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10755

!dc_get_flip_pending_on_otg(dm->dc, acrtc_attach->otg_inst);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1076

if (dc_enable_dmub_notifications(adev->dm.dc) &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1080

dc_stat_get_dmub_notification(adev->dm.dc, &notify);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10880

dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10917

dc_exit_ips_for_hw_access(dm->dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11078

dc_exit_ips_for_hw_access(dm->dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11151

dc_exit_ips_for_hw_access(dm->dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11152

WARN_ON(!dc_commit_streams(dm->dc, &params));

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11175

dc_allow_idle_optimizations(dm->dc, true);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11247

if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11248

pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11305

dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1138

if (adev->dm.dc->fbc_compressor == NULL)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11591

dc_exit_ips_for_hw_access(dm->dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11592

dc_update_planes_and_stream(dm->dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1161

adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12185

dm->dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12228

dm->dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1254

adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12585

static int dm_update_plane_state(struct dc *dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1264

adev->dm.dc->res_pool->audios[i]->inst;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12649

dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12688

dc_new_plane_state = dc_create_plane_state(dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12721

dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1313

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13139

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1314

struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1315

struct abm *abm = adev->dm.dc->res_pool->abm;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1316

struct dc_context *ctx = adev->dm.dc->ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13184

if (dc_resource_is_dsc_encoding_supported(dc)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13318

ret = dm_update_plane_state(dc, state, plane,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13358

ret = dm_update_plane_state(dc, state, plane,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13371

if (dc_resource_is_dsc_encoding_supported(dc)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13530

if (dc_resource_is_dsc_encoding_supported(dc)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13557

status = dc_validate_global_state(dc, dm_state->context, DC_VALIDATE_MODE_ONLY);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13678

res = dc_wake_and_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13720

if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13727

res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13743

res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13993

dm_helpers_read_mccs_caps(adev->dm.dc->ctx, amdgpu_dm_connector->dc_link, sink);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13999

dm_helpers_mccs_vcp_set(adev->dm.dc->ctx, amdgpu_dm_connector->dc_link, sink);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

14020

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

14024

if (dc->current_state) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

14025

for (i = 0; i < dc->current_state->stream_count; ++i)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

14026

dc->current_state->streams[i]

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

14030

dm_enable_per_frame_crtc_master_sync(dc->current_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

14031

dc_trigger_sync(dc, dc->current_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

14036

static inline void amdgpu_dm_exit_ips_for_hw_access(struct dc *dc)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

14038

if (dc->ctx->dmub_srv && !dc->ctx->dmub_srv->idle_exit_counter)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

14039

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

14053

amdgpu_dm_exit_ips_for_hw_access(ctx->dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

14077

amdgpu_dm_exit_ips_for_hw_access(ctx->dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

14097

if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1420

if (dc->caps.is_apu &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1421

dc->res_pool->usb4_dpia_count != 0 &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1422

!dc->debug.dpia_debug.bits.disable_dpia) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

14225

is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1424

hw_params.disable_dpia = dc->debug.dpia_debug.bits.disable_dpia;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1426

hw_params.enable_non_transparent_setconfig = dc->config.consolidated_dpia_dp_lt;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1427

hw_params.disable_dpia_bw_allocation = !dc->config.usb4_bw_alloc_support;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1460

if (!adev->dm.dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1461

adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1462

if (!adev->dm.dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1481

adev->dm.dc->debug.sanity_checks = true;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1487

adev->dm.dc->debug.sanity_checks = true;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1713

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1714

int max_caps = dc->caps.max_links;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1997

dm->power_module = mod_power_create(dm->dc, init_data, dm->num_of_edps);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2014

struct dc *dc = dm->dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2019

dc_link = dc->links[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2202

adev->dm.dc = dc_create(&init_data);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2204

if (adev->dm.dc) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2206

dce_version_to_string(adev->dm.dc->ctx->dce_version));

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2213

adev->dm.dc->debug.force_single_disp_pipe_split = false;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2214

adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2218

adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2220

adev->dm.dc->debug.disable_stutter = true;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2223

adev->dm.dc->debug.disable_stutter = true;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2226

adev->dm.dc->debug.disable_dsc = true;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2229

adev->dm.dc->debug.disable_clock_gate = true;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2232

adev->dm.dc->debug.force_subvp_mclk_switch = true;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2235

adev->dm.dc->debug.force_disable_subvp = true;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2236

adev->dm.dc->debug.fams2_config.bits.enable = false;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2240

adev->dm.dc->debug.using_dml2 = true;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2241

adev->dm.dc->debug.using_dml21 = true;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2245

adev->dm.dc->debug.hdcp_lc_force_fw_enable = true;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2248

adev->dm.dc->debug.hdcp_lc_enable_sw_fallback = true;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2251

adev->dm.dc->debug.skip_detection_link_training = true;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2253

adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2256

adev->dm.dc->debug.ignore_cable_id = true;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2258

if (adev->dm.dc->caps.dp_hdmi21_pcon_support)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2267

dc_hardware_init(adev->dm.dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2281

dc_setup_system_context(adev->dm.dc, &pa_config);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2284

adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2294

if (adev->dm.dc->caps.max_links > 0) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2301

if (adev->dm.dc->caps.ips_support &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2302

adev->dm.dc->config.disable_ips != DMUB_IPS_DISABLE_ALL)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2305

if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2306

adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2315

dc_init_callbacks(adev->dm.dc, &init_params);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2317

if (adev->dm.dc->caps.max_links > 0) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2325

if (dc_is_dmub_outbox_supported(adev->dm.dc)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2360

dc_enable_dmub_outbox(adev->dm.dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2364

dc_dmub_srv_enable_dpia_trace(adev->dm.dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2382

adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2383

adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2468

if (adev->dm.dc) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2469

dc_deinit_callbacks(adev->dm.dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2470

dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2471

if (dc_enable_dmub_notifications(adev->dm.dc)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2489

if (adev->dm.hpd_rx_offload_wq && adev->dm.dc) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2490

for (i = 0; i < adev->dm.dc->caps.max_links; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2502

if (adev->dm.dc)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2503

dc_destroy(&adev->dm.dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2642

return dm_read_reg(adev->dm.dc->ctx, address);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2650

return dm_write_reg(adev->dm.dc->ctx, address, value);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

291

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2953

if (!adev || !adev->dm.dc || !adev->dm.dc->ctx ||

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2954

!adev->dm.dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2958

dmub = adev->dm.dc->ctx->dmub_srv->dmub;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2988

dc_dmub_srv_boot_time_crc_init(adev->dm.dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3002

dmcu = adev->dm.dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3030

} else if (adev->dm.dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3034

dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3036

if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

304

if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

305

dc_allow_idle_optimizations(dc, false);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3237

oem_ddc_service = dc_get_oem_i2c_device(adev->dm.dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3330

rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3335

if (dc_supports_vrr(adev->dm.dc->ctx->dce_version)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3354

if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3370

static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3380

context = dc_state_create_current_copy(dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3395

if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context))

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3398

res = dc_state_remove_stream(dc, context, del_streams[i]);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3406

return dc_commit_streams(dc, &params);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3414

for (i = 0; i < dm->dc->caps.max_links; i++)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3499

dc_allow_idle_optimizations(adev->dm.dc, false);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3501

dm->cached_dc_state = dc_state_create_copy(dm->dc->current_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3506

res = amdgpu_dm_commit_zero_streams(dm->dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3542

dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3544

if (dm->dc->caps.ips_support && adev->in_s0ix)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3545

dc_allow_idle_optimizations(dm->dc, true);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3547

dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3683

update_planes_and_stream_adapter(dm->dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3720

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3724

if (!dc)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3727

for (li = 0; li < dc->link_count; li++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3728

struct dc_link *l = dc->links[li];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3785

if (dm->dc->caps.ips_support) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3792

dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3793

dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3817

link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3825

dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3826

dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3828

dc_resume(dm->dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3841

if (dc_is_dmub_outbox_supported(adev->dm.dc)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3843

dc_enable_dmub_outbox(adev->dm.dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3848

dc_exit_ips_for_hw_access(dm->dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3849

WARN_ON(!dc_commit_streams(dm->dc, &commit_params));

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3872

dm_state->context = dc_state_create(dm->dc, NULL);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3879

if (dc_is_dmub_outbox_supported(adev->dm.dc)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3881

dc_enable_dmub_outbox(adev->dm.dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3885

dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3886

dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3889

dc_resume(dm->dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3938

dc_exit_ips_for_hw_access(dm->dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

411

static inline bool update_planes_and_stream_adapter(struct dc *dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

424

dc_post_update_surfaces_to_stream(dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

426

return dc_update_planes_and_stream(dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4374

struct dc *dc = aconnector->dc_link->ctx->dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4382

if (dc->caps.ips_support && dc->ctx->dmub_srv->idle_allowed) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4383

dc_allow_idle_optimizations(dc, false);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4420

if (reallow_idle && dc->caps.ips_support)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4421

dc_allow_idle_optimizations(dc, true);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4432

struct dc *dc = aconnector->dc_link->ctx->dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4503

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4563

struct dc *dc = aconnector->dc_link->ctx->dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4653

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4693

if (dc_is_dmub_outbox_supported(adev->dm.dc)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4762

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4771

adev->dm.dc->ctx->dce_version >= DCE_VERSION_8_0

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4803

dc_interrupt_to_irq_source(dc, src_id, 0);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4822

if (dc_supports_vrr(adev->dm.dc->ctx->dce_version)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4834

dc_interrupt_to_irq_source(dc, src_id, 0);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4865

dc_interrupt_to_irq_source(dc, i, 0);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4900

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4944

dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4983

dc_interrupt_to_irq_source(dc, i, 0);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5017

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5032

if (dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5036

dc_interrupt_to_irq_source(dc, i, 0);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5141

context = dc_state_create_current_copy(adev->dm.dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5372

struct dc_state *cur_dc_state = dm->dc->current_state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5438

if (dm->dc->caps.ips_support && dm->dc->ctx->dmub_srv->idle_allowed) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5439

dc_allow_idle_optimizations(dm->dc, false);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

545

dc_stream_adjust_vmin_vmax(adev->dm.dc, stream, adjust);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5472

if (dm->dc->caps.ips_support && reallow_idle)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5473

dc_allow_idle_optimizations(dm->dc, true);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5637

if (plane_id >= dm->dc->caps.max_streams)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5712

int max_overlay = dm->dc->caps.max_slave_planes;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5714

dm->display_indexes_num = dm->dc->caps.max_streams;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5720

link_cnt = dm->dc->caps.max_links;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5727

primary_planes = dm->dc->caps.max_streams;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5738

plane = &dm->dc->caps.planes[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5756

for (i = 0; i < dm->dc->caps.max_planes; ++i) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5757

struct dc_plane_cap *plane = &dm->dc->caps.planes[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5779

for (i = 0; i < dm->dc->caps.max_streams; i++)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5867

link = dc_get_link_at_index(dm->dc, i);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5921

dc_exit_ips_for_hw_access(dm->dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

624

dc_stream_fc_disable_writeback(adev->dm.dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

695

if (!dc_get_flip_pending_on_otg(adev->dm.dc, acrtc->otg_inst)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7379

dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7390

dc_dsc_parse_dsc_edid(aconnector->dc_link->ctx->dc, &sink->edid_caps, dsc_caps);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7392

dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7401

dc_dsc_parse_dsc_edid(aconnector->dc_link->ctx->dc, &sink->edid_caps, dsc_caps);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7413

struct dc *dc = sink->ctx->dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7418

dc_dsc_get_default_config_option(dc, &dsc_options);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7432

if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7433

dc->debug.dsc_min_slice_height_override,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7441

if (dc_dsc_compute_config(dc->res_pool->dscs[0],

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7456

if (dc_dsc_compute_config(dc->res_pool->dscs[0],

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7474

struct dc *dc = sink->ctx->dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7485

dc_dsc_get_default_config_option(dc, &dsc_options);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7497

dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7503

if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7518

sink_bw_in_kbps = dc_link_bw_kbps_from_raw_frl_link_rate_data(dc, sink->edid_caps.max_frl_rate);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7519

dsc_sink_bw_in_kbps = dc_link_bw_kbps_from_raw_frl_link_rate_data(dc, sink->edid_caps.frl_dsc_max_frl_rate);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7533

if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7559

dsc_sink_bw_in_kbps = dc_link_bw_kbps_from_raw_frl_link_rate_data(dc, sink->edid_caps.frl_dsc_max_frl_rate);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7563

if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8361

static enum dc_status dm_validate_stream_and_context(struct dc *dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8371

dc_plane_state = dc_create_plane_state(dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8375

dc_state = dc_state_create(dc, NULL);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8397

dc_result = dc_validate_stream(dc, stream);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8399

dc_result = dc_validate_plane(dc, dc_plane_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8402

dc_result = dc_state_add_stream(dc, dc_state, stream);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8405

dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8412

dc_result = dc_validate_global_state(dc, dc_state, DC_VALIDATE_MODE_ONLY);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8460

dc_result = dc_validate_stream(adev->dm.dc, stream);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8469

dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

908

if (notify->link_index > adev->dm.dc->link_count) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

920

link = adev->dm.dc->links[link_index];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9262

const struct dc *dc = dc_link->dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9269

if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9468

ddc_service->ctx->dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9473

ddc_service->ctx->dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9550

struct dc *dc = dm->dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9551

struct dc_link *link = dc_get_link_at_index(dc, link_index);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9950

dc_stream_adjust_vmin_vmax(dm->dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

351

struct dc *dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

85

struct dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1146

bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1747

bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1917

bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

2028

if (dc_plane_state->ctx && dc_plane_state->ctx->dc)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

2029

color_caps = &dc_plane_state->ctx->dc->caps.color;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c

233

bool hw_3d_lut = adev->dm.dc->caps.color.dpp.hw_3d_lut ||

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c

234

adev->dm.dc->caps.color.mpc.preblend;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

546

if (!dc_stream_configure_crc(stream_state->ctx->dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

556

dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

561

dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

807

if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state, 0,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

903

dc_stream_configure_crc(stream_state->ctx->dc, stream_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

918

if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state, i,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

927

dc_stream_configure_crc(stream_state->ctx->dc, stream_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

170

if (!idle_work->dm->dc->idle_optimizations_allowed) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

174

dc_allow_idle_optimizations(idle_work->dm->dc, false);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

187

dc_post_update_surfaces_to_stream(idle_work->dm->dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

188

dc_allow_idle_optimizations(idle_work->dm->dc, true);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

257

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

271

if (dc->caps.ips_support &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

272

dc->config.disable_ips != DMUB_IPS_DISABLE_ALL &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

290

} else if (dc_supports_vrr(dm->dc->ctx->dce_version)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

497

if (adev->dm.dc->caps.color.mpc.ogam_ram)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

634

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

684

if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

765

acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

766

acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

782

has_degamma = dm->adev->dm.dc->caps.color.dpp.dcn_arch &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

783

dm->adev->dm.dc->ctx->dce_version != DCN_VERSION_4_01;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

90

rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1032

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1035

if (dc->ctx->dmub_srv && dc->ctx->dmub_srv->dmub)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1037

(bool)dc->ctx->dmub_srv->dmub->feature_caps.replay_supported;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1302

pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1583

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1685

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1769

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1869

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1953

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2053

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2133

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2230

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2308

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2362

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2431

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2500

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

264

struct dc *dc = (struct dc *)link->dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2687

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2690

seq_printf(m, "IPS config: %d\n", dc->config.disable_ips);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2691

seq_printf(m, "Idle optimization: %d\n", dc->idle_optimizations_allowed);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2698

dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2734

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2742

if (!dc_dmub_srv_ips_query_residency_info(dc->ctx, panel_inst, &info, mode)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2769

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2774

if (!dc_dmub_srv_ips_residency_cntl(dc->ctx, panel_inst, !!val))

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3198

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3204

if (dc->idle_optimizations_allowed) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3205

dc_allow_idle_optimizations(dc, false);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3212

dc_allow_idle_optimizations(dc, true);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3229

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3236

if (dc->idle_optimizations_allowed) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3237

dc_allow_idle_optimizations(dc, false);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3241

link->dc->link_srv->edp_replay_residency(link, &residency, is_start, PR_RESIDENCY_MODE_PHY);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3244

dc_allow_idle_optimizations(dc, true);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3259

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3265

if (dc->idle_optimizations_allowed) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3266

dc_allow_idle_optimizations(dc, false);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

327

dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3270

link->dc->link_srv->edp_replay_residency(link, &residency, false, PR_RESIDENCY_MODE_PHY);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3273

dc_allow_idle_optimizations(dc, true);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3290

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3296

if (dc->idle_optimizations_allowed) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3297

dc_allow_idle_optimizations(dc, false);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3304

dc_allow_idle_optimizations(dc, true);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3321

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3327

if (dc->idle_optimizations_allowed) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3328

dc_allow_idle_optimizations(dc, false);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3332

link->dc->link_srv->edp_get_psr_residency(link, &residency, PSR_RESIDENCY_MODE_PHY);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3335

dc_allow_idle_optimizations(dc, true);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3352

*val = adev->dm.dc->config.allow_edp_hotplug_detection;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3365

adev->dm.dc->config.allow_edp_hotplug_detection = (uint32_t) val;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

341

dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3497

struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3525

if (!dc_wake_and_execute_gpint(adev->dm.dc->ctx, cmd, res, NULL, DM_DMUB_WAIT_TYPE_WAIT))

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3541

struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3553

if (!dc_wake_and_execute_gpint(adev->dm.dc->ctx, cmd, 0, &response, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3583

dc_dmub_trace_event_control(adev->dm.dc, val);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3695

struct dc *dc = (struct dc *)link->dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3747

dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3776

dc_link_set_preferred_training_settings(dc, &prefer_link_settings,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

398

struct dc *dc = (struct dc *)link->dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4128

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4135

if (!dc->hwss.log_hw_state)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4138

dc->hwss.log_hw_state(dc, &log_ctx);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4167

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4173

if (dc->hwss.log_hw_state)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4174

dc->hwss.log_hw_state(dc, NULL);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4350

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4351

bool mall_supported = dc->caps.mall_size_total;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4352

bool subvp_supported = dc->caps.subvp_fw_processing_delay_us;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4356

struct hubbub *hubbub = dc->res_pool->hubbub;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4361

if (dc->cap_funcs.get_subvp_en)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4362

subvp_in_use = dc->cap_funcs.get_subvp_en(dc, dc->current_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4382

adev->dm.dc->debug.set_mst_en_for_sst = val;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4391

*val = adev->dm.dc->debug.set_mst_en_for_sst;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4406

adev->dm.dc->debug.ignore_cable_id = val;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4415

*val = adev->dm.dc->debug.ignore_cable_id;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4430

adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4443

*val = adev->dm.dc->debug.visual_confirm;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4462

adev->dm.dc->debug.skip_detection_link_training = false;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4464

adev->dm.dc->debug.skip_detection_link_training = true;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4477

*val = adev->dm.dc->debug.skip_detection_link_training;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4497

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4502

int num_pipes = dc->res_pool->pipe_count;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4510

if (!dc->hwss.get_dcc_en_bits) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4515

dc->hwss.get_dcc_en_bits(dc, dcc_en_bits);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4606

if (adev->dm.dc->caps.ips_support) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

461

dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

476

dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, true);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

618

struct dc *dc = (struct dc *)link->dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

692

dc_link_set_drive_settings(dc, &link_lane_settings, link);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

207

const struct dc *dc = aconnector->dc_link->dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

239

(dc->caps.fused_io_supported || dc->debug.hdcp_lc_force_fw_enable);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

240

link_adjust.hdcp2.use_sw_locality_fallback = dc->debug.hdcp_lc_enable_sw_fallback;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

48

link->dc->caps.i2c_speed_in_khz};

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

546

const struct dc *dc = aconnector->dc_link->dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

590

link->adjust.hdcp2.use_fw_locality_check = (dc->caps.fused_io_supported || dc->debug.hdcp_lc_force_fw_enable);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

591

link->adjust.hdcp2.use_sw_locality_fallback = dc->debug.hdcp_lc_enable_sw_fallback;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

61

link->dc->caps.i2c_speed_in_khz};

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

748

struct cp_psp *cp_psp, struct dc *dc)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

750

int max_caps = dc->caps.max_links;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

785

if (dc->ctx->dce_version == DCN_VERSION_3_1 ||

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

786

dc->ctx->dce_version == DCN_VERSION_3_14 ||

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

787

dc->ctx->dce_version == DCN_VERSION_3_15 ||

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

788

dc->ctx->dce_version == DCN_VERSION_3_16 ||

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

789

dc->ctx->dce_version == DCN_VERSION_3_2 ||

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

790

dc->ctx->dce_version == DCN_VERSION_3_21 ||

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

791

dc->ctx->dce_version == DCN_VERSION_3_5 ||

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

792

dc->ctx->dce_version == DCN_VERSION_3_51 ||

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

793

dc->ctx->dce_version == DCN_VERSION_3_6 ||

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

794

dc->ctx->dce_version == DCN_VERSION_4_01)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

797

config->ddc.handle = dc_get_link_at_index(dc, i);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h

95

struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev, struct cp_psp *cp_psp, struct dc *dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1175

if (link->dc->hwss.prepare_ddc)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1176

link->dc->hwss.prepare_ddc(link);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1339

if (dc_get_edp_link_panel_inst(ctx->dc, link, &panel_inst) && panel_inst == 1) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1374

ret = dc_interrupt_set(ctx->dc, irq_source, enable);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1417

struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1421

struct dc_state *dc_state = ctx->dc->current_state;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1422

struct clk_mgr *clk_mgr = ctx->dc->clk_mgr;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1528

ctx->dc->clk_mgr->funcs->update_clocks(

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1529

ctx->dc->clk_mgr,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

189

populate_hdmi_info_from_connector(link->dc->config.enable_frl, &connector->display_info.hdmi, edid_caps);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

1006

dc_interrupt_set(adev->dm.dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

1013

dc_interrupt_set(adev->dm.dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

499

dc_interrupt_set(adev->dm.dc, src, false);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

536

dc_interrupt_set(adev->dm.dc, src, true);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

561

dc_interrupt_set(adev->dm.dc, src, true);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

664

adev->dm.dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

668

dc_interrupt_ack(adev->dm.dc, src);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

706

dc_interrupt_set(adev->dm.dc, src, st);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

719

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

737

if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

738

dc_allow_idle_optimizations(dc, false);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

740

dc_interrupt_set(adev->dm.dc, irq_source, st);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

794

dc_interrupt_set(adev->dm.dc, irq_source, st);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

820

dc_interrupt_set(adev->dm.dc, irq_source, st);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

884

dc_interrupt_set(adev->dm.dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

908

if (!dc_interrupt_set(adev->dm.dc, i, false))

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

953

dc_interrupt_set(adev->dm.dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

960

dc_interrupt_set(adev->dm.dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.c

297

dc_allow_idle_optimizations(dm->dc, false);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.c

330

dc_post_update_surfaces_to_stream(dm->dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.c

331

dc_allow_idle_optimizations(dm->dc, true);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.c

474

ASSERT(dm->dc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1184

if (aconnector->dc_link->dc->caps.dp_hdmi21_pcon_support &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1187

aconnector->dc_link->dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1191

aconnector->dc_link->dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1194

aconnector->dc_link->dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1217

dc_dsc_get_default_config_option(stream->sink->ctx->dc, &dsc_options);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1222

stream->sink->ctx->dc->res_pool->dscs[0],

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1327

stream->sink->ctx->dc->res_pool->dscs[0],

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1328

stream->sink->ctx->dc->debug.dsc_min_slice_height_override,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1440

const struct dc *dc = dc_link->dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1522

__func__, dc->current_state->stream_count);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1527

for (i = 0; i < dc->current_state->stream_count; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1528

stream = dc->current_state->streams[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1579

res_pool = stream->ctx->dc->res_pool;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1599

res_pool->funcs->remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1621

if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1866

is_dsc_possible = dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0],

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1867

stream->sink->ctx->dc->debug.dsc_min_slice_height_override,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

2025

dc_dsc_get_default_config_option(stream->link->dc, &dsc_options);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

2027

if (dc_dsc_compute_config(stream->sink->ctx->dc->res_pool->dscs[0],

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

305

if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

921

dc_dsc_get_default_config_option(params[i].sink->ctx->dc, &dsc_options);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

926

params[i].sink->ctx->dc->res_pool->dscs[0],

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

974

dc_dsc_get_default_config_option(param.sink->ctx->dc, &dsc_options);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

979

param.sink->ctx->dc->res_pool->dscs[0],

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1050

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1052

struct dc_plane_cap *plane_cap = &dc->caps.planes[0];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1235

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1270

if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1406

adev->dm.dc->caps.color.dpp.gamma_corr)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1639

struct dpp_color_caps dpp_color_caps = dm->dc->caps.color.dpp;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1661

if (dm->dc->caps.color.mpc.gamut_remap)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1665

if (dpp_color_caps.hw_3d_lut || dm->dc->caps.color.mpc.preblend) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1681

if (dpp_color_caps.ogam_ram || dm->dc->caps.color.mpc.preblend) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1824

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1833

if (dc->ctx->dce_version >= DCN_VERSION_3_0) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1879

unsigned int primary_zpos = dm->dc->caps.max_slave_planes;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

271

struct dc *dc = adev->dm.dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

285

if (!dc->cap_funcs.get_dcc_compression_cap)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

298

if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

102

struct dc *dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

108

dc = link->ctx->dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

113

if (!dc->caps.dmub_caps.psr)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

126

if (dc_get_edp_link_panel_inst(dc, link, &panel_inst) && panel_inst == 1)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

149

for (i = 0; i < dm->dc->current_state->stream_count; i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

150

const struct dc_link *link = dm->dc->current_state->streams[i]->link;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

38

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

40

if (!dc->caps.dmcub_support)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

43

if (dc->ctx->dce_version < DCN_VERSION_3_1)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

100

if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub ||

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

101

!dc->ctx->dmub_srv->dmub->feature_caps.replay_supported)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

125

link->ctx->dc->debug.visual_confirm == VISUAL_CONFIRM_REPLAY;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

126

debug_flags->bitfields.skip_crtc_disabled = dc->debug.replay_skip_crtc_disabled;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

85

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c

188

struct dc *dc = dm->dc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c

189

struct dc_link *link = dc_get_link_at_index(dc, link_index);

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3054

if (ctx->dc->config.multi_mon_pp_mclk_switch)

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3073

if (ctx->dc->debug.bandwidth_calcs_trace) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3123

if (ctx->dc->caps.max_slave_planes) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3153

if (ctx->dc->caps.max_slave_planes) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3181

if (ctx->dc->caps.max_slave_planes) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3209

if (ctx->dc->caps.max_slave_planes) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3244

if (ctx->dc->caps.max_slave_planes) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3274

if (ctx->dc->caps.max_slave_planes) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3302

if (ctx->dc->caps.max_slave_planes) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3330

if (ctx->dc->caps.max_slave_planes) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3364

if (ctx->dc->caps.max_slave_planes) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3393

if (ctx->dc->caps.max_slave_planes) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3420

if (ctx->dc->caps.max_slave_planes) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3447

if (ctx->dc->caps.max_slave_planes) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3495

if (ctx->dc->caps.max_slave_planes) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3523

if (ctx->dc->caps.max_slave_planes) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3551

if (ctx->dc->caps.max_slave_planes) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3579

if (ctx->dc->caps.max_slave_planes) {

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

1506

if (dcb->ctx->dc->config.force_bios_enable_lttpr && *dce_caps == 0) {

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

3223

else if (bp->base.ctx->dc->config.force_bios_fixed_vs) {

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

3234

if (bp->base.ctx->dc->config.force_bios_fixed_vs && info->ext_disp_conn_info.fixdpvoltageswing == 0) {

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

3235

info->ext_disp_conn_info.fixdpvoltageswing = bp->base.ctx->dc->config.force_bios_fixed_vs & 0xF;

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

1067

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

1068

bp->base.ctx->dc->debug.dmub_command_table) {

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

180

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

181

bp->base.ctx->dc->debug.dmub_command_table) {

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

196

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

197

bp->base.ctx->dc->debug.dmub_command_table) {

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

230

if (!BIOS_CMD_TABLE_REVISION(dig1transmittercontrol, frev, crev) && (bp->base.ctx->dc->ctx->dce_version <= DCN_VERSION_2_0))

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

296

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

297

bp->base.ctx->dc->debug.dmub_command_table) {

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

327

static struct dc_link *get_link_by_phy_id(struct dc *p_dc, uint32_t phy_id)

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

382

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

383

bp->base.ctx->dc->debug.dmub_command_table) {

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

385

struct dc_link *link = get_link_by_phy_id(bp->base.ctx->dc, dig_v1_7.phyid);

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

431

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

432

bp->base.ctx->dc->debug.dmub_command_table) {

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

559

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

560

bp->base.ctx->dc->debug.dmub_command_table) {

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

575

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

576

bp->base.ctx->dc->debug.dmub_command_table) {

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

870

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

871

bp->base.ctx->dc->debug.dmub_command_table) {

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

888

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

889

bp->base.ctx->dc->debug.dmub_command_table) {

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

105

dc_get_edp_links(dc, edp_links, &edp_num);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

106

if (dc->hwss.exit_optimized_pwr_state)

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

107

dc->hwss.exit_optimized_pwr_state(dc, dc->current_state);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

117

dc->link_srv->edp_set_psr_allow_active(edp_link, &allow_active, false, false, NULL);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

118

dc->link_srv->edp_set_replay_allow_active(edp_link, &allow_active, false, false, NULL);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

124

void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

131

dc_get_edp_links(dc, edp_links, &edp_num);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

137

dc->link_srv->edp_set_psr_allow_active(edp_link,

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

139

dc->link_srv->edp_set_replay_allow_active(edp_link,

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

144

if (dc->hwss.optimize_pwr_state)

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

145

dc->hwss.optimize_pwr_state(dc, dc->current_state);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

55

struct dc *dc,

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

71

if (!stream->dpms_off || dc->is_switch_in_progress_dest || (stream_status && stream_status->plane_count))

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

79

struct dc *dc,

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

82

(void)dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

98

void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

206

struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

243

struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

311

if (clk_mgr_dce->base.ctx->dc->config.ignore_dpref_ss)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

318

struct dc *dc,

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

325

if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

326

dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

340

dce_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

111

struct dc *dc = context->clk_mgr->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

116

pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

118

pp_display_cfg->crtc_index = (uint8_t)dc->res_pool->res_cap->num_timing_generator;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

184

struct dc *dc,

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

190

if (dc->bw_vbios && dc->bw_vbios->memory_type == bw_def_hbm)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

209

if (dc->bw_vbios && (dc->ctx->asic_id.chip_family == FAMILY_AI) &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

210

ASICREV_IS_VEGA20_P(dc->ctx->asic_id.hw_internal_rev) && (context->stream_count >= 2)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

213

div64_s64(dc->bw_vbios->high_yclk.value,

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

221

dc,

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

239

if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

240

dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

258

dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

55

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

64

if (dc->sclk_lvls.num_levels == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

67

for (i = 0; i < dc->sclk_lvls.num_levels; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

68

if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

69

return dc->sclk_lvls.clocks_in_khz[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

77

return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.h

39

struct dc *dc,

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

108

struct dc *dc = clk_mgr->base.ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

109

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

178

dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

62

struct dc *dc = clk_mgr_base->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

63

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

107

dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

133

if (dce121_xgmi_enabled(ctx->dc->hwseq))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

163

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

164

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

192

struct dc *dc = clk_mgr_base->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

193

struct dc_debug_options *debug = &dc->debug;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

204

if (dc->work_arounds.skip_clock_update)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

209

display_count = clk_mgr_helper_get_active_display_cnt(dc, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

274

ramp_up_dispclk_with_dpp(clk_mgr, dc, new_clocks, safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

318

struct dc_debug_options *debug = &ctx->dc->debug;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

87

struct dc *dc,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

128

struct dc *dc = clk_mgr->base.ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

129

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

110

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

152

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

155

struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

183

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

185

struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

222

struct dc *dc = clk_mgr_base->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

229

struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

234

if (dc->work_arounds.skip_clock_update)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

238

dc->debug.force_clock_mode & 0x1) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

246

display_count = clk_mgr_helper_get_active_display_cnt(dc, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

247

if (dc->res_pool->pp_smu)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

248

pp_smu = &dc->res_pool->pp_smu->nv_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

258

if (dc->debug.force_min_dcfclk_mhz > 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

259

int force_min_dcfclk_khz = dc->debug.force_min_dcfclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

284

total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

324

if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

102

dc->debug.force_clock_mode & 0x1) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

119

if (dc->debug.force_min_dcfclk_mhz > 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

120

new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

121

new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

133

total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

157

if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

184

struct dc_debug_options *debug = &ctx->dc->debug;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

90

struct dc *dc = clk_mgr_base->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

98

if (dc->work_arounds.skip_clock_update)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

113

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

119

dpp_inst = clk_mgr->base.ctx->dc->res_pool->dpps[i]->inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

137

struct dc *dc = clk_mgr_base->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

143

struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

145

if (dc->work_arounds.skip_clock_update)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

152

if (safe_to_lower && !dc->debug.disable_48mhz_pwrdwn) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

156

display_count = rn_get_active_display_cnt_wa(dc, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

518

struct dc_debug_options *debug = &clk_mgr_base->ctx->dc->debug;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

55

static int rn_get_active_display_cnt_wa(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

70

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

71

const struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

712

struct dc_debug_options *debug = &ctx->dc->debug;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

763

if (ctx->dc->config.is_single_rank_dimm)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

785

if (ctx->dc->config.is_asymmetric_memory)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

90

struct dc *dc = clk_mgr_base->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

91

struct dc_state *context = dc->current_state;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

95

display_count = rn_get_active_display_cnt_wa(dc, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

146

struct dc *dc = clk_mgr->base.ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

147

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

199

struct dc *dc = clk_mgr_base->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

206

struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

211

if (dc->work_arounds.skip_clock_update || !clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

215

(dc->debug.force_clock_mode & 0x1)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

223

display_count = clk_mgr_helper_get_active_display_cnt(dc, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

231

if (dc->debug.force_min_dcfclk_mhz > 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

232

int force_min_dcfclk_khz = dc->debug.force_min_dcfclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

256

if (dc->clk_mgr->dc_mode_softmax_enabled && safe_to_lower && !p_state_change_support) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

257

int softmax_memclk_khz = dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

270

if (dc->clk_mgr->dc_mode_softmax_enabled &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

271

new_clocks->dramclk_khz <= (int)(dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

273

(uint16_t)dc->clk_mgr->bw_params->dc_mode_softmax_memclk);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

307

if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

432

clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

433

clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

101

struct dc *dc = clk_mgr_base->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

107

if (dc->work_arounds.skip_clock_update)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

118

display_count = vg_get_active_display_cnt_wa(dc, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

142

if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) && !dc->debug.disable_min_fclk) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

148

new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz) && !dc->debug.disable_min_fclk) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

63

struct dc *dc,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

79

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

80

const struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

101

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

102

const struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

119

struct dc *dc = clk_mgr_base->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

122

for (i = 0; i < dc->res_pool->pipe_count; ++i) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

123

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

130

reset_sync_context_for_pipe(dc, context, i);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

144

struct dc *dc = clk_mgr_base->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

150

if (dc->work_arounds.skip_clock_update)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

170

display_count = dcn31_get_active_display_cnt_wa(dc, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

244

if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

258

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

644

struct dc *dc = clk_mgr_base->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

645

struct dc_state *context = dc->current_state;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

648

display_count = dcn31_get_active_display_cnt_wa(dc, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

753

if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

77

struct dc *dc,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

193

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

211

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

242

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

327

if (!clk_mgr->base.ctx->dc->debug.enable_z9_disable_interface &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

111

struct dc *dc,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

135

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

136

const struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

154

struct dc *dc = clk_mgr_base->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

157

for (i = 0; i < dc->res_pool->pipe_count; ++i) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

160

: &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

169

reset_sync_context_for_pipe(dc, context, i);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

215

struct dc *dc = clk_mgr_base->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

221

if (dc->work_arounds.skip_clock_update)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

224

display_count = dcn314_get_active_display_cnt_wa(dc, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

304

if (dc->debug.min_disp_clk_khz > 0 && requested_dispclk_khz < dc->debug.min_disp_clk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

305

requested_dispclk_khz = dc->debug.min_disp_clk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

323

if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

337

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

870

if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

914

if (ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

212

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

230

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

261

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

105

struct dc *dc = clk_mgr_base->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

108

for (i = 0; i < dc->res_pool->pipe_count; ++i) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

109

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

120

reset_sync_context_for_pipe(dc, context, i);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

135

struct dc *dc = clk_mgr_base->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

141

if (dc->work_arounds.skip_clock_update)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

144

display_count = dcn315_get_active_display_cnt_wa(dc, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

214

if (dc->debug.min_disp_clk_khz > 0 && requested_dispclk_khz < dc->debug.min_disp_clk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

215

requested_dispclk_khz = dc->debug.min_disp_clk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

233

if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

247

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

58

struct dc *dc,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

683

if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

77

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

78

const struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

206

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

224

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

255

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

108

struct dc *dc = clk_mgr_base->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

111

for (i = 0; i < dc->res_pool->pipe_count; ++i) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

114

: &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

124

reset_sync_context_for_pipe(dc, context, i);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

145

struct dc *dc = clk_mgr_base->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

151

if (dc->work_arounds.skip_clock_update)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

166

display_count = dcn316_get_active_display_cnt_wa(dc, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

222

if (dc->debug.min_disp_clk_khz > 0 && requested_dispclk_khz < dc->debug.min_disp_clk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

223

requested_dispclk_khz = dc->debug.min_disp_clk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

241

if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

255

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

668

if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

70

struct dc *dc,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

89

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

90

const struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

181

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

199

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

230

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1080

clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1081

clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1193

if (ctx->dc->debug.disable_dtb_ref_clk_switch) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1211

if (ctx->dc->debug.disable_dtb_ref_clk_switch &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

203

if (!clk_mgr->base.ctx->dc->debug.disable_dtb_ref_clk_switch) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

236

if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

239

< (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

241

= (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

247

if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

250

< (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

252

= (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

274

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

287

dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

332

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

369

struct dc *dc = clk_mgr->base.ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

383

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

386

struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

426

if (dc->debug.override_dispclk_programming) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

437

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

439

struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

473

if (dc->debug.override_dispclk_programming) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

639

struct dc *dc = clk_mgr_base->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

645

struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

652

(dc->debug.force_clock_mode & 0x1)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

664

display_count = clk_mgr_helper_get_active_display_cnt(dc, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

678

!dc->work_arounds.clock_update_disable_mask.fclk) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

688

if (dc->debug.force_min_dcfclk_mhz > 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

689

int force_min_dcfclk_khz = dc->debug.force_min_dcfclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

696

!dc->work_arounds.clock_update_disable_mask.dcfclk) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

702

!dc->work_arounds.clock_update_disable_mask.dcfclk_ds) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

722

!dc->work_arounds.clock_update_disable_mask.uclk) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

727

if (dc->clk_mgr->dc_mode_softmax_enabled) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

732

if (dc->debug.disable_dc_mode_overwrite) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

733

dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)dc->clk_mgr->bw_params->max_memclk_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

734

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)dc->clk_mgr->bw_params->max_memclk_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

737

(uint16_t)dc->clk_mgr->bw_params->dc_mode_softmax_memclk);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

739

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)dc->clk_mgr->bw_params->max_memclk_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

755

!dc->work_arounds.clock_update_disable_mask.fclk) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

762

!dc->work_arounds.clock_update_disable_mask.uclk) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

770

!dc->work_arounds.clock_update_disable_mask.uclk) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

771

if (dc->clk_mgr->dc_mode_softmax_enabled && dc->debug.disable_dc_mode_overwrite)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

773

(uint16_t)max((int)dc->clk_mgr->bw_params->dc_mode_softmax_memclk,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

818

if (!dc->debug.disable_dtb_ref_clk_switch &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

827

if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

859

if (dc->config.enable_auto_dpm_test_logs) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1216

struct dc *dc = clk_mgr_base->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1217

struct dc_state *context = dc->current_state;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1220

display_count = dcn35_get_active_display_cnt_wa(dc, context, NULL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1509

if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1564

if (ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

157

struct dc *dc,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1580

if (ctx->dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1586

ctx->dc->debug.ignore_pg = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1587

ctx->dc->debug.disable_dpp_power_gate = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1588

ctx->dc->debug.disable_hubp_power_gate = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1589

ctx->dc->debug.disable_dsc_power_gate = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1592

if (ctx->dc->config.disable_ips == DMUB_IPS_ENABLE &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1595

ctx->dc->config.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1598

ctx->dc->config.disable_ips = DMUB_IPS_DISABLE_ALL; /*pmfw not support it, disable it all*/

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

173

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

174

const struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

192

struct dc *dc = clk_mgr_base->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

195

if (dc->ctx->dce_environment == DCE_ENV_DIAG)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

198

for (i = 0; i < dc->res_pool->pipe_count; ++i) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

199

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

205

: &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

214

if (!dc->config.unify_link_enc_assignment) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

233

has_active_hpo = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(old_pipe) &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

234

dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(new_pipe);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

242

!dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

248

reset_sync_context_for_pipe(dc, context, i);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

264

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

277

dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

302

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

330

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

331

struct dpp *old_dpp = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.dpp;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

340

const struct dc *dc_struct = link->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

398

struct dc *dc = clk_mgr_base->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

405

if (dc->work_arounds.skip_clock_update)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

408

display_count = dcn35_get_active_display_cnt_wa(dc, context, &all_active_disps);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

427

if (clk_mgr->base.ctx->dc->config.allow_0_dtb_clk)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

469

if (dc->debug.force_min_dcfclk_mhz > 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

470

int force_min_dcfclk_khz = dc->debug.force_min_dcfclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

505

if (dc->debug.min_disp_clk_khz > 0 && requested_dispclk_khz < dc->debug.min_disp_clk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

506

requested_dispclk_khz = dc->debug.min_disp_clk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

517

if (!dc->debug.disable_dtb_ref_clk_switch &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

536

if (dc->debug.notify_dpia_hr_bw)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

549

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

667

if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

129

if (clk_mgr->base.ctx->dc->debug.disable_timeout)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

280

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1092

struct dc *dc = clk_mgr_base->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1093

struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1107

(dc->debug.force_clock_mode & 0x1)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1128

if (!dc->debug.disable_dtb_ref_clk_switch &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1181

if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1246

struct dc *dc = clk_mgr_base->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1268

if (dc->config.enable_auto_dpm_test_logs)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1354

const struct dc *dc = clk_mgr->base.ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1355

struct dc_state *context = dc->current_state;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1388

return clk_mgr->base.ctx->dc->current_state->bw_ctx.bw.dcn.clk.dramclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1395

return clk_mgr->base.ctx->dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1448

clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1449

clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

150

is_df_throttle_opt_enabled = !clk_mgr->base.ctx->dc->debug.force_subvp_df_throttle;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1612

if (ctx->dc->debug.disable_dtb_ref_clk_switch &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

201

if (clk_mgr->ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

262

if (!clk_mgr->base.ctx->dc->debug.disable_dtb_ref_clk_switch) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

291

if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

294

< (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

296

= (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

299

if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

302

< (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

304

= (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

544

use_hpo_encoder = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(otg_master);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

553

dccg->ctx->dc->link_srv->dp_get_encoding_format(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

565

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

624

struct dc *dc = clk_mgr->base.ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

634

if (dc->debug.override_dispclk_programming) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

776

struct dc *dc = clk_mgr_base->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

791

int total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

806

display_count = clk_mgr_helper_get_active_display_cnt(dc, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

845

if (dc->debug.force_min_dcfclk_mhz > 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

846

int force_min_dcfclk_khz = dc->debug.force_min_dcfclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

925

if (dc->clk_mgr->dc_mode_softmax_enabled) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

102

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

103

const struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

175

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

203

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

204

struct dpp *old_dpp = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.dpp;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

218

struct dc *dc = clk_mgr_base->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

224

if (dc->work_arounds.skip_clock_update)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

227

has_active_display = dcn42_has_active_display(dc, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

243

if (clk_mgr->base.ctx->dc->config.allow_0_dtb_clk)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

285

if (dc->debug.force_min_dcfclk_mhz > 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

286

int force_min_dcfclk_khz = dc->debug.force_min_dcfclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

304

if (dc->debug.min_deep_sleep_dcfclk_khz > 0 &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

305

clk_mgr_base->clks.dcfclk_deep_sleep_khz < (int)dc->debug.min_deep_sleep_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

306

clk_mgr_base->clks.dcfclk_deep_sleep_khz = (int)dc->debug.min_deep_sleep_dcfclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

329

if (dc->debug.min_disp_clk_khz > 0 && requested_dispclk_khz < (uint32_t)dc->debug.min_disp_clk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

330

requested_dispclk_khz = (uint32_t)dc->debug.min_disp_clk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

340

if (!dc->debug.disable_dtb_ref_clk_switch && new_clocks->dtbclk_en &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

367

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

448

if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

511

if (ctx->dc->config.ignore_dpref_ss) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

756

struct dc *dc = clk_mgr_base->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

757

struct dc_state *context = dc->current_state;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

761

if (dcn42_has_active_display(dc, context) == false)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

88

bool dcn42_has_active_display(struct dc *dc, const struct dc_state *context)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

916

if (clk_mgr_base->ctx->dc->debug.pstate_enabled && smu_dpm_clks.mc_address.quad_part != 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

970

if (clk_mgr_base->ctx->dc_bios->integrated_info && clk_mgr_base->ctx->dc->config.use_default_clock_table == false) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

75

bool dcn42_has_active_display(struct dc *dc, const struct dc_state *context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

76

int dcn42_get_active_display_cnt_wa(struct dc *dc, struct dc_state *context, int *all_active_disps);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

77

bool dcn42_has_active_display(struct dc *dc, const struct dc_state *context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

120

if (clk_mgr->base.ctx->dc->debug.disable_timeout)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

256

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

151

if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1000

if (!dc->vm_helper) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1005

memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));

drivers/gpu/drm/amd/display/dc/core/dc.c

1013

dc->bw_dceip = dc_dceip;

drivers/gpu/drm/amd/display/dc/core/dc.c

1021

dc->bw_vbios = dc_vbios;

drivers/gpu/drm/amd/display/dc/core/dc.c

1028

dc->dcn_soc = dcn_soc;

drivers/gpu/drm/amd/display/dc/core/dc.c

1036

dc->dcn_ip = dcn_ip;

drivers/gpu/drm/amd/display/dc/core/dc.c

1039

dc->dml2_options.bb_from_dmub = init_params->bb_from_dmub;

drivers/gpu/drm/amd/display/dc/core/dc.c

1041

dc->dml2_options.bb_from_dmub = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

1043

if (!dc_construct_ctx(dc, init_params)) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1048

dc_ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/core/dc.c

1073

dc->vendor_signature = init_params->vendor_signature;

drivers/gpu/drm/amd/display/dc/core/dc.c

1086

dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version);

drivers/gpu/drm/amd/display/dc/core/dc.c

1087

if (!dc->res_pool)

drivers/gpu/drm/amd/display/dc/core/dc.c

1091

if (dc->caps.i2c_speed_in_khz_hdcp == 0)

drivers/gpu/drm/amd/display/dc/core/dc.c

1092

dc->caps.i2c_speed_in_khz_hdcp = dc->caps.i2c_speed_in_khz;

drivers/gpu/drm/amd/display/dc/core/dc.c

1093

if (dc->check_config.max_optimizable_video_width == 0)

drivers/gpu/drm/amd/display/dc/core/dc.c

1094

dc->check_config.max_optimizable_video_width = 5120;

drivers/gpu/drm/amd/display/dc/core/dc.c

1095

dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);

drivers/gpu/drm/amd/display/dc/core/dc.c

1096

if (!dc->clk_mgr)

drivers/gpu/drm/amd/display/dc/core/dc.c

1099

dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;

drivers/gpu/drm/amd/display/dc/core/dc.c

1101

if (dc->res_pool->funcs->update_bw_bounding_box)

drivers/gpu/drm/amd/display/dc/core/dc.c

1102

dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);

drivers/gpu/drm/amd/display/dc/core/dc.c

1103

dc->soc_and_ip_translator = dc_create_soc_and_ip_translator(dc_ctx->dce_version);

drivers/gpu/drm/amd/display/dc/core/dc.c

1104

if (!dc->soc_and_ip_translator)

drivers/gpu/drm/amd/display/dc/core/dc.c

1108

if (!create_links(dc, init_params->num_virtual_links))

drivers/gpu/drm/amd/display/dc/core/dc.c

1114

if (!create_link_encoders(dc))

drivers/gpu/drm/amd/display/dc/core/dc.c

1121

dc->current_state = dc_state_create(dc, NULL);

drivers/gpu/drm/amd/display/dc/core/dc.c

1123

if (!dc->current_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1135

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

1139

(void)dc;

drivers/gpu/drm/amd/display/dc/core/dc.c

1147

static void apply_ctx_interdependent_lock(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

1152

(void)dc;

drivers/gpu/drm/amd/display/dc/core/dc.c

1157

if (dc->hwss.interdependent_update_lock)

drivers/gpu/drm/amd/display/dc/core/dc.c

1158

dc->hwss.interdependent_update_lock(dc, context, lock);

drivers/gpu/drm/amd/display/dc/core/dc.c

1160

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1162

struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1168

dc->hwss.pipe_control_lock(dc, pipe_ctx, lock);

drivers/gpu/drm/amd/display/dc/core/dc.c

1174

static void dc_update_visual_confirm_color(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc.c

1176

if (dc->debug.visual_confirm & VISUAL_CONFIRM_EXPLICIT) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1182

if (dc->ctx->dce_version >= DCN_VERSION_1_0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1185

if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)

drivers/gpu/drm/amd/display/dc/core/dc.c

1187

else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)

drivers/gpu/drm/amd/display/dc/core/dc.c

1189

else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)

drivers/gpu/drm/amd/display/dc/core/dc.c

1191

else if (dc->debug.visual_confirm == VISUAL_CONFIRM_HW_CURSOR)

drivers/gpu/drm/amd/display/dc/core/dc.c

1193

else if (dc->debug.visual_confirm == VISUAL_CONFIRM_DCC)

drivers/gpu/drm/amd/display/dc/core/dc.c

1194

get_dcc_visual_confirm_color(dc, pipe_ctx, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1196

if (dc->ctx->dce_version < DCN_VERSION_2_0)

drivers/gpu/drm/amd/display/dc/core/dc.c

1198

dc, pipe_ctx->stream->output_color_space, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1200

if (dc->ctx->dce_version >= DCN_VERSION_2_0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1201

if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE)

drivers/gpu/drm/amd/display/dc/core/dc.c

1203

else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP)

drivers/gpu/drm/amd/display/dc/core/dc.c

1205

else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MCLK_SWITCH)

drivers/gpu/drm/amd/display/dc/core/dc.c

1207

else if (dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS2)

drivers/gpu/drm/amd/display/dc/core/dc.c

1208

get_fams2_visual_confirm_color(dc, context, pipe_ctx, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1209

else if (dc->debug.visual_confirm == VISUAL_CONFIRM_VABC)

drivers/gpu/drm/amd/display/dc/core/dc.c

1211

else if (dc->debug.visual_confirm == VISUAL_CONFIRM_BOOSTED_REFRESH_RATE)

drivers/gpu/drm/amd/display/dc/core/dc.c

1218

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

1230

switch (dc->debug.visual_confirm) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1238

dc_dmub_srv_get_visual_confirm_color_cmd(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

1239

memcpy(color, &dc->ctx->dmub_srv->dmub->visual_confirm_color, sizeof(struct tg_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1252

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1276

bool dc_stream_adjust_vmin_vmax(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

1286

if (dc->ctx->dce_version > DCE_VERSION_MAX) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1287

if (dc->optimized_required &&

drivers/gpu/drm/amd/display/dc/core/dc.c

1295

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

1303

if (dc->caps.max_v_total != 0 &&

drivers/gpu/drm/amd/display/dc/core/dc.c

1304

(adjust->v_total_max > dc->caps.max_v_total || adjust->v_total_min > dc->caps.max_v_total)) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1307

return set_long_vtotal(dc, stream, adjust);

drivers/gpu/drm/amd/display/dc/core/dc.c

1313

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1316

dc->hwss.set_drr(&pipe,

drivers/gpu/drm/amd/display/dc/core/dc.c

1321

if (dc->debug.visual_confirm == VISUAL_CONFIRM_BOOSTED_REFRESH_RATE) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1323

dc_update_visual_confirm_color(dc, dc->current_state, pipe);

drivers/gpu/drm/amd/display/dc/core/dc.c

1324

dc->hwss.update_visual_confirm_color(dc, pipe, pipe->plane_res.hubp->mpcc_id);

drivers/gpu/drm/amd/display/dc/core/dc.c

1329

if (dc->hwss.notify_cursor_offload_drr_update)

drivers/gpu/drm/amd/display/dc/core/dc.c

1330

dc->hwss.notify_cursor_offload_drr_update(dc, dc->current_state, stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

1339

static void disable_dangling_plane(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc.c

1342

struct dc_state *dangling_context = dc_state_create_current_copy(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

1350

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1352

dc->current_state->res_ctx.pipe_ctx[i].stream;

drivers/gpu/drm/amd/display/dc/core/dc.c

1357

(dc->current_state->res_ctx.pipe_ctx[i].top_pipe))

drivers/gpu/drm/amd/display/dc/core/dc.c

1359

dc->current_state->res_ctx.pipe_ctx[i].top_pipe->pipe_idx;

drivers/gpu/drm/amd/display/dc/core/dc.c

1362

dc->current_state->res_ctx.pipe_ctx[i].top_pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

1371

dc->current_state->stream_count != context->stream_count)

drivers/gpu/drm/amd/display/dc/core/dc.c

1374

if (old_stream && !dc->current_state->res_ctx.pipe_ctx[i].top_pipe &&

drivers/gpu/drm/amd/display/dc/core/dc.c

1375

!dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1378

old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1386

bool is_phantom = dc_state_get_stream_subvp_type(dc->current_state, old_stream) == SUBVP_PHANTOM;

drivers/gpu/drm/amd/display/dc/core/dc.c

1387

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1397

if (dc->hwseq->funcs.blank_pixel_data)

drivers/gpu/drm/amd/display/dc/core/dc.c

1398

dc->hwseq->funcs.blank_pixel_data(dc, pipe, true);

drivers/gpu/drm/amd/display/dc/core/dc.c

1404

dc_state_rem_all_phantom_planes_for_stream(dc, old_stream, dangling_context, true);

drivers/gpu/drm/amd/display/dc/core/dc.c

1406

dc_state_rem_all_planes_for_stream(dc, old_stream, dangling_context);

drivers/gpu/drm/amd/display/dc/core/dc.c

1407

disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);

drivers/gpu/drm/amd/display/dc/core/dc.c

1410

if (!dc->debug.using_dml2)

drivers/gpu/drm/amd/display/dc/core/dc.c

1411

set_p_state_switch_method(dc, context, pipe);

drivers/gpu/drm/amd/display/dc/core/dc.c

1412

dc_update_visual_confirm_color(dc, context, pipe);

drivers/gpu/drm/amd/display/dc/core/dc.c

1415

if (dc->hwss.apply_ctx_for_surface) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1416

apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, true);

drivers/gpu/drm/amd/display/dc/core/dc.c

1417

dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);

drivers/gpu/drm/amd/display/dc/core/dc.c

1418

apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

1419

dc->hwss.post_unlock_program_front_end(dc, dangling_context);

drivers/gpu/drm/amd/display/dc/core/dc.c

1422

if (dc->res_pool->funcs->prepare_mcache_programming)

drivers/gpu/drm/amd/display/dc/core/dc.c

1423

dc->res_pool->funcs->prepare_mcache_programming(dc, dangling_context);

drivers/gpu/drm/amd/display/dc/core/dc.c

1424

if (dc->hwss.program_front_end_for_ctx) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1425

dc->hwss.interdependent_update_lock(dc, dc->current_state, true);

drivers/gpu/drm/amd/display/dc/core/dc.c

1426

dc->hwss.program_front_end_for_ctx(dc, dangling_context);

drivers/gpu/drm/amd/display/dc/core/dc.c

1427

dc->hwss.interdependent_update_lock(dc, dc->current_state, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

1428

dc->hwss.post_unlock_program_front_end(dc, dangling_context);

drivers/gpu/drm/amd/display/dc/core/dc.c

1442

current_ctx = dc->current_state;

drivers/gpu/drm/amd/display/dc/core/dc.c

1443

dc->current_state = dangling_context;

drivers/gpu/drm/amd/display/dc/core/dc.c

1448

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

1454

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1482

for (j = 0; j < dc->res_pool->stream_enc_count; j++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1483

if (dc->res_pool->stream_enc[j]->id == enc_inst) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1484

tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg(

drivers/gpu/drm/amd/display/dc/core/dc.c

1485

dc->res_pool->stream_enc[j]);

drivers/gpu/drm/amd/display/dc/core/dc.c

1490

dc->res_pool->dp_clock_source->funcs->get_dp_dto_frequency_100hz(

drivers/gpu/drm/amd/display/dc/core/dc.c

1491

dc->res_pool->dp_clock_source,

drivers/gpu/drm/amd/display/dc/core/dc.c

1499

dc->link_srv->set_dpms_off(pipe);

drivers/gpu/drm/amd/display/dc/core/dc.c

1510

struct dc *dc_create(const struct dc_init_data *init_params)

drivers/gpu/drm/amd/display/dc/core/dc.c

1512

struct dc *dc = kvzalloc_obj(*dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

1515

if (!dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

1519

dc->caps.linear_pitch_alignment = 64;

drivers/gpu/drm/amd/display/dc/core/dc.c

1520

if (!dc_construct_ctx(dc, init_params))

drivers/gpu/drm/amd/display/dc/core/dc.c

1523

if (!dc_construct(dc, init_params))

drivers/gpu/drm/amd/display/dc/core/dc.c

1526

full_pipe_count = dc->res_pool->pipe_count;

drivers/gpu/drm/amd/display/dc/core/dc.c

1527

if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)

drivers/gpu/drm/amd/display/dc/core/dc.c

1529

dc->caps.max_streams = min(

drivers/gpu/drm/amd/display/dc/core/dc.c

1531

dc->res_pool->stream_enc_count);

drivers/gpu/drm/amd/display/dc/core/dc.c

1533

dc->caps.max_links = dc->link_count;

drivers/gpu/drm/amd/display/dc/core/dc.c

1534

dc->caps.max_audios = dc->res_pool->audio_count;

drivers/gpu/drm/amd/display/dc/core/dc.c

1535

dc->caps.linear_pitch_alignment = 64;

drivers/gpu/drm/amd/display/dc/core/dc.c

1537

dc->caps.max_dp_protocol_version = DP_VERSION_1_4;

drivers/gpu/drm/amd/display/dc/core/dc.c

1539

dc->caps.max_otg_num = dc->res_pool->res_cap->num_timing_generator;

drivers/gpu/drm/amd/display/dc/core/dc.c

1541

if (dc->res_pool->dmcu != NULL)

drivers/gpu/drm/amd/display/dc/core/dc.c

1542

dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;

drivers/gpu/drm/amd/display/dc/core/dc.c

1545

dc->dcn_reg_offsets = init_params->dcn_reg_offsets;

drivers/gpu/drm/amd/display/dc/core/dc.c

1546

dc->nbio_reg_offsets = init_params->nbio_reg_offsets;

drivers/gpu/drm/amd/display/dc/core/dc.c

1547

dc->clk_reg_offsets = init_params->clk_reg_offsets;

drivers/gpu/drm/amd/display/dc/core/dc.c

1550

dc->versions.dc_ver = DC_VER;

drivers/gpu/drm/amd/display/dc/core/dc.c

1552

dc->build_id = DC_BUILD_ID;

drivers/gpu/drm/amd/display/dc/core/dc.c

1556

return dc;

drivers/gpu/drm/amd/display/dc/core/dc.c

1559

dc_destruct(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

1560

kvfree(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

1564

static void detect_edp_presence(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

1571

dc_get_edp_links(dc, edp_links, &edp_num);

drivers/gpu/drm/amd/display/dc/core/dc.c

1577

if (dc->config.edp_not_connected) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1586

void dc_hardware_init(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

1589

detect_edp_presence(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

1590

if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW)

drivers/gpu/drm/amd/display/dc/core/dc.c

1591

dc->hwss.init_hw(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

1592

dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);

drivers/gpu/drm/amd/display/dc/core/dc.c

1595

void dc_init_callbacks(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

1598

dc->ctx->cp_psp = init_params->cp_psp;

drivers/gpu/drm/amd/display/dc/core/dc.c

1601

void dc_deinit_callbacks(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

1603

memset(&dc->ctx->cp_psp, 0, sizeof(dc->ctx->cp_psp));

drivers/gpu/drm/amd/display/dc/core/dc.c

1606

void dc_destroy(struct dc **dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

1608

dc_destruct(*dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

1609

kvfree(*dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

1610

*dc = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

1614

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

1618

int pipe_count = dc->res_pool->pipe_count;

drivers/gpu/drm/amd/display/dc/core/dc.c

1632

dc->hwss.enable_per_frame_crtc_position_reset(

drivers/gpu/drm/amd/display/dc/core/dc.c

1633

dc, multisync_count, multisync_pipes);

drivers/gpu/drm/amd/display/dc/core/dc.c

1638

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

1644

int pipe_count = dc->res_pool->pipe_count;

drivers/gpu/drm/amd/display/dc/core/dc.c

165

static void destroy_links(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

1674

dc->hwss.enable_vblanks_synchronization &&

drivers/gpu/drm/amd/display/dc/core/dc.c

169

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

170

if (NULL != dc->links[i])

drivers/gpu/drm/amd/display/dc/core/dc.c

171

dc->link_srv->destroy_link(&dc->links[i]);

drivers/gpu/drm/amd/display/dc/core/dc.c

1730

if (dc->config.use_pipe_ctx_sync_logic) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1762

dc->hwss.enable_timing_synchronization(

drivers/gpu/drm/amd/display/dc/core/dc.c

1763

dc, ctx, group_index, group_size, pipe_set);

drivers/gpu/drm/amd/display/dc/core/dc.c

1766

dc->hwss.enable_vblanks_synchronization(

drivers/gpu/drm/amd/display/dc/core/dc.c

1767

dc, group_index, group_size, pipe_set);

drivers/gpu/drm/amd/display/dc/core/dc.c

1775

static bool streams_changed(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

1781

if (stream_count != dc->current_state->stream_count)

drivers/gpu/drm/amd/display/dc/core/dc.c

1784

for (i = 0; i < dc->current_state->stream_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1785

if (dc->current_state->streams[i] != streams[i])

drivers/gpu/drm/amd/display/dc/core/dc.c

1794

bool dc_validate_boot_timing(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

1812

if (dc->debug.force_odm_combine) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1830

for (i = 0; i < dc->res_pool->stream_enc_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1831

if (dc->res_pool->stream_enc[i]->id == enc_inst) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1833

se = dc->res_pool->stream_enc[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1835

tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(

drivers/gpu/drm/amd/display/dc/core/dc.c

1836

dc->res_pool->stream_enc[i]);

drivers/gpu/drm/amd/display/dc/core/dc.c

1842

if (i == dc->res_pool->stream_enc_count) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1847

if (tg_inst >= dc->res_pool->timing_generator_count) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1857

tg = dc->res_pool->timing_generators[tg_inst];

drivers/gpu/drm/amd/display/dc/core/dc.c

1934

if (tg_inst < (unsigned int)dc->res_pool->res_cap->num_dsc) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1935

dsc = dc->res_pool->dscs[tg_inst];

drivers/gpu/drm/amd/display/dc/core/dc.c

2007

dc->res_pool->dp_clock_source->funcs->get_dp_dto_frequency_100hz(

drivers/gpu/drm/amd/display/dc/core/dc.c

2008

dc->res_pool->dp_clock_source,

drivers/gpu/drm/amd/display/dc/core/dc.c

202

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

2022

if (pixels_per_cycle != 1 && !dc->debug.enable_dp_dig_pixel_rate_div_policy) {

drivers/gpu/drm/amd/display/dc/core/dc.c

207

struct dc_bios *bios = dc->ctx->dc_bios;

drivers/gpu/drm/amd/display/dc/core/dc.c

2072

if (dc->link_srv->edp_is_ilr_optimization_required(link, crtc_timing)) {

drivers/gpu/drm/amd/display/dc/core/dc.c

209

dc->link_count = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

2097

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

2105

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

2111

context = dc->current_state;

drivers/gpu/drm/amd/display/dc/core/dc.c

2112

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

2117

dc->hwss.setup_stereo)

drivers/gpu/drm/amd/display/dc/core/dc.c

2118

dc->hwss.setup_stereo(pipe, dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

2123

void dc_trigger_sync(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc.c

2125

if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2126

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

2128

enable_timing_multisync(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

2129

program_timing_sync(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

2133

static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc.c

2138

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2146

void dc_z10_restore(const struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

2148

if (dc->hwss.z10_restore)

drivers/gpu/drm/amd/display/dc/core/dc.c

2149

dc->hwss.z10_restore(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

2152

void dc_z10_save_init(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

2154

if (dc->hwss.z10_save_init)

drivers/gpu/drm/amd/display/dc/core/dc.c

2155

dc->hwss.z10_save_init(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

2166

static void determine_pipe_unlock_order(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc.c

2172

if (!dc->config.set_pipe_unlock_order)

drivers/gpu/drm/amd/display/dc/core/dc.c

2175

memset(dc->scratch.pipes_to_unlock_first, 0, sizeof(dc->scratch.pipes_to_unlock_first));

drivers/gpu/drm/amd/display/dc/core/dc.c

2176

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2187

resource_calculate_det_for_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i])) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2188

dc->scratch.pipes_to_unlock_first[i] = true;

drivers/gpu/drm/amd/display/dc/core/dc.c

2204

static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc.c

2206

struct dc_bios *dcb = dc->ctx->dc_bios;

drivers/gpu/drm/amd/display/dc/core/dc.c

2214

dc_z10_restore(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

2215

dc_allow_idle_optimizations(dc, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

2217

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2218

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

2221

subvp_prev_use |= (dc_state_get_pipe_subvp_type(dc->current_state, old_pipe) == SUBVP_PHANTOM);

drivers/gpu/drm/amd/display/dc/core/dc.c

2230

disable_vbios_mode_if_required(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

2231

dc->hwss.enable_accelerated_mode(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

2232

} else if (get_seamless_boot_stream_count(dc->current_state) > 0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2239

disable_vbios_mode_if_required(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

2242

if (dc->hwseq->funcs.wait_for_pipe_update_if_needed) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2243

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2248

dc->hwseq->funcs.wait_for_pipe_update_if_needed(dc, pipe, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

2256

dc->hwss.prepare_bandwidth(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

2261

if (dc->hwss.subvp_pipe_control_lock)

drivers/gpu/drm/amd/display/dc/core/dc.c

2262

dc->hwss.subvp_pipe_control_lock(dc, context, true, true, NULL, subvp_prev_use);

drivers/gpu/drm/amd/display/dc/core/dc.c

2263

if (dc->hwss.dmub_hw_control_lock)

drivers/gpu/drm/amd/display/dc/core/dc.c

2264

dc->hwss.dmub_hw_control_lock(dc, context, true);

drivers/gpu/drm/amd/display/dc/core/dc.c

2266

if (dc->hwss.update_dsc_pg)

drivers/gpu/drm/amd/display/dc/core/dc.c

2267

dc->hwss.update_dsc_pg(dc, context, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

2269

disable_dangling_plane(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

2273

if (dc->hwss.apply_ctx_for_surface) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2277

apply_ctx_interdependent_lock(dc, context, context->streams[i], true);

drivers/gpu/drm/amd/display/dc/core/dc.c

2278

dc->hwss.apply_ctx_for_surface(

drivers/gpu/drm/amd/display/dc/core/dc.c

2279

dc, context->streams[i],

drivers/gpu/drm/amd/display/dc/core/dc.c

2282

apply_ctx_interdependent_lock(dc, context, context->streams[i], false);

drivers/gpu/drm/amd/display/dc/core/dc.c

2283

dc->hwss.post_unlock_program_front_end(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

2288

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2290

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);

drivers/gpu/drm/amd/display/dc/core/dc.c

2293

for (i = 0; i < dc->current_state->stream_count; i++)

drivers/gpu/drm/amd/display/dc/core/dc.c

2294

dc_dmub_srv_control_cursor_offload(dc, dc->current_state, dc->current_state->streams[i], false);

drivers/gpu/drm/amd/display/dc/core/dc.c

2296

result = dc->hwss.apply_ctx_to_hw(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

2299

dc_dmub_srv_control_cursor_offload(dc, context, context->streams[i], true);

drivers/gpu/drm/amd/display/dc/core/dc.c

2303

dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_STEADY;

drivers/gpu/drm/amd/display/dc/core/dc.c

2307

dc_trigger_sync(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

2317

determine_pipe_unlock_order(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

2319

if (dc->res_pool->funcs->prepare_mcache_programming)

drivers/gpu/drm/amd/display/dc/core/dc.c

2320

dc->res_pool->funcs->prepare_mcache_programming(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

2321

if (dc->hwss.program_front_end_for_ctx) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2322

dc->hwss.interdependent_update_lock(dc, context, true);

drivers/gpu/drm/amd/display/dc/core/dc.c

2323

dc->hwss.program_front_end_for_ctx(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

2325

if (dc->hwseq->funcs.set_wait_for_update_needed_for_pipe) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2326

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2328

dc->hwseq->funcs.set_wait_for_update_needed_for_pipe(dc, pipe);

drivers/gpu/drm/amd/display/dc/core/dc.c

2332

dc->hwss.interdependent_update_lock(dc, context, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

2333

dc->hwss.post_unlock_program_front_end(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

2336

if (dc->hwss.commit_subvp_config)

drivers/gpu/drm/amd/display/dc/core/dc.c

2337

dc->hwss.commit_subvp_config(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

2338

if (dc->hwss.subvp_pipe_control_lock)

drivers/gpu/drm/amd/display/dc/core/dc.c

2339

dc->hwss.subvp_pipe_control_lock(dc, context, false, true, NULL, subvp_prev_use);

drivers/gpu/drm/amd/display/dc/core/dc.c

2340

if (dc->hwss.dmub_hw_control_lock)

drivers/gpu/drm/amd/display/dc/core/dc.c

2341

dc->hwss.dmub_hw_control_lock(dc, context, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

2349

if (dc->hwss.apply_ctx_for_surface) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2350

apply_ctx_interdependent_lock(dc, context, context->streams[i], true);

drivers/gpu/drm/amd/display/dc/core/dc.c

2351

dc->hwss.apply_ctx_for_surface(

drivers/gpu/drm/amd/display/dc/core/dc.c

2352

dc, context->streams[i],

drivers/gpu/drm/amd/display/dc/core/dc.c

2355

apply_ctx_interdependent_lock(dc, context, context->streams[i], false);

drivers/gpu/drm/amd/display/dc/core/dc.c

2356

dc->hwss.post_unlock_program_front_end(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

2369

dc->hwss.setup_stereo)

drivers/gpu/drm/amd/display/dc/core/dc.c

2370

dc->hwss.setup_stereo(pipe, dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

2382

dc_enable_stereo(dc, context, dc_streams, context->stream_count);

drivers/gpu/drm/amd/display/dc/core/dc.c

2387

hwss_wait_for_no_pipes_pending(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

239

for (i = 0; dc->link_count < connectors_num && i < MAX_LINKS; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2392

hwss_wait_for_odm_update_pending_complete(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

2394

dc->hwss.optimize_bandwidth(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

2398

dc_trigger_sync(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

2401

if (dc->hwss.update_dsc_pg)

drivers/gpu/drm/amd/display/dc/core/dc.c

2402

dc->hwss.update_dsc_pg(dc, context, true);

drivers/gpu/drm/amd/display/dc/core/dc.c

2404

if (dc->ctx->dce_version >= DCE_VERSION_MAX)

drivers/gpu/drm/amd/display/dc/core/dc.c

2409

context->stream_mask = get_stream_mask(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

2411

if (context->stream_mask != dc->current_state->stream_mask)

drivers/gpu/drm/amd/display/dc/core/dc.c

2412

dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, context->stream_mask);

drivers/gpu/drm/amd/display/dc/core/dc.c

2422

old_state = dc->current_state;

drivers/gpu/drm/amd/display/dc/core/dc.c

2423

dc->current_state = context;

drivers/gpu/drm/amd/display/dc/core/dc.c

2427

dc_state_retain(dc->current_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

2432

static bool commit_minimal_transition_state(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

2447

enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params)

drivers/gpu/drm/amd/display/dc/core/dc.c

2459

if (dc->ctx->dce_environment == DCE_ENV_VIRTUAL_HW)

drivers/gpu/drm/amd/display/dc/core/dc.c

2462

if (!streams_changed(dc, params->streams, params->stream_count) &&

drivers/gpu/drm/amd/display/dc/core/dc.c

2463

dc->current_state->power_source == params->power_source)

drivers/gpu/drm/amd/display/dc/core/dc.c

2466

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

247

DC_LOG_DC("BIOS object table - printing link object info for connector number: %d, link_index: %d", i, dc->link_count);

drivers/gpu/drm/amd/display/dc/core/dc.c

2477

res = dc_validate_stream(dc, stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

2483

dc_stream_log(dc, stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

249

link_init_params.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/core/dc.c

2498

if (params->stream_count > dc->current_state->stream_count &&

drivers/gpu/drm/amd/display/dc/core/dc.c

2499

dc->current_state->stream_count == 1) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2500

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2501

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

2508

res = commit_minimal_transition_state(dc, dc->current_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

2510

context = dc_state_create_current_copy(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

2516

res = dc_validate_with_context(dc, set, params->stream_count, context, DC_VALIDATE_MODE_AND_PROGRAMMING);

drivers/gpu/drm/amd/display/dc/core/dc.c

252

link_init_params.link_index = dc->link_count;

drivers/gpu/drm/amd/display/dc/core/dc.c

2521

if (res == DC_OK && dc->res_pool->funcs->link_encs_assign && !dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/core/dc.c

2522

dc->res_pool->funcs->link_encs_assign(

drivers/gpu/drm/amd/display/dc/core/dc.c

2523

dc, context, context->streams, context->stream_count);

drivers/gpu/drm/amd/display/dc/core/dc.c

253

link_init_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc.c

2533

if (dc->hwss.is_pipe_topology_transition_seamless &&

drivers/gpu/drm/amd/display/dc/core/dc.c

2534

!dc->hwss.is_pipe_topology_transition_seamless(dc, dc->current_state, context)) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2535

res = commit_minimal_transition_state(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

254

link = dc->link_srv->create_link(&link_init_params);

drivers/gpu/drm/amd/display/dc/core/dc.c

2542

res = dc_commit_state_no_check(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

2555

if (dc->hwss.is_abm_supported)

drivers/gpu/drm/amd/display/dc/core/dc.c

2556

status->is_abm_supported = dc->hwss.is_abm_supported(dc, context, params->streams[i]);

drivers/gpu/drm/amd/display/dc/core/dc.c

257

dc->links[dc->link_count] = link;

drivers/gpu/drm/amd/display/dc/core/dc.c

2574

struct dc *dc, bool acquire,

drivers/gpu/drm/amd/display/dc/core/dc.c

258

link->dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc.c

2582

const struct resource_pool *pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/core/dc.c

2583

struct resource_context *res_ctx = &dc->current_state->res_ctx;

drivers/gpu/drm/amd/display/dc/core/dc.c

259

++dc->link_count;

drivers/gpu/drm/amd/display/dc/core/dc.c

2609

static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc.c

2623

dc->hwss.update_pending_status(pipe);

drivers/gpu/drm/amd/display/dc/core/dc.c

2637

static void process_deferred_updates(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

2641

if (dc->debug.enable_mem_low_power.bits.cm) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2642

ASSERT(dc->dcn_ip->max_num_dpp);

drivers/gpu/drm/amd/display/dc/core/dc.c

2643

for (i = 0; i < dc->dcn_ip->max_num_dpp; i++)

drivers/gpu/drm/amd/display/dc/core/dc.c

2644

if (dc->res_pool->dpps[i]->funcs->dpp_deferred_update)

drivers/gpu/drm/amd/display/dc/core/dc.c

2645

dc->res_pool->dpps[i]->funcs->dpp_deferred_update(dc->res_pool->dpps[i]);

drivers/gpu/drm/amd/display/dc/core/dc.c

2649

void dc_post_update_surfaces_to_stream(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

2652

struct dc_state *context = dc->current_state;

drivers/gpu/drm/amd/display/dc/core/dc.c

2654

if ((!dc->optimized_required) || get_seamless_boot_stream_count(context) > 0)

drivers/gpu/drm/amd/display/dc/core/dc.c

2657

post_surface_trace(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

266

dc->lowest_dpia_link_index = MAX_LINKS;

drivers/gpu/drm/amd/display/dc/core/dc.c

2664

if (dc->ctx->dce_version < DCE_VERSION_MAX)

drivers/gpu/drm/amd/display/dc/core/dc.c

2669

if (is_flip_pending_in_pipes(dc, context))

drivers/gpu/drm/amd/display/dc/core/dc.c

267

for (i = 0; i < dc->res_pool->usb4_dpia_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2672

for (i = 0; i < dc->res_pool->pipe_count; i++)

drivers/gpu/drm/amd/display/dc/core/dc.c

2676

dc->hwss.disable_plane(dc, context, &context->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/core/dc.c

2679

process_deferred_updates(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

2681

dc->hwss.optimize_bandwidth(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

2683

if (dc->hwss.update_dsc_pg)

drivers/gpu/drm/amd/display/dc/core/dc.c

2684

dc->hwss.update_dsc_pg(dc, context, true);

drivers/gpu/drm/amd/display/dc/core/dc.c

2687

dc->optimized_required = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

2690

void dc_get_default_tiling_info(const struct dc *dc, struct dc_tiling_info *tiling_info)

drivers/gpu/drm/amd/display/dc/core/dc.c

2692

if (!dc || !tiling_info)

drivers/gpu/drm/amd/display/dc/core/dc.c

2694

if (dc->res_pool && dc->res_pool->funcs && dc->res_pool->funcs->get_default_tiling_info) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2695

dc->res_pool->funcs->get_default_tiling_info(tiling_info);

drivers/gpu/drm/amd/display/dc/core/dc.c

271

link_init_params.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/core/dc.c

273

link_init_params.link_index = dc->link_count;

drivers/gpu/drm/amd/display/dc/core/dc.c

274

link_init_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc.c

277

link = dc->link_srv->create_link(&link_init_params);

drivers/gpu/drm/amd/display/dc/core/dc.c

279

if (dc->lowest_dpia_link_index > dc->link_count)

drivers/gpu/drm/amd/display/dc/core/dc.c

280

dc->lowest_dpia_link_index = dc->link_count;

drivers/gpu/drm/amd/display/dc/core/dc.c

282

dc->links[dc->link_count] = link;

drivers/gpu/drm/amd/display/dc/core/dc.c

283

link->dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc.c

284

++dc->link_count;

drivers/gpu/drm/amd/display/dc/core/dc.c

297

link->link_index = dc->link_count;

drivers/gpu/drm/amd/display/dc/core/dc.c

298

dc->links[dc->link_count] = link;

drivers/gpu/drm/amd/display/dc/core/dc.c

299

dc->link_count++;

drivers/gpu/drm/amd/display/dc/core/dc.c

301

link->ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/core/dc.c

302

link->dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc.c

3023

static void force_immediate_gsl_plane_flip(struct dc *dc, struct dc_surface_update *updates, int surface_count)

drivers/gpu/drm/amd/display/dc/core/dc.c

3025

(void)dc;

drivers/gpu/drm/amd/display/dc/core/dc.c

318

enc_init.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/core/dc.c

329

dc->caps.num_of_internal_disp = get_num_of_internal_disp(dc->links, dc->link_count);

drivers/gpu/drm/amd/display/dc/core/dc.c

3365

static void copy_stream_update_to_stream(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

3371

struct dc_context *dc_ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/core/dc.c

341

static bool create_link_encoders(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

344

unsigned int num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia;

drivers/gpu/drm/amd/display/dc/core/dc.c

345

unsigned int num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc;

drivers/gpu/drm/amd/display/dc/core/dc.c

3482

struct dc_state *dsc_validate_context = dc_state_create_copy(dc->current_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

3487

if (dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context,

drivers/gpu/drm/amd/display/dc/core/dc.c

3560

static void update_seamless_boot_flags(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

3576

dc->optimized_required = true;

drivers/gpu/drm/amd/display/dc/core/dc.c

358

if (num_dig_link_enc > dc->res_pool->dig_link_enc_count) {

drivers/gpu/drm/amd/display/dc/core/dc.c

3582

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

3595

static void backup_and_set_minimal_pipe_split_policy(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

360

struct link_encoder *link_enc = dc->res_pool->link_encoders[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

3601

if (!dc->config.is_vmin_only_asic) {

drivers/gpu/drm/amd/display/dc/core/dc.c

3602

policy->mpc_policy = dc->debug.pipe_split_policy;

drivers/gpu/drm/amd/display/dc/core/dc.c

3603

dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;

drivers/gpu/drm/amd/display/dc/core/dc.c

3605

policy->dynamic_odm_policy = dc->debug.enable_single_display_2to1_odm_policy;

drivers/gpu/drm/amd/display/dc/core/dc.c

3606

dc->debug.enable_single_display_2to1_odm_policy = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

3607

policy->subvp_policy = dc->debug.force_disable_subvp;

drivers/gpu/drm/amd/display/dc/core/dc.c

3608

dc->debug.force_disable_subvp = true;

drivers/gpu/drm/amd/display/dc/core/dc.c

3616

static void restore_minimal_pipe_split_policy(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

362

if (!link_enc && dc->res_pool->funcs->link_enc_create_minimal) {

drivers/gpu/drm/amd/display/dc/core/dc.c

3622

if (!dc->config.is_vmin_only_asic)

drivers/gpu/drm/amd/display/dc/core/dc.c

3623

dc->debug.pipe_split_policy = policy->mpc_policy;

drivers/gpu/drm/amd/display/dc/core/dc.c

3624

dc->debug.enable_single_display_2to1_odm_policy =

drivers/gpu/drm/amd/display/dc/core/dc.c

3626

dc->debug.force_disable_subvp = policy->subvp_policy;

drivers/gpu/drm/amd/display/dc/core/dc.c

363

link_enc = dc->res_pool->funcs->link_enc_create_minimal(dc->ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

3654

static bool update_planes_and_stream_state(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

366

dc->res_pool->link_encoders[i] = link_enc;

drivers/gpu/drm/amd/display/dc/core/dc.c

3666

struct dc_context *dc_ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/core/dc.c

367

dc->res_pool->dig_link_enc_count++;

drivers/gpu/drm/amd/display/dc/core/dc.c

3677

context = dc->current_state;

drivers/gpu/drm/amd/display/dc/core/dc.c

3679

&dc->check_config, srf_updates, surface_count, stream_update).update_type;

drivers/gpu/drm/amd/display/dc/core/dc.c

3680

if (full_update_required_weak(dc, srf_updates, surface_count, stream_update, stream))

drivers/gpu/drm/amd/display/dc/core/dc.c

3687

force_immediate_gsl_plane_flip(dc, srf_updates, surface_count);

drivers/gpu/drm/amd/display/dc/core/dc.c

3689

backup_planes_and_stream_state(&dc->scratch.current_state, stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

3692

copy_stream_update_to_stream(dc, context, stream, stream_update);

drivers/gpu/drm/amd/display/dc/core/dc.c

3725

update_surface_trace(dc, srf_updates, surface_count);

drivers/gpu/drm/amd/display/dc/core/dc.c

3737

context = dc_state_create_copy(dc->current_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

3746

dc_state_remove_phantom_streams_and_planes(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

3747

dc_state_release_phantom_streams_and_planes(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

3750

if (!dc_state_rem_all_planes_for_stream(dc, stream, context)) {

drivers/gpu/drm/amd/display/dc/core/dc.c

3757

if (!dc_state_add_all_planes_for_stream(dc, stream, new_planes, surface_count, context)) {

drivers/gpu/drm/amd/display/dc/core/dc.c

3771

for (j = 0; j < dc->res_pool->pipe_count; j++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

3786

if (dc->check_config.deferred_transition_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

3787

if (dc->check_config.transition_countdown_to_steady_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

3791

dc->check_config.deferred_transition_state = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

3796

backup_and_set_minimal_pipe_split_policy(dc, context, &policy);

drivers/gpu/drm/amd/display/dc/core/dc.c

3798

if (dc->res_pool->funcs->validate_bandwidth(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING) != DC_OK) {

drivers/gpu/drm/amd/display/dc/core/dc.c

3800

restore_minimal_pipe_split_policy(dc, context, &policy);

drivers/gpu/drm/amd/display/dc/core/dc.c

3806

restore_minimal_pipe_split_policy(dc, context, &policy);

drivers/gpu/drm/amd/display/dc/core/dc.c

3808

update_seamless_boot_flags(dc, context, surface_count, stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

3813

backup_planes_and_stream_state(&dc->scratch.new_state, stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

382

static void destroy_link_encoders(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

3825

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

3832

bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

3834

for (k = 0; k < (int)dc->res_pool->pipe_count; k++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

3843

if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) {

drivers/gpu/drm/amd/display/dc/core/dc.c

3844

hwss_add_begin_cursor_offload_update(seq_state, dc, tmp_pipe);

drivers/gpu/drm/amd/display/dc/core/dc.c

3846

hwss_add_cursor_lock(seq_state, dc, pipe_to_program, true);

drivers/gpu/drm/amd/display/dc/core/dc.c

3848

hwss_add_cursor_lock(seq_state, dc, pipe_to_program->next_odm_pipe, true);

drivers/gpu/drm/amd/display/dc/core/dc.c

3852

hwss_add_set_cursor_attribute(seq_state, dc, tmp_pipe);

drivers/gpu/drm/amd/display/dc/core/dc.c

3853

if (dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/core/dc.c

3855

if (dc->hwss.set_cursor_sdr_white_level)

drivers/gpu/drm/amd/display/dc/core/dc.c

3856

hwss_add_set_cursor_sdr_white_level(seq_state, dc, tmp_pipe);

drivers/gpu/drm/amd/display/dc/core/dc.c

3857

if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe)

drivers/gpu/drm/amd/display/dc/core/dc.c

3858

hwss_add_update_cursor_offload_pipe(seq_state, dc, tmp_pipe);

drivers/gpu/drm/amd/display/dc/core/dc.c

3862

if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) {

drivers/gpu/drm/amd/display/dc/core/dc.c

3863

hwss_add_commit_cursor_offload_update(seq_state, dc, pipe_to_program);

drivers/gpu/drm/amd/display/dc/core/dc.c

3865

hwss_add_cursor_lock(seq_state, dc, pipe_to_program, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

3867

hwss_add_cursor_lock(seq_state, dc, pipe_to_program->next_odm_pipe, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

3873

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

388

if (!dc->res_pool)

drivers/gpu/drm/amd/display/dc/core/dc.c

3880

bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

3882

for (k = 0; k < (int)dc->res_pool->pipe_count; k++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

3895

if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update)

drivers/gpu/drm/amd/display/dc/core/dc.c

3896

hwss_add_begin_cursor_offload_update(seq_state, dc, tmp_pipe);

drivers/gpu/drm/amd/display/dc/core/dc.c

3898

hwss_add_cursor_lock(seq_state, dc, pipe_to_program, true);

drivers/gpu/drm/amd/display/dc/core/dc.c

3901

hwss_add_set_cursor_position(seq_state, dc, tmp_pipe);

drivers/gpu/drm/amd/display/dc/core/dc.c

3902

if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe)

drivers/gpu/drm/amd/display/dc/core/dc.c

3903

hwss_add_update_cursor_offload_pipe(seq_state, dc, tmp_pipe);

drivers/gpu/drm/amd/display/dc/core/dc.c

3905

if (dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/core/dc.c

391

num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia;

drivers/gpu/drm/amd/display/dc/core/dc.c

3910

if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update)

drivers/gpu/drm/amd/display/dc/core/dc.c

3911

hwss_add_commit_cursor_offload_update(seq_state, dc, pipe_to_program);

drivers/gpu/drm/amd/display/dc/core/dc.c

3913

hwss_add_cursor_lock(seq_state, dc, pipe_to_program, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

392

num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc;

drivers/gpu/drm/amd/display/dc/core/dc.c

3968

struct dc *dc = stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc.c

3969

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/core/dc.c

402

struct link_encoder *link_enc = dc->res_pool->link_encoders[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

406

dc->res_pool->link_encoders[i] = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

407

dc->res_pool->dig_link_enc_count--;

drivers/gpu/drm/amd/display/dc/core/dc.c

4070

static void commit_planes_do_stream_update_sequence(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

4084

for (j = 0; j < (int)dc->res_pool->pipe_count; j++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4089

if (stream_update->periodic_interrupt && dc->hwss.setup_periodic_interrupt)

drivers/gpu/drm/amd/display/dc/core/dc.c

4090

hwss_add_setup_periodic_interrupt(&seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4111

dc->hwss.set_dmdata_attributes &&

drivers/gpu/drm/amd/display/dc/core/dc.c

4119

hwss_add_program_output_csc(&seq_state, dc, pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

4140

program_cursor_attributes_sequence(dc, stream, context, &seq_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

4143

program_cursor_position_sequence(dc, stream, context, &seq_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

4197

struct pipe_ctx *dpms_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

4202

if (dpms_pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)

drivers/gpu/drm/amd/display/dc/core/dc.c

4205

hwss_add_dc_set_optimized_required(&seq_state, dc, true);

drivers/gpu/drm/amd/display/dc/core/dc.c

4209

hwss_add_prepare_bandwidth(&seq_state, dc, dc->current_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

4210

hwss_add_link_set_dpms_on(&seq_state, dc->current_state, dpms_pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4218

hwss_add_link_set_dpms_on(&seq_state, dc->current_state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

423

static bool set_long_vtotal(struct dc *dc, struct dc_stream_state *stream, struct dc_crtc_timing_adjust *adjust)

drivers/gpu/drm/amd/display/dc/core/dc.c

4231

hwss_add_abm_set_immediate_disable(&seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4241

static void commit_planes_do_stream_update(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

425

if (!dc || !stream || !adjust)

drivers/gpu/drm/amd/display/dc/core/dc.c

4250

if (dc->debug.enable_block_sequence_programming) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4254

commit_planes_do_stream_update_sequence(dc, stream, stream_update,

drivers/gpu/drm/amd/display/dc/core/dc.c

4259

hwss_execute_sequence(dc, context->block_sequence, num_steps);

drivers/gpu/drm/amd/display/dc/core/dc.c

4266

for (j = 0; j < dc->res_pool->pipe_count; j++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4271

if (stream_update->periodic_interrupt && dc->hwss.setup_periodic_interrupt)

drivers/gpu/drm/amd/display/dc/core/dc.c

4272

dc->hwss.setup_periodic_interrupt(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

428

if (!dc->current_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

4283

dc->hwss.update_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4286

dc->link_srv->dp_trace_source_sequence(

drivers/gpu/drm/amd/display/dc/core/dc.c

4293

dc->hwss.set_dmdata_attributes &&

drivers/gpu/drm/amd/display/dc/core/dc.c

4295

dc->hwss.set_dmdata_attributes(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4298

dc_stream_set_gamut_remap(dc, stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

4301

dc_stream_program_csc_matrix(dc, stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

4319

program_cursor_attributes(dc, stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

4322

program_cursor_position(dc, stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

4329

dc->link_srv->update_dsc_config(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4333

dc->link_srv->increase_mst_payload(pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

4336

dc->link_srv->reduce_mst_payload(pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

434

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

4354

dc->link_srv->dp_set_test_pattern(stream->link,

drivers/gpu/drm/amd/display/dc/core/dc.c

4364

struct pipe_ctx *dpms_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

4368

dc->link_srv->set_dpms_off(dpms_pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

437

if (dc->hwss.set_long_vtotal)

drivers/gpu/drm/amd/display/dc/core/dc.c

4370

if (dpms_pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4376

dc->optimized_required = true;

drivers/gpu/drm/amd/display/dc/core/dc.c

438

dc->hwss.set_long_vtotal(&pipe, 1, adjust->v_total_min, adjust->v_total_max);

drivers/gpu/drm/amd/display/dc/core/dc.c

4380

dc->hwss.prepare_bandwidth(dc, dc->current_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

4381

dc->link_srv->set_dpms_on(dc->current_state, dpms_pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4390

dc->link_srv->set_dpms_on(dc->current_state, dpms_pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4403

dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4414

static bool dc_dmub_should_send_dirty_rect_cmd(struct dc *dc, struct dc_stream_state *stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

4416

(void)dc;

drivers/gpu/drm/amd/display/dc/core/dc.c

4431

void dc_dmub_update_dirty_rect(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

4443

if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream))

drivers/gpu/drm/amd/display/dc/core/dc.c

4446

if (!dc->config.frame_update_cmd_version2 && !dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))

drivers/gpu/drm/amd/display/dc/core/dc.c

4466

if (dc->config.frame_update_cmd_version2)

drivers/gpu/drm/amd/display/dc/core/dc.c

4474

for (j = 0; j < dc->res_pool->pipe_count; j++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4485

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);

drivers/gpu/drm/amd/display/dc/core/dc.c

4491

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

4505

if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream))

drivers/gpu/drm/amd/display/dc/core/dc.c

4508

if (!dc->config.frame_update_cmd_version2 && !dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))

drivers/gpu/drm/amd/display/dc/core/dc.c

4528

if (dc->config.frame_update_cmd_version2)

drivers/gpu/drm/amd/display/dc/core/dc.c

4536

for (j = 0; j < dc->res_pool->pipe_count; j++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4580

static void build_dmub_cmd_list(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

4590

build_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates, context, dc_dmub_cmd, dmub_cmd_count);

drivers/gpu/drm/amd/display/dc/core/dc.c

4593

static void commit_plane_for_stream_offload_fams2_flip(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

460

bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

4603

dc_dmub_update_dirty_rect(dc, surface_count, stream,

drivers/gpu/drm/amd/display/dc/core/dc.c

4610

for (j = 0; j < dc->res_pool->pipe_count; j++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4621

dc->hwss.update_plane_addr(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4626

dc_dmub_srv_fams2_passthrough_flip(dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

4633

static void commit_planes_for_stream_fast(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

4649

determine_pipe_unlock_order(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

4651

if (dc->debug.fams2_config.bits.enable &&

drivers/gpu/drm/amd/display/dc/core/dc.c

4652

dc->debug.fams2_config.bits.enable_offload_flip &&

drivers/gpu/drm/amd/display/dc/core/dc.c

4653

dc_state_is_fams2_in_use(dc, context)) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4671

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

4673

dc_z10_restore(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

468

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

4682

for (i = 0; i < (int)dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4686

if (!dc->debug.using_dml2)

drivers/gpu/drm/amd/display/dc/core/dc.c

4687

set_p_state_switch_method(dc, context, pipe);

drivers/gpu/drm/amd/display/dc/core/dc.c

4689

if (dc->debug.visual_confirm)

drivers/gpu/drm/amd/display/dc/core/dc.c

4690

dc_update_visual_confirm_color(dc, context, pipe);

drivers/gpu/drm/amd/display/dc/core/dc.c

4697

for (j = 0; j < dc->res_pool->pipe_count; j++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4707

dc->hwss.program_triplebuffer != NULL &&

drivers/gpu/drm/amd/display/dc/core/dc.c

4708

!pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {

drivers/gpu/drm/amd/display/dc/core/dc.c

471

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

4718

commit_plane_for_stream_offload_fams2_flip(dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

4724

build_dmub_cmd_list(dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

4731

hwss_build_fast_sequence(dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

4739

hwss_execute_sequence(dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

4753

static void commit_planes_for_stream(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

4770

determine_pipe_unlock_order(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

4775

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

4777

dc_z10_restore(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

4778

if (update_type == UPDATE_TYPE_FULL && dc->optimized_required)

drivers/gpu/drm/amd/display/dc/core/dc.c

4779

hwss_process_outstanding_hw_updates(dc, dc->current_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

4781

if (update_type != UPDATE_TYPE_FAST && dc->res_pool->funcs->prepare_mcache_programming)

drivers/gpu/drm/amd/display/dc/core/dc.c

4782

dc->res_pool->funcs->prepare_mcache_programming(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

4784

for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4788

if (!dc->debug.using_dml2)

drivers/gpu/drm/amd/display/dc/core/dc.c

4789

set_p_state_switch_method(dc, context, pipe);

drivers/gpu/drm/amd/display/dc/core/dc.c

4791

if (dc->debug.visual_confirm)

drivers/gpu/drm/amd/display/dc/core/dc.c

4792

dc_update_visual_confirm_color(dc, context, pipe);

drivers/gpu/drm/amd/display/dc/core/dc.c

4797

dc_allow_idle_optimizations(dc, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

4800

dc->hwss.prepare_bandwidth(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

4802

if (dc->hwss.update_dsc_pg)

drivers/gpu/drm/amd/display/dc/core/dc.c

4803

dc->hwss.update_dsc_pg(dc, context, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

4805

context_clock_trace(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

4809

hwss_wait_for_outstanding_hw_updates(dc, dc->current_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

4816

for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4817

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc.c

4820

subvp_prev_use |= (dc_state_get_pipe_subvp_type(dc->current_state, old_pipe) == SUBVP_PHANTOM);

drivers/gpu/drm/amd/display/dc/core/dc.c

4825

for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4846

if (should_use_dmub_inbox1_lock(dc, stream->link)) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4853

dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,

drivers/gpu/drm/amd/display/dc/core/dc.c

4862

if (dc->hwss.wait_for_dcc_meta_propagation) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4863

dc->hwss.wait_for_dcc_meta_propagation(dc, top_pipe_to_program);

drivers/gpu/drm/amd/display/dc/core/dc.c

4866

if (dc->hwseq->funcs.wait_for_pipe_update_if_needed)

drivers/gpu/drm/amd/display/dc/core/dc.c

4867

dc->hwseq->funcs.wait_for_pipe_update_if_needed(dc, top_pipe_to_program, update_type < UPDATE_TYPE_FULL);

drivers/gpu/drm/amd/display/dc/core/dc.c

4869

if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4870

if (dc->hwss.subvp_pipe_control_lock)

drivers/gpu/drm/amd/display/dc/core/dc.c

4871

dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, NULL, subvp_prev_use);

drivers/gpu/drm/amd/display/dc/core/dc.c

4873

if (dc->hwss.dmub_hw_control_lock)

drivers/gpu/drm/amd/display/dc/core/dc.c

4874

dc->hwss.dmub_hw_control_lock(dc, context, true);

drivers/gpu/drm/amd/display/dc/core/dc.c

4876

dc->hwss.interdependent_update_lock(dc, context, true);

drivers/gpu/drm/amd/display/dc/core/dc.c

4878

if (dc->hwss.subvp_pipe_control_lock)

drivers/gpu/drm/amd/display/dc/core/dc.c

4879

dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);

drivers/gpu/drm/amd/display/dc/core/dc.c

4881

if (dc->hwss.dmub_hw_control_lock)

drivers/gpu/drm/amd/display/dc/core/dc.c

4882

dc->hwss.dmub_hw_control_lock(dc, context, true);

drivers/gpu/drm/amd/display/dc/core/dc.c

4888

dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);

drivers/gpu/drm/amd/display/dc/core/dc.c

4891

dc_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

4895

commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

4902

if (dc->hwss.apply_ctx_for_surface)

drivers/gpu/drm/amd/display/dc/core/dc.c

4903

dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

4904

if (dc->hwss.program_front_end_for_ctx)

drivers/gpu/drm/amd/display/dc/core/dc.c

4905

dc->hwss.program_front_end_for_ctx(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

4907

if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4908

dc->hwss.interdependent_update_lock(dc, context, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

4910

dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

4912

dc->hwss.post_unlock_program_front_end(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

4915

if (dc->hwss.commit_subvp_config)

drivers/gpu/drm/amd/display/dc/core/dc.c

4916

dc->hwss.commit_subvp_config(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

4921

if (dc->hwss.subvp_pipe_control_lock)

drivers/gpu/drm/amd/display/dc/core/dc.c

4922

dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes,

drivers/gpu/drm/amd/display/dc/core/dc.c

4925

if (dc->hwss.dmub_hw_control_lock)

drivers/gpu/drm/amd/display/dc/core/dc.c

4926

dc->hwss.dmub_hw_control_lock(dc, context, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

4931

for (j = 0; j < dc->res_pool->pipe_count; j++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4934

if ((dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP ||

drivers/gpu/drm/amd/display/dc/core/dc.c

4935

dc->debug.visual_confirm == VISUAL_CONFIRM_MCLK_SWITCH) &&

drivers/gpu/drm/amd/display/dc/core/dc.c

4941

dc->hwss.update_visual_confirm_color(dc, pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

4951

for (j = 0; j < dc->res_pool->pipe_count; j++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4959

dc->hwss.program_triplebuffer != NULL &&

drivers/gpu/drm/amd/display/dc/core/dc.c

4960

!pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4973

for (j = 0; j < dc->res_pool->pipe_count; j++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4991

if (dc->hwss.apply_ctx_for_surface && pipe_stream_status)

drivers/gpu/drm/amd/display/dc/core/dc.c

4992

dc->hwss.apply_ctx_for_surface(

drivers/gpu/drm/amd/display/dc/core/dc.c

4993

dc, pipe_ctx->stream, pipe_stream_status->plane_count, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

4997

for (j = 0; j < dc->res_pool->pipe_count; j++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5008

if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5010

dc->hwss.program_triplebuffer(

drivers/gpu/drm/amd/display/dc/core/dc.c

5011

dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);

drivers/gpu/drm/amd/display/dc/core/dc.c

5015

if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5016

dc->hwss.program_front_end_for_ctx(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

5019

if (dc->hwseq->funcs.set_wait_for_update_needed_for_pipe && update_type == UPDATE_TYPE_FULL) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5020

for (j = 0; j < dc->res_pool->pipe_count; j++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5023

dc->hwseq->funcs.set_wait_for_update_needed_for_pipe(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

5027

if (dc->debug.validate_dml_output) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5028

for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5034

cur_pipe->plane_res.hubp, dc->ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

5044

if (dc->hwss.set_flip_control_gsl)

drivers/gpu/drm/amd/display/dc/core/dc.c

5048

for (j = 0; j < dc->res_pool->pipe_count; j++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5058

dc->hwss.set_flip_control_gsl(pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

5067

for (j = 0; j < dc->res_pool->pipe_count; j++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5081

dc->hwss.trigger_3dlut_dma_load)

drivers/gpu/drm/amd/display/dc/core/dc.c

5082

dc->hwss.trigger_3dlut_dma_load(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

5085

if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5087

dc->hwss.program_triplebuffer(

drivers/gpu/drm/amd/display/dc/core/dc.c

5088

dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);

drivers/gpu/drm/amd/display/dc/core/dc.c

5091

dc->hwss.update_plane_addr(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

5096

if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5097

dc->hwss.interdependent_update_lock(dc, context, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

5099

dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

5115

if (should_use_dmub_inbox1_lock(dc, stream->link)) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5122

dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,

drivers/gpu/drm/amd/display/dc/core/dc.c

5136

if (dc->hwss.enable_phantom_streams)

drivers/gpu/drm/amd/display/dc/core/dc.c

5137

dc->hwss.enable_phantom_streams(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

5142

dc->hwss.post_unlock_program_front_end(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

5150

if (dc->hwss.disable_phantom_streams)

drivers/gpu/drm/amd/display/dc/core/dc.c

5151

dc->hwss.disable_phantom_streams(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

5155

if (dc->hwss.commit_subvp_config)

drivers/gpu/drm/amd/display/dc/core/dc.c

5156

dc->hwss.commit_subvp_config(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

5160

if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5161

if (dc->hwss.subvp_pipe_control_lock)

drivers/gpu/drm/amd/display/dc/core/dc.c

5162

dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, NULL, subvp_prev_use);

drivers/gpu/drm/amd/display/dc/core/dc.c

5163

if (dc->hwss.dmub_hw_control_lock)

drivers/gpu/drm/amd/display/dc/core/dc.c

5164

dc->hwss.dmub_hw_control_lock(dc, context, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

5166

if (dc->hwss.subvp_pipe_control_lock)

drivers/gpu/drm/amd/display/dc/core/dc.c

5167

dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);

drivers/gpu/drm/amd/display/dc/core/dc.c

5168

if (dc->hwss.dmub_hw_control_lock)

drivers/gpu/drm/amd/display/dc/core/dc.c

5169

dc->hwss.dmub_hw_control_lock(dc, context, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

5173

for (j = 0; j < dc->res_pool->pipe_count; j++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5185

if (dc->hwss.program_cursor_offload_now)

drivers/gpu/drm/amd/display/dc/core/dc.c

5186

dc->hwss.program_cursor_offload_now(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

5191

current_stream_mask = get_stream_mask(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

5194

dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, current_stream_mask);

drivers/gpu/drm/amd/display/dc/core/dc.c

5218

static bool could_mpcc_tree_change_for_active_pipes(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5226

struct dc_stream_status *cur_stream_status = stream_get_status(dc->current_state, stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

5234

dc->current_state->stream_count > 0 &&

drivers/gpu/drm/amd/display/dc/core/dc.c

5235

dc->debug.pipe_split_policy != MPC_SPLIT_AVOID) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5248

dc->current_state->stream_count == 1 &&

drivers/gpu/drm/amd/display/dc/core/dc.c

5249

dc->debug.enable_single_display_2to1_odm_policy) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5261

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5262

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

5264

if (dc_state_get_pipe_subvp_type(dc->current_state, pipe) != SUBVP_NONE) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5293

static void release_minimal_transition_state(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5298

restore_minimal_pipe_split_policy(dc, base_context, policy);

drivers/gpu/drm/amd/display/dc/core/dc.c

5316

static struct dc_state *create_minimal_transition_state(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5325

backup_and_set_minimal_pipe_split_policy(dc, base_context, policy);

drivers/gpu/drm/amd/display/dc/core/dc.c

5327

if (dc->res_pool->funcs->validate_bandwidth(dc, minimal_transition_context,

drivers/gpu/drm/amd/display/dc/core/dc.c

5336

release_minimal_transition_state(dc, minimal_transition_context, base_context, policy);

drivers/gpu/drm/amd/display/dc/core/dc.c

534

struct dc *dc = stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc.c

5344

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5349

return dc->hwss.is_pipe_topology_transition_seamless(dc, initial_state,

drivers/gpu/drm/amd/display/dc/core/dc.c

5351

dc->hwss.is_pipe_topology_transition_seamless(dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5355

static void swap_and_release_current_context(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5360

struct dc_state *old = dc->current_state;

drivers/gpu/drm/amd/display/dc/core/dc.c

537

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

5370

dc->current_state = new_context;

drivers/gpu/drm/amd/display/dc/core/dc.c

5374

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5398

static bool commit_minimal_transition_based_on_new_context(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5408

create_minimal_transition_state(dc, new_context,

drivers/gpu/drm/amd/display/dc/core/dc.c

5413

dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5414

dc->current_state,

drivers/gpu/drm/amd/display/dc/core/dc.c

5418

commit_planes_for_stream(dc, srf_updates,

drivers/gpu/drm/amd/display/dc/core/dc.c

5422

dc, intermediate_context, stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

5423

dc_state_retain(dc->current_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

5427

dc, intermediate_context, new_context, &policy);

drivers/gpu/drm/amd/display/dc/core/dc.c

5432

static bool commit_minimal_transition_based_on_current_context(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5438

struct dc_state *old_current_state = dc->current_state;

drivers/gpu/drm/amd/display/dc/core/dc.c

5453

restore_planes_and_stream_state(&dc->scratch.current_state, stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

5455

intermediate_context = create_minimal_transition_state(dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5460

dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5461

dc->current_state,

drivers/gpu/drm/amd/display/dc/core/dc.c

5467

commit_planes_for_stream(dc, srf_updates,

drivers/gpu/drm/amd/display/dc/core/dc.c

5471

dc, intermediate_context, stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

5472

dc_state_retain(dc->current_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

5475

release_minimal_transition_state(dc, intermediate_context,

drivers/gpu/drm/amd/display/dc/core/dc.c

5483

restore_planes_and_stream_state(&dc->scratch.new_state, stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

549

dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/core/dc.c

550

dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/core/dc.c

5506

static bool commit_minimal_transition_state_in_dc_update(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5513

dc, new_context, stream, NULL,

drivers/gpu/drm/amd/display/dc/core/dc.c

5516

success = commit_minimal_transition_based_on_current_context(dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5541

static bool commit_minimal_transition_state(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5553

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5563

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5564

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

5566

if (pipe->stream && dc_state_get_pipe_subvp_type(dc->current_state, pipe) == SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5575

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5592

if (pipe_in_use != dc->res_pool->pipe_count && !subvp_in_use && !odm_in_use)

drivers/gpu/drm/amd/display/dc/core/dc.c

5596

dc->current_state == transition_base_context ? "current" : "new",

drivers/gpu/drm/amd/display/dc/core/dc.c

5599

dc->debug.pipe_split_policy != MPC_SPLIT_AVOID ? "MPC in Use" :

drivers/gpu/drm/amd/display/dc/core/dc.c

5603

transition_context = create_minimal_transition_state(dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5606

ret = dc_commit_state_no_check(dc, transition_context);

drivers/gpu/drm/amd/display/dc/core/dc.c

5607

release_minimal_transition_state(dc, transition_context, transition_base_context, &policy);

drivers/gpu/drm/amd/display/dc/core/dc.c

5618

for (i = 0; i < dc->current_state->stream_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5619

for (j = 0; j < (unsigned int)dc->current_state->stream_status[i].plane_count; j++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5620

dc->current_state->stream_status[i].plane_states[j]->update_flags.raw = 0xFFFFFFFF;

drivers/gpu/drm/amd/display/dc/core/dc.c

5749

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5756

const struct dc_state *context = dc->current_state;

drivers/gpu/drm/amd/display/dc/core/dc.c

5767

if (dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/dc/core/dc.c

5770

if (dc_can_clear_cursor_limit(dc))

drivers/gpu/drm/amd/display/dc/core/dc.c

5777

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5783

if (full_update_required_weak(dc, srf_updates, surface_count, stream_update, stream))

drivers/gpu/drm/amd/display/dc/core/dc.c

5831

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5839

&& !full_update_required(dc, srf_updates, surface_count, stream_update, stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

5842

static bool update_planes_and_stream_v2(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5860

is_fast_update_only = fast_update_only(dc, fast_update, srf_updates,

drivers/gpu/drm/amd/display/dc/core/dc.c

5863

dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5871

!commit_minimal_transition_state(dc, dc->current_state))

drivers/gpu/drm/amd/display/dc/core/dc.c

5875

dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5886

if (!commit_minimal_transition_state(dc, context)) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5893

if (dc->hwss.is_pipe_topology_transition_seamless &&

drivers/gpu/drm/amd/display/dc/core/dc.c

5894

!dc->hwss.is_pipe_topology_transition_seamless(

drivers/gpu/drm/amd/display/dc/core/dc.c

5895

dc, dc->current_state, context))

drivers/gpu/drm/amd/display/dc/core/dc.c

5896

commit_minimal_transition_state_in_dc_update(dc, context, stream,

drivers/gpu/drm/amd/display/dc/core/dc.c

5899

if (is_fast_update_only && !dc->check_config.enable_legacy_fast_update) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5900

commit_planes_for_stream_fast(dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5909

dc->hwss.is_pipe_topology_transition_seamless &&

drivers/gpu/drm/amd/display/dc/core/dc.c

5910

!dc->hwss.is_pipe_topology_transition_seamless(

drivers/gpu/drm/amd/display/dc/core/dc.c

5911

dc, dc->current_state, context)) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5916

dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5924

if (dc->current_state != context)

drivers/gpu/drm/amd/display/dc/core/dc.c

5925

swap_and_release_current_context(dc, context, stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

5929

static void commit_planes_and_stream_update_on_current_context(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5940

if (fast_update_only(dc, fast_update, srf_updates, surface_count,

drivers/gpu/drm/amd/display/dc/core/dc.c

5942

!dc->check_config.enable_legacy_fast_update)

drivers/gpu/drm/amd/display/dc/core/dc.c

5943

commit_planes_for_stream_fast(dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5949

dc->current_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

5952

dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5958

dc->current_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

5961

static void commit_planes_and_stream_update_with_new_context(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

5986

if (!dc->hwss.is_pipe_topology_transition_seamless(dc, dc->current_state, new_context)) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5987

if (!dc->debug.disable_deferred_minimal_transitions) {

drivers/gpu/drm/amd/display/dc/core/dc.c

5988

dc->check_config.deferred_transition_state = true;

drivers/gpu/drm/amd/display/dc/core/dc.c

5989

dc->check_config.transition_countdown_to_steady_state =

drivers/gpu/drm/amd/display/dc/core/dc.c

5990

dc->debug.num_fast_flips_to_steady_state_override ?

drivers/gpu/drm/amd/display/dc/core/dc.c

5991

dc->debug.num_fast_flips_to_steady_state_override :

drivers/gpu/drm/amd/display/dc/core/dc.c

5994

if (commit_minimal_transition_based_on_new_context(dc, new_context, stream, stream_update,

drivers/gpu/drm/amd/display/dc/core/dc.c

5998

new_context = dc->current_state;

drivers/gpu/drm/amd/display/dc/core/dc.c

600

struct dc *dc = stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc.c

6007

commit_minimal_transition_based_on_current_context(dc, new_context, stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

6010

commit_minimal_transition_state_in_dc_update(dc, new_context, stream,

drivers/gpu/drm/amd/display/dc/core/dc.c

6013

} else if (dc->check_config.deferred_transition_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6015

dc->check_config.transition_countdown_to_steady_state =

drivers/gpu/drm/amd/display/dc/core/dc.c

6016

dc->debug.num_fast_flips_to_steady_state_override ?

drivers/gpu/drm/amd/display/dc/core/dc.c

6017

dc->debug.num_fast_flips_to_steady_state_override :

drivers/gpu/drm/amd/display/dc/core/dc.c

6022

commit_planes_for_stream(dc, srf_updates, surface_count, stream, stream_update, update_type, new_context);

drivers/gpu/drm/amd/display/dc/core/dc.c

6023

swap_and_release_current_context(dc, new_context, stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

6027

static bool update_planes_and_stream_v3(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

603

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

6045

if (!update_planes_and_stream_state(dc, srf_updates, surface_count,

drivers/gpu/drm/amd/display/dc/core/dc.c

6050

if (new_context == dc->current_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6051

commit_planes_and_stream_update_on_current_context(dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

6055

if (dc->check_config.transition_countdown_to_steady_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

6056

dc->check_config.transition_countdown_to_steady_state--;

drivers/gpu/drm/amd/display/dc/core/dc.c

6058

commit_planes_and_stream_update_with_new_context(dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

6079

bool dc_update_planes_and_stream(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

6085

dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

6103

void dc_commit_updates_for_stream(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

6113

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

6119

if (dc->ctx->dce_version >= DCN_VERSION_4_01) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6120

ret = update_planes_and_stream_v3(dc, srf_updates, surface_count,

drivers/gpu/drm/amd/display/dc/core/dc.c

6123

ret = update_planes_and_stream_v2(dc, srf_updates, surface_count,

drivers/gpu/drm/amd/display/dc/core/dc.c

6127

if (ret && dc->ctx->dce_version >= DCN_VERSION_3_2)

drivers/gpu/drm/amd/display/dc/core/dc.c

6131

uint8_t dc_get_current_stream_count(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

6133

return dc->current_state->stream_count;

drivers/gpu/drm/amd/display/dc/core/dc.c

6136

struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)

drivers/gpu/drm/amd/display/dc/core/dc.c

6138

if (i < dc->current_state->stream_count)

drivers/gpu/drm/amd/display/dc/core/dc.c

6139

return dc->current_state->streams[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

6144

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

6148

return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);

drivers/gpu/drm/amd/display/dc/core/dc.c

615

dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/core/dc.c

6154

bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)

drivers/gpu/drm/amd/display/dc/core/dc.c

6157

if (dc == NULL)

drivers/gpu/drm/amd/display/dc/core/dc.c

6160

return dal_irq_service_set(dc->res_pool->irqs, src, enable);

drivers/gpu/drm/amd/display/dc/core/dc.c

6163

void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)

drivers/gpu/drm/amd/display/dc/core/dc.c

6165

dal_irq_service_ack(dc->res_pool->irqs, src);

drivers/gpu/drm/amd/display/dc/core/dc.c

6183

bool dc_get_flip_pending_on_otg(struct dc *dc, int otg_inst)

drivers/gpu/drm/amd/display/dc/core/dc.c

6188

if (!dc || !dc->current_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

6191

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

6193

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6194

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

6213

void dc_power_down_on_boot(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

6215

if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW &&

drivers/gpu/drm/amd/display/dc/core/dc.c

6216

dc->hwss.power_down_on_boot) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6217

if (dc->current_state->stream_count > 0)

drivers/gpu/drm/amd/display/dc/core/dc.c

6220

if (dc->caps.ips_support)

drivers/gpu/drm/amd/display/dc/core/dc.c

6221

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

6222

dc->hwss.power_down_on_boot(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

6226

void dc_set_power_state(struct dc *dc, enum dc_acpi_cm_power_state power_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

6228

if (!dc->current_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

6231

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

6235

dc_state_construct(dc, dc->current_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

6237

dc_z10_restore(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

6239

dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, power_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

6241

dc->hwss.init_hw(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

6243

if (dc->hwss.init_sys_ctx != NULL &&

drivers/gpu/drm/amd/display/dc/core/dc.c

6244

dc->vm_pa_config.valid) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6245

dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);

drivers/gpu/drm/amd/display/dc/core/dc.c

6249

if (dc->caps.ips_support)

drivers/gpu/drm/amd/display/dc/core/dc.c

6250

dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3);

drivers/gpu/drm/amd/display/dc/core/dc.c

6252

if (dc->caps.ips_v2_support) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6253

if (dc->clk_mgr->funcs->set_low_power_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

6254

dc->clk_mgr->funcs->set_low_power_state(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/core/dc.c

6258

ASSERT(dc->current_state->stream_count == 0);

drivers/gpu/drm/amd/display/dc/core/dc.c

6259

dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, power_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

6261

dc_state_destruct(dc->current_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

6267

void dc_resume(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

6271

for (i = 0; i < dc->link_count; i++)

drivers/gpu/drm/amd/display/dc/core/dc.c

6272

dc->link_srv->resume(dc->links[i]);

drivers/gpu/drm/amd/display/dc/core/dc.c

6275

bool dc_is_dmcu_initialized(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

6277

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/core/dc.c

6284

enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)

drivers/gpu/drm/amd/display/dc/core/dc.c

6286

if (dc->hwss.set_clock)

drivers/gpu/drm/amd/display/dc/core/dc.c

6287

return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);

drivers/gpu/drm/amd/display/dc/core/dc.c

6290

void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)

drivers/gpu/drm/amd/display/dc/core/dc.c

6292

if (dc->hwss.get_clock)

drivers/gpu/drm/amd/display/dc/core/dc.c

6293

dc->hwss.get_clock(dc, clock_type, clock_cfg);

drivers/gpu/drm/amd/display/dc/core/dc.c

6297

bool dc_set_psr_allow_active(struct dc *dc, bool enable)

drivers/gpu/drm/amd/display/dc/core/dc.c

6302

for (i = 0; i < dc->current_state->stream_count ; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6304

struct dc_stream_state *stream = dc->current_state->streams[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

6327

bool dc_set_replay_allow_active(struct dc *dc, bool active)

drivers/gpu/drm/amd/display/dc/core/dc.c

6332

for (i = 0; i < dc->current_state->stream_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6334

struct dc_stream_state *stream = dc->current_state->streams[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

6359

bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips)

drivers/gpu/drm/amd/display/dc/core/dc.c

6361

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

6363

dc->config.disable_ips = disable_ips;

drivers/gpu/drm/amd/display/dc/core/dc.c

6368

void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, char const *caller_name)

drivers/gpu/drm/amd/display/dc/core/dc.c

6374

struct dc_state *context = dc->current_state;

drivers/gpu/drm/amd/display/dc/core/dc.c

6376

if (dc->debug.disable_idle_power_optimizations) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6381

if (allow != dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/dc/core/dc.c

6383

dc->idle_optimizations_allowed, allow, caller_name);

drivers/gpu/drm/amd/display/dc/core/dc.c

6385

if (dc->caps.ips_support && (dc->config.disable_ips == DMUB_IPS_DISABLE_ALL))

drivers/gpu/drm/amd/display/dc/core/dc.c

6388

if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->is_smu_present)

drivers/gpu/drm/amd/display/dc/core/dc.c

6389

if (!dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr))

drivers/gpu/drm/amd/display/dc/core/dc.c

6392

if (allow == dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/dc/core/dc.c

6395

if (dc->hwss.apply_idle_power_optimizations && dc->clk_mgr != NULL &&

drivers/gpu/drm/amd/display/dc/core/dc.c

6396

dc->hwss.apply_idle_power_optimizations(dc, allow)) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6397

dc->idle_optimizations_allowed = allow;

drivers/gpu/drm/amd/display/dc/core/dc.c

6402

if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->get_hard_min_fclk)

drivers/gpu/drm/amd/display/dc/core/dc.c

6403

idle_fclk_khz = dc->clk_mgr->funcs->get_hard_min_fclk(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/core/dc.c

6405

if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->get_hard_min_memclk)

drivers/gpu/drm/amd/display/dc/core/dc.c

6406

idle_dramclk_khz = dc->clk_mgr->funcs->get_hard_min_memclk(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/core/dc.c

6408

if (dc->res_pool && context) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6409

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6414

if (!dc->caps.is_apu)

drivers/gpu/drm/amd/display/dc/core/dc.c

6421

void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name)

drivers/gpu/drm/amd/display/dc/core/dc.c

6423

if (dc->caps.ips_support)

drivers/gpu/drm/amd/display/dc/core/dc.c

6424

dc_allow_idle_optimizations_internal(dc, false, caller_name);

drivers/gpu/drm/amd/display/dc/core/dc.c

6427

bool dc_dmub_is_ips_idle_state(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

6429

if (dc->debug.disable_idle_power_optimizations)

drivers/gpu/drm/amd/display/dc/core/dc.c

6432

if (!dc->caps.ips_support || (dc->config.disable_ips == DMUB_IPS_DISABLE_ALL))

drivers/gpu/drm/amd/display/dc/core/dc.c

6435

if (!dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/core/dc.c

6438

return dc->ctx->dmub_srv->idle_allowed;

drivers/gpu/drm/amd/display/dc/core/dc.c

644

bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,

drivers/gpu/drm/amd/display/dc/core/dc.c

6442

void dc_unlock_memory_clock_frequency(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

6444

if (dc->clk_mgr->funcs->set_hard_min_memclk)

drivers/gpu/drm/amd/display/dc/core/dc.c

6445

dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

6447

if (dc->clk_mgr->funcs->set_hard_max_memclk)

drivers/gpu/drm/amd/display/dc/core/dc.c

6448

dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/core/dc.c

6452

void dc_lock_memory_clock_frequency(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

6454

if (dc->clk_mgr->funcs->get_memclk_states_from_smu)

drivers/gpu/drm/amd/display/dc/core/dc.c

6455

dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/core/dc.c

6457

if (dc->clk_mgr->funcs->set_hard_min_memclk)

drivers/gpu/drm/amd/display/dc/core/dc.c

6458

dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);

drivers/gpu/drm/amd/display/dc/core/dc.c

6460

if (dc->clk_mgr->funcs->set_hard_max_memclk)

drivers/gpu/drm/amd/display/dc/core/dc.c

6461

dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/core/dc.c

6464

static void blank_and_force_memclk(struct dc *dc, bool apply, unsigned int memclk_mhz)

drivers/gpu/drm/amd/display/dc/core/dc.c

6467

struct dc_state *context = dc->current_state;

drivers/gpu/drm/amd/display/dc/core/dc.c

6472

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6476

dc->hwss.disable_pixel_data(dc, pipe, true);

drivers/gpu/drm/amd/display/dc/core/dc.c

6487

if (dc->clk_mgr->funcs->set_max_memclk)

drivers/gpu/drm/amd/display/dc/core/dc.c

6488

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, memclk_mhz);

drivers/gpu/drm/amd/display/dc/core/dc.c

6489

if (dc->clk_mgr->funcs->set_min_memclk)

drivers/gpu/drm/amd/display/dc/core/dc.c

6490

dc->clk_mgr->funcs->set_min_memclk(dc->clk_mgr, memclk_mhz);

drivers/gpu/drm/amd/display/dc/core/dc.c

6492

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6496

dc->hwss.disable_pixel_data(dc, pipe, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

6521

void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable)

drivers/gpu/drm/amd/display/dc/core/dc.c

6526

if (!dc->config.dc_mode_clk_limit_support)

drivers/gpu/drm/amd/display/dc/core/dc.c

6529

softMax = dc->clk_mgr->bw_params->dc_mode_softmax_memclk;

drivers/gpu/drm/amd/display/dc/core/dc.c

653

&dc->current_state->res_ctx, stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

6530

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6531

if (dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz > maxDPM)

drivers/gpu/drm/amd/display/dc/core/dc.c

6532

maxDPM = dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz;

drivers/gpu/drm/amd/display/dc/core/dc.c

6534

funcMin = (dc->clk_mgr->clks.dramclk_khz + 999) / 1000;

drivers/gpu/drm/amd/display/dc/core/dc.c

6535

p_state_change_support = dc->clk_mgr->clks.p_state_change_support;

drivers/gpu/drm/amd/display/dc/core/dc.c

6537

if (enable && !dc->clk_mgr->dc_mode_softmax_enabled) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6539

if (funcMin <= softMax && dc->clk_mgr->funcs->set_max_memclk)

drivers/gpu/drm/amd/display/dc/core/dc.c

6540

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, softMax);

drivers/gpu/drm/amd/display/dc/core/dc.c

6544

blank_and_force_memclk(dc, true, softMax);

drivers/gpu/drm/amd/display/dc/core/dc.c

6547

} else if (!enable && dc->clk_mgr->dc_mode_softmax_enabled) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6549

if (funcMin <= softMax && dc->clk_mgr->funcs->set_max_memclk)

drivers/gpu/drm/amd/display/dc/core/dc.c

6550

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, maxDPM);

drivers/gpu/drm/amd/display/dc/core/dc.c

6554

blank_and_force_memclk(dc, true, maxDPM);

drivers/gpu/drm/amd/display/dc/core/dc.c

6558

dc->clk_mgr->dc_mode_softmax_enabled = enable;

drivers/gpu/drm/amd/display/dc/core/dc.c

6560

bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

6566

if (dc->hwss.does_plane_fit_in_mall && dc->hwss.does_plane_fit_in_mall(dc, pitch, height, format, cursor_attr))

drivers/gpu/drm/amd/display/dc/core/dc.c

6572

void dc_hardware_release(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

6574

dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

6576

if (dc->hwss.hardware_release)

drivers/gpu/drm/amd/display/dc/core/dc.c

6577

dc->hwss.hardware_release(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

6580

void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

6582

if (dc->current_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

6583

dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down = true;

drivers/gpu/drm/amd/display/dc/core/dc.c

659

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

6598

bool dc_is_dmub_outbox_supported(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

6600

if (!dc->caps.dmcub_support)

drivers/gpu/drm/amd/display/dc/core/dc.c

6603

switch (dc->ctx->asic_id.chip_family) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6607

if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&

drivers/gpu/drm/amd/display/dc/core/dc.c

6608

!dc->debug.dpia_debug.bits.disable_dpia)

drivers/gpu/drm/amd/display/dc/core/dc.c

6615

if (!dc->debug.dpia_debug.bits.disable_dpia)

drivers/gpu/drm/amd/display/dc/core/dc.c

6624

return dc->debug.enable_dmub_aux_for_legacy_ddc;

drivers/gpu/drm/amd/display/dc/core/dc.c

6640

bool dc_enable_dmub_notifications(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

6642

return dc_is_dmub_outbox_supported(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

6652

void dc_enable_dmub_outbox(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

6654

struct dc_context *dc_ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/core/dc.c

6669

bool dc_process_dmub_aux_transfer_async(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

6676

if (link_index >= dc->link_count || !dc->links[link_index])

drivers/gpu/drm/amd/display/dc/core/dc.c

6685

if (!dc->links[link_index]->ddc->ddc_pin)

drivers/gpu/drm/amd/display/dc/core/dc.c

6690

cmd.dp_aux_access.aux_control.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

6726

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/core/dc.c

6735

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc.c

6740

struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx;

drivers/gpu/drm/amd/display/dc/core/dc.c

6744

if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))

drivers/gpu/drm/amd/display/dc/core/dc.c

6765

if (dc->hwss.set_pipe && pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc.c

6766

dc->hwss.set_pipe(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

6789

status = dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/core/dc.c

6800

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc.c

6806

if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))

drivers/gpu/drm/amd/display/dc/core/dc.c

6820

status = dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);

drivers/gpu/drm/amd/display/dc/core/dc.c

6830

uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

6835

for (index = 0; index < dc->link_count; index++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6839

if (!dc->links[index]->ddc->ddc_pin) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6840

if (dc->links[index]->ddc_hw_inst == dpia_port_index) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6863

bool dc_process_dmub_set_config_async(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

6875

cmd.set_config_access.set_config_control.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

6879

if (!dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6908

enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

6919

cmd.set_mst_alloc_slots.mst_slots_control.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

6922

if (!dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))

drivers/gpu/drm/amd/display/dc/core/dc.c

6953

void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps)

drivers/gpu/drm/amd/display/dc/core/dc.c

6959

cmd.set_tps_notification.tps_notification.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

6962

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/core/dc.c

6973

void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

6981

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/core/dc.c

6993

void dc_print_dmub_diagnostic_data(const struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

6995

dc_dmub_srv_log_diagnostic_data(dc->ctx->dmub_srv);

drivers/gpu/drm/amd/display/dc/core/dc.c

7002

void dc_disable_accelerated_mode(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

7004

bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 0);

drivers/gpu/drm/amd/display/dc/core/dc.c

7017

void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable)

drivers/gpu/drm/amd/display/dc/core/dc.c

7033

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

7044

dc_get_edp_links(dc, edp_links, &edp_num);

drivers/gpu/drm/amd/display/dc/core/dc.c

7069

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

7083

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

7094

dc_get_edp_links(dc, edp_links, &edp_num);

drivers/gpu/drm/amd/display/dc/core/dc.c

7113

void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties)

drivers/gpu/drm/amd/display/dc/core/dc.c

7116

unsigned int max_cursor_size = dc->caps.max_cursor_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

7119

if (dc->debug.allow_sw_cursor_fallback && dc->res_pool->funcs->get_max_hw_cursor_size) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7120

for (i = 0; i < dc->current_state->stream_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7121

stream_cursor_size = dc->res_pool->funcs->get_max_hw_cursor_size(dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

7122

dc->current_state,

drivers/gpu/drm/amd/display/dc/core/dc.c

7123

dc->current_state->streams[i]);

drivers/gpu/drm/amd/display/dc/core/dc.c

7146

void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link,

drivers/gpu/drm/amd/display/dc/core/dc.c

7149

(void)dc;

drivers/gpu/drm/amd/display/dc/core/dc.c

7156

edp_link->dc->link_srv->edp_set_panel_power(edp_link, powerOn);

drivers/gpu/drm/amd/display/dc/core/dc.c

7173

if (!context->clk_mgr || !context->clk_mgr->ctx || !context->clk_mgr->ctx->dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

7175

struct dc *dc = context->clk_mgr->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc.c

7177

if (dc->res_pool->funcs->get_power_profile)

drivers/gpu/drm/amd/display/dc/core/dc.c

7178

profile.power_level = dc->res_pool->funcs->get_power_profile(context);

drivers/gpu/drm/amd/display/dc/core/dc.c

718

bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream, uint8_t idx,

drivers/gpu/drm/amd/display/dc/core/dc.c

7193

struct dc *dc = context->clk_mgr->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc.c

7195

if (dc->res_pool->funcs->get_det_buffer_size)

drivers/gpu/drm/amd/display/dc/core/dc.c

7196

return dc->res_pool->funcs->get_det_buffer_size(context);

drivers/gpu/drm/amd/display/dc/core/dc.c

7214

struct dc *dc;

drivers/gpu/drm/amd/display/dc/core/dc.c

7219

dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc.c

7221

if (link->link_index < dc->lowest_dpia_link_index)

drivers/gpu/drm/amd/display/dc/core/dc.c

7224

*host_router_index = (link->link_index - dc->lowest_dpia_link_index) / dc->caps.num_of_dpias_per_host_router;

drivers/gpu/drm/amd/display/dc/core/dc.c

7225

if (*host_router_index < dc->caps.num_of_host_routers)

drivers/gpu/drm/amd/display/dc/core/dc.c

7231

bool dc_is_cursor_limit_pending(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

7235

for (i = 0; i < dc->current_state->stream_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7236

if (dc_stream_is_cursor_limit_pending(dc, dc->current_state->streams[i]))

drivers/gpu/drm/amd/display/dc/core/dc.c

7243

bool dc_can_clear_cursor_limit(const struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

7247

for (i = 0; i < dc->current_state->stream_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7248

if (dc_state_can_clear_stream_cursor_subvp_limit(dc->current_state->streams[i], dc->current_state))

drivers/gpu/drm/amd/display/dc/core/dc.c

725

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

7255

void dc_get_underflow_debug_data_for_otg(struct dc *dc, unsigned int primary_otg_inst,

drivers/gpu/drm/amd/display/dc/core/dc.c

7261

if (dc->res_pool->timing_generators[i] &&

drivers/gpu/drm/amd/display/dc/core/dc.c

7262

dc->res_pool->timing_generators[i]->inst == primary_otg_inst) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7263

tg = dc->res_pool->timing_generators[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

7268

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

7269

if (dc->hwss.get_underflow_debug_data)

drivers/gpu/drm/amd/display/dc/core/dc.c

7270

dc->hwss.get_underflow_debug_data(dc, tg, out_data);

drivers/gpu/drm/amd/display/dc/core/dc.c

7273

void dc_get_power_feature_status(struct dc *dc, unsigned int primary_otg_inst,

drivers/gpu/drm/amd/display/dc/core/dc.c

7277

out_data->uclk_p_state = dc->current_state->clk_mgr->clks.p_state_change_support;

drivers/gpu/drm/amd/display/dc/core/dc.c

7278

out_data->fams = dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching;

drivers/gpu/drm/amd/display/dc/core/dc.c

728

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

7281

bool dc_capture_register_software_state(struct dc *dc, struct dc_register_software_state *state)

drivers/gpu/drm/amd/display/dc/core/dc.c

7288

if (!dc || !dc->current_state || !state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7297

context = dc->current_state;

drivers/gpu/drm/amd/display/dc/core/dc.c

7304

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7310

for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7430

if (dc->res_pool->hubbub) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7432

for (i = 0; i < 4u && i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

744

void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,

drivers/gpu/drm/amd/display/dc/core/dc.c

7456

for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7492

if (dc->clk_mgr && dc->clk_mgr->clks.dispclk_khz > 0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7494

state->dccg.dispclk_khz = dc->clk_mgr->clks.dispclk_khz;

drivers/gpu/drm/amd/display/dc/core/dc.c

7497

for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7501

state->dccg.dppclk_khz[i] = dc->clk_mgr->clks.dppclk_khz;

drivers/gpu/drm/amd/display/dc/core/dc.c

751

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

7525

struct pipe_ctx *pipe_ctx = (i < dc->res_pool->pipe_count) ? &res_ctx->pipe_ctx[i] : NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

7539

for (unsigned int pipe_idx = 0; pipe_idx < MAX_PIPES && pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

754

if (dc->current_state->res_ctx.pipe_ctx[i].stream

drivers/gpu/drm/amd/display/dc/core/dc.c

7555

for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

756

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

7583

for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7651

for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

776

if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==

drivers/gpu/drm/amd/display/dc/core/dc.c

7769

for (i = 0; i < max_pipes && i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

778

pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

7857

void dc_log_preos_dmcub_info(const struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

7859

dc_dmub_srv_log_preos_dmcub_info(dc->ctx->dmub_srv);

drivers/gpu/drm/amd/display/dc/core/dc.c

7862

bool dc_get_qos_info(struct dc *dc, struct dc_qos_info *info)

drivers/gpu/drm/amd/display/dc/core/dc.c

7864

const struct dc_clocks *clk = &dc->current_state->bw_ctx.bw.dcn.clk;

drivers/gpu/drm/amd/display/dc/core/dc.c

7871

if (!dc->hwss.measure_memory_qos) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7875

dc->hwss.measure_memory_qos(dc, &measured);

drivers/gpu/drm/amd/display/dc/core/dc.c

788

dc_exit_ips_for_hw_access(stream->ctx->dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

7884

if (dc->clk_mgr && dc->clk_mgr->funcs->get_requested_memory_qos) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7885

dc->clk_mgr->funcs->get_requested_memory_qos(dc->clk_mgr, &requested);

drivers/gpu/drm/amd/display/dc/core/dc.c

7897

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

7900

if (!dc->clk_mgr || !dc->clk_mgr->funcs)

drivers/gpu/drm/amd/display/dc/core/dc.c

7903

return dc->clk_mgr->funcs->override_memory_bandwidth_request(

drivers/gpu/drm/amd/display/dc/core/dc.c

7904

dc->clk_mgr, bw_mbps * 1000) / 1000;

drivers/gpu/drm/amd/display/dc/core/dc.c

7917

struct dc *dc;

drivers/gpu/drm/amd/display/dc/core/dc.c

7944

dc_exit_ips_for_hw_access(scratch->dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

7946

scratch->dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

7982

scratch->dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

7983

scratch->dc->current_state,

drivers/gpu/drm/amd/display/dc/core/dc.c

7989

static void transition_countdown_init(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

7991

dc->check_config.transition_countdown_to_steady_state =

drivers/gpu/drm/amd/display/dc/core/dc.c

7992

dc->debug.num_fast_flips_to_steady_state_override ?

drivers/gpu/drm/amd/display/dc/core/dc.c

7993

dc->debug.num_fast_flips_to_steady_state_override :

drivers/gpu/drm/amd/display/dc/core/dc.c

8005

dc_exit_ips_for_hw_access(scratch->dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

8016

fast_update_only(scratch->dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

8022

!scratch->dc->check_config.enable_legacy_fast_update;

drivers/gpu/drm/amd/display/dc/core/dc.c

8025

scratch->dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

8036

if (scratch->new_context == scratch->dc->current_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

8047

const bool seamless = scratch->dc->hwss.is_pipe_topology_transition_seamless(

drivers/gpu/drm/amd/display/dc/core/dc.c

8048

scratch->dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

8049

scratch->dc->current_state,

drivers/gpu/drm/amd/display/dc/core/dc.c

8054

if (scratch->dc->check_config.deferred_transition_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

8056

transition_countdown_init(scratch->dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

8060

if (!scratch->dc->debug.disable_deferred_minimal_transitions) {

drivers/gpu/drm/amd/display/dc/core/dc.c

8061

scratch->dc->check_config.deferred_transition_state = true;

drivers/gpu/drm/amd/display/dc/core/dc.c

8062

transition_countdown_init(scratch->dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

8066

scratch->dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

8079

scratch->backup_context = scratch->dc->current_state;

drivers/gpu/drm/amd/display/dc/core/dc.c

808

bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

8080

restore_planes_and_stream_state(&scratch->dc->scratch.current_state, scratch->stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

8083

scratch->dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

8101

restore_planes_and_stream_state(&scratch->dc->scratch.new_state, scratch->stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

8113

scratch->dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

8131

scratch->dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

814

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

8148

scratch->dc->check_config.deferred_transition_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

8167

scratch->dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

817

if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {

drivers/gpu/drm/amd/display/dc/core/dc.c

8179

swap_and_release_current_context(scratch->dc, scratch->intermediate_context, scratch->stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

818

pipes = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

8180

dc_state_retain(scratch->dc->current_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

819

dc->hwss.program_gamut_remap(pipes);

drivers/gpu/drm/amd/display/dc/core/dc.c

8191

if (scratch->dc->check_config.transition_countdown_to_steady_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

8192

scratch->dc->check_config.transition_countdown_to_steady_state--;

drivers/gpu/drm/amd/display/dc/core/dc.c

8196

swap_and_release_current_context(scratch->dc, scratch->new_context, scratch->stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

8201

if (scratch->dc->check_config.deferred_transition_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

8212

restore_planes_and_stream_state(&scratch->dc->scratch.new_state, scratch->stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

8228

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

8235

const enum dce_version version = dc->ctx->dce_version;

drivers/gpu/drm/amd/display/dc/core/dc.c

8239

.dc = dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

827

bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

833

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

836

if (dc->current_state->res_ctx.pipe_ctx[i].stream

drivers/gpu/drm/amd/display/dc/core/dc.c

839

pipes = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

840

dc->hwss.program_output_csc(dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

852

void dc_stream_set_static_screen_params(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

861

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

867

if (dc->current_state->res_ctx.pipe_ctx[j].stream

drivers/gpu/drm/amd/display/dc/core/dc.c

870

&dc->current_state->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

875

dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, params);

drivers/gpu/drm/amd/display/dc/core/dc.c

878

static void dc_destruct(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

881

if (dc->res_pool && dc->res_pool->funcs->link_encs_assign &&

drivers/gpu/drm/amd/display/dc/core/dc.c

882

!dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/core/dc.c

883

link_enc_cfg_init(dc, dc->current_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

885

if (dc->current_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

886

dc_state_release(dc->current_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

887

dc->current_state = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

890

destroy_links(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

892

destroy_link_encoders(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

894

if (dc->clk_mgr) {

drivers/gpu/drm/amd/display/dc/core/dc.c

895

dc_destroy_clk_mgr(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/core/dc.c

896

dc->clk_mgr = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

899

dc_destroy_resource_pool(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

901

dc_destroy_soc_and_ip_translator(&dc->soc_and_ip_translator);

drivers/gpu/drm/amd/display/dc/core/dc.c

903

if (dc->link_srv)

drivers/gpu/drm/amd/display/dc/core/dc.c

904

link_destroy_link_service(&dc->link_srv);

drivers/gpu/drm/amd/display/dc/core/dc.c

906

if (dc->ctx) {

drivers/gpu/drm/amd/display/dc/core/dc.c

907

if (dc->ctx->gpio_service)

drivers/gpu/drm/amd/display/dc/core/dc.c

908

dal_gpio_service_destroy(&dc->ctx->gpio_service);

drivers/gpu/drm/amd/display/dc/core/dc.c

910

if (dc->ctx->created_bios)

drivers/gpu/drm/amd/display/dc/core/dc.c

911

dal_bios_parser_destroy(&dc->ctx->dc_bios);

drivers/gpu/drm/amd/display/dc/core/dc.c

912

kfree(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/core/dc.c

913

dc_perf_trace_destroy(&dc->ctx->perf_trace);

drivers/gpu/drm/amd/display/dc/core/dc.c

915

kfree(dc->ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

916

dc->ctx = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

919

kfree(dc->bw_vbios);

drivers/gpu/drm/amd/display/dc/core/dc.c

920

dc->bw_vbios = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

922

kfree(dc->bw_dceip);

drivers/gpu/drm/amd/display/dc/core/dc.c

923

dc->bw_dceip = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

925

kfree(dc->dcn_soc);

drivers/gpu/drm/amd/display/dc/core/dc.c

926

dc->dcn_soc = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

928

kfree(dc->dcn_ip);

drivers/gpu/drm/amd/display/dc/core/dc.c

929

dc->dcn_ip = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

931

kfree(dc->vm_helper);

drivers/gpu/drm/amd/display/dc/core/dc.c

932

dc->vm_helper = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

936

static bool dc_construct_ctx(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

945

dc_stream_init_rmcm_3dlut(dc);

drivers/gpu/drm/amd/display/dc/core/dc.c

949

dc_ctx->dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc.c

95

dc->ctx

drivers/gpu/drm/amd/display/dc/core/dc.c

967

dc->dml.logger = dc_ctx->logger;

drivers/gpu/drm/amd/display/dc/core/dc.c

978

dc->ctx = dc_ctx;

drivers/gpu/drm/amd/display/dc/core/dc.c

98

dc->ctx->logger

drivers/gpu/drm/amd/display/dc/core/dc.c

980

dc->link_srv = link_create_link_service();

drivers/gpu/drm/amd/display/dc/core/dc.c

981

if (!dc->link_srv)

drivers/gpu/drm/amd/display/dc/core/dc.c

987

static bool dc_construct(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

996

dc->config = init_params->flags;

drivers/gpu/drm/amd/display/dc/core/dc.c

999

dc->vm_helper = kzalloc_obj(struct vm_helper);

drivers/gpu/drm/amd/display/dc/core/dc_debug.c

176

void post_surface_trace(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc_debug.c

178

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/core/dc_debug.c

185

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_debug.c

188

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/core/dc_debug.c

40

dc->ctx->logger

drivers/gpu/drm/amd/display/dc/core/dc_debug.c

45

if (dc->debug.surface_trace) \

drivers/gpu/drm/amd/display/dc/core/dc_debug.c

50

if (dc->debug.clock_trace) \

drivers/gpu/drm/amd/display/dc/core/dc_debug.c

55

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_debug.c

60

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1001

if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1002

block_sequence[*num_steps].params.commit_cursor_offload_update_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1008

block_sequence[*num_steps].params.cursor_lock_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1031

if (dc->hwss.set_flip_control_gsl && current_mpc_pipe->plane_state->update_flags.raw) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1037

if (dc->hwss.program_triplebuffer && dc->debug.enable_tri_buf && current_mpc_pipe->plane_state->update_flags.raw) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1038

block_sequence[*num_steps].params.program_triplebuffer_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1044

if (dc->hwss.update_plane_addr && current_mpc_pipe->plane_state->update_flags.bits.addr_update) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1047

block_sequence[*num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1054

block_sequence[*num_steps].params.update_plane_addr_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1061

block_sequence[*num_steps].params.set_input_transfer_func_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1068

if (dc->hwss.program_gamut_remap &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1107

block_sequence[*num_steps].params.set_output_transfer_func_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1113

if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1114

dc->hwss.update_visual_confirm_color) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1115

block_sequence[*num_steps].params.update_visual_confirm_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1122

block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1129

block_sequence[*num_steps].params.set_output_csc_params.mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1136

block_sequence[*num_steps].params.set_ocsc_default_params.mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1149

if (dc->hwss.pipe_control_lock) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1150

block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1156

if (dc->hwss.subvp_pipe_control_lock_fast) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1157

block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1164

if (dc->hwss.dmub_hw_control_lock_fast) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1165

block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1181

if (dc->hwss.program_cursor_offload_now) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1182

block_sequence[*num_steps].params.program_cursor_update_now_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1198

void hwss_execute_sequence(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1204

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1211

dc->hwss.subvp_pipe_control_lock_fast(params);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1214

dc->hwss.pipe_control_lock(params->pipe_control_lock_params.dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1224

dc->hwss.program_triplebuffer(params->program_triplebuffer_params.dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1229

dc->hwss.update_plane_addr(params->update_plane_addr_params.dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1233

hws->funcs.set_input_transfer_func(params->set_input_transfer_func_params.dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1247

hwss_setup_periodic_interrupt(dc, params);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1250

hwss_update_info_frame(dc, params);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1265

hws->funcs.set_output_transfer_func(params->set_output_transfer_func_params.dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1270

dc->hwss.update_visual_confirm_color(params->update_visual_confirm_params.dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1290

dc->hwss.wait_for_dcc_meta_propagation(

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1291

params->wait_for_dcc_meta_propagation_params.dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1295

dc->hwss.dmub_hw_control_lock_fast(params);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1307

dc->hwss.program_cursor_offload_now(

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1308

params->program_cursor_update_now_params.dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1316

dc->hwss.apply_update_flags_for_phantom(params->apply_update_flags_for_phantom_params.pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1319

dc->hwss.update_phantom_vp_position(params->update_phantom_vp_position_params.dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1663

hwss_disable_audio_stream(dc, params);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1666

hwss_prepare_bandwidth(dc, params);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1682

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1687

seq_state->steps[*seq_state->num_steps].params.pipe_control_lock_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1714

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1719

seq_state->steps[*seq_state->num_steps].params.program_triplebuffer_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1731

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1735

seq_state->steps[*seq_state->num_steps].params.update_plane_addr_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1746

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1751

seq_state->steps[*seq_state->num_steps].params.set_input_transfer_func_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1801

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1806

seq_state->steps[*seq_state->num_steps].params.set_output_transfer_func_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1818

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1823

seq_state->steps[*seq_state->num_steps].params.update_visual_confirm_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1924

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1928

seq_state->steps[*seq_state->num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1965

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1970

seq_state->steps[*seq_state->num_steps].params.update_phantom_vp_position_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2231

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2235

seq_state->steps[*seq_state->num_steps].params.set_abm_pipe_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2472

void hwss_wait_for_all_blank_complete(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2476

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

248

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2493

void hwss_wait_for_odm_update_pending_complete(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2512

hwss_wait_for_all_blank_complete(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2515

void hwss_wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

252

(void)dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2530

dc->hwss.update_pending_status(pipe);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2540

void hwss_wait_for_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2549

int opp_count = dc->res_pool->res_cap->num_opp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2554

for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2564

if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && dc->hwss.wait_for_all_pending_updates) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2565

dc->hwss.wait_for_all_pending_updates(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2575

if ((dc->res_pool->opps[opp_inst] != NULL) &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2576

(dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst])) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2577

dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2578

dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2583

hwss_wait_for_odm_update_pending_complete(dc, dc_context);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2586

void hwss_process_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2589

hwss_wait_for_outstanding_hw_updates(dc, dc_context);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2592

if (dc->hwss.program_outstanding_updates)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2593

dc->hwss.program_outstanding_updates(dc, dc_context);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2791

void hwss_update_info_frame(struct dc *dc, union block_sequence_params *params)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2795

if (dc->hwss.update_info_frame)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2796

dc->hwss.update_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2799

void hwss_setup_periodic_interrupt(struct dc *dc, union block_sequence_params *params)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2803

if (dc->hwss.setup_periodic_interrupt)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2804

dc->hwss.setup_periodic_interrupt(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2912

struct dc *dc = params->set_abm_pipe_params.dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2915

dc->hwss.set_pipe(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2929

struct dc *dc = params->set_abm_immediate_disable_params.dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2932

if (dc && dc->hwss.set_abm_immediate_disable)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2933

dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2956

struct dc *dc = params->dc_set_optimized_required_params.dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2959

dc->optimized_required = optimized_required;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3039

struct dc *dc = params->update_force_pstate_params.dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3041

struct dce_hwseq *hwseq = dc->hwseq;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3044

hwseq->funcs.update_force_pstate(dc, context);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3354

struct dc *dc = params->dc_ip_request_cntl_params.dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3356

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3359

hws->funcs.dc_ip_request_cntl(dc, enable);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3444

struct dc *dc = params->mpc_update_mpcc_params.dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3446

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3449

hws->funcs.update_mpcc(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3507

struct dc *dc = params->abort_cursor_offload_update_params.dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3510

if (dc && dc->hwss.abort_cursor_offload_update)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3511

dc->hwss.abort_cursor_offload_update(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3516

struct dc *dc = params->cursor_lock_params.dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3520

if (dc && dc->hwss.cursor_lock)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3521

dc->hwss.cursor_lock(dc, pipe_ctx, lock);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3526

struct dc *dc = params->begin_cursor_offload_update_params.dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3529

if (dc && dc->hwss.begin_cursor_offload_update)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3530

dc->hwss.begin_cursor_offload_update(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3535

struct dc *dc = params->commit_cursor_offload_update_params.dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3538

if (dc && dc->hwss.commit_cursor_offload_update)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3539

dc->hwss.commit_cursor_offload_update(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3544

struct dc *dc = params->update_cursor_offload_pipe_params.dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3547

if (dc && dc->hwss.update_cursor_offload_pipe)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3548

dc->hwss.update_cursor_offload_pipe(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3561

struct dc *dc = params->set_cursor_attribute_params.dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3564

if (dc && dc->hwss.set_cursor_attribute)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3565

dc->hwss.set_cursor_attribute(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3588

struct dc *dc = params->set_cursor_position_params.dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3591

if (dc && dc->hwss.set_cursor_position)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3592

dc->hwss.set_cursor_position(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3597

struct dc *dc = params->set_cursor_sdr_white_level_params.dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3600

if (dc && dc->hwss.set_cursor_sdr_white_level)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3601

dc->hwss.set_cursor_sdr_white_level(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3606

struct dc *dc = params->program_gamut_remap_params.pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3608

if (dc && dc->hwss.program_gamut_remap)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3609

dc->hwss.program_gamut_remap(params->program_gamut_remap_params.pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3614

struct dc *dc = params->program_output_csc_params.dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3620

if (dc && dc->hwss.program_output_csc)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3621

dc->hwss.program_output_csc(dc, pipe_ctx, colorspace, matrix, opp_id);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3765

if (link && link->dc && link->dc->link_srv && link->dc->link_srv->dp_trace_source_sequence)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3766

link->dc->link_srv->dp_trace_source_sequence(link, source);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3775

pipe_ctx->stream->link->dc && pipe_ctx->stream->link->dc->link_srv &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3776

pipe_ctx->stream->link->dc->link_srv->increase_mst_payload)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3777

pipe_ctx->stream->link->dc->link_srv->increase_mst_payload(pipe_ctx, mst_stream_bw);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3786

pipe_ctx->stream->link->dc && pipe_ctx->stream->link->dc->link_srv &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3787

pipe_ctx->stream->link->dc->link_srv->reduce_mst_payload)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3788

pipe_ctx->stream->link->dc->link_srv->reduce_mst_payload(pipe_ctx, mst_stream_bw);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3802

if (link && link->dc && link->dc->link_srv && link->dc->link_srv->dp_set_test_pattern)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3803

link->dc->link_srv->dp_set_test_pattern(link, test_pattern, test_pattern_color_space,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3812

pipe_ctx->stream->link->dc && pipe_ctx->stream->link->dc->link_srv &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3813

pipe_ctx->stream->link->dc->link_srv->set_dpms_off)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3814

pipe_ctx->stream->link->dc->link_srv->set_dpms_off(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3817

void hwss_disable_audio_stream(struct dc *dc, union block_sequence_params *params)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3819

if (dc->hwss.disable_audio_stream)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3820

dc->hwss.disable_audio_stream(

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3824

void hwss_prepare_bandwidth(struct dc *dc, union block_sequence_params *params)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3826

if (dc && dc->hwss.prepare_bandwidth)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3827

dc->hwss.prepare_bandwidth(dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3837

pipe_ctx->stream->link->dc && pipe_ctx->stream->link->dc->link_srv &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3838

pipe_ctx->stream->link->dc->link_srv->set_dpms_on)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3839

pipe_ctx->stream->link->dc->link_srv->set_dpms_on(state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3943

struct dc *dc, bool optimized_required)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3947

seq_state->steps[*seq_state->num_steps].params.dc_set_optimized_required_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3954

struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3958

seq_state->steps[*seq_state->num_steps].params.set_abm_immediate_disable_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4091

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4096

seq_state->steps[*seq_state->num_steps].params.dc_ip_request_cntl_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

440

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

453

if (dc->caps.is_apu) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

455

*color = sm_ver_colors[dc->config.smart_mux_version];

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4669

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4674

seq_state->steps[*seq_state->num_steps].params.abort_cursor_offload_update_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4681

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4686

seq_state->steps[*seq_state->num_steps].params.set_cursor_attribute_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4717

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4722

seq_state->steps[*seq_state->num_steps].params.set_cursor_position_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4729

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4734

seq_state->steps[*seq_state->num_steps].params.set_cursor_sdr_white_level_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4741

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4749

seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4769

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4774

seq_state->steps[*seq_state->num_steps].params.update_force_pstate_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4817

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4822

seq_state->steps[*seq_state->num_steps].params.begin_cursor_offload_update_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4829

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4839

seq_state->steps[*seq_state->num_steps].params.cursor_lock_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4859

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4864

seq_state->steps[*seq_state->num_steps].params.update_cursor_offload_pipe_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4871

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4876

seq_state->steps[*seq_state->num_steps].params.commit_cursor_offload_update_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5015

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5020

seq_state->steps[*seq_state->num_steps].params.setup_periodic_interrupt_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5124

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5129

seq_state->steps[*seq_state->num_steps].params.prepare_bandwidth_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

592

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

605

if (dc->ctx->dce_version < DCN_VERSION_4_01) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

639

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

646

if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !vba)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

669

for (unsigned int i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

712

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

719

if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !context || !dc->debug.fams2_config.bits.enable)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

723

if (!dc_state_is_fams2_in_use(dc, context)) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

731

void hwss_build_fast_sequence(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

742

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

753

if (dc->hwss.wait_for_dcc_meta_propagation) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

754

block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

759

if (dc->hwss.subvp_pipe_control_lock_fast) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

760

block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

767

if (dc->hwss.dmub_hw_control_lock_fast) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

768

is_dmub_lock_required = dc_state_is_fams2_in_use(dc, context) ||

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

769

dmub_hw_lock_mgr_does_link_require_lock(dc, stream->link);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

771

block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

777

if (dc->hwss.pipe_control_lock) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

778

block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

786

block_sequence[*num_steps].params.send_dmcub_cmd_params.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

793

if (dc->hwss.setup_periodic_interrupt && stream->update_flags.bits.periodic_interrupt) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

794

block_sequence[*num_steps].params.setup_periodic_interrupt_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

802

block_sequence[*num_steps].params.update_info_frame_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

815

if (dc->hwss.set_dmdata_attributes && stream->update_flags.bits.dmdata &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

838

if ((dc->hwss.set_cursor_attribute && stream->update_flags.bits.cursor_attr) ||

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

839

(dc->hwss.set_cursor_position && stream->update_flags.bits.cursor_pos))

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

840

enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

843

if (dc->hwss.set_cursor_attribute && stream->update_flags.bits.cursor_attr) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

855

if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

856

block_sequence[*num_steps].params.begin_cursor_offload_update_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

862

block_sequence[*num_steps].params.cursor_lock_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

869

block_sequence[*num_steps].params.cursor_lock_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

893

if (dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

902

block_sequence[*num_steps].params.set_cursor_sdr_white_level_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

908

if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

909

block_sequence[*num_steps].params.update_cursor_offload_pipe_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

919

if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

920

block_sequence[*num_steps].params.commit_cursor_offload_update_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

926

block_sequence[*num_steps].params.cursor_lock_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

933

block_sequence[*num_steps].params.cursor_lock_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

945

if (dc->hwss.set_cursor_position && stream->update_flags.bits.cursor_pos) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

961

if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

962

block_sequence[*num_steps].params.begin_cursor_offload_update_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

968

block_sequence[*num_steps].params.cursor_lock_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

976

block_sequence[*num_steps].params.set_cursor_position_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

981

if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

982

block_sequence[*num_steps].params.update_cursor_offload_pipe_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

989

if (dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

150

stream->link_enc = stream->ctx->dc->res_pool->link_encoders[eng_idx];

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

171

for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

180

for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

246

link_enc = link->dc->res_pool->link_encoders[assignment.eng_id - ENGINE_ID_DIGA];

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

252

static void clear_enc_assignments(const struct dc *dc, struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

265

for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

266

if (dc->res_pool->link_encoders[i])

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

274

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

277

clear_enc_assignments(dc, state);

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

29

#define DC_LOGGER dc->ctx->logger

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

290

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

300

ASSERT(dc->current_state->res_ctx.link_enc_cfg_ctx.mode == LINK_ENC_CFG_STEADY);

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

303

for (i = 0; i < dc->current_state->stream_count; i++)

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

304

dc->res_pool->funcs->link_enc_unassign(state, dc->current_state->streams[i]);

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

329

if (state != dc->current_state) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

330

struct dc_state *prev_state = dc->current_state;

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

399

link_enc_cfg_validate(dc, state);

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

40

for (i = 0; i < stream->ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

403

dc->current_state->res_ctx.link_enc_cfg_ctx.transient_assignments[i] =

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

41

link_enc = stream->ctx->dc->res_pool->link_encoders[i];

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

410

dc->current_state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

452

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

457

struct dc_stream_state *stream = link_enc_cfg_get_stream_using_link_enc(dc, eng_id);

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

466

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

473

struct link_enc_assignment assignment = get_assignment(dc, i);

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

485

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

491

stream = link_enc_cfg_get_stream_using_link_enc(dc, eng_id);

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

500

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

512

struct link_enc_assignment assignment = get_assignment(dc, i);

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

517

link_enc = link->dc->res_pool->link_encoders[assignment.eng_id - ENGINE_ID_DIGA];

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

525

struct link_encoder *link_enc_cfg_get_next_avail_link_enc(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

536

struct link_enc_assignment assignment = get_assignment(dc, i);

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

542

for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

544

dc->res_pool->link_encoders[i] != NULL) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

545

link_enc = dc->res_pool->link_encoders[i];

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

562

link->dc->res_pool->funcs->link_encs_assign) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

563

link_enc = link_enc_cfg_get_link_enc_used_by_link(link->ctx->dc, link);

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

566

link->ctx->dc);

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

574

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

58

static struct link_enc_assignment get_assignment(struct dc *dc, int i)

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

587

dc->current_state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

593

link_enc = stream->link->dc->res_pool->link_encoders[assignment.eng_id - ENGINE_ID_DIGA];

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

601

bool link_enc_cfg_is_link_enc_avail(struct dc *dc, enum engine_id eng_id, struct dc_link *link)

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

608

struct link_enc_assignment assignment = get_assignment(dc, i);

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

62

if (dc->current_state->res_ctx.link_enc_cfg_ctx.mode == LINK_ENC_CFG_TRANSIENT)

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

622

bool link_enc_cfg_validate(struct dc *dc, struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

63

assignment = dc->current_state->res_ctx.link_enc_cfg_ctx.transient_assignments[i];

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

65

assignment = dc->current_state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

699

for (j = 0; j < dc->res_pool->res_cap->num_dig_link_enc; j++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

734

void link_enc_cfg_set_transient_mode(struct dc *dc, struct dc_state *current_state, struct dc_state *new_state)

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

104

return link->dc->link_srv->is_hdcp1x_supported(link, signal);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

109

return link->dc->link_srv->is_hdcp2x_supported(link, signal);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

114

link->dc->link_srv->clear_dprx_states(link);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

119

return link->dc->link_srv->reset_cur_dp_mst_topology(link);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

126

return link->dc->link_srv->dp_link_bandwidth_kbps(link, link_settings);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

131

return link->dc->link_srv->frl_link_bandwidth_kbps(link_rate);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

139

return link->dc->link_srv->frl_margin_check_uncompressed_video(params, inter);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

146

return link->dc->link_srv->dp_required_hblank_size_bytes(link,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

150

void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map)

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

152

dc->link_srv->get_cur_res_map(dc, map);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

155

void dc_restore_link_res_map(const struct dc *dc, uint32_t *map)

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

157

dc->link_srv->restore_res_map(dc, map);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

162

link->dc->link_srv->wait_for_unlocked(link);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

169

return link->dc->link_srv->update_dsc_config(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

173

dc_get_oem_i2c_device(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

175

return dc->res_pool->oem_device;

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

179

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

182

if (dc->res_pool->oem_device)

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

184

dc->res_pool,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

185

dc->res_pool->oem_device,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

192

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

197

struct dc_link *link = dc->links[link_index];

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

201

dc->res_pool,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

207

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

210

struct ddc_service *ddc = dc->res_pool->oem_device;

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

214

dc->res_pool,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

223

link->dc->link_srv->dp_handle_automated_test(link);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

234

return link->dc->link_srv->dp_set_test_pattern(link, test_pattern,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

239

void dc_link_set_drive_settings(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

245

dc->link_srv->get_cur_link_res(link, &link_res);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

246

dc->link_srv->dp_set_drive_settings(link, &link_res, lt_settings);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

249

void dc_link_set_preferred_link_settings(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

253

dc->link_srv->dp_set_preferred_link_settings(dc, link_setting, link);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

256

void dc_link_set_preferred_training_settings(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

262

dc->link_srv->dp_set_preferred_training_settings(dc, link_setting,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

268

return link->dc->link_srv->dp_trace_is_initialized(link);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

275

link->dc->link_srv->dp_trace_set_is_logged_flag(link, in_detection, is_logged);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

280

return link->dc->link_srv->dp_trace_is_logged(link, in_detection);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

286

return link->dc->link_srv->dp_trace_get_lt_end_timestamp(link, in_detection);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

292

return link->dc->link_srv->dp_trace_get_lt_counts(link, in_detection);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

297

return link->dc->link_srv->dp_trace_get_link_loss_count(link);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

306

return link->dc->link_srv->add_remote_sink(link, edid, len, init_data);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

311

link->dc->link_srv->remove_remote_sink(link, sink);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

318

const struct dc *dc = ddc->link->dc;

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

320

return dc->link_srv->aux_transfer_raw(

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

324

uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw)

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

326

return dc->link_srv->bw_kbps_from_raw_frl_link_rate_data(bw);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

332

return link->dc->link_srv->edp_decide_link_settings(link, link_setting, req_bw);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

339

return link->dc->link_srv->dp_get_max_link_enc_cap(link, max_link_enc_cap);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

345

return link->dc->link_srv->mst_decide_link_encoding_format(link);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

350

return link->dc->link_srv->dp_get_verified_link_cap(link);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

359

else if (link->dc->link_srv->dp_get_encoding_format(&link->verified_link_cap) ==

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

362

else if (link->dc->link_srv->dp_get_encoding_format(&link->verified_link_cap) ==

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

381

return link->dc->link_srv->dp_is_sink_present(link);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

386

return link->dc->link_srv->dp_is_fec_supported(link);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

39

struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index)

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

392

link->dc->link_srv->dp_overwrite_extended_receiver_cap(link);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

397

return link->dc->link_srv->dp_should_enable_fec(link);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

403

link->dc->link_srv->dpia_handle_usb4_bandwidth_allocation_for_link(link, peak_bw);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

410

return link->dc->link_srv->dp_parse_link_loss_status(link, hpd_irq_dpcd_data);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

415

return link->dc->link_srv->dp_should_allow_hpd_rx_irq(link);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

420

link->dc->link_srv->dp_handle_link_loss(link);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

427

return link->dc->link_srv->dp_read_hpd_rx_irq_data(link, irq_data);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

434

return link->dc->link_srv->dp_handle_hpd_rx_irq(link, out_hpd_irq_dpcd_data,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

44

return dc->links[link_index];

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

440

link->dc->link_srv->dpcd_write_rx_power_ctrl(link, on);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

446

return link->dc->link_srv->dp_decide_lttpr_mode(link, link_setting);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

451

link->dc->link_srv->edp_panel_backlight_power_on(link, wait_for_hpd);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

456

return link->dc->link_srv->edp_get_backlight_level(link);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

463

return link->dc->link_srv->edp_get_backlight_level_nits(link,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

47

void dc_get_edp_links(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

471

return link->dc->link_srv->edp_set_backlight_level(link,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

480

return link->dc->link_srv->edp_set_backlight_level_nits(link, isHDR,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

486

return link->dc->link_srv->edp_get_target_backlight_pwm(link);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

491

return link->dc->link_srv->edp_get_psr_state(link, state);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

497

return link->dc->link_srv->edp_set_psr_allow_active(link, allow_active, wait,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

505

return link->dc->link_srv->edp_setup_psr(link, stream, psr_config, psr_context);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

511

return link->dc->link_srv->edp_set_replay_allow_active(link, allow_active, wait,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

517

return link->dc->link_srv->edp_get_replay_state(link, state);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

522

return link->dc->link_srv->dp_pr_enable(link, enable);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

528

return link->dc->link_srv->dp_pr_update_state(link, update_state_data);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

534

return link->dc->link_srv->dp_pr_set_general_cmd(link, general_cmd_data);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

539

return link->dc->link_srv->dp_pr_get_state(link, state);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

54

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

544

return link->dc->link_srv->edp_wait_for_t12(link);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

549

return link->dc->link_srv->hdmi_frl_poll_status_flag(link);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

555

return link->dc->link_srv->hdmi_frl_get_verified_link_cap(link);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

558

void dc_link_set_preferred_frl_link_settings(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

56

if (!dc->links[i])

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

563

link->dc->link_srv->hdmi_frl_set_preferred_link_settings(dc, link_setting, lt_overrides, link);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

568

return link->dc->link_srv->get_hpd_state(link);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

573

link->dc->link_srv->enable_hpd(link);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

578

link->dc->link_srv->disable_hpd(link);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

58

if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP) {

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

583

link->dc->link_srv->enable_hpd_filter(link, enable);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

586

enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *new_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

588

return dc->link_srv->validate_dp_tunnel_bandwidth(dc, new_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

59

edp_links[*edp_num] = dc->links[i];

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

595

link->dc->link_srv->edp_get_alpm_support(link, auxless_support, auxwake_support);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

66

bool dc_get_edp_link_panel_inst(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

76

dc_get_edp_links(dc, edp_links, &edp_num);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

87

return link->dc->link_srv->detect_link(link, reason);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

93

return link->dc->link_srv->detect_connection_type(link, type);

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

98

return link->dc->link_srv->get_status(link);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1014

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1018

if (dc->debug.visual_confirm == VISUAL_CONFIRM_DISABLE || !pipe_ctx->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1024

if ((dc->debug.visual_confirm_rect_height >= VISUAL_CONFIRM_BASE_MIN) &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1025

dc->debug.visual_confirm_rect_height <= VISUAL_CONFIRM_BASE_MAX)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1026

*base_offset = dc->debug.visual_confirm_rect_height;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

106

static void capture_pipe_topology_data(struct dc *dc, int plane_idx, int slice_idx, int stream_idx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

109

struct pipe_topology_snapshot *current_snapshot = &dc->debug_data.topology_history.snapshots[dc->debug_data.topology_history.current_snapshot_index];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

125

static void start_new_topology_snapshot(struct dc *dc, struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

128

dc->debug_data.topology_history.current_snapshot_index = (dc->debug_data.topology_history.current_snapshot_index + 1) % MAX_TOPOLOGY_SNAPSHOTS;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

131

struct pipe_topology_snapshot *current_snapshot = &dc->debug_data.topology_history.snapshots[dc->debug_data.topology_history.current_snapshot_index];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

135

current_snapshot->timestamp_us = dm_get_timestamp(dc->ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1554

if ((pipe_ctx->stream->ctx->dc->config.use_spl) && (!pipe_ctx->stream->ctx->dc->debug.disable_spl)) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1775

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1778

(void)dc;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2050

struct dc *dc = otg_master->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2053

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2383

static void resource_log_pipe(struct dc *dc, struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2387

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2398

capture_pipe_topology_data(dc, plane_idx, slice_idx, stream_idx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2410

capture_pipe_topology_data(dc, 0xF, slice_idx, stream_idx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2421

capture_pipe_topology_data(dc, plane_idx, slice_idx, stream_idx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2431

capture_pipe_topology_data(dc, 0xF, slice_idx, stream_idx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2440

capture_pipe_topology_data(dc, plane_idx, slice_idx, stream_idx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2449

capture_pipe_topology_data(dc, plane_idx, slice_idx, stream_idx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2456

static void resource_log_pipe_for_stream(struct dc *dc, struct dc_state *state,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2479

resource_log_pipe(dc, dpp_pipes[dpp_idx],

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2485

resource_log_pipe(dc, opp_heads[slice_idx],

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2513

void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2517

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2521

start_new_topology_snapshot(dc, state);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2535

resource_log_pipe_for_stream(dc, state, otg_master, stream_idx, is_phantom_pipe);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2551

resource_log_pipe_for_stream(dc, state, otg_master, stream_idx, is_phantom_pipe);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

271

struct resource_pool *dc_create_resource_pool(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

281

init_data->num_virtual_links, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2821

const struct dc *dc = link->dc;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2822

const struct resource_context *res_ctx = &dc->current_state->res_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2825

link_res->hpo_frl_link_enc = get_temp_hpo_frl_link_enc(res_ctx, dc->res_pool, link);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2830

dc->res_pool, link);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

285

init_data->num_virtual_links, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

289

init_data->num_virtual_links, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

294

(uint8_t)init_data->num_virtual_links, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

298

(uint8_t)init_data->num_virtual_links, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

302

(uint8_t)init_data->num_virtual_links, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3024

const struct dc *dc = link->dc;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3025

const struct resource_context *res_ctx = &dc->current_state->res_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3059

static bool add_dio_link_enc_to_ctx(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

306

(uint8_t)init_data->num_virtual_links, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3084

int new_enc_index = find_free_dio_link_enc(res_ctx, dc->links[link_index], pool, stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

310

(uint8_t)init_data->num_virtual_links, dc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3134

struct dc *dc = stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3136

return dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

316

(uint8_t)init_data->num_virtual_links, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3167

if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(otg_master)) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3176

if (stream->ctx->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3192

stream->ctx->dc, context, stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

321

(uint8_t)init_data->num_virtual_links, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

327

res_pool = dcn10_create_resource_pool(init_data, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

330

res_pool = dcn20_create_resource_pool(init_data, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

333

res_pool = dcn21_create_resource_pool(init_data, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

336

res_pool = dcn201_create_resource_pool(init_data, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

339

res_pool = dcn30_create_resource_pool(init_data, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

342

res_pool = dcn301_create_resource_pool(init_data, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

345

res_pool = dcn302_create_resource_pool(init_data, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

348

res_pool = dcn303_create_resource_pool(init_data, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

351

res_pool = dcn31_create_resource_pool(init_data, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

354

res_pool = dcn314_create_resource_pool(init_data, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

357

res_pool = dcn315_create_resource_pool(init_data, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

360

res_pool = dcn316_create_resource_pool(init_data, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

363

res_pool = dcn32_create_resource_pool(init_data, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

366

res_pool = dcn321_create_resource_pool(init_data, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

369

res_pool = dcn35_create_resource_pool(init_data, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

372

res_pool = dcn351_create_resource_pool(init_data, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

375

res_pool = dcn36_create_resource_pool(init_data, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

378

res_pool = dcn401_create_resource_pool(init_data, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

381

res_pool = dcn42_create_resource_pool(init_data, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

384

res_pool = dcn42b_create_resource_pool(init_data, dc);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

392

if (dc->ctx->dc_bios->fw_info_valid) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

394

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4048

static void mark_seamless_boot_stream(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4051

struct dc_bios *dcb = dc->ctx->dc_bios;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4053

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4057

if (!dc->config.allow_seamless_boot_optimization)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4061

if (dc_validate_boot_timing(dc, stream->sink, &stream->timing)) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

412

void dc_destroy_resource_pool(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

414

if (dc) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

415

if (dc->res_pool)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

416

dc->res_pool->funcs->destroy(&dc->res_pool);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4164

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4168

const struct resource_pool *pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4170

struct dc_context *dc_ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4178

mark_seamless_boot_stream(dc, stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

418

kfree(dc->hwseq);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4194

acquired = acquire_otg_master_pipe_for_stream(dc->current_state,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4203

dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4236

if (!add_dio_link_enc_to_ctx(dc, context, pool, pipe_ctx, stream))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4246

if (!dc->link_srv->dp_decide_link_settings(stream,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4250

dc->link_srv->dp_decide_tunnel_settings(stream,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4253

if (dc->link_srv->dp_get_encoding_format(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4271

if (dc->config.unify_link_enc_assignment && is_dio_encoder)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4272

if (!add_dio_link_enc_to_ctx(dc, context, pool, pipe_ctx, stream))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4318

bool dc_resource_is_dsc_encoding_supported(const struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4320

if (dc->res_pool == NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4323

return dc->res_pool->res_cap->num_dsc > 0;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4364

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4382

if (!dc_state_add_plane(dc, stream, set[i].plane_states[j], state))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4406

enum dc_status dc_validate_with_context(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4424

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4495

if (!dc_state_rem_all_planes_for_stream(dc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

451

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4519

if (!dc_state_rem_all_phantom_planes_for_stream(dc, del_streams[i], context, true)) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4524

res = dc_state_remove_phantom_stream(dc, context, del_streams[i]);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4525

dc_state_release_phantom_stream(dc, context, del_streams[i]);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4527

if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context)) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4532

res = dc_state_remove_stream(dc, context, del_streams[i]);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4544

mark_seamless_boot_stream(dc, add_streams[i]);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

455

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4557

res = dc_state_add_stream(dc, context, add_streams[i]);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4561

if (!add_all_planes_for_stream(dc, add_streams[i], set, set_count, context)) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4573

if (!add_all_planes_for_stream(dc, unchanged_streams[i], set, set_count, context)) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4585

res = dc_validate_global_state(dc, context, validate_mode);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4588

if ((dc->hwss.calculate_pix_rate_divider) && (res == DC_OK)) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4590

dc->hwss.calculate_pix_rate_divider(dc, context, add_streams[i]);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

462

create_funcs->read_dce_straps(dc->ctx, &straps);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4700

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4711

if (dc->res_pool->funcs->validate_global) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4712

result = dc->res_pool->funcs->validate_global(dc, new_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4720

for (j = 0; j < dc->res_pool->pipe_count; j++) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4727

if (dc->debug.enable_hblank_borrow)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4730

if (dc->res_pool->funcs->patch_unknown_plane_state &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4733

result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4747

dc->res_pool,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4750

pipe_ctx->clock_source = dc->res_pool->dp_clock_source;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4753

dc->res_pool,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4759

result = resource_build_scaling_params_for_context(dc, new_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4762

result = dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, validate_mode);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5193

if (pipe_ctx->stream->ctx->dc->res_pool->funcs->get_vstartup_for_pipe)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5194

vstartup_start = pipe_ctx->stream->ctx->dc->res_pool->funcs->get_vstartup_for_pipe(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5227

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5232

const struct resource_pool *pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5245

if (!dc->config.disable_disp_pll_sharing)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5316

if (pipe_ctx_old->stream->ctx->dc->config.unify_link_enc_assignment) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5319

} else if (pipe_ctx_old->stream->ctx->dc->res_pool->funcs->link_encs_assign) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5321

struct dc *dc = pipe_ctx_old->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5323

link_enc_cfg_get_link_enc_used_by_stream_current(dc, pipe_ctx_old->stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5468

enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5470

if (dc == NULL || stream == NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5474

struct timing_generator *tg = dc->res_pool->timing_generators[0];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5492

res = dc->link_srv->validate_mode_timing(stream,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5499

enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5509

if (dc->res_pool->funcs->validate_plane)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5510

return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

557

dc->caps.dynamic_audio = false;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

559

dc->caps.dynamic_audio = true;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5639

const struct dc *dc = link->dc;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5640

const struct resource_context *res_ctx = &dc->current_state->res_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5644

if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5645

link_res->hpo_dp_link_enc = get_temp_hpo_dp_link_enc(res_ctx, dc->res_pool, link);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5648

} else if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5649

dc->config.unify_link_enc_assignment) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5651

dc->res_pool, link);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5659

void reset_syncd_pipes_from_disabled_pipes(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5666

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5667

pipe_ctx_old = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5677

for (j = 0; j < dc->res_pool->pipe_count; j++) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5687

void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5700

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

572

dc->hwseq = create_funcs->create_hwseq(ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5721

void reset_sync_context_for_pipe(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5729

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5738

uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5743

if (dc->ctx->dce_version == DCN_VERSION_3_1 &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5744

dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5840

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5848

const struct resource_pool *pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5880

dcn20_acquire_dsc(dc, &state->res_ctx, &sec_pipe->stream_res.dsc, sec_pipe->stream_res.opp->inst);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5887

dcn20_build_mapped_resource(dc, state, sec_pipe->stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5894

enum dc_status update_dp_encoder_resources_for_test_harness(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5898

if (dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5902

&context->res_ctx, dc->res_pool, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5908

&context->res_ctx, dc->res_pool,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5914

if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, dc->res_pool, pipe_ctx, pipe_ctx->stream))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5920

&context->res_ctx, dc->res_pool,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5929

if (pipe_ctx->link_res.dio_link_enc == NULL && dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5930

if (!add_dio_link_enc_to_ctx(dc, context, dc->res_pool, pipe_ctx, pipe_ctx->stream))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5943

if (context->clk_mgr->ctx->dc->res_pool->funcs->program_mcache_pipe_config)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5944

context->clk_mgr->ctx->dc->res_pool->funcs->program_mcache_pipe_config(context, mcache_params);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5949

void resource_init_common_dml2_callbacks(struct dc *dc, struct dml2_configuration_options *dml2_options)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5951

dml2_options->callbacks.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5970

dml2_options->svp_pstate.callbacks.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

643

if (stream1->ctx->dc->config.vblank_alignment_dto_params &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

644

stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0 &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

670

if (diff < stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

723

if (stream1->ctx->dc->caps.disable_dp_clk_share)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

98

dc->ctx->logger

drivers/gpu/drm/amd/display/dc/core/dc_stat.c

48

void dc_stat_get_dmub_notification(const struct dc *dc, struct dmub_notification *notify)

drivers/gpu/drm/amd/display/dc/core/dc_stat.c

55

struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub;

drivers/gpu/drm/amd/display/dc/core/dc_stat.c

68

get_link_index_from_dpia_port_index(dc, notify->instance);

drivers/gpu/drm/amd/display/dc/core/dc_stat.c

83

void dc_stat_get_dmub_dataout(const struct dc *dc, uint32_t *dataout)

drivers/gpu/drm/amd/display/dc/core/dc_stat.c

85

struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub;

drivers/gpu/drm/amd/display/dc/core/dc_state.c

1010

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

1018

if (dc->current_state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

1019

is_fams2_in_use |= dc->current_state->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable;

drivers/gpu/drm/amd/display/dc/core/dc_state.c

184

static void init_state(struct dc *dc, struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

190

memcpy(&state->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));

drivers/gpu/drm/amd/display/dc/core/dc_state.c

194

struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *params)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

203

init_state(dc, state);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

204

dc_state_construct(dc, state);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

210

if (dc->debug.using_dml2) {

drivers/gpu/drm/amd/display/dc/core/dc_state.c

212

status = dml2_create(dc, &dc->dml2_options, &state->bw_ctx.dml2);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

220

if (dc->caps.dcmode_power_limits_present) {

drivers/gpu/drm/amd/display/dc/core/dc_state.c

224

dc_power_status = dml2_create(dc, &dc->dml2_dc_power_options, &state->bw_ctx.dml2_dc_power_source);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

315

void dc_state_copy_current(struct dc *dc, struct dc_state *dst_state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

317

dc_state_copy(dst_state, dc->current_state);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

320

struct dc_state *dc_state_create_current_copy(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

322

return dc_state_create_copy(dc->current_state);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

325

void dc_state_construct(struct dc *dc, struct dc_state *state)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

327

state->clk_mgr = dc->clk_mgr;

drivers/gpu/drm/amd/display/dc/core/dc_state.c

330

if (dc->res_pool)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

331

link_enc_cfg_init(dc, state);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

408

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

412

(void)dc;

drivers/gpu/drm/amd/display/dc/core/dc_state.c

415

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

417

if (state->stream_count >= dc->res_pool->timing_generator_count) {

drivers/gpu/drm/amd/display/dc/core/dc_state.c

427

state, dc->res_pool, stream);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

43

dc->ctx->logger

drivers/gpu/drm/amd/display/dc/core/dc_state.c

438

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

452

dc->current_state, dc->res_pool, stream, 1);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

454

state, dc->res_pool, stream);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

465

dc_stream_release_3dlut_for_stream(dc, stream);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

485

static void remove_mpc_combine_for_stream(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

494

new_ctx, cur_ctx, dc->res_pool,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

499

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

504

struct resource_pool *pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/core/dc_state.c

526

dc->current_state, pool, otg_master_pipe, plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

531

remove_mpc_combine_for_stream(dc, state,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

532

dc->current_state,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

535

dc->current_state, pool,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

544

dc->current_state, dc->res_pool, stream,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

548

dc->current_state, pool,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

567

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

574

struct resource_pool *pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/core/dc_state.c

628

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

653

if (!dc_state_remove_plane(dc, stream, del_planes[i], state))

drivers/gpu/drm/amd/display/dc/core/dc_state.c

660

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

670

if (!dc_state_add_plane(dc, stream, plane_states[i], state)) {

drivers/gpu/drm/amd/display/dc/core/dc_state.c

745

struct dc_stream_state *dc_state_create_phantom_stream(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

751

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

770

void dc_state_release_phantom_stream(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

774

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

784

struct dc_plane_state *dc_state_create_phantom_plane(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

789

struct dc_plane_state *phantom_plane = dc_create_plane_state(dc);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

791

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

806

void dc_state_release_phantom_plane(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

810

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

821

enum dc_status dc_state_add_phantom_stream(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

828

enum dc_status res = dc_state_add_stream(dc, state, phantom_stream);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

856

enum dc_status dc_state_remove_phantom_stream(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

877

return dc_state_remove_stream(dc, state, phantom_stream);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

881

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

886

bool res = dc_state_add_plane(dc, phantom_stream, phantom_plane, state);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

898

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

903

return dc_state_remove_plane(dc, phantom_stream, phantom_plane, state);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

907

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

933

if (!dc_state_remove_plane(dc, phantom_stream, del_planes[i], state))

drivers/gpu/drm/amd/display/dc/core/dc_state.c

936

dc_state_release_phantom_plane(dc, state, del_planes[i]);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

943

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

949

return dc_state_add_all_planes_for_stream(dc, phantom_stream, phantom_planes, plane_count, state);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

953

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

960

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_state.c

966

dc_state_rem_all_phantom_planes_for_stream(dc, phantom_stream, state, false);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

967

dc_state_remove_phantom_stream(dc, state, phantom_stream);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

975

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_state.c

986

dc_state_release_phantom_stream(dc, state, phantom_streams[i]);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

991

dc_state_release_phantom_plane(dc, state, phantom_planes[i]);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

1003

unsigned int num_rmcm = dc->caps.color.mpc.num_rmcm_3dluts;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

1007

if (dc->res_pool->rmcm_3dlut[i].isInUse &&

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

1008

dc->res_pool->rmcm_3dlut[i].stream == stream)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

1009

return &dc->res_pool->rmcm_3dlut[i];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

1018

if (!dc->res_pool->rmcm_3dlut[i].isInUse) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

1019

dc->res_pool->rmcm_3dlut[i].isInUse = true;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

1020

dc->res_pool->rmcm_3dlut[i].stream = stream;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

1021

return &dc->res_pool->rmcm_3dlut[i];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

1031

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

1035

dc_stream_get_3dlut_for_stream(dc, stream, false);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

1045

void dc_stream_init_rmcm_3dlut(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

1047

unsigned int num_rmcm = dc->caps.color.mpc.num_rmcm_3dluts;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

1050

dc->res_pool->rmcm_3dlut[i].isInUse = false;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

1051

dc->res_pool->rmcm_3dlut[i].stream = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

1052

dc->res_pool->rmcm_3dlut[i].protection_bits = 0;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

1343

bool dc_stream_is_cursor_limit_pending(struct dc *dc, struct dc_stream_state *stream)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

1347

if (dc->current_state)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

1348

is_limit_pending = dc_state_get_stream_cursor_subvp_limit(stream, dc->current_state);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

1353

bool dc_stream_can_clear_cursor_limit(struct dc *dc, struct dc_stream_state *stream)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

1357

if (dc->current_state)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

1358

can_clear_limit = dc_state_get_stream_cursor_subvp_limit(stream, dc->current_state) &&

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

1361

dc_stream_check_cursor_attributes(stream, dc->current_state, &stream->cursor_attributes));

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

267

if (new_stream->ctx->dc->res_pool->funcs->link_encs_assign &&

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

268

!new_stream->ctx->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

286

struct dc *dc = stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

287

return dc_state_get_stream_status(dc->current_state, stream);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

293

struct dc *dc = stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

294

return dc_state_get_stream_status(dc->current_state, stream);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

304

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

310

bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

315

res_ctx = &dc->current_state->res_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

326

if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

327

dc->hwss.begin_cursor_offload_update(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

329

dc->hwss.cursor_lock(dc, pipe_to_program, true);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

331

dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, true);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

335

dc->hwss.set_cursor_attribute(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

336

if (dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

338

if (dc->hwss.set_cursor_sdr_white_level)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

339

dc->hwss.set_cursor_sdr_white_level(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

340

if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

341

dc->hwss.update_cursor_offload_pipe(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

345

if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

346

dc->hwss.commit_cursor_offload_update(dc, pipe_to_program);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

348

dc->hwss.cursor_lock(dc, pipe_to_program, false);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

350

dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, false);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

363

const struct dc *dc;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

37

#define DC_LOGGER dc->ctx->logger

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

381

dc = stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

386

if (dc->debug.allow_sw_cursor_fallback && dc->res_pool->funcs->get_max_hw_cursor_size) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

387

max_cursor_size = dc->res_pool->funcs->get_max_hw_cursor_size(dc, state, stream);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

410

if (dc_stream_check_cursor_attributes(stream, stream->ctx->dc->current_state, attributes)) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

422

struct dc *dc;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

428

dc = stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

431

dc_z10_restore(dc);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

433

if (dc->idle_optimizations_allowed) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

434

dc_allow_idle_optimizations(dc, false);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

438

program_cursor_attributes(dc, stream);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

441

if (reset_idle_optimizations && !dc->debug.disable_dmub_reallow_idle)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

442

dc_allow_idle_optimizations(dc, true);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

451

struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

457

bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

462

res_ctx = &dc->current_state->res_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

477

if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

478

dc->hwss.begin_cursor_offload_update(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

480

dc->hwss.cursor_lock(dc, pipe_to_program, true);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

483

dc->hwss.set_cursor_position(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

484

if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

485

dc->hwss.update_cursor_offload_pipe(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

487

if (dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

492

if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

493

dc->hwss.commit_cursor_offload_update(dc, pipe_to_program);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

495

dc->hwss.cursor_lock(dc, pipe_to_program, false);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

523

struct dc *dc;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

531

dc = stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

534

dc_z10_restore(dc);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

537

if (dc->idle_optimizations_allowed &&

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

538

(!old_position->enable || dc->debug.exit_idle_opt_for_cursor_updates) &&

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

540

dc_allow_idle_optimizations(dc, false);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

544

program_cursor_position(dc, stream);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

546

if (reset_idle_optimizations && !dc->debug.disable_dmub_reallow_idle)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

547

dc_allow_idle_optimizations(dc, true);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

550

if (dc->debug.visual_confirm == VISUAL_CONFIRM_HW_CURSOR) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

554

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

555

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

563

dc->hwss.update_visual_confirm_color(dc, pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

573

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

574

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

592

bool dc_stream_add_writeback(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

615

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

619

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

638

if (dc->hwss.enable_writeback) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

64

if (stream->ctx->dc->caps.dual_link_dvi &&

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

640

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

645

if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

651

if (dc->hwss.enable_writeback) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

652

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

656

dc->hwss.update_writeback(dc, wb_info, dc->current_state);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

659

dc->hwss.enable_writeback(dc, wb_info, dc->current_state);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

666

bool dc_stream_fc_disable_writeback(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

670

struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

687

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

703

bool dc_stream_remove_writeback(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

741

if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

746

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

749

if (dc->hwss.disable_writeback) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

750

struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

753

dc->hwss.disable_writeback(dc, dwb_pipe_inst);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

762

struct dc *dc = stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

764

&dc->current_state->res_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

766

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

785

struct dc *dc;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

793

dc = stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

794

res_ctx = &dc->current_state->res_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

796

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

804

if (dc->hwss.send_immediate_sdp_message != NULL)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

805

dc->hwss.send_immediate_sdp_message(pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

825

struct dc *dc;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

831

dc = stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

832

res_ctx = &dc->current_state->res_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

834

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

855

bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

860

if (!dc->hwss.dmdata_status_done)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

864

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

872

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

874

return dc->hwss.dmdata_status_done(pipe);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

877

bool dc_stream_set_dynamic_metadata(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

890

if (!dc->hwss.program_dmdata_engine)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

894

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

908

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

910

dc->hwss.program_dmdata_engine(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

920

enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

924

if (dc->res_pool->funcs->add_dsc_to_stream_resource) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

925

return dc->res_pool->funcs->add_dsc_to_stream_resource(dc, state, stream);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

936

struct pipe_ctx *pipe = &stream->ctx->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

945

void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

999

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

117

struct dc *dc;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

122

!plane_state->ctx->dc) {

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

128

dc = plane_state->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

130

if (dc->current_state == NULL)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

134

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

136

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

150

dc_exit_ips_for_hw_access(dc);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

152

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

154

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

160

dc->hwss.update_pending_status(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

288

struct dc *dc;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

294

dc = plane_state->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

296

if (!dc || !dc->current_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

299

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

300

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

305

if (dc->hwss.clear_surface_dcc_and_tiling)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

306

dc->hwss.clear_surface_dcc_and_tiling(pipe_ctx, plane_state, clear_tiling);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

74

for (i = 0; i < plane_state->ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

87

struct dc_plane_state *dc_create_plane_state(const struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

96

dc_plane_construct(dc->ctx, plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c

37

unsigned int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config)

drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c

42

if (dc->hwss.init_sys_ctx) {

drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c

43

num_vmids = dc->hwss.init_sys_ctx(dc->hwseq, dc, pa_config);

drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c

48

memcpy(&dc->vm_pa_config, pa_config, sizeof(struct dc_phy_addr_space_config));

drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c

49

dc->vm_pa_config.valid = true;

drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c

50

dc->dml2_options.gpuvm_enable = true;

drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c

51

dc_z10_save_init(dc);

drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c

57

void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid)

drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c

59

dc->hwss.init_vm_ctx(dc->hwseq, dc, va_config, vmid);

drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c

62

int dc_get_vmid_use_vector(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c

68

in_use |= dc->vm_helper->hubp_vmid_usage[i].vmid_usage[0]

drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c

69

| dc->vm_helper->hubp_vmid_usage[i].vmid_usage[1];

drivers/gpu/drm/amd/display/dc/dc.h

1359

struct dc *dc_create(const struct dc_init_data *init_params);

drivers/gpu/drm/amd/display/dc/dc.h

1360

void dc_hardware_init(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc.h

1362

int dc_get_vmid_use_vector(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc.h

1363

void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);

drivers/gpu/drm/amd/display/dc/dc.h

1365

unsigned int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);

drivers/gpu/drm/amd/display/dc/dc.h

1366

void dc_init_callbacks(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

1368

void dc_deinit_callbacks(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc.h

1369

void dc_destroy(struct dc **dc);

drivers/gpu/drm/amd/display/dc/dc.h

1770

const struct dc *dc;

drivers/gpu/drm/amd/display/dc/dc.h

2040

struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc.h

2049

void dc_get_default_tiling_info(const struct dc *dc, struct dc_tiling_info *tiling_info);

drivers/gpu/drm/amd/display/dc/dc.h

2071

bool dc_validate_boot_timing(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2075

enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/dc.h

2077

enum dc_status dc_validate_with_context(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2087

struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2092

struct dc *dc, bool acquire,

drivers/gpu/drm/amd/display/dc/dc.h

2097

bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc.h

2114

enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params);

drivers/gpu/drm/amd/display/dc/dc.h

2117

struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2122

uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);

drivers/gpu/drm/amd/display/dc/dc.h

2123

bool dc_set_fva_vrr_adjust(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2128

int dc_get_hw_max_fva_factor(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2132

void dc_set_vstartup_start(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2150

struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index);

drivers/gpu/drm/amd/display/dc/dc.h

2153

bool dc_get_edp_link_panel_inst(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2158

void dc_get_edp_links(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2162

void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link,

drivers/gpu/drm/amd/display/dc/dc.h

2263

struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2273

struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2287

dc_get_oem_i2c_device(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc.h

2290

struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2413

void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map);

drivers/gpu/drm/amd/display/dc/dc.h

2430

void dc_restore_link_res_map(const struct dc *dc, uint32_t *map);

drivers/gpu/drm/amd/display/dc/dc.h

2440

uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw);

drivers/gpu/drm/amd/display/dc/dc.h

2511

void dc_link_set_drive_settings(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2542

void dc_link_set_preferred_link_settings(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2551

void dc_link_set_preferred_frl_link_settings(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2568

void dc_link_set_preferred_training_settings(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2777

enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *new_ctx);

drivers/gpu/drm/amd/display/dc/dc.h

2881

struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2884

bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);

drivers/gpu/drm/amd/display/dc/dc.h

2885

void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);

drivers/gpu/drm/amd/display/dc/dc.h

2886

bool dc_get_flip_pending_on_otg(struct dc *dc, int otg_inst);

drivers/gpu/drm/amd/display/dc/dc.h

2888

struct dc *dc, uint32_t link_index);

drivers/gpu/drm/amd/display/dc/dc.h

2890

void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable);

drivers/gpu/drm/amd/display/dc/dc.h

2895

struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2897

void dc_resume(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc.h

2899

void dc_power_down_on_boot(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc.h

2908

bool dc_is_dmcu_initialized(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc.h

2910

enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);

drivers/gpu/drm/amd/display/dc/dc.h

2911

void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);

drivers/gpu/drm/amd/display/dc/dc.h

2913

bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2919

#define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __func__)

drivers/gpu/drm/amd/display/dc/dc.h

2920

#define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__)

drivers/gpu/drm/amd/display/dc/dc.h

2922

void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name);

drivers/gpu/drm/amd/display/dc/dc.h

2923

void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name);

drivers/gpu/drm/amd/display/dc/dc.h

2924

bool dc_dmub_is_ips_idle_state(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc.h

2927

void dc_unlock_memory_clock_frequency(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc.h

2930

void dc_lock_memory_clock_frequency(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc.h

2933

void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);

drivers/gpu/drm/amd/display/dc/dc.h

2936

void dc_hardware_release(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc.h

2939

void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc.h

2941

bool dc_set_psr_allow_active(struct dc *dc, bool enable);

drivers/gpu/drm/amd/display/dc/dc.h

2943

bool dc_set_replay_allow_active(struct dc *dc, bool active);

drivers/gpu/drm/amd/display/dc/dc.h

2945

bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips);

drivers/gpu/drm/amd/display/dc/dc.h

2947

void dc_z10_restore(const struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc.h

2948

void dc_z10_save_init(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc.h

2950

bool dc_is_dmub_outbox_supported(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc.h

2951

bool dc_enable_dmub_notifications(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc.h

2954

struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2958

void dc_enable_dmub_outbox(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc.h

2960

bool dc_process_dmub_aux_transfer_async(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2972

uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2975

bool dc_process_dmub_set_config_async(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2980

enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2985

void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps);

drivers/gpu/drm/amd/display/dc/dc.h

2987

void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2990

void dc_print_dmub_diagnostic_data(const struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc.h

2992

void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties);

drivers/gpu/drm/amd/display/dc/dc.h

3004

void dc_log_preos_dmcub_info(const struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc.h

3010

struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

3015

void dc_disable_accelerated_mode(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc.h

3020

bool dc_is_cursor_limit_pending(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc.h

3021

bool dc_can_clear_cursor_limit(const struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc.h

3034

void dc_get_underflow_debug_data_for_otg(struct dc *dc, unsigned int primary_otg_inst, struct dc_underflow_debug_data *out_data);

drivers/gpu/drm/amd/display/dc/dc.h

3036

void dc_get_power_feature_status(struct dc *dc, unsigned int primary_otg_inst, struct power_features *out_data);

drivers/gpu/drm/amd/display/dc/dc.h

3531

bool dc_capture_register_software_state(struct dc *dc, struct dc_register_software_state *state);

drivers/gpu/drm/amd/display/dc/dc.h

3555

bool dc_get_qos_info(struct dc *dc, struct dc_qos_info *info);

drivers/gpu/drm/amd/display/dc/dc.h

3567

struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

540

struct dc;

drivers/gpu/drm/amd/display/dc/dc.h

545

bool (*get_dcc_compression_cap)(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

548

bool (*get_subvp_en)(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dc.h

817

unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \

drivers/gpu/drm/amd/display/dc/dc.h

818

dm_get_timestamp(dc->ctx) : 0

drivers/gpu/drm/amd/display/dc/dc.h

821

if (dc->debug.bw_val_profile.enable) \

drivers/gpu/drm/amd/display/dc/dc.h

822

dc->debug.bw_val_profile.total_count++

drivers/gpu/drm/amd/display/dc/dc.h

825

if (dc->debug.bw_val_profile.enable) { \

drivers/gpu/drm/amd/display/dc/dc.h

827

voltage_level_tick = dm_get_timestamp(dc->ctx); \

drivers/gpu/drm/amd/display/dc/dc.h

828

dc->debug.bw_val_profile.skip_ ## status ## _count++; \

drivers/gpu/drm/amd/display/dc/dc.h

832

if (dc->debug.bw_val_profile.enable) \

drivers/gpu/drm/amd/display/dc/dc.h

833

voltage_level_tick = dm_get_timestamp(dc->ctx)

drivers/gpu/drm/amd/display/dc/dc.h

836

if (dc->debug.bw_val_profile.enable) \

drivers/gpu/drm/amd/display/dc/dc.h

837

watermark_tick = dm_get_timestamp(dc->ctx)

drivers/gpu/drm/amd/display/dc/dc.h

840

if (dc->debug.bw_val_profile.enable) { \

drivers/gpu/drm/amd/display/dc/dc.h

841

end_tick = dm_get_timestamp(dc->ctx); \

drivers/gpu/drm/amd/display/dc/dc.h

842

dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \

drivers/gpu/drm/amd/display/dc/dc.h

843

dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \

drivers/gpu/drm/amd/display/dc/dc.h

845

dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \

drivers/gpu/drm/amd/display/dc/dc.h

846

dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1045

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1049

if (dc->config.frame_update_cmd_version2 == true) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1053

if (!dc_get_edp_link_panel_inst(hubp->ctx->dc,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1171

void dc_dmub_srv_enable_dpia_trace(const struct dc *dc)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1173

struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1183

if (!dc_wake_and_execute_gpint(dc->ctx, DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1189

if (!dc_wake_and_execute_gpint(dc->ctx, DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1203

void dc_dmub_srv_cursor_offload_init(struct dc *dc)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1206

struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1209

if (!dc->config.enable_cursor_offload)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1233

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1238

void dc_dmub_srv_control_cursor_offload(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1245

if (!dc_dmub_srv_is_cursor_offload_enabled(dc))

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1271

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1275

void dc_dmub_srv_program_cursor_now(struct dc *dc, const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1280

if (!dc_dmub_srv_is_cursor_offload_enabled(dc))

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1294

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1305

if (dc_dmub_srv->ctx->dc->debug.dmcub_emulation)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1311

if (dc_dmub_srv->ctx->dc->debug.disable_timeout) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1328

static int count_active_streams(const struct dc *dc)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1332

for (i = 0; i < dc->current_state->stream_count; ++i) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1333

struct dc_stream_state *stream = dc->current_state->streams[i];

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1335

if (stream && (!stream->dpms_off || dc->config.disable_ips_in_dpms_off))

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1342

static void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1348

if (dc->debug.dmcub_emulation)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1351

if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1354

dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1366

if (dc->work_arounds.skip_psr_ips_crtc_disable)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1380

dc_dmub_srv_wait_for_idle(dc->ctx->dmub_srv, DM_DMUB_WAIT_TYPE_WAIT, NULL);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1386

if (dc->config.disable_ips == DMUB_IPS_ENABLE ||

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1387

dc->config.disable_ips == DMUB_IPS_DISABLE_DYNAMIC) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1394

} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS1) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1396

} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1400

} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2_Z10) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1405

} else if (dc->config.disable_ips == DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1407

if (count_active_streams(dc) == 0) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1422

} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_Z8_RETENTION) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1429

if (dc->config.disable_ips_rcg == DMUB_IPS_RCG_ENABLE) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1432

} else if (dc->config.disable_ips_rcg == DMUB_IPS0_RCG_DISABLE) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1434

} else if (dc->config.disable_ips_rcg == DMUB_IPS1_RCG_DISABLE) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1438

if (dc->config.disable_ips_in_vpb == DMUB_IPS_VPB_ENABLE_IPS1_AND_RCG) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1440

} else if (dc->config.disable_ips_in_vpb == DMUB_IPS_VPB_ENABLE_ALL) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1457

dm_execute_dmub_cmd(dc->ctx, &cmd, allow_idle ? DM_DMUB_WAIT_TYPE_NO_WAIT : DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1464

static void dc_dmub_srv_exit_low_power_state(const struct dc *dc)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1469

if (dc->debug.dmcub_emulation)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1472

if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1475

dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1477

if (dc->clk_mgr->funcs->exit_low_power_state) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1510

if (!dc->caps.ips_v2_support && ((prev_driver_signals.bits.allow_ips2 || prev_driver_signals.all == 0) &&

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1511

(!dc->debug.optimize_ips_handshake ||

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1518

if (!dc->debug.optimize_ips_handshake || !ips_fw->signals.bits.ips2_commit)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1519

udelay(dc->debug.ips2_eval_delay_us);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1527

dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1537

udelay(dc->debug.ips2_entry_delay_us);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1544

dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1559

if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1567

dmub_srv_sync_inboxes(dc->ctx->dmub_srv->dmub);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1571

dc_dmub_srv_notify_idle(dc, false);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1590

if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1658

dc_dmub_srv_apply_idle_power_optimizations(dc_dmub_srv->ctx->dc, false);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

166

} while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1666

!dc_dmub_srv->ctx->dc->debug.disable_dmub_reallow_idle)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1667

dc_dmub_srv_apply_idle_power_optimizations(dc_dmub_srv->ctx->dc, true);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1672

void dc_dmub_srv_apply_idle_power_optimizations(const struct dc *dc, bool allow_idle)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1674

struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1679

allow_idle &= (!dc->debug.ips_disallow_entry);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1696

dc_dmub_srv_exit_low_power_state(dc);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1718

dc_dmub_srv_notify_idle(dc, allow_idle);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1741

dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, false);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1755

!ctx->dc->debug.disable_dmub_reallow_idle)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1756

dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, true);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1798

dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, false);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1805

!ctx->dc->debug.disable_dmub_reallow_idle)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1806

dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, true);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1811

static void dc_dmub_srv_rb_based_fams2_update_config(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1832

global_cmd->config.global.features.bits.enable_stall_recovery = dc->debug.fams2_config.bits.enable_stall_recovery;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1833

global_cmd->config.global.features.bits.enable_debug = dc->debug.fams2_config.bits.enable_debug;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1834

global_cmd->config.global.features.bits.enable_offload_flip = dc->debug.fams2_config.bits.enable_offload_flip;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1864

global_cmd->config.global.features.bits.enable_visual_confirm = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS2;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1866

global_cmd->config.global.features.bits.enable_ppt_check = dc->debug.fams2_config.bits.enable_ppt_check;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1875

dm_execute_dmub_cmd_list(dc->ctx, num_cmds, cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1878

static void dc_dmub_srv_ib_based_fams2_update_config(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1882

struct dmub_fams2_config_v2 *config = (struct dmub_fams2_config_v2 *)dc->ctx->dmub_srv->dmub->ib_mem_gart.cpu_addr;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1892

cmd.ib_fams2_config.ib_data.src.quad_part = dc->ctx->dmub_srv->dmub->ib_mem_gart.gpu_addr;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1901

config->global.features.bits.enable_stall_recovery = dc->debug.fams2_config.bits.enable_stall_recovery;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1902

config->global.features.bits.enable_offload_flip = dc->debug.fams2_config.bits.enable_offload_flip;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1903

config->global.features.bits.enable_debug = dc->debug.fams2_config.bits.enable_debug;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1919

config->global.features.bits.enable_visual_confirm = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS2;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1921

config->global.features.bits.enable_ppt_check = dc->debug.fams2_config.bits.enable_ppt_check;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1923

dm_execute_dmub_cmd_list(dc->ctx, 1, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1926

void dc_dmub_srv_fams2_update_config(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1930

if (dc->debug.fams_version.major == 2)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1931

dc_dmub_srv_rb_based_fams2_update_config(dc, context, enable);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1932

if (dc->debug.fams_version.major == 3)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1933

dc_dmub_srv_ib_based_fams2_update_config(dc, context, enable);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1936

void dc_dmub_srv_fams2_drr_update(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1958

dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1962

struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2057

dm_execute_dmub_cmd_list(dc->ctx, num_cmds, cmds, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

221

} while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2361

bool dc_dmub_srv_is_cursor_offload_enabled(const struct dc *dc)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2363

return dc->ctx->dmub_srv && dc->ctx->dmub_srv->cursor_offload_enabled;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2366

void dc_dmub_srv_boot_time_crc_init(const struct dc *dc, uint64_t gpu_addr, uint32_t size)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2373

if (!dc || !dc->ctx || !dc->ctx->dmub_srv || size == 0)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2376

dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2387

result = dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2393

void dc_dmub_srv_release_hw(const struct dc *dc)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2395

struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2408

dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

284

} while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

374

bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

376

struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

380

void dc_dmub_trace_event_control(struct dc *dc, bool enable)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

382

dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

385

void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

398

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

401

void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

412

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

415

static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

421

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

429

static void dc_dmub_srv_populate_fams_pipe_info(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

437

for (j = 0; j < dc->res_pool->pipe_count; j++) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

447

bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

457

if (dc == NULL)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

46

static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

460

visual_confirm_enabled = (uint8_t)(dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

469

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

482

(uint16_t)dc->debug.fpo_vactive_margin_us;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

488

for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

50

dc_srv->ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

503

config_data->pipe_data[k].pipes = dc_dmub_srv_get_pipes_for_stream(dc, pipe->stream);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

504

dc_dmub_srv_populate_fams_pipe_info(dc, context, pipe, &config_data->pipe_data[k]);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

512

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

521

if (dc_dmub_srv->ctx->dc->debug.dmcub_emulation)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

541

void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

546

if (!dc_get_edp_link_panel_inst(dc, pipe_ctx->stream->link, &panel_inst) &&

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

547

dc->debug.visual_confirm == VISUAL_CONFIRM_DISABLE)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

56

if (dc_dmub_srv->ctx->dc->debug.enable_dmu_recovery)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

560

if (dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

562

memcpy(&dc->ctx->dmub_srv->dmub->visual_confirm_color,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

585

static void populate_subvp_cmd_drr_info(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

60

struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

626

(((uint64_t)phantom_timing->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

632

dc->caps.subvp_fw_processing_delay_us - drr_active_us), 2) + drr_active_us;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

633

max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us - dc->caps.subvp_fw_processing_delay_us;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

643

max_vtotal_supported = max_vtotal_supported - dc->caps.subvp_drr_max_vblank_margin_us;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

648

(uint16_t)dc->caps.subvp_drr_vblank_start_margin_us;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

665

static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

677

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

70

dc_dmub_srv_construct(dc_srv, dc, dmub);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

705

populate_subvp_cmd_drr_info(dc, context, pipe, vblank_pipe, pipe_data);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

722

static void update_subvp_prefetch_end_to_mall_start(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

749

(((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

752

(((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

760

(uint16_t)div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

768

(uint16_t)div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

787

static void populate_subvp_cmd_pipe_info(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

839

(uint16_t)div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

842

(uint16_t)div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

854

for (j = 0; j < dc->res_pool->pipe_count; j++) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

882

void dc_dmub_setup_subvp_dmub_command(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

901

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

914

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

928

populate_subvp_cmd_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

934

populate_subvp_cmd_vblank_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

939

update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

941

cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = (uint8_t)dc->caps.subvp_pstate_allow_width_us;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

942

cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = (uint8_t)dc->caps.subvp_vertical_int_margin_us;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

947

(dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

952

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

97

} while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

100

void dc_dmub_setup_subvp_dmub_command(struct dc *dc, struct dc_state *context, bool enable);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

106

void dc_dmub_srv_enable_dpia_trace(const struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

111

void dc_dmub_srv_apply_idle_power_optimizations(const struct dc *dc, bool allow_idle);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

197

void dc_dmub_srv_fams2_update_config(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

200

void dc_dmub_srv_fams2_drr_update(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

208

struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

33

struct dc;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

335

void dc_dmub_srv_cursor_offload_init(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

345

void dc_dmub_srv_control_cursor_offload(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

354

void dc_dmub_srv_program_cursor_now(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

363

bool dc_dmub_srv_is_cursor_offload_enabled(const struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

372

void dc_dmub_srv_boot_time_crc_init(const struct dc *dc, uint64_t gpu_addr, uint32_t size);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

379

void dc_dmub_srv_release_hw(const struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

83

bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

85

void dc_dmub_trace_event_control(struct dc *dc, bool enable);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

87

void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

89

void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

90

bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool enable_pstate, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

93

void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/dc_dsc.h

127

void dc_dsc_get_default_config_option(const struct dc *dc, struct dc_dsc_config_options *options);

drivers/gpu/drm/amd/display/dc/dc_dsc.h

70

bool dc_dsc_parse_dsc_dpcd(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_dsc.h

75

bool dc_dsc_parse_dsc_edid(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

29

bool dc_edid_parser_send_cea(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

35

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

50

bool dc_edid_parser_recv_cea_ack(struct dc *dc, int *offset)

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

52

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

63

bool dc_edid_parser_recv_amd_vsdb(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

68

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/dc_edid_parser.h

31

bool dc_edid_parser_send_cea(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_edid_parser.h

37

bool dc_edid_parser_recv_cea_ack(struct dc *dc, int *offset);

drivers/gpu/drm/amd/display/dc/dc_edid_parser.h

39

bool dc_edid_parser_recv_amd_vsdb(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_helper.c

634

if (ctx->dmub_srv && ctx->dc->debug.dmub_offload_enabled) {

drivers/gpu/drm/amd/display/dc/dc_helper.c

684

ctx->dc->debug.dmub_offload_enabled &&

drivers/gpu/drm/amd/display/dc/dc_helper.c

685

!ctx->dc->debug.dmcub_emulation) {

drivers/gpu/drm/amd/display/dc/dc_plane.h

39

struct dc_plane_state *dc_create_plane_state(const struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

139

pipe_ctx->stream->ctx->dc->debug.max_downscale_src_width;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

140

spl_in->basic_out.always_scale = pipe_ctx->stream->ctx->dc->debug.always_scale;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

147

spl_in->prefer_easf = pipe_ctx->stream->ctx->dc->config.prefer_easf;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

149

if (pipe_ctx->stream->ctx->dc->debug.force_easf == 1)

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

151

else if (pipe_ctx->stream->ctx->dc->debug.force_easf == 2)

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

153

else if (pipe_ctx->stream->ctx->dc->debug.force_easf == 3)

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

156

unsigned int sharpness_setting = pipe_ctx->stream->ctx->dc->debug.force_sharpness;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

157

unsigned int force_sharpness_level = pipe_ctx->stream->ctx->dc->debug.force_sharpness_level;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

189

if (pipe_ctx->stream->ctx->dc->debug.force_lls > 0)

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

190

spl_in->lls_pref = pipe_ctx->stream->ctx->dc->debug.force_lls;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

194

if (pipe_ctx->stream->ctx->dc->debug.force_cositing)

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

195

spl_in->basic_in.cositing = pipe_ctx->stream->ctx->dc->debug.force_cositing - 1;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

207

(enum scale_to_sharpness_policy)pipe_ctx->stream->ctx->dc->debug.scale_to_sharpness_policy;

drivers/gpu/drm/amd/display/dc/dc_stat.h

40

void dc_stat_get_dmub_notification(const struct dc *dc, struct dmub_notification *notify);

drivers/gpu/drm/amd/display/dc/dc_stat.h

41

void dc_stat_get_dmub_dataout(const struct dc *dc, uint32_t *dataout);

drivers/gpu/drm/amd/display/dc/dc_state.h

31

struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *params);

drivers/gpu/drm/amd/display/dc/dc_state.h

34

void dc_state_copy_current(struct dc *dc, struct dc_state *dst_state);

drivers/gpu/drm/amd/display/dc/dc_state.h

35

struct dc_state *dc_state_create_current_copy(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc_state.h

36

void dc_state_construct(struct dc *dc, struct dc_state *state);

drivers/gpu/drm/amd/display/dc/dc_state.h

41

enum dc_status dc_state_add_stream(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_state.h

46

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_state.h

51

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_state.h

57

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_state.h

63

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_state.h

68

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

101

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

105

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

47

struct dc_stream_state *dc_state_create_phantom_stream(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

50

struct dc_plane_state *dc_state_create_phantom_plane(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

55

void dc_state_release_phantom_stream(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

58

void dc_state_release_phantom_plane(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

63

enum dc_status dc_state_add_phantom_stream(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

67

enum dc_status dc_state_remove_phantom_stream(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

72

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

78

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

84

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

90

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

97

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_stream.h

377

bool dc_update_planes_and_stream(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_stream.h

387

struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_stream.h

419

void dc_commit_updates_for_stream(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_stream.h

428

void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/dc_stream.h

430

uint8_t dc_get_current_stream_count(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc_stream.h

431

struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);

drivers/gpu/drm/amd/display/dc/dc_stream.h

455

bool dc_stream_add_writeback(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_stream.h

459

bool dc_stream_fc_disable_writeback(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_stream.h

463

bool dc_stream_remove_writeback(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_stream.h

467

enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_stream.h

471

bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/dc_stream.h

473

bool dc_stream_set_dynamic_metadata(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_stream.h

477

enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/dc_stream.h

484

struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_stream.h

490

void dc_trigger_sync(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dc_stream.h

522

struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_stream.h

526

struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_stream.h

551

bool dc_stream_adjust_vmin_vmax(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_stream.h

555

bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_stream.h

571

bool dc_stream_configure_crc(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_stream.h

580

bool dc_stream_get_crc(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_stream.h

587

void dc_stream_set_static_screen_params(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_stream.h

592

void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,

drivers/gpu/drm/amd/display/dc/dc_stream.h

598

bool dc_stream_set_gamut_remap(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_stream.h

601

bool dc_stream_program_csc_matrix(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_stream.h

605

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_stream.h

610

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_stream.h

613

void dc_stream_init_rmcm_3dlut(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc_stream.h

617

void dc_dmub_update_dirty_rect(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc_stream.h

623

bool dc_stream_is_cursor_limit_pending(struct dc *dc, struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/dc_stream.h

624

bool dc_stream_can_clear_cursor_limit(struct dc *dc, struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/dc_trace.h

28

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[index]; \

drivers/gpu/drm/amd/display/dc/dc_types.h

857

struct dc *dc;

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

124

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

134

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

187

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

196

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

205

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

214

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

240

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

249

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

258

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

267

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

336

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

360

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

404

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

459

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

466

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

476

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

483

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

493

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

500

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

510

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

517

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

527

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

534

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

690

if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmistream)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

701

if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar) {

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

740

if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar) {

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

762

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

769

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) {

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

778

if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar)

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

322

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

326

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

331

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1315

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && !disallow_rcg)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

142

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc && allow_rcg)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1589

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1595

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1601

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1607

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1624

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1630

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1636

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1642

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1683

if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmistream)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1694

if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1746

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

175

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1909

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1920

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1931

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1942

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1960

if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmistream) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1974

if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1998

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2011

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2021

if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2093

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2101

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2109

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2117

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2136

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

214

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2142

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2148

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2154

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2160

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2170

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2177

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2184

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2191

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2198

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

241

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

278

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

327

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

372

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

398

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && allow_rcg)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

431

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

468

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

505

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.hdmistream && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

527

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

284

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

291

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

301

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

308

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

318

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

325

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

335

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

342

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

406

if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar) {

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

434

if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar) {

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

460

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

469

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

478

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

487

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

513

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

522

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

531

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

540

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

558

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

567

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

576

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

585

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

607

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

615

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

623

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

631

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

770

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) {

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

777

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

784

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) {

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

792

if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

877

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

884

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

891

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

898

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

111

dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

127

dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

143

dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

159

dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

175

dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

194

dccg->ctx->dc->debug.root_clock_optimization.bits.hdmistream ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

207

HDMICHARCLK0_ROOT_GATE_DISABLE, dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

278

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) {

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

285

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

291

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) {

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

300

if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar)

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

84

if (dccg->ctx->dc->debug.disable_clock_gate)

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

463

struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc->link->aux_hw_inst];

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

532

if (ddc->ctx->dc->config.dp_connector_no_native_i2c && ddc->link->no_ddc_pin)

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

535

struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

655

if (ddc->ctx->dc->config.dp_connector_no_native_i2c && ddc->link->no_ddc_pin) {

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

657

if (ddc->ctx->dc->debug.enable_dmub_aux_for_legacy_ddc) {

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

663

if (ddc->ctx->dc->debug.enable_dmub_aux_for_legacy_ddc ||

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

690

aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

742

aux_engine = ddc->ctx->dc->res_pool->engines[ddc->link->aux_hw_inst];

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

789

struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

798

if (ddc->ctx->dc->config.dp_connector_no_native_i2c && ddc->link->no_ddc_pin) {

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

799

struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc->link->aux_hw_inst];

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

892

aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

896

if (ddc->ctx->dc->config.dp_connector_no_native_i2c && ddc->link->no_ddc_pin) {

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

897

aux_engine = ddc->ctx->dc->res_pool->engines[ddc->link->aux_hw_inst];

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1094

dtbclk_p_src_clk_khz = clock_source->ctx->dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(clock_source->ctx->dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1097

dtbclk_p_src_clk_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1114

clock_source->ctx->dc->res_pool->dccg->funcs->set_dp_dto(

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1115

clock_source->ctx->dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1117

if (clock_source->ctx->dc->caps.is_apu &&

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1121

clock_source->ctx->dc->res_pool->dccg->funcs->set_hdmistreamclk(

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1122

clock_source->ctx->dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1131

clock_source->ctx->dc->res_pool->dccg->funcs->set_dp_dto(

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1132

clock_source->ctx->dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1218

unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1224

if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization &&

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1225

clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) {

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1363

if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization &&

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1364

clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) {

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1370

clock_source->ctx->dc->clk_mgr->dprefclk_khz*1000);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1406

unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

970

unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

977

if (clock_source->ctx->dc->clk_mgr->dp_dto_source_clock_in_khz != 0 &&

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

980

dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dp_dto_source_clock_in_khz;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

383

const struct dc_config *config = &dmcu->ctx->dc->config;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

399

for (i = 0; i < ctx->dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

400

if (ctx->dc->links[i]->link_enc->features.flags.bits.DP_IS_USB_C) {

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

401

if (ctx->dc->links[i]->link_enc->transmitter >= TRANSMITTER_UNIPHY_A &&

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

402

ctx->dc->links[i]->link_enc->transmitter <= TRANSMITTER_UNIPHY_F) {

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

403

tx_interrupt_mask |= 1 << ctx->dc->links[i]->link_enc->transmitter;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c

35

struct dc *dc = ddc->ctx->dc;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c

36

struct dc_bios *dcb = dc->ctx->dc_bios;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c

40

if (!dc->ctx->dc_bios->fw_info.oem_i2c_present)

drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c

43

id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

328

if (dce_i2c_hw->ctx->dc->debug.enable_mem_low_power.bits.i2c) {

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

343

set_speed(dce_i2c_hw, dce_i2c_hw->ctx->dc->caps.i2c_speed_in_khz);

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

432

set_speed(dce_i2c_hw, dce_i2c_hw->ctx->dc->caps.i2c_speed_in_khz_hdcp);

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

437

if (dce_i2c_hw->ctx->dc->debug.enable_mem_low_power.bits.i2c) {

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

756

if (ctx->dc->debug.scl_reset_length10)

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

1006

if (enc110->base.ctx->dc->debug.hdmi20_disable) {

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

2040

if (enc110->base.ctx->dc->debug.hdmi20_disable) {

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

347

if (ctx->dc->caps.psp_setup_panel_mode)

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

838

enc110->base.ctx->dc->debug.hdmi20_disable) &&

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

841

if (enc110->base.ctx->dc->debug.hdmi20_disable &&

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

322

uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

349

uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

376

uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

409

uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

196

if (xfm_dce->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {

drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c

143

struct dc_context *dc = abm->ctx;

drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c

148

ret = dmub_abm_save_restore(dc, panel_inst, pData);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c

224

if (ctx->dc->caps.dmcub_support) {

drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c

42

struct dc_context *dc = abm->ctx;

drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c

47

dc_get_edp_links(dc->dc, edp_links, &edp_num);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c

68

dc_allow_idle_optimizations(abm->ctx->dc, false);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c

75

dc_allow_idle_optimizations(abm->ctx->dc, false);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

144

struct dc_context *dc = abm->ctx;

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

154

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

165

struct dc_context *dc = abm->ctx;

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

169

dmub_flush_buffer_mem(&dc->dmub_srv->dmub->scratch_mem_fb);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

172

memcpy(dc->dmub_srv->dmub->scratch_mem_fb.cpu_addr, (void *)src, bytes);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

178

cmd.abm_init_config.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_addr;

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

185

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

193

struct dc_context *dc = abm->ctx;

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

203

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

221

struct dc_context *dc,

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

230

dmub_flush_buffer_mem(&dc->dmub_srv->dmub->scratch_mem_fb);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

233

memcpy(dc->dmub_srv->dmub->scratch_mem_fb.cpu_addr, (void *)pData, bytes);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

239

cmd.abm_save_restore.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_addr;

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

247

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

250

memcpy((void *)pData, dc->dmub_srv->dmub->scratch_mem_fb.cpu_addr, bytes);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

262

struct dc_context *dc = abm->ctx;

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

275

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

286

struct dc_context *dc = abm->ctx;

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

297

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

306

struct dc_context *dc = abm->ctx;

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

316

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

56

static void dmub_abm_enable_fractional_pwm(struct dc_context *dc)

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

59

uint32_t fractional_pwm = (dc->dc->config.disable_fractional_pwm == false) ? 1 : 0;

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

60

uint32_t edp_id_count = dc->dc_edp_id_count;

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

75

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.h

44

struct dc_context *dc,

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

101

if (dmub_hw_lock_mgr_does_link_require_lock(dc, link))

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

107

bool should_use_dmub_inbox1_lock(const struct dc *dc, const struct dc_link *link)

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

110

if (!dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

113

if (dc->ctx->dce_version >= DCN_VERSION_4_01)

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

116

if (dmub_hw_lock_has_inbox0_lock(dc))

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

119

return dmub_hw_lock_mgr_does_link_require_lock(dc, link);

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

122

bool should_use_dmub_inbox0_lock_for_link(const struct dc *dc, const struct dc_link *link)

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

124

return dmub_hw_lock_has_inbox0_lock(dc) && dmub_hw_lock_mgr_does_link_require_lock(dc, link);

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

31

static bool dmub_hw_lock_has_inbox0_lock(const struct dc *dc)

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

33

return dc->ctx && dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

34

dc->hwss.dmub_hw_control_lock &&

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

35

dc->hwss.dmub_hw_control_lock_fast &&

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

36

dc->ctx->dmub_srv->dmub->meta_info.feature_bits.bits.inbox0_lock_support;

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

72

bool dmub_hw_lock_mgr_does_link_require_lock(const struct dc *dc, const struct dc_link *link)

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

87

dc_get_edp_links(dc, edp_links, &edp_num);

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

94

bool dmub_hw_lock_mgr_does_context_require_lock(const struct dc *dc, const struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h

48

bool should_use_dmub_inbox1_lock(const struct dc *dc, const struct dc_link *link);

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h

58

bool dmub_hw_lock_mgr_does_link_require_lock(const struct dc *dc, const struct dc_link *link);

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h

68

bool dmub_hw_lock_mgr_does_context_require_lock(const struct dc *dc, const struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h

81

bool should_use_dmub_inbox0_lock_for_link(const struct dc *dc, const struct dc_link *link);

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

143

struct dc_context *dc = dmub->ctx;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

171

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

182

struct dc_context *dc = dmub->ctx;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

199

dc_wake_and_execute_dmub_cmd(dc->dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

234

struct dc_context *dc = dmub->ctx;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

248

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

258

struct dc_context *dc = dmub->ctx;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

267

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

276

struct dc_context *dc = dmub->ctx;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

286

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

298

struct dc_context *dc = dmub->ctx;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

302

struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

357

copy_settings_data->use_phy_fsm = link->ctx->dc->debug.psr_power_use_phy_fsm;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

365

copy_settings_data->debug.bitfields.visual_confirm = dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

368

copy_settings_data->debug.bitfields.enable_ips_visual_confirm = dc->dc->debug.enable_ips_visual_confirm;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

379

copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

397

!link->dc->debug.disable_fec) &&

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

400

link->dc->caps.edp_dsc_support)) &&

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

427

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

438

struct dc_context *dc = dmub->ctx;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

448

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

100

struct dc_context *dc = dmub->ctx;

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

109

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

121

struct dc_context *dc = dmub->ctx;

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

125

struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx;

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

175

copy_settings_data->debug.bitfields.enable_ips_visual_confirm = dc->dc->debug.enable_ips_visual_confirm;

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

182

!link->dc->debug.disable_fec) &&

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

185

link->dc->caps.edp_dsc_support)) &&

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

197

copy_settings_data->auxless_alpm_data.lfps_setup_ns = (uint16_t)dc->dc->debug.auxless_alpm_lfps_setup_ns;

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

198

copy_settings_data->auxless_alpm_data.lfps_period_ns = (uint16_t)dc->dc->debug.auxless_alpm_lfps_period_ns;

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

199

copy_settings_data->auxless_alpm_data.lfps_silence_ns = (uint16_t)dc->dc->debug.auxless_alpm_lfps_silence_ns;

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

201

(uint16_t)dc->dc->debug.auxless_alpm_lfps_t1t2_us;

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

203

(uint16_t)dc->dc->debug.auxless_alpm_lfps_t1t2_offset_us;

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

204

copy_settings_data->auxless_alpm_data.lttpr_count = link->dc->link_srv->dp_get_lttpr_count(link);

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

207

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

222

struct dc_context *dc = dmub->ctx;

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

235

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

293

struct dc_context *dc = dmub->ctx;

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

310

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

50

struct dc_context *dc = dmub->ctx;

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

66

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c

761

if (ctx->dc->debug.disable_stutter) {

drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c

237

if (xfm_dce->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

110

static unsigned int dcn10_get_hubp_states(struct dc *dc, char *pBuf, unsigned int bufSize, bool invarOnly)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

112

struct dc_context *dc_ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

113

struct resource_pool *pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

119

const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

189

static unsigned int dcn10_get_rq_states(struct dc *dc, char *pBuf, unsigned int bufSize)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

191

struct resource_pool *pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

231

static unsigned int dcn10_get_dlg_states(struct dc *dc, char *pBuf, unsigned int bufSize)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

233

struct resource_pool *pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

288

static unsigned int dcn10_get_ttu_states(struct dc *dc, char *pBuf, unsigned int bufSize)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

290

struct resource_pool *pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

328

static unsigned int dcn10_get_cm_states(struct dc *dc, char *pBuf, unsigned int bufSize)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

330

struct resource_pool *pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

383

static unsigned int dcn10_get_mpcc_states(struct dc *dc, char *pBuf, unsigned int bufSize)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

385

struct resource_pool *pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

414

static unsigned int dcn10_get_otg_states(struct dc *dc, char *pBuf, unsigned int bufSize)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

416

struct resource_pool *pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

435

pix_clk = dc->current_state->res_ctx.pipe_ctx[i].stream_res.pix_clk_params.requested_pix_clk_100hz / 10;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

470

static unsigned int dcn10_get_clock_states(struct dc *dc, char *pBuf, unsigned int bufSize)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

478

dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

479

dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

480

dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

481

dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

482

dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

483

dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

491

static void dcn10_clear_otpc_underflow(struct dc *dc)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

493

struct resource_pool *pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

508

static void dcn10_clear_hubp_underflow(struct dc *dc)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

510

struct resource_pool *pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

524

void dcn10_clear_status_bits(struct dc *dc, unsigned int mask)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

539

dcn10_clear_hubp_underflow(dc);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

542

dcn10_clear_otpc_underflow(dc);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

545

void dcn10_get_hw_state(struct dc *dc, char *pBuf, unsigned int bufSize, unsigned int mask)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

570

chars_printed = dcn10_get_hubbub_state(dc, pBuf, remaining_buf_size);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

576

chars_printed = dcn10_get_hubp_states(dc, pBuf, remaining_buf_size, mask & DC_HW_STATE_INVAR_ONLY);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

582

chars_printed = dcn10_get_rq_states(dc, pBuf, remaining_buf_size);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

588

chars_printed = dcn10_get_dlg_states(dc, pBuf, remaining_buf_size);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

594

chars_printed = dcn10_get_ttu_states(dc, pBuf, remaining_buf_size);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

600

chars_printed = dcn10_get_cm_states(dc, pBuf, remaining_buf_size);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

606

chars_printed = dcn10_get_mpcc_states(dc, pBuf, remaining_buf_size);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

612

chars_printed = dcn10_get_otg_states(dc, pBuf, remaining_buf_size);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

618

chars_printed = dcn10_get_clock_states(dc, pBuf, remaining_buf_size);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

72

static unsigned int dcn10_get_hubbub_state(struct dc *dc, char *pBuf, unsigned int bufSize)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

74

struct dc_context *dc_ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

81

const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

85

dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.h

31

struct dc;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.h

33

void dcn10_clear_status_bits(struct dc *dc, unsigned int mask);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.h

35

void dcn10_log_hw_state(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.h

38

void dcn10_get_hw_state(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c

208

if (enc10->base.ctx->dc->debug.hdmi20_disable) {

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

265

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

443

if (enc10->base.ctx->dc->debug.hdmi20_disable) {

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c

61

if (afmt->ctx->dc->debug.enable_mem_low_power.bits.afmt == false)

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c

71

if (afmt->ctx->dc->debug.enable_mem_low_power.bits.afmt == false)

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

101

uint32_t xtal = panel_cntl->ctx->dc->res_pool->ref_clocks.dccg_ref_clock_inKhz;

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

176

if (dcn31_panel_cntl->base.ctx->dc->config.support_edp0_on_dp1) {

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

73

uint32_t freq_to_set = panel_cntl->ctx->dc->debug.pwm_freq;

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c

56

if (vpg->ctx->dc->debug.enable_mem_low_power.bits.vpg == false)

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c

70

if (vpg->ctx->dc->debug.enable_mem_low_power.bits.vpg == false &&

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

650

enc10->base.ctx->dc->debug.hdmi20_disable) &&

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

653

if (enc10->base.ctx->dc->debug.hdmi20_disable &&

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

781

if (enc10->base.ctx->dc->debug.hdmi20_disable) {

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1029

link->dc->link_srv->dp_trace_source_sequence(link,

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

937

link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_DP_VID_STREAM);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

956

link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_FIFO_STEER_RESET);

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

254

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

502

if (enc10->base.ctx->dc->debug.hdmi20_disable) {

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

549

link->dc->link_srv->dp_trace_source_sequence(link,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c

109

if (enc10->base.ctx->dc->debug.ignore_ffe)

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c

450

if (enc10->base.ctx->dc->debug.hdmi20_disable) {

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c

453

if (enc10->base.ctx->dc->config.force_hdmi21_frl_enc_enable) {

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

539

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

586

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c

203

if (enc10->base.ctx->dc->debug.hdmi20_disable) {

drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c

206

if (enc10->base.ctx->dc->config.force_hdmi21_frl_enc_enable) {

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

292

if (enc10->base.ctx->dc->debug.ignore_ffe)

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

503

if (enc10->base.ctx->dc->debug.hdmi20_disable) {

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

506

if (enc10->base.ctx->dc->config.force_hdmi21_frl_enc_enable) {

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

575

if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) {

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

585

link = link_enc_cfg_get_link_using_link_enc(enc->ctx->dc, enc->preferred_engine);

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

602

dpia_control.fec_rdy = link->dc->link_srv->dp_should_enable_fec(link);

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

622

if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) {

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

632

link = link_enc_cfg_get_link_using_link_enc(enc->ctx->dc, enc->preferred_engine);

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

649

dpia_control.fec_rdy = link->dc->link_srv->dp_should_enable_fec(link);

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

668

if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) {

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

681

link = link_enc_cfg_get_link_using_link_enc(enc->ctx->dc, enc->preferred_engine);

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

112

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

153

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

293

if (enc->ctx->dc->debug.dig_fifo_off_in_blank)

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

384

link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

158

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

249

if (enc10->base.ctx->dc->debug.ignore_ffe)

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

545

if (enc10->base.ctx->dc->debug.hdmi20_disable) {

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

548

if (enc10->base.ctx->dc->config.force_hdmi21_frl_enc_enable) {

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

111

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

346

link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

70

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c

205

if (enc10->base.ctx->dc->debug.hdmi20_disable)

drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c

207

if (enc10->base.ctx->dc->config.force_hdmi21_frl_enc_enable) {

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

284

if (enc10->base.ctx->dc->debug.hdmi20_disable)

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

286

if (enc10->base.ctx->dc->config.force_hdmi21_frl_enc_enable) {

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

330

if (!enc->ctx->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

345

if (!enc->ctx->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

359

if (!enc->ctx->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

364

link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

58

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

98

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

128

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

166

if (enc10->base.ctx->dc->debug.ignore_ffe)

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

172

if (enc10->base.ctx->dc->debug.select_ffe)

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

174

(uint8_t)enc10->base.ctx->dc->debug.select_ffe;

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

536

if (enc10->base.ctx->dc->debug.hdmi20_disable) {

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

539

if (enc10->base.ctx->dc->config.force_hdmi21_frl_enc_enable) {

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

113

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

375

link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

72

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.c

217

if (enc10->base.ctx->dc->debug.hdmi20_disable) {

drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.c

220

if (enc10->base.ctx->dc->config.force_hdmi21_frl_enc_enable) {

drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c

43

if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {

drivers/gpu/drm/amd/display/dc/dm_services.h

127

struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1006

v->dcc_enable[input_idx] = dc->res_pool->hubbub->funcs->dcc_support_pixel_format(

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1060

hack_bounding_box(v, &dc->debug, context);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1067

&& dc->debug.force_single_disp_pipe_split) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1073

(dc->debug.sr_exit_time_dpm0_ns

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1074

|| dc->debug.sr_enter_plus_exit_time_dpm0_ns)) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1076

if (dc->debug.sr_enter_plus_exit_time_dpm0_ns)

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1078

dc->debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1079

if (dc->debug.sr_exit_time_dpm0_ns)

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1080

v->sr_exit_time = dc->debug.sr_exit_time_dpm0_ns / 1000.0f;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1138

if (dc->debug.voltage_align_fclk)

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1169

if (dc->debug.max_disp_clk == true)

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1170

context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1173

(int)dc->debug.min_disp_clk_khz) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1175

(int)dc->debug.min_disp_clk_khz;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1184

(int)(dc->dcn_soc->max_dppclk_vmin0p65 * 1000);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1188

(int)(dc->dcn_soc->max_dppclk_vmid0p72 * 1000);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1192

(int)(dc->dcn_soc->max_dppclk_vnom0p8 * 1000);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1196

(int)(dc->dcn_soc->max_dppclk_vmax0p9 * 1000);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1269

dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe, input_idx);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1285

dcn_bw_calc_rq_dlg_ttu(dc, v, pipe, input_idx);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1298

dc->dcn_soc->sr_enter_plus_exit_time;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1299

context->bw_ctx.dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1306

bw_limit = dc->dcn_soc->percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1312

if (bw_limit_pass && v->voltage_level <= (int)get_highest_allowed_voltage_level(dc->config.is_vmin_only_asic))

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1319

struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1331

dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 =

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1333

dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 =

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1334

dc->dcn_soc->number_of_channels *

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1337

dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 =

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1338

dc->dcn_soc->number_of_channels *

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1341

dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 =

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1342

dc->dcn_soc->number_of_channels *

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1348

struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1352

dc->dcn_soc->dcfclkv_min0p65 = dcfclks->data[0].clocks_in_khz / 1000.0f;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1353

dc->dcn_soc->dcfclkv_mid0p72 = dcfclks->data[dcfclks->num_levels - 3].clocks_in_khz / 1000.0f;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1354

dc->dcn_soc->dcfclkv_nom0p8 = dcfclks->data[dcfclks->num_levels - 2].clocks_in_khz / 1000.0f;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1355

dc->dcn_soc->dcfclkv_max0p9 = dcfclks->data[dcfclks->num_levels - 1].clocks_in_khz / 1000.0f;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1360

struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1365

*min_fclk_khz = (int)(dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000.0f / 32.0f);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1366

*min_dcfclk_khz = (int)(dc->dcn_soc->dcfclkv_min0p65 * 1000.0f);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1367

*socclk_khz = (int)(dc->dcn_soc->socclk * 1000.0f);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1371

struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1380

if (dc->res_pool->pp_smu)

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1381

pp = &dc->res_pool->pp_smu->rv_funcs;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1406

if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1432

void dcn_bw_sync_calcs_and_dml(struct dc *dc)

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1468

dc->dcn_soc->sr_exit_time * 1000,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1469

dc->dcn_soc->sr_enter_plus_exit_time * 1000,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1470

dc->dcn_soc->urgent_latency * 1000,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1471

dc->dcn_soc->write_back_latency * 1000,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1472

dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1473

dc->dcn_soc->max_request_size,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1474

dc->dcn_soc->dcfclkv_max0p9 * 1000,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1475

dc->dcn_soc->dcfclkv_nom0p8 * 1000,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1476

dc->dcn_soc->dcfclkv_mid0p72 * 1000,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1477

dc->dcn_soc->dcfclkv_min0p65 * 1000,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1478

dc->dcn_soc->max_dispclk_vmax0p9 * 1000,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1479

dc->dcn_soc->max_dispclk_vnom0p8 * 1000,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1480

dc->dcn_soc->max_dispclk_vmid0p72 * 1000,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1481

dc->dcn_soc->max_dispclk_vmin0p65 * 1000,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1482

dc->dcn_soc->max_dppclk_vmax0p9 * 1000,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1483

dc->dcn_soc->max_dppclk_vnom0p8 * 1000,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1484

dc->dcn_soc->max_dppclk_vmid0p72 * 1000,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1485

dc->dcn_soc->max_dppclk_vmin0p65 * 1000,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1486

dc->dcn_soc->socclk * 1000,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1487

dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 * 1000,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1488

dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 * 1000,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1489

dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 * 1000,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1490

dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1491

dc->dcn_soc->phyclkv_max0p9 * 1000,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1492

dc->dcn_soc->phyclkv_nom0p8 * 1000,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1493

dc->dcn_soc->phyclkv_mid0p72 * 1000,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1494

dc->dcn_soc->phyclkv_min0p65 * 1000,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1495

dc->dcn_soc->downspreading * 100,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1496

dc->dcn_soc->round_trip_ping_latency_cycles,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1497

dc->dcn_soc->urgent_out_of_order_return_per_channel,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1498

dc->dcn_soc->number_of_channels,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1499

dc->dcn_soc->vmm_page_size,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1500

dc->dcn_soc->dram_clock_change_latency * 1000,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1501

dc->dcn_soc->return_bus_width);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1536

dc->dcn_ip->rob_buffer_size_in_kbyte,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1537

dc->dcn_ip->det_buffer_size_in_kbyte,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1538

dc->dcn_ip->dpp_output_buffer_pixels,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1539

dc->dcn_ip->opp_output_buffer_lines,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1540

dc->dcn_ip->pixel_chunk_size_in_kbyte,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1541

dc->dcn_ip->pte_enable,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1542

dc->dcn_ip->pte_chunk_size,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1543

dc->dcn_ip->meta_chunk_size,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1544

dc->dcn_ip->writeback_chunk_size,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1545

dc->dcn_ip->odm_capability,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1546

dc->dcn_ip->dsc_capability,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1547

dc->dcn_ip->line_buffer_size,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1548

dc->dcn_ip->max_line_buffer_lines,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1549

dc->dcn_ip->is_line_buffer_bpp_fixed,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1550

dc->dcn_ip->line_buffer_fixed_bpp,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1551

dc->dcn_ip->writeback_luma_buffer_size,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1552

dc->dcn_ip->writeback_chroma_buffer_size,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1553

dc->dcn_ip->max_num_dpp,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1554

dc->dcn_ip->max_num_writeback,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1555

dc->dcn_ip->max_dchub_topscl_throughput,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1556

dc->dcn_ip->max_pscl_tolb_throughput,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1557

dc->dcn_ip->max_lb_tovscl_throughput,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1558

dc->dcn_ip->max_vscl_tohscl_throughput,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1559

dc->dcn_ip->max_hscl_ratio,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1560

dc->dcn_ip->max_vscl_ratio,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1561

dc->dcn_ip->max_hscl_taps,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1562

dc->dcn_ip->max_vscl_taps,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1563

dc->dcn_ip->pte_buffer_size_in_requests,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1564

dc->dcn_ip->dispclk_ramping_margin,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1565

dc->dcn_ip->under_scan_factor * 100,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1566

dc->dcn_ip->max_inter_dcn_tile_repeaters,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1567

dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1568

dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1569

dc->dcn_ip->dcfclk_cstate_latency);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1571

dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1572

dc->dml.soc.sr_enter_plus_exit_time_us = dc->dcn_soc->sr_enter_plus_exit_time;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1573

dc->dml.soc.urgent_latency_us = dc->dcn_soc->urgent_latency;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1574

dc->dml.soc.writeback_latency_us = dc->dcn_soc->write_back_latency;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1575

dc->dml.soc.ideal_dram_bw_after_urgent_percent =

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1576

dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1577

dc->dml.soc.max_request_size_bytes = dc->dcn_soc->max_request_size;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1578

dc->dml.soc.downspread_percent = dc->dcn_soc->downspreading;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1579

dc->dml.soc.round_trip_ping_latency_dcfclk_cycles =

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1580

dc->dcn_soc->round_trip_ping_latency_cycles;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1581

dc->dml.soc.urgent_out_of_order_return_per_channel_bytes =

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1582

dc->dcn_soc->urgent_out_of_order_return_per_channel;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1583

dc->dml.soc.num_chans = dc->dcn_soc->number_of_channels;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1584

dc->dml.soc.vmm_page_size_bytes = dc->dcn_soc->vmm_page_size;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1585

dc->dml.soc.dram_clock_change_latency_us = dc->dcn_soc->dram_clock_change_latency;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1586

dc->dml.soc.return_bus_width_bytes = dc->dcn_soc->return_bus_width;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1588

dc->dml.ip.rob_buffer_size_kbytes = (unsigned int)dc->dcn_ip->rob_buffer_size_in_kbyte;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1589

dc->dml.ip.det_buffer_size_kbytes = (unsigned int)dc->dcn_ip->det_buffer_size_in_kbyte;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1590

dc->dml.ip.dpp_output_buffer_pixels = (unsigned int)dc->dcn_ip->dpp_output_buffer_pixels;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1591

dc->dml.ip.opp_output_buffer_lines = (unsigned int)dc->dcn_ip->opp_output_buffer_lines;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1592

dc->dml.ip.pixel_chunk_size_kbytes = (unsigned int)dc->dcn_ip->pixel_chunk_size_in_kbyte;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1593

dc->dml.ip.pte_enable = dc->dcn_ip->pte_enable == dcn_bw_yes;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1594

dc->dml.ip.pte_chunk_size_kbytes = (unsigned int)dc->dcn_ip->pte_chunk_size;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1595

dc->dml.ip.meta_chunk_size_kbytes = (unsigned int)dc->dcn_ip->meta_chunk_size;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1596

dc->dml.ip.writeback_chunk_size_kbytes = dc->dcn_ip->writeback_chunk_size;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1597

dc->dml.ip.line_buffer_size_bits = dc->dcn_ip->line_buffer_size;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1598

dc->dml.ip.max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1599

dc->dml.ip.IsLineBufferBppFixed = dc->dcn_ip->is_line_buffer_bpp_fixed == dcn_bw_yes;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1600

dc->dml.ip.LineBufferFixedBpp = dc->dcn_ip->line_buffer_fixed_bpp;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1601

dc->dml.ip.writeback_luma_buffer_size_kbytes = dc->dcn_ip->writeback_luma_buffer_size;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1602

dc->dml.ip.writeback_chroma_buffer_size_kbytes = dc->dcn_ip->writeback_chroma_buffer_size;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1603

dc->dml.ip.max_num_dpp = dc->dcn_ip->max_num_dpp;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1604

dc->dml.ip.max_num_wb = dc->dcn_ip->max_num_writeback;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1605

dc->dml.ip.max_dchub_pscl_bw_pix_per_clk = dc->dcn_ip->max_dchub_topscl_throughput;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1606

dc->dml.ip.max_pscl_lb_bw_pix_per_clk = dc->dcn_ip->max_pscl_tolb_throughput;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1607

dc->dml.ip.max_lb_vscl_bw_pix_per_clk = dc->dcn_ip->max_lb_tovscl_throughput;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1608

dc->dml.ip.max_vscl_hscl_bw_pix_per_clk = dc->dcn_ip->max_vscl_tohscl_throughput;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1609

dc->dml.ip.max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1610

dc->dml.ip.max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1611

dc->dml.ip.max_hscl_taps = dc->dcn_ip->max_hscl_taps;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1612

dc->dml.ip.max_vscl_taps = dc->dcn_ip->max_vscl_taps;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1614

dc->dml.ip.dispclk_ramp_margin_percent = dc->dcn_ip->dispclk_ramping_margin;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1615

dc->dml.ip.underscan_factor = dc->dcn_ip->under_scan_factor;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1616

dc->dml.ip.max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1617

dc->dml.ip.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1618

dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1619

dc->dml.ip.bug_forcing_LC_req_same_size_fixed =

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1620

dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1621

dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip->dcfclk_cstate_latency;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

318

if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

333

input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs->

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

40

dc->ctx->logger

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

453

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

458

struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

497

input->clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0f;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

640

static bool dcn_bw_apply_registry_override(struct dc *dc)

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

644

if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

645

&& dc->debug.sr_exit_time_ns) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

647

dc->dcn_soc->sr_exit_time = dc->debug.sr_exit_time_ns / 1000.0f;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

650

if ((int)(dc->dcn_soc->sr_enter_plus_exit_time * 1000)

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

651

!= dc->debug.sr_enter_plus_exit_time_ns

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

652

&& dc->debug.sr_enter_plus_exit_time_ns) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

654

dc->dcn_soc->sr_enter_plus_exit_time =

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

655

dc->debug.sr_enter_plus_exit_time_ns / 1000.0f;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

658

if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->debug.urgent_latency_ns

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

659

&& dc->debug.urgent_latency_ns) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

661

dc->dcn_soc->urgent_latency = dc->debug.urgent_latency_ns / 1000.0f;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

664

if ((int)(dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency * 1000)

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

665

!= dc->debug.percent_of_ideal_drambw

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

666

&& dc->debug.percent_of_ideal_drambw) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

668

dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency =

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

669

(float)dc->debug.percent_of_ideal_drambw;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

672

if ((int)(dc->dcn_soc->dram_clock_change_latency * 1000)

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

673

!= dc->debug.dram_clock_change_latency_ns

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

674

&& dc->debug.dram_clock_change_latency_ns) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

676

dc->dcn_soc->dram_clock_change_latency =

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

677

dc->debug.dram_clock_change_latency_ns / 1000.0f;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

751

struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

761

const struct resource_pool *pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

773

if (dcn_bw_apply_registry_override(dc))

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

774

dcn_bw_sync_calcs_and_dml(dc);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

778

v->sr_exit_time = dc->dcn_soc->sr_exit_time;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

779

v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

780

v->urgent_latency = dc->dcn_soc->urgent_latency;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

781

v->write_back_latency = dc->dcn_soc->write_back_latency;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

783

dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

785

v->dcfclkv_min0p65 = dc->dcn_soc->dcfclkv_min0p65;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

786

v->dcfclkv_mid0p72 = dc->dcn_soc->dcfclkv_mid0p72;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

787

v->dcfclkv_nom0p8 = dc->dcn_soc->dcfclkv_nom0p8;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

788

v->dcfclkv_max0p9 = dc->dcn_soc->dcfclkv_max0p9;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

790

v->max_dispclk_vmin0p65 = dc->dcn_soc->max_dispclk_vmin0p65;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

791

v->max_dispclk_vmid0p72 = dc->dcn_soc->max_dispclk_vmid0p72;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

792

v->max_dispclk_vnom0p8 = dc->dcn_soc->max_dispclk_vnom0p8;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

793

v->max_dispclk_vmax0p9 = dc->dcn_soc->max_dispclk_vmax0p9;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

795

v->max_dppclk_vmin0p65 = dc->dcn_soc->max_dppclk_vmin0p65;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

796

v->max_dppclk_vmid0p72 = dc->dcn_soc->max_dppclk_vmid0p72;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

797

v->max_dppclk_vnom0p8 = dc->dcn_soc->max_dppclk_vnom0p8;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

798

v->max_dppclk_vmax0p9 = dc->dcn_soc->max_dppclk_vmax0p9;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

800

v->socclk = dc->dcn_soc->socclk;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

802

v->fabric_and_dram_bandwidth_vmin0p65 = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

803

v->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

804

v->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

805

v->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

807

v->phyclkv_min0p65 = dc->dcn_soc->phyclkv_min0p65;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

808

v->phyclkv_mid0p72 = dc->dcn_soc->phyclkv_mid0p72;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

809

v->phyclkv_nom0p8 = dc->dcn_soc->phyclkv_nom0p8;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

810

v->phyclkv_max0p9 = dc->dcn_soc->phyclkv_max0p9;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

812

v->downspreading = dc->dcn_soc->downspreading;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

813

v->round_trip_ping_latency_cycles = (float)dc->dcn_soc->round_trip_ping_latency_cycles;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

814

v->urgent_out_of_order_return_per_channel = (float)dc->dcn_soc->urgent_out_of_order_return_per_channel;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

815

v->number_of_channels = (float)dc->dcn_soc->number_of_channels;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

816

v->vmm_page_size = (float)dc->dcn_soc->vmm_page_size;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

817

v->dram_clock_change_latency = dc->dcn_soc->dram_clock_change_latency;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

818

v->return_bus_width = (float)dc->dcn_soc->return_bus_width;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

820

v->rob_buffer_size_in_kbyte = dc->dcn_ip->rob_buffer_size_in_kbyte;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

821

v->det_buffer_size_in_kbyte = dc->dcn_ip->det_buffer_size_in_kbyte;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

822

v->dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

823

v->opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

824

v->pixel_chunk_size_in_kbyte = dc->dcn_ip->pixel_chunk_size_in_kbyte;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

825

v->pte_enable = dc->dcn_ip->pte_enable;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

826

v->pte_chunk_size = (float)dc->dcn_ip->pte_chunk_size;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

827

v->meta_chunk_size = (float)dc->dcn_ip->meta_chunk_size;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

828

v->writeback_chunk_size = (float)dc->dcn_ip->writeback_chunk_size;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

829

v->odm_capability = dc->dcn_ip->odm_capability;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

830

v->dsc_capability = dc->dcn_ip->dsc_capability;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

831

v->line_buffer_size = (float)dc->dcn_ip->line_buffer_size;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

832

v->is_line_buffer_bpp_fixed = dc->dcn_ip->is_line_buffer_bpp_fixed;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

833

v->line_buffer_fixed_bpp = (float)dc->dcn_ip->line_buffer_fixed_bpp;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

834

v->max_line_buffer_lines = (float)dc->dcn_ip->max_line_buffer_lines;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

835

v->writeback_luma_buffer_size = (float)dc->dcn_ip->writeback_luma_buffer_size;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

836

v->writeback_chroma_buffer_size = (float)dc->dcn_ip->writeback_chroma_buffer_size;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

837

v->max_num_dpp = (float)dc->dcn_ip->max_num_dpp;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

838

v->max_num_writeback = (float)dc->dcn_ip->max_num_writeback;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

839

v->max_dchub_topscl_throughput = (float)dc->dcn_ip->max_dchub_topscl_throughput;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

840

v->max_pscl_tolb_throughput = (float)dc->dcn_ip->max_pscl_tolb_throughput;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

841

v->max_lb_tovscl_throughput = (float)dc->dcn_ip->max_lb_tovscl_throughput;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

842

v->max_vscl_tohscl_throughput = (float)dc->dcn_ip->max_vscl_tohscl_throughput;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

843

v->max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

844

v->max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

845

v->max_hscl_taps = (float)dc->dcn_ip->max_hscl_taps;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

846

v->max_vscl_taps = (float)dc->dcn_ip->max_vscl_taps;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

847

v->under_scan_factor = dc->dcn_ip->under_scan_factor;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

848

v->pte_buffer_size_in_requests = (float)dc->dcn_ip->pte_buffer_size_in_requests;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

849

v->dispclk_ramping_margin = (float)dc->dcn_ip->dispclk_ramping_margin;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

850

v->max_inter_dcn_tile_repeaters = (float)dc->dcn_ip->max_inter_dcn_tile_repeaters;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

852

dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

854

dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

991

if (dc->debug.optimized_watermark) {

drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

127

void dcn10_resource_construct_fp(struct dc *dc)

drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

130

if (dc->ctx->dce_version == DCN_VERSION_1_01) {

drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

131

struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc;

drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

132

struct dcn_ip_params *dcn_ip = dc->dcn_ip;

drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

133

struct display_mode_lib *dml = &dc->dml;

drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

140

if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {

drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

141

dc->dcn_soc->urgent_latency = 3;

drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

142

dc->debug.disable_dmcu = true;

drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

143

dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f;

drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

146

dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;

drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

147

ASSERT(dc->dcn_soc->number_of_channels < 3);

drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

148

if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/

drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

149

dc->dcn_soc->number_of_channels = 2;

drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

151

if (dc->dcn_soc->number_of_channels == 1) {

drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

152

dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f;

drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

153

dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f;

drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

154

dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f;

drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

155

dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f;

drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

156

if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev))

drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

157

dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f;

drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.h

30

void dcn10_resource_construct_fp(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1046

static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1049

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1054

if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1060

static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1066

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1087

int minmum_z8_residency = dc->debug.minimum_z8_residency_time > 0 ? dc->debug.minimum_z8_residency_time : 1000;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1143

void dcn20_calculate_dlg_params(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1155

dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1162

if ((int)dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1163

context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1178

context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1180

if ((unsigned int)context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1181

context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)dc->debug.min_disp_clk_khz;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1183

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1207

if (dc->ctx->dce_version < DCN_VERSION_3_1 &&

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1228

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1235

if (dc->ctx->dce_version == DCN_VERSION_2_01)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1253

context->bw_ctx.bw.dcn.clk.zstate_support = decide_zstate_support(dc, context);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1318

int dcn20_populate_dml_pipes_from_context(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1331

for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1343

if (dc->debug.disable_timing_sync ||

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1355

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1373

pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1375

pipes[pipe_cnt].pipe.dest.use_maximum_vstartup = dc->ctx->dce_version == DCN_VERSION_2_01;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1461

if (dc->link_srv->dp_is_128b_132b_signal(&res_ctx->pipe_ctx[i]))

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1552

pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1689

|| dc->debug.always_scale; /*support always scale*/

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1735

dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1740

void dcn20_calculate_wm(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1752

for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1756

pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1778

if (dc->config.forced_clocks) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1782

if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1783

pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1784

if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1785

pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1791

if (dc->res_pool->funcs->populate_dml_pipes)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1792

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1795

pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1858

void dcn20_update_bounding_box(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1875

if (dc->bb_overrides.min_dcfclk_mhz > 0) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1876

min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1878

if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1992

void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1996

if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1997

&& dc->bb_overrides.sr_exit_time_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1998

bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2002

!= dc->bb_overrides.sr_enter_plus_exit_time_ns

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2003

&& dc->bb_overrides.sr_enter_plus_exit_time_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2005

dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2009

!= dc->bb_overrides.sr_exit_z8_time_ns

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2010

&& dc->bb_overrides.sr_exit_z8_time_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2011

bb->sr_exit_z8_time_us = dc->bb_overrides.sr_exit_z8_time_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2015

!= dc->bb_overrides.sr_enter_plus_exit_z8_time_ns

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2016

&& dc->bb_overrides.sr_enter_plus_exit_z8_time_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2017

bb->sr_enter_plus_exit_z8_time_us = dc->bb_overrides.sr_enter_plus_exit_z8_time_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2019

if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2020

&& dc->bb_overrides.urgent_latency_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2021

bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2025

!= dc->bb_overrides.dram_clock_change_latency_ns

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2026

&& dc->bb_overrides.dram_clock_change_latency_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2028

dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2032

!= dc->bb_overrides.dummy_clock_change_latency_ns

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2033

&& dc->bb_overrides.dummy_clock_change_latency_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2035

dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2039

static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2049

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2053

out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, validate_mode);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2068

dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, validate_mode);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2069

dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2089

bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2101

dc->debug.disable_dram_clock_change_vactive_support;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2103

dc->debug.enable_dram_clock_change_one_display_vactive;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2106

ASSERT(context != dc->current_state);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2109

return dcn20_validate_bandwidth_internal(dc, context, validate_mode, pipes);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2112

voltage_supported = dcn20_validate_bandwidth_internal(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING, pipes);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2124

memset(pipes, 0, dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st));

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2125

voltage_supported = dcn20_validate_bandwidth_internal(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING, pipes);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2165

int dcn21_populate_dml_pipes_from_context(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2175

pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2179

pipes[i].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2186

static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2190

if (dc->bb_overrides.sr_exit_time_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2192

dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2193

dc->bb_overrides.sr_exit_time_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2197

if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2199

dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2200

dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2204

if (dc->bb_overrides.urgent_latency_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2205

bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2208

if (dc->bb_overrides.dram_clock_change_latency_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2210

dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2211

dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2246

static void dcn21_calculate_wm(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2257

struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2261

patch_bounding_box(dc, &context->bw_ctx.dml.soc);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2263

for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2267

pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2292

if (dc->res_pool->funcs->populate_dml_pipes)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2293

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2296

pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2331

bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2341

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2348

ASSERT(context != dc->current_state);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2350

out = dcn21_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, validate_mode, false);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2365

dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, validate_mode);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2366

dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2413

void dcn21_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2415

struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2416

struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2473

dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2486

void dcn201_populate_dml_writeback_from_context_fpu(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2498

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

38

dc->ctx->logger

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

989

void dcn20_populate_dml_writeback_from_context(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

998

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

31

void dcn20_populate_dml_writeback_from_context(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

39

void dcn20_calculate_dlg_params(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

44

int dcn20_populate_dml_pipes_from_context(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

48

void dcn20_calculate_wm(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

57

void dcn20_update_bounding_box(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

62

void dcn20_patch_bounding_box(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

64

bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

75

int dcn21_populate_dml_pipes_from_context(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

79

bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, enum

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

81

void dcn21_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

85

void dcn201_populate_dml_writeback_from_context_fpu(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

185

struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

195

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

222

if (dc->dml.ip.writeback_max_hscl_taps > 1) {

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

262

dc->current_state->bw_ctx.dml.ip.writeback_line_buffer_buffer_size);

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

293

void dcn30_fpu_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

298

if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) {

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

301

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

302

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

303

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

308

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

335

dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(dc, context);

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

338

dummy_latency_index = dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(dc,

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

346

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

347

dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel,

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

366

if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

371

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

372

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

373

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

413

if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

418

dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

422

int min_dram_speed_mts_offset = dc->clk_mgr->bw_params->clk_table.num_entries - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

425

dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz * 16;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

434

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dram_speed_mts)

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

439

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

441

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

442

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

467

dc->res_pool->funcs->update_soc_for_wm_a(dc, context);

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

483

for (pipe_i = 0, pipe_idx = 0; pipe_i < dc->res_pool->pipe_count; pipe_i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

490

if (dc->config.forced_clocks) {

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

494

if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

495

pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

496

if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

497

pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

504

dc->dml.soc.num_chans <= 4 &&

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

508

for (state_i = 0; state_i < dc->dml.soc.num_states; state_i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

509

if (dc->dml.soc.clock_limits[state_i].dram_speed_mts > 1700) {

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

510

context->bw_ctx.dml.vba.DRAMSpeed = dc->dml.soc.clock_limits[state_i].dram_speed_mts;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

516

dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

521

dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

524

dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(dc, context);

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

527

void dcn30_fpu_update_dram_channel_width_bytes(struct dc *dc)

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

531

if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

532

dcn3_0_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

573

void dcn30_fpu_update_bw_bounding_box(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

584

dcn3_0_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

585

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

605

dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

606

if (dc->current_state)

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

607

dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

626

int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

639

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

640

dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel,

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

667

double pstate_latency_us = base->ctx->dc->dml.soc.dram_clock_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

668

double sr_exit_time_us = base->ctx->dc->dml.soc.sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

669

double sr_enter_plus_exit_time_us = base->ctx->dc->dml.soc.sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

727

void patch_dcn30_soc_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *soc_bb)

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

732

if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

735

if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h

33

struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h

41

void dcn30_fpu_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h

44

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h

49

void dcn30_fpu_update_dram_channel_width_bytes(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h

57

void dcn30_fpu_update_bw_bounding_box(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h

63

int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h

71

void patch_dcn30_soc_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *dcn3_0_ip);

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

323

void dcn301_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

325

struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

326

struct dcn301_resource_pool *pool = TO_DCN301_RES_POOL(dc->res_pool);

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

392

dcn3_01_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

393

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

396

!= dc->debug.dram_clock_change_latency_ns

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

397

&& dc->debug.dram_clock_change_latency_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

398

dcn3_01_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

400

dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30);

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

427

void dcn301_fpu_calculate_wm_and_dlg(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

436

struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

468

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

475

if (dc->config.forced_clocks) {

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

479

if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

480

pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

481

if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

482

pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

486

dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h

30

void dcn301_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h

36

void dcn301_fpu_calculate_wm_and_dlg(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

196

void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

212

if (dc->ctx->dc_bios->vram_info.num_chans)

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

213

dcn3_02_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

215

if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

216

dcn3_02_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

218

dcn3_02_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

219

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

344

dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30);

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

345

if (dc->current_state)

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

346

dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30);

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.h

30

void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

192

void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

208

if (dc->ctx->dc_bios->vram_info.num_chans)

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

209

dcn3_03_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

211

if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

212

dcn3_03_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

214

dcn3_03_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

215

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

363

dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30);

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

364

if (dc->current_state)

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

365

dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30);

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.h

29

void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

454

void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

458

if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

459

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

460

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

461

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

465

void dcn315_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

469

if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

474

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

476

dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

478

dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

483

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

493

(uint32_t)dc->debug.minimum_z8_residency_time * 1000U;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

516

if (get_stutter_period(&context->bw_ctx.dml, pipes, pipe_cnt) < dc->debug.minimum_z8_residency_time &&

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

525

dc->res_pool->funcs->update_soc_for_wm_a(dc, context);

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

540

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

550

if (dc->config.forced_clocks || dc->debug.max_disp_clk) {

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

554

if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

555

pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

556

if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

557

pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

562

dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

575

for (i = 0; i < dc->res_pool->pipe_count; i++)

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

579

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

593

void dcn31_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

595

struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

606

dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

607

dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

659

dcn3_1_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

660

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

663

!= dc->debug.dram_clock_change_latency_ns

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

664

&& dc->debug.dram_clock_change_latency_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

665

dcn3_1_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

668

dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31);

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

671

void dcn315_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

678

dcn3_15_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

679

dcn3_15_ip.max_num_dpp = dc->res_pool->pipe_count;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

724

!= dc->debug.dram_clock_change_latency_ns

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

725

&& dc->debug.dram_clock_change_latency_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

726

dcn3_15_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

729

dml_init_instance(&dc->dml, &dcn3_15_soc, &dcn3_15_ip, DML_PROJECT_DCN315);

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

732

void dcn316_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

734

struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

745

dcn3_16_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

746

dcn3_16_ip.max_num_dpp = dc->res_pool->pipe_count;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

801

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

804

!= dc->debug.dram_clock_change_latency_ns

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

805

&& dc->debug.dram_clock_change_latency_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

806

dcn3_16_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

809

dml_init_instance(&dc->dml, &dcn3_16_soc, &dcn3_16_ip, DML_PROJECT_DCN31);

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h

38

void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h

39

void dcn315_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h

42

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h

47

void dcn31_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h

48

void dcn315_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h

49

void dcn316_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h

55

int dcn31x_populate_dml_pipes_from_context(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

182

void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

194

if (dc->config.use_default_clock_table == false) {

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

195

dcn3_14_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

196

dcn3_14_ip.max_num_dpp = dc->res_pool->pipe_count;

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

265

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

268

dcn20_patch_bounding_box(dc, &dcn3_14_soc);

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

269

dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN314);

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

307

int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

320

dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

322

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

357

if (dc->debug.dml_hostvm_override == DML_HOSTVM_NO_OVERRIDE)

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

358

pipes[i].pipe.src.hostvm = dc->vm_pa_config.is_hvm_enabled || dc->res_pool->hubbub->riommu_active;

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

396

&& pipe->plane_state->rotation == ROTATION_ANGLE_0 && !dc->debug.disable_z9_mpc) {

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

402

} else if (context->stream_count >= dc->debug.crb_alloc_policy_min_disp_count

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

403

&& dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) {

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

404

context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64;

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

409

if (dc->debug.force_odm_combine_4to1)

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

412

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

418

if (cur_pipe->stream->signal == SIGNAL_TYPE_EDP && dc->debug.seamless_boot_odm_combine &&

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.h

35

void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.h

36

int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1040

static bool subvp_validate_static_schedulability(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1051

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1077

schedulable = subvp_subvp_admissable(dc, context) && subvp_subvp_schedulable(dc, context);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1082

if (dcn32_subvp_drr_admissable(dc, context))

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1083

schedulable = subvp_drr_schedulable(dc, context);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1084

else if (dcn32_subvp_vblank_admissable(dc, context, vlevel))

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1085

schedulable = subvp_vblank_schedulable(dc, context);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1096

static void assign_subvp_index(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1101

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1203

struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1235

dc_pipe_idx < dc->res_pool->pipe_count; dc_pipe_idx++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1271

static void update_pipes_with_slice_table(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1278

dc->current_state, dc->res_pool,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1284

dc->current_state, dc->res_pool,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1289

static bool update_pipes_with_split_flags(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1298

&slice_table, dc, context, vba,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1300

update_pipes_with_slice_table(dc, context, &slice_table);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1304

static bool should_apply_odm_power_optimization(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1316

if (!dc->debug.enable_single_display_2to1_odm_policy)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1351

if (dc->config.enable_windowed_mpo_odm) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1365

&slice_table, dc, context, v,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1398

struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1420

*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, new_vlevel, split, merge);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1441

static bool dcn32_full_validate_bw_helper(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1464

if (dc->debug.dml_disallow_alternate_prefetch_modes)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1474

*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1479

if (!dcn32_apply_merge_split_flags_helper(dc, context, repopulate_pipes, split, merge))

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1491

if (!dc->debug.force_disable_subvp && !dc->caps.dmub_caps.gecc_enable && dcn32_all_pipes_have_stream_and_plane(dc, context) &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1492

!dcn32_mpo_in_use(context) && !dcn32_any_surfaces_rotated(dc, context) && !is_test_pattern_enabled(context) &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1496

dc->debug.force_subvp_mclk_switch)) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1500

while (!found_supported_config && dcn32_enough_pipes_for_subvp(dc, context) &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1501

dcn32_assign_subvp_pipe(dc, context, &dc_pipe_idx)) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1522

dc->res_pool->funcs->add_phantom_pipes(dc, context, pipes, *pipe_cnt, dc_pipe_idx);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1524

*pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1542

&& subvp_validate_static_schedulability(dc, context, *vlevel))

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1546

if (dcn32_subvp_drr_admissable(dc, context) && subvp_drr_schedulable(dc, context)) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1565

dc_state_remove_phantom_streams_and_planes(dc, context);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1566

dc_state_release_phantom_streams_and_planes(dc, context);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1568

*pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1574

*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1579

dcn32_helper_populate_phantom_dlg_params(dc, context, pipes, *pipe_cnt);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1589

*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1593

assign_subvp_index(dc, context);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1597

if (should_apply_odm_power_optimization(dc, context, vba, split, merge))

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1599

dc, context, pipes, split, merge, vlevel, *pipe_cnt);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1604

static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1608

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1613

if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1619

static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1632

dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1650

context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1660

if ((unsigned int)context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1661

context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)dc->debug.min_disp_clk_khz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1675

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1755

context->bw_ctx.bw.dcn.clk.num_ways = dcn32_helper_calculate_num_ways_for_subvp(dc, context);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1759

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1764

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1780

struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1793

for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1794

if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1795

&& dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1810

for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1822

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1829

const struct resource_pool *pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

183

static bool dcn32_apply_merge_split_flags_helper(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1831

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1887

dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

189

double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

190

double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1908

struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

191

double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1919

if (dc->config.enable_windowed_mpo_odm) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

192

double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1921

dc, context, vba, split, merge))

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1929

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1977

dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

198

(uint16_t)clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2003

for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2005

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2033

hsplit_pipe = dcn32_find_split_pipe(dc, context, old_index);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2039

dc, &context->res_ctx,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2056

pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2061

dc, &context->res_ctx,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2075

pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2080

dc, &context->res_ctx,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2086

dcn20_build_mapped_resource(dc, context, pipe->stream);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2089

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2109

bool dcn32_internal_validate_bw(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2131

dc_state_remove_phantom_streams_and_planes(dc, context);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2132

dc_state_release_phantom_streams_and_planes(dc, context);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2134

dc->res_pool->funcs->update_soc_for_wm_a(dc, context);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2137

resource_update_pipes_for_stream_with_slice_count(context, dc->current_state, dc->res_pool, context->streams[i], 1);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2138

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2146

context->bw_ctx.dml.soc.max_vratio_pre = dcn32_determine_max_vratio_prefetch(dc, context);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2149

if (!dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2155

(dc->debug.dml_disallow_alternate_prefetch_modes &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2179

vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2190

for (i = 0, pipe_idx = 0; i < (int)dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2198

&& !dc->config.enable_windowed_mpo_odm

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2209

if (!dcn32_apply_merge_split_flags_helper(dc, context, &repopulate_pipes, split, merge))

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2213

if (!dcn20_validate_dsc(dc, context)) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2223

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2224

if (!dc->config.enable_windowed_mpo_odm)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2225

dcn32_update_dml_pipes_odm_policy_based_on_context(dc, context, pipes);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2274

void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2290

bool subvp_in_use = dcn32_subvp_in_use(dc, context);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2308

dummy_latency_index = dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(dc,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2314

if (context->bw_ctx.dml.soc.fclk_change_latency_us < dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2317

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2320

dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2321

dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, DC_VALIDATE_MODE_AND_PROGRAMMING);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2337

if (!pstate_en || (!dc->debug.disable_fpo_optimizations &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2340

fpo_candidate_stream = dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(dc, context);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2349

dummy_latency_index = dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(dc,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2358

dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2362

if (context->bw_ctx.dml.soc.fclk_change_latency_us < dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2365

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2367

dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel_temp,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

238

if (clk_mgr->base.ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2388

context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2389

dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2412

if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2413

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2414

context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2415

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2416

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2481

if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2486

dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2490

int min_dram_speed_mts_offset = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2493

dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz * 16;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2502

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dram_speed_mts)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2507

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2509

context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2510

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2511

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2529

if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2549

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2550

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2551

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2568

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2575

if (dc->config.forced_clocks) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2579

if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2580

pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2581

if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2582

pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2592

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2594

dcn32_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2599

dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2604

dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

278

int dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

295

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

296

dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, DC_VALIDATE_MODE_AND_PROGRAMMING);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

300

dcn32_subvp_in_use(dc, context))

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3025

void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3030

dcn3_2_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3033

if ((int)(dcn3_2_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3034

&& dc->bb_overrides.sr_exit_time_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3035

dc->dml2_options.bbox_overrides.sr_exit_latency_us =

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3036

dcn3_2_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3040

!= dc->bb_overrides.sr_enter_plus_exit_time_ns

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3041

&& dc->bb_overrides.sr_enter_plus_exit_time_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3042

dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us =

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3044

dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3047

if ((int)(dcn3_2_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3048

&& dc->bb_overrides.urgent_latency_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3049

dcn3_2_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3050

dc->dml2_options.bbox_overrides.urgent_latency_us =

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3051

dcn3_2_soc.urgent_latency_pixel_data_only_us = dc->bb_overrides.urgent_latency_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3055

!= dc->bb_overrides.dram_clock_change_latency_ns

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3056

&& dc->bb_overrides.dram_clock_change_latency_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3057

dc->dml2_options.bbox_overrides.dram_clock_change_latency_us =

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3059

dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3063

!= dc->bb_overrides.fclk_clock_change_latency_ns

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3064

&& dc->bb_overrides.fclk_clock_change_latency_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3065

dc->dml2_options.bbox_overrides.fclk_change_latency_us =

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3067

dc->bb_overrides.fclk_clock_change_latency_ns / 1000;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3071

!= dc->bb_overrides.dummy_clock_change_latency_ns

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3072

&& dc->bb_overrides.dummy_clock_change_latency_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3074

dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3078

if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3081

if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3083

dc->dml2_options.bbox_overrides.dram_clock_change_latency_us =

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3088

dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us =

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3093

dc->dml2_options.bbox_overrides.sr_exit_latency_us =

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3100

if (dc->ctx->dc_bios->vram_info.num_chans) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3101

dc->dml2_options.bbox_overrides.dram_num_chan =

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3102

dcn3_2_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3103

dcn3_2_soc.mall_allocated_for_dcn_mbytes = (double)(dcn32_calc_num_avail_chans_for_mall(dc,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3104

dc->ctx->dc_bios->vram_info.num_chans) * dc->caps.mall_size_per_mem_channel);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3107

if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3108

unsigned int dram_channel_width_bytes = (unsigned int)dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3110

dc->dml2_options.bbox_overrides.dram_chanel_width_bytes = dram_channel_width_bytes;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3115

dcn3_2_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3117

dcn3_2_ip.min_prefetch_in_strobe_us = dc->debug.min_prefetch_in_strobe_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3120

dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3121

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3122

dc->dml2_options.bbox_overrides.disp_pll_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3123

dc->dml2_options.bbox_overrides.xtalclk_mhz = dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3124

dc->dml2_options.bbox_overrides.dchub_refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3125

dc->dml2_options.bbox_overrides.dprefclk_mhz = dc->clk_mgr->dprefclk_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3129

if (dc->debug.use_legacy_soc_bb_mechanism) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3282

build_synthetic_soc_states(dc->debug.disable_dc_mode_overwrite, bw_params,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3287

dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3288

if (dc->current_state)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3289

dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3292

if (dc->clk_mgr->bw_params->clk_table.num_entries > 1) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3295

dc->dml2_options.bbox_overrides.clks_table.num_states = dc->clk_mgr->bw_params->clk_table.num_entries;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3297

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3298

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3300

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3301

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3303

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3304

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3306

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3307

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3309

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3310

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3312

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3313

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3315

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3316

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dppclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3318

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3319

if (dc->clk_mgr->bw_params->clk_table.entries[i].dcfclk_mhz)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3320

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3321

dc->clk_mgr->bw_params->clk_table.entries[i].dcfclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3324

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3325

if (dc->clk_mgr->bw_params->clk_table.entries[i].fclk_mhz)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3326

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3327

dc->clk_mgr->bw_params->clk_table.entries[i].fclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3330

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3331

if (dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3332

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3333

dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3336

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3337

if (dc->clk_mgr->bw_params->clk_table.entries[i].socclk_mhz)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3338

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3339

dc->clk_mgr->bw_params->clk_table.entries[i].socclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3342

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3343

if (dc->clk_mgr->bw_params->clk_table.entries[i].dtbclk_mhz)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3344

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3345

dc->clk_mgr->bw_params->clk_table.entries[i].dtbclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3348

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3349

if (dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3350

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3351

dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3352

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3353

dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

336

void dcn32_helper_populate_phantom_dlg_params(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3410

bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3423

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3436

if (!dc->debug.disable_subvp_high_refresh && min_refresh >= subvp_min_refresh && pipe->stream &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

345

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3466

double dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3468

(void)dc;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3501

void dcn32_assign_fpo_vactive_candidate(struct dc *dc, const struct dc_state *context, struct dc_stream_state **fpo_candidate_stream)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3506

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3538

bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, struct dc_stream_state *fpo_candidate_stream, uint32_t vactive_margin_req_us)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3545

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3563

pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed || blank_us >= dc->debug.fpo_vactive_max_blank_us) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3579

void dcn32_override_min_req_memclk(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3582

if ((context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dcn32_subvp_in_use(dc, context)) &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3583

dc->dml.soc.num_chans <= 8) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3584

int num_mclk_levels = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3586

if (context->bw_ctx.dml.vba.DRAMSpeed <= dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 16 &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3588

context->bw_ctx.dml.vba.DRAMSpeed = dc->clk_mgr->bw_params->clk_table.entries[1].memclk_mhz * 16;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3594

unsigned int dcn32_get_max_dispclk_mhz(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3596

(void)dc;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

469

void dcn32_set_phantom_stream_timing(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

490

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

503

pstate_width_fw_delay_lines = (uint32_t)(((double)(dc->caps.subvp_fw_processing_delay_us +

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

504

dc->caps.subvp_pstate_allow_width_us) / 1000000) *

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

519

pstate_width_fw_delay_lines + dc->caps.subvp_swath_height_margin_lines);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

527

phantom_vactive += dc->debug.subvp_extra_lines;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

561

static unsigned int dcn32_get_num_free_pipes(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

567

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

578

free_pipes = dc->res_pool->pipe_count - num_pipes;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

602

static bool dcn32_assign_subvp_pipe(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

609

unsigned int free_pipes = dcn32_get_num_free_pipes(dc, context);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

612

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

635

(!dcn32_is_psr_capable(pipe) || (context->stream_count == 1 && dc->caps.dmub_caps.subvp_psr)) &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

637

(refresh_rate < 120 || dcn32_allow_subvp_high_refresh_rate(dc, context, pipe)) &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

683

static bool dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

686

unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

689

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

706

free_pipes = dcn32_get_num_free_pipes(dc, context);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

710

if (free_pipes >= min_pipe_split && free_pipes < dc->res_pool->pipe_count)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

729

static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

739

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

755

dc->caps.subvp_prefetch_end_to_mall_start_us +

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

756

dc->caps.subvp_fw_processing_delay_us + 1);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

800

static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

821

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

838

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

860

dc->caps.subvp_prefetch_end_to_mall_start_us);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

901

static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

927

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

955

dc->caps.subvp_prefetch_end_to_mall_start_us);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

988

static bool subvp_subvp_admissable(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

997

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

34

void dcn32_helper_populate_phantom_dlg_params(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

39

void dcn32_set_phantom_stream_timing(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

47

bool dcn32_internal_validate_bw(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

54

void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

59

void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

61

int dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

72

void dcn32_assign_fpo_vactive_candidate(struct dc *dc, const struct dc_state *context, struct dc_stream_state **fpo_candidate_stream);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

74

bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, struct dc_stream_state *fpo_candidate_stream, uint32_t vactive_margin_req);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

76

void dcn32_override_min_req_memclk(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

80

unsigned int dcn32_get_max_dispclk_mhz(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

610

void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

614

dcn3_21_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

617

if ((int)(dcn3_21_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

618

&& dc->bb_overrides.sr_exit_time_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

619

dc->dml2_options.bbox_overrides.sr_exit_latency_us =

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

620

dcn3_21_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

624

!= dc->bb_overrides.sr_enter_plus_exit_time_ns

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

625

&& dc->bb_overrides.sr_enter_plus_exit_time_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

626

dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us =

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

628

dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

631

if ((int)(dcn3_21_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

632

&& dc->bb_overrides.urgent_latency_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

633

dcn3_21_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

634

dc->dml2_options.bbox_overrides.urgent_latency_us =

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

635

dcn3_21_soc.urgent_latency_pixel_data_only_us = dc->bb_overrides.urgent_latency_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

639

!= dc->bb_overrides.dram_clock_change_latency_ns

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

640

&& dc->bb_overrides.dram_clock_change_latency_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

641

dc->dml2_options.bbox_overrides.dram_clock_change_latency_us =

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

643

dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

647

!= dc->bb_overrides.fclk_clock_change_latency_ns

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

648

&& dc->bb_overrides.fclk_clock_change_latency_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

649

dc->dml2_options.bbox_overrides.fclk_change_latency_us =

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

651

dc->bb_overrides.fclk_clock_change_latency_ns / 1000;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

655

!= dc->bb_overrides.dummy_clock_change_latency_ns

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

656

&& dc->bb_overrides.dummy_clock_change_latency_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

658

dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

662

if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

665

if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

667

dc->dml2_options.bbox_overrides.dram_clock_change_latency_us =

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

672

dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us =

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

677

dc->dml2_options.bbox_overrides.sr_exit_latency_us =

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

684

if (dc->ctx->dc_bios->vram_info.num_chans) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

685

dc->dml2_options.bbox_overrides.dram_num_chan =

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

686

dcn3_21_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

687

dcn3_21_soc.mall_allocated_for_dcn_mbytes = (double)(dcn32_calc_num_avail_chans_for_mall(dc,

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

688

dc->ctx->dc_bios->vram_info.num_chans) * dc->caps.mall_size_per_mem_channel);

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

691

if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

692

unsigned int dram_channel_width_bytes = (unsigned int)dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

694

dc->dml2_options.bbox_overrides.dram_chanel_width_bytes = dram_channel_width_bytes;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

699

dcn3_21_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

701

dcn3_21_ip.min_prefetch_in_strobe_us = dc->debug.min_prefetch_in_strobe_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

704

dcn3_21_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

705

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

706

dc->dml2_options.bbox_overrides.disp_pll_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

707

dc->dml2_options.bbox_overrides.xtalclk_mhz = dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

708

dc->dml2_options.bbox_overrides.dchub_refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

709

dc->dml2_options.bbox_overrides.dprefclk_mhz = dc->clk_mgr->dprefclk_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

712

if (dc->debug.use_legacy_soc_bb_mechanism) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

858

build_synthetic_soc_states(dc->debug.disable_dc_mode_overwrite, bw_params,

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

863

dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

864

if (dc->current_state)

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

865

dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

867

if (dc->clk_mgr->bw_params->clk_table.num_entries > 1) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

870

dc->dml2_options.bbox_overrides.clks_table.num_states = dc->clk_mgr->bw_params->clk_table.num_entries;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

872

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

873

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

875

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

876

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

878

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

879

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

881

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

882

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

884

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

885

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

887

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

888

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

890

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

891

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dppclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

894

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

895

if (dc->clk_mgr->bw_params->clk_table.entries[i].dcfclk_mhz)

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

896

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

897

dc->clk_mgr->bw_params->clk_table.entries[i].dcfclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

900

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

901

if (dc->clk_mgr->bw_params->clk_table.entries[i].fclk_mhz)

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

902

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

903

dc->clk_mgr->bw_params->clk_table.entries[i].fclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

906

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

907

if (dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

908

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

909

dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

912

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

913

if (dc->clk_mgr->bw_params->clk_table.entries[i].socclk_mhz)

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

914

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

915

dc->clk_mgr->bw_params->clk_table.entries[i].socclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

918

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

919

if (dc->clk_mgr->bw_params->clk_table.entries[i].dtbclk_mhz)

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

920

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

921

dc->clk_mgr->bw_params->clk_table.entries[i].dtbclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

924

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

925

if (dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

926

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

927

dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

928

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

929

dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.h

32

void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

228

void dcn35_update_bw_bounding_box_fpu(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

235

dc->scratch.update_bw_bounding_box.clock_limits;

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

241

dc->res_pool->res_cap->num_timing_generator;

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

242

dcn3_5_ip.max_num_dpp = dc->res_pool->pipe_count;

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

322

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

325

!= dc->debug.dram_clock_change_latency_ns

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

326

&& dc->debug.dram_clock_change_latency_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

328

dc->debug.dram_clock_change_latency_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

331

if (dc->bb_overrides.dram_clock_change_latency_ns > 0)

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

333

dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

335

if (dc->bb_overrides.sr_exit_time_ns > 0)

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

336

dcn3_5_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

338

if (dc->bb_overrides.sr_enter_plus_exit_time_ns > 0)

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

340

dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

342

if (dc->bb_overrides.sr_exit_z8_time_ns > 0)

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

343

dcn3_5_soc.sr_exit_z8_time_us = dc->bb_overrides.sr_exit_z8_time_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

345

if (dc->bb_overrides.sr_enter_plus_exit_z8_time_ns > 0)

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

347

dc->bb_overrides.sr_enter_plus_exit_z8_time_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

350

dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip,

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

357

dc->dml2_options.bbox_overrides.clks_table.num_states =

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

359

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

361

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

363

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

365

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

367

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

369

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

372

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dram_speed_mts = (unsigned int)clock_limits[i].dram_speed_mts;

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

373

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

375

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

377

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

379

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

381

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

383

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

385

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

387

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

393

dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = dcn3_5_soc.dram_clock_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

395

dc->dml2_options.bbox_overrides.sr_exit_latency_us = dcn3_5_soc.sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

396

dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us = dcn3_5_soc.sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

398

dc->dml2_options.bbox_overrides.sr_exit_z8_time_us = dcn3_5_soc.sr_exit_z8_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

399

dc->dml2_options.bbox_overrides.sr_enter_plus_exit_z8_time_us = dcn3_5_soc.sr_enter_plus_exit_z8_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

438

int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

452

dcn31_populate_dml_pipes_from_context(dc, context, pipes,

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

455

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

534

if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

545

dc->debug.crb_alloc_policy_min_disp_count &&

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

546

dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) {

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

548

dc->debug.crb_alloc_policy * 64;

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

553

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

560

dc->debug.seamless_boot_odm_combine &&

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

575

void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

579

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

583

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

597

dc->debug.minimum_z8_residency_time > 0 ? dc->debug.minimum_z8_residency_time : 1000;

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

600

dc->debug.minimum_z10_residency_time > 0 ? dc->debug.minimum_z10_residency_time : 5000;

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h

34

void dcn35_update_bw_bounding_box_fpu(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h

37

int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h

42

void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

261

void dcn351_update_bw_bounding_box_fpu(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

268

dc->scratch.update_bw_bounding_box.clock_limits;

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

274

dc->res_pool->res_cap->num_timing_generator;

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

275

dcn3_51_ip.max_num_dpp = dc->res_pool->pipe_count;

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

355

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

358

!= dc->debug.dram_clock_change_latency_ns

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

359

&& dc->debug.dram_clock_change_latency_ns) {

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

361

dc->debug.dram_clock_change_latency_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

364

if (dc->bb_overrides.dram_clock_change_latency_ns > 0)

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

366

dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

368

if (dc->bb_overrides.sr_exit_time_ns > 0)

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

369

dcn3_51_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

371

if (dc->bb_overrides.sr_enter_plus_exit_time_ns > 0)

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

373

dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

375

if (dc->bb_overrides.sr_exit_z8_time_ns > 0)

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

376

dcn3_51_soc.sr_exit_z8_time_us = dc->bb_overrides.sr_exit_z8_time_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

378

if (dc->bb_overrides.sr_enter_plus_exit_z8_time_ns > 0)

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

380

dc->bb_overrides.sr_enter_plus_exit_z8_time_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

383

dml_init_instance(&dc->dml, &dcn3_51_soc, &dcn3_51_ip,

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

390

dc->dml2_options.bbox_overrides.clks_table.num_states =

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

392

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

394

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

396

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

398

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

400

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

402

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

404

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dram_speed_mts = (unsigned int)clock_limits[i].dram_speed_mts;

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

405

dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz =

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

407

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

409

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

411

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

413

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

415

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

417

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

419

dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels =

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

425

dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = dcn3_51_soc.dram_clock_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

427

dc->dml2_options.bbox_overrides.sr_exit_latency_us = dcn3_51_soc.sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

428

dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us = dcn3_51_soc.sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

430

dc->dml2_options.bbox_overrides.sr_exit_z8_time_us = dcn3_51_soc.sr_exit_z8_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

431

dc->dml2_options.bbox_overrides.sr_enter_plus_exit_z8_time_us = dcn3_51_soc.sr_enter_plus_exit_z8_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

470

int dcn351_populate_dml_pipes_from_context_fpu(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

484

dcn31_populate_dml_pipes_from_context(dc, context, pipes,

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

487

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

566

if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

577

dc->debug.crb_alloc_policy_min_disp_count &&

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

578

dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) {

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

580

dc->debug.crb_alloc_policy * 64;

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

585

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

592

dc->debug.seamless_boot_odm_combine &&

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

607

void dcn351_decide_zstate_support(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

612

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

627

dc->debug.minimum_z8_residency_time > 0 ? dc->debug.minimum_z8_residency_time : 1000;

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.h

12

int dcn351_populate_dml_pipes_from_context_fpu(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.h

17

void dcn351_decide_zstate_support(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.h

9

void dcn351_update_bw_bounding_box_fpu(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

137

if (stream->ctx->dc->caps.max_v_total != 0) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

14

const struct dc *in_dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

154

stream->ctx->dc->config.enable_fpo_flicker_detection == 1)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

295

if (!stream->ctx->dc->debug.enable_single_display_2to1_odm_policy ||

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

298

stream_desc->overrides.disable_subvp = stream->ctx->dc->debug.force_disable_subvp ||

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

453

const struct dc *in_dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

578

} else if ((plane_state->ctx->dc->config.use_spl == true) &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

590

if (plane_state->ctx->dc->debug.always_scale == true) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

65

const struct dc *in_dc)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

792

bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

82

unsigned int max_hw_v_total = stream->ctx->dc->caps.max_v_total;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

84

if (stream->ctx->dc->caps.vtotal_limited_by_fp2) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

928

void dml21_extract_watermark_sets(const struct dc *in_dc, union dcn_watermark_set *watermarks, struct dml2_context *in_ctx)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h

20

void dml21_populate_dml_init_params(struct dml2_initialize_instance_in_out *dml_init, const struct dml2_configuration_options *config, const struct dc *in_dc);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h

21

bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h

23

void dml21_extract_watermark_sets(const struct dc *in_dc, union dcn_watermark_set *watermarks, struct dml2_context *in_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h

9

struct dc;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

197

static bool is_sub_vp_enabled(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

201

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

237

bool sub_vp_enabled = is_sub_vp_enabled(pipe_ctx->stream->ctx->dc, context);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

243

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

251

phantom_stream = dml_ctx->config.svp_pstate.callbacks.create_phantom_stream(dc, context, main_stream);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

274

dml_ctx->config.svp_pstate.callbacks.add_phantom_stream(dc, context, phantom_stream, main_stream);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

280

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

289

phantom_plane = dml_ctx->config.svp_pstate.callbacks.create_phantom_plane(dc, context, main_plane);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

317

dml_ctx->config.svp_pstate.callbacks.add_phantom_plane(dc, phantom_stream, phantom_plane, context);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

322

void dml21_handle_phantom_streams_planes(const struct dc *dc, struct dc_state *context, struct dml2_context *dml_ctx)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

346

dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

363

dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

375

dml2_map_dc_pipes(dml_ctx, context, NULL, &dml_ctx->v21.dml_to_dc_pipe_mapping, dc->current_state);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

379

static unsigned int dml21_build_fams2_stream_programming_v2(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

418

switch (dc->debug.fams_version.minor) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

433

for (dc_pipe_idx = 0; dc_pipe_idx < dc->res_pool->pipe_count; dc_pipe_idx++) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

463

switch (dc->debug.fams_version.minor) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

472

for (dc_pipe_idx = 0; dc_pipe_idx < dc->res_pool->pipe_count; dc_pipe_idx++) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

476

switch (dc->debug.fams_version.minor) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

498

void dml21_build_fams2_programming(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

512

if (dc->debug.fams_version.major == 2) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

513

num_fams2_streams = dml21_build_fams2_stream_programming_v2(dc, context, dml_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

84

int dml21_find_dc_pipes_for_plane(const struct dc *in_dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

34

int dml21_find_dc_pipes_for_plane(const struct dc *in_dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

45

void dml21_handle_phantom_streams_planes(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

47

void dml21_build_fams2_programming(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c

48

bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h

13

struct dc;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h

31

bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c

134

if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c

135

context->bw_ctx.bw.dcn.clk.num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c

170

static bool dml21_check_mode_support(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c

19

static void dml21_populate_configuration_options(const struct dc *in_dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c

199

static bool dml21_mode_check_and_programming(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c

259

bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c

273

void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c

35

void dml21_init(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c

46

void dml21_reinit(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c

51

static void dml21_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c

91

num_pipes = dml21_find_dc_pipes_for_plane(dc, context, in_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.h

12

struct dc;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.h

26

void dml21_init(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.h

52

void dml21_reinit(const struct dc *in_dc, struct dml2_context *dml_ctx,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.h

54

bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.h

58

void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1014

ctx->config.callbacks.dc->res_pool,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1021

ctx->config.callbacks.dc->res_pool,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

764

ctx->config.callbacks.acquire_secondary_pipe_for_mpc_odm(ctx->config.callbacks.dc, state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

798

ctx->config.callbacks.acquire_secondary_pipe_for_mpc_odm(ctx->config.callbacks.dc, state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

985

ctx->config.callbacks.dc->res_pool,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

992

ctx->config.callbacks.dc->res_pool,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

126

ctx->config.svp_pstate.callbacks.release_dsc(&context->res_ctx, ctx->config.svp_pstate.callbacks.dc->res_pool, &pipe->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

742

ctx->config.svp_pstate.callbacks.dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

752

ctx->config.svp_pstate.callbacks.add_phantom_stream(ctx->config.svp_pstate.callbacks.dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

773

ctx->config.svp_pstate.callbacks.dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

806

ctx->config.svp_pstate.callbacks.add_phantom_plane(ctx->config.svp_pstate.callbacks.dc, phantom_stream, phantom_plane, state);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

863

if (!ctx->config.svp_pstate.callbacks.remove_phantom_plane(ctx->config.svp_pstate.callbacks.dc, stream, del_planes[i], context))

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

865

ctx->config.svp_pstate.callbacks.release_phantom_plane(ctx->config.svp_pstate.callbacks.dc, context, del_planes[i]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

884

ctx->config.svp_pstate.callbacks.remove_phantom_stream(ctx->config.svp_pstate.callbacks.dc, state, phantom_stream);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

885

ctx->config.svp_pstate.callbacks.release_phantom_stream(ctx->config.svp_pstate.callbacks.dc, state, phantom_stream);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

246

void dml2_init_socbb_params(struct dml2_context *dml2, const struct dc *in_dc, struct soc_bounding_box_st *out)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

330

void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

34

void dml2_init_ip_params(struct dml2_context *dml2, const struct dc *in_dc, struct ip_params_st *out)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

616

void dml2_translate_ip_params(const struct dc *in, struct ip_params_st *out)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

685

void dml2_translate_socbb_params(const struct dc *in, struct soc_bounding_box_st *out)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

719

void dml2_translate_soc_states(const struct dc *dc, struct soc_states_st *out, int num_states)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

725

out->state_array[i].dcfclk_mhz = dc->dml.soc.clock_limits[i].dcfclk_mhz;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

726

out->state_array[i].dispclk_mhz = dc->dml.soc.clock_limits[i].dispclk_mhz;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

727

out->state_array[i].dppclk_mhz = dc->dml.soc.clock_limits[i].dppclk_mhz;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

728

out->state_array[i].dram_speed_mts = dc->dml.soc.clock_limits[i].dram_speed_mts;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

729

out->state_array[i].dtbclk_mhz = dc->dml.soc.clock_limits[i].dtbclk_mhz;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

730

out->state_array[i].socclk_mhz = dc->dml.soc.clock_limits[i].socclk_mhz;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

731

out->state_array[i].fabricclk_mhz = dc->dml.soc.clock_limits[i].fabricclk_mhz;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

732

out->state_array[i].dscclk_mhz = dc->dml.soc.clock_limits[i].dscclk_mhz;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

733

out->state_array[i].phyclk_d18_mhz = dc->dml.soc.clock_limits[i].phyclk_d18_mhz;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

734

out->state_array[i].phyclk_d32_mhz = dc->dml.soc.clock_limits[i].phyclk_d32_mhz;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

735

out->state_array[i].phyclk_mhz = dc->dml.soc.clock_limits[i].phyclk_mhz;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

736

out->state_array[i].sr_enter_plus_exit_time_us = dc->dml.soc.sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

737

out->state_array[i].sr_exit_time_us = dc->dml.soc.sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

738

out->state_array[i].fclk_change_latency_us = dc->dml.soc.fclk_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

739

out->state_array[i].dram_clock_change_latency_us = dc->dml.soc.dram_clock_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

740

out->state_array[i].usr_retraining_latency_us = dc->dml.soc.usr_retraining_latency_us;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

741

out->state_array[i].writeback_latency_us = dc->dml.soc.writeback_latency_us;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

745

out->state_array[i].sr_exit_z8_time_us = dc->dml.soc.sr_exit_z8_time_us;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

746

out->state_array[i].sr_enter_plus_exit_z8_time_us = dc->dml.soc.sr_enter_plus_exit_z8_time_us;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

750

out->state_array[i].urgent_latency_pixel_data_only_us = dc->dml.soc.urgent_latency_pixel_data_only_us;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

751

out->state_array[i].urgent_latency_pixel_mixed_with_vm_data_us = dc->dml.soc.urgent_latency_pixel_mixed_with_vm_data_us;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

752

out->state_array[i].urgent_latency_vm_data_only_us = dc->dml.soc.urgent_latency_vm_data_only_us;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

753

out->state_array[i].urgent_latency_adjustment_fabric_clock_component_us = dc->dml.soc.urgent_latency_adjustment_fabric_clock_component_us;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

754

out->state_array[i].urgent_latency_adjustment_fabric_clock_reference_mhz = dc->dml.soc.urgent_latency_adjustment_fabric_clock_reference_mhz;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.h

30

void dml2_init_ip_params(struct dml2_context *dml2, const struct dc *in_dc, struct ip_params_st *out);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.h

31

void dml2_init_socbb_params(struct dml2_context *dml2, const struct dc *in_dc, struct soc_bounding_box_st *out);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.h

32

void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.h

34

void dml2_translate_ip_params(const struct dc *in_dc, struct ip_params_st *out);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.h

35

void dml2_translate_socbb_params(const struct dc *in_dc, struct soc_bounding_box_st *out);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.h

36

void dml2_translate_soc_states(const struct dc *in_dc, struct soc_states_st *out, int num_states);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

169

bool is_dtbclk_required(const struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

173

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

282

void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state, struct dml2_context *in_ctx, unsigned int pipe_cnt)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

296

if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

297

context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

372

if (dc->config.forced_clocks || dc->debug.max_disp_clk) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.h

122

void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state, struct dml2_context *in_ctx, unsigned int pipe_cnt);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.h

31

struct dc;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.h

45

bool is_dtbclk_required(const struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.h

96

enum dc_status dml2_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c

122

void dml2_reinit(const struct dc *in_dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c

27

bool dml2_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c

51

static void dml2_init(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c

93

bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

115

struct dc *dc;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

117

struct dc_stream_state* (*create_phantom_stream)(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

120

struct dc_plane_state* (*create_phantom_plane)(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

123

enum dc_status (*add_phantom_stream)(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

127

bool (*add_phantom_plane)(const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

128

bool (*remove_phantom_plane)(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

132

enum dc_status (*remove_phantom_stream)(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

135

void (*release_phantom_plane)(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

138

void (*release_phantom_stream)(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

146

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

149

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

152

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

260

bool dml2_create(const struct dc *in_dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

269

void dml2_reinit(const struct dc *in_dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

297

bool dml2_validate(const struct dc *in_dc,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

310

void dml2_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

312

void dml2_apply_debug_options(const struct dc *dc, struct dml2_context *dml2);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

314

bool dml2_validate_and_build_resource(const struct dc *in_dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

36

struct dc;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

73

struct dc *dc;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

76

bool (*can_support_mclk_switch_using_fw_based_vblank_stretch)(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

77

bool (*acquire_secondary_pipe_for_mpc_odm)(const struct dc *dc, struct dc_state *state, struct pipe_ctx *pri_pipe, struct pipe_ctx *sec_pipe, bool odm);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

372

if (!context->streams[0]->sink->link->dc->caps.is_apu) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

384

if (!context->streams[0]->sink->link->dc->caps.is_apu) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

39

void initialize_dml2_ip_params(struct dml2_context *dml2, const struct dc *in_dc, struct ip_params_st *out)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

392

if (!context->streams[0]->sink->link->dc->caps.is_apu) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

401

bool dml2_validate_and_build_resource(const struct dc *in_dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

47

void initialize_dml2_soc_bbox(struct dml2_context *dml2, const struct dc *in_dc, struct soc_bounding_box_st *out)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

490

if (context->streams[0]->sink->link->dc->caps.is_apu)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

544

void dml2_apply_debug_options(const struct dc *dc, struct dml2_context *dml2)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

546

if (dc->debug.override_odm_optimization) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

547

dml2->config.minimize_dispclk_using_odm = dc->debug.minimize_dispclk_using_odm;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

558

void dml2_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

56

const struct dc *in_dc, const struct soc_bounding_box_st *in_bbox, struct soc_states_st *out)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.h

14

struct dc;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.h

19

void initialize_dml2_ip_params(struct dml2_context *dml2, const struct dc *in_dc, struct ip_params_st *out);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.h

20

void initialize_dml2_soc_bbox(struct dml2_context *dml2, const struct dc *in_dc, struct soc_bounding_box_st *out);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.h

22

const struct dc *in_dc, const struct soc_bounding_box_st *in_bbox, struct soc_states_st *out);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

137

dpp->ctx->dc->debug.max_downscale_src_width != 0 &&

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

138

scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

174

if (!dpp->ctx->dc->debug.always_scale) {

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

168

if (dpp->base.ctx->dc->debug.enable_mem_low_power.bits.dscl) {

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

169

dpp->base.ctx->dc->optimized_required = true;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

468

if (dpp->base.ctx->dc->debug.use_max_lb) {

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

619

dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

630

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl) {

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

659

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl)

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

57

if (dpp_base->ctx->dc->debug.cm_in_bypass)

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

203

dpp->ctx->dc->debug.max_downscale_src_width != 0 &&

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

204

scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

251

if (!dpp->ctx->dc->debug.always_scale) {

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1239

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1434

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

487

dpp->ctx->dc->debug.max_downscale_src_width != 0 &&

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

488

scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

531

if (!dpp->ctx->dc->debug.always_scale) {

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

602

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

608

dpp_base->ctx->dc->optimized_required = true;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

620

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

626

dpp_base->ctx->dc->optimized_required = true;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

638

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

644

dpp_base->ctx->dc->optimized_required = true;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

133

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

136

if (dpp_base->ctx->dc->caps.ips_v2_support)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

141

dpp_base->ctx->dc->optimized_required = true;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

231

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

51

if (dpp_base->ctx->dc->debug.cm_in_bypass)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1052

if (dpp_base->ctx->dc->caps.ips_v2_support) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1083

dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1112

if ((dpp->base.ctx->dc->config.use_spl) && (!dpp->base.ctx->dc->debug.disable_spl)) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1122

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1151

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1161

if (dpp->base.ctx->dc->config.prefer_easf)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1201

if (dpp->base.ctx->dc->config.prefer_easf)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

158

if (dpp->base.ctx->dc->caps.ips_v2_support) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

166

if (dpp->base.ctx->dc->debug.enable_mem_low_power.bits.dscl) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

167

dpp->base.ctx->dc->optimized_required = true;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

294

if ((dpp->base.ctx->dc->config.use_spl) && (!dpp->base.ctx->dc->debug.disable_spl)) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

480

if (dpp->base.ctx->dc->debug.use_max_lb) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

527

if ((dpp->base.ctx->dc->config.use_spl) && (!dpp->base.ctx->dc->debug.disable_spl)) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

966

if (dpp_base->ctx->dc->caps.ips_v2_support) {

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1062

struct dc *dc;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1064

if (!dsc || !dsc->ctx || !dsc->ctx->dc || !dsc->funcs->dsc_get_single_enc_caps)

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1067

dc = dsc->ctx->dc;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1069

if (!dc->clk_mgr || !dc->clk_mgr->funcs->get_max_clock_khz || !dc->res_pool || dc->debug.disable_dsc)

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1073

max_dscclk_khz = dc->clk_mgr->funcs->get_max_clock_khz(dc->clk_mgr, CLK_TYPE_DSCCLK);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1087

max_odm_combine_factor = dc->caps.max_odm_combine_factor;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1088

num_dsc = dc->res_pool->res_cap->num_dsc;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1112

if (dsc && dsc->ctx->dc) {

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1113

if (dsc->ctx->dc->clk_mgr &&

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1114

dsc->ctx->dc->clk_mgr->funcs->get_max_clock_khz) {

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1116

max_dispclk_khz = dsc->ctx->dc->clk_mgr->funcs->get_max_clock_khz(dsc->ctx->dc->clk_mgr, CLK_TYPE_DISPCLK);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1142

if (!dsc || !dsc->ctx || !dsc->ctx->dc || dsc->ctx->dc->debug.disable_dsc)

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

2158

void dc_dsc_get_default_config_option(const struct dc *dc, struct dc_dsc_config_options *options)

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

2160

options->dsc_min_slice_height_override = dc->debug.dsc_min_slice_height_override;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

2161

options->dsc_force_odm_hslice_override = dc->debug.force_odm_combine;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

701

bool dc_dsc_parse_dsc_dpcd(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

769

if (dc->debug.dsc_bpp_increment_div) {

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

774

if (dc->debug.dsc_bpp_increment_div >= 1)

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

776

if (dc->debug.dsc_bpp_increment_div >= 2)

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

778

if (dc->debug.dsc_bpp_increment_div >= 4)

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

780

if (dc->debug.dsc_bpp_increment_div >= 8)

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

782

if (dc->debug.dsc_bpp_increment_div >= 16)

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

823

bool dc_dsc_parse_dsc_edid(const struct dc *dc, const struct dc_edid_caps *edid_caps,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

826

(void)dc;

drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c

178

i2c_command.speed = link->ddc->ctx->dc->caps.i2c_speed_in_khz;

drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_link_encoder.c

49

if (enc->ctx->dc->caps.ips_v2_support) {

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

609

hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

830

struct dc *dc = hubbub1->base.ctx->dc;

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

840

if (dc->debug.disable_dcc == DCC_DISABLE)

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

883

if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

470

struct dc;

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

221

struct dc *dc = hubbub->ctx->dc;

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

230

if (dc->debug.disable_dcc == DCC_DISABLE)

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

279

if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

615

if (hubbub1->base.ctx->dc->clk_mgr->clks.prev_p_state_change_support == true &&

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

616

hubbub1->base.ctx->dc->clk_mgr->clks.p_state_change_support == false)

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

626

hubbub->funcs->allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);

drivers/gpu/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c

73

hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

135

if (!hubbub1->base.ctx->dc->config.skip_riommu_prefetch_wa) {

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

613

hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

132

if (safe_to_lower || hubbub->ctx->dc->debug.disable_stutter)

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

133

hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

280

struct dc *dc = hubbub->ctx->dc;

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

289

if (dc->debug.disable_dcc == DCC_DISABLE)

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

338

if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

382

uint32_t refclk_mhz = hubbub->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

1044

if (hubbub->ctx->dc->debug.disable_clock_gate) {

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

753

if (safe_to_lower || hubbub->ctx->dc->debug.disable_stutter)

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

754

hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

808

struct dc *dc = hubbub->ctx->dc;

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

816

if (dc->debug.disable_dcc == DCC_DISABLE)

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

865

if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

766

struct dc *dc = hubbub->ctx->dc;

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

769

if (!safe_to_lower && dc->debug.disable_stutter_for_wm_program &&

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

770

(ASICREV_IS_GC_11_0_0(dc->ctx->asic_id.hw_internal_rev) ||

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

771

ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev))) {

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

810

hubbub1_allow_self_refresh_control(hubbub, !dc->debug.disable_stutter);

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

812

if (dc->debug.disable_stutter_for_wm_program &&

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

813

(ASICREV_IS_GC_11_0_0(dc->ctx->asic_id.hw_internal_rev) ||

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

814

ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev))) {

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

817

} else if (dc->debug.disable_stutter) {

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

818

hubbub1_allow_self_refresh_control(hubbub, !dc->debug.disable_stutter);

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

821

hubbub32_force_usr_retraining_allow(hubbub, dc->debug.force_usr_allow);

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

970

uint32_t refclk_mhz = hubbub->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

994

if (hubbub->ctx->dc->debug.disable_clock_gate) {

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

330

if (safe_to_lower || hubbub->ctx->dc->debug.disable_stutter)

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

331

hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

333

hubbub32_force_usr_retraining_allow(hubbub, hubbub->ctx->dc->debug.force_usr_allow);

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

522

if (hubbub->ctx->dc->debug.disable_clock_gate) {

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

531

hubbub->ctx->dc->debug.enable_fine_grain_clock_gating

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

493

hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

495

hubbub32_force_usr_retraining_allow(hubbub, hubbub->ctx->dc->debug.force_usr_allow);

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

837

struct dc *dc = hubbub->ctx->dc;

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

838

const int max_dcc_plane_width = (int)dc->caps.dcc_plane_width_limit;

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

850

if (dc->debug.disable_dcc == DCC_DISABLE)

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

977

if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&

drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c

451

if (!safe_to_lower && hubbub->ctx->dc->debug.disable_stutter_for_wm_program) {

drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c

479

if (safe_to_lower || hubbub->ctx->dc->debug.disable_stutter)

drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c

480

hubbub42_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);

drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c

481

if (safe_to_lower && hubbub->ctx->dc->debug.disable_stutter_for_wm_program) {

drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c

484

hubbub32_force_usr_retraining_allow(hubbub, hubbub->ctx->dc->debug.force_usr_allow);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

794

if (hubp->ctx->dc->debug.enable_dmcub_surface_flip && address->type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

52

hubp35_set_fgcg(hubp, hubp->ctx->dc->debug.enable_fine_grain_clock_gating.bits.dchub);

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

30

hubp42_set_fgcg(hubp, hubp->ctx->dc->debug.enable_fine_grain_clock_gating.bits.dchub);

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

47

void dce_pipe_control_lock(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

53

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

89

void dce60_pipe_control_lock(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1293

void dce_pipe_control_lock(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1301

void dce60_pipe_control_lock(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

109

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

112

dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

114

dc->clk_mgr->funcs->update_clocks(

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

115

dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

121

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

124

dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

126

dc->clk_mgr->funcs->update_clocks(

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

127

dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

134

void dce100_hw_sequencer_construct(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

136

dce110_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

138

dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating;

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

139

dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

140

dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

141

dc->hwss.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling;

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

73

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

80

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h

32

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h

35

void dce100_hw_sequencer_construct(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h

38

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h

42

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h

45

bool dce100_enable_display_power_gating(struct dc *dc, uint8_t controller_id,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1058

if (!link->dc->config.edp_no_power_sequencing)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1066

ctx->dc->link_srv->edp_receiver_ready_T7(link);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1075

if (ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1076

ctx->dc->debug.dmub_command_table) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1090

!link->dc->config.edp_no_power_sequencing &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1099

ctx->dc->link_srv->edp_backlight_enable_aux(link, enable);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1103

if (!link->dc->config.edp_no_power_sequencing)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1111

ctx->dc->link_srv->edp_add_delay_for_T9(link);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1127

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1138

dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1139

clk_mgr = dc->clk_mgr;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1148

if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1167

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1177

dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1178

clk_mgr = dc->clk_mgr;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1205

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1207

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1214

if (!dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1227

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1234

dc->hwss.disable_audio_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1238

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1245

if (!(dc->ctx->dce_version >= DCN_VERSION_3_5)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1266

struct dce_hwseq *hws = link->dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1284

struct dce_hwseq *hws = link->dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1292

link->dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1295

if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1312

!link->dc->config.edp_no_power_sequencing) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1320

link->dc->link_srv->edp_receiver_ready_T9(link);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1327

if (link->dc->res_pool->dccg &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1328

link->dc->res_pool->dccg->funcs->set_hdmistreamclk) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1329

link->dc->res_pool->dccg->funcs->set_hdmistreamclk(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1330

link->dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1391

dp_link_info->encoding = link->dc->link_srv->dp_get_encoding_format(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1404

link->dc->link_srv->dp_is_fec_supported(link)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1590

static void program_scaler(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1599

if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1602

color_space_to_black_color(dc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1632

struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1636

struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1643

color_space_to_black_color(dc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1658

dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1698

struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1705

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1711

hws->funcs.disable_stream_gating(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1729

if (dc->config.disable_hbr_audio_dp2)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1731

dc->link_srv->dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1736

if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1737

check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1769

if (!(hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1773

hws->funcs.enable_stream_timing(pipe_ctx, context, dc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1776

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1800

dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1808

((link->dc->config.smart_mux_version && link->dc->is_switch_in_progress_dest)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1812

dc->link_srv->set_dsc_enable(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1816

dc->link_srv->set_dpms_on(context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1823

if (hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1825

hws->funcs.enable_stream_timing(pipe_ctx, context, dc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1843

static void power_down_encoders(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1847

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1848

struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1852

dc->link_srv->blank_dp_stream(link, false);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1872

static void power_down_controllers(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1876

for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1877

dc->res_pool->timing_generators[i]->funcs->disable_crtc(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1878

dc->res_pool->timing_generators[i]);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1882

static void power_down_clock_sources(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1886

if (dc->res_pool->dp_clock_source->funcs->cs_power_down(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1887

dc->res_pool->dp_clock_source) == false)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1890

for (i = 0; i < dc->res_pool->clk_src_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1891

if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1892

dc->res_pool->clock_sources[i]) == false)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1897

static void power_down_all_hw_blocks(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1899

power_down_encoders(dc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1901

power_down_controllers(dc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1903

power_down_clock_sources(dc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1905

if (dc->fbc_compressor)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1906

dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1910

struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1914

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1916

if (dc->caps.ips_support)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1919

for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1920

tg = dc->res_pool->timing_generators[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1925

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1931

dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1932

dc->hwss.disable_plane(dc, dc->current_state,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1933

&dc->current_state->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1955

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1963

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1964

if (dc->links[i]->local_sink &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1965

dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1966

edp_links_with_sink[*edp_with_sink_num] = dc->links[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1973

static void clean_up_dsc_blocks(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1978

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1979

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1982

if (!dc->caps.is_apu ||

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1983

dc->ctx->dce_version < DCN_VERSION_3_15)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1986

for (i = 0; i < (unsigned int)dc->res_pool->res_cap->num_dsc; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1989

dsc = dc->res_pool->dscs[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1993

if (i < dc->res_pool->timing_generator_count) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1994

tg = dc->res_pool->timing_generators[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1999

if (i < dc->res_pool->stream_enc_count) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2000

se = dc->res_pool->stream_enc[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2019

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2024

if (dc->debug.enable_otg_frame_sync_pwa == 0)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2035

DC_LOGGER_INIT(dc->ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2054

void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2062

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2071

struct dc_bios *dcb = dc->ctx->dc_bios;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2072

DC_LOGGER_INIT(dc->ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2074

get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2075

dc_get_edp_links(dc, edp_links, &edp_num);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2078

hws->funcs.init_pipes(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2083

if (edp_num && edp_stream_num && dc->ctx->dce_version > DCE_VERSION_10_0) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2094

can_apply_edp_fast_boot = dc_validate_boot_timing(dc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

210

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2100

if (dc->is_switch_in_progress_dest && edp_link->is_dds)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2113

dc->res_pool->dccg->funcs->get_pixel_rate_div(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2114

dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2123

dc_hwss_enable_otg_pwa(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2149

keep_edp_vdd_on |= dc->is_switch_in_progress_dest;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2158

clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2160

power_down_all_hw_blocks(dc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

217

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2172

clean_up_dsc_blocks(dc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2174

disable_vga_and_power_gate_all_controllers(dc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2176

dc->hwss.edp_power_control(edp_link_with_sink, false);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2178

clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

218

unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2180

bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2203

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2207

unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2217

dc->bw_vbios->blackout_duration, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2339

struct dc *dc = pipe_ctx[0]->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2341

if (dc->fbc_compressor)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2354

static bool should_enable_fbc(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2361

unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2364

ASSERT(dc->fbc_compressor);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2367

if (!dc->ctx->fbc_gpu_addr)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2374

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2387

if (i == dc->res_pool->pipe_count)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2420

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2425

if (should_enable_fbc(dc, context, &pipe_idx)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2428

struct compressor *compr = dc->fbc_compressor;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2434

compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2444

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2453

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2473

dc->link_srv->set_dpms_off(pipe_ctx_old);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2482

if (dc->caps.dynamic_audio == true) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2485

update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2501

pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2504

dc->res_pool,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2508

dc->hwss.disable_plane(dc, dc->current_state, pipe_ctx_old);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2516

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2540

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2556

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2558

dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2564

dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2565

dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2569

dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2570

dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2590

if (i == dc->res_pool->pipe_count) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2591

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2609

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2612

dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2614

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2617

dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2618

dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2622

dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2623

dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2646

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2649

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2650

struct dc_bios *dcb = dc->ctx->dc_bios;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2653

bool was_hpo_acquired = resource_is_hpo_acquired(dc->current_state);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2657

if (dc->config.use_pipe_ctx_sync_logic)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2658

reset_syncd_pipes_from_disabled_pipes(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2662

hws->funcs.reset_hw_ctx_wrap(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2672

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2674

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2682

dce_crtc_switch_to_clk_src(dc->hwseq,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2688

dc, (uint8_t)i, dc->ctx->dc_bios,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2692

if (dc->fbc_compressor)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2693

dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2695

dce110_setup_audio_dto(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2697

if (dc->hwseq->funcs.setup_hpo_hw_control && was_hpo_acquired != is_hpo_acquired) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2698

dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, is_hpo_acquired);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2701

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2703

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2723

dc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2730

hws->funcs.resync_fifo_dccg_dio(hws, dc, context, i);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2735

if (dc->debug.enable_otg_frame_sync_pwa && context->stream_count == 1) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2737

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2741

dc_hwss_enable_otg_pwa(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2746

if (dc->fbc_compressor)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2747

enable_fbc(dc, dc->current_state);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2798

static void program_surface_visibility(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2821

dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2844

static void update_plane_addr(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2847

(void)dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

286

dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2883

void dce110_power_down(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2885

power_down_all_hw_blocks(dc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2886

disable_vga_and_power_gate_all_controllers(dc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

289

(void)dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2928

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2938

DC_LOGGER_INIT(dc->ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2977

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2983

DC_LOGGER_INIT(dc->ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3009

static void dce110_init_pipes(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3012

(void)dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3016

static void dce110_init_hw(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3023

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3027

bp = dc->ctx->dc_bios;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3028

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3029

xfm = dc->res_pool->transforms[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3033

dc, (uint8_t)i, bp,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3036

dc, (uint8_t)i, bp,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3039

dc->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3043

dce_clock_gating_power_up(dc->hwseq, false);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3046

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3051

struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3056

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3057

struct timing_generator *tg = dc->res_pool->timing_generators[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3067

for (i = 0; i < dc->res_pool->audio_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3068

struct audio *audio = dc->res_pool->audios[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3072

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3073

struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3081

abm = dc->res_pool->abm;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3085

dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3089

if (dc->fbc_compressor)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3090

dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3096

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3099

struct clk_mgr *dccg = dc->clk_mgr;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3101

dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3110

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3113

struct clk_mgr *dccg = dc->clk_mgr;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3115

dce110_set_displaymarks(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3125

struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3132

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3139

dce_enable_fe_clock(dc->hwseq, mi->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3167

program_scaler(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3180

if (dc->config.gpu_vm_support)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3191

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3194

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3235

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3245

if (dc->fbc_compressor)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3246

dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3248

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3262

dce110_program_front_end_for_pipe(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3264

dc->hwss.update_plane_addr(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3266

program_surface_visibility(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3270

if (dc->fbc_compressor)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3271

enable_fbc(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3275

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3278

(void)dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3282

static void dce110_power_down_fe(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3285

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3290

if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3294

dc, (uint8_t)fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3296

dc->res_pool->transforms[fe_idx]->funcs->transform_reset(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3297

dc->res_pool->transforms[fe_idx]);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3301

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3305

(void)dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3311

static void program_output_csc(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3317

(void)dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3344

.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3408

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3411

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3506

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3507

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3509

link->dc->current_state->res_ctx.pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3511

link->dc->res_pool->dp_clock_source;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3521

link->dc->hwss.edp_wait_for_hpd_ready(link, true);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3540

dc->link_srv->dp_get_encoding_format(link_settings),

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3551

if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3552

if (dc->clk_mgr->funcs->notify_link_rate_change)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3553

dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3568

dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_LINK_PHY);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3575

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3577

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3580

link->dc->hwss.edp_backlight_control &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3582

link->dc->hwss.edp_backlight_control(link, false);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3595

dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3661

void dce110_hw_sequencer_construct(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3663

dc->hwss = dce110_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3664

dc->hwseq->funcs = dce110_private_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

610

dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

613

(void)dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

672

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

694

DC_LOGGER_INIT(dc->ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

727

const struct dc *dc = link->dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

735

dc->hwss.update_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

809

if (!(link->dc->link_srv->get_hpd_state(link) ^ power_up)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

851

ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link)), 1000000);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

856

ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link)), 1000000);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

862

ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link),

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

863

ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link),

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

878

if (ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link) != 0) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

917

if (ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

918

ctx->dc->debug.dmub_command_table) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

938

ctx->dc->link_srv->dp_trace_set_edp_power_timestamp(link, power_up);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

943

ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link),

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

944

ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link));

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

972

ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link) != 0) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

979

ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link)), 1000000);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

122

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

32

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

36

void dce110_hw_sequencer_construct(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

39

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

45

struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

62

void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

64

void dce110_power_down(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

71

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

75

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

114

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

121

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

152

void dce112_hw_sequencer_construct(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

157

dce110_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

158

dc->hwseq->funcs.enable_display_power_gating = dce112_enable_display_power_gating;

drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.h

32

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.h

34

void dce112_hw_sequencer_construct(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

152

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

157

(void)dc;

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

165

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

264

void dce120_hw_sequencer_construct(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

269

dce110_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

270

dc->hwseq->funcs.enable_display_power_gating = dce120_enable_display_power_gating;

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

271

dc->hwss.update_dchub = dce120_update_dchub;

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

272

dc->hwss.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling;

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.h

32

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.h

35

void dce120_hw_sequencer_construct(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

115

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

120

if (dce60_should_enable_fbc(dc, context, &pipe_idx)) {

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

123

struct compressor *compr = dc->fbc_compressor;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

129

compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

181

static void dce60_program_surface_visibility(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

232

static void dce60_program_scaler(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

239

if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

242

color_space_to_black_color(dc,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

271

struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

278

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

286

dce_enable_fe_clock(dc->hwseq, mi->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

314

dce60_program_scaler(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

327

if (dc->config.gpu_vm_support)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

338

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

341

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

382

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

392

if (dc->fbc_compressor)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

393

dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

395

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

409

dce60_program_front_end_for_pipe(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

411

dc->hwss.update_plane_addr(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

413

dce60_program_surface_visibility(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

417

if (dc->fbc_compressor)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

418

dce60_enable_fbc(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

421

void dce60_hw_sequencer_construct(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

423

dce110_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

425

dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

426

dc->hwss.apply_ctx_for_surface = dce60_apply_ctx_for_surface;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

427

dc->hwss.cursor_lock = dce60_pipe_control_lock;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

428

dc->hwss.pipe_control_lock = dce60_pipe_control_lock;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

429

dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

430

dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

431

dc->hwss.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

50

static bool dce60_should_enable_fbc(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

57

unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

60

ASSERT(dc->fbc_compressor);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

63

if (!dc->ctx->fbc_gpu_addr)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

70

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

86

if (i == dc->res_pool->pipe_count)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.h

32

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.h

34

void dce60_hw_sequencer_construct(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c

45

void dce80_hw_sequencer_construct(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c

47

dce110_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c

49

dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating;

drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c

50

dc->hwss.pipe_control_lock = dce_pipe_control_lock;

drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c

51

dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;

drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c

52

dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;

drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c

53

dc->hwss.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling;

drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.h

32

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.h

34

void dce80_hw_sequencer_construct(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1008

if (hws->ctx->dc->debug.disable_hubp_power_gate)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

103

void dcn10_wait_for_pipe_update_if_needed(struct dc *dc, struct pipe_ctx *pipe_ctx, bool is_surface_update_only)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1078

static void undo_DEGVIDCN10_253_wa(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1080

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1081

struct hubp *hubp = dc->res_pool->hubps[0];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1098

static void apply_DEGVIDCN10_253_wa(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1100

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1101

struct hubp *hubp = dc->res_pool->hubps[0];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1104

if (dc->debug.disable_stutter)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1110

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1111

if (!dc->res_pool->hubps[i]->power_gated)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1128

void dcn10_bios_golden_init(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1130

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1131

struct dc_bios *bp = dc->ctx->dc_bios;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1135

if (hws->funcs.s0i3_golden_init_wa && hws->funcs.s0i3_golden_init_wa(dc))

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1138

if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1140

dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1154

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1160

if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1162

dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub))

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1163

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1164

!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1169

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1176

if (!dc->hwseq->wa.false_optc_underflow)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1181

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1182

struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1187

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1226

struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1250

dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1288

color_space_to_black_color(dc, color_space, &black_color);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

129

dc->hwss.calc_vupdate_position(dc, pipe_ctx, &vupdate_start,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1307

false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

132

dc->hwss.get_position(&pipe_ctx, 1, &position);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1328

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1335

DC_LOGGER_INIT(dc->ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1349

dc->link_srv->set_dpms_off(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1351

dc->hwss.disable_audio_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1358

if (dc->caps.dynamic_audio == true) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1361

update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1374

dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1384

for (i = 0; i < dc->res_pool->pipe_count; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1385

if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1388

if (i == dc->res_pool->pipe_count)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1396

static bool dcn10_hw_wa_force_recovery(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1401

if (!dc->debug.recovery_enabled)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1413

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1415

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1424

hubbub1_soft_reset(dc->res_pool->hubbub, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1426

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1428

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1436

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1438

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1447

hubbub1_soft_reset(dc->res_pool->hubbub, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1448

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1450

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1462

void dcn10_verify_allow_pstate_change_high(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1464

struct hubbub *hubbub = dc->res_pool->hubbub;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1472

dcn10_log_hw_state(dc, NULL);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1476

if (dcn10_hw_wa_force_recovery(dc)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1485

void dcn10_plane_atomic_disconnect(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1489

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1492

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1510

dc->optimized_required = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1515

if (dc->debug.sanity_checks)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1516

hws->funcs.verify_allow_pstate_change_high(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1532

void dcn10_plane_atomic_power_down(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1536

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1537

DC_LOGGER_INIT(dc->ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1565

void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1567

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1572

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1584

dc->optimized_required = false; /* We're powering off, no need to optimize */

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1586

hws->funcs.plane_atomic_power_down(dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1598

void dcn10_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1601

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1602

DC_LOGGER_INIT(dc->ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1607

hws->funcs.plane_atomic_disable(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1609

apply_DEGVIDCN10_253_wa(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1615

void dcn10_init_pipes(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1618

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1619

struct hubbub *hubbub = dc->res_pool->hubbub;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1630

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1631

struct timing_generator *tg = dc->res_pool->timing_generators[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1646

hws->funcs.init_blank(dc, tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1657

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1659

struct hubp *hubp = dc->res_pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1674

for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1681

dc->res_pool->mpc->funcs->mpc_init_single_inst(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1682

dc->res_pool->mpc, i);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1685

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1686

struct timing_generator *tg = dc->res_pool->timing_generators[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1687

struct hubp *hubp = dc->res_pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1688

struct dpp *dpp = dc->res_pool->dpps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1710

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1725

dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1726

dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1727

dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1728

pipe_ctx->stream_res.opp = dc->res_pool->opps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1730

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1735

dc->hwss.disable_plane(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1749

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1751

if (dc->res_pool->opps[i]->mpc_tree_params.opp_list) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1752

if (dc->res_pool->opps[i]->mpc_tree_params.opp_list->mpcc_bot) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1753

int bot_id = dc->res_pool->opps[i]->mpc_tree_params.opp_list->mpcc_bot->mpcc_id;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1756

dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1774

for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1776

struct timing_generator *tg = dc->res_pool->timing_generators[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

179

void dcn10_set_wait_for_update_needed_for_pipe(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1791

for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1794

dc->res_pool->dscs[i]->funcs->dsc_read_state(dc->res_pool->dscs[i], &s);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1800

hws->funcs.dsc_pg_control(hws, dc->res_pool->dscs[i]->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1805

void dcn10_init_hw(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1808

struct abm *abm = dc->res_pool->abm;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1809

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1810

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1811

struct dc_bios *dcb = dc->ctx->dc_bios;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1812

struct resource_pool *res_pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1817

if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1818

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1821

if (dc->clk_mgr && dc->clk_mgr->clks.dispclk_khz != 0 && dc->clk_mgr->clks.dppclk_khz != 0) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1822

dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz = dc->clk_mgr->clks.dispclk_khz;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1823

dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz = dc->clk_mgr->clks.dppclk_khz;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1827

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1828

dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1831

hws->funcs.disable_vga(dc->hwseq);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1833

if (!dc_dmub_srv_optimized_init_done(dc->ctx->dmub_srv))

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1834

hws->funcs.bios_golden_init(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1837

if (dc->ctx->dc_bios->fw_info_valid) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1839

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1844

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1860

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1865

struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1881

dc->link_srv->blank_all_dp_displays(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1884

hws->funcs.enable_power_gating_plane(dc->hwseq, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1892

if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1894

hws->funcs.init_pipes(dc, dc->current_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1895

if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1896

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1897

!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1909

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

191

dc->hwss.get_position(&pipe_ctx, 1, &position);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1910

struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1930

if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1931

dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1933

if (!dc->debug.disable_clock_gate) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1935

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1936

dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

194

dc->hwss.calc_vupdate_position(dc, pipe_ctx, &vupdate_start,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1941

if (dc->clk_mgr && dc->clk_mgr->funcs->notify_wm_ranges)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1942

dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1950

void dcn10_power_down_on_boot(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1957

dc_get_edp_links(dc, edp_links, &edp_num);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1963

dc->hwseq->funcs.edp_backlight_control &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1964

dc->hwseq->funcs.power_down &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1965

dc->hwss.edp_power_control) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1966

dc->hwseq->funcs.edp_backlight_control(edp_link, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1967

dc->hwseq->funcs.power_down(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1968

dc->hwss.edp_power_control(edp_link, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1970

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1971

struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1975

dc->hwseq->funcs.power_down) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1976

dc->hwseq->funcs.power_down(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1988

if (dc->clk_mgr->funcs->set_low_power_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1989

dc->clk_mgr->funcs->set_low_power_state(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1993

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1997

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2000

for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2002

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2015

dcn10_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2017

hws->funcs.enable_stream_gating(dc, pipe_ctx_old);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2052

void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2054

(void)dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2078

bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2081

(void)dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2091

if (!dpp_base->ctx->dc->debug.always_use_regamma

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2157

bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2177

else if (cm_helper_translate_curve_to_hw_format(dc->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2196

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2200

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2208

if (dc->debug.sanity_checks)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2209

hws->funcs.verify_allow_pstate_change_high(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2216

if (dc->debug.sanity_checks)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2217

hws->funcs.verify_allow_pstate_change_high(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

223

void dcn10_lock_all_pipes(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2238

static void delay_cursor_until_vupdate(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2246

if (!dc->hwss.calc_vupdate_position || !dc->hwss.get_position)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2252

dc->hwss.calc_vupdate_position(dc, pipe_ctx, &vupdate_start,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2255

dc->hwss.get_position(&pipe_ctx, 1, &position);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2286

void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2294

delay_cursor_until_vupdate(dc, pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2296

if (pipe->stream && should_use_dmub_inbox1_lock(dc, pipe->stream->link)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2303

dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2308

dc->res_pool->mpc->funcs->cursor_lock(dc->res_pool->mpc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

232

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

233

old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2429

static int dcn10_align_pixel_clocks(struct dc *dc, int group_size,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2442

dc->res_pool->dp_clock_source->ctx->dc->clk_mgr->dprefclk_khz*10;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2444

DC_LOGGER_INIT(dc->ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2450

if (dc->config.vblank_alignment_dto_params &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2451

dc->res_pool->dp_clock_source->funcs->override_dp_pix_clk) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2453

(dc->config.vblank_alignment_dto_params >> 32) & 0x7FFF;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2455

(dc->config.vblank_alignment_dto_params >> 48) & 0x7FFF;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2457

dc->config.vblank_alignment_dto_params & 0xFFFFFFFF;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2463

dc->res_pool->dp_clock_source->funcs->get_dp_dto_frequency_100hz(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2464

dc->res_pool->dp_clock_source,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

249

dc->hwss.pipe_control_lock(dc, pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2498

dc->res_pool->dp_clock_source->funcs->override_dp_pix_clk(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2499

dc->res_pool->dp_clock_source,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2502

dc->res_pool->dp_clock_source->funcs->get_dp_dto_frequency_100hz(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2503

dc->res_pool->dp_clock_source,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

251

dc->hwss.pipe_control_lock(dc, pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2519

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2530

DC_LOGGER_INIT(dc->ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

255

static void log_mpc_crc(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2555

master = dcn10_align_pixel_clocks(dc, group_size, grouped_pipes);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2585

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

259

struct dc_context *dc_ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2597

DC_LOGGER_INIT(dc->ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

260

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2669

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2675

DC_LOGGER_INIT(dc->ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

270

static void dcn10_log_hubbub_state(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2729

dcn10_hubbub_read_fb_aperture(hws->ctx->dc->res_pool->hubbub, &fb_base_value, &fb_offset_value);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

273

struct dc_context *dc_ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2778

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

278

dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2783

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2785

if (dc->debug.sanity_checks) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2786

hws->funcs.verify_allow_pstate_change_high(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2789

undo_DEGVIDCN10_253_wa(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2791

power_on_plane_resources(dc->hwseq,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2802

if (dc->config.gpu_vm_support)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2805

if (dc->debug.sanity_checks) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2806

hws->funcs.verify_allow_pstate_change_high(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2874

void dcn10_program_output_csc(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2880

(void)dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2926

void dcn10_update_visual_confirm_color(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2930

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2937

void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2944

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2986

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

299

static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2996

if (dc->debug.sanity_checks)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2998

dc->res_pool->mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3001

new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3008

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

301

struct dc_context *dc_ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

302

struct resource_pool *pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3028

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3032

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3072

dc->clk_mgr->clks.dispclk_khz)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3077

dc->clk_mgr->clks.dispclk_khz / 2;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3084

if (dc->res_pool->dccg)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3085

dc->res_pool->dccg->funcs->update_dpp_dto(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3086

dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3090

dc->clk_mgr->clks.dppclk_khz = should_divided_by_2 ?

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3091

dc->clk_mgr->clks.dispclk_khz / 2 :

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3092

dc->clk_mgr->clks.dispclk_khz;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3123

hws->funcs.update_mpcc(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3143

if (dc->hwss.abort_cursor_offload_update)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3144

dc->hwss.abort_cursor_offload_update(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3146

dc->hwss.set_cursor_attribute(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3147

dc->hwss.set_cursor_position(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3149

if (dc->hwss.set_cursor_sdr_white_level)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3150

dc->hwss.set_cursor_sdr_white_level(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3155

dc->hwss.program_gamut_remap(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3157

dc->hwss.program_output_csc(dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3186

dc->hwss.update_plane_addr(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3193

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3204

color_space_to_black_color(dc, color_space, &black_color);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3224

dc->hwss.set_pipe(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3228

dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3255

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3259

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3276

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3278

hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3282

dcn10_enable_plane(dc, pipe_ctx, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3284

dcn10_update_dchubp_dpp(dc, pipe_ctx, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3291

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3300

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3303

void dcn10_wait_for_pending_cleared(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3310

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3336

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3341

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3350

false_optc_underflow_wa(dc, pipe_ctx->stream, tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3354

for (i = 0; i < dc->res_pool->pipe_count; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3356

dc->hwss.disable_plane(dc, dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3358

for (i = 0; i < dc->res_pool->pipe_count; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3360

dc->hwss.optimize_bandwidth(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3364

if (dc->hwseq->wa.DEGVIDCN10_254)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3365

hubbub1_wm_change_req_wa(dc->res_pool->hubbub);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3368

static void dcn10_stereo_hw_frame_pack_wa(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3378

hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3385

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3388

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3389

struct hubbub *hubbub = dc->res_pool->hubbub;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3392

if (dc->debug.sanity_checks)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3393

hws->funcs.verify_allow_pstate_change_high(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3398

dc->clk_mgr->funcs->update_clocks(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3399

dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3403

dc->optimized_required = hubbub->funcs->program_watermarks(hubbub,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3405

dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3407

dcn10_stereo_hw_frame_pack_wa(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3409

if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3412

dc, &min_fclk_khz, &min_dcfclk_khz, &socclk_khz);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3415

dc, min_fclk_khz, min_dcfclk_khz, socclk_khz);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3418

if (dc->debug.sanity_checks)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3419

hws->funcs.verify_allow_pstate_change_high(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3423

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3426

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3427

struct hubbub *hubbub = dc->res_pool->hubbub;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3430

if (dc->debug.sanity_checks)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3431

hws->funcs.verify_allow_pstate_change_high(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3436

dc->clk_mgr->funcs->update_clocks(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3437

dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3443

dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3446

dcn10_stereo_hw_frame_pack_wa(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3448

if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3451

dc, &min_fclk_khz, &min_dcfclk_khz, &socclk_khz);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3454

dc, min_fclk_khz, min_dcfclk_khz, socclk_khz);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3457

if (dc->debug.sanity_checks)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3458

hws->funcs.verify_allow_pstate_change_high(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3569

void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3577

if (!dc_set_generic_gpio_for_stereo(true, dc->ctx->gpio_service))

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3578

dc_set_generic_gpio_for_stereo(false, dc->ctx->gpio_service);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3580

dc_set_generic_gpio_for_stereo(false, dc->ctx->gpio_service);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3609

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3613

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3616

if (dc->debug.sanity_checks) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3617

hws->funcs.verify_allow_pstate_change_high(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3635

if (dc->debug.sanity_checks) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3636

hws->funcs.verify_allow_pstate_change_high(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3642

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3647

(void)dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3659

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3678

if (dc->hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3679

struct dce_hwseq *hwseq = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3680

struct timing_generator *wa_tg = dc->res_pool->timing_generators[0];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3684

struct hubbub *hubbub = dc->res_pool->hubbub;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3686

hubbub->funcs->allow_self_refresh_control(hubbub, !dc->debug.disable_stutter);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3694

struct hubbub *hubbub = hws->ctx->dc->res_pool->hubbub;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3707

.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4006

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4012

int vupdate_pos = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4022

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4036

vline_pos += dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4051

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4058

dcn10_cal_vline_position(dc, pipe_ctx, &start_line, &end_line);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4063

void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4066

int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4083

struct dce_hwseq *hws = link->dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4112

enum dc_status dcn10_set_clock(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4118

struct dc_state *context = dc->current_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4122

if (!dc->clk_mgr || !dc->clk_mgr->funcs->get_clock)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4125

dc->clk_mgr->funcs->get_clock(dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4145

if (dc->clk_mgr->funcs->update_clocks)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4146

dc->clk_mgr->funcs->update_clocks(dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4152

void dcn10_get_clock(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4156

struct dc_state *context = dc->current_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4158

if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4159

dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4163

void dcn10_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4165

struct resource_pool *pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

454

static void dcn10_log_color_state(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

458

struct dc_context *dc_ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

459

struct resource_pool *pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

528

dc->caps.color.dpp.input_lut_shared,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

529

dc->caps.color.dpp.icsc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

530

dc->caps.color.dpp.dgam_ram,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

531

dc->caps.color.dpp.dgam_rom_caps.srgb,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

532

dc->caps.color.dpp.dgam_rom_caps.bt2020,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

533

dc->caps.color.dpp.dgam_rom_caps.gamma2_2,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

534

dc->caps.color.dpp.dgam_rom_caps.pq,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

535

dc->caps.color.dpp.dgam_rom_caps.hlg,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

536

dc->caps.color.dpp.post_csc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

537

dc->caps.color.dpp.gamma_corr,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

538

dc->caps.color.dpp.dgam_rom_for_yuv,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

539

dc->caps.color.dpp.hw_3d_lut,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

540

dc->caps.color.dpp.ogam_ram,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

541

dc->caps.color.dpp.ocsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

556

dc->caps.color.mpc.gamut_remap,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

557

dc->caps.color.mpc.num_3dluts,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

558

dc->caps.color.mpc.ogam_ram,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

559

dc->caps.color.mpc.ocsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

616

void dcn10_log_hw_state(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

619

struct dc_context *dc_ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

620

struct resource_pool *pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

626

dcn10_log_hubbub_state(dc, log_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

628

dcn10_log_hubp_states(dc, log_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

630

if (dc->hwss.log_color_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

631

dc->hwss.log_color_state(dc, log_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

633

dcn10_log_color_state(dc, log_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

728

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

729

struct link_encoder *lenc = dc->links[i]->link_enc;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

748

dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

749

dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

750

dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

751

dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

752

dc->current_state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

753

dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

754

dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

756

log_mpc_crc(dc, log_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

762

struct hpo_frl_link_encoder *hpo_frl_link_enc = dc->links[i]->hpo_frl_link_enc;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

857

bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

859

(void)dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

90

const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

947

if (hws->ctx->dc->debug.disable_dpp_power_gate)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

104

void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

108

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

112

void dcn10_init_hw(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

113

void dcn10_init_pipes(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

114

void dcn10_power_down_on_boot(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

116

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

118

void dcn10_plane_atomic_disconnect(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

123

void dce110_power_down(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

124

void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

126

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

132

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

137

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

148

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

159

void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

161

void dcn10_log_hw_state(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

163

void dcn10_get_hw_state(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

167

void dcn10_clear_status_bits(struct dc *dc, unsigned int mask);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

169

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

187

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

189

enum dc_status dcn10_set_clock(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

193

void dcn10_get_clock(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

196

bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

197

void dcn10_bios_golden_init(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

198

void dcn10_plane_atomic_power_down(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

202

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

205

void dcn10_wait_for_pending_cleared(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

208

void dcn10_verify_allow_pstate_change_high(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

210

void dcn10_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

213

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

32

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

34

void dcn10_hw_sequencer_construct(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

38

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

42

void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

46

struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

48

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

51

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

54

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

58

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

61

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

64

void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

66

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

71

void dcn10_program_output_csc(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

76

bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

78

bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

80

void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

81

void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

83

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

85

void dcn10_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

87

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

91

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c

125

void dcn10_hw_sequencer_construct(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c

127

dc->hwss = dcn10_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c

128

dc->hwseq->funcs = dcn10_private_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.h

29

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.h

31

void dcn10_hw_sequencer_construct(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1000

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1022

bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1026

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1043

cm_helper_translate_curve_to_hw_format(dc->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1108

bool dcn20_set_input_transfer_func(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1112

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1184

void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1187

(void)dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1210

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1227

color_space_to_black_color(dc, color_space, &black_color);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1230

dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1232

if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1244

dc->hwss.set_disp_pattern_generator(dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1257

dc->hwss.set_disp_pattern_generator(dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1269

dc->hwss.set_pipe(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1307

void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1314

dcn20_power_on_plane_resources(dc->hwseq, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1364

if (dc->vm_pa_config.valid) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1369

apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1370

apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1388

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1440

dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1454

dcn20_setup_gsl_group_as_lock(dc, pipe, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1456

if (pipe->stream && should_use_dmub_inbox1_lock(dc, pipe->stream->link)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1466

dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1479

if (dc->hwseq->funcs.perform_3dlut_wa_unlock)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1480

dc->hwseq->funcs.perform_3dlut_wa_unlock(pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

152

dc->caps.color.dpp.input_lut_shared,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

153

dc->caps.color.dpp.icsc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

154

dc->caps.color.dpp.dgam_ram,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

155

dc->caps.color.dpp.dgam_rom_caps.srgb,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

156

dc->caps.color.dpp.dgam_rom_caps.bt2020,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

157

dc->caps.color.dpp.dgam_rom_caps.gamma2_2,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

158

dc->caps.color.dpp.dgam_rom_caps.pq,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

159

dc->caps.color.dpp.dgam_rom_caps.hlg,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

160

dc->caps.color.dpp.post_csc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

161

dc->caps.color.dpp.gamma_corr,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

162

dc->caps.color.dpp.dgam_rom_for_yuv,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

163

dc->caps.color.dpp.hw_3d_lut,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

164

dc->caps.color.dpp.ogam_ram,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

165

dc->caps.color.dpp.ocsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1676

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1680

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1684

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1766

hws->funcs.update_mpcc(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1782

(context == dc->current_state && plane_state->update_flags.bits.position_change) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1783

(context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1784

(context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1800

if (dc->hwss.abort_cursor_offload_update)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1801

dc->hwss.abort_cursor_offload_update(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1803

dc->hwss.set_cursor_attribute(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1804

dc->hwss.set_cursor_position(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1806

if (dc->hwss.set_cursor_sdr_white_level)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1807

dc->hwss.set_cursor_sdr_white_level(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1818

dc->hwss.program_gamut_remap(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1821

dc->hwss.program_output_csc(dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

185

dc->caps.color.mpc.gamut_remap,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

186

dc->caps.color.mpc.num_3dluts,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1861

params.subvp_save_surf_addr.dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1866

dc->hwss.update_plane_addr(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

187

dc->caps.color.mpc.ogam_ram,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

188

dc->caps.color.mpc.ocsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1903

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

192

static int find_free_gsl_group(const struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1923

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1927

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1931

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1938

hws->funcs.blank_pixel_data(dc, pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

194

if (dc->res_pool->gsl_groups.gsl_0 == 0)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1946

dcn20_program_tg(dc, pipe_ctx, context, hws);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1949

hws->funcs.update_odm(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1953

hws->funcs.enable_plane(dc, pipe_ctx, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1955

dcn20_enable_plane(dc, pipe_ctx, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1957

if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1958

dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

196

if (dc->res_pool->gsl_groups.gsl_1 == 0)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1962

if (dc->res_pool->hubbub->funcs->program_det_size)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1963

dc->res_pool->hubbub->funcs->program_det_size(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1964

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1966

if (dc->res_pool->hubbub->funcs->program_det_segments)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1967

dc->res_pool->hubbub->funcs->program_det_segments(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1968

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1974

dcn20_update_dchubp_dpp(dc, pipe_ctx, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

198

if (dc->res_pool->gsl_groups.gsl_2 == 0)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1985

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1994

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2019

dc->hwss.set_pipe(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2031

dc->hwss.set_disp_pattern_generator(dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2044

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2050

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2053

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2055

if (resource_is_pipe_topology_changed(dc->current_state, context))

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2056

resource_log_pipe_topology_update(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2058

if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2059

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2065

dc->hwss.program_triplebuffer(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2066

dc, pipe, pipe->plane_state->triplebuffer_flips);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2071

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2072

if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2079

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2080

dc->res_pool->hubbub->funcs->force_pstate_change_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2081

dc->res_pool->hubbub, true, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2086

for (i = 0; i < dc->res_pool->pipe_count; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2087

dcn20_detect_pipe_changes(dc->current_state, context, &dc->current_state->res_ctx.pipe_ctx[i],

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2093

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2094

struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2096

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2099

dc_state_get_pipe_subvp_type(dc->current_state, pipe) == SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2100

struct timing_generator *tg = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2103

if (dc->hwseq->funcs.blank_pixel_data)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2104

dc->hwseq->funcs.blank_pixel_data(dc, pipe, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2111

for (i = 0; i < dc->res_pool->pipe_count; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2116

hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2119

for (i = 0; i < dc->res_pool->pipe_count; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2122

struct hubbub *hubbub = dc->res_pool->hubbub;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2136

dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2137

if (dc->res_pool->hubbub->funcs->program_det_segments)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2138

dc->res_pool->hubbub->funcs->program_det_segments(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2139

hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2141

hws->funcs.plane_atomic_disconnect(dc, dc->current_state,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2142

&dc->current_state->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2143

DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2147

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2153

hws->funcs.update_odm(dc, context, pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2160

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2166

hws->funcs.program_pipe(dc, pipe, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2178

dcn20_program_pipe(dc, pipe, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2192

hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2199

dc->current_state->stream_status[0].plane_count == 1 &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

220

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2210

void dcn20_post_unlock_reset_opp(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2214

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2220

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, opp_head);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2225

if (dc->hwseq->funcs.dsc_pg_status)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2226

is_dsc_ungated = dc->hwseq->funcs.dsc_pg_status(dc->hwseq, dsc->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2244

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2250

struct dce_hwseq *hwseq = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2253

for (i = 0; i < dc->res_pool->pipe_count; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2254

if (resource_is_pipe_type(&dc->current_state->res_ctx.pipe_ctx[i], OPP_HEAD) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2256

dcn20_post_unlock_reset_opp(dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2257

&dc->current_state->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2259

for (i = 0; i < dc->res_pool->pipe_count; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2261

dc->hwss.disable_plane(dc, dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2269

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2283

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2285

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2305

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2306

dc->res_pool->hubbub->funcs->force_pstate_change_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2307

dc->res_pool->hubbub, false, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2309

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2323

if (dc->hwss.apply_update_flags_for_phantom)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2324

dc->hwss.apply_update_flags_for_phantom(pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2325

if (dc->hwss.update_phantom_vp_position)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2326

dc->hwss.update_phantom_vp_position(dc, context, pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2327

dcn20_program_pipe(dc, pipe, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2345

dc->hwseq->funcs.update_force_pstate(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2351

hwseq->funcs.program_mall_pipe_config(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2355

dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

236

group_idx = find_free_gsl_group(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2360

if (dc->current_state->stream_status[0].plane_count == 1 &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2363

struct timing_generator *tg = dc->res_pool->timing_generators[0];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2365

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2374

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2377

struct hubbub *hubbub = dc->res_pool->hubbub;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2382

dc->clk_mgr->funcs->update_clocks(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2383

dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2387

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2401

dc->optimized_required |= hubbub->funcs->program_watermarks(hubbub,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2403

dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2414

dc->optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.dml.ip.min_comp_buffer_size_kbytes);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2417

dc->optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.bw.dcn.compbuf_size_kb);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2425

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2428

struct hubbub *hubbub = dc->res_pool->hubbub;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2431

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

244

dc->res_pool->gsl_groups.gsl_0 = 1;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2444

dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2447

if (dc->clk_mgr->dc_mode_softmax_enabled) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2448

int softmax_memclk_khz = dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2450

if (dc->clk_mgr->clks.dramclk_khz > softmax_memclk_khz &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2452

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2460

dc_dmub_srv_p_state_delegate(dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2463

dc->clk_mgr->clks.fw_based_mclk_switching = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2465

dc->clk_mgr->clks.fw_based_mclk_switching = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2468

dc->clk_mgr->funcs->update_clocks(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2469

dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2473

!dc->debug.disable_extblankadj) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2474

for (i = 0; i < dc->res_pool->pipe_count; ++i) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

248

dc->res_pool->gsl_groups.gsl_1 = 1;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2487

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2491

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2494

if (dc->res_pool->funcs->validate_bandwidth(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING) != DC_OK)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2498

dc->hwss.prepare_bandwidth(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2501

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

252

dc->res_pool->gsl_groups.gsl_2 = 1;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2522

hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2525

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2540

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2550

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2551

mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2554

optc = dc->res_pool->timing_generators[dwb->otg_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2567

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2574

dwb = dc->res_pool->dwbc[dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2575

mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2613

void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2615

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2628

void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2630

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2665

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2683

dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2686

int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

270

dc->res_pool->gsl_groups.gsl_0 = 0;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2702

return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2733

void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

274

dc->res_pool->gsl_groups.gsl_1 = 0;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2745

vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2768

struct dce_hwseq *hws = link->dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

278

dc->res_pool->gsl_groups.gsl_2 = 0;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2783

if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2812

void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2815

int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2825

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2832

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2835

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2848

dc->link_srv->set_dpms_off(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2850

dc->hwss.disable_audio_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2858

if (dc->caps.dynamic_audio == true) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2861

update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2873

dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2894

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2895

&& dc->ctx->dce_version >= DCN_VERSION_3_5) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2918

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2922

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2925

for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2927

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2940

dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2942

hws->funcs.enable_stream_gating(dc, pipe_ctx_old);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2949

void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2956

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3004

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3014

if (dc->debug.sanity_checks)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3016

dc->res_pool->mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3019

new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3026

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3045

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3047

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3054

if (!dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3057

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3062

dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3089

if (dc->res_pool->dccg->funcs->set_pixel_rate_div)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3090

dc->res_pool->dccg->funcs->set_pixel_rate_div(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3091

dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3099

if (dc->hwss.program_dmdata_engine)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3100

dc->hwss.program_dmdata_engine(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3103

dc->hwss.update_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3106

dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3149

void dcn20_fpga_init_hw(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3152

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3153

struct resource_pool *res_pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3154

struct dc_state *context = dc->current_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3156

if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3157

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3171

dcn10_hubbub_global_timer_enable(dc->res_pool->hubbub, true, 2);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3176

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->refclk_setup)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3177

dc->res_pool->dccg->funcs->refclk_setup(dc->res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3182

for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3183

struct timing_generator *tg = dc->res_pool->timing_generators[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3186

dcn20_init_blank(dc, tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3190

struct timing_generator *tg = dc->res_pool->timing_generators[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3196

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3206

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3213

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3214

struct timing_generator *tg = dc->res_pool->timing_generators[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3216

struct hubp *hubp = dc->res_pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3217

struct dpp *dpp = dc->res_pool->dpps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3234

dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3235

pipe_ctx->stream_res.opp = dc->res_pool->opps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3237

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3244

for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3245

struct timing_generator *tg = dc->res_pool->timing_generators[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3251

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3254

dc->hwss.disable_plane(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3260

for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3261

struct timing_generator *tg = dc->res_pool->timing_generators[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3266

if (dc->res_pool->hubbub->funcs->init_crb)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3267

dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3270

void dcn20_set_disp_pattern_generator(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3278

(void)dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

361

struct dc *dc = hws->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

363

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->dccg_init)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

364

dc->res_pool->dccg->funcs->dccg_init(dc->res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

379

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

383

(void)dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

393

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

396

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

403

unsigned int num_opp_cap = (unsigned int)dc->res_pool->res_cap->num_opp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

407

color_space_to_black_color(dc, color_space, &black_color);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

421

opp = dc->res_pool->opps[opp_id_src0];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

434

bottom_opp = dc->res_pool->opps[opp_id_src1];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

471

if (hws->ctx->dc->debug.disable_dsc_power_gate)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

547

if (hws->ctx->dc->debug.disable_dpp_power_gate)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

608

struct dpp *dpp5 = hws->ctx->dc->res_pool->dpps[dpp_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

629

if (hws->ctx->dc->debug.disable_hubp_power_gate)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

698

void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

700

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

704

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

710

dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

715

dc->hwss.set_flip_control_gsl(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

723

hws->funcs.plane_atomic_power_down(dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

738

void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

743

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

748

dcn20_plane_atomic_disable(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

75

void dcn20_log_color_state(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

760

void dcn20_disable_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

762

dcn20_blank_pixel_data(dc, pipe_ctx, blank);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

79

struct dc_context *dc_ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

80

struct resource_pool *pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

822

struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

824

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

833

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

841

if (dc->res_pool->dccg->funcs->set_pixel_rate_div)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

842

dc->res_pool->dccg->funcs->set_pixel_rate_div(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

843

dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

877

dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

883

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

884

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

895

dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

907

if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal)))

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

908

dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

951

hws->funcs.blank_pixel_data(dc, pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

994

void dcn20_program_output_csc(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

111

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

115

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

119

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

121

void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

127

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

137

void dcn20_fpga_init_hw(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

142

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

145

void dcn20_set_disp_pattern_generator(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

154

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

163

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

167

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

171

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

31

void dcn20_log_color_state(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

38

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

41

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

43

void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

44

void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

45

bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

47

bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

49

void dcn20_program_output_csc(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

57

void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

59

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

63

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

67

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

71

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

74

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

77

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

80

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

85

struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

86

void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

87

void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

88

void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

90

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

94

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

98

void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c

143

void dcn20_hw_sequencer_construct(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c

145

dc->hwss = dcn20_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c

146

dc->hwseq->funcs = dcn20_private_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.h

29

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.h

31

void dcn20_hw_sequencer_construct(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

136

void dcn201_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

141

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

168

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

171

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

180

color_space_to_black_color(dc, color_space, &black_color);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

189

ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

190

opp = dc->res_pool->opps[opp_id_src0];

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

227

void dcn201_init_hw(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

230

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

231

struct resource_pool *res_pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

232

struct dc_state *context = dc->current_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

237

if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

238

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

240

hws->funcs.bios_golden_init(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

242

if (dc->ctx->dc_bios->fw_info_valid) {

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

244

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

248

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

262

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

267

struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

279

dcn201_init_blank(dc, tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

329

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

346

dc->hwss.disable_plane(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

365

if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

366

dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

368

if (!dc->debug.disable_clock_gate) {

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

370

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

371

dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

378

void dcn201_plane_atomic_disconnect(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

382

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

385

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

416

dc->optimized_required = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

421

if (dc->debug.sanity_checks)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

422

hws->funcs.verify_allow_pstate_change_high(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

425

void dcn201_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

433

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

436

if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

439

} else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

444

dc, pipe_ctx->stream->output_color_space,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

489

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

509

if (dc->debug.sanity_checks)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

511

dc->res_pool->mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

514

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

515

new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

529

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

53

dc->ctx->logger

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

533

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

540

if (dc->debug.sanity_checks)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

541

hws->funcs.verify_allow_pstate_change_high(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

555

if (dc->debug.sanity_checks)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

556

hws->funcs.verify_allow_pstate_change_high(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

563

gpu_addr_to_uma(pipe_ctx->stream->ctx->dc->hwseq, &attributes->address);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

576

gpu_addr_to_uma(pipe_ctx->stream->ctx->dc->hwseq,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

600

struct dce_hwseq *hws = link->dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

32

void dcn201_init_hw(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

35

void dcn201_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

36

void dcn201_plane_atomic_disconnect(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

37

void dcn201_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

40

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

44

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c

132

void dcn201_hw_sequencer_construct(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c

134

dc->hwss = dcn201_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c

135

dc->hwseq->funcs = dcn201_private_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.h

29

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.h

31

void dcn201_hw_sequencer_construct(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

101

dc->clk_mgr->funcs->update_clocks(

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

102

dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

108

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

111

dc->clk_mgr->funcs->update_clocks(

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

112

dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

134

pipe_ctx->stream->ctx->dc->link_srv->set_dpms_on(context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

135

pipe_ctx->stream->ctx->dc->link_srv->set_dpms_off(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

143

struct dc_context *dc = abm->ctx;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

156

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

161

static void dmub_abm_set_backlight(struct dc_context *dc, uint32_t backlight_pwm_u16_16,

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

175

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

183

struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

216

struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

246

struct dc_context *dc = pipe_ctx->stream->ctx;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

259

if (dc->dc->res_pool->dmcu) {

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

282

dmub_abm_set_backlight(dc, backlight_pwm_u16_16, frame_ramp, panel_cntl->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

287

bool dcn21_is_abm_supported(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

292

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

68

int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

84

return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

89

bool dcn21_s0i3_golden_init_wa(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

91

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done)

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

92

return !dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done(dc->res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

98

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

31

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

34

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

37

bool dcn21_s0i3_golden_init_wa(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

40

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

44

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

56

bool dcn21_is_abm_supported(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c

146

void dcn21_hw_sequencer_construct(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c

148

dc->hwss = dcn21_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c

149

dc->hwseq->funcs = dcn21_private_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.h

29

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.h

31

void dcn21_hw_sequencer_construct(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1001

stream = dc->current_state->streams[0];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1002

plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1022

if (dc->current_state->stream_count == 1 &&

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1024

dc->current_state->stream_status[0].plane_count == 1 &&

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1028

dc->hwss.does_plane_fit_in_mall &&

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1029

dc->hwss.does_plane_fit_in_mall(dc, plane->plane_size.surface_pitch,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1060

unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1063

(100LL + dc->debug.mall_additional_timer_percent) + denom - 1),

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1087

(100LL + dc->debug.mall_additional_timer_percent) + denom - 1),

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1122

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1136

cmd.mall.debug_bits = dc->debug.mall_error_as_fatal;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1138

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1155

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1160

bool dcn30_does_plane_fit_in_mall(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1169

unsigned int mall_size = dc->caps.mall_size_total;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1172

if (dc->debug.mall_size_override)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1173

mall_size = 1024 * 1024 * dc->debug.mall_size_override;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1176

cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1198

void dcn30_hardware_release(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1203

dc_dmub_srv_p_state_delegate(dc, false, NULL);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1204

dc_dmub_setup_subvp_dmub_command(dc, dc->current_state, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1210

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1211

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1216

if (dc_state_get_pipe_subvp_type(dc->current_state, pipe) == SUBVP_MAIN) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1224

if (dc->current_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1225

if ((!dc->clk_mgr->clks.p_state_change_support || subvp_in_use ||

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1226

dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1227

dc->res_pool->hubbub->funcs->force_pstate_change_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1228

dc->res_pool->hubbub->funcs->force_pstate_change_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1229

dc->res_pool->hubbub, true, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1232

void dcn30_set_disp_pattern_generator(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1240

(void)dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1245

void dcn30_prepare_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1248

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !dc->clk_mgr->clks.fw_based_mclk_switching) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1249

dc->optimized_required = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1253

if (dc->clk_mgr->dc_mode_softmax_enabled) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1254

int softmax_memclk_khz = dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1256

if (dc->clk_mgr->clks.dramclk_khz <= softmax_memclk_khz &&

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1258

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1261

dcn20_prepare_bandwidth(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1263

if (!dc->clk_mgr->clks.fw_based_mclk_switching)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1264

dc_dmub_srv_p_state_delegate(dc, false, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1294

void dcn30_get_underflow_debug_data(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1299

struct hubbub *hubbub = dc->res_pool->hubbub;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1308

struct hubp *hubp = dc->res_pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1309

struct dpp *dpp = dc->res_pool->dpps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1310

struct output_pixel_processor *opp = dc->res_pool->opps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1311

struct display_stream_compressor *dsc = dc->res_pool->dscs[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1312

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1313

struct timing_generator *optc = dc->res_pool->timing_generators[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1314

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

161

dc->caps.color.dpp.input_lut_shared,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

162

dc->caps.color.dpp.icsc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

163

dc->caps.color.dpp.dgam_ram,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

164

dc->caps.color.dpp.dgam_rom_caps.srgb,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

165

dc->caps.color.dpp.dgam_rom_caps.bt2020,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

166

dc->caps.color.dpp.dgam_rom_caps.gamma2_2,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

167

dc->caps.color.dpp.dgam_rom_caps.pq,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

168

dc->caps.color.dpp.dgam_rom_caps.hlg,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

169

dc->caps.color.dpp.post_csc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

170

dc->caps.color.dpp.gamma_corr,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

171

dc->caps.color.dpp.dgam_rom_for_yuv,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

172

dc->caps.color.dpp.hw_3d_lut,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

173

dc->caps.color.dpp.ogam_ram,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

174

dc->caps.color.dpp.ocsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

229

dc->caps.color.mpc.gamut_remap,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

230

dc->caps.color.mpc.num_3dluts,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

231

dc->caps.color.mpc.ogam_ram,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

232

dc->caps.color.mpc.ocsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

262

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

263

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

317

bool dcn30_set_input_transfer_func(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

321

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

364

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

395

bool dcn30_set_output_transfer_func(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

400

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

432

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

442

ASSERT(wb_info->mpcc_inst < (int)dc->res_pool->mpcc_count);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

443

mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

447

dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

455

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

460

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

465

dcn30_set_writeback(dc, wb_info, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

472

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

482

dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

496

mcif_wb = dc->res_pool->mcif_wb[0];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

504

warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

511

mcif_wb = dc->res_pool->mcif_wb[wb_info[i].dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

519

warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

529

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

536

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

537

mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

544

dcn30_mmhubbub_warmup(dc, 1, wb_info);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

547

dcn30_set_writeback(dc, wb_info, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

556

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

563

dwb = dc->res_pool->dwbc[dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

564

mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

573

dc->res_pool->mpc->funcs->disable_dwb_mux(dc->res_pool->mpc, dwb_pipe_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

577

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

597

ASSERT(dc->res_pool->res_cap->num_dwb >= 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

598

ASSERT(stream->num_wb_info <= (unsigned int)dc->res_pool->res_cap->num_dwb);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

608

for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

624

dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

628

ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

629

dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

632

dc->hwss.update_writeback(dc, &wb_info, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

635

dc->hwss.enable_writeback(dc, &wb_info, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

639

dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

644

void dcn30_init_hw(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

646

struct abm **abms = dc->res_pool->multiple_abms;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

647

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

648

struct dc_bios *dcb = dc->ctx->dc_bios;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

649

struct resource_pool *res_pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

655

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

656

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

663

hws->funcs.bios_golden_init(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

664

hws->funcs.disable_vga(dc->hwseq);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

667

if (dc->debug.enable_mem_low_power.bits.dmcu) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

669

if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

675

if (dc->debug.enable_mem_low_power.bits.optc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

68

dc->ctx->logger

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

680

if (dc->debug.enable_mem_low_power.bits.vga) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

685

if (dc->ctx->dc_bios->fw_info_valid) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

687

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

692

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

708

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

713

struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

728

dc->link_srv->blank_all_dp_displays(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

731

hws->funcs.enable_power_gating_plane(dc->hwseq, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

739

if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

740

hws->funcs.init_pipes(dc, dc->current_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

741

if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

742

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

743

!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

75

void dcn30_log_color_state(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

751

if (!dc->config.seamless_boot_edp_requested) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

755

dc_get_edp_links(dc, edp_links, &edp_num);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

760

dc->hwss.edp_backlight_control &&

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

762

dc->hwss.edp_power_control) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

763

dc->hwss.edp_backlight_control(edp_link, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

764

hws->funcs.power_down(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

765

dc->hwss.edp_power_control(edp_link, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

767

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

768

struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

773

hws->funcs.power_down(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

787

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

788

struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

79

struct dc_context *dc_ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

796

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

80

struct resource_pool *pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

802

if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

803

dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

805

if (!dc->debug.disable_clock_gate) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

807

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

808

dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

813

if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

814

dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

816

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->notify_wm_ranges)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

817

dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

820

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->set_hard_max_memclk &&

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

821

!dc->clk_mgr->dc_mode_softmax_enabled)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

822

dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

824

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

825

dc->res_pool->hubbub->funcs->force_pstate_change_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

826

dc->res_pool->hubbub, false, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

827

if (dc->res_pool->hubbub->funcs->init_crb)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

828

dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

831

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

832

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

833

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

949

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

953

(!dc->res_pool->dccg->funcs->enable_hdmicharclk))

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

966

bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

975

if (!dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

979

if (dc->current_state) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

983

for (i = 0; i < dc->current_state->stream_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

984

if (dc->current_state->stream_status[i].plane_count)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

989

if (i == dc->current_state->stream_count) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

996

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

106

void dcn30_set_hubp_blank(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

110

void dcn30_prepare_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

115

void dcn30_get_underflow_debug_data(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

31

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

34

void dcn30_init_hw(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

36

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

40

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

44

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

48

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

52

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

56

void dcn30_log_color_state(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

62

bool dcn30_set_input_transfer_func(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

68

bool dcn30_set_output_transfer_func(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

79

void dcn30_hw_set_fva_vrr_adj(struct dc *dc, struct pipe_ctx **pipe_ctx, int num_pipes,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

83

int dcn30_hw_get_max_fva_factor(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

88

bool dcn30_does_plane_fit_in_mall(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

94

bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

96

void dcn30_hardware_release(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

98

void dcn30_set_disp_pattern_generator(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c

153

void dcn30_hw_sequencer_construct(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c

155

dc->hwss = dcn30_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c

156

dc->hwseq->funcs = dcn30_private_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.h

29

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.h

31

void dcn30_hw_sequencer_construct(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c

149

void dcn301_hw_sequencer_construct(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c

151

dc->hwss = dcn301_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c

152

dc->hwseq->funcs = dcn301_private_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.h

29

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.h

31

void dcn301_hw_sequencer_construct(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

107

if (hws->ctx->dc->debug.disable_hubp_power_gate)

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

165

if (hws->ctx->dc->debug.disable_dsc_power_gate)

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

50

if (hws->ctx->dc->debug.disable_dpp_power_gate)

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c

34

void dcn302_hw_sequencer_construct(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c

36

dcn30_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c

38

dc->hwseq->funcs.dpp_pg_control = dcn302_dpp_pg_control;

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c

39

dc->hwseq->funcs.hubp_pg_control = dcn302_hubp_pg_control;

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c

40

dc->hwseq->funcs.dsc_pg_control = dcn302_dsc_pg_control;

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.h

29

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.h

31

void dcn302_hw_sequencer_construct(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_init.c

32

void dcn303_hw_sequencer_construct(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_init.c

34

dcn30_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_init.c

36

dc->hwseq->funcs.dpp_pg_control = dcn303_dpp_pg_control;

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_init.c

37

dc->hwseq->funcs.hubp_pg_control = dcn303_hubp_pg_control;

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_init.c

38

dc->hwseq->funcs.dsc_pg_control = dcn303_dsc_pg_control;

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_init.c

39

dc->hwseq->funcs.enable_power_gating_plane = dcn303_enable_power_gating_plane;

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_init.h

29

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_init.h

31

void dcn303_hw_sequencer_construct(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

100

if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

102

for (i = 0; i < dc->res_pool->stream_enc_count; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

103

if (dc->res_pool->stream_enc[i]->vpg)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

104

dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

105

for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

106

dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

107

for (i = 0; i < dc->res_pool->hpo_frl_stream_enc_count; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

108

dc->res_pool->hpo_frl_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_frl_stream_enc[i]->vpg);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

113

void dcn31_init_hw(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

115

struct abm **abms = dc->res_pool->multiple_abms;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

116

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

117

struct dc_bios *dcb = dc->ctx->dc_bios;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

118

struct resource_pool *res_pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

123

if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

124

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

127

hws->funcs.bios_golden_init(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

129

hws->funcs.disable_vga(dc->hwseq);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

135

enable_memory_low_power(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

137

if (dc->ctx->dc_bios->fw_info_valid) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

139

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

144

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

160

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

165

struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

183

dc->link_srv->blank_all_dp_displays(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

186

hws->funcs.enable_power_gating_plane(dc->hwseq, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

194

if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

197

if (!dc->caps.seamless_odm) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

198

for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

199

struct timing_generator *tg = dc->res_pool->timing_generators[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

211

dc->link_srv->blank_all_edp_displays(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

217

hws->funcs.init_pipes(dc, dc->current_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

218

if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

219

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

220

!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

229

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

230

struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

238

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

244

if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

245

dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, dc->debug.enable_mem_low_power.bits.i2c);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

250

if (!dc->debug.disable_clock_gate) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

252

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

253

dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

258

if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

259

dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

261

if (dc->clk_mgr && dc->clk_mgr->funcs->notify_wm_ranges)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

262

dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

264

if (dc->clk_mgr && dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

265

dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

267

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

268

dc->res_pool->hubbub->funcs->force_pstate_change_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

269

dc->res_pool->hubbub, false, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

271

if (dc->res_pool->hubbub->funcs->init_crb)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

272

dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

276

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

277

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

278

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

290

if (hws->ctx->dc->debug.disable_dsc_power_gate)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

293

if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc &&

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

294

hws->ctx->dc->res_pool->dccg->funcs->enable_dsc &&

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

296

hws->ctx->dc->res_pool->dccg->funcs->enable_dsc(

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

297

hws->ctx->dc->res_pool->dccg, dsc_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

336

if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

337

if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

338

hws->ctx->dc->res_pool->dccg->funcs->disable_dsc(

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

339

hws->ctx->dc->res_pool->dccg, dsc_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

352

if (enable && !hws->ctx->dc->debug.disable_hubp_power_gate)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

366

if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

405

else if (pipe_ctx->stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

432

void dcn31_z10_save_init(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

440

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

443

void dcn31_z10_restore(const struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

451

if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv))

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

458

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

466

if (hws->ctx->dc->debug.disable_hubp_power_gate)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

500

int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

522

return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

526

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

539

dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

543

if (dc->hwseq)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

544

dc->hwseq->wa_state.skip_blank_stream = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

548

dc->hwss.blank_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

549

if (dc->hwseq)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

550

dc->hwseq->wa_state.skip_blank_stream = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

589

dc->link_srv->set_dpms_off(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

591

dc->hwss.disable_audio_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

599

((link->dc->config.smart_mux_version && link->dc->is_switch_in_progress_dest)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

603

dc->link_srv->set_dsc_enable(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

612

if (dc->caps.dynamic_audio == true) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

615

update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

620

if (dc->hwseq)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

621

dc->hwseq->wa_state.skip_blank_stream = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

628

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

632

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

635

for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

637

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

65

dc->ctx->logger

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

652

dc->res_pool->hubbub->funcs->program_det_size &&

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

653

dc->res_pool->hubbub->funcs->wait_for_det_apply) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

654

dc->res_pool->hubbub->funcs->program_det_size(

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

655

dc->res_pool->hubbub, pipe_ctx_old->plane_res.hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

657

dc->res_pool->hubbub->funcs->wait_for_det_apply(

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

658

dc->res_pool->hubbub, pipe_ctx_old->plane_res.hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

661

dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

663

hws->funcs.enable_stream_gating(dc, pipe_ctx_old);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

670

if (!dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

671

link_enc_cfg_set_transient_mode(dc, dc->current_state, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

676

if (hws->ctx->dc->debug.hpo_optimization)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

698

static void dmub_abm_set_backlight(struct dc_context *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

718

dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

72

static void enable_memory_low_power(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

724

struct dc_context *dc = pipe_ctx->stream->ctx;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

74

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

742

dmub_abm_set_backlight(dc, backlight_level_params, panel_cntl->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

77

if (dc->debug.enable_mem_low_power.bits.dmcu) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

79

if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

85

if (dc->debug.enable_mem_low_power.bits.optc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

90

if (dc->debug.enable_mem_low_power.bits.vga) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

95

if (dc->debug.enable_mem_low_power.bits.mpc &&

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

96

dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

97

dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

31

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

33

void dcn31_init_hw(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

46

void dcn31_z10_restore(const struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

47

void dcn31_z10_save_init(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

50

int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

52

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

56

bool dcn31_is_abm_supported(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

58

void dcn31_init_pipes(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c

155

void dcn31_hw_sequencer_construct(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c

157

dc->hwss = dcn31_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c

158

dc->hwseq->funcs = dcn31_private_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.h

29

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.h

31

void dcn31_hw_sequencer_construct(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

173

void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

181

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

212

struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

235

if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc &&

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

236

hws->ctx->dc->res_pool->dccg->funcs->enable_dsc &&

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

238

hws->ctx->dc->res_pool->dccg->funcs->enable_dsc(

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

239

hws->ctx->dc->res_pool->dccg, dsc_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

241

if (!hws->ctx->dc->debug.disable_dsc_power_gate) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

289

if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

290

if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

291

hws->ctx->dc->res_pool->dccg->funcs->disable_dsc(

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

292

hws->ctx->dc->res_pool->dccg, dsc_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

302

if (enable && !hws->ctx->dc->debug.disable_hubp_power_gate)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

316

if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

339

stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

367

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

371

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

401

void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

407

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

411

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

423

reset_sync_context_for_pipe(dc, context, (uint8_t)i);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

428

hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

430

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

434

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

460

if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

463

if (hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

464

hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

465

hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

485

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

491

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

496

dc->link_srv->dp_get_encoding_format(

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

510

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

512

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

515

link->dc->hwss.edp_backlight_control &&

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

517

link->dc->hwss.edp_backlight_control(link, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

530

dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

554

if (hws->ctx->dc->debug.disable_dpp_power_gate) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

559

struct dpp *dpp = hws->ctx->dc->res_pool->dpps[dpp_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

32

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

34

void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

42

void dcn314_calculate_pix_rate_divider(struct dc *dc, struct dc_state *context, const struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

44

void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c

162

void dcn314_hw_sequencer_construct(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c

164

dc->hwss = dcn314_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c

165

dc->hwseq->funcs = dcn314_private_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.h

30

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.h

32

void dcn314_hw_sequencer_construct(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1000

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1001

dc->caps.dmub_caps.subvp_psr = dc->ctx->dmub_srv->dmub->feature_caps.subvp_psr_support;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1002

dc->caps.dmub_caps.gecc_enable = dc->ctx->dmub_srv->dmub->feature_caps.gecc_enable;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1003

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1004

dc->caps.dmub_caps.aux_backlight_support = dc->ctx->dmub_srv->dmub->feature_caps.abm_aux_backlight_support;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1007

dc->caps.dmub_caps.fams_ver = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1008

if (dc->caps.dmub_caps.fams_ver == 2) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1010

dc->debug.fams2_config.bits.enable &= true;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1011

} else if (dc->ctx->dmub_srv->dmub->fw_version <

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1014

dc->debug.fams2_config.bits.enable = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1015

if (dc->debug.using_dml2 && dc->res_pool->funcs->update_bw_bounding_box &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1016

dc->clk_mgr && dc->clk_mgr->bw_params) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1018

dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1020

dc->debug.force_disable_subvp = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1021

dc->debug.disable_fpo_optimizations = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1029

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1033

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1145

void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1176

struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1195

dc->hwseq->funcs.blank_pixel_data(dc, pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1203

struct dce_hwseq *hws = stream->ctx->dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1209

stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1238

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1242

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1259

void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1266

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1271

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1272

dc_state = dc->current_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1281

reset_sync_context_for_pipe(dc, context, (uint8_t)i);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1286

hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1288

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1292

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1315

dc_trigger_sync(dc, dc->current_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1324

struct dce_hwseq *hws = link->dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1338

if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1371

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1376

if (dc_is_dp_signal(pipe_ctx->stream->signal) && !dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1377

dc->debug.enable_dp_dig_pixel_rate_div_policy)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1399

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1405

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1410

dc->link_srv->dp_get_encoding_format(

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1424

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1426

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1429

link->dc->hwss.edp_backlight_control &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1431

link->dc->hwss.edp_backlight_control(link, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1445

dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1454

void dcn32_update_phantom_vp_position(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1461

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1539

void dcn32_update_dsc_pg(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1543

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1546

for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1547

struct display_stream_compressor *dsc = dc->res_pool->dscs[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1562

void dcn32_disable_phantom_streams(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1564

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1567

for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1569

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1575

if (dc_state_get_pipe_subvp_type(dc->current_state, pipe_ctx_old) != SUBVP_PHANTOM)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1586

hws->funcs.reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1588

hws->funcs.enable_stream_gating(dc, pipe_ctx_old);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1595

void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1599

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1601

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1603

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1610

old_pipe->stream && dc_state_get_pipe_subvp_type(dc->current_state, old_pipe) != SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1619

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1621

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1645

dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1651

hws->funcs.resync_fifo_dccg_dio(hws, dc, context, i);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1658

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1661

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1669

unsigned int num_opp_cap = (unsigned int)dc->res_pool->res_cap->num_opp;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1673

color_space_to_black_color(dc, color_space, &black_color);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1689

if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1690

opp = dc->res_pool->opps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1703

if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src1) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1704

bottom_opp = dc->res_pool->opps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

172

if (hws->ctx->dc->debug.disable_hubp_power_gate)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

175

if (hws->ctx->dc->debug.ignore_pg)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1762

bool dcn32_is_pipe_topology_transition_seamless(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1770

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1815

void dcn32_prepare_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1822

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1823

dc->optimized_required = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1827

if (dc->clk_mgr->dc_mode_softmax_enabled) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1828

int softmax_memclk_khz = dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1830

if (dc->clk_mgr->clks.dramclk_khz <= softmax_memclk_khz &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1832

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1835

dcn20_prepare_bandwidth(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1838

dc_dmub_srv_p_state_delegate(dc, false, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1840

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1848

void dcn32_interdependent_update_lock(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1855

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1865

dc->hwss.pipe_control_lock(dc, pipe, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1867

dc->hwss.pipe_control_lock(dc, pipe, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1871

void dcn32_program_outstanding_updates(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1874

struct hubbub *hubbub = dc->res_pool->hubbub;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

204

static bool dcn32_check_no_memory_request_for_cab(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

209

for (i = 0; i < dc->current_state->stream_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

210

if ((dc->current_state->stream_status[i].plane_count) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

211

(dc->current_state->streams[i]->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED))

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

216

if (i == dc->current_state->stream_count)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

227

static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

238

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

244

mall_ss_size_bytes += dcn32_helper_calculate_mall_bytes_for_cursor(dc, pipe, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

248

if (dc->debug.force_mall_ss_num_ways > 0) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

249

num_ways = dc->debug.force_mall_ss_num_ways;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

250

} else if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

251

num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, mall_ss_size_bytes);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

259

bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

268

if (!dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

271

for (i = 0; i < dc->current_state->stream_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

273

if (dc->current_state->streams[i] != NULL &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

274

dc->current_state->streams[i]->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

275

(dc->current_state->stream_count > 1 || (!dc->current_state->streams[i]->dpms_off &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

276

dc->current_state->stream_status[i].plane_count > 0)))

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

284

if (dcn32_check_no_memory_request_for_cab(dc)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

291

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

300

ways = dcn32_calculate_cab_allocation(dc, dc->current_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

305

for (i = 0; i < dc->current_state->stream_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

306

for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

307

plane = dc->current_state->stream_status[i].plane_states[j];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

318

if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

325

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

342

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

352

void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

357

if (!dc->ctx || !dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

360

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

369

dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

378

void dcn32_subvp_pipe_control_lock(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

391

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

412

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

424

dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

430

struct dc *dc = params->subvp_pipe_control_lock_fast_params.dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

442

dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

451

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

452

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

488

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

529

bool dcn32_set_input_transfer_func(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

533

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

534

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

569

bool dcn32_set_output_transfer_func(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

573

(void)dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

575

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

608

void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

616

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

635

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

637

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

64

dc->ctx->logger

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

657

old_stream_status = dc_state_get_stream_status(dc->current_state, old_pipe->stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

661

(!old_pipe->stream || (dc_state_get_pipe_subvp_type(dc->current_state, old_pipe) != SUBVP_MAIN &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

675

void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

678

unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

681

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

713

num_ways <= dc->caps.cache_num_ways &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

729

void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

732

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

738

hws->funcs.update_mall_sel(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

741

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

757

static void dcn32_initialize_min_clocks(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

759

struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

761

if (!dc->clk_mgr || !dc->clk_mgr->bw_params || !dc->clk_mgr->funcs)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

765

clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

766

clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

767

clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

768

clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

769

clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

773

if (dc->debug.disable_boot_optimizations) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

774

clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

775

} else if (dc->clk_mgr->funcs->get_dispclk_from_dentist) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

78

struct dc *dc = hws->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

781

clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

784

if (dc->clk_mgr->funcs->update_clocks)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

785

dc->clk_mgr->funcs->update_clocks(dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

786

dc->current_state,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

790

void dcn32_init_hw(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

792

struct abm **abms = dc->res_pool->multiple_abms;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

793

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

794

struct dc_bios *dcb = dc->ctx->dc_bios;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

795

struct resource_pool *res_pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

80

if (dc->debug.disable_dsc_power_gate)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

801

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

802

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

809

hws->funcs.bios_golden_init(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

810

hws->funcs.disable_vga(dc->hwseq);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

814

if (dc->debug.enable_mem_low_power.bits.optc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

819

if (dc->debug.enable_mem_low_power.bits.vga) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

824

if (dc->ctx->dc_bios->fw_info_valid) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

826

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

83

if (!dc->debug.enable_double_buffered_dsc_pg_support)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

830

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

846

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

851

struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

86

if (dc->debug.ignore_pg)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

870

hws->funcs.enable_power_gating_plane(dc->hwseq, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

873

dc->link_srv->blank_all_dp_displays(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

881

if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

885

if (dc->hwss.enable_accelerated_mode && dc->debug.disable_boot_optimizations)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

886

dc->hwss.enable_accelerated_mode(dc, dc->current_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

888

hws->funcs.init_pipes(dc, dc->current_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

890

if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

891

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

892

!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

894

dcn32_initialize_min_clocks(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

903

dc_allow_idle_optimizations(dc, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

904

dc_allow_idle_optimizations(dc, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

912

if (!dc->config.seamless_boot_edp_requested) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

916

dc_get_edp_links(dc, edp_links, &edp_num);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

922

dc->hwss.edp_backlight_control &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

924

dc->hwss.edp_power_control) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

925

dc->hwss.edp_backlight_control(edp_link, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

926

hws->funcs.power_down(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

927

dc->hwss.edp_power_control(edp_link, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

931

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

932

struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

937

hws->funcs.power_down(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

951

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

952

struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

960

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

966

if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

967

dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

969

if (!dc->debug.disable_clock_gate) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

971

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

972

dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

977

if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

978

dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

980

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->notify_wm_ranges)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

981

dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

983

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->set_hard_max_memclk &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

984

!dc->clk_mgr->dc_mode_softmax_enabled)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

985

dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

987

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

988

dc->res_pool->hubbub->funcs->force_pstate_change_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

989

dc->res_pool->hubbub, false, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

991

if (dc->res_pool->hubbub->funcs->init_crb)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

992

dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

994

if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

995

dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

998

if (dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

999

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

100

void dcn32_update_phantom_vp_position(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

110

void dcn32_update_dsc_pg(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

114

void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

116

void dcn32_disable_phantom_streams(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

119

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

122

bool dcn32_is_pipe_topology_transition_seamless(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

126

void dcn32_prepare_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

129

void dcn32_interdependent_update_lock(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

132

void dcn32_program_outstanding_updates(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

31

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

44

bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

46

void dcn32_cab_for_ss_control(struct dc *dc, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

48

void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

53

bool dcn32_set_input_transfer_func(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

60

bool dcn32_set_output_transfer_func(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

64

void dcn32_init_hw(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

66

void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

68

void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

70

void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

72

void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

78

void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

80

void dcn32_subvp_pipe_control_lock(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

94

void dcn32_calculate_pix_rate_divider(struct dc *dc, struct dc_state *context, const struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c

173

void dcn32_hw_sequencer_init_functions(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c

175

dc->hwss = dcn32_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c

176

dc->hwseq->funcs = dcn32_private_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.h

29

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.h

31

void dcn32_hw_sequencer_init_functions(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1004

for (uj = 0; uj < dc->res_pool->pipe_count; ++uj) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

101

if (dc->debug.enable_mem_low_power.bits.mpc &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

102

dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1022

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1023

update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1024

if (dc->links[i]->type != dc_connection_none)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1025

update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1029

for (ui = 0; ui < dc->res_pool->timing_generator_count; ui++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

103

dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1030

struct timing_generator *tg = dc->res_pool->timing_generators[ui];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1037

dc_get_edp_links(dc, edp_links, &edp_num);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1045

if (dc->caps.sequential_ono) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1046

for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

105

if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1060

void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

107

for (i = 0; i < dc->res_pool->stream_enc_count; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1070

for (i = 0; i < (int)dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1071

struct pipe_ctx *cur_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

108

dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

110

for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

111

dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

113

for (i = 0; i < dc->res_pool->hpo_frl_stream_enc_count; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

114

dc->res_pool->hpo_frl_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_frl_stream_enc[i]->vpg);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1140

for (i = 0; i < dc->link_count; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1141

if (dc->links[i]->type != dc_connection_none)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1142

update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1144

for (ui = 0; ui < dc->res_pool->hpo_frl_stream_enc_count; ui++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1146

dc->res_pool->hpo_frl_stream_enc[ui]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1152

for (ui = 0; ui < dc->res_pool->hpo_dp_stream_enc_count; ui++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1154

dc->res_pool->hpo_dp_stream_enc[ui]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1166

if (dc->caps.sequential_ono) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1167

for (ui = 0; ui < dc->res_pool->pipe_count; ui++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1178

for (uj = 0; uj < dc->res_pool->pipe_count; ++uj) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1186

for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

120

static void print_pg_status(struct dc *dc, const char *debug_func, const char *debug_log)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

122

if (dc->debug.enable_pg_cntl_debug_logs && dc->res_pool->pg_cntl) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1223

void dcn35_hw_block_power_down(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1228

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

123

if (dc->res_pool->pg_cntl->funcs->print_pg_status)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1232

if (dc->debug.ignore_pg)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

124

dc->res_pool->pg_cntl->funcs->print_pg_status(dc->res_pool->pg_cntl, debug_func, debug_log);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1240

if (!dc->caps.sequential_ono) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1241

for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1249

for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1256

for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1301

void dcn35_hw_block_power_up(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1305

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1309

if (dc->debug.ignore_pg)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1316

if (!dc->caps.sequential_ono) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1317

for (i = 0; i < (unsigned int)dc->res_pool->res_cap->num_dsc; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1324

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1331

if (dc->caps.sequential_ono) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1343

void dcn35_root_clock_control(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1347

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1353

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1356

if (dc->hwseq->funcs.dpp_root_clock_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1357

dc->hwseq->funcs.dpp_root_clock_control(dc->hwseq, i, power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1360

if (dc->hwseq->funcs.dpstream_root_clock_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1361

dc->hwseq->funcs.dpstream_root_clock_control(dc->hwseq, i, power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1364

for (i = 0; i < dc->res_pool->dig_link_enc_count; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1366

if (dc->hwseq->funcs.physymclk_root_clock_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1367

dc->hwseq->funcs.physymclk_root_clock_control(dc->hwseq, i, power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1370

if (dc->hwseq->funcs.hdmistream_root_clock_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1371

dc->hwseq->funcs.hdmistream_root_clock_control(dc->hwseq, power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1373

for (i = 0; i < (unsigned int)dc->res_pool->res_cap->num_dsc; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1376

if (dc->res_pool->dccg->funcs->enable_dsc)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1377

dc->res_pool->dccg->funcs->enable_dsc(dc->res_pool->dccg, i);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1379

if (dc->res_pool->dccg->funcs->disable_dsc)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1380

dc->res_pool->dccg->funcs->disable_dsc(dc->res_pool->dccg, i);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1386

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1389

if (dc->hwseq->funcs.dpp_root_clock_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1390

dc->hwseq->funcs.dpp_root_clock_control(dc->hwseq, i, power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1393

if (dc->hwseq->funcs.dpstream_root_clock_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1394

dc->hwseq->funcs.dpstream_root_clock_control(dc->hwseq, i, power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1397

for (i = 0; i < dc->res_pool->dig_link_enc_count; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1399

if (dc->hwseq->funcs.physymclk_root_clock_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1400

dc->hwseq->funcs.physymclk_root_clock_control(dc->hwseq, i, power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1403

if (dc->hwseq->funcs.hdmistream_root_clock_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1404

dc->hwseq->funcs.hdmistream_root_clock_control(dc->hwseq, power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1409

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1414

if (dc->hwss.calc_blocks_to_ungate) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1415

dc->hwss.calc_blocks_to_ungate(dc, context, &pg_update_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1417

if (dc->hwss.root_clock_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1418

dc->hwss.root_clock_control(dc, &pg_update_state, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

142

void dcn35_init_hw(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1420

if (dc->hwss.hw_block_power_up)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1421

dc->hwss.hw_block_power_up(dc, &pg_update_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1424

dcn20_prepare_bandwidth(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1426

print_pg_status(dc, __func__, ": after rcg and power up");

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1430

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1435

print_pg_status(dc, __func__, ": before rcg and power up");

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1437

dcn20_optimize_bandwidth(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1439

if (dc->hwss.calc_blocks_to_gate) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

144

struct abm **abms = dc->res_pool->multiple_abms;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1440

dc->hwss.calc_blocks_to_gate(dc, context, &pg_update_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1442

if (dc->hwss.hw_block_power_down)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1443

dc->hwss.hw_block_power_down(dc, &pg_update_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1445

if (dc->hwss.root_clock_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1446

dc->hwss.root_clock_control(dc, &pg_update_state, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1449

print_pg_status(dc, __func__, ": after rcg and power up");

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

145

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

146

struct dc_bios *dcb = dc->ctx->dc_bios;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

147

struct resource_pool *res_pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1475

if (pipe_ctx[i]->stream && pipe_ctx[i]->stream->ctx->dc->debug.static_screen_wait_frames) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1477

struct dc *dc = pipe_ctx[i]->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1480

if (frame_rate >= 120 && dc->caps.ips_support &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1481

dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

152

print_pg_status(dc, __func__, ": start");

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

154

if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

155

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1554

const struct dc *dc = pipe_ctx->stream->link->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1566

if (pix_clk_mhz > dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1597

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1605

if (dc_is_dp_signal(pipe_ctx->stream->signal) && !dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1606

dc->debug.enable_dp_dig_pixel_rate_div_policy)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

161

hws->funcs.bios_golden_init(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1615

static void dcn35_calc_blocks_to_ungate_for_hw_release(struct dc *dc, struct pg_block_update *update_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1622

for (i = 0; i < dc->res_pool->pipe_count; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1634

void dcn35_hardware_release(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1638

dcn35_calc_blocks_to_ungate_for_hw_release(dc, &pg_update_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1640

if (dc->hwss.root_clock_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1641

dc->hwss.root_clock_control(dc, &pg_update_state, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1643

if (dc->hwss.hw_block_power_up)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1644

dc->hwss.hw_block_power_up(dc, &pg_update_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1647

void dcn35_abort_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1649

if (!dc_dmub_srv_is_cursor_offload_enabled(dc))

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1668

if (dc->hwss.begin_cursor_offload_update)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1669

dc->hwss.begin_cursor_offload_update(dc, pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1671

if (dc->hwss.commit_cursor_offload_update)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1672

dc->hwss.commit_cursor_offload_update(dc, pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1675

void dcn35_begin_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1677

volatile struct dmub_cursor_offload_v1 *cs = dc->ctx->dmub_srv->dmub->cursor_offload_v1;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1698

void dcn35_commit_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

170

if (dc->ctx->dc_bios->fw_info_valid) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1700

volatile struct dmub_cursor_offload_v1 *cs = dc->ctx->dmub_srv->dmub->cursor_offload_v1;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1718

shared_stream = &dc->ctx->dmub_srv->dmub->shared_state[DMUB_SHARED_STATE_FEATURE__CURSOR_OFFLOAD_V1]

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

172

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1727

void dcn35_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1729

volatile struct dmub_cursor_offload_v1 *cs = dc->ctx->dmub_srv->dmub->cursor_offload_v1;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

177

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1775

void dcn35_notify_cursor_offload_drr_update(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1778

dc_dmub_srv_control_cursor_offload(dc, context, stream, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1781

void dcn35_program_cursor_offload_now(struct dc *dc, const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1783

dc_dmub_srv_program_cursor_now(dc, pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1788

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1793

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1809

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1811

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1814

link->dc->hwss.edp_backlight_control &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1816

link->dc->hwss.edp_backlight_control(link, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1835

dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

193

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

198

struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

216

dc->link_srv->blank_all_dp_displays(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

219

res_pool->hubbub->funcs->dchubbub_init(dc->res_pool->hubbub);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

226

if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

229

if (!dc->caps.seamless_odm) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

230

for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

231

struct timing_generator *tg = dc->res_pool->timing_generators[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

243

dc->link_srv->blank_all_edp_displays(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

249

hws->funcs.init_pipes(dc, dc->current_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

250

print_pg_status(dc, __func__, ": after init_pipes");

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

252

if (dc->res_pool->hubbub->funcs->allow_self_refresh_control &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

253

!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

254

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

255

!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

263

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

264

struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

271

if (dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

272

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

279

if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

280

dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, !dc->debug.enable_mem_low_power.bits.i2c);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

285

if (!dc->debug.disable_clock_gate) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

290

if (dc->debug.disable_mem_low_power) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

291

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->enable_memory_low_power)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

292

dc->res_pool->dccg->funcs->enable_memory_low_power(dc->res_pool->dccg, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

294

if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

295

dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

297

if (dc->clk_mgr && dc->clk_mgr->funcs->notify_wm_ranges)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

298

dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

300

if (dc->clk_mgr && dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

301

dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

305

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

306

dc->res_pool->hubbub->funcs->force_pstate_change_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

307

dc->res_pool->hubbub, false, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

309

if (dc->res_pool->hubbub->funcs->init_crb)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

310

dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

312

if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

313

dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

315

if (dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

316

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

317

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

318

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

319

dc->caps.dmub_caps.aux_backlight_support = dc->ctx->dmub_srv->dmub->feature_caps.abm_aux_backlight_support;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

322

if (dc->res_pool->pg_cntl) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

323

if (dc->res_pool->pg_cntl->funcs->init_pg_status)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

324

dc->res_pool->pg_cntl->funcs->init_pg_status(dc->res_pool->pg_cntl);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

326

print_pg_status(dc, __func__, ": after init_pg_status");

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

431

void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

439

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

474

struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

490

if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

493

if (hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

494

hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

495

hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

501

if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

504

if (hws->ctx->dc->res_pool->dccg->funcs->set_dpstreamclk_root_clock_gating) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

505

hws->ctx->dc->res_pool->dccg->funcs->set_dpstreamclk_root_clock_gating(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

506

hws->ctx->dc->res_pool->dccg, dp_hpo_inst, clock_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

512

if (!hws->ctx->dc->debug.root_clock_optimization.bits.hdmistream)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

515

if (hws->ctx->dc->res_pool->dccg->funcs->set_hdmistreamclk_root_clock_gating) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

516

hws->ctx->dc->res_pool->dccg->funcs->set_hdmistreamclk_root_clock_gating(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

517

hws->ctx->dc->res_pool->dccg, clock_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

523

if (!hws->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

526

if (hws->ctx->dc->res_pool->dccg->funcs->set_physymclk_root_clock_gating) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

527

hws->ctx->dc->res_pool->dccg->funcs->set_physymclk_root_clock_gating(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

528

hws->ctx->dc->res_pool->dccg, phy_inst, clock_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

537

void dcn35_power_down_on_boot(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

544

dc_get_edp_links(dc, edp_links, &edp_num);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

550

dc->hwseq->funcs.edp_backlight_control &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

551

dc->hwseq->funcs.power_down &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

552

dc->hwss.edp_power_control) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

553

dc->hwseq->funcs.edp_backlight_control(edp_link, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

554

dc->hwseq->funcs.power_down(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

555

dc->hwss.edp_power_control(edp_link, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

557

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

558

struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

562

dc->hwseq->funcs.power_down) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

563

dc->hwseq->funcs.power_down(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

575

if (dc->clk_mgr->funcs->set_low_power_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

576

dc->clk_mgr->funcs->set_low_power_state(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

578

if (dc->clk_mgr->clks.pwr_state == DCN_PWR_STATE_LOW_POWER)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

579

dc_allow_idle_optimizations(dc, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

582

bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

584

if (dc->debug.dmcub_emulation)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

591

for (i = 0; i < dc->current_state->stream_count; ++i) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

592

struct dc_stream_state *stream = dc->current_state->streams[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

624

dc_dmub_srv_apply_idle_power_optimizations(dc, enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

629

void dcn35_z10_restore(const struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

631

if (dc->debug.disable_z10)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

634

dc_dmub_srv_apply_idle_power_optimizations(dc, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

636

dcn31_z10_restore(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

639

void dcn35_init_pipes(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

642

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

643

struct hubbub *hubbub = dc->res_pool->hubbub;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

644

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

655

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

656

struct timing_generator *tg = dc->res_pool->timing_generators[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

671

hws->funcs.init_blank(dc, tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

682

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

684

struct hubp *hubp = dc->res_pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

699

for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

706

dc->res_pool->mpc->funcs->mpc_init_single_inst(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

707

dc->res_pool->mpc, i);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

710

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

711

struct timing_generator *tg = dc->res_pool->timing_generators[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

712

struct hubp *hubp = dc->res_pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

713

struct dpp *dpp = dc->res_pool->dpps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

735

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

750

dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

751

dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

752

dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

753

pipe_ctx->stream_res.opp = dc->res_pool->opps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

755

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

760

dc->hwss.disable_plane(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

774

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

776

if (dc->res_pool->opps[i]->mpc_tree_params.opp_list) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

777

if (dc->res_pool->opps[i]->mpc_tree_params.opp_list->mpcc_bot) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

778

int bot_id = dc->res_pool->opps[i]->mpc_tree_params.opp_list->mpcc_bot->mpcc_id;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

78

static void enable_memory_low_power(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

781

dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

80

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

800

for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

801

struct timing_generator *tg = dc->res_pool->timing_generators[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

816

for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

821

dc->res_pool->dscs[i]->funcs->dsc_read_state(dc->res_pool->dscs[i], &s);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

828

pg_cntl->funcs->dsc_pg_control(pg_cntl, dc->res_pool->dscs[i]->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

83

if (dc->debug.enable_mem_low_power.bits.dmcu) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

834

void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

85

if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

852

if (dc->vm_pa_config.valid) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

857

apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

858

apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

875

void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

881

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

887

dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

892

dc->hwss.set_flip_control_gsl(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

91

if (dc->debug.enable_mem_low_power.bits.optc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

913

void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

915

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

919

DC_LOGGER_INIT(dc->ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

924

if (dc->debug.disable_dpp_power_gate) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

932

hws->funcs.plane_atomic_disable(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

944

void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

956

for (ui = 0; ui < dc->res_pool->hpo_frl_stream_enc_count; ui++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

958

dc->res_pool->hpo_frl_stream_enc[ui]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

96

if (dc->debug.enable_mem_low_power.bits.vga) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

964

for (ui = 0; ui < dc->res_pool->hpo_dp_stream_enc_count; ui++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

966

dc->res_pool->hpo_dp_stream_enc[ui]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

977

for (ui = 0; ui < dc->res_pool->pipe_count; ui++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

997

if (dc->caps.sequential_ono) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

104

void dcn35_hardware_release(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

106

void dcn35_abort_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

107

void dcn35_begin_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

108

void dcn35_commit_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

109

void dcn35_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

110

void dcn35_notify_cursor_offload_drr_update(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

112

void dcn35_program_cursor_offload_now(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

32

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

34

void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

50

void dcn35_init_hw(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

56

void dcn35_power_down_on_boot(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

58

bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

60

void dcn35_z10_restore(const struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

62

void dcn35_init_pipes(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

63

void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

64

void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

66

void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

68

void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

70

void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

72

void dcn35_hw_block_power_up(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

74

void dcn35_hw_block_power_down(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

76

void dcn35_root_clock_control(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

80

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

84

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c

180

void dcn35_hw_sequencer_construct(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c

182

dc->hwss = dcn35_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c

183

dc->hwseq->funcs = dcn35_private_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.h

30

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.h

32

void dcn35_hw_sequencer_construct(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

103

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

105

if (!pg_cntl || dc->debug.ignore_pg)

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

108

for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

152

void dcn351_hw_block_power_up(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

156

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

158

if (!pg_cntl || dc->debug.ignore_pg)

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

170

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

38

void dcn351_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

43

dcn35_calc_blocks_to_gate(dc, context, update_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

45

for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

58

void dcn351_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

63

dcn35_calc_blocks_to_ungate(dc, context, update_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

65

for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

99

void dcn351_hw_block_power_down(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h

32

void dcn351_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h

34

void dcn351_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h

36

void dcn351_hw_block_power_up(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h

38

void dcn351_hw_block_power_down(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c

168

void dcn351_hw_sequencer_construct(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c

170

dc->hwss = dcn351_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c

171

dc->hwseq->funcs = dcn351_private_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.h

29

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.h

31

void dcn351_hw_sequencer_construct(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1003

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1004

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1012

if (!dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1019

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1034

if (dc->res_pool->dccg->funcs->set_pixel_rate_div) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1035

dc->res_pool->dccg->funcs->set_pixel_rate_div(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1036

dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1045

if (dc->hwss.program_dmdata_engine)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1046

dc->hwss.program_dmdata_engine(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1049

dc->hwss.update_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1052

dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1075

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1080

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1096

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1098

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1101

link->dc->hwss.edp_backlight_control &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1103

link->dc->hwss.edp_backlight_control(link, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1116

link->dc->hwss.edp_backlight_control &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1118

link->dc->hwss.edp_power_control(link, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1122

dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1132

.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1299

static bool dcn401_check_no_memory_request_for_cab(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1304

for (i = 0; i < dc->current_state->stream_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1305

if ((dc->current_state->stream_status[i].plane_count) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1306

(dc->current_state->streams[i]->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1314

static uint32_t dcn401_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1325

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1331

mall_ss_size_bytes += dcn32_helper_calculate_mall_bytes_for_cursor(dc, pipe, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1335

if (dc->debug.force_mall_ss_num_ways > 0)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1336

num_ways = dc->debug.force_mall_ss_num_ways;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1337

else if (dc->res_pool->funcs->calculate_mall_ways_from_bytes)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1338

num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, mall_ss_size_bytes);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1345

bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1354

if (!dc->ctx->dmub_srv || !dc->current_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1357

for (i = 0; i < dc->current_state->stream_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1359

if (dc->current_state->streams[i] != NULL &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1360

dc->current_state->streams[i]->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1371

if (dcn401_check_no_memory_request_for_cab(dc)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1382

ways = dcn401_calculate_cab_allocation(dc, dc->current_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1387

for (i = 0; i < dc->current_state->stream_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1388

for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1389

plane = dc->current_state->stream_status[i].plane_states[j];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1400

if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

141

void dcn401_init_hw(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1415

dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1420

void dcn401_wait_for_dcc_meta_propagation(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

143

struct abm **abms = dc->res_pool->multiple_abms;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

144

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1440

if (is_wait_needed && dc->debug.dcc_meta_propagation_delay_us > 0) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1441

udelay(dc->debug.dcc_meta_propagation_delay_us);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1445

void dcn401_prepare_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1448

struct hubbub *hubbub = dc->res_pool->hubbub;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

145

struct dc_bios *dcb = dc->ctx->dc_bios;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1454

dc->optimized_required = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1458

if (dc->clk_mgr->dc_mode_softmax_enabled) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1459

int softmax_memclk_khz = dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

146

struct resource_pool *res_pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1461

if (dc->clk_mgr->clks.dramclk_khz <= softmax_memclk_khz &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1463

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1467

dc->clk_mgr->funcs->update_clocks(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1468

dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1476

dc->optimized_required |= hubbub->funcs->program_watermarks(hubbub,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1478

dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1482

dc->optimized_required |= hubbub->funcs->program_arbiter(hubbub, &context->bw_ctx.bw.dcn.arb_regs, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1488

dc->optimized_required |= (compbuf_size != dc->current_state->bw_ctx.bw.dcn.arb_regs.compbuf_size);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1493

if (dc->debug.fams2_config.bits.enable) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1494

dcn401_dmub_hw_control_lock(dc, context, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1495

dcn401_fams2_update_config(dc, context, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1496

dcn401_dmub_hw_control_lock(dc, context, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1507

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1511

struct hubbub *hubbub = dc->res_pool->hubbub;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1514

if (dc->debug.fams2_config.bits.enable) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1515

dcn401_dmub_hw_control_lock(dc, context, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1516

dcn401_fams2_update_config(dc, context, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1517

dcn401_dmub_hw_control_lock(dc, context, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1523

dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1530

if (dc->clk_mgr->dc_mode_softmax_enabled) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1531

int softmax_memclk_khz = dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1533

if (dc->clk_mgr->clks.dramclk_khz > softmax_memclk_khz &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1535

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

154

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1542

dc->clk_mgr->funcs->update_clocks(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1543

dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1547

for (i = 0; i < dc->res_pool->pipe_count; ++i) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

155

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1559

void dcn401_dmub_hw_control_lock(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1567

if (!dc->ctx || !dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1570

if (!dc->debug.fams2_config.bits.enable && !dc_dmub_srv_is_cursor_offload_enabled(dc))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1577

dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

158

dc->caps.dcmode_power_limits_present = dc->clk_mgr->funcs->is_dc_mode_present &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1582

struct dc *dc = params->dmub_hw_control_lock_fast_params.dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

159

dc->clk_mgr->funcs->is_dc_mode_present(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1592

dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1596

void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1602

if (!dc->ctx || !dc->ctx->dmub_srv || !dc->debug.fams2_config.bits.enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1609

dc_dmub_srv_fams2_update_config(dc, context, enable && fams2_info_required);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1612

static void update_dsc_for_odm_change(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1622

old_otg_master = &dc->current_state->res_ctx.pipe_ctx[otg_master->pipe_idx];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1626

&dc->current_state->res_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1651

void dcn401_update_odm(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1686

update_dsc_for_odm_change(dc, context, otg_master);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1693

dc->hwseq->funcs.blank_pixel_data(dc, otg_master, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1696

static void dcn401_add_dsc_sequence_for_odm_change(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1706

old_otg_master = &dc->current_state->res_ctx.pipe_ctx[otg_master->pipe_idx];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1710

&dc->current_state->res_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

172

if (dc->debug.enable_mem_low_power.bits.optc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1722

bool should_use_dto_dscclk = (dc->res_pool->dccg->funcs->set_dto_dscclk != NULL) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1733

hwss_add_dccg_set_dto_dscclk(seq_state, dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1751

hwss_add_dccg_set_dto_dscclk(seq_state, dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

177

if (dc->debug.enable_mem_low_power.bits.vga) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1788

void dcn401_update_odm_sequence(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

182

if (dc->ctx->dc_bios->fw_info_valid) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1823

dcn401_add_dsc_sequence_for_odm_change(dc, context, otg_master, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1827

if (dc->hwseq->funcs.blank_pixel_data_sequence)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1828

dc->hwseq->funcs.blank_pixel_data_sequence(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1829

dc, otg_master, true, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1839

struct dce_hwseq *hws = link->dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

184

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1848

if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1866

void dcn401_hardware_release(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1868

if (!dc->debug.disable_force_pstate_allow_on_hw_release) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1869

if (dc->ctx->dmub_srv && dc->debug.fams2_config.bits.enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1870

dc_dmub_srv_fams2_update_config(dc, dc->current_state, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1875

if (dc->current_state) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1876

if ((!dc->clk_mgr->clks.p_state_change_support ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1877

dc->current_state->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1878

dc->res_pool->hubbub->funcs->force_pstate_change_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1879

dc->res_pool->hubbub->funcs->force_pstate_change_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

188

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1880

dc->res_pool->hubbub, true, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1882

dc->current_state->bw_ctx.bw.dcn.clk.p_state_change_support = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1883

dc->clk_mgr->funcs->update_clocks(dc->clk_mgr, dc->current_state, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1886

if (dc->current_state) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1887

dc->clk_mgr->clks.p_state_change_support = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1888

dc->clk_mgr->funcs->update_clocks(dc->clk_mgr, dc->current_state, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1891

if (dc->ctx->dmub_srv && dc->debug.fams2_config.bits.enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1892

dc_dmub_srv_fams2_update_config(dc, dc->current_state, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1896

void dcn401_wait_for_det_buffer_update_under_otg_master(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1900

struct hubbub *hubbub = dc->res_pool->hubbub;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1929

void dcn401_interdependent_update_lock(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1937

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1945

dc->hwss.pipe_control_lock(dc, pipe, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1949

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1959

if (dc->scratch.pipes_to_unlock_first[i]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1960

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1961

dc->hwss.pipe_control_lock(dc, pipe, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1963

dcn401_wait_for_det_buffer_update_under_otg_master(dc, dc->current_state, old_pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1968

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1969

if (dc->scratch.pipes_to_unlock_first[i])

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1980

dc->hwss.pipe_control_lock(dc, pipe, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2036

void dcn401_program_outstanding_updates(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2039

struct hubbub *hubbub = dc->res_pool->hubbub;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2047

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

206

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2067

dc->link_srv->set_dpms_off(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2069

dc->hwss.disable_audio_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2077

if (dc->caps.dynamic_audio == true) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2080

update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2092

dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

211

struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2116

if (dc->res_pool->dccg->funcs->set_dtbclk_p_src)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2117

dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, REFCLK, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2133

static void dc_hwss_disable_otg_pwa(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2135

if (dc->debug.enable_otg_frame_sync_pwa) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2139

for (i = dc->res_pool->timing_generator_count - 1; i >= 0 ; i--) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2140

struct timing_generator *tg = dc->res_pool->timing_generators[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2151

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2155

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2157

dc_hwss_disable_otg_pwa(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2159

for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2161

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2175

hws->funcs.reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2177

hws->funcs.enable_stream_gating(dc, pipe_ctx_old);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2211

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2231

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2235

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2239

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2246

hws->funcs.blank_pixel_data(dc, pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2254

dcn401_program_tg(dc, pipe_ctx, context, hws);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2257

hws->funcs.update_odm(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2261

hws->funcs.enable_plane(dc, pipe_ctx, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2263

dc->hwss.enable_plane(dc, pipe_ctx, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2265

if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2266

dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2270

if (dc->res_pool->hubbub->funcs->program_det_size)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2271

dc->res_pool->hubbub->funcs->program_det_size(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2272

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2273

if (dc->res_pool->hubbub->funcs->program_det_segments)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2274

dc->res_pool->hubbub->funcs->program_det_segments(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2275

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2281

dc->hwss.update_dchubp_dpp(dc, pipe_ctx, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2292

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2301

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2326

dc->hwss.set_pipe(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

233

hws->funcs.enable_power_gating_plane(dc->hwseq, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2338

dc->hwss.set_disp_pattern_generator(dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2351

hws->funcs.program_cm_hist(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

236

dc->link_srv->blank_all_dp_displays(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2364

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2369

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2376

if (dc->hwseq->funcs.blank_pixel_data_sequence)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2377

dc->hwseq->funcs.blank_pixel_data_sequence(dc, pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2404

dcn401_setup_vupdate_interrupt_sequence(dc, pipe_ctx, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2409

hws->funcs.update_odm_sequence(dc, context, pipe_ctx, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2413

if (dc->hwss.enable_plane_sequence)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2414

dc->hwss.enable_plane_sequence(dc, pipe_ctx, context, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2418

if (dc->res_pool->hubbub->funcs->program_det_size) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2419

hwss_add_hubp_program_det_size(seq_state, dc->res_pool->hubbub,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2423

if (dc->res_pool->hubbub->funcs->program_det_segments) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2424

hwss_add_hubp_program_det_segments(seq_state, dc->res_pool->hubbub,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2433

if (dc->hwss.update_dchubp_dpp_sequence)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2434

dc->hwss.update_dchubp_dpp_sequence(dc, pipe_ctx, context, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

244

if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2449

hwss_add_dpp_set_input_transfer_func(seq_state, dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2459

hwss_add_dpp_set_output_transfer_func(seq_state, dc, pipe_ctx, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

248

if (dc->hwss.enable_accelerated_mode && dc->debug.disable_boot_optimizations)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2480

hwss_add_abm_set_pipe(seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

249

dc->hwss.enable_accelerated_mode(dc, dc->current_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

251

hws->funcs.init_pipes(dc, dc->current_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2513

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2519

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2522

if (resource_is_pipe_topology_changed(dc->current_state, context))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2523

resource_log_pipe_topology_update(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2525

if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2526

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

253

if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2534

dc->hwss.program_triplebuffer(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2535

dc, pipe, pipe->plane_state->triplebuffer_flips);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

254

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2540

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2541

if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2548

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2549

dc->res_pool->hubbub->funcs->force_pstate_change_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

255

!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2550

dc->res_pool->hubbub, true, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2555

for (i = 0; i < dc->res_pool->pipe_count; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2556

dc->hwss.detect_pipe_changes(dc->current_state, context, &dc->current_state->res_ctx.pipe_ctx[i],

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2562

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2563

struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2565

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2568

dc_state_get_pipe_subvp_type(dc->current_state, pipe) == SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2569

struct timing_generator *tg = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

257

dcn401_initialize_min_clocks(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2572

if (dc->hwseq->funcs.blank_pixel_data)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2573

dc->hwseq->funcs.blank_pixel_data(dc, pipe, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2580

for (i = 0; i < dc->res_pool->pipe_count; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2585

hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2588

for (i = 0; i < dc->res_pool->pipe_count; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2591

struct hubbub *hubbub = dc->res_pool->hubbub;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2605

dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2606

if (dc->res_pool->hubbub->funcs->program_det_segments)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2607

dc->res_pool->hubbub->funcs->program_det_segments(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2608

hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2610

hws->funcs.plane_atomic_disconnect(dc, dc->current_state,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2611

&dc->current_state->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2612

DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2616

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2622

hws->funcs.update_odm(dc, context, pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2629

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2635

hws->funcs.program_pipe(dc, pipe, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2647

dcn401_program_pipe(dc, pipe, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

266

dc_allow_idle_optimizations(dc, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2661

hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2668

dc->current_state->stream_status[0].plane_count == 1 &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

267

dc_allow_idle_optimizations(dc, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2676

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2682

struct dce_hwseq *hwseq = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2685

for (i = 0; i < dc->res_pool->pipe_count; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2686

if (resource_is_pipe_type(&dc->current_state->res_ctx.pipe_ctx[i], OPP_HEAD) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2688

dc->hwss.post_unlock_reset_opp(dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2689

&dc->current_state->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2691

for (i = 0; i < dc->res_pool->pipe_count; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2693

dc->hwss.disable_plane(dc, dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2701

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2715

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2717

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2737

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2738

dc->res_pool->hubbub->funcs->force_pstate_change_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2739

dc->res_pool->hubbub, false, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2742

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

275

if (!dc->config.seamless_boot_edp_requested) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2756

if (dc->hwss.apply_update_flags_for_phantom)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2757

dc->hwss.apply_update_flags_for_phantom(pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2758

if (dc->hwss.update_phantom_vp_position)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2759

dc->hwss.update_phantom_vp_position(dc, context, pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2760

dcn401_program_pipe(dc, pipe, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2778

dc->hwseq->funcs.update_force_pstate(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2783

hwseq->funcs.program_mall_pipe_config(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2787

dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

279

dc_get_edp_links(dc, edp_links, &edp_num);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2793

if (dc->current_state->stream_status[0].plane_count == 1 &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2796

struct timing_generator *tg = dc->res_pool->timing_generators[0];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2798

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2808

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2812

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2815

if (dc->res_pool->funcs->validate_bandwidth(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING) != DC_OK)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2819

dc->hwss.prepare_bandwidth(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2822

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2843

hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2846

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

285

dc->hwss.edp_backlight_control &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

287

dc->hwss.edp_power_control) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

288

dc->hwss.edp_backlight_control(edp_link, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

289

hws->funcs.power_down(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

290

dc->hwss.edp_power_control(edp_link, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

294

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

295

struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

302

hws->funcs.power_down(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3057

void dcn401_plane_atomic_power_down(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3061

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3091

void dcn401_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3093

volatile struct dmub_cursor_offload_v1 *cs = dc->ctx->dmub_srv->dmub->cursor_offload_v1;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3147

void dcn401_plane_atomic_power_down_sequence(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3152

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3159

hwss_add_dc_ip_request_cntl(seq_state, dc, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

316

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

317

struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3176

hwss_add_dc_ip_request_cntl(seq_state, dc, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3185

void dcn401_plane_atomic_disconnect_sequence(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3192

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3215

hwss_add_dc_set_optimized_required(seq_state, dc, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3222

if (dc->debug.sanity_checks)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3223

dc->hwseq->funcs.verify_allow_pstate_change_high_sequence(dc, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3227

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

324

if (link->ctx->dc->config.dp_connector_no_native_i2c && link->no_ddc_pin) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3245

color_space_to_black_color(dc, color_space, &black_color);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3249

hwss_add_abm_set_immediate_disable(seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3251

if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3297

hwss_add_abm_set_pipe(seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3306

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3313

unsigned int num_dwb_cap = (unsigned int)dc->res_pool->res_cap->num_dwb;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3326

for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3342

dcn401_disable_writeback_sequence(dc, wb_info, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3346

ASSERT(wb_info->dwb_pipe_inst < dc->res_pool->res_cap->num_dwb);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3347

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3351

dcn401_update_writeback_sequence(dc, wb_info, context, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3354

dcn401_enable_writeback_sequence(dc, wb_info, context, mpcc_inst, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3358

dcn401_disable_writeback_sequence(dc, wb_info, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3364

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3373

if (!wb_info->wb_enabled || wb_info->dwb_pipe_inst >= dc->res_pool->res_cap->num_dwb)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3376

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3377

mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3392

hwss_add_mpc_set_dwb_mux(seq_state, dc->res_pool->mpc, wb_info->dwb_pipe_inst, mpcc_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3399

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3406

if (wb_info->dwb_pipe_inst >= dc->res_pool->res_cap->num_dwb)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3409

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3410

mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3416

hwss_add_mpc_disable_dwb_mux(seq_state, dc->res_pool->mpc, wb_info->dwb_pipe_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3423

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3432

if (!wb_info->wb_enabled || wb_info->dwb_pipe_inst >= dc->res_pool->res_cap->num_dwb)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3435

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3436

mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3445

static int find_free_gsl_group(const struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3447

if (dc->res_pool->gsl_groups.gsl_0 == 0)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3449

if (dc->res_pool->gsl_groups.gsl_1 == 0)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3451

if (dc->res_pool->gsl_groups.gsl_2 == 0)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3458

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3475

group_idx = find_free_gsl_group(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3483

dc->res_pool->gsl_groups.gsl_0 = 1;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3487

dc->res_pool->gsl_groups.gsl_1 = 1;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3491

dc->res_pool->gsl_groups.gsl_2 = 1;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3509

dc->res_pool->gsl_groups.gsl_0 = 0;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

351

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3513

dc->res_pool->gsl_groups.gsl_1 = 0;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3517

dc->res_pool->gsl_groups.gsl_2 = 0;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3531

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3543

if (dc->hwss.wait_for_mpcc_disconnect_sequence)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3544

dc->hwss.wait_for_mpcc_disconnect_sequence(dc, dc->res_pool, pipe_ctx, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3550

dcn401_setup_gsl_group_as_lock_sequence(dc, pipe_ctx, false, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3566

if (dc->hwseq->funcs.plane_atomic_power_down_sequence)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3567

dc->hwseq->funcs.plane_atomic_power_down_sequence(dc, pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

357

if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

358

dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3585

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3590

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3595

if (dc->hwss.wait_for_mpcc_disconnect_sequence)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3596

dc->hwss.wait_for_mpcc_disconnect_sequence(dc, dc->res_pool, opp_head, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

360

if (!dc->debug.disable_clock_gate) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3601

if (dc->hwseq && dc->hwseq->funcs.dsc_pg_status)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3602

hwss_add_dsc_pg_status(seq_state, dc->hwseq, dsc->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

362

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3622

void dcn401_dc_ip_request_cntl(struct dc *dc, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3624

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

363

dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3630

void dcn401_enable_plane_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3635

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3650

hwss_add_dc_ip_request_cntl(seq_state, dc, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3662

hwss_add_dc_ip_request_cntl(seq_state, dc, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3677

if (dc->vm_pa_config.valid && pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3679

dc->vm_pa_config.system_aperture.start_addr, dc->vm_pa_config.system_aperture.end_addr);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3691

void dcn401_update_dchubp_dpp_sequence(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3696

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

370

if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3700

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

371

dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

373

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->notify_wm_ranges)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

374

dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

376

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3769

hws->funcs.update_mpcc_sequence(dc, pipe_ctx, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

377

dc->res_pool->hubbub->funcs->force_pstate_change_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

378

dc->res_pool->hubbub, false, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3785

(context == dc->current_state && plane_state->update_flags.bits.position_change) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3786

(context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3787

(context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

380

if (dc->res_pool->hubbub->funcs->init_crb)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3802

hwss_add_abort_cursor_offload_update(seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3804

hwss_add_set_cursor_attribute(seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3807

hwss_add_set_cursor_position(seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

381

dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3810

if (dc->hwss.set_cursor_sdr_white_level)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3811

hwss_add_set_cursor_sdr_white_level(seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3825

hwss_add_program_output_csc(seq_state, dc, pipe_ctx, pipe_ctx->stream->output_color_space,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

383

if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

384

dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3858

hwss_add_dmub_subvp_save_surf_addr(seq_state, dc->ctx->dmub_srv,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3863

hwss_add_hubp_update_plane_addr(seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

387

if (dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3875

void dcn401_update_mpcc_sequence(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

388

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3884

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

389

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

390

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver > 0;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

391

dc->caps.dmub_caps.fams_ver = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3934

hwss_add_mpc_update_visual_confirm(seq_state, dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

394

dc->debug.fams2_config.bits.enable &=

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3946

if (dc->debug.sanity_checks)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

395

dc->caps.dmub_caps.fams_ver == dc->debug.fams_version.ver;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3954

hwss_add_mpc_update_visual_confirm(seq_state, dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3974

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

398

if ((!dc->debug.fams2_config.bits.enable || dchub_ref_freq_changed) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3981

if (dc->debug.sanity_checks)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3982

dc->hwseq->funcs.verify_allow_pstate_change_high_sequence(dc, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

399

dc->res_pool->funcs->update_bw_bounding_box &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

400

dc->clk_mgr && dc->clk_mgr->bw_params) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4001

if (dc->debug.sanity_checks)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4002

dc->hwseq->funcs.verify_allow_pstate_change_high_sequence(dc, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4005

void dcn401_setup_vupdate_interrupt_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4009

int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

402

dc->res_pool->funcs->update_bw_bounding_box(dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

403

dc->clk_mgr->bw_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4035

void dcn401_program_mall_pipe_config_sequence(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4039

unsigned int num_ways = dcn401_calculate_cab_allocation(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4045

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4076

uint32_t mall_sel = (num_ways <= dc->caps.cache_num_ways &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

408

static void dcn401_get_mcm_lut_xable_from_pipe_ctx(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4086

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4097

void dcn401_verify_allow_pstate_change_high_sequence(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4100

struct hubbub *hubbub = dc->res_pool->hubbub;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4107

dcn401_hw_wa_force_recovery_sequence(dc, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4111

bool dcn401_hw_wa_force_recovery_sequence(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4117

if (!dc->debug.recovery_enabled)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4121

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4122

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4132

hwss_add_hubbub_soft_reset(seq_state, dc->res_pool->hubbub, hubbub1_soft_reset, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4135

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4136

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4146

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4147

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

415

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4157

hwss_add_hubbub_soft_reset(seq_state, dc->res_pool->hubbub, hubbub1_soft_reset, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4160

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4161

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

441

void dcn401_populate_mcm_luts(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

449

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

464

dcn401_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, &shaper_xable, &lut3d_xable, &lut1d_xable);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

52

dc->ctx->logger

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

524

if (dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_33)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

59

void dcn401_initialize_min_clocks(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

61

struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

64

clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

642

void dcn401_trigger_3dlut_dma_load(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

644

(void)dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

65

clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

657

struct dc *dc = pipe_ctx->stream_res.opp->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

658

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

66

clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

664

dcn401_populate_mcm_luts(dc, pipe_ctx, plane_state->mcm_luts, plane_state->lut_bank_a);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

67

clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

68

if (dc->debug.disable_boot_optimizations) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

69

clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

705

bool dcn401_set_output_transfer_func(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

709

(void)dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

711

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

76

if (dc->clk_mgr->funcs->get_dispclk_from_dentist) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

762

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

77

clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

771

(void)dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

79

clocks->dispclk_khz = dc->clk_mgr->boot_snapshot.dispclk * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

806

struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

808

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

82

clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

826

enable_stream_timing_calc(pipe_ctx, context, dc, &tmds_div, opp_inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

829

if (dc->res_pool->dccg->funcs->set_pixel_rate_div) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

830

dc->res_pool->dccg->funcs->set_pixel_rate_div(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

831

dc->res_pool->dccg, pipe_ctx->stream_res.tg->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

847

if (dc->res_pool->dccg->funcs->set_dtbclk_p_src) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

849

dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, DPREFCLK, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

851

dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, DTBCLK0, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

86

dc->clk_mgr->funcs->update_clocks(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

863

dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

869

if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal)))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

87

dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

870

dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

873

if (dc->debug.enable_hblank_borrow) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

88

dc->current_state,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

906

hws->funcs.blank_pixel_data(dc, pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

967

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

97

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

973

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

100

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

104

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

109

void dcn401_program_front_end_for_ctx(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

110

void dcn401_post_unlock_program_front_end(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

111

bool dcn401_update_bandwidth(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

117

void dcn401_plane_atomic_power_down(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

120

void dcn401_plane_atomic_power_down_sequence(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

124

void dcn401_plane_atomic_disconnect_sequence(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

129

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

133

void dcn401_initialize_min_clocks(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

134

void dcn401_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

137

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

143

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

15

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

150

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

155

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

161

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

167

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

173

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

177

void dcn401_dc_ip_request_cntl(struct dc *dc, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

179

void dcn401_enable_plane_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

183

void dcn401_update_dchubp_dpp_sequence(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

188

void dcn401_update_mpcc_sequence(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

193

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

198

void dcn401_setup_vupdate_interrupt_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

204

void dcn401_program_mall_pipe_config_sequence(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

207

void dcn401_verify_allow_pstate_change_high_sequence(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

210

bool dcn401_hw_wa_force_recovery_sequence(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

37

void dcn401_init_hw(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

41

bool dcn401_set_output_transfer_func(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

44

void dcn401_trigger_3dlut_dma_load(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

51

struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

53

void dcn401_populate_mcm_luts(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

65

bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

67

void dcn401_wait_for_dcc_meta_propagation(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

70

void dcn401_prepare_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

74

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

77

void dcn401_dmub_hw_control_lock(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

80

void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

83

void dcn401_hardware_release(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

84

void dcn401_update_odm(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

86

void dcn401_update_odm_sequence(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

89

void dcn401_wait_for_det_buffer_update_under_otg_master(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

90

void dcn401_interdependent_update_lock(struct dc *dc, struct dc_state *context, bool lock);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

91

void dcn401_program_outstanding_updates(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

93

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

97

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c

175

void dcn401_hw_sequencer_init_functions(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c

177

dc->hwss = dcn401_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c

178

dc->hwseq->funcs = dcn401_private_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.h

10

void dcn401_hw_sequencer_init_functions(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.h

8

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1016

if (dc->caps.sequential_ono) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

102

if (dc->ctx->dc_bios->fw_info_valid) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1039

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

104

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1040

update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1041

if (dc->links[i]->type != dc_connection_none)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1042

update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1046

for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1047

struct timing_generator *tg = dc->res_pool->timing_generators[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1052

if (dc->res_pool->pg_cntl->funcs->optc_pg_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1053

dc->res_pool->pg_cntl->funcs->optc_pg_control(dc->res_pool->pg_cntl, i, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1057

for (i = 0; i < dc->res_pool->hpo_frl_stream_enc_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1058

if (dc->current_state->res_ctx.is_hpo_frl_stream_enc_acquired[i]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1066

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1072

if (dc->hwss.calc_blocks_to_ungate) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1073

dc->hwss.calc_blocks_to_ungate(dc, context, &pg_update_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1075

if (dc->hwss.root_clock_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1076

dc->hwss.root_clock_control(dc, &pg_update_state, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1078

if (dc->hwss.hw_block_power_up)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1079

dc->hwss.hw_block_power_up(dc, &pg_update_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

108

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1082

dcn401_prepare_bandwidth(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1085

void dcn42_optimize_bandwidth(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1089

print_pg_status(dc, __func__, ": before rcg and power up");

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1091

dcn401_optimize_bandwidth(dc, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1093

if (dc->hwss.calc_blocks_to_gate) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1094

dc->hwss.calc_blocks_to_gate(dc, context, &pg_update_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1096

if (dc->hwss.hw_block_power_down)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1097

dc->hwss.hw_block_power_down(dc, &pg_update_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1099

if (dc->hwss.root_clock_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1100

dc->hwss.root_clock_control(dc, &pg_update_state, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1103

print_pg_status(dc, __func__, ": after rcg and power up");

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1107

void dcn42_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1117

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1118

struct pipe_ctx *cur_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1187

for (i = 0; i < dc->link_count; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1188

if (dc->links[i]->type != dc_connection_none)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1189

update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1191

for (i = 0; i < dc->res_pool->stream_enc_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1192

if (dc->current_state->res_ctx.is_stream_enc_acquired[i]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1197

for (i = 0; i < dc->res_pool->hpo_frl_stream_enc_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1199

dc->res_pool->hpo_frl_stream_enc[i]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1205

for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1207

dc->res_pool->hpo_dp_stream_enc[i]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1218

if (count_active_streams(dc) > 0) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1251

void dcn42_hw_block_power_down(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1255

int pipe_count = dc->res_pool->pipe_count;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1256

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

126

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1261

if (dc->debug.ignore_pg)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1282

for (i = dc->res_pool->res_cap->num_dsc-1; i >= 0; i--) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

131

struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1341

void dcn42_hw_block_power_up(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1345

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1350

if (dc->debug.ignore_pg)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1365

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1378

for (i = 0; i < (unsigned int)dc->res_pool->res_cap->num_dsc; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1390

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1402

void dcn42_root_clock_control(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1406

struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1412

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1415

if (dc->hwseq->funcs.dpp_root_clock_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1416

dc->hwseq->funcs.dpp_root_clock_control(dc->hwseq, i, power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1419

if (dc->hwseq->funcs.dpstream_root_clock_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1420

dc->hwseq->funcs.dpstream_root_clock_control(dc->hwseq, i, power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1423

for (i = 0; i < dc->res_pool->dig_link_enc_count; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1425

if (dc->hwseq->funcs.physymclk_root_clock_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1426

dc->hwseq->funcs.physymclk_root_clock_control(dc->hwseq, i, power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1429

if (dc->hwseq->funcs.hdmistream_root_clock_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1430

dc->hwseq->funcs.hdmistream_root_clock_control(dc->hwseq, power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1432

for (i = 0; i < (unsigned int)dc->res_pool->res_cap->num_dsc; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1435

if (dc->res_pool->dccg->funcs->enable_dsc)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1436

dc->res_pool->dccg->funcs->enable_dsc(dc->res_pool->dccg, i);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1438

if (dc->res_pool->dccg->funcs->disable_dsc)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1439

dc->res_pool->dccg->funcs->disable_dsc(dc->res_pool->dccg, i);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1445

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1448

if (dc->hwseq->funcs.dpp_root_clock_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1449

dc->hwseq->funcs.dpp_root_clock_control(dc->hwseq, i, power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1452

if (dc->hwseq->funcs.dpstream_root_clock_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1453

dc->hwseq->funcs.dpstream_root_clock_control(dc->hwseq, i, power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1456

for (i = 0; i < dc->res_pool->dig_link_enc_count; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1458

if (dc->hwseq->funcs.physymclk_root_clock_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1459

dc->hwseq->funcs.physymclk_root_clock_control(dc->hwseq, i, power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1462

if (dc->hwseq->funcs.hdmistream_root_clock_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1463

dc->hwseq->funcs.hdmistream_root_clock_control(dc->hwseq, power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1466

void dcn42_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1468

(void)dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1486

void dcn42_dmub_hw_control_lock(struct dc *dc, struct dc_state *context, bool lock)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1491

if (!dc->ctx || !dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1496

if (!dc->debug.fams2_config.bits.enable && !dc_dmub_srv_is_cursor_offload_enabled(dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1497

&& !dmub_hw_lock_mgr_does_context_require_lock(dc, context))

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1504

dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1509

struct dc *dc = params->dmub_hw_control_lock_fast_params.dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1519

dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1528

void dcn42_power_down_on_boot(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

153

hws->funcs.enable_power_gating_plane(dc->hwseq, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1535

dc_get_edp_links(dc, edp_links, &edp_num);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1541

dc->hwseq->funcs.edp_backlight_control &&

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1542

dc->hwseq->funcs.power_down &&

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1543

dc->hwss.edp_power_control) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1544

dc->hwseq->funcs.edp_backlight_control(edp_link, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1545

dc->hwseq->funcs.power_down(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1546

dc->hwss.edp_power_control(edp_link, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1548

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1549

struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1553

dc->hwseq->funcs.power_down) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1554

dc->hwseq->funcs.power_down(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

156

dc->link_srv->blank_all_dp_displays(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1566

if (dc->clk_mgr->funcs->set_low_power_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1567

dc->clk_mgr->funcs->set_low_power_state(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

164

if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

168

if (dc->hwss.enable_accelerated_mode && dc->debug.disable_boot_optimizations)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

169

dc->hwss.enable_accelerated_mode(dc, dc->current_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

171

hws->funcs.init_pipes(dc, dc->current_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

173

if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

174

dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

175

!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

184

if (!dc->config.seamless_boot_edp_requested) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

188

dc_get_edp_links(dc, edp_links, &edp_num);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

194

dc->hwss.edp_backlight_control &&

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

196

dc->hwss.edp_power_control) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

197

dc->hwss.edp_backlight_control(edp_link, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

198

hws->funcs.power_down(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

199

dc->hwss.edp_power_control(edp_link, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

203

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

204

struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

210

hws->funcs.power_down(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

224

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

225

struct dc_link *link = dc->links[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

233

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

239

if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

240

dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

242

if (!dc->debug.disable_clock_gate) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

251

if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

252

dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

254

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->notify_wm_ranges)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

255

dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

257

if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

258

dc->res_pool->hubbub->funcs->force_pstate_change_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

259

dc->res_pool->hubbub, false, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

261

if (dc->res_pool->hubbub->funcs->init_crb)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

262

dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

264

if (dc->res_pool->hubbub->funcs->set_request_limit &&

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

265

dc->clk_mgr && dc->clk_mgr->bw_params &&

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

266

dc->config.sdpif_request_limit_words_per_umc > 0)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

267

dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

268

dc->clk_mgr->bw_params->num_channels,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

269

dc->config.sdpif_request_limit_words_per_umc);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

272

if (dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

273

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

274

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

275

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver > 0;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

276

dc->caps.dmub_caps.fams_ver = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

279

dc->debug.fams2_config.bits.enable &=

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

280

dc->caps.dmub_caps.fams_ver == dc->debug.fams_version.ver;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

284

if ((!dc->debug.fams2_config.bits.enable || dchub_ref_freq_changed) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

285

dc->res_pool->funcs->update_bw_bounding_box &&

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

286

dc->clk_mgr && dc->clk_mgr->bw_params) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

288

dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

291

if (dc->res_pool->pg_cntl) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

292

if (dc->res_pool->pg_cntl->funcs->init_pg_status)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

293

dc->res_pool->pg_cntl->funcs->init_pg_status(dc->res_pool->pg_cntl);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

295

print_pg_status(dc, __func__, ": after init_pg_status");

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

298

void dcn42_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

305

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

354

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

364

if (dc->debug.sanity_checks)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

366

dc->res_pool->mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

369

new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

376

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

384

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

388

(void)dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

468

static bool is_rmcm_3dlut_fl_supported(struct dc *dc, enum dc_cm2_gpu_mem_size size)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

470

if (!dc->caps.color.mpc.rmcm_3d_lut_caps.dma_3d_lut)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

473

return dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_17 != 0u;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

475

return dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_33 != 0u;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

479

static void dcn42_set_mcm_location_post_blend(struct dc *dc, struct pipe_ctx *pipe_ctx, bool bPostBlend)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

481

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

493

static void dcn42_get_mcm_lut_xable_from_pipe_ctx(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

500

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

54

static void print_pg_status(struct dc *dc, const char *debug_func, const char *debug_log)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

56

if (dc->debug.enable_pg_cntl_debug_logs && dc->res_pool->pg_cntl) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

57

if (dc->res_pool->pg_cntl->funcs->print_pg_status)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

579

struct dc *dc = hubp->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

58

dc->res_pool->pg_cntl->funcs->print_pg_status(dc->res_pool->pg_cntl, debug_func, debug_log);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

586

struct dc_rmcm_3dlut *rmcm_3dlut = dc_stream_get_3dlut_for_stream(dc, stream, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

594

dcn42_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, &shaper_xable, &lut3d_xable, &lut1d_xable);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

605

dc->ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

61

void dcn42_init_hw(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

63

struct abm **abms = dc->res_pool->multiple_abms;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

64

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

65

struct dc_bios *dcb = dc->ctx->dc_bios;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

66

struct resource_pool *res_pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

694

void dcn42_populate_mcm_luts(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

702

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

717

dcn42_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, &shaper_xable, &lut3d_xable, &lut1d_xable);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

722

dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

728

is_rmcm_3dlut_fl_supported(dc, mcm_luts.lut3d_data.gpu_mem_params.size)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

74

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

75

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

78

dc->caps.dcmode_power_limits_present = dc->clk_mgr->funcs->is_dc_mode_present &&

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

79

dc->clk_mgr->funcs->is_dc_mode_present(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

898

struct dc *dc = pipe_ctx->stream_res.opp->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

899

struct mpc *mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

905

dcn42_populate_mcm_luts(dc, pipe_ctx, plane_state->mcm_luts, plane_state->lut_bank_a);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

92

if (dc->debug.enable_mem_low_power.bits.optc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

945

void dcn42_hardware_release(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

947

dcn35_hardware_release(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

948

dc_dmub_srv_release_hw(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

951

static int count_active_streams(const struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

955

for (i = 0; i < dc->current_state->stream_count; ++i) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

956

struct dc_stream_state *stream = dc->current_state->streams[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

958

if (stream && (!stream->dpms_off || dc->config.disable_ips_in_dpms_off))

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

965

void dcn42_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

97

if (dc->debug.enable_mem_low_power.bits.vga) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

977

for (i = 0; i < dc->res_pool->hpo_frl_stream_enc_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

979

dc->res_pool->hpo_frl_stream_enc[i]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

985

for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

987

dc->res_pool->hpo_dp_stream_enc[i]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

996

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

10

void dcn42_init_hw(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

11

void dcn42_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

14

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

21

void dcn42_populate_mcm_luts(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

34

void dcn42_hardware_release(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

37

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

39

void dcn42_optimize_bandwidth(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

40

void dcn42_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

42

void dcn42_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

44

void dcn42_hw_block_power_down(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

46

void dcn42_hw_block_power_up(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

48

void dcn42_root_clock_control(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

50

void dcn42_dmub_hw_control_lock(struct dc *dc, struct dc_state *context, bool lock);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

52

void dcn42_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

53

void dcn42_power_down_on_boot(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c

170

void dcn42_hw_sequencer_init_functions(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c

172

dc->hwss = dcn42_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c

173

dc->hwseq->funcs = dcn42_private_funcs;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.h

7

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.h

9

void dcn42_hw_sequencer_init_functions(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

105

for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

112

dc->res_pool->mpc->funcs->mpc_init_single_inst(

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

113

dc->res_pool->mpc, i);

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

117

for (i = 0; i < dc->res_pool->res_cap->num_dwb; i++)

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

118

dc->res_pool->dwbc[i]->mcif = dc->res_pool->mcif_wb[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

120

for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

121

struct timing_generator *tg = dc->res_pool->timing_generators[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

122

struct hubp *hubp = dc->res_pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

123

struct dpp *dpp = dc->res_pool->dpps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

145

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

160

dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

161

dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

162

dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

163

pipe_ctx->stream_res.opp = dc->res_pool->opps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

165

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

170

dc->hwss.disable_plane(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

184

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

186

if (dc->res_pool->opps[i]->mpc_tree_params.opp_list) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

187

if (dc->res_pool->opps[i]->mpc_tree_params.opp_list->mpcc_bot) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

188

int bot_id = dc->res_pool->opps[i]->mpc_tree_params.opp_list->mpcc_bot->mpcc_id;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

191

dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

209

for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

211

struct timing_generator *tg = dc->res_pool->timing_generators[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

226

for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

229

dc->res_pool->dscs[i]->funcs->dsc_read_state(dc->res_pool->dscs[i], &s);

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

235

hws->funcs.dsc_pg_control(hws, dc->res_pool->dscs[i]->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

46

void dcn42b_init_pipes(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

49

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

50

struct hubbub *hubbub = dc->res_pool->hubbub;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

61

for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

62

struct timing_generator *tg = dc->res_pool->timing_generators[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

77

hws->funcs.init_blank(dc, tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

88

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

90

struct hubp *hubp = dc->res_pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.h

13

void dcn42b_init_pipes(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_init.c

12

void dcn42b_hw_sequencer_init_functions(struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_init.c

15

dcn42_hw_sequencer_init_functions(dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_init.c

18

dc->hwseq->funcs.init_pipes = dcn42b_init_pipes;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_init.h

10

struct dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_init.h

12

void dcn42b_hw_sequencer_init_functions(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

112

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1229

void (*hardware_release)(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1236

void (*init_hw)(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1237

void (*power_down_on_boot)(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1238

void (*enable_accelerated_mode)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1240

enum dc_status (*apply_ctx_to_hw)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1242

void (*disable_plane)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1243

void (*disable_plane_sequence)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1245

void (*disable_pixel_data)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1246

void (*apply_ctx_for_surface)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1249

void (*program_front_end_for_ctx)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1251

void (*wait_for_pending_cleared)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1253

void (*post_unlock_program_front_end)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1255

void (*update_plane_addr)(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1259

void (*wait_for_mpcc_disconnect)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1262

void (*wait_for_mpcc_disconnect_sequence)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1269

void (*program_triplebuffer)(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1272

void (*update_dsc_pg)(struct dc *dc, struct dc_state *context, bool safe_to_disable);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1276

void (*pipe_control_lock)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1278

void (*interdependent_update_lock)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1282

void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1289

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1293

void (*enable_per_frame_crtc_position_reset)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1295

void (*enable_timing_synchronization)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1299

void (*enable_vblanks_synchronization)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1302

void (*setup_periodic_interrupt)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1318

void (*prepare_bandwidth)(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1319

bool (*update_bandwidth)(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1320

void (*optimize_bandwidth)(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1337

void (*abort_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1338

void (*begin_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1339

void (*commit_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1340

void (*update_cursor_offload_pipe)(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1341

void (*notify_cursor_offload_drr_update)(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1343

void (*program_cursor_offload_now)(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1347

void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

135

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1350

void (*trigger_3dlut_dma_load)(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1354

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1357

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1362

void (*update_writeback)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1365

void (*enable_writeback)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1368

void (*disable_writeback)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1372

enum dc_status (*set_clock)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1375

void (*get_clock)(struct dc *dc, enum dc_clock_type clock_type,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1377

void (*optimize_pwr_state)(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1379

void (*exit_optimized_pwr_state)(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1381

void (*calculate_pix_rate_divider)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1390

void (*setup_stereo)(struct pipe_ctx *pipe_ctx, struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1393

void (*log_hw_state)(struct dc *dc, struct dc_log_buffer_ctx *log_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1394

void (*log_color_state)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1396

void (*get_hw_state)(struct dc *dc, char *pBuf,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1398

void (*clear_status_bits)(struct dc *dc, unsigned int mask);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

141

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1430

void (*get_dcc_en_bits)(struct dc *dc, int *dcc_en_bits);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1437

unsigned int (*get_max_dispclk_mhz)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1441

bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1443

bool (*does_plane_fit_in_mall)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1448

void (*commit_subvp_config)(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1449

void (*enable_phantom_streams)(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1450

void (*disable_phantom_streams)(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1451

void (*subvp_pipe_control_lock)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1459

void (*z10_restore)(const struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1460

void (*z10_save_init)(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1461

bool (*is_abm_supported)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1464

void (*set_disp_pattern_generator)(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1471

void (*blank_phantom)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1475

void (*update_visual_confirm_color)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1478

void (*update_phantom_vp_position)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1483

void (*calc_blocks_to_gate)(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1485

void (*calc_blocks_to_ungate)(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1487

void (*hw_block_power_up)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1489

void (*hw_block_power_down)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1491

void (*root_clock_control)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1493

bool (*is_pipe_topology_transition_seamless)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1496

void (*wait_for_dcc_meta_propagation)(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1498

void (*dmub_hw_control_lock)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1501

void (*fams2_update_config)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1506

void (*program_outstanding_updates)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1514

void (*enable_plane)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1517

void (*enable_plane_sequence)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1521

void (*update_dchubp_dpp)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1524

void (*update_dchubp_dpp_sequence)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1528

void (*post_unlock_reset_opp)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1531

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1534

void (*get_underflow_debug_data)(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1546

void (*measure_memory_qos)(struct dc *dc, struct dc_measured_memory_qos *qos);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1551

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1576

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1585

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1599

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1608

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1617

void hwss_execute_sequence(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1621

void hwss_build_fast_sequence(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1630

void hwss_wait_for_all_blank_complete(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1633

void hwss_wait_for_odm_update_pending_complete(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1636

void hwss_wait_for_no_pipes_pending(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1639

void hwss_wait_for_outstanding_hw_updates(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1642

void hwss_process_outstanding_hw_updates(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1727

void hwss_prepare_bandwidth(struct dc *dc, union block_sequence_params *params);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

173

const struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1741

void hwss_update_info_frame(struct dc *dc, union block_sequence_params *params);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

178

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1915

void hwss_setup_periodic_interrupt(struct dc *dc, union block_sequence_params *params);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1917

void hwss_disable_audio_stream(struct dc *dc, union block_sequence_params *params);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1920

struct dc *dc, struct pipe_ctx *pipe_ctx, bool lock);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1926

struct dc *dc, struct pipe_ctx *pipe_ctx, bool enableTripleBuffer);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1929

struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1932

struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1944

struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1947

struct dc *dc, struct pipe_ctx *pipe_ctx, int mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1965

struct dc *dc, struct pipe_ctx *top_pipe_to_program);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1974

struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2027

struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

206

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2063

struct dc *dc, bool optimized_required);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2066

struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2090

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

219

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2310

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2314

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2326

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2330

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2334

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2344

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2373

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2377

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2386

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2390

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2438

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2471

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

292

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

329

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

356

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

393

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

403

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

408

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

453

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

484

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

632

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

64

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

70

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

707

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

728

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

733

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

739

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

749

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

764

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

769

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

774

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

791

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

796

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

801

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

81

const struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

87

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

898

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

92

struct dc *dc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

100

bool (*enable_display_power_gating)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

104

void (*blank_pixel_data)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

107

void (*blank_pixel_data_sequence)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

114

struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

117

void (*setup_vupdate_interrupt)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

119

void (*setup_vupdate_interrupt_sequence)(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

121

bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

122

void (*init_blank)(struct dc *dc, struct timing_generator *tg);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

124

void (*bios_golden_init)(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

125

void (*plane_atomic_power_down)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

128

void (*plane_atomic_power_down_sequence)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

132

void (*plane_atomic_disable)(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

161

void (*update_odm)(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

163

void (*update_odm_sequence)(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

165

void (*program_all_writeback_pipes_in_tree)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

169

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

173

bool (*s0i3_golden_init_wa)(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

177

void (*verify_allow_pstate_change_high)(struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

178

void (*verify_allow_pstate_change_high_sequence)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

180

void (*program_pipe)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

184

struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

199

void (*enable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

201

void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

202

void (*program_mall_pipe_config_sequence)(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

204

void (*update_force_pstate)(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

205

void (*update_mall_sel)(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

209

void (*resync_fifo_dccg_dio)(struct dce_hwseq *hws, struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

215

struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

217

void (*reset_back_end_for_pipe)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

220

void (*populate_mcm_luts)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

225

void (*wait_for_pipe_update_if_needed)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool is_surface_update_only);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

226

void (*set_wait_for_update_needed_for_pipe)(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

227

void (*dc_ip_request_cntl)(struct dc *dc, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

228

void (*program_cm_hist)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

77

void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

78

void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

79

void (*init_pipes)(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

80

void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

81

void (*plane_atomic_disconnect)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

84

void (*plane_atomic_disconnect_sequence)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

88

void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

89

void (*update_mpcc_sequence)(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

91

bool (*set_input_transfer_func)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

94

bool (*set_output_transfer_func)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

97

void (*power_down)(struct dc *dc);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

101

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

104

struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

113

struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

125

struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

140

struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

164

struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

169

struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

182

struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

187

struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

193

struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

209

struct dc *dc, struct dc_state *state,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

213

struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

228

unsigned int (*get_max_hw_cursor_size)(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

89

struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

93

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

98

struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

36

struct dc;

drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h

37

struct dc;

drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h

623

struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h

628

struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h

634

struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h

637

struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h

640

struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h

644

void dcn_bw_sync_calcs_and_dml(struct dc *dc);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

432

void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

434

void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

567

struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

571

struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

77

dc->ctx->logger

drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h

104

struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h

108

bool link_enc_cfg_is_link_enc_avail(struct dc *dc, enum engine_id eng_id, struct dc_link *link);

drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h

111

bool link_enc_cfg_validate(struct dc *dc, struct dc_state *state);

drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h

118

void link_enc_cfg_set_transient_mode(struct dc *dc, struct dc_state *current_state, struct dc_state *new_state);

drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h

39

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h

58

struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h

78

struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h

83

struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h

88

struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h

93

struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h

97

struct link_encoder *link_enc_cfg_get_next_avail_link_enc(struct dc *dc);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

130

void (*get_cur_res_map)(const struct dc *dc, uint32_t *map);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

131

void (*restore_res_map)(const struct dc *dc, uint32_t *map);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

145

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/link_service.h

161

void (*blank_all_dp_displays)(struct dc *dc);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

162

void (*blank_all_edp_displays)(struct dc *dc);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

311

bool (*dp_pr_get_panel_inst)(const struct dc *dc, const struct dc_link *link, unsigned int *inst_out);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

323

void (*hdmi_frl_set_preferred_link_settings)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/link_service.h

338

void (*dp_set_preferred_link_settings)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/link_service.h

341

void (*dp_set_preferred_training_settings)(struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/link_service.h

84

const struct dc *dc;

drivers/gpu/drm/amd/display/dc/inc/resource.h

107

struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/resource.h

111

struct resource_pool *dc_create_resource_pool(struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/resource.h

115

void dc_destroy_resource_pool(struct dc *dc);

drivers/gpu/drm/amd/display/dc/inc/resource.h

118

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/resource.h

129

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/resource.h

489

void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state);

drivers/gpu/drm/amd/display/dc/inc/resource.h

587

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/resource.h

592

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/resource.h

617

void reset_syncd_pipes_from_disabled_pipes(struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/resource.h

620

void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/resource.h

624

void reset_sync_context_for_pipe(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/resource.h

628

uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter);

drivers/gpu/drm/amd/display/dc/inc/resource.h

636

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/resource.h

647

enum dc_status update_dp_encoder_resources_for_test_harness(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/inc/resource.h

660

void resource_init_common_dml2_callbacks(struct dc *dc, struct dml2_configuration_options *dml2_options);

drivers/gpu/drm/amd/display/dc/inc/soc_and_ip_translator.h

19

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

208

struct dc *dc = irq_service->ctx->dc;

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

210

dc_interrupt_to_irq_source(irq_service->ctx->dc,

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

220

tg = dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

104

if (needs_divider_update && link->dc->res_pool->funcs->update_dc_state_for_encoder_switch) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

105

link->dc->res_pool->funcs->update_dc_state_for_encoder_switch(link,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

112

link->dc->link_srv->dp_get_encoding_format(&pipes[i]->link_config.dp_link_settings),

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

129

if (link->dc->config.disable_hbr_audio_dp2 &&

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

131

link->dc->link_srv->dp_is_128b_132b_signal(pipes[i]))

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

139

if (was_hpo_acquired != is_hpo_acquired && link->dc->hwss.setup_hpo_hw_control)

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

140

link->dc->hwss.setup_hpo_hw_control(link->dc->hwseq, is_hpo_acquired);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

158

dc_update_planes_and_stream(dc, NULL, 0, streams_on_link[i], &stream_update);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

199

struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

324

test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

330

test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

471

resource_build_test_pattern_params(&link->dc->current_state->res_ctx,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

488

} else if (link->dc->hwss.set_disp_pattern_generator) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

504

link->dc->hwss.set_disp_pattern_generator(link->dc,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

528

} else if (link->dc->hwss.set_disp_pattern_generator) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

536

link->dc->hwss.set_disp_pattern_generator(link->dc,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

631

struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

667

link->dc->hwss.unblank_stream(

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

705

link->dc->hwss.blank_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

71

struct dc_state *state = link->dc->current_state;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

75

bool was_hpo_acquired = resource_is_hpo_acquired(link->dc->current_state);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

82

struct dc *dc = (struct dc *)link->dc;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

84

needs_divider_update = (link->dc->link_srv->dp_get_encoding_format(link_setting) !=

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

85

link->dc->link_srv->dp_get_encoding_format((const struct dc_link_settings *) &link->cur_link_settings))

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

856

if (should_use_dmub_inbox1_lock(pipe_ctx->stream->link->dc, pipe_ctx->stream->link)) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

890

link->dc->hwss.update_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

904

if (should_use_dmub_inbox1_lock(pipe_ctx->stream->link->dc, pipe_ctx->stream->link)) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

929

void dp_set_preferred_link_settings(struct dc *dc,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

949

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

96

link->dc,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

970

void dp_set_preferred_training_settings(struct dc *dc,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

990

dm_helpers_dp_mst_update_branch_bandwidth(dc->ctx, link);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

994

dp_set_preferred_link_settings(dc, &link->preferred_link_setting, link);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.h

36

void dp_set_preferred_link_settings(struct dc *dc,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.h

39

void dp_set_preferred_training_settings(struct dc *dc,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c

110

link->dp_trace.detect_lt_trace.timestamps.start = dm_get_timestamp(link->dc->ctx);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c

112

link->dp_trace.commit_lt_trace.timestamps.start = dm_get_timestamp(link->dc->ctx);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c

119

link->dp_trace.detect_lt_trace.timestamps.end = dm_get_timestamp(link->dc->ctx);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c

121

link->dp_trace.commit_lt_trace.timestamps.end = dm_get_timestamp(link->dc->ctx);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c

152

link->dp_trace.edp_trace_power_timestamps.poweroff = dm_get_timestamp(link->dc->ctx);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c

154

link->dp_trace.edp_trace_power_timestamps.poweron = dm_get_timestamp(link->dc->ctx);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c

169

if (link != NULL && link->dc->debug.enable_driver_sequence_debug)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

110

pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

153

link->dc->link_srv->dp_trace_source_sequence(link,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

165

if (!link->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

182

link->dc->link_srv->dp_trace_source_sequence(link,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

192

if (!link->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

200

link->dc->link_srv->dp_trace_source_sequence(link,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

210

if (!link->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

218

link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

228

if (!link->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

244

if (!link->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

280

pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

300

pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

335

if (!link->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

54

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

65

pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(pipe_ctx->stream->link,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

85

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

107

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

120

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

132

if (!link->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

139

link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

150

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

152

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

154

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

156

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

158

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

52

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

54

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

56

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

58

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

60

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

62

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

64

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

66

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

68

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

70

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

103

if (link->dc->config.enable_dpia_pre_training || link->dc->config.unify_link_enc_assignment) {

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

104

uint8_t fec_rdy = link->dc->link_srv->dp_should_enable_fec(link);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

121

link->dc->link_srv->dp_trace_source_sequence(link,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

132

if (!link->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

136

if (link->dc->config.enable_dpia_pre_training || link->dc->config.unify_link_enc_assignment) {

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

147

link->dc->link_srv->dp_trace_source_sequence(link,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

175

if (!link->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

176

return link->is_dig_mapping_flexible && link->dc->res_pool->funcs->link_encs_assign;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

44

if (!link->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

50

status = dc_process_dmub_set_mst_slots(link->dc, link->link_index,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

69

if (!link->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

76

link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

99

if (!link->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

103

link->dc->link_srv->dp_trace_source_sequence(link,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

120

if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

121

link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

122

link->dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

144

if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

145

link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

146

link->dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

157

link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

55

hpo_dp_stream_encoder->ctx->dc->link_srv->dp_link_bandwidth_kbps(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

101

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

103

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

105

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

109

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

112

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

116

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

119

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

140

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

170

link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

62

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

64

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

66

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

68

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

70

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

93

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

95

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

97

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

99

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c

34

struct dc *dc = stream->link->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c

35

struct dc_stream_state *temp_stream = &dc->scratch.temp_stream;

drivers/gpu/drm/amd/display/dc/link/link_detection.c

1007

if (link->dc->hwss.prepare_ddc)

drivers/gpu/drm/amd/display/dc/link/link_detection.c

1008

link->dc->hwss.prepare_ddc(link);

drivers/gpu/drm/amd/display/dc/link/link_detection.c

1037

if (!link->dc->hwss.dac_load_detect)

drivers/gpu/drm/amd/display/dc/link/link_detection.c

1040

return link->dc->hwss.dac_load_detect(link);

drivers/gpu/drm/amd/display/dc/link/link_detection.c

1057

struct audio_support *aud_support = &link->dc->res_pool->audio_support;

drivers/gpu/drm/amd/display/dc/link/link_detection.c

1061

struct dc *dc = dc_ctx->dc;

drivers/gpu/drm/amd/display/dc/link/link_detection.c

1073

(!link->dc->config.allow_edp_hotplug_detection)) &&

drivers/gpu/drm/amd/display/dc/link/link_detection.c

1144

if (dc->config.enable_mipi_converter_optimization &&

drivers/gpu/drm/amd/display/dc/link/link_detection.c

1149

dc->config.edp_no_power_sequencing = true;

drivers/gpu/drm/amd/display/dc/link/link_detection.c

1327

link->ctx->dc->debug.hdmi20_disable = true;

drivers/gpu/drm/amd/display/dc/link/link_detection.c

1335

if (dc_is_hdmi_signal(link->connector_signal) && dc->debug.enable_hdmi_idcc) {

drivers/gpu/drm/amd/display/dc/link/link_detection.c

1446

if (dc_ctx->dc->res_pool->funcs->get_panel_config_defaults)

drivers/gpu/drm/amd/display/dc/link/link_detection.c

1447

dc_ctx->dc->res_pool->funcs->get_panel_config_defaults(&link->panel_config);

drivers/gpu/drm/amd/display/dc/link/link_detection.c

1544

if (!link->dc->config.edp_no_power_sequencing)

drivers/gpu/drm/amd/display/dc/link/link_detection.c

1545

link->dc->hwss.edp_power_control(link, true);

drivers/gpu/drm/amd/display/dc/link/link_detection.c

1546

link->dc->hwss.edp_wait_for_hpd_ready(link, true);

drivers/gpu/drm/amd/display/dc/link/link_detection.c

1567

if (!link->dc->config.edp_no_power_sequencing)

drivers/gpu/drm/amd/display/dc/link/link_detection.c

1568

link->dc->hwss.edp_power_control(link, false);

drivers/gpu/drm/amd/display/dc/link/link_detection.c

204

aud_support = &link->dc->res_pool->audio_support;

drivers/gpu/drm/amd/display/dc/link/link_detection.c

308

.speed = ddc->ctx->dc->caps.i2c_speed_in_khz };

drivers/gpu/drm/amd/display/dc/link/link_detection.c

591

struct audio_support *audio_support = &link->dc->res_pool->audio_support;

drivers/gpu/drm/amd/display/dc/link/link_detection.c

607

if (link->dc->debug.disable_dp_plus_plus_wa &&

drivers/gpu/drm/amd/display/dc/link/link_detection.c

710

!link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)

drivers/gpu/drm/amd/display/dc/link/link_detection.c

718

!link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around) {

drivers/gpu/drm/amd/display/dc/link/link_detection.c

758

static bool should_prepare_phy_clocks_for_link_verification(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/link/link_detection.c

764

for (i = 0; i < dc->current_state->stream_count; i++) {

drivers/gpu/drm/amd/display/dc/link/link_detection.c

765

if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {

drivers/gpu/drm/amd/display/dc/link/link_detection.c

783

for (i = 0; i < link->dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/link/link_detection.c

784

if (link->dc->links[i] != NULL &&

drivers/gpu/drm/amd/display/dc/link/link_detection.c

785

dc_is_hdmi_signal(link->dc->links[i]->connector_signal))

drivers/gpu/drm/amd/display/dc/link/link_detection.c

793

for (i = 0; i < link->dc->current_state->stream_count; i++) {

drivers/gpu/drm/amd/display/dc/link/link_detection.c

794

if (dc_is_hdmi_signal(link->dc->current_state->streams[i]->signal))

drivers/gpu/drm/amd/display/dc/link/link_detection.c

796

if (link == link->dc->current_state->streams[i]->link &&

drivers/gpu/drm/amd/display/dc/link/link_detection.c

797

(dc_is_hdmi_frl_signal(link->dc->current_state->streams[i]->signal)))

drivers/gpu/drm/amd/display/dc/link/link_detection.c

802

for (i = 0; i < link->dc->current_state->stream_count; i++) {

drivers/gpu/drm/amd/display/dc/link/link_detection.c

804

link->dc->current_state->streams[i]->signal)) {

drivers/gpu/drm/amd/display/dc/link/link_detection.c

813

for (i = 0; i < link->dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/link/link_detection.c

814

if (link->dc->links[i] != NULL &&

drivers/gpu/drm/amd/display/dc/link/link_detection.c

815

link->dc->links[i]->local_sink != NULL &&

drivers/gpu/drm/amd/display/dc/link/link_detection.c

816

link != link->dc->links[i] &&

drivers/gpu/drm/amd/display/dc/link/link_detection.c

818

link->dc->links[i]->local_sink->sink_signal)) {

drivers/gpu/drm/amd/display/dc/link/link_detection.c

828

static void prepare_phy_clocks_for_destructive_link_verification(const struct dc *dc)

drivers/gpu/drm/amd/display/dc/link/link_detection.c

830

dc_z10_restore(dc);

drivers/gpu/drm/amd/display/dc/link/link_detection.c

831

clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/link/link_detection.c

834

static void restore_phy_clocks_for_destructive_link_verification(const struct dc *dc)

drivers/gpu/drm/amd/display/dc/link/link_detection.c

836

clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/link/link_detection.c

843

should_prepare_phy_clocks_for_link_verification(link->dc, reason);

drivers/gpu/drm/amd/display/dc/link/link_detection.c

846

prepare_phy_clocks_for_destructive_link_verification(link->dc);

drivers/gpu/drm/amd/display/dc/link/link_detection.c

870

restore_phy_clocks_for_destructive_link_verification(link->dc);

drivers/gpu/drm/amd/display/dc/link/link_detection.c

902

if (!link->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/link_detection.c

904

link->dc->res_pool->funcs->link_encs_assign &&

drivers/gpu/drm/amd/display/dc/link/link_detection.c

906

link->ctx->dc,

drivers/gpu/drm/amd/display/dc/link/link_detection.c

914

if (link->dc->debug.skip_detection_link_training ||

drivers/gpu/drm/amd/display/dc/link/link_detection.c

917

!link->dc->config.enable_dpia_pre_training)) {

drivers/gpu/drm/amd/display/dc/link/link_detection.c

931

link->dc->current_state->res_ctx.pipe_ctx;

drivers/gpu/drm/amd/display/dc/link/link_detection.c

936

} else if (link->dc->config.skip_frl_pretraining) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

101

link_blank_dp_stream(dc->links[i], true);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

106

void link_blank_all_edp_displays(struct dc *dc)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

112

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

113

if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) ||

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

114

(!dc->links[i]->edp_sink_present))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

118

status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

122

link_blank_dp_stream(dc->links[i], true);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

129

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

140

for (j = 0; j < dc->res_pool->stream_enc_count; j++) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

141

if (fe == dc->res_pool->stream_enc[j]->id) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

142

dc->res_pool->stream_enc[j]->funcs->dp_blank(link,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

143

dc->res_pool->stream_enc[j]);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

149

if (((!dc->is_switch_in_progress_dest) && ((!link->wa_flags.dp_keep_receiver_powered) || hw_init)) &&

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

159

struct dc_state *state = link->dc->current_state;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

181

dc_commit_updates_for_stream(link->ctx->dc, NULL, 0,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1814

link->dc->hwss.edp_power_control(link, false);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1835

link->dc->hwss.disable_link_output(link, link_res, SIGNAL_TYPE_DISPLAY_PORT);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1837

link->dc->hwss.disable_link_output(link, link_res, signal);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1859

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1895

if (dc->debug.enable_hdmi_idcc) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1915

dc->hwss.enable_tmds_link_output(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1932

struct dc *core_dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2065

!link->dc->config.enable_dpia_pre_training)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2074

link->dc->debug.set_mst_en_for_sst) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2084

if (!link->dc->config.edp_no_power_sequencing)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2085

link->dc->hwss.edp_power_control(link, true);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2086

link->dc->hwss.edp_wait_for_hpd_ready(link, true);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2164

struct dc *dc = stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2171

dc->hwss.enable_lvds_link_output(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2212

link->dc->hwss.enable_analog_link_output(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2222

link->dc->hwss.enable_dp_link_output(link,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2366

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2399

dc->hwss.disable_audio_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2402

dc->hwss.blank_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2447

dc->hwss.disable_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2449

dc->hwss.disable_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2469

if (link->connector_signal == SIGNAL_TYPE_EDP && dc->debug.psp_disabled_wa) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2481

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2515

if (!dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2552

dc->hwss.update_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2564

dc->hwss.enable_audio_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2665

dc->hwss.enable_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2697

dc->hwss.unblank_stream(pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2707

dc->hwss.enable_audio_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

349

.speed = link->ctx->dc->caps.i2c_speed_in_khz,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

541

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

585

pipe_ctx->stream->link->dc, link_enc->transmitter);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

640

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

648

dc->hwss.set_avmute(pipe_ctx, enable);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

688

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

695

result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

701

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

708

result = dm_helpers_dp_write_hblank_reduction(dc->ctx, stream);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

722

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

726

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

798

if (dc->debug.enable_hblank_borrow) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

83

void link_blank_all_dp_displays(struct dc *dc)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

89

for (i = 0; i < dc->link_count; i++) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

90

if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) ||

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

91

(dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

95

dp_retrieve_lttpr_cap(dc->links[i]);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

97

status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

35

void link_blank_all_dp_displays(struct dc *dc);

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

36

void link_blank_all_edp_displays(struct dc *dc);

drivers/gpu/drm/amd/display/dc/link/link_factory.c

422

link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL;

drivers/gpu/drm/amd/display/dc/link/link_factory.c

423

link->dc->res_pool->dig_link_enc_count--;

drivers/gpu/drm/amd/display/dc/link/link_factory.c

444

if (link->ctx->dc->config.dp_connector_no_native_i2c && link->no_ddc_pin) {

drivers/gpu/drm/amd/display/dc/link/link_factory.c

524

struct dc_bios *bios = init_params->dc->ctx->dc_bios;

drivers/gpu/drm/amd/display/dc/link/link_factory.c

538

link->dc = init_params->dc;

drivers/gpu/drm/amd/display/dc/link/link_factory.c

588

if (link->dc->res_pool->funcs->link_init)

drivers/gpu/drm/amd/display/dc/link/link_factory.c

589

link->dc->res_pool->funcs->link_init(link);

drivers/gpu/drm/amd/display/dc/link/link_factory.c

601

if (link->ctx->dc->config.dp_connector_no_native_i2c && link->no_ddc_pin) {

drivers/gpu/drm/amd/display/dc/link/link_factory.c

650

link->dc->res_pool->funcs->link_enc_create(dc_ctx, &enc_init_data);

drivers/gpu/drm/amd/display/dc/link/link_factory.c

697

if (!(!link->dc->config.smart_mux_version || dc_ctx->dc_edp_id_count == 0))

drivers/gpu/drm/amd/display/dc/link/link_factory.c

701

if (!link->dc->config.allow_edp_hotplug_detection

drivers/gpu/drm/amd/display/dc/link/link_factory.c

705

switch (link->dc->config.allow_edp_hotplug_detection) {

drivers/gpu/drm/amd/display/dc/link/link_factory.c

765

link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc;

drivers/gpu/drm/amd/display/dc/link/link_factory.c

766

link->dc->res_pool->dig_link_enc_count++;

drivers/gpu/drm/amd/display/dc/link/link_factory.c

770

if (link->dc->res_pool->funcs->panel_cntl_create &&

drivers/gpu/drm/amd/display/dc/link/link_factory.c

777

link->dc->res_pool->funcs->panel_cntl_create(

drivers/gpu/drm/amd/display/dc/link/link_factory.c

866

(link->dc->res_pool->funcs->hpo_frl_link_enc_create)) {

drivers/gpu/drm/amd/display/dc/link/link_factory.c

870

link->hpo_frl_link_enc = link->dc->res_pool->funcs->hpo_frl_link_enc_create(

drivers/gpu/drm/amd/display/dc/link/link_factory.c

915

link->dc = init_params->dc;

drivers/gpu/drm/amd/display/dc/link/link_factory.c

955

if (link->dc->res_pool->funcs->get_preferred_eng_id_dpia)

drivers/gpu/drm/amd/display/dc/link/link_factory.c

956

link->dpia_preferred_eng_id = link->dc->res_pool->funcs->get_preferred_eng_id_dpia(link->ddc_hw_inst);

drivers/gpu/drm/amd/display/dc/link/link_resource.c

100

for (i = 0; i < dc->caps.max_links; i++) {

drivers/gpu/drm/amd/display/dc/link/link_resource.c

102

link = dc->links[i];

drivers/gpu/drm/amd/display/dc/link/link_resource.c

41

pipe = &link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/link/link_resource.c

52

void link_get_cur_res_map(const struct dc *dc, uint32_t *map)

drivers/gpu/drm/amd/display/dc/link/link_resource.c

60

if (dc->caps.dp_hpo) {

drivers/gpu/drm/amd/display/dc/link/link_resource.c

61

for (i = 0; i < dc->caps.max_links; i++) {

drivers/gpu/drm/amd/display/dc/link/link_resource.c

62

link = dc->links[i];

drivers/gpu/drm/amd/display/dc/link/link_resource.c

75

void link_restore_res_map(const struct dc *dc, uint32_t *map)

drivers/gpu/drm/amd/display/dc/link/link_resource.c

83

if (dc->caps.dp_hpo) {

drivers/gpu/drm/amd/display/dc/link/link_resource.c

84

available_hpo_dp_count = dc->res_pool->hpo_dp_link_enc_count;

drivers/gpu/drm/amd/display/dc/link/link_resource.c

86

for (i = 0; i < dc->caps.max_links; i++) {

drivers/gpu/drm/amd/display/dc/link/link_resource.c

88

link = dc->links[i];

drivers/gpu/drm/amd/display/dc/link/link_resource.h

28

void link_get_cur_res_map(const struct dc *dc, uint32_t *map);

drivers/gpu/drm/amd/display/dc/link/link_resource.h

29

void link_restore_res_map(const struct dc *dc, uint32_t *map);

drivers/gpu/drm/amd/display/dc/link/link_validation.c

554

for (i = 0; i < link->dc->res_pool->hpo_frl_stream_enc_count; i++) {

drivers/gpu/drm/amd/display/dc/link/link_validation.c

555

if (link->dc->res_pool->hpo_frl_stream_enc[i]->id == hpo_eng_id) {

drivers/gpu/drm/amd/display/dc/link/link_validation.c

571

link->dc->res_pool->hpo_frl_stream_enc[hpo_frl_stream_enc_index]->funcs->validate_hdmi_frl_output(

drivers/gpu/drm/amd/display/dc/link/link_validation.c

572

link->dc->res_pool->hpo_frl_stream_enc[hpo_frl_stream_enc_index],

drivers/gpu/drm/amd/display/dc/link/link_validation.c

622

if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 && link->dc->config.no_native422_support) {

drivers/gpu/drm/amd/display/dc/link/link_validation.c

692

enum dc_status link_validate_dp_tunnel_bandwidth(const struct dc *dc, const struct dc_state *new_ctx)

drivers/gpu/drm/amd/display/dc/link/link_validation.c

694

(void)dc;

drivers/gpu/drm/amd/display/dc/link/link_validation.h

36

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

123

if (ddc_service->link && ddc_service->ctx->dc->config.dp_connector_no_native_i2c &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

387

command.speed = ddc->ctx->dc->caps.i2c_speed_in_khz;

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

511

!ddc->link->dc->debug.disable_fixed_vs_aux_timeout_wa &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

529

if (ddc->ctx->dc->config.dp_connector_no_native_i2c && ddc->link->no_ddc_pin) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

530

if (ddc->ctx->dc->res_pool->engines[ddc->link->aux_hw_inst]->funcs->configure_timeout) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

531

ddc->ctx->dc->res_pool->engines[ddc->link->aux_hw_inst]->funcs->configure_timeout(ddc, timeout);

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

535

if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

536

ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1250

if (link->dc->caps.dp_hdmi21_pcon_support) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1413

if (!link->dc->vendor_signature.is_valid) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1464

link->dc->caps.min_horizontal_blanking_period != 0) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1466

uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1479

link->dc->caps.min_horizontal_blanking_period,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1489

link->dc->vendor_signature.data.raw,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1490

sizeof(link->dc->vendor_signature.data.raw));

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1521

link->dc, link->link_enc->transmitter);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1522

if (dc_wake_and_execute_dmub_cmd(link->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1645

bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1647

if (!vbios_lttpr_interop || !link->dc->caps.extended_aux_timeout_support)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2064

link->dc->debug.dpia_debug.bits.enable_force_tbt3_work_around &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2297

struct resource_context *res_ctx = &link->dc->current_state->res_ctx;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2298

struct resource_pool *res_pool = link->dc->res_pool;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2306

if (!link->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2336

struct resource_context *res_ctx = &link->dc->current_state->res_ctx;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2337

struct resource_pool *res_pool = link->dc->res_pool;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2341

if (!link->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2381

if (!link->dc->debug.ignore_cable_id &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2423

link->dc->debug.disable_uhbr)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2514

link->dc->debug.usbc_combo_phy_reset_wa)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2578

if (link->ctx->dc->config.dp_connector_no_native_i2c && link->no_ddc_pin)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

285

struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

343

struct resource_context *res_ctx = &link->dc->current_state->res_ctx;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

344

struct resource_pool *res_pool = link->dc->res_pool;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

347

if (!link->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

360

if (link->dc->debug.disable_fec)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

372

|| !link->dc->caps.edp_dsc_support))

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

531

if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->debug.support_eDP1_5)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

675

link->dc->debug.force_dp2_lt_fallback_method)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

245

if (link->dc->debug.dpia_debug.bits.enable_usb4_bw_zero_alloc_patch) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

315

if (link->ctx->dc->debug.enable_replay_esd_recovery) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

329

struct dc_state *state = link->dc->current_state;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

348

link_set_dpms_on(link->dc->current_state, pipes[i]);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

516

!link->dc->config.enable_dpia_pre_training)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

111

dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

114

replay = dc->res_pool->replay;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

119

if (!dp_pr_get_panel_inst(dc, link, &panel_inst))

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

127

if (dc->current_state->res_ctx.pipe_ctx[i].stream

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

133

dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst + 1;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

204

bool dp_pr_get_panel_inst(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

208

if (!dc || !link || !inst_out)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

211

if (dc->config.frame_update_cmd_version2 == false)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

212

return dc_get_edp_link_panel_inst(dc, link, inst_out);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

218

if (dc->current_state->res_ctx.pipe_ctx[i].stream &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

219

dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

221

if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

222

*inst_out = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

247

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

251

if (!dp_pr_get_panel_inst(dc, link, &panel_inst))

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

268

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

277

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

282

if (!dp_pr_get_panel_inst(dc, link, &panel_inst))

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

286

if (dc->current_state->res_ctx.pipe_ctx[i].stream &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

287

dc->current_state->res_ctx.pipe_ctx[i].stream->link &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

288

dc->current_state->res_ctx.pipe_ctx[i].stream->link == link &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

289

dc_is_dp_sst_signal(dc->current_state->res_ctx.pipe_ctx[i].stream->link->connector_signal)) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

290

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

327

cmd.pr_copy_settings.data.auxless_alpm_data.lfps_setup_ns = (uint16_t)dc->debug.auxless_alpm_lfps_setup_ns;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

328

cmd.pr_copy_settings.data.auxless_alpm_data.lfps_period_ns = (uint16_t)dc->debug.auxless_alpm_lfps_period_ns;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

329

cmd.pr_copy_settings.data.auxless_alpm_data.lfps_silence_ns = (uint16_t)dc->debug.auxless_alpm_lfps_silence_ns;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

331

(uint16_t)dc->debug.auxless_alpm_lfps_t1t2_us;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

333

(uint16_t)dc->debug.auxless_alpm_lfps_t1t2_offset_us;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

334

cmd.pr_copy_settings.data.auxless_alpm_data.lttpr_count = link->dc->link_srv->dp_get_lttpr_count(link);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

354

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

360

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

364

if (!dp_pr_get_panel_inst(dc, link, &panel_inst))

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

375

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

381

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

385

if (!dp_pr_get_panel_inst(dc, link, &panel_inst))

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

396

dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

402

const struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

407

if (!dp_pr_get_panel_inst(dc, link, &panel_inst))

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

412

if (!dc_wake_and_execute_gpint(dc->ctx, DMUB_GPINT__GET_REPLAY_STATE, (uint16_t)panel_inst,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

54

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

60

if (dc->current_state->res_ctx.pipe_ctx[i].stream &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

61

dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

62

struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

72

dc_stream_set_static_screen_params(dc, &stream, 1, &params);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

81

struct dc *dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.h

31

bool dp_pr_get_panel_inst(const struct dc *dc, const struct dc_link *link, unsigned int *inst_out);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c

149

if (!link->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c

184

if (!link->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c

66

link->dc->hwss.enable_dp_link_output(link, link_res, signal,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c

75

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c

82

dc->hwss.disable_link_output(link, link_res, signal);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c

87

if (dc->clk_mgr->funcs->notify_link_rate_change)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c

88

dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1616

link->ctx->dc->debug_data.ltFailCount++;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1682

if (!link->dc->config.consolidated_dpia_dp_lt && link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1736

!link->dc->config.enable_dpia_pre_training) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

710

if (link->dc->debug.lttpr_mode_override == LTTPR_MODE_TRANSPARENT) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

712

} else if (link->dc->debug.lttpr_mode_override == LTTPR_MODE_NON_TRANSPARENT) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

714

} else if (link->dc->debug.lttpr_mode_override == LTTPR_MODE_NON_LTTPR) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

785

if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->dc->debug.dpia_debug.bits.force_non_lttpr)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

814

if (!link->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

926

const struct dc *dc = link->dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

928

enum dp_link_encoding encoding = dc->link_srv->dp_get_encoding_format(&lt_settings->link_settings);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

204

if (link->dc->debug.legacy_dp2_lt) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

158

bool vbios_lttpr_force_non_transparent = link->dc->caps.vbios_lttpr_enable;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

159

bool vbios_lttpr_aware = link->dc->caps.vbios_lttpr_aware;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

174

if (link->dc->config.allow_lttpr_non_transparent_mode.bits.DP1_4A &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

175

link->dc->caps.extended_aux_timeout_support) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

242

if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

434

if (link->ctx->dc->work_arounds.lt_early_cr_pattern)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

930

if (link->dc->debug.dpia_debug.bits.extend_aux_rd_interval)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

972

if (!link->dc->config.consolidated_dpia_dp_lt)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

990

dc_process_dmub_dpia_set_tps_notification(link->ctx->dc, link->link_index, pattern);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

125

if (link->ctx->dc->work_arounds.lt_early_cr_pattern)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

229

pre_disable_intercept_delay_ms = link->dc->debug.fixed_vs_aux_delay_config_wa;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

233

pre_disable_intercept_delay_ms = link->dc->debug.fixed_vs_aux_delay_config_wa * 2;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1017

dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1019

replay = dc->res_pool->replay;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1024

if (!dp_pr_get_panel_inst(dc, link, &panel_inst))

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1032

if (dc->current_state->res_ctx.pipe_ctx[i].stream

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1038

dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst + 1;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1095

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1096

struct dmub_replay *replay = dc->res_pool->replay;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1102

if (dp_pr_get_panel_inst(dc, link, &panel_inst))

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1116

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1117

struct dmub_replay *replay = dc->res_pool->replay;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1123

if (!dp_pr_get_panel_inst(dc, link, &panel_inst))

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1139

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1140

struct dmub_replay *replay = dc->res_pool->replay;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1143

if (!dp_pr_get_panel_inst(dc, link, &panel_inst))

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1160

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1161

struct dmub_replay *replay = dc->res_pool->replay;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1164

if (!dp_pr_get_panel_inst(dc, link, &panel_inst))

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1191

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1195

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1210

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1211

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1237

if (link->dc->caps.is_apu)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1239

if (!link->dc->config.smart_mux_version)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1245

static void edp_set_assr_enable(const struct dc *pDC, struct dc_link *link,

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1291

if (link->dc->config.use_assr_psp_message) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1292

edp_set_assr_enable(link->dc, link, link_res, enable);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

165

!link->dc->caps.dmub_caps.aux_backlight_support) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

399

link->dc->hwss.edp_power_control(link, true);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

401

link->dc->hwss.edp_wait_for_hpd_ready(link, true);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

402

if (link->dc->hwss.edp_backlight_control)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

403

link->dc->hwss.edp_backlight_control(link, true);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

410

if (!link->dc->config.edp_no_power_sequencing)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

411

link->dc->hwss.edp_power_control(link, true);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

412

link->dc->hwss.edp_wait_for_hpd_ready(link, true);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

415

if (link->dc->hwss.edp_backlight_control)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

416

link->dc->hwss.edp_backlight_control(link, true);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

425

if (link->dc->hwss.edp_backlight_control)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

426

link->dc->hwss.edp_backlight_control(link, false);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

429

if (!link->dc->config.edp_no_power_sequencing)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

430

link->dc->hwss.edp_power_control(link, false);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

436

if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

437

link->dc->hwss.edp_wait_for_T12(link);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

530

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

534

if (dc->current_state->res_ctx.pipe_ctx[i].stream) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

535

if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

536

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

548

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

573

dc->hwss.set_backlight_level(

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

583

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

584

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

585

struct dmub_psr *psr = dc->res_pool->psr;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

591

if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

616

dc_z10_restore(dc);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

631

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

632

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

633

struct dmub_psr *psr = dc->res_pool->psr;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

636

if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

688

struct dc *dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

728

dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

729

dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

730

psr = dc->res_pool->psr;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

735

if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

791

if (dc->config.dp_connector_no_native_i2c && link->no_ddc_pin)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

799

if (dc->current_state->res_ctx.pipe_ctx[i].stream

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

805

dc->current_state->res_ctx.

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

833

link->dc->res_pool->timing_generator_count;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

854

if (dc->debug.disable_z10 || dc->debug.psr_skip_crtc_disable)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

910

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

911

struct dmub_psr *psr = dc->res_pool->psr;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

914

if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

925

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

926

struct dmub_psr *psr = dc->res_pool->psr;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

939

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

940

struct dmub_replay *replay = dc->res_pool->replay;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

946

if (!dp_pr_get_panel_inst(dc, link, &panel_inst))

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

972

struct dc *dc = link->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

973

struct dmub_replay *replay = dc->res_pool->replay;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

977

if (!dp_pr_get_panel_inst(dc, link, &panel_inst))

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

991

struct dc *dc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

1016

if (dc->res_pool->dccg->funcs->set_hdmistreamclk) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

1017

dc->res_pool->dccg->funcs->set_hdmistreamclk(

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

1018

dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

1027

link_stream->ctx->dc->hwss.update_info_frame(pipe);

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

1032

link_stream->ctx->dc->hwss.enable_audio_stream(pipe);

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

1033

link_stream->ctx->dc->hwss.enable_stream(pipe);

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

1034

link_stream->ctx->dc->hwss.unblank_stream(pipe,

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

148

if (link->dc->debug.max_frl_rate != 0 && encoder_link_rate > link->dc->debug.max_frl_rate)

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

149

encoder_link_rate = link->dc->debug.max_frl_rate;

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

273

if (link->dc->debug.limit_ffe == 0)

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

434

uint8_t FFE_Levels = (uint8_t)ddc_service->link->dc->debug.limit_ffe;

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

609

if (ddc_service->link->dc->debug.limit_ffe == 0) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

635

if (ddc_service->link->dc->debug.limit_ffe == 0) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

744

link->ctx->dc->hwss.setup_hdmi_frl_link(link, 0,

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

750

link->dc->hwss.disable_link_output(link, link_res, SIGNAL_TYPE_HDMI_FRL);

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

781

link->ctx->dc->debug.force_frl_rate;

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

784

link->ctx->dc->debug.force_frl_always;

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

787

link->ctx->dc->debug.force_frl_max ? true :

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

790

link->ctx->dc->debug.force_frl_dsc ? true :

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

793

link->ctx->dc->debug.apply_vsdb_rcc_wa;

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

834

link->dc->hwss.disable_link_output(link, &link_res, link->connector_signal);

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

835

link->dc->res_pool->clock_sources[t_id]->funcs->cs_power_down(

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

836

link->dc->res_pool->clock_sources[t_id]);

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

849

if (link->dc->ctx->dce_version <= DCN_VERSION_3_0)

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

850

link->dc->hwss.disable_link_output(link, &link_res, SIGNAL_TYPE_HDMI_FRL);

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

852

link->dc->hwss.disable_link_output(link, &link_res, link->connector_signal);

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

854

link->dc->res_pool->clock_sources[t_id]->funcs->cs_power_down(

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

855

link->dc->res_pool->clock_sources[t_id]);

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

874

stream = link->dc->current_state->streams[i];

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

882

link->dc->hwss.disable_link_output(link, &link_res, link_stream->signal);

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

886

void hdmi_frl_set_preferred_link_settings(struct dc *dc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

899

struct dc_stream_state *temp_stream = &dc->scratch.temp_stream;

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

904

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

957

(!link_stream->ctx->dc->res_pool->dccg->funcs->enable_hdmicharclk) ||

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

999

dc->hwss.setup_hdmi_frl_link(link,

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.h

47

void hdmi_frl_set_preferred_link_settings(struct dc *dc,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

410

if (mpc->ctx->dc->debug.cm_in_bypass) {

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

415

if (mpc->ctx->dc->work_arounds.dedcn20_305_wa == false) {

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

437

if (mpc->ctx->dc->debug.cm_in_bypass) {

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1297

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1458

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

349

if (mpc->ctx->dc->debug.cm_in_bypass) {

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

384

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

833

if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

844

if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

877

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

272

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm)

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

52

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

695

if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

76

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm) {

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

80

} else if (!mpc->ctx->dc->debug.disable_mem_low_power) {

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

987

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

156

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

227

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

178

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

230

if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

630

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

82

if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

165

oppn10->base.ctx->dc->debug.force_chroma_subsampling_1tap;

drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

373

!opp->ctx->dc->debug.force_chroma_subsampling_1tap &&

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

353

struct dc *dc = optc->ctx->dc;

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

355

if (dc->caps.dmub_caps.mclk_sw && !dc->debug.disable_fams)

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

356

dc_dmub_srv_drr_update_cmd(dc, optc->inst, vtotal_min, vtotal_max);

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

254

struct dc *dc = optc->ctx->dc;

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

256

if (dc->caps.dmub_caps.mclk_sw && !dc->debug.disable_fams)

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

257

dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

312

if (optc1->base.ctx->dc->debug.otg_crc_db && optc1->tg_mask->OTG_CRC_WINDOW_DB_EN != 0)

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

345

if (optc1->base.ctx->dc->debug.otg_crc_db && optc1->tg_mask->OTG_CRC_WINDOW_DB_EN != 0)

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

373

struct dc *dc = optc->ctx->dc;

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

375

if (dc->caps.dmub_caps.mclk_sw && !dc->debug.disable_fams)

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

376

dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

626

optc1, CTX->dc->debug.enable_fine_grain_clock_gating.bits.optc);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

294

struct dc *dc = optc->ctx->dc;

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

296

if (dc->caps.dmub_caps.fams_ver == 1 && !dc->debug.disable_fams)

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

298

dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

319

struct dc *dc = optc->ctx->dc;

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

323

if (dc->caps.dmub_caps.fams_ver == dc->debug.fams_version.ver && dc->debug.fams2_config.bits.enable) {

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

336

dc_dmub_srv_fams2_drr_update(dc, optc->inst,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

388

struct dc *dc = optc->ctx->dc;

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

390

if (dc->caps.dmub_caps.fams_ver == dc->debug.fams_version.ver && dc->debug.fams2_config.bits.enable) {

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

392

dc_dmub_srv_fams2_drr_update(dc, optc->inst,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

398

} else if (dc->caps.dmub_caps.fams_ver == 1 && !dc->debug.disable_fams) {

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

400

dc_dmub_srv_drr_update_cmd(dc, optc->inst, vtotal_min, vtotal_max);

drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c

288

optc1, CTX->dc->debug.enable_fine_grain_clock_gating.bits.optc);

drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c

98

if (optc1->base.ctx->dc->debug.enable_otg_frame_sync_pwa) {

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

182

bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg ||

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

183

pg_cntl->ctx->dc->debug.disable_hubp_power_gate ||

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

184

pg_cntl->ctx->dc->debug.disable_dpp_power_gate ||

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

185

pg_cntl->ctx->dc->idle_optimizations_allowed;

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

258

if (pg_cntl->ctx->dc->debug.ignore_pg ||

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

259

pg_cntl->ctx->dc->debug.disable_hpo_power_gate ||

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

260

pg_cntl->ctx->dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

306

if (pg_cntl->ctx->dc->debug.ignore_pg ||

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

307

pg_cntl->ctx->dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

350

if (pg_cntl->ctx->dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

360

if (pg_cntl->ctx->dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

370

if (pg_cntl->ctx->dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

388

if (pg_cntl->ctx->dc->debug.ignore_pg ||

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

389

pg_cntl->ctx->dc->debug.disable_optc_power_gate ||

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

390

pg_cntl->ctx->dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

402

for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

403

struct pipe_ctx *pipe_ctx = &pg_cntl->ctx->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

434

for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

444

if (pg_cntl->ctx->dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

477

for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

487

for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

516

for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

52

if (pg_cntl->ctx->dc->debug.ignore_pg)

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

83

bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg ||

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

84

pg_cntl->ctx->dc->debug.disable_dsc_power_gate ||

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

85

pg_cntl->ctx->dc->idle_optimizations_allowed;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

127

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

128

pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

134

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) {

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

136

pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc(

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

137

pg_cntl->ctx->dc->res_pool->dccg, dsc_inst);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

178

bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

179

pg_cntl->ctx->dc->debug.disable_hubp_power_gate ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

180

pg_cntl->ctx->dc->debug.disable_dpp_power_gate ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

181

pg_cntl->ctx->dc->idle_optimizations_allowed;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

200

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

201

pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, false);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

231

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

232

pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

263

bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

264

pg_cntl->ctx->dc->debug.disable_hpo_power_gate ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

265

pg_cntl->ctx->dc->idle_optimizations_allowed;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

286

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

287

pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, false);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

293

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

294

pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

319

bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

320

pg_cntl->ctx->dc->idle_optimizations_allowed ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

321

pg_cntl->ctx->dc->debug.disable_io_clk_power_gate;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

370

if (pg_cntl->ctx->dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

380

if (pg_cntl->ctx->dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

391

if (pg_cntl->ctx->dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

417

bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

418

pg_cntl->ctx->dc->idle_optimizations_allowed ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

419

pg_cntl->ctx->dc->debug.disable_mem_power_gate;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

471

bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

472

pg_cntl->ctx->dc->idle_optimizations_allowed ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

473

pg_cntl->ctx->dc->debug.disable_dio_power_gate;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

490

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

491

pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, false);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

498

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

499

pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

516

if (pg_cntl->ctx->dc->debug.ignore_pg ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

517

pg_cntl->ctx->dc->debug.disable_optc_power_gate ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

518

pg_cntl->ctx->dc->idle_optimizations_allowed)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

530

for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

531

struct pipe_ctx *pipe_ctx = &pg_cntl->ctx->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

562

for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

589

for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

599

for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

60

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc && power_on)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

61

pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc(

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

62

pg_cntl->ctx->dc->res_pool->dccg, dsc_inst);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

64

bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

65

pg_cntl->ctx->dc->debug.disable_dsc_power_gate ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

66

pg_cntl->ctx->dc->idle_optimizations_allowed;

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

85

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

86

pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, false);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1041

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1045

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1115

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1127

dc->caps.max_downscale_ratio = 200;

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1128

dc->caps.i2c_speed_in_khz = 40;

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1129

dc->caps.i2c_speed_in_khz_hdcp = 40;

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1130

dc->caps.max_cursor_size = 128;

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1131

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1132

dc->caps.dual_link_dvi = true;

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1133

dc->caps.disable_dp_clk_share = true;

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1134

dc->caps.extended_aux_timeout_support = false;

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1135

dc->debug = debug_defaults;

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1136

dc->check_config = config_defaults;

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1201

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1203

for (i = 0; i < dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1204

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1206

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1211

dce100_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1222

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1230

if (dce100_resource_construct(num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

714

ctx->dc->caps.extended_aux_timeout_support);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

849

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

853

(void)dc;

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

867

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

875

const uint32_t max_pix_clk_khz = max(dc->clk_mgr->clks.max_supported_dispclk_khz, 400000);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

877

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

896

if (dc->ctx->dce_version == DCE_VERSION_6_0 ||

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

897

dc->ctx->dce_version == DCE_VERSION_6_4)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

929

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

932

(void)dc;

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

940

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

946

result = resource_map_pool_resources(dc, new_ctx, dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

949

result = resource_map_clock_resources(dc, new_ctx, dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

952

result = build_mapped_resource(dc, new_ctx, dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h

34

struct dc;

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h

40

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h

45

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h

49

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h

54

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1102

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1105

(void)dc;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1113

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1119

result = resource_map_pool_resources(dc, new_ctx, dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1122

result = resource_map_clock_resources(dc, new_ctx, dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1126

result = build_mapped_resource(dc, new_ctx, dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1139

struct dc *dc = stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1140

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1157

if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) {

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1159

struct dc_bios *dcb = dc->ctx->dc_bios;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1162

dc,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1192

color_space_to_black_color(dc,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1284

ctx->dc->caps.max_slave_planes = 1;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1285

ctx->dc->caps.max_slave_yuv_planes = 1;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1286

ctx->dc->caps.max_slave_rgb_planes = 0;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1291

static void bw_calcs_data_update_from_pplib(struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1297

dc->ctx,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1301

dc->bw_vbios->high_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1303

dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1305

dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1307

dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1309

dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1311

dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1313

dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1315

dc->bw_vbios->low_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1317

dc->sclk_lvls = clks;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1321

dc->ctx,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1324

dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1326

dc->bw_vbios->mid_voltage_max_dispclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1328

dc->bw_vbios->low_voltage_max_dispclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1333

dc->ctx,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1337

dc->bw_vbios->low_yclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1339

dc->bw_vbios->mid_yclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1342

dc->bw_vbios->high_yclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1358

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1364

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1379

dc->caps.max_downscale_ratio = 150;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1380

dc->caps.i2c_speed_in_khz = 40;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1381

dc->caps.i2c_speed_in_khz_hdcp = 40;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1382

dc->caps.max_cursor_size = 128;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1383

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1384

dc->caps.is_apu = true;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1385

dc->caps.extended_aux_timeout_support = false;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1386

dc->debug = debug_defaults;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1387

dc->check_config = config_defaults;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1447

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1513

if (dc->config.fbc_support)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1514

dc->fbc_compressor = dce110_compressor_create(ctx);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1519

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1524

dce110_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1526

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1529

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1531

dc->caps.planes[pool->base.underlay_pipe_index] = underlay_plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1533

bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1535

bw_calcs_data_update_from_pplib(dc);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1546

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1555

if (dce110_resource_construct(num_virtual_links, dc, pool, asic_id))

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

57

dc->ctx->logger

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

738

ctx->dc->caps.extended_aux_timeout_support);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

948

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

958

dc->res_pool->underlay_pipe_index))

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

971

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

983

dc->ctx,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

984

dc->bw_dceip,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

985

dc->bw_vbios,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

987

dc->res_pool->pipe_count,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

998

if (memcmp(&dc->current_state->bw_ctx.bw.dce,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.h

31

struct dc;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.h

45

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1025

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1031

result = resource_map_pool_resources(dc, new_ctx, dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1034

result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1038

result = build_mapped_resource(dc, new_ctx, dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1044

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1047

(void)dc;

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1074

static void bw_calcs_data_update_from_pplib(struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1082

if (!dc->bw_vbios)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1085

if (dc->bw_vbios->memory_type == bw_def_hbm)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1092

dc->ctx,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1098

dc->ctx,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1102

dc->bw_vbios->high_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1104

dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1106

dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1108

dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1110

dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1112

dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1114

dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1116

dc->bw_vbios->low_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1121

dc->ctx,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1125

dc->bw_vbios->low_yclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1127

dc->bw_vbios->mid_yclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1130

dc->bw_vbios->high_yclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1138

dc->bw_vbios->high_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1140

dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1142

dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1144

dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1146

dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1148

dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1150

dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1152

dc->bw_vbios->low_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1157

dc->ctx,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1166

dc->bw_vbios->low_yclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1168

dc->bw_vbios->mid_yclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1171

dc->bw_vbios->high_yclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1222

dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1237

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1241

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1254

dc->caps.max_downscale_ratio = 200;

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1255

dc->caps.i2c_speed_in_khz = 100;

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1256

dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1257

dc->caps.max_cursor_size = 128;

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1258

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1259

dc->caps.dual_link_dvi = true;

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1260

dc->caps.extended_aux_timeout_support = false;

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1261

dc->debug = debug_defaults;

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1262

dc->check_config = config_defaults;

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1335

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1406

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1410

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1412

for (i = 0; i < dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1413

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1416

dce112_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1418

bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1420

bw_calcs_data_update_from_pplib(dc);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1431

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1439

if (dce112_resource_construct(num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

63

dc->ctx->logger

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

714

ctx->dc->caps.extended_aux_timeout_support);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

876

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

880

(void)dc;

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

894

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

906

dc->ctx,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

907

dc->bw_dceip,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

908

dc->bw_vbios,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

910

dc->res_pool->pipe_count,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

919

if (memcmp(&dc->current_state->bw_ctx.bw.dce,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

967

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

982

dc->res_pool->dp_clock_source;

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

985

dc->res_pool->dp_clock_source;

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

989

&context->res_ctx, dc->res_pool,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

998

dc->res_pool,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h

31

struct dc;

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h

36

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h

39

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h

46

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h

51

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1001

dc->bw_vbios->high_yclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1052

dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1065

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1071

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1087

dc->caps.max_downscale_ratio = 200;

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1088

dc->caps.i2c_speed_in_khz = 100;

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1089

dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1090

dc->caps.max_cursor_size = 128;

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1091

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1092

dc->caps.dual_link_dvi = true;

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1093

dc->caps.psp_setup_panel_mode = true;

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1094

dc->caps.extended_aux_timeout_support = false;

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1095

dc->debug = debug_defaults;

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1096

dc->check_config = config_defaults;

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1162

irq_init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1257

if (!resource_construct(num_virtual_links, dc, &pool->base, res_funcs))

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1261

if (!dce120_hw_sequencer_create(dc))

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1264

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1266

for (i = 0; i < dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1267

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1269

bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1271

bw_calcs_data_update_from_pplib(dc);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1273

if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1274

ddc_init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1276

ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1279

pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1296

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1304

if (dce120_resource_construct(num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

455

ctx->dc->caps.extended_aux_timeout_support);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

567

static bool dce120_hw_sequencer_create(struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

572

dce120_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

668

struct dc *dc = pool->base.oem_device->ctx->dc;

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

670

dc->link_srv->destroy_ddc_service(&pool->base.oem_device);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

925

static void bw_calcs_data_update_from_pplib(struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

938

dc->ctx,

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

952

dc->bw_vbios->high_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

954

dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

956

dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

958

dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

960

dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

962

dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

964

dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

966

dc->bw_vbios->low_sclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

971

dc->ctx,

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

993

if (dc->bw_vbios->memory_type == bw_def_hbm)

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

996

dc->bw_vbios->low_yclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

998

dc->bw_vbios->mid_yclk = bw_frc_to_fixed(

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.h

31

struct dc;

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.h

36

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1005

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1073

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1075

for (i = 0; i < dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1076

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1078

dc->caps.disable_dp_clk_share = true;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1080

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1085

dce60_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1096

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1104

if (dce60_construct(num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1114

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1118

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1133

dc->caps.max_downscale_ratio = 200;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1134

dc->caps.i2c_speed_in_khz = 40;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1135

dc->caps.max_cursor_size = 64;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1136

dc->caps.is_apu = true;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1203

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1271

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1273

for (i = 0; i < dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1274

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1276

dc->caps.disable_dp_clk_share = true;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1278

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1283

dce60_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1294

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1302

if (dce61_construct(num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1312

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1316

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1331

dc->caps.max_downscale_ratio = 200;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1332

dc->caps.i2c_speed_in_khz = 40;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1333

dc->caps.max_cursor_size = 64;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1334

dc->caps.is_apu = true;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1400

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1468

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1470

for (i = 0; i < dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1471

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1473

dc->caps.disable_dp_clk_share = true;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1475

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1480

dce60_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1491

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1499

if (dce64_construct(num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

549

ctx->dc->caps.extended_aux_timeout_support);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

916

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

920

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

935

dc->caps.max_downscale_ratio = 200;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

936

dc->caps.i2c_speed_in_khz = 40;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

937

dc->caps.max_cursor_size = 64;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

938

dc->caps.dual_link_dvi = true;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

939

dc->caps.extended_aux_timeout_support = false;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.h

31

struct dc;

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.h

36

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.h

40

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.h

44

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1017

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1085

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1087

for (i = 0; i < dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1088

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1090

dc->caps.disable_dp_clk_share = true;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1092

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1097

dce80_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1108

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1116

if (dce80_construct(num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1126

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1130

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1145

dc->caps.max_downscale_ratio = 200;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1146

dc->caps.i2c_speed_in_khz = 40;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1147

dc->caps.i2c_speed_in_khz_hdcp = 40;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1148

dc->caps.max_cursor_size = 128;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1149

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1150

dc->caps.is_apu = true;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1217

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1285

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1287

for (i = 0; i < dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1288

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1290

dc->caps.disable_dp_clk_share = true;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1292

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1297

dce80_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1308

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1316

if (dce81_construct(num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1326

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1330

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1345

dc->caps.max_downscale_ratio = 200;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1346

dc->caps.i2c_speed_in_khz = 40;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1347

dc->caps.i2c_speed_in_khz_hdcp = 40;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1348

dc->caps.max_cursor_size = 128;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1349

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1350

dc->caps.is_apu = true;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1351

dc->debug = debug_defaults;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1352

dc->check_config = config_defaults;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1415

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1483

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1485

for (i = 0; i < dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1486

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1488

dc->caps.disable_dp_clk_share = true;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1490

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1495

dce80_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1506

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1514

if (dce83_construct(num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

555

ctx->dc->caps.extended_aux_timeout_support);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

923

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

927

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

942

dc->caps.max_downscale_ratio = 200;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

943

dc->caps.i2c_speed_in_khz = 40;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

944

dc->caps.i2c_speed_in_khz_hdcp = 40;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

945

dc->caps.max_cursor_size = 128;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

946

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

947

dc->caps.dual_link_dvi = true;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

948

dc->caps.extended_aux_timeout_support = false;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

949

dc->debug = debug_defaults;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

950

dc->check_config = config_defaults;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.h

31

struct dc;

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.h

36

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.h

40

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.h

44

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1082

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1086

(void)dc;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1097

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1103

result = resource_map_pool_resources(dc, new_ctx, dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1106

result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1110

result = build_mapped_resource(dc, new_ctx, dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1147

static bool dcn10_get_dcc_compression_cap(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1151

return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1152

dc->res_pool->hubbub,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1167

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1174

voltage_supported = dcn_validate_bandwidth(dc, context, validate_mode);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1191

static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1243

dc->dcn_soc->number_of_channels == 1)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1359

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1364

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1391

if (dc->ctx->dce_version == DCN_VERSION_1_01)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1393

dc->caps.max_video_width = 3840;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1394

dc->caps.max_downscale_ratio = 200;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1395

dc->caps.i2c_speed_in_khz = 100;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1396

dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1397

dc->caps.max_cursor_size = 256;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1398

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1399

dc->caps.max_slave_planes = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1400

dc->caps.max_slave_yuv_planes = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1401

dc->caps.max_slave_rgb_planes = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1402

dc->caps.is_apu = true;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1403

dc->caps.post_blend_color_processing = false;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1404

dc->caps.extended_aux_timeout_support = false;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1407

dc->caps.force_dp_tps4_for_cp2520 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1410

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1411

dc->caps.color.dpp.input_lut_shared = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1412

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1413

dc->caps.color.dpp.dgam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1414

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1415

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1416

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1417

dc->caps.color.dpp.dgam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1418

dc->caps.color.dpp.dgam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1419

dc->caps.color.dpp.post_csc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1420

dc->caps.color.dpp.gamma_corr = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1421

dc->caps.color.dpp.dgam_rom_for_yuv = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1423

dc->caps.color.dpp.hw_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1424

dc->caps.color.dpp.ogam_ram = 1; // RGAM on DCN1

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1425

dc->caps.color.dpp.ogam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1426

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1427

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1428

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1429

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1430

dc->caps.color.dpp.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1433

dc->caps.color.mpc.gamut_remap = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1434

dc->caps.color.mpc.num_3dluts = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1435

dc->caps.color.mpc.shared_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1436

dc->caps.color.mpc.ogam_ram = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1437

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1438

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1439

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1440

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1441

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1442

dc->caps.color.mpc.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1443

dc->debug = debug_defaults_drv;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1444

dc->check_config = config_defaults;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1446

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1447

dc->debug = debug_defaults_drv;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1466

if (dc->ctx->dce_version == DCN_VERSION_1_0) {

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1475

if (dc->ctx->dce_version == DCN_VERSION_1_01)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1512

dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1513

memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1514

memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1517

dcn10_resource_construct_fp(dc);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1520

if (!dc->config.is_vmin_only_asic)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1521

if (ASICREV_IS_RAVEN2(dc->ctx->asic_id.hw_internal_rev))

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1522

switch (dc->ctx->asic_id.pci_revision_id) {

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1532

dc->config.is_vmin_only_asic = true;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1546

dc->debug.az_endpoint_mute_only = false;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1549

if (!dc->debug.disable_pplib_clock_request) {

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1563

dcn_bw_update_from_pplib_fclks(dc, &fclks);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1578

dcn_bw_update_from_pplib_dcfclks(dc, &dcfclks);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1585

dcn_bw_sync_calcs_and_dml(dc);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1586

if (!dc->debug.disable_pplib_wm_range) {

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1587

dc->res_pool = &pool->base;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1590

dc, &min_fclk_khz, &min_dcfclk_khz, &socclk_khz);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1593

dc, min_fclk_khz, min_dcfclk_khz, socclk_khz);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1598

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1683

dc->dml.ip.max_num_dpp = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1684

dc->dcn_ip->max_num_dpp = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1708

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1712

dcn10_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1713

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1715

for (i = 0; i < dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1716

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1718

dc->cap_funcs = cap_funcs;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1731

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1739

if (dcn10_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

662

ctx->dc->caps.extended_aux_timeout_support);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h

35

struct dc;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h

47

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1226

struct dc *dc = pool->base.oem_device->ctx->dc;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1228

dc->link_srv->destroy_ddc_service(&pool->base.oem_device);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1260

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1261

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1268

if (!dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1329

struct resource_pool *pool = pipe_ctx->stream->ctx->dc->res_pool;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1346

enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1348

(void)dc;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1362

void dcn20_acquire_dsc(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1368

const struct resource_pool *pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1369

struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1413

enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1421

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1433

dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1447

static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1459

dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1470

enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1474

result = resource_map_pool_resources(dc, new_ctx, dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1477

result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1481

result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1484

result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1490

enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1494

result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1516

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1522

const struct resource_pool *pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1561

dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1632

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1644

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1682

bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1687

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1718

struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1726

if (dc && primary_pipe) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1736

if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1737

preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1744

dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1745

preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1759

for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1760

if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1761

&& dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1782

for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1798

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1804

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1822

dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1833

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1862

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1872

bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1877

if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1879

} else if (dc->debug.force_single_disp_pipe_split)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1882

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1902

if ((unsigned int)plane_count > dc->res_pool->pipe_count / 2)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1906

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1924

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1943

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1949

&& dc->config.allow_4to1MPC && dc->res_pool->pipe_count >= 4

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1950

&& !dc->debug.disable_z9_mpc

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1973

if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1977

if (dc->debug.force_odm_combine_4to1 & (1 << pipe->stream_res.tg->inst)) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2058

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2076

dcn20_merge_pipes_for_validate(dc, context);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2078

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2092

vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2098

for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2108

hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2111

dc, &context->res_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2115

dcn20_build_mapped_resource(dc, context, pipe->stream);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2132

hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2142

dc, &context->res_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2145

dcn20_build_mapped_resource(dc, context, pipe->stream);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2148

&context->res_ctx, dc->res_pool,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2162

if (!dcn20_validate_dsc(dc, context)) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2180

enum dc_status dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2187

dc->res_pool->pipe_count);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2192

voltage_supported = dcn20_validate_bandwidth_fp(dc, context, validate_mode, pipes);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2227

bool dcn20_get_dcc_compression_cap(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2231

if (dc->res_pool->hubbub->funcs->get_dcc_compression_cap)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2232

return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2233

dc->res_pool->hubbub, input, output);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2392

static bool init_soc_bounding_box(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2396

get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2398

get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2427

dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2439

dcn20_patch_bounding_box(dc, loaded_bb);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2446

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2450

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2477

dc->caps.max_downscale_ratio = 200;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2478

dc->caps.i2c_speed_in_khz = 100;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2479

dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2480

dc->caps.max_cursor_size = 256;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2481

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2482

dc->caps.dmdata_alloc_size = 2048;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2484

dc->caps.max_slave_planes = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2485

dc->caps.max_slave_yuv_planes = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2486

dc->caps.max_slave_rgb_planes = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2487

dc->caps.post_blend_color_processing = true;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2488

dc->caps.force_dp_tps4_for_cp2520 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2489

dc->caps.extended_aux_timeout_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2490

dc->caps.dmcub_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2493

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2494

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2495

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2496

dc->caps.color.dpp.dgam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2497

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2498

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2499

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2500

dc->caps.color.dpp.dgam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2501

dc->caps.color.dpp.dgam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2502

dc->caps.color.dpp.post_csc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2503

dc->caps.color.dpp.gamma_corr = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2504

dc->caps.color.dpp.dgam_rom_for_yuv = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2506

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2507

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2509

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2510

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2511

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2512

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2513

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2514

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2516

dc->caps.color.mpc.gamut_remap = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2517

dc->caps.color.mpc.num_3dluts = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2518

dc->caps.color.mpc.shared_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2519

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2520

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2521

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2522

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2523

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2524

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2525

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2527

dc->caps.dp_hdmi21_pcon_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2528

dc->check_config = config_defaults;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2530

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2531

dc->debug = debug_defaults_drv;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2534

dc->work_arounds.dedcn20_305_wa = true;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2537

if (dc->vm_helper)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2538

vm_helper_init(dc->vm_helper, 16);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2613

if (!init_soc_bounding_box(dc, pool)) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2619

dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2621

if (!dc->debug.disable_pplib_wm_range) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2663

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2776

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2780

dcn20_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2788

if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2789

dc->hwseq->funcs.enable_power_gating_plane = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2790

dc->debug.disable_dpp_power_gate = true;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2791

dc->debug.disable_hubp_power_gate = true;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2795

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2797

for (i = 0; (unsigned int)i < dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2798

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2800

dc->caps.max_odm_combine_factor = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2802

dc->cap_funcs = cap_funcs;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2804

if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2805

ddc_init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2807

ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2810

pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2826

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2834

if (dcn20_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

829

ctx->dc->caps.extended_aux_timeout_support);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

118

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

122

enum dc_status dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, enum dc_validate_mode validate_mode);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

124

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

127

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

135

bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

142

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

146

void dcn20_acquire_dsc(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

150

struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

155

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

163

enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

164

enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

165

enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, struct dc_state *dc_ctx, struct dc_stream_state *dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

166

enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

35

struct dc;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

50

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

76

bool dcn20_get_dcc_compression_cap(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1063

static bool dcn201_get_dcc_compression_cap(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1067

return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1068

dc->res_pool->hubbub,

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1073

static void dcn201_populate_dml_writeback_from_context(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1078

dcn201_populate_dml_writeback_from_context_fpu(dc, res_ctx, pipes);

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1123

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1127

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1141

dc->caps.max_downscale_ratio = 200;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1142

dc->caps.i2c_speed_in_khz = 100;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1143

dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.5 w/a applied by default*/

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1144

dc->caps.max_cursor_size = 256;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1145

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1146

dc->caps.dmdata_alloc_size = 2048;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1148

dc->caps.max_slave_planes = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1149

dc->caps.max_slave_yuv_planes = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1150

dc->caps.max_slave_rgb_planes = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1151

dc->caps.post_blend_color_processing = true;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1152

dc->caps.force_dp_tps4_for_cp2520 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1153

dc->caps.extended_aux_timeout_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1156

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1157

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1158

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1159

dc->caps.color.dpp.dgam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1160

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1161

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1162

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1163

dc->caps.color.dpp.dgam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1164

dc->caps.color.dpp.dgam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1165

dc->caps.color.dpp.post_csc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1166

dc->caps.color.dpp.gamma_corr = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1167

dc->caps.color.dpp.dgam_rom_for_yuv = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1169

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1170

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1172

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1173

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1174

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1175

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1176

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1177

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1179

dc->caps.color.mpc.gamut_remap = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1180

dc->caps.color.mpc.num_3dluts = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1181

dc->caps.color.mpc.shared_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1182

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1183

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1184

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1185

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1186

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1187

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1188

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1190

dc->debug = debug_defaults_drv;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1191

dc->check_config = config_defaults;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1194

dc->work_arounds.no_connect_phy_config = true;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1195

dc->work_arounds.dedcn20_305_wa = true;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1232

dml_init_instance(&dc->dml, &dcn201_soc, &dcn201_ip, DML_PROJECT_DCN201);

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1235

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1321

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1325

dcn201_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1327

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1329

for (i = 0; i < dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1330

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1332

dc->caps.max_odm_combine_factor = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1334

dc->cap_funcs = cap_funcs;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1347

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1355

if (dcn201_resource_construct(init_data->num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

694

ctx->dc->caps.extended_aux_timeout_support);

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.h

39

struct dc;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.h

48

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1389

if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1398

static void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1401

dcn21_update_bw_bounding_box_fpu(dc, bw_params);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1428

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1433

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1452

dc->caps.max_downscale_ratio = 200;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1453

dc->caps.i2c_speed_in_khz = 100;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1454

dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1455

dc->caps.max_cursor_size = 256;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1456

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1457

dc->caps.dmdata_alloc_size = 2048;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1459

dc->caps.max_slave_planes = 3;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1460

dc->caps.max_slave_yuv_planes = 3;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1461

dc->caps.max_slave_rgb_planes = 3;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1462

dc->caps.post_blend_color_processing = true;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1463

dc->caps.force_dp_tps4_for_cp2520 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1464

dc->caps.extended_aux_timeout_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1465

dc->caps.dmcub_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1466

dc->caps.is_apu = true;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1469

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1470

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1471

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1472

dc->caps.color.dpp.dgam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1473

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1474

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1475

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1476

dc->caps.color.dpp.dgam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1477

dc->caps.color.dpp.dgam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1478

dc->caps.color.dpp.post_csc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1479

dc->caps.color.dpp.gamma_corr = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1480

dc->caps.color.dpp.dgam_rom_for_yuv = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1482

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1483

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1485

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1486

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1487

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1488

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1489

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1490

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1492

dc->caps.color.mpc.gamut_remap = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1493

dc->caps.color.mpc.num_3dluts = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1494

dc->caps.color.mpc.shared_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1495

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1496

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1497

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1498

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1499

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1500

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1501

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1503

dc->caps.dp_hdmi21_pcon_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1504

dc->check_config = config_defaults;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1506

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1507

dc->debug = debug_defaults_drv;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1510

if (dc->vm_helper)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1511

vm_helper_init(dc->vm_helper, 16);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1561

if (!dc->config.disable_dmcu) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1572

dc->debug.dmub_command_table = false;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1575

if (dc->config.disable_dmcu) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1585

if (dc->config.disable_dmcu)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1606

dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1608

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1728

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1732

dcn21_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1734

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1736

for (i = 0; i < dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1737

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1739

dc->caps.max_odm_combine_factor = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1741

dc->cap_funcs = cap_funcs;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1754

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1762

if (dcn21_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

553

ctx->dc->caps.extended_aux_timeout_support);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

776

if (pool->base.abm->ctx->dc->config.disable_dmcu)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

795

bool dcn21_fast_validate_bw(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

814

dcn20_merge_pipes_for_validate(dc, context);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

816

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

853

vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

855

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

879

for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

889

hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

892

dc, &context->res_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

896

dcn20_build_mapped_resource(dc, context, pipe->stream);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

908

hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

918

dc, &context->res_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

921

dcn20_build_mapped_resource(dc, context, pipe->stream);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

924

&context->res_ctx, dc->res_pool,

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

937

if (!dcn20_validate_dsc(dc, context)) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

960

static enum dc_status dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

967

dc->res_pool->pipe_count);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

972

voltage_supported = dcn21_validate_bandwidth_fp(dc, context, validate_mode, pipes);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.h

34

struct dc;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.h

46

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.h

48

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1349

struct dc *dc = pool->base.oem_device->ctx->dc;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1351

dc->link_srv->destroy_ddc_service(&pool->base.oem_device);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1437

enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1440

return dcn20_add_stream_to_ctx(dc, new_ctx, dc_stream);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1477

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1486

dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1489

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1501

struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1504

dcn30_fpu_populate_dml_writeback_from_context(dc, res_ctx, pipes);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1532

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1545

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1645

static bool is_soc_bounding_box_valid(struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1647

uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1655

static bool init_soc_bounding_box(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1661

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1663

if (!is_soc_bounding_box_valid(dc)) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1670

loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1671

dcn20_patch_bounding_box(dc, loaded_bb);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1673

patch_dcn30_soc_bounding_box(dc, &dcn3_0_soc);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1680

const struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1687

const struct resource_pool *pool = dc->res_pool;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1721

dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1742

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1755

for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1756

if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1757

&& dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1772

for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1784

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1805

dcn20_merge_pipes_for_validate(dc, context);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1810

dc->res_pool->funcs->update_soc_for_wm_a(dc, context);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1811

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1831

vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1851

vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1861

if (!dc->config.enable_windowed_mpo_odm) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1862

for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1883

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1904

dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1928

for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1930

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1958

hsplit_pipe = dcn30_find_split_pipe(dc, context, old_index);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1964

dc, &context->res_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1981

pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1986

dc, &context->res_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2000

pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2005

dc, &context->res_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2011

dcn20_build_mapped_resource(dc, context, pipe->stream);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2014

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2024

if (!dcn20_validate_dsc(dc, context)) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2030

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2121

bool dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2133

if (dc->debug.disable_fams)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2136

if (!dc->caps.dmub_caps.mclk_sw)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2156

if (context->streams[0]->vrr_active_variable && (dc->debug.disable_fams_gaming == INGAME_FAMS_DISABLE))

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2172

void dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2174

ASSERT(dc != NULL && context != NULL);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2175

if (dc == NULL || context == NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2182

void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2185

dcn30_fpu_update_soc_for_wm_a(dc, context);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2190

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2196

dcn30_fpu_calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2200

enum dc_status dcn30_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2211

dc->res_pool->pipe_count);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2212

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2220

out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, true);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2237

if (dc->res_pool->funcs->calculate_wm_and_dlg)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2238

dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2260

void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2278

if (dc->ctx->dc_bios->vram_info.num_chans)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2279

dcn3_0_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2282

dcn30_fpu_update_dram_channel_width_bytes(dc);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2383

dcn30_fpu_update_bw_bounding_box(dc, bw_params, &dcn30_bb_max_clk, dcfclk_mhz, dram_speed_mts);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2434

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2438

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2465

dc->caps.max_downscale_ratio = 600;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2466

dc->caps.i2c_speed_in_khz = 100;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2467

dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2468

dc->caps.max_cursor_size = 256;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2469

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2470

dc->caps.dmdata_alloc_size = 2048;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2471

dc->caps.mall_size_per_mem_channel = 8;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2473

dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2474

dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2476

dc->caps.max_slave_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2477

dc->caps.max_slave_yuv_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2478

dc->caps.max_slave_rgb_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2479

dc->caps.post_blend_color_processing = true;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2480

dc->caps.force_dp_tps4_for_cp2520 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2481

dc->caps.hdmi_hpo = true;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2482

dc->config.skip_frl_pretraining = true;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2483

dc->caps.extended_aux_timeout_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2484

dc->caps.dmcub_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2487

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2488

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2489

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2490

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2491

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2492

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2493

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2494

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2495

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2496

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2497

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2498

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2500

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2501

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2503

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2504

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2505

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2506

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2507

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2508

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2510

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2511

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2512

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2513

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2514

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2515

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2516

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2517

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2518

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2520

dc->caps.dp_hdmi21_pcon_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2521

dc->caps.max_v_total = (1 << 15) - 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2522

dc->caps.vtotal_limited_by_fp2 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2531

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2540

dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2543

dc->check_config = config_defaults;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2545

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2546

dc->debug = debug_defaults_drv;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2549

if (dc->vm_helper)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2550

vm_helper_init(dc->vm_helper, 16);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2607

init_soc_bounding_box(dc, pool);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2618

dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2621

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2752

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2757

dcn30_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2759

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2761

for (i = 0; i < dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2762

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2764

dc->caps.max_odm_combine_factor = 4;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2766

dc->cap_funcs = cap_funcs;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2768

if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2769

ddc_init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2771

ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2774

pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2793

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2801

if (dcn30_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

844

ctx->dc->caps.extended_aux_timeout_support);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

98

dc->ctx->logger

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

101

void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

103

bool dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

104

void dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

105

int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

34

struct dc;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

46

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

49

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

59

enum dc_status dcn30_validate_bandwidth(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

62

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

70

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

74

void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

76

struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

79

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

97

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1314

static bool is_soc_bounding_box_valid(struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1316

uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1324

static bool init_soc_bounding_box(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1330

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1332

if (!is_soc_bounding_box_valid(dc)) {

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1340

dcn20_patch_bounding_box(dc, loaded_bb);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1343

if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1346

if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1401

static void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1404

dcn301_fpu_update_bw_bounding_box(dc, bw_params);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1408

static void dcn301_calculate_wm_and_dlg(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1415

dcn301_fpu_calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel_req);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1445

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1450

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1455

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1459

if (dc->ctx->asic_id.chip_id == DEVICE_ID_VGH_1435)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1471

dc->caps.max_downscale_ratio = 600;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1472

dc->caps.i2c_speed_in_khz = 100;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1473

dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a enabled by default*/

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1474

dc->caps.max_cursor_size = 256;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1475

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1476

dc->caps.dmdata_alloc_size = 2048;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1477

dc->caps.max_slave_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1478

dc->caps.max_slave_yuv_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1479

dc->caps.max_slave_rgb_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1480

dc->caps.is_apu = true;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1481

dc->caps.post_blend_color_processing = true;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1482

dc->caps.force_dp_tps4_for_cp2520 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1483

dc->caps.extended_aux_timeout_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1484

dc->caps.dmcub_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1487

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1488

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1489

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1490

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1491

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1492

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1493

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1494

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1495

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1496

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1497

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1498

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1500

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1501

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1503

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1504

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1505

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1506

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1507

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1508

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1510

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1511

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1512

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1513

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1514

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1515

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1516

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1517

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1518

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1520

dc->caps.dp_hdmi21_pcon_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1528

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1536

dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1538

dc->check_config = config_defaults;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1540

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1541

dc->debug = debug_defaults_drv;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1544

if (dc->vm_helper)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1545

vm_helper_init(dc->vm_helper, 16);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1593

init_soc_bounding_box(dc, pool);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1595

if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1607

dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1610

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1743

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1748

dcn301_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1750

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1752

for (i = 0; i < dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1753

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1755

dc->caps.max_odm_combine_factor = 4;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1757

dc->cap_funcs = cap_funcs;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1770

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1778

if (dcn301_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

764

ctx->dc->caps.extended_aux_timeout_support);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

97

dc->ctx->logger

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.h

31

struct dc;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.h

43

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1065

static bool is_soc_bounding_box_valid(struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1067

uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1075

static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1080

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1082

if (!is_soc_bounding_box_valid(dc)) {

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1089

loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1091

dcn20_patch_bounding_box(dc, loaded_bb);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1094

if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1097

if (dc->ctx->dc_bios->funcs->get_soc_bb_info(

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1098

dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1252

struct dc *dc = pool->oem_device->ctx->dc;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1254

dc->link_srv->destroy_ddc_service(&pool->oem_device);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1265

void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1268

dcn302_fpu_update_bw_bounding_box(dc, bw_params);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1345

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1349

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1365

dc->caps.max_downscale_ratio = 600;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1366

dc->caps.i2c_speed_in_khz = 100;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1367

dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1368

dc->caps.max_cursor_size = 256;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1369

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1370

dc->caps.dmdata_alloc_size = 2048;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1371

dc->caps.mall_size_per_mem_channel = 4;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1373

dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1374

dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1375

dc->caps.max_slave_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1376

dc->caps.max_slave_yuv_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1377

dc->caps.max_slave_rgb_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1378

dc->caps.post_blend_color_processing = true;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1379

dc->caps.force_dp_tps4_for_cp2520 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1380

dc->caps.hdmi_hpo = true;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1381

dc->config.skip_frl_pretraining = true;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1382

dc->caps.extended_aux_timeout_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1383

dc->caps.dmcub_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1384

dc->caps.max_v_total = (1 << 15) - 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1385

dc->caps.vtotal_limited_by_fp2 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1388

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1389

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1390

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1391

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1392

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1393

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1394

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1395

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1396

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1397

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1398

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1399

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1401

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1402

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1404

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1405

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1406

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1407

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1408

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1409

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1411

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1412

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->res_cap->num_mpc_3dlut;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1413

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1414

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1415

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1416

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1417

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1418

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1419

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1421

dc->caps.dp_hdmi21_pcon_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1429

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1438

dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1440

dc->check_config = config_defaults;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1442

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1443

dc->debug = debug_defaults_drv;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1446

if (dc->vm_helper)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1447

vm_helper_init(dc->vm_helper, 16);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1500

init_soc_bounding_box(dc, pool);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1503

dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1506

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1629

if (!resource_construct(num_virtual_links, dc, pool,

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1634

dcn302_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1636

dc->caps.max_planes = pool->pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1638

for (i = 0; i < (int)dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1639

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1641

dc->caps.max_odm_combine_factor = 4;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1643

dc->cap_funcs = cap_funcs;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1645

if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1646

ddc_init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1648

ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1651

pool->oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1665

struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1672

if (dcn302_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

82

dc->ctx->logger

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

914

&aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.h

34

struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.h

36

void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1010

static bool is_soc_bounding_box_valid(struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1012

uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1020

static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1025

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1027

if (!is_soc_bounding_box_valid(dc)) {

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1034

loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1036

dcn20_patch_bounding_box(dc, loaded_bb);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1039

if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1042

if (dc->ctx->dc_bios->funcs->get_soc_bb_info(

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1043

dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1196

struct dc *dc = pool->oem_device->ctx->dc;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1198

dc->link_srv->destroy_ddc_service(&pool->oem_device);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1214

void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1217

dcn303_fpu_update_bw_bounding_box(dc, bw_params);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1286

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1290

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1306

dc->caps.max_downscale_ratio = 600;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1307

dc->caps.i2c_speed_in_khz = 100;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1308

dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1309

dc->caps.max_cursor_size = 256;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1310

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1311

dc->caps.dmdata_alloc_size = 2048;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1312

dc->caps.mall_size_per_mem_channel = 4;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1314

dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel *

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1315

dc->ctx->dc_bios->vram_info.num_chans *

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1317

dc->caps.cursor_cache_size =

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1318

dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1319

dc->caps.max_slave_planes = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1320

dc->caps.max_slave_yuv_planes = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1321

dc->caps.max_slave_rgb_planes = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1322

dc->caps.post_blend_color_processing = true;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1323

dc->caps.force_dp_tps4_for_cp2520 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1324

dc->caps.hdmi_hpo = true;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1325

dc->config.skip_frl_pretraining = true;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1326

dc->caps.extended_aux_timeout_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1327

dc->caps.dmcub_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1328

dc->caps.max_v_total = (1 << 15) - 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1329

dc->caps.vtotal_limited_by_fp2 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1332

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1333

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1334

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1335

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1336

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1337

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1338

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1339

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1340

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1341

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1342

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1343

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1345

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1346

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1348

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1349

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1350

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1351

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1352

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1353

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1355

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1356

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->res_cap->num_mpc_3dlut;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1357

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1358

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1359

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1360

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1361

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1362

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1363

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1365

dc->caps.dp_hdmi21_pcon_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1367

dc->config.dc_mode_clk_limit_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1374

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1382

dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1384

dc->check_config = config_defaults;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1386

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1387

dc->debug = debug_defaults_drv;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1390

if (dc->vm_helper)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1391

vm_helper_init(dc->vm_helper, 16);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1432

init_soc_bounding_box(dc, pool);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1435

dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1438

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1561

if (!resource_construct(num_virtual_links, dc, pool,

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1566

dcn303_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1568

dc->caps.max_planes = pool->pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1570

for (i = 0; i < (int)dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1571

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1573

dc->caps.max_odm_combine_factor = 4;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1575

dc->cap_funcs = cap_funcs;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1577

if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1578

ddc_init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1580

ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1583

pool->oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1597

struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1604

if (dcn303_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

81

dc->ctx->logger

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

872

&aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.h

34

struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.h

36

void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1026

ctx->dc->caps.extended_aux_timeout_support);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

110

dc->ctx->logger

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1192

if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1772

int dcn31x_populate_dml_pipes_from_context(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1782

pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1786

if (dc->debug.dml_hostvm_override == DML_HOSTVM_NO_OVERRIDE) {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1788

pipes[i].pipe.src.hostvm = dc->vm_pa_config.is_hvm_enabled;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1789

} else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_FALSE)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1791

else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_TRUE)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1798

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1808

dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1811

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1860

if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1866

} else if (context->stream_count >= dc->debug.crb_alloc_policy_min_disp_count

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1867

&& dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1868

context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1883

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1889

dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1894

dcn31_populate_dml_writeback_from_context(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1899

dcn30_populate_dml_writeback_from_context(dc, res_ctx, pipes);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1904

dcn31_set_mcif_arb_params(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1910

dcn30_set_mcif_arb_params(dc, context, pipes, pipe_cnt);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1914

enum dc_status dcn31_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1925

dc->res_pool->pipe_count);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1926

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1934

out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, true);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1950

if (dc->res_pool->funcs->calculate_wm_and_dlg)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1951

dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1981

static void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1984

dcn31_update_bw_bounding_box_fpu(dc, bw_params);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2046

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2050

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2065

dc->caps.max_downscale_ratio = 600;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2066

dc->caps.i2c_speed_in_khz = 100;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2067

dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2068

dc->caps.max_cursor_size = 256;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2069

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2070

dc->caps.dmdata_alloc_size = 2048;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2072

dc->caps.max_slave_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2073

dc->caps.max_slave_yuv_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2074

dc->caps.max_slave_rgb_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2075

dc->caps.post_blend_color_processing = true;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2076

dc->caps.force_dp_tps4_for_cp2520 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2077

if (dc->config.forceHBR2CP2520)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2078

dc->caps.force_dp_tps4_for_cp2520 = false;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2079

dc->caps.hdmi_hpo = true;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2080

dc->config.skip_frl_pretraining = true;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2081

dc->caps.dp_hpo = true;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2082

dc->caps.dp_hdmi21_pcon_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2083

dc->caps.edp_dsc_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2084

dc->caps.extended_aux_timeout_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2085

dc->caps.dmcub_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2086

dc->caps.is_apu = true;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2087

dc->caps.zstate_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2090

dc->config.allow_4to1MPC = true;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2093

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2094

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2095

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2096

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2097

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2098

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2099

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2100

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2101

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2102

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2103

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2104

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2106

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2107

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2109

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2110

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2111

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2112

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2113

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2114

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2116

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2117

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2118

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2119

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2120

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2121

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2122

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2123

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2124

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2126

dc->caps.num_of_host_routers = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2127

dc->caps.num_of_dpias_per_host_router = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2130

dc->config.use_pipe_ctx_sync_logic = true;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2131

dc->config.disable_hbr_audio_dp2 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2133

dc->config.no_native422_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2142

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2147

dc->caps.vbios_lttpr_aware = true;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2150

dc->check_config = config_defaults;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2152

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2153

dc->debug = debug_defaults_drv;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2156

if (dc->vm_helper)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2157

vm_helper_init(dc->vm_helper, 16);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2173

if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2223

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2362

if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2363

dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2364

!dc->debug.dpia_debug.bits.disable_dpia) {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2369

if (dc->ctx->asic_id.chip_family == AMDGPU_FAMILY_GC_11_0_1)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2373

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2378

dcn31_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2380

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2382

for (i = 0; i < (int)dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2383

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2385

dc->caps.max_odm_combine_factor = 4;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2387

dc->cap_funcs = cap_funcs;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2389

dc->dcn_ip->max_num_dpp = dcn3_1_ip.max_num_dpp;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2401

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2409

if (dcn31_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2424

struct dc_state *state = link->dc->current_state;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2428

if (link->dc->hwss.calculate_pix_rate_divider) {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2431

link->dc->hwss.calculate_pix_rate_divider((struct dc *)link->dc, state, state->streams[i]);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2435

if (link->dc->res_pool->funcs->build_pipe_pix_clk_params)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2436

link->dc->res_pool->funcs->build_pipe_pix_clk_params(&pipes[i]);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

40

enum dc_status dcn31_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

44

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

49

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

53

dcn31_populate_dml_writeback_from_context(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

57

dcn31_set_mcif_arb_params(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

64

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1061

ctx->dc->caps.extended_aux_timeout_support);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1249

if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

125

dc->ctx->logger

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1827

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1834

pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1844

static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1847

dcn314_update_bw_bounding_box_fpu(dc, bw_params);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1856

enum dc_status dcn314_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1867

dc->res_pool->pipe_count);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1868

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1877

out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, false);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1893

if (dc->res_pool->funcs->calculate_wm_and_dlg)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1894

dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1974

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1978

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1994

dc->config.allow_4to1MPC = true;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1995

dc->caps.max_downscale_ratio = 400;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1996

dc->caps.i2c_speed_in_khz = 100;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1997

dc->caps.i2c_speed_in_khz_hdcp = 100;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1998

dc->caps.max_cursor_size = 256;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1999

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2000

dc->caps.dmdata_alloc_size = 2048;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2001

dc->caps.max_slave_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2002

dc->caps.max_slave_yuv_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2003

dc->caps.max_slave_rgb_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2004

dc->caps.post_blend_color_processing = true;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2005

dc->caps.force_dp_tps4_for_cp2520 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2006

if (dc->config.forceHBR2CP2520)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2007

dc->caps.force_dp_tps4_for_cp2520 = false;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2008

dc->caps.hdmi_hpo = true;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2009

dc->caps.dp_hpo = true;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2010

dc->caps.dp_hdmi21_pcon_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2011

dc->caps.edp_dsc_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2012

dc->caps.extended_aux_timeout_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2013

dc->caps.dmcub_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2014

dc->caps.is_apu = true;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2015

dc->caps.seamless_odm = true;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2017

dc->caps.zstate_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2020

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2021

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2022

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2023

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2024

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2025

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2026

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2027

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2028

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2029

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2030

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2031

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2033

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2034

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2036

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2037

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2038

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2039

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2040

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2041

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2043

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2044

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2045

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2046

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2047

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2048

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2049

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2050

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2051

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2053

dc->caps.max_disp_clock_khz_at_vmin = 650000;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2055

dc->caps.num_of_host_routers = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2056

dc->caps.num_of_dpias_per_host_router = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2059

dc->config.use_pipe_ctx_sync_logic = true;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2068

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2073

dc->caps.vbios_lttpr_aware = true;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2076

dc->check_config = config_defaults;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2078

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2079

dc->debug = debug_defaults_drv;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2082

dc->debug.disable_dpp_power_gate = true;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2083

dc->debug.disable_hubp_power_gate = true;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2086

dc->debug.root_clock_optimization.u32All = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2089

if (dc->vm_helper)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2090

vm_helper_init(dc->vm_helper, 16);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2141

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2284

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2289

dcn314_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2291

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2293

for (i = 0; i < (int)dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2294

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2296

dc->caps.max_odm_combine_factor = 4;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2298

dc->cap_funcs = cap_funcs;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2300

dc->dcn_ip->max_num_dpp = dcn3_14_ip.max_num_dpp;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2313

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2321

if (dcn314_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.h

42

enum dc_status dcn314_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.h

48

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1025

ctx->dc->caps.extended_aux_timeout_support);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1191

if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1792

static bool allow_pixel_rate_crb(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1803

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1823

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1833

bool pixel_rate_crb = allow_pixel_rate_crb(dc, context);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1836

dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1839

for (i = 0, pipe_cnt = 0, crb_pipes = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1868

split_required = split_required || (unsigned int)timing->pix_clk_100hz >= (unsigned int)dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1905

for (i = 0, pipe_cnt = 0, crb_idx = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1917

bool split_required = (unsigned int)pipe->stream->timing.pix_clk_100hz >= (unsigned int)dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1947

if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1954

&& (unsigned int)pipe->stream->timing.pix_clk_100hz < (unsigned int)dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1978

static void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1981

dcn315_update_bw_bounding_box_fpu(dc, bw_params);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2020

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2024

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2040

dc->config.allow_4to1MPC = true;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2042

dc->caps.max_downscale_ratio = 600;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2043

dc->caps.i2c_speed_in_khz = 100;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2044

dc->caps.i2c_speed_in_khz_hdcp = 100;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2045

dc->caps.max_cursor_size = 256;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2046

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2047

dc->caps.dmdata_alloc_size = 2048;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2048

dc->caps.max_slave_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2049

dc->caps.max_slave_yuv_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2050

dc->caps.max_slave_rgb_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2051

dc->caps.post_blend_color_processing = true;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2052

dc->caps.force_dp_tps4_for_cp2520 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2053

if (dc->config.forceHBR2CP2520)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2054

dc->caps.force_dp_tps4_for_cp2520 = false;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2055

dc->caps.hdmi_hpo = true;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2056

dc->config.skip_frl_pretraining = true;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2057

dc->caps.dp_hpo = true;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2058

dc->caps.dp_hdmi21_pcon_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2059

dc->caps.edp_dsc_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2060

dc->caps.extended_aux_timeout_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2061

dc->caps.dmcub_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2062

dc->caps.is_apu = true;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2065

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2066

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2067

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2068

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2069

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2070

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2071

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2072

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2073

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2074

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2075

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2076

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2078

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2079

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2081

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2082

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2083

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2084

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2085

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2086

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2088

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2089

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2090

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2091

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2092

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2093

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2094

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2095

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2096

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2098

dc->config.no_native422_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2107

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2112

dc->caps.vbios_lttpr_aware = true;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2115

dc->check_config = config_defaults;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2117

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2118

dc->debug = debug_defaults_drv;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2121

if (dc->vm_helper)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2122

vm_helper_init(dc->vm_helper, 16);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2175

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2315

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2320

dcn31_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2322

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2324

for (i = 0; i < (int)dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2325

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2327

dc->caps.max_odm_combine_factor = 4;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2329

dc->cap_funcs = cap_funcs;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2331

dc->dcn_ip->max_num_dpp = dcn3_15_ip.max_num_dpp;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2344

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2352

if (dcn315_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.h

42

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1018

ctx->dc->caps.extended_aux_timeout_support);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1184

if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1766

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1777

dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1780

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1829

if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1852

static void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1855

dcn316_update_bw_bounding_box_fpu(dc, bw_params);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1893

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1897

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1914

dc->config.allow_4to1MPC = true;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1916

dc->caps.max_downscale_ratio = 600;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1917

dc->caps.i2c_speed_in_khz = 100;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1918

dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.5 w/a applied by default*/

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1919

dc->caps.max_cursor_size = 256;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1920

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1921

dc->caps.dmdata_alloc_size = 2048;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1922

dc->caps.max_slave_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1923

dc->caps.max_slave_yuv_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1924

dc->caps.max_slave_rgb_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1925

dc->caps.post_blend_color_processing = true;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1926

dc->caps.force_dp_tps4_for_cp2520 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1927

if (dc->config.forceHBR2CP2520)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1928

dc->caps.force_dp_tps4_for_cp2520 = false;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1929

dc->caps.hdmi_hpo = true;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1930

dc->config.skip_frl_pretraining = true;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1931

dc->caps.dp_hpo = true;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1932

dc->caps.dp_hdmi21_pcon_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1933

dc->caps.edp_dsc_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1934

dc->caps.extended_aux_timeout_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1935

dc->caps.dmcub_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1936

dc->caps.is_apu = true;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1939

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1940

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1941

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1942

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1943

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1944

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1945

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1946

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1947

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1948

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1949

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1950

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1952

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1953

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1955

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1956

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1957

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1958

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1959

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1960

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1962

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1963

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1964

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1965

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1966

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1967

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1968

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1969

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1970

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1979

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1984

dc->caps.vbios_lttpr_aware = true;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1987

dc->check_config = config_defaults;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1989

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1990

dc->debug = debug_defaults_drv;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1993

if (dc->vm_helper)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1994

vm_helper_init(dc->vm_helper, 16);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2047

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2179

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2184

dcn31_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2186

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2188

for (i = 0; i < (int)dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2189

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2191

dc->caps.max_odm_combine_factor = 4;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2193

dc->cap_funcs = cap_funcs;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2195

dc->dcn_ip->max_num_dpp = dcn3_16_ip.max_num_dpp;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2208

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2216

if (dcn316_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.h

42

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1666

struct dc *dc = pool->base.oem_device->ctx->dc;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1668

dc->link_srv->destroy_ddc_service(&pool->base.oem_device);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1807

static void dcn32_enable_phantom_plane(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1821

dc_state_create_phantom_plane(dc, context, curr_pipe->plane_state));

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1845

dc_state_add_phantom_plane(dc, phantom_stream, phantom_plane, context);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1852

static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1861

phantom_stream = dc_state_create_phantom_stream(dc, context, ref_pipe->stream);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1870

dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1873

dc_state_add_phantom_stream(dc, context, phantom_stream, ref_pipe->stream);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1880

void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1891

phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1895

dcn32_enable_phantom_plane(dc, context, phantom_stream, index);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1897

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1914

static bool dml1_validate(struct dc *dc, struct dc_state *context, enum dc_validate_mode validate_mode)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1923

dc->res_pool->pipe_count);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1931

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1939

out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1955

dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1958

dcn32_override_min_req_memclk(dc, context);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1961

dcn32_override_min_req_dcfclk(dc, context);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1982

enum dc_status dcn32_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1999

if (dc->debug.using_dml2)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2000

status = dml2_validate(dc, context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2004

status = dml1_validate(dc, context, validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2023

if (dc->debug.using_dml2)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2024

status = dml2_validate(dc, context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2028

status = dml1_validate(dc, context, validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2035

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2054

dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2073

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2087

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2099

if (dc->config.enable_windowed_mpo_odm &&

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2100

dc->debug.enable_single_display_2to1_odm_policy) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2183

dcn32_set_det_allocations(dc, context, pipes);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2196

unsigned int dcn32_calculate_mall_ways_from_bytes(const struct dc *dc, unsigned int total_size_in_mall_bytes)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2204

if (dc->caps.max_cab_allocation_bytes == 0) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2209

cache_lines_used = total_size_in_mall_bytes / dc->caps.cache_line_size + 2;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2211

total_cache_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2212

lines_per_way = total_cache_lines / dc->caps.cache_num_ways;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2225

void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2231

dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2235

static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2239

dcn32_update_bw_bounding_box_fpu(dc, bw_params);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2241

if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2242

dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2244

if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2245

dml2_reinit(dc, &dc->dml2_dc_power_options, &dc->current_state->bw_ctx.dml2_dc_power_source);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2250

unsigned int dcn32_get_max_hw_cursor_size(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2259

return limit_cur_to_buf ? dc->caps.max_buffered_cursor_size : dc->caps.max_cursor_size;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2304

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2308

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2369

dc->caps.max_downscale_ratio = 600;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2370

dc->caps.i2c_speed_in_khz = 100;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2371

dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2373

dc->caps.max_cursor_size = 64;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2375

dc->caps.max_buffered_cursor_size = 64; // floor(sqrt(16 * 1024 / 4) * 4, 256) / 4 = 64

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2376

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2377

dc->caps.dmdata_alloc_size = 2048;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2378

dc->caps.mall_size_per_mem_channel = 4;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2380

dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2381

dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2383

dc->caps.cache_line_size = 64;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2384

dc->caps.cache_num_ways = 16;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2387

dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall(

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2388

dc, dc->ctx->dc_bios->vram_info.num_chans) *

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2389

dc->caps.mall_size_per_mem_channel * 1024 * 1024;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2390

dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2392

dc->caps.subvp_fw_processing_delay_us = 15;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2393

dc->caps.subvp_drr_max_vblank_margin_us = 40;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2394

dc->caps.subvp_prefetch_end_to_mall_start_us = 15;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2395

dc->caps.subvp_swath_height_margin_lines = 16;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2396

dc->caps.subvp_pstate_allow_width_us = 20;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2397

dc->caps.subvp_vertical_int_margin_us = 30;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2398

dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2400

dc->caps.max_slave_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2401

dc->caps.max_slave_yuv_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2402

dc->caps.max_slave_rgb_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2403

dc->caps.post_blend_color_processing = true;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2404

dc->caps.force_dp_tps4_for_cp2520 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2405

if (dc->config.forceHBR2CP2520)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2406

dc->caps.force_dp_tps4_for_cp2520 = false;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2407

dc->caps.hdmi_hpo = true;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2408

dc->config.skip_frl_pretraining = true;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2409

dc->caps.dp_hpo = true;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2410

dc->caps.dp_hdmi21_pcon_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2411

dc->caps.edp_dsc_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2412

dc->caps.extended_aux_timeout_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2413

dc->caps.dmcub_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2414

dc->caps.seamless_odm = true;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2415

dc->caps.max_v_total = (1 << 15) - 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2416

dc->caps.vtotal_limited_by_fp2 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2419

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2420

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2421

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2422

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2423

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2424

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2425

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2426

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2427

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2428

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2429

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2430

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2432

dc->caps.color.dpp.hw_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2433

dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2435

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2436

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2437

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2438

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2439

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2440

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2442

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2443

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2444

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2445

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2446

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2447

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2448

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2449

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2450

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2451

dc->caps.color.mpc.preblend = true;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2454

dc->config.use_pipe_ctx_sync_logic = true;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2456

dc->config.dc_mode_clk_limit_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2457

dc->config.enable_windowed_mpo_odm = true;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2458

dc->config.disable_hbr_audio_dp2 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2466

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2471

dc->caps.vbios_lttpr_aware = true;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2474

dc->check_config = config_defaults;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2476

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2477

dc->debug = debug_defaults_drv;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2480

if (dc->vm_helper)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2481

vm_helper_init(dc->vm_helper, 16);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2534

dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2537

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2678

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2683

dcn32_hw_sequencer_init_functions(dc);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2685

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2687

for (i = 0; i < (int)dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2688

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2690

dc->caps.max_odm_combine_factor = 4;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2692

dc->cap_funcs = cap_funcs;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2694

if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2695

ddc_init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2697

ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2700

pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2705

dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2706

dc->dml2_options.use_native_soc_bb_construction = true;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2707

dc->dml2_options.minimize_dispclk_using_odm = true;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2709

resource_init_common_dml2_callbacks(dc, &dc->dml2_options);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2710

dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2711

dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2712

dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2714

dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2715

dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2716

dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2717

dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2719

dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2720

dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2722

dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2723

dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2724

dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2725

dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2726

dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2727

dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2728

dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2730

dc->dml2_options.max_segments_per_hubp = 18;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2731

dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2732

dc->dml2_options.map_dc_pipes_with_callbacks = true;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2734

if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev) && (dc->config.sdpif_request_limit_words_per_umc == 0))

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2735

dc->config.sdpif_request_limit_words_per_umc = 16;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2738

memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options));

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2739

dc->dml2_dc_power_options.use_clock_dc_limits = true;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2752

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2760

if (dcn32_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2879

old_primary_pipe = &primary_pipe->stream->ctx->dc->current_state->res_ctx.pipe_ctx[primary_index];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2917

struct resource_context *old_ctx = &stream->ctx->dc->current_state->res_ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2991

if (!opp_head_pipe->stream->ctx->dc->config.enable_windowed_mpo_odm)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

3044

dcn20_acquire_dsc(free_pipe->stream->ctx->dc,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

3062

unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

3102

if (ASICREV_IS_GC_11_0_0(dc->ctx->asic_id.hw_internal_rev)) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

3105

} else if (ASICREV_IS_GC_11_0_2(dc->ctx->asic_id.hw_internal_rev)) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

827

ctx->dc->caps.extended_aux_timeout_support);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

944

ctx->dc->dml.ip.det_buffer_size_kbytes,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

945

ctx->dc->dml.ip.pixel_chunk_size_kbytes,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

946

ctx->dc->dml.ip.config_return_buffer_size_in_kbytes);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

101

enum dc_status dcn32_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

106

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

111

struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

117

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

122

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

125

void dcn32_merge_pipes_for_subvp(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

128

bool dcn32_all_pipes_have_stream_and_plane(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

131

bool dcn32_subvp_in_use(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

136

bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

162

void dcn32_determine_det_override(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

166

void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

169

struct dc_stream_state *dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

173

bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

175

unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

177

double dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

181

bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

183

bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

185

void dcn32_update_dml_pipes_odm_policy_based_on_context(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

187

void dcn32_override_min_req_dcfclk(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

189

unsigned int dcn32_calculate_mall_ways_from_bytes(const struct dc *dc, unsigned int total_size_in_mall_bytes);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

191

unsigned int dcn32_get_max_hw_cursor_size(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

77

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

95

void dcn32_add_phantom_pipes(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

108

void dcn32_merge_pipes_for_subvp(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

114

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

133

dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

154

bool dcn32_all_pipes_have_stream_and_plane(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

159

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

171

bool dcn32_subvp_in_use(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

176

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

197

bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

201

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

244

static void override_det_for_subvp(struct dc *dc, struct dc_state *context, uint8_t pipe_segments[])

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

260

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

264

if (dcn32_allow_subvp_high_refresh_rate(dc, context, pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

275

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

312

void dcn32_determine_det_override(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

339

for (j = 0; j < dc->res_pool->pipe_count; j++) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

350

for (k = 0; k < dc->res_pool->pipe_count; k++) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

359

for (k = 0; k < dc->res_pool->pipe_count; k++) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

369

override_det_for_subvp(dc, context, pipe_segments);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

370

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

377

for (i = 0; i < dc->res_pool->pipe_count; i++)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

382

void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

389

bool disable_unbounded_requesting = dc->debug.disable_z9_mpc || dc->debug.disable_unbounded_requesting;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

391

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

40

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

416

dcn32_determine_det_override(dc, context, pipes);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

44

(void)dc;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

479

if (fpo_candidate_stream->ctx->dc->config.enable_fpo_flicker_detection == 1 &&

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

517

struct dc_stream_state *dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

529

if (dc->debug.disable_fams)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

532

if (!dc->caps.dmub_caps.mclk_sw)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

545

dcn32_assign_fpo_vactive_candidate(dc, context, &fpo_candidate_stream);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

550

is_fpo_vactive = dcn32_find_vactive_pipe(dc, context, fpo_candidate_stream, dc->debug.fpo_vactive_min_active_margin_us);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

552

if (!is_fpo_vactive || dc->debug.disable_fpo_vactive)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

578

fpo_vactive_margin_us = is_fpo_vactive ? dc->debug.fpo_vactive_margin_us : 0; // For now hardcode the FPO + Vactive stretch margin to be 2000us

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

586

((dc->debug.disable_fams_gaming == INGAME_FAMS_DISABLE) ||

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

587

(context->stream_count > 1 && !(dc->debug.disable_fams_gaming == INGAME_FAMS_MULTI_DISP_ENABLE))))

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

646

bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

657

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

706

bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

718

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

752

void dcn32_update_dml_pipes_odm_policy_based_on_context(struct dc *dc, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

760

for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

779

void dcn32_override_min_req_dcfclk(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

781

if (dcn32_subvp_in_use(dc, context) && context->bw_ctx.bw.dcn.clk.dcfclk_khz <= MIN_SUBVP_DCFCLK_KHZ)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

92

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

96

if (dc->debug.force_subvp_num_ways) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

97

return dc->debug.force_subvp_num_ways;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

98

} else if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

99

return dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1640

struct dc *dc = pool->base.oem_device->ctx->dc;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1642

dc->link_srv->destroy_ddc_service(&pool->base.oem_device);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1742

static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1746

dcn321_update_bw_bounding_box_fpu(dc, bw_params);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1748

if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1749

dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1751

if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1752

dml2_reinit(dc, &dc->dml2_dc_power_options, &dc->current_state->bw_ctx.dml2_dc_power_source);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1799

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1803

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1865

dc->caps.max_downscale_ratio = 600;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1866

dc->caps.i2c_speed_in_khz = 100;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1867

dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1869

dc->caps.max_cursor_size = 64;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1870

dc->caps.max_buffered_cursor_size = 64; // sqrt(16 * 1024 / 4)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1871

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1872

dc->caps.dmdata_alloc_size = 2048;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1873

dc->caps.mall_size_per_mem_channel = 4;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1875

dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1877

dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1878

dc->caps.cache_line_size = 64;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1879

dc->caps.cache_num_ways = 16;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1882

dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall(

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1883

dc, dc->ctx->dc_bios->vram_info.num_chans) *

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1884

dc->caps.mall_size_per_mem_channel * 1024 * 1024;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1885

dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1887

dc->caps.subvp_fw_processing_delay_us = 15;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1888

dc->caps.subvp_drr_max_vblank_margin_us = 40;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1889

dc->caps.subvp_prefetch_end_to_mall_start_us = 15;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1890

dc->caps.subvp_swath_height_margin_lines = 16;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1891

dc->caps.subvp_pstate_allow_width_us = 20;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1892

dc->caps.subvp_vertical_int_margin_us = 30;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1893

dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1894

dc->caps.max_slave_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1895

dc->caps.max_slave_yuv_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1896

dc->caps.max_slave_rgb_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1897

dc->caps.post_blend_color_processing = true;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1898

dc->caps.force_dp_tps4_for_cp2520 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1899

dc->caps.hdmi_hpo = true;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1900

dc->config.skip_frl_pretraining = true;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1901

dc->caps.dp_hpo = true;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1902

dc->caps.dp_hdmi21_pcon_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1903

dc->caps.edp_dsc_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1904

dc->caps.extended_aux_timeout_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1905

dc->caps.dmcub_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1906

dc->caps.max_v_total = (1 << 15) - 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1907

dc->caps.vtotal_limited_by_fp2 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1910

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1911

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1912

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1913

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1914

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1915

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1916

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1917

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1918

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1919

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1920

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1921

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1923

dc->caps.color.dpp.hw_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1924

dc->caps.color.dpp.ogam_ram = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1926

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1927

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1928

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1929

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1930

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1931

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1933

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1934

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1935

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1936

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1937

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1938

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1939

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1940

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1941

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1942

dc->caps.color.mpc.preblend = true;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1944

dc->config.force_hdmi21_frl_enc_enable = true;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1947

dc->config.use_pipe_ctx_sync_logic = true;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1949

dc->config.dc_mode_clk_limit_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1950

dc->config.enable_windowed_mpo_odm = true;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1951

dc->config.disable_hbr_audio_dp2 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1959

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1964

dc->caps.vbios_lttpr_aware = true;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1967

dc->check_config = config_defaults;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1969

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1970

dc->debug = debug_defaults_drv;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1973

if (dc->vm_helper)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1974

vm_helper_init(dc->vm_helper, 16);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2027

dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2030

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2166

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2171

dcn32_hw_sequencer_init_functions(dc);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2173

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2175

for (i = 0; i < (int)dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2176

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2178

dc->caps.max_odm_combine_factor = 4;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2180

dc->cap_funcs = cap_funcs;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2182

if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2183

ddc_init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2185

ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2188

pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2193

dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2194

dc->dml2_options.use_native_soc_bb_construction = true;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2195

dc->dml2_options.minimize_dispclk_using_odm = true;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2197

resource_init_common_dml2_callbacks(dc, &dc->dml2_options);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2198

dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2199

dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2200

dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2202

dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2203

dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2204

dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2205

dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2207

dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2208

dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2210

dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2211

dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2212

dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2213

dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2214

dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2215

dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2216

dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2218

dc->dml2_options.max_segments_per_hubp = 18;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2219

dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2222

memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options));

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2223

dc->dml2_dc_power_options.use_clock_dc_limits = true;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2236

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2244

if (dcn321_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

815

ctx->dc->caps.extended_aux_timeout_support);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

932

ctx->dc->dml.ip.det_buffer_size_kbytes,

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

933

ctx->dc->dml.ip.pixel_chunk_size_kbytes,

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

934

ctx->dc->dml.ip.config_return_buffer_size_in_kbytes);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.h

43

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1192

if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1750

dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1788

ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1841

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1888

static enum dc_status dcn35_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1895

out = dml2_validate(dc, context,

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1904

dcn35_decide_zstate_support(dc, context);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1918

static int populate_dml_pipes_from_context_fpu(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1926

ret = dcn35_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1932

void dcn35_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1935

dcn35_update_bw_bounding_box_fpu(dc, bw_params);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1973

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1977

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1993

dc->config.allow_4to1MPC = true;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2018

dc->caps.max_downscale_ratio = 600;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2019

dc->caps.i2c_speed_in_khz = 100;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2020

dc->caps.i2c_speed_in_khz_hdcp = 100;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2021

dc->caps.max_cursor_size = 256;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2022

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2023

dc->caps.dmdata_alloc_size = 2048;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2024

dc->caps.max_slave_planes = 3;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2025

dc->caps.max_slave_yuv_planes = 3;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2026

dc->caps.max_slave_rgb_planes = 3;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2027

dc->caps.post_blend_color_processing = true;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2028

dc->caps.force_dp_tps4_for_cp2520 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2029

if (dc->config.forceHBR2CP2520)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2030

dc->caps.force_dp_tps4_for_cp2520 = false;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2031

dc->caps.hdmi_hpo = true;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2032

dc->config.skip_frl_pretraining = true;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2033

dc->caps.dp_hpo = true;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2034

dc->caps.dp_hdmi21_pcon_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2036

dc->caps.edp_dsc_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2037

dc->caps.extended_aux_timeout_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2038

dc->caps.dmcub_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2039

dc->caps.is_apu = true;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2040

dc->caps.seamless_odm = true;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2042

dc->caps.zstate_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2043

dc->caps.ips_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2044

dc->caps.max_v_total = (1 << 15) - 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2045

dc->caps.vtotal_limited_by_fp2 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2048

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2049

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2050

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2051

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2052

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2053

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2054

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2055

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2056

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2057

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2058

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2059

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2061

dc->caps.color.dpp.hw_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2062

dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2064

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2065

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2066

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2067

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2068

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2069

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2071

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2072

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2073

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2074

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2075

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2076

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2077

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2078

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2079

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2080

dc->caps.color.mpc.preblend = true;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2082

dc->caps.num_of_host_routers = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2083

dc->caps.num_of_dpias_per_host_router = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2091

dc->caps.max_disp_clock_khz_at_vmin = 650000;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2094

if (dc->ctx->asic_id.hw_internal_rev >= 0x40)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2095

dc->caps.sequential_ono = true;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2098

dc->config.use_pipe_ctx_sync_logic = true;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2101

dc->config.disable_hbr_audio_dp2 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2109

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2114

dc->caps.vbios_lttpr_aware = true;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2117

dc->check_config = config_defaults;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2119

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2120

dc->debug = debug_defaults_drv;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2122

dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2124

if (dc->vm_helper)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2125

vm_helper_init(dc->vm_helper, 16);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2169

dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2191

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2332

if (dc->debug.dpia_debug.bits.disable_dpia)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2336

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2341

dcn35_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2343

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2345

for (i = 0; i < (int)dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2346

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2348

dc->caps.max_odm_combine_factor = 4;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2350

dc->cap_funcs = cap_funcs;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2352

dc->dcn_ip->max_num_dpp = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2354

dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2355

dc->dml2_options.use_native_soc_bb_construction = true;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2356

dc->dml2_options.minimize_dispclk_using_odm = false;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2357

if (dc->config.EnableMinDispClkODM)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2358

dc->dml2_options.minimize_dispclk_using_odm = true;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2359

dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2361

resource_init_common_dml2_callbacks(dc, &dc->dml2_options);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2362

dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2364

dc->dml2_options.max_segments_per_hubp = 24;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2365

dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2366

dc->dml2_options.override_det_buffer_size_kbytes = true;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2368

if (dc->config.sdpif_request_limit_words_per_umc == 0)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2369

dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2382

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2390

if (dcn35_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

881

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

911

dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

939

ctx->dc->caps.extended_aux_timeout_support);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

315

void dcn35_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

46

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1172

if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1730

dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1768

ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1821

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1868

static enum dc_status dcn351_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1875

out = dml2_validate(dc, context,

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1884

dcn35_decide_zstate_support(dc, context);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1890

static int populate_dml_pipes_from_context_fpu(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1898

ret = dcn351_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1905

static void dcn351_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1908

dcn351_update_bw_bounding_box_fpu(dc, bw_params);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1946

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1950

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1966

dc->config.allow_4to1MPC = true;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1991

dc->caps.max_downscale_ratio = 600;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1992

dc->caps.i2c_speed_in_khz = 100;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1993

dc->caps.i2c_speed_in_khz_hdcp = 100;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1994

dc->caps.max_cursor_size = 256;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1995

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1996

dc->caps.dmdata_alloc_size = 2048;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1997

dc->caps.max_slave_planes = 3;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1998

dc->caps.max_slave_yuv_planes = 3;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1999

dc->caps.max_slave_rgb_planes = 3;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2000

dc->caps.post_blend_color_processing = true;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2001

dc->caps.force_dp_tps4_for_cp2520 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2002

if (dc->config.forceHBR2CP2520)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2003

dc->caps.force_dp_tps4_for_cp2520 = false;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2004

dc->caps.hdmi_hpo = true;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2005

dc->config.skip_frl_pretraining = true;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2006

dc->caps.dp_hpo = true;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2007

dc->caps.dp_hdmi21_pcon_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2009

dc->caps.edp_dsc_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2010

dc->caps.extended_aux_timeout_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2011

dc->caps.dmcub_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2012

dc->caps.is_apu = true;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2013

dc->caps.seamless_odm = true;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2015

dc->caps.zstate_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2016

dc->caps.ips_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2017

dc->caps.max_v_total = (1 << 15) - 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2018

dc->caps.vtotal_limited_by_fp2 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2021

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2022

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2023

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2024

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2025

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2026

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2027

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2028

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2029

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2030

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2031

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2032

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2034

dc->caps.color.dpp.hw_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2035

dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2037

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2038

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2039

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2040

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2041

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2042

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2044

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2045

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2046

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2047

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2048

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2049

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2050

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2051

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2052

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2053

dc->caps.color.mpc.preblend = true;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2055

dc->caps.num_of_host_routers = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2056

dc->caps.num_of_dpias_per_host_router = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2064

dc->caps.max_disp_clock_khz_at_vmin = 650000;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2067

dc->config.use_pipe_ctx_sync_logic = true;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2071

dc->config.use_assr_psp_message = true;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2080

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2085

dc->caps.vbios_lttpr_aware = true;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2088

dc->check_config = config_defaults;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2090

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2091

dc->debug = debug_defaults_drv;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2094

dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2096

if (dc->vm_helper)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2097

vm_helper_init(dc->vm_helper, 16);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2141

dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2163

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2304

if (dc->debug.dpia_debug.bits.disable_dpia)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2308

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2313

dcn351_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2315

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2317

for (i = 0; i < (int)dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2318

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2320

dc->caps.max_odm_combine_factor = 4;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2322

dc->cap_funcs = cap_funcs;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2325

dc->dcn_ip->max_num_dpp = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2327

dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2328

dc->dml2_options.use_native_soc_bb_construction = true;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2329

dc->dml2_options.minimize_dispclk_using_odm = false;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2330

if (dc->config.EnableMinDispClkODM)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2331

dc->dml2_options.minimize_dispclk_using_odm = true;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2332

dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2334

resource_init_common_dml2_callbacks(dc, &dc->dml2_options);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2335

dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2337

dc->dml2_options.max_segments_per_hubp = 24;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2338

dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2339

dc->dml2_options.override_det_buffer_size_kbytes = true;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2341

if (dc->config.sdpif_request_limit_words_per_umc == 0)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2342

dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2355

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2363

if (dcn351_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

861

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

891

dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

919

ctx->dc->caps.extended_aux_timeout_support);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.h

21

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1179

if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1737

dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1775

ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1828

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1875

static enum dc_status dcn35_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1882

out = dml2_validate(dc, context,

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1891

dcn35_decide_zstate_support(dc, context);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1898

static int populate_dml_pipes_from_context_fpu(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1906

ret = dcn35_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1946

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1950

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1988

dc->caps.max_downscale_ratio = 600;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1989

dc->caps.i2c_speed_in_khz = 100;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1990

dc->caps.i2c_speed_in_khz_hdcp = 100;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1991

dc->caps.max_cursor_size = 256;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1992

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1993

dc->caps.dmdata_alloc_size = 2048;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1994

dc->caps.max_slave_planes = 3;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1995

dc->caps.max_slave_yuv_planes = 3;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1996

dc->caps.max_slave_rgb_planes = 3;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1997

dc->caps.post_blend_color_processing = true;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1998

dc->caps.force_dp_tps4_for_cp2520 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1999

if (dc->config.forceHBR2CP2520)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2000

dc->caps.force_dp_tps4_for_cp2520 = false;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2001

dc->caps.hdmi_hpo = true;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2002

dc->config.skip_frl_pretraining = true;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2003

dc->caps.dp_hpo = true;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2004

dc->caps.dp_hdmi21_pcon_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2006

dc->caps.edp_dsc_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2007

dc->caps.extended_aux_timeout_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2008

dc->caps.dmcub_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2009

dc->caps.is_apu = true;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2010

dc->caps.seamless_odm = true;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2012

dc->caps.zstate_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2013

dc->caps.ips_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2014

dc->caps.max_v_total = (1 << 15) - 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2015

dc->caps.vtotal_limited_by_fp2 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2018

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2019

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2020

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2021

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2022

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2023

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2024

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2025

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2026

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2027

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2028

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2029

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2031

dc->caps.color.dpp.hw_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2032

dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2034

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2035

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2036

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2037

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2038

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2039

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2041

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2042

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2043

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2044

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2045

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2046

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2047

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2048

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2049

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2050

dc->caps.color.mpc.preblend = true;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2052

dc->caps.num_of_host_routers = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2053

dc->caps.num_of_dpias_per_host_router = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2061

dc->caps.max_disp_clock_khz_at_vmin = 650000;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2064

if (dc->ctx->asic_id.hw_internal_rev >= 0x40)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2065

dc->caps.sequential_ono = true;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2068

dc->config.use_pipe_ctx_sync_logic = true;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2070

dc->config.disable_hbr_audio_dp2 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2078

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2083

dc->caps.vbios_lttpr_aware = true;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2086

dc->check_config = config_defaults;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2088

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2089

dc->debug = debug_defaults_drv;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2092

dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2094

if (dc->vm_helper)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2095

vm_helper_init(dc->vm_helper, 16);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2139

dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2161

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2302

if (dc->debug.dpia_debug.bits.disable_dpia)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2306

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2311

dcn35_hw_sequencer_construct(dc);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2313

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2315

for (i = 0; i < (int)dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2316

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2318

dc->caps.max_odm_combine_factor = 4;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2320

dc->cap_funcs = cap_funcs;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2322

dc->dcn_ip->max_num_dpp = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2324

dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2325

dc->dml2_options.use_native_soc_bb_construction = true;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2326

dc->dml2_options.minimize_dispclk_using_odm = false;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2327

if (dc->config.EnableMinDispClkODM)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2328

dc->dml2_options.minimize_dispclk_using_odm = true;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2329

dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2331

resource_init_common_dml2_callbacks(dc, &dc->dml2_options);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2332

dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2334

dc->dml2_options.max_segments_per_hubp = 24;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2335

dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2336

dc->dml2_options.override_det_buffer_size_kbytes = true;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2338

if (dc->config.sdpif_request_limit_words_per_umc == 0)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2339

dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2352

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2360

if (dcn36_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

868

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

898

dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

926

ctx->dc->caps.extended_aux_timeout_support);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.h

21

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1432

static unsigned int dcn401_calc_num_avail_chans_for_mall(struct dc *dc, unsigned int num_chans)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1446

if (ASICREV_IS_GC_12_0_0_A0(dc->ctx->asic_id.hw_internal_rev)) {

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1448

} else if (ASICREV_IS_GC_12_0_1_A0(dc->ctx->asic_id.hw_internal_rev)) {

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1656

struct dc *dc = pool->base.oem_device->ctx->dc;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1658

dc->link_srv->destroy_ddc_service(&pool->base.oem_device);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1741

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1763

static void dcn401_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1769

dc->caps.max_cab_allocation_bytes = dcn401_calc_num_avail_chans_for_mall(

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1770

dc, bw_params->num_channels) *

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1771

dc->caps.mall_size_per_mem_channel * 1024 * 1024;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1772

dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1775

if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1776

dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1778

if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1779

dml2_reinit(dc, &dc->dml2_dc_power_options, &dc->current_state->bw_ctx.dml2_dc_power_source);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1782

static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1785

dcn401_update_bw_bounding_box_fpu(dc, bw_params);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1795

enum dc_status dcn401_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1812

if (dc->debug.using_dml2) {

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1814

status = dml2_validate(dc, context,

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1837

if (dc->debug.using_dml2) {

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1839

status = dml2_validate(dc, context,

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1849

void dcn401_prepare_mcache_programming(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1852

if (dc->debug.using_dml21) {

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1854

dml2_prepare_mcache_programming(dc, context,

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1873

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1912

if ((unsigned int)pixel_clk_params->requested_pix_clk_100hz > (unsigned int)(4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1914

} else if ((unsigned int)pixel_clk_params->requested_pix_clk_100hz > (unsigned int)(2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1916

} else if ((unsigned int)pixel_clk_params->requested_pix_clk_100hz > (unsigned int)(stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1995

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1999

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2054

dc->caps.max_downscale_ratio = 600;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2055

dc->caps.i2c_speed_in_khz = 95;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2056

dc->caps.i2c_speed_in_khz_hdcp = 95; /*1.4 w/a applied by default*/

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2058

dc->caps.max_cursor_size = 64;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2059

dc->caps.max_buffered_cursor_size = 64;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2060

dc->caps.cursor_not_scaled = true;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2061

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2062

dc->caps.dmdata_alloc_size = 2048;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2063

dc->caps.mall_size_per_mem_channel = 4;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2064

dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2065

dc->caps.cache_line_size = 64;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2066

dc->caps.cache_num_ways = 16;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2069

dc->caps.max_cab_allocation_bytes = dcn401_calc_num_avail_chans_for_mall(

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2070

dc, dc->ctx->dc_bios->vram_info.num_chans) *

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2071

dc->caps.mall_size_per_mem_channel * 1024 * 1024;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2072

dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2074

dc->caps.subvp_fw_processing_delay_us = 15;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2075

dc->caps.subvp_drr_max_vblank_margin_us = 40;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2076

dc->caps.subvp_prefetch_end_to_mall_start_us = 15;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2077

dc->caps.subvp_swath_height_margin_lines = 16;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2078

dc->caps.subvp_pstate_allow_width_us = 20;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2079

dc->caps.subvp_vertical_int_margin_us = 30;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2080

dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2082

dc->caps.max_slave_planes = 3;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2083

dc->caps.max_slave_yuv_planes = 3;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2084

dc->caps.max_slave_rgb_planes = 3;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2085

dc->caps.post_blend_color_processing = true;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2086

dc->caps.force_dp_tps4_for_cp2520 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2087

dc->caps.hdmi_hpo = true;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2088

dc->caps.dp_hpo = true;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2089

dc->caps.dp_hdmi21_pcon_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2090

dc->caps.edp_dsc_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2091

dc->caps.extended_aux_timeout_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2092

dc->caps.dmcub_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2093

dc->caps.max_v_total = (1 << 15) - 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2094

dc->caps.vtotal_limited_by_fp2 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2096

if (ASICREV_IS_GC_12_0_1_A0(dc->ctx->asic_id.hw_internal_rev))

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2097

dc->caps.dcc_plane_width_limit = 7680;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2100

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2101

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2102

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2103

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2104

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2105

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2106

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2107

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2108

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2109

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2110

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2111

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2113

dc->caps.color.dpp.hw_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2114

dc->caps.color.dpp.ogam_ram = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2116

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2117

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2118

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2119

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2120

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2121

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2123

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2124

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2125

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2126

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2127

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2128

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2129

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2130

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2131

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2132

dc->caps.color.mpc.preblend = true;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2134

dc->config.force_hdmi21_frl_enc_enable = true;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2135

dc->config.use_spl = true;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2136

dc->config.prefer_easf = true;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2138

dc->config.dcn_sharpness_range.sdr_rgb_min = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2139

dc->config.dcn_sharpness_range.sdr_rgb_max = 1750;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2140

dc->config.dcn_sharpness_range.sdr_rgb_mid = 750;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2141

dc->config.dcn_sharpness_range.sdr_yuv_min = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2142

dc->config.dcn_sharpness_range.sdr_yuv_max = 3500;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2143

dc->config.dcn_sharpness_range.sdr_yuv_mid = 1500;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2144

dc->config.dcn_sharpness_range.hdr_rgb_min = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2145

dc->config.dcn_sharpness_range.hdr_rgb_max = 2750;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2146

dc->config.dcn_sharpness_range.hdr_rgb_mid = 1500;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2148

dc->config.dcn_override_sharpness_range.sdr_rgb_min = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2149

dc->config.dcn_override_sharpness_range.sdr_rgb_max = 3250;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2150

dc->config.dcn_override_sharpness_range.sdr_rgb_mid = 1250;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2151

dc->config.dcn_override_sharpness_range.sdr_yuv_min = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2152

dc->config.dcn_override_sharpness_range.sdr_yuv_max = 3500;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2153

dc->config.dcn_override_sharpness_range.sdr_yuv_mid = 1500;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2154

dc->config.dcn_override_sharpness_range.hdr_rgb_min = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2155

dc->config.dcn_override_sharpness_range.hdr_rgb_max = 2750;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2156

dc->config.dcn_override_sharpness_range.hdr_rgb_mid = 1500;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2158

dc->config.dc_mode_clk_limit_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2159

dc->config.enable_windowed_mpo_odm = true;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2160

dc->config.set_pipe_unlock_order = true; /* Need to ensure DET gets freed before allocating */

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2169

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2174

dc->caps.vbios_lttpr_aware = true;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2177

dc->check_config = config_defaults;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2179

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2180

dc->debug = debug_defaults_drv;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2183

if (dc->vm_helper)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2184

vm_helper_init(dc->vm_helper, 16);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2237

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2373

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2378

dcn401_hw_sequencer_init_functions(dc);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2380

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2382

for (i = 0; i < (int)dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2383

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2385

dc->caps.max_odm_combine_factor = 4;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2387

dc->cap_funcs = cap_funcs;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2389

if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2390

ddc_init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2392

ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2395

pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2401

if (dc->config.sdpif_request_limit_words_per_umc == 0)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2402

dc->config.sdpif_request_limit_words_per_umc = 16;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2404

dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2405

dc->dml2_options.use_native_soc_bb_construction = true;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2406

dc->dml2_options.minimize_dispclk_using_odm = true;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2407

dc->dml2_options.map_dc_pipes_with_callbacks = true;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2408

dc->dml2_options.force_tdlut_enable = true;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2410

resource_init_common_dml2_callbacks(dc, &dc->dml2_options);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2411

dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2412

dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2413

dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2415

dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2416

dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2417

dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2418

dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2420

dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2421

dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2423

dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2424

dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2425

dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2426

dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2427

dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2428

dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2429

dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2431

dc->dml2_options.max_segments_per_hubp = 20;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2432

dc->dml2_options.det_segment_size = DCN4_01_CRB_SEGMENT_SIZE_KB;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2435

dc->caps.scl_caps.sharpener_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2438

memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options));

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2439

dc->dml2_dc_power_options.use_clock_dc_limits = true;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2452

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2460

if (dcn401_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

818

ctx->dc->caps.extended_aux_timeout_support);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

21

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

25

enum dc_status dcn401_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

29

void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1649

struct dc *dc = pool->base.oem_device->ctx->dc;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1651

dc->link_srv->destroy_ddc_service(&pool->base.oem_device);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1667

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1706

if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1708

} else if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1710

} else if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1752

ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1805

dsc401_set_fgcg(dsc, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1824

static void dcn42_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1829

if (dc->current_state && dc->current_state->bw_ctx.dml2)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1830

dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1833

static void dcn42_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1836

dcn42_update_bw_bounding_box_fpu(dc, bw_params);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1839

enum dc_status dcn42_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1848

dcn42_decide_odm_override(dc, context);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1851

out = dml2_validate(dc, context, context->bw_ctx.dml2,

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1857

dcn42_decide_zstate_support(dc, context);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1864

void dcn42_prepare_mcache_programming(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1867

if (dc->debug.using_dml21) {

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1869

dml2_prepare_mcache_programming(dc, context,

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1884

if ((unsigned int)(eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1904

static unsigned int dcn42_get_max_hw_cursor_size(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1910

return dc->caps.max_cursor_size;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1960

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1964

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2018

dc->caps.ips_v2_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2019

dc->caps.max_downscale_ratio = 600;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2020

dc->caps.i2c_speed_in_khz = 100;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2021

dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2023

dc->caps.max_cursor_size = 64;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2024

dc->caps.max_buffered_cursor_size = 64;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2025

dc->caps.cursor_not_scaled = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2026

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2027

dc->caps.dmdata_alloc_size = 2048;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2028

dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2030

dc->caps.max_slave_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2031

dc->caps.max_slave_yuv_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2032

dc->caps.max_slave_rgb_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2033

dc->caps.post_blend_color_processing = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2034

dc->caps.force_dp_tps4_for_cp2520 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2035

if (dc->config.forceHBR2CP2520)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2036

dc->caps.force_dp_tps4_for_cp2520 = false;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2037

dc->caps.hdmi_hpo = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2038

dc->caps.dp_hdmi21_pcon_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2039

dc->caps.dp_hpo = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2040

dc->caps.edp_dsc_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2041

dc->caps.extended_aux_timeout_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2042

dc->caps.dmcub_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2043

dc->caps.is_apu = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2044

dc->caps.seamless_odm = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2045

dc->caps.zstate_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2046

dc->caps.ips_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2047

dc->caps.max_v_total = (1 << 15) - 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2048

dc->caps.vtotal_limited_by_fp2 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2051

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2052

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2053

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2054

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2055

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2056

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2057

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2058

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2059

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2060

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2061

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2062

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2064

dc->caps.color.dpp.hw_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2065

dc->caps.color.dpp.ogam_ram = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2067

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2068

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2069

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2070

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2071

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2072

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2074

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2076

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2077

dc->caps.color.mpc.num_rmcm_3dluts = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2078

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2079

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2080

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2081

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2082

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2083

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2084

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2085

dc->caps.color.mpc.preblend = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2086

dc->caps.color.mpc.mcm_3d_lut_caps.dma_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2087

dc->caps.color.mpc.mcm_3d_lut_caps.lut_dim_caps.dim_9 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2088

dc->caps.color.mpc.mcm_3d_lut_caps.lut_dim_caps.dim_17 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2089

dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.linear_1d = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2090

dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.swizzle_3d_bgr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2091

dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.swizzle_3d_rgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2092

dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.unorm_12msb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2093

dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.unorm_12lsb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2094

dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.float_fp1_5_10 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2095

dc->caps.color.mpc.mcm_3d_lut_caps.mem_pixel_order_support.order_rgba = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2096

dc->caps.color.mpc.mcm_3d_lut_caps.mem_pixel_order_support.order_bgra = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2097

dc->caps.color.mpc.rmcm_3d_lut_caps.dma_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2098

dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_17 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2099

dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_33 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2100

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.linear_1d = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2101

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.swizzle_3d_bgr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2102

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.swizzle_3d_rgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2103

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.unorm_12msb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2104

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.unorm_12lsb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2105

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.float_fp1_5_10 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2106

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_pixel_order_support.order_rgba = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2107

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_pixel_order_support.order_bgra = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2109

dc->caps.num_of_host_routers = 3;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2110

dc->caps.num_of_dpias_per_host_router = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2118

dc->caps.max_disp_clock_khz_at_vmin = 650000;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2119

dc->config.use_spl = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2120

dc->config.prefer_easf = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2122

dc->config.dcn_sharpness_range.sdr_rgb_min = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2123

dc->config.dcn_sharpness_range.sdr_rgb_max = 1750;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2124

dc->config.dcn_sharpness_range.sdr_rgb_mid = 750;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2125

dc->config.dcn_sharpness_range.sdr_yuv_min = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2126

dc->config.dcn_sharpness_range.sdr_yuv_max = 3500;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2127

dc->config.dcn_sharpness_range.sdr_yuv_mid = 1500;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2128

dc->config.dcn_sharpness_range.hdr_rgb_min = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2129

dc->config.dcn_sharpness_range.hdr_rgb_max = 2750;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2130

dc->config.dcn_sharpness_range.hdr_rgb_mid = 1500;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2132

dc->config.dcn_override_sharpness_range.sdr_rgb_min = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2133

dc->config.dcn_override_sharpness_range.sdr_rgb_max = 3250;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2134

dc->config.dcn_override_sharpness_range.sdr_rgb_mid = 1250;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2135

dc->config.dcn_override_sharpness_range.sdr_yuv_min = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2136

dc->config.dcn_override_sharpness_range.sdr_yuv_max = 3500;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2137

dc->config.dcn_override_sharpness_range.sdr_yuv_mid = 1500;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2138

dc->config.dcn_override_sharpness_range.hdr_rgb_min = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2139

dc->config.dcn_override_sharpness_range.hdr_rgb_max = 2750;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2140

dc->config.dcn_override_sharpness_range.hdr_rgb_mid = 1500;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2142

dc->config.use_pipe_ctx_sync_logic = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2143

dc->config.dc_mode_clk_limit_support = false;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2144

dc->config.enable_windowed_mpo_odm = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2145

dc->config.set_pipe_unlock_order = true; /* Need to ensure DET gets freed before allocating */

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2147

dc->config.use_assr_psp_message = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2149

dc->config.frame_update_cmd_version2 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2158

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2161

dc->caps.vbios_lttpr_aware = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2163

dc->check_config = config_defaults;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2165

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2166

dc->debug = debug_defaults_drv;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2169

dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2171

if (dc->vm_helper)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2172

vm_helper_init(dc->vm_helper, 16);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2235

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2371

pool->base.usb4_dpia_count = dc->caps.num_of_host_routers * dc->caps.num_of_dpias_per_host_router;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2372

if (dc->debug.dpia_debug.bits.disable_dpia)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2376

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2381

dcn42_hw_sequencer_init_functions(dc);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2383

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2385

for (i = 0; i < dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2386

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2388

dc->caps.max_odm_combine_factor = 4;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2390

dc->cap_funcs = cap_funcs;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2391

dc->dcn_ip->max_num_dpp = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2394

if (dc->config.sdpif_request_limit_words_per_umc == 0)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2395

dc->config.sdpif_request_limit_words_per_umc = 16;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2397

dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2399

dc->dml2_options.use_native_soc_bb_construction = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2400

dc->dml2_options.minimize_dispclk_using_odm = false;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2401

if (dc->config.EnableMinDispClkODM)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2402

dc->dml2_options.minimize_dispclk_using_odm = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2403

dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2404

dc->dml2_options.map_dc_pipes_with_callbacks = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2405

dc->dml2_options.force_tdlut_enable = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2407

resource_init_common_dml2_callbacks(dc, &dc->dml2_options);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2408

dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch =

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2411

dc->dml2_options.max_segments_per_hubp = 24;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2412

dc->dml2_options.det_segment_size = DCN42_CRB_SEGMENT_SIZE_KB;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2413

dc->dml2_options.gpuvm_enable = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2414

dc->dml2_options.hostvm_enable = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2416

dc->dml2_options.pmo.force_mandatory_uclk_pstate_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2419

dc->caps.scl_caps.sharpener_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2431

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2439

if (dcn42_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

833

ctx->dc->caps.extended_aux_timeout_support);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h

590

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h

592

enum dc_status dcn42_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h

596

void dcn42_prepare_mcache_programming(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c

13

void dcn42_decide_zstate_support(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c

18

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c

21

for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c

49

bool dcn42_decide_odm_override(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c

53

DC_LOGGER_INIT(dc->ctx->logger);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c

54

if (dc->ctx->dce_environment == DCE_ENV_DIAG)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c

59

if (dc->debug.force_odm2to1_for_edp_pixclk_mhz != 0 &&

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c

60

context->streams[0]->timing.pix_clk_100hz > dc->debug.force_odm2to1_for_edp_pixclk_mhz * 10000) {

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c

65

odm_override, context->streams[0]->timing.pix_clk_100hz / 10000, dc->debug.force_odm2to1_for_edp_pixclk_mhz);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h

31

void dcn42_decide_zstate_support(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h

32

bool dcn42_decide_odm_override(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1614

struct dc *dc = pool->base.oem_device->ctx->dc;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1616

dc->link_srv->destroy_ddc_service(&pool->base.oem_device);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1632

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1671

if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1673

} else if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1675

} else if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1717

ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1770

dsc401_set_fgcg(dsc, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1789

static void dcn42b_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1794

if (dc->current_state && dc->current_state->bw_ctx.dml2)

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1795

dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1798

static void dcn42b_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1801

dcn42b_update_bw_bounding_box_fpu(dc, bw_params);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1805

enum dc_status dcn42b_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1813

out = dml2_validate(dc, context, context->bw_ctx.dml2,

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1818

dcn42_decide_zstate_support(dc, context);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1825

void dcn42b_prepare_mcache_programming(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1828

if (dc->debug.using_dml21) {

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1830

dml2_prepare_mcache_programming(dc, context,

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1845

if ((unsigned int)(eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1865

static unsigned int dcn42b_get_max_hw_cursor_size(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1872

return dc->caps.max_cursor_size;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1913

struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1917

struct dc_context *ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1958

dc->caps.ips_v2_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1959

dc->caps.max_downscale_ratio = 600;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1960

dc->caps.i2c_speed_in_khz = 100;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1961

dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1963

dc->caps.max_cursor_size = 64;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1964

dc->caps.max_buffered_cursor_size = 64;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1965

dc->caps.cursor_not_scaled = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1966

dc->caps.min_horizontal_blanking_period = 80;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1967

dc->caps.dmdata_alloc_size = 2048;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1968

dc->caps.mall_size_per_mem_channel = 4;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1970

dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel *

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1971

dc->ctx->dc_bios->vram_info.num_chans * 1048576;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1972

dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1973

dc->caps.cache_line_size = 64;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1974

dc->caps.cache_num_ways = 16;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1977

dc->caps.max_cab_allocation_bytes =

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1978

dcn32_calc_num_avail_chans_for_mall(dc, dc->ctx->dc_bios->vram_info.num_chans) *

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1979

dc->caps.mall_size_per_mem_channel * 1024 * 1024;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1980

dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1982

dc->caps.subvp_fw_processing_delay_us = 15;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1983

dc->caps.subvp_drr_max_vblank_margin_us = 40;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1984

dc->caps.subvp_prefetch_end_to_mall_start_us = 15;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1985

dc->caps.subvp_swath_height_margin_lines = 16;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1986

dc->caps.subvp_pstate_allow_width_us = 20;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1987

dc->caps.subvp_vertical_int_margin_us = 30;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1988

dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1990

dc->caps.max_slave_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1991

dc->caps.max_slave_yuv_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1992

dc->caps.max_slave_rgb_planes = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1993

dc->caps.post_blend_color_processing = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1994

dc->caps.force_dp_tps4_for_cp2520 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1995

if (dc->config.forceHBR2CP2520)

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1996

dc->caps.force_dp_tps4_for_cp2520 = false;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1997

dc->caps.dp_hdmi21_pcon_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1998

dc->caps.dp_hpo = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1999

dc->caps.dp_hdmi21_pcon_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2000

dc->caps.edp_dsc_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2001

dc->caps.extended_aux_timeout_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2002

dc->caps.dmcub_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2003

dc->caps.is_apu = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2004

dc->caps.seamless_odm = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2005

dc->caps.zstate_support = false;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2006

dc->caps.ips_support = false;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2007

dc->caps.max_v_total = (1 << 15) - 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2008

dc->caps.vtotal_limited_by_fp2 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2009

dc->config.disable_ips = DMUB_IPS_DISABLE_ALL;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2012

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2013

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2014

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2015

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2016

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2017

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2018

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2019

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2020

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2021

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2022

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2023

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2025

dc->caps.color.dpp.hw_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2026

dc->caps.color.dpp.ogam_ram = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2028

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2029

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2030

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2031

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2032

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2033

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2035

dc->caps.color.mpc.gamut_remap = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2037

dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2038

dc->caps.color.mpc.num_rmcm_3dluts = 2;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2039

dc->caps.color.mpc.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2040

dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2041

dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2042

dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2043

dc->caps.color.mpc.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2044

dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2045

dc->caps.color.mpc.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2046

dc->caps.color.mpc.preblend = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2047

dc->caps.color.mpc.mcm_3d_lut_caps.dma_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2048

dc->caps.color.mpc.mcm_3d_lut_caps.lut_dim_caps.dim_9 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2049

dc->caps.color.mpc.mcm_3d_lut_caps.lut_dim_caps.dim_17 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2050

dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.linear_1d = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2051

dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.swizzle_3d_bgr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2052

dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.swizzle_3d_rgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2053

dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.unorm_12msb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2054

dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.unorm_12lsb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2055

dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.float_fp1_5_10 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2056

dc->caps.color.mpc.mcm_3d_lut_caps.mem_pixel_order_support.order_rgba = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2057

dc->caps.color.mpc.mcm_3d_lut_caps.mem_pixel_order_support.order_bgra = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2058

dc->caps.color.mpc.rmcm_3d_lut_caps.dma_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2059

dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_17 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2060

dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_33 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2061

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.linear_1d = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2062

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.swizzle_3d_bgr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2063

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.swizzle_3d_rgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2064

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.unorm_12msb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2065

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.unorm_12lsb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2066

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.float_fp1_5_10 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2067

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_pixel_order_support.order_rgba = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2068

dc->caps.color.mpc.rmcm_3d_lut_caps.mem_pixel_order_support.order_bgra = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2070

dc->caps.num_of_host_routers = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2071

dc->caps.num_of_dpias_per_host_router = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2079

dc->caps.max_disp_clock_khz_at_vmin = 650000;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2080

dc->config.use_spl = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2081

dc->config.prefer_easf = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2083

dc->config.dcn_sharpness_range.sdr_rgb_min = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2084

dc->config.dcn_sharpness_range.sdr_rgb_max = 1750;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2085

dc->config.dcn_sharpness_range.sdr_rgb_mid = 750;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2086

dc->config.dcn_sharpness_range.sdr_yuv_min = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2087

dc->config.dcn_sharpness_range.sdr_yuv_max = 3500;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2088

dc->config.dcn_sharpness_range.sdr_yuv_mid = 1500;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2089

dc->config.dcn_sharpness_range.hdr_rgb_min = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2090

dc->config.dcn_sharpness_range.hdr_rgb_max = 2750;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2091

dc->config.dcn_sharpness_range.hdr_rgb_mid = 1500;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2093

dc->config.dcn_override_sharpness_range.sdr_rgb_min = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2094

dc->config.dcn_override_sharpness_range.sdr_rgb_max = 3250;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2095

dc->config.dcn_override_sharpness_range.sdr_rgb_mid = 1250;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2096

dc->config.dcn_override_sharpness_range.sdr_yuv_min = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2097

dc->config.dcn_override_sharpness_range.sdr_yuv_max = 3500;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2098

dc->config.dcn_override_sharpness_range.sdr_yuv_mid = 1500;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2099

dc->config.dcn_override_sharpness_range.hdr_rgb_min = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2100

dc->config.dcn_override_sharpness_range.hdr_rgb_max = 2750;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2101

dc->config.dcn_override_sharpness_range.hdr_rgb_mid = 1500;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2103

dc->config.use_pipe_ctx_sync_logic = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2104

dc->config.dc_mode_clk_limit_support = false;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2105

dc->config.enable_windowed_mpo_odm = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2106

dc->config.set_pipe_unlock_order = true; /* Need to ensure DET gets freed before allocating */

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2108

dc->config.use_assr_psp_message = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2110

dc->config.frame_update_cmd_version2 = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2119

dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2122

dc->caps.vbios_lttpr_aware = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2124

dc->check_config = config_defaults;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2126

if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2127

dc->debug = debug_defaults_drv;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2129

dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2131

if (dc->vm_helper)

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2132

vm_helper_init(dc->vm_helper, 16);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2187

init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2333

if (!resource_construct(num_virtual_links, dc, &pool->base,

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2338

dcn42b_hw_sequencer_init_functions(dc);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2340

dc->caps.max_planes = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2341

dc->config.dp_connector_no_native_i2c = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2343

for (i = 0; i < (int)dc->caps.max_planes; ++i)

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2344

dc->caps.planes[i] = plane_cap;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2346

dc->caps.max_odm_combine_factor = 4;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2348

dc->cap_funcs = cap_funcs;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2349

dc->dcn_ip->max_num_dpp = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2352

if (dc->config.sdpif_request_limit_words_per_umc == 0)

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2353

dc->config.sdpif_request_limit_words_per_umc = 16;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2355

dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2357

dc->dml2_options.use_native_soc_bb_construction = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2358

dc->dml2_options.minimize_dispclk_using_odm = false;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2359

if (dc->config.EnableMinDispClkODM)

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2360

dc->dml2_options.minimize_dispclk_using_odm = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2361

dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2362

dc->dml2_options.map_dc_pipes_with_callbacks = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2363

dc->dml2_options.force_tdlut_enable = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2365

resource_init_common_dml2_callbacks(dc, &dc->dml2_options);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2366

dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch =

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2368

dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2369

dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes =

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2372

dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2373

dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2374

dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2375

dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2377

dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2378

dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2380

dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2381

dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2382

dc->dml2_options.mall_cfg.max_cab_allocation_bytes =

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2383

dc->caps.max_cab_allocation_bytes;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2384

dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2385

dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2386

dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2387

dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2389

dc->dml2_options.max_segments_per_hubp = 24;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2390

dc->dml2_options.det_segment_size = DCN42_CRB_SEGMENT_SIZE_KB;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2391

dc->dml2_options.gpuvm_enable = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2392

dc->dml2_options.hostvm_enable = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2395

dc->caps.scl_caps.sharpener_support = true;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2407

struct dc *dc)

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2415

if (dcn42b_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

862

ctx->dc->caps.extended_aux_timeout_support);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h

550

struct dc *dc);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h

552

enum dc_status dcn42b_validate_bandwidth(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h

556

void dcn42b_prepare_mcache_programming(struct dc *dc, struct dc_state *context);

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

212

void dcn401_update_soc_bb_with_values_from_clk_mgr(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config)

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

214

soc_bb->dprefclk_mhz = dc->clk_mgr->dprefclk_khz / 1000;

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

215

soc_bb->dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

216

soc_bb->mall_allocated_for_dcn_mbytes = dc->caps.mall_size_total / (1024 * 1024);

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

218

if (dc->clk_mgr->funcs->is_smu_present &&

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

219

dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr)) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

221

dc->clk_mgr->bw_params,

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

226

void dcn401_update_soc_bb_with_values_from_vbios(struct dml2_soc_bb *soc_bb, const struct dc *dc)

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

228

soc_bb->dchub_refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

229

soc_bb->xtalclk_mhz = dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency / 1000;

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

232

if (dc->ctx->dc_bios->bb_info.dram_clock_change_latency_100ns)

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

234

dc->ctx->dc_bios->bb_info.dram_clock_change_latency_100ns / 10.0;

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

236

if (dc->ctx->dc_bios->bb_info.dram_sr_enter_exit_latency_100ns)

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

238

dc->ctx->dc_bios->bb_info.dram_sr_enter_exit_latency_100ns / 10.0;

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

240

if (dc->ctx->dc_bios->bb_info.dram_sr_exit_latency_100ns)

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

242

dc->ctx->dc_bios->bb_info.dram_sr_exit_latency_100ns / 10.0;

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

245

void dcn401_update_soc_bb_with_values_from_software_policy(struct dml2_soc_bb *soc_bb, const struct dc *dc)

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

248

if (dc->bb_overrides.sr_exit_time_ns)

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

250

dc->bb_overrides.sr_exit_time_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

252

if (dc->bb_overrides.sr_enter_plus_exit_time_ns)

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

254

dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

256

if (dc->bb_overrides.dram_clock_change_latency_ns)

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

258

dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

260

if (dc->bb_overrides.fclk_clock_change_latency_ns)

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

262

dc->bb_overrides.fclk_clock_change_latency_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

265

if (dc->bb_overrides.sr_exit_z8_time_ns)

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

267

dc->bb_overrides.sr_exit_z8_time_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

269

if (dc->bb_overrides.sr_enter_plus_exit_z8_time_ns)

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

271

dc->bb_overrides.sr_enter_plus_exit_z8_time_ns / 1000.0;

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

274

static void apply_soc_bb_updates(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config)

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

281

dcn401_update_soc_bb_with_values_from_clk_mgr(soc_bb, dc, config);

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

282

dcn401_update_soc_bb_with_values_from_vbios(soc_bb, dc);

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

283

dcn401_update_soc_bb_with_values_from_software_policy(soc_bb, dc);

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

286

void dcn401_get_soc_bb(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config)

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

291

apply_soc_bb_updates(soc_bb, dc, config);

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h

17

void dcn401_get_soc_bb(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config);

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h

18

void dcn401_update_soc_bb_with_values_from_clk_mgr(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config);

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h

19

void dcn401_update_soc_bb_with_values_from_vbios(struct dml2_soc_bb *soc_bb, const struct dc *dc);

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h

20

void dcn401_update_soc_bb_with_values_from_software_policy(struct dml2_soc_bb *soc_bb, const struct dc *dc);

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

15

static void get_default_soc_bb(struct dml2_soc_bb *soc_bb, const struct dc *dc)

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

151

static void dcn42_update_soc_bb_with_values_from_clk_mgr(struct dml2_soc_bb *soc_bb, const struct dc *dc)

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

153

soc_bb->dprefclk_mhz = dc->clk_mgr->dprefclk_khz / 1000;

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

154

soc_bb->dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

155

soc_bb->mall_allocated_for_dcn_mbytes = dc->caps.mall_size_total / (1024 * 1024);

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

157

if (dc->clk_mgr->funcs->is_smu_present &&

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

158

dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr)) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

160

dc->clk_mgr->bw_params);

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

163

if (dc->clk_mgr->bw_params->vram_type == Ddr5MemType) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

168

static void apply_soc_bb_updates(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config)

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

17

if (dc->ctx->dce_version == DCN_VERSION_4_2B) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

176

dcn42_update_soc_bb_with_values_from_clk_mgr(soc_bb, dc);

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

177

dcn401_update_soc_bb_with_values_from_vbios(soc_bb, dc);

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

178

dcn401_update_soc_bb_with_values_from_software_policy(soc_bb, dc);

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

181

void dcn42_get_soc_bb(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config)

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

184

get_default_soc_bb(soc_bb, dc);

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

186

apply_soc_bb_updates(soc_bb, dc, config);

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.h

15

void dcn42_get_soc_bb(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config);

drivers/gpu/drm/amd/display/include/logger_interface.h

128

unsigned long long perf_trc_start_stmp = dm_get_timestamp(dc->ctx)

drivers/gpu/drm/amd/display/include/logger_interface.h

132

unsigned long long perf_trc_end_stmp = dm_get_timestamp(dc->ctx); \

drivers/gpu/drm/amd/display/include/logger_interface.h

133

if (dc->debug.performance_trace) { \

drivers/gpu/drm/amd/display/include/logger_interface.h

44

struct dc *dc,

drivers/gpu/drm/amd/display/include/logger_interface.h

48

void post_surface_trace(struct dc *dc);

drivers/gpu/drm/amd/display/include/logger_interface.h

51

struct dc *dc,

drivers/gpu/drm/amd/display/modules/freesync/freesync.c

1011

if (stream->ctx->dc->caps.max_v_total != 0 && stream->timing.h_total != 0) {

drivers/gpu/drm/amd/display/modules/freesync/freesync.c

1199

cur_tick = dm_get_timestamp(core_freesync->dc->ctx);

drivers/gpu/drm/amd/display/modules/freesync/freesync.c

1201

div_u64(dm_get_elapse_time_in_ns(core_freesync->dc->ctx, cur_tick, 0), 1000);

drivers/gpu/drm/amd/display/modules/freesync/freesync.c

128

unsigned int max_hw_v_total = stream->ctx->dc->caps.max_v_total;

drivers/gpu/drm/amd/display/modules/freesync/freesync.c

130

if (stream->ctx->dc->caps.vtotal_limited_by_fp2) {

drivers/gpu/drm/amd/display/modules/freesync/freesync.c

55

struct dc *dc;

drivers/gpu/drm/amd/display/modules/freesync/freesync.c

61

struct mod_freesync *mod_freesync_create(struct dc *dc)

drivers/gpu/drm/amd/display/modules/freesync/freesync.c

69

if (dc == NULL)

drivers/gpu/drm/amd/display/modules/freesync/freesync.c

72

core_freesync->dc = dc;

drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h

113

struct mod_freesync *mod_freesync_create(struct dc *dc);

drivers/gpu/drm/amd/display/modules/inc/mod_power.h

191

struct mod_power *mod_power_create(struct dc *dc,

drivers/gpu/drm/amd/display/modules/inc/mod_stats.h

44

struct mod_stats *mod_stats_create(struct dc *dc,

drivers/gpu/drm/amd/display/modules/inc/mod_vmid.h

40

struct dc *dc,

drivers/gpu/drm/amd/display/modules/power/power.c

101

struct mod_power *mod_power_create(struct dc *dc,

drivers/gpu/drm/amd/display/modules/power/power.c

111

if (dc == NULL)

drivers/gpu/drm/amd/display/modules/power/power.c

196

if ((dc->res_pool->dmcu != NULL) && (dc->res_pool->dmcu->dmcu_version.abm_version < 0x23))

drivers/gpu/drm/amd/display/modules/power/power.c

257

core_power->dc = dc;

drivers/gpu/drm/amd/display/modules/power/power.c

465

struct dc *dc = NULL;

drivers/gpu/drm/amd/display/modules/power/power.c

482

dc = core_power->dc;

drivers/gpu/drm/amd/display/modules/power/power.c

485

if (link != NULL && dc_get_edp_link_panel_inst(dc, link, &panel_inst)) {

drivers/gpu/drm/amd/display/modules/power/power.c

486

if (link->ctx->dc->config.dp_connector_no_native_i2c && link->no_ddc_pin) {

drivers/gpu/drm/amd/display/modules/power/power.c

499

mod_power_replay_notify_mode_change(mod_power, dc, link, stream, stream_index);

drivers/gpu/drm/amd/display/modules/power/power_abm.c

1006

if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst))

drivers/gpu/drm/amd/display/modules/power/power_abm.c

515

struct dc *dc = NULL;

drivers/gpu/drm/amd/display/modules/power/power_abm.c

521

dc = core_power->dc;

drivers/gpu/drm/amd/display/modules/power/power_abm.c

537

(dc->ctx, acpi_display_type, ext_backlight_caps)) {

drivers/gpu/drm/amd/display/modules/power/power_abm.c

673

struct dc *dc = NULL;

drivers/gpu/drm/amd/display/modules/power/power_abm.c

682

dc = core_power->dc;

drivers/gpu/drm/amd/display/modules/power/power_abm.c

693

dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/modules/power/power_abm.c

701

} else if (dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/modules/power/power_abm.c

702

if (!dmub_init_abm_config(dc->res_pool, params, i))

drivers/gpu/drm/amd/display/modules/power/power_abm.c

852

if (link->ctx->dc->config.dp_connector_no_native_i2c && link->no_ddc_pin) {

drivers/gpu/drm/amd/display/modules/power/power_abm.c

859

if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &panel_inst))

drivers/gpu/drm/amd/display/modules/power/power_abm.c

897

if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst))

drivers/gpu/drm/amd/display/modules/power/power_abm.c

918

if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst))

drivers/gpu/drm/amd/display/modules/power/power_abm.c

944

if (link->ctx->dc->config.dp_connector_no_native_i2c && link->no_ddc_pin) {

drivers/gpu/drm/amd/display/modules/power/power_abm.c

951

if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &panel_inst))

drivers/gpu/drm/amd/display/modules/power/power_abm.c

982

if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst))

drivers/gpu/drm/amd/display/modules/power/power_helpers.h

122

struct dc *dc;

drivers/gpu/drm/amd/display/modules/power/power_helpers.h

173

bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link,

drivers/gpu/drm/amd/display/modules/power/power_helpers.h

207

struct dc *dc,

drivers/gpu/drm/amd/display/modules/power/power_psr.c

192

dc_stream_set_static_screen_params(core_power->dc,

drivers/gpu/drm/amd/display/modules/power/power_psr.c

451

link->dc->link_srv->edp_get_psr_residency(link, residency, mode);

drivers/gpu/drm/amd/display/modules/power/power_psr.c

46

struct dc *dc = NULL;

drivers/gpu/drm/amd/display/modules/power/power_psr.c

506

return link->dc->link_srv->edp_set_sink_vtotal_in_psr_active(

drivers/gpu/drm/amd/display/modules/power/power_psr.c

55

dc = core_power->dc;

drivers/gpu/drm/amd/display/modules/power/power_psr.c

632

bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link,

drivers/gpu/drm/amd/display/modules/power/power_psr.c

641

!dc->caps.edp_dsc_support ||

drivers/gpu/drm/amd/display/modules/power/power_psr.c

66

if (dc->ctx->asic_id.chip_family >= AMDGPU_FAMILY_GC_11_0_1)

drivers/gpu/drm/amd/display/modules/power/power_psr.c

72

mod_power_only_edp(dc->current_state, stream);

drivers/gpu/drm/amd/display/modules/power/power_psr.c

90

psr_su_set_dsc_slice_height(dc, link,

drivers/gpu/drm/amd/display/modules/power/power_replay.c

374

return link->dc->link_srv->edp_set_coasting_vtotal(link, coasting_vtotal, frame_skip_number);

drivers/gpu/drm/amd/display/modules/power/power_replay.c

402

link->dc->link_srv->edp_send_replay_cmd(link, Replay_Set_Timing_Sync_Supported,

drivers/gpu/drm/amd/display/modules/power/power_replay.c

431

link->dc->link_srv->edp_send_replay_cmd(link, Replay_Disabled_Adaptive_Sync_SDP,

drivers/gpu/drm/amd/display/modules/power/power_replay.c

463

link->dc->link_srv->edp_send_replay_cmd(link, Replay_Set_General_Cmd,

drivers/gpu/drm/amd/display/modules/power/power_replay.c

502

link->dc->link_srv->edp_send_replay_cmd(link, Replay_Set_Pseudo_VTotal, &cmd_data);

drivers/gpu/drm/amd/display/modules/power/power_replay.c

761

if (link && link->dc && link->dc->link_srv)

drivers/gpu/drm/amd/display/modules/power/power_replay.c

762

link->dc->link_srv->edp_replay_residency(link, residency, is_start, mode);

drivers/gpu/drm/amd/display/modules/power/power_replay.c

791

return link->dc->link_srv->edp_set_replay_power_opt_and_coasting_vtotal(link, &power_opt, coasting_vtotal, frame_skip_number);

drivers/gpu/drm/amd/display/modules/power/power_replay.c

795

struct dc *dc,

drivers/gpu/drm/amd/display/modules/power/power_replay.c

803

if (!mod_power || !dc || !link || !stream)

drivers/gpu/drm/amd/display/modules/power/power_replay.c

811

mod_power_only_edp(dc->current_state, stream));

drivers/gpu/drm/amd/display/modules/power/power_replay.c

818

dc->link_srv->dp_setup_replay(link, stream);

drivers/gpu/drm/amd/display/modules/vmid/vmid.c

121

dc_setup_vm_context(core_vmid->dc, &va_config, vmid);

drivers/gpu/drm/amd/display/modules/vmid/vmid.c

139

struct dc *dc,

drivers/gpu/drm/amd/display/modules/vmid/vmid.c

148

if (dc == NULL)

drivers/gpu/drm/amd/display/modules/vmid/vmid.c

156

core_vmid->dc = dc;

drivers/gpu/drm/amd/display/modules/vmid/vmid.c

30

struct dc *dc;

drivers/gpu/drm/amd/display/modules/vmid/vmid.c

60

int ord_int = dc_get_vmid_use_vector(core_vmid->dc);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

103

ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

127

prate = clk_get_rate(crtc->dc->hlcdc->sys_clk);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

129

if (!crtc->dc->desc->fixed_clksrc) {

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

170

if (!crtc->dc->desc->is_xlcdc) {

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

186

(crtc->dc->desc->is_xlcdc ? ATMEL_XLCDC_MODE_MASK |

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

190

clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

199

return atmel_hlcdc_dc_mode_valid(crtc->dc, mode);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

207

struct regmap *regmap = crtc->dc->hlcdc->regmap;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

214

if (crtc->dc->desc->is_xlcdc) {

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

246

clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

259

struct regmap *regmap = crtc->dc->hlcdc->regmap;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

267

clk_prepare_enable(crtc->dc->hlcdc->sys_clk);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

287

if (crtc->dc->desc->is_xlcdc) {

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

426

output_fmts = crtc->dc->desc->is_xlcdc ? ATMEL_XLCDC_OUTPUT_MODE_MASK :

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

437

if (crtc->dc->desc->conflicting_output_formats)

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

448

if (crtc->dc->desc->is_xlcdc) {

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

564

if (c->dc->desc->is_xlcdc)

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

58

struct atmel_hlcdc_dc *dc;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

583

struct regmap *regmap = crtc->dc->hlcdc->regmap;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

594

struct regmap *regmap = crtc->dc->hlcdc->regmap;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

612

struct atmel_hlcdc_dc *dc = dev->dev_private;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

617

if (!dc->layers[i])

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

620

switch (dc->layers[i]->desc->type) {

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

622

primary = atmel_hlcdc_layer_to_plane(dc->layers[i]);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

626

cursor = atmel_hlcdc_layer_to_plane(dc->layers[i]);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

639

crtc->dc = dc;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

645

if (dc->layers[i] &&

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

646

dc->layers[i]->desc->type == ATMEL_HLCDC_OVERLAY_LAYER) {

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

647

overlay = atmel_hlcdc_layer_to_plane(dc->layers[i]);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

658

dc->crtc = &crtc->base;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

72

struct regmap *regmap = crtc->dc->hlcdc->regmap;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

1004

struct atmel_hlcdc_dc *dc = drm_dev->dev_private;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

1006

clk_prepare_enable(dc->hlcdc->periph_clk);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

1007

regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, dc->suspend.imr);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

1009

return drm_atomic_helper_resume(drm_dev, dc->suspend.state);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

684

atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

694

if (hsync_len > dc->desc->max_spw + 1 || hsync_len < 1)

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

697

if (vsync_len > dc->desc->max_spw + 1 || vsync_len < 1)

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

700

if (hfront_porch > dc->desc->max_hpw + 1 || hfront_porch < 1 ||

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

701

hback_porch > dc->desc->max_hpw + 1 || hback_porch < 1 ||

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

705

if (vfront_porch > dc->desc->max_vpw + 1 || vfront_porch < 1 ||

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

706

vback_porch > dc->desc->max_vpw || vback_porch < 0 ||

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

727

struct atmel_hlcdc_dc *dc = dev->dev_private;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

732

regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_IMR, &imr);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

733

regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

739

atmel_hlcdc_crtc_irq(dc->crtc);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

743

atmel_hlcdc_layer_irq(dc->layers[i]);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

751

struct atmel_hlcdc_dc *dc = dev->dev_private;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

757

if (dc->layers[i])

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

761

regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, cfg);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

766

struct atmel_hlcdc_dc *dc = dev->dev_private;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

769

regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, 0xffffffff);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

770

regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

802

struct atmel_hlcdc_dc *dc = dev->dev_private;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

825

dev->mode_config.min_width = dc->desc->min_width;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

826

dev->mode_config.min_height = dc->desc->min_height;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

827

dev->mode_config.max_width = dc->desc->max_width;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

828

dev->mode_config.max_height = dc->desc->max_height;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

844

struct atmel_hlcdc_dc *dc = atmel_hlcdc_dc_of_dev(dev);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

858

dc->desc = match->data;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

859

dc->hlcdc = dev_get_drvdata(dev->dev->parent);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

860

dev->dev_private = dc;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

862

ret = clk_prepare_enable(dc->hlcdc->periph_clk);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

885

ret = atmel_hlcdc_dc_irq_install(dev, dc->hlcdc->irq);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

900

clk_disable_unprepare(dc->hlcdc->periph_clk);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

907

struct atmel_hlcdc_dc *dc = dev->dev_private;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

920

clk_disable_unprepare(dc->hlcdc->periph_clk);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

938

struct atmel_hlcdc_dc *dc;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

945

dc = devm_drm_dev_alloc(&pdev->dev, &atmel_hlcdc_dc_driver, struct atmel_hlcdc_dc, dev);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

946

if (IS_ERR(dc))

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

947

return PTR_ERR(dc);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

948

ddev = &dc->dev;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

984

struct atmel_hlcdc_dc *dc = drm_dev->dev_private;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

985

struct regmap *regmap = dc->hlcdc->regmap;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

992

dc->suspend.state = state;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

994

regmap_read(regmap, ATMEL_HLCDC_IMR, &dc->suspend.imr);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

995

regmap_write(regmap, ATMEL_HLCDC_IDR, dc->suspend.imr);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

996

clk_disable_unprepare(dc->hlcdc->periph_clk);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h

383

struct atmel_hlcdc_dc *dc);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h

387

struct atmel_hlcdc_dc *dc);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h

486

atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c

73

struct atmel_hlcdc_dc *dc = dev->dev_private;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c

74

struct drm_crtc *crtc = dc->crtc;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

1016

struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

1041

dc->desc->ops->lcdc_csc_init(plane, desc);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

1083

struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

1085

dc->desc->ops->lcdc_irq_dbg(plane, desc);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

1117

struct atmel_hlcdc_dc *dc = p->dev->dev_private;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

1124

dscr = dma_pool_alloc(dc->dscrpool, GFP_KERNEL, &dscr_dma);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

1140

dma_pool_free(dc->dscrpool, state->dscrs[i],

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

1173

struct atmel_hlcdc_dc *dc = p->dev->dev_private;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

1177

dma_pool_free(dc->dscrpool, state->dscrs[i],

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

1189

struct atmel_hlcdc_dc *dc = p->dev->dev_private;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

1209

dc->desc->ops->lcdc_csc_init(plane, plane->layer.desc);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

1223

struct atmel_hlcdc_dc *dc = dev->dev_private;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

1241

atmel_hlcdc_layer_init(&plane->layer, desc, dc->hlcdc->regmap);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

1251

dc->layers[desc->id] = &plane->layer;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

1258

struct atmel_hlcdc_dc *dc = dev->dev_private;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

1259

const struct atmel_hlcdc_layer_desc *descs = dc->desc->layers;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

1260

int nlayers = dc->desc->nlayers;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

1263

dc->dscrpool = dmam_pool_create("atmel-hlcdc-dscr", dev->dev,

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

1266

if (!dc->dscrpool)

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

408

struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

426

dc->desc->ops->plane_setup_scaler(plane, state);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

580

struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

585

if (!dc->desc->is_xlcdc)

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

593

dc->desc->ops->lcdc_update_buffers(plane, state, sr, i);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

831

struct atmel_hlcdc_dc *dc)

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

848

struct atmel_hlcdc_dc *dc)

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

863

regmap_write(dc->hlcdc->regmap, ATMEL_XLCDC_ATTRE, ATMEL_XLCDC_BASE_UPDATE |

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

875

struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

877

dc->desc->ops->lcdc_atomic_disable(plane, dc);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

881

struct atmel_hlcdc_dc *dc)

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

900

struct atmel_hlcdc_dc *dc)

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

916

regmap_write(dc->hlcdc->regmap, ATMEL_XLCDC_ATTRE, ATMEL_XLCDC_BASE_UPDATE |

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

929

struct atmel_hlcdc_dc *dc = p->dev->dev_private;

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

940

dc->desc->ops->lcdc_update_general_settings(plane, hstate);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c

946

dc->desc->ops->lcdc_atomic_update(plane, dc);

drivers/gpu/drm/drm_mipi_dbi.c

1041

gpiod_set_value_cansleep(dbi->dc, 0);

drivers/gpu/drm/drm_mipi_dbi.c

1080

gpiod_set_value_cansleep(dbi->dc, 0);

drivers/gpu/drm/drm_mipi_dbi.c

1091

gpiod_set_value_cansleep(dbi->dc, 1);

drivers/gpu/drm/drm_mipi_dbi.c

1134

struct gpio_desc *dc)

drivers/gpu/drm/drm_mipi_dbi.c

1161

if (dc) {

drivers/gpu/drm/drm_mipi_dbi.c

1163

dbi->dc = dc;

drivers/gpu/drm/drm_mipi_dbi.c

291

if (!dbi->dc || !full || swap ||

drivers/gpu/drm/drm_mipi_dbi.c

742

static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi, int dc,

drivers/gpu/drm/drm_mipi_dbi.c

760

__func__, dc, max_chunk);

drivers/gpu/drm/drm_mipi_dbi.c

765

if (!dc) {

drivers/gpu/drm/drm_mipi_dbi.c

860

static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int dc,

drivers/gpu/drm/drm_mipi_dbi.c

876

return mipi_dbi_spi1e_transfer(dbi, dc, buf, len, bpw);

drivers/gpu/drm/drm_mipi_dbi.c

884

__func__, dc, max_chunk);

drivers/gpu/drm/drm_mipi_dbi.c

899

if (dc) {

drivers/gpu/drm/drm_mipi_dbi.c

907

if (dc)

drivers/gpu/drm/i915/gt/selftest_rps.c

544

u64 dc, dt;

drivers/gpu/drm/i915/gt/selftest_rps.c

546

dc = READ_ONCE(*cntr);

drivers/gpu/drm/i915/gt/selftest_rps.c

549

dc = READ_ONCE(*cntr) - dc;

drivers/gpu/drm/i915/gt/selftest_rps.c

552

return div64_u64(1000 * 1000 * dc, dt);

drivers/gpu/drm/i915/gt/selftest_rps.c

573

u64 dc, dt;

drivers/gpu/drm/i915/gt/selftest_rps.c

575

dc = intel_uncore_read_fw(engine->uncore, CS_GPR(0));

drivers/gpu/drm/i915/gt/selftest_rps.c

578

dc = intel_uncore_read_fw(engine->uncore, CS_GPR(0)) - dc;

drivers/gpu/drm/i915/gt/selftest_rps.c

581

return div64_u64(1000 * 1000 * dc, dt);

drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c

317

ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,

drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c

337

if (!IS_ERR_OR_NULL(ipu_crtc->dc))

drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c

338

ipu_dc_put(ipu_crtc->dc);

drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c

349

ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);

drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c

350

if (IS_ERR(ipu_crtc->dc))

drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c

351

return PTR_ERR(ipu_crtc->dc);

drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c

38

struct ipu_dc *dc;

drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c

57

ipu_dc_enable_channel(ipu_crtc->dc);

drivers/gpu/drm/imx/ipuv3/ipuv3-crtc.c

89

ipu_dc_disable_channel(ipu_crtc->dc);

drivers/gpu/drm/loongson/loongson_device.c

29

.dc = {

drivers/gpu/drm/loongson/loongson_device.c

61

.dc = {

drivers/gpu/drm/loongson/loongson_device.c

93

[CHIP_LS7A1000] = &ls7a1000_gfx.dc,

drivers/gpu/drm/loongson/loongson_device.c

94

[CHIP_LS7A2000] = &ls7a2000_gfx.dc,

drivers/gpu/drm/loongson/lsdc_debugfs.c

74

pci_read_config_word(ldev->dc, PCI_COMMAND, &cmd);

drivers/gpu/drm/loongson/lsdc_debugfs.c

80

pci_write_config_word(ldev->dc, PCI_COMMAND, cmd);

drivers/gpu/drm/loongson/lsdc_debugfs.c

82

pci_read_config_word(ldev->dc, PCI_COMMAND, &cmd);

drivers/gpu/drm/loongson/lsdc_drv.c

205

ldev->dc = pdev;

drivers/gpu/drm/loongson/lsdc_drv.h

271

struct pci_dev *dc;

drivers/gpu/drm/loongson/lsdc_drv.h

72

struct lsdc_desc dc;

drivers/gpu/drm/loongson/lsdc_drv.h

95

return container_of_const(dcp, struct loongson_gfx_desc, dc);

drivers/gpu/drm/loongson/lsdc_gfxpll.c

107

if (dc)

drivers/gpu/drm/loongson/lsdc_gfxpll.c

108

*dc = dc_mhz;

drivers/gpu/drm/loongson/lsdc_gfxpll.c

122

unsigned int dc, gmc, gpu;

drivers/gpu/drm/loongson/lsdc_gfxpll.c

134

this->funcs->get_rates(this, &dc, &gmc, &gpu);

drivers/gpu/drm/loongson/lsdc_gfxpll.c

136

drm_printf(p, "dc: %uMHz, gmc: %uMHz, gpu: %uMHz\n", dc, gmc, gpu);

drivers/gpu/drm/loongson/lsdc_gfxpll.c

81

unsigned int *dc,

drivers/gpu/drm/loongson/lsdc_gfxpll.h

29

unsigned int *dc, unsigned int *gmc, unsigned int *gpu);

drivers/gpu/drm/meson/meson_registers.h

1687

#define VPU_RDARB_SLAVE_TO_MASTER_PORT(dc, port) (port << (16 + dc))

drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h

25

u8 dc;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

181

ior->func->dp->drive(ior, i, ocfg.pc, ocfg.dc, ocfg.pe, ocfg.tx_pu);

drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c

64

g94_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu)

drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c

77

nvkm_wr32(device, 0x61c118 + loff, data[0] | (dc << shift));

drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c

129

gf119_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c

142

nvkm_wr32(device, 0x61c118 + loff, data[0] | (dc << shift));

drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c

34

gm200_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu)

drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c

49

nvkm_wr32(device, 0x61c118 + loff, data[0] | (dc << shift));

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h

86

int dc, int pe, int tx_pu);

drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c

181

info->dc = nvbios_rd08(bios, data + 0x02);

drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c

189

info->dc = nvbios_rd08(bios, data + 0x01);

drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c

194

info->dc = nvbios_rd08(bios, data + 0x00);

drivers/gpu/drm/panel/panel-ilitek-ili9341.c

484

static int ili9341_dpi_probe(struct spi_device *spi, struct gpio_desc *dc,

drivers/gpu/drm/panel/panel-ilitek-ili9341.c

512

ret = mipi_dbi_spi_init(spi, ili->dbi, dc);

drivers/gpu/drm/panel/panel-ilitek-ili9341.c

537

struct gpio_desc *dc;

drivers/gpu/drm/panel/panel-ilitek-ili9341.c

544

dc = devm_gpiod_get_optional(dev, "dc", GPIOD_OUT_LOW);

drivers/gpu/drm/panel/panel-ilitek-ili9341.c

545

if (IS_ERR(dc))

drivers/gpu/drm/panel/panel-ilitek-ili9341.c

546

return dev_err_probe(dev, PTR_ERR(dc), "Failed to get gpio 'dc'\n");

drivers/gpu/drm/panel/panel-ilitek-ili9341.c

548

return ili9341_dpi_probe(spi, dc, reset);

drivers/gpu/drm/panel/panel-sitronix-st7701.c

1359

struct gpio_desc *dc;

drivers/gpu/drm/panel/panel-sitronix-st7701.c

1369

dc = devm_gpiod_get_optional(&spi->dev, "dc", GPIOD_OUT_LOW);

drivers/gpu/drm/panel/panel-sitronix-st7701.c

1370

if (IS_ERR(dc))

drivers/gpu/drm/panel/panel-sitronix-st7701.c

1371

return dev_err_probe(&spi->dev, PTR_ERR(dc), "Failed to get GPIO for D/CX\n");

drivers/gpu/drm/panel/panel-sitronix-st7701.c

1373

err = mipi_dbi_spi_init(spi, &st7701->dbi, dc);

drivers/gpu/drm/sitronix/st7735r.c

243

struct gpio_desc *dc;

drivers/gpu/drm/sitronix/st7735r.c

269

dc = devm_gpiod_get(dev, "dc", GPIOD_OUT_LOW);

drivers/gpu/drm/sitronix/st7735r.c

270

if (IS_ERR(dc))

drivers/gpu/drm/sitronix/st7735r.c

271

return dev_err_probe(dev, PTR_ERR(dc), "Failed to get GPIO 'dc'\n");

drivers/gpu/drm/sitronix/st7735r.c

279

ret = mipi_dbi_spi_init(spi, dbi, dc);

drivers/gpu/drm/solomon/ssd130x-spi.c

18

struct gpio_desc *dc;

drivers/gpu/drm/solomon/ssd130x-spi.c

38

gpiod_set_value_cansleep(t->dc, 0);

drivers/gpu/drm/solomon/ssd130x-spi.c

41

gpiod_set_value_cansleep(t->dc, 1);

drivers/gpu/drm/solomon/ssd130x-spi.c

67

struct gpio_desc *dc;

drivers/gpu/drm/solomon/ssd130x-spi.c

70

dc = devm_gpiod_get(dev, "dc", GPIOD_OUT_LOW);

drivers/gpu/drm/solomon/ssd130x-spi.c

71

if (IS_ERR(dc))

drivers/gpu/drm/solomon/ssd130x-spi.c

72

return dev_err_probe(dev, PTR_ERR(dc),

drivers/gpu/drm/solomon/ssd130x-spi.c

80

t->dc = dc;

drivers/gpu/drm/tegra/dc.c

1007

struct tegra_dc *dc = to_tegra_dc(new_state->crtc);

drivers/gpu/drm/tegra/dc.c

1010

u64 dma_mask = *dc->dev->dma_mask;

drivers/gpu/drm/tegra/dc.c

1023

if (!dc->soc->has_nvdisplay)

drivers/gpu/drm/tegra/dc.c

1050

tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);

drivers/gpu/drm/tegra/dc.c

1054

tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);

drivers/gpu/drm/tegra/dc.c

1058

value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);

drivers/gpu/drm/tegra/dc.c

1060

tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);

drivers/gpu/drm/tegra/dc.c

1062

value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);

drivers/gpu/drm/tegra/dc.c

1066

if (dc->soc->has_nvdisplay)

drivers/gpu/drm/tegra/dc.c

1074

tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);

drivers/gpu/drm/tegra/dc.c

1077

if (dc->soc->has_nvdisplay) {

drivers/gpu/drm/tegra/dc.c

1086

tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR);

drivers/gpu/drm/tegra/dc.c

1090

tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR);

drivers/gpu/drm/tegra/dc.c

1098

tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);

drivers/gpu/drm/tegra/dc.c

1114

struct tegra_dc *dc;

drivers/gpu/drm/tegra/dc.c

1121

dc = to_tegra_dc(old_state->crtc);

drivers/gpu/drm/tegra/dc.c

1123

value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);

drivers/gpu/drm/tegra/dc.c

1125

tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);

drivers/gpu/drm/tegra/dc.c

1170

struct tegra_dc *dc = to_tegra_dc(new_state->crtc);

drivers/gpu/drm/tegra/dc.c

1184

tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);

drivers/gpu/drm/tegra/dc.c

1185

(void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);

drivers/gpu/drm/tegra/dc.c

1188

tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);

drivers/gpu/drm/tegra/dc.c

1189

(void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);

drivers/gpu/drm/tegra/dc.c

1209

struct tegra_dc *dc)

drivers/gpu/drm/tegra/dc.c

1229

plane->dc = dc;

drivers/gpu/drm/tegra/dc.c

1231

if (!dc->soc->has_nvdisplay) {

drivers/gpu/drm/tegra/dc.c

1354

struct tegra_dc *dc,

drivers/gpu/drm/tegra/dc.c

1371

plane->dc = dc;

drivers/gpu/drm/tegra/dc.c

1373

num_formats = dc->soc->num_overlay_formats;

drivers/gpu/drm/tegra/dc.c

1374

formats = dc->soc->overlay_formats;

drivers/gpu/drm/tegra/dc.c

1406

dev_err(dc->dev, "failed to create rotation property: %d\n",

drivers/gpu/drm/tegra/dc.c

1413

struct tegra_dc *dc)

drivers/gpu/drm/tegra/dc.c

1418

for (i = 0; i < dc->soc->num_wgrps; i++) {

drivers/gpu/drm/tegra/dc.c

1419

const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];

drivers/gpu/drm/tegra/dc.c

1421

if (wgrp->dc == dc->pipe) {

drivers/gpu/drm/tegra/dc.c

1431

plane = tegra_shared_plane_create(drm, dc,

drivers/gpu/drm/tegra/dc.c

1451

struct tegra_dc *dc)

drivers/gpu/drm/tegra/dc.c

1458

primary = tegra_primary_plane_create(drm, dc);

drivers/gpu/drm/tegra/dc.c

1462

if (dc->soc->supports_cursor)

drivers/gpu/drm/tegra/dc.c

1468

planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i,

drivers/gpu/drm/tegra/dc.c

148

static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)

drivers/gpu/drm/tegra/dc.c

152

tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);

drivers/gpu/drm/tegra/dc.c

153

value = tegra_dc_readl(dc, offset);

drivers/gpu/drm/tegra/dc.c

154

tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);

drivers/gpu/drm/tegra/dc.c

1748

struct tegra_dc *dc = node->info_ent->data;

drivers/gpu/drm/tegra/dc.c

1752

drm_modeset_lock(&dc->base.mutex, NULL);

drivers/gpu/drm/tegra/dc.c

1754

if (!dc->base.state->active) {

drivers/gpu/drm/tegra/dc.c

1763

offset, tegra_dc_readl(dc, offset));

drivers/gpu/drm/tegra/dc.c

1767

drm_modeset_unlock(&dc->base.mutex);

drivers/gpu/drm/tegra/dc.c

177

dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);

drivers/gpu/drm/tegra/dc.c

1774

struct tegra_dc *dc = node->info_ent->data;

drivers/gpu/drm/tegra/dc.c

1778

drm_modeset_lock(&dc->base.mutex, NULL);

drivers/gpu/drm/tegra/dc.c

1780

if (!dc->base.state->active) {

drivers/gpu/drm/tegra/dc.c

1786

tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);

drivers/gpu/drm/tegra/dc.c

1787

tegra_dc_commit(dc);

drivers/gpu/drm/tegra/dc.c

1789

drm_crtc_wait_one_vblank(&dc->base);

drivers/gpu/drm/tegra/dc.c

1790

drm_crtc_wait_one_vblank(&dc->base);

drivers/gpu/drm/tegra/dc.c

1792

value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);

drivers/gpu/drm/tegra/dc.c

1795

tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);

drivers/gpu/drm/tegra/dc.c

1798

drm_modeset_unlock(&dc->base.mutex);

drivers/gpu/drm/tegra/dc.c

1805

struct tegra_dc *dc = node->info_ent->data;

drivers/gpu/drm/tegra/dc.c

1807

seq_printf(s, "frames: %lu\n", dc->stats.frames);

drivers/gpu/drm/tegra/dc.c

1808

seq_printf(s, "vblank: %lu\n", dc->stats.vblank);

drivers/gpu/drm/tegra/dc.c

1809

seq_printf(s, "underflow: %lu\n", dc->stats.underflow);

drivers/gpu/drm/tegra/dc.c

1810

seq_printf(s, "overflow: %lu\n", dc->stats.overflow);

drivers/gpu/drm/tegra/dc.c

1812

seq_printf(s, "frames total: %lu\n", dc->stats.frames_total);

drivers/gpu/drm/tegra/dc.c

1813

seq_printf(s, "vblank total: %lu\n", dc->stats.vblank_total);

drivers/gpu/drm/tegra/dc.c

1814

seq_printf(s, "underflow total: %lu\n", dc->stats.underflow_total);

drivers/gpu/drm/tegra/dc.c

1815

seq_printf(s, "overflow total: %lu\n", dc->stats.overflow_total);

drivers/gpu/drm/tegra/dc.c

1831

struct tegra_dc *dc = to_tegra_dc(crtc);

drivers/gpu/drm/tegra/dc.c

1839

dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),

drivers/gpu/drm/tegra/dc.c

1841

if (!dc->debugfs_files)

drivers/gpu/drm/tegra/dc.c

1845

dc->debugfs_files[i].data = dc;

drivers/gpu/drm/tegra/dc.c

1847

drm_debugfs_create_files(dc->debugfs_files, count, root, minor);

drivers/gpu/drm/tegra/dc.c

185

return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));

drivers/gpu/drm/tegra/dc.c

1856

struct tegra_dc *dc = to_tegra_dc(crtc);

drivers/gpu/drm/tegra/dc.c

1865

drm_debugfs_remove_files(dc->debugfs_files, count, root, minor);

drivers/gpu/drm/tegra/dc.c

1866

kfree(dc->debugfs_files);

drivers/gpu/drm/tegra/dc.c

1867

dc->debugfs_files = NULL;

drivers/gpu/drm/tegra/dc.c

1872

struct tegra_dc *dc = to_tegra_dc(crtc);

drivers/gpu/drm/tegra/dc.c

1875

if (dc->syncpt && !dc->soc->has_nvdisplay)

drivers/gpu/drm/tegra/dc.c

1876

return host1x_syncpt_read(dc->syncpt);

drivers/gpu/drm/tegra/dc.c

1879

return (u32)drm_crtc_vblank_count(&dc->base);

drivers/gpu/drm/tegra/dc.c

1884

struct tegra_dc *dc = to_tegra_dc(crtc);

drivers/gpu/drm/tegra/dc.c

1887

value = tegra_dc_readl(dc, DC_CMD_INT_MASK);

drivers/gpu/drm/tegra/dc.c

1889

tegra_dc_writel(dc, value, DC_CMD_INT_MASK);

drivers/gpu/drm/tegra/dc.c

1896

struct tegra_dc *dc = to_tegra_dc(crtc);

drivers/gpu/drm/tegra/dc.c

1899

value = tegra_dc_readl(dc, DC_CMD_INT_MASK);

drivers/gpu/drm/tegra/dc.c

1901

tegra_dc_writel(dc, value, DC_CMD_INT_MASK);

drivers/gpu/drm/tegra/dc.c

191

tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));

drivers/gpu/drm/tegra/dc.c

1918

static int tegra_dc_set_timings(struct tegra_dc *dc,

drivers/gpu/drm/tegra/dc.c

1925

if (!dc->soc->has_nvdisplay) {

drivers/gpu/drm/tegra/dc.c

1926

tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);

drivers/gpu/drm/tegra/dc.c

1929

tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);

drivers/gpu/drm/tegra/dc.c

1934

tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);

drivers/gpu/drm/tegra/dc.c

1938

tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);

drivers/gpu/drm/tegra/dc.c

194

bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev)

drivers/gpu/drm/tegra/dc.c

1942

tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);

drivers/gpu/drm/tegra/dc.c

1945

tegra_dc_writel(dc, value, DC_DISP_ACTIVE);

drivers/gpu/drm/tegra/dc.c

196

struct device_node *np = dc->dev->of_node;

drivers/gpu/drm/tegra/dc.c

1962

int tegra_dc_state_setup_clock(struct tegra_dc *dc,

drivers/gpu/drm/tegra/dc.c

1969

if (!clk_has_parent(dc->clk, clk))

drivers/gpu/drm/tegra/dc.c

1979

static void tegra_dc_update_voltage_state(struct tegra_dc *dc,

drivers/gpu/drm/tegra/dc.c

1986

if (!dc->has_opp_table)

drivers/gpu/drm/tegra/dc.c

1990

rate = DIV_ROUND_UP(clk_get_rate(dc->clk) * 2, state->div + 2);

drivers/gpu/drm/tegra/dc.c

1993

opp = dev_pm_opp_find_freq_ceil(dc->dev, &rate);

drivers/gpu/drm/tegra/dc.c

2001

opp = dev_pm_opp_find_freq_floor(dc->dev, &rate);

drivers/gpu/drm/tegra/dc.c

2004

dev_err(dc->dev, "failed to find OPP for %luHz: %pe\n",

drivers/gpu/drm/tegra/dc.c

2019

err = dev_pm_genpd_set_performance_state(dc->dev, pstate);

drivers/gpu/drm/tegra/dc.c

2021

dev_err(dc->dev, "failed to set power domain state to %lu: %d\n",

drivers/gpu/drm/tegra/dc.c

2025

static void tegra_dc_set_clock_rate(struct tegra_dc *dc,

drivers/gpu/drm/tegra/dc.c

2030

err = clk_set_parent(dc->clk, state->clk);

drivers/gpu/drm/tegra/dc.c

2032

dev_err(dc->dev, "failed to set parent clock: %d\n", err);

drivers/gpu/drm/tegra/dc.c

2045

dev_err(dc->dev,

drivers/gpu/drm/tegra/dc.c

2049

err = clk_set_rate(dc->clk, state->pclk);

drivers/gpu/drm/tegra/dc.c

2051

dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",

drivers/gpu/drm/tegra/dc.c

2052

dc->clk, state->pclk, err);

drivers/gpu/drm/tegra/dc.c

2055

DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),

drivers/gpu/drm/tegra/dc.c

2059

tegra_dc_update_voltage_state(dc, state);

drivers/gpu/drm/tegra/dc.c

2062

static void tegra_dc_stop(struct tegra_dc *dc)

drivers/gpu/drm/tegra/dc.c

2067

value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);

drivers/gpu/drm/tegra/dc.c

2069

tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);

drivers/gpu/drm/tegra/dc.c

2071

tegra_dc_commit(dc);

drivers/gpu/drm/tegra/dc.c

2074

static bool tegra_dc_idle(struct tegra_dc *dc)

drivers/gpu/drm/tegra/dc.c

2078

value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);

drivers/gpu/drm/tegra/dc.c

2083

static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)

drivers/gpu/drm/tegra/dc.c

2088

if (tegra_dc_idle(dc))

drivers/gpu/drm/tegra/dc.c

2094

dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");

drivers/gpu/drm/tegra/dc.c

2108

struct tegra_dc *dc = to_tegra_dc(crtc);

drivers/gpu/drm/tegra/dc.c

2112

if (dc->soc->has_nvdisplay)

drivers/gpu/drm/tegra/dc.c

2147

if (tegra->dc != dc)

drivers/gpu/drm/tegra/dc.c

2198

struct tegra_dc *dc = to_tegra_dc(crtc);

drivers/gpu/drm/tegra/dc.c

2202

if (!tegra_dc_idle(dc)) {

drivers/gpu/drm/tegra/dc.c

2203

tegra_dc_stop(dc);

drivers/gpu/drm/tegra/dc.c

2209

tegra_dc_wait_idle(dc, 100);

drivers/gpu/drm/tegra/dc.c

221

void tegra_dc_commit(struct tegra_dc *dc)

drivers/gpu/drm/tegra/dc.c

2228

if (dc->rgb) {

drivers/gpu/drm/tegra/dc.c

2229

value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);

drivers/gpu/drm/tegra/dc.c

223

tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);

drivers/gpu/drm/tegra/dc.c

2232

tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);

drivers/gpu/drm/tegra/dc.c

2235

tegra_dc_stats_reset(&dc->stats);

drivers/gpu/drm/tegra/dc.c

224

tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);

drivers/gpu/drm/tegra/dc.c

2247

err = host1x_client_suspend(&dc->client);

drivers/gpu/drm/tegra/dc.c

2249

dev_err(dc->dev, "failed to suspend: %d\n", err);

drivers/gpu/drm/tegra/dc.c

2251

if (dc->has_opp_table) {

drivers/gpu/drm/tegra/dc.c

2252

err = dev_pm_genpd_set_performance_state(dc->dev, 0);

drivers/gpu/drm/tegra/dc.c

2254

dev_err(dc->dev,

drivers/gpu/drm/tegra/dc.c

2264

struct tegra_dc *dc = to_tegra_dc(crtc);

drivers/gpu/drm/tegra/dc.c

2269

tegra_dc_set_clock_rate(dc, crtc_state);

drivers/gpu/drm/tegra/dc.c

2271

err = host1x_client_resume(&dc->client);

drivers/gpu/drm/tegra/dc.c

2273

dev_err(dc->dev, "failed to resume: %d\n", err);

drivers/gpu/drm/tegra/dc.c

2278

if (dc->syncpt) {

drivers/gpu/drm/tegra/dc.c

2279

u32 syncpt = host1x_syncpt_id(dc->syncpt), enable;

drivers/gpu/drm/tegra/dc.c

2281

if (dc->soc->has_nvdisplay)

drivers/gpu/drm/tegra/dc.c

2287

tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);

drivers/gpu/drm/tegra/dc.c

2290

tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);

drivers/gpu/drm/tegra/dc.c

2293

if (dc->soc->has_nvdisplay) {

drivers/gpu/drm/tegra/dc.c

2296

tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);

drivers/gpu/drm/tegra/dc.c

2303

tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);

drivers/gpu/drm/tegra/dc.c

2307

tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);

drivers/gpu/drm/tegra/dc.c

2310

tegra_dc_writel(dc, value, DC_CMD_INT_MASK);

drivers/gpu/drm/tegra/dc.c

2312

tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);

drivers/gpu/drm/tegra/dc.c

2316

tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);

drivers/gpu/drm/tegra/dc.c

2320

tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);

drivers/gpu/drm/tegra/dc.c

2325

tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);

drivers/gpu/drm/tegra/dc.c

2329

tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);

drivers/gpu/drm/tegra/dc.c

2333

tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);

drivers/gpu/drm/tegra/dc.c

2337

tegra_dc_writel(dc, value, DC_CMD_INT_MASK);

drivers/gpu/drm/tegra/dc.c

2340

if (dc->soc->supports_background_color)

drivers/gpu/drm/tegra/dc.c

2341

tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);

drivers/gpu/drm/tegra/dc.c

2343

tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);

drivers/gpu/drm/tegra/dc.c

2346

if (!dc->soc->has_nvdisplay) {

drivers/gpu/drm/tegra/dc.c

2348

tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);

drivers/gpu/drm/tegra/dc.c

2352

tegra_dc_set_timings(dc, mode);

drivers/gpu/drm/tegra/dc.c

2355

if (dc->soc->supports_interlacing) {

drivers/gpu/drm/tegra/dc.c

2356

value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);

drivers/gpu/drm/tegra/dc.c

2358

tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);

drivers/gpu/drm/tegra/dc.c

2361

value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);

drivers/gpu/drm/tegra/dc.c

2364

tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);

drivers/gpu/drm/tegra/dc.c

2366

if (!dc->soc->has_nvdisplay) {

drivers/gpu/drm/tegra/dc.c

2367

value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);

drivers/gpu/drm/tegra/dc.c

2370

tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);

drivers/gpu/drm/tegra/dc.c

2374

if (dc->soc->has_nvdisplay) {

drivers/gpu/drm/tegra/dc.c

2376

tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);

drivers/gpu/drm/tegra/dc.c

2379

if (dc->rgb) {

drivers/gpu/drm/tegra/dc.c

2382

tegra_dc_writel(dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);

drivers/gpu/drm/tegra/dc.c

2385

tegra_dc_commit(dc);

drivers/gpu/drm/tegra/dc.c

2417

struct tegra_dc *dc = to_tegra_dc(crtc);

drivers/gpu/drm/tegra/dc.c

2421

tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);

drivers/gpu/drm/tegra/dc.c

2422

value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);

drivers/gpu/drm/tegra/dc.c

2425

tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);

drivers/gpu/drm/tegra/dc.c

2426

value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);

drivers/gpu/drm/tegra/dc.c

2499

struct tegra_dc *dc = to_tegra_dc(crtc);

drivers/gpu/drm/tegra/dc.c

2510

if (dc->soc->has_nvdisplay)

drivers/gpu/drm/tegra/dc.c

2636

struct tegra_dc *dc = data;

drivers/gpu/drm/tegra/dc.c

2639

status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);

drivers/gpu/drm/tegra/dc.c

2640

tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);

drivers/gpu/drm/tegra/dc.c

2646

dc->stats.frames_total++;

drivers/gpu/drm/tegra/dc.c

2647

dc->stats.frames++;

drivers/gpu/drm/tegra/dc.c

2654

drm_crtc_handle_vblank(&dc->base);

drivers/gpu/drm/tegra/dc.c

2655

dc->stats.vblank_total++;

drivers/gpu/drm/tegra/dc.c

2656

dc->stats.vblank++;

drivers/gpu/drm/tegra/dc.c

2663

dc->stats.underflow_total++;

drivers/gpu/drm/tegra/dc.c

2664

dc->stats.underflow++;

drivers/gpu/drm/tegra/dc.c

2671

dc->stats.overflow_total++;

drivers/gpu/drm/tegra/dc.c

2672

dc->stats.overflow++;

drivers/gpu/drm/tegra/dc.c

2676

dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__);

drivers/gpu/drm/tegra/dc.c

2677

dc->stats.underflow_total++;

drivers/gpu/drm/tegra/dc.c

2678

dc->stats.underflow++;

drivers/gpu/drm/tegra/dc.c

2684

static bool tegra_dc_has_window_groups(struct tegra_dc *dc)

drivers/gpu/drm/tegra/dc.c

2688

if (!dc->soc->wgrps)

drivers/gpu/drm/tegra/dc.c

2691

for (i = 0; i < dc->soc->num_wgrps; i++) {

drivers/gpu/drm/tegra/dc.c

2692

const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];

drivers/gpu/drm/tegra/dc.c

2694

if (wgrp->dc == dc->pipe && wgrp->num_windows > 0)

drivers/gpu/drm/tegra/dc.c

2715

struct tegra_dc *dc = host1x_client_to_dc(client);

drivers/gpu/drm/tegra/dc.c

2725

host1x_syncpt_release_vblank_reservation(client, 26 + dc->pipe);

drivers/gpu/drm/tegra/dc.c

2732

if (!tegra_dc_has_window_groups(dc))

drivers/gpu/drm/tegra/dc.c

2741

if (dc->soc->has_nvdisplay)

drivers/gpu/drm/tegra/dc.c

2744

dc->syncpt = host1x_syncpt_request(client, flags);

drivers/gpu/drm/tegra/dc.c

2745

if (!dc->syncpt)

drivers/gpu/drm/tegra/dc.c

2746

dev_warn(dc->dev, "failed to allocate syncpoint\n");

drivers/gpu/drm/tegra/dc.c

2754

if (dc->soc->wgrps)

drivers/gpu/drm/tegra/dc.c

2755

primary = tegra_dc_add_shared_planes(drm, dc);

drivers/gpu/drm/tegra/dc.c

2757

primary = tegra_dc_add_planes(drm, dc);

drivers/gpu/drm/tegra/dc.c

2764

if (dc->soc->supports_cursor) {

drivers/gpu/drm/tegra/dc.c

2765

cursor = tegra_dc_cursor_plane_create(drm, dc);

drivers/gpu/drm/tegra/dc.c

2772

cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true);

drivers/gpu/drm/tegra/dc.c

2779

err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,

drivers/gpu/drm/tegra/dc.c

2784

drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);

drivers/gpu/drm/tegra/dc.c

2790

if (dc->soc->pitch_align > tegra->pitch_align)

drivers/gpu/drm/tegra/dc.c

2791

tegra->pitch_align = dc->soc->pitch_align;

drivers/gpu/drm/tegra/dc.c

2794

if (dc->soc->has_nvdisplay)

drivers/gpu/drm/tegra/dc.c

2799

err = tegra_dc_rgb_init(drm, dc);

drivers/gpu/drm/tegra/dc.c

2801

dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);

drivers/gpu/drm/tegra/dc.c

2805

err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,

drivers/gpu/drm/tegra/dc.c

2806

dev_name(dc->dev), dc);

drivers/gpu/drm/tegra/dc.c

2808

dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,

drivers/gpu/drm/tegra/dc.c

2829

host1x_syncpt_put(dc->syncpt);

drivers/gpu/drm/tegra/dc.c

2836

struct tegra_dc *dc = host1x_client_to_dc(client);

drivers/gpu/drm/tegra/dc.c

2839

if (!tegra_dc_has_window_groups(dc))

drivers/gpu/drm/tegra/dc.c

2845

devm_free_irq(dc->dev, dc->irq, dc);

drivers/gpu/drm/tegra/dc.c

2847

err = tegra_dc_rgb_exit(dc);

drivers/gpu/drm/tegra/dc.c

2849

dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);

drivers/gpu/drm/tegra/dc.c

2854

host1x_syncpt_put(dc->syncpt);

drivers/gpu/drm/tegra/dc.c

2871

struct tegra_dc *dc = host1x_client_to_dc(client);

drivers/gpu/drm/tegra/dc.c

2875

err = reset_control_assert(dc->rst);

drivers/gpu/drm/tegra/dc.c

2881

if (dc->soc->has_powergate)

drivers/gpu/drm/tegra/dc.c

2882

tegra_pmc_powergate_power_off(dc->pmc, dc->powergate);

drivers/gpu/drm/tegra/dc.c

2884

clk_disable_unprepare(dc->clk);

drivers/gpu/drm/tegra/dc.c

2892

struct tegra_dc *dc = host1x_client_to_dc(client);

drivers/gpu/drm/tegra/dc.c

2902

if (dc->soc->has_powergate) {

drivers/gpu/drm/tegra/dc.c

2903

err = tegra_pmc_powergate_sequence_power_up(dc->pmc,

drivers/gpu/drm/tegra/dc.c

2904

dc->powergate,

drivers/gpu/drm/tegra/dc.c

2905

dc->clk, dc->rst);

drivers/gpu/drm/tegra/dc.c

2911

err = clk_prepare_enable(dc->clk);

drivers/gpu/drm/tegra/dc.c

2917

err = reset_control_deassert(dc->rst);

drivers/gpu/drm/tegra/dc.c

2927

clk_disable_unprepare(dc->clk);

drivers/gpu/drm/tegra/dc.c

3060

.dc = 0,

drivers/gpu/drm/tegra/dc.c

3065

.dc = 1,

drivers/gpu/drm/tegra/dc.c

3070

.dc = 1,

drivers/gpu/drm/tegra/dc.c

3075

.dc = 2,

drivers/gpu/drm/tegra/dc.c

3080

.dc = 2,

drivers/gpu/drm/tegra/dc.c

3085

.dc = 2,

drivers/gpu/drm/tegra/dc.c

3111

.dc = 0,

drivers/gpu/drm/tegra/dc.c

3116

.dc = 1,

drivers/gpu/drm/tegra/dc.c

3121

.dc = 1,

drivers/gpu/drm/tegra/dc.c

3126

.dc = 2,

drivers/gpu/drm/tegra/dc.c

3131

.dc = 2,

drivers/gpu/drm/tegra/dc.c

3136

.dc = 2,

drivers/gpu/drm/tegra/dc.c

3187

static int tegra_dc_parse_dt(struct tegra_dc *dc)

drivers/gpu/drm/tegra/dc.c

3193

err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);

drivers/gpu/drm/tegra/dc.c

3195

dev_err(dc->dev, "missing \"nvidia,head\" property\n");

drivers/gpu/drm/tegra/dc.c

3210

if (np == dc->dev->of_node) {

drivers/gpu/drm/tegra/dc.c

3219

dc->pipe = value;

drivers/gpu/drm/tegra/dc.c

3226

struct tegra_dc *dc = dev_get_drvdata(dev);

drivers/gpu/drm/tegra/dc.c

3229

return dc->pipe == pipe;

drivers/gpu/drm/tegra/dc.c

3232

static int tegra_dc_couple(struct tegra_dc *dc)

drivers/gpu/drm/tegra/dc.c

3239

if (dc->soc->coupled_pm && dc->pipe == 1) {

drivers/gpu/drm/tegra/dc.c

3243

companion = driver_find_device(dc->dev->driver, NULL, (const void *)0,

drivers/gpu/drm/tegra/dc.c

3249

dc->client.parent = &parent->client;

drivers/gpu/drm/tegra/dc.c

3251

dev_dbg(dc->dev, "coupled to %s\n", dev_name(companion));

drivers/gpu/drm/tegra/dc.c

3258

static int tegra_dc_init_opp_table(struct tegra_dc *dc)

drivers/gpu/drm/tegra/dc.c

3263

err = devm_tegra_core_dev_init_opp_table(dc->dev, &opp_params);

drivers/gpu/drm/tegra/dc.c

3268

dc->has_opp_table = false;

drivers/gpu/drm/tegra/dc.c

3270

dc->has_opp_table = true;

drivers/gpu/drm/tegra/dc.c

3278

struct tegra_dc *dc;

drivers/gpu/drm/tegra/dc.c

3287

dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);

drivers/gpu/drm/tegra/dc.c

3288

if (!dc)

drivers/gpu/drm/tegra/dc.c

3291

dc->soc = of_device_get_match_data(&pdev->dev);

drivers/gpu/drm/tegra/dc.c

3293

INIT_LIST_HEAD(&dc->list);

drivers/gpu/drm/tegra/dc.c

3294

dc->dev = &pdev->dev;

drivers/gpu/drm/tegra/dc.c

3296

err = tegra_dc_parse_dt(dc);

drivers/gpu/drm/tegra/dc.c

3300

err = tegra_dc_couple(dc);

drivers/gpu/drm/tegra/dc.c

3304

dc->clk = devm_clk_get(&pdev->dev, NULL);

drivers/gpu/drm/tegra/dc.c

3305

if (IS_ERR(dc->clk)) {

drivers/gpu/drm/tegra/dc.c

3307

return PTR_ERR(dc->clk);

drivers/gpu/drm/tegra/dc.c

3310

dc->rst = devm_reset_control_get(&pdev->dev, "dc");

drivers/gpu/drm/tegra/dc.c

3311

if (IS_ERR(dc->rst)) {

drivers/gpu/drm/tegra/dc.c

3313

return PTR_ERR(dc->rst);

drivers/gpu/drm/tegra/dc.c

3317

err = clk_prepare_enable(dc->clk);

drivers/gpu/drm/tegra/dc.c

3323

err = reset_control_assert(dc->rst);

drivers/gpu/drm/tegra/dc.c

3325

clk_disable_unprepare(dc->clk);

drivers/gpu/drm/tegra/dc.c

3331

clk_disable_unprepare(dc->clk);

drivers/gpu/drm/tegra/dc.c

3333

if (dc->soc->has_powergate) {

drivers/gpu/drm/tegra/dc.c

3334

dc->pmc = devm_tegra_pmc_get(dc->dev);

drivers/gpu/drm/tegra/dc.c

3335

if (IS_ERR(dc->pmc))

drivers/gpu/drm/tegra/dc.c

3336

return dev_err_probe(dc->dev, PTR_ERR(dc->pmc),

drivers/gpu/drm/tegra/dc.c

3339

if (dc->pipe == 0)

drivers/gpu/drm/tegra/dc.c

3340

dc->powergate = TEGRA_POWERGATE_DIS;

drivers/gpu/drm/tegra/dc.c

3342

dc->powergate = TEGRA_POWERGATE_DISB;

drivers/gpu/drm/tegra/dc.c

3344

tegra_pmc_powergate_power_off(dc->pmc, dc->powergate);

drivers/gpu/drm/tegra/dc.c

3347

err = tegra_dc_init_opp_table(dc);

drivers/gpu/drm/tegra/dc.c

3351

dc->regs = devm_platform_ioremap_resource(pdev, 0);

drivers/gpu/drm/tegra/dc.c

3352

if (IS_ERR(dc->regs))

drivers/gpu/drm/tegra/dc.c

3353

return PTR_ERR(dc->regs);

drivers/gpu/drm/tegra/dc.c

3355

dc->irq = platform_get_irq(pdev, 0);

drivers/gpu/drm/tegra/dc.c

3356

if (dc->irq < 0)

drivers/gpu/drm/tegra/dc.c

3359

if (dc->soc->has_nvdisplay) {

drivers/gpu/drm/tegra/dc.c

3363

dc->cmu_output_lut =

drivers/gpu/drm/tegra/dc.c

3364

dmam_alloc_coherent(dc->dev, ARRAY_SIZE(default_srgb_lut) * sizeof(u64),

drivers/gpu/drm/tegra/dc.c

3365

&dc->cmu_output_lut_phys, GFP_KERNEL);

drivers/gpu/drm/tegra/dc.c

3367

if (!dc->cmu_output_lut) {

drivers/gpu/drm/tegra/dc.c

3368

dev_err(dc->dev, "failed to allocate lut for cmu\n");

drivers/gpu/drm/tegra/dc.c

3374

dc->cmu_output_lut[i] = (r << 32) | (r << 16) | r;

drivers/gpu/drm/tegra/dc.c

3378

err = tegra_dc_rgb_probe(dc);

drivers/gpu/drm/tegra/dc.c

3383

platform_set_drvdata(pdev, dc);

drivers/gpu/drm/tegra/dc.c

3386

INIT_LIST_HEAD(&dc->client.list);

drivers/gpu/drm/tegra/dc.c

3387

dc->client.ops = &dc_client_ops;

drivers/gpu/drm/tegra/dc.c

3388

dc->client.dev = &pdev->dev;

drivers/gpu/drm/tegra/dc.c

3390

err = host1x_client_register(&dc->client);

drivers/gpu/drm/tegra/dc.c

3401

tegra_dc_rgb_remove(dc);

drivers/gpu/drm/tegra/dc.c

3408

struct tegra_dc *dc = platform_get_drvdata(pdev);

drivers/gpu/drm/tegra/dc.c

3410

host1x_client_unregister(&dc->client);

drivers/gpu/drm/tegra/dc.c

3412

tegra_dc_rgb_remove(dc);

drivers/gpu/drm/tegra/dc.c

417

struct tegra_dc *dc = plane->dc;

drivers/gpu/drm/tegra/dc.c

422

if (plane->index == 0 && dc->soc->has_win_a_without_filters)

drivers/gpu/drm/tegra/dc.c

432

struct tegra_dc *dc = plane->dc;

drivers/gpu/drm/tegra/dc.c

437

if (plane->index == 0 && dc->soc->has_win_a_without_filters)

drivers/gpu/drm/tegra/dc.c

440

if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter)

drivers/gpu/drm/tegra/dc.c

450

struct tegra_dc *dc = plane->dc;

drivers/gpu/drm/tegra/dc.c

527

if (dc->soc->supports_block_linear) {

drivers/gpu/drm/tegra/dc.c

633

if (dc->soc->has_legacy_blending)

drivers/gpu/drm/tegra/dc.c

729

struct tegra_dc *dc = to_tegra_dc(new_plane_state->crtc);

drivers/gpu/drm/tegra/dc.c

753

if (dc->soc->has_legacy_blending) {

drivers/gpu/drm/tegra/dc.c

764

!dc->soc->supports_block_linear) {

drivers/gpu/drm/tegra/dc.c

904

struct tegra_dc *dc)

drivers/gpu/drm/tegra/dc.c

921

plane->dc = dc;

drivers/gpu/drm/tegra/dc.c

923

num_formats = dc->soc->num_primary_formats;

drivers/gpu/drm/tegra/dc.c

924

formats = dc->soc->primary_formats;

drivers/gpu/drm/tegra/dc.c

925

modifiers = dc->soc->modifiers;

drivers/gpu/drm/tegra/dc.c

951

dev_err(dc->dev, "failed to create rotation property: %d\n",

drivers/gpu/drm/tegra/dc.h

123

static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value,

drivers/gpu/drm/tegra/dc.h

126

trace_dc_writel(dc->dev, offset, value);

drivers/gpu/drm/tegra/dc.h

127

writel(value, dc->regs + (offset << 2));

drivers/gpu/drm/tegra/dc.h

130

static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned int offset)

drivers/gpu/drm/tegra/dc.h

132

u32 value = readl(dc->regs + (offset << 2));

drivers/gpu/drm/tegra/dc.h

134

trace_dc_readl(dc->dev, offset, value);

drivers/gpu/drm/tegra/dc.h

165

bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev);

drivers/gpu/drm/tegra/dc.h

166

void tegra_dc_commit(struct tegra_dc *dc);

drivers/gpu/drm/tegra/dc.h

167

int tegra_dc_state_setup_clock(struct tegra_dc *dc,

drivers/gpu/drm/tegra/dc.h

175

int tegra_dc_rgb_probe(struct tegra_dc *dc);

drivers/gpu/drm/tegra/dc.h

176

void tegra_dc_rgb_remove(struct tegra_dc *dc);

drivers/gpu/drm/tegra/dc.h

177

int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc);

drivers/gpu/drm/tegra/dc.h

178

int tegra_dc_rgb_exit(struct tegra_dc *dc);

drivers/gpu/drm/tegra/dc.h

52

unsigned int dc;

drivers/gpu/drm/tegra/dsi.c

1025

err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent,

drivers/gpu/drm/tegra/dsi.c

848

struct tegra_dc *dc = to_tegra_dc(encoder->crtc);

drivers/gpu/drm/tegra/dsi.c

862

if (dc) {

drivers/gpu/drm/tegra/dsi.c

863

value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);

drivers/gpu/drm/tegra/dsi.c

865

tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);

drivers/gpu/drm/tegra/dsi.c

867

tegra_dc_commit(dc);

drivers/gpu/drm/tegra/dsi.c

913

struct tegra_dc *dc = to_tegra_dc(encoder->crtc);

drivers/gpu/drm/tegra/dsi.c

938

tegra_dsi_configure(dsi, dc->pipe, mode);

drivers/gpu/drm/tegra/dsi.c

941

value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);

drivers/gpu/drm/tegra/dsi.c

943

tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);

drivers/gpu/drm/tegra/dsi.c

945

tegra_dc_commit(dc);

drivers/gpu/drm/tegra/dsi.c

961

struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);

drivers/gpu/drm/tegra/hdmi.c

1172

struct tegra_dc *dc = to_tegra_dc(encoder->crtc);

drivers/gpu/drm/tegra/hdmi.c

1183

if (dc) {

drivers/gpu/drm/tegra/hdmi.c

1184

value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);

drivers/gpu/drm/tegra/hdmi.c

1186

tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);

drivers/gpu/drm/tegra/hdmi.c

1188

tegra_dc_commit(dc);

drivers/gpu/drm/tegra/hdmi.c

1217

struct tegra_dc *dc = to_tegra_dc(encoder->crtc);

drivers/gpu/drm/tegra/hdmi.c

1264

tegra_dc_writel(dc, VSYNC_H_POSITION(1),

drivers/gpu/drm/tegra/hdmi.c

1266

tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,

drivers/gpu/drm/tegra/hdmi.c

1272

tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);

drivers/gpu/drm/tegra/hdmi.c

1276

tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);

drivers/gpu/drm/tegra/hdmi.c

1279

tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);

drivers/gpu/drm/tegra/hdmi.c

1285

if (dc->pipe)

drivers/gpu/drm/tegra/hdmi.c

1421

value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);

drivers/gpu/drm/tegra/hdmi.c

1423

tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);

drivers/gpu/drm/tegra/hdmi.c

1425

tegra_dc_commit(dc);

drivers/gpu/drm/tegra/hdmi.c

1447

struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);

drivers/gpu/drm/tegra/hdmi.c

1452

err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent,

drivers/gpu/drm/tegra/hub.c

105

return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));

drivers/gpu/drm/tegra/hub.c

111

tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));

drivers/gpu/drm/tegra/hub.c

197

struct tegra_dc *dc = plane->dc;

drivers/gpu/drm/tegra/hub.c

202

tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL);

drivers/gpu/drm/tegra/hub.c

207

value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);

drivers/gpu/drm/tegra/hub.c

217

struct tegra_dc *dc = plane->dc;

drivers/gpu/drm/tegra/hub.c

222

tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL);

drivers/gpu/drm/tegra/hub.c

227

value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);

drivers/gpu/drm/tegra/hub.c

236

tegra_shared_plane_get_owner(struct tegra_plane *plane, struct tegra_dc *dc)

drivers/gpu/drm/tegra/hub.c

241

return tegra_dc_readl(dc, offset) & OWNER_MASK;

drivers/gpu/drm/tegra/hub.c

244

static bool tegra_dc_owns_shared_plane(struct tegra_dc *dc,

drivers/gpu/drm/tegra/hub.c

247

struct device *dev = dc->dev;

drivers/gpu/drm/tegra/hub.c

249

if (tegra_shared_plane_get_owner(plane, dc) == dc->pipe) {

drivers/gpu/drm/tegra/hub.c

250

if (plane->dc == dc)

drivers/gpu/drm/tegra/hub.c

254

dc->pipe, plane->index);

drivers/gpu/drm/tegra/hub.c

265

struct tegra_dc *old = plane->dc, *dc = new ? new : old;

drivers/gpu/drm/tegra/hub.c

270

value = tegra_dc_readl(dc, offset);

drivers/gpu/drm/tegra/hub.c

294

tegra_dc_writel(dc, value, offset);

drivers/gpu/drm/tegra/hub.c

296

plane->dc = new;

drivers/gpu/drm/tegra/hub.c

369

static void tegra_dc_assign_shared_plane(struct tegra_dc *dc,

drivers/gpu/drm/tegra/hub.c

375

if (!tegra_dc_owns_shared_plane(dc, plane)) {

drivers/gpu/drm/tegra/hub.c

376

err = tegra_shared_plane_set_owner(plane, dc);

drivers/gpu/drm/tegra/hub.c

420

static void tegra_dc_remove_shared_plane(struct tegra_dc *dc,

drivers/gpu/drm/tegra/hub.c

434

struct tegra_dc *dc = to_tegra_dc(new_plane_state->crtc);

drivers/gpu/drm/tegra/hub.c

452

!dc->soc->supports_block_linear) {

drivers/gpu/drm/tegra/hub.c

458

!dc->soc->supports_sector_layout) {

drivers/gpu/drm/tegra/hub.c

490

struct tegra_dc *dc;

drivers/gpu/drm/tegra/hub.c

498

dc = to_tegra_dc(old_state->crtc);

drivers/gpu/drm/tegra/hub.c

500

err = host1x_client_resume(&dc->client);

drivers/gpu/drm/tegra/hub.c

502

dev_err(dc->dev, "failed to resume: %d\n", err);

drivers/gpu/drm/tegra/hub.c

511

if (WARN_ON(p->dc == NULL))

drivers/gpu/drm/tegra/hub.c

512

p->dc = dc;

drivers/gpu/drm/tegra/hub.c

518

tegra_dc_remove_shared_plane(dc, p);

drivers/gpu/drm/tegra/hub.c

520

host1x_client_suspend(&dc->client);

drivers/gpu/drm/tegra/hub.c

540

struct tegra_dc *dc = to_tegra_dc(new_state->crtc);

drivers/gpu/drm/tegra/hub.c

559

err = host1x_client_resume(&dc->client);

drivers/gpu/drm/tegra/hub.c

561

dev_err(dc->dev, "failed to resume: %d\n", err);

drivers/gpu/drm/tegra/hub.c

567

tegra_dc_assign_shared_plane(dc, p);

drivers/gpu/drm/tegra/hub.c

598

dev_err(dc->dev, "invalid minimum width: %u\n", min_width);

drivers/gpu/drm/tegra/hub.c

716

if (dc->soc->supports_block_linear) {

drivers/gpu/drm/tegra/hub.c

745

host1x_client_suspend(&dc->client);

drivers/gpu/drm/tegra/hub.c

757

struct tegra_dc *dc,

drivers/gpu/drm/tegra/hub.c

780

plane->wgrp->parent = &dc->client;

drivers/gpu/drm/tegra/hub.c

886

struct tegra_dc_state *dc = to_dc_state(new);

drivers/gpu/drm/tegra/hub.c

889

if (!hub_state->clk || dc->pclk > hub_state->rate) {

drivers/gpu/drm/tegra/hub.c

890

hub_state->dc = to_tegra_dc(dc->base.crtc);

drivers/gpu/drm/tegra/hub.c

891

hub_state->clk = hub_state->dc->clk;

drivers/gpu/drm/tegra/hub.c

892

hub_state->rate = dc->pclk;

drivers/gpu/drm/tegra/hub.c

900

static void tegra_display_hub_update(struct tegra_dc *dc)

drivers/gpu/drm/tegra/hub.c

905

err = host1x_client_resume(&dc->client);

drivers/gpu/drm/tegra/hub.c

907

dev_err(dc->dev, "failed to resume: %d\n", err);

drivers/gpu/drm/tegra/hub.c

911

value = tegra_dc_readl(dc, DC_CMD_IHUB_COMMON_MISC_CTL);

drivers/gpu/drm/tegra/hub.c

913

tegra_dc_writel(dc, value, DC_CMD_IHUB_COMMON_MISC_CTL);

drivers/gpu/drm/tegra/hub.c

915

value = tegra_dc_readl(dc, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER);

drivers/gpu/drm/tegra/hub.c

917

tegra_dc_writel(dc, value, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER);

drivers/gpu/drm/tegra/hub.c

919

tegra_dc_writel(dc, COMMON_UPDATE, DC_CMD_STATE_CONTROL);

drivers/gpu/drm/tegra/hub.c

920

tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);

drivers/gpu/drm/tegra/hub.c

921

tegra_dc_writel(dc, COMMON_ACTREQ, DC_CMD_STATE_CONTROL);

drivers/gpu/drm/tegra/hub.c

922

tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);

drivers/gpu/drm/tegra/hub.c

924

host1x_client_suspend(&dc->client);

drivers/gpu/drm/tegra/hub.c

950

if (hub_state->dc)

drivers/gpu/drm/tegra/hub.c

951

tegra_display_hub_update(hub_state->dc);

drivers/gpu/drm/tegra/hub.c

97

dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);

drivers/gpu/drm/tegra/hub.h

64

struct tegra_dc *dc;

drivers/gpu/drm/tegra/hub.h

81

struct tegra_dc *dc,

drivers/gpu/drm/tegra/output.c

254

struct tegra_dc *dc = to_tegra_dc(crtc);

drivers/gpu/drm/tegra/output.c

256

if (tegra_dc_has_output(dc, dev))

drivers/gpu/drm/tegra/plane.c

140

static int tegra_dc_pin(struct tegra_dc *dc, struct tegra_plane_state *state)

drivers/gpu/drm/tegra/plane.c

149

map = host1x_bo_pin(dc->dev, &bo->base, DMA_TO_DEVICE, &dc->client.cache);

drivers/gpu/drm/tegra/plane.c

155

if (!dc->client.group) {

drivers/gpu/drm/tegra/plane.c

178

dev_err(dc->dev, "failed to map plane %u: %d\n", i, err);

drivers/gpu/drm/tegra/plane.c

189

static void tegra_dc_unpin(struct tegra_dc *dc, struct tegra_plane_state *state)

drivers/gpu/drm/tegra/plane.c

203

struct tegra_dc *dc = to_tegra_dc(state->crtc);

drivers/gpu/drm/tegra/plane.c

213

return tegra_dc_pin(dc, to_tegra_plane_state(state));

drivers/gpu/drm/tegra/plane.c

219

struct tegra_dc *dc = to_tegra_dc(state->crtc);

drivers/gpu/drm/tegra/plane.c

221

if (dc)

drivers/gpu/drm/tegra/plane.c

222

tegra_dc_unpin(dc, to_tegra_plane_state(state));

drivers/gpu/drm/tegra/plane.c

635

if (p == tegra || p->dc != tegra->dc)

drivers/gpu/drm/tegra/plane.c

679

if (p == tegra || p->dc != tegra->dc)

drivers/gpu/drm/tegra/plane.c

730

if (p->dc != tegra->dc)

drivers/gpu/drm/tegra/plane.c

770

struct device *dev = plane->dc->dev;

drivers/gpu/drm/tegra/plane.c

771

struct tegra_dc *dc = plane->dc;

drivers/gpu/drm/tegra/plane.c

785

if (plane->index == 1 && dc->soc->has_win_b_vfilter_mem_client) {

drivers/gpu/drm/tegra/plane.c

97

struct tegra_dc *dc = to_tegra_dc(crtc);

drivers/gpu/drm/tegra/plane.c

99

if (!dc->soc->supports_sector_layout)

drivers/gpu/drm/tegra/plane.h

17

struct tegra_dc *dc;

drivers/gpu/drm/tegra/rgb.c

107

tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable));

drivers/gpu/drm/tegra/rgb.c

110

tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS);

drivers/gpu/drm/tegra/rgb.c

113

value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1));

drivers/gpu/drm/tegra/rgb.c

125

tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));

drivers/gpu/drm/tegra/rgb.c

130

tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL);

drivers/gpu/drm/tegra/rgb.c

132

tegra_dc_commit(rgb->dc);

drivers/gpu/drm/tegra/rgb.c

153

struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);

drivers/gpu/drm/tegra/rgb.c

187

err = tegra_dc_state_setup_clock(dc, crtc_state, rgb->clk_parent,

drivers/gpu/drm/tegra/rgb.c

19

struct tegra_dc *dc;

drivers/gpu/drm/tegra/rgb.c

208

int tegra_dc_rgb_probe(struct tegra_dc *dc)

drivers/gpu/drm/tegra/rgb.c

214

np = of_get_child_by_name(dc->dev->of_node, "rgb");

drivers/gpu/drm/tegra/rgb.c

218

err = devm_add_action_or_reset(dc->dev, tegra_dc_of_node_put, np);

drivers/gpu/drm/tegra/rgb.c

225

rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL);

drivers/gpu/drm/tegra/rgb.c

229

rgb->output.dev = dc->dev;

drivers/gpu/drm/tegra/rgb.c

231

rgb->dc = dc;

drivers/gpu/drm/tegra/rgb.c

237

rgb->clk = devm_clk_get(dc->dev, NULL);

drivers/gpu/drm/tegra/rgb.c

239

dev_err(dc->dev, "failed to get clock\n");

drivers/gpu/drm/tegra/rgb.c

244

rgb->clk_parent = devm_clk_get(dc->dev, "parent");

drivers/gpu/drm/tegra/rgb.c

246

dev_err(dc->dev, "failed to get parent clock\n");

drivers/gpu/drm/tegra/rgb.c

253

dev_err(dc->dev, "failed to set parent clock: %d\n", err);

drivers/gpu/drm/tegra/rgb.c

260

dev_err(dc->dev, "failed to get pll_d_out0: %d\n", err);

drivers/gpu/drm/tegra/rgb.c

264

if (dc->soc->has_pll_d2_out0) {

drivers/gpu/drm/tegra/rgb.c

268

dev_err(dc->dev, "failed to get pll_d2_out0: %d\n", err);

drivers/gpu/drm/tegra/rgb.c

273

dc->rgb = &rgb->output;

drivers/gpu/drm/tegra/rgb.c

284

void tegra_dc_rgb_remove(struct tegra_dc *dc)

drivers/gpu/drm/tegra/rgb.c

288

if (!dc->rgb)

drivers/gpu/drm/tegra/rgb.c

291

rgb = to_rgb(dc->rgb);

drivers/gpu/drm/tegra/rgb.c

295

tegra_output_remove(dc->rgb);

drivers/gpu/drm/tegra/rgb.c

296

dc->rgb = NULL;

drivers/gpu/drm/tegra/rgb.c

299

int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc)

drivers/gpu/drm/tegra/rgb.c

301

struct tegra_output *output = dc->rgb;

drivers/gpu/drm/tegra/rgb.c

305

if (!dc->rgb)

drivers/gpu/drm/tegra/rgb.c

371

output->encoder.possible_crtcs = drm_crtc_mask(&dc->base);

drivers/gpu/drm/tegra/rgb.c

376

int tegra_dc_rgb_exit(struct tegra_dc *dc)

drivers/gpu/drm/tegra/rgb.c

378

if (dc->rgb)

drivers/gpu/drm/tegra/rgb.c

379

tegra_output_exit(dc->rgb);

drivers/gpu/drm/tegra/rgb.c

81

static void tegra_dc_write_regs(struct tegra_dc *dc,

drivers/gpu/drm/tegra/rgb.c

88

tegra_dc_writel(dc, table[i].value, table[i].offset);

drivers/gpu/drm/tegra/rgb.c

96

tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));

drivers/gpu/drm/tegra/rgb.c

97

tegra_dc_commit(rgb->dc);

drivers/gpu/drm/tegra/sor.c

1293

struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);

drivers/gpu/drm/tegra/sor.c

1303

SOR_STATE_ASY_OWNER(dc->pipe + 1);

drivers/gpu/drm/tegra/sor.c

1351

tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);

drivers/gpu/drm/tegra/sor.c

1358

tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);

drivers/gpu/drm/tegra/sor.c

1365

tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);

drivers/gpu/drm/tegra/sor.c

1372

tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);

drivers/gpu/drm/tegra/sor.c

1375

tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe);

drivers/gpu/drm/tegra/sor.c

1813

struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);

drivers/gpu/drm/tegra/sor.c

1833

err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,

drivers/gpu/drm/tegra/sor.c

2212

struct tegra_dc *dc = to_tegra_dc(encoder->crtc);

drivers/gpu/drm/tegra/sor.c

2228

value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);

drivers/gpu/drm/tegra/sor.c

2235

tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);

drivers/gpu/drm/tegra/sor.c

2237

tegra_dc_commit(dc);

drivers/gpu/drm/tegra/sor.c

2254

struct tegra_dc *dc = to_tegra_dc(encoder->crtc);

drivers/gpu/drm/tegra/sor.c

2437

value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);

drivers/gpu/drm/tegra/sor.c

2452

if (!dc->soc->has_nvdisplay) {

drivers/gpu/drm/tegra/sor.c

2460

tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);

drivers/gpu/drm/tegra/sor.c

2463

tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);

drivers/gpu/drm/tegra/sor.c

2465

value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);

drivers/gpu/drm/tegra/sor.c

2467

tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);

drivers/gpu/drm/tegra/sor.c

2554

if (!dc->soc->has_nvdisplay) {

drivers/gpu/drm/tegra/sor.c

2557

tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);

drivers/gpu/drm/tegra/sor.c

2560

value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);

drivers/gpu/drm/tegra/sor.c

2563

if (dc->soc->has_nvdisplay) {

drivers/gpu/drm/tegra/sor.c

2564

tegra_dc_writel(dc, lower_32_bits(dc->cmu_output_lut_phys),

drivers/gpu/drm/tegra/sor.c

2566

tegra_dc_writel(dc, upper_32_bits(dc->cmu_output_lut_phys),

drivers/gpu/drm/tegra/sor.c

2569

tegra_dc_writel(dc, OUTPUT_LUT_MODE_INTERPOLATE | OUTPUT_LUT_SIZE_SIZE_1025,

drivers/gpu/drm/tegra/sor.c

2598

tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);

drivers/gpu/drm/tegra/sor.c

2603

value |= SOR_STATE_ASY_OWNER(1 + dc->pipe);

drivers/gpu/drm/tegra/sor.c

2611

value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);

drivers/gpu/drm/tegra/sor.c

2614

tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);

drivers/gpu/drm/tegra/sor.c

2617

value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);

drivers/gpu/drm/tegra/sor.c

2620

tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);

drivers/gpu/drm/tegra/sor.c

2636

value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);

drivers/gpu/drm/tegra/sor.c

2643

tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);

drivers/gpu/drm/tegra/sor.c

2645

if (dc->soc->has_nvdisplay) {

drivers/gpu/drm/tegra/sor.c

2646

value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));

drivers/gpu/drm/tegra/sor.c

2649

tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));

drivers/gpu/drm/tegra/sor.c

2652

tegra_dc_commit(dc);

drivers/gpu/drm/tegra/sor.c

2671

struct tegra_dc *dc = to_tegra_dc(encoder->crtc);

drivers/gpu/drm/tegra/sor.c

2697

value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);

drivers/gpu/drm/tegra/sor.c

2699

tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);

drivers/gpu/drm/tegra/sor.c

2700

tegra_dc_commit(dc);

drivers/gpu/drm/tegra/sor.c

2735

struct tegra_dc *dc = to_tegra_dc(encoder->crtc);

drivers/gpu/drm/tegra/sor.c

2938

if (dc->soc->has_nvdisplay) {

drivers/gpu/drm/tegra/sor.c

2939

value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);

drivers/gpu/drm/tegra/sor.c

2940

tegra_dc_writel(dc, lower_32_bits(dc->cmu_output_lut_phys),

drivers/gpu/drm/tegra/sor.c

2942

tegra_dc_writel(dc, upper_32_bits(dc->cmu_output_lut_phys),

drivers/gpu/drm/tegra/sor.c

2945

tegra_dc_writel(dc, OUTPUT_LUT_MODE_INTERPOLATE | OUTPUT_LUT_SIZE_SIZE_1025,

drivers/gpu/drm/tegra/sor.c

2949

tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);

drivers/gpu/drm/tegra/sor.c

2952

value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);

drivers/gpu/drm/tegra/sor.c

2954

tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);

drivers/gpu/drm/tegra/sor.c

2956

tegra_dc_commit(dc);

drivers/gpu/drm/tiny/hx8357d.c

285

struct gpio_desc *dc;

drivers/gpu/drm/tiny/hx8357d.c

299

dc = devm_gpiod_get(dev, "dc", GPIOD_OUT_LOW);

drivers/gpu/drm/tiny/hx8357d.c

300

if (IS_ERR(dc))

drivers/gpu/drm/tiny/hx8357d.c

301

return dev_err_probe(dev, PTR_ERR(dc), "Failed to get GPIO 'dc'\n");

drivers/gpu/drm/tiny/hx8357d.c

309

ret = mipi_dbi_spi_init(spi, &dbidev->dbi, dc);

drivers/gpu/drm/tiny/ili9163.c

205

struct gpio_desc *dc;

drivers/gpu/drm/tiny/ili9163.c

228

dc = devm_gpiod_get_optional(dev, "dc", GPIOD_OUT_LOW);

drivers/gpu/drm/tiny/ili9163.c

229

if (IS_ERR(dc)) {

drivers/gpu/drm/tiny/ili9163.c

231

return PTR_ERR(dc);

drivers/gpu/drm/tiny/ili9163.c

240

ret = mipi_dbi_spi_init(spi, dbi, dc);

drivers/gpu/drm/tiny/ili9225.c

113

if (!dbi->dc || !full || swap ||

drivers/gpu/drm/tiny/ili9225.c

384

gpiod_set_value_cansleep(dbi->dc, 0);

drivers/gpu/drm/tiny/ili9225.c

395

gpiod_set_value_cansleep(dbi->dc, 1);

drivers/gpu/drm/tiny/ili9341.c

242

struct gpio_desc *dc;

drivers/gpu/drm/tiny/ili9341.c

261

dc = devm_gpiod_get_optional(dev, "dc", GPIOD_OUT_LOW);

drivers/gpu/drm/tiny/ili9341.c

262

if (IS_ERR(dc))

drivers/gpu/drm/tiny/ili9341.c

263

return dev_err_probe(dev, PTR_ERR(dc), "Failed to get GPIO 'dc'\n");

drivers/gpu/drm/tiny/ili9341.c

271

ret = mipi_dbi_spi_init(spi, dbi, dc);

drivers/gpu/drm/tiny/ili9486.c

101

gpiod_set_value_cansleep(mipi->dc, 1);

drivers/gpu/drm/tiny/ili9486.c

267

struct gpio_desc *dc;

drivers/gpu/drm/tiny/ili9486.c

286

dc = devm_gpiod_get(dev, "dc", GPIOD_OUT_LOW);

drivers/gpu/drm/tiny/ili9486.c

287

if (IS_ERR(dc))

drivers/gpu/drm/tiny/ili9486.c

288

return dev_err_probe(dev, PTR_ERR(dc), "Failed to get GPIO 'dc'\n");

drivers/gpu/drm/tiny/ili9486.c

296

ret = mipi_dbi_spi_init(spi, dbi, dc);

drivers/gpu/drm/tiny/ili9486.c

79

gpiod_set_value_cansleep(mipi->dc, 0);

drivers/gpu/drm/tiny/mi0283qt.c

246

struct gpio_desc *dc;

drivers/gpu/drm/tiny/mi0283qt.c

265

dc = devm_gpiod_get_optional(dev, "dc", GPIOD_OUT_LOW);

drivers/gpu/drm/tiny/mi0283qt.c

266

if (IS_ERR(dc))

drivers/gpu/drm/tiny/mi0283qt.c

267

return dev_err_probe(dev, PTR_ERR(dc), "Failed to get GPIO 'dc'\n");

drivers/gpu/drm/tiny/mi0283qt.c

279

ret = mipi_dbi_spi_init(spi, dbi, dc);

drivers/gpu/drm/tiny/panel-mipi-dbi.c

380

struct gpio_desc *dc;

drivers/gpu/drm/tiny/panel-mipi-dbi.c

422

dc = devm_gpiod_get_optional(dev, "dc", GPIOD_OUT_LOW | GPIOD_FLAGS_BIT_NONEXCLUSIVE);

drivers/gpu/drm/tiny/panel-mipi-dbi.c

423

if (IS_ERR(dc))

drivers/gpu/drm/tiny/panel-mipi-dbi.c

424

return dev_err_probe(dev, PTR_ERR(dc), "Failed to get GPIO 'dc'\n");

drivers/gpu/drm/tiny/panel-mipi-dbi.c

426

ret = mipi_dbi_spi_init(spi, dbi, dc);

drivers/gpu/drm/tiny/pixpaper.c

1072

panel->dc = devm_gpiod_get(dev, "dc", GPIOD_OUT_HIGH);

drivers/gpu/drm/tiny/pixpaper.c

1073

if (IS_ERR(panel->dc))

drivers/gpu/drm/tiny/pixpaper.c

1074

return PTR_ERR(panel->dc);

drivers/gpu/drm/tiny/pixpaper.c

505

struct gpio_desc *dc;

drivers/gpu/drm/tiny/pixpaper.c

555

gpiod_set_value_cansleep(panel->dc, 0);

drivers/gpu/drm/tiny/pixpaper.c

575

gpiod_set_value_cansleep(panel->dc, 1);

drivers/gpu/drm/verisilicon/vs_bridge.c

148

struct vs_dc *dc = crtc->dc;

drivers/gpu/drm/verisilicon/vs_bridge.c

151

regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_bridge.c

153

regmap_assign_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_bridge.c

157

regmap_assign_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_bridge.c

161

regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_bridge.c

165

regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_bridge.c

167

regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_START,

drivers/gpu/drm/verisilicon/vs_bridge.c

169

regmap_set_bits(dc->regs, VSDC_DISP_PANEL_START,

drivers/gpu/drm/verisilicon/vs_bridge.c

172

regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG_EX(crtc->id),

drivers/gpu/drm/verisilicon/vs_bridge.c

183

struct vs_dc *dc = crtc->dc;

drivers/gpu/drm/verisilicon/vs_bridge.c

186

regmap_clear_bits(dc->regs, VSDC_DISP_DP_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_bridge.c

188

regmap_write(dc->regs, VSDC_DISP_DPI_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_bridge.c

201

struct vs_dc *dc = crtc->dc;

drivers/gpu/drm/verisilicon/vs_bridge.c

215

regmap_write(dc->regs, VSDC_DISP_DP_CONFIG(output), dp_fmt);

drivers/gpu/drm/verisilicon/vs_bridge.c

216

regmap_assign_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_bridge.c

228

struct vs_dc *dc = crtc->dc;

drivers/gpu/drm/verisilicon/vs_bridge.c

231

regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_START,

drivers/gpu/drm/verisilicon/vs_bridge.c

234

regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_bridge.c

237

regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG_EX(crtc->id),

drivers/gpu/drm/verisilicon/vs_crtc.c

104

struct vs_dc *dc = vcrtc->dc;

drivers/gpu/drm/verisilicon/vs_crtc.c

112

clk_rate = clk_round_rate(dc->pix_clk[output], clk_rate);

drivers/gpu/drm/verisilicon/vs_crtc.c

133

struct vs_dc *dc = vcrtc->dc;

drivers/gpu/drm/verisilicon/vs_crtc.c

135

regmap_set_bits(dc->regs, VSDC_TOP_IRQ_EN, VSDC_TOP_IRQ_VSYNC(vcrtc->id));

drivers/gpu/drm/verisilicon/vs_crtc.c

143

struct vs_dc *dc = vcrtc->dc;

drivers/gpu/drm/verisilicon/vs_crtc.c

145

regmap_clear_bits(dc->regs, VSDC_TOP_IRQ_EN, VSDC_TOP_IRQ_VSYNC(vcrtc->id));

drivers/gpu/drm/verisilicon/vs_crtc.c

158

struct vs_crtc *vs_crtc_init(struct drm_device *drm_dev, struct vs_dc *dc,

drivers/gpu/drm/verisilicon/vs_crtc.c

168

vcrtc->dc = dc;

drivers/gpu/drm/verisilicon/vs_crtc.c

172

primary = vs_primary_plane_init(drm_dev, dc);

drivers/gpu/drm/verisilicon/vs_crtc.c

179

cursor = vs_cursor_plane_init(drm_dev, dc);

drivers/gpu/drm/verisilicon/vs_crtc.c

27

struct vs_dc *dc = vcrtc->dc;

drivers/gpu/drm/verisilicon/vs_crtc.c

32

clk_disable_unprepare(dc->pix_clk[output]);

drivers/gpu/drm/verisilicon/vs_crtc.c

39

struct vs_dc *dc = vcrtc->dc;

drivers/gpu/drm/verisilicon/vs_crtc.c

42

drm_WARN_ON(&dc->drm_dev->base,

drivers/gpu/drm/verisilicon/vs_crtc.c

43

clk_prepare_enable(dc->pix_clk[output]));

drivers/gpu/drm/verisilicon/vs_crtc.c

52

struct vs_dc *dc = vcrtc->dc;

drivers/gpu/drm/verisilicon/vs_crtc.c

55

regmap_write(dc->regs, VSDC_DISP_HSIZE(output),

drivers/gpu/drm/verisilicon/vs_crtc.c

58

regmap_write(dc->regs, VSDC_DISP_VSIZE(output),

drivers/gpu/drm/verisilicon/vs_crtc.c

61

regmap_write(dc->regs, VSDC_DISP_HSYNC(output),

drivers/gpu/drm/verisilicon/vs_crtc.c

66

regmap_set_bits(dc->regs, VSDC_DISP_HSYNC(output),

drivers/gpu/drm/verisilicon/vs_crtc.c

68

regmap_write(dc->regs, VSDC_DISP_VSYNC(output),

drivers/gpu/drm/verisilicon/vs_crtc.c

73

regmap_set_bits(dc->regs, VSDC_DISP_VSYNC(output),

drivers/gpu/drm/verisilicon/vs_crtc.c

76

WARN_ON(clk_set_rate(dc->pix_clk[output], mode->crtc_clock * 1000));

drivers/gpu/drm/verisilicon/vs_crtc.c

83

struct vs_dc *dc = vcrtc->dc;

drivers/gpu/drm/verisilicon/vs_crtc.c

92

rate = clk_round_rate(dc->pix_clk[output], mode->clock * HZ_PER_KHZ);

drivers/gpu/drm/verisilicon/vs_crtc.h

19

struct vs_dc *dc;

drivers/gpu/drm/verisilicon/vs_crtc.h

28

struct vs_crtc *vs_crtc_init(struct drm_device *drm_dev, struct vs_dc *dc,

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

108

struct vs_dc *dc = vcrtc->dc;

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

110

regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

114

vs_cursor_plane_commit(dc, output);

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

125

struct vs_dc *dc = vcrtc->dc;

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

127

regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

131

vs_cursor_plane_commit(dc, output);

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

141

struct vs_dc *dc;

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

153

dc = vcrtc->dc;

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

158

regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

163

regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

168

regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

173

regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

181

regmap_write(dc->regs, VSDC_CURSOR_ADDRESS(output),

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

194

regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

196

regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output),

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

200

regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

203

regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output),

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

208

regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

210

regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output),

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

214

regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

217

regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output),

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

221

vs_cursor_plane_commit(dc, output);

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

249

struct vs_dc *dc)

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

251

int32_t max_cursor_size = dc->identity.max_cursor_size;

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

51

struct vs_dc *dc;

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

69

dc = vcrtc->dc;

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

74

new_plane_state->crtc_w > dc->identity.max_cursor_size)

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

93

static void vs_cursor_plane_commit(struct vs_dc *dc, unsigned int output)

drivers/gpu/drm/verisilicon/vs_cursor_plane.c

95

regmap_set_bits(dc->regs, VSDC_CURSOR_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_dc.c

101

dc->ahb_clk = devm_clk_get_enabled(dev, "ahb");

drivers/gpu/drm/verisilicon/vs_dc.c

102

if (IS_ERR(dc->ahb_clk)) {

drivers/gpu/drm/verisilicon/vs_dc.c

104

return PTR_ERR(dc->ahb_clk);

drivers/gpu/drm/verisilicon/vs_dc.c

113

ret = reset_control_bulk_deassert(VSDC_RESET_COUNT, dc->rsts);

drivers/gpu/drm/verisilicon/vs_dc.c

126

dc->regs = devm_regmap_init_mmio(dev, regs, &vs_dc_regmap_cfg);

drivers/gpu/drm/verisilicon/vs_dc.c

127

if (IS_ERR(dc->regs)) {

drivers/gpu/drm/verisilicon/vs_dc.c

128

ret = PTR_ERR(dc->regs);

drivers/gpu/drm/verisilicon/vs_dc.c

132

ret = vs_fill_chip_identity(dc->regs, &dc->identity);

drivers/gpu/drm/verisilicon/vs_dc.c

136

dev_info(dev, "Found DC%x rev %x customer %x\n", dc->identity.model,

drivers/gpu/drm/verisilicon/vs_dc.c

137

dc->identity.revision, dc->identity.customer_id);

drivers/gpu/drm/verisilicon/vs_dc.c

139

if (port_count > dc->identity.display_count) {

drivers/gpu/drm/verisilicon/vs_dc.c

145

for (i = 0; i < dc->identity.display_count; i++) {

drivers/gpu/drm/verisilicon/vs_dc.c

147

dc->pix_clk[i] = devm_clk_get(dev, pixclk_name);

drivers/gpu/drm/verisilicon/vs_dc.c

148

if (IS_ERR(dc->pix_clk[i])) {

drivers/gpu/drm/verisilicon/vs_dc.c

150

ret = PTR_ERR(dc->pix_clk[i]);

drivers/gpu/drm/verisilicon/vs_dc.c

156

dev_name(dev), dc);

drivers/gpu/drm/verisilicon/vs_dc.c

162

dev_set_drvdata(dev, dc);

drivers/gpu/drm/verisilicon/vs_dc.c

164

ret = vs_drm_initialize(dc, pdev);

drivers/gpu/drm/verisilicon/vs_dc.c

171

reset_control_bulk_assert(VSDC_RESET_COUNT, dc->rsts);

drivers/gpu/drm/verisilicon/vs_dc.c

177

struct vs_dc *dc = dev_get_drvdata(&pdev->dev);

drivers/gpu/drm/verisilicon/vs_dc.c

179

vs_drm_finalize(dc);

drivers/gpu/drm/verisilicon/vs_dc.c

183

reset_control_bulk_assert(VSDC_RESET_COUNT, dc->rsts);

drivers/gpu/drm/verisilicon/vs_dc.c

188

struct vs_dc *dc = dev_get_drvdata(&pdev->dev);

drivers/gpu/drm/verisilicon/vs_dc.c

190

vs_drm_shutdown_handler(dc);

drivers/gpu/drm/verisilicon/vs_dc.c

33

struct vs_dc *dc = private;

drivers/gpu/drm/verisilicon/vs_dc.c

36

regmap_read(dc->regs, VSDC_TOP_IRQ_ACK, &irqs);

drivers/gpu/drm/verisilicon/vs_dc.c

38

vs_drm_handle_irq(dc, irqs);

drivers/gpu/drm/verisilicon/vs_dc.c

46

struct vs_dc *dc;

drivers/gpu/drm/verisilicon/vs_dc.c

74

dc = devm_kzalloc(dev, sizeof(*dc), GFP_KERNEL);

drivers/gpu/drm/verisilicon/vs_dc.c

75

if (!dc)

drivers/gpu/drm/verisilicon/vs_dc.c

78

dc->rsts[0].id = "core";

drivers/gpu/drm/verisilicon/vs_dc.c

79

dc->rsts[1].id = "axi";

drivers/gpu/drm/verisilicon/vs_dc.c

80

dc->rsts[2].id = "ahb";

drivers/gpu/drm/verisilicon/vs_dc.c

83

dc->rsts);

drivers/gpu/drm/verisilicon/vs_dc.c

89

dc->core_clk = devm_clk_get_enabled(dev, "core");

drivers/gpu/drm/verisilicon/vs_dc.c

90

if (IS_ERR(dc->core_clk)) {

drivers/gpu/drm/verisilicon/vs_dc.c

92

return PTR_ERR(dc->core_clk);

drivers/gpu/drm/verisilicon/vs_dc.c

95

dc->axi_clk = devm_clk_get_enabled(dev, "axi");

drivers/gpu/drm/verisilicon/vs_dc.c

96

if (IS_ERR(dc->axi_clk)) {

drivers/gpu/drm/verisilicon/vs_dc.c

98

return PTR_ERR(dc->axi_clk);

drivers/gpu/drm/verisilicon/vs_drm.c

100

vdrm->dc = dc;

drivers/gpu/drm/verisilicon/vs_drm.c

101

dc->drm_dev = vdrm;

drivers/gpu/drm/verisilicon/vs_drm.c

112

for (i = 0; i < dc->identity.display_count; i++) {

drivers/gpu/drm/verisilicon/vs_drm.c

113

crtc = vs_crtc_init(drm, dc, i);

drivers/gpu/drm/verisilicon/vs_drm.c

124

ret = drm_vblank_init(drm, dc->identity.display_count);

drivers/gpu/drm/verisilicon/vs_drm.c

148

void vs_drm_finalize(struct vs_dc *dc)

drivers/gpu/drm/verisilicon/vs_drm.c

150

struct vs_drm_dev *vdrm = dc->drm_dev;

drivers/gpu/drm/verisilicon/vs_drm.c

156

dc->drm_dev = NULL;

drivers/gpu/drm/verisilicon/vs_drm.c

159

void vs_drm_shutdown_handler(struct vs_dc *dc)

drivers/gpu/drm/verisilicon/vs_drm.c

161

struct vs_drm_dev *vdrm = dc->drm_dev;

drivers/gpu/drm/verisilicon/vs_drm.c

166

void vs_drm_handle_irq(struct vs_dc *dc, u32 irqs)

drivers/gpu/drm/verisilicon/vs_drm.c

170

for (i = 0; i < dc->identity.display_count; i++) {

drivers/gpu/drm/verisilicon/vs_drm.c

173

if (dc->drm_dev->crtcs[i])

drivers/gpu/drm/verisilicon/vs_drm.c

174

drm_crtc_handle_vblank(&dc->drm_dev->crtcs[i]->base);

drivers/gpu/drm/verisilicon/vs_drm.c

179

drm_warn_once(&dc->drm_dev->base,

drivers/gpu/drm/verisilicon/vs_drm.c

85

int vs_drm_initialize(struct vs_dc *dc, struct platform_device *pdev)

drivers/gpu/drm/verisilicon/vs_drm.h

19

struct vs_dc *dc;

drivers/gpu/drm/verisilicon/vs_drm.h

23

int vs_drm_initialize(struct vs_dc *dc, struct platform_device *pdev);

drivers/gpu/drm/verisilicon/vs_drm.h

24

void vs_drm_finalize(struct vs_dc *dc);

drivers/gpu/drm/verisilicon/vs_drm.h

25

void vs_drm_shutdown_handler(struct vs_dc *dc);

drivers/gpu/drm/verisilicon/vs_drm.h

26

void vs_drm_handle_irq(struct vs_dc *dc, u32 irqs);

drivers/gpu/drm/verisilicon/vs_plane.h

86

struct drm_plane *vs_primary_plane_init(struct drm_device *dev, struct vs_dc *dc);

drivers/gpu/drm/verisilicon/vs_plane.h

87

struct drm_plane *vs_cursor_plane_init(struct drm_device *dev, struct vs_dc *dc);

drivers/gpu/drm/verisilicon/vs_primary_plane.c

105

struct vs_dc *dc;

drivers/gpu/drm/verisilicon/vs_primary_plane.c

117

dc = vcrtc->dc;

drivers/gpu/drm/verisilicon/vs_primary_plane.c

119

regmap_update_bits(dc->regs, VSDC_FB_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_primary_plane.c

122

regmap_update_bits(dc->regs, VSDC_FB_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_primary_plane.c

125

regmap_assign_bits(dc->regs, VSDC_FB_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_primary_plane.c

131

regmap_write(dc->regs, VSDC_FB_ADDRESS(output),

drivers/gpu/drm/verisilicon/vs_primary_plane.c

133

regmap_write(dc->regs, VSDC_FB_STRIDE(output),

drivers/gpu/drm/verisilicon/vs_primary_plane.c

136

regmap_write(dc->regs, VSDC_FB_TOP_LEFT(output),

drivers/gpu/drm/verisilicon/vs_primary_plane.c

138

regmap_write(dc->regs, VSDC_FB_BOTTOM_RIGHT(output),

drivers/gpu/drm/verisilicon/vs_primary_plane.c

141

regmap_write(dc->regs, VSDC_FB_SIZE(output),

drivers/gpu/drm/verisilicon/vs_primary_plane.c

144

regmap_write(dc->regs, VSDC_FB_BLEND_CONFIG(output),

drivers/gpu/drm/verisilicon/vs_primary_plane.c

147

vs_primary_plane_commit(dc, output);

drivers/gpu/drm/verisilicon/vs_primary_plane.c

165

struct drm_plane *vs_primary_plane_init(struct drm_device *drm_dev, struct vs_dc *dc)

drivers/gpu/drm/verisilicon/vs_primary_plane.c

171

dc->identity.formats->array,

drivers/gpu/drm/verisilicon/vs_primary_plane.c

172

dc->identity.formats->num,

drivers/gpu/drm/verisilicon/vs_primary_plane.c

56

static void vs_primary_plane_commit(struct vs_dc *dc, unsigned int output)

drivers/gpu/drm/verisilicon/vs_primary_plane.c

58

regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output),

drivers/gpu/drm/verisilicon/vs_primary_plane.c

70

struct vs_dc *dc = vcrtc->dc;

drivers/gpu/drm/verisilicon/vs_primary_plane.c

72

regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output),

drivers/gpu/drm/verisilicon/vs_primary_plane.c

74

regmap_update_bits(dc->regs, VSDC_FB_CONFIG_EX(output),

drivers/gpu/drm/verisilicon/vs_primary_plane.c

78

vs_primary_plane_commit(dc, output);

drivers/gpu/drm/verisilicon/vs_primary_plane.c

89

struct vs_dc *dc = vcrtc->dc;

drivers/gpu/drm/verisilicon/vs_primary_plane.c

91

regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output),

drivers/gpu/drm/verisilicon/vs_primary_plane.c

94

vs_primary_plane_commit(dc, output);

drivers/gpu/ipu-v3/ipu-common.c

1080

.dc = 5,

drivers/gpu/ipu-v3/ipu-common.c

1089

.dc = 1,

drivers/gpu/ipu-v3/ipu-dc.c

109

static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority)

drivers/gpu/ipu-v3/ipu-dc.c

113

reg = readl(dc->base + DC_RL_CH(event));

drivers/gpu/ipu-v3/ipu-dc.c

116

writel(reg, dc->base + DC_RL_CH(event));

drivers/gpu/ipu-v3/ipu-dc.c

119

static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand,

drivers/gpu/ipu-v3/ipu-dc.c

122

struct ipu_dc_priv *priv = dc->priv;

drivers/gpu/ipu-v3/ipu-dc.c

160

int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,

drivers/gpu/ipu-v3/ipu-dc.c

163

struct ipu_dc_priv *priv = dc->priv;

drivers/gpu/ipu-v3/ipu-dc.c

168

dc->di = ipu_di_get_num(di);

drivers/gpu/ipu-v3/ipu-dc.c

186

if (dc->di)

drivers/gpu/ipu-v3/ipu-dc.c

192

dc_link_event(dc, DC_EVT_NL, addr, 3);

drivers/gpu/ipu-v3/ipu-dc.c

193

dc_link_event(dc, DC_EVT_EOL, addr, 2);

drivers/gpu/ipu-v3/ipu-dc.c

194

dc_link_event(dc, DC_EVT_NEW_DATA, addr, 1);

drivers/gpu/ipu-v3/ipu-dc.c

197

dc_write_tmpl(dc, addr, WROD(0), 0, map, SYNC_WAVE, 0, sync, 1);

drivers/gpu/ipu-v3/ipu-dc.c

199

dc_link_event(dc, DC_EVT_NL, addr + 2, 3);

drivers/gpu/ipu-v3/ipu-dc.c

200

dc_link_event(dc, DC_EVT_EOL, addr + 3, 2);

drivers/gpu/ipu-v3/ipu-dc.c

201

dc_link_event(dc, DC_EVT_NEW_DATA, addr + 1, 1);

drivers/gpu/ipu-v3/ipu-dc.c

204

dc_write_tmpl(dc, addr + 2, WROD(0), 0, map, SYNC_WAVE, 8, sync, 1);

drivers/gpu/ipu-v3/ipu-dc.c

205

dc_write_tmpl(dc, addr + 3, WROD(0), 0, map, SYNC_WAVE, 4, sync, 0);

drivers/gpu/ipu-v3/ipu-dc.c

206

dc_write_tmpl(dc, addr + 4, WRG, 0, map, NULL_WAVE, 0, 0, 1);

drivers/gpu/ipu-v3/ipu-dc.c

207

dc_write_tmpl(dc, addr + 1, WROD(0), 0, map, SYNC_WAVE, 0, sync, 1);

drivers/gpu/ipu-v3/ipu-dc.c

210

dc_link_event(dc, DC_EVT_NF, 0, 0);

drivers/gpu/ipu-v3/ipu-dc.c

211

dc_link_event(dc, DC_EVT_NFIELD, 0, 0);

drivers/gpu/ipu-v3/ipu-dc.c

212

dc_link_event(dc, DC_EVT_EOF, 0, 0);

drivers/gpu/ipu-v3/ipu-dc.c

213

dc_link_event(dc, DC_EVT_EOFIELD, 0, 0);

drivers/gpu/ipu-v3/ipu-dc.c

214

dc_link_event(dc, DC_EVT_NEW_CHAN, 0, 0);

drivers/gpu/ipu-v3/ipu-dc.c

215

dc_link_event(dc, DC_EVT_NEW_ADDR, 0, 0);

drivers/gpu/ipu-v3/ipu-dc.c

217

reg = readl(dc->base + DC_WR_CH_CONF);

drivers/gpu/ipu-v3/ipu-dc.c

222

writel(reg, dc->base + DC_WR_CH_CONF);

drivers/gpu/ipu-v3/ipu-dc.c

224

writel(0x0, dc->base + DC_WR_CH_ADDR);

drivers/gpu/ipu-v3/ipu-dc.c

225

writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di));

drivers/gpu/ipu-v3/ipu-dc.c

246

void ipu_dc_enable_channel(struct ipu_dc *dc)

drivers/gpu/ipu-v3/ipu-dc.c

250

reg = readl(dc->base + DC_WR_CH_CONF);

drivers/gpu/ipu-v3/ipu-dc.c

252

writel(reg, dc->base + DC_WR_CH_CONF);

drivers/gpu/ipu-v3/ipu-dc.c

256

void ipu_dc_disable_channel(struct ipu_dc *dc)

drivers/gpu/ipu-v3/ipu-dc.c

260

val = readl(dc->base + DC_WR_CH_CONF);

drivers/gpu/ipu-v3/ipu-dc.c

262

writel(val, dc->base + DC_WR_CH_CONF);

drivers/gpu/ipu-v3/ipu-dc.c

311

struct ipu_dc *dc;

drivers/gpu/ipu-v3/ipu-dc.c

316

dc = &priv->channels[channel];

drivers/gpu/ipu-v3/ipu-dc.c

320

if (dc->in_use) {

drivers/gpu/ipu-v3/ipu-dc.c

325

dc->in_use = true;

drivers/gpu/ipu-v3/ipu-dc.c

329

return dc;

drivers/gpu/ipu-v3/ipu-dc.c

333

void ipu_dc_put(struct ipu_dc *dc)

drivers/gpu/ipu-v3/ipu-dc.c

335

struct ipu_dc_priv *priv = dc->priv;

drivers/gpu/ipu-v3/ipu-dc.c

338

dc->in_use = false;

drivers/i2c/busses/i2c-ibm_iic.c

182

u8 dc;

drivers/i2c/busses/i2c-ibm_iic.c

191

dc = in_8(&iic->directcntl);

drivers/i2c/busses/i2c-ibm_iic.c

192

if (!DIRCTNL_FREE(dc)){

drivers/i2c/busses/i2c-ibm_iic.c

200

dc = in_8(&iic->directcntl);

drivers/i2c/busses/i2c-ibm_iic.c

201

if (DIRCTNL_FREE(dc))

drivers/i2c/busses/i2c-ibm_iic.c

205

dc ^= DIRCNTL_SCC;

drivers/i2c/busses/i2c-ibm_iic.c

206

out_8(&iic->directcntl, dc);

drivers/i2c/busses/i2c-ibm_iic.c

208

dc ^= DIRCNTL_SCC;

drivers/i2c/busses/i2c-ibm_iic.c

209

out_8(&iic->directcntl, dc);

drivers/iommu/riscv/iommu.c

1101

struct riscv_iommu_dc *dc,

drivers/iommu/riscv/iommu.c

1118

if (!FIELD_GET(RISCV_IOMMU_DC_TC_PDTV, dc->tc) &&

drivers/iommu/riscv/iommu.c

1119

FIELD_GET(RISCV_IOMMU_DC_FSC_MODE, dc->fsc) !=

drivers/iommu/riscv/iommu.c

1127

FIELD_GET(RISCV_IOMMU_DC_TA_PSCID, dc->ta));

drivers/iommu/riscv/iommu.c

1171

struct riscv_iommu_dc *dc;

drivers/iommu/riscv/iommu.c

1178

dc = riscv_iommu_get_dc(iommu, fwspec->ids[i]);

drivers/iommu/riscv/iommu.c

1179

tc = READ_ONCE(dc->tc);

drivers/iommu/riscv/iommu.c

1183

WRITE_ONCE(dc->tc, tc & ~RISCV_IOMMU_DC_TC_V);

drivers/iommu/riscv/iommu.c

1193

riscv_iommu_iodir_iotinval(iommu, false, dc->iohgatp, dc, NULL);

drivers/iommu/riscv/iommu.c

1205

dc = riscv_iommu_get_dc(iommu, fwspec->ids[i]);

drivers/iommu/riscv/iommu.c

1206

tc = READ_ONCE(dc->tc);

drivers/iommu/riscv/iommu.c

1209

WRITE_ONCE(dc->fsc, fsc);

drivers/iommu/riscv/iommu.c

1210

WRITE_ONCE(dc->ta, ta & RISCV_IOMMU_PC_TA_PSCID);

drivers/iommu/riscv/iommu.c

1213

WRITE_ONCE(dc->tc, tc);

drivers/iommu/riscv/iommu.c

1223

riscv_iommu_iodir_iotinval(iommu, false, dc->iohgatp, dc, NULL);

drivers/iommu/riscv/iommu.c

1435

struct riscv_iommu_dc *dc;

drivers/iommu/riscv/iommu.c

1462

dc = riscv_iommu_get_dc(iommu, fwspec->ids[i]);

drivers/iommu/riscv/iommu.c

1463

if (!dc) {

drivers/iommu/riscv/iommu.c

1467

if (READ_ONCE(dc->tc) & RISCV_IOMMU_DC_TC_V)

drivers/iommu/riscv/iommu.c

1469

WRITE_ONCE(dc->tc, tc);

drivers/ipack/devices/scc2698.h

60

u8 dc, r3; /* reserved */

drivers/ipack/devices/scc2698.h

78

u8 dc, r1; /* reserved */

drivers/md/bcache/bcache.h

1004

bool bch_cached_dev_error(struct cached_dev *dc);

drivers/md/bcache/bcache.h

1010

void bch_write_bdev_super(struct cached_dev *dc, struct closure *parent);

drivers/md/bcache/bcache.h

1034

int bch_cached_dev_attach(struct cached_dev *dc, struct cache_set *c,

drivers/md/bcache/bcache.h

1036

void bch_cached_dev_detach(struct cached_dev *dc);

drivers/md/bcache/bcache.h

1037

int bch_cached_dev_run(struct cached_dev *dc);

drivers/md/bcache/bcache.h

902

static inline void cached_dev_put(struct cached_dev *dc)

drivers/md/bcache/bcache.h

904

if (refcount_dec_and_test(&dc->count))

drivers/md/bcache/bcache.h

905

schedule_work(&dc->detach);

drivers/md/bcache/bcache.h

908

static inline bool cached_dev_get(struct cached_dev *dc)

drivers/md/bcache/bcache.h

910

if (!refcount_inc_not_zero(&dc->count))

drivers/md/bcache/bcache.h

973

void bch_count_backing_io_errors(struct cached_dev *dc, struct bio *bio);

drivers/md/bcache/btree.c

1779

struct cached_dev *dc;

drivers/md/bcache/btree.c

1784

dc = container_of(d, struct cached_dev, disk);

drivers/md/bcache/btree.c

1786

spin_lock(&dc->writeback_keys.lock);

drivers/md/bcache/btree.c

1788

&dc->writeback_keys.keys, node)

drivers/md/bcache/btree.c

1792

spin_unlock(&dc->writeback_keys.lock);

drivers/md/bcache/debug.c

108

void bch_data_verify(struct cached_dev *dc, struct bio *bio)

drivers/md/bcache/debug.c

137

dc->disk.c,

drivers/md/bcache/debug.c

139

dc->bdev,

drivers/md/bcache/debug.h

12

void bch_data_verify(struct cached_dev *dc, struct bio *bio);

drivers/md/bcache/debug.h

21

static inline void bch_data_verify(struct cached_dev *dc, struct bio *bio) {}

drivers/md/bcache/io.c

55

void bch_count_backing_io_errors(struct cached_dev *dc, struct bio *bio)

drivers/md/bcache/io.c

59

WARN_ONCE(!dc, "NULL pointer of struct cached_dev");

drivers/md/bcache/io.c

69

dc->bdev);

drivers/md/bcache/io.c

73

errors = atomic_add_return(1, &dc->io_errors);

drivers/md/bcache/io.c

74

if (errors < dc->error_limit)

drivers/md/bcache/io.c

76

dc->bdev);

drivers/md/bcache/io.c

78

bch_cached_dev_error(dc);

drivers/md/bcache/request.c

1010

if (should_writeback(dc, s->orig_bio,

drivers/md/bcache/request.c

1011

cache_mode(dc),

drivers/md/bcache/request.c

1022

!bdev_max_discard_sectors(dc->bdev))

drivers/md/bcache/request.c

1030

bch_writeback_add(dc);

drivers/md/bcache/request.c

1042

GFP_NOIO, &dc->disk.bio_split);

drivers/md/bcache/request.c

1054

&dc->disk.bio_split);

drivers/md/bcache/request.c

1090

struct cached_dev *dc = bio->bi_private;

drivers/md/bcache/request.c

1093

bch_count_backing_io_errors(dc, bio);

drivers/md/bcache/request.c

1105

struct cached_dev *dc = container_of(d, struct cached_dev, disk);

drivers/md/bcache/request.c

1109

!bdev_max_discard_sectors(dc->bdev)) {

drivers/md/bcache/request.c

1115

clone_bio = bio_alloc_clone(dc->bdev, orig_bio, GFP_NOIO,

drivers/md/bcache/request.c

1125

clone_bio->bi_private = dc;

drivers/md/bcache/request.c

1135

struct cached_dev *dc;

drivers/md/bcache/request.c

1155

dc = container_of(d, struct cached_dev, disk);

drivers/md/bcache/request.c

1161

atomic_long_set(&dc->writeback_rate.rate, 1);

drivers/md/bcache/request.c

1175

struct cached_dev *dc = container_of(d, struct cached_dev, disk);

drivers/md/bcache/request.c

1180

dc->io_disable)) {

drivers/md/bcache/request.c

1197

quit_max_writeback_rate(d->c, dc);

drivers/md/bcache/request.c

1203

bio->bi_iter.bi_sector += dc->sb.data_offset;

drivers/md/bcache/request.c

1205

if (cached_dev_get(dc)) {

drivers/md/bcache/request.c

1206

bio_set_dev(bio, dc->bdev);

drivers/md/bcache/request.c

1219

s->iop.bypass = check_should_bypass(dc, bio);

drivers/md/bcache/request.c

1222

cached_dev_write(dc, s);

drivers/md/bcache/request.c

1224

cached_dev_read(dc, s);

drivers/md/bcache/request.c

1235

struct cached_dev *dc = container_of(d, struct cached_dev, disk);

drivers/md/bcache/request.c

1237

if (dc->io_disable)

drivers/md/bcache/request.c

1239

if (!dc->bdev->bd_disk->fops->ioctl)

drivers/md/bcache/request.c

1241

return dc->bdev->bd_disk->fops->ioctl(dc->bdev, mode, cmd, arg);

drivers/md/bcache/request.c

1244

void bch_cached_dev_request_init(struct cached_dev *dc)

drivers/md/bcache/request.c

1246

dc->disk.cache_miss = cached_dev_cache_miss;

drivers/md/bcache/request.c

1247

dc->disk.ioctl = cached_dev_ioctl;

drivers/md/bcache/request.c

30

static unsigned int cache_mode(struct cached_dev *dc)

drivers/md/bcache/request.c

32

return BDEV_CACHE_MODE(&dc->sb);

drivers/md/bcache/request.c

35

static bool verify(struct cached_dev *dc)

drivers/md/bcache/request.c

358

static struct hlist_head *iohash(struct cached_dev *dc, uint64_t k)

drivers/md/bcache/request.c

360

return &dc->io_hash[hash_64(k, RECENT_IO_BITS)];

drivers/md/bcache/request.c

363

static bool check_should_bypass(struct cached_dev *dc, struct bio *bio)

drivers/md/bcache/request.c

365

struct cache_set *c = dc->disk.c;

drivers/md/bcache/request.c

366

unsigned int mode = cache_mode(dc);

drivers/md/bcache/request.c

37

return dc->verify;

drivers/md/bcache/request.c

371

if (test_bit(BCACHE_DEV_DETACHING, &dc->disk.flags) ||

drivers/md/bcache/request.c

383

if (BDEV_STATE(&dc->sb) == BDEV_STATE_CLEAN &&

drivers/md/bcache/request.c

407

(dc->cache_readahead_policy != BCH_CACHE_READA_ALL))

drivers/md/bcache/request.c

417

if (bypass_torture_test(dc)) {

drivers/md/bcache/request.c

425

if (!congested && !dc->sequential_cutoff)

drivers/md/bcache/request.c

428

spin_lock(&dc->io_lock);

drivers/md/bcache/request.c

430

hlist_for_each_entry(i, iohash(dc, bio->bi_iter.bi_sector), hash)

drivers/md/bcache/request.c

435

i = list_first_entry(&dc->io_lru, struct io, lru);

drivers/md/bcache/request.c

448

hlist_add_head(&i->hash, iohash(dc, i->last));

drivers/md/bcache/request.c

449

list_move_tail(&i->lru, &dc->io_lru);

drivers/md/bcache/request.c

451

spin_unlock(&dc->io_lock);

drivers/md/bcache/request.c

456

if (dc->sequential_cutoff &&

drivers/md/bcache/request.c

457

sectors >= dc->sequential_cutoff >> 9) {

drivers/md/bcache/request.c

471

bch_mark_sectors_bypassed(c, dc, bio_sectors(bio));

drivers/md/bcache/request.c

596

struct cached_dev *dc;

drivers/md/bcache/request.c

622

dc = container_of(s->d, struct cached_dev, disk);

drivers/md/bcache/request.c

623

if (dc && atomic_read(&dc->has_dirty))

drivers/md/bcache/request.c

657

struct cached_dev *dc = container_of(s->d,

drivers/md/bcache/request.c

669

dc->bdev, bio->bi_status);

drivers/md/bcache/request.c

676

bch_count_backing_io_errors(dc, bio);

drivers/md/bcache/request.c

769

struct cached_dev *dc = container_of(s->d, struct cached_dev, disk);

drivers/md/bcache/request.c

771

cached_dev_put(dc);

drivers/md/bcache/request.c

836

struct cached_dev *dc = container_of(s->d, struct cached_dev, disk);

drivers/md/bcache/request.c

860

if (verify(dc) && s->recoverable && !s->read_dirty_data)

drivers/md/bcache/request.c

861

bch_data_verify(dc, s->orig_bio);

drivers/md/bcache/request.c

863

closure_get(&dc->disk.cl);

drivers/md/bcache/request.c

878

struct cached_dev *dc = container_of(s->d, struct cached_dev, disk);

drivers/md/bcache/request.c

886

else if (s->iop.bio || verify(dc))

drivers/md/bcache/request.c

896

struct cached_dev *dc = container_of(s->d, struct cached_dev, disk);

drivers/md/bcache/request.c

931

0, GFP_NOWAIT, &dc->disk.bio_split);

drivers/md/bcache/request.c

962

static void cached_dev_read(struct cached_dev *dc, struct search *s)

drivers/md/bcache/request.c

975

struct cached_dev *dc = container_of(s->d, struct cached_dev, disk);

drivers/md/bcache/request.c

977

up_read_non_owner(&dc->writeback_lock);

drivers/md/bcache/request.c

981

static void cached_dev_write(struct cached_dev *dc, struct search *s)

drivers/md/bcache/request.c

985

struct bkey start = KEY(dc->disk.id, bio->bi_iter.bi_sector, 0);

drivers/md/bcache/request.c

986

struct bkey end = KEY(dc->disk.id, bio_end_sector(bio), 0);

drivers/md/bcache/request.c

990

down_read_non_owner(&dc->writeback_lock);

drivers/md/bcache/request.c

991

if (bch_keybuf_check_overlapping(&dc->writeback_keys, &start, &end)) {

drivers/md/bcache/request.h

39

void bch_cached_dev_request_init(struct cached_dev *dc);

drivers/md/bcache/stats.c

201

struct cached_dev *dc = container_of(d, struct cached_dev, disk);

drivers/md/bcache/stats.c

203

mark_cache_stats(&dc->accounting.collector, hit, bypass);

drivers/md/bcache/stats.c

209

struct cached_dev *dc = container_of(d, struct cached_dev, disk);

drivers/md/bcache/stats.c

211

atomic_inc(&dc->accounting.collector.cache_miss_collisions);

drivers/md/bcache/stats.c

215

void bch_mark_sectors_bypassed(struct cache_set *c, struct cached_dev *dc,

drivers/md/bcache/stats.c

218

atomic_add(sectors, &dc->accounting.collector.sectors_bypassed);

drivers/md/bcache/stats.h

59

struct cached_dev *dc,

drivers/md/bcache/super.c

1004

struct cached_dev *dc;

drivers/md/bcache/super.c

1006

list_for_each_entry(dc, &c->cached_devs, list)

drivers/md/bcache/super.c

1007

sectors += bdev_nr_sectors(dc->bdev);

drivers/md/bcache/super.c

1015

struct cached_dev *dc = arg;

drivers/md/bcache/super.c

1023

while (!kthread_should_stop() && !dc->io_disable) {

drivers/md/bcache/super.c

1024

q = bdev_get_queue(dc->bdev);

drivers/md/bcache/super.c

1026

dc->offline_seconds++;

drivers/md/bcache/super.c

1028

dc->offline_seconds = 0;

drivers/md/bcache/super.c

1030

if (dc->offline_seconds >= BACKING_DEV_OFFLINE_TIMEOUT) {

drivers/md/bcache/super.c

1032

dc->bdev,

drivers/md/bcache/super.c

1035

dc->disk.name);

drivers/md/bcache/super.c

1036

dc->io_disable = true;

drivers/md/bcache/super.c

1039

bcache_device_stop(&dc->disk);

drivers/md/bcache/super.c

1050

int bch_cached_dev_run(struct cached_dev *dc)

drivers/md/bcache/super.c

1053

struct bcache_device *d = &dc->disk;

drivers/md/bcache/super.c

1054

char *buf = kmemdup_nul(dc->sb.label, SB_LABEL_SIZE, GFP_KERNEL);

drivers/md/bcache/super.c

1057

kasprintf(GFP_KERNEL, "CACHED_UUID=%pU", dc->sb.uuid),

drivers/md/bcache/super.c

1062

if (dc->io_disable) {

drivers/md/bcache/super.c

1063

pr_err("I/O disabled on cached dev %pg\n", dc->bdev);

drivers/md/bcache/super.c

1068

if (atomic_xchg(&dc->running, 1)) {

drivers/md/bcache/super.c

1069

pr_info("cached dev %pg is running already\n", dc->bdev);

drivers/md/bcache/super.c

1075

BDEV_STATE(&dc->sb) != BDEV_STATE_NONE) {

drivers/md/bcache/super.c

1080

SET_BDEV_STATE(&dc->sb, BDEV_STATE_STALE);

drivers/md/bcache/super.c

1081

bch_write_bdev_super(dc, &cl);

drivers/md/bcache/super.c

1088

bd_link_disk_holder(dc->bdev, dc->disk.disk);

drivers/md/bcache/super.c

1103

dc->status_update_thread = kthread_run(cached_dev_status_update,

drivers/md/bcache/super.c

1104

dc, "bcache_status_update");

drivers/md/bcache/super.c

1105

if (IS_ERR(dc->status_update_thread)) {

drivers/md/bcache/super.c

1123

static void cancel_writeback_rate_update_dwork(struct cached_dev *dc)

drivers/md/bcache/super.c

1129

&dc->disk.flags))

drivers/md/bcache/super.c

1138

cancel_delayed_work_sync(&dc->writeback_rate_update);

drivers/md/bcache/super.c

1143

struct cached_dev *dc = container_of(w, struct cached_dev, detach);

drivers/md/bcache/super.c

1144

struct cache_set *c = dc->disk.c;

drivers/md/bcache/super.c

1146

BUG_ON(!test_bit(BCACHE_DEV_DETACHING, &dc->disk.flags));

drivers/md/bcache/super.c

1147

BUG_ON(refcount_read(&dc->count));

drivers/md/bcache/super.c

1150

if (test_and_clear_bit(BCACHE_DEV_WB_RUNNING, &dc->disk.flags))

drivers/md/bcache/super.c

1151

cancel_writeback_rate_update_dwork(dc);

drivers/md/bcache/super.c

1153

if (!IS_ERR_OR_NULL(dc->writeback_thread)) {

drivers/md/bcache/super.c

1154

kthread_stop(dc->writeback_thread);

drivers/md/bcache/super.c

1155

dc->writeback_thread = NULL;

drivers/md/bcache/super.c

1160

bcache_device_detach(&dc->disk);

drivers/md/bcache/super.c

1161

list_move(&dc->list, &uncached_devices);

drivers/md/bcache/super.c

1164

clear_bit(BCACHE_DEV_DETACHING, &dc->disk.flags);

drivers/md/bcache/super.c

1165

clear_bit(BCACHE_DEV_UNLINK_DONE, &dc->disk.flags);

drivers/md/bcache/super.c

1169

pr_info("Caching disabled for %pg\n", dc->bdev);

drivers/md/bcache/super.c

1172

closure_put(&dc->disk.cl);

drivers/md/bcache/super.c

1175

void bch_cached_dev_detach(struct cached_dev *dc)

drivers/md/bcache/super.c

1179

if (test_bit(BCACHE_DEV_CLOSING, &dc->disk.flags))

drivers/md/bcache/super.c

1182

if (test_and_set_bit(BCACHE_DEV_DETACHING, &dc->disk.flags))

drivers/md/bcache/super.c

1189

closure_get(&dc->disk.cl);

drivers/md/bcache/super.c

1191

bch_writeback_queue(dc);

drivers/md/bcache/super.c

1193

cached_dev_put(dc);

drivers/md/bcache/super.c

1196

int bch_cached_dev_attach(struct cached_dev *dc, struct cache_set *c,

drivers/md/bcache/super.c

1205

(!set_uuid && memcmp(dc->sb.set_uuid, c->set_uuid, 16)))

drivers/md/bcache/super.c

1208

if (dc->disk.c) {

drivers/md/bcache/super.c

1209

pr_err("Can't attach %pg: already attached\n", dc->bdev);

drivers/md/bcache/super.c

1214

pr_err("Can't attach %pg: shutting down\n", dc->bdev);

drivers/md/bcache/super.c

1218

if (dc->sb.block_size < c->cache->sb.block_size) {

drivers/md/bcache/super.c

1221

dc->bdev);

drivers/md/bcache/super.c

1227

if (!memcmp(dc->sb.uuid, exist_dc->sb.uuid, 16)) {

drivers/md/bcache/super.c

1229

dc->bdev);

drivers/md/bcache/super.c

1235

u = uuid_find(c, dc->sb.uuid);

drivers/md/bcache/super.c

1238

(BDEV_STATE(&dc->sb) == BDEV_STATE_STALE ||

drivers/md/bcache/super.c

1239

BDEV_STATE(&dc->sb) == BDEV_STATE_NONE)) {

drivers/md/bcache/super.c

1246

if (BDEV_STATE(&dc->sb) == BDEV_STATE_DIRTY) {

drivers/md/bcache/super.c

1247

pr_err("Couldn't find uuid for %pg in set\n", dc->bdev);

drivers/md/bcache/super.c

1253

pr_err("Not caching %pg, no room for UUID\n", dc->bdev);

drivers/md/bcache/super.c

1268

memcpy(u->uuid, dc->sb.uuid, 16);

drivers/md/bcache/super.c

1269

memcpy(u->label, dc->sb.label, SB_LABEL_SIZE);

drivers/md/bcache/super.c

1273

memcpy(dc->sb.set_uuid, c->set_uuid, 16);

drivers/md/bcache/super.c

1274

SET_BDEV_STATE(&dc->sb, BDEV_STATE_CLEAN);

drivers/md/bcache/super.c

1276

bch_write_bdev_super(dc, &cl);

drivers/md/bcache/super.c

1283

bcache_device_attach(&dc->disk, c, u - c->uuids);

drivers/md/bcache/super.c

1284

list_move(&dc->list, &c->cached_devs);

drivers/md/bcache/super.c

1292

refcount_set(&dc->count, 1);

drivers/md/bcache/super.c

1295

down_write(&dc->writeback_lock);

drivers/md/bcache/super.c

1296

if (bch_cached_dev_writeback_start(dc)) {

drivers/md/bcache/super.c

1297

up_write(&dc->writeback_lock);

drivers/md/bcache/super.c

1299

dc->disk.disk->disk_name);

drivers/md/bcache/super.c

1303

if (BDEV_STATE(&dc->sb) == BDEV_STATE_DIRTY) {

drivers/md/bcache/super.c

1304

atomic_set(&dc->has_dirty, 1);

drivers/md/bcache/super.c

1305

bch_writeback_queue(dc);

drivers/md/bcache/super.c

1308

bch_sectors_dirty_init(&dc->disk);

drivers/md/bcache/super.c

1310

ret = bch_cached_dev_run(dc);

drivers/md/bcache/super.c

1312

up_write(&dc->writeback_lock);

drivers/md/bcache/super.c

1319

kthread_stop(dc->writeback_thread);

drivers/md/bcache/super.c

1320

cancel_writeback_rate_update_dwork(dc);

drivers/md/bcache/super.c

1321

pr_err("Couldn't run cached device %pg\n", dc->bdev);

drivers/md/bcache/super.c

1325

bcache_device_link(&dc->disk, c, "bdev");

drivers/md/bcache/super.c

1331

set_disk_ro(dc->disk.disk, 1);

drivers/md/bcache/super.c

1335

up_write(&dc->writeback_lock);

drivers/md/bcache/super.c

1338

dc->bdev,

drivers/md/bcache/super.c

1339

dc->disk.disk->disk_name,

drivers/md/bcache/super.c

1340

dc->disk.c->set_uuid);

drivers/md/bcache/super.c

1347

struct cached_dev *dc = container_of(kobj, struct cached_dev,

drivers/md/bcache/super.c

1349

kfree(dc);

drivers/md/bcache/super.c

1355

closure_type(dc, struct cached_dev, disk.cl);

drivers/md/bcache/super.c

1357

if (test_and_clear_bit(BCACHE_DEV_WB_RUNNING, &dc->disk.flags))

drivers/md/bcache/super.c

1358

cancel_writeback_rate_update_dwork(dc);

drivers/md/bcache/super.c

1360

if (!IS_ERR_OR_NULL(dc->writeback_thread))

drivers/md/bcache/super.c

1361

kthread_stop(dc->writeback_thread);

drivers/md/bcache/super.c

1362

if (!IS_ERR_OR_NULL(dc->status_update_thread))

drivers/md/bcache/super.c

1363

kthread_stop(dc->status_update_thread);

drivers/md/bcache/super.c

1367

if (atomic_read(&dc->running)) {

drivers/md/bcache/super.c

1368

bd_unlink_disk_holder(dc->bdev, dc->disk.disk);

drivers/md/bcache/super.c

1369

del_gendisk(dc->disk.disk);

drivers/md/bcache/super.c

1371

bcache_device_free(&dc->disk);

drivers/md/bcache/super.c

1372

list_del(&dc->list);

drivers/md/bcache/super.c

1381

down(&dc->sb_write_mutex);

drivers/md/bcache/super.c

1382

up(&dc->sb_write_mutex);

drivers/md/bcache/super.c

1384

if (dc->sb_disk)

drivers/md/bcache/super.c

1385

folio_put(virt_to_folio(dc->sb_disk));

drivers/md/bcache/super.c

1387

if (dc->bdev_file)

drivers/md/bcache/super.c

1388

fput(dc->bdev_file);

drivers/md/bcache/super.c

1392

kobject_put(&dc->disk.kobj);

drivers/md/bcache/super.c

1397

closure_type(dc, struct cached_dev, disk.cl);

drivers/md/bcache/super.c

1398

struct bcache_device *d = &dc->disk;

drivers/md/bcache/super.c

1404

bch_cache_accounting_destroy(&dc->accounting);

drivers/md/bcache/super.c

1410

static int cached_dev_init(struct cached_dev *dc, unsigned int block_size)

drivers/md/bcache/super.c

1414

struct request_queue *q = bdev_get_queue(dc->bdev);

drivers/md/bcache/super.c

1417

INIT_LIST_HEAD(&dc->list);

drivers/md/bcache/super.c

1418

closure_init(&dc->disk.cl, NULL);

drivers/md/bcache/super.c

1419

set_closure_fn(&dc->disk.cl, cached_dev_flush, system_percpu_wq);

drivers/md/bcache/super.c

1420

kobject_init(&dc->disk.kobj, &bch_cached_dev_ktype);

drivers/md/bcache/super.c

1421

INIT_WORK(&dc->detach, cached_dev_detach_finish);

drivers/md/bcache/super.c

1422

sema_init(&dc->sb_write_mutex, 1);

drivers/md/bcache/super.c

1423

INIT_LIST_HEAD(&dc->io_lru);

drivers/md/bcache/super.c

1424

spin_lock_init(&dc->io_lock);

drivers/md/bcache/super.c

1425

bch_cache_accounting_init(&dc->accounting, &dc->disk.cl);

drivers/md/bcache/super.c

1427

dc->sequential_cutoff = 4 << 20;

drivers/md/bcache/super.c

1429

for (io = dc->io; io < dc->io + RECENT_IO; io++) {

drivers/md/bcache/super.c

1430

list_add(&io->lru, &dc->io_lru);

drivers/md/bcache/super.c

1431

hlist_add_head(&io->hash, dc->io_hash + RECENT_IO);

drivers/md/bcache/super.c

1434

if (bdev_io_opt(dc->bdev))

drivers/md/bcache/super.c

1435

dc->partial_stripes_expensive = !!(q->limits.features &

drivers/md/bcache/super.c

1438

ret = bcache_device_init(&dc->disk, block_size,

drivers/md/bcache/super.c

1439

bdev_nr_sectors(dc->bdev) - dc->sb.data_offset,

drivers/md/bcache/super.c

1440

dc->bdev, &bcache_cached_ops);

drivers/md/bcache/super.c

1444

atomic_set(&dc->io_errors, 0);

drivers/md/bcache/super.c

1445

dc->io_disable = false;

drivers/md/bcache/super.c

1446

dc->error_limit = DEFAULT_CACHED_DEV_ERROR_LIMIT;

drivers/md/bcache/super.c

1448

dc->stop_when_cache_set_failed = BCH_CACHED_DEV_STOP_AUTO;

drivers/md/bcache/super.c

1450

bch_cached_dev_request_init(dc);

drivers/md/bcache/super.c

1451

bch_cached_dev_writeback_init(dc);

drivers/md/bcache/super.c

1459

struct cached_dev *dc)

drivers/md/bcache/super.c

1465

memcpy(&dc->sb, sb, sizeof(struct cache_sb));

drivers/md/bcache/super.c

1466

dc->bdev_file = bdev_file;

drivers/md/bcache/super.c

1467

dc->bdev = file_bdev(bdev_file);

drivers/md/bcache/super.c

1468

dc->sb_disk = sb_disk;

drivers/md/bcache/super.c

1470

if (cached_dev_init(dc, sb->block_size << 9))

drivers/md/bcache/super.c

1474

if (kobject_add(&dc->disk.kobj, bdev_kobj(dc->bdev), "bcache"))

drivers/md/bcache/super.c

1476

if (bch_cache_accounting_add_kobjs(&dc->accounting, &dc->disk.kobj))

drivers/md/bcache/super.c

1479

pr_info("registered backing device %pg\n", dc->bdev);

drivers/md/bcache/super.c

1481

list_add(&dc->list, &uncached_devices);

drivers/md/bcache/super.c

1484

bch_cached_dev_attach(dc, c, NULL);

drivers/md/bcache/super.c

1486

if (BDEV_STATE(&dc->sb) == BDEV_STATE_NONE ||

drivers/md/bcache/super.c

1487

BDEV_STATE(&dc->sb) == BDEV_STATE_STALE) {

drivers/md/bcache/super.c

1489

ret = bch_cached_dev_run(dc);

drivers/md/bcache/super.c

1496

pr_notice("error %pg: %s\n", dc->bdev, err);

drivers/md/bcache/super.c

1497

bcache_device_stop(&dc->disk);

drivers/md/bcache/super.c

1619

bool bch_cached_dev_error(struct cached_dev *dc)

drivers/md/bcache/super.c

1621

if (!dc || test_bit(BCACHE_DEV_CLOSING, &dc->disk.flags))

drivers/md/bcache/super.c

1624

dc->io_disable = true;

drivers/md/bcache/super.c

1629

dc->disk.disk->disk_name, dc->bdev);

drivers/md/bcache/super.c

1631

bcache_device_stop(&dc->disk);

drivers/md/bcache/super.c

1786

struct cached_dev *dc)

drivers/md/bcache/super.c

1788

if (dc->stop_when_cache_set_failed == BCH_CACHED_DEV_STOP_ALWAYS) {

drivers/md/bcache/super.c

1792

} else if (atomic_read(&dc->has_dirty)) {

drivers/md/bcache/super.c

1810

dc->io_disable = true;

drivers/md/bcache/super.c

1827

struct cached_dev *dc;

drivers/md/bcache/super.c

1840

dc = container_of(d, struct cached_dev, disk);

drivers/md/bcache/super.c

1841

bch_cached_dev_detach(dc);

drivers/md/bcache/super.c

1843

conditional_stop_bcache_device(c, d, dc);

drivers/md/bcache/super.c

1989

struct cached_dev *dc, *t;

drivers/md/bcache/super.c

2140

list_for_each_entry_safe(dc, t, &uncached_devices, list)

drivers/md/bcache/super.c

2141

bch_cached_dev_attach(dc, c, NULL);

drivers/md/bcache/super.c

2458

struct cached_dev *dc, *t;

drivers/md/bcache/super.c

2461

list_for_each_entry_safe(dc, t, &c->cached_devs, list)

drivers/md/bcache/super.c

2462

if (dc->bdev->bd_dev == dev)

drivers/md/bcache/super.c

2464

list_for_each_entry_safe(dc, t, &uncached_devices, list)

drivers/md/bcache/super.c

2465

if (dc->bdev->bd_dev == dev)

drivers/md/bcache/super.c

2704

struct cached_dev *dc;

drivers/md/bcache/super.c

2714

struct cached_dev *dc, *tdc;

drivers/md/bcache/super.c

2719

list_for_each_entry_safe(dc, tdc, &uncached_devices, list) {

drivers/md/bcache/super.c

2723

pdev->dc = dc;

drivers/md/bcache/super.c

2728

char *pdev_set_uuid = pdev->dc->sb.set_uuid;

drivers/md/bcache/super.c

2744

bcache_device_stop(&pdev->dc->disk);

drivers/md/bcache/super.c

2764

struct cached_dev *dc, *tdc;

drivers/md/bcache/super.c

2804

list_for_each_entry_safe(dc, tdc, &uncached_devices, list)

drivers/md/bcache/super.c

2805

bcache_device_stop(&dc->disk);

drivers/md/bcache/super.c

281

struct cached_dev *dc = bio->bi_private;

drivers/md/bcache/super.c

284

bch_count_backing_io_errors(dc, bio);

drivers/md/bcache/super.c

286

closure_put(&dc->sb_write);

drivers/md/bcache/super.c

331

closure_type(dc, struct cached_dev, sb_write);

drivers/md/bcache/super.c

333

up(&dc->sb_write_mutex);

drivers/md/bcache/super.c

336

void bch_write_bdev_super(struct cached_dev *dc, struct closure *parent)

drivers/md/bcache/super.c

338

struct closure *cl = &dc->sb_write;

drivers/md/bcache/super.c

339

struct bio *bio = &dc->sb_bio;

drivers/md/bcache/super.c

341

down(&dc->sb_write_mutex);

drivers/md/bcache/super.c

344

bio_init(bio, dc->bdev, dc->sb_bv, 1, 0);

drivers/md/bcache/super.c

346

bio->bi_private = dc;

drivers/md/bcache/super.c

350

__write_super(&dc->sb, dc->sb_disk, bio);

drivers/md/bcache/sysfs.c

172

struct cached_dev *dc = container_of(kobj, struct cached_dev,

drivers/md/bcache/sysfs.c

175

int wb = dc->writeback_running;

drivers/md/bcache/sysfs.c

177

#define var(stat) (dc->stat)

drivers/md/bcache/sysfs.c

182

BDEV_CACHE_MODE(&dc->sb));

drivers/md/bcache/sysfs.c

187

dc->cache_readahead_policy);

drivers/md/bcache/sysfs.c

192

dc->stop_when_cache_set_failed);

drivers/md/bcache/sysfs.c

195

sysfs_printf(data_csum, "%i", dc->disk.data_csum);

drivers/md/bcache/sysfs.c

204

wb ? atomic_long_read(&dc->writeback_rate.rate) << 9 : 0);

drivers/md/bcache/sysfs.c

205

sysfs_printf(io_errors, "%i", atomic_read(&dc->io_errors));

drivers/md/bcache/sysfs.c

206

sysfs_printf(io_error_limit, "%i", dc->error_limit);

drivers/md/bcache/sysfs.c

207

sysfs_printf(io_disable, "%i", dc->io_disable);

drivers/md/bcache/sysfs.c

230

wb ? atomic_long_read(&dc->writeback_rate.rate) << 9

drivers/md/bcache/sysfs.c

232

bch_hprint(dirty, bcache_dev_sectors_dirty(&dc->disk) << 9);

drivers/md/bcache/sysfs.c

233

bch_hprint(target, dc->writeback_rate_target << 9);

drivers/md/bcache/sysfs.c

235

wb ? dc->writeback_rate_proportional << 9 : 0);

drivers/md/bcache/sysfs.c

237

wb ? dc->writeback_rate_integral_scaled << 9 : 0);

drivers/md/bcache/sysfs.c

238

bch_hprint(change, wb ? dc->writeback_rate_change << 9 : 0);

drivers/md/bcache/sysfs.c

239

next_io = wb ? div64_s64(dc->writeback_rate.next-local_clock(),

drivers/md/bcache/sysfs.c

255

bcache_dev_sectors_dirty(&dc->disk) << 9);

drivers/md/bcache/sysfs.c

257

sysfs_hprint(stripe_size, ((uint64_t)dc->disk.stripe_size) << 9);

drivers/md/bcache/sysfs.c

262

sysfs_print(running, atomic_read(&dc->running));

drivers/md/bcache/sysfs.c

263

sysfs_print(state, states[BDEV_STATE(&dc->sb)]);

drivers/md/bcache/sysfs.c

266

memcpy(buf, dc->sb.label, SB_LABEL_SIZE);

drivers/md/bcache/sysfs.c

273

snprintf(buf, BDEVNAME_SIZE + 1, "%pg", dc->bdev);

drivers/md/bcache/sysfs.c

280

snprintf(buf, 36+1, "%pU", dc->sb.uuid);

drivers/md/bcache/sysfs.c

292

struct cached_dev *dc = container_of(kobj, struct cached_dev,

drivers/md/bcache/sysfs.c

302

#define d_strtoul(var) sysfs_strtoul(var, dc->var)

drivers/md/bcache/sysfs.c

303

#define d_strtoul_nonzero(var) sysfs_strtoul_clamp(var, dc->var, 1, INT_MAX)

drivers/md/bcache/sysfs.c

304

#define d_strtoi_h(var) sysfs_hatoi(var, dc->var)

drivers/md/bcache/sysfs.c

306

sysfs_strtoul(data_csum, dc->disk.data_csum);

drivers/md/bcache/sysfs.c

308

sysfs_strtoul_bool(bypass_torture_test, dc->bypass_torture_test);

drivers/md/bcache/sysfs.c

309

sysfs_strtoul_bool(writeback_metadata, dc->writeback_metadata);

drivers/md/bcache/sysfs.c

310

sysfs_strtoul_bool(writeback_running, dc->writeback_running);

drivers/md/bcache/sysfs.c

311

sysfs_strtoul_bool(writeback_consider_fragment, dc->writeback_consider_fragment);

drivers/md/bcache/sysfs.c

312

sysfs_strtoul_clamp(writeback_delay, dc->writeback_delay, 0, UINT_MAX);

drivers/md/bcache/sysfs.c

314

sysfs_strtoul_clamp(writeback_percent, dc->writeback_percent,

drivers/md/bcache/sysfs.c

319

long int v = atomic_long_read(&dc->writeback_rate.rate);

drivers/md/bcache/sysfs.c

324

atomic_long_set(&dc->writeback_rate.rate, v);

drivers/md/bcache/sysfs.c

332

dc->writeback_rate_update_seconds,

drivers/md/bcache/sysfs.c

335

dc->writeback_rate_i_term_inverse,

drivers/md/bcache/sysfs.c

338

dc->writeback_rate_p_term_inverse,

drivers/md/bcache/sysfs.c

341

dc->writeback_rate_fp_term_low,

drivers/md/bcache/sysfs.c

342

1, dc->writeback_rate_fp_term_mid - 1);

drivers/md/bcache/sysfs.c

344

dc->writeback_rate_fp_term_mid,

drivers/md/bcache/sysfs.c

345

dc->writeback_rate_fp_term_low + 1,

drivers/md/bcache/sysfs.c

346

dc->writeback_rate_fp_term_high - 1);

drivers/md/bcache/sysfs.c

348

dc->writeback_rate_fp_term_high,

drivers/md/bcache/sysfs.c

349

dc->writeback_rate_fp_term_mid + 1, UINT_MAX);

drivers/md/bcache/sysfs.c

351

dc->writeback_rate_minimum,

drivers/md/bcache/sysfs.c

354

sysfs_strtoul_clamp(io_error_limit, dc->error_limit, 0, INT_MAX);

drivers/md/bcache/sysfs.c

359

dc->io_disable = v ? 1 : 0;

drivers/md/bcache/sysfs.c

363

dc->sequential_cutoff,

drivers/md/bcache/sysfs.c

367

bch_cache_accounting_clear(&dc->accounting);

drivers/md/bcache/sysfs.c

371

v = bch_cached_dev_run(dc);

drivers/md/bcache/sysfs.c

381

if ((unsigned int) v != BDEV_CACHE_MODE(&dc->sb)) {

drivers/md/bcache/sysfs.c

382

SET_BDEV_CACHE_MODE(&dc->sb, v);

drivers/md/bcache/sysfs.c

383

bch_write_bdev_super(dc, NULL);

drivers/md/bcache/sysfs.c

392

if ((unsigned int) v != dc->cache_readahead_policy)

drivers/md/bcache/sysfs.c

393

dc->cache_readahead_policy = v;

drivers/md/bcache/sysfs.c

401

dc->stop_when_cache_set_failed = v;

drivers/md/bcache/sysfs.c

407

memcpy(dc->sb.label, buf, size);

drivers/md/bcache/sysfs.c

409

dc->sb.label[size] = '\0';

drivers/md/bcache/sysfs.c

410

if (size && dc->sb.label[size - 1] == '\n')

drivers/md/bcache/sysfs.c

411

dc->sb.label[size - 1] = '\0';

drivers/md/bcache/sysfs.c

412

bch_write_bdev_super(dc, NULL);

drivers/md/bcache/sysfs.c

413

if (dc->disk.c) {

drivers/md/bcache/sysfs.c

414

memcpy(dc->disk.c->uuids[dc->disk.id].label,

drivers/md/bcache/sysfs.c

416

bch_uuid_write(dc->disk.c);

drivers/md/bcache/sysfs.c

422

add_uevent_var(env, "CACHED_UUID=%pU", dc->sb.uuid);

drivers/md/bcache/sysfs.c

424

kobject_uevent_env(&disk_to_dev(dc->disk.disk)->kobj,

drivers/md/bcache/sysfs.c

438

v = bch_cached_dev_attach(dc, c, set_uuid);

drivers/md/bcache/sysfs.c

447

if (attr == &sysfs_detach && dc->disk.c)

drivers/md/bcache/sysfs.c

448

bch_cached_dev_detach(dc);

drivers/md/bcache/sysfs.c

451

bcache_device_stop(&dc->disk);

drivers/md/bcache/sysfs.c

458

struct cached_dev *dc = container_of(kobj, struct cached_dev,

drivers/md/bcache/sysfs.c

470

if (IS_ERR_OR_NULL(dc->writeback_thread)) {

drivers/md/bcache/sysfs.c

475

if (dc->writeback_running) {

drivers/md/bcache/sysfs.c

476

dc->writeback_running = false;

drivers/md/bcache/sysfs.c

478

dc->disk.disk->disk_name);

drivers/md/bcache/sysfs.c

485

bch_writeback_queue(dc);

drivers/md/bcache/sysfs.c

493

if ((dc->disk.c != NULL) &&

drivers/md/bcache/sysfs.c

494

(!test_and_set_bit(BCACHE_DEV_WB_RUNNING, &dc->disk.flags)))

drivers/md/bcache/sysfs.c

495

schedule_delayed_work(&dc->writeback_rate_update,

drivers/md/bcache/sysfs.c

496

dc->writeback_rate_update_seconds * HZ);

drivers/md/bcache/writeback.c

101

struct cache_set *c = dc->disk.c;

drivers/md/bcache/writeback.c

1047

void bch_cached_dev_writeback_init(struct cached_dev *dc)

drivers/md/bcache/writeback.c

1049

sema_init(&dc->in_flight, 64);

drivers/md/bcache/writeback.c

105

if (dc->writeback_consider_fragment &&

drivers/md/bcache/writeback.c

1050

init_rwsem(&dc->writeback_lock);

drivers/md/bcache/writeback.c

1051

bch_keybuf_init(&dc->writeback_keys);

drivers/md/bcache/writeback.c

1053

dc->writeback_metadata = true;

drivers/md/bcache/writeback.c

1054

dc->writeback_running = false;

drivers/md/bcache/writeback.c

1055

dc->writeback_consider_fragment = true;

drivers/md/bcache/writeback.c

1056

dc->writeback_percent = 10;

drivers/md/bcache/writeback.c

1057

dc->writeback_delay = 30;

drivers/md/bcache/writeback.c

1058

atomic_long_set(&dc->writeback_rate.rate, 1024);

drivers/md/bcache/writeback.c

1059

dc->writeback_rate_minimum = 8;

drivers/md/bcache/writeback.c

1061

dc->writeback_rate_update_seconds = WRITEBACK_RATE_UPDATE_SECS_DEFAULT;

drivers/md/bcache/writeback.c

1062

dc->writeback_rate_p_term_inverse = 40;

drivers/md/bcache/writeback.c

1063

dc->writeback_rate_fp_term_low = 1;

drivers/md/bcache/writeback.c

1064

dc->writeback_rate_fp_term_mid = 10;

drivers/md/bcache/writeback.c

1065

dc->writeback_rate_fp_term_high = 1000;

drivers/md/bcache/writeback.c

1066

dc->writeback_rate_i_term_inverse = 10000;

drivers/md/bcache/writeback.c

1069

dc->rate_update_retry = 0;

drivers/md/bcache/writeback.c

1071

WARN_ON(test_and_clear_bit(BCACHE_DEV_WB_RUNNING, &dc->disk.flags));

drivers/md/bcache/writeback.c

1072

INIT_DELAYED_WORK(&dc->writeback_rate_update, update_writeback_rate);

drivers/md/bcache/writeback.c

1075

int bch_cached_dev_writeback_start(struct cached_dev *dc)

drivers/md/bcache/writeback.c

1077

dc->writeback_write_wq = alloc_workqueue("bcache_writeback_wq",

drivers/md/bcache/writeback.c

1079

if (!dc->writeback_write_wq)

drivers/md/bcache/writeback.c

1082

cached_dev_get(dc);

drivers/md/bcache/writeback.c

1083

dc->writeback_thread = kthread_create(bch_writeback_thread, dc,

drivers/md/bcache/writeback.c

1085

if (IS_ERR(dc->writeback_thread)) {

drivers/md/bcache/writeback.c

1086

cached_dev_put(dc);

drivers/md/bcache/writeback.c

1087

destroy_workqueue(dc->writeback_write_wq);

drivers/md/bcache/writeback.c

1088

return PTR_ERR(dc->writeback_thread);

drivers/md/bcache/writeback.c

1090

dc->writeback_running = true;

drivers/md/bcache/writeback.c

1092

WARN_ON(test_and_set_bit(BCACHE_DEV_WB_RUNNING, &dc->disk.flags));

drivers/md/bcache/writeback.c

1093

schedule_delayed_work(&dc->writeback_rate_update,

drivers/md/bcache/writeback.c

1094

dc->writeback_rate_update_seconds * HZ);

drivers/md/bcache/writeback.c

1096

bch_writeback_queue(dc);

drivers/md/bcache/writeback.c

113

fp_term = (int64_t)dc->writeback_rate_fp_term_low *

drivers/md/bcache/writeback.c

116

fp_term = (int64_t)dc->writeback_rate_fp_term_mid *

drivers/md/bcache/writeback.c

119

fp_term = (int64_t)dc->writeback_rate_fp_term_high *

drivers/md/bcache/writeback.c

129

if ((error < 0 && dc->writeback_rate_integral > 0) ||

drivers/md/bcache/writeback.c

131

dc->writeback_rate.next + NSEC_PER_MSEC))) {

drivers/md/bcache/writeback.c

142

dc->writeback_rate_integral += error *

drivers/md/bcache/writeback.c

143

dc->writeback_rate_update_seconds;

drivers/md/bcache/writeback.c

146

integral_scaled = div_s64(dc->writeback_rate_integral,

drivers/md/bcache/writeback.c

147

dc->writeback_rate_i_term_inverse);

drivers/md/bcache/writeback.c

150

dc->writeback_rate_minimum, NSEC_PER_SEC);

drivers/md/bcache/writeback.c

152

dc->writeback_rate_proportional = proportional_scaled;

drivers/md/bcache/writeback.c

153

dc->writeback_rate_integral_scaled = integral_scaled;

drivers/md/bcache/writeback.c

154

dc->writeback_rate_change = new_rate -

drivers/md/bcache/writeback.c

155

atomic_long_read(&dc->writeback_rate.rate);

drivers/md/bcache/writeback.c

156

atomic_long_set(&dc->writeback_rate.rate, new_rate);

drivers/md/bcache/writeback.c

157

dc->writeback_rate_target = target;

drivers/md/bcache/writeback.c

208

struct cached_dev *dc)

drivers/md/bcache/writeback.c

224

atomic_long_set(&dc->writeback_rate.rate, INT_MAX);

drivers/md/bcache/writeback.c

227

dc->writeback_rate_proportional = 0;

drivers/md/bcache/writeback.c

228

dc->writeback_rate_integral_scaled = 0;

drivers/md/bcache/writeback.c

229

dc->writeback_rate_change = 0;

drivers/md/bcache/writeback.c

244

struct cached_dev *dc = container_of(to_delayed_work(work),

drivers/md/bcache/writeback.c

247

struct cache_set *c = dc->disk.c;

drivers/md/bcache/writeback.c

253

set_bit(BCACHE_DEV_RATE_DW_RUNNING, &dc->disk.flags);

drivers/md/bcache/writeback.c

261

if (!test_bit(BCACHE_DEV_WB_RUNNING, &dc->disk.flags) ||

drivers/md/bcache/writeback.c

263

clear_bit(BCACHE_DEV_RATE_DW_RUNNING, &dc->disk.flags);

drivers/md/bcache/writeback.c

275

if (atomic_read(&dc->has_dirty) && dc->writeback_percent &&

drivers/md/bcache/writeback.c

276

!set_at_max_writeback_rate(c, dc)) {

drivers/md/bcache/writeback.c

278

if (!down_read_trylock((&dc->writeback_lock))) {

drivers/md/bcache/writeback.c

279

dc->rate_update_retry++;

drivers/md/bcache/writeback.c

280

if (dc->rate_update_retry <=

drivers/md/bcache/writeback.c

283

down_read(&dc->writeback_lock);

drivers/md/bcache/writeback.c

284

dc->rate_update_retry = 0;

drivers/md/bcache/writeback.c

286

__update_writeback_rate(dc);

drivers/md/bcache/writeback.c

288

up_read(&dc->writeback_lock);

drivers/md/bcache/writeback.c

297

if (test_bit(BCACHE_DEV_WB_RUNNING, &dc->disk.flags) &&

drivers/md/bcache/writeback.c

299

schedule_delayed_work(&dc->writeback_rate_update,

drivers/md/bcache/writeback.c

30

static uint64_t __calc_target_rate(struct cached_dev *dc)

drivers/md/bcache/writeback.c

300

dc->writeback_rate_update_seconds * HZ);

drivers/md/bcache/writeback.c

307

clear_bit(BCACHE_DEV_RATE_DW_RUNNING, &dc->disk.flags);

drivers/md/bcache/writeback.c

312

static unsigned int writeback_delay(struct cached_dev *dc,

drivers/md/bcache/writeback.c

315

if (test_bit(BCACHE_DEV_DETACHING, &dc->disk.flags) ||

drivers/md/bcache/writeback.c

316

!dc->writeback_percent)

drivers/md/bcache/writeback.c

319

return bch_next_delay(&dc->writeback_rate, sectors);

drivers/md/bcache/writeback.c

32

struct cache_set *c = dc->disk.c;

drivers/md/bcache/writeback.c

324

struct cached_dev *dc;

drivers/md/bcache/writeback.c

336

if (!io->dc->writeback_percent)

drivers/md/bcache/writeback.c

355

struct cached_dev *dc = io->dc;

drivers/md/bcache/writeback.c

372

atomic_inc(&PTR_BUCKET(dc->disk.c, &w->key, i)->pin);

drivers/md/bcache/writeback.c

374

ret = bch_btree_insert(dc->disk.c, &keys, NULL, &w->key);

drivers/md/bcache/writeback.c

380

? &dc->disk.c->writeback_keys_failed

drivers/md/bcache/writeback.c

381

: &dc->disk.c->writeback_keys_done);

drivers/md/bcache/writeback.c

384

bch_keybuf_del(&dc->writeback_keys, w);

drivers/md/bcache/writeback.c

385

up(&dc->in_flight);

drivers/md/bcache/writeback.c

397

bch_count_backing_io_errors(io->dc, bio);

drivers/md/bcache/writeback.c

407

struct cached_dev *dc = io->dc;

drivers/md/bcache/writeback.c

411

if (atomic_read(&dc->writeback_sequence_next) != io->sequence) {

drivers/md/bcache/writeback.c

413

closure_wait(&dc->writeback_ordering_wait, cl);

drivers/md/bcache/writeback.c

415

if (atomic_read(&dc->writeback_sequence_next) == io->sequence) {

drivers/md/bcache/writeback.c

420

closure_wake_up(&dc->writeback_ordering_wait);

drivers/md/bcache/writeback.c

423

continue_at(cl, write_dirty, io->dc->writeback_write_wq);

drivers/md/bcache/writeback.c

439

bio_set_dev(&io->bio, io->dc->bdev);

drivers/md/bcache/writeback.c

443

closure_bio_submit(io->dc->disk.c, &io->bio, cl);

drivers/md/bcache/writeback.c

446

atomic_set(&dc->writeback_sequence_next, next_sequence);

drivers/md/bcache/writeback.c

447

closure_wake_up(&dc->writeback_ordering_wait);

drivers/md/bcache/writeback.c

449

continue_at(cl, write_dirty_finish, io->dc->writeback_write_wq);

drivers/md/bcache/writeback.c

458

bch_count_io_errors(io->dc->disk.c->cache,

drivers/md/bcache/writeback.c

469

closure_bio_submit(io->dc->disk.c, &io->bio, cl);

drivers/md/bcache/writeback.c

471

continue_at(cl, write_dirty, io->dc->writeback_write_wq);

drivers/md/bcache/writeback.c

474

static void read_dirty(struct cached_dev *dc)

drivers/md/bcache/writeback.c

48

div64_u64(bdev_nr_sectors(dc->bdev) << WRITEBACK_SHARE_SHIFT,

drivers/md/bcache/writeback.c

484

BUG_ON(!llist_empty(&dc->writeback_ordering_wait.list));

drivers/md/bcache/writeback.c

485

atomic_set(&dc->writeback_sequence_next, sequence);

drivers/md/bcache/writeback.c

493

next = bch_keybuf_next(&dc->writeback_keys);

drivers/md/bcache/writeback.c

496

!test_bit(CACHE_SET_IO_DISABLE, &dc->disk.c->flags) &&

drivers/md/bcache/writeback.c

502

BUG_ON(ptr_stale(dc->disk.c, &next->key, 0));

drivers/md/bcache/writeback.c

52

div_u64(cache_sectors * dc->writeback_percent, 100);

drivers/md/bcache/writeback.c

533

} while ((next = bch_keybuf_next(&dc->writeback_keys)));

drivers/md/bcache/writeback.c

546

io->dc = dc;

drivers/md/bcache/writeback.c

552

bio_set_dev(&io->bio, dc->disk.c->cache->bdev);

drivers/md/bcache/writeback.c

560

down(&dc->in_flight);

drivers/md/bcache/writeback.c

570

delay = writeback_delay(dc, size);

drivers/md/bcache/writeback.c

573

!test_bit(CACHE_SET_IO_DISABLE, &dc->disk.c->flags) &&

drivers/md/bcache/writeback.c

576

delay = writeback_delay(dc, 0);

drivers/md/bcache/writeback.c

584

bch_keybuf_del(&dc->writeback_keys, w);

drivers/md/bcache/writeback.c

61

static void __update_writeback_rate(struct cached_dev *dc)

drivers/md/bcache/writeback.c

643

struct cached_dev *dc = container_of(buf,

drivers/md/bcache/writeback.c

647

BUG_ON(KEY_INODE(k) != dc->disk.id);

drivers/md/bcache/writeback.c

652

static void refill_full_stripes(struct cached_dev *dc)

drivers/md/bcache/writeback.c

654

struct keybuf *buf = &dc->writeback_keys;

drivers/md/bcache/writeback.c

659

stripe = offset_to_stripe(&dc->disk, KEY_OFFSET(&buf->last_scanned));

drivers/md/bcache/writeback.c

666

stripe = find_next_bit(dc->disk.full_dirty_stripes,

drivers/md/bcache/writeback.c

667

dc->disk.nr_stripes, stripe);

drivers/md/bcache/writeback.c

669

if (stripe == dc->disk.nr_stripes)

drivers/md/bcache/writeback.c

672

next_stripe = find_next_zero_bit(dc->disk.full_dirty_stripes,

drivers/md/bcache/writeback.c

673

dc->disk.nr_stripes, stripe);

drivers/md/bcache/writeback.c

675

buf->last_scanned = KEY(dc->disk.id,

drivers/md/bcache/writeback.c

676

stripe * dc->disk.stripe_size, 0);

drivers/md/bcache/writeback.c

678

bch_refill_keybuf(dc->disk.c, buf,

drivers/md/bcache/writeback.c

679

&KEY(dc->disk.id,

drivers/md/bcache/writeback.c

680

next_stripe * dc->disk.stripe_size, 0),

drivers/md/bcache/writeback.c

691

if (stripe == dc->disk.nr_stripes) {

drivers/md/bcache/writeback.c

701

static bool refill_dirty(struct cached_dev *dc)

drivers/md/bcache/writeback.c

703

struct keybuf *buf = &dc->writeback_keys;

drivers/md/bcache/writeback.c

704

struct bkey start = KEY(dc->disk.id, 0, 0);

drivers/md/bcache/writeback.c

705

struct bkey end = KEY(dc->disk.id, MAX_KEY_OFFSET, 0);

drivers/md/bcache/writeback.c

717

if (dc->partial_stripes_expensive) {

drivers/md/bcache/writeback.c

718

refill_full_stripes(dc);

drivers/md/bcache/writeback.c

724

bch_refill_keybuf(dc->disk.c, buf, &end, dirty_pred);

drivers/md/bcache/writeback.c

734

bch_refill_keybuf(dc->disk.c, buf, &start_pos, dirty_pred);

drivers/md/bcache/writeback.c

741

struct cached_dev *dc = arg;

drivers/md/bcache/writeback.c

742

struct cache_set *c = dc->disk.c;

drivers/md/bcache/writeback.c

745

bch_ratelimit_reset(&dc->writeback_rate);

drivers/md/bcache/writeback.c

749

down_write(&dc->writeback_lock);

drivers/md/bcache/writeback.c

758

if (!test_bit(BCACHE_DEV_DETACHING, &dc->disk.flags) &&

drivers/md/bcache/writeback.c

759

(!atomic_read(&dc->has_dirty) || !dc->writeback_running)) {

drivers/md/bcache/writeback.c

760

up_write(&dc->writeback_lock);

drivers/md/bcache/writeback.c

773

searched_full_index = refill_dirty(dc);

drivers/md/bcache/writeback.c

776

RB_EMPTY_ROOT(&dc->writeback_keys.keys)) {

drivers/md/bcache/writeback.c

777

atomic_set(&dc->has_dirty, 0);

drivers/md/bcache/writeback.c

778

SET_BDEV_STATE(&dc->sb, BDEV_STATE_CLEAN);

drivers/md/bcache/writeback.c

779

bch_write_bdev_super(dc, NULL);

drivers/md/bcache/writeback.c

786

if (test_bit(BCACHE_DEV_DETACHING, &dc->disk.flags)) {

drivers/md/bcache/writeback.c

790

memset(&dc->sb.set_uuid, 0, 16);

drivers/md/bcache/writeback.c

791

SET_BDEV_STATE(&dc->sb, BDEV_STATE_NONE);

drivers/md/bcache/writeback.c

793

bch_write_bdev_super(dc, &cl);

drivers/md/bcache/writeback.c

796

up_write(&dc->writeback_lock);

drivers/md/bcache/writeback.c

817

up_write(&dc->writeback_lock);

drivers/md/bcache/writeback.c

819

read_dirty(dc);

drivers/md/bcache/writeback.c

822

unsigned int delay = dc->writeback_delay * HZ;

drivers/md/bcache/writeback.c

827

!test_bit(BCACHE_DEV_DETACHING, &dc->disk.flags))

drivers/md/bcache/writeback.c

83

int64_t target = __calc_target_rate(dc);

drivers/md/bcache/writeback.c

830

bch_ratelimit_reset(&dc->writeback_rate);

drivers/md/bcache/writeback.c

834

if (dc->writeback_write_wq)

drivers/md/bcache/writeback.c

835

destroy_workqueue(dc->writeback_write_wq);

drivers/md/bcache/writeback.c

837

cached_dev_put(dc);

drivers/md/bcache/writeback.c

84

int64_t dirty = bcache_dev_sectors_dirty(&dc->disk);

drivers/md/bcache/writeback.c

87

div_s64(error, dc->writeback_rate_p_term_inverse);

drivers/md/bcache/writeback.h

102

static inline bool should_writeback(struct cached_dev *dc, struct bio *bio,

drivers/md/bcache/writeback.h

105

unsigned int in_use = dc->disk.c->gc_stats.in_use;

drivers/md/bcache/writeback.h

108

test_bit(BCACHE_DEV_DETACHING, &dc->disk.flags) ||

drivers/md/bcache/writeback.h

115

if (dc->partial_stripes_expensive &&

drivers/md/bcache/writeback.h

116

bcache_dev_stripe_dirty(dc, bio->bi_iter.bi_sector,

drivers/md/bcache/writeback.h

128

static inline void bch_writeback_queue(struct cached_dev *dc)

drivers/md/bcache/writeback.h

130

if (!IS_ERR_OR_NULL(dc->writeback_thread))

drivers/md/bcache/writeback.h

131

wake_up_process(dc->writeback_thread);

drivers/md/bcache/writeback.h

134

static inline void bch_writeback_add(struct cached_dev *dc)

drivers/md/bcache/writeback.h

136

if (!atomic_read(&dc->has_dirty) &&

drivers/md/bcache/writeback.h

137

!atomic_xchg(&dc->has_dirty, 1)) {

drivers/md/bcache/writeback.h

138

if (BDEV_STATE(&dc->sb) != BDEV_STATE_DIRTY) {

drivers/md/bcache/writeback.h

139

SET_BDEV_STATE(&dc->sb, BDEV_STATE_DIRTY);

drivers/md/bcache/writeback.h

141

bch_write_bdev_super(dc, NULL);

drivers/md/bcache/writeback.h

144

bch_writeback_queue(dc);

drivers/md/bcache/writeback.h

152

void bch_cached_dev_writeback_init(struct cached_dev *dc);

drivers/md/bcache/writeback.h

153

int bch_cached_dev_writeback_start(struct cached_dev *dc);

drivers/md/bcache/writeback.h

78

static inline bool bcache_dev_stripe_dirty(struct cached_dev *dc,

drivers/md/bcache/writeback.h

82

int stripe = offset_to_stripe(&dc->disk, offset);

drivers/md/bcache/writeback.h

88

if (atomic_read(dc->disk.stripe_sectors_dirty + stripe))

drivers/md/bcache/writeback.h

91

if (nr_sectors <= dc->disk.stripe_size)

drivers/md/bcache/writeback.h

94

nr_sectors -= dc->disk.stripe_size;

drivers/md/dm-delay.c

110

if (!delay_is_fast(dc)) {

drivers/md/dm-delay.c

119

spin_lock(&dc->delayed_bios_lock);

drivers/md/dm-delay.c

120

list_splice(&local_list, &dc->delayed_bios);

drivers/md/dm-delay.c

121

spin_unlock(&dc->delayed_bios_lock);

drivers/md/dm-delay.c

122

mutex_unlock(&dc->process_bios_lock);

drivers/md/dm-delay.c

125

queue_timeout(dc, next_expires);

drivers/md/dm-delay.c

132

struct delay_c *dc = data;

drivers/md/dm-delay.c

135

flush_delayed_bios(dc, false);

drivers/md/dm-delay.c

136

spin_lock(&dc->delayed_bios_lock);

drivers/md/dm-delay.c

137

if (unlikely(list_empty(&dc->delayed_bios))) {

drivers/md/dm-delay.c

139

spin_unlock(&dc->delayed_bios_lock);

drivers/md/dm-delay.c

142

spin_unlock(&dc->delayed_bios_lock);

drivers/md/dm-delay.c

143

fsleep(dc->worker_sleep_us);

drivers/md/dm-delay.c

153

struct delay_c *dc;

drivers/md/dm-delay.c

155

dc = container_of(work, struct delay_c, flush_expired_bios);

drivers/md/dm-delay.c

156

flush_delayed_bios(dc, false);

drivers/md/dm-delay.c

161

struct delay_c *dc = ti->private;

drivers/md/dm-delay.c

163

if (dc->kdelayd_wq) {

drivers/md/dm-delay.c

164

timer_shutdown_sync(&dc->delay_timer);

drivers/md/dm-delay.c

165

destroy_workqueue(dc->kdelayd_wq);

drivers/md/dm-delay.c

168

if (dc->read.dev)

drivers/md/dm-delay.c

169

dm_put_device(ti, dc->read.dev);

drivers/md/dm-delay.c

170

if (dc->write.dev)

drivers/md/dm-delay.c

171

dm_put_device(ti, dc->write.dev);

drivers/md/dm-delay.c

172

if (dc->flush.dev)

drivers/md/dm-delay.c

173

dm_put_device(ti, dc->flush.dev);

drivers/md/dm-delay.c

174

if (dc->worker)

drivers/md/dm-delay.c

175

kthread_stop(dc->worker);

drivers/md/dm-delay.c

177

mutex_destroy(&dc->process_bios_lock);

drivers/md/dm-delay.c

179

kfree(dc);

drivers/md/dm-delay.c

218

struct delay_c *dc;

drivers/md/dm-delay.c

227

dc = kzalloc_obj(*dc);

drivers/md/dm-delay.c

228

if (!dc) {

drivers/md/dm-delay.c

233

ti->private = dc;

drivers/md/dm-delay.c

234

INIT_LIST_HEAD(&dc->delayed_bios);

drivers/md/dm-delay.c

235

mutex_init(&dc->process_bios_lock);

drivers/md/dm-delay.c

236

spin_lock_init(&dc->delayed_bios_lock);

drivers/md/dm-delay.c

237

dc->may_delay = true;

drivers/md/dm-delay.c

238

dc->argc = argc;

drivers/md/dm-delay.c

240

ret = delay_class_ctr(ti, &dc->read, argv);

drivers/md/dm-delay.c

243

min_delay = max_delay = dc->read.delay;

drivers/md/dm-delay.c

246

ret = delay_class_ctr(ti, &dc->write, argv);

drivers/md/dm-delay.c

249

ret = delay_class_ctr(ti, &dc->flush, argv);

drivers/md/dm-delay.c

255

ret = delay_class_ctr(ti, &dc->write, argv + 3);

drivers/md/dm-delay.c

258

max_delay = max(max_delay, dc->write.delay);

drivers/md/dm-delay.c

259

min_delay = min_not_zero(min_delay, dc->write.delay);

drivers/md/dm-delay.c

262

ret = delay_class_ctr(ti, &dc->flush, argv + 3);

drivers/md/dm-delay.c

268

ret = delay_class_ctr(ti, &dc->flush, argv + 6);

drivers/md/dm-delay.c

271

max_delay = max(max_delay, dc->flush.delay);

drivers/md/dm-delay.c

272

min_delay = min_not_zero(min_delay, dc->flush.delay);

drivers/md/dm-delay.c

277

dc->worker_sleep_us = 1000;

drivers/md/dm-delay.c

279

dc->worker_sleep_us = (min_delay * 1000) >> SLEEP_SHIFT;

drivers/md/dm-delay.c

284

dc->worker = kthread_run(&flush_worker_fn, dc, "dm-delay-flush-worker");

drivers/md/dm-delay.c

285

if (IS_ERR(dc->worker)) {

drivers/md/dm-delay.c

286

ret = PTR_ERR(dc->worker);

drivers/md/dm-delay.c

287

dc->worker = NULL;

drivers/md/dm-delay.c

291

timer_setup(&dc->delay_timer, handle_delayed_timer, 0);

drivers/md/dm-delay.c

292

INIT_WORK(&dc->flush_expired_bios, flush_expired_bios);

drivers/md/dm-delay.c

293

dc->kdelayd_wq = alloc_workqueue("kdelayd",

drivers/md/dm-delay.c

296

if (!dc->kdelayd_wq) {

drivers/md/dm-delay.c

314

static int delay_bio(struct delay_c *dc, struct delay_class *c, struct bio *bio)

drivers/md/dm-delay.c

324

delayed->context = dc;

drivers/md/dm-delay.c

327

spin_lock(&dc->delayed_bios_lock);

drivers/md/dm-delay.c

328

if (unlikely(!dc->may_delay)) {

drivers/md/dm-delay.c

329

spin_unlock(&dc->delayed_bios_lock);

drivers/md/dm-delay.c

333

list_add_tail(&delayed->list, &dc->delayed_bios);

drivers/md/dm-delay.c

334

spin_unlock(&dc->delayed_bios_lock);

drivers/md/dm-delay.c

336

if (delay_is_fast(dc))

drivers/md/dm-delay.c

337

wake_up_process(dc->worker);

drivers/md/dm-delay.c

339

queue_timeout(dc, expires);

drivers/md/dm-delay.c

346

struct delay_c *dc = ti->private;

drivers/md/dm-delay.c

348

spin_lock(&dc->delayed_bios_lock);

drivers/md/dm-delay.c

349

dc->may_delay = false;

drivers/md/dm-delay.c

350

spin_unlock(&dc->delayed_bios_lock);

drivers/md/dm-delay.c

352

if (!delay_is_fast(dc))

drivers/md/dm-delay.c

353

timer_delete(&dc->delay_timer);

drivers/md/dm-delay.c

354

flush_delayed_bios(dc, true);

drivers/md/dm-delay.c

359

struct delay_c *dc = ti->private;

drivers/md/dm-delay.c

361

dc->may_delay = true;

drivers/md/dm-delay.c

366

struct delay_c *dc = ti->private;

drivers/md/dm-delay.c

372

c = &dc->flush;

drivers/md/dm-delay.c

374

c = &dc->write;

drivers/md/dm-delay.c

376

c = &dc->read;

drivers/md/dm-delay.c

382

return delay_bio(dc, c, bio);

drivers/md/dm-delay.c

389

struct delay_c *dc = ti->private;

drivers/md/dm-delay.c

390

struct delay_class *c = &dc->read;

drivers/md/dm-delay.c

406

struct delay_c *dc = ti->private;

drivers/md/dm-delay.c

411

DMEMIT("%u %u %u", dc->read.ops, dc->write.ops, dc->flush.ops);

drivers/md/dm-delay.c

415

DMEMIT_DELAY_CLASS(&dc->read);

drivers/md/dm-delay.c

416

if (dc->argc >= 6) {

drivers/md/dm-delay.c

418

DMEMIT_DELAY_CLASS(&dc->write);

drivers/md/dm-delay.c

420

if (dc->argc >= 9) {

drivers/md/dm-delay.c

422

DMEMIT_DELAY_CLASS(&dc->flush);

drivers/md/dm-delay.c

435

struct delay_c *dc = ti->private;

drivers/md/dm-delay.c

438

ret = fn(ti, dc->read.dev, dc->read.start, ti->len, data);

drivers/md/dm-delay.c

441

ret = fn(ti, dc->write.dev, dc->write.start, ti->len, data);

drivers/md/dm-delay.c

444

ret = fn(ti, dc->flush.dev, dc->flush.start, ti->len, data);

drivers/md/dm-delay.c

59

struct delay_c *dc = timer_container_of(dc, t, delay_timer);

drivers/md/dm-delay.c

61

queue_work(dc->kdelayd_wq, &dc->flush_expired_bios);

drivers/md/dm-delay.c

64

static void queue_timeout(struct delay_c *dc, unsigned long expires)

drivers/md/dm-delay.c

66

timer_reduce(&dc->delay_timer, expires);

drivers/md/dm-delay.c

69

static inline bool delay_is_fast(struct delay_c *dc)

drivers/md/dm-delay.c

71

return !!dc->worker;

drivers/md/dm-delay.c

86

static void flush_delayed_bios(struct delay_c *dc, bool flush_all)

drivers/md/dm-delay.c

95

mutex_lock(&dc->process_bios_lock);

drivers/md/dm-delay.c

96

spin_lock(&dc->delayed_bios_lock);

drivers/md/dm-delay.c

97

list_replace_init(&dc->delayed_bios, &local_list);

drivers/md/dm-delay.c

98

spin_unlock(&dc->delayed_bios_lock);

drivers/media/dvb-frontends/dib0090.c

157

const struct dc_calibration *dc;

drivers/media/dvb-frontends/dib0090.c

1659

if (state->dc->addr == 0x07)

drivers/media/dvb-frontends/dib0090.c

1664

*val &= ~(0x1f << state->dc->offset);

drivers/media/dvb-frontends/dib0090.c

1665

*val |= state->step << state->dc->offset;

drivers/media/dvb-frontends/dib0090.c

1667

dib0090_write_reg(state, state->dc->addr, *val);

drivers/media/dvb-frontends/dib0090.c

1691

state->dc = dc_table;

drivers/media/dvb-frontends/dib0090.c

1694

state->dc = dc_p1g_table;

drivers/media/dvb-frontends/dib0090.c

1699

(state->dc->i == 1) ? "I" : "Q");

drivers/media/dvb-frontends/dib0090.c

1700

dib0090_write_reg(state, 0x01, state->dc->bb1);

drivers/media/dvb-frontends/dib0090.c

1701

dib0090_write_reg(state, 0x07, state->bb7 | (state->dc->i << 7));

drivers/media/dvb-frontends/dib0090.c

1731

if (state->dc->pga && state->adc_diff < 0)

drivers/media/dvb-frontends/dib0090.c

1733

if (state->dc->pga == 0 && state->adc_diff > 0)

drivers/media/dvb-frontends/dib0090.c

1752

state->dc->addr, state->adc_diff, state->step);

drivers/media/dvb-frontends/dib0090.c

1754

state->dc++;

drivers/media/dvb-frontends/dib0090.c

1755

if (state->dc->addr == 0) /* done */

drivers/media/pci/ivtv/ivtv-ioctl.c

232

struct v4l2_decoder_cmd *dc, int try)

drivers/media/pci/ivtv/ivtv-ioctl.c

239

switch (dc->cmd) {

drivers/media/pci/ivtv/ivtv-ioctl.c

241

dc->flags &= V4L2_DEC_CMD_START_MUTE_AUDIO;

drivers/media/pci/ivtv/ivtv-ioctl.c

242

dc->start.speed = ivtv_validate_speed(itv->speed, dc->start.speed);

drivers/media/pci/ivtv/ivtv-ioctl.c

243

if (dc->start.speed < 0)

drivers/media/pci/ivtv/ivtv-ioctl.c

244

dc->start.format = V4L2_DEC_START_FMT_GOP;

drivers/media/pci/ivtv/ivtv-ioctl.c

246

dc->start.format = V4L2_DEC_START_FMT_NONE;

drivers/media/pci/ivtv/ivtv-ioctl.c

247

if (dc->start.speed != 500 && dc->start.speed != 1500)

drivers/media/pci/ivtv/ivtv-ioctl.c

248

dc->flags = dc->start.speed == 1000 ? 0 :

drivers/media/pci/ivtv/ivtv-ioctl.c

252

itv->speed_mute_audio = dc->flags & V4L2_DEC_CMD_START_MUTE_AUDIO;

drivers/media/pci/ivtv/ivtv-ioctl.c

259

return ivtv_start_decoding(id, dc->start.speed);

drivers/media/pci/ivtv/ivtv-ioctl.c

263

dc->flags &= V4L2_DEC_CMD_STOP_IMMEDIATELY | V4L2_DEC_CMD_STOP_TO_BLACK;

drivers/media/pci/ivtv/ivtv-ioctl.c

264

if (dc->flags & V4L2_DEC_CMD_STOP_IMMEDIATELY)

drivers/media/pci/ivtv/ivtv-ioctl.c

265

dc->stop.pts = 0;

drivers/media/pci/ivtv/ivtv-ioctl.c

273

return ivtv_stop_v4l2_decode_stream(s, dc->flags, dc->stop.pts);

drivers/media/pci/ivtv/ivtv-ioctl.c

276

dc->flags &= V4L2_DEC_CMD_PAUSE_TO_BLACK;

drivers/media/pci/ivtv/ivtv-ioctl.c

284

(dc->flags & V4L2_DEC_CMD_PAUSE_TO_BLACK) ? 1 : 0);

drivers/media/pci/ivtv/ivtv-ioctl.c

290

dc->flags = 0;

drivers/media/platform/chips-media/coda/coda-common.c

1204

struct v4l2_decoder_cmd *dc)

drivers/media/platform/chips-media/coda/coda-common.c

1214

ret = v4l2_m2m_ioctl_try_decoder_cmd(file, fh, dc);

drivers/media/platform/chips-media/coda/coda-common.c

1218

switch (dc->cmd) {

drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c

893

static int wave5_vpu_dec_decoder_cmd(struct file *file, void *fh, struct v4l2_decoder_cmd *dc)

drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c

899

dev_dbg(inst->dev->dev, "decoder command: %u\n", dc->cmd);

drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c

901

ret = v4l2_m2m_ioctl_try_decoder_cmd(file, fh, dc);

drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c

905

switch (dc->cmd) {

drivers/media/rc/ir-spi.c

131

u8 dc;

drivers/media/rc/ir-spi.c

155

ret = device_property_read_u8(dev, "duty-cycle", &dc);

drivers/media/rc/ir-spi.c

157

dc = 50;

drivers/media/rc/ir-spi.c

163

ir_spi_set_duty_cycle(idata->rc, dc);

drivers/media/test-drivers/vicodec/vicodec-core.c

1234

struct v4l2_decoder_cmd *dc)

drivers/media/test-drivers/vicodec/vicodec-core.c

1245

ret = v4l2_m2m_ioctl_try_decoder_cmd(file, priv, dc);

drivers/media/test-drivers/vicodec/vicodec-core.c

1252

ret = v4l2_m2m_ioctl_decoder_cmd(file, priv, dc);

drivers/media/test-drivers/vicodec/vicodec-core.c

1256

if (dc->cmd == V4L2_DEC_CMD_STOP &&

drivers/media/test-drivers/vicodec/vicodec-core.c

1260

if (dc->cmd == V4L2_DEC_CMD_START &&

drivers/media/v4l2-core/v4l2-mem2mem.c

1479

struct v4l2_decoder_cmd *dc)

drivers/media/v4l2-core/v4l2-mem2mem.c

1481

if (dc->cmd != V4L2_DEC_CMD_STOP && dc->cmd != V4L2_DEC_CMD_START)

drivers/media/v4l2-core/v4l2-mem2mem.c

1484

dc->flags = 0;

drivers/media/v4l2-core/v4l2-mem2mem.c

1486

if (dc->cmd == V4L2_DEC_CMD_STOP) {

drivers/media/v4l2-core/v4l2-mem2mem.c

1487

dc->stop.pts = 0;

drivers/media/v4l2-core/v4l2-mem2mem.c

1488

} else if (dc->cmd == V4L2_DEC_CMD_START) {

drivers/media/v4l2-core/v4l2-mem2mem.c

1489

dc->start.speed = 0;

drivers/media/v4l2-core/v4l2-mem2mem.c

1490

dc->start.format = V4L2_DEC_START_FMT_NONE;

drivers/media/v4l2-core/v4l2-mem2mem.c

1524

struct v4l2_decoder_cmd *dc)

drivers/media/v4l2-core/v4l2-mem2mem.c

1526

if (dc->cmd != V4L2_DEC_CMD_STOP && dc->cmd != V4L2_DEC_CMD_START)

drivers/media/v4l2-core/v4l2-mem2mem.c

1529

if (dc->cmd == V4L2_DEC_CMD_STOP)

drivers/media/v4l2-core/v4l2-mem2mem.c

1552

struct v4l2_decoder_cmd *dc)

drivers/media/v4l2-core/v4l2-mem2mem.c

1556

return v4l2_m2m_decoder_cmd(file, fh->m2m_ctx, dc);

drivers/media/v4l2-core/v4l2-mem2mem.c

1561

struct v4l2_decoder_cmd *dc)

drivers/media/v4l2-core/v4l2-mem2mem.c

1563

if (dc->cmd != V4L2_DEC_CMD_FLUSH)

drivers/media/v4l2-core/v4l2-mem2mem.c

1566

dc->flags = 0;

drivers/media/v4l2-core/v4l2-mem2mem.c

1573

struct v4l2_decoder_cmd *dc)

drivers/media/v4l2-core/v4l2-mem2mem.c

1581

ret = v4l2_m2m_ioctl_stateless_try_decoder_cmd(file, priv, dc);

drivers/mtd/nand/raw/marvell_nand.c

271

#define MARVELL_LAYOUT(ws, dc, ds, nc, fcc, db, sb, eb, ldb, lsb, leb) \

drivers/mtd/nand/raw/marvell_nand.c

274

.chunk = dc, \

drivers/net/ethernet/intel/e1000/e1000_ethtool.c

52

{ "tx_deferred_ok", E1000_STAT(stats.dc) },

drivers/net/ethernet/intel/e1000/e1000_hw.h

1261

u64 dc;

drivers/net/ethernet/intel/e1000/e1000_main.c

3637

adapter->stats.dc += er32(DC);

drivers/net/ethernet/intel/e1000e/ethtool.c

72

E1000_STAT("tx_deferred_ok", stats.dc),

drivers/net/ethernet/intel/e1000e/hw.h

389

u64 dc;

drivers/net/ethernet/intel/e1000e/netdev.c

4948

adapter->stats.dc += phy_data;

drivers/net/ethernet/intel/e1000e/netdev.c

4997

adapter->stats.dc += er32(DC);

drivers/net/ethernet/intel/ice/ice_flex_pipe.c

239

ice_set_key(u8 *key, u16 size, u8 *val, u8 *upd, u8 *dc, u8 *nm, u16 off,

drivers/net/ethernet/intel/ice/ice_flex_pipe.c

263

dc ? dc[i] : 0, nm ? nm[i] : 0,

drivers/net/ethernet/intel/ice/ice_flex_pipe.c

334

u8 val, dc, nm;

drivers/net/ethernet/intel/ice/ice_flex_pipe.c

363

dc = 0xFF;

drivers/net/ethernet/intel/ice/ice_flex_pipe.c

368

dc = 0xF7;

drivers/net/ethernet/intel/ice/ice_flex_pipe.c

373

&val, NULL, &dc, &nm, 0, sizeof(u8));

drivers/net/ethernet/intel/igb/e1000_hw.h

178

u64 dc;

drivers/net/ethernet/intel/igb/igb_ethtool.c

50

IGB_STAT("tx_deferred_ok", stats.dc),

drivers/net/ethernet/intel/igb/igb_ethtool.c

563

regs_buff[64] = adapter->stats.dc;

drivers/net/ethernet/intel/igb/igb_main.c

6843

adapter->stats.dc += rd32(E1000_DC);

drivers/net/ethernet/intel/igc/igc_ethtool.c

245

regs_buff[40] = adapter->stats.dc;

drivers/net/ethernet/intel/igc/igc_ethtool.c

44

IGC_STAT("tx_deferred_ok", stats.dc),

drivers/net/ethernet/intel/igc/igc_hw.h

215

u64 dc;

drivers/net/ethernet/intel/igc/igc_main.c

5239

adapter->stats.dc += rd32(IGC_DC);

drivers/net/wireless/ath/ath11k/thermal.c

141

param.dc = ATH11K_THERMAL_DEFAULT_DUTY_CYCLE;

drivers/net/wireless/ath/ath11k/wmi.c

3099

cmd->dc = param->dc;

drivers/net/wireless/ath/ath11k/wmi.c

3132

ar->pdev->pdev_id, param->enable, param->dc,

drivers/net/wireless/ath/ath11k/wmi.h

4001

u32 dc;

drivers/net/wireless/ath/ath11k/wmi.h

4010

u32 dc;

drivers/net/wireless/ath/ath12k/wmi.c

3467

cmd->dc = cpu_to_le32(100);

drivers/net/wireless/ath/ath12k/wmi.h

4169

__le32 dc;

drivers/net/wireless/ath/ath9k/ar9003_wow.c

256

u32 dc = REG_READ(ah, AR_DIRECT_CONNECT);

drivers/net/wireless/ath/ath9k/ar9003_wow.c

258

if (!(dc & AR_DC_TSF2_ENABLE))

drivers/net/wireless/marvell/libertas/if_spi.h

81

#define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_ID(dc) ((dc & 0xffff0000)>>16)

drivers/net/wireless/marvell/libertas/if_spi.h

82

#define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_REV(dc) (dc & 0x000000ff)

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9343

static void rt2800_write_dc(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 alc, u8 iorq, u8 dc)

drivers/net/wireless/ralink/rt2x00/rt2800lib.c

9357

bbp = dc;

drivers/net/wireless/realtek/rtw89/rtw8852bt_rfk.c

2025

u32 corr, dc;

drivers/net/wireless/realtek/rtw89/rtw8852bt_rfk.c

2042

dc = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD);

drivers/net/wireless/realtek/rtw89/rtw8852bt_rfk.c

2043

dc_i = u32_get_bits(dc, B_PRT_COM_DCI);

drivers/net/wireless/realtek/rtw89/rtw8852bt_rfk.c

2044

dc_q = u32_get_bits(dc, B_PRT_COM_DCQ);

drivers/net/xen-netback/netback.c

1325

pending_ring_idx_t dc, dp;

drivers/net/xen-netback/netback.c

1329

dc = queue->dealloc_cons;

drivers/net/xen-netback/netback.c

1341

while (dc != dp) {

drivers/net/xen-netback/netback.c

1344

queue->dealloc_ring[pending_index(dc++)];

drivers/net/xen-netback/netback.c

1360

queue->dealloc_cons = dc;

drivers/perf/amlogic/meson_ddr_pmu_core.c

89

struct dmc_counter dc = {0}, sum_dc = {0};

drivers/perf/amlogic/meson_ddr_pmu_core.c

94

pmu->info.hw_info->get_counters(&pmu->info, &dc);

drivers/perf/amlogic/meson_ddr_pmu_core.c

96

ddr_cnt_addition(&sum_dc, &pmu->counters, &dc, chann_nr);

drivers/power/supply/bq2515x_charger.c

303

bool dc = false;

drivers/power/supply/bq2515x_charger.c

315

dc = val & BQ2515X_VIN_GOOD;

drivers/power/supply/bq2515x_charger.c

317

ret = bq2515x->mains_online != dc;

drivers/power/supply/bq2515x_charger.c

319

bq2515x->mains_online = dc;

drivers/power/supply/da9052-battery.c

230

bool dc;

drivers/power/supply/da9052-battery.c

244

dc = dcinsel && dcindet;

drivers/power/supply/da9052-battery.c

248

if (dc || vbus) {

drivers/power/supply/smb347-charger.c

310

bool dc = false;

drivers/power/supply/smb347-charger.c

323

dc = !(val & IRQSTAT_E_DCIN_UV_STAT);

drivers/power/supply/smb347-charger.c

327

ret = smb->mains_online != dc || smb->usb_online != usb;

drivers/power/supply/smb347-charger.c

328

smb->mains_online = dc;

drivers/pwm/pwm-bcm-kona.c

105

unsigned long prescale = PRESCALE_MIN, pc, dc;

drivers/pwm/pwm-bcm-kona.c

125

dc = mul_u64_u64_div_u64(rate, duty_ns, div);

drivers/pwm/pwm-bcm-kona.c

132

if (pc <= PERIOD_COUNT_MAX && dc <= DUTY_CYCLE_HIGH_MAX)

drivers/pwm/pwm-bcm-kona.c

149

writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));

drivers/pwm/pwm-brcmstb.c

109

dc = PWM_ON_PERIOD_MAX;

drivers/pwm/pwm-brcmstb.c

125

dc = mul_u64_u64_div_u64(duty_ns + 1, rate, NSEC_PER_SEC);

drivers/pwm/pwm-brcmstb.c

131

if (pc == PWM_PERIOD_MIN || (dc < PWM_ON_MIN && duty_ns))

drivers/pwm/pwm-brcmstb.c

135

if (pc <= PWM_ON_PERIOD_MAX && dc <= PWM_ON_PERIOD_MAX)

drivers/pwm/pwm-brcmstb.c

170

brcmstb_pwm_writel(p, dc, PWM_ON(channel));

drivers/pwm/pwm-brcmstb.c

99

unsigned long pc, dc, cword = CONST_VAR_F_MAX;

drivers/pwm/pwm-pxa.c

72

unsigned long period_cycles, prescale, pv, dc;

drivers/pwm/pwm-pxa.c

91

dc = PWMDCR_FD;

drivers/pwm/pwm-pxa.c

93

dc = mul_u64_u64_div_u64(pv + 1, duty_ns, period_ns);

drivers/pwm/pwm-pxa.c

96

writel(dc, pc->mmio_base + offset + PWMDCR);

drivers/pwm/pwm-rz-mtu3.c

283

u16 dc, pv;

drivers/pwm/pwm-rz-mtu3.c

289

RZ_MTU3_TGRB, &dc);

drivers/pwm/pwm-rz-mtu3.c

292

RZ_MTU3_TGRD, &dc);

drivers/pwm/pwm-rz-mtu3.c

300

tmp = NSEC_PER_SEC * (u64)dc << (2 * prescale);

drivers/pwm/pwm-rz-mtu3.c

326

u16 pv, dc;

drivers/pwm/pwm-rz-mtu3.c

354

dc = rz_mtu3_pwm_calculate_pv_or_dc(duty_cycles, prescale);

drivers/pwm/pwm-rz-mtu3.c

378

RZ_MTU3_TGRB, dc);

drivers/pwm/pwm-rz-mtu3.c

383

RZ_MTU3_TGRD, dc);

drivers/pwm/pwm-rzg2l-gpt.c

266

unsigned long pv, dc;

drivers/pwm/pwm-rzg2l-gpt.c

295

dc = rzg2l_gpt_calculate_pv_or_dc(duty_ticks, prescale);

drivers/pwm/pwm-rzg2l-gpt.c

329

rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch), dc);

drivers/pwm/pwm-spear.c

100

dc = div64_u64(val, div);

drivers/pwm/pwm-spear.c

103

if (pv < PWMPCR_MIN_PERIOD || dc < PWMDCR_MIN_DUTY)

drivers/pwm/pwm-spear.c

110

if (pv > PWMPCR_MAX_PERIOD || dc > PWMDCR_MAX_DUTY) {

drivers/pwm/pwm-spear.c

128

spear_pwm_writel(pc, pwm->hwpwm, PWMDCR, dc);

drivers/pwm/pwm-spear.c

80

unsigned long prescale = PWMCR_MIN_PRESCALE, pv, dc;

drivers/pwm/pwm-vt8500.c

105

dc = div64_u64(c, period_ns);

drivers/pwm/pwm-vt8500.c

113

writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm));

drivers/pwm/pwm-vt8500.c

76

unsigned long period_cycles, prescale, pv, dc;

drivers/scsi/esas2r/esas2r.h

1109

struct esas2r_disc_context *dc);

drivers/scsi/esas2r/esas2r.h

1111

struct esas2r_disc_context *dc,

drivers/scsi/esas2r/esas2r_disc.c

1007

if (dc->flags & DCF_DEV_SCAN) {

drivers/scsi/esas2r/esas2r_disc.c

1008

dc->dev_ix++;

drivers/scsi/esas2r/esas2r_disc.c

1009

dc->state = DCS_PT_DEV_INFO;

drivers/scsi/esas2r/esas2r_disc.c

1010

} else if (dc->flags & DCF_DEV_CHANGE) {

drivers/scsi/esas2r/esas2r_disc.c

1011

dc->curr_targ++;

drivers/scsi/esas2r/esas2r_disc.c

1012

dc->state = DCS_DEV_ADD;

drivers/scsi/esas2r/esas2r_disc.c

1022

if (!(dc->flags & DCF_POLLED))

drivers/scsi/esas2r/esas2r_disc.c

1047

struct esas2r_disc_context *dc =

drivers/scsi/esas2r/esas2r_disc.c

1075

dc->state = DCS_DEV_ADD;

drivers/scsi/esas2r/esas2r_disc.c

1076

dc->curr_targ = a->targetdb;

drivers/scsi/esas2r/esas2r_disc.c

1086

struct esas2r_disc_context *dc =

drivers/scsi/esas2r/esas2r_disc.c

1088

struct esas2r_target *t = dc->curr_targ;

drivers/scsi/esas2r/esas2r_disc.c

1093

dc->state = DCS_DISC_DONE;

drivers/scsi/esas2r/esas2r_disc.c

1105

dc->curr_virt_id = esas2r_targ_get_id(t, a);

drivers/scsi/esas2r/esas2r_disc.c

1110

dc->block_size = luevt->id.tgtlun_raid.dwblock_size;

drivers/scsi/esas2r/esas2r_disc.c

1111

dc->interleave = luevt->id.tgtlun_raid.dwinterleave;

drivers/scsi/esas2r/esas2r_disc.c

1113

dc->block_size = 0;

drivers/scsi/esas2r/esas2r_disc.c

1114

dc->interleave = 0;

drivers/scsi/esas2r/esas2r_disc.c

1121

dc->state = DCS_PT_DEV_ADDR;

drivers/scsi/esas2r/esas2r_disc.c

1122

dc->dev_addr_type = ATTO_GDA_AT_PORT;

drivers/scsi/esas2r/esas2r_disc.c

1123

dc->curr_phys_id = luevt->wphys_target_id;

drivers/scsi/esas2r/esas2r_disc.c

1131

dc->raid_grp_name[0] = 0;

drivers/scsi/esas2r/esas2r_disc.c

1133

esas2r_targ_db_add_raid(a, dc);

drivers/scsi/esas2r/esas2r_disc.c

1136

esas2r_trace("curr_virt_id: %d", dc->curr_virt_id);

drivers/scsi/esas2r/esas2r_disc.c

1137

esas2r_trace("curr_phys_id: %d", dc->curr_phys_id);

drivers/scsi/esas2r/esas2r_disc.c

1143

if (dc->state == DCS_DEV_ADD) {

drivers/scsi/esas2r/esas2r_disc.c

1146

dc->curr_targ++;

drivers/scsi/esas2r/esas2r_disc.c

291

struct esas2r_disc_context *dc = &a->disc_ctx;

drivers/scsi/esas2r/esas2r_disc.c

298

dc->disc_evt |= disc_evt;

drivers/scsi/esas2r/esas2r_disc.c

314

struct esas2r_disc_context *dc = &a->disc_ctx;

drivers/scsi/esas2r/esas2r_disc.c

326

if (dc->disc_evt) {

drivers/scsi/esas2r/esas2r_disc.c

352

esas2r_trace("disc_evt: %d", dc->disc_evt);

drivers/scsi/esas2r/esas2r_disc.c

354

dc->flags = 0;

drivers/scsi/esas2r/esas2r_disc.c

357

dc->flags |= DCF_POLLED;

drivers/scsi/esas2r/esas2r_disc.c

359

rq->interrupt_cx = dc;

drivers/scsi/esas2r/esas2r_disc.c

363

if (dc->disc_evt & DCDE_DEV_SCAN) {

drivers/scsi/esas2r/esas2r_disc.c

364

dc->disc_evt &= ~DCDE_DEV_SCAN;

drivers/scsi/esas2r/esas2r_disc.c

366

dc->flags |= DCF_DEV_SCAN;

drivers/scsi/esas2r/esas2r_disc.c

367

dc->state = DCS_BLOCK_DEV_SCAN;

drivers/scsi/esas2r/esas2r_disc.c

368

} else if (dc->disc_evt & DCDE_DEV_CHANGE) {

drivers/scsi/esas2r/esas2r_disc.c

369

dc->disc_evt &= ~DCDE_DEV_CHANGE;

drivers/scsi/esas2r/esas2r_disc.c

371

dc->flags |= DCF_DEV_CHANGE;

drivers/scsi/esas2r/esas2r_disc.c

372

dc->state = DCS_DEV_RMV;

drivers/scsi/esas2r/esas2r_disc.c

389

struct esas2r_disc_context *dc =

drivers/scsi/esas2r/esas2r_disc.c

394

while (dc->flags & (DCF_DEV_CHANGE | DCF_DEV_SCAN)) {

drivers/scsi/esas2r/esas2r_disc.c

397

switch (dc->state) {

drivers/scsi/esas2r/esas2r_disc.c

433

dc->flags &= ~(DCF_DEV_CHANGE | DCF_DEV_SCAN);

drivers/scsi/esas2r/esas2r_disc.c

439

dc->state = DCS_DISC_DONE;

drivers/scsi/esas2r/esas2r_disc.c

505

struct esas2r_disc_context *dc =

drivers/scsi/esas2r/esas2r_disc.c

512

dc->state = DCS_DISC_DONE;

drivers/scsi/esas2r/esas2r_disc.c

520

struct esas2r_disc_context *dc =

drivers/scsi/esas2r/esas2r_disc.c

539

rq->interrupt_cx = dc;

drivers/scsi/esas2r/esas2r_disc.c

551

struct esas2r_disc_context *dc =

drivers/scsi/esas2r/esas2r_disc.c

560

dc->scan_gen = rq->func_rsp.mgt_rsp.scan_generation;

drivers/scsi/esas2r/esas2r_disc.c

562

dc->state = DCS_RAID_GRP_INFO;

drivers/scsi/esas2r/esas2r_disc.c

563

dc->raid_grp_ix = 0;

drivers/scsi/esas2r/esas2r_disc.c

569

if (!(dc->flags & DCF_POLLED))

drivers/scsi/esas2r/esas2r_disc.c

580

struct esas2r_disc_context *dc =

drivers/scsi/esas2r/esas2r_disc.c

587

esas2r_trace("raid_group_idx: %d", dc->raid_grp_ix);

drivers/scsi/esas2r/esas2r_disc.c

589

if (dc->raid_grp_ix >= VDA_MAX_RAID_GROUPS) {

drivers/scsi/esas2r/esas2r_disc.c

590

dc->state = DCS_DISC_DONE;

drivers/scsi/esas2r/esas2r_disc.c

606

dc->scan_gen,

drivers/scsi/esas2r/esas2r_disc.c

611

grpinfo->grp_index = dc->raid_grp_ix;

drivers/scsi/esas2r/esas2r_disc.c

615

rq->interrupt_cx = dc;

drivers/scsi/esas2r/esas2r_disc.c

627

struct esas2r_disc_context *dc =

drivers/scsi/esas2r/esas2r_disc.c

637

dc->scan_gen = rq->func_rsp.mgt_rsp.scan_generation;

drivers/scsi/esas2r/esas2r_disc.c

638

dc->raid_grp_ix = 0;

drivers/scsi/esas2r/esas2r_disc.c

649

dc->raid_grp_ix++;

drivers/scsi/esas2r/esas2r_disc.c

651

memcpy(&dc->raid_grp_name[0],

drivers/scsi/esas2r/esas2r_disc.c

655

dc->interleave = le32_to_cpu(grpinfo->interleave);

drivers/scsi/esas2r/esas2r_disc.c

656

dc->block_size = le32_to_cpu(grpinfo->block_size);

drivers/scsi/esas2r/esas2r_disc.c

658

dc->state = DCS_PART_INFO;

drivers/scsi/esas2r/esas2r_disc.c

659

dc->part_num = 0;

drivers/scsi/esas2r/esas2r_disc.c

669

dc->dev_ix = 0;

drivers/scsi/esas2r/esas2r_disc.c

670

dc->state = DCS_PT_DEV_INFO;

drivers/scsi/esas2r/esas2r_disc.c

679

if (!(dc->flags & DCF_POLLED))

drivers/scsi/esas2r/esas2r_disc.c

690

struct esas2r_disc_context *dc =

drivers/scsi/esas2r/esas2r_disc.c

697

esas2r_trace("part_num: %d", dc->part_num);

drivers/scsi/esas2r/esas2r_disc.c

699

if (dc->part_num >= VDA_MAX_PARTITIONS) {

drivers/scsi/esas2r/esas2r_disc.c

700

dc->state = DCS_RAID_GRP_INFO;

drivers/scsi/esas2r/esas2r_disc.c

701

dc->raid_grp_ix++;

drivers/scsi/esas2r/esas2r_disc.c

717

dc->scan_gen,

drivers/scsi/esas2r/esas2r_disc.c

722

partinfo->part_no = dc->part_num;

drivers/scsi/esas2r/esas2r_disc.c

725

&dc->raid_grp_name[0],

drivers/scsi/esas2r/esas2r_disc.c

730

rq->interrupt_cx = dc;

drivers/scsi/esas2r/esas2r_disc.c

742

struct esas2r_disc_context *dc =

drivers/scsi/esas2r/esas2r_disc.c

752

dc->scan_gen = rq->func_rsp.mgt_rsp.scan_generation;

drivers/scsi/esas2r/esas2r_disc.c

753

dc->raid_grp_ix = 0;

drivers/scsi/esas2r/esas2r_disc.c

754

dc->state = DCS_RAID_GRP_INFO;

drivers/scsi/esas2r/esas2r_disc.c

758

dc->part_num = partinfo->part_no;

drivers/scsi/esas2r/esas2r_disc.c

760

dc->curr_virt_id = le16_to_cpu(partinfo->target_id);

drivers/scsi/esas2r/esas2r_disc.c

762

esas2r_targ_db_add_raid(a, dc);

drivers/scsi/esas2r/esas2r_disc.c

764

dc->part_num++;

drivers/scsi/esas2r/esas2r_disc.c

772

dc->state = DCS_RAID_GRP_INFO;

drivers/scsi/esas2r/esas2r_disc.c

773

dc->raid_grp_ix++;

drivers/scsi/esas2r/esas2r_disc.c

780

if (!(dc->flags & DCF_POLLED))

drivers/scsi/esas2r/esas2r_disc.c

791

struct esas2r_disc_context *dc =

drivers/scsi/esas2r/esas2r_disc.c

798

esas2r_trace("dev_ix: %d", dc->dev_ix);

drivers/scsi/esas2r/esas2r_disc.c

809

dc->scan_gen,

drivers/scsi/esas2r/esas2r_disc.c

810

dc->dev_ix,

drivers/scsi/esas2r/esas2r_disc.c

816

rq->interrupt_cx = dc;

drivers/scsi/esas2r/esas2r_disc.c

828

struct esas2r_disc_context *dc =

drivers/scsi/esas2r/esas2r_disc.c

838

dc->scan_gen = rq->func_rsp.mgt_rsp.scan_generation;

drivers/scsi/esas2r/esas2r_disc.c

839

dc->dev_ix = 0;

drivers/scsi/esas2r/esas2r_disc.c

840

dc->state = DCS_PT_DEV_INFO;

drivers/scsi/esas2r/esas2r_disc.c

844

dc->dev_ix = le16_to_cpu(rq->func_rsp.mgt_rsp.dev_index);

drivers/scsi/esas2r/esas2r_disc.c

846

dc->curr_virt_id = le16_to_cpu(devinfo->target_id);

drivers/scsi/esas2r/esas2r_disc.c

849

dc->curr_phys_id =

drivers/scsi/esas2r/esas2r_disc.c

851

dc->dev_addr_type = ATTO_GDA_AT_PORT;

drivers/scsi/esas2r/esas2r_disc.c

852

dc->state = DCS_PT_DEV_ADDR;

drivers/scsi/esas2r/esas2r_disc.c

854

esas2r_trace("curr_virt_id: %d", dc->curr_virt_id);

drivers/scsi/esas2r/esas2r_disc.c

855

esas2r_trace("curr_phys_id: %d", dc->curr_phys_id);

drivers/scsi/esas2r/esas2r_disc.c

857

dc->dev_ix++;

drivers/scsi/esas2r/esas2r_disc.c

866

dc->state = DCS_DISC_DONE;

drivers/scsi/esas2r/esas2r_disc.c

873

if (!(dc->flags & DCF_POLLED))

drivers/scsi/esas2r/esas2r_disc.c

884

struct esas2r_disc_context *dc =

drivers/scsi/esas2r/esas2r_disc.c

915

rq->interrupt_cx = dc;

drivers/scsi/esas2r/esas2r_disc.c

927

hi->data.get_dev_addr.target_id = le32_to_cpu(dc->curr_phys_id);

drivers/scsi/esas2r/esas2r_disc.c

928

hi->data.get_dev_addr.addr_type = dc->dev_addr_type;

drivers/scsi/esas2r/esas2r_disc.c

942

struct esas2r_disc_context *dc =

drivers/scsi/esas2r/esas2r_disc.c

959

if (dc->dev_addr_type == ATTO_GDA_AT_PORT) {

drivers/scsi/esas2r/esas2r_disc.c

961

memcpy(&dc->sas_addr,

drivers/scsi/esas2r/esas2r_disc.c

965

memset(&dc->sas_addr, 0, sizeof(dc->sas_addr));

drivers/scsi/esas2r/esas2r_disc.c

968

dc->dev_addr_type = ATTO_GDA_AT_UNIQUE;

drivers/scsi/esas2r/esas2r_disc.c

975

dc,

drivers/scsi/esas2r/esas2r_disc.c

984

memcpy(&t->sas_addr, &dc->sas_addr,

drivers/scsi/esas2r/esas2r_int.c

392

struct esas2r_disc_context *dc;

drivers/scsi/esas2r/esas2r_int.c

404

dc = (struct esas2r_disc_context *)rq->interrupt_cx;

drivers/scsi/esas2r/esas2r_int.c

406

dc->disc_evt = 0;

drivers/scsi/esas2r/esas2r_targdb.c

121

dc)

drivers/scsi/esas2r/esas2r_targdb.c

127

if (dc->curr_virt_id >= ESAS2R_MAX_TARGETS) {

drivers/scsi/esas2r/esas2r_targdb.c

133

t = a->targetdb + dc->curr_virt_id;

drivers/scsi/esas2r/esas2r_targdb.c

140

esas2r_hdebug("add RAID %s, T:%d", dc->raid_grp_name,

drivers/scsi/esas2r/esas2r_targdb.c

145

if (dc->interleave == 0

drivers/scsi/esas2r/esas2r_targdb.c

146

|| dc->block_size == 0) {

drivers/scsi/esas2r/esas2r_targdb.c

156

t->block_size = dc->block_size;

drivers/scsi/esas2r/esas2r_targdb.c

157

t->inter_byte = dc->interleave;

drivers/scsi/esas2r/esas2r_targdb.c

158

t->inter_block = dc->interleave / dc->block_size;

drivers/scsi/esas2r/esas2r_targdb.c

159

t->virt_targ_id = dc->curr_virt_id;

drivers/scsi/esas2r/esas2r_targdb.c

173

struct esas2r_disc_context *dc,

drivers/scsi/esas2r/esas2r_targdb.c

181

if (dc->curr_virt_id >= ESAS2R_MAX_TARGETS) {

drivers/scsi/esas2r/esas2r_targdb.c

192

t = a->targetdb + dc->curr_virt_id;

drivers/scsi/esas2r/esas2r_targdb.c

202

dc->curr_virt_id,

drivers/scsi/esas2r/esas2r_targdb.c

203

dc->curr_phys_id);

drivers/scsi/esas2r/esas2r_targdb.c

208

t->virt_targ_id = dc->curr_virt_id;

drivers/scsi/esas2r/esas2r_targdb.c

209

t->phys_targ_id = dc->curr_phys_id;

drivers/scsi/qla2xxx/qla_init.c

3978

uint16_t dc;

drivers/scsi/qla2xxx/qla_init.c

3991

pci_read_config_word(vha->hw->pdev, 0x54, &dc);

drivers/scsi/qla2xxx/qla_init.c

3998

dc &= MPS_MASK;

drivers/scsi/qla2xxx/qla_init.c

3999

if (dc == (dw & MPS_MASK))

drivers/scsi/qla2xxx/qla_init.c

4003

dw |= dc;

drivers/spi/spi-ti-qspi.c

260

cmd, qspi->dc, *txbuf);

drivers/spi/spi-ti-qspi.c

287

cmd, qspi->dc, *txbuf);

drivers/spi/spi-ti-qspi.c

292

cmd, qspi->dc, *txbuf);

drivers/spi/spi-ti-qspi.c

335

dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);

drivers/spi/spi-ti-qspi.c

60

u32 dc;

drivers/spi/spi-ti-qspi.c

674

qspi->dc = 0;

drivers/spi/spi-ti-qspi.c

677

qspi->dc |= QSPI_CKPHA(spi_get_chipselect(spi, 0));

drivers/spi/spi-ti-qspi.c

679

qspi->dc |= QSPI_CKPOL(spi_get_chipselect(spi, 0));

drivers/spi/spi-ti-qspi.c

681

qspi->dc |= QSPI_CSPOL(spi_get_chipselect(spi, 0));

drivers/spi/spi-ti-qspi.c

693

ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);

drivers/staging/fbtft/fb_agm1264k-fl.c

30

#define RS gpio.dc

drivers/staging/fbtft/fb_pcd8544.c

122

gpiod_set_value(par->gpio.dc, 1);

drivers/staging/fbtft/fb_ra8875.c

42

gpiod_set_value(par->gpio.dc, 1);

drivers/staging/fbtft/fb_ssd1305.c

171

gpiod_set_value(par->gpio.dc, 1);

drivers/staging/fbtft/fb_ssd1306.c

191

gpiod_set_value(par->gpio.dc, 1);

drivers/staging/fbtft/fb_ssd1325.c

147

gpiod_set_value(par->gpio.dc, 1);

drivers/staging/fbtft/fb_ssd1331.c

106

gpiod_set_value(par->gpio.dc, 1);

drivers/staging/fbtft/fb_ssd1331.c

84

gpiod_set_value(par->gpio.dc, 0);

drivers/staging/fbtft/fb_tls8204.c

112

gpiod_set_value(par->gpio.dc, 1);

drivers/staging/fbtft/fb_tls8204.c

97

gpiod_set_value(par->gpio.dc, 0);

drivers/staging/fbtft/fb_uc1611.c

257

gpiod_set_value(par->gpio.dc, 1);

drivers/staging/fbtft/fb_uc1701.c

139

gpiod_set_value(par->gpio.dc, 1);

drivers/staging/fbtft/fb_uc1701.c

141

gpiod_set_value(par->gpio.dc, 0);

drivers/staging/fbtft/fbtft-bus.c

135

gpiod_set_value(par->gpio.dc, 1);

drivers/staging/fbtft/fbtft-core.c

1051

!par->gpio.dc) {

drivers/staging/fbtft/fbtft-core.c

37

int fbtft_write_buf_dc(struct fbtft_par *par, void *buf, size_t len, int dc)

drivers/staging/fbtft/fbtft-core.c

41

gpiod_set_value(par->gpio.dc, dc);

drivers/staging/fbtft/fbtft-core.c

98

ret = fbtft_request_one_gpio(par, "dc", 0, &par->gpio.dc);

drivers/staging/fbtft/fbtft-io.c

47

u64 val, dc, tmp;

drivers/staging/fbtft/fbtft-io.c

67

dc = (*src & 0x0100) ? 1 : 0;

drivers/staging/fbtft/fbtft-io.c

69

tmp |= dc << bits;

drivers/staging/fbtft/fbtft.h

211

struct gpio_desc *dc;

drivers/staging/fbtft/fbtft.h

242

int fbtft_write_buf_dc(struct fbtft_par *par, void *buf, size_t len, int dc);

drivers/staging/media/av7110/av7110_hw.c

1000

if (!dc->data) {

drivers/staging/media/av7110/av7110_hw.c

1001

ret = MoveWindowAbs(av7110, av7110->osdwin, dc->x0, dc->y0);

drivers/staging/media/av7110/av7110_hw.c

1017

ret = DrawBlock(av7110, av7110->osdwin, 0, 0, 720, 576, dc->color);

drivers/staging/media/av7110/av7110_hw.c

1020

ret = OSDSetColor(av7110, dc->color, dc->x0, dc->y0, dc->x1, dc->y1);

drivers/staging/media/av7110/av7110_hw.c

1024

ret = OSDSetPalette(av7110, dc->data, dc->color, dc->x0);

drivers/staging/media/av7110/av7110_hw.c

1026

int i, len = dc->x0 - dc->color + 1;

drivers/staging/media/av7110/av7110_hw.c

1027

u8 __user *colors = (u8 __user *)dc->data;

drivers/staging/media/av7110/av7110_hw.c

1039

ret = OSDSetColor(av7110, dc->color + i, r, g, b, blend);

drivers/staging/media/av7110/av7110_hw.c

1047

dc->x0, dc->y0, 0, 0, dc->color);

drivers/staging/media/av7110/av7110_hw.c

1050

dc->y1 = dc->y0;

drivers/staging/media/av7110/av7110_hw.c

1053

ret = OSDSetBlock(av7110, dc->x0, dc->y0, dc->x1, dc->y1, dc->color, dc->data);

drivers/staging/media/av7110/av7110_hw.c

1056

ret = DrawBlock(av7110, av7110->osdwin, dc->x0, dc->y0,

drivers/staging/media/av7110/av7110_hw.c

1057

dc->x1 - dc->x0 + 1, dc->y1, dc->color);

drivers/staging/media/av7110/av7110_hw.c

1060

ret = DrawBlock(av7110, av7110->osdwin, dc->x0, dc->y0,

drivers/staging/media/av7110/av7110_hw.c

1061

dc->x1 - dc->x0 + 1, dc->y1 - dc->y0 + 1, dc->color);

drivers/staging/media/av7110/av7110_hw.c

1065

dc->x0, dc->y0, dc->x1 - dc->x0, dc->y1 - dc->y0, dc->color);

drivers/staging/media/av7110/av7110_hw.c

1071

if (strncpy_from_user(textbuf, dc->data, 240) < 0) {

drivers/staging/media/av7110/av7110_hw.c

1076

if (dc->x1 > 3)

drivers/staging/media/av7110/av7110_hw.c

1077

dc->x1 = 3;

drivers/staging/media/av7110/av7110_hw.c

1078

ret = SetFont(av7110, av7110->osdwin, dc->x1,

drivers/staging/media/av7110/av7110_hw.c

1079

(u16)(dc->color & 0xffff), (u16)(dc->color >> 16));

drivers/staging/media/av7110/av7110_hw.c

1083

ret = WriteText(av7110, av7110->osdwin, dc->x0, dc->y0, textbuf);

drivers/staging/media/av7110/av7110_hw.c

1087

if (dc->x0 < 1 || dc->x0 > 7) {

drivers/staging/media/av7110/av7110_hw.c

1090

av7110->osdwin = dc->x0;

drivers/staging/media/av7110/av7110_hw.c

1095

ret = MoveWindowAbs(av7110, av7110->osdwin, dc->x0, dc->y0);

drivers/staging/media/av7110/av7110_hw.c

1100

if (dc->color < OSD_BITMAP1 || dc->color > OSD_CURSOR) {

drivers/staging/media/av7110/av7110_hw.c

1104

if (dc->color >= OSD_BITMAP1 && dc->color <= OSD_BITMAP8HR)

drivers/staging/media/av7110/av7110_hw.c

1105

av7110->osdbpp[av7110->osdwin] = (1 << (dc->color & 3)) - 1;

drivers/staging/media/av7110/av7110_hw.c

1108

ret = CreateOSDWindow(av7110, av7110->osdwin, (osd_raw_window_t)dc->color,

drivers/staging/media/av7110/av7110_hw.c

1109

dc->x1 - dc->x0 + 1, dc->y1 - dc->y0 + 1);

drivers/staging/media/av7110/av7110_hw.c

1112

if (!dc->data) {

drivers/staging/media/av7110/av7110_hw.c

1113

ret = MoveWindowAbs(av7110, av7110->osdwin, dc->x0, dc->y0);

drivers/staging/media/av7110/av7110_hw.c

1125

dprintk(1, "%s(%d) returns with -ERESTARTSYS\n", __func__, dc->cmd);

drivers/staging/media/av7110/av7110_hw.c

1127

dprintk(1, "%s(%d) returns with %d\n", __func__, dc->cmd, ret);

drivers/staging/media/av7110/av7110_hw.c

982

int av7110_osd_cmd(struct av7110 *av7110, osd_cmd_t *dc)

drivers/staging/media/av7110/av7110_hw.c

989

switch (dc->cmd) {

drivers/staging/media/av7110/av7110_hw.c

994

av7110->osdbpp[av7110->osdwin] = (dc->color - 1) & 7;

drivers/staging/media/av7110/av7110_hw.c

997

dc->x1 - dc->x0 + 1, dc->y1 - dc->y0 + 1);

drivers/staging/media/av7110/av7110_hw.h

480

int av7110_osd_cmd(struct av7110 *av7110, osd_cmd_t *dc);

drivers/target/target_core_xcopy.c

302

int dc = (desc[1] & 0x02);

drivers/target/target_core_xcopy.c

323

desc_len, xop->stdi, xop->dtdi, dc);

drivers/tty/n_gsm.c

2511

static void gsm_dlci_copy_config_values(struct gsm_dlci *dlci, struct gsm_dlci_config *dc)

drivers/tty/n_gsm.c

2513

memset(dc, 0, sizeof(*dc));

drivers/tty/n_gsm.c

2514

dc->channel = (u32)dlci->addr;

drivers/tty/n_gsm.c

2515

dc->adaption = (u32)dlci->adaption;

drivers/tty/n_gsm.c

2516

dc->mtu = (u32)dlci->mtu;

drivers/tty/n_gsm.c

2517

dc->priority = (u32)dlci->prio;

drivers/tty/n_gsm.c

2519

dc->i = 1;

drivers/tty/n_gsm.c

2521

dc->i = 2;

drivers/tty/n_gsm.c

2522

dc->k = (u32)dlci->k;

drivers/tty/n_gsm.c

2531

static int gsm_dlci_config(struct gsm_dlci *dlci, struct gsm_dlci_config *dc, int open)

drivers/tty/n_gsm.c

2542

for (i = 0; i < ARRAY_SIZE(dc->reserved); i++)

drivers/tty/n_gsm.c

2543

if (dc->reserved[i])

drivers/tty/n_gsm.c

2551

if (dc->adaption != 1 && dc->adaption != 2)

drivers/tty/n_gsm.c

2553

if (dc->mtu > MAX_MTU || dc->mtu < MIN_MTU || dc->mtu > gsm->mru)

drivers/tty/n_gsm.c

2555

if (dc->priority >= 64)

drivers/tty/n_gsm.c

2557

if (dc->i == 0 || dc->i > 2) /* UIH and UI only */

drivers/tty/n_gsm.c

2559

if (dc->k > 7)

drivers/tty/n_gsm.c

2561

if (dc->flags & ~GSM_FL_RESTART) /* allow future extensions */

drivers/tty/n_gsm.c

2568

if (dc->adaption != dlci->adaption)

drivers/tty/n_gsm.c

2570

if (dc->mtu != dlci->mtu)

drivers/tty/n_gsm.c

2572

if (dc->i != dlci->ftype)

drivers/tty/n_gsm.c

2575

if (dc->priority != dlci->prio)

drivers/tty/n_gsm.c

2577

if (dc->flags & GSM_FL_RESTART)

drivers/tty/n_gsm.c

2600

dlci->adaption = (int)dc->adaption;

drivers/tty/n_gsm.c

2602

if (dc->mtu)

drivers/tty/n_gsm.c

2603

dlci->mtu = (unsigned int)dc->mtu;

drivers/tty/n_gsm.c

2607

if (dc->priority)

drivers/tty/n_gsm.c

2608

dlci->prio = (u8)dc->priority;

drivers/tty/n_gsm.c

2612

if (dc->i == 1)

drivers/tty/n_gsm.c

2614

else if (dc->i == 2)

drivers/tty/n_gsm.c

2617

if (dc->k)

drivers/tty/n_gsm.c

2618

dlci->k = (u8)dc->k;

drivers/tty/n_gsm.c

3832

struct gsm_dlci_config dc;

drivers/tty/n_gsm.c

3860

if (copy_from_user(&dc, (void __user *)arg, sizeof(dc)))

drivers/tty/n_gsm.c

3862

if (dc.channel == 0 || dc.channel >= NUM_DLCI)

drivers/tty/n_gsm.c

3864

addr = array_index_nospec(dc.channel, NUM_DLCI);

drivers/tty/n_gsm.c

3871

gsm_dlci_copy_config_values(dlci, &dc);

drivers/tty/n_gsm.c

3872

if (copy_to_user((void __user *)arg, &dc, sizeof(dc)))

drivers/tty/n_gsm.c

3876

if (copy_from_user(&dc, (void __user *)arg, sizeof(dc)))

drivers/tty/n_gsm.c

3878

if (dc.channel == 0 || dc.channel >= NUM_DLCI)

drivers/tty/n_gsm.c

3880

addr = array_index_nospec(dc.channel, NUM_DLCI);

drivers/tty/n_gsm.c

3887

return gsm_dlci_config(dlci, &dc, 0);

drivers/tty/n_gsm.c

4485

struct gsm_dlci_config dc;

drivers/tty/n_gsm.c

4510

if (copy_from_user(&dc, (void __user *)arg, sizeof(dc)))

drivers/tty/n_gsm.c

4512

if (dc.channel != dlci->addr)

drivers/tty/n_gsm.c

4514

gsm_dlci_copy_config_values(dlci, &dc);

drivers/tty/n_gsm.c

4515

if (copy_to_user((void __user *)arg, &dc, sizeof(dc)))

drivers/tty/n_gsm.c

4519

if (copy_from_user(&dc, (void __user *)arg, sizeof(dc)))

drivers/tty/n_gsm.c

4521

if (dc.channel >= NUM_DLCI)

drivers/tty/n_gsm.c

4523

if (dc.channel != 0 && dc.channel != dlci->addr)

drivers/tty/n_gsm.c

4525

return gsm_dlci_config(dlci, &dc, 1);

drivers/tty/nozomi.c

1000

if (receive_data(port, dc)) {

drivers/tty/nozomi.c

1001

writew(mask1, dc->reg_fcr);

drivers/tty/nozomi.c

1006

if (receive_data(port, dc)) {

drivers/tty/nozomi.c

1007

writew(mask2, dc->reg_fcr);

drivers/tty/nozomi.c

1012

if (receive_data(port, dc)) {

drivers/tty/nozomi.c

1013

writew(mask2, dc->reg_fcr);

drivers/tty/nozomi.c

1018

if (receive_data(port, dc)) {

drivers/tty/nozomi.c

1019

writew(mask1, dc->reg_fcr);

drivers/tty/nozomi.c

1024

dev_err(&dc->pdev->dev, "port out of sync!, toggle:%d\n",

drivers/tty/nozomi.c

1036

static int handle_data_ul(struct nozomi *dc, enum port_type port, u16 read_iir)

drivers/tty/nozomi.c

1038

u8 *toggle = &(dc->port[port].toggle_ul);

drivers/tty/nozomi.c

1041

dc->last_ier &= ~MDM_UL;

drivers/tty/nozomi.c

1042

writew(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

1043

if (send_data(port, dc)) {

drivers/tty/nozomi.c

1044

writew(MDM_UL1, dc->reg_fcr);

drivers/tty/nozomi.c

1045

dc->last_ier = dc->last_ier | MDM_UL;

drivers/tty/nozomi.c

1046

writew(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

1051

dc->last_ier &= ~MDM_UL;

drivers/tty/nozomi.c

1052

writew(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

1053

if (send_data(port, dc)) {

drivers/tty/nozomi.c

1054

writew(MDM_UL2, dc->reg_fcr);

drivers/tty/nozomi.c

1055

dc->last_ier = dc->last_ier | MDM_UL;

drivers/tty/nozomi.c

1056

writew(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

1062

dc->last_ier &= ~MDM_UL;

drivers/tty/nozomi.c

1063

writew(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

1064

if (send_data(port, dc)) {

drivers/tty/nozomi.c

1065

writew(MDM_UL2, dc->reg_fcr);

drivers/tty/nozomi.c

1066

dc->last_ier = dc->last_ier | MDM_UL;

drivers/tty/nozomi.c

1067

writew(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

1072

dc->last_ier &= ~MDM_UL;

drivers/tty/nozomi.c

1073

writew(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

1074

if (send_data(port, dc)) {

drivers/tty/nozomi.c

1075

writew(MDM_UL1, dc->reg_fcr);

drivers/tty/nozomi.c

1076

dc->last_ier = dc->last_ier | MDM_UL;

drivers/tty/nozomi.c

1077

writew(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

1082

writew(read_iir & MDM_UL, dc->reg_fcr);

drivers/tty/nozomi.c

1083

dev_err(&dc->pdev->dev, "port out of sync!\n");

drivers/tty/nozomi.c

1091

struct nozomi *dc = dev_id;

drivers/tty/nozomi.c

1095

if (!dc)

drivers/tty/nozomi.c

1098

spin_lock(&dc->spin_mutex);

drivers/tty/nozomi.c

1099

read_iir = readw(dc->reg_iir);

drivers/tty/nozomi.c

1108

read_iir &= dc->last_ier;

drivers/tty/nozomi.c

1115

dc->last_ier);

drivers/tty/nozomi.c

1118

if (unlikely(!nozomi_read_config_table(dc))) {

drivers/tty/nozomi.c

1119

dc->last_ier = 0x0;

drivers/tty/nozomi.c

1120

writew(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

1121

dev_err(&dc->pdev->dev, "Could not read status from "

drivers/tty/nozomi.c

1124

writew(RESET, dc->reg_fcr);

drivers/tty/nozomi.c

1131

dc->last_ier &= ~CTRL_UL;

drivers/tty/nozomi.c

1132

writew(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

1133

if (send_flow_control(dc)) {

drivers/tty/nozomi.c

1134

writew(CTRL_UL, dc->reg_fcr);

drivers/tty/nozomi.c

1135

dc->last_ier = dc->last_ier | CTRL_UL;

drivers/tty/nozomi.c

1136

writew(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

1140

receive_flow_control(dc);

drivers/tty/nozomi.c

1141

writew(CTRL_DL, dc->reg_fcr);

drivers/tty/nozomi.c

1144

if (!handle_data_dl(dc, PORT_MDM,

drivers/tty/nozomi.c

1145

&(dc->port[PORT_MDM].toggle_dl), read_iir,

drivers/tty/nozomi.c

1147

dev_err(&dc->pdev->dev, "MDM_DL out of sync!\n");

drivers/tty/nozomi.c

1152

if (!handle_data_ul(dc, PORT_MDM, read_iir)) {

drivers/tty/nozomi.c

1153

dev_err(&dc->pdev->dev, "MDM_UL out of sync!\n");

drivers/tty/nozomi.c

1158

if (!handle_data_dl(dc, PORT_DIAG,

drivers/tty/nozomi.c

1159

&(dc->port[PORT_DIAG].toggle_dl), read_iir,

drivers/tty/nozomi.c

1161

dev_err(&dc->pdev->dev, "DIAG_DL out of sync!\n");

drivers/tty/nozomi.c

1166

dc->last_ier &= ~DIAG_UL;

drivers/tty/nozomi.c

1167

writew(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

1168

if (send_data(PORT_DIAG, dc)) {

drivers/tty/nozomi.c

1169

writew(DIAG_UL, dc->reg_fcr);

drivers/tty/nozomi.c

1170

dc->last_ier = dc->last_ier | DIAG_UL;

drivers/tty/nozomi.c

1171

writew(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

1175

if (receive_data(PORT_APP1, dc))

drivers/tty/nozomi.c

1176

writew(APP1_DL, dc->reg_fcr);

drivers/tty/nozomi.c

1179

dc->last_ier &= ~APP1_UL;

drivers/tty/nozomi.c

1180

writew(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

1181

if (send_data(PORT_APP1, dc)) {

drivers/tty/nozomi.c

1182

writew(APP1_UL, dc->reg_fcr);

drivers/tty/nozomi.c

1183

dc->last_ier = dc->last_ier | APP1_UL;

drivers/tty/nozomi.c

1184

writew(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

1188

if (receive_data(PORT_APP2, dc))

drivers/tty/nozomi.c

1189

writew(APP2_DL, dc->reg_fcr);

drivers/tty/nozomi.c

1192

dc->last_ier &= ~APP2_UL;

drivers/tty/nozomi.c

1193

writew(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

1194

if (send_data(PORT_APP2, dc)) {

drivers/tty/nozomi.c

1195

writew(APP2_UL, dc->reg_fcr);

drivers/tty/nozomi.c

1196

dc->last_ier = dc->last_ier | APP2_UL;

drivers/tty/nozomi.c

1197

writew(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

1202

spin_unlock(&dc->spin_mutex);

drivers/tty/nozomi.c

1205

if (test_and_clear_bit(a, &dc->flip))

drivers/tty/nozomi.c

1206

tty_flip_buffer_push(&dc->port[a].port);

drivers/tty/nozomi.c

1210

spin_unlock(&dc->spin_mutex);

drivers/tty/nozomi.c

1214

static void nozomi_get_card_type(struct nozomi *dc)

drivers/tty/nozomi.c

1220

size += pci_resource_len(dc->pdev, i);

drivers/tty/nozomi.c

1223

dc->card_type = size == 2048 ? F32_2 : F32_8;

drivers/tty/nozomi.c

1225

dev_info(&dc->pdev->dev, "Card type is: %d\n", dc->card_type);

drivers/tty/nozomi.c

1228

static void nozomi_setup_private_data(struct nozomi *dc)

drivers/tty/nozomi.c

1230

void __iomem *offset = dc->base_addr + dc->card_type / 2;

drivers/tty/nozomi.c

1233

dc->reg_fcr = (void __iomem *)(offset + R_FCR);

drivers/tty/nozomi.c

1234

dc->reg_iir = (void __iomem *)(offset + R_IIR);

drivers/tty/nozomi.c

1235

dc->reg_ier = (void __iomem *)(offset + R_IER);

drivers/tty/nozomi.c

1236

dc->last_ier = 0;

drivers/tty/nozomi.c

1237

dc->flip = 0;

drivers/tty/nozomi.c

1239

dc->port[PORT_MDM].token_dl = MDM_DL;

drivers/tty/nozomi.c

1240

dc->port[PORT_DIAG].token_dl = DIAG_DL;

drivers/tty/nozomi.c

1241

dc->port[PORT_APP1].token_dl = APP1_DL;

drivers/tty/nozomi.c

1242

dc->port[PORT_APP2].token_dl = APP2_DL;

drivers/tty/nozomi.c

1245

init_waitqueue_head(&dc->port[i].tty_wait);

drivers/tty/nozomi.c

1251

const struct nozomi *dc = dev_get_drvdata(dev);

drivers/tty/nozomi.c

1253

return sprintf(buf, "%d\n", dc->card_type);

drivers/tty/nozomi.c

1260

const struct nozomi *dc = dev_get_drvdata(dev);

drivers/tty/nozomi.c

1262

return sprintf(buf, "%u\n", dc->open_ttys);

drivers/tty/nozomi.c

1266

static void make_sysfs_files(struct nozomi *dc)

drivers/tty/nozomi.c

1268

if (device_create_file(&dc->pdev->dev, &dev_attr_card_type))

drivers/tty/nozomi.c

1269

dev_err(&dc->pdev->dev,

drivers/tty/nozomi.c

1271

if (device_create_file(&dc->pdev->dev, &dev_attr_open_ttys))

drivers/tty/nozomi.c

1272

dev_err(&dc->pdev->dev,

drivers/tty/nozomi.c

1276

static void remove_sysfs_files(struct nozomi *dc)

drivers/tty/nozomi.c

1278

device_remove_file(&dc->pdev->dev, &dev_attr_card_type);

drivers/tty/nozomi.c

1279

device_remove_file(&dc->pdev->dev, &dev_attr_open_ttys);

drivers/tty/nozomi.c

1287

struct nozomi *dc = NULL;

drivers/tty/nozomi.c

1301

dc = kzalloc_obj(struct nozomi);

drivers/tty/nozomi.c

1302

if (unlikely(!dc)) {

drivers/tty/nozomi.c

1308

dc->pdev = pdev;

drivers/tty/nozomi.c

1310

ret = pci_enable_device(dc->pdev);

drivers/tty/nozomi.c

1316

ret = pci_request_regions(dc->pdev, NOZOMI_NAME);

drivers/tty/nozomi.c

1324

nozomi_get_card_type(dc);

drivers/tty/nozomi.c

1326

dc->base_addr = pci_iomap(dc->pdev, 0, dc->card_type);

drivers/tty/nozomi.c

1327

if (!dc->base_addr) {

drivers/tty/nozomi.c

1333

dc->send_buf = kmalloc(SEND_BUF_MAX, GFP_KERNEL);

drivers/tty/nozomi.c

1334

if (!dc->send_buf) {

drivers/tty/nozomi.c

1341

if (kfifo_alloc(&dc->port[i].fifo_ul, FIFO_BUFFER_SIZE_UL,

drivers/tty/nozomi.c

1350

spin_lock_init(&dc->spin_mutex);

drivers/tty/nozomi.c

1352

nozomi_setup_private_data(dc);

drivers/tty/nozomi.c

1355

dc->last_ier = 0;

drivers/tty/nozomi.c

1356

writew(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

1359

NOZOMI_NAME, dc);

drivers/tty/nozomi.c

1365

DBG1("base_addr: %p", dc->base_addr);

drivers/tty/nozomi.c

1367

make_sysfs_files(dc);

drivers/tty/nozomi.c

1369

dc->index_start = ndev_idx * MAX_PORT;

drivers/tty/nozomi.c

1370

ndevs[ndev_idx] = dc;

drivers/tty/nozomi.c

1372

pci_set_drvdata(pdev, dc);

drivers/tty/nozomi.c

1375

dc->last_ier = RESET;

drivers/tty/nozomi.c

1376

iowrite16(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

1378

dc->state = NOZOMI_STATE_ENABLED;

drivers/tty/nozomi.c

1382

struct port *port = &dc->port[i];

drivers/tty/nozomi.c

1383

port->dc = dc;

drivers/tty/nozomi.c

1387

dc->index_start + i, &pdev->dev);

drivers/tty/nozomi.c

1401

tty_unregister_device(ntty_driver, dc->index_start + i);

drivers/tty/nozomi.c

1402

tty_port_destroy(&dc->port[i].port);

drivers/tty/nozomi.c

1404

free_irq(pdev->irq, dc);

drivers/tty/nozomi.c

1409

kfifo_free(&dc->port[i].fifo_ul);

drivers/tty/nozomi.c

1411

kfree(dc->send_buf);

drivers/tty/nozomi.c

1412

iounmap(dc->base_addr);

drivers/tty/nozomi.c

1418

kfree(dc);

drivers/tty/nozomi.c

1423

static void tty_exit(struct nozomi *dc)

drivers/tty/nozomi.c

1428

tty_port_tty_hangup(&dc->port[i].port, false);

drivers/tty/nozomi.c

1432

while (dc->open_ttys)

drivers/tty/nozomi.c

1435

tty_unregister_device(ntty_driver, dc->index_start + i);

drivers/tty/nozomi.c

1436

tty_port_destroy(&dc->port[i].port);

drivers/tty/nozomi.c

1445

struct nozomi *dc = pci_get_drvdata(pdev);

drivers/tty/nozomi.c

1448

dc->last_ier = 0;

drivers/tty/nozomi.c

1449

writew(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

1451

tty_exit(dc);

drivers/tty/nozomi.c

1462

write_mem32(dc->port[PORT_CTRL].ul_addr[0], (u32 *)&ctrl, 2);

drivers/tty/nozomi.c

1463

writew(CTRL_UL, dc->reg_fcr); /* push the token to the card. */

drivers/tty/nozomi.c

1465

remove_sysfs_files(dc);

drivers/tty/nozomi.c

1467

free_irq(pdev->irq, dc);

drivers/tty/nozomi.c

1470

kfifo_free(&dc->port[i].fifo_ul);

drivers/tty/nozomi.c

1472

kfree(dc->send_buf);

drivers/tty/nozomi.c

1474

iounmap(dc->base_addr);

drivers/tty/nozomi.c

1480

ndevs[dc->index_start / MAX_PORT] = NULL;

drivers/tty/nozomi.c

1482

kfree(dc);

drivers/tty/nozomi.c

1514

struct nozomi *dc = get_dc_by_tty(tty);

drivers/tty/nozomi.c

1516

if (!port || !dc || dc->state != NOZOMI_STATE_READY)

drivers/tty/nozomi.c

1532

struct nozomi *dc = port->dc;

drivers/tty/nozomi.c

1536

spin_lock_irqsave(&dc->spin_mutex, flags);

drivers/tty/nozomi.c

1537

dc->last_ier = dc->last_ier | port->token_dl;

drivers/tty/nozomi.c

1538

writew(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

1539

dc->open_ttys++;

drivers/tty/nozomi.c

1540

spin_unlock_irqrestore(&dc->spin_mutex, flags);

drivers/tty/nozomi.c

1554

struct nozomi *dc = port->dc;

drivers/tty/nozomi.c

1558

spin_lock_irqsave(&dc->spin_mutex, flags);

drivers/tty/nozomi.c

1559

dc->last_ier &= ~(port->token_dl);

drivers/tty/nozomi.c

1560

writew(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

1561

dc->open_ttys--;

drivers/tty/nozomi.c

1562

spin_unlock_irqrestore(&dc->spin_mutex, flags);

drivers/tty/nozomi.c

1586

struct nozomi *dc = get_dc_by_tty(tty);

drivers/tty/nozomi.c

1591

if (!dc || !port)

drivers/tty/nozomi.c

1596

spin_lock_irqsave(&dc->spin_mutex, flags);

drivers/tty/nozomi.c

1598

if (port == &(dc->port[PORT_MDM])) {

drivers/tty/nozomi.c

1601

enable_transmit_ul(tty->index % MAX_PORT, dc);

drivers/tty/nozomi.c

1603

dev_err(&dc->pdev->dev,

drivers/tty/nozomi.c

1607

enable_transmit_ul(tty->index % MAX_PORT, dc);

drivers/tty/nozomi.c

1609

spin_unlock_irqrestore(&dc->spin_mutex, flags);

drivers/tty/nozomi.c

1627

const struct nozomi *dc = get_dc_by_tty(tty);

drivers/tty/nozomi.c

1629

if (dc)

drivers/tty/nozomi.c

1656

struct nozomi *dc = get_dc_by_tty(tty);

drivers/tty/nozomi.c

1659

spin_lock_irqsave(&dc->spin_mutex, flags);

drivers/tty/nozomi.c

1669

spin_unlock_irqrestore(&dc->spin_mutex, flags);

drivers/tty/nozomi.c

1738

struct nozomi *dc = get_dc_by_tty(tty);

drivers/tty/nozomi.c

1741

spin_lock_irqsave(&dc->spin_mutex, flags);

drivers/tty/nozomi.c

1742

enable_transmit_dl(tty->index % MAX_PORT, dc);

drivers/tty/nozomi.c

1745

spin_unlock_irqrestore(&dc->spin_mutex, flags);

drivers/tty/nozomi.c

1754

struct nozomi *dc = get_dc_by_tty(tty);

drivers/tty/nozomi.c

1757

spin_lock_irqsave(&dc->spin_mutex, flags);

drivers/tty/nozomi.c

1759

spin_unlock_irqrestore(&dc->spin_mutex, flags);

drivers/tty/nozomi.c

1766

struct nozomi *dc = get_dc_by_tty(tty);

drivers/tty/nozomi.c

1768

if (unlikely(!dc || !port))

drivers/tty/nozomi.c

315

struct nozomi *dc;

drivers/tty/nozomi.c

463

static void nozomi_setup_memory(struct nozomi *dc)

drivers/tty/nozomi.c

465

void __iomem *offset = dc->base_addr + dc->config_table.dl_start;

drivers/tty/nozomi.c

472

dc->port[PORT_MDM].dl_addr[CH_A] = offset;

drivers/tty/nozomi.c

473

dc->port[PORT_MDM].dl_addr[CH_B] =

drivers/tty/nozomi.c

474

(offset += dc->config_table.dl_mdm_len1);

drivers/tty/nozomi.c

475

dc->port[PORT_MDM].dl_size[CH_A] =

drivers/tty/nozomi.c

476

dc->config_table.dl_mdm_len1 - buff_offset;

drivers/tty/nozomi.c

477

dc->port[PORT_MDM].dl_size[CH_B] =

drivers/tty/nozomi.c

478

dc->config_table.dl_mdm_len2 - buff_offset;

drivers/tty/nozomi.c

481

dc->port[PORT_DIAG].dl_addr[CH_A] =

drivers/tty/nozomi.c

482

(offset += dc->config_table.dl_mdm_len2);

drivers/tty/nozomi.c

483

dc->port[PORT_DIAG].dl_size[CH_A] =

drivers/tty/nozomi.c

484

dc->config_table.dl_diag_len1 - buff_offset;

drivers/tty/nozomi.c

485

dc->port[PORT_DIAG].dl_addr[CH_B] =

drivers/tty/nozomi.c

486

(offset += dc->config_table.dl_diag_len1);

drivers/tty/nozomi.c

487

dc->port[PORT_DIAG].dl_size[CH_B] =

drivers/tty/nozomi.c

488

dc->config_table.dl_diag_len2 - buff_offset;

drivers/tty/nozomi.c

491

dc->port[PORT_APP1].dl_addr[CH_A] =

drivers/tty/nozomi.c

492

(offset += dc->config_table.dl_diag_len2);

drivers/tty/nozomi.c

493

dc->port[PORT_APP1].dl_size[CH_A] =

drivers/tty/nozomi.c

494

dc->config_table.dl_app1_len - buff_offset;

drivers/tty/nozomi.c

497

dc->port[PORT_APP2].dl_addr[CH_A] =

drivers/tty/nozomi.c

498

(offset += dc->config_table.dl_app1_len);

drivers/tty/nozomi.c

499

dc->port[PORT_APP2].dl_size[CH_A] =

drivers/tty/nozomi.c

500

dc->config_table.dl_app2_len - buff_offset;

drivers/tty/nozomi.c

503

dc->port[PORT_CTRL].dl_addr[CH_A] =

drivers/tty/nozomi.c

504

(offset += dc->config_table.dl_app2_len);

drivers/tty/nozomi.c

505

dc->port[PORT_CTRL].dl_size[CH_A] =

drivers/tty/nozomi.c

506

dc->config_table.dl_ctrl_len - buff_offset;

drivers/tty/nozomi.c

508

offset = dc->base_addr + dc->config_table.ul_start;

drivers/tty/nozomi.c

511

dc->port[PORT_MDM].ul_addr[CH_A] = offset;

drivers/tty/nozomi.c

512

dc->port[PORT_MDM].ul_size[CH_A] =

drivers/tty/nozomi.c

513

dc->config_table.ul_mdm_len1 - buff_offset;

drivers/tty/nozomi.c

514

dc->port[PORT_MDM].ul_addr[CH_B] =

drivers/tty/nozomi.c

515

(offset += dc->config_table.ul_mdm_len1);

drivers/tty/nozomi.c

516

dc->port[PORT_MDM].ul_size[CH_B] =

drivers/tty/nozomi.c

517

dc->config_table.ul_mdm_len2 - buff_offset;

drivers/tty/nozomi.c

520

dc->port[PORT_DIAG].ul_addr[CH_A] =

drivers/tty/nozomi.c

521

(offset += dc->config_table.ul_mdm_len2);

drivers/tty/nozomi.c

522

dc->port[PORT_DIAG].ul_size[CH_A] =

drivers/tty/nozomi.c

523

dc->config_table.ul_diag_len - buff_offset;

drivers/tty/nozomi.c

526

dc->port[PORT_APP1].ul_addr[CH_A] =

drivers/tty/nozomi.c

527

(offset += dc->config_table.ul_diag_len);

drivers/tty/nozomi.c

528

dc->port[PORT_APP1].ul_size[CH_A] =

drivers/tty/nozomi.c

529

dc->config_table.ul_app1_len - buff_offset;

drivers/tty/nozomi.c

532

dc->port[PORT_APP2].ul_addr[CH_A] =

drivers/tty/nozomi.c

533

(offset += dc->config_table.ul_app1_len);

drivers/tty/nozomi.c

534

dc->port[PORT_APP2].ul_size[CH_A] =

drivers/tty/nozomi.c

535

dc->config_table.ul_app2_len - buff_offset;

drivers/tty/nozomi.c

538

dc->port[PORT_CTRL].ul_addr[CH_A] =

drivers/tty/nozomi.c

539

(offset += dc->config_table.ul_app2_len);

drivers/tty/nozomi.c

540

dc->port[PORT_CTRL].ul_size[CH_A] =

drivers/tty/nozomi.c

541

dc->config_table.ul_ctrl_len - buff_offset;

drivers/tty/nozomi.c

546

static void dump_table(const struct nozomi *dc)

drivers/tty/nozomi.c

548

DBG3("signature: 0x%08X", dc->config_table.signature);

drivers/tty/nozomi.c

549

DBG3("version: 0x%04X", dc->config_table.version);

drivers/tty/nozomi.c

551

dc->config_table.product_information);

drivers/tty/nozomi.c

552

DBG3("toggle enabled: %d", dc->config_table.toggle.enabled);

drivers/tty/nozomi.c

553

DBG3("toggle up_mdm: %d", dc->config_table.toggle.mdm_ul);

drivers/tty/nozomi.c

554

DBG3("toggle dl_mdm: %d", dc->config_table.toggle.mdm_dl);

drivers/tty/nozomi.c

555

DBG3("toggle dl_dbg: %d", dc->config_table.toggle.diag_dl);

drivers/tty/nozomi.c

557

DBG3("dl_start: 0x%04X", dc->config_table.dl_start);

drivers/tty/nozomi.c

558

DBG3("dl_mdm_len0: 0x%04X, %d", dc->config_table.dl_mdm_len1,

drivers/tty/nozomi.c

559

dc->config_table.dl_mdm_len1);

drivers/tty/nozomi.c

560

DBG3("dl_mdm_len1: 0x%04X, %d", dc->config_table.dl_mdm_len2,

drivers/tty/nozomi.c

561

dc->config_table.dl_mdm_len2);

drivers/tty/nozomi.c

562

DBG3("dl_diag_len0: 0x%04X, %d", dc->config_table.dl_diag_len1,

drivers/tty/nozomi.c

563

dc->config_table.dl_diag_len1);

drivers/tty/nozomi.c

564

DBG3("dl_diag_len1: 0x%04X, %d", dc->config_table.dl_diag_len2,

drivers/tty/nozomi.c

565

dc->config_table.dl_diag_len2);

drivers/tty/nozomi.c

566

DBG3("dl_app1_len: 0x%04X, %d", dc->config_table.dl_app1_len,

drivers/tty/nozomi.c

567

dc->config_table.dl_app1_len);

drivers/tty/nozomi.c

568

DBG3("dl_app2_len: 0x%04X, %d", dc->config_table.dl_app2_len,

drivers/tty/nozomi.c

569

dc->config_table.dl_app2_len);

drivers/tty/nozomi.c

570

DBG3("dl_ctrl_len: 0x%04X, %d", dc->config_table.dl_ctrl_len,

drivers/tty/nozomi.c

571

dc->config_table.dl_ctrl_len);

drivers/tty/nozomi.c

572

DBG3("ul_start: 0x%04X, %d", dc->config_table.ul_start,

drivers/tty/nozomi.c

573

dc->config_table.ul_start);

drivers/tty/nozomi.c

574

DBG3("ul_mdm_len[0]: 0x%04X, %d", dc->config_table.ul_mdm_len1,

drivers/tty/nozomi.c

575

dc->config_table.ul_mdm_len1);

drivers/tty/nozomi.c

576

DBG3("ul_mdm_len[1]: 0x%04X, %d", dc->config_table.ul_mdm_len2,

drivers/tty/nozomi.c

577

dc->config_table.ul_mdm_len2);

drivers/tty/nozomi.c

578

DBG3("ul_diag_len: 0x%04X, %d", dc->config_table.ul_diag_len,

drivers/tty/nozomi.c

579

dc->config_table.ul_diag_len);

drivers/tty/nozomi.c

580

DBG3("ul_app1_len: 0x%04X, %d", dc->config_table.ul_app1_len,

drivers/tty/nozomi.c

581

dc->config_table.ul_app1_len);

drivers/tty/nozomi.c

582

DBG3("ul_app2_len: 0x%04X, %d", dc->config_table.ul_app2_len,

drivers/tty/nozomi.c

583

dc->config_table.ul_app2_len);

drivers/tty/nozomi.c

584

DBG3("ul_ctrl_len: 0x%04X, %d", dc->config_table.ul_ctrl_len,

drivers/tty/nozomi.c

585

dc->config_table.ul_ctrl_len);

drivers/tty/nozomi.c

588

static inline void dump_table(const struct nozomi *dc) { }

drivers/tty/nozomi.c

595

static int nozomi_read_config_table(struct nozomi *dc)

drivers/tty/nozomi.c

597

read_mem32((u32 *) &dc->config_table, dc->base_addr + 0,

drivers/tty/nozomi.c

600

if (dc->config_table.signature != NOZOMI_CONFIG_MAGIC) {

drivers/tty/nozomi.c

601

dev_err(&dc->pdev->dev, "ConfigTable Bad! 0x%08X != 0x%08X\n",

drivers/tty/nozomi.c

602

dc->config_table.signature, NOZOMI_CONFIG_MAGIC);

drivers/tty/nozomi.c

606

if ((dc->config_table.version == 0)

drivers/tty/nozomi.c

607

|| (dc->config_table.toggle.enabled == TOGGLE_VALID)) {

drivers/tty/nozomi.c

611

nozomi_setup_memory(dc);

drivers/tty/nozomi.c

613

dc->port[PORT_MDM].toggle_ul = dc->config_table.toggle.mdm_ul;

drivers/tty/nozomi.c

614

dc->port[PORT_MDM].toggle_dl = dc->config_table.toggle.mdm_dl;

drivers/tty/nozomi.c

615

dc->port[PORT_DIAG].toggle_dl = dc->config_table.toggle.diag_dl;

drivers/tty/nozomi.c

617

dc->port[PORT_MDM].toggle_ul,

drivers/tty/nozomi.c

618

dc->port[PORT_MDM].toggle_dl, dc->port[PORT_DIAG].toggle_dl);

drivers/tty/nozomi.c

620

dump_table(dc);

drivers/tty/nozomi.c

623

memset(&dc->port[i].ctrl_dl, 0, sizeof(struct ctrl_dl));

drivers/tty/nozomi.c

624

memset(&dc->port[i].ctrl_ul, 0, sizeof(struct ctrl_ul));

drivers/tty/nozomi.c

628

dc->last_ier = dc->last_ier | CTRL_DL;

drivers/tty/nozomi.c

629

writew(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

631

dc->state = NOZOMI_STATE_ALLOCATED;

drivers/tty/nozomi.c

632

dev_info(&dc->pdev->dev, "Initialization OK!\n");

drivers/tty/nozomi.c

636

if ((dc->config_table.version > 0)

drivers/tty/nozomi.c

637

&& (dc->config_table.toggle.enabled != TOGGLE_VALID)) {

drivers/tty/nozomi.c

641

dev_info(&dc->pdev->dev, "Version of card: %d\n",

drivers/tty/nozomi.c

642

dc->config_table.version);

drivers/tty/nozomi.c

645

nozomi_setup_memory(dc);

drivers/tty/nozomi.c

653

write_mem32(dc->port[PORT_MDM].ul_addr[CH_A],

drivers/tty/nozomi.c

655

write_mem32(dc->port[PORT_MDM].ul_addr[CH_B],

drivers/tty/nozomi.c

658

writew(MDM_UL | DIAG_DL | MDM_DL, dc->reg_fcr);

drivers/tty/nozomi.c

667

static void enable_transmit_ul(enum port_type port, struct nozomi *dc)

drivers/tty/nozomi.c

672

dc->last_ier |= mask[port];

drivers/tty/nozomi.c

673

writew(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

675

dev_err(&dc->pdev->dev, "Called with wrong port?\n");

drivers/tty/nozomi.c

680

static void disable_transmit_ul(enum port_type port, struct nozomi *dc)

drivers/tty/nozomi.c

686

dc->last_ier &= mask[port];

drivers/tty/nozomi.c

687

writew(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

689

dev_err(&dc->pdev->dev, "Called with wrong port?\n");

drivers/tty/nozomi.c

694

static void enable_transmit_dl(enum port_type port, struct nozomi *dc)

drivers/tty/nozomi.c

699

dc->last_ier |= mask[port];

drivers/tty/nozomi.c

700

writew(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

702

dev_err(&dc->pdev->dev, "Called with wrong port?\n");

drivers/tty/nozomi.c

707

static void disable_transmit_dl(enum port_type port, struct nozomi *dc)

drivers/tty/nozomi.c

713

dc->last_ier &= mask[port];

drivers/tty/nozomi.c

714

writew(dc->last_ier, dc->reg_ier);

drivers/tty/nozomi.c

716

dev_err(&dc->pdev->dev, "Called with wrong port?\n");

drivers/tty/nozomi.c

724

static int send_data(enum port_type index, struct nozomi *dc)

drivers/tty/nozomi.c

727

struct port *port = &dc->port[index];

drivers/tty/nozomi.c

733

size = kfifo_out(&port->fifo_ul, dc->send_buf,

drivers/tty/nozomi.c

743

write_mem32(addr + 4, (u32 *) dc->send_buf, size);

drivers/tty/nozomi.c

751

static int receive_data(enum port_type index, struct nozomi *dc)

drivers/tty/nozomi.c

756

struct port *port = &dc->port[index];

drivers/tty/nozomi.c

768

disable_transmit_dl(index, dc);

drivers/tty/nozomi.c

774

dev_err(&dc->pdev->dev, "size == 0?\n");

drivers/tty/nozomi.c

795

set_bit(index, &dc->flip);

drivers/tty/nozomi.c

851

static int receive_flow_control(struct nozomi *dc)

drivers/tty/nozomi.c

858

read_mem32((u32 *) &ctrl_dl, dc->port[PORT_CTRL].dl_addr[CH_A], 2);

drivers/tty/nozomi.c

881

if (dc->state == NOZOMI_STATE_ALLOCATED) {

drivers/tty/nozomi.c

886

dc->state = NOZOMI_STATE_READY;

drivers/tty/nozomi.c

887

dev_info(&dc->pdev->dev, "Device READY!\n");

drivers/tty/nozomi.c

891

dev_err(&dc->pdev->dev,

drivers/tty/nozomi.c

896

DBG1("0x%04X->0x%04X", *((u16 *)&dc->port[port].ctrl_dl),

drivers/tty/nozomi.c

899

old_ctrl = dc->port[port].ctrl_dl;

drivers/tty/nozomi.c

900

dc->port[port].ctrl_dl = ctrl_dl;

drivers/tty/nozomi.c

905

disable_transmit_ul(port, dc);

drivers/tty/nozomi.c

909

if (kfifo_len(&dc->port[port].fifo_ul)) {

drivers/tty/nozomi.c

913

kfifo_len(&dc->port[port].fifo_ul));

drivers/tty/nozomi.c

914

enable_transmit_ul(port, dc);

drivers/tty/nozomi.c

926

dc->port[port].tty_icount.cts++;

drivers/tty/nozomi.c

928

dc->port[port].tty_icount.dsr++;

drivers/tty/nozomi.c

930

dc->port[port].tty_icount.rng++;

drivers/tty/nozomi.c

932

dc->port[port].tty_icount.dcd++;

drivers/tty/nozomi.c

934

wake_up_interruptible(&dc->port[port].tty_wait);

drivers/tty/nozomi.c

938

dc->port[port].tty_icount.dcd, dc->port[port].tty_icount.cts,

drivers/tty/nozomi.c

939

dc->port[port].tty_icount.rng, dc->port[port].tty_icount.dsr);

drivers/tty/nozomi.c

945

const struct nozomi *dc)

drivers/tty/nozomi.c

957

dev_err(&dc->pdev->dev,

drivers/tty/nozomi.c

969

static int send_flow_control(struct nozomi *dc)

drivers/tty/nozomi.c

975

if (dc->port[i].update_flow_control) {

drivers/tty/nozomi.c

980

dc->port[i].ctrl_ul.port = port2ctrl(i, dc);

drivers/tty/nozomi.c

981

ctrl = (u16 *)&dc->port[i].ctrl_ul;

drivers/tty/nozomi.c

982

write_mem32(dc->port[PORT_CTRL].ul_addr[0], \

drivers/tty/nozomi.c

984

dc->port[i].update_flow_control = 0;

drivers/tty/nozomi.c

996

static int handle_data_dl(struct nozomi *dc, enum port_type port, u8 *toggle,

drivers/usb/core/devio.c

2464

struct usbdevfs_disconnect_claim dc;

drivers/usb/core/devio.c

2467

if (copy_from_user(&dc, arg, sizeof(dc)))

drivers/usb/core/devio.c

2470

intf = usb_ifnum_to_if(ps->dev, dc.interface);

drivers/usb/core/devio.c

2480

if ((dc.flags & USBDEVFS_DISCONNECT_CLAIM_IF_DRIVER) &&

drivers/usb/core/devio.c

2481

strncmp(dc.driver, intf->dev.driver->name,

drivers/usb/core/devio.c

2482

sizeof(dc.driver)) != 0)

drivers/usb/core/devio.c

2485

if ((dc.flags & USBDEVFS_DISCONNECT_CLAIM_EXCEPT_DRIVER) &&

drivers/usb/core/devio.c

2486

strncmp(dc.driver, intf->dev.driver->name,

drivers/usb/core/devio.c

2487

sizeof(dc.driver)) == 0)

drivers/usb/core/devio.c

2494

return claimintf(ps, dc.interface);

drivers/usb/musb/cppi_dma.h

128

struct dma_chan *dc;

drivers/usb/musb/musb_cppi41.c

148

struct dma_chan *dc = cppi41_channel->dc;

drivers/usb/musb/musb_cppi41.c

162

dma_desc = dmaengine_prep_slave_single(dc,

drivers/usb/musb/musb_cppi41.c

174

dma_async_issue_pending(dc);

drivers/usb/musb/musb_cppi41.c

243

dmaengine_tx_status(cppi41_channel->dc, cppi41_channel->cookie,

drivers/usb/musb/musb_cppi41.c

417

struct dma_chan *dc = cppi41_channel->dc;

drivers/usb/musb/musb_cppi41.c

465

dma_desc = dmaengine_prep_slave_single(dc, dma_addr, len, direction,

drivers/usb/musb/musb_cppi41.c

478

dma_async_issue_pending(dc);

drivers/usb/musb/musb_cppi41.c

498

if (!cppi41_channel->dc)

drivers/usb/musb/musb_cppi41.c

628

ret = dmaengine_terminate_all(cppi41_channel->dc);

drivers/usb/musb/musb_cppi41.c

647

struct dma_chan *dc;

drivers/usb/musb/musb_cppi41.c

651

dc = ctrl->tx_channel[i].dc;

drivers/usb/musb/musb_cppi41.c

652

if (dc)

drivers/usb/musb/musb_cppi41.c

653

dma_release_channel(dc);

drivers/usb/musb/musb_cppi41.c

654

dc = ctrl->rx_channel[i].dc;

drivers/usb/musb/musb_cppi41.c

655

if (dc)

drivers/usb/musb/musb_cppi41.c

656

dma_release_channel(dc);

drivers/usb/musb/musb_cppi41.c

680

struct dma_chan *dc;

drivers/usb/musb/musb_cppi41.c

719

dc = dma_request_chan(dev->parent, str);

drivers/usb/musb/musb_cppi41.c

720

if (IS_ERR(dc)) {

drivers/usb/musb/musb_cppi41.c

721

ret = dev_err_probe(dev, PTR_ERR(dc),

drivers/usb/musb/musb_cppi41.c

726

cppi41_channel->dc = dc;

drivers/usb/serial/safe_serial.c

105

#define MY_USB_DEVICE(vend, prod, dc, ic, isc) \

drivers/usb/serial/safe_serial.c

112

.bDeviceClass = (dc),\

drivers/video/fbdev/geode/gxfb.h

33

uint32_t dc[DC_REG_COUNT];

drivers/video/fbdev/geode/lxfb.h

43

uint32_t dc[DC_REG_COUNT];

drivers/video/fbdev/geode/lxfb_ops.c

604

memcpy(par->dc, par->dc_regs, sizeof(par->dc));

drivers/video/fbdev/geode/lxfb_ops.c

619

filt = par->dc[DC_IRQ_FILT_CTL] | DC_IRQ_FILT_CTL_H_FILT_SEL;

drivers/video/fbdev/geode/lxfb_ops.c

670

for (i = 0; i < ARRAY_SIZE(par->dc); i++) {

drivers/video/fbdev/geode/lxfb_ops.c

685

write_dc(par, i, par->dc[i] | DC_DV_CTL_CLEAR_DV_RAM);

drivers/video/fbdev/geode/lxfb_ops.c

704

write_dc(par, i, par->dc[i]);

drivers/video/fbdev/geode/lxfb_ops.c

714

filt = par->dc[DC_IRQ_FILT_CTL] | DC_IRQ_FILT_CTL_H_FILT_SEL;

drivers/video/fbdev/geode/lxfb_ops.c

806

write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG]);

drivers/video/fbdev/geode/lxfb_ops.c

808

write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG]);

drivers/video/fbdev/geode/suspend_gx.c

103

write_dc(par, i, par->dc[i] & ~(DC_DISPLAY_CFG_VDEN |

drivers/video/fbdev/geode/suspend_gx.c

122

write_dc(par, i, par->dc[i]);

drivers/video/fbdev/geode/suspend_gx.c

198

write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG] &

drivers/video/fbdev/geode/suspend_gx.c

201

write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG] &

drivers/video/fbdev/geode/suspend_gx.c

225

write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG]);

drivers/video/fbdev/geode/suspend_gx.c

227

write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG]);

drivers/video/fbdev/geode/suspend_gx.c

31

memcpy(par->dc, par->dc_regs, sizeof(par->dc));

drivers/video/fbdev/geode/suspend_gx.c

86

for (i = 0; i < ARRAY_SIZE(par->dc); i++) {

drivers/video/fbdev/geode/suspend_gx.c

95

write_dc(par, i, par->dc[i] & ~(DC_GENERAL_CFG_VIDE |

fs/f2fs/segment.c

1000

dc->bio_ref = 0;

fs/f2fs/segment.c

1004

return dc;

fs/f2fs/segment.c

1040

struct discard_cmd *dc;

fs/f2fs/segment.c

1043

dc = rb_entry(node, struct discard_cmd, rb_node);

fs/f2fs/segment.c

1045

if (blkaddr < dc->di.lstart)

fs/f2fs/segment.c

1047

else if (blkaddr >= dc->di.lstart + dc->di.len)

fs/f2fs/segment.c

1050

return dc;

fs/f2fs/segment.c

1064

struct discard_cmd *dc;

fs/f2fs/segment.c

1076

dc = rb_entry(*pnode, struct discard_cmd, rb_node);

fs/f2fs/segment.c

1078

if (blkaddr < dc->di.lstart)

fs/f2fs/segment.c

1080

else if (blkaddr >= dc->di.lstart + dc->di.len)

fs/f2fs/segment.c

1089

dc = rb_entry(parent, struct discard_cmd, rb_node);

fs/f2fs/segment.c

1091

if (parent && blkaddr > dc->di.lstart)

fs/f2fs/segment.c

1096

if (parent && blkaddr < dc->di.lstart)

fs/f2fs/segment.c

1103

tmp_node = rb_prev(&dc->rb_node);

fs/f2fs/segment.c

1107

tmp_node = rb_next(&dc->rb_node);

fs/f2fs/segment.c

1109

return dc;

fs/f2fs/segment.c

1113

struct discard_cmd *dc)

fs/f2fs/segment.c

1115

if (dc->state == D_DONE)

fs/f2fs/segment.c

1116

atomic_sub(dc->queued, &dcc->queued_discard);

fs/f2fs/segment.c

1118

list_del(&dc->list);

fs/f2fs/segment.c

1119

rb_erase_cached(&dc->rb_node, &dcc->root);

fs/f2fs/segment.c

1120

dcc->undiscard_blks -= dc->di.len;

fs/f2fs/segment.c

1122

kmem_cache_free(discard_cmd_slab, dc);

fs/f2fs/segment.c

1128

struct discard_cmd *dc)

fs/f2fs/segment.c

1133

trace_f2fs_remove_discard(dc->bdev, dc->di.start, dc->di.len);

fs/f2fs/segment.c

1135

spin_lock_irqsave(&dc->lock, flags);

fs/f2fs/segment.c

1136

if (dc->bio_ref) {

fs/f2fs/segment.c

1137

spin_unlock_irqrestore(&dc->lock, flags);

fs/f2fs/segment.c

1140

spin_unlock_irqrestore(&dc->lock, flags);

fs/f2fs/segment.c

1142

f2fs_bug_on(sbi, dc->ref);

fs/f2fs/segment.c

1144

if (dc->error == -EOPNOTSUPP)

fs/f2fs/segment.c

1145

dc->error = 0;

fs/f2fs/segment.c

1147

if (dc->error)

fs/f2fs/segment.c

1150

dc->di.lstart, dc->di.start, dc->di.len, dc->error);

fs/f2fs/segment.c

1151

__detach_discard_cmd(dcc, dc);

fs/f2fs/segment.c

1156

struct discard_cmd *dc = (struct discard_cmd *)bio->bi_private;

fs/f2fs/segment.c

1159

spin_lock_irqsave(&dc->lock, flags);

fs/f2fs/segment.c

1160

if (!dc->error)

fs/f2fs/segment.c

1161

dc->error = blk_status_to_errno(bio->bi_status);

fs/f2fs/segment.c

1162

dc->bio_ref--;

fs/f2fs/segment.c

1163

if (!dc->bio_ref && dc->state == D_SUBMIT) {

fs/f2fs/segment.c

1164

dc->state = D_DONE;

fs/f2fs/segment.c

1165

complete_all(&dc->wait);

fs/f2fs/segment.c

1167

spin_unlock_irqrestore(&dc->lock, flags);

fs/f2fs/segment.c

1250

struct discard_cmd *dc, blk_opf_t flag,

fs/f2fs/segment.c

1255

struct block_device *bdev = dc->bdev;

fs/f2fs/segment.c

1259

trace_f2fs_issue_reset_zone(bdev, dc->di.start);

fs/f2fs/segment.c

1261

spin_lock_irqsave(&dc->lock, flags);

fs/f2fs/segment.c

1262

dc->state = D_SUBMIT;

fs/f2fs/segment.c

1263

dc->bio_ref++;

fs/f2fs/segment.c

1264

spin_unlock_irqrestore(&dc->lock, flags);

fs/f2fs/segment.c

1270

dc->queued++;

fs/f2fs/segment.c

1271

list_move_tail(&dc->list, wait_list);

fs/f2fs/segment.c

1274

__check_sit_bitmap(sbi, dc->di.lstart, dc->di.lstart + dc->di.len);

fs/f2fs/segment.c

1276

bio->bi_iter.bi_sector = SECTOR_FROM_BLOCK(dc->di.start);

fs/f2fs/segment.c

1277

bio->bi_private = dc;

fs/f2fs/segment.c

1282

f2fs_update_iostat(sbi, NULL, FS_ZONE_RESET_IO, dc->di.len * F2FS_BLKSIZE);

fs/f2fs/segment.c

1289

struct discard_cmd *dc, int *issued)

fs/f2fs/segment.c

1291

struct block_device *bdev = dc->bdev;

fs/f2fs/segment.c

1300

if (dc->state != D_PREP)

fs/f2fs/segment.c

1313

if (f2fs_blkz_is_seq(sbi, devi, dc->di.start)) {

fs/f2fs/segment.c

1314

__submit_zone_reset_cmd(sbi, dc, flag,

fs/f2fs/segment.c

1330

trace_f2fs_issue_discard(bdev, dc->di.start, dc->di.len);

fs/f2fs/segment.c

1332

lstart = dc->di.lstart;

fs/f2fs/segment.c

1333

start = dc->di.start;

fs/f2fs/segment.c

1334

len = dc->di.len;

fs/f2fs/segment.c

1337

dc->di.len = 0;

fs/f2fs/segment.c

1353

dc->di.len += len;

fs/f2fs/segment.c

1363

spin_lock_irqsave(&dc->lock, flags);

fs/f2fs/segment.c

1365

dc->state = D_SUBMIT;

fs/f2fs/segment.c

1367

dc->state = D_PARTIAL;

fs/f2fs/segment.c

1368

dc->bio_ref++;

fs/f2fs/segment.c

1369

spin_unlock_irqrestore(&dc->lock, flags);

fs/f2fs/segment.c

1372

dc->queued++;

fs/f2fs/segment.c

1373

list_move_tail(&dc->list, wait_list);

fs/f2fs/segment.c

1378

bio->bi_private = dc;

fs/f2fs/segment.c

1407

struct discard_cmd *dc;

fs/f2fs/segment.c

1413

dc = rb_entry(parent, struct discard_cmd, rb_node);

fs/f2fs/segment.c

1415

if (lstart < dc->di.lstart) {

fs/f2fs/segment.c

1417

} else if (lstart >= dc->di.lstart + dc->di.len) {

fs/f2fs/segment.c

1426

dc = __create_discard_cmd(sbi, bdev, lstart, start, len);

fs/f2fs/segment.c

1428

rb_link_node(&dc->rb_node, parent, p);

fs/f2fs/segment.c

1429

rb_insert_color_cached(&dc->rb_node, &dcc->root, leftmost);

fs/f2fs/segment.c

1433

struct discard_cmd *dc)

fs/f2fs/segment.c

1435

list_move_tail(&dc->list, &dcc->pend_list[plist_idx(dc->di.len)]);

fs/f2fs/segment.c

1439

struct discard_cmd *dc, block_t blkaddr)

fs/f2fs/segment.c

1442

struct discard_info di = dc->di;

fs/f2fs/segment.c

1445

if (dc->state == D_DONE || dc->di.len == 1) {

fs/f2fs/segment.c

1446

__remove_discard_cmd(sbi, dc);

fs/f2fs/segment.c

1453

dc->di.len = blkaddr - dc->di.lstart;

fs/f2fs/segment.c

1454

dcc->undiscard_blks += dc->di.len;

fs/f2fs/segment.c

1455

__relocate_discard_cmd(dcc, dc);

fs/f2fs/segment.c

1461

__insert_discard_cmd(sbi, dc->bdev, blkaddr + 1,

fs/f2fs/segment.c

1465

dc->di.lstart++;

fs/f2fs/segment.c

1466

dc->di.len--;

fs/f2fs/segment.c

1467

dc->di.start++;

fs/f2fs/segment.c

1468

dcc->undiscard_blks += dc->di.len;

fs/f2fs/segment.c

1469

__relocate_discard_cmd(dcc, dc);

fs/f2fs/segment.c

1480

struct discard_cmd *dc;

fs/f2fs/segment.c

1487

dc = __lookup_discard_cmd_ret(&dcc->root, lstart,

fs/f2fs/segment.c

1489

if (dc)

fs/f2fs/segment.c

1490

prev_dc = dc;

fs/f2fs/segment.c

1599

struct discard_cmd *dc;

fs/f2fs/segment.c

1604

dc = __lookup_discard_cmd_ret(&dcc->root, dcc->next_pos,

fs/f2fs/segment.c

1606

if (!dc)

fs/f2fs/segment.c

1607

dc = next_dc;

fs/f2fs/segment.c

1611

while (dc) {

fs/f2fs/segment.c

1615

if (dc->state != D_PREP)

fs/f2fs/segment.c

1626

dcc->next_pos = dc->di.lstart + dc->di.len;

fs/f2fs/segment.c

1627

err = __submit_discard_cmd(sbi, dpolicy, dc, issued);

fs/f2fs/segment.c

1632

node = rb_next(&dc->rb_node);

fs/f2fs/segment.c

1634

__remove_discard_cmd(sbi, dc);

fs/f2fs/segment.c

1635

dc = rb_entry_safe(node, struct discard_cmd, rb_node);

fs/f2fs/segment.c

1640

if (!dc)

fs/f2fs/segment.c

1656

struct discard_cmd *dc, *tmp;

fs/f2fs/segment.c

1688

list_for_each_entry_safe(dc, tmp, pend_list, list) {

fs/f2fs/segment.c

1689

f2fs_bug_on(sbi, dc->state != D_PREP);

fs/f2fs/segment.c

1706

__submit_discard_cmd(sbi, dpolicy, dc, &issued);

fs/f2fs/segment.c

1735

struct discard_cmd *dc, *tmp;

fs/f2fs/segment.c

1742

list_for_each_entry_safe(dc, tmp, pend_list, list) {

fs/f2fs/segment.c

1743

f2fs_bug_on(sbi, dc->state != D_PREP);

fs/f2fs/segment.c

1744

__remove_discard_cmd(sbi, dc);

fs/f2fs/segment.c

1759

struct discard_cmd *dc)

fs/f2fs/segment.c

1764

wait_for_completion_io(&dc->wait);

fs/f2fs/segment.c

1766

f2fs_bug_on(sbi, dc->state != D_DONE);

fs/f2fs/segment.c

1767

dc->ref--;

fs/f2fs/segment.c

1768

if (!dc->ref) {

fs/f2fs/segment.c

1769

if (!dc->error)

fs/f2fs/segment.c

1770

len = dc->di.len;

fs/f2fs/segment.c

1771

__remove_discard_cmd(sbi, dc);

fs/f2fs/segment.c

1785

struct discard_cmd *dc = NULL, *iter, *tmp;

fs/f2fs/segment.c

1789

dc = NULL;

fs/f2fs/segment.c

1805

dc = iter;

fs/f2fs/segment.c

1811

if (dc) {

fs/f2fs/segment.c

1812

trimmed += __wait_one_discard_bio(sbi, dc);

fs/f2fs/segment.c

1841

struct discard_cmd *dc;

fs/f2fs/segment.c

1845

dc = __lookup_discard_cmd(sbi, blkaddr);

fs/f2fs/segment.c

1847

if (dc && f2fs_sb_has_blkzoned(sbi) && bdev_is_zoned(dc->bdev)) {

fs/f2fs/segment.c

1848

int devi = f2fs_bdev_index(sbi, dc->bdev);

fs/f2fs/segment.c

1855

if (f2fs_blkz_is_seq(sbi, devi, dc->di.start)) {

fs/f2fs/segment.c

1857

if (dc->state == D_PREP)

fs/f2fs/segment.c

1858

__submit_zone_reset_cmd(sbi, dc, REQ_SYNC,

fs/f2fs/segment.c

1860

dc->ref++;

fs/f2fs/segment.c

1863

__wait_one_discard_bio(sbi, dc);

fs/f2fs/segment.c

1868

if (dc) {

fs/f2fs/segment.c

1869

if (dc->state == D_PREP) {

fs/f2fs/segment.c

1870

__punch_discard_cmd(sbi, dc, blkaddr);

fs/f2fs/segment.c

1872

dc->ref++;

fs/f2fs/segment.c

1879

__wait_one_discard_bio(sbi, dc);

fs/f2fs/segment.c

3415

struct discard_cmd *dc;

fs/f2fs/segment.c

3427

dc = __lookup_discard_cmd_ret(&dcc->root, start,

fs/f2fs/segment.c

3429

if (!dc)

fs/f2fs/segment.c

3430

dc = next_dc;

fs/f2fs/segment.c

3434

while (dc && dc->di.lstart <= end) {

fs/f2fs/segment.c

3438

if (dc->di.len < dpolicy->granularity)

fs/f2fs/segment.c

3441

if (dc->state != D_PREP) {

fs/f2fs/segment.c

3442

list_move_tail(&dc->list, &dcc->fstrim_list);

fs/f2fs/segment.c

3446

err = __submit_discard_cmd(sbi, dpolicy, dc, &issued);

fs/f2fs/segment.c

3449

start = dc->di.lstart + dc->di.len;

fs/f2fs/segment.c

3452

__remove_discard_cmd(sbi, dc);

fs/f2fs/segment.c

3461

node = rb_next(&dc->rb_node);

fs/f2fs/segment.c

3463

__remove_discard_cmd(sbi, dc);

fs/f2fs/segment.c

3464

dc = rb_entry_safe(node, struct discard_cmd, rb_node);

fs/f2fs/segment.c

981

struct discard_cmd *dc;

fs/f2fs/segment.c

987

dc = f2fs_kmem_cache_alloc(discard_cmd_slab, GFP_NOFS, true, NULL);

fs/f2fs/segment.c

988

INIT_LIST_HEAD(&dc->list);

fs/f2fs/segment.c

989

dc->bdev = bdev;

fs/f2fs/segment.c

990

dc->di.lstart = lstart;

fs/f2fs/segment.c

991

dc->di.start = start;

fs/f2fs/segment.c

992

dc->di.len = len;

fs/f2fs/segment.c

993

dc->ref = 0;

fs/f2fs/segment.c

994

dc->state = D_PREP;

fs/f2fs/segment.c

995

dc->queued = 0;

fs/f2fs/segment.c

996

dc->error = 0;

fs/f2fs/segment.c

997

init_completion(&dc->wait);

fs/f2fs/segment.c

998

list_add_tail(&dc->list, pend_list);

fs/f2fs/segment.c

999

spin_lock_init(&dc->lock);

fs/f2fs/sysfs.c

1839

struct discard_cmd *dc, *tmp;

fs/f2fs/sysfs.c

1845

list_for_each_entry_safe(dc, tmp, pend_list, list)

fs/nfsd/nfs4state.c

4680

struct nfsd4_destroy_clientid *dc = &u->destroy_clientid;

fs/nfsd/nfs4state.c

4687

unconf = find_unconfirmed_client(&dc->clientid, true, nn);

fs/nfsd/nfs4state.c

4688

conf = find_confirmed_client(&dc->clientid, true, nn);

fs/nfsd/nfs4xdr.c

2073

struct nfsd4_destroy_clientid *dc = &u->destroy_clientid;

fs/nfsd/nfs4xdr.c

2074

return nfsd4_decode_clientid4(argp, &dc->clientid);

fs/unicode/mkutf8data.c

2494

unsigned int *dc;

fs/unicode/mkutf8data.c

2512

dc = unicode_data[*um].utf32nfdi;

fs/unicode/mkutf8data.c

2513

if (dc) {

fs/unicode/mkutf8data.c

2514

for (j = 0; dc[j]; j++)

fs/unicode/mkutf8data.c

2515

mapping[i++] = dc[j];

fs/unicode/mkutf8data.c

2549

unsigned int *dc;

fs/unicode/mkutf8data.c

2566

dc = unicode_data[*um].utf32nfdicf;

fs/unicode/mkutf8data.c

2567

if (dc) {

fs/unicode/mkutf8data.c

2568

for (j = 0; dc[j]; j++)

fs/unicode/mkutf8data.c

2569

mapping[i++] = dc[j];

include/drm/drm_mipi_dbi.h

160

struct gpio_desc *dc);

include/drm/drm_mipi_dbi.h

71

struct gpio_desc *dc;

include/linux/mlx5/mlx5_ifc_fpga.h

47

u8 dc[0x1];

include/media/v4l2-mem2mem.h

473

struct v4l2_decoder_cmd *dc);

include/media/v4l2-mem2mem.h

906

struct v4l2_decoder_cmd *dc);

include/media/v4l2-mem2mem.h

910

struct v4l2_decoder_cmd *dc);

include/media/v4l2-mem2mem.h

912

struct v4l2_decoder_cmd *dc);

include/media/v4l2-mem2mem.h

914

struct v4l2_decoder_cmd *dc);

include/trace/events/tegra_apb_dma.h

11

TP_PROTO(struct dma_chan *dc, dma_cookie_t cookie, struct dma_tx_state *state),

include/trace/events/tegra_apb_dma.h

12

TP_ARGS(dc, cookie, state),

include/trace/events/tegra_apb_dma.h

14

__string(chan, dev_name(&dc->dev->device))

include/trace/events/tegra_apb_dma.h

28

TP_PROTO(struct dma_chan *dc, int count, void *ptr),

include/trace/events/tegra_apb_dma.h

29

TP_ARGS(dc, count, ptr),

include/trace/events/tegra_apb_dma.h

31

__string(chan, dev_name(&dc->dev->device))

include/trace/events/tegra_apb_dma.h

45

TP_PROTO(struct dma_chan *dc, int irq),

include/trace/events/tegra_apb_dma.h

46

TP_ARGS(dc, irq),

include/trace/events/tegra_apb_dma.h

48

__string(chan, dev_name(&dc->dev->device))

include/video/imx-ipu-v3.h

286

void ipu_dc_put(struct ipu_dc *dc);

include/video/imx-ipu-v3.h

287

int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,

include/video/imx-ipu-v3.h

290

void ipu_dc_enable_channel(struct ipu_dc *dc);

include/video/imx-ipu-v3.h

291

void ipu_dc_disable_channel(struct ipu_dc *dc);

include/video/imx-ipu-v3.h

483

int dc;

lib/crypto/x86/curve25519.h

1001

fmul2(dc, dc, ab, tmp2);

lib/crypto/x86/curve25519.h

1032

u64 *dc = tmp1 + (u32)8U;

lib/crypto/x86/curve25519.h

1035

fsqr2(dc, ab, tmp2);

lib/crypto/x86/curve25519.h

1043

fmul2(nq, dc, ab, tmp2);

lib/crypto/x86/curve25519.h

982

u64 *dc = tmp1 + (u32)8U;

lib/crypto/x86/curve25519.h

997

d0 = dc;

lib/crypto/x86/curve25519.h

998

c0 = dc + (u32)4U;

net/core/utils.c

190

u8 *d, *dc = NULL;

net/core/utils.c

228

dc = d;

net/core/utils.c

230

if (dc - dbuf >= sizeof(dbuf))

net/core/utils.c

263

if (!dc && d + 2 < dbuf + sizeof(dbuf)) {

net/core/utils.c

271

if ((dc && d + 4 < dbuf + sizeof(dbuf)) ||

net/core/utils.c

284

if (dc) {

net/core/utils.c

285

while (d >= dc)

net/core/utils.c

287

while (i >= dc - dbuf)

net/wireless/core.h

281

} dc;

net/wireless/sme.c

1421

ev->dc.ie = ((u8 *)ev) + sizeof(*ev);

net/wireless/sme.c

1422

ev->dc.ie_len = ie_len;

net/wireless/sme.c

1423

memcpy((void *)ev->dc.ie, ie, ie_len);

net/wireless/sme.c

1424

ev->dc.reason = reason;

net/wireless/sme.c

1425

ev->dc.locally_generated = locally_generated;

net/wireless/util.c

1164

ev->dc.ie, ev->dc.ie_len,

net/wireless/util.c

1165

ev->dc.reason,

net/wireless/util.c

1166

!ev->dc.locally_generated);