usr/src/boot/efi/include/Protocol/PciRootBridgeIo.h
102
#define EFI_PCI_ADDRESS(bus, dev, func, reg) \
usr/src/boot/efi/include/Protocol/PciRootBridgeIo.h
107
(((UINTN) (reg)) < 256 ? ((UINTN) (reg)) : (UINT64) (LShiftU64 ((UINT64) (reg), 32))))
usr/src/boot/i386/libi386/vbe.c
191
biosvbe_palette_data(int mode, int reg, struct paletteentry *pe)
usr/src/boot/i386/libi386/vbe.c
197
v86.edx = reg;
usr/src/boot/sys/amd64/include/asmacros.h
208
#define PCPU_ADDR(member, reg) \
usr/src/boot/sys/amd64/include/asmacros.h
209
movq %gs:PC_PRVSPACE, reg ; \
usr/src/boot/sys/amd64/include/asmacros.h
210
addq $PC_ ## member, reg
usr/src/boot/sys/amd64/include/cpufunc.h
475
rxcr(u_int reg)
usr/src/boot/sys/amd64/include/cpufunc.h
479
__asm __volatile("xgetbv" : "=a" (low), "=d" (high) : "c" (reg));
usr/src/boot/sys/amd64/include/cpufunc.h
484
load_xcr(u_int reg, u_long val)
usr/src/boot/sys/amd64/include/cpufunc.h
490
__asm __volatile("xsetbv" : : "c" (reg), "a" (low), "d" (high));
usr/src/boot/sys/i386/include/cpufunc.h
449
rxcr(u_int reg)
usr/src/boot/sys/i386/include/cpufunc.h
453
__asm __volatile("xgetbv" : "=a" (low), "=d" (high) : "c" (reg));
usr/src/boot/sys/i386/include/cpufunc.h
458
load_xcr(u_int reg, uint64_t val)
usr/src/boot/sys/i386/include/cpufunc.h
464
__asm __volatile("xsetbv" : : "c" (reg), "a" (low), "d" (high));
usr/src/boot/sys/i386/include/cpufunc.h
687
read_cyrix_reg(u_char reg)
usr/src/boot/sys/i386/include/cpufunc.h
689
outb(0x22, reg);
usr/src/boot/sys/i386/include/cpufunc.h
694
write_cyrix_reg(u_char reg, u_char data)
usr/src/boot/sys/i386/include/cpufunc.h
696
outb(0x22, reg);
usr/src/boot/sys/i386/include/cpufunc.h
777
u_char read_cyrix_reg(u_char reg);
usr/src/boot/sys/i386/include/cpufunc.h
786
void write_cyrix_reg(u_char reg, u_char data);
usr/src/cmd/amdzen/udf.c
125
reg = (uint16_t)lval;
usr/src/cmd/amdzen/udf.c
131
udf_readone(fd, inst, func, reg, flags);
usr/src/cmd/amdzen/udf.c
32
udf_readone(int fd, uint8_t inst, uint8_t func, uint16_t reg,
usr/src/cmd/amdzen/udf.c
42
zui.zui_reg = reg;
usr/src/cmd/amdzen/udf.c
51
inst, func, reg, zui.zui_data);
usr/src/cmd/amdzen/udf.c
54
func, reg, zui.zui_data);
usr/src/cmd/amdzen/udf.c
68
uint16_t reg;
usr/src/cmd/awk/lex.c
170
int reg = 0; /* 1 => return a REGEXPR now */
usr/src/cmd/awk/lex.c
186
if (reg) {
usr/src/cmd/awk/lex.c
187
reg = 0;
usr/src/cmd/awk/lex.c
551
reg = 1;
usr/src/cmd/basename/basename.c
141
r = regcomp(®, suf_pat, 0);
usr/src/cmd/basename/basename.c
148
r = regexec(®, string, 2, pmatch, 0);
usr/src/cmd/basename/basename.c
48
regex_t reg;
usr/src/cmd/bhyve/amd64/task_switch.c
113
GETREG(struct vcpu *vcpu, int reg)
usr/src/cmd/bhyve/amd64/task_switch.c
118
error = vm_get_register(vcpu, reg, &val);
usr/src/cmd/bhyve/amd64/task_switch.c
124
SETREG(struct vcpu *vcpu, int reg, uint64_t val)
usr/src/cmd/bhyve/amd64/task_switch.c
128
error = vm_set_register(vcpu, reg, val);
usr/src/cmd/bhyve/amd64/task_switch.c
190
int error, reg;
usr/src/cmd/bhyve/amd64/task_switch.c
192
reg = ISLDT(sel) ? VM_REG_GUEST_LDTR : VM_REG_GUEST_GDTR;
usr/src/cmd/bhyve/amd64/task_switch.c
193
error = vm_get_desc(vcpu, reg, &base, &limit, &access);
usr/src/cmd/bhyve/amd64/task_switch.c
196
if (reg == VM_REG_GUEST_LDTR) {
usr/src/cmd/bhyve/amd64/task_switch.c
223
int error, reg;
usr/src/cmd/bhyve/amd64/task_switch.c
225
reg = ISLDT(sel) ? VM_REG_GUEST_LDTR : VM_REG_GUEST_GDTR;
usr/src/cmd/bhyve/amd64/task_switch.c
226
error = vm_get_desc(vcpu, reg, &base, &limit, &access);
usr/src/cmd/bhyve/amd64/task_switch.c
480
update_seg_desc(struct vcpu *vcpu, int reg, struct seg_desc *sd)
usr/src/cmd/bhyve/amd64/task_switch.c
484
error = vm_set_desc(vcpu, reg, sd->base, sd->limit, sd->access);
usr/src/cmd/bhyve/common/gdb.c
1003
uintmax_t reg;
usr/src/cmd/bhyve/common/gdb.c
1005
reg = parse_integer(data, len);
usr/src/cmd/bhyve/common/gdb.c
1006
if (reg >= nitems(gdb_regset)) {
usr/src/cmd/bhyve/common/gdb.c
1011
if (vm_get_register(vcpus[cur_vcpu], gdb_regset[reg].id, ®val) ==
usr/src/cmd/bhyve/common/gdb.c
1018
append_unsigned_native(regval, gdb_regset[reg].size);
usr/src/cmd/bhyve/common/pci_e82545.c
100
#define E82545_ARRAY_ENTRY(reg, offset) (reg + (offset<<2))
usr/src/cmd/bhyve/common/pci_e82545.c
1600
e82545_write_ra(struct e82545_softc *sc, int reg, uint32_t wval)
usr/src/cmd/bhyve/common/pci_e82545.c
1605
idx = reg >> 1;
usr/src/cmd/bhyve/common/pci_e82545.c
1610
if (reg & 0x1) {
usr/src/cmd/bhyve/common/pci_e82545.c
1626
e82545_read_ra(struct e82545_softc *sc, int reg)
usr/src/cmd/bhyve/common/pci_e82545.c
1632
idx = reg >> 1;
usr/src/cmd/bhyve/common/pci_e82545.c
1637
if (reg & 0x1) {
usr/src/cmd/bhyve/common/pci_emul.c
357
const uint32_t reg, const uint8_t size, const uint32_t def)
usr/src/cmd/bhyve/common/pci_emul.c
369
switch (reg) {
usr/src/cmd/bhyve/common/pci_emul.c
392
return pci_host_read_config(host_sel, reg, size);
usr/src/cmd/bhyve/common/pci_emul.h
243
uint32_t reg, uint8_t size, uint32_t def);
usr/src/cmd/bhyve/common/pci_irq.c
107
if (pirq->reg != (val & (PIRQ_DIS | PIRQ_IRQ))) {
usr/src/cmd/bhyve/common/pci_irq.c
108
if (pirq->active_count != 0 && pirq_valid_irq(pirq->reg))
usr/src/cmd/bhyve/common/pci_irq.c
109
vm_isa_deassert_irq(ctx, pirq->reg & PIRQ_IRQ, -1);
usr/src/cmd/bhyve/common/pci_irq.c
110
pirq->reg = val & (PIRQ_DIS | PIRQ_IRQ);
usr/src/cmd/bhyve/common/pci_irq.c
111
if (pirq->active_count != 0 && pirq_valid_irq(pirq->reg))
usr/src/cmd/bhyve/common/pci_irq.c
112
vm_isa_assert_irq(ctx, pirq->reg & PIRQ_IRQ, -1);
usr/src/cmd/bhyve/common/pci_irq.c
143
pirqs[i].reg = PIRQ_DIS;
usr/src/cmd/bhyve/common/pci_irq.c
168
if (pirq->active_count == 1 && pirq_valid_irq(pirq->reg)) {
usr/src/cmd/bhyve/common/pci_irq.c
169
vm_isa_assert_irq(pi->pi_vmctx, pirq->reg & PIRQ_IRQ,
usr/src/cmd/bhyve/common/pci_irq.c
191
if (pirq->active_count == 0 && pirq_valid_irq(pirq->reg)) {
usr/src/cmd/bhyve/common/pci_irq.c
192
vm_isa_deassert_irq(pi->pi_vmctx, pirq->reg & PIRQ_IRQ,
usr/src/cmd/bhyve/common/pci_irq.c
227
if (pirqs[best_pin].reg == PIRQ_DIS) {
usr/src/cmd/bhyve/common/pci_irq.c
240
pirqs[best_pin].reg = best_irq;
usr/src/cmd/bhyve/common/pci_irq.c
251
return (pirqs[pin - 1].reg & PIRQ_IRQ);
usr/src/cmd/bhyve/common/pci_irq.c
67
uint8_t reg;
usr/src/cmd/bhyve/common/pci_irq.c
83
pirq_valid_irq(int reg)
usr/src/cmd/bhyve/common/pci_irq.c
86
if (reg & PIRQ_DIS)
usr/src/cmd/bhyve/common/pci_irq.c
88
return (IRQ_PERMITTED(reg & PIRQ_IRQ));
usr/src/cmd/bhyve/common/pci_irq.c
96
return (pirqs[pin - 1].reg);
usr/src/cmd/bhyve/common/pci_passthru.c
110
passthru_read_config(const struct passthru_softc *sc, long reg, int width)
usr/src/cmd/bhyve/common/pci_passthru.c
114
pi.pci_off = reg;
usr/src/cmd/bhyve/common/pci_passthru.c
1184
pci_host_read_config(const struct pcisel *sel __unused, long reg __unused,
usr/src/cmd/bhyve/common/pci_passthru.c
1191
pci_host_write_config(const struct pcisel *sel __unused, long reg __unused,
usr/src/cmd/bhyve/common/pci_passthru.c
124
passthru_write_config(const struct passthru_softc *sc, long reg, int width,
usr/src/cmd/bhyve/common/pci_passthru.c
129
pi.pci_off = reg;
usr/src/cmd/bhyve/common/pci_passthru.c
676
set_pcir_handler(struct passthru_softc *sc, int reg, int len,
usr/src/cmd/bhyve/common/pci_passthru.c
679
if (reg > PCI_REGMAX || reg + len > PCI_REGMAX + 1)
usr/src/cmd/bhyve/common/pci_passthru.c
682
for (int i = reg; i < reg + len; ++i) {
usr/src/cmd/bhyve/common/pci_passthru.h
22
uint32_t pci_host_read_config(const struct pcisel *sel, long reg, int width);
usr/src/cmd/bhyve/common/pci_passthru.h
23
void pci_host_write_config(const struct pcisel *sel, long reg, int width,
usr/src/cmd/bhyve/common/pci_passthru.h
30
int set_pcir_handler(struct passthru_softc *sc, int reg, int len,
usr/src/cmd/bhyve/common/pci_xhci.c
2196
uint32_t reg;
usr/src/cmd/bhyve/common/pci_xhci.c
2215
reg = portregs->portsc;
usr/src/cmd/bhyve/common/pci_xhci.c
2218
reg = portregs->portpmsc;
usr/src/cmd/bhyve/common/pci_xhci.c
2221
reg = portregs->portli;
usr/src/cmd/bhyve/common/pci_xhci.c
2224
reg = portregs->porthlpmc;
usr/src/cmd/bhyve/common/pci_xhci.c
2229
reg = 0xffffffff;
usr/src/cmd/bhyve/common/pci_xhci.c
2234
offset, port, reg));
usr/src/cmd/bhyve/common/pci_xhci.c
2236
return (reg);
usr/src/cmd/bhyve/common/uart_emul.c
363
uint8_t iir, intr_reason, reg;
usr/src/cmd/bhyve/common/uart_emul.c
372
reg = sc->dll;
usr/src/cmd/bhyve/common/uart_emul.c
377
reg = sc->dlh;
usr/src/cmd/bhyve/common/uart_emul.c
384
reg = uart_rxfifo_getchar(sc->backend);
usr/src/cmd/bhyve/common/uart_emul.c
387
reg = sc->ier;
usr/src/cmd/bhyve/common/uart_emul.c
402
reg = iir;
usr/src/cmd/bhyve/common/uart_emul.c
405
reg = sc->lcr;
usr/src/cmd/bhyve/common/uart_emul.c
408
reg = sc->mcr;
usr/src/cmd/bhyve/common/uart_emul.c
420
reg = sc->lsr;
usr/src/cmd/bhyve/common/uart_emul.c
429
reg = sc->msr;
usr/src/cmd/bhyve/common/uart_emul.c
433
reg = sc->scr;
usr/src/cmd/bhyve/common/uart_emul.c
436
reg = 0xFF;
usr/src/cmd/bhyve/common/uart_emul.c
444
return (reg);
usr/src/cmd/cxgbetool/cxgbetool.c
437
struct t4_reg32_cmd reg;
usr/src/cmd/cxgbetool/cxgbetool.c
439
reg.reg = addr;
usr/src/cmd/cxgbetool/cxgbetool.c
440
reg.value = val;
usr/src/cmd/cxgbetool/cxgbetool.c
442
if (doit(iff_name, T4_IOCTL_PUT32, ®) < 0)
usr/src/cmd/cxgbetool/cxgbetool.c
449
struct t4_reg32_cmd reg;
usr/src/cmd/cxgbetool/cxgbetool.c
451
reg.reg = addr;
usr/src/cmd/cxgbetool/cxgbetool.c
453
if (doit(iff_name, T4_IOCTL_GET32, ®) < 0)
usr/src/cmd/cxgbetool/cxgbetool.c
455
return reg.value;
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fabric.c
886
#define SET_TBL(n, err, reg, sz) \
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fabric.c
888
fab_master_err_tbl[n].reg_offset = offsetof(fab_data_t, reg); \
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
139
uint64_t reg;
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
155
if (nvlist_lookup_uint64(erpt, "tlu-cess", ®) == 0) {
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
156
data->pcie_ce_status = (uint32_t)reg | (uint32_t)(reg >> 32);
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
167
uint64_t reg;
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
195
if (nvlist_lookup_uint64(erpt, "tlu-uess", ®) == 0) {
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
196
data->pcie_ue_status = (uint32_t)reg | (uint32_t)(reg >> 32);
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
200
if ((reg & (uint64_t)entry->fire_bit) &&
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
211
if (nvlist_lookup_uint64(erpt, "tlu-tueh1l", ®) == 0) {
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
212
data->pcie_ue_hdr[0] = (uint32_t)(reg >> 32);
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
213
data->pcie_ue_hdr[1] = (uint32_t)(reg);
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
215
if (nvlist_lookup_uint64(erpt, "tlu-tueh2l", ®) == 0) {
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
216
data->pcie_ue_hdr[2] = (uint32_t)(reg >> 32);
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
217
data->pcie_ue_hdr[3] = (uint32_t)(reg);
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
227
data->pcie_ue_tgt_addr = reg;
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
241
if (nvlist_lookup_uint64(erpt, "tlu-rueh1l", ®) == 0) {
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
242
data->pcie_ue_hdr[0] = (uint32_t)(reg >> 32);
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
243
data->pcie_ue_hdr[1] = (uint32_t)(reg);
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
245
if (nvlist_lookup_uint64(erpt, "tlu-rueh2l", ®) == 0) {
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
246
data->pcie_ue_hdr[2] = (uint32_t)(reg >> 32);
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
247
data->pcie_ue_hdr[3] = (uint32_t)(reg);
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
258
uint64_t reg;
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
275
if (nvlist_lookup_uint64(erpt, "tlu-roeeh1l", ®) == 0) {
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
276
data->pcie_ue_hdr[0] = (uint32_t)(reg >> 32);
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
277
data->pcie_ue_hdr[1] = (uint32_t)(reg);
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
279
if (nvlist_lookup_uint64(erpt, "tlu-roeeh2l", ®) == 0) {
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
280
data->pcie_ue_hdr[2] = (uint32_t)(reg >> 32);
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
281
data->pcie_ue_hdr[3] = (uint32_t)(reg);
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
319
uint64_t reg;
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
350
if (nvlist_lookup_uint64(erpt, "mmu-tfsr", ®) == 0) {
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
351
fmd_hdl_debug(hdl, "tfsr 0x%llx\n", reg);
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
353
temp = (reg & 0x3F0000) >> 16;
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
357
temp = (reg & 0xFFFF);
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
362
if (nvlist_lookup_uint64(erpt, "mmu-tfar", ®) == 0) {
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
363
fmd_hdl_debug(hdl, "tfar 0x%llx\n", reg);
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
365
data->pcie_ue_hdr[2] = reg;
usr/src/cmd/fm/modules/common/fabric-xlate/fx_fire.c
367
data->pcie_ue_tgt_addr = reg;
usr/src/cmd/fm/modules/common/fabric-xlate/fx_subr.c
189
uint32_t reg;
usr/src/cmd/fm/modules/common/fabric-xlate/fx_subr.c
194
reg = (uint32_t)*((uint16_t *)
usr/src/cmd/fm/modules/common/fabric-xlate/fx_subr.c
197
reg = *((uint32_t *)((uint32_t)data + tbl->reg_offset));
usr/src/cmd/fm/modules/common/fabric-xlate/fx_subr.c
201
if (!(reg & entry->reg_bit))
usr/src/cmd/fm/modules/common/fabric-xlate/fx_subr.c
221
fmd_hdl_debug(hdl, "Sending ereport: %s 0x%x\n", fab_buf, reg);
usr/src/cmd/fs.d/udfs/common/ud_lib.c
1485
make_regid(ud_handle_t h, struct regid *reg, char *id, int32_t type)
usr/src/cmd/fs.d/udfs/common/ud_lib.c
1487
reg->reg_flags = 0;
usr/src/cmd/fs.d/udfs/common/ud_lib.c
1488
(void) strncpy(reg->reg_id, id, 23);
usr/src/cmd/fs.d/udfs/common/ud_lib.c
1494
dis = (struct dom_id_suffix *)reg->reg_ids;
usr/src/cmd/fs.d/udfs/common/ud_lib.c
1502
uis = (struct udf_id_suffix *)reg->reg_ids;
usr/src/cmd/fs.d/udfs/common/ud_lib.c
1509
iis = (struct impl_id_suffix *)reg->reg_ids;
usr/src/cmd/fs.d/udfs/common/ud_lib.c
1516
print_regid(FILE *fout, char *name, struct regid *reg, int32_t type)
usr/src/cmd/fs.d/udfs/common/ud_lib.c
1519
name, reg->reg_flags, reg->reg_id);
usr/src/cmd/fs.d/udfs/common/ud_lib.c
1525
dis = (struct dom_id_suffix *)reg->reg_ids;
usr/src/cmd/fs.d/udfs/common/ud_lib.c
1536
uis = (struct udf_id_suffix *)reg->reg_ids;
usr/src/cmd/fs.d/udfs/common/ud_lib.c
1544
iis = (struct impl_id_suffix *)reg->reg_ids;
usr/src/cmd/fs.d/udfs/common/ud_lib.c
1553
print_regid(FILE *fout, char *name, struct regid *reg)
usr/src/cmd/fs.d/udfs/common/ud_lib.c
1556
name, reg->reg_flags, reg->reg_id);
usr/src/cmd/fs.d/udfs/common/ud_lib.c
1558
if (strncmp(reg->reg_id, "*OSTA UDF Compliant", 19) == 0) {
usr/src/cmd/fs.d/udfs/common/ud_lib.c
1560
reg->reg_ids[0] | (reg->reg_ids[1] << 8),
usr/src/cmd/fs.d/udfs/common/ud_lib.c
1561
(reg->reg_ids[2] & 1) ?
usr/src/cmd/fs.d/udfs/common/ud_lib.c
1563
(reg->reg_ids[2] & 2) ?
usr/src/cmd/fs.d/udfs/common/ud_lib.c
1565
} else if ((strncmp(reg->reg_id, "*UDF Virtual Partition", 22) == 0) ||
usr/src/cmd/fs.d/udfs/common/ud_lib.c
1566
(strncmp(reg->reg_id, "*UDF Sparable Partition", 23) == 0) ||
usr/src/cmd/fs.d/udfs/common/ud_lib.c
1567
(strncmp(reg->reg_id, "*UDF Virtual Alloc Tbl", 22) == 0) ||
usr/src/cmd/fs.d/udfs/common/ud_lib.c
1568
(strncmp(reg->reg_id, "*UDF Sparing Table", 18) == 0)) {
usr/src/cmd/fs.d/udfs/common/ud_lib.c
1571
reg->reg_ids[0] | (reg->reg_ids[1] << 8),
usr/src/cmd/fs.d/udfs/common/ud_lib.c
1572
reg->reg_ids[2], reg->reg_ids[3]);
usr/src/cmd/fs.d/udfs/common/ud_lib.c
1576
reg->reg_ids[0], reg->reg_ids[1]);
usr/src/cmd/mandoc/roff.c
3044
struct roffreg *reg;
usr/src/cmd/mandoc/roff.c
3047
reg = r->regtab;
usr/src/cmd/mandoc/roff.c
3049
while (reg != NULL && (reg->key.sz != len ||
usr/src/cmd/mandoc/roff.c
3050
strncmp(reg->key.p, name, len) != 0))
usr/src/cmd/mandoc/roff.c
3051
reg = reg->next;
usr/src/cmd/mandoc/roff.c
3053
if (NULL == reg) {
usr/src/cmd/mandoc/roff.c
3055
reg = mandoc_malloc(sizeof(struct roffreg));
usr/src/cmd/mandoc/roff.c
3056
reg->key.p = mandoc_strndup(name, len);
usr/src/cmd/mandoc/roff.c
3057
reg->key.sz = len;
usr/src/cmd/mandoc/roff.c
3058
reg->val = 0;
usr/src/cmd/mandoc/roff.c
3059
reg->step = 0;
usr/src/cmd/mandoc/roff.c
3060
reg->next = r->regtab;
usr/src/cmd/mandoc/roff.c
3061
r->regtab = reg;
usr/src/cmd/mandoc/roff.c
3065
reg->val += val;
usr/src/cmd/mandoc/roff.c
3067
reg->val -= val;
usr/src/cmd/mandoc/roff.c
3069
reg->val = val;
usr/src/cmd/mandoc/roff.c
3071
reg->step = step;
usr/src/cmd/mandoc/roff.c
3113
struct roffreg *reg;
usr/src/cmd/mandoc/roff.c
3122
for (reg = r->regtab; reg; reg = reg->next) {
usr/src/cmd/mandoc/roff.c
3123
if (len == reg->key.sz &&
usr/src/cmd/mandoc/roff.c
3124
0 == strncmp(name, reg->key.p, len)) {
usr/src/cmd/mandoc/roff.c
3127
reg->val += reg->step;
usr/src/cmd/mandoc/roff.c
3130
reg->val -= reg->step;
usr/src/cmd/mandoc/roff.c
3135
return reg->val;
usr/src/cmd/mandoc/roff.c
3146
struct roffreg *reg;
usr/src/cmd/mandoc/roff.c
3155
for (reg = r->regtab; reg; reg = reg->next)
usr/src/cmd/mandoc/roff.c
3156
if (len == reg->key.sz &&
usr/src/cmd/mandoc/roff.c
3157
0 == strncmp(name, reg->key.p, len))
usr/src/cmd/mandoc/roff.c
3164
roff_freereg(struct roffreg *reg)
usr/src/cmd/mandoc/roff.c
3168
while (NULL != reg) {
usr/src/cmd/mandoc/roff.c
3169
free(reg->key.p);
usr/src/cmd/mandoc/roff.c
3170
old_reg = reg;
usr/src/cmd/mandoc/roff.c
3171
reg = reg->next;
usr/src/cmd/mandoc/roff.c
3213
struct roffreg *reg, **prev;
usr/src/cmd/mandoc/roff.c
3225
reg = *prev;
usr/src/cmd/mandoc/roff.c
3226
if (reg == NULL || !strcmp(name, reg->key.p))
usr/src/cmd/mandoc/roff.c
3228
prev = ®->next;
usr/src/cmd/mandoc/roff.c
3230
if (reg != NULL) {
usr/src/cmd/mandoc/roff.c
3231
*prev = reg->next;
usr/src/cmd/mandoc/roff.c
3232
free(reg->key.p);
usr/src/cmd/mandoc/roff.c
3233
free(reg);
usr/src/cmd/mdb/common/mdb/mdb_help.c
149
regex_t reg;
usr/src/cmd/mdb/common/mdb/mdb_help.c
222
if (regexec(&f->reg, name, 1, &pmatch, 0) == 0 ||
usr/src/cmd/mdb/common/mdb/mdb_help.c
224
regexec(&f->reg, iwp->iwlk_descr, 1, &pmatch, 0) == 0))
usr/src/cmd/mdb/common/mdb/mdb_help.c
265
if ((err = regcomp(&f.reg, f.pattern, REG_EXTENDED)) != 0) {
usr/src/cmd/mdb/common/mdb/mdb_help.c
269
nbytes = regerror(err, &f.reg, NULL, 0);
usr/src/cmd/mdb/common/mdb/mdb_help.c
271
(void) regerror(err, &f.reg, buf, nbytes);
usr/src/cmd/mdb/common/mdb/mdb_help.c
311
if (regexec(&f->reg, name, 1, &pmatch, 0) == 0 ||
usr/src/cmd/mdb/common/mdb/mdb_help.c
313
regexec(&f->reg, idcp->idc_descr, 1, &pmatch, 0) == 0))
usr/src/cmd/mdb/common/mdb/mdb_help.c
354
if ((err = regcomp(&f.reg, f.pattern, REG_EXTENDED)) != 0) {
usr/src/cmd/mdb/common/mdb/mdb_help.c
358
nbytes = regerror(err, &f.reg, NULL, 0);
usr/src/cmd/mdb/common/mdb/mdb_help.c
360
(void) regerror(err, &f.reg, buf, nbytes);
usr/src/cmd/mdb/common/modules/libc/findstack_subr.c
221
mdb_reg_t reg;
usr/src/cmd/mdb/common/modules/libc/findstack_subr.c
265
if (mdb_getareg(addr, STACKS_REGS_FP, ®) != 0) {
usr/src/cmd/mdb/common/modules/libc/findstack_subr.c
270
fsip->fsi_sp = fp = (uintptr_t)reg;
usr/src/cmd/mdb/common/modules/libc/findstack_subr.c
273
if (mdb_getareg(addr, STACKS_REGS_RC, ®) != 0) {
usr/src/cmd/mdb/common/modules/libc/findstack_subr.c
278
fsip->fsi_pc = (uintptr_t)reg;
usr/src/cmd/mdb/i86pc/modules/common/apic_common.c
39
apic_ioapic_read(int ioapic_ix, uint32_t reg)
usr/src/cmd/mdb/i86pc/modules/common/apic_common.c
44
ioapic[APIC_IO_REG] = reg;
usr/src/cmd/mdb/i86pc/modules/common/apic_common.c
56
int reg;
usr/src/cmd/mdb/i86pc/modules/common/apic_common.c
90
for (reg = 0; reg <= reg_max; reg++) {
usr/src/cmd/mdb/i86pc/modules/common/apic_common.c
93
high = APIC_READ_IOAPIC_RDT_ENTRY_HIGH_DWORD(i, reg);
usr/src/cmd/mdb/i86pc/modules/common/apic_common.c
94
low = APIC_READ_IOAPIC_RDT_ENTRY_LOW_DWORD(i, reg);
usr/src/cmd/mdb/i86pc/modules/common/apic_common.c
96
mdb_printf("%2d %8x %8x\n", reg, high, low);
usr/src/cmd/mdb/i86pc/modules/unix/unix.c
420
#define DUMP(reg) #reg, regs->r_##reg
usr/src/cmd/mdb/i86pc/modules/unix/unix.c
445
#define DUMP(reg) #reg, regs->r_##reg
usr/src/cmd/mdb/intel/mdb/mdb_bhyve.c
1412
int reg = bhyve_lookup_reg(tgt, rname);
usr/src/cmd/mdb/intel/mdb/mdb_bhyve.c
1415
if (reg == -1)
usr/src/cmd/mdb/intel/mdb/mdb_bhyve.c
1418
ret = vmm_getreg(bd->bd_vmm, bd->bd_curcpu, reg, rp);
usr/src/cmd/mdb/intel/mdb/mdb_bhyve.c
1433
int reg = bhyve_lookup_reg(tgt, rname);
usr/src/cmd/mdb/intel/mdb/mdb_bhyve.c
1439
if (reg == -1)
usr/src/cmd/mdb/intel/mdb/mdb_bhyve.c
1442
ret = vmm_setreg(bd->bd_vmm, bd->bd_curcpu, reg, r);
usr/src/cmd/mdb/intel/mdb/proc_amd64dep.c
300
struct _fpreg reg;
usr/src/cmd/mdb/intel/mdb/proc_amd64dep.c
353
exp = fpru.reg.exponent & 0x7fff;
usr/src/cmd/mdb/intel/mdb/proc_amd64dep.c
358
if (fpru.reg.significand[0] == 0 &&
usr/src/cmd/mdb/intel/mdb/proc_amd64dep.c
359
fpru.reg.significand[1] == 0 &&
usr/src/cmd/mdb/intel/mdb/proc_amd64dep.c
360
fpru.reg.significand[2] == 0 &&
usr/src/cmd/mdb/intel/mdb/proc_amd64dep.c
361
fpru.reg.significand[3] == 0)
usr/src/cmd/mdb/intel/mdb/proc_amd64dep.c
367
} else if (fpru.reg.significand[3] & 0x8000) {
usr/src/cmd/mdb/intel/mdb/proc_amd64dep.c
374
i, fpru.reg.exponent,
usr/src/cmd/mdb/intel/mdb/proc_amd64dep.c
375
fpru.reg.significand[3], fpru.reg.significand[2],
usr/src/cmd/mdb/intel/mdb/proc_amd64dep.c
376
fpru.reg.significand[1], fpru.reg.significand[0],
usr/src/cmd/mdb/intel/mdb/proc_ia32dep.c
241
struct _fpreg reg;
usr/src/cmd/mdb/intel/mdb/proc_ia32dep.c
289
fpru.reg = fps._st[i];
usr/src/cmd/mdb/intel/mdb/proc_ia32dep.c
291
i, fpru.reg.exponent,
usr/src/cmd/mdb/intel/mdb/proc_ia32dep.c
292
fpru.reg.significand[3], fpru.reg.significand[2],
usr/src/cmd/mdb/intel/mdb/proc_ia32dep.c
293
fpru.reg.significand[1], fpru.reg.significand[0],
usr/src/cmd/pcieadm/pcieadm_bar.c
302
int *reg;
usr/src/cmd/pcieadm/pcieadm_bar.c
304
"reg", ®);
usr/src/cmd/pcieadm/pcieadm_bar.c
419
const pci_regspec_t *rsp = (pci_regspec_t *)reg;
usr/src/cmd/pcieadm/pcieadm_bar.c
489
pcieadm_bar_parse_u64(const char *reg, const char *desc)
usr/src/cmd/pcieadm/pcieadm_bar.c
495
ull = strtoull(reg, &eptr, 0);
usr/src/cmd/pcieadm/pcieadm_bar.c
497
errx(EXIT_FAILURE, "failed to parse %s %s", desc, reg);
usr/src/cmd/pcieadm/pcieadm_bar.c
592
uint64_t reg = pcieadm_bar_parse_u64(argv[0], "register");
usr/src/cmd/pcieadm/pcieadm_bar.c
606
if (!ops->pop_bar(bar, len, reg, buf, karg, B_FALSE)) {
usr/src/cmd/pcieadm/pcieadm_bar.c
608
" from BAR %u", len, reg, bar);
usr/src/cmd/pcieadm/pcieadm_bar.c
734
uint64_t reg = pcieadm_bar_parse_u64(argv[0], "register");
usr/src/cmd/pcieadm/pcieadm_bar.c
781
if (!ops->pop_bar(bar, len, reg, buf, karg, B_TRUE)) {
usr/src/cmd/pcieadm/pcieadm_bar.c
783
" from BAR %u", len, reg, bar);
usr/src/cmd/pcieadm/pcieadm_cfgspace.c
4917
uint64_t reg)
usr/src/cmd/pcieadm/pcieadm_cfgspace.c
4919
uint64_t scale = bitx64(reg, 11, 9);
usr/src/cmd/pcieadm/pcieadm_cfgspace.c
4920
uint64_t time = bitx64(reg, 8, 0);
usr/src/cmd/pcieadm/pcieadm_cfgspace.c
4923
pcieadm_regdef_printf(walkp, print, regdef, reg, "%" PRIu64 " ns\n",
usr/src/cmd/picl/plugins/common/devtree/picldevtree.c
3221
reg:8; /* register number */
usr/src/cmd/picl/plugins/common/devtree/picldevtree.c
3241
len = snprintf(buf, sz, "i%x,%x,%x,%x", p->dev, p->fn, p->reg,
usr/src/cmd/picl/plugins/common/devtree/picldevtree.c
3245
len = snprintf(buf, sz, "m%x,%x,%x,%x", p->dev, p->fn, p->reg,
usr/src/cmd/picl/plugins/common/devtree/picldevtree.c
3250
p->reg, p->phys_hi, p->phys_lo);
usr/src/cmd/picl/plugins/sun4u/psvc/psvcobj/psvcobj.c
2367
i2c_reg_t reg;
usr/src/cmd/picl/plugins/sun4u/psvc/psvcobj/psvcobj.c
2383
reg.reg_num = 0;
usr/src/cmd/picl/plugins/sun4u/psvc/psvcobj/psvcobj.c
2384
ret = ioctl_retry(fp, I2C_GET_REG, (void *)®);
usr/src/cmd/picl/plugins/sun4u/psvc/psvcobj/psvcobj.c
2659
i2c_reg_t reg;
usr/src/cmd/picl/plugins/sun4u/psvc/psvcobj/psvcobj.c
2682
reg.reg_num = 0x10;
usr/src/cmd/picl/plugins/sun4u/psvc/psvcobj/psvcobj.c
2683
ret = ioctl_retry(fp, I2C_GET_REG, (void *)®);
usr/src/cmd/prtconf/prt_xxx.c
184
struct regspec *reg;
usr/src/cmd/prtconf/prt_xxx.c
208
reg = (struct regspec *)(data + *(di_off_t *)(&dp->par_reg));
usr/src/cmd/prtconf/prt_xxx.c
210
obio_printregs(reg + i, ilev);
usr/src/cmd/prtconf/prt_xxx.c
251
struct pcm_regs *reg;
usr/src/cmd/prtconf/prt_xxx.c
272
reg = (struct pcm_regs *)(data + *(di_off_t *)(&dp->ppd_reg));
usr/src/cmd/prtconf/prt_xxx.c
274
pcmcia_printregs(reg + i, ilev);
usr/src/cmd/prtconf/prt_xxx.c
293
struct regspec *reg;
usr/src/cmd/prtconf/prt_xxx.c
317
reg = (struct regspec *)(data + *(di_off_t *)(&dp->par_reg));
usr/src/cmd/prtconf/prt_xxx.c
319
obio_printregs(reg + i, ilev);
usr/src/cmd/ptools/pflags/pflags.c
541
dumpregs32(const prgregset_t reg)
usr/src/cmd/ptools/pflags/pflags.c
546
prgregset_n_to_32(reg, reg32);
usr/src/cmd/ptools/pflags/pflags.c
560
dumpregs(const prgregset_t reg, int is64)
usr/src/cmd/ptools/pflags/pflags.c
568
dumpregs32(reg);
usr/src/cmd/ptools/pflags/pflags.c
575
regname[i], width, (long)reg[i]);
usr/src/cmd/ptools/pstack/pstack.c
679
print_syscall(const lwpstatus_t *psp, prgregset_t reg)
usr/src/cmd/ptools/pstack/pstack.c
686
(void) printf(" %.*lx %-8s (", length, (long)reg[R_PC], sname);
usr/src/cmd/ptools/pstack/pstack.c
696
prgregset_t reg;
usr/src/cmd/ptools/pstack/pstack.c
698
(void) memcpy(reg, psp->pr_reg, sizeof (reg));
usr/src/cmd/ptools/pstack/pstack.c
704
print_syscall(psp, reg);
usr/src/cmd/ptools/pstack/pstack.c
710
(void) Pstack_iter(h->proc, reg, print_frame, h);
usr/src/cmd/rcm_daemon/common/ip_anon_rcm.c
104
static ip_status_t *findreg(char *reg);
usr/src/cmd/rcm_daemon/common/ip_anon_rcm.c
105
static ip_status_t *addreg(char *reg);
usr/src/cmd/rcm_daemon/common/ip_anon_rcm.c
542
findreg(char *reg)
usr/src/cmd/rcm_daemon/common/ip_anon_rcm.c
550
if (strcmp(tlist->device, reg) == 0)
usr/src/cmd/rcm_daemon/common/ip_anon_rcm.c
560
addreg(char *reg)
usr/src/cmd/rcm_daemon/common/ip_anon_rcm.c
570
(void) strcpy(tentry->device, reg);
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
161
phci_list_t *reg;
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
170
reg = reg_list;
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
171
while (reg) {
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
172
next = reg->next;
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
173
free(reg->phci.path);
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
174
free(reg);
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
175
reg = next;
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
243
phci_list_t *reg;
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
249
for (reg = reg_list; reg != NULL; reg = reg->next) {
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
250
(void) rcm_unregister_interest(hdl, reg->phci.path, 0);
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
251
reg->referenced = CACHE_STALE;
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
272
phci_list_t *reg;
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
282
if ((reg = lookup_phci(rsrc)) == NULL) {
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
288
len = snprintf(&c, 1, MPXIO_MSG_USAGE, s_state(reg->phci.state));
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
291
s_state(reg->phci.state)) > len + 1)) {
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
512
phci_list_t *reg;
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
514
for (reg = reg_list; reg != NULL; reg = reg->next) {
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
515
if (strcmp(reg->phci.path, rsrc) == 0)
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
516
return (reg);
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
654
phci_list_t *reg;
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
660
for (reg = reg_list; reg != NULL; reg = reg->next)
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
661
reg->referenced = CACHE_STALE;
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
675
if ((reg = lookup_phci(group->phcis[i].path)) != NULL) {
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
676
if (reg->referenced == CACHE_STALE)
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
677
reg->referenced = CACHE_REFERENCED;
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
678
reg->phci.state = group->phcis[i].state;
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
685
reg = (phci_list_t *)calloc(1, sizeof (*reg));
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
686
if (reg == NULL) {
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
692
reg->phci.path = strdup(group->phcis[i].path);
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
693
if (reg->phci.path == NULL) {
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
694
free(reg);
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
700
reg->phci.state = group->phcis[i].state;
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
701
reg->referenced = CACHE_NEW;
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
704
reg->next = reg_list;
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
705
reg_list = reg;
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
713
reg = reg_list;
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
715
while (reg) {
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
718
if (reg->referenced == CACHE_STALE) {
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
719
(void) rcm_unregister_interest(hdl, reg->phci.path, 0);
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
720
free(reg->phci.path);
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
722
reg_list = reg->next;
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
723
free(reg);
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
724
reg = reg_list;
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
726
prev_reg->next = reg->next;
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
727
free(reg);
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
728
reg = prev_reg->next;
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
734
if (reg->referenced == CACHE_NEW) {
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
735
if (rcm_register_interest(hdl, reg->phci.path, 0, NULL)
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
739
reg->phci.path, strerror(errno));
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
743
prev_reg = reg;
usr/src/cmd/rcm_daemon/common/mpxio_rcm.c
744
reg = reg->next;
usr/src/cmd/rpcbind/pmap_svc.c
168
PMAP reg;
usr/src/cmd/rpcbind/pmap_svc.c
174
if (!svc_getargs(xprt, (xdrproc_t)xdr_pmap, (char *)®)) {
usr/src/cmd/rpcbind/pmap_svc.c
188
if ((op == PMAPPROC_SET) && (reg.pm_port < IPPORT_RESERVED) &&
usr/src/cmd/rpcbind/pmap_svc.c
193
rpcbreg.r_prog = reg.pm_prog;
usr/src/cmd/rpcbind/pmap_svc.c
194
rpcbreg.r_vers = reg.pm_vers;
usr/src/cmd/rpcbind/pmap_svc.c
199
sprintf(buf, "0.0.0.0.%d.%d", (reg.pm_port >> 8) & 0xff,
usr/src/cmd/rpcbind/pmap_svc.c
200
reg.pm_port & 0xff);
usr/src/cmd/rpcbind/pmap_svc.c
202
if (reg.pm_prot == IPPROTO_UDP) {
usr/src/cmd/rpcbind/pmap_svc.c
204
} else if (reg.pm_prot == IPPROTO_TCP) {
usr/src/cmd/rpcbind/pmap_svc.c
224
PMAP_LOG(ans, xprt, op, reg.pm_prog);
usr/src/cmd/rpcbind/pmap_svc.c
244
PMAP reg;
usr/src/cmd/rpcbind/pmap_svc.c
249
if (!svc_getargs(xprt, (xdrproc_t)xdr_pmap, (char *)®)) {
usr/src/cmd/rpcbind/pmap_svc.c
257
fnd = find_service_pmap(reg.pm_prog, reg.pm_vers, reg.pm_prot);
usr/src/cmd/rpcbind/pmap_svc.c
263
if (reg.pm_prot == IPPROTO_UDP) {
usr/src/cmd/rpcbind/pmap_svc.c
292
delete_prog(reg.pm_prog);
usr/src/cmd/rpcbind/pmap_svc.c
308
rpcbs_getaddr(RPCBVERS_2_STAT, reg.pm_prog, reg.pm_vers,
usr/src/cmd/rpcbind/pmap_svc.c
309
reg.pm_prot == IPPROTO_UDP ? udptrans : tcptrans,
usr/src/cmd/sgs/libld/common/machrel.amd.c
670
uint8_t reg; /* Register */
usr/src/cmd/sgs/libld/common/machrel.amd.c
674
reg = offset[2] >> 3; /* Encoded dest. reg. operand */
usr/src/cmd/sgs/libld/common/machrel.amd.c
687
((offset[1] == INSN_ADDMR) && (reg == REG_ESP))) {
usr/src/cmd/sgs/libld/common/machrel.amd.c
699
offset[2] = 0xc0 | reg;
usr/src/cmd/sgs/libld/common/machrel.amd.c
713
offset[2] = 0x80 | (reg << 3) | reg;
usr/src/cmd/truss/fcall.c
1551
trap_one_stack(prgregset_t reg)
usr/src/cmd/truss/fcall.c
1558
uintptr_t sp = reg[R_SP];
usr/src/cmd/truss/fcall.c
1559
uintptr_t pc = reg[R_PC];
usr/src/cmd/truss/fcall.c
1627
prgregset_t reg;
usr/src/cmd/truss/fcall.c
1629
(void) memcpy(reg, Lsp->pr_reg, sizeof (prgregset_t));
usr/src/cmd/truss/fcall.c
1631
trap_one_stack(reg);
usr/src/cmd/truss/fcall.c
1640
prgregset_t reg;
usr/src/cmd/truss/fcall.c
1646
if (td_thr_getgregs(Thp, reg) != TD_PARTIALREG)
usr/src/cmd/truss/fcall.c
1649
make_thr_stack(Thp, reg);
usr/src/cmd/truss/fcall.c
1650
trap_one_stack(reg);
usr/src/cmd/truss/fcall.c
706
make_thr_stack(const td_thrhandle_t *Thp, prgregset_t reg)
usr/src/cmd/truss/fcall.c
710
uintptr_t sp = reg[R_SP];
usr/src/cmd/vgrind/retest.c
20
char reg[132];
usr/src/cmd/vgrind/retest.c
29
scanf ("%s", reg);
usr/src/cmd/vgrind/retest.c
30
ireg = convexp(reg);
usr/src/common/bitext/bitext.c
110
reg &= ~(mask << low);
usr/src/common/bitext/bitext.c
111
reg |= val << low;
usr/src/common/bitext/bitext.c
113
return (reg);
usr/src/common/bitext/bitext.c
117
bitset32(uint32_t reg, uint_t high, uint_t low, uint32_t val)
usr/src/common/bitext/bitext.c
128
reg &= ~(mask << low);
usr/src/common/bitext/bitext.c
129
reg |= val << low;
usr/src/common/bitext/bitext.c
131
return (reg);
usr/src/common/bitext/bitext.c
135
bitset64(uint64_t reg, uint_t high, uint_t low, uint64_t val)
usr/src/common/bitext/bitext.c
146
reg &= ~(mask << low);
usr/src/common/bitext/bitext.c
147
reg |= val << low;
usr/src/common/bitext/bitext.c
149
return (reg);
usr/src/common/bitext/bitext.c
27
bitx8(uint8_t reg, uint_t high, uint_t low)
usr/src/common/bitext/bitext.c
36
return ((reg >> low) & mask);
usr/src/common/bitext/bitext.c
40
bitx16(uint16_t reg, uint_t high, uint_t low)
usr/src/common/bitext/bitext.c
49
return ((reg >> low) & mask);
usr/src/common/bitext/bitext.c
54
bitx32(uint32_t reg, uint_t high, uint_t low)
usr/src/common/bitext/bitext.c
64
return ((reg >> low) & mask);
usr/src/common/bitext/bitext.c
68
bitx64(uint64_t reg, uint_t high, uint_t low)
usr/src/common/bitext/bitext.c
77
return ((reg >> low) & mask);
usr/src/common/bitext/bitext.c
81
bitset8(uint8_t reg, uint_t high, uint_t low, uint8_t val)
usr/src/common/bitext/bitext.c
92
reg &= ~(mask << low);
usr/src/common/bitext/bitext.c
93
reg |= val << low;
usr/src/common/bitext/bitext.c
95
return (reg);
usr/src/common/bitext/bitext.c
99
bitset16(uint16_t reg, uint_t high, uint_t low, uint16_t val)
usr/src/common/dis/i386/dis_tables.c
3230
dtrace_get_modrm(dis86_t *x, uint_t *mode, uint_t *reg, uint_t *r_m)
usr/src/common/dis/i386/dis_tables.c
3235
dtrace_get_SIB(x, mode, reg, r_m);
usr/src/common/dis/i386/dis_tables.c
3245
dtrace_rex_adjust(uint_t rex_prefix, uint_t mode, uint_t *reg, uint_t *r_m)
usr/src/common/dis/i386/dis_tables.c
3247
if (reg != NULL && r_m == NULL) {
usr/src/common/dis/i386/dis_tables.c
3249
*reg += 8;
usr/src/common/dis/i386/dis_tables.c
3251
if (reg != NULL && (REX_R & rex_prefix) != 0)
usr/src/common/dis/i386/dis_tables.c
3252
*reg += 8;
usr/src/common/dis/i386/dis_tables.c
3264
dtrace_vex_adjust(uint_t vex_byte1, uint_t mode, uint_t *reg, uint_t *r_m)
usr/src/common/dis/i386/dis_tables.c
3266
if (reg != NULL && r_m == NULL) {
usr/src/common/dis/i386/dis_tables.c
3268
*reg += 8;
usr/src/common/dis/i386/dis_tables.c
3270
if (reg != NULL && ((VEX_R & vex_byte1) == 0))
usr/src/common/dis/i386/dis_tables.c
3271
*reg += 8;
usr/src/common/dis/i386/dis_tables.c
3332
dtrace_evex_adjust_reg(uint_t evex_byte1, uint_t *reg)
usr/src/common/dis/i386/dis_tables.c
3334
if (reg != NULL) {
usr/src/common/dis/i386/dis_tables.c
3336
*reg += 8;
usr/src/common/dis/i386/dis_tables.c
3339
*reg += 16;
usr/src/common/dis/i386/dis_tables.c
4003
#define STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, vbit) { \
usr/src/common/dis/i386/dis_tables.c
4004
dtrace_get_modrm(x, &mode, ®, &r_m); \
usr/src/common/dis/i386/dis_tables.c
4005
dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
usr/src/common/dis/i386/dis_tables.c
4007
dtrace_get_operand(x, REG_ONLY, reg, wbit, 1 - vbit); \
usr/src/common/dis/i386/dis_tables.c
4016
#define MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, w2, vbit) { \
usr/src/common/dis/i386/dis_tables.c
4017
dtrace_get_modrm(x, &mode, ®, &r_m); \
usr/src/common/dis/i386/dis_tables.c
4018
dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
usr/src/common/dis/i386/dis_tables.c
4020
dtrace_get_operand(x, REG_ONLY, reg, w2, 1 - vbit); \
usr/src/common/dis/i386/dis_tables.c
4029
#define THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize, vbit) { \
usr/src/common/dis/i386/dis_tables.c
4030
dtrace_get_modrm(x, &mode, ®, &r_m); \
usr/src/common/dis/i386/dis_tables.c
4031
dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
usr/src/common/dis/i386/dis_tables.c
4033
dtrace_get_operand(x, REG_ONLY, reg, w2, 1+vbit); \
usr/src/common/dis/i386/dis_tables.c
4040
#define FOUROPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize) { \
usr/src/common/dis/i386/dis_tables.c
4041
dtrace_get_modrm(x, &mode, ®, &r_m); \
usr/src/common/dis/i386/dis_tables.c
4042
dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
usr/src/common/dis/i386/dis_tables.c
4044
dtrace_get_operand(x, REG_ONLY, reg, w2, 3); \
usr/src/common/dis/i386/dis_tables.c
4052
#define ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, wbit, immsize) { \
usr/src/common/dis/i386/dis_tables.c
4053
dtrace_get_modrm(x, &mode, ®, &r_m); \
usr/src/common/dis/i386/dis_tables.c
4054
dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
usr/src/common/dis/i386/dis_tables.c
4087
uint_t reg; /* reg value from ModRM byte */
usr/src/common/dis/i386/dis_tables.c
4265
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
4272
opcode3 = (((mode << 3) | reg)>>1) & 0x0F;
usr/src/common/dis/i386/dis_tables.c
4273
opcode4 = ((reg << 3) | r_m) & 0x0F;
usr/src/common/dis/i386/dis_tables.c
4302
reg = (b >> 3) & 0x7;
usr/src/common/dis/i386/dis_tables.c
4798
reg = opcode3;
usr/src/common/dis/i386/dis_tables.c
4934
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
4949
dp = (instable_t *)&dis_op0FC7m3[reg];
usr/src/common/dis/i386/dis_tables.c
4958
} else if (reg == 4 || reg == 5) {
usr/src/common/dis/i386/dis_tables.c
4962
dp = (instable_t *)&dis_op0FC7[reg];
usr/src/common/dis/i386/dis_tables.c
5147
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
5148
dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
5150
dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
usr/src/common/dis/i386/dis_tables.c
5167
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
5168
dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
5169
dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
usr/src/common/dis/i386/dis_tables.c
5180
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
5181
dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
5182
dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
usr/src/common/dis/i386/dis_tables.c
5194
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
5195
dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
5201
dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);
usr/src/common/dis/i386/dis_tables.c
5205
dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
usr/src/common/dis/i386/dis_tables.c
5216
THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND,
usr/src/common/dis/i386/dis_tables.c
5224
STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
usr/src/common/dis/i386/dis_tables.c
5234
STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
usr/src/common/dis/i386/dis_tables.c
5240
STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
usr/src/common/dis/i386/dis_tables.c
5251
MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1);
usr/src/common/dis/i386/dis_tables.c
5256
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
5260
MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1);
usr/src/common/dis/i386/dis_tables.c
5266
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
5267
dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
5269
dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
usr/src/common/dis/i386/dis_tables.c
5278
STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
usr/src/common/dis/i386/dis_tables.c
5296
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
5307
reg = REGNO(opcode2);
usr/src/common/dis/i386/dis_tables.c
5308
dtrace_rex_adjust(rex_prefix, mode, ®, NULL);
usr/src/common/dis/i386/dis_tables.c
5310
r_m = reg;
usr/src/common/dis/i386/dis_tables.c
5325
reg = REGNO(opcode7);
usr/src/common/dis/i386/dis_tables.c
5326
dtrace_rex_adjust(rex_prefix, mode, ®, NULL);
usr/src/common/dis/i386/dis_tables.c
5327
dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
usr/src/common/dis/i386/dis_tables.c
5355
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
5358
dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 1 - vbit);
usr/src/common/dis/i386/dis_tables.c
5400
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
5580
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
5613
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
5614
dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
5615
dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit);
usr/src/common/dis/i386/dis_tables.c
5626
reg = REGNO(opcode5);
usr/src/common/dis/i386/dis_tables.c
5628
reg = REGNO(opcode2);
usr/src/common/dis/i386/dis_tables.c
5629
dtrace_rex_adjust(rex_prefix, mode, ®, NULL);
usr/src/common/dis/i386/dis_tables.c
5630
dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);
usr/src/common/dis/i386/dis_tables.c
5640
reg = REGNO(opcode2);
usr/src/common/dis/i386/dis_tables.c
5641
dtrace_rex_adjust(rex_prefix, mode, ®, NULL);
usr/src/common/dis/i386/dis_tables.c
5642
dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);
usr/src/common/dis/i386/dis_tables.c
5648
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
5659
reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x3;
usr/src/common/dis/i386/dis_tables.c
5660
dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0);
usr/src/common/dis/i386/dis_tables.c
5670
reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x7;
usr/src/common/dis/i386/dis_tables.c
5671
dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0);
usr/src/common/dis/i386/dis_tables.c
5679
STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
usr/src/common/dis/i386/dis_tables.c
5687
STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
usr/src/common/dis/i386/dis_tables.c
5698
MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0);
usr/src/common/dis/i386/dis_tables.c
5707
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
5711
dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
5713
dtrace_get_operand(x, REG_ONLY, reg, MM_OPND, 1);
usr/src/common/dis/i386/dis_tables.c
5724
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
5728
THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 1,
usr/src/common/dis/i386/dis_tables.c
5734
THREEOPERAND(x, mode, reg, r_m, rex_prefix, LONG_OPND, XMM_OPND,
usr/src/common/dis/i386/dis_tables.c
5748
THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, 1, 1);
usr/src/common/dis/i386/dis_tables.c
5760
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
5764
MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0);
usr/src/common/dis/i386/dis_tables.c
5774
STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
usr/src/common/dis/i386/dis_tables.c
5801
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
5810
MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1);
usr/src/common/dis/i386/dis_tables.c
5818
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
5827
MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);
usr/src/common/dis/i386/dis_tables.c
5833
MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);
usr/src/common/dis/i386/dis_tables.c
5838
MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1);
usr/src/common/dis/i386/dis_tables.c
5846
MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);
usr/src/common/dis/i386/dis_tables.c
5854
MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0);
usr/src/common/dis/i386/dis_tables.c
5861
MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0);
usr/src/common/dis/i386/dis_tables.c
5867
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
5870
dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
5872
dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
usr/src/common/dis/i386/dis_tables.c
5882
THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1,
usr/src/common/dis/i386/dis_tables.c
5953
FOUROPERAND(x, mode, reg, r_m, rex_prefix, XMM_OPND, XMM_OPND,
usr/src/common/dis/i386/dis_tables.c
5959
ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, XMM_OPND, 1);
usr/src/common/dis/i386/dis_tables.c
6202
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6220
dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6237
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6261
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6275
if (reg == 5) {
usr/src/common/dis/i386/dis_tables.c
6277
} else if (reg == 6) {
usr/src/common/dis/i386/dis_tables.c
6291
dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6324
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6326
if ((dp == &dis_opAVX0F[0xA][0xE]) && (reg == 3))
usr/src/common/dis/i386/dis_tables.c
6329
dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6336
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6337
dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6368
dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
usr/src/common/dis/i386/dis_tables.c
6399
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6400
dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6402
dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
usr/src/common/dis/i386/dis_tables.c
6430
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6431
dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6433
dtrace_get_operand(x, REG_ONLY, reg, vreg->dgr_arg2, 2);
usr/src/common/dis/i386/dis_tables.c
6447
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6448
dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6462
dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
usr/src/common/dis/i386/dis_tables.c
6469
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6470
dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6471
dtrace_get_operand(x, REG_ONLY, reg, wbit, 3);
usr/src/common/dis/i386/dis_tables.c
6518
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6519
dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6528
dtrace_get_operand(x, REG_ONLY, reg, XMM_OPND, 1);
usr/src/common/dis/i386/dis_tables.c
6543
dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
usr/src/common/dis/i386/dis_tables.c
6551
dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
usr/src/common/dis/i386/dis_tables.c
6554
dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
usr/src/common/dis/i386/dis_tables.c
6564
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6565
dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6567
dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
usr/src/common/dis/i386/dis_tables.c
6578
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6580
(void) strncpy(x->d86_mnem, dis_AVXvgrp7[opcode2 - 1][reg],
usr/src/common/dis/i386/dis_tables.c
6583
dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6603
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6604
dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6605
dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, vbit);
usr/src/common/dis/i386/dis_tables.c
6616
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6617
dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6619
dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
usr/src/common/dis/i386/dis_tables.c
6625
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6626
dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6627
dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
usr/src/common/dis/i386/dis_tables.c
6638
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6639
dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6640
dtrace_get_operand(x, mode, reg, wbit, 1);
usr/src/common/dis/i386/dis_tables.c
6648
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6649
dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6650
dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
usr/src/common/dis/i386/dis_tables.c
6661
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6662
dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6665
dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
usr/src/common/dis/i386/dis_tables.c
6674
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6675
dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6677
dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
usr/src/common/dis/i386/dis_tables.c
6684
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6685
dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6697
dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
usr/src/common/dis/i386/dis_tables.c
6704
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6705
dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6715
dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
usr/src/common/dis/i386/dis_tables.c
6724
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6725
dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6728
dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
usr/src/common/dis/i386/dis_tables.c
6738
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6739
dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6742
dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
usr/src/common/dis/i386/dis_tables.c
6749
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6750
dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6754
dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit - 1);
usr/src/common/dis/i386/dis_tables.c
6762
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6763
dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6767
dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
usr/src/common/dis/i386/dis_tables.c
6774
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6775
dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6776
dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
usr/src/common/dis/i386/dis_tables.c
6798
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6799
dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6801
switch (reg) {
usr/src/common/dis/i386/dis_tables.c
6833
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6835
dtrace_evex_adjust_reg(evex_byte1, ®);
usr/src/common/dis/i386/dis_tables.c
6838
dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
usr/src/common/dis/i386/dis_tables.c
6848
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6850
dtrace_evex_adjust_reg(evex_byte1, ®);
usr/src/common/dis/i386/dis_tables.c
6853
dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
usr/src/common/dis/i386/dis_tables.c
6863
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6865
dtrace_evex_adjust_reg(evex_byte1, ®);
usr/src/common/dis/i386/dis_tables.c
6868
dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
usr/src/common/dis/i386/dis_tables.c
6879
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6881
dtrace_evex_adjust_reg(evex_byte1, ®);
usr/src/common/dis/i386/dis_tables.c
6888
dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
usr/src/common/dis/i386/dis_tables.c
6894
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6896
dtrace_evex_adjust_reg(evex_byte1, ®);
usr/src/common/dis/i386/dis_tables.c
6903
dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
usr/src/common/dis/i386/dis_tables.c
6909
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6911
dtrace_evex_adjust_reg(evex_byte1, ®);
usr/src/common/dis/i386/dis_tables.c
6914
dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
usr/src/common/dis/i386/dis_tables.c
6930
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6932
dtrace_evex_adjust_reg(evex_byte1, ®);
usr/src/common/dis/i386/dis_tables.c
6935
dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
usr/src/common/dis/i386/dis_tables.c
6952
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6954
dtrace_evex_adjust_reg(evex_byte1, ®);
usr/src/common/dis/i386/dis_tables.c
6957
dtrace_get_operand(x, REG_ONLY, reg, KOPMASK_OPND, 2);
usr/src/common/dis/i386/dis_tables.c
6974
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6976
dtrace_evex_adjust_reg(evex_byte1, ®);
usr/src/common/dis/i386/dis_tables.c
6979
dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
usr/src/common/dis/i386/dis_tables.c
6987
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
6989
dtrace_evex_adjust_reg(evex_byte1, ®);
usr/src/common/dis/i386/dis_tables.c
6992
dtrace_get_operand(x, REG_ONLY, reg, wbit, 3);
usr/src/common/dis/i386/dis_tables.c
7011
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
7013
dtrace_evex_adjust_reg(evex_byte1, ®);
usr/src/common/dis/i386/dis_tables.c
7016
dtrace_get_operand(x, REG_ONLY, reg, wbit, 3);
usr/src/common/dis/i386/dis_tables.c
7043
dtrace_get_modrm(x, &mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
7044
dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
usr/src/common/dis/i386/dis_tables.c
7045
dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
usr/src/common/vga/vgasubr.c
100
vga_get_reg(vgaregmap_t reg, int indexreg)
usr/src/common/vga/vgasubr.c
102
return (GETB(reg, indexreg));
usr/src/common/vga/vgasubr.c
106
vga_set_reg(vgaregmap_t reg, int indexreg, int v)
usr/src/common/vga/vgasubr.c
108
PUTB(reg, indexreg, v);
usr/src/common/vga/vgasubr.c
112
vga_get_crtc(vgaregmap_t reg, int i)
usr/src/common/vga/vgasubr.c
114
return (vga_get_indexed(reg, VGA_CRTC_ADR, VGA_CRTC_DATA, i));
usr/src/common/vga/vgasubr.c
118
vga_set_crtc(vgaregmap_t reg, int i, int v)
usr/src/common/vga/vgasubr.c
120
vga_set_indexed(reg, VGA_CRTC_ADR, VGA_CRTC_DATA, i, v);
usr/src/common/vga/vgasubr.c
124
vga_get_seq(vgaregmap_t reg, int i)
usr/src/common/vga/vgasubr.c
126
return (vga_get_indexed(reg, VGA_SEQ_ADR, VGA_SEQ_DATA, i));
usr/src/common/vga/vgasubr.c
130
vga_set_seq(vgaregmap_t reg, int i, int v)
usr/src/common/vga/vgasubr.c
132
vga_set_indexed(reg, VGA_SEQ_ADR, VGA_SEQ_DATA, i, v);
usr/src/common/vga/vgasubr.c
136
vga_get_grc(vgaregmap_t reg, int i)
usr/src/common/vga/vgasubr.c
138
return (vga_get_indexed(reg, VGA_GRC_ADR, VGA_GRC_DATA, i));
usr/src/common/vga/vgasubr.c
142
vga_set_grc(vgaregmap_t reg, int i, int v)
usr/src/common/vga/vgasubr.c
144
vga_set_indexed(reg, VGA_GRC_ADR, VGA_GRC_DATA, i, v);
usr/src/common/vga/vgasubr.c
148
vga_get_atr(vgaregmap_t reg, int i)
usr/src/common/vga/vgasubr.c
152
(void) GETB(reg, CGA_STAT);
usr/src/common/vga/vgasubr.c
153
PUTB(reg, VGA_ATR_AD, i);
usr/src/common/vga/vgasubr.c
154
ret = GETB(reg, VGA_ATR_DATA);
usr/src/common/vga/vgasubr.c
156
(void) GETB(reg, CGA_STAT);
usr/src/common/vga/vgasubr.c
157
PUTB(reg, VGA_ATR_AD, VGA_ATR_ENB_PLT);
usr/src/common/vga/vgasubr.c
163
vga_set_atr(vgaregmap_t reg, int i, int v)
usr/src/common/vga/vgasubr.c
165
(void) GETB(reg, CGA_STAT);
usr/src/common/vga/vgasubr.c
166
PUTB(reg, VGA_ATR_AD, i);
usr/src/common/vga/vgasubr.c
167
PUTB(reg, VGA_ATR_AD, v);
usr/src/common/vga/vgasubr.c
169
(void) GETB(reg, CGA_STAT);
usr/src/common/vga/vgasubr.c
170
PUTB(reg, VGA_ATR_AD, VGA_ATR_ENB_PLT);
usr/src/common/vga/vgasubr.c
175
vgaregmap_t reg,
usr/src/common/vga/vgasubr.c
181
PUTB(reg, indexreg, index);
usr/src/common/vga/vgasubr.c
182
PUTB(reg, datareg, val);
usr/src/common/vga/vgasubr.c
187
vgaregmap_t reg,
usr/src/common/vga/vgasubr.c
192
PUTB(reg, indexreg, index);
usr/src/common/vga/vgasubr.c
193
return (GETB(reg, datareg));
usr/src/common/vga/vgasubr.c
203
vgaregmap_t reg,
usr/src/common/vga/vgasubr.c
210
PUTB(reg, VGA_DAC_WR_AD, index);
usr/src/common/vga/vgasubr.c
211
PUTB(reg, VGA_DAC_DATA, r >> 2);
usr/src/common/vga/vgasubr.c
212
PUTB(reg, VGA_DAC_DATA, g >> 2);
usr/src/common/vga/vgasubr.c
213
PUTB(reg, VGA_DAC_DATA, b >> 2);
usr/src/common/vga/vgasubr.c
218
vgaregmap_t reg,
usr/src/common/vga/vgasubr.c
224
PUTB(reg, VGA_DAC_RD_AD, index);
usr/src/common/vga/vgasubr.c
225
*r = GETB(reg, VGA_DAC_DATA) << 2;
usr/src/common/vga/vgasubr.c
226
*g = GETB(reg, VGA_DAC_DATA) << 2;
usr/src/common/vga/vgasubr.c
227
*b = GETB(reg, VGA_DAC_DATA) << 2;
usr/src/common/vga/vgasubr.c
233
vga_dump_regs(vgaregmap_t reg, int maxseq, int maxcrtc, int maxatr, int maxgrc)
usr/src/common/vga/vgasubr.c
241
printf("%2x ", vga_get_seq(reg, i+j));
usr/src/common/vga/vgasubr.c
245
printf("%2x ", vga_get_seq(reg, i+j));
usr/src/common/vga/vgasubr.c
253
printf("%2x ", vga_get_crtc(reg, i+j));
usr/src/common/vga/vgasubr.c
257
printf("%2x ", vga_get_crtc(reg, i+j));
usr/src/common/vga/vgasubr.c
265
printf("%2x ", vga_get_atr(reg, i+j));
usr/src/common/vga/vgasubr.c
269
printf("%2x ", vga_get_atr(reg, i+j));
usr/src/common/vga/vgasubr.c
277
printf("%2x ", vga_get_grc(reg, i+j));
usr/src/common/vga/vgasubr.c
281
printf("%2x ", vga_get_grc(reg, i+j));
usr/src/common/vga/vgasubr.c
52
#define PUTB(reg, off, v) ddi_put8(reg->handle, reg->addr + (off), v)
usr/src/common/vga/vgasubr.c
53
#define GETB(reg, off) ddi_get8(reg->handle, reg->addr + (off))
usr/src/common/vga/vgasubr.c
60
#define PUTB(reg, off, v) outb(reg + (off), v)
usr/src/common/vga/vgasubr.c
61
#define GETB(reg, off) inb(reg + (off))
usr/src/common/vga/vgasubr.c
92
vga_get_hardware_settings(vgaregmap_t reg, int *width, int *height)
usr/src/common/vga/vgasubr.c
94
*width = (GET_HORIZ_END(reg)+1)*8;
usr/src/common/vga/vgasubr.c
95
*height = GET_VERT_END(reg)+1;
usr/src/common/vga/vgasubr.c
96
if (GET_VERT_X2(reg)) *height *= 2;
usr/src/compat/bhyve/amd64/machine/cpufunc.h
177
rxcr(u_int reg)
usr/src/compat/bhyve/amd64/machine/cpufunc.h
181
__asm __volatile("xgetbv" : "=a" (low), "=d" (high) : "c" (reg));
usr/src/compat/bhyve/amd64/machine/cpufunc.h
186
load_xcr(u_int reg, u_long val)
usr/src/compat/bhyve/amd64/machine/cpufunc.h
192
__asm __volatile("xsetbv" : : "c" (reg), "a" (low), "d" (high));
usr/src/grub/grub-0.97/netboot/e1000.c
148
#define E1000_WRITE_REG(a, reg, value) ( \
usr/src/grub/grub-0.97/netboot/e1000.c
150
(writel((value), ((a)->hw_addr + E1000_##reg))) : \
usr/src/grub/grub-0.97/netboot/e1000.c
151
(writel((value), ((a)->hw_addr + E1000_82542_##reg))))
usr/src/grub/grub-0.97/netboot/e1000.c
153
#define E1000_READ_REG(a, reg) ( \
usr/src/grub/grub-0.97/netboot/e1000.c
155
readl((a)->hw_addr + E1000_##reg) : \
usr/src/grub/grub-0.97/netboot/e1000.c
156
readl((a)->hw_addr + E1000_82542_##reg))
usr/src/grub/grub-0.97/netboot/e1000.c
158
#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
usr/src/grub/grub-0.97/netboot/e1000.c
160
writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))) : \
usr/src/grub/grub-0.97/netboot/e1000.c
161
writel((value), ((a)->hw_addr + E1000_82542_##reg + ((offset) << 2))))
usr/src/grub/grub-0.97/netboot/e1000.c
163
#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
usr/src/grub/grub-0.97/netboot/e1000.c
165
readl((a)->hw_addr + E1000_##reg + ((offset) << 2)) : \
usr/src/grub/grub-0.97/netboot/e1000.c
166
readl((a)->hw_addr + E1000_82542_##reg + ((offset) << 2)))
usr/src/grub/grub-0.97/netboot/e1000_hw.h
251
#define E1000_READ_REG_IO(a, reg) \
usr/src/grub/grub-0.97/netboot/e1000_hw.h
252
e1000_read_reg_io((a), E1000_##reg)
usr/src/grub/grub-0.97/netboot/e1000_hw.h
253
#define E1000_WRITE_REG_IO(a, reg, val) \
usr/src/grub/grub-0.97/netboot/e1000_hw.h
254
e1000_write_reg_io((a), E1000_##reg, val)
usr/src/grub/grub-0.97/netboot/forcedeth.c
397
u32 reg;
usr/src/grub/grub-0.97/netboot/forcedeth.c
402
reg = readl(base + NvRegAdapterControl);
usr/src/grub/grub-0.97/netboot/forcedeth.c
403
if (reg & NVREG_ADAPTCTL_RUNNING) {
usr/src/grub/grub-0.97/netboot/forcedeth.c
405
writel(reg & ~NVREG_ADAPTCTL_RUNNING,
usr/src/grub/grub-0.97/netboot/forcedeth.c
408
reg = readl(base + NvRegMIIControl);
usr/src/grub/grub-0.97/netboot/forcedeth.c
409
if (reg & NVREG_MIICTL_INUSE) {
usr/src/grub/grub-0.97/netboot/forcedeth.c
414
reg =
usr/src/grub/grub-0.97/netboot/forcedeth.c
418
reg |= NVREG_MIICTL_WRITE;
usr/src/grub/grub-0.97/netboot/forcedeth.c
420
writel(reg, base + NvRegMIIControl);
usr/src/grub/grub-0.97/netboot/forcedeth.c
444
reg = readl(base + NvRegAdapterControl);
usr/src/grub/grub-0.97/netboot/forcedeth.c
445
writel(reg | NVREG_ADAPTCTL_RUNNING,
usr/src/grub/grub-0.97/netboot/pci.c
270
int reg;
usr/src/grub/grub-0.97/netboot/pci.c
362
for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
usr/src/grub/grub-0.97/netboot/pci.c
363
pcibios_read_config_dword(bus, devfn, reg, &ioaddr);
usr/src/grub/grub-0.97/netboot/r8169.c
121
#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
usr/src/grub/grub-0.97/netboot/r8169.c
122
#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
usr/src/grub/grub-0.97/netboot/r8169.c
123
#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
usr/src/grub/grub-0.97/netboot/r8169.c
124
#define RTL_R8(reg) readb (ioaddr + (reg))
usr/src/grub/grub-0.97/netboot/r8169.c
125
#define RTL_R16(reg) readw (ioaddr + (reg))
usr/src/grub/grub-0.97/netboot/r8169.c
126
#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
usr/src/grub/grub-0.97/netboot/sis900.c
239
u8 reg;
usr/src/grub/grub-0.97/netboot/sis900.c
253
pcibios_read_config_byte(p->bus,p->devfn, 0x48, ®);
usr/src/grub/grub-0.97/netboot/sis900.c
254
pcibios_write_config_byte(p->bus,p->devfn, 0x48, reg | 0x40);
usr/src/grub/grub-0.97/netboot/sis900.c
261
pcibios_write_config_byte(p->bus,p->devfn, 0x48, reg & ~0x40);
usr/src/grub/grub-0.97/netboot/tg3.c
104
#define tw32(reg,val) tg3_write_indirect_reg32((reg),(val))
usr/src/grub/grub-0.97/netboot/tg3.c
105
#define tw32_mailbox(reg, val) writel(((val) & 0xffffffff), tg3.regs + (reg))
usr/src/grub/grub-0.97/netboot/tg3.c
106
#define tw16(reg,val) writew(((val) & 0xffff), tg3.regs + (reg))
usr/src/grub/grub-0.97/netboot/tg3.c
107
#define tw8(reg,val) writeb(((val) & 0xff), tg3.regs + (reg))
usr/src/grub/grub-0.97/netboot/tg3.c
108
#define tr32(reg) readl(tg3.regs + (reg))
usr/src/grub/grub-0.97/netboot/tg3.c
109
#define tr16(reg) readw(tg3.regs + (reg))
usr/src/grub/grub-0.97/netboot/tg3.c
110
#define tr8(reg) readb(tg3.regs + (reg))
usr/src/grub/grub-0.97/netboot/tg3.c
112
static void tw32_carefully(uint32_t reg, uint32_t val)
usr/src/grub/grub-0.97/netboot/tg3.c
114
tw32(reg, val);
usr/src/grub/grub-0.97/netboot/tg3.c
115
tr32(reg);
usr/src/grub/grub-0.97/netboot/tg3.c
119
static void tw32_mailbox2(uint32_t reg, uint32_t val)
usr/src/grub/grub-0.97/netboot/tg3.c
121
tw32_mailbox(reg, val);
usr/src/grub/grub-0.97/netboot/tg3.c
122
tr32(reg);
usr/src/grub/grub-0.97/netboot/tg3.c
172
static int tg3_readphy(struct tg3 *tp, int reg, uint32_t *val)
usr/src/grub/grub-0.97/netboot/tg3.c
183
frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
usr/src/grub/grub-0.97/netboot/tg3.c
212
static int tg3_writephy(struct tg3 *tp, int reg, uint32_t val)
usr/src/grub/grub-0.97/netboot/tg3.c
221
frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
usr/src/grub/grub-0.97/netboot/tlan.c
1185
int TLan_MiiReadReg(struct nic *nic __unused, u16 phy, u16 reg, u16 * val)
usr/src/grub/grub-0.97/netboot/tlan.c
1206
TLan_MiiSendData(BASE, reg, 5); /* Register # */
usr/src/grub/grub-0.97/netboot/tlan.c
1345
void TLan_MiiWriteReg(struct nic *nic __unused, u16 phy, u16 reg, u16 val)
usr/src/grub/grub-0.97/netboot/tlan.c
1362
TLan_MiiSendData(BASE, reg, 5); /* Register # */
usr/src/lib/brand/shared/brand/common/brand_util.c
333
brand_proc_reg_t reg;
usr/src/lib/brand/shared/brand/common/brand_util.c
346
reg.sbr_version = version;
usr/src/lib/brand/shared/brand/common/brand_util.c
348
reg.sbr_handler = (caddr_t)brand_handler_table;
usr/src/lib/brand/shared/brand/common/brand_util.c
350
reg.sbr_handler = (caddr_t)brand_handler;
usr/src/lib/brand/shared/brand/common/brand_util.c
353
if ((err = __systemcall(&rval, SYS_brand, B_REGISTER, ®)) != 0) {
usr/src/lib/fm/libfmd_snmp/common/module.c
550
sunFmModuleTable_return(unsigned int reg, void *arg)
usr/src/lib/fm/libfmd_snmp/common/problem.c
693
sunFmProblemTable_return(unsigned int reg, void *arg)
usr/src/lib/fm/libfmd_snmp/common/problem.c
859
sunFmFaultEventTable_return(unsigned int reg, void *arg)
usr/src/lib/fm/libfmd_snmp/common/resource.c
563
sunFmResourceTable_return(unsigned int reg, void *arg)
usr/src/lib/fm/libfmd_snmp/common/resource.c
708
sunFmResourceCount_return(unsigned int reg, void *arg)
usr/src/lib/fm/topo/modules/common/pcibus/did.c
338
uint_t reg;
usr/src/lib/fm/topo/modules/common/pcibus/did.c
357
if (di_uintprop_get(mp, src, DI_REGPROP, ®) < 0) {
usr/src/lib/fm/topo/modules/common/pcibus/did.c
365
np->dp_bus = PCI_REG_BUS_G(reg);
usr/src/lib/fm/topo/modules/common/pcibus/did.c
368
np->dp_dev = PCI_REG_DEV_G(reg);
usr/src/lib/fm/topo/modules/common/pcibus/did.c
369
np->dp_fn = PCI_REG_FUNC_G(reg);
usr/src/lib/fm/topo/modules/common/pcibus/did.c
370
np->dp_bdf = (PCI_REG_BUS_G(reg) << 8) | (PCI_REG_DEV_G(reg) << 3) |
usr/src/lib/fm/topo/modules/common/pcibus/did.c
371
PCI_REG_FUNC_G(reg);
usr/src/lib/fm/topo/modules/common/usb/topo_usb.c
681
int *vend, *reg, *nports;
usr/src/lib/fm/topo/modules/common/usb/topo_usb.c
701
if (di_prop_lookup_ints(DDI_DEV_T_ANY, node, "reg", ®) != 1 ||
usr/src/lib/fm/topo/modules/common/usb/topo_usb.c
702
*reg <= 0) {
usr/src/lib/fm/topo/modules/common/usb/topo_usb.c
707
if ((l = topo_usb_lport_find(plist, (uint_t)*reg)) == NULL) {
usr/src/lib/fm/topo/modules/common/usb/topo_usb.c
709
"port %d", *reg);
usr/src/lib/libc/sparc/gen/getctxt.c
41
greg_t *reg;
usr/src/lib/libc/sparc/gen/getctxt.c
54
reg = ucp->uc_mcontext.gregs;
usr/src/lib/libc/sparc/gen/getctxt.c
55
reg[REG_SP] = getfp();
usr/src/lib/libc/sparc/gen/getctxt.c
56
reg[REG_O7] = caller();
usr/src/lib/libc/sparc/gen/getctxt.c
57
reg[REG_PC] = reg[REG_O7] + 8;
usr/src/lib/libc/sparc/gen/getctxt.c
58
reg[REG_nPC] = reg[REG_PC] + 4;
usr/src/lib/libc/sparc/gen/getctxt.c
59
reg[REG_O0] = 0;
usr/src/lib/libc/sparc/gen/makectxt.c
103
reg[REG_SP] = (greg_t)sp - STACK_BIAS; /* sp (when done) */
usr/src/lib/libc/sparc/gen/makectxt.c
104
reg[REG_O7] = (greg_t)resumecontext - 8; /* return pc */
usr/src/lib/libc/sparc/gen/makectxt.c
110
greg_t *reg;
usr/src/lib/libc/sparc/gen/makectxt.c
117
reg = ucp->uc_mcontext.gregs;
usr/src/lib/libc/sparc/gen/makectxt.c
118
reg[REG_PC] = (greg_t)func;
usr/src/lib/libc/sparc/gen/makectxt.c
119
reg[REG_nPC] = reg[REG_PC] + 0x4;
usr/src/lib/libc/sparc/gen/makectxt.c
143
*tsp++ = reg[REG_O0 + argno] = va_arg(ap, long);
usr/src/lib/libc/sparc/gen/makectxt.c
150
reg[REG_SP] = (greg_t)sp - STACK_BIAS; /* sp (when done) */
usr/src/lib/libc/sparc/gen/makectxt.c
151
reg[REG_O7] = (greg_t)resumecontext - 8; /* return pc */
usr/src/lib/libc/sparc/gen/makectxt.c
57
greg_t *reg;
usr/src/lib/libc/sparc/gen/makectxt.c
64
reg = ucp->uc_mcontext.gregs;
usr/src/lib/libc/sparc/gen/makectxt.c
65
reg[REG_PC] = (greg_t)func;
usr/src/lib/libc/sparc/gen/makectxt.c
66
reg[REG_nPC] = reg[REG_PC] + 0x4;
usr/src/lib/libc/sparc/gen/makectxt.c
96
*tsp++ = reg[REG_O0 + argno] = va_arg(ap, long);
usr/src/lib/libc/sparc/gen/siglongjmp.c
47
greg_t *reg = uc.uc_mcontext.gregs;
usr/src/lib/libc/sparc/gen/siglongjmp.c
62
_fetch_globals(®[REG_G1]);
usr/src/lib/libc/sparc/gen/siglongjmp.c
65
reg[REG_PC] = bp->sjs_pc;
usr/src/lib/libc/sparc/gen/siglongjmp.c
66
reg[REG_nPC] = reg[REG_PC] + 0x4;
usr/src/lib/libc/sparc/gen/siglongjmp.c
67
reg[REG_SP] = bp->sjs_sp;
usr/src/lib/libc/sparc/gen/siglongjmp.c
75
reg[REG_O0] = (greg_t)val;
usr/src/lib/libc/sparc/gen/siglongjmp.c
77
reg[REG_O0] = (greg_t)1;
usr/src/lib/libc/sparc/gen/swapctxt.c
40
greg_t *reg;
usr/src/lib/libc/sparc/gen/swapctxt.c
52
reg = oucp->uc_mcontext.gregs;
usr/src/lib/libc/sparc/gen/swapctxt.c
53
reg[REG_SP] = getfp();
usr/src/lib/libc/sparc/gen/swapctxt.c
54
reg[REG_O7] = caller();
usr/src/lib/libc/sparc/gen/swapctxt.c
55
reg[REG_PC] = reg[REG_O7] + 8;
usr/src/lib/libc/sparc/gen/swapctxt.c
56
reg[REG_nPC] = reg[REG_PC] + 4;
usr/src/lib/libc/sparc/gen/swapctxt.c
57
reg[REG_O0] = 0;
usr/src/lib/libc/sparcv9/gen/getctxt.c
41
greg_t *reg;
usr/src/lib/libc/sparcv9/gen/getctxt.c
54
reg = ucp->uc_mcontext.gregs;
usr/src/lib/libc/sparcv9/gen/getctxt.c
55
reg[REG_SP] = getfp();
usr/src/lib/libc/sparcv9/gen/getctxt.c
56
reg[REG_O7] = caller();
usr/src/lib/libc/sparcv9/gen/getctxt.c
57
reg[REG_PC] = reg[REG_O7] + 8;
usr/src/lib/libc/sparcv9/gen/getctxt.c
58
reg[REG_nPC] = reg[REG_PC] + 4;
usr/src/lib/libc/sparcv9/gen/getctxt.c
59
reg[REG_O0] = 0;
usr/src/lib/libc/sparcv9/gen/makectxt.c
103
reg[REG_SP] = (greg_t)sp - STACK_BIAS; /* sp (when done) */
usr/src/lib/libc/sparcv9/gen/makectxt.c
104
reg[REG_O7] = (greg_t)resumecontext - 8; /* return pc */
usr/src/lib/libc/sparcv9/gen/makectxt.c
110
greg_t *reg;
usr/src/lib/libc/sparcv9/gen/makectxt.c
117
reg = ucp->uc_mcontext.gregs;
usr/src/lib/libc/sparcv9/gen/makectxt.c
118
reg[REG_PC] = (greg_t)func;
usr/src/lib/libc/sparcv9/gen/makectxt.c
119
reg[REG_nPC] = reg[REG_PC] + 0x4;
usr/src/lib/libc/sparcv9/gen/makectxt.c
143
*tsp++ = reg[REG_O0 + argno] = va_arg(ap, long);
usr/src/lib/libc/sparcv9/gen/makectxt.c
150
reg[REG_SP] = (greg_t)sp - STACK_BIAS; /* sp (when done) */
usr/src/lib/libc/sparcv9/gen/makectxt.c
151
reg[REG_O7] = (greg_t)resumecontext - 8; /* return pc */
usr/src/lib/libc/sparcv9/gen/makectxt.c
57
greg_t *reg;
usr/src/lib/libc/sparcv9/gen/makectxt.c
64
reg = ucp->uc_mcontext.gregs;
usr/src/lib/libc/sparcv9/gen/makectxt.c
65
reg[REG_PC] = (greg_t)func;
usr/src/lib/libc/sparcv9/gen/makectxt.c
66
reg[REG_nPC] = reg[REG_PC] + 0x4;
usr/src/lib/libc/sparcv9/gen/makectxt.c
96
*tsp++ = reg[REG_O0 + argno] = va_arg(ap, long);
usr/src/lib/libc/sparcv9/gen/siglongjmp.c
46
greg_t *reg = uc.uc_mcontext.gregs;
usr/src/lib/libc/sparcv9/gen/siglongjmp.c
61
_fetch_globals(®[REG_G1]);
usr/src/lib/libc/sparcv9/gen/siglongjmp.c
64
reg[REG_PC] = bp->sjs_pc;
usr/src/lib/libc/sparcv9/gen/siglongjmp.c
65
reg[REG_nPC] = reg[REG_PC] + 0x4;
usr/src/lib/libc/sparcv9/gen/siglongjmp.c
66
reg[REG_SP] = bp->sjs_sp;
usr/src/lib/libc/sparcv9/gen/siglongjmp.c
67
reg[REG_ASI] = bp->sjs_asi;
usr/src/lib/libc/sparcv9/gen/siglongjmp.c
68
reg[REG_FPRS] = bp->sjs_fprs;
usr/src/lib/libc/sparcv9/gen/siglongjmp.c
76
reg[REG_O0] = (greg_t)val;
usr/src/lib/libc/sparcv9/gen/siglongjmp.c
78
reg[REG_O0] = (greg_t)1;
usr/src/lib/libc/sparcv9/gen/swapctxt.c
40
greg_t *reg;
usr/src/lib/libc/sparcv9/gen/swapctxt.c
52
reg = oucp->uc_mcontext.gregs;
usr/src/lib/libc/sparcv9/gen/swapctxt.c
53
reg[REG_SP] = getfp();
usr/src/lib/libc/sparcv9/gen/swapctxt.c
54
reg[REG_O7] = caller();
usr/src/lib/libc/sparcv9/gen/swapctxt.c
55
reg[REG_PC] = reg[REG_O7] + 8;
usr/src/lib/libc/sparcv9/gen/swapctxt.c
56
reg[REG_nPC] = reg[REG_PC] + 4;
usr/src/lib/libc/sparcv9/gen/swapctxt.c
57
reg[REG_O0] = 0;
usr/src/lib/libcurses/screen/mbinsshift.c
57
reg chtype rb;
usr/src/lib/libdevinfo/devinfo_devlink.c
2066
regex_t reg;
usr/src/lib/libdevinfo/devinfo_devlink.c
2080
if (regcomp(®, re, REG_EXTENDED) != 0)
usr/src/lib/libdevinfo/devinfo_devlink.c
2082
linkd.regp = ®
usr/src/lib/libdevinfo/devinfo_devlink.c
2099
regfree(®);
usr/src/lib/libdevinfo/devinfo_devlink.c
3774
regex_t reg;
usr/src/lib/libdevinfo/devinfo_devlink.c
3788
if (regcomp(®, re, REG_EXTENDED) != 0)
usr/src/lib/libdevinfo/devinfo_devlink.c
3790
linkd.regp = ®
usr/src/lib/libdevinfo/devinfo_devlink.c
3800
regfree(®);
usr/src/lib/libdtrace/common/dt_cg.c
100
dif_instr_t instr = DIF_INSTR_SETX((uint_t)intoff, reg);
usr/src/lib/libdtrace/common/dt_cg.c
115
dt_cg_setx(dt_irlist_t *dlp, int reg, uint64_t x)
usr/src/lib/libdtrace/common/dt_cg.c
117
dt_cg_xsetx(dlp, NULL, DT_LBL_NONE, reg, x);
usr/src/lib/libdtrace/common/dt_cg.c
1256
int reg, n;
usr/src/lib/libdtrace/common/dt_cg.c
1315
reg = dt_regset_alloc(drp);
usr/src/lib/libdtrace/common/dt_cg.c
1319
dt_cg_setx(dlp, reg, n);
usr/src/lib/libdtrace/common/dt_cg.c
1321
instr = DIF_INSTR_FMT(DIF_OP_SLL, dnp->dn_reg, reg, dnp->dn_reg);
usr/src/lib/libdtrace/common/dt_cg.c
1325
DIF_OP_SRA : DIF_OP_SRL, dnp->dn_reg, reg, dnp->dn_reg);
usr/src/lib/libdtrace/common/dt_cg.c
1328
dt_regset_free(drp, reg);
usr/src/lib/libdtrace/common/dt_cg.c
1398
int reg, treg;
usr/src/lib/libdtrace/common/dt_cg.c
1421
reg = dt_regset_alloc(drp);
usr/src/lib/libdtrace/common/dt_cg.c
1423
dt_cg_setx(dlp, reg, off / NBBY);
usr/src/lib/libdtrace/common/dt_cg.c
1424
instr = DIF_INSTR_FMT(DIF_OP_ADD, dx->dtxl_dreg, reg, reg);
usr/src/lib/libdtrace/common/dt_cg.c
1436
instr = DIF_INSTR_STORE(DIF_OP_STB, treg, reg);
usr/src/lib/libdtrace/common/dt_cg.c
1439
instr = DIF_INSTR_STORE(DIF_OP_STH, treg, reg);
usr/src/lib/libdtrace/common/dt_cg.c
1442
instr = DIF_INSTR_STORE(DIF_OP_STW, treg, reg);
usr/src/lib/libdtrace/common/dt_cg.c
1445
instr = DIF_INSTR_STORE(DIF_OP_STX, treg, reg);
usr/src/lib/libdtrace/common/dt_cg.c
1462
instr = DIF_INSTR_COPYS(treg, szreg, reg);
usr/src/lib/libdtrace/common/dt_cg.c
1479
DIF_REG_R0, reg);
usr/src/lib/libdtrace/common/dt_cg.c
1489
dt_regset_free(drp, reg);
usr/src/lib/libdtrace/common/dt_cg.c
1749
int reg;
usr/src/lib/libdtrace/common/dt_cg.c
1752
reg = dt_cg_xlate_expand(dnp, idp, dlp, drp);
usr/src/lib/libdtrace/common/dt_cg.c
1755
dnp->dn_reg = reg;
usr/src/lib/libdtrace/common/dt_cg.c
1902
int reg;
usr/src/lib/libdtrace/common/dt_cg.c
1904
reg = dt_regset_alloc(drp);
usr/src/lib/libdtrace/common/dt_cg.c
1911
dt_cg_setx(dlp, reg, m.ctm_offset / NBBY);
usr/src/lib/libdtrace/common/dt_cg.c
1914
dnp->dn_left->dn_reg, reg, dnp->dn_left->dn_reg);
usr/src/lib/libdtrace/common/dt_cg.c
1918
dt_regset_free(drp, reg);
usr/src/lib/libdtrace/common/dt_cg.c
2144
int reg = dt_cg_xlate_expand(dnp, idp,
usr/src/lib/libdtrace/common/dt_cg.c
2147
dnp->dn_reg = reg;
usr/src/lib/libdtrace/common/dt_cg.c
415
int reg;
usr/src/lib/libdtrace/common/dt_cg.c
429
reg = dt_regset_alloc(drp);
usr/src/lib/libdtrace/common/dt_cg.c
430
dt_cg_setx(dlp, reg, size);
usr/src/lib/libdtrace/common/dt_cg.c
431
instr = DIF_INSTR_COPYS(src->dn_reg, reg, dst->dn_reg);
usr/src/lib/libdtrace/common/dt_cg.c
433
dt_regset_free(drp, reg);
usr/src/lib/libdtrace/common/dt_cg.c
436
reg = dt_cg_field_set(src, dlp, drp, dst);
usr/src/lib/libdtrace/common/dt_cg.c
438
reg = src->dn_reg;
usr/src/lib/libdtrace/common/dt_cg.c
442
instr = DIF_INSTR_STORE(DIF_OP_STB, reg, dst->dn_reg);
usr/src/lib/libdtrace/common/dt_cg.c
445
instr = DIF_INSTR_STORE(DIF_OP_STH, reg, dst->dn_reg);
usr/src/lib/libdtrace/common/dt_cg.c
448
instr = DIF_INSTR_STORE(DIF_OP_STW, reg, dst->dn_reg);
usr/src/lib/libdtrace/common/dt_cg.c
451
instr = DIF_INSTR_STORE(DIF_OP_STX, reg, dst->dn_reg);
usr/src/lib/libdtrace/common/dt_cg.c
460
dt_regset_free(drp, reg);
usr/src/lib/libdtrace/common/dt_cg.c
562
int reg;
usr/src/lib/libdtrace/common/dt_cg.c
573
reg = dt_regset_alloc(drp);
usr/src/lib/libdtrace/common/dt_cg.c
574
dt_cg_setx(dlp, reg, t.dtdt_size);
usr/src/lib/libdtrace/common/dt_cg.c
576
reg = DIF_REG_R0;
usr/src/lib/libdtrace/common/dt_cg.c
580
reg = DIF_REG_R0;
usr/src/lib/libdtrace/common/dt_cg.c
583
instr = DIF_INSTR_PUSHTS(op, t.dtdt_kind, reg, dnp->dn_reg);
usr/src/lib/libdtrace/common/dt_cg.c
587
if (reg != DIF_REG_R0)
usr/src/lib/libdtrace/common/dt_cg.c
588
dt_regset_free(drp, reg);
usr/src/lib/libdtrace/common/dt_cg.c
651
int reg;
usr/src/lib/libdtrace/common/dt_cg.c
662
reg = dt_regset_alloc(drp);
usr/src/lib/libdtrace/common/dt_cg.c
663
dt_cg_setx(dlp, reg, size);
usr/src/lib/libdtrace/common/dt_cg.c
665
instr = DIF_INSTR_FMT(op, dnp->dn_reg, reg, dnp->dn_reg);
usr/src/lib/libdtrace/common/dt_cg.c
667
dt_regset_free(drp, reg);
usr/src/lib/libdtrace/common/dt_cg.c
96
dt_cg_xsetx(dt_irlist_t *dlp, dt_ident_t *idp, uint_t lbl, int reg, uint64_t x)
usr/src/lib/libdtrace/common/dt_link.c
753
#define DT_MAKE_RETL(reg) (0x81c02008 | ((reg) << 14))
usr/src/lib/libdtrace/common/dt_regset.c
110
int reg;
usr/src/lib/libdtrace/common/dt_regset.c
114
reg = (int)((wx << BT_ULSHIFT) | bx);
usr/src/lib/libdtrace/common/dt_regset.c
115
BT_SET(drp->dr_bitmap, reg);
usr/src/lib/libdtrace/common/dt_regset.c
116
return (reg);
usr/src/lib/libdtrace/common/dt_regset.c
127
dt_regset_free(dt_regset_t *drp, int reg)
usr/src/lib/libdtrace/common/dt_regset.c
129
assert(reg >= 0 && reg < drp->dr_size);
usr/src/lib/libdtrace/common/dt_regset.c
130
assert(BT_TEST(drp->dr_bitmap, reg) != 0);
usr/src/lib/libdtrace/common/dt_regset.c
131
BT_CLEAR(drp->dr_bitmap, reg);
usr/src/lib/libdtrace/common/dt_regset.c
78
int reg;
usr/src/lib/libdtrace/common/dt_regset.c
80
for (reg = 0; reg < drp->dr_size; reg++) {
usr/src/lib/libdtrace/common/dt_regset.c
81
if (BT_TEST(drp->dr_bitmap, reg) != 0) {
usr/src/lib/libdtrace/common/dt_regset.c
82
dt_dprintf("%%r%d was left allocated\n", reg);
usr/src/lib/libdwarf/common/pro_frame.c
447
Dwarf_Unsigned reg,
usr/src/lib/libdwarf/common/pro_frame.c
453
res = dwarf_fde_cfa_offset_a(fde,reg,offset,error);
usr/src/lib/libdwarf/common/pro_frame.c
463
Dwarf_Unsigned reg,
usr/src/lib/libdwarf/common/pro_frame.c
481
regno = reg;
usr/src/lib/libi2c/common/libi2c.c
238
int nreg, *reg;
usr/src/lib/libi2c/common/libi2c.c
241
nreg = di_prop_lookup_ints(DDI_DEV_T_ANY, dn, "reg", ®);
usr/src/lib/libi2c/common/libi2c.c
246
(void) snprintf(name, sizeof (name), "%x,%x", reg[0], reg[1]);
usr/src/lib/libi2c/common/libi2c.c
539
int nreg, *reg;
usr/src/lib/libi2c/common/libi2c.c
543
nreg = di_prop_lookup_ints(DDI_DEV_T_ANY, dn, "reg", ®);
usr/src/lib/libi2c/common/libi2c.c
556
if (reg[type_idx] == I2C_ADDR_7BIT) {
usr/src/lib/libi2c/common/libi2c.c
558
} else if (reg[type_idx] == I2C_ADDR_10BIT) {
usr/src/lib/libi2c/common/libi2c.c
563
di_node_name(dn), di_bus_addr(dn), reg[type_idx]));
usr/src/lib/libi2c/common/libi2c.c
566
if ((addr->ia_type == I2C_ADDR_7BIT && reg[addr_idx] >= 1 << 7) ||
usr/src/lib/libi2c/common/libi2c.c
567
(addr->ia_type == I2C_ADDR_10BIT && reg[addr_idx] >= 1 << 10)) {
usr/src/lib/libi2c/common/libi2c.c
570
di_bus_addr(dn), reg[addr_idx]));
usr/src/lib/libi2c/common/libi2c.c
573
addr->ia_addr = (uint16_t)reg[1];
usr/src/lib/libpicltree/picltree.c
3250
el->reg.version = regp->version;
usr/src/lib/libpicltree/picltree.c
3251
el->reg.critical = regp->critical;
usr/src/lib/libpicltree/picltree.c
3253
el->reg.name = strdup(regp->name);
usr/src/lib/libpicltree/picltree.c
3254
if (el->reg.name == NULL)
usr/src/lib/libpicltree/picltree.c
3257
el->reg.plugin_init = regp->plugin_init;
usr/src/lib/libpicltree/picltree.c
3258
el->reg.plugin_fini = regp->plugin_fini;
usr/src/lib/libpicltree/picltree.c
3283
if (p->reg.plugin_fini)
usr/src/lib/libpicltree/picltree.c
3284
(p->reg.plugin_fini)();
usr/src/lib/libpicltree/picltree.c
3513
if (iter->reg.plugin_init)
usr/src/lib/libpicltree/picltree.c
3514
(iter->reg.plugin_init)();
usr/src/lib/libpicltree/ptree_impl.h
211
picld_plugin_reg_t reg;
usr/src/lib/libproc/common/P32ton.c
642
struct _fpreg reg;
usr/src/lib/libproc/common/P32ton.c
647
exp = fpru.reg.exponent & 0x7fff;
usr/src/lib/libproc/common/P32ton.c
652
if (fpru.reg.significand[0] == 0 &&
usr/src/lib/libproc/common/P32ton.c
653
fpru.reg.significand[1] == 0 &&
usr/src/lib/libproc/common/P32ton.c
654
fpru.reg.significand[2] == 0 &&
usr/src/lib/libproc/common/P32ton.c
655
fpru.reg.significand[3] == 0)
usr/src/lib/libproc/common/P32ton.c
661
} else if (fpru.reg.significand[3] & 0x8000) {
usr/src/lib/libproc/common/Pcontrol.c
2148
Pputareg(struct ps_prochandle *P, int regno, prgreg_t reg)
usr/src/lib/libproc/common/Pcontrol.c
2160
P->status.pr_lwp.pr_reg[regno] = reg;
usr/src/lib/libproc/common/Pcontrol.c
3694
Lputareg(struct ps_lwphandle *L, int regno, prgreg_t reg)
usr/src/lib/libproc/common/Pcontrol.c
3706
L->lwp_status.pr_reg[regno] = reg;
usr/src/lib/libprtdiag_psr/sparc/javelin/common/javelin.c
1262
int *reg = NULL;
usr/src/lib/libprtdiag_psr/sparc/javelin/common/javelin.c
1289
reg = (int *)(get_prop_val(prop));
usr/src/lib/libprtdiag_psr/sparc/javelin/common/javelin.c
1292
if ((upa_id == NULL) || (reg == NULL)) {
usr/src/lib/libprtdiag_psr/sparc/javelin/common/javelin.c
1295
offset = reg[1];
usr/src/lib/libprtdiag_psr/sparc/tazmo/common/tazmo.c
1471
int *reg = NULL;
usr/src/lib/libprtdiag_psr/sparc/tazmo/common/tazmo.c
1498
reg = (int *)(get_prop_val(prop));
usr/src/lib/libprtdiag_psr/sparc/tazmo/common/tazmo.c
1501
if ((upa_id == NULL) || (reg == NULL)) {
usr/src/lib/libprtdiag_psr/sparc/tazmo/common/tazmo.c
1504
offset = reg[1];
usr/src/lib/libslp/clib/SLPReg.c
693
struct rereg_entry *reg;
usr/src/lib/libslp/clib/SLPReg.c
702
if (!(reg = malloc(sizeof (*reg)))) {
usr/src/lib/libslp/clib/SLPReg.c
708
if (!(reg->url = strdup(url))) {
usr/src/lib/libslp/clib/SLPReg.c
709
free(reg);
usr/src/lib/libslp/clib/SLPReg.c
715
reg->msg = msg;
usr/src/lib/libslp/clib/SLPReg.c
716
reg->lifetime = lifetime;
usr/src/lib/libslp/clib/SLPReg.c
717
reg->wake_time = (time(NULL) + lifetime) - 60;
usr/src/lib/libslp/clib/SLPReg.c
718
reg->next = NULL;
usr/src/lib/libslp/clib/SLPReg.c
722
reg->wake_time < next_wake_time ?
usr/src/lib/libslp/clib/SLPReg.c
723
reg->wake_time : next_wake_time;
usr/src/lib/libslp/clib/SLPReg.c
728
reregs = reg;
usr/src/lib/libslp/clib/SLPReg.c
733
reg->next = reregs;
usr/src/lib/libslp/clib/SLPReg.c
734
reregs = reg;
usr/src/lib/libslp/javalib/com/sun/slp/PermSARegTable.java
101
Transact.transactTCPMsg(addr, reg, true);
usr/src/lib/libslp/javalib/com/sun/slp/PermSARegTable.java
97
private void send(SrvLocMsg reg) {
usr/src/lib/libslp/javalib/com/sun/slp/SARequester.java
261
pregtable.reg(URL, srvReg);
usr/src/lib/libslp/javalib/com/sun/slp/ServerDATable.java
420
SrvLocMsg reg = (SrvLocMsg)regs.nextElement();
usr/src/lib/libslp/javalib/com/sun/slp/ServerDATable.java
423
if (reg instanceof SSrvReg) {
usr/src/lib/libslp/javalib/com/sun/slp/ServerDATable.java
424
regurl = ((SSrvReg)reg).URL;
usr/src/lib/libslp/javalib/com/sun/slp/ServerDATable.java
426
regurl = ((CSrvReg)reg).URL;
usr/src/lib/libslp/javalib/com/sun/slp/ServerDATable.java
429
SrvLocHeader hdr = reg.getHeader();
usr/src/lib/libslp/javalib/com/sun/slp/ServerDATable.java
443
deleted.addElement(reg);
usr/src/lib/libslp/javalib/com/sun/slp/ServerDATable.java
458
if (reg instanceof SSrvReg) {
usr/src/lib/libslp/javalib/com/sun/slp/ServerDATable.java
459
SSrvReg sreg = (SSrvReg)reg;
usr/src/lib/libslp/javalib/com/sun/slp/ServerDATable.java
467
forwardRegOrDereg(addr, reg);
usr/src/lib/libslp/javalib/com/sun/slp/ServerDATable.java
479
SrvLocMsg reg = (SrvLocMsg)deleted.elementAt(i);
usr/src/lib/libslp/javalib/com/sun/slp/ServerDATable.java
480
SrvLocHeader hdr = reg.getHeader();
usr/src/lib/libslp/javalib/com/sun/slp/ServerDATable.java
482
if (reg instanceof SSrvReg) {
usr/src/lib/libslp/javalib/com/sun/slp/ServerDATable.java
483
regurl = ((SSrvReg)reg).URL;
usr/src/lib/libslp/javalib/com/sun/slp/ServerDATable.java
485
regurl = ((CSrvReg)reg).URL;
usr/src/lib/libslp/javalib/com/sun/slp/ServiceTable.java
343
pregTable.reg(surl, creg);
usr/src/lib/libvmm/libvmm.c
506
vmm_mapreg(int reg)
usr/src/lib/libvmm/libvmm.c
510
if (reg < 0)
usr/src/lib/libvmm/libvmm.c
513
if (reg < KDIREG_NGREG)
usr/src/lib/libvmm/libvmm.c
514
return (vmm_kdi_regmap[reg]);
usr/src/lib/libvmm/libvmm.c
516
if (reg >= VMM_REG_OFFSET &&
usr/src/lib/libvmm/libvmm.c
517
reg < VMM_REG_OFFSET + ARRAY_SIZE(vmm_sys_regmap))
usr/src/lib/libvmm/libvmm.c
518
return (vmm_sys_regmap[reg - VMM_REG_OFFSET]);
usr/src/lib/libvmm/libvmm.c
539
vmm_getreg(vmm_t *vmm, int vcpuid, int reg, uint64_t *val)
usr/src/lib/libvmm/libvmm.c
541
reg = vmm_mapreg(reg);
usr/src/lib/libvmm/libvmm.c
543
if (reg == VM_REG_LAST)
usr/src/lib/libvmm/libvmm.c
546
return (vm_get_register(vmm->vmm_vcpu[vcpuid], reg, val));
usr/src/lib/libvmm/libvmm.c
550
vmm_setreg(vmm_t *vmm, int vcpuid, int reg, uint64_t val)
usr/src/lib/libvmm/libvmm.c
552
reg = vmm_mapreg(reg);
usr/src/lib/libvmm/libvmm.c
554
if (reg == VM_REG_LAST)
usr/src/lib/libvmm/libvmm.c
557
return (vm_set_register(vmm->vmm_vcpu[vcpuid], reg, val));
usr/src/lib/libvmmapi/common/vmmapi.c
803
vm_set_desc(struct vcpu *vcpu, int reg,
usr/src/lib/libvmmapi/common/vmmapi.c
811
vmsegdesc.regnum = reg;
usr/src/lib/libvmmapi/common/vmmapi.c
821
vm_get_desc(struct vcpu *vcpu, int reg, uint64_t *base, uint32_t *limit,
usr/src/lib/libvmmapi/common/vmmapi.c
829
vmsegdesc.regnum = reg;
usr/src/lib/libvmmapi/common/vmmapi.c
841
vm_get_seg_desc(struct vcpu *vcpu, int reg, struct seg_desc *seg_desc)
usr/src/lib/libvmmapi/common/vmmapi.c
845
error = vm_get_desc(vcpu, reg, &seg_desc->base, &seg_desc->limit,
usr/src/lib/libvmmapi/common/vmmapi.c
851
vm_set_register(struct vcpu *vcpu, int reg, uint64_t val)
usr/src/lib/libvmmapi/common/vmmapi.c
858
vmreg.regnum = reg;
usr/src/lib/libvmmapi/common/vmmapi.c
866
vm_get_register(struct vcpu *vcpu, int reg, uint64_t *ret_val)
usr/src/lib/libvmmapi/common/vmmapi.c
873
vmreg.regnum = reg;
usr/src/lib/libvmmapi/common/vmmapi.h
185
int vm_set_desc(struct vcpu *vcpu, int reg,
usr/src/lib/libvmmapi/common/vmmapi.h
187
int vm_get_desc(struct vcpu *vcpu, int reg,
usr/src/lib/libvmmapi/common/vmmapi.h
189
int vm_get_seg_desc(struct vcpu *vcpu, int reg, struct seg_desc *seg_desc);
usr/src/lib/libvmmapi/common/vmmapi.h
190
int vm_set_register(struct vcpu *vcpu, int reg, uint64_t val);
usr/src/lib/libvmmapi/common/vmmapi.h
191
int vm_get_register(struct vcpu *vcpu, int reg, uint64_t *retval);
usr/src/lib/libzoneinfo/common/libzone.c
916
regex_t reg;
usr/src/lib/libzoneinfo/common/libzone.c
920
ret = regcomp(®, expr, REG_EXTENDED);
usr/src/lib/libzoneinfo/common/libzone.c
925
ret = regexec((const regex_t *)®, string, N_MATCH, pmatch, 0);
usr/src/lib/libzoneinfo/common/libzone.c
930
regfree(®);
usr/src/lib/libzoneinfo/common/libzone.c
936
regfree(®);
usr/src/lib/smbsrv/libmlsvc/common/spoolss_svc.c
693
static spoolss_winreg_t reg[] = {
usr/src/lib/smbsrv/libmlsvc/common/spoolss_svc.c
724
for (i = 0; i < sizeof (reg) / sizeof (reg[0]); ++i) {
usr/src/lib/smbsrv/libmlsvc/common/spoolss_svc.c
727
rp = ®[i];
usr/src/test/bhyve-tests/tests/kdev/payload_vhpet_freq.c
27
write_hpet(uint_t reg, uint32_t value)
usr/src/test/bhyve-tests/tests/kdev/payload_vhpet_freq.c
29
volatile uint32_t *ptr = (uint32_t *)(MMIO_HPET_BASE + reg);
usr/src/test/bhyve-tests/tests/kdev/payload_vlapic_freq.c
29
write_vlapic(uint_t reg, uint32_t value)
usr/src/test/bhyve-tests/tests/kdev/payload_vlapic_freq.c
31
volatile uint32_t *ptr = (uint32_t *)(MMIO_LAPIC_BASE + reg);
usr/src/test/bhyve-tests/tests/kdev/payload_vlapic_freq.c
36
read_vlapic(uint_t reg)
usr/src/test/bhyve-tests/tests/kdev/payload_vlapic_freq.c
38
volatile uint32_t *ptr = (uint32_t *)(MMIO_LAPIC_BASE + reg);
usr/src/test/bhyve-tests/tests/kdev/payload_vlapic_freq_periodic.c
33
write_vlapic(uint_t reg, uint32_t value)
usr/src/test/bhyve-tests/tests/kdev/payload_vlapic_freq_periodic.c
35
volatile uint32_t *ptr = (uint32_t *)(MMIO_LAPIC_BASE + reg);
usr/src/test/bhyve-tests/tests/kdev/payload_vlapic_freq_periodic.c
40
read_vlapic(uint_t reg)
usr/src/test/bhyve-tests/tests/kdev/payload_vlapic_freq_periodic.c
42
volatile uint32_t *ptr = (uint32_t *)(MMIO_LAPIC_BASE + reg);
usr/src/test/bhyve-tests/tests/kdev/payload_vlapic_mmio_access.c
26
write_vlapic(uint_t reg, uint32_t value)
usr/src/test/bhyve-tests/tests/kdev/payload_vlapic_mmio_access.c
28
volatile uint32_t *ptr = (uint32_t *)(MMIO_LAPIC_BASE + reg);
usr/src/test/bhyve-tests/tests/kdev/payload_vlapic_mmio_access.c
33
read_vlapic(uint_t reg)
usr/src/test/bhyve-tests/tests/kdev/payload_vlapic_mmio_access.c
35
volatile uint32_t *ptr = (uint32_t *)(MMIO_LAPIC_BASE + reg);
usr/src/test/bhyve-tests/tests/kdev/payload_vlapic_mmio_access.c
55
for (uint_t reg = 0; reg < 0x1000; reg += 16) {
usr/src/test/bhyve-tests/tests/kdev/payload_vlapic_mmio_access.c
65
val = read_vlapic(reg);
usr/src/test/bhyve-tests/tests/kdev/payload_vlapic_mmio_access.c
66
write_vlapic(reg, val);
usr/src/test/bhyve-tests/tests/kdev/payload_vlapic_msr_access.c
27
reg_readable(uint32_t reg)
usr/src/test/bhyve-tests/tests/kdev/payload_vlapic_msr_access.c
29
switch (reg) {
usr/src/test/bhyve-tests/tests/kdev/payload_vlapic_msr_access.c
68
reg_writable(uint32_t reg)
usr/src/test/bhyve-tests/tests/kdev/payload_vlapic_msr_access.c
70
switch (reg) {
usr/src/test/bhyve-tests/tests/vmm/self_destruct.c
73
uint64_t reg = 0;
usr/src/test/bhyve-tests/tests/vmm/self_destruct.c
74
if (vm_get_register(vcpu, VM_REG_GUEST_RAX, ®) == 0) {
usr/src/test/i2c-tests/tests/ioctl/i2c_ioctl_util.c
167
int *reg;
usr/src/test/i2c-tests/tests/ioctl/i2c_ioctl_util.c
168
int nreg = di_prop_lookup_ints(DDI_DEV_T_ANY, dn, "reg", ®);
usr/src/test/i2c-tests/tests/ioctl/i2c_ioctl_util.c
172
if (reg[0] == I2C_ADDR_7BIT && reg[1] == addr) {
usr/src/test/i2c-tests/tests/ioctl/i2c_ioctl_util.c
182
int nreg, *reg;
usr/src/test/i2c-tests/tests/ioctl/i2c_ioctl_util.c
185
nreg = di_prop_lookup_ints(DDI_DEV_T_ANY, dn, "reg", ®);
usr/src/test/i2c-tests/tests/ioctl/i2c_ioctl_util.c
190
(void) snprintf(name, sizeof (name), "%x,%x", reg[0], reg[1]);
usr/src/test/os-tests/tests/xsave/xsave_util.c
303
xsu_dump_vector(FILE *f, const upad512_t *reg, uint32_t nu32, const char *name,
usr/src/test/os-tests/tests/xsave/xsave_util.c
309
"0x%08x 0x%08x }\n", name, idx, i + 3, i, reg->_l[i + 3],
usr/src/test/os-tests/tests/xsave/xsave_util.c
310
reg->_l[i + 2], reg->_l[i + 1], reg->_l[i]);
usr/src/tools/smatch/src/compile-i386.c
1090
struct storage *reg = NULL;
usr/src/tools/smatch/src/compile-i386.c
1101
reg = temp_from_bits(bit_size);
usr/src/tools/smatch/src/compile-i386.c
1102
emit_move(src, reg, ctype, "begin copy ..");
usr/src/tools/smatch/src/compile-i386.c
1110
emit_move(reg, dest, ctype, ".... end copy");
usr/src/tools/smatch/src/compile-i386.c
1111
put_reg(reg);
usr/src/tools/smatch/src/compile-i386.c
115
struct reg_info *reg;
usr/src/tools/smatch/src/compile-i386.c
1182
backing = src->reg->contains;
usr/src/tools/smatch/src/compile-i386.c
1185
if (backing->reg != src->reg)
usr/src/tools/smatch/src/compile-i386.c
1188
backing->reg = dest->reg;
usr/src/tools/smatch/src/compile-i386.c
1190
dest->reg->contains = backing;
usr/src/tools/smatch/src/compile-i386.c
1202
if (src->reg) {
usr/src/tools/smatch/src/compile-i386.c
1203
struct reg_info *info = src->reg;
usr/src/tools/smatch/src/compile-i386.c
1209
dest->reg->contains = src;
usr/src/tools/smatch/src/compile-i386.c
1210
src->reg = dest->reg;
usr/src/tools/smatch/src/compile-i386.c
1215
src->reg->contains = dest;
usr/src/tools/smatch/src/compile-i386.c
1216
dest->reg = src->reg;
usr/src/tools/smatch/src/compile-i386.c
1311
struct storage *reg, *new;
usr/src/tools/smatch/src/compile-i386.c
1326
reg = get_reg_value(right, ®class_32);
usr/src/tools/smatch/src/compile-i386.c
1329
insn("div", reg, REG_EAX, NULL);
usr/src/tools/smatch/src/compile-i386.c
1330
put_reg(reg);
usr/src/tools/smatch/src/compile-i386.c
1332
reg = REG_EAX;
usr/src/tools/smatch/src/compile-i386.c
1334
reg = REG_EDX;
usr/src/tools/smatch/src/compile-i386.c
1335
emit_move(reg, new, NULL, NULL);
usr/src/tools/smatch/src/compile-i386.c
1440
struct storage *reg;
usr/src/tools/smatch/src/compile-i386.c
1446
reg = get_reg_value(val, ®class_32);
usr/src/tools/smatch/src/compile-i386.c
1449
insn("test", reg, reg, NULL);
usr/src/tools/smatch/src/compile-i386.c
1450
put_reg(reg);
usr/src/tools/smatch/src/compile-i386.c
211
#define byte_reg(reg) ((reg) - 16)
usr/src/tools/smatch/src/compile-i386.c
212
#define highbyte_reg(reg) ((reg)-12)
usr/src/tools/smatch/src/compile-i386.c
213
#define word_reg(reg) ((reg)-8)
usr/src/tools/smatch/src/compile-i386.c
247
#define REGSTORAGE(nr) [nr] = { .type = STOR_REG, .reg = reg_info_table + (nr) }
usr/src/tools/smatch/src/compile-i386.c
275
static struct storage * get_hardreg(struct storage *reg, int clear)
usr/src/tools/smatch/src/compile-i386.c
277
struct reg_info *info = reg->reg;
usr/src/tools/smatch/src/compile-i386.c
289
return reg;
usr/src/tools/smatch/src/compile-i386.c
297
static void put_reg(struct storage *reg)
usr/src/tools/smatch/src/compile-i386.c
299
struct reg_info *info = reg->reg;
usr/src/tools/smatch/src/compile-i386.c
369
struct storage *reg;
usr/src/tools/smatch/src/compile-i386.c
372
info = value->reg;
usr/src/tools/smatch/src/compile-i386.c
378
reg = get_reg(class);
usr/src/tools/smatch/src/compile-i386.c
379
emit_move(value, reg, value->ctype, "reload register");
usr/src/tools/smatch/src/compile-i386.c
380
info = reg->reg;
usr/src/tools/smatch/src/compile-i386.c
382
value->reg = info;
usr/src/tools/smatch/src/compile-i386.c
383
return reg;
usr/src/tools/smatch/src/compile-i386.c
451
strcpy(name, s->reg->name);
usr/src/tools/smatch/src/example.c
1003
reg = hardregs + i;
usr/src/tools/smatch/src/example.c
1004
FOR_EACH_PTR_TAG(reg->contains, p) {
usr/src/tools/smatch/src/example.c
1008
reg->dead--;
usr/src/tools/smatch/src/example.c
1010
show_pseudo(pseudo), reg->name);
usr/src/tools/smatch/src/example.c
1013
PACK_PTR_LIST(®->contains);
usr/src/tools/smatch/src/example.c
1078
struct hardreg *reg = getreg(state, br->cond, NULL);
usr/src/tools/smatch/src/example.c
1079
output_insn(state, "testl %s,%s", reg->name, reg->name);
usr/src/tools/smatch/src/example.c
1095
struct hardreg *reg = hardregs + SWITCH_REG;
usr/src/tools/smatch/src/example.c
1098
output_insn(state, "switch on %s", reg->name);
usr/src/tools/smatch/src/example.c
1106
struct hardreg *reg = getreg(state, ret->src, NULL);
usr/src/tools/smatch/src/example.c
1107
if (reg != wants)
usr/src/tools/smatch/src/example.c
1108
output_insn(state, "movl %s,%s", reg->name, wants->name);
usr/src/tools/smatch/src/example.c
1148
struct hardreg *reg = getreg(state, insn->src1, NULL);
usr/src/tools/smatch/src/example.c
1149
output_insn(state, "testl %s,%s", reg->name, reg->name);
usr/src/tools/smatch/src/example.c
1160
struct hardreg *reg;
usr/src/tools/smatch/src/example.c
1258
struct hardreg *reg, *orig;
usr/src/tools/smatch/src/example.c
1269
reg = asm_arguments[index].reg;
usr/src/tools/smatch/src/example.c
1272
move_reg(state, orig, reg);
usr/src/tools/smatch/src/example.c
1274
fill_reg(state, reg, pseudo);
usr/src/tools/smatch/src/example.c
1275
string = reg->name;
usr/src/tools/smatch/src/example.c
1287
arg->reg = NULL;
usr/src/tools/smatch/src/example.c
1300
struct hardreg *reg;
usr/src/tools/smatch/src/example.c
1310
reg = target_reg(state, pseudo, NULL);
usr/src/tools/smatch/src/example.c
1312
arg->reg = reg;
usr/src/tools/smatch/src/example.c
1313
string = reg->name;
usr/src/tools/smatch/src/example.c
1464
static void write_reg_to_storage(struct bb_state *state, struct hardreg *reg, pseudo_t pseudo, struct storage *storage)
usr/src/tools/smatch/src/example.c
1472
if (reg == out)
usr/src/tools/smatch/src/example.c
1474
output_insn(state, "movl %s,%s", reg->name, out->name);
usr/src/tools/smatch/src/example.c
1477
if (reg->busy < VERY_BUSY) {
usr/src/tools/smatch/src/example.c
1479
storage->regno = reg - hardregs;
usr/src/tools/smatch/src/example.c
1480
reg->busy = REG_FIXED;
usr/src/tools/smatch/src/example.c
1489
output_insn(state, "movl %s,%s", reg->name, out->name);
usr/src/tools/smatch/src/example.c
1500
output_insn(state, "movl %s,%s", reg->name, show_memop(storage));
usr/src/tools/smatch/src/example.c
1544
struct hardreg *reg = hardregs + i;
usr/src/tools/smatch/src/example.c
1547
FOR_EACH_PTR_TAG(reg->contains, p) {
usr/src/tools/smatch/src/example.c
1549
write_reg_to_storage(state, reg, pseudo, out);
usr/src/tools/smatch/src/example.c
156
struct hardreg *reg;
usr/src/tools/smatch/src/example.c
1581
static int final_pseudo_flush(struct bb_state *state, pseudo_t pseudo, struct hardreg *reg)
usr/src/tools/smatch/src/example.c
1627
output_insn(state, "movl %s,%s", reg->name, show_memop(out));
usr/src/tools/smatch/src/example.c
1631
if (reg == dst)
usr/src/tools/smatch/src/example.c
1633
output_insn(state, "movl %s,%s", reg->name, dst->name);
usr/src/tools/smatch/src/example.c
1650
struct hardreg *reg = hardregs + out->regno;
usr/src/tools/smatch/src/example.c
1654
reg->busy = REG_FIXED;
usr/src/tools/smatch/src/example.c
1655
FOR_EACH_PTR_TAG(reg->contains, p) {
usr/src/tools/smatch/src/example.c
1664
if (final_pseudo_flush(state, p, reg)) {
usr/src/tools/smatch/src/example.c
1670
PACK_PTR_LIST(®->contains);
usr/src/tools/smatch/src/example.c
1672
flush_reg(state, reg);
usr/src/tools/smatch/src/example.c
1757
struct hardreg *reg = hardregs + s->regno;
usr/src/tools/smatch/src/example.c
1758
reg->used = 1;
usr/src/tools/smatch/src/example.c
183
return op->reg->name;
usr/src/tools/smatch/src/example.c
381
static void flush_reg(struct bb_state *state, struct hardreg *reg)
usr/src/tools/smatch/src/example.c
385
if (reg->busy)
usr/src/tools/smatch/src/example.c
386
output_comment(state, "reg %s flushed while busy is %d!", reg->name, reg->busy);
usr/src/tools/smatch/src/example.c
387
if (!reg->contains)
usr/src/tools/smatch/src/example.c
389
reg->dead = 0;
usr/src/tools/smatch/src/example.c
390
reg->used = 1;
usr/src/tools/smatch/src/example.c
391
FOR_EACH_PTR_TAG(reg->contains, pseudo) {
usr/src/tools/smatch/src/example.c
396
flush_one_pseudo(state, reg, pseudo);
usr/src/tools/smatch/src/example.c
398
free_ptr_list(®->contains);
usr/src/tools/smatch/src/example.c
401
static struct storage_hash *find_pseudo_storage(struct bb_state *state, pseudo_t pseudo, struct hardreg *reg)
usr/src/tools/smatch/src/example.c
430
if (reg && !reg->used) {
usr/src/tools/smatch/src/example.c
432
src->storage->regno = reg - hardregs;
usr/src/tools/smatch/src/example.c
440
static void mark_reg_dead(struct bb_state *state, pseudo_t pseudo, struct hardreg *reg)
usr/src/tools/smatch/src/example.c
444
FOR_EACH_PTR_TAG(reg->contains, p) {
usr/src/tools/smatch/src/example.c
449
output_comment(state, "marking pseudo %s in reg %s dead", show_pseudo(pseudo), reg->name);
usr/src/tools/smatch/src/example.c
451
reg->dead++;
usr/src/tools/smatch/src/example.c
455
static void add_pseudo_reg(struct bb_state *state, pseudo_t pseudo, struct hardreg *reg)
usr/src/tools/smatch/src/example.c
457
output_comment(state, "added pseudo %s to reg %s", show_pseudo(pseudo), reg->name);
usr/src/tools/smatch/src/example.c
458
add_ptr_list_tag(®->contains, pseudo, TAG_DIRTY);
usr/src/tools/smatch/src/example.c
477
struct hardreg *reg = hardregs;
usr/src/tools/smatch/src/example.c
479
for (i = 0; i < REGNO; i++, reg++) {
usr/src/tools/smatch/src/example.c
480
if (!reg->contains)
usr/src/tools/smatch/src/example.c
481
return reg;
usr/src/tools/smatch/src/example.c
490
struct hardreg *reg;
usr/src/tools/smatch/src/example.c
493
reg = preferred_reg(state, target);
usr/src/tools/smatch/src/example.c
494
if (reg && !reg->contains)
usr/src/tools/smatch/src/example.c
497
reg = empty_reg(state);
usr/src/tools/smatch/src/example.c
498
if (reg)
usr/src/tools/smatch/src/example.c
506
reg = hardregs + i;
usr/src/tools/smatch/src/example.c
507
if (!reg->busy) {
usr/src/tools/smatch/src/example.c
508
flush_reg(state, reg);
usr/src/tools/smatch/src/example.c
516
add_pseudo_reg(state, pseudo, reg);
usr/src/tools/smatch/src/example.c
517
return reg;
usr/src/tools/smatch/src/example.c
523
struct hardreg *reg;
usr/src/tools/smatch/src/example.c
528
reg = hardregs + i;
usr/src/tools/smatch/src/example.c
529
FOR_EACH_PTR_TAG(reg->contains, p) {
usr/src/tools/smatch/src/example.c
532
output_comment(state, "found pseudo %s in reg %s (busy=%d)", show_pseudo(pseudo), reg->name, reg->busy);
usr/src/tools/smatch/src/example.c
533
return reg;
usr/src/tools/smatch/src/example.c
542
struct hardreg *reg = find_in_reg(state, pseudo);
usr/src/tools/smatch/src/example.c
544
if (reg)
usr/src/tools/smatch/src/example.c
545
flush_reg(state, reg);
usr/src/tools/smatch/src/example.c
548
static void flush_cc_cache_to_reg(struct bb_state *state, pseudo_t pseudo, struct hardreg *reg)
usr/src/tools/smatch/src/example.c
554
output_insn(state, "%s %s", opcodes[opcode], reg->name);
usr/src/tools/smatch/src/example.c
642
struct hardreg *reg;
usr/src/tools/smatch/src/example.c
644
reg = find_in_reg(state, pseudo);
usr/src/tools/smatch/src/example.c
645
if (reg)
usr/src/tools/smatch/src/example.c
646
return reg;
usr/src/tools/smatch/src/example.c
647
reg = target_reg(state, pseudo, target);
usr/src/tools/smatch/src/example.c
648
return fill_reg(state, reg, pseudo);
usr/src/tools/smatch/src/example.c
659
struct hardreg *reg;
usr/src/tools/smatch/src/example.c
669
reg = preferred_reg(state, target);
usr/src/tools/smatch/src/example.c
670
if (reg && !reg->contains) {
usr/src/tools/smatch/src/example.c
671
output_comment(state, "copying %s to preferred target %s", show_pseudo(target), reg->name);
usr/src/tools/smatch/src/example.c
672
move_reg(state, src, reg);
usr/src/tools/smatch/src/example.c
673
return reg;
usr/src/tools/smatch/src/example.c
677
reg = hardregs + i;
usr/src/tools/smatch/src/example.c
678
if (!reg->contains) {
usr/src/tools/smatch/src/example.c
679
output_comment(state, "copying %s to %s", show_pseudo(target), reg->name);
usr/src/tools/smatch/src/example.c
680
output_insn(state, "movl %s,%s", src->name, reg->name);
usr/src/tools/smatch/src/example.c
681
return reg;
usr/src/tools/smatch/src/example.c
693
op->reg->busy--;
usr/src/tools/smatch/src/example.c
718
op->reg = getreg(state, pseudo, target);
usr/src/tools/smatch/src/example.c
719
op->reg->busy++;
usr/src/tools/smatch/src/example.c
735
struct hardreg *reg;
usr/src/tools/smatch/src/example.c
760
reg = find_in_reg(state, pseudo);
usr/src/tools/smatch/src/example.c
761
if (reg) {
usr/src/tools/smatch/src/example.c
763
op->reg = reg;
usr/src/tools/smatch/src/example.c
764
reg->busy++;
usr/src/tools/smatch/src/example.c
774
op->reg = hardregs + src->regno;
usr/src/tools/smatch/src/example.c
775
op->reg->busy++;
usr/src/tools/smatch/src/example.c
797
struct hardreg *reg;
usr/src/tools/smatch/src/example.c
814
reg = target_reg(state, pseudo, NULL);
usr/src/tools/smatch/src/example.c
815
output_insn(state, "lea %s,%s", show_op(state, op), reg->name);
usr/src/tools/smatch/src/example.c
816
return reg->name;
usr/src/tools/smatch/src/example.c
864
static void kill_dead_reg(struct hardreg *reg)
usr/src/tools/smatch/src/example.c
866
if (reg->dead) {
usr/src/tools/smatch/src/example.c
869
FOR_EACH_PTR_TAG(reg->contains, p) {
usr/src/tools/smatch/src/example.c
872
reg->dead--;
usr/src/tools/smatch/src/example.c
875
PACK_PTR_LIST(®->contains);
usr/src/tools/smatch/src/example.c
876
assert(!reg->dead);
usr/src/tools/smatch/src/example.c
893
dst = target_copy_reg(state, src->reg, insn->target);
usr/src/tools/smatch/src/example.c
906
static int is_dead_reg(struct bb_state *state, pseudo_t pseudo, struct hardreg *reg)
usr/src/tools/smatch/src/example.c
909
FOR_EACH_PTR_TAG(reg->contains, p) {
usr/src/tools/smatch/src/example.c
997
struct hardreg *reg;
usr/src/uts/common/fs/udfs/udf_subr.c
905
ud_update_regid(struct regid *reg)
usr/src/uts/common/fs/udfs/udf_subr.c
909
bzero(reg->reg_id, 23);
usr/src/uts/common/fs/udfs/udf_subr.c
910
(void) strncpy(reg->reg_id, SUN_IMPL_ID, SUN_IMPL_ID_LEN);
usr/src/uts/common/fs/udfs/udf_subr.c
911
reg->reg_ids[0] = SUN_OS_CLASS;
usr/src/uts/common/fs/udfs/udf_subr.c
912
reg->reg_ids[1] = SUN_OS_ID;
usr/src/uts/common/fs/zfs/lua/lapi.c
608
Table *reg = hvalue(&G(L)->l_registry);
usr/src/uts/common/fs/zfs/lua/lapi.c
611
gt = luaH_getint(reg, LUA_RIDX_GLOBALS);
usr/src/uts/common/fs/zfs/lua/lapi.c
734
Table *reg = hvalue(&G(L)->l_registry);
usr/src/uts/common/fs/zfs/lua/lapi.c
738
gt = luaH_getint(reg, LUA_RIDX_GLOBALS);
usr/src/uts/common/fs/zfs/lua/lapi.c
984
Table *reg = hvalue(&G(L)->l_registry);
usr/src/uts/common/fs/zfs/lua/lapi.c
985
const TValue *gt = luaH_getint(reg, LUA_RIDX_GLOBALS);
usr/src/uts/common/fs/zfs/lua/lcode.c
130
static int patchtestreg (FuncState *fs, int node, int reg) {
usr/src/uts/common/fs/zfs/lua/lcode.c
134
if (reg != NO_REG && reg != GETARG_B(*i))
usr/src/uts/common/fs/zfs/lua/lcode.c
135
SETARG_A(*i, reg);
usr/src/uts/common/fs/zfs/lua/lcode.c
149
static void patchlistaux (FuncState *fs, int list, int vtarget, int reg,
usr/src/uts/common/fs/zfs/lua/lcode.c
153
if (patchtestreg(fs, list, reg))
usr/src/uts/common/fs/zfs/lua/lcode.c
249
int luaK_codek (FuncState *fs, int reg, int k) {
usr/src/uts/common/fs/zfs/lua/lcode.c
251
return luaK_codeABx(fs, OP_LOADK, reg, k);
usr/src/uts/common/fs/zfs/lua/lcode.c
253
int p = luaK_codeABx(fs, OP_LOADKX, reg, 0);
usr/src/uts/common/fs/zfs/lua/lcode.c
276
static void freereg (FuncState *fs, int reg) {
usr/src/uts/common/fs/zfs/lua/lcode.c
277
if (!ISK(reg) && reg >= fs->nactvar) {
usr/src/uts/common/fs/zfs/lua/lcode.c
279
lua_assert(reg == fs->freereg);
usr/src/uts/common/fs/zfs/lua/lcode.c
420
static void discharge2reg (FuncState *fs, expdesc *e, int reg) {
usr/src/uts/common/fs/zfs/lua/lcode.c
424
luaK_nil(fs, reg, 1);
usr/src/uts/common/fs/zfs/lua/lcode.c
428
luaK_codeABC(fs, OP_LOADBOOL, reg, e->k == VTRUE, 0);
usr/src/uts/common/fs/zfs/lua/lcode.c
432
luaK_codek(fs, reg, e->u.info);
usr/src/uts/common/fs/zfs/lua/lcode.c
436
luaK_codek(fs, reg, luaK_numberK(fs, e->u.nval));
usr/src/uts/common/fs/zfs/lua/lcode.c
441
SETARG_A(*pc, reg);
usr/src/uts/common/fs/zfs/lua/lcode.c
445
if (reg != e->u.info)
usr/src/uts/common/fs/zfs/lua/lcode.c
446
luaK_codeABC(fs, OP_MOVE, reg, e->u.info, 0);
usr/src/uts/common/fs/zfs/lua/lcode.c
454
e->u.info = reg;
usr/src/uts/common/fs/zfs/lua/lcode.c
467
static void exp2reg (FuncState *fs, expdesc *e, int reg) {
usr/src/uts/common/fs/zfs/lua/lcode.c
468
discharge2reg(fs, e, reg);
usr/src/uts/common/fs/zfs/lua/lcode.c
477
p_f = code_label(fs, reg, 0, 1);
usr/src/uts/common/fs/zfs/lua/lcode.c
478
p_t = code_label(fs, reg, 1, 0);
usr/src/uts/common/fs/zfs/lua/lcode.c
482
patchlistaux(fs, e->f, final, reg, p_f);
usr/src/uts/common/fs/zfs/lua/lcode.c
483
patchlistaux(fs, e->t, final, reg, p_t);
usr/src/uts/common/fs/zfs/lua/lcode.c
486
e->u.info = reg;
usr/src/uts/common/fs/zfs/lua/lcode.h
49
LUAI_FUNC int luaK_codek (FuncState *fs, int reg, int k);
usr/src/uts/common/fs/zfs/lua/ldebug.c
317
static const char *getobjname (Proto *p, int lastpc, int reg,
usr/src/uts/common/fs/zfs/lua/ldebug.c
354
static int findsetreg (Proto *p, int lastpc, int reg) {
usr/src/uts/common/fs/zfs/lua/ldebug.c
365
if (a <= reg && reg <= a + b) /* set registers from 'a' to 'a+b' */
usr/src/uts/common/fs/zfs/lua/ldebug.c
370
if (reg >= a + 2) /* affect all regs above its base */
usr/src/uts/common/fs/zfs/lua/ldebug.c
376
if (reg >= a) /* affect all registers above base */
usr/src/uts/common/fs/zfs/lua/ldebug.c
391
if (reg == a) /* jumped code can change 'a' */
usr/src/uts/common/fs/zfs/lua/ldebug.c
396
if (testAMode(op) && reg == a) /* any instruction that set A */
usr/src/uts/common/fs/zfs/lua/ldebug.c
405
static const char *getobjname (Proto *p, int lastpc, int reg,
usr/src/uts/common/fs/zfs/lua/ldebug.c
408
*name = luaF_getlocalname(p, reg + 1, lastpc);
usr/src/uts/common/fs/zfs/lua/ldebug.c
412
pc = findsetreg(p, lastpc, reg);
usr/src/uts/common/fs/zfs/lua/lparser.c
1273
int reg;
usr/src/uts/common/fs/zfs/lua/lparser.c
1277
reg = e.u.info;
usr/src/uts/common/fs/zfs/lua/lparser.c
1278
return reg;
usr/src/uts/common/fs/zfs/lua/lparser.c
180
int reg = registerlocalvar(ls, name);
usr/src/uts/common/fs/zfs/lua/lparser.c
185
dyd->actvar.arr[dyd->actvar.n++].idx = cast(short, reg);
usr/src/uts/common/fs/zfs/lua/lparser.c
321
int reg = fs->freereg;
usr/src/uts/common/fs/zfs/lua/lparser.c
323
luaK_nil(fs, reg, extra);
usr/src/uts/common/fs/zfs/lua/lparser.c
654
int reg = ls->fs->freereg;
usr/src/uts/common/fs/zfs/lua/lparser.c
668
fs->freereg = reg; /* free registers */
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1002
uint_t reg;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1010
status = hci1394_ohci_phy_read_no_lock(ohci_hdl, address, ®);
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1017
reg = reg | bits;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1018
status = hci1394_ohci_phy_write_no_lock(ohci_hdl, address, reg);
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1039
uint_t reg;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1047
status = hci1394_ohci_phy_read_no_lock(ohci_hdl, address, ®);
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1054
reg = reg & ~bits;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1055
status = hci1394_ohci_phy_write_no_lock(ohci_hdl, address, reg);
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1279
uint32_t reg;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1297
reg = ddi_get32(ohci_hdl->ohci_reg_handle,
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1299
phy_info = phy_info | ((reg << IEEE1394_SELFID_PHYID_SHIFT) &
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1303
status = hci1394_ohci_phy_read(ohci_hdl, 1, ®);
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1307
phy_info = phy_info | ((reg << IEEE1394_SELFID_GAP_CNT_SHIFT) &
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1311
status = hci1394_ohci_phy_read(ohci_hdl, 2, ®);
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1315
phy_info = phy_info | ((reg & 0xC0) << 8);
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1316
num_ports = reg & 0x1F;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1328
count + 3, ®);
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1333
if ((reg & 0x04) == 0) {
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1338
} else if ((reg & 0x08) == 0) {
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1370
uint32_t reg;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1376
reg = ddi_get32(ohci_hdl->ohci_reg_handle,
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1378
generation_count = (reg & OHCI_SLFC_GEN_MASK) >> OHCI_SLFC_GEN_SHIFT;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1431
uint32_t reg;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1438
reg = ddi_get32(ohci_hdl->ohci_reg_handle,
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1440
*addr = ((uint64_t)reg) << 32;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1441
reg = ddi_get32(ohci_hdl->ohci_reg_handle,
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1443
*addr = *addr | (uint64_t)reg;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1460
uint32_t reg;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1466
reg = ddi_get32(ohci_hdl->ohci_reg_handle,
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1468
guid = ((uint64_t)reg) << 32;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1469
reg = ddi_get32(ohci_hdl->ohci_reg_handle,
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1471
guid = guid | (uint64_t)reg;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1842
uint32_t reg;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1846
reg = ddi_get32(ohci_hdl->ohci_reg_handle,
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1848
*nodeid = (reg & 0xFFFF) << 16;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1861
uint32_t reg;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1865
reg = ((nodeid & 0xFFC00000) >> 16);
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1867
&ohci_hdl->ohci_regs->node_id, reg);
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1882
uint32_t reg;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1887
reg = ddi_get32(ohci_hdl->ohci_reg_handle,
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1889
*nodeid = reg & 0xFFFF;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1890
if ((reg & OHCI_NDID_IDVALID) == 0) {
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1991
uint32_t reg;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1995
reg = ddi_get32(ohci_hdl->ohci_reg_handle,
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
1997
*atreq_retries = reg & OHCI_RET_MAX_ATREQ_MASK;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2009
uint32_t reg;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2015
reg = ddi_get32(ohci_hdl->ohci_reg_handle,
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2017
reg = reg & ~OHCI_RET_MAX_ATREQ_MASK;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2018
reg = reg | (atreq_retries & OHCI_RET_MAX_ATREQ_MASK);
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2020
&ohci_hdl->ohci_regs->at_retries, reg);
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2122
uint32_t reg;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2126
reg = ddi_get32(ohci_hdl->ohci_reg_handle,
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2128
if ((reg & OHCI_REG_NODEID_ROOT) && (reg & OHCI_NDID_IDVALID)) {
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2147
uint32_t reg;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2151
reg = ddi_get32(ohci_hdl->ohci_reg_handle,
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2153
if (reg & OHCI_REG_BUSOPTIONS_CMC) {
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2350
uint32_t reg;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2358
reg = ddi_get32(ohci_hdl->ohci_reg_handle,
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2360
*busgen = (reg & OHCI_SLFC_GEN_MASK) >> OHCI_SLFC_GEN_SHIFT;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2361
*size = reg & OHCI_SLFC_NUM_QUADS_MASK;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2362
if ((reg & OHCI_SLFC_ERROR) == 0) {
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2378
uint32_t reg;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2388
reg = ddi_get32(ohci_hdl->ohci_selfid.bi_handle,
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2390
if (ohci_hdl->ohci_drvinfo->di_gencnt != ((reg & OHCI_SLFC_GEN_MASK) >>
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2480
uint32_t reg;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2486
reg = ddi_get32(ohci_hdl->ohci_reg_handle,
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2488
if (reg & OHCI_CC_ACTIVE_MASK) {
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2494
reg = ddi_get32(ohci_hdl->ohci_reg_handle,
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2496
if (reg & OHCI_CC_ACTIVE_MASK) {
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2706
uint32_t reg;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2711
reg = ddi_get32(ohci_hdl->ohci_reg_handle,
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2713
if (reg & OHCI_HC_PROG_PHY_ENBL) {
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2735
uint32_t reg;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2740
reg = ddi_get32(ohci_hdl->ohci_reg_handle,
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
2742
if (reg & OHCI_HC_PROG_PHY_ENBL) {
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
858
uint_t reg;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
867
reg = OHCI_PHY_IBR;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
869
reg = reg | OHCI_PHY_RHB;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
872
reg = reg | ohci_hdl->ohci_gap_count;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
874
reg = reg | OHCI_PHY_MAX_GAP;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
882
status = hci1394_ohci_phy_write(ohci_hdl, 0x1, reg);
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
903
uint_t reg;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
911
(void) hci1394_ohci_phy_read(ohci_hdl, 0x1, ®);
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
912
reg = reg | OHCI_PHY_IBR;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
913
reg = reg & ~OHCI_PHY_RHB;
usr/src/uts/common/io/1394/adapters/hci1394_ohci.c
920
status = hci1394_ohci_phy_write(ohci_hdl, 0x1, reg);
usr/src/uts/common/io/1394/s1394_cmp.c
145
s1394_cmp_read(s1394_target_t *target, t1394_cmp_reg_t reg, uint32_t *valp)
usr/src/uts/common/io/1394/s1394_cmp.c
151
if (reg == T1394_CMP_OMPR) {
usr/src/uts/common/io/1394/s1394_cmp.c
156
} else if (reg == T1394_CMP_IMPR) {
usr/src/uts/common/io/1394/s1394_cmp.c
167
s1394_cmp_cas(s1394_target_t *target, t1394_cmp_reg_t reg, uint32_t arg_val,
usr/src/uts/common/io/1394/s1394_cmp.c
174
if (reg == T1394_CMP_OMPR) {
usr/src/uts/common/io/1394/s1394_cmp.c
181
} else if (reg == T1394_CMP_IMPR) {
usr/src/uts/common/io/1394/s1394_cmp.c
194
s1394_cmp_notify_reg_change(hal, reg, target);
usr/src/uts/common/io/1394/s1394_cmp.c
328
s1394_cmp_notify_reg_change(s1394_hal_t *hal, t1394_cmp_reg_t reg,
usr/src/uts/common/io/1394/s1394_cmp.c
364
cb(arg, reg);
usr/src/uts/common/io/1394/s1394_cmp.c
48
static void s1394_cmp_notify_reg_change(s1394_hal_t *hal, t1394_cmp_reg_t reg,
usr/src/uts/common/io/1394/s1394_hotplug.c
138
uint32_t reg[6];
usr/src/uts/common/io/1394/s1394_hotplug.c
321
reg[0] = node->node_guid_hi;
usr/src/uts/common/io/1394/s1394_hotplug.c
322
reg[1] = node->node_guid_lo;
usr/src/uts/common/io/1394/s1394_hotplug.c
323
s1394_cfgrom_parse_unit_dir(unit_dir, ®[2], ®[3], ®[4],
usr/src/uts/common/io/1394/s1394_hotplug.c
324
®[5]);
usr/src/uts/common/io/1394/s1394_hotplug.c
326
reg[3] = nunit;
usr/src/uts/common/io/1394/s1394_hotplug.c
329
(int *)reg, 6);
usr/src/uts/common/io/1394/s1394_hotplug.c
335
cmn_err(CE_CONT, "!reg[%d]: 0x%08x", j, reg[j]);
usr/src/uts/common/io/1394/t1394.c
1310
t1394_cmp_read(t1394_handle_t t1394_hdl, t1394_cmp_reg_t reg, uint32_t *valp)
usr/src/uts/common/io/1394/t1394.c
1316
result = s1394_cmp_read((s1394_target_t *)t1394_hdl, reg, valp);
usr/src/uts/common/io/1394/t1394.c
1337
t1394_cmp_cas(t1394_handle_t t1394_hdl, t1394_cmp_reg_t reg, uint32_t arg_val,
usr/src/uts/common/io/1394/t1394.c
1344
result = s1394_cmp_cas((s1394_target_t *)t1394_hdl, reg, arg_val,
usr/src/uts/common/io/1394/targets/av1394/av1394_isoch_recv.c
409
size_t reg, tail;
usr/src/uts/common/io/1394/targets/av1394/av1394_isoch_recv.c
413
icp->ic_pktsz, ®, &tail);
usr/src/uts/common/io/1394/targets/av1394/av1394_isoch_recv.c
419
dmac_laddress + coff, reg,
usr/src/uts/common/io/1394/targets/av1394/av1394_isoch_recv.c
423
off += reg;
usr/src/uts/common/io/1394/targets/av1394/av1394_isoch_recv.c
424
coff += reg;
usr/src/uts/common/io/afe/afe.c
1185
afe_mii_read(void *arg, uint8_t phy, uint8_t reg)
usr/src/uts/common/io/afe/afe.c
1197
return (afe_miireadcomet(afep, phy, reg));
usr/src/uts/common/io/afe/afe.c
1199
return (afe_miireadgeneral(afep, phy, reg));
usr/src/uts/common/io/afe/afe.c
1205
afe_miireadgeneral(afe_t *afep, uint8_t phy, uint8_t reg)
usr/src/uts/common/io/afe/afe.c
1230
afe_miiwritebit(afep, (reg & i) ? 1 : 0);
usr/src/uts/common/io/afe/afe.c
1247
afe_miireadcomet(afe_t *afep, uint8_t phy, uint8_t reg)
usr/src/uts/common/io/afe/afe.c
1252
switch (reg) {
usr/src/uts/common/io/afe/afe.c
1254
reg = CSR_BMCR;
usr/src/uts/common/io/afe/afe.c
1257
reg = CSR_BMSR;
usr/src/uts/common/io/afe/afe.c
1260
reg = CSR_PHYIDR1;
usr/src/uts/common/io/afe/afe.c
1263
reg = CSR_PHYIDR2;
usr/src/uts/common/io/afe/afe.c
1266
reg = CSR_ANAR;
usr/src/uts/common/io/afe/afe.c
1269
reg = CSR_ANLPAR;
usr/src/uts/common/io/afe/afe.c
1272
reg = CSR_ANER;
usr/src/uts/common/io/afe/afe.c
1277
return (GETCSR16(afep, reg) & 0xFFFF);
usr/src/uts/common/io/afe/afe.c
1281
afe_mii_write(void *arg, uint8_t phy, uint8_t reg, uint16_t val)
usr/src/uts/common/io/afe/afe.c
1294
afe_miiwritecomet(afep, phy, reg, val);
usr/src/uts/common/io/afe/afe.c
1297
afe_miiwritegeneral(afep, phy, reg, val);
usr/src/uts/common/io/afe/afe.c
1303
afe_miiwritegeneral(afe_t *afep, uint8_t phy, uint8_t reg, uint16_t val)
usr/src/uts/common/io/afe/afe.c
1327
afe_miiwritebit(afep, (reg & i) ? 1 : 0);
usr/src/uts/common/io/afe/afe.c
1344
afe_miiwritecomet(afe_t *afep, uint8_t phy, uint8_t reg, uint16_t val)
usr/src/uts/common/io/afe/afe.c
1349
switch (reg) {
usr/src/uts/common/io/afe/afe.c
1351
reg = CSR_BMCR;
usr/src/uts/common/io/afe/afe.c
1354
reg = CSR_BMSR;
usr/src/uts/common/io/afe/afe.c
1357
reg = CSR_PHYIDR1;
usr/src/uts/common/io/afe/afe.c
1360
reg = CSR_PHYIDR2;
usr/src/uts/common/io/afe/afe.c
1363
reg = CSR_ANAR;
usr/src/uts/common/io/afe/afe.c
1366
reg = CSR_ANLPAR;
usr/src/uts/common/io/afe/afe.c
1369
reg = CSR_ANER;
usr/src/uts/common/io/afe/afe.c
1374
PUTCSR16(afep, reg, val);
usr/src/uts/common/io/afe/afeimpl.h
289
#define GETCSR(afep, reg) \
usr/src/uts/common/io/afe/afeimpl.h
290
ddi_get32(afep->afe_regshandle, (uint32_t *)(afep->afe_regs + reg))
usr/src/uts/common/io/afe/afeimpl.h
292
#define GETCSR16(afep, reg) \
usr/src/uts/common/io/afe/afeimpl.h
293
ddi_get16(afep->afe_regshandle, (uint16_t *)(afep->afe_regs + reg))
usr/src/uts/common/io/afe/afeimpl.h
295
#define PUTCSR(afep, reg, val) \
usr/src/uts/common/io/afe/afeimpl.h
296
ddi_put32(afep->afe_regshandle, (uint32_t *)(afep->afe_regs + reg), val)
usr/src/uts/common/io/afe/afeimpl.h
298
#define PUTCSR16(afep, reg, val) \
usr/src/uts/common/io/afe/afeimpl.h
299
ddi_put16(afep->afe_regshandle, (uint16_t *)(afep->afe_regs + reg), val)
usr/src/uts/common/io/afe/afeimpl.h
301
#define SETBIT(afep, reg, val) PUTCSR(afep, reg, GETCSR(afep, reg) | (val))
usr/src/uts/common/io/afe/afeimpl.h
303
#define CLRBIT(afep, reg, val) PUTCSR(afep, reg, GETCSR(afep, reg) & ~(val))
usr/src/uts/common/io/arn/arn_ath9k.h
841
boolean_t ath9k_hw_wait(struct ath_hal *ah, uint32_t reg, uint32_t mask,
usr/src/uts/common/io/arn/arn_eeprom.c
61
uint32_t reg, uint32_t mask,
usr/src/uts/common/io/arn/arn_eeprom.c
66
regVal = REG_READ(ah, reg) & ~mask;
usr/src/uts/common/io/arn/arn_eeprom.c
69
REG_WRITE(ah, reg, regVal);
usr/src/uts/common/io/arn/arn_hw.c
1003
reg, val);
usr/src/uts/common/io/arn/arn_hw.c
115
ath9k_hw_wait(struct ath_hal *ah, uint32_t reg, uint32_t mask, uint32_t val)
usr/src/uts/common/io/arn/arn_hw.c
120
if ((REG_READ(ah, reg) & mask) == val)
usr/src/uts/common/io/arn/arn_hw.c
127
reg, REG_READ(ah, reg), mask, val));
usr/src/uts/common/io/arn/arn_hw.c
1356
uint32_t reg, uint32_t value)
usr/src/uts/common/io/arn/arn_hw.c
1362
if (reg == 0x7894) {
usr/src/uts/common/io/arn/arn_hw.c
1396
uint32_t reg, uint32_t value)
usr/src/uts/common/io/arn/arn_hw.c
1403
return (ath9k_hw_def_ini_fixup(ah, pEepData, reg, value));
usr/src/uts/common/io/arn/arn_hw.c
1476
uint32_t reg = INI_RA(&ahp->ah_iniModes, i, 0);
usr/src/uts/common/io/arn/arn_hw.c
1479
REG_WRITE(ah, reg, val);
usr/src/uts/common/io/arn/arn_hw.c
1481
if (reg >= 0x7800 && reg < 0x78a0 &&
usr/src/uts/common/io/arn/arn_hw.c
1503
uint32_t reg = INI_RA(&ahp->ah_iniCommon, i, 0);
usr/src/uts/common/io/arn/arn_hw.c
1506
REG_WRITE(ah, reg, val);
usr/src/uts/common/io/arn/arn_hw.c
1508
if (reg >= 0x7800 && reg < 0x78a0 &&
usr/src/uts/common/io/arn/arn_hw.c
52
uint32_t reg, uint32_t value);
usr/src/uts/common/io/arn/arn_hw.c
994
uint32_t reg =
usr/src/uts/common/io/arn/arn_mac.c
1036
uint32_t reg;
usr/src/uts/common/io/arn/arn_mac.c
1047
reg = REG_READ(ah, AR_OBS_BUS_1);
usr/src/uts/common/io/arn/arn_mac.c
1051
__func__, reg));
usr/src/uts/common/io/asy.c
533
asy_put_idx(const struct asycom *asy, asy_reg_t reg, uint8_t val)
usr/src/uts/common/io/asy.c
537
ASSERT(reg >= ASY_ACR);
usr/src/uts/common/io/asy.c
538
ASSERT(reg <= ASY_NREG);
usr/src/uts/common/io/asy.c
550
asy_put(asy, ASY_SPR, asy_reg_table[reg].asy_reg_off);
usr/src/uts/common/io/asy.c
557
asy_get_idx(const struct asycom *asy, asy_reg_t reg)
usr/src/uts/common/io/asy.c
563
ASSERT(reg >= ASY_ACR);
usr/src/uts/common/io/asy.c
564
ASSERT(reg <= ASY_NREG);
usr/src/uts/common/io/asy.c
570
asy_put(asy, ASY_SPR, asy_reg_table[reg].asy_reg_off);
usr/src/uts/common/io/asy.c
582
asy_put_add(const struct asycom *asy, asy_reg_t reg, uint8_t val)
usr/src/uts/common/io/asy.c
587
ASSERT(reg == ASY_ASR);
usr/src/uts/common/io/asy.c
599
asy_put_reg(asy, reg, val);
usr/src/uts/common/io/asy.c
606
asy_get_add(const struct asycom *asy, asy_reg_t reg)
usr/src/uts/common/io/asy.c
612
ASSERT(reg >= ASY_ASR);
usr/src/uts/common/io/asy.c
613
ASSERT(reg <= ASY_TFL);
usr/src/uts/common/io/asy.c
628
val = asy_get_reg(asy, reg);
usr/src/uts/common/io/asy.c
637
asy_put_ext(const struct asycom *asy, asy_reg_t reg, uint8_t val)
usr/src/uts/common/io/asy.c
650
ASSERT(reg >= ASY_EFR);
usr/src/uts/common/io/asy.c
651
ASSERT(reg <= ASY_XOFF2);
usr/src/uts/common/io/asy.c
660
asy_put_reg(asy, reg, val);
usr/src/uts/common/io/asy.c
667
asy_get_ext(const struct asycom *asy, asy_reg_t reg)
usr/src/uts/common/io/asy.c
680
ASSERT(reg >= ASY_EFR);
usr/src/uts/common/io/asy.c
681
ASSERT(reg <= ASY_XOFF2);
usr/src/uts/common/io/asy.c
690
val = asy_get_reg(asy, reg);
usr/src/uts/common/io/asy.c
699
asy_put_reg(const struct asycom *asy, asy_reg_t reg, uint8_t val)
usr/src/uts/common/io/asy.c
701
ASSERT(asy->asy_hwtype >= asy_reg_table[reg].asy_min_hwtype);
usr/src/uts/common/io/asy.c
704
asy->asy_ioaddr + asy_reg_table[reg].asy_reg_off, val);
usr/src/uts/common/io/asy.c
708
asy_get_reg(const struct asycom *asy, asy_reg_t reg)
usr/src/uts/common/io/asy.c
710
ASSERT(asy->asy_hwtype >= asy_reg_table[reg].asy_min_hwtype);
usr/src/uts/common/io/asy.c
713
asy->asy_ioaddr + asy_reg_table[reg].asy_reg_off));
usr/src/uts/common/io/asy.c
717
asy_put(const struct asycom *asy, asy_reg_t reg, uint8_t val)
usr/src/uts/common/io/asy.c
721
ASSERT(reg > ASY_ILLEGAL);
usr/src/uts/common/io/asy.c
722
ASSERT(reg < ASY_NREG);
usr/src/uts/common/io/asy.c
724
ASSERT(asy->asy_hwtype >= asy_reg_table[reg].asy_min_hwtype);
usr/src/uts/common/io/asy.c
725
ASSERT(asy_reg_table[reg].asy_put_reg != NULL);
usr/src/uts/common/io/asy.c
727
asy_reg_table[reg].asy_put_reg(asy, reg, val);
usr/src/uts/common/io/asy.c
731
asy_get(const struct asycom *asy, asy_reg_t reg)
usr/src/uts/common/io/asy.c
737
ASSERT(reg > ASY_ILLEGAL);
usr/src/uts/common/io/asy.c
738
ASSERT(reg < ASY_NREG);
usr/src/uts/common/io/asy.c
740
ASSERT(asy->asy_hwtype >= asy_reg_table[reg].asy_min_hwtype);
usr/src/uts/common/io/asy.c
741
ASSERT(asy_reg_table[reg].asy_get_reg != NULL);
usr/src/uts/common/io/asy.c
743
val = asy_reg_table[reg].asy_get_reg(asy, reg);
usr/src/uts/common/io/asy.c
749
asy_set(const struct asycom *asy, asy_reg_t reg, uint8_t bits)
usr/src/uts/common/io/asy.c
751
uint8_t val = asy_get(asy, reg);
usr/src/uts/common/io/asy.c
753
asy_put(asy, reg, val | bits);
usr/src/uts/common/io/asy.c
757
asy_clr(const struct asycom *asy, asy_reg_t reg, uint8_t bits)
usr/src/uts/common/io/asy.c
759
uint8_t val = asy_get(asy, reg);
usr/src/uts/common/io/asy.c
761
asy_put(asy, reg, val & ~bits);
usr/src/uts/common/io/atge/atge.h
122
#define FLUSH(atge, reg) \
usr/src/uts/common/io/atge/atge.h
123
(void) INL(atge, reg)
usr/src/uts/common/io/atge/atge.h
125
#define OUTL_OR(atge, reg, v) \
usr/src/uts/common/io/atge/atge.h
126
OUTL(atge, reg, (INL(atge, reg) | v))
usr/src/uts/common/io/atge/atge.h
128
#define OUTL_AND(atge, reg, v) \
usr/src/uts/common/io/atge/atge.h
129
OUTL(atge, reg, (INL(atge, reg) & v))
usr/src/uts/common/io/atge/atge_l1.c
558
uint32_t reg;
usr/src/uts/common/io/atge/atge_l1.c
563
reg = INL(atgep, ATGE_MAC_CFG);
usr/src/uts/common/io/atge/atge_l1.c
564
if ((reg & ATGE_CFG_TX_ENB) != 0) {
usr/src/uts/common/io/atge/atge_l1.c
565
reg &= ~ATGE_CFG_TX_ENB;
usr/src/uts/common/io/atge/atge_l1.c
566
OUTL(atgep, ATGE_MAC_CFG, reg);
usr/src/uts/common/io/atge/atge_l1.c
570
reg = INL(atgep, ATGE_DMA_CFG);
usr/src/uts/common/io/atge/atge_l1.c
571
if ((reg & DMA_CFG_RD_ENB) != 0) {
usr/src/uts/common/io/atge/atge_l1.c
572
reg &= ~DMA_CFG_RD_ENB;
usr/src/uts/common/io/atge/atge_l1.c
573
OUTL(atgep, ATGE_DMA_CFG, reg);
usr/src/uts/common/io/atge/atge_l1.c
592
uint32_t reg;
usr/src/uts/common/io/atge/atge_l1.c
597
reg = INL(atgep, ATGE_MAC_CFG);
usr/src/uts/common/io/atge/atge_l1.c
598
if ((reg & ATGE_CFG_RX_ENB) != 0) {
usr/src/uts/common/io/atge/atge_l1.c
599
reg &= ~ATGE_CFG_RX_ENB;
usr/src/uts/common/io/atge/atge_l1.c
600
OUTL(atgep, ATGE_MAC_CFG, reg);
usr/src/uts/common/io/atge/atge_l1.c
604
reg = INL(atgep, ATGE_DMA_CFG);
usr/src/uts/common/io/atge/atge_l1.c
605
if ((reg & DMA_CFG_WR_ENB) != 0) {
usr/src/uts/common/io/atge/atge_l1.c
606
reg &= ~DMA_CFG_WR_ENB;
usr/src/uts/common/io/atge/atge_l1.c
607
OUTL(atgep, ATGE_DMA_CFG, reg);
usr/src/uts/common/io/atge/atge_l1c.c
415
uint32_t reg;
usr/src/uts/common/io/atge/atge_l1c.c
513
reg = ATGE_USECS(atgep->atge_int_rx_mod) << IM_TIMER_RX_SHIFT;
usr/src/uts/common/io/atge/atge_l1c.c
514
reg |= ATGE_USECS(atgep->atge_int_tx_mod) << IM_TIMER_TX_SHIFT;
usr/src/uts/common/io/atge/atge_l1c.c
515
OUTL(atgep, ATGE_IM_TIMER, reg);
usr/src/uts/common/io/atge/atge_l1c.c
520
reg = 0;
usr/src/uts/common/io/atge/atge_l1c.c
522
reg |= MASTER_IM_RX_TIMER_ENB;
usr/src/uts/common/io/atge/atge_l1c.c
524
reg |= MASTER_IM_TX_TIMER_ENB;
usr/src/uts/common/io/atge/atge_l1c.c
525
OUTL(atgep, ATGE_MASTER_CFG, reg);
usr/src/uts/common/io/atge/atge_l1c.c
532
uint32_t *reg;
usr/src/uts/common/io/atge/atge_l1c.c
539
reg = &smb.rx_frames;
usr/src/uts/common/io/atge/atge_l1c.c
540
while (reg++ <= &smb.rx_pkts_filtered) {
usr/src/uts/common/io/atge/atge_l1c.c
549
reg = &smb.tx_frames;
usr/src/uts/common/io/atge/atge_l1c.c
550
while (reg++ <= &smb.tx_mcast_bytes) {
usr/src/uts/common/io/atge/atge_l1c.c
665
uint32_t reg;
usr/src/uts/common/io/atge/atge_l1c.c
670
reg = INL(atgep, ATGE_MAC_CFG);
usr/src/uts/common/io/atge/atge_l1c.c
671
if ((reg & ATGE_CFG_TX_ENB) != 0) {
usr/src/uts/common/io/atge/atge_l1c.c
672
reg &= ~ATGE_CFG_TX_ENB;
usr/src/uts/common/io/atge/atge_l1c.c
673
OUTL(atgep, ATGE_MAC_CFG, reg);
usr/src/uts/common/io/atge/atge_l1c.c
677
reg = INL(atgep, ATGE_DMA_CFG);
usr/src/uts/common/io/atge/atge_l1c.c
678
if ((reg & DMA_CFG_RD_ENB) != 0) {
usr/src/uts/common/io/atge/atge_l1c.c
679
reg &= ~DMA_CFG_RD_ENB;
usr/src/uts/common/io/atge/atge_l1c.c
680
OUTL(atgep, ATGE_DMA_CFG, reg);
usr/src/uts/common/io/atge/atge_l1c.c
700
uint32_t reg;
usr/src/uts/common/io/atge/atge_l1c.c
705
reg = INL(atgep, ATGE_MAC_CFG);
usr/src/uts/common/io/atge/atge_l1c.c
706
if ((reg & ATGE_CFG_RX_ENB) != 0) {
usr/src/uts/common/io/atge/atge_l1c.c
707
reg &= ~ATGE_CFG_RX_ENB;
usr/src/uts/common/io/atge/atge_l1c.c
708
OUTL(atgep, ATGE_MAC_CFG, reg);
usr/src/uts/common/io/atge/atge_l1c.c
712
reg = INL(atgep, ATGE_DMA_CFG);
usr/src/uts/common/io/atge/atge_l1c.c
713
if ((reg & DMA_CFG_WR_ENB) != 0) {
usr/src/uts/common/io/atge/atge_l1c.c
714
reg &= ~DMA_CFG_WR_ENB;
usr/src/uts/common/io/atge/atge_l1c.c
715
OUTL(atgep, ATGE_DMA_CFG, reg);
usr/src/uts/common/io/atge/atge_l1e.c
340
uint32_t reg;
usr/src/uts/common/io/atge/atge_l1e.c
401
reg = ATGE_USECS(ATGE_IM_RX_TIMER_DEFAULT) << IM_TIMER_RX_SHIFT;
usr/src/uts/common/io/atge/atge_l1e.c
402
reg |= ATGE_USECS(ATGE_IM_TX_TIMER_DEFAULT) << IM_TIMER_TX_SHIFT;
usr/src/uts/common/io/atge/atge_l1e.c
403
OUTL(atgep, ATGE_IM_TIMER, reg);
usr/src/uts/common/io/atge/atge_l1e.c
405
reg = INL(atgep, ATGE_MASTER_CFG);
usr/src/uts/common/io/atge/atge_l1e.c
406
reg &= ~(L1E_MASTER_CHIP_REV_MASK | L1E_MASTER_CHIP_ID_MASK);
usr/src/uts/common/io/atge/atge_l1e.c
407
reg &= ~(L1E_MASTER_IM_RX_TIMER_ENB | L1E_MASTER_IM_TX_TIMER_ENB);
usr/src/uts/common/io/atge/atge_l1e.c
408
reg |= L1E_MASTER_IM_RX_TIMER_ENB;
usr/src/uts/common/io/atge/atge_l1e.c
409
reg |= L1E_MASTER_IM_TX_TIMER_ENB;
usr/src/uts/common/io/atge/atge_l1e.c
410
OUTL(atgep, ATGE_MASTER_CFG, reg);
usr/src/uts/common/io/atge/atge_l1e.c
670
uint32_t *reg;
usr/src/uts/common/io/atge/atge_l1e.c
677
reg = &smb.rx_frames;
usr/src/uts/common/io/atge/atge_l1e.c
678
while (reg++ <= &smb.rx_pkts_filtered) {
usr/src/uts/common/io/atge/atge_l1e.c
687
reg = &smb.tx_frames;
usr/src/uts/common/io/atge/atge_l1e.c
688
while (reg++ <= &smb.tx_mcast_bytes) {
usr/src/uts/common/io/atge/atge_l1e.c
700
uint32_t *reg;
usr/src/uts/common/io/atge/atge_l1e.c
712
reg = &smb->rx_frames;
usr/src/uts/common/io/atge/atge_l1e.c
713
while (reg++ <= &smb->rx_pkts_filtered) {
usr/src/uts/common/io/atge/atge_l1e.c
714
*reg = INL(atgep, L1E_RX_MIB_BASE + i);
usr/src/uts/common/io/atge/atge_l1e.c
720
reg = &smb->tx_frames;
usr/src/uts/common/io/atge/atge_l1e.c
721
while (reg++ <= &smb->tx_mcast_bytes) {
usr/src/uts/common/io/atge/atge_l1e.c
722
*reg = INL(atgep, L1E_TX_MIB_BASE + i);
usr/src/uts/common/io/atge/atge_l1e.c
827
uint32_t reg;
usr/src/uts/common/io/atge/atge_l1e.c
829
reg = INL(atgep, ATGE_MAC_CFG);
usr/src/uts/common/io/atge/atge_l1e.c
830
ATGE_DB(("%s: %s() reg : %x", atgep->atge_name, __func__, reg));
usr/src/uts/common/io/atge/atge_l1e.c
832
if ((reg & (ATGE_CFG_TX_ENB | ATGE_CFG_RX_ENB)) != 0) {
usr/src/uts/common/io/atge/atge_l1e.c
833
reg &= ~ATGE_CFG_TX_ENB | ATGE_CFG_RX_ENB;
usr/src/uts/common/io/atge/atge_l1e.c
834
OUTL(atgep, ATGE_MAC_CFG, reg);
usr/src/uts/common/io/atge/atge_main.c
2049
uint32_t reg;
usr/src/uts/common/io/atge/atge_main.c
2150
reg = atgep->atge_max_frame_size;
usr/src/uts/common/io/atge/atge_main.c
2152
reg = (atgep->atge_max_frame_size * 2) / 3;
usr/src/uts/common/io/atge/atge_main.c
2154
reg = atgep->atge_max_frame_size / 2;
usr/src/uts/common/io/atge/atge_main.c
2157
ROUNDUP(reg, TX_JUMBO_THRESH_UNIT) >>
usr/src/uts/common/io/atge/atge_main.c
2187
reg = INL(atgep, 0x1008);
usr/src/uts/common/io/atge/atge_main.c
2188
OUTL(atgep, 0x1008, reg | 0x8000);
usr/src/uts/common/io/atge/atge_main.c
2200
reg = INL(atgep, L1E_SRAM_RX_FIFO_LEN);
usr/src/uts/common/io/atge/atge_main.c
2201
rxf_hi = (reg * 4) / 5;
usr/src/uts/common/io/atge/atge_main.c
2202
rxf_lo = reg/ 5;
usr/src/uts/common/io/atge/atge_main.c
2222
reg = INL(atgep, L1_SRAM_RX_FIFO_LEN);
usr/src/uts/common/io/atge/atge_main.c
2223
rxf_lo = reg / 16;
usr/src/uts/common/io/atge/atge_main.c
2226
rxf_hi = (reg * 7) / 8;
usr/src/uts/common/io/atge/atge_main.c
2229
reg = INL(atgep, L1_SRAM_RRD_LEN);
usr/src/uts/common/io/atge/atge_main.c
2230
rrd_lo = reg / 8;
usr/src/uts/common/io/atge/atge_main.c
2231
rrd_hi = (reg * 7) / 8;
usr/src/uts/common/io/atge/atge_main.c
2267
reg = INL(atgep, L1C_SRAM_RX_FIFO_LEN);
usr/src/uts/common/io/atge/atge_main.c
2268
rxf_hi = (reg * 8) / 10;
usr/src/uts/common/io/atge/atge_main.c
2269
rxf_lo = (reg * 3) / 10;
usr/src/uts/common/io/atge/atge_main.c
2284
reg = RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB |
usr/src/uts/common/io/atge/atge_main.c
2286
OUTL(atgep, ATGE_RXQ_CFG, reg);
usr/src/uts/common/io/atge/atge_main.c
2290
reg = (128 <<
usr/src/uts/common/io/atge/atge_main.c
2294
reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
usr/src/uts/common/io/atge/atge_main.c
2297
reg |= TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB;
usr/src/uts/common/io/atge/atge_main.c
2299
OUTL(atgep, ATGE_TXQ_CFG, reg);
usr/src/uts/common/io/atge/atge_main.c
2328
reg =
usr/src/uts/common/io/atge/atge_main.c
2338
OUTL(atgep, ATGE_RXQ_CFG, reg);
usr/src/uts/common/io/atge/atge_main.c
2342
reg =
usr/src/uts/common/io/atge/atge_main.c
2352
OUTL(atgep, ATGE_TXQ_CFG, reg);
usr/src/uts/common/io/atge/atge_main.c
2390
reg =
usr/src/uts/common/io/atge/atge_main.c
2394
reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M;
usr/src/uts/common/io/atge/atge_main.c
2395
OUTL(atgep, ATGE_RXQ_CFG, reg);
usr/src/uts/common/io/atge/atge_main.c
2399
reg = (128 <<
usr/src/uts/common/io/atge/atge_main.c
2406
reg >>= 1;
usr/src/uts/common/io/atge/atge_main.c
2410
reg |= (L1C_TXQ_CFG_TPD_BURST_DEFAULT <<
usr/src/uts/common/io/atge/atge_main.c
2413
reg |= TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB;
usr/src/uts/common/io/atge/atge_main.c
2415
OUTL(atgep, L1C_TXQ_CFG, reg);
usr/src/uts/common/io/atge/atge_main.c
2449
reg = (ATGE_CFG_TX_CRC_ENB | ATGE_CFG_TX_AUTO_PAD |
usr/src/uts/common/io/atge/atge_main.c
2466
reg |= ATGE_CFG_HASH_ALG_CRC32 | ATGE_CFG_SPEED_MODE_SW;
usr/src/uts/common/io/atge/atge_main.c
2471
reg |= ATGE_CFG_SPEED_10_100;
usr/src/uts/common/io/atge/atge_main.c
2474
reg |= ATGE_CFG_SPEED_1000;
usr/src/uts/common/io/atge/atge_main.c
2479
reg |= L1C_CFG_SINGLE_PAUSE_ENB;
usr/src/uts/common/io/atge/atge_main.c
2483
OUTL(atgep, ATGE_MAC_CFG, reg);
usr/src/uts/common/io/atge/atge_main.c
2586
uint32_t reg;
usr/src/uts/common/io/atge/atge_main.c
2623
reg = INL(atgep, ATGE_TXQ_CFG);
usr/src/uts/common/io/atge/atge_main.c
2624
reg = reg & ~TXQ_CFG_ENB;
usr/src/uts/common/io/atge/atge_main.c
2625
OUTL(atgep, ATGE_TXQ_CFG, reg);
usr/src/uts/common/io/atge/atge_main.c
2627
reg = INL(atgep, ATGE_RXQ_CFG);
usr/src/uts/common/io/atge/atge_main.c
2628
reg = reg & ~RXQ_CFG_ENB;
usr/src/uts/common/io/atge/atge_main.c
2629
OUTL(atgep, ATGE_RXQ_CFG, reg);
usr/src/uts/common/io/atge/atge_main.c
2631
reg = INL(atgep, ATGE_DMA_CFG);
usr/src/uts/common/io/atge/atge_main.c
2632
reg = reg & ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB);
usr/src/uts/common/io/atge/atge_main.c
2633
OUTL(atgep, ATGE_DMA_CFG, reg);
usr/src/uts/common/io/atge/atge_main.c
2644
reg = INL(atgep, ATGE_DMA_CFG);
usr/src/uts/common/io/atge/atge_main.c
2645
reg &= ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB);
usr/src/uts/common/io/atge/atge_main.c
2646
OUTL(atgep, ATGE_DMA_CFG, reg);
usr/src/uts/common/io/atge/atge_main.c
2651
reg = INL(atgep, ATGE_TXQ_CFG);
usr/src/uts/common/io/atge/atge_main.c
2652
reg = reg & ~TXQ_CFG_ENB;
usr/src/uts/common/io/atge/atge_main.c
2653
OUTL(atgep, ATGE_TXQ_CFG, reg);
usr/src/uts/common/io/atge/atge_main.c
2655
reg = INL(atgep, ATGE_RXQ_CFG);
usr/src/uts/common/io/atge/atge_main.c
2656
reg = reg & ~RXQ_CFG_ENB;
usr/src/uts/common/io/atge/atge_main.c
2657
OUTL(atgep, ATGE_RXQ_CFG, reg);
usr/src/uts/common/io/atge/atge_main.c
2664
reg = INL(atgep, ATGE_DMA_CFG);
usr/src/uts/common/io/atge/atge_main.c
2665
reg &= ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB);
usr/src/uts/common/io/atge/atge_main.c
2666
OUTL(atgep, ATGE_DMA_CFG, reg);
usr/src/uts/common/io/atge/atge_main.c
2671
reg = INL(atgep, L1C_TXQ_CFG);
usr/src/uts/common/io/atge/atge_main.c
2672
reg = reg & ~TXQ_CFG_ENB;
usr/src/uts/common/io/atge/atge_main.c
2673
OUTL(atgep, L1C_TXQ_CFG, reg);
usr/src/uts/common/io/atge/atge_main.c
2675
reg = INL(atgep, ATGE_RXQ_CFG);
usr/src/uts/common/io/atge/atge_main.c
2676
reg = reg & ~RXQ_CFG_ENB;
usr/src/uts/common/io/atge/atge_main.c
2677
OUTL(atgep, ATGE_RXQ_CFG, reg);
usr/src/uts/common/io/atge/atge_main.c
2682
if ((reg = INL(atgep, ATGE_IDLE_STATUS)) == 0)
usr/src/uts/common/io/atge/atge_main.c
429
uint32_t reg;
usr/src/uts/common/io/atge/atge_main.c
434
reg = INL(atgep, ATGE_MAC_CFG);
usr/src/uts/common/io/atge/atge_main.c
435
reg &= ~(ATGE_CFG_FULL_DUPLEX | ATGE_CFG_TX_FC | ATGE_CFG_RX_FC |
usr/src/uts/common/io/atge/atge_main.c
444
reg |= ATGE_CFG_HASH_ALG_CRC32 | ATGE_CFG_SPEED_MODE_SW;
usr/src/uts/common/io/atge/atge_main.c
454
reg |= ATGE_CFG_SPEED_10_100;
usr/src/uts/common/io/atge/atge_main.c
457
reg |= ATGE_CFG_SPEED_1000;
usr/src/uts/common/io/atge/atge_main.c
463
reg |= ATGE_CFG_FULL_DUPLEX;
usr/src/uts/common/io/atge/atge_main.c
468
reg |= ATGE_CFG_TX_ENB | ATGE_CFG_RX_ENB | ATGE_CFG_RX_FC;
usr/src/uts/common/io/atge/atge_main.c
472
reg |= ATGE_CFG_TX_ENB | ATGE_CFG_RX_ENB;
usr/src/uts/common/io/atge/atge_main.c
476
OUTL(atgep, ATGE_MAC_CFG, reg);
usr/src/uts/common/io/atge/atge_main.c
480
reg = ATGE_USECS(ATGE_IM_RX_TIMER_DEFAULT) << IM_TIMER_RX_SHIFT;
usr/src/uts/common/io/atge/atge_main.c
481
reg |= ATGE_USECS(ATGE_IM_TX_TIMER_DEFAULT) <<
usr/src/uts/common/io/atge/atge_main.c
483
OUTL(atgep, ATGE_IM_TIMER, reg);
usr/src/uts/common/io/atge/atge_main.c
489
reg = ATGE_USECS(atgep->atge_int_rx_mod) << IM_TIMER_RX_SHIFT;
usr/src/uts/common/io/atge/atge_main.c
490
reg |= ATGE_USECS(atgep->atge_int_tx_mod) << IM_TIMER_TX_SHIFT;
usr/src/uts/common/io/atge/atge_main.c
491
OUTL(atgep, ATGE_IM_TIMER, reg);
usr/src/uts/common/io/atge/atge_main.c
496
reg = 0;
usr/src/uts/common/io/atge/atge_main.c
498
reg |= MASTER_IM_RX_TIMER_ENB;
usr/src/uts/common/io/atge/atge_main.c
500
reg |= MASTER_IM_TX_TIMER_ENB;
usr/src/uts/common/io/atge/atge_main.c
501
OUTL(atgep, ATGE_MASTER_CFG, reg);
usr/src/uts/common/io/atge/atge_main.c
898
uint32_t reg;
usr/src/uts/common/io/atge/atge_main.c
900
reg = INL(atgep, ATGE_SPI_CTRL);
usr/src/uts/common/io/atge/atge_main.c
901
if ((reg & SPI_VPD_ENB) != 0) {
usr/src/uts/common/io/atge/atge_main.c
905
reg &= ~SPI_VPD_ENB;
usr/src/uts/common/io/atge/atge_main.c
906
OUTL(atgep, ATGE_SPI_CTRL, reg);
usr/src/uts/common/io/atge/atge_main.c
950
uint32_t reg;
usr/src/uts/common/io/atge/atge_main.c
960
reg = INL(atgep, ATGE_MASTER_CFG);
usr/src/uts/common/io/atge/atge_main.c
963
reg = INL(atgep, ATGE_MASTER_CFG);
usr/src/uts/common/io/atge/atge_main.c
964
if ((reg & MASTER_RESET) == 0)
usr/src/uts/common/io/atge/atge_main.c
970
reg);
usr/src/uts/common/io/atge/atge_main.c
974
if ((reg = INL(atgep, ATGE_IDLE_STATUS)) == 0)
usr/src/uts/common/io/atge/atge_main.c
982
reg);
usr/src/uts/common/io/atge/atge_main.c
993
reg = INL(atgep, 0x1008) | 0x8000;
usr/src/uts/common/io/atge/atge_main.c
994
OUTL(atgep, 0x1008, reg);
usr/src/uts/common/io/atge/atge_mii.c
107
atge_mii_write(void *arg, uint8_t phy, uint8_t reg, uint16_t val)
usr/src/uts/common/io/atge/atge_mii.c
117
MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
usr/src/uts/common/io/atge/atge_mii.c
130
" val :%d", phy, reg, val);
usr/src/uts/common/io/atge/atge_mii.c
187
uint16_t reg, pn;
usr/src/uts/common/io/atge/atge_mii.c
207
reg = atge_mii_read(atgep, phyaddr, ATPHY_CDTC);
usr/src/uts/common/io/atge/atge_mii.c
209
if ((reg & PHY_CDTC_ENB) == 0)
usr/src/uts/common/io/atge/atge_mii.c
215
reg = atge_mii_read(atgep, phyaddr, ATPHY_CDTS);
usr/src/uts/common/io/atge/atge_mii.c
217
if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) {
usr/src/uts/common/io/atge/atge_mii.c
231
reg = atge_mii_read(atgep, phyaddr, ATPHY_DBG_DATA);
usr/src/uts/common/io/atge/atge_mii.c
232
atge_mii_write(atgep, phyaddr, ATPHY_DBG_DATA, reg | 0x03);
usr/src/uts/common/io/atge/atge_mii.c
272
uint16_t reg;
usr/src/uts/common/io/atge/atge_mii.c
276
reg = atge_mii_read(atgep, phyaddr, ATPHY_DBG_DATA);
usr/src/uts/common/io/atge/atge_mii.c
277
atge_mii_write(atgep, phyaddr, ATPHY_DBG_DATA, reg & 0xDFFF);
usr/src/uts/common/io/atge/atge_mii.c
283
reg = atge_mii_read(atgep, phyaddr, ATPHY_DBG_DATA);
usr/src/uts/common/io/atge/atge_mii.c
284
atge_mii_write(atgep, phyaddr, ATPHY_DBG_DATA, reg & 0xFFF7);
usr/src/uts/common/io/atge/atge_mii.c
350
atge_l1c_mii_read(void *arg, uint8_t phy, uint8_t reg)
usr/src/uts/common/io/atge/atge_mii.c
358
return (atge_mii_read(arg, phy, reg));
usr/src/uts/common/io/atge/atge_mii.c
362
atge_l1c_mii_write(void *arg, uint8_t phy, uint8_t reg, uint16_t val)
usr/src/uts/common/io/atge/atge_mii.c
370
if (reg == MII_CONTROL) {
usr/src/uts/common/io/atge/atge_mii.c
378
atge_mii_write(arg, phy, reg, val | MII_CONTROL_RESET);
usr/src/uts/common/io/atge/atge_mii.c
381
atge_mii_write(arg, phy, reg, val);
usr/src/uts/common/io/atge/atge_mii.c
64
atge_mii_read(void *arg, uint8_t phy, uint8_t reg)
usr/src/uts/common/io/atge/atge_mii.c
73
MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
usr/src/uts/common/io/atge/atge_mii.c
86
phy, reg);
usr/src/uts/common/io/atge/atge_mii.c
97
if (reg == MII_STATUS)
usr/src/uts/common/io/atge/atge_mii.c
99
else if (reg == MII_EXTSTATUS)
usr/src/uts/common/io/audio/ac97/ac97.c
312
ac_probe_reg(ac97_t *ac, uint8_t reg)
usr/src/uts/common/io/audio/ac97/ac97.c
318
val = RD(reg);
usr/src/uts/common/io/audio/ac97/ac97.c
319
WR(reg, 0xffff);
usr/src/uts/common/io/audio/ac97/ac97.c
320
if (RD(reg) != 0) {
usr/src/uts/common/io/audio/ac97/ac97.c
324
WR(reg, val);
usr/src/uts/common/io/audio/ac97/ac97.c
65
#define SHADOW(ac, reg) ((ac)->shadow[((reg) / sizeof (uint16_t))])
usr/src/uts/common/io/audio/ac97/ac97.c
651
ac_wr(ac97_t *ac, uint8_t reg, uint16_t val)
usr/src/uts/common/io/audio/ac97/ac97.c
653
if ((reg < LAST_SHADOW_REG) && (reg > 0)) {
usr/src/uts/common/io/audio/ac97/ac97.c
654
SHADOW(ac, reg) = val;
usr/src/uts/common/io/audio/ac97/ac97.c
657
ac->wr(ac->private, reg, val);
usr/src/uts/common/io/audio/ac97/ac97.c
667
ac_rd(ac97_t *ac, uint8_t reg)
usr/src/uts/common/io/audio/ac97/ac97.c
669
if ((reg < LAST_SHADOW_REG) && (reg > 0)) {
usr/src/uts/common/io/audio/ac97/ac97.c
670
return (SHADOW(ac, reg));
usr/src/uts/common/io/audio/ac97/ac97.c
672
return (ac->rd(ac->private, reg));
usr/src/uts/common/io/audio/ac97/ac97.c
680
ac_set(ac97_t *ac, uint8_t reg, uint16_t val)
usr/src/uts/common/io/audio/ac97/ac97.c
682
ac_wr(ac, reg, ac->rd(ac->private, reg) | val);
usr/src/uts/common/io/audio/ac97/ac97.c
690
ac_clr(ac97_t *ac, uint8_t reg, uint16_t val)
usr/src/uts/common/io/audio/ac97/ac97.c
692
ac_wr(ac, reg, ac->rd(ac->private, reg) & ~val);
usr/src/uts/common/io/audio/ac97/ac97.c
827
ac_stereo_set(ac97_ctrl_t *ctrl, uint64_t value, uint8_t reg)
usr/src/uts/common/io/audio/ac97/ac97.c
837
ac_wr(ac, reg, ac_val_scale(left, right, ctrl->actrl_bits) | mute);
usr/src/uts/common/io/audio/ac97/ac97.c
841
ac_mono_set(ac97_ctrl_t *ctrl, uint64_t value, uint8_t reg, int shift)
usr/src/uts/common/io/audio/ac97/ac97.c
854
v = SHADOW(ac, reg);
usr/src/uts/common/io/audio/ac97/ac97.c
861
ac_wr(ac, reg, v);
usr/src/uts/common/io/audio/drv/audio1575/audio1575.c
1331
audio1575_write_ac97(void *arg, uint8_t reg, uint16_t data)
usr/src/uts/common/io/audio/drv/audio1575/audio1575.c
1344
PUT16(M1575_CPR_REG+2, reg);
usr/src/uts/common/io/audio/drv/audio1575/audio1575.c
1356
(void) audio1575_read_ac97(statep, reg);
usr/src/uts/common/io/audio/drv/audio1575/audio1575.c
1375
audio1575_read_ac97(void *arg, uint8_t reg)
usr/src/uts/common/io/audio/drv/audio1575/audio1575.c
1392
addr = (reg | M1575_CPR_READ);
usr/src/uts/common/io/audio/drv/audio1575/audio1575.c
1410
if (addr != reg) {
usr/src/uts/common/io/audio/drv/audio1575/audio1575.h
395
#define GET8(reg) \
usr/src/uts/common/io/audio/drv/audio1575/audio1575.h
396
ddi_get8(statep->regsh, (void *)(statep->regsp + (reg)))
usr/src/uts/common/io/audio/drv/audio1575/audio1575.h
398
#define GET16(reg) \
usr/src/uts/common/io/audio/drv/audio1575/audio1575.h
399
ddi_get16(statep->regsh, (void *)(statep->regsp + (reg)))
usr/src/uts/common/io/audio/drv/audio1575/audio1575.h
401
#define GET32(reg) \
usr/src/uts/common/io/audio/drv/audio1575/audio1575.h
402
ddi_get32(statep->regsh, (void *)(statep->regsp + (reg)))
usr/src/uts/common/io/audio/drv/audio1575/audio1575.h
404
#define PUT8(reg, val) \
usr/src/uts/common/io/audio/drv/audio1575/audio1575.h
405
ddi_put8(statep->regsh, (void *)(statep->regsp + (reg)), (val))
usr/src/uts/common/io/audio/drv/audio1575/audio1575.h
407
#define PUT16(reg, val) \
usr/src/uts/common/io/audio/drv/audio1575/audio1575.h
408
ddi_put16(statep->regsh, (void *)(statep->regsp + (reg)), (val))
usr/src/uts/common/io/audio/drv/audio1575/audio1575.h
410
#define PUT32(reg, val) \
usr/src/uts/common/io/audio/drv/audio1575/audio1575.h
411
ddi_put32(statep->regsh, (void *)(statep->regsp + (reg)), (val))
usr/src/uts/common/io/audio/drv/audio1575/audio1575.h
413
#define SET8(reg, bit) PUT8(reg, GET8(reg) | (bit))
usr/src/uts/common/io/audio/drv/audio1575/audio1575.h
414
#define SET16(reg, bit) PUT16(reg, GET16(reg) | (bit))
usr/src/uts/common/io/audio/drv/audio1575/audio1575.h
415
#define SET32(reg, bit) PUT32(reg, GET32(reg) | (bit))
usr/src/uts/common/io/audio/drv/audio1575/audio1575.h
416
#define CLR8(reg, bit) PUT8(reg, GET8(reg) & ~(bit))
usr/src/uts/common/io/audio/drv/audio1575/audio1575.h
417
#define CLR16(reg, bit) PUT16(reg, GET16(reg) & ~(bit))
usr/src/uts/common/io/audio/drv/audio1575/audio1575.h
418
#define CLR32(reg, bit) PUT32(reg, GET32(reg) & ~(bit))
usr/src/uts/common/io/audio/drv/audio810/audio810.c
1610
audio810_write_ac97(void *arg, uint8_t reg, uint16_t data)
usr/src/uts/common/io/audio/drv/audio810/audio810.c
1615
I810_AM_PUT16(reg, data);
usr/src/uts/common/io/audio/drv/audio810/audio810.c
1618
(void) audio810_read_ac97(statep, reg);
usr/src/uts/common/io/audio/drv/audio810/audio810.c
1635
audio810_read_ac97(void *arg, uint8_t reg)
usr/src/uts/common/io/audio/drv/audio810/audio810.c
1641
val = I810_AM_GET16(reg);
usr/src/uts/common/io/audio/drv/audio810/audio810.h
219
#define I810_BM_GET8(reg) \
usr/src/uts/common/io/audio/drv/audio810/audio810.h
221
(void *)((char *)statep->bm_regs_base + (reg)))
usr/src/uts/common/io/audio/drv/audio810/audio810.h
223
#define I810_BM_GET16(reg) \
usr/src/uts/common/io/audio/drv/audio810/audio810.h
225
(void *)((char *)statep->bm_regs_base + (reg)))
usr/src/uts/common/io/audio/drv/audio810/audio810.h
227
#define I810_BM_GET32(reg) \
usr/src/uts/common/io/audio/drv/audio810/audio810.h
229
(void *)((char *)statep->bm_regs_base + (reg)))
usr/src/uts/common/io/audio/drv/audio810/audio810.h
231
#define I810_BM_PUT8(reg, val) \
usr/src/uts/common/io/audio/drv/audio810/audio810.h
233
(void *)((char *)statep->bm_regs_base + (reg)), (val))
usr/src/uts/common/io/audio/drv/audio810/audio810.h
235
#define I810_BM_PUT16(reg, val) \
usr/src/uts/common/io/audio/drv/audio810/audio810.h
237
(void *)((char *)statep->bm_regs_base + (reg)), (val))
usr/src/uts/common/io/audio/drv/audio810/audio810.h
239
#define I810_BM_PUT32(reg, val) \
usr/src/uts/common/io/audio/drv/audio810/audio810.h
241
(void *)((char *)statep->bm_regs_base + (reg)), (val))
usr/src/uts/common/io/audio/drv/audio810/audio810.h
243
#define I810_AM_GET16(reg) \
usr/src/uts/common/io/audio/drv/audio810/audio810.h
245
(void *)((char *)statep->am_regs_base + (reg)))
usr/src/uts/common/io/audio/drv/audio810/audio810.h
247
#define I810_AM_PUT16(reg, val) \
usr/src/uts/common/io/audio/drv/audio810/audio810.h
249
(void *)((char *)statep->am_regs_base + (reg)), (val))
usr/src/uts/common/io/audio/drv/audiocmihd/audiocmihd.c
158
cmediahd_read_ac97(void *arg, uint8_t reg)
usr/src/uts/common/io/audio/drv/audiocmihd/audiocmihd.c
166
val |= reg << 16;
usr/src/uts/common/io/audio/drv/audiocmihd/audiocmihd.c
177
cmediahd_write_ac97(void *arg, uint8_t reg, uint16_t data)
usr/src/uts/common/io/audio/drv/audiocmihd/audiocmihd.c
184
val |= reg << 16;
usr/src/uts/common/io/audio/drv/audiocmihd/audiocmihd.c
195
cmediahd_read_fp_ac97(void *arg, uint8_t reg)
usr/src/uts/common/io/audio/drv/audiocmihd/audiocmihd.c
205
val |= reg << 16;
usr/src/uts/common/io/audio/drv/audiocmihd/audiocmihd.c
215
cmediahd_write_fp_ac97(void *arg, uint8_t reg, uint16_t data)
usr/src/uts/common/io/audio/drv/audiocmihd/audiocmihd.c
224
val |= reg << 16;
usr/src/uts/common/io/audio/drv/audiocmihd/audiocmihd.c
233
spi_write(void *arg, int codec_num, unsigned char reg, int val)
usr/src/uts/common/io/audio/drv/audiocmihd/audiocmihd.c
257
tmp |= (reg << shift);
usr/src/uts/common/io/audio/drv/audiocmihd/audiocmihd.c
276
i2c_write(void *arg, unsigned char codec_num, unsigned char reg,
usr/src/uts/common/io/audio/drv/audiocmihd/audiocmihd.c
296
OUTB(devc, reg, TWO_WIRE_MAP);
usr/src/uts/common/io/audio/drv/audiocmihd/audiocmihd.h
354
#define INB(devc, reg) ddi_get8(devc->regsh, (void *)(reg))
usr/src/uts/common/io/audio/drv/audiocmihd/audiocmihd.h
355
#define OUTB(devc, val, reg) ddi_put8(devc->regsh, (void *)(reg), (val))
usr/src/uts/common/io/audio/drv/audiocmihd/audiocmihd.h
357
#define INW(devc, reg) ddi_get16(devc->regsh, (void *)(reg))
usr/src/uts/common/io/audio/drv/audiocmihd/audiocmihd.h
358
#define OUTW(devc, val, reg) ddi_put16(devc->regsh, (void *)(reg), (val))
usr/src/uts/common/io/audio/drv/audiocmihd/audiocmihd.h
360
#define INL(devc, reg) ddi_get32(devc->regsh, (void *)(reg))
usr/src/uts/common/io/audio/drv/audiocmihd/audiocmihd.h
361
#define OUTL(devc, val, reg) ddi_put32(devc->regsh, (void *)(reg), (val))
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.c
1100
unsigned int reg;
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.c
1150
reg = 0;
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.c
1152
reg = AC97SLOT_CENTER | AC97SLOT_LFE | AC97SLOT_REAR_LEFT |
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.c
1155
reg = AC97SLOT_CENTER | AC97SLOT_LFE;
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.c
1158
reg |= 0x40;
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.c
1159
emu10k_write_reg(devc, AC97SLOT, 0, reg);
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.c
1268
reg = INL(devc, devc->regs + 0x18) & ~A_IOCFG_GPOUT0;
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.c
1269
reg |= ((devc->feature_mask & SB_INVSP) ? 0x4 : 0);
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.c
1270
OUTL(devc, reg, devc->regs + 0x18);
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.c
1273
reg = INL(devc, devc->regs + HCFG) & ~HCFG_GPOUT0;
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.c
1274
reg |= ((devc->feature_mask & SB_INVSP) ? HCFG_GPOUT0 : 0);
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.c
1275
OUTL(devc, reg, devc->regs + HCFG);
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.c
217
emu10k_read_reg(emu10k_devc_t *devc, int reg, int chn)
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.c
224
ptr = ((reg << 16) & ptr_addr_mask) | (chn & 0x3f);
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.c
227
if (reg & 0xff000000) {
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.c
228
size = (reg >> 24) & 0x3f;
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.c
229
offset = (reg >> 16) & 0x1f;
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.c
239
emu10k_write_reg(emu10k_devc_t *devc, int reg, int chn, uint32_t value)
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.c
246
ptr = ((reg << 16) & ptr_addr_mask) | (chn & 0x3f);
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.c
248
if (reg & 0xff000000) {
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.c
249
size = (reg >> 24) & 0x3f;
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.c
250
offset = (reg >> 16) & 0x1f;
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.c
283
emu10k_write_efx(emu10k_devc_t *devc, int reg, unsigned int value)
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.c
285
emu10k_write_reg(devc, reg, 0, value);
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.h
436
#define INB(devc, reg) ddi_get8(devc->regsh, (void *)(reg))
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.h
437
#define OUTB(devc, val, reg) ddi_put8(devc->regsh, (void *)(reg), (val))
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.h
439
#define INW(devc, reg) ddi_get16(devc->regsh, (void *)(reg))
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.h
440
#define OUTW(devc, val, reg) ddi_put16(devc->regsh, (void *)(reg), (val))
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.h
442
#define INL(devc, reg) ddi_get32(devc->regsh, (void *)(reg))
usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.h
443
#define OUTL(devc, val, reg) ddi_put32(devc->regsh, (void *)(reg), (val))
usr/src/uts/common/io/audio/drv/audioens/audioens.c
240
SRCRegRead(audioens_dev_t *dev, unsigned short reg)
usr/src/uts/common/io/audio/drv/audioens/audioens.c
253
PUT32(dev, CONC_dSRCIO_OFF, (dtemp & SRC_CTLMASK) | ((int)reg << 25));
usr/src/uts/common/io/audio/drv/audioens/audioens.c
266
SRCRegWrite(audioens_dev_t *dev, unsigned short reg, unsigned short val)
usr/src/uts/common/io/audio/drv/audioens/audioens.c
281
((int)reg << 25) | val;
usr/src/uts/common/io/audio/drv/audiohd/audiohd.h
881
#define AUDIOHD_REG_GET8(reg) \
usr/src/uts/common/io/audio/drv/audiohd/audiohd.h
883
(void *)((char *)statep->hda_reg_base + (reg)))
usr/src/uts/common/io/audio/drv/audiohd/audiohd.h
885
#define AUDIOHD_REG_GET16(reg) \
usr/src/uts/common/io/audio/drv/audiohd/audiohd.h
887
(void *)((char *)statep->hda_reg_base + (reg)))
usr/src/uts/common/io/audio/drv/audiohd/audiohd.h
889
#define AUDIOHD_REG_GET32(reg) \
usr/src/uts/common/io/audio/drv/audiohd/audiohd.h
891
(void *)((char *)statep->hda_reg_base + (reg)))
usr/src/uts/common/io/audio/drv/audiohd/audiohd.h
893
#define AUDIOHD_REG_GET64(reg) \
usr/src/uts/common/io/audio/drv/audiohd/audiohd.h
895
(void *)((char *)statep->hda_reg_base + (reg)))
usr/src/uts/common/io/audio/drv/audiohd/audiohd.h
897
#define AUDIOHD_REG_SET8(reg, val) \
usr/src/uts/common/io/audio/drv/audiohd/audiohd.h
899
(void *)((char *)statep->hda_reg_base + (reg)), (val))
usr/src/uts/common/io/audio/drv/audiohd/audiohd.h
901
#define AUDIOHD_REG_SET16(reg, val) \
usr/src/uts/common/io/audio/drv/audiohd/audiohd.h
903
(void *)((char *)statep->hda_reg_base + (reg)), (val))
usr/src/uts/common/io/audio/drv/audiohd/audiohd.h
905
#define AUDIOHD_REG_SET32(reg, val) \
usr/src/uts/common/io/audio/drv/audiohd/audiohd.h
907
(void *)((char *)statep->hda_reg_base + (reg)), (val))
usr/src/uts/common/io/audio/drv/audiohd/audiohd.h
909
#define AUDIOHD_REG_SET64(reg, val) \
usr/src/uts/common/io/audio/drv/audiohd/audiohd.h
911
(void *)((char *)statep->hda_reg_base + (reg)), (val))
usr/src/uts/common/io/audio/drv/audioixp/audioixp.c
1079
audioixp_rd97(void *arg, uint8_t reg)
usr/src/uts/common/io/audio/drv/audioixp/audioixp.c
1091
((unsigned)reg << IXP_AUDIO_OUT_PHY_ADDR_SHIFT);
usr/src/uts/common/io/audio/drv/audioixp/audioixp.c
1105
audio_dev_warn(statep->adev, "time out reading codec reg %d", reg);
usr/src/uts/common/io/audio/drv/audioixp/audioixp.c
1121
audioixp_wr97(void *arg, uint8_t reg, uint16_t data)
usr/src/uts/common/io/audio/drv/audioixp/audioixp.c
1133
((unsigned)reg << IXP_AUDIO_OUT_PHY_ADDR_SHIFT) |
usr/src/uts/common/io/audio/drv/audioixp/audioixp.c
1137
(void) audioixp_rd97(statep, reg);
usr/src/uts/common/io/audio/drv/audioixp/audioixp.h
263
#define GET32(reg) \
usr/src/uts/common/io/audio/drv/audioixp/audioixp.h
264
ddi_get32(statep->regsh, (void *)(statep->regsp + (reg)))
usr/src/uts/common/io/audio/drv/audioixp/audioixp.h
266
#define PUT32(reg, val) \
usr/src/uts/common/io/audio/drv/audioixp/audioixp.h
267
ddi_put32(statep->regsh, (void *)(statep->regsp + (reg)), (val))
usr/src/uts/common/io/audio/drv/audioixp/audioixp.h
269
#define SET32(reg, val) PUT32(reg, GET32(reg) | ((uint32_t)(val)))
usr/src/uts/common/io/audio/drv/audioixp/audioixp.h
271
#define CLR32(reg, val) PUT32(reg, GET32(reg) & ~((uint32_t)(val)))
usr/src/uts/common/io/audio/drv/audiols/audiols.c
149
read_chan(audigyls_dev_t *dev, int reg, int chn)
usr/src/uts/common/io/audio/drv/audiols/audiols.c
155
OUTL(dev, PR, (reg << 16) | (chn & 0xffff));
usr/src/uts/common/io/audio/drv/audiols/audiols.c
164
write_chan(audigyls_dev_t *dev, int reg, int chn, uint32_t value)
usr/src/uts/common/io/audio/drv/audiols/audiols.c
168
OUTL(dev, PR, (reg << 16) | (chn & 0x7));
usr/src/uts/common/io/audio/drv/audiols/audiols.c
175
read_reg(audigyls_dev_t *dev, int reg)
usr/src/uts/common/io/audio/drv/audiols/audiols.c
177
return (read_chan(dev, reg, 0));
usr/src/uts/common/io/audio/drv/audiols/audiols.c
181
write_reg(audigyls_dev_t *dev, int reg, uint32_t value)
usr/src/uts/common/io/audio/drv/audiols/audiols.c
183
write_chan(dev, reg, 0, value);
usr/src/uts/common/io/audio/drv/audiols/audiols.c
247
audigyls_i2c_write(audigyls_dev_t *dev, int reg, int data)
usr/src/uts/common/io/audio/drv/audiols/audiols.c
251
tmp = (reg << 9 | data) << 16; /* set the upper 16 bits */
usr/src/uts/common/io/audio/drv/audiols/audiols.h
245
#define INB(dev, reg) \
usr/src/uts/common/io/audio/drv/audiols/audiols.h
246
ddi_get8(dev->regsh, (void *)(dev->base + reg))
usr/src/uts/common/io/audio/drv/audiols/audiols.h
247
#define OUTB(dev, reg, val) \
usr/src/uts/common/io/audio/drv/audiols/audiols.h
248
ddi_put8(dev->regsh, (void *)(dev->base + reg), (val))
usr/src/uts/common/io/audio/drv/audiols/audiols.h
250
#define INW(dev, reg) \
usr/src/uts/common/io/audio/drv/audiols/audiols.h
251
ddi_get16(dev->regsh, (void *)(dev->base + reg))
usr/src/uts/common/io/audio/drv/audiols/audiols.h
252
#define OUTW(dev, reg, val) \
usr/src/uts/common/io/audio/drv/audiols/audiols.h
253
ddi_put16(dev->regsh, (void *)(dev->base + reg), (val))
usr/src/uts/common/io/audio/drv/audiols/audiols.h
255
#define INL(dev, reg) \
usr/src/uts/common/io/audio/drv/audiols/audiols.h
256
ddi_get32(dev->regsh, (void *)(dev->base + reg))
usr/src/uts/common/io/audio/drv/audiols/audiols.h
257
#define OUTL(dev, reg, val) \
usr/src/uts/common/io/audio/drv/audiols/audiols.h
258
ddi_put32(dev->regsh, (void *)(dev->base + reg), (val))
usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c
132
read_reg(p16x_dev_t *dev, int reg, int chn)
usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c
137
OUTL(dev, (reg << 16) | (chn & 0xffff), PTR); /* Pointer */
usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c
145
write_reg(p16x_dev_t *dev, int reg, int chn, unsigned int value)
usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c
149
OUTL(dev, (reg << 16) | (chn & 0xffff), PTR); /* Pointer */
usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c
155
set_reg_bits(p16x_dev_t *dev, int reg, int chn, unsigned int mask)
usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c
159
OUTL(dev, (reg << 16) | (chn & 0xffff), PTR); /* Pointer */
usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c
167
clear_reg_bits(p16x_dev_t *dev, int reg, int chn, unsigned int mask)
usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.c
171
OUTL(dev, (reg << 16) | (chn & 0xffff), PTR); /* Pointer */
usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.h
100
ddi_put8(dev->regsh, (void *)((char *)dev->base+(reg)), (val))
usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.h
88
#define INL(dev, reg) \
usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.h
89
ddi_get32(dev->regsh, (void *)((char *)dev->base+(reg)))
usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.h
90
#define INW(dev, reg) \
usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.h
91
ddi_get16(dev->regsh, (void *)((char *)dev->base+(reg)))
usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.h
92
#define INB(dev, reg) \
usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.h
93
ddi_get8(dev->regsh, (void *)((char *)dev->base+(reg)))
usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.h
95
#define OUTL(dev, val, reg) \
usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.h
96
ddi_put32(dev->regsh, (void *)((char *)dev->base+(reg)), (val))
usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.h
97
#define OUTW(dev, val, reg) \
usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.h
98
ddi_put16(dev->regsh, (void *)((char *)dev->base+(reg)), (val))
usr/src/uts/common/io/audio/drv/audiop16x/audiop16x.h
99
#define OUTB(dev, val, reg) \
usr/src/uts/common/io/audio/drv/audiopci/audiopci.c
762
audiopci_mono(audiopci_dev_t *dev, audiopci_ctrl_num_t num, uint8_t reg)
usr/src/uts/common/io/audio/drv/audiopci/audiopci.c
770
audiopci_ak_write(dev, reg, val);
usr/src/uts/common/io/audio/drv/audiopci/audiopci.c
774
audiopci_mono8(audiopci_dev_t *dev, audiopci_ctrl_num_t num, uint8_t reg)
usr/src/uts/common/io/audio/drv/audiopci/audiopci.c
782
audiopci_ak_write(dev, reg, val);
usr/src/uts/common/io/audio/drv/audiosolo/audiosolo.c
310
solo_write(solo_dev_t *dev, uint8_t reg, uint8_t val)
usr/src/uts/common/io/audio/drv/audiosolo/audiosolo.c
312
solo_cmd1(dev, reg, val);
usr/src/uts/common/io/audio/drv/audiosolo/audiosolo.c
316
solo_read(solo_dev_t *dev, uint8_t reg)
usr/src/uts/common/io/audio/drv/audiosolo/audiosolo.c
318
if (solo_cmd(dev, 0xc0) && solo_cmd(dev, reg)) {
usr/src/uts/common/io/audio/drv/audiots/audiots.c
1021
audiots_read_ac97(audiots_state_t *state, int reg)
usr/src/uts/common/io/audio/drv/audiots/audiots.c
1077
ddi_put16(acch, addr, (reg|AP_ACRD_W_PRIMARY_CODEC|
usr/src/uts/common/io/audio/drv/audiots/audiots.c
1155
uint16_t reg = reg8;
usr/src/uts/common/io/audio/drv/audiots/audiots.c
1157
reg &= AP_ACWR_INDEX_MASK;
usr/src/uts/common/io/audio/drv/audiots/audiots.c
1161
reg |= AP_ACWR_W_PRIMARY_CODEC|AP_ACWR_W_WRITE_MIXER_REG;
usr/src/uts/common/io/audio/drv/audiots/audiots.c
1163
reg |= AP_ACWR_W_PRIMARY_CODEC|AP_ACWR_W_WRITE_MIXER_REG|
usr/src/uts/common/io/audio/drv/audiots/audiots.c
1173
ddi_put16(handle, reg_addr, reg);
usr/src/uts/common/io/audio/drv/audiots/audiots.c
740
audiots_get_ac97(void *arg, uint8_t reg)
usr/src/uts/common/io/audio/drv/audiots/audiots.c
757
reg &= AP_ACRD_INDEX_MASK;
usr/src/uts/common/io/audio/drv/audiots/audiots.c
759
if ((first = audiots_read_ac97(state, reg)) != 0) {
usr/src/uts/common/io/audio/drv/audiots/audiots.c
769
if ((next = audiots_read_ac97(state, reg)) != 0) {
usr/src/uts/common/io/audio/drv/audiovia823x/audiovia823x.h
170
#define INL(devc, reg) ddi_get32(devc->regsh, (void *)(reg))
usr/src/uts/common/io/audio/drv/audiovia823x/audiovia823x.h
172
#define INB(devc, reg) ddi_get8(devc->regsh, (void *)(reg))
usr/src/uts/common/io/audio/drv/audiovia823x/audiovia823x.h
174
#define OUTL(devc, reg, val) ddi_put32(devc->regsh, (void *)(reg), (val))
usr/src/uts/common/io/audio/drv/audiovia823x/audiovia823x.h
176
#define OUTB(devc, reg, val) ddi_put8(devc->regsh, (void *)(reg), (val))
usr/src/uts/common/io/axf/axf_usbgem.c
409
uint16_t reg;
usr/src/uts/common/io/bfe/bfe.c
311
bfe_wait_bit(bfe_t *bfe, uint32_t reg, uint32_t bit,
usr/src/uts/common/io/bfe/bfe.c
318
v = INL(bfe, reg);
usr/src/uts/common/io/bfe/bfe.c
340
bfe_read_phy(bfe_t *bfe, uint32_t reg)
usr/src/uts/common/io/bfe/bfe.c
346
(reg << BFE_MDIO_RA_SHIFT) |
usr/src/uts/common/io/bfe/bfe.c
355
bfe_write_phy(bfe_t *bfe, uint32_t reg, uint32_t val)
usr/src/uts/common/io/bfe/bfe.c
361
(reg << BFE_MDIO_RA_SHIFT) |
usr/src/uts/common/io/bfe/bfe.h
83
#define FLUSH(bfe, reg) \
usr/src/uts/common/io/bfe/bfe.h
84
(void) INL(bfe, reg)
usr/src/uts/common/io/bfe/bfe.h
86
#define OUTL_OR(bfe, reg, v) \
usr/src/uts/common/io/bfe/bfe.h
87
OUTL(bfe, reg, (INL(bfe, reg) | v))
usr/src/uts/common/io/bfe/bfe.h
89
#define OUTL_AND(bfe, reg, v) \
usr/src/uts/common/io/bfe/bfe.h
90
OUTL(bfe, reg, (INL(bfe, reg) & v))
usr/src/uts/common/io/bge/bge_chip2.c
3464
void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits);
usr/src/uts/common/io/bge/bge_chip2.c
4212
uint32_t reg;
usr/src/uts/common/io/bge/bge_chip2.c
4278
reg = (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5762)
usr/src/uts/common/io/bge/bge_chip2.c
4280
regval = bge_reg_get32(bgep, reg);
usr/src/uts/common/io/bge/bge_chip2.c
4292
bge_reg_put32(bgep, reg,
usr/src/uts/common/io/bge/bge_chip2.c
4298
reg = (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5762)
usr/src/uts/common/io/bge/bge_chip2.c
4300
regval = bge_reg_get32(bgep, reg);
usr/src/uts/common/io/bge/bge_chip2.c
4301
bge_reg_put32(bgep, reg, (regval |
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
112
u32_t reg,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
132
(reg << 16) |
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
39
u32_t reg,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
59
(reg << 16) |
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
2249
u32_t reg;
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
2254
reg = 0xffffffff;
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
2258
reg ^= buf[j];
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
2262
tmp = reg & 0x01;
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
2264
reg >>= 1;
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
2268
reg ^= 0xedb88320;
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
2273
return ~reg;
usr/src/uts/common/io/bnx/bnxhwi.c
312
u32_t reg;
usr/src/uts/common/io/bnx/bnxhwi.c
317
reg = 0xffffffff;
usr/src/uts/common/io/bnx/bnxhwi.c
320
reg ^= buf[j];
usr/src/uts/common/io/bnx/bnxhwi.c
323
tmp = reg & 0x01;
usr/src/uts/common/io/bnx/bnxhwi.c
325
reg >>= 1;
usr/src/uts/common/io/bnx/bnxhwi.c
328
reg ^= 0xedb88320;
usr/src/uts/common/io/bnx/bnxhwi.c
333
return (~reg);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
10641
reg_set[i].reg, reg_set[i].val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
10713
elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2865
u16 reg, u16 val)
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2876
tmp = ((phy->addr << 21) | (reg << 16) | val |
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2900
u16 reg, u16 *ret_val)
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2912
val = ((phy->addr << 21) | (reg << 16) |
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2943
u8 devad, u16 reg, u16 *ret_val)
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2961
val = ((phy->addr << 21) | (devad << 16) | reg |
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3022
u8 devad, u16 reg, u16 val)
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3041
tmp = ((phy->addr << 21) | (devad << 16) | reg |
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3458
u8 devad, u16 reg, u16 or_val)
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
346
static u32 elink_bits_en(struct elink_dev *cb, u32 reg, u32 bits)
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3461
elink_cl45_read(cb, phy, devad, reg, &val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3462
elink_cl45_write(cb, phy, devad, reg, val | or_val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3467
u8 devad, u16 reg, u16 and_val)
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3470
elink_cl45_read(cb, phy, devad, reg, &val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3471
elink_cl45_write(cb, phy, devad, reg, val & and_val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3477
u8 devad, u16 reg, u16 *ret_val)
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
348
u32 val = REG_RD(cb, reg);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3487
reg, ret_val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3494
u8 devad, u16 reg, u16 val)
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3504
reg, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
351
REG_WR(cb, reg, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
355
static u32 elink_bits_dis(struct elink_dev *cb, u32 reg, u32 bits)
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
357
u32 val = REG_RD(cb, reg);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
360
REG_WR(cb, reg, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3960
elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3995
elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
4049
elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
4202
elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
4608
elink_cl45_write(cb, phy, wc_regs[i].devad, wc_regs[i].reg,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
67
#define REG_RD(cb, reg) elink_cb_reg_read(cb, reg)
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
68
#define REG_WR(cb, reg, val) elink_cb_reg_write(cb, reg, val)
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
69
#define EMAC_RD(cb, reg) REG_RD(cb, emac_base + reg)
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
70
#define EMAC_WR(cb, reg, val) REG_WR(cb, emac_base + reg, val)
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
9882
u16 reg;
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
9884
reg = MDIO_XS_8706_REG_BANK_RX0 +
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
9887
elink_cl45_read(cb, phy, MDIO_XS_DEVAD, reg, &val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
9893
" reg 0x%x <-- val 0x%x\n", reg, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
9894
elink_cl45_write(cb, phy, MDIO_XS_DEVAD, reg, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
206
static void ecore_wr_64(struct _lm_device_t *pdev, u32 reg, u32 val_lo,
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
213
REG_WR_DMAE_LEN(pdev, reg, wb_write, 2);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
702
u32 reg;
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
705
reg = PXP2_REG_RQ_ONCHIP_AT + abs_idx*8;
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
707
reg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx*8;
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
709
ecore_wr_64(pdev, reg, ILT_ADDR1(page_mapping.as_u64), ILT_ADDR2(page_mapping.as_u64));
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
898
u32 base_reg, u32 reg)
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
905
ecore_init_wr_wb(pdev, reg + i*8,
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_mcp.c
1103
u32_t reg = 0 ;
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_mcp.c
1106
reg = REG_RD(pdev, offset);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_mcp.c
1110
if( REG_RD(pdev, offset) != reg )
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_mcp.c
1115
return reg; // mcp is hang on this value as program counter!
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_phy.c
240
u32_t reg,
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_phy.c
263
tmp = (pdev->vars.phy_addr << 21) | (reg << 16) | (val & EMAC_MDIO_COMM_DATA) |
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_phy.c
314
u32_t reg,
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_phy.c
337
val = (pdev->vars.phy_addr << 21) | (reg << 16) |
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_phy.c
392
u16_t reg, // offset
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_phy.c
401
rc = elink_phy_read(&pdev->params.link, phy_addr, dev_addr, reg, ret_val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_phy.c
420
u16_t reg, // offset
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_phy.c
429
rc = elink_phy_write(&pdev->params.link, phy_addr, dev_addr, reg, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/include/lm5710.h
3701
u32_t reg,
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/include/lm5710.h
3707
u32_t reg,
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/include/lm5710.h
3713
u32_t reg,
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/include/lm5710.h
3720
u32_t reg,
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/include/lm5710.h
3729
u16_t reg, // offset
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/include/lm5710.h
3737
u16_t reg, // offset
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
217
u32_t reg = PXP_REG_HST_ZONE_PERMISSION_TABLE + LM_FW_VF_QZONE_ID(vf_info,q_idx) * 4;
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
219
REG_WR(PFDEV(pdev), reg, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
3537
u32_t reg = PXP_REG_HST_ZONE_PERMISSION_TABLE + LM_FW_VF_QZONE_ID(vf_info,q_idx) * 4;
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
3539
REG_WR(PFDEV(pdev), reg, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
556
u32_t reg = PXP_REG_HST_ZONE_PERMISSION_TABLE + LM_FW_VF_QZONE_ID(vf_info,q_idx) * 4;
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
558
REG_WR(PFDEV(pdev), reg, val);
usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/clc.h
253
u16 reg;
usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/clc.h
538
u8 devad, u16 reg, u16 *ret_val);
usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/clc.h
541
u8 devad, u16 reg, u16 val);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
1001
pci_regspec_t *reg;
usr/src/uts/common/io/cardbus/cardbus_cfg.c
1028
DDI_PROP_DONTPASS, "reg", (caddr_t)®,
usr/src/uts/common/io/cardbus/cardbus_cfg.c
1038
if ((reg[i].pci_size_low != 0) || (reg[i].pci_size_hi != 0)) {
usr/src/uts/common/io/cardbus/cardbus_cfg.c
1039
switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) {
usr/src/uts/common/io/cardbus/cardbus_cfg.c
1044
entry, reg[i].pci_size_low, &io_answer);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
1047
reg[i].pci_phys_low = io_answer;
usr/src/uts/common/io/cardbus/cardbus_cfg.c
1051
reg[i].pci_phys_hi | PCI_REG_REL_M;
usr/src/uts/common/io/cardbus/cardbus_cfg.c
1052
range.par_phys_low = reg[i].pci_phys_low;
usr/src/uts/common/io/cardbus/cardbus_cfg.c
1053
range.par_phys_mid = reg[i].pci_phys_mid;
usr/src/uts/common/io/cardbus/cardbus_cfg.c
1054
range.rng_size = reg[i].pci_size_low;
usr/src/uts/common/io/cardbus/cardbus_cfg.c
1060
kmem_free(reg, length);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
1067
kmem_free(reg, length);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
108
uint16_t reg;
usr/src/uts/common/io/cardbus/cardbus_cfg.c
1095
uint32_t reg[3], *breg;
usr/src/uts/common/io/cardbus/cardbus_cfg.c
1109
if ((length / sizeof (reg)) < 1) {
usr/src/uts/common/io/cardbus/cardbus_cfg.c
1117
reg[0] = 0;
usr/src/uts/common/io/cardbus/cardbus_cfg.c
1118
reg[1] = breg[1] + phdl->io_base;
usr/src/uts/common/io/cardbus/cardbus_cfg.c
1119
reg[2] = breg[2];
usr/src/uts/common/io/cardbus/cardbus_cfg.c
1136
"reg", (int *)reg, 3);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3059
int reg[10] = { PCI_ADDR_CONFIG, 0, 0, 0, 0};
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3061
reg[0] = PCICFG_MAKE_REG_HIGH(bus, device, func, 0);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3064
"reg", reg, 5));
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3072
uint32_t reg[3];
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3104
reg[0] = 0;
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3105
reg[1] = node->reg;
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3106
reg[2] = node->span;
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3109
"basereg", (int *)reg, 3);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3131
pci_regspec_t *reg;
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3145
(caddr_t)®, &rlen);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3148
"cardbus_config_setup, reg = 0x%p\n", (void *) reg);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3173
kmem_free((caddr_t)reg, rlen);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3178
"reg", (int *)reg, 5)) != 0) {
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3181
kmem_free((caddr_t)reg, rlen);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3195
PCI_REG_BUS_G(reg->pci_phys_hi),
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3196
PCI_REG_DEV_G(reg->pci_phys_hi),
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3197
PCI_REG_FUNC_G(reg->pci_phys_hi));
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3198
kmem_free((caddr_t)reg, rlen);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3204
PCI_REG_BUS_G(reg->pci_phys_hi),
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3205
PCI_REG_DEV_G(reg->pci_phys_hi),
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3206
PCI_REG_FUNC_G(reg->pci_phys_hi),
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3207
reg->pci_phys_hi, (void *) cfgaddr);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3231
PCI_REG_BUS_G(reg->pci_phys_hi),
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3232
PCI_REG_DEV_G(reg->pci_phys_hi),
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3233
PCI_REG_FUNC_G(reg->pci_phys_hi));
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3238
kmem_free((caddr_t)reg, rlen);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3336
pci_regspec_t *available, *reg;
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3344
"reg", (caddr_t)®, &rlen);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3364
kmem_free((caddr_t)reg, rlen);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3381
PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi),
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3382
PCI_REG_DEV_G(reg->pci_phys_hi),
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3383
PCI_REG_FUNC_G(reg->pci_phys_hi), 0);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3407
kmem_free((caddr_t)reg, rlen);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3495
pci_regspec_t *reg;
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3503
dip, DDI_PROP_DONTPASS, "reg", (caddr_t)®, &rlen);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3525
hiword = PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi),
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3526
PCI_REG_DEV_G(reg->pci_phys_hi),
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3527
PCI_REG_FUNC_G(reg->pci_phys_hi),
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3564
bcopy(reg, newreg, rlen);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
3574
kmem_free((caddr_t)reg, rlen);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
789
pci_regspec_t *reg;
usr/src/uts/common/io/cardbus/cardbus_cfg.c
880
DDI_PROP_DONTPASS, "reg", (caddr_t)®,
usr/src/uts/common/io/cardbus/cardbus_cfg.c
892
if ((reg[i].pci_size_low != 0) || (reg[i].pci_size_hi != 0)) {
usr/src/uts/common/io/cardbus/cardbus_cfg.c
893
offset = PCI_REG_REG_G(reg[i].pci_phys_hi);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
894
switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) {
usr/src/uts/common/io/cardbus/cardbus_cfg.c
898
entry, reg[i].pci_size_low, &mem_answer);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
911
reg[i].pci_phys_low = PCICFG_HIADDR(mem_answer);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
912
reg[i].pci_phys_mid = PCICFG_LOADDR(mem_answer);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
919
entry, reg[i].pci_size_low, &mem_answer);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
925
reg[i].pci_phys_low = (uint32_t)mem_answer;
usr/src/uts/common/io/cardbus/cardbus_cfg.c
926
reg[i].pci_phys_mid = 0;
usr/src/uts/common/io/cardbus/cardbus_cfg.c
955
entry, reg[i].pci_size_low, &io_answer);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
960
reg[i].pci_phys_low = io_answer;
usr/src/uts/common/io/cardbus/cardbus_cfg.c
965
kmem_free(reg, length);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
976
®[i]) != PCICFG_SUCCESS) {
usr/src/uts/common/io/cardbus/cardbus_cfg.c
977
kmem_free(reg, length);
usr/src/uts/common/io/cardbus/cardbus_cfg.c
984
kmem_free(reg, length);
usr/src/uts/common/io/chxge/ch.h
285
uint32_t t1_os_pci_read_config_2(ch_t *obj, uint32_t reg, uint16_t *val);
usr/src/uts/common/io/chxge/ch.h
286
uint32_t t1_os_pci_read_config_4(ch_t *obj, uint32_t reg, uint32_t *val);
usr/src/uts/common/io/chxge/ch.h
287
int t1_os_pci_write_config_2(ch_t *obj, uint32_t reg, uint16_t val);
usr/src/uts/common/io/chxge/ch.h
288
int t1_os_pci_write_config_4(ch_t *obj, uint32_t reg, uint32_t val);
usr/src/uts/common/io/chxge/com/ch_subr.c
61
int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,
usr/src/uts/common/io/chxge/com/ch_subr.c
65
u32 val = t1_read_reg_4(adapter, reg) & mask;
usr/src/uts/common/io/chxge/com/common.h
240
int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,
usr/src/uts/common/io/chxge/com/cphy.h
101
return cphy->mdio_read(cphy->adapter, cphy->addr, mmd, reg, valp);
usr/src/uts/common/io/chxge/com/cphy.h
104
static inline int mdio_write(struct cphy *cphy, int mmd, int reg,
usr/src/uts/common/io/chxge/com/cphy.h
107
return cphy->mdio_write(cphy->adapter, cphy->addr, mmd, reg, val);
usr/src/uts/common/io/chxge/com/cphy.h
110
static inline int simple_mdio_read(struct cphy *cphy, int reg,
usr/src/uts/common/io/chxge/com/cphy.h
113
return mdio_read(cphy, 0, reg, valp);
usr/src/uts/common/io/chxge/com/cphy.h
116
static inline int simple_mdio_write(struct cphy *cphy, int reg,
usr/src/uts/common/io/chxge/com/cphy.h
119
return mdio_write(cphy, 0, reg, val);
usr/src/uts/common/io/chxge/com/cphy.h
98
static inline int mdio_read(struct cphy *cphy, int mmd, int reg,
usr/src/uts/common/io/chxge/com/fpga_defs.h
237
#define MAC_REG_ADDR(idx, reg) (MAC_REG_BASE + (idx) * 128 + (reg))
usr/src/uts/common/io/chxge/com/mv88e1xxx.c
41
static void mdio_set_bit(struct cphy *cphy, int reg, u32 bitval)
usr/src/uts/common/io/chxge/com/mv88e1xxx.c
45
(void) simple_mdio_read(cphy, reg, &val);
usr/src/uts/common/io/chxge/com/mv88e1xxx.c
46
(void) simple_mdio_write(cphy, reg, val | bitval);
usr/src/uts/common/io/chxge/com/mv88e1xxx.c
52
static void mdio_clear_bit(struct cphy *cphy, int reg, u32 bitval)
usr/src/uts/common/io/chxge/com/mv88e1xxx.c
56
(void) simple_mdio_read(cphy, reg, &val);
usr/src/uts/common/io/chxge/com/mv88e1xxx.c
57
(void) simple_mdio_write(cphy, reg, val & ~bitval);
usr/src/uts/common/io/chxge/com/pm3393.c
101
(void) t1_tpi_write(cmac->adapter, OFFSET(reg), data32);
usr/src/uts/common/io/chxge/com/pm3393.c
93
static int pmread(struct cmac *cmac, u32 reg, u32 * data32)
usr/src/uts/common/io/chxge/com/pm3393.c
95
(void) t1_tpi_read(cmac->adapter, OFFSET(reg), data32);
usr/src/uts/common/io/chxge/com/pm3393.c
99
static int pmwrite(struct cmac *cmac, u32 reg, u32 data32)
usr/src/uts/common/io/chxge/glue.c
102
t1_os_pci_read_config_2(ch_t *obj, uint32_t reg, uint16_t *val)
usr/src/uts/common/io/chxge/glue.c
104
*val = pci_config_get16(obj->ch_hpci, reg);
usr/src/uts/common/io/chxge/glue.c
109
t1_os_pci_write_config_2(ch_t *obj, uint32_t reg, uint16_t val)
usr/src/uts/common/io/chxge/glue.c
111
pci_config_put16(obj->ch_hpci, reg, val);
usr/src/uts/common/io/chxge/glue.c
116
t1_os_pci_read_config_4(ch_t *obj, uint32_t reg, uint32_t *val)
usr/src/uts/common/io/chxge/glue.c
118
*val = pci_config_get32(obj->ch_hpci, reg);
usr/src/uts/common/io/chxge/glue.c
123
t1_os_pci_write_config_4(ch_t *obj, uint32_t reg, uint32_t val)
usr/src/uts/common/io/chxge/glue.c
125
pci_config_put32(obj->ch_hpci, reg, val);
usr/src/uts/common/io/chxge/glue.c
176
uint32_t reg;
usr/src/uts/common/io/chxge/glue.c
220
pe->pe_reg_val = reg = t1_sge_get_ptimeout(chp);
usr/src/uts/common/io/chxge/glue.c
222
pe->pe_reg_val = reg = t1_read_reg_4(chp, pe->addr);
usr/src/uts/common/io/chxge/glue.c
240
reg = t1_read_reg_4(chp, pe->addr);
usr/src/uts/common/io/chxge/glue.c
241
pe->pe_reg_val |= (reg & ~pe->pe_mask32);
usr/src/uts/common/io/chxge/glue.c
264
pe->pe_reg_val = reg = pci_config_get32(chp->ch_hpci, pe->addr);
usr/src/uts/common/io/chxge/glue.c
278
reg = pci_config_get32(chp->ch_hpci, pe->addr);
usr/src/uts/common/io/chxge/glue.c
279
pe->pe_reg_val |= (reg & ~pe->pe_mask32);
usr/src/uts/common/io/comstar/port/iscsit/iscsit_isns.c
1544
isns_reg_type_t reg)
usr/src/uts/common/io/comstar/port/iscsit/iscsit_isns.c
1551
switch (reg) {
usr/src/uts/common/io/comstar/port/iscsit/iscsit_isns.c
1562
rc = isnst_register(svr, itarget, reg);
usr/src/uts/common/io/comstar/port/iscsit/iscsit_isns.c
1566
rc = isnst_register(svr, NULL, reg);
usr/src/uts/common/io/comstar/port/iscsit/iscsit_isns.c
296
isns_reg_type_t reg);
usr/src/uts/common/io/comstar/port/qlt/qlt.c
10015
REG_WR16(qlt, reg, data);
usr/src/uts/common/io/comstar/port/qlt/qlt.c
10025
uint32_t reg = entry->addr;
usr/src/uts/common/io/comstar/port/qlt/qlt.c
10045
*bp++ = REG_RD8(qlt, reg++);
usr/src/uts/common/io/comstar/port/qlt/qlt.c
10055
uint32_t reg = entry->addr;
usr/src/uts/common/io/comstar/port/qlt/qlt.c
10067
REG_WR32(qlt, reg, entry->data);
usr/src/uts/common/io/comstar/port/qlt/qlt.c
9903
uint32_t reg = entry->pci_offset;
usr/src/uts/common/io/comstar/port/qlt/qlt.c
9926
*bp++ = REG_RD8(qlt, reg++);
usr/src/uts/common/io/comstar/port/qlt/qlt.c
9938
uint32_t reg = entry->pci_offset;
usr/src/uts/common/io/comstar/port/qlt/qlt.c
9951
REG_WR32(qlt, reg, entry->data);
usr/src/uts/common/io/comstar/port/qlt/qlt.c
9961
uint32_t reg = entry->pci_offset;
usr/src/uts/common/io/comstar/port/qlt/qlt.c
9986
*bp++ = REG_RD8(qlt, reg++);
usr/src/uts/common/io/comstar/port/qlt/qlt.c
9999
uint32_t reg = entry->pci_offset;
usr/src/uts/common/io/cxgbe/common/common.h
572
void t4_hw_pci_read_cfg4(adapter_t *adapter, int reg, u32 *val);
usr/src/uts/common/io/cxgbe/common/common.h
732
u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach);
usr/src/uts/common/io/cxgbe/common/common.h
884
unsigned int mmd, unsigned int reg, unsigned int *valp);
usr/src/uts/common/io/cxgbe/common/common.h
886
unsigned int mmd, unsigned int reg, unsigned int val);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
1068
u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach)
usr/src/uts/common/io/cxgbe/common/t4_hw.c
1090
ldst_cmd.u.pcie.r = reg;
usr/src/uts/common/io/cxgbe/common/t4_hw.c
1103
reg, -ret);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
1110
t4_hw_pci_read_cfg4(adap, reg, &val);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
145
static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
usr/src/uts/common/io/cxgbe/common/t4_hw.c
149
u32 val = t4_read_reg(adapter, reg);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
163
static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
usr/src/uts/common/io/cxgbe/common/t4_hw.c
166
return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
usr/src/uts/common/io/cxgbe/common/t4_hw.c
244
void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
usr/src/uts/common/io/cxgbe/common/t4_hw.c
246
u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
3021
unsigned int reg = reg_ranges[range];
usr/src/uts/common/io/cxgbe/common/t4_hw.c
3023
u32 *bufp = (u32 *)((char *)buf + reg);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
3028
while (reg <= last_reg && bufp < buf_end) {
usr/src/uts/common/io/cxgbe/common/t4_hw.c
3029
*bufp++ = t4_read_reg(adap, reg);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
3030
reg += sizeof(u32);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
45
t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
usr/src/uts/common/io/cxgbe/common/t4_hw.c
4629
static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
usr/src/uts/common/io/cxgbe/common/t4_hw.c
4634
unsigned int status = t4_read_reg(adapter, reg);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
4652
t4_write_reg(adapter, reg, status);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
47
*val = pci_config_get8(sc->pci_regh, reg);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
51
t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
usr/src/uts/common/io/cxgbe/common/t4_hw.c
53
pci_config_put8(sc->pci_regh, reg, val);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
57
t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
usr/src/uts/common/io/cxgbe/common/t4_hw.c
59
*val = pci_config_get16(sc->pci_regh, reg);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
63
t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
usr/src/uts/common/io/cxgbe/common/t4_hw.c
65
pci_config_put16(sc->pci_regh, reg, val);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
69
t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
usr/src/uts/common/io/cxgbe/common/t4_hw.c
7042
unsigned int mmd, unsigned int reg, unsigned int *valp)
usr/src/uts/common/io/cxgbe/common/t4_hw.c
7056
c.u.mdio.raddr = cpu_to_be16(reg);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
7076
unsigned int mmd, unsigned int reg, unsigned int val)
usr/src/uts/common/io/cxgbe/common/t4_hw.c
7089
c.u.mdio.raddr = cpu_to_be16(reg);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
71
*val = pci_config_get32(sc->pci_regh, reg);
usr/src/uts/common/io/cxgbe/common/t4_hw.c
75
t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
usr/src/uts/common/io/cxgbe/common/t4_hw.c
77
pci_config_put32(sc->pci_regh, reg, val);
usr/src/uts/common/io/cxgbe/common/t4_regs.h
269
#define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
usr/src/uts/common/io/cxgbe/common/t4_regs.h
272
#define MC_REG(reg, idx) (reg + MC_STRIDE * idx)
usr/src/uts/common/io/cxgbe/common/t4_regs.h
48
#define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
usr/src/uts/common/io/cxgbe/common/t4_regs.h
485
#define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
usr/src/uts/common/io/cxgbe/common/t4_regs.h
488
#define EDC_T5_REG(reg, idx) (reg + EDC_T5_STRIDE * idx)
usr/src/uts/common/io/cxgbe/common/t4_regs.h
82
#define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1036
#define ulp_region(reg) \
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1038
md->base = t4_read_reg(padap, A_ULP_ ## reg ## _LLIMIT);\
usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
1039
(md++)->limit = t4_read_reg(padap, A_ULP_ ## reg ## _ULIMIT);\
usr/src/uts/common/io/cxgbe/t4nex/t4_ioctl.c
106
r.reg &= ~0x3;
usr/src/uts/common/io/cxgbe/t4nex/t4_ioctl.c
109
t4_write_reg(sc, r.reg, r.value);
usr/src/uts/common/io/cxgbe/t4nex/t4_ioctl.c
111
r.value = t4_read_reg(sc, r.reg);
usr/src/uts/common/io/cxgbe/t4nex/t4_ioctl.c
84
r.reg &= ~0x3;
usr/src/uts/common/io/cxgbe/t4nex/t4_ioctl.c
87
pci_config_put32(sc->pci_regh, r.reg, r.value);
usr/src/uts/common/io/cxgbe/t4nex/t4_ioctl.c
89
r.value = pci_config_get32(sc->pci_regh, r.reg);
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
143
int rc, id, *reg;
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
152
"reg", ®, &n);
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
156
pf = PCI_REG_FUNC_G(reg[0]);
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
157
ddi_prop_free(reg);
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
1610
uint32_t reg;
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
1625
reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, n);
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
1627
t4_write_reg(sc, reg, start | pf);
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
1628
(void) t4_read_reg(sc, reg);
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
2572
t4_read_reg(struct adapter *sc, uint32_t reg)
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
2574
const uint32_t val = ddi_get32(sc->regh, (uint32_t *)(sc->regp + reg));
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
2575
DTRACE_PROBE3(t4__reg__read, struct adapter *, sc, uint32_t, reg,
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
2581
t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
2583
DTRACE_PROBE3(t4__reg__write, struct adapter *, sc, uint32_t, reg,
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
2585
ddi_put32(sc->regh, (uint32_t *)(sc->regp + reg), val);
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
2589
t4_read_reg64(struct adapter *sc, uint32_t reg)
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
2591
const uint64_t val = ddi_get64(sc->regh, (uint64_t *)(sc->regp + reg));
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
2592
DTRACE_PROBE3(t4__reg__read, struct adapter *, sc, uint32_t, reg,
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
2598
t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
2600
DTRACE_PROBE3(t4__reg__write, struct adapter *, sc, uint32_t, reg,
usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c
2602
ddi_put64(sc->regh, (uint64_t *)(sc->regp + reg), val);
usr/src/uts/common/io/cxgbe/t4nex/t4nex.h
51
uint32_t reg;
usr/src/uts/common/io/dmfe/dmfe_log.c
73
uint32_t reg;
usr/src/uts/common/io/dmfe/dmfe_log.c
89
reg = dmfe_chip_get32(dmfep, 8*i);
usr/src/uts/common/io/dmfe/dmfe_log.c
90
cmn_err(CE_NOTE, "!%s: CR%d\t%08x", dmfep->ifname, i, reg);
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
1001
reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
1002
reg |= (1 << 22);
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
1003
E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
1006
reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
1007
reg |= (1 << 22);
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
1008
E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
1011
reg = E1000_READ_REG(hw, E1000_TARC(0));
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
1012
reg &= ~(0xF << 27); /* 30:27 */
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
1014
reg &= ~(1 << 20);
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
1015
E1000_WRITE_REG(hw, E1000_TARC(0), reg);
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
1018
reg = E1000_READ_REG(hw, E1000_TARC(1));
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
1020
reg &= ~(1 << 28);
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
1022
reg |= (1 << 28);
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
1023
E1000_WRITE_REG(hw, E1000_TARC(1), reg);
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
1028
reg = E1000_READ_REG(hw, E1000_RFCTL);
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
1029
reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
1030
E1000_WRITE_REG(hw, E1000_RFCTL, reg);
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
1045
u32 reg;
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
1110
reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL;
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
1113
ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
1117
reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE;
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
1118
ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
1122
ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
1135
reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
1136
reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
1137
E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
usr/src/uts/common/io/e1000api/e1000_80003es2lan.c
996
u32 reg;
usr/src/uts/common/io/e1000api/e1000_82542.c
448
u32 e1000_translate_register_82542(u32 reg)
usr/src/uts/common/io/e1000api/e1000_82542.c
456
switch (reg) {
usr/src/uts/common/io/e1000api/e1000_82542.c
458
reg = 0x00040;
usr/src/uts/common/io/e1000api/e1000_82542.c
461
reg = 0x00108;
usr/src/uts/common/io/e1000api/e1000_82542.c
464
reg = 0x00110;
usr/src/uts/common/io/e1000api/e1000_82542.c
467
reg = 0x00114;
usr/src/uts/common/io/e1000api/e1000_82542.c
470
reg = 0x00118;
usr/src/uts/common/io/e1000api/e1000_82542.c
473
reg = 0x00120;
usr/src/uts/common/io/e1000api/e1000_82542.c
476
reg = 0x00128;
usr/src/uts/common/io/e1000api/e1000_82542.c
479
reg = 0x00138;
usr/src/uts/common/io/e1000api/e1000_82542.c
482
reg = 0x0013C;
usr/src/uts/common/io/e1000api/e1000_82542.c
485
reg = 0x00140;
usr/src/uts/common/io/e1000api/e1000_82542.c
488
reg = 0x00148;
usr/src/uts/common/io/e1000api/e1000_82542.c
491
reg = 0x00150;
usr/src/uts/common/io/e1000api/e1000_82542.c
494
reg = 0x00160;
usr/src/uts/common/io/e1000api/e1000_82542.c
497
reg = 0x00168;
usr/src/uts/common/io/e1000api/e1000_82542.c
500
reg = 0x00200;
usr/src/uts/common/io/e1000api/e1000_82542.c
503
reg = 0x00420;
usr/src/uts/common/io/e1000api/e1000_82542.c
506
reg = 0x00424;
usr/src/uts/common/io/e1000api/e1000_82542.c
509
reg = 0x00428;
usr/src/uts/common/io/e1000api/e1000_82542.c
512
reg = 0x00430;
usr/src/uts/common/io/e1000api/e1000_82542.c
515
reg = 0x00438;
usr/src/uts/common/io/e1000api/e1000_82542.c
518
reg = 0x00440;
usr/src/uts/common/io/e1000api/e1000_82542.c
521
reg = 0x00600;
usr/src/uts/common/io/e1000api/e1000_82542.c
524
reg = 0x08010;
usr/src/uts/common/io/e1000api/e1000_82542.c
527
reg = 0x08018;
usr/src/uts/common/io/e1000api/e1000_82542.c
533
return reg;
usr/src/uts/common/io/e1000api/e1000_82571.c
1272
u32 reg;
usr/src/uts/common/io/e1000api/e1000_82571.c
1277
reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
usr/src/uts/common/io/e1000api/e1000_82571.c
1278
reg |= (1 << 22);
usr/src/uts/common/io/e1000api/e1000_82571.c
1279
E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
usr/src/uts/common/io/e1000api/e1000_82571.c
1282
reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
usr/src/uts/common/io/e1000api/e1000_82571.c
1283
reg |= (1 << 22);
usr/src/uts/common/io/e1000api/e1000_82571.c
1284
E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
usr/src/uts/common/io/e1000api/e1000_82571.c
1287
reg = E1000_READ_REG(hw, E1000_TARC(0));
usr/src/uts/common/io/e1000api/e1000_82571.c
1288
reg &= ~(0xF << 27); /* 30:27 */
usr/src/uts/common/io/e1000api/e1000_82571.c
1292
reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
usr/src/uts/common/io/e1000api/e1000_82571.c
1296
reg |= (1 << 26);
usr/src/uts/common/io/e1000api/e1000_82571.c
1301
E1000_WRITE_REG(hw, E1000_TARC(0), reg);
usr/src/uts/common/io/e1000api/e1000_82571.c
1304
reg = E1000_READ_REG(hw, E1000_TARC(1));
usr/src/uts/common/io/e1000api/e1000_82571.c
1308
reg &= ~((1 << 29) | (1 << 30));
usr/src/uts/common/io/e1000api/e1000_82571.c
1309
reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
usr/src/uts/common/io/e1000api/e1000_82571.c
1311
reg &= ~(1 << 28);
usr/src/uts/common/io/e1000api/e1000_82571.c
1313
reg |= (1 << 28);
usr/src/uts/common/io/e1000api/e1000_82571.c
1314
E1000_WRITE_REG(hw, E1000_TARC(1), reg);
usr/src/uts/common/io/e1000api/e1000_82571.c
1325
reg = E1000_READ_REG(hw, E1000_CTRL);
usr/src/uts/common/io/e1000api/e1000_82571.c
1326
reg &= ~(1 << 29);
usr/src/uts/common/io/e1000api/e1000_82571.c
1327
E1000_WRITE_REG(hw, E1000_CTRL, reg);
usr/src/uts/common/io/e1000api/e1000_82571.c
1338
reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
usr/src/uts/common/io/e1000api/e1000_82571.c
1339
reg &= ~(1 << 23);
usr/src/uts/common/io/e1000api/e1000_82571.c
1340
reg |= (1 << 22);
usr/src/uts/common/io/e1000api/e1000_82571.c
1341
E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
usr/src/uts/common/io/e1000api/e1000_82571.c
1348
reg = E1000_READ_REG(hw, E1000_PBA_ECC);
usr/src/uts/common/io/e1000api/e1000_82571.c
1349
reg |= E1000_PBA_ECC_CORR_EN;
usr/src/uts/common/io/e1000api/e1000_82571.c
1350
E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
usr/src/uts/common/io/e1000api/e1000_82571.c
1358
reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
usr/src/uts/common/io/e1000api/e1000_82571.c
1359
reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
usr/src/uts/common/io/e1000api/e1000_82571.c
1360
E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
usr/src/uts/common/io/e1000api/e1000_82571.c
1367
reg = E1000_READ_REG(hw, E1000_RFCTL);
usr/src/uts/common/io/e1000api/e1000_82571.c
1368
reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
usr/src/uts/common/io/e1000api/e1000_82571.c
1369
E1000_WRITE_REG(hw, E1000_RFCTL, reg);
usr/src/uts/common/io/e1000api/e1000_82571.c
1376
reg = E1000_READ_REG(hw, E1000_GCR);
usr/src/uts/common/io/e1000api/e1000_82571.c
1377
reg |= (1 << 22);
usr/src/uts/common/io/e1000api/e1000_82571.c
1378
E1000_WRITE_REG(hw, E1000_GCR, reg);
usr/src/uts/common/io/e1000api/e1000_82571.c
1386
reg = E1000_READ_REG(hw, E1000_GCR2);
usr/src/uts/common/io/e1000api/e1000_82571.c
1387
reg |= 1;
usr/src/uts/common/io/e1000api/e1000_82571.c
1388
E1000_WRITE_REG(hw, E1000_GCR2, reg);
usr/src/uts/common/io/e1000api/e1000_82575.c
1296
u32 reg;
usr/src/uts/common/io/e1000api/e1000_82575.c
1305
reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
usr/src/uts/common/io/e1000api/e1000_82575.c
1306
reg |= E1000_PCS_CFG_PCS_EN;
usr/src/uts/common/io/e1000api/e1000_82575.c
1307
E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
usr/src/uts/common/io/e1000api/e1000_82575.c
1310
reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
usr/src/uts/common/io/e1000api/e1000_82575.c
1311
reg &= ~E1000_CTRL_EXT_SDP3_DATA;
usr/src/uts/common/io/e1000api/e1000_82575.c
1312
E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
usr/src/uts/common/io/e1000api/e1000_82575.c
135
u32 reg = 0;
usr/src/uts/common/io/e1000api/e1000_82575.c
1394
u32 reg;
usr/src/uts/common/io/e1000api/e1000_82575.c
1404
reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
usr/src/uts/common/io/e1000api/e1000_82575.c
1405
reg &= ~E1000_PCS_CFG_PCS_EN;
usr/src/uts/common/io/e1000api/e1000_82575.c
1406
E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
usr/src/uts/common/io/e1000api/e1000_82575.c
1409
reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
usr/src/uts/common/io/e1000api/e1000_82575.c
1410
reg |= E1000_CTRL_EXT_SDP3_DATA;
usr/src/uts/common/io/e1000api/e1000_82575.c
1411
E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
usr/src/uts/common/io/e1000api/e1000_82575.c
143
reg = E1000_READ_REG(hw, E1000_MDIC);
usr/src/uts/common/io/e1000api/e1000_82575.c
144
ext_mdio = !!(reg & E1000_MDIC_DEST);
usr/src/uts/common/io/e1000api/e1000_82575.c
151
reg = E1000_READ_REG(hw, E1000_MDICNFG);
usr/src/uts/common/io/e1000api/e1000_82575.c
152
ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
usr/src/uts/common/io/e1000api/e1000_82575.c
1636
u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
usr/src/uts/common/io/e1000api/e1000_82575.c
1667
reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
usr/src/uts/common/io/e1000api/e1000_82575.c
1677
reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
usr/src/uts/common/io/e1000api/e1000_82575.c
1705
reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
usr/src/uts/common/io/e1000api/e1000_82575.c
1717
reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
usr/src/uts/common/io/e1000api/e1000_82575.c
1722
reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
usr/src/uts/common/io/e1000api/e1000_82575.c
1726
reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
usr/src/uts/common/io/e1000api/e1000_82575.c
1747
DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
usr/src/uts/common/io/e1000api/e1000_82575.c
1750
reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
usr/src/uts/common/io/e1000api/e1000_82575.c
1753
reg |= E1000_PCS_LCTL_FORCE_FCTRL;
usr/src/uts/common/io/e1000api/e1000_82575.c
1755
DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
usr/src/uts/common/io/e1000api/e1000_82575.c
1758
E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
usr/src/uts/common/io/e1000api/e1000_api.c
1392
s32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, u32 offset,
usr/src/uts/common/io/e1000api/e1000_api.c
1395
return e1000_write_8bit_ctrl_reg_generic(hw, reg, offset, data);
usr/src/uts/common/io/e1000api/e1000_api.h
119
u32 e1000_translate_register_82542(u32 reg);
usr/src/uts/common/io/e1000api/e1000_api.h
89
s32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, u32 offset,
usr/src/uts/common/io/e1000api/e1000_defines.h
1343
#define GG82563_REG(page, reg) \
usr/src/uts/common/io/e1000api/e1000_defines.h
1344
(((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
usr/src/uts/common/io/e1000api/e1000_hw.h
1117
s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
usr/src/uts/common/io/e1000api/e1000_hw.h
1118
s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
usr/src/uts/common/io/e1000api/e1000_hw.h
1119
void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
usr/src/uts/common/io/e1000api/e1000_hw.h
1120
void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
usr/src/uts/common/io/e1000api/e1000_i210.c
650
u32 i, reg;
usr/src/uts/common/io/e1000api/e1000_i210.c
655
reg = E1000_READ_REG(hw, E1000_EECD);
usr/src/uts/common/io/e1000api/e1000_i210.c
656
if (reg & E1000_EECD_FLUDONE_I210) {
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
1038
u16 reg;
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
1047
®);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
1054
reg &
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
1067
reg);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
1079
ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
1084
reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
1088
reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
1094
reg |= 50 <<
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
1101
ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
1144
u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
1222
reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
1223
E1000_WRITE_REG(hw, E1000_LTRV, reg);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
1226
reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK;
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
1227
reg |= obff_hwm;
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
1228
E1000_WRITE_REG(hw, E1000_SVT, reg);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
1231
reg = E1000_READ_REG(hw, E1000_SVCR);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
1232
reg |= E1000_SVCR_OFF_EN;
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
1237
reg |= E1000_SVCR_OFF_MASKINT;
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
1238
E1000_WRITE_REG(hw, E1000_SVCR, reg);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
2519
u32 reg = 0;
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
2543
reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
2544
reg |= E1000_CTRL_FRCSPD;
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
2545
E1000_WRITE_REG(hw, E1000_CTRL, reg);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
3121
u16 reg;
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
3149
hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
3150
reg &= ~BM_WUC_HOST_WU_BIT;
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
3151
hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5006
u32 ctrl, reg;
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5075
reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5076
reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5077
reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5078
E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5104
reg = E1000_READ_REG(hw, E1000_KABGTXD);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5105
reg |= E1000_KABGTXD_BGSQLBIAS;
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5106
E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5210
u32 reg;
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5215
reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5216
reg |= (1 << 22);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5219
reg |= E1000_CTRL_EXT_PHYPDEN;
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5220
E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5223
reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5224
reg |= (1 << 22);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5225
E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5228
reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5229
reg |= (1 << 22);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5230
E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5233
reg = E1000_READ_REG(hw, E1000_TARC(0));
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5235
reg |= (1 << 28) | (1 << 29);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5236
reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5237
E1000_WRITE_REG(hw, E1000_TARC(0), reg);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5240
reg = E1000_READ_REG(hw, E1000_TARC(1));
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5242
reg &= ~(1 << 28);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5244
reg |= (1 << 28);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5245
reg |= (1 << 24) | (1 << 26) | (1 << 30);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5246
E1000_WRITE_REG(hw, E1000_TARC(1), reg);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5250
reg = E1000_READ_REG(hw, E1000_STATUS);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5251
reg &= ~(1UL << 31);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5252
E1000_WRITE_REG(hw, E1000_STATUS, reg);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5258
reg = E1000_READ_REG(hw, E1000_RFCTL);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5259
reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5265
reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5266
E1000_WRITE_REG(hw, E1000_RFCTL, reg);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5270
reg = E1000_READ_REG(hw, E1000_PBECCSTS);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5271
reg |= E1000_PBECCSTS_ECC_ENABLE;
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5272
E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5274
reg = E1000_READ_REG(hw, E1000_CTRL);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5275
reg |= E1000_CTRL_MEHE;
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5276
E1000_WRITE_REG(hw, E1000_CTRL, reg);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5592
u32 reg;
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5604
reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5605
reg |= (E1000_PHY_CTRL_GBE_DISABLE |
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5607
E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5628
reg = E1000_READ_REG(hw, E1000_CTRL);
usr/src/uts/common/io/e1000api/e1000_ich8lan.c
5629
E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
usr/src/uts/common/io/e1000api/e1000_ich8lan.h
134
#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
usr/src/uts/common/io/e1000api/e1000_ich8lan.h
135
((reg) & MAX_PHY_REG_ADDRESS))
usr/src/uts/common/io/e1000api/e1000_mac.c
2229
s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
usr/src/uts/common/io/e1000api/e1000_mac.c
2238
E1000_WRITE_REG(hw, reg, regvalue);
usr/src/uts/common/io/e1000api/e1000_mac.c
2243
regvalue = E1000_READ_REG(hw, reg);
usr/src/uts/common/io/e1000api/e1000_mac.c
2248
DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
usr/src/uts/common/io/e1000api/e1000_mac.c
281
u32 reg;
usr/src/uts/common/io/e1000api/e1000_mac.c
286
reg = E1000_READ_REG(hw, E1000_STATUS);
usr/src/uts/common/io/e1000api/e1000_mac.c
287
bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
usr/src/uts/common/io/e1000api/e1000_mac.h
79
s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
usr/src/uts/common/io/e1000api/e1000_nvm.c
234
u32 i, reg = 0;
usr/src/uts/common/io/e1000api/e1000_nvm.c
240
reg = E1000_READ_REG(hw, E1000_EERD);
usr/src/uts/common/io/e1000api/e1000_nvm.c
242
reg = E1000_READ_REG(hw, E1000_EEWR);
usr/src/uts/common/io/e1000api/e1000_nvm.c
244
if (reg & E1000_NVM_RW_REG_DONE)
usr/src/uts/common/io/e1000api/e1000_phy.c
3093
static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
usr/src/uts/common/io/e1000api/e1000_phy.c
3097
if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
usr/src/uts/common/io/e1000api/e1000_phy.c
3433
u16 reg = BM_PHY_REG_NUM(offset);
usr/src/uts/common/io/e1000api/e1000_phy.c
3454
DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
usr/src/uts/common/io/e1000api/e1000_phy.c
3457
ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
usr/src/uts/common/io/e1000api/e1000_phy.c
3474
DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);
usr/src/uts/common/io/e1000api/e1000_phy.c
3537
u16 reg = BM_PHY_REG_NUM(offset);
usr/src/uts/common/io/e1000api/e1000_phy.c
3564
if (reg > MAX_PHY_MULTI_PAGE_REG) {
usr/src/uts/common/io/e1000api/e1000_phy.c
3577
page << IGP_PAGE_SHIFT, reg);
usr/src/uts/common/io/e1000api/e1000_phy.c
3579
ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
usr/src/uts/common/io/e1000api/e1000_phy.c
3646
u16 reg = BM_PHY_REG_NUM(offset);
usr/src/uts/common/io/e1000api/e1000_phy.c
3679
!(MAX_PHY_REG_ADDRESS & reg) &&
usr/src/uts/common/io/e1000api/e1000_phy.c
3689
if (reg > MAX_PHY_MULTI_PAGE_REG) {
usr/src/uts/common/io/e1000api/e1000_phy.c
3702
page << IGP_PAGE_SHIFT, reg);
usr/src/uts/common/io/e1000api/e1000_phy.c
3704
ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
usr/src/uts/common/io/e1000api/e1000_phy.h
160
#define BM_PHY_REG(page, reg) \
usr/src/uts/common/io/e1000api/e1000_phy.h
161
(((reg) & MAX_PHY_REG_ADDRESS) |\
usr/src/uts/common/io/e1000api/e1000_phy.h
163
(((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
usr/src/uts/common/io/e1000api/e1000_vf.h
292
s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
usr/src/uts/common/io/e1000g/e1000_osdep.h
122
#define E1000_WRITE_REG(hw, reg, value) \
usr/src/uts/common/io/e1000g/e1000_osdep.h
126
(uint32_t *)((uintptr_t)(hw)->hw_addr + reg), \
usr/src/uts/common/io/e1000g/e1000_osdep.h
131
e1000_translate_register_82542(reg)), \
usr/src/uts/common/io/e1000g/e1000_osdep.h
135
#define E1000_READ_REG(hw, reg) (\
usr/src/uts/common/io/e1000g/e1000_osdep.h
138
(uint32_t *)((uintptr_t)(hw)->hw_addr + reg)) : \
usr/src/uts/common/io/e1000g/e1000_osdep.h
141
e1000_translate_register_82542(reg))))
usr/src/uts/common/io/e1000g/e1000_osdep.h
143
#define E1000_WRITE_REG_ARRAY(hw, reg, offset, value) \
usr/src/uts/common/io/e1000g/e1000_osdep.h
148
reg + ((offset) << 2)),\
usr/src/uts/common/io/e1000g/e1000_osdep.h
153
e1000_translate_register_82542(reg) + \
usr/src/uts/common/io/e1000g/e1000_osdep.h
157
#define E1000_READ_REG_ARRAY(hw, reg, offset) (\
usr/src/uts/common/io/e1000g/e1000_osdep.h
160
(uint32_t *)((uintptr_t)(hw)->hw_addr + reg + \
usr/src/uts/common/io/e1000g/e1000_osdep.h
164
e1000_translate_register_82542(reg) + \
usr/src/uts/common/io/e1000g/e1000_osdep.h
168
#define E1000_WRITE_REG_ARRAY_DWORD(a, reg, offset, value) \
usr/src/uts/common/io/e1000g/e1000_osdep.h
169
E1000_WRITE_REG_ARRAY(a, reg, offset, value)
usr/src/uts/common/io/e1000g/e1000_osdep.h
170
#define E1000_READ_REG_ARRAY_DWORD(a, reg, offset) \
usr/src/uts/common/io/e1000g/e1000_osdep.h
171
E1000_READ_REG_ARRAY(a, reg, offset)
usr/src/uts/common/io/e1000g/e1000_osdep.h
174
#define E1000_READ_FLASH_REG(hw, reg) \
usr/src/uts/common/io/e1000g/e1000_osdep.h
176
(uint32_t *)((uintptr_t)(hw)->flash_address + (reg)))
usr/src/uts/common/io/e1000g/e1000_osdep.h
178
#define E1000_READ_FLASH_REG16(hw, reg) \
usr/src/uts/common/io/e1000g/e1000_osdep.h
180
(uint16_t *)((uintptr_t)(hw)->flash_address + (reg)))
usr/src/uts/common/io/e1000g/e1000_osdep.h
182
#define E1000_WRITE_FLASH_REG(hw, reg, value) \
usr/src/uts/common/io/e1000g/e1000_osdep.h
184
(uint32_t *)((uintptr_t)(hw)->flash_address + (reg)), (value))
usr/src/uts/common/io/e1000g/e1000_osdep.h
186
#define E1000_WRITE_FLASH_REG16(hw, reg, value) \
usr/src/uts/common/io/e1000g/e1000_osdep.h
188
(uint16_t *)((uintptr_t)(hw)->flash_address + (reg)), (value))
usr/src/uts/common/io/e1000g/e1000_osdep.h
231
#define E1000_WRITE_REG_IO(a, reg, val) { \
usr/src/uts/common/io/e1000g/e1000_osdep.h
234
reg); \
usr/src/uts/common/io/e1000g/e1000g_main.c
2605
Adapter->unicst_addr[slot].reg.high = 0;
usr/src/uts/common/io/e1000g/e1000g_main.c
2606
Adapter->unicst_addr[slot].reg.low = 0;
usr/src/uts/common/io/e1000g/e1000g_main.c
2654
Adapter->unicst_addr[slot].reg.high = 0;
usr/src/uts/common/io/e1000g/e1000g_main.c
2655
Adapter->unicst_addr[slot].reg.low = 0;
usr/src/uts/common/io/e1000g/e1000g_main.c
4671
ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0);
usr/src/uts/common/io/e1000g/e1000g_main.c
4672
ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1);
usr/src/uts/common/io/e1000g/e1000g_main.c
4674
ether_addr.reg.low = ntohl(ether_addr.reg.low);
usr/src/uts/common/io/e1000g/e1000g_main.c
4675
ether_addr.reg.high = ntohl(ether_addr.reg.high);
usr/src/uts/common/io/e1000g/e1000g_osdep.c
109
e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
usr/src/uts/common/io/e1000g/e1000g_osdep.c
112
PCI_EX_CONF_CAP + reg);
usr/src/uts/common/io/e1000g/e1000g_osdep.c
123
e1000_write_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
usr/src/uts/common/io/e1000g/e1000g_osdep.c
135
(off_t)(pcie_cap + reg), *value);
usr/src/uts/common/io/e1000g/e1000g_osdep.c
46
e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
usr/src/uts/common/io/e1000g/e1000g_osdep.c
48
pci_config_put16(OS_DEP(hw)->cfg_handle, reg, *value);
usr/src/uts/common/io/e1000g/e1000g_osdep.c
52
e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
usr/src/uts/common/io/e1000g/e1000g_osdep.c
55
pci_config_get16(OS_DEP(hw)->cfg_handle, reg);
usr/src/uts/common/io/e1000g/e1000g_osdep.c
69
uint16_t reg; /* register contents */
usr/src/uts/common/io/e1000g/e1000g_osdep.c
91
(void) e1000_read_phy_reg(hw, offset, ®);
usr/src/uts/common/io/e1000g/e1000g_osdep.c
94
reg |= spd_bit; /* enable: set the spd bit */
usr/src/uts/common/io/e1000g/e1000g_osdep.c
96
reg &= ~spd_bit; /* disable: clear the spd bit */
usr/src/uts/common/io/e1000g/e1000g_osdep.c
98
(void) e1000_write_phy_reg(hw, offset, reg);
usr/src/uts/common/io/e1000g/e1000g_stat.c
40
static uint32_t e1000g_read_phy_stat(struct e1000_hw *hw, int reg);
usr/src/uts/common/io/e1000g/e1000g_stat.c
864
e1000g_read_phy_stat(struct e1000_hw *hw, int reg)
usr/src/uts/common/io/e1000g/e1000g_stat.c
873
switch (reg) {
usr/src/uts/common/io/e1000g/e1000g_stat.c
926
val = E1000_READ_REG(hw, reg);
usr/src/uts/common/io/e1000g/e1000g_sw.h
615
} reg;
usr/src/uts/common/io/eedev/eedev.c
580
eedev_create(const eedev_reg_t *reg, eedev_hdl_t **hdlp)
usr/src/uts/common/io/eedev/eedev.c
586
if (reg->ereg_vers != EEDEV_REG_VERS0) {
usr/src/uts/common/io/eedev/eedev.c
590
if (reg->ereg_size == 0 || reg->ereg_dip == NULL ||
usr/src/uts/common/io/eedev/eedev.c
591
reg->ereg_ops == NULL || reg->ereg_ops->eo_read == NULL) {
usr/src/uts/common/io/eedev/eedev.c
595
if (!reg->ereg_ro && reg->ereg_ops->eo_write == NULL) {
usr/src/uts/common/io/eedev/eedev.c
599
if (reg->ereg_seg > reg->ereg_size ||
usr/src/uts/common/io/eedev/eedev.c
600
reg->ereg_read_gran > reg->ereg_size ||
usr/src/uts/common/io/eedev/eedev.c
601
reg->ereg_write_gran > reg->ereg_size) {
usr/src/uts/common/io/eedev/eedev.c
605
if (reg->ereg_name != NULL) {
usr/src/uts/common/io/eedev/eedev.c
606
size_t len = strnlen(reg->ereg_name, EEDEV_NAME_MAX);
usr/src/uts/common/io/eedev/eedev.c
612
if (!ISALNUM(reg->ereg_name[i])) {
usr/src/uts/common/io/eedev/eedev.c
624
dip = eedev_dip_find(reg->ereg_dip);
usr/src/uts/common/io/eedev/eedev.c
626
dip = eedev_dip_create(reg->ereg_dip);
usr/src/uts/common/io/eedev/eedev.c
630
if (reg->ereg_name != NULL) {
usr/src/uts/common/io/eedev/eedev.c
631
name = kmem_asprintf("%s:%d:%s", ddi_driver_name(reg->ereg_dip),
usr/src/uts/common/io/eedev/eedev.c
632
ddi_get_instance(reg->ereg_dip), reg->ereg_name);
usr/src/uts/common/io/eedev/eedev.c
635
ddi_driver_name(reg->ereg_dip),
usr/src/uts/common/io/eedev/eedev.c
636
ddi_get_instance(reg->ereg_dip));
usr/src/uts/common/io/eedev/eedev.c
657
hdl->eh_ops = reg->ereg_ops;
usr/src/uts/common/io/eedev/eedev.c
658
hdl->eh_driver = reg->ereg_driver;
usr/src/uts/common/io/eedev/eedev.c
660
VERIFY3U(hdl->eh_size, ==, reg->ereg_size);
usr/src/uts/common/io/eedev/eedev.c
661
VERIFY3U(hdl->eh_seg, ==, reg->ereg_seg);
usr/src/uts/common/io/eedev/eedev.c
662
VERIFY3U(hdl->eh_read_gran, ==, reg->ereg_read_gran);
usr/src/uts/common/io/eedev/eedev.c
663
VERIFY3U(hdl->eh_write_gran, ==, reg->ereg_write_gran);
usr/src/uts/common/io/eedev/eedev.c
664
if (reg->ereg_max_read != 0) {
usr/src/uts/common/io/eedev/eedev.c
665
VERIFY3U(hdl->eh_max_read, ==, reg->ereg_max_read);
usr/src/uts/common/io/eedev/eedev.c
668
if (reg->ereg_max_write != 0) {
usr/src/uts/common/io/eedev/eedev.c
669
VERIFY3U(hdl->eh_max_write, ==, reg->ereg_max_write);
usr/src/uts/common/io/eedev/eedev.c
675
hdl->eh_driver = reg->ereg_driver;
usr/src/uts/common/io/eedev/eedev.c
678
hdl->eh_ops = reg->ereg_ops;
usr/src/uts/common/io/eedev/eedev.c
686
hdl->eh_ops = reg->ereg_ops;
usr/src/uts/common/io/eedev/eedev.c
687
hdl->eh_driver = reg->ereg_driver;
usr/src/uts/common/io/eedev/eedev.c
688
hdl->eh_size = reg->ereg_size;
usr/src/uts/common/io/eedev/eedev.c
689
hdl->eh_seg = reg->ereg_seg;
usr/src/uts/common/io/eedev/eedev.c
690
hdl->eh_read_gran = reg->ereg_read_gran;
usr/src/uts/common/io/eedev/eedev.c
691
hdl->eh_write_gran = reg->ereg_write_gran;
usr/src/uts/common/io/eedev/eedev.c
692
hdl->eh_max_read = reg->ereg_max_read;
usr/src/uts/common/io/eedev/eedev.c
693
hdl->eh_max_write = reg->ereg_max_write;
usr/src/uts/common/io/eedev/eedev.c
704
if (reg->ereg_ro) {
usr/src/uts/common/io/efe/efe.c
498
efe_mii_read(void *arg, uint8_t phy, uint8_t reg)
usr/src/uts/common/io/efe/efe.c
503
reg << MMCTL_PHYREG | phy << MMCTL_PHYADDR);
usr/src/uts/common/io/efe/efe.c
517
efe_mii_write(void *arg, uint8_t phy, uint8_t reg, uint16_t data)
usr/src/uts/common/io/efe/efe.c
524
reg << MMCTL_PHYREG | phy << MMCTL_PHYADDR);
usr/src/uts/common/io/efe/efe.h
312
#define GETCSR(efep, reg) \
usr/src/uts/common/io/efe/efe.h
314
(efep)->efe_regs + ((reg) / sizeof (uint32_t)))
usr/src/uts/common/io/efe/efe.h
316
#define PUTCSR(efep, reg, val) \
usr/src/uts/common/io/efe/efe.h
318
(efep)->efe_regs + ((reg) / sizeof (uint32_t)), (val))
usr/src/uts/common/io/efe/efe.h
320
#define CLRBIT(efep, reg, bit) \
usr/src/uts/common/io/efe/efe.h
321
PUTCSR(efep, reg, (GETCSR(efep, reg) & ~(bit)))
usr/src/uts/common/io/efe/efe.h
323
#define SETBIT(efep, reg, bit) \
usr/src/uts/common/io/efe/efe.h
324
PUTCSR(efep, reg, (GETCSR(efep, reg) | (bit)))
usr/src/uts/common/io/elxl/elxl.c
2056
elxl_mii_read(void *arg, uint8_t phy, uint8_t reg)
usr/src/uts/common/io/elxl/elxl.c
2073
ex_mii_send_bits(sc, reg, 5);
usr/src/uts/common/io/elxl/elxl.c
2108
elxl_mii_write(void *arg, uint8_t phy, uint8_t reg, uint16_t data)
usr/src/uts/common/io/elxl/elxl.c
2122
ex_mii_send_bits(sc, reg, 5);
usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_hba.c
3002
uint32_t reg;
usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_hba.c
3022
reg = ddi_get32(hba->pci_acc_handle,
usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_hba.c
3025
id = ((reg >> PCI_CAP_ID_SHIFT) & PCI_CAP_ID_MASK);
usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_hba.c
3026
next = ((reg >> PCI_CAP_NEXT_PTR_SHIFT) &
usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_hba.c
3066
reg = ddi_get32(hba->pci_acc_handle,
usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_hba.c
3069
eid = ((reg >> PCIE_EXT_CAP_ID_SHIFT) & PCIE_EXT_CAP_ID_MASK);
usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_hba.c
3070
eversion = ((reg >> PCIE_EXT_CAP_VER_SHIFT) &
usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_hba.c
3072
enext = ((reg >> PCIE_EXT_CAP_NEXT_PTR_SHIFT) &
usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_sli3.c
4747
uint32_t reg;
usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_sli3.c
4764
reg = (ha_copy >> (ring_no * 4)) & 0x0f;
usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_sli3.c
5018
if (reg & HA_R0RE_REQ) {
usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_sli3.c
5037
if ((reg & HA_R0CE_RSP) || hba->channel_tx_count) {
usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_solaris.c
1407
uint16_t reg;
usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_solaris.c
1415
reg = ddi_get16(hba->pci_acc_handle,
usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_solaris.c
1420
reg &= ~1;
usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_solaris.c
1426
reg);
usr/src/uts/common/io/fibre-channel/fca/oce/oce_intr.c
221
uint32_t reg;
usr/src/uts/common/io/fibre-channel/fca/oce/oce_intr.c
223
reg = OCE_CFG_READ32(dev, PCICFG_INTR_CTRL);
usr/src/uts/common/io/fibre-channel/fca/oce/oce_intr.c
224
reg |= HOSTINTR_MASK;
usr/src/uts/common/io/fibre-channel/fca/oce/oce_intr.c
225
OCE_CFG_WRITE32(dev, PCICFG_INTR_CTRL, reg);
usr/src/uts/common/io/fibre-channel/fca/oce/oce_intr.c
260
uint32_t reg;
usr/src/uts/common/io/fibre-channel/fca/oce/oce_intr.c
262
reg = OCE_CFG_READ32(dev, PCICFG_INTR_CTRL);
usr/src/uts/common/io/fibre-channel/fca/oce/oce_intr.c
263
reg &= ~HOSTINTR_MASK;
usr/src/uts/common/io/fibre-channel/fca/oce/oce_intr.c
264
OCE_CFG_WRITE32(dev, PCICFG_INTR_CTRL, reg);
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
16268
ql_read_regs(ql_adapter_state_t *ha, void *buf, void *reg, uint32_t count,
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
16278
reg32 = reg;
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
16285
reg16 = reg;
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
16292
reg8 = reg;
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
19238
pci_regspec_t *reg, *reg2;
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
19254
DDI_PROP_DONTPASS, "reg", (int **)®, &rlen)) !=
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
19263
reg2 = reg;
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
19282
reg2 = reg;
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
19287
if ((caddr_t)reg2 >= (caddr_t)reg + rlen) {
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
19288
reg2 = reg;
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
19294
bcopy(reg, nreg, rlen);
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
19314
ddi_prop_free(reg);
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
22063
uint8_t *reg = (uint8_t *)ha->iobase + entry->pci_offset;
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
22092
*bp++ = RD_REG_BYTE(ha, reg++);
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
22105
uint8_t *reg = (uint8_t *)ha->iobase + entry->pci_offset;
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
22122
WRT_REG_DWORD(ha, reg, entry->data);
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
22134
uint8_t *reg = (uint8_t *)ha->iobase + entry->pci_offset;
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
22166
*bp++ = RD_REG_BYTE(ha, reg++);
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
22180
uint8_t *reg = (uint8_t *)ha->iobase + entry->pci_offset;
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
22202
WRT_REG_WORD(ha, reg, data);
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
22214
uint8_t *reg = (uint8_t *)ha->iobase + entry->addr;
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
22217
(void *)reg);
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
22238
*bp++ = RD_REG_BYTE(ha, reg++);
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
22249
uint8_t *reg = (uint8_t *)ha->iobase + entry->addr;
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
22252
entry->addr, entry->data, (void *)reg);
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
22265
WRT_REG_DWORD(ha, reg, entry->data);
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
22620
uint8_t *reg = (uint8_t *)ha->iobase + 0xc4;
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
22649
*bp++ = RD_REG_BYTE(ha, reg + i);
usr/src/uts/common/io/fibre-channel/fca/qlge/qlge.c
342
ql_wait_reg_rdy(qlge_t *qlge, uint32_t reg, uint32_t bit, uint32_t err_bit)
usr/src/uts/common/io/fibre-channel/fca/qlge/qlge.c
348
temp = ql_read_reg(qlge, reg);
usr/src/uts/common/io/fibre-channel/fca/qlge/qlge.c
359
"Waiting for reg %x to come ready failed.", reg);
usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_dbg.c
1017
if (iocp->ioc_count != sizeof (*reg)) {
usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_dbg.c
1020
ql_write_reg(qlge, reg->addr, reg->value);
usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_dbg.c
113
ql_read_reg(qlge_t *qlge, uint32_t reg)
usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_dbg.c
115
uint32_t data = ql_get32(qlge, reg);
usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_dbg.c
124
ql_write_reg(qlge_t *qlge, uint32_t reg, uint32_t data)
usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_dbg.c
126
ql_put32(qlge, reg, data);
usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_dbg.c
147
ql_wait_reg_bit(qlge_t *qlge, uint32_t reg, uint32_t wait_bit, int set,
usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_dbg.c
164
reg_status = ql_read_reg(qlge, reg);
usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_dbg.c
182
qlge->instance, reg, wait_bit);
usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_dbg.c
1824
ql_read_serdes_reg(qlge_t *qlge, uint32_t reg, uint32_t *data)
usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_dbg.c
1833
ql_write_reg(qlge, REG_XG_SERDES_ADDR, reg | PROC_ADDR_R);
usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_dbg.c
960
struct ql_device_reg *reg;
usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_dbg.c
995
reg = (struct ql_device_reg *)(void *)dmp->b_rptr;
usr/src/uts/common/io/hme/hme.c
351
#define GET_MIFREG(reg) \
usr/src/uts/common/io/hme/hme.c
352
ddi_get32(hmep->hme_mifregh, (uint32_t *)&hmep->hme_mifregp->reg)
usr/src/uts/common/io/hme/hme.c
353
#define PUT_MIFREG(reg, value) \
usr/src/uts/common/io/hme/hme.c
354
ddi_put32(hmep->hme_mifregh, (uint32_t *)&hmep->hme_mifregp->reg, value)
usr/src/uts/common/io/hme/hme.c
356
#define GET_ETXREG(reg) \
usr/src/uts/common/io/hme/hme.c
357
ddi_get32(hmep->hme_etxregh, (uint32_t *)&hmep->hme_etxregp->reg)
usr/src/uts/common/io/hme/hme.c
358
#define PUT_ETXREG(reg, value) \
usr/src/uts/common/io/hme/hme.c
359
ddi_put32(hmep->hme_etxregh, (uint32_t *)&hmep->hme_etxregp->reg, value)
usr/src/uts/common/io/hme/hme.c
360
#define GET_ERXREG(reg) \
usr/src/uts/common/io/hme/hme.c
361
ddi_get32(hmep->hme_erxregh, (uint32_t *)&hmep->hme_erxregp->reg)
usr/src/uts/common/io/hme/hme.c
362
#define PUT_ERXREG(reg, value) \
usr/src/uts/common/io/hme/hme.c
363
ddi_put32(hmep->hme_erxregh, (uint32_t *)&hmep->hme_erxregp->reg, value)
usr/src/uts/common/io/hme/hme.c
364
#define GET_MACREG(reg) \
usr/src/uts/common/io/hme/hme.c
365
ddi_get32(hmep->hme_bmacregh, (uint32_t *)&hmep->hme_bmacregp->reg)
usr/src/uts/common/io/hme/hme.c
366
#define PUT_MACREG(reg, value) \
usr/src/uts/common/io/hme/hme.c
368
(uint32_t *)&hmep->hme_bmacregp->reg, value)
usr/src/uts/common/io/hme/hme.c
369
#define GET_GLOBREG(reg) \
usr/src/uts/common/io/hme/hme.c
370
ddi_get32(hmep->hme_globregh, (uint32_t *)&hmep->hme_globregp->reg)
usr/src/uts/common/io/hme/hme.c
371
#define PUT_GLOBREG(reg, value) \
usr/src/uts/common/io/hme/hme.c
373
(uint32_t *)&hmep->hme_globregp->reg, value)
usr/src/uts/common/io/hme/hme.c
952
int reg;
usr/src/uts/common/io/hme/hme.c
975
reg = regs[0];
usr/src/uts/common/io/hme/hme.c
983
if ((PCI_REG_BUS_G(reg) != rom->bus) ||
usr/src/uts/common/io/hme/hme.c
984
(PCI_REG_DEV_G(reg) != rom->dev) ||
usr/src/uts/common/io/hme/hme.c
985
(PCI_REG_FUNC_G(reg) != 0)) {
usr/src/uts/common/io/hxge/hpi_rxdma.h
110
#define RXDMA_REG_READ64(handle, reg, channel, data_p) {\
usr/src/uts/common/io/hxge/hpi_rxdma.h
111
HXGE_REG_RD64(handle, (HXGE_RXDMA_OFFSET(reg, handle.is_vraddr,\
usr/src/uts/common/io/hxge/hpi_rxdma.h
115
#define RXDMA_REG_READ32(handle, reg, channel, data_p) \
usr/src/uts/common/io/hxge/hpi_rxdma.h
116
HXGE_REG_RD32(handle, (HXGE_RXDMA_OFFSET(reg, handle.is_vraddr,\
usr/src/uts/common/io/hxge/hpi_rxdma.h
119
#define RXDMA_REG_WRITE64(handle, reg, channel, data) {\
usr/src/uts/common/io/hxge/hpi_rxdma.h
120
HXGE_REG_WR64(handle, (HXGE_RXDMA_OFFSET(reg, handle.is_vraddr,\
usr/src/uts/common/io/hxge/hpi_txdma.h
51
#define TXDMA_REG_READ64(handle, reg, channel, val_p) \
usr/src/uts/common/io/hxge/hpi_txdma.h
53
(HXGE_TXDMA_OFFSET(reg, handle.is_vraddr, channel)), val_p)
usr/src/uts/common/io/hxge/hpi_txdma.h
55
#define TXDMA_REG_WRITE64(handle, reg, channel, data) \
usr/src/uts/common/io/hxge/hpi_txdma.h
57
HXGE_TXDMA_OFFSET(reg, handle.is_vraddr, channel), data)
usr/src/uts/common/io/i2c/ctrl/i2csim/i2csim.c
574
i2c_ctrl_register_t *reg;
usr/src/uts/common/io/i2c/ctrl/i2csim/i2csim.c
576
ret = i2c_ctrl_register_alloc(I2C_CTRL_PROVIDER, ®);
usr/src/uts/common/io/i2c/ctrl/i2csim/i2csim.c
583
reg->ic_type = i2csim_ctrls[i].isc_type;
usr/src/uts/common/io/i2c/ctrl/i2csim/i2csim.c
584
reg->ic_nports = i2csim_ctrls[i].isc_nports;
usr/src/uts/common/io/i2c/ctrl/i2csim/i2csim.c
585
reg->ic_name = i2csim_ctrls[i].isc_name;
usr/src/uts/common/io/i2c/ctrl/i2csim/i2csim.c
586
reg->ic_dip = i2csim.sim_dip;
usr/src/uts/common/io/i2c/ctrl/i2csim/i2csim.c
587
reg->ic_drv = (void *)&i2csim_ctrls[i];
usr/src/uts/common/io/i2c/ctrl/i2csim/i2csim.c
588
reg->ic_ops = i2csim_ctrls[i].isc_ops;
usr/src/uts/common/io/i2c/ctrl/i2csim/i2csim.c
590
ret = i2c_ctrl_register(reg, &i2csim.sim_hdls[i]);
usr/src/uts/common/io/i2c/ctrl/i2csim/i2csim.c
591
i2c_ctrl_register_free(reg);
usr/src/uts/common/io/i2c/ctrl/ismt/ismt.c
1001
ret = i2c_ctrl_register(reg, &ismt->ismt_hdl);
usr/src/uts/common/io/i2c/ctrl/ismt/ismt.c
1002
i2c_ctrl_register_free(reg);
usr/src/uts/common/io/i2c/ctrl/ismt/ismt.c
187
ismt_read32(ismt_t *ismt, uint32_t reg)
usr/src/uts/common/io/i2c/ctrl/ismt/ismt.c
189
ASSERT3U(reg, <, ismt->ismt_regsize);
usr/src/uts/common/io/i2c/ctrl/ismt/ismt.c
191
reg)));
usr/src/uts/common/io/i2c/ctrl/ismt/ismt.c
195
ismt_write32(ismt_t *ismt, uint32_t reg, uint32_t val)
usr/src/uts/common/io/i2c/ctrl/ismt/ismt.c
197
ASSERT3U(reg, <, ismt->ismt_regsize);
usr/src/uts/common/io/i2c/ctrl/ismt/ismt.c
198
ddi_put32(ismt->ismt_regs, (uint32_t *)(ismt->ismt_base + reg), val);
usr/src/uts/common/io/i2c/ctrl/ismt/ismt.c
202
ismt_write64(ismt_t *ismt, uint32_t reg, uint64_t val)
usr/src/uts/common/io/i2c/ctrl/ismt/ismt.c
204
ASSERT3U(reg, <, ismt->ismt_regsize);
usr/src/uts/common/io/i2c/ctrl/ismt/ismt.c
205
ddi_put64(ismt->ismt_regs, (uint64_t *)(ismt->ismt_base + reg), val);
usr/src/uts/common/io/i2c/ctrl/ismt/ismt.c
986
i2c_ctrl_register_t *reg;
usr/src/uts/common/io/i2c/ctrl/ismt/ismt.c
988
ret = i2c_ctrl_register_alloc(I2C_CTRL_PROVIDER, ®);
usr/src/uts/common/io/i2c/ctrl/ismt/ismt.c
995
reg->ic_type = I2C_CTRL_TYPE_SMBUS;
usr/src/uts/common/io/i2c/ctrl/ismt/ismt.c
996
reg->ic_nports = 1;
usr/src/uts/common/io/i2c/ctrl/ismt/ismt.c
997
reg->ic_dip = ismt->ismt_dip;
usr/src/uts/common/io/i2c/ctrl/ismt/ismt.c
998
reg->ic_drv = ismt;
usr/src/uts/common/io/i2c/ctrl/ismt/ismt.c
999
reg->ic_ops = &ismt_ctrl_ops;
usr/src/uts/common/io/i2c/ctrl/pchsmbus/pchsmbus.c
1059
i2c_ctrl_register_t *reg;
usr/src/uts/common/io/i2c/ctrl/pchsmbus/pchsmbus.c
1061
ret = i2c_ctrl_register_alloc(I2C_CTRL_PROVIDER, ®);
usr/src/uts/common/io/i2c/ctrl/pchsmbus/pchsmbus.c
1068
reg->ic_type = I2C_CTRL_TYPE_SMBUS;
usr/src/uts/common/io/i2c/ctrl/pchsmbus/pchsmbus.c
1069
reg->ic_nports = 1;
usr/src/uts/common/io/i2c/ctrl/pchsmbus/pchsmbus.c
1070
reg->ic_dip = pch->ps_dip;
usr/src/uts/common/io/i2c/ctrl/pchsmbus/pchsmbus.c
1071
reg->ic_drv = pch;
usr/src/uts/common/io/i2c/ctrl/pchsmbus/pchsmbus.c
1072
reg->ic_ops = &pchsmbus_ctrl_ops;
usr/src/uts/common/io/i2c/ctrl/pchsmbus/pchsmbus.c
1074
ret = i2c_ctrl_register(reg, &pch->ps_hdl);
usr/src/uts/common/io/i2c/ctrl/pchsmbus/pchsmbus.c
1075
i2c_ctrl_register_free(reg);
usr/src/uts/common/io/i2c/eeprom/at24c/at24c.c
201
uint32_t idx, reg;
usr/src/uts/common/io/i2c/eeprom/at24c/at24c.c
205
at24c_page_to_addr(at, page, pageoff, &idx, ®);
usr/src/uts/common/io/i2c/eeprom/at24c/at24c.c
207
if (i2c_reg_get(NULL, at->at_regs[idx], reg, at->at_buf, nbytes,
usr/src/uts/common/io/i2c/eeprom/at24c/at24c.c
212
"client %u, addr 0x%x: 0x%x/0x%x", nbytes, idx, reg,
usr/src/uts/common/io/i2c/eeprom/at24c/at24c.c
241
uint32_t idx, reg;
usr/src/uts/common/io/i2c/eeprom/at24c/at24c.c
245
at24c_page_to_addr(at, page, pageoff, &idx, ®);
usr/src/uts/common/io/i2c/eeprom/at24c/at24c.c
253
if (!i2c_reg_put(NULL, at->at_regs[idx], reg, at->at_buf, nbytes,
usr/src/uts/common/io/i2c/eeprom/at24c/at24c.c
256
"client %u, addr 0x%x: 0x%x/0x%x", nbytes, idx, reg,
usr/src/uts/common/io/i2c/eeprom/at24c/at24c.c
282
reg, err.i2c_error, err.i2c_ctrl);
usr/src/uts/common/io/i2c/eeprom/at24c/at24c.c
289
"on client %u, addr 0x%x: 0x%x/0x%x", idx, reg,
usr/src/uts/common/io/i2c/eeprom/at24c/at24c.c
393
eedev_reg_t reg;
usr/src/uts/common/io/i2c/eeprom/at24c/at24c.c
395
bzero(®, sizeof (reg));
usr/src/uts/common/io/i2c/eeprom/at24c/at24c.c
396
reg.ereg_vers = EEDEV_REG_VERS0;
usr/src/uts/common/io/i2c/eeprom/at24c/at24c.c
397
reg.ereg_size = at->at_ident->ati_size;
usr/src/uts/common/io/i2c/eeprom/at24c/at24c.c
404
reg.ereg_seg = at->at_ident->ati_page;
usr/src/uts/common/io/i2c/eeprom/at24c/at24c.c
405
reg.ereg_read_gran = 1;
usr/src/uts/common/io/i2c/eeprom/at24c/at24c.c
406
reg.ereg_write_gran = 1;
usr/src/uts/common/io/i2c/eeprom/at24c/at24c.c
415
reg.ereg_max_read = MIN(i2c_reg_max_read(at->at_regs[0]), AT24C_MAX_IO);
usr/src/uts/common/io/i2c/eeprom/at24c/at24c.c
416
reg.ereg_max_write = MIN(i2c_reg_max_write(at->at_regs[0]),
usr/src/uts/common/io/i2c/eeprom/at24c/at24c.c
418
reg.ereg_max_write = MIN(reg.ereg_max_write, at->at_ident->ati_page);
usr/src/uts/common/io/i2c/eeprom/at24c/at24c.c
419
reg.ereg_dip = at->at_dip;
usr/src/uts/common/io/i2c/eeprom/at24c/at24c.c
420
reg.ereg_driver = at;
usr/src/uts/common/io/i2c/eeprom/at24c/at24c.c
421
reg.ereg_ops = &at24c_eedev_ops;
usr/src/uts/common/io/i2c/eeprom/at24c/at24c.c
423
if ((ret = eedev_create(®, &at->at_eedev)) != 0) {
usr/src/uts/common/io/i2c/eeprom/ee100x/ee100x.c
211
eedev_reg_t reg;
usr/src/uts/common/io/i2c/eeprom/ee100x/ee100x.c
213
bzero(®, sizeof (reg));
usr/src/uts/common/io/i2c/eeprom/ee100x/ee100x.c
214
reg.ereg_vers = EEDEV_REG_VERS;
usr/src/uts/common/io/i2c/eeprom/ee100x/ee100x.c
215
reg.ereg_size = EE1004_LEN;
usr/src/uts/common/io/i2c/eeprom/ee100x/ee100x.c
216
reg.ereg_seg = EE1004_SEG;
usr/src/uts/common/io/i2c/eeprom/ee100x/ee100x.c
217
reg.ereg_read_gran = 1;
usr/src/uts/common/io/i2c/eeprom/ee100x/ee100x.c
218
reg.ereg_ro = true;
usr/src/uts/common/io/i2c/eeprom/ee100x/ee100x.c
219
reg.ereg_dip = ee->ee_dip;
usr/src/uts/common/io/i2c/eeprom/ee100x/ee100x.c
220
reg.ereg_driver = ee;
usr/src/uts/common/io/i2c/eeprom/ee100x/ee100x.c
221
reg.ereg_name = NULL;
usr/src/uts/common/io/i2c/eeprom/ee100x/ee100x.c
222
reg.ereg_ops = &ee100x_eedev_ops;
usr/src/uts/common/io/i2c/eeprom/ee100x/ee100x.c
223
reg.ereg_max_read = MIN(i2c_reg_max_read(ee->ee_mem_hdl),
usr/src/uts/common/io/i2c/eeprom/ee100x/ee100x.c
226
if ((ret = eedev_create(®, &ee->ee_devhdl)) != 0) {
usr/src/uts/common/io/i2c/eeprom/spd511x/spd511x.c
342
eedev_reg_t reg;
usr/src/uts/common/io/i2c/eeprom/spd511x/spd511x.c
344
bzero(®, sizeof (reg));
usr/src/uts/common/io/i2c/eeprom/spd511x/spd511x.c
345
reg.ereg_vers = EEDEV_REG_VERS;
usr/src/uts/common/io/i2c/eeprom/spd511x/spd511x.c
346
reg.ereg_size = HUB_NVM_NPAGES * HUB_NVM_PAGE_SIZE;
usr/src/uts/common/io/i2c/eeprom/spd511x/spd511x.c
347
reg.ereg_seg = HUB_NVM_PAGE_SIZE;
usr/src/uts/common/io/i2c/eeprom/spd511x/spd511x.c
348
reg.ereg_read_gran = 1;
usr/src/uts/common/io/i2c/eeprom/spd511x/spd511x.c
349
reg.ereg_ro = true;
usr/src/uts/common/io/i2c/eeprom/spd511x/spd511x.c
350
reg.ereg_dip = spd->spd_dip;
usr/src/uts/common/io/i2c/eeprom/spd511x/spd511x.c
351
reg.ereg_driver = spd;
usr/src/uts/common/io/i2c/eeprom/spd511x/spd511x.c
352
reg.ereg_name = NULL;
usr/src/uts/common/io/i2c/eeprom/spd511x/spd511x.c
353
reg.ereg_ops = &spd5118_eedev_ops;
usr/src/uts/common/io/i2c/eeprom/spd511x/spd511x.c
354
reg.ereg_max_read = MIN(i2c_reg_max_read(spd->spd_regs),
usr/src/uts/common/io/i2c/eeprom/spd511x/spd511x.c
357
if ((ret = eedev_create(®, &spd->spd_eehdl)) != 0) {
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
115
const pca953x_regs_t reg, uint8_t *regp, uint8_t *bitp)
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
123
*regp = pca->pca_ident->pi_nbanks * reg + gpio_id / NBBY;
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
131
uint8_t reg;
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
142
pca953x_gpio_to_reg_bit(pca, gpio_id, PCA953X_R_INPUT, ®, NULL);
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
143
if (inp != NULL && !i2c_reg_get(*txnp, pca->pca_regs, reg, inp,
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
146
"register 0x%x: 0x%x/0x%x", reg, err.i2c_error,
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
151
pca953x_gpio_to_reg_bit(pca, gpio_id, PCA953X_R_OUTPUT, ®, NULL);
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
152
if (outp != NULL && !i2c_reg_get(*txnp, pca->pca_regs, reg, outp,
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
155
"register 0x%x: 0x%x/0x%x", reg, err.i2c_error,
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
160
pca953x_gpio_to_reg_bit(pca, gpio_id, PCA953X_R_POLARITY, ®, NULL);
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
161
if (polp != NULL && !i2c_reg_get(*txnp, pca->pca_regs, reg, polp,
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
164
"register 0x%x: 0x%x/0x%x", reg, err.i2c_error,
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
168
pca953x_gpio_to_reg_bit(pca, gpio_id, PCA953X_R_CONFIG, ®, NULL);
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
169
if (cfgp != NULL && !i2c_reg_get(*txnp, pca->pca_regs, reg, cfgp,
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
172
"register 0x%x: 0x%x/0x%x", reg, err.i2c_error,
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
190
uint8_t reg;
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
193
pca953x_gpio_to_reg_bit(pca, gpio_id, PCA953X_R_OUTPUT, ®, NULL);
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
194
if (out != nout && i2c_reg_put(txn, pca->pca_regs, reg, &nout,
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
197
"register 0x%x: 0x%x/0x%x", reg, err.i2c_error,
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
202
pca953x_gpio_to_reg_bit(pca, gpio_id, PCA953X_R_POLARITY, ®, NULL);
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
203
if (pol != npol && i2c_reg_put(txn, pca->pca_regs, reg, &npol,
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
206
"register 0x%x: 0x%x/0x%x", reg, err.i2c_error,
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
211
pca953x_gpio_to_reg_bit(pca, gpio_id, PCA953X_R_CONFIG, ®, NULL);
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
212
if (cfg != ncfg && i2c_reg_put(txn, pca->pca_regs, reg, &ncfg,
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
215
"register 0x%x: 0x%x/0x%x", reg, err.i2c_error,
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
518
uint8_t reg, bit, val;
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
521
pca953x_gpio_to_reg_bit(pca, gpio_id, PCA953X_R_INPUT, ®, &bit);
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
522
if (!i2c_reg_get(NULL, pca->pca_regs, reg, &val, sizeof (val), &err)) {
usr/src/uts/common/io/i2c/gpio/pca953x/pca953x.c
524
"register 0x%x: 0x%x/0x%x", reg, err.i2c_error,
usr/src/uts/common/io/i2c/nexus/i2cnex_client.c
328
int *reg;
usr/src/uts/common/io/i2c/nexus/i2cnex_client.c
339
"reg", ®, &nreg) != DDI_PROP_SUCCESS) {
usr/src/uts/common/io/i2c/nexus/i2cnex_client.c
344
ddi_prop_free(reg);
usr/src/uts/common/io/i2c/nexus/i2cnex_client.c
348
addr.ia_type = reg[regno * 2];
usr/src/uts/common/io/i2c/nexus/i2cnex_client.c
349
addr.ia_addr = reg[regno * 2 + 1];
usr/src/uts/common/io/i2c/nexus/i2cnex_client.c
350
ddi_prop_free(reg);
usr/src/uts/common/io/i2c/nexus/i2cnex_client.c
374
int *reg;
usr/src/uts/common/io/i2c/nexus/i2cnex_client.c
404
"reg", ®, &nreg) != DDI_PROP_SUCCESS) {
usr/src/uts/common/io/i2c/nexus/i2cnex_client.c
408
if (reg[i * 2] == addr->ia_type && reg[i * 2 + 1] ==
usr/src/uts/common/io/i2c/nexus/i2cnex_client.c
417
ddi_prop_free(reg);
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
204
i2c_ctrl_register_free(i2c_ctrl_register_t *reg)
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
206
if (reg == NULL)
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
208
kmem_free(reg, sizeof (i2c_ctrl_register_t));
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
214
i2c_ctrl_register_t *reg;
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
220
reg = kmem_zalloc(sizeof (i2c_ctrl_register_t), KM_SLEEP);
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
221
reg->ic_vers = I2C_CTRL_PROVIDER_V0;
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
223
*regp = reg;
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
436
i2c_ctrl_register(const i2c_ctrl_register_t *reg, i2c_ctrl_hdl_t **hdlp)
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
442
if (reg == NULL || hdlp == NULL) {
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
446
if (reg->ic_vers != I2C_CTRL_PROVIDER_V0) {
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
450
if (reg->ic_ops == NULL) {
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
454
if (reg->ic_ops->i2c_port_name_f == NULL) {
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
458
if (reg->ic_ops->i2c_prop_info_f == NULL) {
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
462
if (reg->ic_ops->i2c_prop_get_f == NULL) {
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
466
switch (reg->ic_type) {
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
468
if (reg->ic_ops->i2c_io_i2c_f == NULL) {
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
473
if (reg->ic_ops->i2c_io_smbus_f == NULL) {
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
483
if (reg->ic_dip == NULL) {
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
487
if (reg->ic_nports == 0 || reg->ic_nports > I2C_MAX_PORTS) {
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
491
if (reg->ic_name != NULL) {
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
492
size_t len = strnlen(reg->ic_name, I2C_NAME_MAX);
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
498
if (len == 0 || reg->ic_name[len] != '\0') {
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
503
if (!ISALNUM(reg->ic_name[i])) {
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
507
namep = reg->ic_name;
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
510
ddi_driver_name(reg->ic_dip),
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
511
ddi_get_instance(reg->ic_dip)) >= sizeof (name)) {
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
518
if (devopsp[ddi_driver_major(reg->ic_dip)]->devo_bus_ops !=
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
536
ctrl->ic_drv = reg->ic_drv;
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
537
ctrl->ic_ops = reg->ic_ops;
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
538
ctrl->ic_type = reg->ic_type;
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
539
ctrl->ic_nexus = i2cnex_nex_alloc(I2C_NEXUS_T_CTRL, reg->ic_dip, NULL,
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
555
ctrl->ic_nports = reg->ic_nports;
usr/src/uts/common/io/i2c/nexus/i2cnex_ctrl.c
556
i2c_root_t *root = i2c_root_init(reg->ic_dip);
usr/src/uts/common/io/i2c/nexus/i2cnex_mux.c
137
i2c_mux_register(const i2c_mux_register_t *reg, i2c_mux_hdl_t **muxp)
usr/src/uts/common/io/i2c/nexus/i2cnex_mux.c
142
if (reg->mr_vers != I2C_MUX_PROVIDER_V0) {
usr/src/uts/common/io/i2c/nexus/i2cnex_mux.c
146
if (reg->mr_nports == 0 || reg->mr_nports > I2C_MAX_PORTS) {
usr/src/uts/common/io/i2c/nexus/i2cnex_mux.c
150
if (reg->mr_dip == NULL) {
usr/src/uts/common/io/i2c/nexus/i2cnex_mux.c
154
if (devopsp[ddi_driver_major(reg->mr_dip)]->devo_bus_ops !=
usr/src/uts/common/io/i2c/nexus/i2cnex_mux.c
159
if (reg->mr_ops == NULL ||
usr/src/uts/common/io/i2c/nexus/i2cnex_mux.c
160
reg->mr_ops->mux_port_name_f == NULL ||
usr/src/uts/common/io/i2c/nexus/i2cnex_mux.c
161
reg->mr_ops->mux_port_enable_f == NULL ||
usr/src/uts/common/io/i2c/nexus/i2cnex_mux.c
162
reg->mr_ops->mux_port_disable_f == NULL) {
usr/src/uts/common/io/i2c/nexus/i2cnex_mux.c
166
if (snprintf(name, sizeof (name), "%s%d", ddi_driver_name(reg->mr_dip),
usr/src/uts/common/io/i2c/nexus/i2cnex_mux.c
167
ddi_get_instance(reg->mr_dip)) >= sizeof (name)) {
usr/src/uts/common/io/i2c/nexus/i2cnex_mux.c
179
if (!i2c_dip_is_dev(reg->mr_dip)) {
usr/src/uts/common/io/i2c/nexus/i2cnex_mux.c
183
i2c_nexus_t *nex = i2c_dev_to_nexus(reg->mr_dip);
usr/src/uts/common/io/i2c/nexus/i2cnex_mux.c
186
i2c_txn_t *txn = i2c_txn_alloc(ctrl, I2C_LOCK_TAG_MUX_REG, reg->mr_dip);
usr/src/uts/common/io/i2c/nexus/i2cnex_mux.c
198
mux->im_drv = reg->mr_drv;
usr/src/uts/common/io/i2c/nexus/i2cnex_mux.c
199
mux->im_ops = reg->mr_ops;
usr/src/uts/common/io/i2c/nexus/i2cnex_mux.c
200
mux->im_nports = reg->mr_nports;
usr/src/uts/common/io/i2c/nexus/i2cnex_mux.c
52
i2c_mux_register_free(i2c_mux_register_t *reg)
usr/src/uts/common/io/i2c/nexus/i2cnex_mux.c
54
if (reg == NULL)
usr/src/uts/common/io/i2c/nexus/i2cnex_mux.c
56
kmem_free(reg, sizeof (i2c_mux_register_t));
usr/src/uts/common/io/i2c/nexus/i2cnex_mux.c
71
i2c_mux_register_t *reg;
usr/src/uts/common/io/i2c/nexus/i2cnex_mux.c
77
reg = kmem_zalloc(sizeof (i2c_mux_register_t), KM_SLEEP);
usr/src/uts/common/io/i2c/nexus/i2cnex_mux.c
78
reg->mr_vers = I2C_MUX_PROVIDER_V0;
usr/src/uts/common/io/i2c/nexus/i2cnex_mux.c
79
*regp = reg;
usr/src/uts/common/io/i2c/nexus/i2cnex_user.c
347
int *reg;
usr/src/uts/common/io/i2c/nexus/i2cnex_user.c
365
DDI_PROP_DONTPASS, "reg", ®, &nreg) != DDI_PROP_SUCCESS) {
usr/src/uts/common/io/i2c/nexus/i2cnex_user.c
371
ddi_prop_free(reg);
usr/src/uts/common/io/i2c/nexus/i2cnex_user.c
377
i2c_addr_t addr = { reg[i], reg[i + 1] };
usr/src/uts/common/io/i2c/nexus/i2cnex_user.c
379
ddi_prop_free(reg);
usr/src/uts/common/io/i2c/nexus/i2cnex_user.c
393
ddi_prop_free(reg);
usr/src/uts/common/io/i2c/sensor/tmp43x/tmp43x.c
228
tmp43x_reg_type(tmp43x_reg_t reg)
usr/src/uts/common/io/i2c/sensor/tmp43x/tmp43x.c
230
switch (reg) {
usr/src/uts/common/io/i2c/sensor/tmp43x/tmp43x.c
243
panic("tmp43x programmer error: unknown register 0x%x", reg);
usr/src/uts/common/io/i2c/sensor/tmp43x/tmp43x.c
248
tmp43x_write_ctl(tmp43x_t *tmp, tmp43x_reg_t reg, uint8_t val)
usr/src/uts/common/io/i2c/sensor/tmp43x/tmp43x.c
254
if (tmp->tmp_rinfo[i].tri_reg == reg) {
usr/src/uts/common/io/i2c/sensor/tmp43x/tmp43x.c
262
VERIFY3U(tmp43x_reg_type(reg), ==, TMP43X_REG_TYPE_1B);
usr/src/uts/common/io/i2c/sensor/tmp43x/tmp43x.c
276
tmp43x_read_ctl(tmp43x_t *tmp, tmp43x_reg_t reg, uint8_t *valp)
usr/src/uts/common/io/i2c/sensor/tmp43x/tmp43x.c
282
if (tmp->tmp_rinfo[i].tri_reg == reg) {
usr/src/uts/common/io/i2c/sensor/tmp43x/tmp43x.c
289
VERIFY3U(tmp43x_reg_type(reg), ==, TMP43X_REG_TYPE_1B);
usr/src/uts/common/io/i2c/sensor/tmp43x/tmp43x.c
302
tmp43x_temp_read(tmp43x_t *tmp, tmp43x_reg_t reg, sensor_ioctl_scalar_t *scalar)
usr/src/uts/common/io/i2c/sensor/tmp43x/tmp43x.c
309
if (tmp->tmp_rinfo[i].tri_reg == reg) {
usr/src/uts/common/io/i2c/sensor/tmp43x/tmp43x.c
316
VERIFY3U(tmp43x_reg_type(reg), ==, TMP43X_REG_TYPE_TEMP);
usr/src/uts/common/io/i2c/sensor/tmp43x/tmp43x.c
328
tmp->tmp_raw[reg] = val;
usr/src/uts/common/io/i2c/sensor/tmp43x/tmp43x.c
333
tmp->tmp_temp[reg] = temp;
usr/src/uts/common/io/i40e/core/i40e_adminq.c
302
u32 reg = 0;
usr/src/uts/common/io/i40e/core/i40e_adminq.c
319
reg = rd32(hw, hw->aq.asq.bal);
usr/src/uts/common/io/i40e/core/i40e_adminq.c
320
if (reg != I40E_LO_DWORD(hw->aq.asq.desc_buf.pa))
usr/src/uts/common/io/i40e/core/i40e_adminq.c
335
u32 reg = 0;
usr/src/uts/common/io/i40e/core/i40e_adminq.c
355
reg = rd32(hw, hw->aq.arq.bal);
usr/src/uts/common/io/i40e/core/i40e_adminq.c
356
if (reg != I40E_LO_DWORD(hw->aq.arq.desc_buf.pa))
usr/src/uts/common/io/i40e/core/i40e_common.c
1304
u32 cnt, reg = 0;
usr/src/uts/common/io/i40e/core/i40e_common.c
1307
reg = rd32(hw, I40E_GLGEN_RSTAT);
usr/src/uts/common/io/i40e/core/i40e_common.c
1308
if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
usr/src/uts/common/io/i40e/core/i40e_common.c
1314
DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg);
usr/src/uts/common/io/i40e/core/i40e_common.c
1331
u32 reg = 0;
usr/src/uts/common/io/i40e/core/i40e_common.c
1345
reg = rd32(hw, I40E_GLGEN_RSTAT);
usr/src/uts/common/io/i40e/core/i40e_common.c
1346
if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
usr/src/uts/common/io/i40e/core/i40e_common.c
1350
if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
usr/src/uts/common/io/i40e/core/i40e_common.c
1357
reg = rd32(hw, I40E_GLNVM_ULD);
usr/src/uts/common/io/i40e/core/i40e_common.c
1358
reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
usr/src/uts/common/io/i40e/core/i40e_common.c
1360
if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
usr/src/uts/common/io/i40e/core/i40e_common.c
1367
if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
usr/src/uts/common/io/i40e/core/i40e_common.c
1370
DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
usr/src/uts/common/io/i40e/core/i40e_common.c
1380
reg = rd32(hw, I40E_PFGEN_CTRL);
usr/src/uts/common/io/i40e/core/i40e_common.c
1382
(reg | I40E_PFGEN_CTRL_PFSWR_MASK));
usr/src/uts/common/io/i40e/core/i40e_common.c
1384
reg = rd32(hw, I40E_PFGEN_CTRL);
usr/src/uts/common/io/i40e/core/i40e_common.c
1385
if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
usr/src/uts/common/io/i40e/core/i40e_common.c
1395
} else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
usr/src/uts/common/io/i40e/core/i40e_common.c
6425
u16 reg, u8 phy_addr, u16 *value)
usr/src/uts/common/io/i40e/core/i40e_common.c
6432
command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
usr/src/uts/common/io/i40e/core/i40e_common.c
6470
u16 reg, u8 phy_addr, u16 value)
usr/src/uts/common/io/i40e/core/i40e_common.c
6480
command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
usr/src/uts/common/io/i40e/core/i40e_common.c
6511
u8 page, u16 reg, u8 phy_addr, u16 *value)
usr/src/uts/common/io/i40e/core/i40e_common.c
6518
command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
usr/src/uts/common/io/i40e/core/i40e_common.c
6585
u8 page, u16 reg, u8 phy_addr, u16 value)
usr/src/uts/common/io/i40e/core/i40e_common.c
6592
command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
usr/src/uts/common/io/i40e/core/i40e_common.c
6652
u8 page, u16 reg, u8 phy_addr, u16 value)
usr/src/uts/common/io/i40e/core/i40e_common.c
6659
reg, phy_addr, value);
usr/src/uts/common/io/i40e/core/i40e_common.c
6669
page, reg, phy_addr, value);
usr/src/uts/common/io/i40e/core/i40e_common.c
6690
u8 page, u16 reg, u8 phy_addr, u16 *value)
usr/src/uts/common/io/i40e/core/i40e_common.c
6696
status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
usr/src/uts/common/io/i40e/core/i40e_common.c
6706
status = i40e_read_phy_register_clause45(hw, page, reg,
usr/src/uts/common/io/i40e/core/i40e_dcb.c
48
u32 reg;
usr/src/uts/common/io/i40e/core/i40e_dcb.c
53
reg = rd32(hw, I40E_PRTDCB_GENS);
usr/src/uts/common/io/i40e/core/i40e_dcb.c
54
*status = (u16)((reg & I40E_PRTDCB_GENS_DCBX_STATUS_MASK) >>
usr/src/uts/common/io/i40e/core/i40e_prototype.h
618
u16 reg, u8 phy_addr, u16 *value);
usr/src/uts/common/io/i40e/core/i40e_prototype.h
620
u16 reg, u8 phy_addr, u16 value);
usr/src/uts/common/io/i40e/core/i40e_prototype.h
622
u8 page, u16 reg, u8 phy_addr, u16 *value);
usr/src/uts/common/io/i40e/core/i40e_prototype.h
624
u8 page, u16 reg, u8 phy_addr, u16 value);
usr/src/uts/common/io/i40e/core/i40e_prototype.h
626
u8 page, u16 reg, u8 phy_addr, u16 *value);
usr/src/uts/common/io/i40e/core/i40e_prototype.h
628
u8 page, u16 reg, u8 phy_addr, u16 value);
usr/src/uts/common/io/i40e/i40e_intr.c
214
uint32_t reg;
usr/src/uts/common/io/i40e/i40e_intr.c
216
reg = I40E_PFINT_DYN_CTL0_INTENA_MASK |
usr/src/uts/common/io/i40e/i40e_intr.c
219
I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, reg);
usr/src/uts/common/io/i40e/i40e_intr.c
227
uint32_t reg;
usr/src/uts/common/io/i40e/i40e_intr.c
229
reg = I40E_ITR_INDEX_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT;
usr/src/uts/common/io/i40e/i40e_intr.c
230
I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, reg);
usr/src/uts/common/io/i40e/i40e_intr.c
243
uint32_t reg;
usr/src/uts/common/io/i40e/i40e_intr.c
247
reg = I40E_PFINT_DYN_CTLN_INTENA_MASK |
usr/src/uts/common/io/i40e/i40e_intr.c
250
I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vector - 1), reg);
usr/src/uts/common/io/i40e/i40e_intr.c
256
uint32_t reg;
usr/src/uts/common/io/i40e/i40e_intr.c
260
reg = I40E_ITR_INDEX_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
usr/src/uts/common/io/i40e/i40e_intr.c
261
I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vector - 1), reg);
usr/src/uts/common/io/i40e/i40e_intr.c
279
uint32_t reg;
usr/src/uts/common/io/i40e/i40e_intr.c
282
reg = I40E_READ_REG(hw, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE));
usr/src/uts/common/io/i40e/i40e_intr.c
283
reg |= I40E_QINT_RQCTL_CAUSE_ENA_MASK;
usr/src/uts/common/io/i40e/i40e_intr.c
284
I40E_WRITE_REG(hw, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE), reg);
usr/src/uts/common/io/i40e/i40e_intr.c
286
reg = I40E_READ_REG(hw, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE));
usr/src/uts/common/io/i40e/i40e_intr.c
287
reg |= I40E_QINT_TQCTL_CAUSE_ENA_MASK;
usr/src/uts/common/io/i40e/i40e_intr.c
288
I40E_WRITE_REG(hw, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE), reg);
usr/src/uts/common/io/i40e/i40e_intr.c
307
uint32_t reg;
usr/src/uts/common/io/i40e/i40e_intr.c
310
reg = I40E_READ_REG(hw, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE));
usr/src/uts/common/io/i40e/i40e_intr.c
311
reg &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
usr/src/uts/common/io/i40e/i40e_intr.c
312
I40E_WRITE_REG(hw, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE), reg);
usr/src/uts/common/io/i40e/i40e_intr.c
314
reg = I40E_READ_REG(hw, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE));
usr/src/uts/common/io/i40e/i40e_intr.c
315
reg &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
usr/src/uts/common/io/i40e/i40e_intr.c
316
I40E_WRITE_REG(hw, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE), reg);
usr/src/uts/common/io/i40e/i40e_intr.c
334
uint32_t reg;
usr/src/uts/common/io/i40e/i40e_intr.c
335
reg = I40E_QUEUE_TYPE_EOL;
usr/src/uts/common/io/i40e/i40e_intr.c
336
I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0, reg);
usr/src/uts/common/io/i40e/i40e_intr.c
341
uint32_t reg;
usr/src/uts/common/io/i40e/i40e_intr.c
343
reg = I40E_QUEUE_TYPE_EOL;
usr/src/uts/common/io/i40e/i40e_intr.c
344
I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(i), reg);
usr/src/uts/common/io/i40e/i40e_intr.c
358
uint32_t reg;
usr/src/uts/common/io/i40e/i40e_intr.c
368
reg = I40E_READ_REG(hw, I40E_PFINT_DYN_CTLN(i));
usr/src/uts/common/io/i40e/i40e_intr.c
369
VERIFY0(reg & I40E_PFINT_DYN_CTLN_INTENA_MASK);
usr/src/uts/common/io/i40e/i40e_intr.c
371
reg = I40E_READ_REG(hw, I40E_PFINT_LNKLSTN(i));
usr/src/uts/common/io/i40e/i40e_intr.c
372
VERIFY3U(reg, ==, I40E_QUEUE_TYPE_EOL);
usr/src/uts/common/io/i40e/i40e_intr.c
388
uint32_t reg;
usr/src/uts/common/io/i40e/i40e_intr.c
391
reg = (queue << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
usr/src/uts/common/io/i40e/i40e_intr.c
394
I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(vector), reg);
usr/src/uts/common/io/i40e/i40e_intr.c
395
DEBUGOUT2("PFINT_LNKLSTN[%u] = 0x%x", vector, reg);
usr/src/uts/common/io/i40e/i40e_intr.c
407
uint32_t reg;
usr/src/uts/common/io/i40e/i40e_intr.c
412
reg = (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
usr/src/uts/common/io/i40e/i40e_intr.c
418
I40E_WRITE_REG(hw, I40E_QINT_RQCTL(queue), reg);
usr/src/uts/common/io/i40e/i40e_intr.c
419
DEBUGOUT2("QINT_RQCTL[%u] = 0x%x", queue, reg);
usr/src/uts/common/io/i40e/i40e_intr.c
429
uint32_t reg;
usr/src/uts/common/io/i40e/i40e_intr.c
434
reg = (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
usr/src/uts/common/io/i40e/i40e_intr.c
440
I40E_WRITE_REG(hw, I40E_QINT_TQCTL(queue), reg);
usr/src/uts/common/io/i40e/i40e_intr.c
441
DEBUGOUT2("QINT_TQCTL[%u] = 0x%x", queue, reg);
usr/src/uts/common/io/i40e/i40e_intr.c
496
uint32_t reg;
usr/src/uts/common/io/i40e/i40e_intr.c
501
reg = (I40E_INTR_NOTX_QUEUE << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
usr/src/uts/common/io/i40e/i40e_intr.c
503
I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0, reg);
usr/src/uts/common/io/i40e/i40e_intr.c
505
reg = (I40E_INTR_NOTX_INTR << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
usr/src/uts/common/io/i40e/i40e_intr.c
511
I40E_WRITE_REG(hw, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE), reg);
usr/src/uts/common/io/i40e/i40e_intr.c
513
reg = (I40E_INTR_NOTX_INTR << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
usr/src/uts/common/io/i40e/i40e_intr.c
519
I40E_WRITE_REG(hw, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE), reg);
usr/src/uts/common/io/i40e/i40e_intr.c
530
uint32_t reg;
usr/src/uts/common/io/i40e/i40e_intr.c
537
reg = I40E_READ_REG(hw, I40E_QINT_RQCTL(queue));
usr/src/uts/common/io/i40e/i40e_intr.c
538
ASSERT0(reg & I40E_QINT_RQCTL_CAUSE_ENA_MASK);
usr/src/uts/common/io/i40e/i40e_intr.c
539
reg |= I40E_QINT_RQCTL_CAUSE_ENA_MASK;
usr/src/uts/common/io/i40e/i40e_intr.c
540
I40E_WRITE_REG(hw, I40E_QINT_RQCTL(queue), reg);
usr/src/uts/common/io/i40e/i40e_intr.c
551
uint32_t reg;
usr/src/uts/common/io/i40e/i40e_intr.c
558
reg = I40E_READ_REG(hw, I40E_QINT_RQCTL(queue));
usr/src/uts/common/io/i40e/i40e_intr.c
559
ASSERT3U(reg & I40E_QINT_RQCTL_CAUSE_ENA_MASK, ==,
usr/src/uts/common/io/i40e/i40e_intr.c
561
reg &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
usr/src/uts/common/io/i40e/i40e_intr.c
562
I40E_WRITE_REG(hw, I40E_QINT_RQCTL(queue), reg);
usr/src/uts/common/io/i40e/i40e_intr.c
574
uint32_t reg;
usr/src/uts/common/io/i40e/i40e_intr.c
589
reg = I40E_ITR_INDEX_OTHER << I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT;
usr/src/uts/common/io/i40e/i40e_intr.c
590
I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0, reg);
usr/src/uts/common/io/i40e/i40e_intr.c
598
reg = I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
usr/src/uts/common/io/i40e/i40e_intr.c
599
I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, reg);
usr/src/uts/common/io/i40e/i40e_intr.c
702
uint32_t reg;
usr/src/uts/common/io/i40e/i40e_intr.c
704
reg = I40E_READ_REG(hw, I40E_PFINT_ICR0);
usr/src/uts/common/io/i40e/i40e_intr.c
712
if (reg & I40E_PFINT_ICR0_ADMINQ_MASK)
usr/src/uts/common/io/i40e/i40e_intr.c
719
reg = I40E_READ_REG(hw, I40E_PFINT_ICR0_ENA);
usr/src/uts/common/io/i40e/i40e_intr.c
720
reg |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
usr/src/uts/common/io/i40e/i40e_intr.c
721
I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, reg);
usr/src/uts/common/io/i40e/i40e_intr.c
830
uint32_t reg;
usr/src/uts/common/io/i40e/i40e_intr.c
843
reg = I40E_READ_REG(hw, I40E_PFINT_ICR0);
usr/src/uts/common/io/i40e/i40e_intr.c
851
if (reg == 0) {
usr/src/uts/common/io/i40e/i40e_intr.c
857
if (reg & I40E_PFINT_ICR0_ADMINQ_MASK)
usr/src/uts/common/io/i40e/i40e_intr.c
861
if (reg & I40E_INTR_NOTX_RX_MASK)
usr/src/uts/common/io/i40e/i40e_intr.c
864
if (reg & I40E_INTR_NOTX_TX_MASK)
usr/src/uts/common/io/i40e/i40e_main.c
1687
uint32_t reg;
usr/src/uts/common/io/i40e/i40e_main.c
1701
reg = I40E_READ_REG(hw, I40E_GLPCI_CNF2);
usr/src/uts/common/io/i40e/i40e_main.c
1711
request = (reg & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
usr/src/uts/common/io/i40e/i40e_main.c
2597
uint32_t reg;
usr/src/uts/common/io/i40e/i40e_main.c
2611
reg = I40E_READ_REG(hw, I40E_QRX_ENA(itrq->itrq_index));
usr/src/uts/common/io/i40e/i40e_main.c
2612
if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK))
usr/src/uts/common/io/i40e/i40e_main.c
2614
VERIFY((reg & I40E_QRX_ENA_QENA_REQ_MASK) ==
usr/src/uts/common/io/i40e/i40e_main.c
2616
reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
usr/src/uts/common/io/i40e/i40e_main.c
2617
I40E_WRITE_REG(hw, I40E_QRX_ENA(itrq->itrq_index), reg);
usr/src/uts/common/io/i40e/i40e_main.c
2633
uint32_t reg;
usr/src/uts/common/io/i40e/i40e_main.c
2650
reg = I40E_READ_REG(hw, I40E_QTX_ENA(itrq->itrq_index));
usr/src/uts/common/io/i40e/i40e_main.c
2651
if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) != 0) {
usr/src/uts/common/io/i40e/i40e_main.c
2652
reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
usr/src/uts/common/io/i40e/i40e_main.c
2653
I40E_WRITE_REG(hw, I40E_QTX_ENA(itrq->itrq_index), reg);
usr/src/uts/common/io/i40e/i40e_main.c
2673
uint32_t reg;
usr/src/uts/common/io/i40e/i40e_main.c
2677
reg = I40E_READ_REG(hw, I40E_QRX_ENA(itrq->itrq_index));
usr/src/uts/common/io/i40e/i40e_main.c
2678
if ((reg & I40E_QRX_ENA_QENA_STAT_MASK) == 0)
usr/src/uts/common/io/i40e/i40e_main.c
2683
if ((reg & I40E_QRX_ENA_QENA_STAT_MASK) != 0) {
usr/src/uts/common/io/i40e/i40e_main.c
2690
reg = I40E_READ_REG(hw, I40E_QTX_ENA(itrq->itrq_index));
usr/src/uts/common/io/i40e/i40e_main.c
2691
if ((reg & I40E_QTX_ENA_QENA_STAT_MASK) == 0)
usr/src/uts/common/io/i40e/i40e_main.c
2696
if ((reg & I40E_QTX_ENA_QENA_STAT_MASK) != 0) {
usr/src/uts/common/io/i40e/i40e_main.c
2854
uint32_t reg;
usr/src/uts/common/io/i40e/i40e_main.c
2879
reg = I40E_READ_REG(hw, I40E_QRX_ENA(itrq->itrq_index));
usr/src/uts/common/io/i40e/i40e_main.c
2880
VERIFY0(reg & (I40E_QRX_ENA_QENA_REQ_MASK |
usr/src/uts/common/io/i40e/i40e_main.c
2882
reg |= I40E_QRX_ENA_QENA_REQ_MASK;
usr/src/uts/common/io/i40e/i40e_main.c
2883
I40E_WRITE_REG(hw, I40E_QRX_ENA(itrq->itrq_index), reg);
usr/src/uts/common/io/i40e/i40e_main.c
2891
reg = I40E_READ_REG(hw, I40E_QRX_ENA(itrq->itrq_index));
usr/src/uts/common/io/i40e/i40e_main.c
2893
if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
usr/src/uts/common/io/i40e/i40e_main.c
2898
if ((reg & I40E_QRX_ENA_QENA_STAT_MASK) == 0) {
usr/src/uts/common/io/i40e/i40e_main.c
2983
uint32_t reg;
usr/src/uts/common/io/i40e/i40e_main.c
3001
reg = I40E_QTX_CTL_PF_QUEUE;
usr/src/uts/common/io/i40e/i40e_main.c
3002
reg |= (hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
usr/src/uts/common/io/i40e/i40e_main.c
3004
I40E_WRITE_REG(hw, I40E_QTX_CTL(itrq->itrq_index), reg);
usr/src/uts/common/io/i40e/i40e_main.c
3010
reg = I40E_READ_REG(hw, I40E_QTX_ENA(itrq->itrq_index));
usr/src/uts/common/io/i40e/i40e_main.c
3011
VERIFY0(reg & (I40E_QTX_ENA_QENA_REQ_MASK |
usr/src/uts/common/io/i40e/i40e_main.c
3013
reg |= I40E_QTX_ENA_QENA_REQ_MASK;
usr/src/uts/common/io/i40e/i40e_main.c
3014
I40E_WRITE_REG(hw, I40E_QTX_ENA(itrq->itrq_index), reg);
usr/src/uts/common/io/i40e/i40e_main.c
3022
reg = I40E_READ_REG(hw, I40E_QTX_ENA(itrq->itrq_index));
usr/src/uts/common/io/i40e/i40e_main.c
3024
if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
usr/src/uts/common/io/i40e/i40e_main.c
3029
if ((reg & I40E_QTX_ENA_QENA_STAT_MASK) == 0) {
usr/src/uts/common/io/i40e/i40e_osdep.h
156
#define i40e_read_pci_cfg(hw, reg) \
usr/src/uts/common/io/i40e/i40e_osdep.h
157
(pci_config_get16(OS_DEP(hw)->ios_cfg_handle, (reg)))
usr/src/uts/common/io/i40e/i40e_osdep.h
158
#define i40e_write_pci_cfg(hw, reg, value) \
usr/src/uts/common/io/i40e/i40e_osdep.h
159
(pci_config_put16(OS_DEP(hw)->ios_cfg_handle, (reg), (value)))
usr/src/uts/common/io/i40e/i40e_osdep.h
168
#define wr32(hw, reg, value) \
usr/src/uts/common/io/i40e/i40e_osdep.h
170
(uint32_t *)((uintptr_t)(hw)->hw_addr + (reg)), (value))
usr/src/uts/common/io/i40e/i40e_osdep.h
171
#define rd32(hw, reg) \
usr/src/uts/common/io/i40e/i40e_osdep.h
173
(uint32_t *)((uintptr_t)(hw)->hw_addr + (reg)))
usr/src/uts/common/io/i40e/i40e_stats.c
106
i40e_stat_get_uint48(i40e_t *i40e, uintptr_t reg, kstat_named_t *kstat,
usr/src/uts/common/io/i40e/i40e_stats.c
115
(uint64_t *)((uintptr_t)hw->hw_addr + reg));
usr/src/uts/common/io/i40e/i40e_stats.c
137
i40e_stat_get_uint32(i40e_t *i40e, uintptr_t reg, kstat_named_t *kstat,
usr/src/uts/common/io/i40e/i40e_stats.c
146
(uint32_t *)((uintptr_t)hw->hw_addr + reg));
usr/src/uts/common/io/i8042.c
1086
i8042_send(struct i8042 *global, int reg, unsigned char val)
usr/src/uts/common/io/i8042.c
1100
ddi_put8(global->io_handle, global->io_addr+reg, val);
usr/src/uts/common/io/i8042.c
403
static void i8042_send(struct i8042 *global, int reg, unsigned char cmd);
usr/src/uts/common/io/igb/e1000_osdep.h
112
#define E1000_WRITE_REG(hw, reg, value) \
usr/src/uts/common/io/igb/e1000_osdep.h
114
(uint32_t *)((uintptr_t)(hw)->hw_addr + reg), (value))
usr/src/uts/common/io/igb/e1000_osdep.h
116
#define E1000_READ_REG(hw, reg) \
usr/src/uts/common/io/igb/e1000_osdep.h
118
(uint32_t *)((uintptr_t)(hw)->hw_addr + reg))
usr/src/uts/common/io/igb/e1000_osdep.h
120
#define E1000_WRITE_REG_ARRAY(hw, reg, offset, value) \
usr/src/uts/common/io/igb/e1000_osdep.h
122
(uint32_t *)((uintptr_t)(hw)->hw_addr + reg + ((offset) << 2)), \
usr/src/uts/common/io/igb/e1000_osdep.h
125
#define E1000_READ_REG_ARRAY(hw, reg, offset) \
usr/src/uts/common/io/igb/e1000_osdep.h
127
(uint32_t *)((uintptr_t)(hw)->hw_addr + reg + ((offset) << 2)))
usr/src/uts/common/io/igb/e1000_osdep.h
129
#define E1000_WRITE_REG_ARRAY_DWORD(a, reg, offset, value) \
usr/src/uts/common/io/igb/e1000_osdep.h
130
E1000_WRITE_REG_ARRAY(a, reg, offset, value)
usr/src/uts/common/io/igb/e1000_osdep.h
131
#define E1000_READ_REG_ARRAY_DWORD(a, reg, offset) \
usr/src/uts/common/io/igb/e1000_osdep.h
132
E1000_READ_REG_ARRAY(a, reg, offset)
usr/src/uts/common/io/igb/e1000_osdep.h
135
#define E1000_READ_FLASH_REG(hw, reg) \
usr/src/uts/common/io/igb/e1000_osdep.h
137
(uint32_t *)((uintptr_t)(hw)->flash_address + (reg)))
usr/src/uts/common/io/igb/e1000_osdep.h
139
#define E1000_READ_FLASH_REG16(hw, reg) \
usr/src/uts/common/io/igb/e1000_osdep.h
141
(uint16_t *)((uintptr_t)(hw)->flash_address + (reg)))
usr/src/uts/common/io/igb/e1000_osdep.h
143
#define E1000_WRITE_FLASH_REG(hw, reg, value) \
usr/src/uts/common/io/igb/e1000_osdep.h
145
(uint32_t *)((uintptr_t)(hw)->flash_address + (reg)), (value))
usr/src/uts/common/io/igb/e1000_osdep.h
147
#define E1000_WRITE_FLASH_REG16(hw, reg, value) \
usr/src/uts/common/io/igb/e1000_osdep.h
149
(uint16_t *)((uintptr_t)(hw)->flash_address + (reg)), (value))
usr/src/uts/common/io/igb/e1000_osdep.h
198
#define E1000_WRITE_REG_IO(a, reg, val) { \
usr/src/uts/common/io/igb/e1000_osdep.h
201
reg); \
usr/src/uts/common/io/igb/igb_main.c
3735
uint32_t reg;
usr/src/uts/common/io/igb/igb_main.c
3748
reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
usr/src/uts/common/io/igb/igb_main.c
3749
reg |= E1000_CTRL_EXT_PBA_CLR;
usr/src/uts/common/io/igb/igb_main.c
3752
reg |= E1000_CTRL_EXT_IRCA; /* Called NSICR in the EAS */
usr/src/uts/common/io/igb/igb_main.c
3754
E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
usr/src/uts/common/io/igb/igb_osdep.c
103
(off_t)(pcie_cap + reg), *value);
usr/src/uts/common/io/igb/igb_osdep.c
49
e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
usr/src/uts/common/io/igb/igb_osdep.c
51
pci_config_put16(OS_DEP(hw)->cfg_handle, reg, *value);
usr/src/uts/common/io/igb/igb_osdep.c
55
e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
usr/src/uts/common/io/igb/igb_osdep.c
58
pci_config_get16(OS_DEP(hw)->cfg_handle, reg);
usr/src/uts/common/io/igb/igb_osdep.c
67
e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
usr/src/uts/common/io/igb/igb_osdep.c
79
(pcie_cap + reg));
usr/src/uts/common/io/igb/igb_osdep.c
91
e1000_write_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
usr/src/uts/common/io/igb/igb_sensor.c
78
uint32_t reg;
usr/src/uts/common/io/igb/igb_sensor.c
84
reg = E1000_READ_REG(&igb->hw, E1000_THMJT);
usr/src/uts/common/io/igb/igb_sensor.c
86
if (E1000_THMJT_VALID(reg) == 0) {
usr/src/uts/common/io/igb/igb_sensor.c
93
scalar->sis_value = E1000_THMJT_TEMP(reg);
usr/src/uts/common/io/igb/igb_sw.h
344
} reg;
usr/src/uts/common/io/igc/core/igc_defines.h
1155
#define GG82563_REG(page, reg) \
usr/src/uts/common/io/igc/core/igc_defines.h
1156
(((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
usr/src/uts/common/io/igc/core/igc_hw.h
541
s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
usr/src/uts/common/io/igc/core/igc_hw.h
542
s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
usr/src/uts/common/io/igc/core/igc_hw.h
543
void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
usr/src/uts/common/io/igc/core/igc_hw.h
544
void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
usr/src/uts/common/io/igc/core/igc_i225.c
862
u32 i, reg;
usr/src/uts/common/io/igc/core/igc_i225.c
867
reg = IGC_READ_REG(hw, IGC_EECD);
usr/src/uts/common/io/igc/core/igc_i225.c
868
if (reg & IGC_EECD_FLUDONE_I225) {
usr/src/uts/common/io/igc/core/igc_nvm.c
197
u32 i, reg = 0;
usr/src/uts/common/io/igc/core/igc_nvm.c
203
reg = IGC_READ_REG(hw, IGC_EERD);
usr/src/uts/common/io/igc/core/igc_nvm.c
205
reg = IGC_READ_REG(hw, IGC_EEWR);
usr/src/uts/common/io/igc/core/igc_nvm.c
207
if (reg & IGC_NVM_RW_REG_DONE)
usr/src/uts/common/io/igc/igc.c
1090
igc_led_get_mode(uint32_t led, uint32_t reg)
usr/src/uts/common/io/igc/igc.c
1093
return (bitx32(reg, 3 + off, off));
usr/src/uts/common/io/igc/igc.c
1097
igc_led_set_mode(uint32_t led, uint32_t reg, i225_led_mode_t mode)
usr/src/uts/common/io/igc/igc.c
1100
return (bitset32(reg, 3 + off, off, mode));
usr/src/uts/common/io/igc/igc.c
1104
igc_led_get_ivrt(uint32_t led, uint32_t reg)
usr/src/uts/common/io/igc/igc.c
1107
return (bitx32(reg, off, off));
usr/src/uts/common/io/igc/igc.c
1111
igc_led_set_blink(uint32_t led, uint32_t reg, bool en)
usr/src/uts/common/io/igc/igc.c
1114
return (bitset32(reg, off, off, en));
usr/src/uts/common/io/igc/igc.c
1174
const uint32_t reg = IGC_IVAR0 + ivarno * 4;
usr/src/uts/common/io/igc/igc.c
1193
ivar = igc_read32(igc, reg);
usr/src/uts/common/io/igc/igc.c
1195
igc_write32(igc, reg, ivar);
usr/src/uts/common/io/igc/igc.c
513
igc_read32(igc_t *igc, uint32_t reg)
usr/src/uts/common/io/igc/igc.c
516
ASSERT3U(reg, <, igc->igc_regs_size);
usr/src/uts/common/io/igc/igc.c
517
addr = (uint32_t *)(igc->igc_regs_base + reg);
usr/src/uts/common/io/igc/igc.c
522
igc_write32(igc_t *igc, uint32_t reg, uint32_t val)
usr/src/uts/common/io/igc/igc.c
525
ASSERT3U(reg, <, igc->igc_regs_size);
usr/src/uts/common/io/igc/igc.c
526
addr = (uint32_t *)(igc->igc_regs_base + reg);
usr/src/uts/common/io/igc/igc_gld.c
460
uint32_t reg;
usr/src/uts/common/io/igc/igc_gld.c
464
reg = igc_read32(igc, IGC_RCTL);
usr/src/uts/common/io/igc/igc_gld.c
466
reg |= IGC_RCTL_UPE | IGC_RCTL_MPE;
usr/src/uts/common/io/igc/igc_gld.c
469
reg &= ~(IGC_RCTL_UPE | IGC_RCTL_MPE);
usr/src/uts/common/io/igc/igc_gld.c
472
igc_write32(igc, IGC_RCTL, reg);
usr/src/uts/common/io/igc/igc_osdep.c
44
IGC_READ_REG(struct igc_hw *hw, uint32_t reg)
usr/src/uts/common/io/igc/igc_osdep.c
48
return (igc_read32(igc, reg));
usr/src/uts/common/io/igc/igc_osdep.c
52
IGC_WRITE_REG(struct igc_hw *hw, uint32_t reg, uint32_t val)
usr/src/uts/common/io/igc/igc_osdep.c
56
igc_write32(igc, reg, val);
usr/src/uts/common/io/igc/igc_osdep.c
60
IGC_WRITE_REG_ARRAY(struct igc_hw *hw, uint32_t reg, uint32_t offset,
usr/src/uts/common/io/igc/igc_osdep.c
65
ASSERT3U(reg, <, igc->igc_regs_size);
usr/src/uts/common/io/igc/igc_osdep.c
66
ASSERT3U(offset + reg, <=, igc->igc_regs_size);
usr/src/uts/common/io/igc/igc_osdep.c
67
igc_write32(igc, reg + offset, val);
usr/src/uts/common/io/igc/igc_stat.c
36
igc_stats_update_u64(igc_t *igc, kstat_named_t *ks, uint32_t reg)
usr/src/uts/common/io/igc/igc_stat.c
38
uint64_t val = igc_read32(igc, reg);
usr/src/uts/common/io/igc/igc_stat.c
39
val += (uint64_t)igc_read32(igc, reg + 4) << 32UL;
usr/src/uts/common/io/iprb/iprb.c
1547
iprb_mii_read(void *arg, uint8_t phy, uint8_t reg)
usr/src/uts/common/io/iprb/iprb.c
1559
((uint32_t)reg << MDI_REGAD_SHIFT);
usr/src/uts/common/io/iprb/iprb.c
1573
iprb_mii_write(void *arg, uint8_t phy, uint8_t reg, uint16_t data)
usr/src/uts/common/io/iprb/iprb.c
1580
((uint32_t)reg << MDI_REGAD_SHIFT) |
usr/src/uts/common/io/iwh/iwh_hw.h
2570
#define IWH_READ(sc, reg) \
usr/src/uts/common/io/iwh/iwh_hw.h
2571
ddi_get32((sc)->sc_handle, (uint32_t *)((sc)->sc_base + (reg)))
usr/src/uts/common/io/iwh/iwh_hw.h
2573
#define IWH_WRITE(sc, reg, val) \
usr/src/uts/common/io/iwh/iwh_hw.h
2574
ddi_put32((sc)->sc_handle, (uint32_t *)((sc)->sc_base + (reg)), (val))
usr/src/uts/common/io/iwh/iwh_hw.h
602
#define FH_RCSR_GET_RDBC_SIZE(reg) \
usr/src/uts/common/io/iwh/iwh_hw.h
603
((reg & FH_RCSR_RX_CONFIG_RDBC_SIZE_MASK) >> \
usr/src/uts/common/io/iwk/iwk_hw.h
3193
#define IWK_READ(sc, reg) \
usr/src/uts/common/io/iwk/iwk_hw.h
3194
ddi_get32((sc)->sc_handle, (uint32_t *)((sc)->sc_base + (reg)))
usr/src/uts/common/io/iwk/iwk_hw.h
3196
#define IWK_WRITE(sc, reg, val) \
usr/src/uts/common/io/iwk/iwk_hw.h
3197
ddi_put32((sc)->sc_handle, (uint32_t *)((sc)->sc_base + (reg)), (val))
usr/src/uts/common/io/iwk/iwk_hw.h
604
#define FH_RCSR_GET_RDBC_SIZE(reg) \
usr/src/uts/common/io/iwk/iwk_hw.h
605
((reg & FH_RCSR_RX_CONFIG_RDBC_SIZE_MASK) >> \
usr/src/uts/common/io/iwn/if_iwn.c
416
iwn_read(struct iwn_softc *sc, int reg)
usr/src/uts/common/io/iwn/if_iwn.c
419
return (ddi_get32(sc->sc_regh, (uint32_t *)(sc->sc_base + reg)));
usr/src/uts/common/io/iwn/if_iwn.c
423
iwn_write(struct iwn_softc *sc, int reg, uint32_t val)
usr/src/uts/common/io/iwn/if_iwn.c
426
ddi_put32(sc->sc_regh, (uint32_t *)(sc->sc_base + reg), val);
usr/src/uts/common/io/iwn/if_iwn.c
430
iwn_write_1(struct iwn_softc *sc, int reg, uint8_t val)
usr/src/uts/common/io/iwn/if_iwn.c
432
ddi_put8(sc->sc_regh, (uint8_t *)(sc->sc_base + reg), val);
usr/src/uts/common/io/iwn/if_iwn.c
5313
uint32_t reg;
usr/src/uts/common/io/iwn/if_iwn.c
5330
reg = pci_config_get32(sc->sc_pcih,
usr/src/uts/common/io/iwn/if_iwn.c
5332
if (!(reg & PCIE_LINKCTL_ASPM_CTL_L0S)) /* L0s Entry disabled. */
usr/src/uts/common/io/iwn/if_iwn.c
7098
uint32_t reg;
usr/src/uts/common/io/iwn/if_iwn.c
7113
reg = pci_config_get32(sc->sc_pcih,
usr/src/uts/common/io/iwn/if_iwn.c
7116
if (reg & PCIE_LINKCTL_ASPM_CTL_L1) /* L1 Entry enabled. */
usr/src/uts/common/io/iwn/if_iwn.c
774
uint32_t reg;
usr/src/uts/common/io/iwn/if_iwn.c
841
reg = pci_config_get8(sc->sc_pcih, 0x41);
usr/src/uts/common/io/iwn/if_iwn.c
842
if (reg)
usr/src/uts/common/io/iwn/if_iwnreg.h
1985
#define IWN_READ(sc, reg) \
usr/src/uts/common/io/iwn/if_iwnreg.h
1986
iwn_read(sc, reg)
usr/src/uts/common/io/iwn/if_iwnreg.h
1988
#define IWN_WRITE(sc, reg, val) \
usr/src/uts/common/io/iwn/if_iwnreg.h
1989
iwn_write(sc, reg, val)
usr/src/uts/common/io/iwn/if_iwnreg.h
1991
#define IWN_WRITE_1(sc, reg, val) \
usr/src/uts/common/io/iwn/if_iwnreg.h
1992
iwn_write_1(sc, reg, val)
usr/src/uts/common/io/iwn/if_iwnreg.h
1994
#define IWN_SETBITS(sc, reg, mask) \
usr/src/uts/common/io/iwn/if_iwnreg.h
1995
IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask))
usr/src/uts/common/io/iwn/if_iwnreg.h
1997
#define IWN_CLRBITS(sc, reg, mask) \
usr/src/uts/common/io/iwn/if_iwnreg.h
1998
IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask))
usr/src/uts/common/io/iwp/iwp_hw.h
2568
#define IWP_READ(sc, reg) \
usr/src/uts/common/io/iwp/iwp_hw.h
2569
ddi_get32((sc)->sc_handle, (uint32_t *)((sc)->sc_base + (reg)))
usr/src/uts/common/io/iwp/iwp_hw.h
2571
#define IWP_WRITE(sc, reg, val) \
usr/src/uts/common/io/iwp/iwp_hw.h
2572
ddi_put32((sc)->sc_handle, (uint32_t *)((sc)->sc_base + (reg)), (val))
usr/src/uts/common/io/iwp/iwp_hw.h
599
#define FH_RCSR_GET_RDBC_SIZE(reg) \
usr/src/uts/common/io/iwp/iwp_hw.h
600
((reg & FH_RCSR_RX_CONFIG_RDBC_SIZE_MASK) >> \
usr/src/uts/common/io/ixgbe/core/ixgbe_82598.c
1079
s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
usr/src/uts/common/io/ixgbe/core/ixgbe_82598.c
1086
IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
usr/src/uts/common/io/ixgbe/core/ixgbe_82598.c
1103
s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
usr/src/uts/common/io/ixgbe/core/ixgbe_82598.c
1109
atlas_ctl = (reg << 8) | val;
usr/src/uts/common/io/ixgbe/core/ixgbe_82598.c
413
u32 reg;
usr/src/uts/common/io/ixgbe/core/ixgbe_82598.c
538
reg = hw->fc.pause_time * 0x00010001;
usr/src/uts/common/io/ixgbe/core/ixgbe_82598.c
540
IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_82598.h
45
s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val);
usr/src/uts/common/io/ixgbe/core/ixgbe_82598.h
46
s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val);
usr/src/uts/common/io/ixgbe/core/ixgbe_82599.c
1715
#define IXGBE_WRITE_REG_BE32(a, reg, value) \
usr/src/uts/common/io/ixgbe/core/ixgbe_82599.c
1716
IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
usr/src/uts/common/io/ixgbe/core/ixgbe_82599.c
2103
s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
usr/src/uts/common/io/ixgbe/core/ixgbe_82599.c
2110
(reg << 8));
usr/src/uts/common/io/ixgbe/core/ixgbe_82599.c
2127
s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
usr/src/uts/common/io/ixgbe/core/ixgbe_82599.c
2133
core_ctl = (reg << 8) | val;
usr/src/uts/common/io/ixgbe/core/ixgbe_82599.h
56
s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
usr/src/uts/common/io/ixgbe/core/ixgbe_82599.h
57
s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
usr/src/uts/common/io/ixgbe/core/ixgbe_api.c
1504
s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)
usr/src/uts/common/io/ixgbe/core/ixgbe_api.c
1506
return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg,
usr/src/uts/common/io/ixgbe/core/ixgbe_api.c
1518
s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)
usr/src/uts/common/io/ixgbe/core/ixgbe_api.c
1520
return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg,
usr/src/uts/common/io/ixgbe/core/ixgbe_api.c
1579
s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val)
usr/src/uts/common/io/ixgbe/core/ixgbe_api.c
1582
reg, val), IXGBE_NOT_IMPLEMENTED);
usr/src/uts/common/io/ixgbe/core/ixgbe_api.c
1594
s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val)
usr/src/uts/common/io/ixgbe/core/ixgbe_api.c
1597
(hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);
usr/src/uts/common/io/ixgbe/core/ixgbe_api.c
1644
s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)
usr/src/uts/common/io/ixgbe/core/ixgbe_api.c
1647
(hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);
usr/src/uts/common/io/ixgbe/core/ixgbe_api.c
1659
s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)
usr/src/uts/common/io/ixgbe/core/ixgbe_api.c
1662
(hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);
usr/src/uts/common/io/ixgbe/core/ixgbe_api.h
145
s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val);
usr/src/uts/common/io/ixgbe/core/ixgbe_api.h
146
s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val);
usr/src/uts/common/io/ixgbe/core/ixgbe_api.h
184
s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val);
usr/src/uts/common/io/ixgbe/core/ixgbe_api.h
185
s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val);
usr/src/uts/common/io/ixgbe/core/ixgbe_api.h
191
s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val);
usr/src/uts/common/io/ixgbe/core/ixgbe_api.h
192
s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val);
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
1089
u32 reg;
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
1094
reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
1095
bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
1099
reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
1100
if (reg & IXGBE_FACTPS_LFS)
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
1795
u32 reg;
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
1802
reg = IXGBE_READ_REG(hw, IXGBE_EERD);
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
1804
reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
1806
if (reg & IXGBE_EEPROM_RW_REG_DONE) {
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
242
u32 reg = 0, reg_bp = 0;
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
275
reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
280
reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
2823
u32 reg;
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
2935
reg = hw->fc.pause_time * 0x00010001;
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
2937
IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
304
reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
316
reg |= IXGBE_PCS1GANA_ASM_PAUSE;
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
317
reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
338
reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
358
IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
359
reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
363
reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
365
IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
366
DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
385
DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
4163
u32 offset, reg;
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
4172
reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
4173
switch (reg & IXGBE_GCR_EXT_VT_MODE_MASK) {
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
4193
reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset));
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
4194
reg |= IXGBE_TXDCTL_ENABLE;
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
4195
IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
4199
reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset));
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
4200
reg &= ~IXGBE_TXDCTL_ENABLE;
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
4201
IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
5574
u32 reg, i;
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
5576
reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
usr/src/uts/common/io/ixgbe/core/ixgbe_common.c
5579
(reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
usr/src/uts/common/io/ixgbe/core/ixgbe_common.h
39
#define IXGBE_WRITE_REG64(hw, reg, value) \
usr/src/uts/common/io/ixgbe/core/ixgbe_common.h
41
IXGBE_WRITE_REG(hw, reg, (u32) value); \
usr/src/uts/common/io/ixgbe/core/ixgbe_common.h
42
IXGBE_WRITE_REG(hw, reg + 4, (u32) (value >> 32)); \
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
115
u32 reg = 0;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
120
reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
121
IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
123
reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
125
reg &= ~IXGBE_RMCS_ARBDIS;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
127
reg |= IXGBE_RMCS_RRM;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
129
reg |= IXGBE_RMCS_DFP;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
131
IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
138
reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
141
reg |= IXGBE_RT2CR_LSP;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
143
IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
146
reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
147
reg |= IXGBE_RDRXCTL_RDMTS_1_2;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
148
reg |= IXGBE_RDRXCTL_MPBEN;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
149
reg |= IXGBE_RDRXCTL_MCEN;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
150
IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
152
reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
154
reg &= ~IXGBE_RXCTRL_DMBYPS;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
155
IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
174
u32 reg, max_credits;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
177
reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
180
reg &= ~IXGBE_DPMCS_ARBDIS;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
181
reg |= IXGBE_DPMCS_TSOEF;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
184
reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
186
IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
191
reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
192
reg |= (u32)(refill[i]);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
193
reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
196
reg |= IXGBE_TDTQ2TCCR_GSP;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
199
reg |= IXGBE_TDTQ2TCCR_LSP;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
201
IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
221
u32 reg;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
224
reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
226
reg &= ~IXGBE_PDPMCS_ARBDIS;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
228
reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
230
IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
234
reg = refill[i];
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
235
reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
236
reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
239
reg |= IXGBE_TDPT2TCCR_GSP;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
242
reg |= IXGBE_TDPT2TCCR_LSP;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
244
IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
248
reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
249
reg |= IXGBE_DTXCTL_ENDBUBD;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
250
IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
264
u32 fcrtl, reg;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
268
reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
269
reg &= ~IXGBE_RMCS_TFCE_802_3X;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
270
reg |= IXGBE_RMCS_TFCE_PRIORITY;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
271
IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
274
reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
275
reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
278
reg |= IXGBE_FCTRL_RPFCE;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
280
IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
291
reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
293
IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
297
reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
299
IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
316
u32 reg = 0;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
322
reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
323
reg |= ((0x1010101) * j);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
324
IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
325
reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
326
reg |= ((0x1010101) * j);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
327
IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
331
reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
332
reg |= ((0x1010101) * i);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82598.c
333
IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
125
u32 reg = 0;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
134
reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
135
IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
143
reg = 0;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
145
reg |= (map[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT));
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
147
IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
153
reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
155
reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
158
reg |= IXGBE_RTRPT4C_LSP;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
160
IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
167
reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
168
IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
186
u32 reg, max_credits;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
198
reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
199
reg |= (u32)(refill[i]);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
200
reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
203
reg |= IXGBE_RTTDT2C_GSP;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
206
reg |= IXGBE_RTTDT2C_LSP;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
208
IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
215
reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
216
IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
236
u32 reg;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
243
reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
246
IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
254
reg = 0;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
256
reg |= (map[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT));
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
258
IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
262
reg = refill[i];
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
263
reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
264
reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
267
reg |= IXGBE_RTTPT2C_GSP;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
270
reg |= IXGBE_RTTPT2C_LSP;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
272
IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
279
reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
281
IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
296
u32 i, j, fcrtl, reg;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
303
reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
304
reg |= IXGBE_MFLCN_DPF;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
311
reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
314
reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
317
reg |= IXGBE_MFLCN_RPFCE;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
319
IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
339
reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
350
reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
354
IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
363
reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
365
IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
384
u32 reg = 0;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
406
reg = 0x01010101 * (i / 4);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
407
IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
420
reg = 0x00000000;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
422
reg = 0x01010101;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
424
reg = 0x02020202;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
426
reg = 0x03030303;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
428
reg = 0x04040404;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
430
reg = 0x05050505;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
432
reg = 0x06060606;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
434
reg = 0x07070707;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
435
IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
451
reg = 0x01010101 * (i / 8);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
452
IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
465
reg = 0x00000000;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
467
reg = 0x01010101;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
469
reg = 0x02020202;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
471
reg = 0x03030303;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
472
IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
510
u32 reg;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
514
reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
515
reg |= IXGBE_RTTDCS_ARBDIS;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
516
IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
518
reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
521
switch (reg & IXGBE_MRQC_MRQE_MASK) {
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
525
reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
531
reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
540
reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
547
reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
550
reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
553
IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
557
reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
560
reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
562
reg |= IXGBE_MTQC_VT_ENA;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
564
IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
572
reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
573
reg &= ~IXGBE_RTTDCS_ARBDIS;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
574
IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
577
reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
578
reg |= IXGBE_SECTX_DCB;
usr/src/uts/common/io/ixgbe/core/ixgbe_dcb_82599.c
579
IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c
109
s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c
121
reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c
122
csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c
135
if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c
186
s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c
195
reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c
196
csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c
211
if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c
2695
u16 reg;
usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c
2702
®);
usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c
2707
reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c
2711
reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c
2716
reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_phy.h
216
s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg,
usr/src/uts/common/io/ixgbe/core/ixgbe_phy.h
218
s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg,
usr/src/uts/common/io/ixgbe/core/ixgbe_type.h
4180
s32 (*read_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val);
usr/src/uts/common/io/ixgbe/core/ixgbe_type.h
4181
s32 (*read_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
usr/src/uts/common/io/ixgbe/core/ixgbe_type.h
4183
s32 (*write_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val);
usr/src/uts/common/io/ixgbe/core/ixgbe_type.h
4184
s32 (*write_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
usr/src/uts/common/io/ixgbe/core/ixgbe_x540.c
739
u32 reg;
usr/src/uts/common/io/ixgbe/core/ixgbe_x540.c
745
reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
usr/src/uts/common/io/ixgbe/core/ixgbe_x540.c
746
if (reg & IXGBE_EEC_FLUDONE) {
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1000
IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
113
static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
115
return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
126
static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
128
return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1291
u32 reg;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1296
reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1297
reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1298
IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1301
reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1302
reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1303
IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1314
u32 reg;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1319
reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1320
reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1321
IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1324
reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1325
reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1326
IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1338
u32 idx, reg, num_qs, start_q, bitmask;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1343
reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1344
switch (reg & IXGBE_MRQC_MRQE_MASK) {
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1363
reg = 0;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1364
reg |= (bitmask << (start_q % 32));
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1365
IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1366
IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1379
u32 i, j, reg, q, shift, vf, idx;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1384
reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1385
switch (reg & IXGBE_MRQC_MRQE_MASK) {
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
139
static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
143
status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
158
static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
162
status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
181
u8 reg;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
184
status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
187
reg |= IXGBE_PE_BIT1;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
188
status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1903
u16 reg;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1910
®);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1913
!(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1919
®);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
192
status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1922
!(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1929
®);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1935
if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1939
} else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1943
®);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1949
if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
195
reg &= ~IXGBE_PE_BIT1;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1958
IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
196
status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1961
!(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1966
IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1972
if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
1990
u16 reg;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
200
status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
2009
IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
2014
reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
2018
IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
2027
®);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
203
reg &= ~IXGBE_PE_BIT1;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
2032
reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
2037
reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
204
status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
2045
®);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
2050
reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
2055
reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
2063
®);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
2068
reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
2072
reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
210
status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
213
reg |= IXGBE_PE_BIT1;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
214
status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
2503
u16 reg;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
2508
®);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
2516
if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
2520
®);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
2525
reg &= ~IXGBE_MDIO_POWER_UP_STALL;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
2530
reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
3150
u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
3152
u32 value = IXGBE_READ_REG(hw, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
544
u16 reg, u16 *val)
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
546
return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
560
u16 reg, u16 *val)
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
562
return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
575
u8 addr, u16 reg, u16 val)
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
577
return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
591
u8 addr, u16 reg, u16 val)
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
593
return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
883
u32 reg, high_pri_tc;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
888
reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
889
reg &= ~IXGBE_DMACR_DMAC_EN;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
890
IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
899
reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
902
reg &= ~IXGBE_DMACR_DMACWT_MASK;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
903
reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
905
reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
909
reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
912
reg |= IXGBE_DMACR_EN_MNG_IND;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
915
reg |= IXGBE_DMACR_DMAC_EN;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
916
IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
931
u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
954
reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
955
reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
970
reg |= (rx_pb_size > maxframe_size_kb) ?
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
973
IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
986
u32 reg;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
991
reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
992
reg &= ~IXGBE_DMACR_DMAC_EN;
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
993
IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
998
reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c
999
reg |= IXGBE_DMACR_DMAC_EN;
usr/src/uts/common/io/ixgbe/ixgbe_debug.c
111
if (reg = IXGBE_READ_REG(hw, IXGBE_RAL(i))) {
usr/src/uts/common/io/ixgbe/ixgbe_debug.c
113
i, reg, i, IXGBE_READ_REG(hw, IXGBE_RAH(i)));
usr/src/uts/common/io/ixgbe/ixgbe_debug.c
120
if (reg = IXGBE_READ_REG(hw, IXGBE_MTA(i))) {
usr/src/uts/common/io/ixgbe/ixgbe_debug.c
121
ixgbe_log(ixgbe, "mta(%d): 0x%x\n", i, reg);
usr/src/uts/common/io/ixgbe/ixgbe_debug.c
130
if (reg = IXGBE_READ_REG(hw, off)) {
usr/src/uts/common/io/ixgbe/ixgbe_debug.c
131
ixgbe_log(ixgbe, "vfta(0x%x): 0x%x\n", off, reg);
usr/src/uts/common/io/ixgbe/ixgbe_debug.c
140
if (reg = IXGBE_READ_REG(hw, IXGBE_MDEF(i))) {
usr/src/uts/common/io/ixgbe/ixgbe_debug.c
141
ixgbe_log(ixgbe, "mdef(%d): 0x%x\n", i, reg);
usr/src/uts/common/io/ixgbe/ixgbe_debug.c
43
uint32_t ivar, reg, hw_index;
usr/src/uts/common/io/ixgbe/ixgbe_main.c
1354
uint32_t reg, i;
usr/src/uts/common/io/ixgbe/ixgbe_main.c
1364
reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
usr/src/uts/common/io/ixgbe/ixgbe_main.c
1366
if (((reg >> IXGBE_LED_MODE_SHIFT(i)) &
usr/src/uts/common/io/ixgbe/ixgbe_main.c
4778
uint32_t reg;
usr/src/uts/common/io/ixgbe/ixgbe_main.c
4786
reg = IXGBE_READ_REG(&ixgbe->hw, IXGBE_HLREG0);
usr/src/uts/common/io/ixgbe/ixgbe_main.c
4787
reg |= IXGBE_HLREG0_LPBK;
usr/src/uts/common/io/ixgbe/ixgbe_main.c
4788
IXGBE_WRITE_REG(&ixgbe->hw, IXGBE_HLREG0, reg);
usr/src/uts/common/io/ixgbe/ixgbe_main.c
4790
reg = IXGBE_READ_REG(&ixgbe->hw, IXGBE_AUTOC);
usr/src/uts/common/io/ixgbe/ixgbe_main.c
4791
reg &= ~IXGBE_AUTOC_LMS_MASK;
usr/src/uts/common/io/ixgbe/ixgbe_main.c
4792
IXGBE_WRITE_REG(&ixgbe->hw, IXGBE_AUTOC, reg);
usr/src/uts/common/io/ixgbe/ixgbe_main.c
4830
reg = IXGBE_READ_REG(&ixgbe->hw, IXGBE_AUTOC);
usr/src/uts/common/io/ixgbe/ixgbe_main.c
4831
reg |= (IXGBE_AUTOC_FLU |
usr/src/uts/common/io/ixgbe/ixgbe_main.c
4833
IXGBE_WRITE_REG(&ixgbe->hw, IXGBE_AUTOC, reg);
usr/src/uts/common/io/ixgbe/ixgbe_osdep.c
34
ixgbe_read_pci_cfg(struct ixgbe_hw *hw, uint32_t reg)
usr/src/uts/common/io/ixgbe/ixgbe_osdep.c
36
return (pci_config_get16(OS_DEP(hw)->cfg_handle, reg));
usr/src/uts/common/io/ixgbe/ixgbe_osdep.c
40
ixgbe_write_pci_cfg(struct ixgbe_hw *hw, uint32_t reg, uint32_t val)
usr/src/uts/common/io/ixgbe/ixgbe_osdep.c
42
pci_config_put16(OS_DEP(hw)->cfg_handle, reg, val);
usr/src/uts/common/io/ixgbe/ixgbe_osdep.h
100
IXGBE_WRITE_REG(a, ((reg) + ((index) << 2)), (value))
usr/src/uts/common/io/ixgbe/ixgbe_osdep.h
102
#define IXGBE_READ_REG(a, reg) \
usr/src/uts/common/io/ixgbe/ixgbe_osdep.h
104
(uint32_t *)((uintptr_t)(a)->hw_addr + reg))
usr/src/uts/common/io/ixgbe/ixgbe_osdep.h
106
#define IXGBE_READ_REG_ARRAY(a, reg, index) \
usr/src/uts/common/io/ixgbe/ixgbe_osdep.h
107
IXGBE_READ_REG(a, ((reg) + ((index) << 2)))
usr/src/uts/common/io/ixgbe/ixgbe_osdep.h
95
#define IXGBE_WRITE_REG(a, reg, value) \
usr/src/uts/common/io/ixgbe/ixgbe_osdep.h
97
(uint32_t *)((uintptr_t)(a)->hw_addr + reg), (value))
usr/src/uts/common/io/ixgbe/ixgbe_osdep.h
99
#define IXGBE_WRITE_REG_ARRAY(a, reg, index, value) \
usr/src/uts/common/io/ixgbe/ixgbe_sw.h
390
} reg;
usr/src/uts/common/io/mii/mii.c
1067
phy_read(phy_handle_t *ph, uint8_t reg)
usr/src/uts/common/io/mii/mii.c
1071
return ((*mh->m_ops.mii_read)(mh->m_private, ph->phy_addr, reg));
usr/src/uts/common/io/mii/mii.c
1075
phy_write(phy_handle_t *ph, uint8_t reg, uint16_t val)
usr/src/uts/common/io/mii/mii.c
1079
(*mh->m_ops.mii_write)(mh->m_private, ph->phy_addr, reg, val);
usr/src/uts/common/io/mii/mii_marvell.c
151
uint16_t reg;
usr/src/uts/common/io/mii/mii_marvell.c
156
reg = phy_read(ph, MVPHY_PSC);
usr/src/uts/common/io/mii/mii_marvell.c
158
reg |= MV_PSC_AUTO_MDIX;
usr/src/uts/common/io/mii/mii_marvell.c
159
reg &= ~(MV_PSC_EN_DETECT | MV_PSC_DIS_SCRAMBLER);
usr/src/uts/common/io/mii/mii_marvell.c
160
reg |= MV_PSC_LPNP;
usr/src/uts/common/io/mii/mii_marvell.c
165
phy_write(ph, MVPHY_PSC, reg);
usr/src/uts/common/io/mii/mii_marvell.c
184
uint16_t reg;
usr/src/uts/common/io/mii/mii_marvell.c
193
reg = phy_read(ph, MII_CONTROL);
usr/src/uts/common/io/mii/mii_marvell.c
194
reg |= MII_CONTROL_RESET;
usr/src/uts/common/io/mii/mii_marvell.c
195
phy_write(ph, MII_CONTROL, reg);
usr/src/uts/common/io/mii/mii_marvell.c
197
reg = phy_read(ph, MVPHY_PSC);
usr/src/uts/common/io/mii/mii_marvell.c
198
reg &= ~(MV_PSC_AUTO_MDIX);
usr/src/uts/common/io/mii/mii_marvell.c
199
reg &= ~(MV_PSC_EN_DETECT | MV_PSC_DIS_SCRAMBLER);
usr/src/uts/common/io/mii/mii_marvell.c
200
reg |= MV_PSC_LPNP;
usr/src/uts/common/io/mii/mii_marvell.c
202
phy_write(ph, MVPHY_PSC, reg);
usr/src/uts/common/io/mii/mii_marvell.c
210
uint16_t reg;
usr/src/uts/common/io/mii/mii_marvell.c
215
reg = phy_read(ph, MVPHY_PSC);
usr/src/uts/common/io/mii/mii_marvell.c
216
reg |= (MV_PSC_AUTO_X_MODE >> 1);
usr/src/uts/common/io/mii/mii_marvell.c
217
reg |= MV_PSC_ASSERT_CRS_TX;
usr/src/uts/common/io/mii/mii_marvell.c
218
reg &= ~MV_PSC_POL_REVERSE;
usr/src/uts/common/io/mii/mii_marvell.c
219
phy_write(ph, MVPHY_PSC, reg);
usr/src/uts/common/io/mii/mii_marvell.c
227
uint16_t reg;
usr/src/uts/common/io/mii/mii_marvell.c
233
reg = phy_read(ph, MVPHY_PSC);
usr/src/uts/common/io/mii/mii_marvell.c
235
reg &= ~MV_PSC_EN_DETECT_MASK;
usr/src/uts/common/io/mii/mii_marvell.c
236
reg |= MV_PSC_AUTO_X_MODE;
usr/src/uts/common/io/mii/mii_marvell.c
237
reg |= MV_PSC_DOWNSHIFT_EN;
usr/src/uts/common/io/mii/mii_marvell.c
238
reg &= ~MV_PSC_POL_REVERSE;
usr/src/uts/common/io/mii/mii_marvell.c
239
phy_write(ph, MVPHY_PSC, reg);
usr/src/uts/common/io/mii/mii_marvell.c
289
uint16_t reg;
usr/src/uts/common/io/mii/mii_marvell.c
294
reg = phy_read(ph, MVPHY_PSC);
usr/src/uts/common/io/mii/mii_marvell.c
296
reg &= ~MV_PSC_POWER_DOWN;
usr/src/uts/common/io/mii/mii_marvell.c
298
reg &= ~MV_PSC_EN_DETECT_MASK;
usr/src/uts/common/io/mii/mii_marvell.c
299
reg |= MV_PSC_AUTO_X_MODE;
usr/src/uts/common/io/mii/mii_marvell.c
300
reg |= MV_PSC_ASSERT_CRS_TX;
usr/src/uts/common/io/mii/mii_marvell.c
301
reg &= ~MV_PSC_POL_REVERSE;
usr/src/uts/common/io/mii/mii_marvell.c
302
phy_write(ph, MVPHY_PSC, reg);
usr/src/uts/common/io/mii/mii_marvell.c
324
uint16_t reg;
usr/src/uts/common/io/mii/mii_marvell.c
325
reg = phy_read(ph, MVPHY_PSC);
usr/src/uts/common/io/mii/mii_marvell.c
328
reg &= ~MV_PSC_EN_DETECT_MASK;
usr/src/uts/common/io/mii/mii_marvell.c
329
reg |= MV_PSC_AUTO_X_MODE;
usr/src/uts/common/io/mii/mii_marvell.c
330
reg |= MV_PSC_ASSERT_CRS_TX;
usr/src/uts/common/io/mii/mii_marvell.c
331
reg &= ~MV_PSC_POL_REVERSE;
usr/src/uts/common/io/mii/mii_marvell.c
332
phy_write(ph, MVPHY_PSC, reg);
usr/src/uts/common/io/mii/mii_marvell.c
340
uint16_t reg;
usr/src/uts/common/io/mii/mii_marvell.c
342
reg = phy_read(ph, MVPHY_PSC);
usr/src/uts/common/io/mii/mii_marvell.c
345
reg &= ~MV_PSC_EN_DETECT_MASK;
usr/src/uts/common/io/mii/mii_marvell.c
346
reg |= MV_PSC_AUTO_X_MODE;
usr/src/uts/common/io/mii/mii_marvell.c
347
reg |= MV_PSC_ASSERT_CRS_TX;
usr/src/uts/common/io/mii/mii_marvell.c
348
reg &= ~MV_PSC_POL_REVERSE;
usr/src/uts/common/io/mii/mii_marvell.c
350
phy_write(ph, MVPHY_PSC, reg);
usr/src/uts/common/io/mii/mii_marvell.c
362
uint16_t reg, page;
usr/src/uts/common/io/mii/mii_marvell.c
374
reg = phy_read(ph, MVPHY_PSC);
usr/src/uts/common/io/mii/mii_marvell.c
375
reg &= ~MV_PSC_MODE_MASK;
usr/src/uts/common/io/mii/mii_marvell.c
376
reg |= MV_PSC_MODE_1000BASEX;
usr/src/uts/common/io/mii/mii_marvell.c
377
phy_write(ph, MVPHY_PSC, reg);
usr/src/uts/common/io/mii/mii_marvell.c
381
reg = phy_read(ph, MVPHY_PSC);
usr/src/uts/common/io/mii/mii_marvell.c
384
reg &= ~MV_PSC_EN_DETECT_MASK;
usr/src/uts/common/io/mii/mii_marvell.c
385
reg |= MV_PSC_AUTO_X_MODE;
usr/src/uts/common/io/mii/mii_marvell.c
386
reg |= MV_PSC_ASSERT_CRS_TX;
usr/src/uts/common/io/mii/mii_marvell.c
387
reg &= ~MV_PSC_POL_REVERSE;
usr/src/uts/common/io/mii/mii_marvell.c
388
phy_write(ph, MVPHY_PSC, reg);
usr/src/uts/common/io/mii/mii_marvell.c
397
uint16_t reg;
usr/src/uts/common/io/mii/mii_marvell.c
405
reg = phy_read(ph, MVPHY_PSC);
usr/src/uts/common/io/mii/mii_marvell.c
406
reg &= ~MV_PSC_AUTO_X_MODE;
usr/src/uts/common/io/mii/mii_marvell.c
407
reg |= MV_PSC_ASSERT_CRS_TX;
usr/src/uts/common/io/mii/mii_marvell.c
408
reg &= ~MV_PSC_POL_REVERSE;
usr/src/uts/common/io/mii/mii_marvell.c
409
phy_write(ph, MVPHY_PSC, reg);
usr/src/uts/common/io/mii/mii_marvell.c
420
uint16_t reg;
usr/src/uts/common/io/mii/mii_marvell.c
422
reg = phy_read(ph, MVPHY_PSC);
usr/src/uts/common/io/mii/mii_marvell.c
424
reg &= ~MV_PSC_AUTO_X_MODE;
usr/src/uts/common/io/mii/mii_marvell.c
425
reg |= MV_PSC_ASSERT_CRS_TX;
usr/src/uts/common/io/mii/mii_marvell.c
426
reg &= ~MV_PSC_POL_REVERSE;
usr/src/uts/common/io/mii/mii_marvell.c
427
phy_write(ph, MVPHY_PSC, reg);
usr/src/uts/common/io/mii/miipriv.h
35
#define PHY_SET(phy, reg, bit) \
usr/src/uts/common/io/mii/miipriv.h
36
phy_write(phy, reg, phy_read(phy, reg) | (bit))
usr/src/uts/common/io/mii/miipriv.h
37
#define PHY_CLR(phy, reg, bit) \
usr/src/uts/common/io/mii/miipriv.h
38
phy_write(phy, reg, phy_read(phy, reg) & ~(bit))
usr/src/uts/common/io/mxfe/mxfe.c
1591
mxfe_miiread(mxfe_t *mxfep, int phy, int reg)
usr/src/uts/common/io/mxfe/mxfe.c
1595
return (mxfe_miiread98713(mxfep, phy, reg));
usr/src/uts/common/io/mxfe/mxfe.c
1602
mxfe_miireadgeneral(mxfe_t *mxfep, int phy, int reg)
usr/src/uts/common/io/mxfe/mxfe.c
1627
mxfe_miiwritebit(mxfep, (reg & i) ? 1 : 0);
usr/src/uts/common/io/mxfe/mxfe.c
1644
mxfe_miiread98713(mxfe_t *mxfep, int phy, int reg)
usr/src/uts/common/io/mxfe/mxfe.c
1654
retval = mxfe_miireadgeneral(mxfep, phy, reg);
usr/src/uts/common/io/mxfe/mxfe.c
1660
mxfe_miiwrite(mxfe_t *mxfep, int phy, int reg, uint16_t val)
usr/src/uts/common/io/mxfe/mxfe.c
1664
mxfe_miiwrite98713(mxfep, phy, reg, val);
usr/src/uts/common/io/mxfe/mxfe.c
1672
mxfe_miiwritegeneral(mxfe_t *mxfep, int phy, int reg, uint16_t val)
usr/src/uts/common/io/mxfe/mxfe.c
1696
mxfe_miiwritebit(mxfep, (reg & i) ? 1 : 0);
usr/src/uts/common/io/mxfe/mxfe.c
1713
mxfe_miiwrite98713(mxfe_t *mxfep, int phy, int reg, uint16_t val)
usr/src/uts/common/io/mxfe/mxfe.c
1722
mxfe_miiwritegeneral(mxfep, phy, reg, val);
usr/src/uts/common/io/mxfe/mxfeimpl.h
334
#define GETCSR(mxfep, reg) \
usr/src/uts/common/io/mxfe/mxfeimpl.h
335
ddi_get32(mxfep->mxfe_regshandle, mxfep->mxfe_regs + (reg/4))
usr/src/uts/common/io/mxfe/mxfeimpl.h
337
#define PUTCSR(mxfep, reg, val) \
usr/src/uts/common/io/mxfe/mxfeimpl.h
338
ddi_put32(mxfep->mxfe_regshandle, mxfep->mxfe_regs + (reg/4), val)
usr/src/uts/common/io/mxfe/mxfeimpl.h
340
#define SETBIT(mxfep, reg, val) \
usr/src/uts/common/io/mxfe/mxfeimpl.h
341
PUTCSR(mxfep, reg, GETCSR(mxfep, reg) | (val))
usr/src/uts/common/io/mxfe/mxfeimpl.h
343
#define CLRBIT(mxfep, reg, val) \
usr/src/uts/common/io/mxfe/mxfeimpl.h
344
PUTCSR(mxfep, reg, GETCSR(mxfep, reg) & ~(val))
usr/src/uts/common/io/ntxn/niu.c
134
address.reg_addr = (unm_crbword_t)reg;
usr/src/uts/common/io/ntxn/niu.c
402
unm_niu_gb_drop_crc_t reg;
usr/src/uts/common/io/ntxn/niu.c
443
®, 4);
usr/src/uts/common/io/ntxn/niu.c
446
reg.drop_gb0 = data;
usr/src/uts/common/io/ntxn/niu.c
449
reg.drop_gb1 = data;
usr/src/uts/common/io/ntxn/niu.c
452
reg.drop_gb2 = data;
usr/src/uts/common/io/ntxn/niu.c
455
reg.drop_gb3 = data;
usr/src/uts/common/io/ntxn/niu.c
462
®, 4);
usr/src/uts/common/io/ntxn/niu.c
549
long reg;
usr/src/uts/common/io/ntxn/niu.c
563
reg = 0;
usr/src/uts/common/io/ntxn/niu.c
565
UNM_NIU_GB_DROP_WRONGADDR, (void*)®, 4);
usr/src/uts/common/io/ntxn/niu.c
580
reg = 0x0200;
usr/src/uts/common/io/ntxn/niu.c
582
UNM_NIU_FRAME_COUNT_SELECT, reg);
usr/src/uts/common/io/ntxn/niu.c
585
reg = (0x20 << port);
usr/src/uts/common/io/ntxn/niu.c
587
UNM_NIU_FRAME_COUNT_SELECT, reg);
usr/src/uts/common/io/ntxn/niu.c
591
UNM_NIU_FRAME_COUNT, ®, 4);
usr/src/uts/common/io/ntxn/niu.c
598
} while (reg);
usr/src/uts/common/io/ntxn/niu.c
603
UNM_NIU_XGE_CONFIG_1 + (0x10000 * port), ®, 4);
usr/src/uts/common/io/ntxn/niu.c
605
reg = (reg | 0x2000UL);
usr/src/uts/common/io/ntxn/niu.c
607
reg = (reg & ~0x2000UL);
usr/src/uts/common/io/ntxn/niu.c
610
UNM_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
usr/src/uts/common/io/ntxn/niu.c
626
unm_niu_xg_pause_ctl_t reg;
usr/src/uts/common/io/ntxn/niu.c
631
adapter->unm_nic_hw_read_wx(adapter, UNM_NIU_XG_PAUSE_CTL, ®, 4);
usr/src/uts/common/io/ntxn/niu.c
633
reg.xg0_mask = !enable;
usr/src/uts/common/io/ntxn/niu.c
635
reg.xg1_mask = !enable;
usr/src/uts/common/io/ntxn/niu.c
637
adapter->unm_nic_hw_write_wx(adapter, UNM_NIU_XG_PAUSE_CTL, ®, 4);
usr/src/uts/common/io/ntxn/niu.c
646
unm_niu_gb_pause_ctl_t reg;
usr/src/uts/common/io/ntxn/niu.c
651
adapter->unm_nic_hw_read_wx(adapter, UNM_NIU_GB_PAUSE_CTL, ®, 4);
usr/src/uts/common/io/ntxn/niu.c
654
reg.gb0_mask = !enable;
usr/src/uts/common/io/ntxn/niu.c
657
reg.gb1_mask = !enable;
usr/src/uts/common/io/ntxn/niu.c
660
reg.gb2_mask = !enable;
usr/src/uts/common/io/ntxn/niu.c
664
reg.gb3_mask = !enable;
usr/src/uts/common/io/ntxn/niu.c
667
adapter->unm_nic_hw_write_wx(adapter, UNM_NIU_GB_PAUSE_CTL, ®, 4);
usr/src/uts/common/io/ntxn/niu.c
676
unm_niu_gb_mac_config_0_t reg;
usr/src/uts/common/io/ntxn/niu.c
682
®, 4);
usr/src/uts/common/io/ntxn/niu.c
683
reg.rx_flowctl = enable;
usr/src/uts/common/io/ntxn/niu.c
685
®, 4);
usr/src/uts/common/io/ntxn/niu.c
99
unm_niu_gbe_phy_read(struct unm_adapter_s *adapter, long reg,
usr/src/uts/common/io/ntxn/unm_inc.h
1130
#define PF_LINK_SPEED_VAL(pcifn, reg) \
usr/src/uts/common/io/ntxn/unm_inc.h
1131
(((reg) >> (8 * ((pcifn) & 0x3))) & PF_LINK_SPEED_MASK)
usr/src/uts/common/io/ntxn/unm_inc.h
1172
#define UNM_CAM_RAM(reg) (UNM_CAM_RAM_BASE + (reg))
usr/src/uts/common/io/ntxn/unm_inc.h
1199
#define UNM_PCIE_REG(reg) (UNM_CRB_PCIE + (reg))
usr/src/uts/common/io/ntxn/unm_inc.h
1225
#define UNM_PCIX_PH_REG(reg) (UNM_CRB_PCIE + (reg))
usr/src/uts/common/io/ntxn/unm_inc.h
1276
#define UNM_PCIX_PS_REG(reg) (UNM_CRB_PCIX_MD + (reg))
usr/src/uts/common/io/ntxn/unm_inc.h
1277
#define UNM_PCIX_PS2_REG(reg) (UNM_CRB_PCIE2 + (reg))
usr/src/uts/common/io/ntxn/unm_nic.h
104
#define CRB_NORMAL(reg) \
usr/src/uts/common/io/ntxn/unm_nic.h
105
(reg) - UNM_CRB_PCIX_HOST2 + UNM_CRB_PCIX_HOST
usr/src/uts/common/io/ntxn/unm_nic.h
106
#define CRB_NORMALIZE(adapter, reg) \
usr/src/uts/common/io/ntxn/unm_nic.h
107
(void *)(unsigned long)(pci_base_offset(adapter, CRB_NORMAL(reg)))
usr/src/uts/common/io/ntxn/unm_nic.h
667
long unm_nic_phy_read(unm_adapter *adapter, long reg, __uint32_t *);
usr/src/uts/common/io/ntxn/unm_nic.h
754
long reg, unm_crbword_t *readval);
usr/src/uts/common/io/ntxn/unm_nic_ctx.c
260
u32 cap, reg;
usr/src/uts/common/io/ntxn/unm_nic_ctx.c
351
reg = LE_TO_HOST_32(prsp_rds[i].host_producer_crb);
usr/src/uts/common/io/ntxn/unm_nic_ctx.c
352
rcv_desc->host_rx_producer = UNM_NIC_REG(reg - 0x200);
usr/src/uts/common/io/ntxn/unm_nic_ctx.c
357
reg = LE_TO_HOST_32(prsp_sds[0].host_consumer_crb);
usr/src/uts/common/io/ntxn/unm_nic_ctx.c
358
recv_ctx->host_sds_consumer = UNM_NIC_REG(reg - 0x200);
usr/src/uts/common/io/ntxn/unm_nic_ctx.c
360
reg = LE_TO_HOST_32(prsp_sds[0].interrupt_crb);
usr/src/uts/common/io/ntxn/unm_nic_ctx.c
361
adapter->interrupt_crb = UNM_NIC_REG(reg - 0x200);
usr/src/uts/common/io/ntxn/unm_nic_hw.c
1909
unm_nic_phy_read(unm_adapter *adapter, long reg, __uint32_t *readval)
usr/src/uts/common/io/ntxn/unm_nic_hw.c
1915
ret = unm_niu_gbe_phy_read(adapter, reg, readval);
usr/src/uts/common/io/ntxn/unm_nic_hw.c
1937
long reg = 0;
usr/src/uts/common/io/ntxn/unm_nic_hw.c
1956
(0x10000 * portnum), ®, adapter);
usr/src/uts/common/io/ntxn/unm_nic_hw.c
1958
reg = (reg & ~0x2000UL);
usr/src/uts/common/io/ntxn/unm_nic_hw.c
1960
UNM_NIU_XGE_CONFIG_1 + (0x10000 * portnum), reg);
usr/src/uts/common/io/ntxn/unm_nic_hw.c
60
long reg, unm_crbword_t *readval);
usr/src/uts/common/io/nvme/nvme.c
1269
nvme_put64(nvme_t *nvme, uintptr_t reg, uint64_t val)
usr/src/uts/common/io/nvme/nvme.c
1271
ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x7) == 0);
usr/src/uts/common/io/nvme/nvme.c
1274
ddi_put64(nvme->n_regh, (uint64_t *)(nvme->n_regs + reg), val);
usr/src/uts/common/io/nvme/nvme.c
1278
nvme_put32(nvme_t *nvme, uintptr_t reg, uint32_t val)
usr/src/uts/common/io/nvme/nvme.c
1280
ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x3) == 0);
usr/src/uts/common/io/nvme/nvme.c
1283
ddi_put32(nvme->n_regh, (uint32_t *)(nvme->n_regs + reg), val);
usr/src/uts/common/io/nvme/nvme.c
1287
nvme_get64(nvme_t *nvme, uintptr_t reg)
usr/src/uts/common/io/nvme/nvme.c
1291
ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x7) == 0);
usr/src/uts/common/io/nvme/nvme.c
1294
val = ddi_get64(nvme->n_regh, (uint64_t *)(nvme->n_regs + reg));
usr/src/uts/common/io/nvme/nvme.c
1300
nvme_get32(nvme_t *nvme, uintptr_t reg)
usr/src/uts/common/io/nvme/nvme.c
1304
ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x3) == 0);
usr/src/uts/common/io/nvme/nvme.c
1307
val = ddi_get32(nvme->n_regh, (uint32_t *)(nvme->n_regs + reg));
usr/src/uts/common/io/nxge/npi/npi_fflp.c
41
#define GET_HASHTBL_PART_OFFSET_NVIR(partid, reg) \
usr/src/uts/common/io/nxge/npi/npi_fflp.c
42
((partid * HASHTBL_PART_REG_STEP) + reg)
usr/src/uts/common/io/nxge/npi/npi_fflp.c
44
#define GET_HASHTBL_PART_OFFSET(handle, partid, reg) \
usr/src/uts/common/io/nxge/npi/npi_fflp.c
47
(reg & 0x8) + (HASHTBL_PART_REG_VIR_OFFSET)) : \
usr/src/uts/common/io/nxge/npi/npi_fflp.c
48
(partid * HASHTBL_PART_REG_STEP) + reg)
usr/src/uts/common/io/nxge/npi/npi_fflp.c
50
#define FFLP_PART_OFFSET(partid, reg) ((partid * 8) + reg)
usr/src/uts/common/io/nxge/npi/npi_fflp.c
51
#define FFLP_VLAN_OFFSET(vid, reg) ((vid * 8) + reg)
usr/src/uts/common/io/nxge/npi/npi_ipp.h
121
#define IPP_REG_RD(handle, portn, reg, val) {\
usr/src/uts/common/io/nxge/npi/npi_ipp.h
122
NXGE_REG_RD64(handle, IPP_REG_ADDR(portn, reg), val);\
usr/src/uts/common/io/nxge/npi/npi_ipp.h
125
#define IPP_REG_WR(handle, portn, reg, val) {\
usr/src/uts/common/io/nxge/npi/npi_ipp.h
126
NXGE_REG_WR64(handle, IPP_REG_ADDR(portn, reg), val);\
usr/src/uts/common/io/nxge/npi/npi_mac.c
2411
uint32_t reg;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2418
reg = XPCS_CTRL_1_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2421
reg = XPCS_STATUS_1_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2424
reg = XPCS_DEV_ID_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2427
reg = XPCS_SPEED_ABILITY_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2430
reg = XPCS_DEV_IN_PKG_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2433
reg = XPCS_CTRL_2_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2436
reg = XPCS_STATUS_2_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2439
reg = XPCS_PKG_ID_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2442
reg = XPCS_STATUS_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2445
reg = XPCS_TEST_CTRL_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2448
reg = XPCS_CFG_VENDOR_1_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2451
reg = XPCS_DIAG_VENDOR_2_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2454
reg = XPCS_MASK_1_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2457
reg = XPCS_PKT_CNTR_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2460
reg = XPCS_TX_STATE_MC_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2463
reg = XPCS_DESKEW_ERR_CNTR_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2466
reg = XPCS_SYM_ERR_CNTR_L0_L1_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2469
reg = XPCS_SYM_ERR_CNTR_L2_L3_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2472
reg = XPCS_TRAINING_VECTOR_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2481
XPCS_REG_RD(handle, portn, reg, &val);
usr/src/uts/common/io/nxge/npi/npi_mac.c
2491
uint32_t reg;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2498
reg = XPCS_CTRL_1_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2501
reg = XPCS_TEST_CTRL_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2504
reg = XPCS_CFG_VENDOR_1_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2507
reg = XPCS_DIAG_VENDOR_2_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2510
reg = XPCS_MASK_1_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2513
reg = XPCS_PKT_CNTR_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2516
reg = XPCS_DESKEW_ERR_CNTR_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2519
reg = XPCS_TRAINING_VECTOR_REG;
usr/src/uts/common/io/nxge/npi/npi_mac.c
2530
XPCS_REG_WR(handle, portn, reg, val);
usr/src/uts/common/io/nxge/npi/npi_mac.c
36
#define XMAC_WAIT_REG(handle, portn, reg, val) {\
usr/src/uts/common/io/nxge/npi/npi_mac.c
40
XMAC_REG_RD(handle, portn, reg, &val);\
usr/src/uts/common/io/nxge/npi/npi_mac.c
45
#define BMAC_WAIT_REG(handle, portn, reg, val) {\
usr/src/uts/common/io/nxge/npi/npi_mac.c
49
BMAC_REG_RD(handle, portn, reg, &val);\
usr/src/uts/common/io/nxge/npi/npi_mac.h
277
#define XMAC_REG_WR(handle, portn, reg, val)\
usr/src/uts/common/io/nxge/npi/npi_mac.h
278
NXGE_REG_WR64(handle, XMAC_REG_ADDR((portn), (reg)), (val))
usr/src/uts/common/io/nxge/npi/npi_mac.h
280
#define XMAC_REG_RD(handle, portn, reg, val_p)\
usr/src/uts/common/io/nxge/npi/npi_mac.h
281
NXGE_REG_RD64(handle, XMAC_REG_ADDR((portn), (reg)), (val_p))
usr/src/uts/common/io/nxge/npi/npi_mac.h
283
#define BMAC_REG_WR(handle, portn, reg, val)\
usr/src/uts/common/io/nxge/npi/npi_mac.h
284
NXGE_REG_WR64(handle, BMAC_REG_ADDR((portn), (reg)), (val))
usr/src/uts/common/io/nxge/npi/npi_mac.h
286
#define BMAC_REG_RD(handle, portn, reg, val_p)\
usr/src/uts/common/io/nxge/npi/npi_mac.h
287
NXGE_REG_RD64(handle, BMAC_REG_ADDR((portn), (reg)), (val_p))
usr/src/uts/common/io/nxge/npi/npi_mac.h
289
#define PCS_REG_WR(handle, portn, reg, val)\
usr/src/uts/common/io/nxge/npi/npi_mac.h
290
NXGE_REG_WR64(handle, PCS_REG_ADDR((portn), (reg)), (val))
usr/src/uts/common/io/nxge/npi/npi_mac.h
292
#define PCS_REG_RD(handle, portn, reg, val_p)\
usr/src/uts/common/io/nxge/npi/npi_mac.h
293
NXGE_REG_RD64(handle, PCS_REG_ADDR((portn), (reg)), (val_p))
usr/src/uts/common/io/nxge/npi/npi_mac.h
295
#define XPCS_REG_WR(handle, portn, reg, val)\
usr/src/uts/common/io/nxge/npi/npi_mac.h
296
NXGE_REG_WR64(handle, XPCS_ADDR((portn), (reg)), (val))
usr/src/uts/common/io/nxge/npi/npi_mac.h
298
#define XPCS_REG_RD(handle, portn, reg, val_p)\
usr/src/uts/common/io/nxge/npi/npi_mac.h
299
NXGE_REG_RD64(handle, XPCS_ADDR((portn), (reg)), (val_p))
usr/src/uts/common/io/nxge/npi/npi_mac.h
301
#define MIF_REG_WR(handle, reg, val)\
usr/src/uts/common/io/nxge/npi/npi_mac.h
302
NXGE_REG_WR64(handle, MIF_ADDR((reg)), (val))
usr/src/uts/common/io/nxge/npi/npi_mac.h
304
#define MIF_REG_RD(handle, reg, val_p)\
usr/src/uts/common/io/nxge/npi/npi_mac.h
305
NXGE_REG_RD64(handle, MIF_ADDR((reg)), (val_p))
usr/src/uts/common/io/nxge/npi/npi_mac.h
319
#define MIF_REG_RD_NO_SHOW(handle, reg, val_p)\
usr/src/uts/common/io/nxge/npi/npi_mac.h
320
NXGE_REG_RD64_NO_SHOW(handle, MIF_ADDR((reg)), (val_p))
usr/src/uts/common/io/nxge/npi/npi_mac.h
323
#define MIF_REG_RD_NO_SHOW(handle, reg, val_p)\
usr/src/uts/common/io/nxge/npi/npi_mac.h
324
NXGE_REG_RD64(handle, MIF_ADDR((reg)), (val_p))
usr/src/uts/common/io/nxge/npi/npi_mac.h
327
#define ESR_REG_WR(handle, reg, val)\
usr/src/uts/common/io/nxge/npi/npi_mac.h
328
NXGE_REG_WR64(handle, ESR_ADDR((reg)), (val))
usr/src/uts/common/io/nxge/npi/npi_mac.h
330
#define ESR_REG_RD(handle, reg, val_p)\
usr/src/uts/common/io/nxge/npi/npi_mac.h
331
NXGE_REG_RD64(handle, ESR_ADDR((reg)), (val_p))
usr/src/uts/common/io/nxge/npi/npi_rxdma.h
47
#define REG_FZC_RDC_OFFSET(reg, rdc) (reg + RX_LOG_DMA_OFFSET(rdc))
usr/src/uts/common/io/nxge/npi/npi_txc.h
65
#define TXC_FZC_REG_READ64(handle, reg, cn, val_p) \
usr/src/uts/common/io/nxge/npi/npi_txc.h
67
(NXGE_TXC_FZC_OFFSET(reg, cn)), val_p)
usr/src/uts/common/io/nxge/npi/npi_txc.h
69
#define TXC_FZC_REG_WRITE64(handle, reg, cn, data) \
usr/src/uts/common/io/nxge/npi/npi_txc.h
71
(NXGE_TXC_FZC_OFFSET(reg, cn)), data)
usr/src/uts/common/io/nxge/npi/npi_txc.h
73
#define TXC_FZC_CNTL_REG_READ64(handle, reg, port, val_p) \
usr/src/uts/common/io/nxge/npi/npi_txc.h
75
(NXGE_TXC_FZC_CNTL_OFFSET(reg, port)), val_p)
usr/src/uts/common/io/nxge/npi/npi_txc.h
77
#define TXC_FZC_CNTL_REG_WRITE64(handle, reg, port, data) \
usr/src/uts/common/io/nxge/npi/npi_txc.h
79
(NXGE_TXC_FZC_CNTL_OFFSET(reg, port)), data)
usr/src/uts/common/io/nxge/npi/npi_txdma.h
132
#define TX_LOG_REG_READ64(handle, reg, channel, val_p) \
usr/src/uts/common/io/nxge/npi/npi_txdma.h
133
NXGE_REG_RD64(handle, NXGE_TXLOG_OFFSET(reg, channel), val_p)
usr/src/uts/common/io/nxge/npi/npi_txdma.h
135
#define TX_LOG_REG_WRITE64(handle, reg, channel, data) \
usr/src/uts/common/io/nxge/npi/npi_txdma.h
136
NXGE_REG_WR64(handle, NXGE_TXLOG_OFFSET(reg, channel), data)
usr/src/uts/common/io/nxge/nxge_hio.c
864
dmc_reg_name_t *reg = &rx_names[0];
usr/src/uts/common/io/nxge/nxge_hio.c
868
while (reg->name) {
usr/src/uts/common/io/nxge/nxge_hio.c
869
if (offset == reg->offset)
usr/src/uts/common/io/nxge/nxge_hio.c
870
return (reg->name);
usr/src/uts/common/io/nxge/nxge_hio.c
871
reg++;
usr/src/uts/common/io/nxge/nxge_hio.c
881
dmc_reg_name_t *reg = &tx_names[0];
usr/src/uts/common/io/nxge/nxge_hio.c
885
while (reg->name) {
usr/src/uts/common/io/nxge/nxge_hio.c
886
if (offset == reg->offset)
usr/src/uts/common/io/nxge/nxge_hio.c
887
return (reg->name);
usr/src/uts/common/io/nxge/nxge_hio.c
888
reg++;
usr/src/uts/common/io/nxge/nxge_hw.c
1170
uint16_t reg;
usr/src/uts/common/io/nxge/nxge_hw.c
1174
reg = *(uint16_t *)mp->b_rptr;
usr/src/uts/common/io/nxge/nxge_hw.c
1175
(void) nxge_mii_read(nxgep, nxgep->statsp->mac_stats.xcvr_portn, reg,
usr/src/uts/common/io/nxge/nxge_hw.c
1178
reg, *(uint16_t *)mp->b_rptr));
usr/src/uts/common/io/nxge/nxge_hw.c
1187
uint8_t reg;
usr/src/uts/common/io/nxge/nxge_hw.c
1191
reg = (uint8_t)buf[0];
usr/src/uts/common/io/nxge/nxge_hw.c
1194
reg, buf[0], buf[1]));
usr/src/uts/common/io/nxge/nxge_hw.c
1196
reg, buf[1]);
usr/src/uts/common/io/nxge/nxge_hw.c
941
uint8_t *reg;
usr/src/uts/common/io/nxge/nxge_hw.c
947
reg = (uint8_t *)(nxgep->dev_regs->nxge_regp) + buf[0];
usr/src/uts/common/io/nxge/nxge_hw.c
950
reg, buf[0], buf[1]));
usr/src/uts/common/io/nxge/nxge_hw.c
951
NXGE_PIO_WRITE32(nxge_regh, (uint32_t *)reg, 0, buf[1]);
usr/src/uts/common/io/nxge/nxge_mac.c
2562
nxgep->phy_prop.arr[i].reg, \
usr/src/uts/common/io/nxge/nxge_mac.c
2570
nxgep->phy_prop.arr[i].reg, \
usr/src/uts/common/io/nxge/nxge_mac.c
2879
uint16_t reg, uint8_t *data)
usr/src/uts/common/io/nxge/nxge_mac.c
2892
phy_data = ((address + 1) << NLP2020_XCVR_I2C_ADDR_SH) | reg;
usr/src/uts/common/io/nxge/nxge_mac.c
3413
uint16_t dev, reg, val;
usr/src/uts/common/io/nxge/nxge_mac.c
3497
reg = initseq[i].dev_reg & 0xffff;
usr/src/uts/common/io/nxge/nxge_mac.c
3500
if (reg == NLP_INI_WAIT) {
usr/src/uts/common/io/nxge/nxge_mac.c
3504
dev, reg, val)) != NXGE_OK)
usr/src/uts/common/io/nxge/nxge_main.c
1831
uint64_t reg;
usr/src/uts/common/io/nxge/nxge_main.c
1835
bcopy((char *)mp->b_rptr, (char *)®, sizeof (uint64_t));
usr/src/uts/common/io/nxge/nxge_main.c
1840
NXGE_REG_RD64(nxgep->npi_handle, reg, ®data);
usr/src/uts/common/io/nxge/nxge_main.c
1848
uint64_t reg;
usr/src/uts/common/io/nxge/nxge_main.c
1852
reg = buf[0];
usr/src/uts/common/io/nxge/nxge_main.c
1854
NXGE_NPI_PIO_WRITE64(nxgep->npi_handle, reg, buf[1]);
usr/src/uts/common/io/nxge/nxge_virtual.c
1819
nxgep->phy_prop.arr[i].reg = *(uint16_t *)arr;
usr/src/uts/common/io/nxge/nxge_virtual.c
1828
nxgep->phy_prop.arr[i].reg,
usr/src/uts/common/io/pcic.c
1770
pci_regspec_t *reg;
usr/src/uts/common/io/pcic.c
1986
DDI_PROP_DONTPASS, "reg", (caddr_t)®,
usr/src/uts/common/io/pcic.c
1994
bus = PCI_REG_BUS_G(reg->pci_phys_hi);
usr/src/uts/common/io/pcic.c
1995
dev = PCI_REG_DEV_G(reg->pci_phys_hi);
usr/src/uts/common/io/pcic.c
1996
func = PCI_REG_FUNC_G(reg->pci_phys_hi);
usr/src/uts/common/io/pcic.c
1997
kmem_free((caddr_t)reg, length);
usr/src/uts/common/io/pcic.c
345
static uint32_t pcic_getcb(pcicdev_t *pcic, int reg);
usr/src/uts/common/io/pcic.c
346
static void pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value);
usr/src/uts/common/io/pcic.c
5696
pcic_getb(pcicdev_t *pcic, int socket, int reg)
usr/src/uts/common/io/pcic.c
5703
(void *)pcic, socket, reg);
usr/src/uts/common/io/pcic.c
5713
pcic->ioaddr + CB_R2_OFFSET + reg));
usr/src/uts/common/io/pcic.c
5715
work = (socket * PCIC_SOCKET_1) | reg;
usr/src/uts/common/io/pcic.c
5722
pcic_putb(pcicdev_t *pcic, int socket, int reg, int8_t value)
usr/src/uts/common/io/pcic.c
5730
(void *)pcic, socket, reg, value);
usr/src/uts/common/io/pcic.c
5741
ddi_put8(pcic->handle, pcic->ioaddr + CB_R2_OFFSET + reg,
usr/src/uts/common/io/pcic.c
5745
work = (socket * PCIC_SOCKET_1) | reg;
usr/src/uts/common/io/pcic.c
6192
pcic_getcb(pcicdev_t *pcic, int reg)
usr/src/uts/common/io/pcic.c
6197
(uint32_t *)(pcic->ioaddr + CB_CB_OFFSET + reg)));
usr/src/uts/common/io/pcic.c
6201
pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value)
usr/src/uts/common/io/pcic.c
6206
(uint32_t *)(pcic->ioaddr + CB_CB_OFFSET + reg), value);
usr/src/uts/common/io/pciex/hotplug/pciehpc.c
1307
uint16_t reg;
usr/src/uts/common/io/pciex/hotplug/pciehpc.c
1310
reg = pciehpc_reg_get16(ctrl_p,
usr/src/uts/common/io/pciex/hotplug/pciehpc.c
1314
reg &= ~(PCIE_SLOTCTL_INTR_MASK);
usr/src/uts/common/io/pciex/hotplug/pciehpc.c
1316
PCIE_SLOTCTL, reg);
usr/src/uts/common/io/pciex/hotplug/pciehpc.c
1319
reg = pciehpc_reg_get16(ctrl_p,
usr/src/uts/common/io/pciex/hotplug/pciehpc.c
1322
bus_p->bus_pcie_off + PCIE_SLOTSTS, reg);
usr/src/uts/common/io/pciex/hotplug/pciehpc.c
1905
uint16_t reg;
usr/src/uts/common/io/pciex/hotplug/pciehpc.c
1924
reg = pciehpc_reg_get16(ctrl_p,
usr/src/uts/common/io/pciex/hotplug/pciehpc.c
1928
reg | (intr_mask & ~PCIE_SLOTCTL_HP_INTR_EN));
usr/src/uts/common/io/pciex/hotplug/pciehpc.c
1931
reg = pciehpc_reg_get16(ctrl_p,
usr/src/uts/common/io/pciex/hotplug/pciehpc.c
1934
bus_p->bus_pcie_off + PCIE_SLOTSTS, reg);
usr/src/uts/common/io/pciex/hotplug/pciehpc.c
1937
reg = pciehpc_reg_get16(ctrl_p,
usr/src/uts/common/io/pciex/hotplug/pciehpc.c
1941
reg | intr_mask);
usr/src/uts/common/io/pciex/hotplug/pciehpc.c
1967
uint16_t reg;
usr/src/uts/common/io/pciex/hotplug/pciehpc.c
1970
reg = pciehpc_reg_get16(ctrl_p,
usr/src/uts/common/io/pciex/hotplug/pciehpc.c
1974
reg &= ~(PCIE_SLOTCTL_INTR_MASK);
usr/src/uts/common/io/pciex/hotplug/pciehpc.c
1975
pciehpc_reg_put16(ctrl_p, bus_p->bus_pcie_off + PCIE_SLOTCTL, reg);
usr/src/uts/common/io/pciex/hotplug/pciehpc.c
1978
reg = pciehpc_reg_get16(ctrl_p,
usr/src/uts/common/io/pciex/hotplug/pciehpc.c
1981
bus_p->bus_pcie_off + PCIE_SLOTSTS, reg);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
101
static uint32_t pcishpc_read_reg(pcie_hp_ctrl_t *ctrl_p, int reg);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
102
static void pcishpc_write_reg(pcie_hp_ctrl_t *ctrl_p, int reg,
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1118
uint32_t reg;
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1121
reg = pcishpc_read_reg(ctrl_p, PCI_HP_CTRL_SERR_INT_REG);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1124
reg &= ~PCI_HP_SERR_INT_MASK_ALL;
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1126
pcishpc_write_reg(ctrl_p, PCI_HP_CTRL_SERR_INT_REG, reg);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1130
reg = pcishpc_read_reg(ctrl_p, PCI_HP_LOGICAL_SLOT_REGS+slot);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1131
if ((reg & PCI_HP_SLOT_STATE_MASK) == PCI_HP_SLOT_ENABLED) {
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1132
reg &= ~(PCI_HP_SLOT_MASK_ALL |
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1141
reg &= ~(PCI_HP_SLOT_MASK_ALL);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1145
pcishpc_write_reg(ctrl_p, PCI_HP_LOGICAL_SLOT_REGS+slot, reg);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1164
uint32_t reg;
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1167
reg = pcishpc_read_reg(ctrl_p, PCI_HP_CTRL_SERR_INT_REG);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1170
reg |= PCI_HP_SERR_INT_MASK_ALL;
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1172
pcishpc_write_reg(ctrl_p, PCI_HP_CTRL_SERR_INT_REG, reg);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1176
reg = pcishpc_read_reg(ctrl_p, PCI_HP_LOGICAL_SLOT_REGS+slot);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1179
reg |= PCI_HP_SLOT_MASK_ALL;
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1181
pcishpc_write_reg(ctrl_p, PCI_HP_LOGICAL_SLOT_REGS+slot, reg);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1258
uint32_t reg;
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1260
reg = pcishpc_read_reg(slot_p->hs_ctrl,
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1265
reg & ~PCI_HP_SLOT_MRL_SERR_MASK);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1359
uint32_t reg;
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1361
reg = pcishpc_read_reg(slot_p->hs_ctrl,
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1366
reg | PCI_HP_SLOT_MRL_SERR_MASK);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1794
uint32_t reg;
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1798
reg = pcishpc_read_reg(slot_p->hs_ctrl,
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1802
slot_p->hs_info.cn_state = pcishpc_slot_shpc_to_hpc(reg);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1818
slot_p->hs_power_led_state = pcishpc_led_shpc_to_hpc((reg>>2)&3);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1821
slot_p->hs_attn_led_state = pcishpc_led_shpc_to_hpc((reg>>4)&3);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1839
uint32_t reg, cmd_code;
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1844
reg = pcishpc_read_reg(slot_p->hs_ctrl,
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1851
curr_state = pcishpc_slot_shpc_to_hpc(reg);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1860
if (slot_p->hs_power_led_state != pcishpc_led_shpc_to_hpc((reg>>2)&3)) {
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
1869
if (slot_p->hs_attn_led_state != pcishpc_led_shpc_to_hpc((reg>>4)&3)) {
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2361
pcishpc_read_reg(pcie_hp_ctrl_t *ctrl_p, int reg)
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2367
bus_p->bus_pci_hp_off + PCI_HP_DWORD_SELECT_OFF, (uint8_t)reg);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2371
PCI_HP_DWORD_SELECT_OFF) != (uint8_t)reg) {
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2389
pcishpc_write_reg(pcie_hp_ctrl_t *ctrl_p, int reg, uint32_t data)
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2395
bus_p->bus_pci_hp_off + PCI_HP_DWORD_SELECT_OFF, (uint8_t)reg);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2399
PCI_HP_DWORD_SELECT_OFF) != (uint8_t)reg) {
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2428
uint32_t reg;
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2440
reg = pcishpc_read_reg(ctrl_p, PCI_HP_SLOTS_AVAIL_I_REG);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2443
(reg & 31));
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2446
((reg>>8) & 31));
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2449
((reg>>16) & 31));
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2452
((reg>>24) & 31));
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2454
reg = pcishpc_read_reg(ctrl_p, PCI_HP_SLOTS_AVAIL_II_REG);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2457
(reg & 31));
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2459
reg = pcishpc_read_reg(ctrl_p, PCI_HP_SLOT_CONFIGURATION_REG);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2461
numSlots = (reg & 31);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2467
((reg>>8) & 31));
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2470
((reg>>16) & 0x7ff));
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2473
((reg>>29) & 0x1));
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2476
(reg & PCI_HP_SLOT_CONFIG_MRL_SENSOR) ? "Yes" : "No");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2479
(reg & PCI_HP_SLOT_CONFIG_ATTN_BUTTON) ? "Yes" : "No");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2481
reg = pcishpc_read_reg(ctrl_p, PCI_HP_PROF_IF_SBCR_REG);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2483
switch (reg & 7) {
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2507
((reg>>16) &31));
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2510
((reg>>24) & 0xff));
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2512
reg = pcishpc_read_reg(ctrl_p, PCI_HP_COMMAND_STATUS_REG);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2515
(reg & 0xff));
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2518
((reg>>8) & 31));
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2521
((reg>>16) & 1) ? "Yes" : "No");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2524
((reg>>17) & 1) ? "Yes" : "No");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2527
((reg>>18) & 1) ? "Yes" : "No");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2530
((reg>>19) & 1) ? "Yes" : "No");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2532
reg = pcishpc_read_reg(ctrl_p, PCI_HP_IRQ_LOCATOR_REG);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2535
(reg & PCI_HP_IRQ_CMD_COMPLETE) ? "Yes" : "No");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2539
(reg & (PCI_HP_IRQ_SLOT_N_PENDING<<slot)) ? "Yes" : "No");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2542
reg = pcishpc_read_reg(ctrl_p, PCI_HP_SERR_LOCATOR_REG);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2545
(reg & PCI_HP_IRQ_SERR_ARBITER_PENDING) ? "Yes" : "No");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2549
slot+1, (reg &
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2553
reg = pcishpc_read_reg(ctrl_p, PCI_HP_CTRL_SERR_INT_REG);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2556
(reg & PCI_HP_SERR_INT_GLOBAL_IRQ_MASK) ? "Yes" : "No");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2559
(reg & PCI_HP_SERR_INT_GLOBAL_SERR_MASK) ? "Yes" : "No");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2562
(reg & PCI_HP_SERR_INT_CMD_COMPLETE_MASK) ? "Yes" : "No");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2565
(reg & PCI_HP_SERR_INT_ARBITER_SERR_MASK) ? "Yes" : "No");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2568
(reg & PCI_HP_SERR_INT_CMD_COMPLETE_IRQ) ? "Yes" : "No");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2571
(reg & PCI_HP_SERR_INT_ARBITER_IRQ) ? "Yes" : "No");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2577
reg = pcishpc_read_reg(ctrl_p, PCI_HP_LOGICAL_SLOT_REGS+slot);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2580
pcishpc_slot_textslotstate(pcishpc_slot_shpc_to_hpc(reg)));
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2584
(reg>>2) &3)));
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2588
(reg>>4)&3)));
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2591
((reg>>6)&1) ? "Fault Detected" : "No Fault");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2593
((reg>>7)&1) ? "Depressed" : "Not Depressed");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2595
((reg>>8)&1) ? "Not Closed" : "Closed");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2597
((reg>>9)&1) ? "66mhz" : "33mgz");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2599
switch ((reg>>10)&3) {
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2617
switch ((reg>>12)&3) {
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
262
uint32_t irq_locator, irq_serr_locator, reg;
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2633
slot+1, (reg & PCI_HP_SLOT_PRESENCE_DETECTED) ? "Yes" :
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2636
slot+1, (reg & PCI_HP_SLOT_ISO_PWR_DETECTED) ? "Yes" :
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2639
slot+1, (reg & PCI_HP_SLOT_ATTN_DETECTED) ? "Yes" : "No");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2641
slot+1, (reg & PCI_HP_SLOT_MRL_DETECTED) ? "Yes" : "No");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2643
slot+1, (reg & PCI_HP_SLOT_POWER_DETECTED) ? "Yes" : "No");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2646
slot+1, (reg & PCI_HP_SLOT_PRESENCE_MASK) ? "Yes" : "No");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2648
slot+1, (reg & PCI_HP_SLOT_ISO_PWR_MASK) ? "Yes" : "No");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2650
slot+1, (reg & PCI_HP_SLOT_ATTN_MASK) ? "Yes" : "No");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2652
slot+1, (reg & PCI_HP_SLOT_MRL_MASK) ? "Yes" : "No");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2654
slot+1, (reg & PCI_HP_SLOT_POWER_MASK) ? "Yes" : "No");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2656
slot+1, (reg & PCI_HP_SLOT_MRL_SERR_MASK) ? "Yes" : "No");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
2658
slot+1, (reg & PCI_HP_SLOT_POWER_SERR_MASK) ? "Yes" : "No");
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
281
reg = pcishpc_read_reg(ctrl_p, PCI_HP_CTRL_SERR_INT_REG);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
283
if (reg & PCI_HP_SERR_INT_CMD_COMPLETE_IRQ) {
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
290
if (reg & PCI_HP_SERR_INT_ARBITER_IRQ) {
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
297
pcishpc_write_reg(ctrl_p, PCI_HP_CTRL_SERR_INT_REG, reg);
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
310
reg = pcishpc_read_reg(ctrl_p,
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
313
if (reg & PCI_HP_SLOT_PRESENCE_DETECTED)
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
318
if (reg & PCI_HP_SLOT_ISO_PWR_DETECTED)
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
323
if (reg & PCI_HP_SLOT_ATTN_DETECTED) {
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
341
if (reg & PCI_HP_SLOT_MRL_DETECTED)
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
345
if (reg & PCI_HP_SLOT_POWER_DETECTED)
usr/src/uts/common/io/pciex/hotplug/pcishpc.c
351
reg);
usr/src/uts/common/io/pcn/pcn.c
1324
pcn_mii_read(void *arg, uint8_t phy, uint8_t reg)
usr/src/uts/common/io/pcn/pcn.c
1353
val = ((uint16_t)phy << 5) | reg;
usr/src/uts/common/io/pcn/pcn.c
1354
pcn_bcr_write(pcnp, PCN_BCR_MIIADDR, phy << 5 | reg);
usr/src/uts/common/io/pcn/pcn.c
1369
pcn_mii_write(void *arg, uint8_t phy, uint8_t reg, uint16_t val)
usr/src/uts/common/io/pcn/pcn.c
1373
pcn_bcr_write(pcnp, PCN_BCR_MIIADDR, reg | (phy << 5));
usr/src/uts/common/io/pcn/pcn.c
1411
pcn_csr_read(pcn_t *pcnp, uint32_t reg)
usr/src/uts/common/io/pcn/pcn.c
1416
CSR_WRITE_4(pcnp, PCN_IO32_RAP, reg);
usr/src/uts/common/io/pcn/pcn.c
1423
pcn_csr_read16(pcn_t *pcnp, uint32_t reg)
usr/src/uts/common/io/pcn/pcn.c
1428
CSR_WRITE_2(pcnp, PCN_IO16_RAP, reg);
usr/src/uts/common/io/pcn/pcn.c
1435
pcn_csr_write(pcn_t *pcnp, uint32_t reg, uint32_t val)
usr/src/uts/common/io/pcn/pcn.c
1438
CSR_WRITE_4(pcnp, PCN_IO32_RAP, reg);
usr/src/uts/common/io/pcn/pcn.c
1444
pcn_bcr_read(pcn_t *pcnp, uint32_t reg)
usr/src/uts/common/io/pcn/pcn.c
1449
CSR_WRITE_4(pcnp, PCN_IO32_RAP, reg);
usr/src/uts/common/io/pcn/pcn.c
1456
pcn_bcr_read16(pcn_t *pcnp, uint32_t reg)
usr/src/uts/common/io/pcn/pcn.c
1461
CSR_WRITE_2(pcnp, PCN_IO16_RAP, reg);
usr/src/uts/common/io/pcn/pcn.c
1468
pcn_bcr_write(pcn_t *pcnp, uint32_t reg, uint32_t val)
usr/src/uts/common/io/pcn/pcn.c
1471
CSR_WRITE_4(pcnp, PCN_IO32_RAP, reg);
usr/src/uts/common/io/pcn/pcn.c
60
#define CSR_WRITE_4(pcnp, reg, val) \
usr/src/uts/common/io/pcn/pcn.c
61
ddi_put32(pcnp->pcn_regshandle, (uint32_t *)(pcnp->pcn_regs + reg), val)
usr/src/uts/common/io/pcn/pcn.c
63
#define CSR_WRITE_2(pcnp, reg, val) \
usr/src/uts/common/io/pcn/pcn.c
64
ddi_put16(pcnp->pcn_regshandle, (uint16_t *)(pcnp->pcn_regs + reg), val)
usr/src/uts/common/io/pcn/pcn.c
66
#define CSR_READ_4(pcnp, reg) \
usr/src/uts/common/io/pcn/pcn.c
67
ddi_get32(pcnp->pcn_regshandle, (uint32_t *)(pcnp->pcn_regs + reg))
usr/src/uts/common/io/pcn/pcn.c
69
#define CSR_READ_2(pcnp, reg) \
usr/src/uts/common/io/pcn/pcn.c
70
ddi_get16(pcnp->pcn_regshandle, (uint16_t *)(pcnp->pcn_regs + reg))
usr/src/uts/common/io/pcn/pcn.c
72
#define PCN_CSR_SETBIT(pcnp, reg, x) \
usr/src/uts/common/io/pcn/pcn.c
73
pcn_csr_write(pcnp, reg, pcn_csr_read(pcnp, reg) | (x))
usr/src/uts/common/io/pcn/pcn.c
75
#define PCN_CSR_CLRBIT(pcnp, reg, x) \
usr/src/uts/common/io/pcn/pcn.c
76
pcn_csr_write(pcnp, reg, pcn_csr_read(pcnp, reg) & ~(x))
usr/src/uts/common/io/pcn/pcn.c
78
#define PCN_BCR_SETBIT(pncp, reg, x) \
usr/src/uts/common/io/pcn/pcn.c
79
pcn_bcr_write(pcnp, reg, pcn_bcr_read(pcnp, reg) | (x))
usr/src/uts/common/io/pcn/pcn.c
81
#define PCN_BCR_CLRBIT(pcnp, reg, x) \
usr/src/uts/common/io/pcn/pcn.c
82
pcn_bcr_write(pcnp, reg, pcn_bcr_read(pcnp, reg) & ~(x))
usr/src/uts/common/io/power.c
1162
uint8_t reg;
usr/src/uts/common/io/power.c
1177
reg = ddi_get8(hdl, softsp->power_btn_reg);
usr/src/uts/common/io/power.c
1178
if (reg & softsp->power_btn_bit) {
usr/src/uts/common/io/power.c
1179
reg &= softsp->power_btn_bit;
usr/src/uts/common/io/power.c
1180
ddi_put8(hdl, softsp->power_btn_reg, reg);
usr/src/uts/common/io/power.c
1186
reg = ddi_get8(hdl, ®_base[FIRE_SSI_INTR_ENA]);
usr/src/uts/common/io/power.c
1187
reg |= FIRE_SSI_SHUTDOWN_REQ;
usr/src/uts/common/io/power.c
1188
ddi_put8(hdl, ®_base[FIRE_SSI_INTR_ENA], reg);
usr/src/uts/common/io/power.c
435
uint8_t reg;
usr/src/uts/common/io/power.c
451
EPIC_RD(hdl, softsp->power_btn_reg, reg);
usr/src/uts/common/io/power.c
453
if (reg & EPIC_FIRE_INTERRUPT) { /* PB pressed */
usr/src/uts/common/io/power.c
465
reg = ddi_get8(hdl, softsp->power_btn_reg);
usr/src/uts/common/io/power.c
466
if (reg & softsp->power_btn_bit) {
usr/src/uts/common/io/power.c
467
reg &= softsp->power_btn_bit;
usr/src/uts/common/io/power.c
468
ddi_put8(hdl, softsp->power_btn_reg, reg);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_cxt.c
1268
clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_cxt.c
1269
clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_cxt.c
1270
clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_cxt.c
1272
clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_cxt.c
1273
clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_cxt.c
1274
clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_cxt.c
1276
clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_cxt.c
1277
clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_cxt.c
1278
clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_cxt.c
1280
clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_cxt.c
1281
clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_cxt.c
1282
clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_cxt.c
1284
clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_cxt.c
1285
clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_cxt.c
1286
clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_cxt.c
1288
clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_cxt.c
1289
clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_cxt.c
1290
clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_cxt.c
1650
ilt_clients[i].first.reg,
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_cxt.c
1653
ilt_clients[i].last.reg,
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_cxt.c
1656
ilt_clients[i].p_size.reg,
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_cxt.c
178
u32 reg;
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_cxt.c
90
#define ILT_CFG_REG(cli, reg) PSWRQ2_REG_##cli##_##reg##_RT_OFFSET
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c
3060
const struct dbg_dump_reg *reg = (const struct dbg_dump_reg*)&input_regs_arr.ptr[input_offset];
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c
3063
GET_FIELD(reg->data, DBG_DUMP_REG_ADDRESS),
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c
3064
GET_FIELD(reg->data, DBG_DUMP_REG_LENGTH),
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c
3065
GET_FIELD(reg->data, DBG_DUMP_REG_WIDE_BUS));
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c
4169
const struct dbg_idle_chk_cond_reg *reg = &cond_regs[reg_id];
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c
4176
offset += IDLE_CHK_RESULT_REG_HDR_DWORDS + reg->entry_size;
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c
4182
reg_hdr->start_entry = reg->start_entry;
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c
4183
reg_hdr->size = reg->entry_size;
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c
4184
SET_FIELD(reg_hdr->data, DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM, reg->num_entries > 1 || reg->start_entry > 0 ? 1 : 0);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c
4194
const struct dbg_idle_chk_info_reg *reg = &info_regs[reg_id];
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c
4199
offset += IDLE_CHK_RESULT_REG_HDR_DWORDS + reg->size;
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c
4203
block_id = GET_FIELD(reg->data, DBG_IDLE_CHK_INFO_REG_BLOCK_ID);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c
4218
eval_mode = GET_FIELD(reg->mode.data, DBG_MODE_HDR_EVAL_MODE) > 0;
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c
4220
modes_buf_offset = GET_FIELD(reg->mode.data, DBG_MODE_HDR_MODES_BUF_OFFSET);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c
4227
addr = GET_FIELD(reg->data, DBG_IDLE_CHK_INFO_REG_ADDRESS);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c
4228
wide_bus = GET_FIELD(reg->data, DBG_IDLE_CHK_INFO_REG_WIDE_BUS);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c
4234
reg_hdr->size = reg->size;
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c
4238
offset += ecore_grc_dump_addr_range(p_hwfn, p_ptt, dump_buf + offset, dump, addr, reg->size, wide_bus);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c
4309
const struct dbg_idle_chk_cond_reg *reg = &cond_regs[reg_id];
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c
4316
addr = GET_FIELD(reg->data, DBG_IDLE_CHK_COND_REG_ADDRESS);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c
4317
wide_bus = GET_FIELD(reg->data, DBG_IDLE_CHK_COND_REG_WIDE_BUS);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c
4318
if (reg->num_entries > 1 || reg->start_entry > 0) {
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c
4319
padded_entry_size = reg->entry_size > 1 ? OSAL_ROUNDUP_POW_OF_TWO(reg->entry_size) : 1;
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c
4320
addr += (reg->start_entry + entry_id) * padded_entry_size;
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c
4324
if (next_reg_offset + reg->entry_size >= IDLE_CHK_MAX_ENTRIES_SIZE) {
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c
4329
next_reg_offset += ecore_grc_dump_addr_range(p_hwfn, p_ptt, cond_reg_values + next_reg_offset, dump, addr, reg->entry_size, wide_bus);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_hsi_common.h
2543
__le32 reg;
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_init_fw_funcs.c
413
SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_PQ_VALID, 1);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_init_fw_funcs.c
414
SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_RL_VALID, rl_valid ? 1 : 0);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_init_fw_funcs.c
415
SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_VP_PQ_ID, first_tx_pq_id);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_init_fw_funcs.c
416
SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_RL_ID, rl_valid ? pq_params[i].vport_id : 0);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_init_fw_funcs.c
417
SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_VOQ, voq);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_init_fw_funcs.c
418
SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_WRR_WEIGHT_GROUP, pq_params[i].wrr_group);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_phy.c
1732
u16 port, u16 devad, u16 reg, char *p_phy_result_buf)
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_phy.c
1741
(reg << DRV_MB_PARAM_ADDR_SHIFT)),
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_phy.c
1756
u16 port, u16 devad, u16 reg, u16 val,
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_phy.c
1766
(reg << DRV_MB_PARAM_ADDR_SHIFT)),
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_phy.c
322
u32 reg;
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_phy.c
595
addr = bb_stat_regs[reg_id].reg;
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_phy.c
609
if ((bb_stat_regs[reg_id].reg == 0x0000000f) ||
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_phy.c
610
(bb_stat_regs[reg_id].reg == 0x00000018) ||
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_phy.c
611
(bb_stat_regs[reg_id].reg == 0x00000035))
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_phy.c
639
addr = ah_stat_regs[reg_id].reg;
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_phy_api.h
316
u16 port, u16 devad, u16 reg, char *p_phy_result_buf);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_phy_api.h
332
u16 port, u16 devad, u16 reg, u16 val,
usr/src/uts/common/io/qede/579xx/drivers/ecore/hsi_repository/ecore_hsi_common.h
2543
__le32 reg;
usr/src/uts/common/io/qede/qede.h
973
uint32_t reg;
usr/src/uts/common/io/ral/rt2560.c
1824
sc->bbp_prom[i].reg = val >> 8;
usr/src/uts/common/io/ral/rt2560.c
1854
rt2560_bbp_write(sc, rt2560_def_bbp[i].reg,
usr/src/uts/common/io/ral/rt2560.c
1957
RAL_WRITE(sc, rt2560_def_mac[i].reg, rt2560_def_mac[i].val);
usr/src/uts/common/io/ral/rt2560.c
256
rt2560_bbp_write(struct rt2560_softc *sc, uint8_t reg, uint8_t val)
usr/src/uts/common/io/ral/rt2560.c
271
tmp = RT2560_BBP_WRITE | RT2560_BBP_BUSY | reg << 8 | val;
usr/src/uts/common/io/ral/rt2560.c
274
ral_debug(RAL_DBG_HW, "BBP R%u <- 0x%02x\n", reg, val);
usr/src/uts/common/io/ral/rt2560.c
278
rt2560_bbp_read(struct rt2560_softc *sc, uint8_t reg)
usr/src/uts/common/io/ral/rt2560.c
283
val = RT2560_BBP_BUSY | reg << 8;
usr/src/uts/common/io/ral/rt2560.c
298
rt2560_rf_write(struct rt2560_softc *sc, uint8_t reg, uint32_t val)
usr/src/uts/common/io/ral/rt2560.c
314
(reg & 0x3);
usr/src/uts/common/io/ral/rt2560.c
318
sc->rf_regs[reg] = val;
usr/src/uts/common/io/ral/rt2560.c
320
ral_debug(RAL_DBG_HW, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff);
usr/src/uts/common/io/ral/rt2560.c
74
uint32_t reg;
usr/src/uts/common/io/ral/rt2560.c
81
uint8_t reg;
usr/src/uts/common/io/ral/rt2560_reg.h
322
#define RAL_READ(sc, reg) \
usr/src/uts/common/io/ral/rt2560_reg.h
323
ddi_get32((sc)->sc_ioh, (uint32_t *)((uintptr_t)(sc)->sc_rbase + (reg)))
usr/src/uts/common/io/ral/rt2560_reg.h
325
#define RAL_WRITE(sc, reg, val) \
usr/src/uts/common/io/ral/rt2560_reg.h
327
(uint32_t *)((uintptr_t)(sc)->sc_rbase + (reg)), (val))
usr/src/uts/common/io/ral/rt2560_var.h
179
uint8_t reg;
usr/src/uts/common/io/rge/rge_chip.c
30
#define REG32(rgep, reg) ((uint32_t *)(rgep->io_regs+(reg)))
usr/src/uts/common/io/rge/rge_chip.c
31
#define REG16(rgep, reg) ((uint16_t *)(rgep->io_regs+(reg)))
usr/src/uts/common/io/rge/rge_chip.c
32
#define REG8(rgep, reg) ((uint8_t *)(rgep->io_regs+(reg)))
usr/src/uts/common/io/rge/rge_main.c
913
uint32_t reg;
usr/src/uts/common/io/rge/rge_main.c
930
reg = (~(index / RGE_MCAST_NUM)) & 0x7;
usr/src/uts/common/io/rge/rge_main.c
932
reg = index / RGE_MCAST_NUM;
usr/src/uts/common/io/rge/rge_main.c
939
hashp[reg] |= 1 << (index % RGE_MCAST_NUM);
usr/src/uts/common/io/rge/rge_main.c
945
hashp[reg] &= ~ (1 << (index % RGE_MCAST_NUM));
usr/src/uts/common/io/rtls/rtls.c
1904
rtls_mii_read(void *arg, uint8_t phy, uint8_t reg)
usr/src/uts/common/io/rtls/rtls.c
1912
switch (reg) {
usr/src/uts/common/io/rtls/rtls.c
1946
rtls_mii_write(void *arg, uint8_t phy, uint8_t reg, uint16_t val)
usr/src/uts/common/io/rtls/rtls.c
1954
switch (reg) {
usr/src/uts/common/io/rtls/rtls.c
228
rtls_reg_get8(rtls_t *rtlsp, uint32_t reg)
usr/src/uts/common/io/rtls/rtls.c
232
addr = REG8(rtlsp->io_reg, reg);
usr/src/uts/common/io/rtls/rtls.c
237
rtls_reg_get16(rtls_t *rtlsp, uint32_t reg)
usr/src/uts/common/io/rtls/rtls.c
241
addr = REG16(rtlsp->io_reg, reg);
usr/src/uts/common/io/rtls/rtls.c
246
rtls_reg_get32(rtls_t *rtlsp, uint32_t reg)
usr/src/uts/common/io/rtls/rtls.c
250
addr = REG32(rtlsp->io_reg, reg);
usr/src/uts/common/io/rtls/rtls.c
255
rtls_reg_set8(rtls_t *rtlsp, uint32_t reg, uint8_t value)
usr/src/uts/common/io/rtls/rtls.c
259
addr = REG8(rtlsp->io_reg, reg);
usr/src/uts/common/io/rtls/rtls.c
264
rtls_reg_set16(rtls_t *rtlsp, uint32_t reg, uint16_t value)
usr/src/uts/common/io/rtls/rtls.c
268
addr = REG16(rtlsp->io_reg, reg);
usr/src/uts/common/io/rtls/rtls.c
273
rtls_reg_set32(rtls_t *rtlsp, uint32_t reg, uint32_t value)
usr/src/uts/common/io/rtls/rtls.c
277
addr = REG32(rtlsp->io_reg, reg);
usr/src/uts/common/io/rtls/rtls.h
111
#define REG32(reg, off) ((uint32_t *)((uintptr_t)(reg) + off))
usr/src/uts/common/io/rtls/rtls.h
112
#define REG16(reg, off) ((uint16_t *)((uintptr_t)(reg) + off))
usr/src/uts/common/io/rtls/rtls.h
113
#define REG8(reg, off) ((uint8_t *)((uintptr_t)(reg) + off))
usr/src/uts/common/io/rtw/rtw.c
254
#define PRINTREG32(sc, reg) \
usr/src/uts/common/io/rtw/rtw.c
256
"%s: reg[ " #reg " / %03x ] = %08x\n", \
usr/src/uts/common/io/rtw/rtw.c
257
dvname, reg, RTW_READ(regs, reg))
usr/src/uts/common/io/rtw/rtw.c
259
#define PRINTREG16(sc, reg) \
usr/src/uts/common/io/rtw/rtw.c
261
"%s: reg[ " #reg " / %03x ] = %04x\n", \
usr/src/uts/common/io/rtw/rtw.c
262
dvname, reg, RTW_READ16(regs, reg))
usr/src/uts/common/io/rtw/rtw.c
264
#define PRINTREG8(sc, reg) \
usr/src/uts/common/io/rtw/rtw.c
266
"%s: reg[ " #reg " / %03x ] = %02x\n", \
usr/src/uts/common/io/rtw/rtw.c
267
dvname, reg, RTW_READ8(regs, reg))
usr/src/uts/common/io/rtw/rtwphy.c
102
#define RTW_BBP_WRITE_OR_RETURN(reg, val) \
usr/src/uts/common/io/rtw/rtwphy.c
103
if ((rc = rtw_bbp_write(regs, reg, val)) != 0) \
usr/src/uts/common/io/rtw/rtwphyio.c
108
uint32_t mask, reg;
usr/src/uts/common/io/rtw/rtwphyio.c
114
reg = RTW_PHYCFG_HST;
usr/src/uts/common/io/rtw/rtwphyio.c
115
RTW_WRITE(regs, RTW_PHYCFG, reg);
usr/src/uts/common/io/rtw/rtwphyio.c
129
reg |= RTW_PHYCFG_HST_DATA;
usr/src/uts/common/io/rtw/rtwphyio.c
131
reg &= ~RTW_PHYCFG_HST_DATA;
usr/src/uts/common/io/rtw/rtwphyio.c
133
reg |= RTW_PHYCFG_HST_CLK;
usr/src/uts/common/io/rtw/rtwphyio.c
134
RTW_WRITE(regs, RTW_PHYCFG, reg);
usr/src/uts/common/io/rtw/rtwphyio.c
139
reg &= ~RTW_PHYCFG_HST_CLK;
usr/src/uts/common/io/rtw/rtwphyio.c
140
RTW_WRITE(regs, RTW_PHYCFG, reg);
usr/src/uts/common/io/rtw/rtwphyio.c
149
reg |= RTW_PHYCFG_HST_EN;
usr/src/uts/common/io/rtw/rtwphyio.c
150
RTW_WRITE(regs, RTW_PHYCFG, reg);
usr/src/uts/common/io/rtw/rtwphyio.c
159
rtw_rf_macbangbits(struct rtw_regs *regs, uint32_t reg)
usr/src/uts/common/io/rtw/rtwphyio.c
163
RTW_DPRINTF(RTW_DEBUG_PHY, "%s: %08x\n", __func__, reg);
usr/src/uts/common/io/rtw/rtwphyio.c
165
RTW_WRITE(regs, RTW_PHYCFG, RTW_PHYCFG_MAC_POLL | reg);
usr/src/uts/common/io/rtw/rtwphyio.c
301
uint32_t reg;
usr/src/uts/common/io/rtw/rtwphyio.c
308
reg = rtw_grf5101_mac_crypt(addr, val);
usr/src/uts/common/io/rtw/rtwphyio.c
311
reg = rtw_maxim_swizzle(addr, val);
usr/src/uts/common/io/rtw/rtwphyio.c
316
reg = LSHIFT(addr, RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK) |
usr/src/uts/common/io/rtw/rtwphyio.c
324
reg |= RTW_PHYCFG_MAC_RFTYPE_RFMD;
usr/src/uts/common/io/rtw/rtwphyio.c
327
reg |= RTW_PHYCFG_MAC_RFTYPE_INTERSIL;
usr/src/uts/common/io/rtw/rtwphyio.c
330
reg |= RTW_PHYCFG_MAC_RFTYPE_PHILIPS;
usr/src/uts/common/io/rtw/rtwphyio.c
338
return (rtw_rf_macbangbits(regs, reg));
usr/src/uts/common/io/rtw/rtwreg.h
1243
#define RTW_ISSET(regs, reg, mask) \
usr/src/uts/common/io/rtw/rtwreg.h
1244
(RTW_READ((regs), (reg)) & (mask))
usr/src/uts/common/io/rtw/rtwreg.h
1246
#define RTW_CLR(regs, reg, mask) \
usr/src/uts/common/io/rtw/rtwreg.h
1247
RTW_WRITE((regs), (reg), RTW_READ((regs), (reg)) & ~(mask))
usr/src/uts/common/io/rtw/rtwreg.h
91
#define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask))
usr/src/uts/common/io/rum/rum.c
1367
rum_bbp_write(sc, rum_def_bbp[i].reg, rum_def_bbp[i].val);
usr/src/uts/common/io/rum/rum.c
1371
if (sc->bbp_prom[i].reg == 0 || sc->bbp_prom[i].reg == 0xff)
usr/src/uts/common/io/rum/rum.c
1373
rum_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
usr/src/uts/common/io/rum/rum.c
1685
rum_write(sc, rum_def_mac[i].reg, rum_def_mac[i].val);
usr/src/uts/common/io/rum/rum.c
306
rum_read_multi(struct rum_softc *sc, uint16_t reg, void *buf, int len)
usr/src/uts/common/io/rum/rum.c
318
req.wIndex = reg;
usr/src/uts/common/io/rum/rum.c
339
rum_read(struct rum_softc *sc, uint16_t reg)
usr/src/uts/common/io/rum/rum.c
343
rum_read_multi(sc, reg, &val, sizeof (val));
usr/src/uts/common/io/rum/rum.c
349
rum_write_multi(struct rum_softc *sc, uint16_t reg, void *buf, size_t len)
usr/src/uts/common/io/rum/rum.c
361
req.wIndex = reg;
usr/src/uts/common/io/rum/rum.c
387
rum_write(struct rum_softc *sc, uint16_t reg, uint32_t val)
usr/src/uts/common/io/rum/rum.c
391
rum_write_multi(sc, reg, &tmp, sizeof (tmp));
usr/src/uts/common/io/rum/rum.c
406
uint16_t reg = RT2573_MCU_CODE_BASE;
usr/src/uts/common/io/rum/rum.c
412
for (; size >= 4; reg += 4, ucode += 4, size -= 4) {
usr/src/uts/common/io/rum/rum.c
413
rum_write(sc, reg, UGETDW(ucode));
usr/src/uts/common/io/rum/rum.c
71
uint32_t reg;
usr/src/uts/common/io/rum/rum.c
922
rum_bbp_write(struct rum_softc *sc, uint8_t reg, uint8_t val)
usr/src/uts/common/io/rum/rum.c
937
tmp = RT2573_BBP_BUSY | (reg & 0x7f) << 8 | val;
usr/src/uts/common/io/rum/rum.c
942
rum_bbp_read(struct rum_softc *sc, uint8_t reg)
usr/src/uts/common/io/rum/rum.c
956
val = RT2573_BBP_BUSY | RT2573_BBP_READ | reg << 8;
usr/src/uts/common/io/rum/rum.c
971
rum_rf_write(struct rum_softc *sc, uint8_t reg, uint32_t val)
usr/src/uts/common/io/rum/rum.c
987
(reg & 3);
usr/src/uts/common/io/rum/rum.c
99
uint8_t reg;
usr/src/uts/common/io/rum/rum.c
991
sc->rf_regs[reg] = val;
usr/src/uts/common/io/rum/rum.c
993
ral_debug(RAL_DBG_HW, "RF R[%u] <- 0x%05x\n", reg & 3, val & 0xfffff);
usr/src/uts/common/io/rum/rum_var.h
105
uint8_t reg;
usr/src/uts/common/io/rwd/rt2661.c
100
uint8_t reg;
usr/src/uts/common/io/rwd/rt2661.c
2143
rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg)
usr/src/uts/common/io/rwd/rt2661.c
2159
val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8;
usr/src/uts/common/io/rwd/rt2661.c
2197
rt2661_bbp_write(sc, rt2661_def_bbp[i].reg,
usr/src/uts/common/io/rwd/rt2661.c
2203
if (sc->bbp_prom[i].reg == 0)
usr/src/uts/common/io/rwd/rt2661.c
2205
rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
usr/src/uts/common/io/rwd/rt2661.c
2213
rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val)
usr/src/uts/common/io/rwd/rt2661.c
2229
tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val;
usr/src/uts/common/io/rwd/rt2661.c
2233
"BBP R%u <- 0x%02x\n", reg, val);
usr/src/uts/common/io/rwd/rt2661.c
2309
rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val)
usr/src/uts/common/io/rwd/rt2661.c
2326
(reg & 3);
usr/src/uts/common/io/rwd/rt2661.c
2330
sc->rf_regs[reg] = val;
usr/src/uts/common/io/rwd/rt2661.c
2333
"RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff);
usr/src/uts/common/io/rwd/rt2661.c
2476
RT2661_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val);
usr/src/uts/common/io/rwd/rt2661.c
459
sc->bbp_prom[i].reg = val >> 8;
usr/src/uts/common/io/rwd/rt2661.c
462
"BBP R%d=%02x\n", sc->bbp_prom[i].reg,
usr/src/uts/common/io/rwd/rt2661.c
93
uint32_t reg;
usr/src/uts/common/io/rwd/rt2661_reg.h
332
#define RT2661_READ(sc, reg) \
usr/src/uts/common/io/rwd/rt2661_reg.h
334
(uint32_t *)((uintptr_t)(sc)->sc_io_base + (reg)))
usr/src/uts/common/io/rwd/rt2661_reg.h
336
#define RT2661_WRITE(sc, reg, val) \
usr/src/uts/common/io/rwd/rt2661_reg.h
338
(uint32_t *)((uintptr_t)(sc)->sc_io_base + (reg)), (val))
usr/src/uts/common/io/rwd/rt2661_reg.h
340
#define RT2661_MEM_WRITE1(sc, reg, val) \
usr/src/uts/common/io/rwd/rt2661_reg.h
342
(uint8_t *)((sc)->sc_io_base + (reg)), (val))
usr/src/uts/common/io/rwd/rt2661_reg.h
344
#define RT2661_MEM_READ1(sc, reg) \
usr/src/uts/common/io/rwd/rt2661_reg.h
346
(uint8_t *)((sc)->sc_io_base + (reg)))
usr/src/uts/common/io/rwd/rt2661_var.h
145
uint8_t reg;
usr/src/uts/common/io/rwn/rt2860.c
2020
rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg)
usr/src/uts/common/io/rwn/rt2860.c
2038
RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8);
usr/src/uts/common/io/rwn/rt2860.c
2056
rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)
usr/src/uts/common/io/rwn/rt2860.c
2073
RT2860_BBP_CSR_KICK | reg << 8 | val);
usr/src/uts/common/io/rwn/rt2860.c
2098
rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg,
usr/src/uts/common/io/rwn/rt2860.c
2112
rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val)
usr/src/uts/common/io/rwn/rt2860.c
2130
(val & 0x3fffff) << 2 | (reg & 3);
usr/src/uts/common/io/rwn/rt2860.c
2342
RT2860_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val);
usr/src/uts/common/io/rwn/rt2860.c
2403
if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff)
usr/src/uts/common/io/rwn/rt2860.c
2405
rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val);
usr/src/uts/common/io/rwn/rt2860.c
419
sc->bbp[i].reg = val >> 8;
usr/src/uts/common/io/rwn/rt2860.c
422
sc->bbp[i].reg, sc->bbp[i].val);
usr/src/uts/common/io/rwn/rt2860.c
551
uint32_t reg;
usr/src/uts/common/io/rwn/rt2860.c
554
reg = (uint32_t)val << 16;
usr/src/uts/common/io/rwn/rt2860.c
556
reg |= val;
usr/src/uts/common/io/rwn/rt2860.c
558
sc->txpow20mhz[ridx] = reg;
usr/src/uts/common/io/rwn/rt2860.c
559
sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz);
usr/src/uts/common/io/rwn/rt2860.c
560
sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz);
usr/src/uts/common/io/rwn/rt2860.c
91
uint32_t reg;
usr/src/uts/common/io/rwn/rt2860.c
98
uint8_t reg;
usr/src/uts/common/io/rwn/rt2860_reg.h
815
#define RT2860_READ(sc, reg) \
usr/src/uts/common/io/rwn/rt2860_reg.h
817
(uint32_t *)((uintptr_t)(sc)->sc_io_base + (reg)))
usr/src/uts/common/io/rwn/rt2860_reg.h
819
#define RT2860_WRITE(sc, reg, val) \
usr/src/uts/common/io/rwn/rt2860_reg.h
821
(uint32_t *)((uintptr_t)(sc)->sc_io_base + (reg)), (val))
usr/src/uts/common/io/rwn/rt2860_reg.h
823
#define rt2860_mem_write1(sc, reg, val) \
usr/src/uts/common/io/rwn/rt2860_reg.h
825
(uint8_t *)((sc)->sc_io_base + (reg)), (val))
usr/src/uts/common/io/rwn/rt2860_var.h
201
uint8_t reg;
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
101
uint64_t *addr = (uint64_t *)((uintptr_t)lmrc->l_regmap + reg);
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
1350
uint32_t reg;
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
1361
reg = lmrc_read_reg(lmrc, MPI26_SCRATCHPAD2_OFFSET);
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
1362
lmrc->l_max_raid_map_sz = LMRC_MAX_RAID_MAP_SZ(reg);
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
1371
reg = lmrc_read_reg(lmrc, MPI26_SCRATCHPAD0_OFFSET);
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
1373
if (LMRC_FW_MSIX_ENABLED(reg)) {
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
1376
reg = lmrc_read_reg(lmrc, MPI26_SCRATCHPAD1_OFFSET);
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
1377
lmrc->l_max_reply_queues = LMRC_MAX_REPLY_QUEUES_EXT(reg);
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
1398
reg = lmrc_read_reg(lmrc, MPI26_SCRATCHPAD0_OFFSET);
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
1399
lmrc->l_max_fw_cmds = LMRC_FW_MAX_CMD(reg) - 1;
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
1440
reg = lmrc_read_reg(lmrc, MPI26_SCRATCHPAD1_OFFSET);
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
1441
lmrc->l_max_chain_frame_sz = LMRC_MAX_CHAIN_SIZE(reg) *
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
1442
(LMRC_EXT_CHAIN_SIZE_SUPPORT(reg) ? LMRC_1MB_IO : LMRC_256K_IO);
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
1448
lmrc->l_64bit_dma_support = LMRC_64BIT_DMA_SUPPORT(reg);
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
1493
reg = lmrc_read_reg(lmrc, MPI26_SCRATCHPAD3_OFFSET);
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
1494
if (LMRC_NVME_PAGE_SHIFT(reg) > LMRC_DEFAULT_NVME_PAGE_SHIFT) {
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
1495
lmrc->l_nvme_page_sz = 1 << LMRC_NVME_PAGE_SHIFT(reg);
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
1500
reg = lmrc_read_reg(lmrc, MPI26_SCRATCHPAD1_OFFSET);
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
1501
lmrc->l_fw_sync_cache_support = LMRC_SYNC_CACHE_SUPPORT(reg);
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
1504
reg = lmrc_read_reg(lmrc, MPI26_SCRATCHPAD1_OFFSET);
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
1506
LMRC_ATOMIC_DESCRIPTOR_SUPPORT(reg);
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
295
int reg = 0;
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
302
reg = queue / 8;
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
306
lmrc_write_reg(lmrc, lmrc->l_rphi[reg], val);
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
68
lmrc_read_reg_1(lmrc_t *lmrc, uint32_t reg)
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
70
uint32_t *addr = (uint32_t *)((uintptr_t)lmrc->l_regmap + reg);
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
75
lmrc_read_reg(lmrc_t *lmrc, uint32_t reg)
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
78
return (lmrc_read_reg_1(lmrc, reg));
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
82
uint32_t val = lmrc_read_reg_1(lmrc, reg);
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
901
lmrc_wait_for_reg(lmrc_t *lmrc, uint32_t reg, uint32_t bits, uint32_t exp,
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
911
val = lmrc_read_reg(lmrc, reg);
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
92
lmrc_write_reg(lmrc_t *lmrc, uint32_t reg, uint32_t val)
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
94
uint32_t *addr = (uint32_t *)((uintptr_t)lmrc->l_regmap + reg);
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc.c
99
lmrc_write_reg64(lmrc_t *lmrc, uint32_t reg, uint64_t val)
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h
66
#define LMRC_FW_RESET_REQUIRED(reg) (bitx32((reg), 0, 0) != 0)
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h
67
#define LMRC_FW_RESET_ADAPTER(reg) (bitx32((reg), 1, 1) != 0)
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h
68
#define LMRC_FW_MAX_CMD(reg) bitx32((reg), 15, 0)
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h
69
#define LMRC_FW_MSIX_ENABLED(reg) (bitx32((reg), 26, 26) != 0)
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h
70
#define LMRC_FW_STATE(reg) bitx32((reg), 31, 28)
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h
73
#define LMRC_MAX_CHAIN_SIZE(reg) bitx32((reg), 9, 5)
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h
74
#define LMRC_MAX_REPLY_QUEUES_EXT(reg) bitx32((reg), 21, 14)
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h
75
#define LMRC_EXT_CHAIN_SIZE_SUPPORT(reg) (bitx32((reg), 22, 22) != 0)
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h
76
#define LMRC_RDPQ_MODE_SUPPORT(reg) (bitx32((reg), 23, 23) != 0)
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h
77
#define LMRC_SYNC_CACHE_SUPPORT(reg) (bitx32((reg), 24, 24) != 0)
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h
78
#define LMRC_ATOMIC_DESCRIPTOR_SUPPORT(reg) (bitx32((reg), 24, 24) != 0)
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h
79
#define LMRC_64BIT_DMA_SUPPORT(reg) (bitx32((reg), 25, 25) != 0)
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h
80
#define LMRC_INTR_COALESCING_SUPPORT(reg) (bitx32((reg), 26, 26) != 0)
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h
86
#define LMRC_MAX_RAID_MAP_SZ(reg) bitx32((reg), 24, 16)
usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h
89
#define LMRC_NVME_PAGE_SHIFT(reg) bitx32((reg), 7, 0)
usr/src/uts/common/io/scsi/targets/sd.c
22032
mhioc_register_t reg;
usr/src/uts/common/io/scsi/targets/sd.c
22033
if (ddi_copyin((void *)arg, ®,
usr/src/uts/common/io/scsi/targets/sd.c
22040
(uchar_t *)®);
usr/src/uts/common/io/scsi/targets/sd.c
22054
mhioc_register_t reg;
usr/src/uts/common/io/scsi/targets/sd.c
22055
if (ddi_copyin((void *)arg, ®,
usr/src/uts/common/io/scsi/targets/sd.c
22062
(uchar_t *)®);
usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.c
199
#define GET16(ss, reg) \
usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.c
200
ddi_get16(ss->ss_acch, (void *)(ss->ss_regva + reg))
usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.c
201
#define PUT16(ss, reg, val) \
usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.c
202
ddi_put16(ss->ss_acch, (void *)(ss->ss_regva + reg), val)
usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.c
203
#define GET32(ss, reg) \
usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.c
204
ddi_get32(ss->ss_acch, (void *)(ss->ss_regva + reg))
usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.c
205
#define PUT32(ss, reg, val) \
usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.c
206
ddi_put32(ss->ss_acch, (void *)(ss->ss_regva + reg), val)
usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.c
207
#define GET64(ss, reg) \
usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.c
208
ddi_get64(ss->ss_acch, (void *)(ss->ss_regva + reg))
usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.c
210
#define GET8(ss, reg) \
usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.c
211
ddi_get8(ss->ss_acch, (void *)(ss->ss_regva + reg))
usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.c
212
#define PUT8(ss, reg, val) \
usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.c
213
ddi_put8(ss->ss_acch, (void *)(ss->ss_regva + reg), val)
usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.c
215
#define CLR8(ss, reg, mask) PUT8(ss, reg, GET8(ss, reg) & ~(mask))
usr/src/uts/common/io/sdcard/adapters/sdhost/sdhost.c
216
#define SET8(ss, reg, mask) PUT8(ss, reg, GET8(ss, reg) | (mask))
usr/src/uts/common/io/sfe/sfe.c
1746
sfe_mii_read_sis900(struct gem_dev *dp, uint_t reg)
usr/src/uts/common/io/sfe/sfe.c
1753
cmd = MII_READ_CMD(dp->mii_phy_addr, reg);
usr/src/uts/common/io/sfe/sfe.c
1806
sfe_mii_write_sis900(struct gem_dev *dp, uint_t reg, uint16_t val)
usr/src/uts/common/io/sfe/sfe.c
1812
cmd = MII_WRITE_CMD(dp->mii_phy_addr, reg, val);
usr/src/uts/common/io/sfe/sfe_util.c
2083
gem_mii_read(struct gem_dev *dp, uint_t reg)
usr/src/uts/common/io/sfe/sfe_util.c
2088
return ((*dp->gc.gc_mii_read)(dp, reg));
usr/src/uts/common/io/sfe/sfe_util.c
2092
gem_mii_write(struct gem_dev *dp, uint_t reg, uint16_t val)
usr/src/uts/common/io/sfe/sfe_util.c
2097
(*dp->gc.gc_mii_write)(dp, reg, val);
usr/src/uts/common/io/sfe/sfe_util.h
521
uint16_t (*gc_mii_read)(struct gem_dev *dp, uint_t reg);
usr/src/uts/common/io/sfe/sfe_util.h
523
uint_t reg, uint16_t val);
usr/src/uts/common/io/sfxge/common/efx_nic.c
650
efx_oword_t reg;
usr/src/uts/common/io/sfxge/common/efx_nic.c
667
reg = original;
usr/src/uts/common/io/sfxge/common/efx_nic.c
668
EFX_AND_OWORD(reg, rsp->mask);
usr/src/uts/common/io/sfxge/common/efx_nic.c
669
EFX_SET_OWORD_BIT(reg, bit);
usr/src/uts/common/io/sfxge/common/efx_nic.c
671
EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®,
usr/src/uts/common/io/sfxge/common/efx_nic.c
677
if (memcmp(®, &buf, sizeof (reg))) {
usr/src/uts/common/io/sfxge/common/efx_nic.c
683
EFX_OR_OWORD(reg, rsp->mask);
usr/src/uts/common/io/sfxge/common/efx_nic.c
684
EFX_CLEAR_OWORD_BIT(reg, bit);
usr/src/uts/common/io/sfxge/common/efx_nic.c
686
EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®,
usr/src/uts/common/io/sfxge/common/efx_nic.c
692
if (memcmp(®, &buf, sizeof (reg))) {
usr/src/uts/common/io/sfxge/common/efx_nic.c
729
efx_oword_t reg;
usr/src/uts/common/io/sfxge/common/efx_nic.c
740
func(2 * index + 0, B_FALSE, ®.eo_qword[0]);
usr/src/uts/common/io/sfxge/common/efx_nic.c
741
func(2 * index + 1, B_FALSE, ®.eo_qword[1]);
usr/src/uts/common/io/sfxge/common/efx_nic.c
742
EFX_AND_OWORD(reg, rsp->mask);
usr/src/uts/common/io/sfxge/common/efx_nic.c
743
EFSYS_BAR_WRITEO(enp->en_esbp, address, ®, B_TRUE);
usr/src/uts/common/io/sfxge/common/efx_nic.c
751
func(2 * index + 0, B_FALSE, ®.eo_qword[0]);
usr/src/uts/common/io/sfxge/common/efx_nic.c
752
func(2 * index + 1, B_FALSE, ®.eo_qword[1]);
usr/src/uts/common/io/sfxge/common/efx_nic.c
753
EFX_AND_OWORD(reg, rsp->mask);
usr/src/uts/common/io/sfxge/common/efx_nic.c
755
if (memcmp(®, &buf, sizeof (reg))) {
usr/src/uts/common/io/sock_conf.c
103
ASSERT(reg->__smod_priv != NULL);
usr/src/uts/common/io/sock_conf.c
105
reg->__smod_priv->smodp_sock_create_func;
usr/src/uts/common/io/sock_conf.c
107
reg->__smod_priv->smodp_sock_destroy_func;
usr/src/uts/common/io/sock_conf.c
110
if (reg->smod_proto_create_func == NULL ||
usr/src/uts/common/io/sock_conf.c
111
(reg->__smod_priv != NULL &&
usr/src/uts/common/io/sock_conf.c
112
(reg->__smod_priv->smodp_sock_create_func != NULL ||
usr/src/uts/common/io/sock_conf.c
113
reg->__smod_priv->smodp_sock_destroy_func != NULL))) {
usr/src/uts/common/io/sock_conf.c
121
smodp->smod_proto_create_func = reg->smod_proto_create_func;
usr/src/uts/common/io/sock_conf.c
124
smodp->smod_uc_version = reg->smod_uc_version;
usr/src/uts/common/io/sock_conf.c
125
smodp->smod_dc_version = reg->smod_dc_version;
usr/src/uts/common/io/sock_conf.c
126
if (reg->__smod_priv != NULL) {
usr/src/uts/common/io/sock_conf.c
128
reg->__smod_priv->smodp_proto_fallback_func;
usr/src/uts/common/io/sock_conf.c
130
reg->__smod_priv->smodp_fallback_devpath_v4;
usr/src/uts/common/io/sock_conf.c
132
reg->__smod_priv->smodp_fallback_devpath_v6;
usr/src/uts/common/io/sock_conf.c
71
smod_register(const smod_reg_t *reg)
usr/src/uts/common/io/sock_conf.c
79
if (reg->smod_version != SOCKMOD_VERSION ||
usr/src/uts/common/io/sock_conf.c
80
reg->smod_dc_version != SOCK_DC_VERSION ||
usr/src/uts/common/io/sock_conf.c
81
reg->smod_uc_version != SOCK_UC_VERSION) {
usr/src/uts/common/io/sock_conf.c
84
reg->smod_name);
usr/src/uts/common/io/sock_conf.c
90
if ((smodp = smod_find(reg->smod_name)) != NULL) {
usr/src/uts/common/io/sock_conf.c
97
smodp = smod_create(reg->smod_name);
usr/src/uts/common/io/sock_conf.c
98
smodp->smod_version = reg->smod_version;
usr/src/uts/common/io/uath/uath.c
2413
uath_config_multi(struct uath_softc *sc, uint32_t reg, const void *data,
usr/src/uts/common/io/uath/uath.c
2419
write.reg = BE_32(reg);
usr/src/uts/common/io/uath/uath.c
2428
"could not write %d bytes to register 0x%02x\n", len, reg);
usr/src/uts/common/io/uath/uath.c
2434
uath_config(struct uath_softc *sc, uint32_t reg, uint32_t val)
usr/src/uts/common/io/uath/uath.c
2439
write.reg = BE_32(reg);
usr/src/uts/common/io/uath/uath.c
2448
reg);
usr/src/uts/common/io/uath/uath_reg.h
224
uint32_t reg;
usr/src/uts/common/io/udmf/udmf_usbgem.c
208
uint16_t reg;
usr/src/uts/common/io/ural/ural.c
101
uint8_t reg;
usr/src/uts/common/io/ural/ural.c
1313
ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val);
usr/src/uts/common/io/ural/ural.c
1680
ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val);
usr/src/uts/common/io/ural/ural.c
310
ural_read(struct ural_softc *sc, uint16_t reg)
usr/src/uts/common/io/ural/ural.c
323
req.wIndex = reg;
usr/src/uts/common/io/ural/ural.c
347
ural_read_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len)
usr/src/uts/common/io/ural/ural.c
359
req.wIndex = reg;
usr/src/uts/common/io/ural/ural.c
382
ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val)
usr/src/uts/common/io/ural/ural.c
393
req.wIndex = reg;
usr/src/uts/common/io/ural/ural.c
75
uint16_t reg;
usr/src/uts/common/io/ural/ural.c
918
ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val)
usr/src/uts/common/io/ural/ural.c
933
tmp = reg << 8 | val;
usr/src/uts/common/io/ural/ural.c
938
ural_bbp_read(struct ural_softc *sc, uint8_t reg)
usr/src/uts/common/io/ural/ural.c
943
val = RAL_BBP_WRITE | reg << 8;
usr/src/uts/common/io/ural/ural.c
959
ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val)
usr/src/uts/common/io/ural/ural.c
974
tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xffff) << 2 | (reg & 0x3);
usr/src/uts/common/io/ural/ural.c
979
sc->rf_regs[reg] = val;
usr/src/uts/common/io/ural/ural.c
981
ral_debug(RAL_DBG_HW, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff);
usr/src/uts/common/io/ural/ural_var.h
102
uint8_t reg;
usr/src/uts/common/io/urf/urf_usbgem.c
214
uint8_t reg;
usr/src/uts/common/io/urf/urf_usbgem.c
223
IN(dp, CR, ®, &err, usberr);
usr/src/uts/common/io/urf/urf_usbgem.c
224
if ((reg & CR_SOFT_RST) == 0) {
usr/src/uts/common/io/urf/urf_usbgem.c
555
int reg;
usr/src/uts/common/io/urf/urf_usbgem.c
565
reg = BMCR;
usr/src/uts/common/io/urf/urf_usbgem.c
569
reg = BMSR;
usr/src/uts/common/io/urf/urf_usbgem.c
573
reg = ANAR;
usr/src/uts/common/io/urf/urf_usbgem.c
577
reg = ANLP;
usr/src/uts/common/io/urf/urf_usbgem.c
581
reg = ANER;
usr/src/uts/common/io/urf/urf_usbgem.c
588
IN(dp, reg, &val, errp, usberr);
usr/src/uts/common/io/urf/urf_usbgem.c
616
int reg;
usr/src/uts/common/io/urf/urf_usbgem.c
624
reg = BMCR;
usr/src/uts/common/io/urf/urf_usbgem.c
628
reg = BMSR;
usr/src/uts/common/io/urf/urf_usbgem.c
632
reg = ANAR;
usr/src/uts/common/io/urf/urf_usbgem.c
636
reg = ANLP;
usr/src/uts/common/io/urf/urf_usbgem.c
640
reg = ANER;
usr/src/uts/common/io/urf/urf_usbgem.c
647
OUTW(dp, reg, val, errp, usberr);
usr/src/uts/common/io/urf/urf_usbgem.c
683
uint8_t reg;
usr/src/uts/common/io/urf/urf_usbgem.c
706
IN(dp, URF_EEPROM_BASE + 8, ®, &err, usberr);
usr/src/uts/common/io/urf/urf_usbgem.c
707
new = (new << 8) | reg;
usr/src/uts/common/io/urf/urf_usbgem.c
722
IN(dp, CR, ®, &err, usberr);
usr/src/uts/common/io/urf/urf_usbgem.c
723
if ((reg & CR_AUTOLOAD) == 0) {
usr/src/uts/common/io/urtw/urtw.c
1891
if (rate == urtw_ratetable[i].reg)
usr/src/uts/common/io/urtw/urtw.c
1906
return (urtw_ratetable[i].reg);
usr/src/uts/common/io/urtw/urtw.c
209
uint32_t reg;
usr/src/uts/common/io/urtw/urtw.c
214
uint8_t reg;
usr/src/uts/common/io/urtw/urtw.c
2336
if (error = urtw_8225_write_c(sc, urtw_8225_rf_part1[i].reg,
usr/src/uts/common/io/urtw/urtw.c
2376
urtw_8225_rf_part2[i].reg,
usr/src/uts/common/io/urtw/urtw.c
2387
urtw_8225_rf_part3[i].reg,
usr/src/uts/common/io/urtw/urtw.c
2713
if (error = urtw_8225_write_c(sc, urtw_8225v2_rf_part1[i].reg,
usr/src/uts/common/io/urtw/urtw.c
2785
urtw_8225v2_rf_part2[i].reg,
usr/src/uts/common/io/urtw/urtw.c
2796
urtw_8225v2_rf_part3[i].reg,
usr/src/uts/common/io/urtw/urtw.c
3166
(void) urtw_write8_c(sc, urtw_8187b_regtbl[i].reg,
usr/src/uts/common/io/urtw/urtw.c
3277
(void) urtw_8225_write_c(sc, urtw_8225v2_b_rf[i].reg,
usr/src/uts/common/io/usb/clients/audio/usb_ac/usb_ac.c
4362
usb_as_registration_t *reg)
usr/src/uts/common/io/usb/clients/audio/usb_ac/usb_ac.c
4366
for (n = 0; n < reg->reg_n_formats; n++) {
usr/src/uts/common/io/usb/clients/audio/usb_ac/usb_ac.c
4369
reg->reg_formats[n].fmt_alt,
usr/src/uts/common/io/usb/clients/audio/usb_ac/usb_ac.c
4370
reg->reg_formats[n].fmt_chns,
usr/src/uts/common/io/usb/clients/audio/usb_ac/usb_ac.c
4371
reg->reg_formats[n].fmt_precision,
usr/src/uts/common/io/usb/clients/audio/usb_ac/usb_ac.c
4372
reg->reg_formats[n].fmt_encoding);
usr/src/uts/common/io/usb/clients/audio/usb_ac/usb_ac.c
4378
(void *)®->reg_formats[n]);
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
2240
usb_as_registration_t *reg = &uasp->usb_as_reg;
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
2256
reg->reg_ifno = uasp->usb_as_ifno;
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
2263
if (reg->reg_mode && uasp->usb_as_alts[alt].alt_mode !=
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
2264
reg->reg_mode) {
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
2270
reg->reg_mode = uasp->usb_as_alts[alt].alt_mode;
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
2286
reg->reg_formats[n].fmt_termlink =
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
2289
reg->reg_formats[n].fmt_alt = (uchar_t)alt;
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
2290
reg->reg_formats[n].fmt_chns =
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
2292
reg->reg_formats[n].fmt_precision =
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
2294
reg->reg_formats[n].fmt_encoding =
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
2296
reg->reg_formats[n].fmt_n_srs =
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
2298
reg->reg_formats[n++].fmt_srs =
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
2303
reg->reg_n_formats = (uchar_t)n;
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
2314
for (n = 0; n < reg->reg_n_formats; n++) {
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
2318
reg->reg_formats[n].fmt_termlink,
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
2319
reg->reg_formats[n].fmt_alt,
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
2320
reg->reg_formats[n].fmt_chns,
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
2321
reg->reg_formats[n].fmt_precision,
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
2322
reg->reg_formats[n].fmt_encoding);
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
2325
reg->reg_valid++;
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
756
usb_as_registration_t *reg;
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
771
reg = &uasp->usb_as_reg;
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
778
ddi_get_instance(uasp->usb_as_dip), (void *)reg, (void *)format);
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
780
for (n = 0; n < reg->reg_n_formats; n++) {
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
781
if ((format->fmt_chns == reg->reg_formats[n].fmt_chns) &&
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
782
(format->fmt_precision == reg->reg_formats[n].
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
784
reg->reg_formats[n].fmt_encoding)) {
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
786
int n_srs = reg->reg_formats[n].fmt_n_srs;
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
787
uint_t *srs = reg->reg_formats[n].fmt_srs;
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
806
reg->reg_formats[n].fmt_alt;
usr/src/uts/common/io/usb/clients/audio/usb_as/usb_as.c
811
if (n >= reg->reg_n_formats) {
usr/src/uts/common/io/usb/hcd/xhci/xhci.c
1123
xhci_reg_poll(xhci_t *xhcip, xhci_reg_type_t rt, int reg, uint32_t mask,
usr/src/uts/common/io/usb/hcd/xhci/xhci.c
1129
uint32_t val = xhci_get32(xhcip, rt, reg);
usr/src/uts/common/io/usb/hcd/xhci/xhci.c
1781
uint32_t reg;
usr/src/uts/common/io/usb/hcd/xhci/xhci.c
1783
reg = xhci_get32(xhcip, XHCI_R_OPER, XHCI_USBCMD);
usr/src/uts/common/io/usb/hcd/xhci/xhci.c
1791
reg |= XHCI_CMD_RS;
usr/src/uts/common/io/usb/hcd/xhci/xhci.c
1792
xhci_put32(xhcip, XHCI_R_OPER, XHCI_USBCMD, reg);
usr/src/uts/common/io/usb/hcd/xhci/xhci.c
1872
uint32_t reg;
usr/src/uts/common/io/usb/hcd/xhci/xhci.c
1883
reg = xhci_get32(xhcip, XHCI_R_OPER, XHCI_PORTSC(xic.xic_port));
usr/src/uts/common/io/usb/hcd/xhci/xhci.c
1884
reg &= ~XHCI_PS_CLEAR;
usr/src/uts/common/io/usb/hcd/xhci/xhci.c
1885
reg |= XHCI_PS_CSC | XHCI_PS_PEC | XHCI_PS_WRC | XHCI_PS_OCC |
usr/src/uts/common/io/usb/hcd/xhci/xhci.c
1887
xhci_put32(xhcip, XHCI_R_OPER, XHCI_PORTSC(xic.xic_port), reg);
usr/src/uts/common/io/usb/hcd/xhci/xhci.c
1895
uint32_t reg;
usr/src/uts/common/io/usb/hcd/xhci/xhci.c
1909
reg = xhci_get32(xhcip, XHCI_R_OPER, XHCI_PORTSC(xis.xis_port));
usr/src/uts/common/io/usb/hcd/xhci/xhci.c
1910
reg &= ~XHCI_PS_CLEAR;
usr/src/uts/common/io/usb/hcd/xhci/xhci.c
1911
reg |= XHCI_PS_PLS_SET(xis.xis_pls);
usr/src/uts/common/io/usb/hcd/xhci/xhci.c
1912
reg |= XHCI_PS_LWS;
usr/src/uts/common/io/usb/hcd/xhci/xhci.c
1913
xhci_put32(xhcip, XHCI_R_OPER, XHCI_PORTSC(xis.xis_port), reg);
usr/src/uts/common/io/usb/hcd/xhci/xhci_command.c
195
uint64_t reg;
usr/src/uts/common/io/usb/hcd/xhci/xhci_command.c
211
reg = xhci_get64(xhcip, XHCI_R_OPER, XHCI_CRCR);
usr/src/uts/common/io/usb/hcd/xhci/xhci_command.c
226
reg |= XHCI_CRCR_CA;
usr/src/uts/common/io/usb/hcd/xhci/xhci_command.c
227
xhci_put64(xhcip, XHCI_R_OPER, XHCI_CRCR, reg);
usr/src/uts/common/io/usb/hcd/xhci/xhci_event.c
100
reg |= XHCI_ERSTS_SET(XHCI_EVENT_NSEGS);
usr/src/uts/common/io/usb/hcd/xhci/xhci_event.c
101
xhci_put32(xhcip, XHCI_R_RUN, XHCI_ERSTSZ(0), reg);
usr/src/uts/common/io/usb/hcd/xhci/xhci_event.c
81
uint32_t reg;
usr/src/uts/common/io/usb/hcd/xhci/xhci_event.c
98
reg = xhci_get32(xhcip, XHCI_R_RUN, XHCI_ERSTSZ(0));
usr/src/uts/common/io/usb/hcd/xhci/xhci_event.c
99
reg &= ~XHCI_ERSTS_MASK;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
248
uint32_t reg;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
257
reg = xhci_get32(xhcip, XHCI_R_OPER, XHCI_PORTSC(port));
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
272
reg &= ~XHCI_PS_CLEAR;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
276
reg |= XHCI_PS_PED;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
279
reg &= ~XHCI_PS_PP;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
282
reg |= XHCI_PS_CSC;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
285
reg |= XHCI_PS_PRC;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
288
reg |= XHCI_PS_OCC;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
292
reg |= XHCI_PS_PLC;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
295
reg |= XHCI_PS_PEC;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
298
reg |= XHCI_PS_CEC;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
301
reg |= XHCI_PS_WRC;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
310
xhci_put32(xhcip, XHCI_R_OPER, XHCI_PORTSC(port), reg);
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
328
uint32_t reg;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
339
reg = xhci_get32(xhcip, XHCI_R_OPER, index);
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
354
reg &= ~XHCI_PS_CLEAR;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
359
reg = xhci_get32(xhcip, XHCI_R_OPER, index);
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
367
reg &= ~XHCI_PM3_U1TO_SET(0xff);
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
368
reg |= XHCI_PM3_U1TO_SET(val);
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
372
reg = xhci_get32(xhcip, XHCI_R_OPER, index);
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
380
reg &= ~XHCI_PM3_U1TO_SET(0xff);
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
381
reg |= XHCI_PM3_U1TO_SET(val);
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
384
reg |= XHCI_PS_PLS_SET(val);
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
385
reg |= XHCI_PS_LWS;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
389
reg |= XHCI_PS_WCE;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
391
reg &= ~XHCI_PS_WCE;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
394
reg |= XHCI_PS_WDE;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
396
reg &= ~XHCI_PS_WDE;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
399
reg |= XHCI_PS_WOE;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
401
reg &= ~XHCI_PS_WOE;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
404
reg |= XHCI_PS_WPR;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
407
reg |= XHCI_PS_PR;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
410
reg |= XHCI_PS_PP;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
425
xhci_put32(xhcip, XHCI_R_OPER, index, reg);
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
448
uint32_t reg;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
464
reg = xhci_get32(xhcip, XHCI_R_OPER, XHCI_PORTSC(port));
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
474
if (reg & XHCI_PS_CCS)
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
476
if (reg & XHCI_PS_PED)
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
478
if (reg & XHCI_PS_OCA)
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
480
if (reg & XHCI_PS_PR)
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
483
ps |= XHCI_PS_PLS_SET(XHCI_PS_PLS_GET(reg));
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
485
if (reg & XHCI_PS_PP)
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
494
switch (XHCI_PS_SPEED_GET(reg)) {
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
516
if (reg & XHCI_PS_CSC)
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
518
if (reg & XHCI_PS_PEC)
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
520
if (reg & XHCI_PS_OCC)
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
522
if (reg & XHCI_PS_PRC)
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
524
if (reg & XHCI_PS_WRC)
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
526
if (reg & XHCI_PS_PLC)
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
528
if (reg & XHCI_PS_CEC)
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
624
uint32_t reg;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
626
reg = xhci_get32(xhcip, XHCI_R_OPER, XHCI_PORTSC(i));
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
627
if ((reg & XHCI_HUB_INTR_CHANGE_MASK) != 0)
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
780
uint32_t reg;
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
782
reg = xhci_get32(xhcip, XHCI_R_OPER, XHCI_PORTSC(i));
usr/src/uts/common/io/usb/hcd/xhci/xhci_hub.c
791
if (reg & XHCI_PS_DR)
usr/src/uts/common/io/usb/hcd/xhci/xhci_intr.c
105
uint32_t reg;
usr/src/uts/common/io/usb/hcd/xhci/xhci_intr.c
107
reg = xhci_get32(xhcip, XHCI_R_RUN, XHCI_IMAN(0));
usr/src/uts/common/io/usb/hcd/xhci/xhci_intr.c
108
reg |= XHCI_IMAN_INTR_ENA;
usr/src/uts/common/io/usb/hcd/xhci/xhci_intr.c
109
xhci_put32(xhcip, XHCI_R_RUN, XHCI_IMAN(0), reg);
usr/src/uts/common/io/usb/hcd/xhci/xhci_intr.c
113
reg = xhci_get32(xhcip, XHCI_R_OPER, XHCI_USBCMD);
usr/src/uts/common/io/usb/hcd/xhci/xhci_intr.c
114
reg |= XHCI_CMD_INTE;
usr/src/uts/common/io/usb/hcd/xhci/xhci_intr.c
115
xhci_put32(xhcip, XHCI_R_OPER, XHCI_USBCMD, reg);
usr/src/uts/common/io/usb/usba/usba.c
1783
int reg[1];
usr/src/uts/common/io/usb/usba/usba.c
1835
reg[0] = port;
usr/src/uts/common/io/usb/usba/usba.c
1841
DDI_DEV_T_NONE, child_dip, "reg", reg, 1);
usr/src/uts/common/io/usb/usba/usba.c
2338
int reg[2];
usr/src/uts/common/io/usb/usba/usba.c
2380
reg[0] = first_if;
usr/src/uts/common/io/usb/usba/usba.c
2381
reg[1] = child_ud->usb_cfg_value;
usr/src/uts/common/io/usb/usba/usba.c
2400
DDI_DEV_T_NONE, child_dip, "reg", reg, 2);
usr/src/uts/common/io/usb/usba/usba.c
2583
int reg[2];
usr/src/uts/common/io/usb/usba/usba.c
2625
reg[0] = intf;
usr/src/uts/common/io/usb/usba/usba.c
2626
reg[1] = child_ud->usb_cfg_value;
usr/src/uts/common/io/usb/usba/usba.c
2645
DDI_DEV_T_NONE, child_dip, "reg", reg, 2);
usr/src/uts/common/io/usb/usba/usbai_register.c
266
usb_client_detach(dev_info_t *dip, usb_client_dev_data_t *reg)
usr/src/uts/common/io/usb/usba/usbai_register.c
276
ddi_driver_name(dip), ddi_get_instance(dip), (void *)reg);
usr/src/uts/common/io/usb/usba/usbai_register.c
278
usb_free_dev_data(dip, reg);
usr/src/uts/common/io/usb/usba/usbai_register.c
300
usb_client_dev_data_t **reg, usb_reg_parse_lvl_t parse_level,
usr/src/uts/common/io/usb/usba/usbai_register.c
306
rval = usb_get_dev_data(dip, reg, parse_level, flags);
usr/src/uts/common/io/usb/usba/usbai_register.c
326
usb_unregister_client(dev_info_t *dip, usb_client_dev_data_t *reg)
usr/src/uts/common/io/usb/usba/usbai_register.c
328
usb_client_detach(dip, reg);
usr/src/uts/common/io/usb/usba/usbai_register.c
391
usb_client_dev_data_t **reg, usb_reg_parse_lvl_t parse_level,
usr/src/uts/common/io/usb/usba/usbai_register.c
399
if ((dip == NULL) || (reg == NULL)) {
usr/src/uts/common/io/usb/usba/usbai_register.c
408
*reg = NULL;
usr/src/uts/common/io/usb/usba/usbai_register.c
512
*reg = usb_reg;
usr/src/uts/common/io/usb/usba/usbai_register.c
554
usb_free_dev_data(dev_info_t *dip, usb_client_dev_data_t *reg)
usr/src/uts/common/io/usb/usba/usbai_register.c
563
ddi_driver_name(dip), ddi_get_instance(dip), (void *)reg);
usr/src/uts/common/io/usb/usba/usbai_register.c
565
if (reg != NULL) {
usr/src/uts/common/io/usb/usba/usbai_register.c
570
if (reg->dev_serial != NULL) {
usr/src/uts/common/io/usb/usba/usbai_register.c
571
kmem_free((char *)reg->dev_serial,
usr/src/uts/common/io/usb/usba/usbai_register.c
572
strlen((char *)reg->dev_serial) + 1);
usr/src/uts/common/io/usb/usba/usbai_register.c
575
if (reg->dev_product != NULL) {
usr/src/uts/common/io/usb/usba/usbai_register.c
576
kmem_free((char *)reg->dev_product,
usr/src/uts/common/io/usb/usba/usbai_register.c
577
strlen((char *)reg->dev_product) + 1);
usr/src/uts/common/io/usb/usba/usbai_register.c
580
if (reg->dev_mfg != NULL) {
usr/src/uts/common/io/usb/usba/usbai_register.c
581
kmem_free((char *)reg->dev_mfg,
usr/src/uts/common/io/usb/usba/usbai_register.c
582
strlen((char *)reg->dev_mfg) + 1);
usr/src/uts/common/io/usb/usba/usbai_register.c
586
if (reg->dev_cfg != NULL) {
usr/src/uts/common/io/usb/usba/usbai_register.c
587
usb_free_descr_tree(dip, reg);
usr/src/uts/common/io/usb/usba/usbai_register.c
598
(reg == entry->cddl_dev_data)) {
usr/src/uts/common/io/usb/usba/usbai_register.c
630
kmem_free(reg, sizeof (usb_client_dev_data_t));
usr/src/uts/common/io/usbgem/usbgem.c
1022
usbgem_mii_read(struct usbgem_dev *dp, uint_t reg, int *errp)
usr/src/uts/common/io/usbgem/usbgem.c
1027
val = (*dp->ugc.usbgc_mii_read)(dp, reg, errp);
usr/src/uts/common/io/usbgem/usbgem.c
1034
usbgem_mii_write(struct usbgem_dev *dp, uint_t reg, uint16_t val, int *errp)
usr/src/uts/common/io/usbgem/usbgem.c
1037
(*dp->ugc.usbgc_mii_write)(dp, reg, val, errp);
usr/src/uts/common/io/usbgem/usbgem.h
322
uint16_t (*usbgc_mii_read)(struct usbgem_dev *dp, uint_t reg,
usr/src/uts/common/io/usbgem/usbgem.h
324
void (*usbgc_mii_write)(struct usbgem_dev *dp, uint_t reg,
usr/src/uts/common/io/vr/vr.c
599
bcopy(®s[n], &vrp->regset[n].reg, sizeof (pci_regspec_t));
usr/src/uts/common/io/vr/vr.c
607
addr = vrp->regset[n].reg.pci_phys_hi & PCI_REG_ADDR_M;
usr/src/uts/common/io/vr/vr.c
666
PCI_REG_BUS_G(vrp->acc_cfg->reg.pci_phys_hi),
usr/src/uts/common/io/vr/vr.c
667
PCI_REG_DEV_G(vrp->acc_cfg->reg.pci_phys_hi),
usr/src/uts/common/io/vr/vr.c
668
PCI_REG_FUNC_G(vrp->acc_cfg->reg.pci_phys_hi),
usr/src/uts/common/io/vr/vr.h
439
pci_regspec_t reg;
usr/src/uts/common/io/wpi/wpireg.h
633
#define WPI_READ(sc, reg) \
usr/src/uts/common/io/wpi/wpireg.h
634
ddi_get32((sc)->sc_handle, (uint32_t *)((sc)->sc_base + (reg)))
usr/src/uts/common/io/wpi/wpireg.h
636
#define WPI_WRITE(sc, reg, val) \
usr/src/uts/common/io/wpi/wpireg.h
637
ddi_put32((sc)->sc_handle, (uint32_t *)((sc)->sc_base + (reg)), (val))
usr/src/uts/common/io/xge/hal/include/xgehal-device.h
458
__hal_device_register_poll(xge_hal_device_t *hldev, u64 *reg, int op, u64 mask,
usr/src/uts/common/io/xge/hal/include/xgehal-device.h
821
void __hal_serial_mem_write64(xge_hal_device_t *hldev, u64 value, u64 *reg);
usr/src/uts/common/io/xge/hal/include/xgehal-device.h
823
u64 __hal_serial_mem_read64(xge_hal_device_t *hldev, u64 *reg);
usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c
1268
__hal_serial_mem_write64(xge_hal_device_t *hldev, u64 value, u64 *reg)
usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c
127
__hal_device_register_poll(xge_hal_device_t *hldev, u64 *reg,
usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c
1271
(u32)(value>>32), reg);
usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c
1274
(u32)value, reg);
usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c
1280
__hal_serial_mem_read64(xge_hal_device_t *hldev, u64 *reg)
usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c
1283
reg);
usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c
137
val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, reg);
usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c
146
val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, reg);
usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c
2686
__hal_device_handle_serr(xge_hal_device_t *hldev, char *reg, u64 value)
usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c
2698
xge_debug_device(XGE_ERR, "%s: read "XGE_OS_LLXFMT, reg,
usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c
2706
__hal_device_handle_eccerr(xge_hal_device_t *hldev, char *reg, u64 value)
usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c
2721
xge_debug_device(XGE_ERR, "%s: read "XGE_OS_LLXFMT, reg,
usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c
2729
__hal_device_handle_parityerr(xge_hal_device_t *hldev, char *reg, u64 value)
usr/src/uts/common/io/xge/hal/xgehal/xgehal-device.c
2739
xge_debug_device(XGE_ERR, "%s: read "XGE_OS_LLXFMT, reg,
usr/src/uts/common/io/xge/hal/xgehal/xgehal-mgmt.c
502
int reg = (queue / 4);
usr/src/uts/common/io/xge/hal/xgehal/xgehal-mgmt.c
505
addr = (reg == 1)? (&bar0->ring_bump_counter2) :
usr/src/uts/common/io/yge/yge.c
2419
uint32_t reg;
usr/src/uts/common/io/yge/yge.c
2486
reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
usr/src/uts/common/io/yge/yge.c
2489
reg |= GMF_RX_OVER_ON;
usr/src/uts/common/io/yge/yge.c
2490
CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), reg);
usr/src/uts/common/io/yge/yge.c
2502
reg = RX_GMF_FL_THR_DEF + 1;
usr/src/uts/common/io/yge/yge.c
2506
reg = 0x178;
usr/src/uts/common/io/yge/yge.c
2508
CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_FL_THR), reg);
usr/src/uts/common/io/yge/yge.c
2540
reg = CSR_READ_4(dev, MR_ADDR(pnum, TX_GMF_EA));
usr/src/uts/common/io/yge/yge.c
2541
reg &= ~TX_DYN_WM_ENA;
usr/src/uts/common/io/yge/yge.c
2542
CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_EA), reg);
usr/src/uts/common/io/yge/yge.c
275
yge_mii_readreg(yge_port_t *port, uint8_t phy, uint8_t reg)
usr/src/uts/common/io/yge/yge.c
282
GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
usr/src/uts/common/io/yge/yge.c
304
yge_mii_writereg(yge_port_t *port, uint8_t phy, uint8_t reg, uint16_t val)
usr/src/uts/common/io/yge/yge.c
311
GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg));
usr/src/uts/common/io/yge/yge.c
323
yge_mii_read(void *arg, uint8_t phy, uint8_t reg)
usr/src/uts/common/io/yge/yge.c
329
rv = yge_mii_readreg(port, phy, reg);
usr/src/uts/common/io/yge/yge.c
335
yge_mii_write(void *arg, uint8_t phy, uint8_t reg, uint16_t val)
usr/src/uts/common/io/yge/yge.c
340
yge_mii_writereg(port, phy, reg, val);
usr/src/uts/common/io/yge/yge.h
1816
#define CSR_WRITE_4(d, reg, v) \
usr/src/uts/common/io/yge/yge.h
1817
ddi_put32(d->d_regsh, (uint32_t *)(void *)(d->d_regs + (reg)), (v))
usr/src/uts/common/io/yge/yge.h
1818
#define CSR_WRITE_2(d, reg, v) \
usr/src/uts/common/io/yge/yge.h
1819
ddi_put16(d->d_regsh, (uint16_t *)(void *)(d->d_regs + (reg)), (v))
usr/src/uts/common/io/yge/yge.h
1820
#define CSR_WRITE_1(d, reg, v) \
usr/src/uts/common/io/yge/yge.h
1821
ddi_put8(d->d_regsh, (uint8_t *)(void *)(d->d_regs + (reg)), (v))
usr/src/uts/common/io/yge/yge.h
1823
#define CSR_READ_4(d, reg) \
usr/src/uts/common/io/yge/yge.h
1824
ddi_get32(d->d_regsh, (uint32_t *)(void *)(d->d_regs + (reg)))
usr/src/uts/common/io/yge/yge.h
1825
#define CSR_READ_2(d, reg) \
usr/src/uts/common/io/yge/yge.h
1826
ddi_get16(d->d_regsh, (uint16_t *)(void *)(d->d_regs + (reg)))
usr/src/uts/common/io/yge/yge.h
1827
#define CSR_READ_1(d, reg) \
usr/src/uts/common/io/yge/yge.h
1828
ddi_get8(d->d_regsh, (uint8_t *)(void *)(d->d_regs + (reg)))
usr/src/uts/common/io/yge/yge.h
1830
#define CSR_PCI_WRITE_4(d, reg, v) CSR_WRITE_4(d, Y2_CFG_SPC + (reg), (v))
usr/src/uts/common/io/yge/yge.h
1831
#define CSR_PCI_WRITE_2(d, reg, v) CSR_WRITE_2(d, Y2_CFG_SPC + (reg), (v))
usr/src/uts/common/io/yge/yge.h
1832
#define CSR_PCI_WRITE_1(d, reg, v) CSR_WRITE_1(d, Y2_CFG_SPC + (reg), (v))
usr/src/uts/common/io/yge/yge.h
1834
#define CSR_PCI_READ_4(d, reg) CSR_READ_4(d, Y2_CFG_SPC + (reg))
usr/src/uts/common/io/yge/yge.h
1835
#define CSR_PCI_READ_2(d, reg) CSR_READ_2(d, Y2_CFG_SPC + (reg))
usr/src/uts/common/io/yge/yge.h
1836
#define CSR_PCI_READ_1(d, reg) CSR_READ_1(d, Y2_CFG_SPC + (reg))
usr/src/uts/common/io/yge/yge.h
1838
#define GMAC_REG(port, reg) \
usr/src/uts/common/io/yge/yge.h
1839
((BASE_GMAC_1 + (port) * (BASE_GMAC_2 - BASE_GMAC_1)) | (reg))
usr/src/uts/common/io/yge/yge.h
1840
#define GMAC_WRITE_2(sc, port, reg, val) \
usr/src/uts/common/io/yge/yge.h
1841
CSR_WRITE_2((sc), GMAC_REG((port), (reg)), (val))
usr/src/uts/common/io/yge/yge.h
1842
#define GMAC_READ_2(sc, port, reg) \
usr/src/uts/common/io/yge/yge.h
1843
CSR_READ_2((sc), GMAC_REG((port), (reg)))
usr/src/uts/common/io/yge/yge.h
1844
#define GMAC_READ_4(sc, port, reg) \
usr/src/uts/common/io/yge/yge.h
1845
CSR_READ_4((sc), GMAC_REG((port), (reg)))
usr/src/uts/common/io/zyd/zyd.h
199
uint16_t reg;
usr/src/uts/common/io/zyd/zyd_hw.c
108
zyd_write32(struct zyd_softc *sc, uint16_t reg, uint32_t val)
usr/src/uts/common/io/zyd/zyd_hw.c
113
tmp[0] = LE_16(ZYD_REG32_HI(reg));
usr/src/uts/common/io/zyd/zyd_hw.c
115
tmp[2] = LE_16(ZYD_REG32_LO(reg));
usr/src/uts/common/io/zyd/zyd_hw.c
131
zyd_read16(struct zyd_softc *sc, uint16_t reg, uint16_t *val)
usr/src/uts/common/io/zyd/zyd_hw.c
137
regbuf = LE_16(reg);
usr/src/uts/common/io/zyd/zyd_hw.c
168
zyd_write16(struct zyd_softc *sc, uint16_t reg, uint16_t val)
usr/src/uts/common/io/zyd/zyd_hw.c
173
tmp[0] = LE_16(ZYD_REG32_LO(reg));
usr/src/uts/common/io/zyd/zyd_hw.c
195
res = zyd_write16(sc, reqa[i].reg, reqa[i].value);
usr/src/uts/common/io/zyd/zyd_hw.c
72
zyd_read32(struct zyd_softc *sc, uint16_t reg, uint32_t *val)
usr/src/uts/common/io/zyd/zyd_hw.c
78
regs[0] = LE_16(ZYD_REG32_HI(reg));
usr/src/uts/common/io/zyd/zyd_hw.c
79
regs[1] = LE_16(ZYD_REG32_LO(reg));
usr/src/uts/common/os/brand.c
472
brand_proc_reg_t reg;
usr/src/uts/common/os/brand.c
507
if (copyin((void *)arg1, ®, sizeof (reg)) != 0)
usr/src/uts/common/os/brand.c
516
reg.sbr_version = reg32.sbr_version;
usr/src/uts/common/os/brand.c
517
reg.sbr_handler = (caddr_t)(uintptr_t)reg32.sbr_handler;
usr/src/uts/common/os/brand.c
521
if (reg.sbr_version != brandvers)
usr/src/uts/common/os/brand.c
523
spd->spd_handler = reg.sbr_handler;
usr/src/uts/common/os/sunddi.c
175
} reg, *reglist;
usr/src/uts/common/os/sunddi.c
193
reg = reglist[rnumber];
usr/src/uts/common/os/sunddi.c
194
reg.addr += offset;
usr/src/uts/common/os/sunddi.c
196
reg.size = len;
usr/src/uts/common/os/sunddi.c
201
chosen_reg, (int *)®, (sizeof (reg)/sizeof (int)))
usr/src/uts/common/os/sunpci.c
624
uint16_t reg;
usr/src/uts/common/os/sunpci.c
626
reg = pci_config_get16(confhdl, cap_ptr + PCI_CAP_ID_REGS_OFF);
usr/src/uts/common/os/sunpci.c
628
switch ((reg & PCI_HTCAP_ADDRMAP_MAPTYPE_MASK) >>
usr/src/uts/common/os/sunpci.c
632
nwords = 3 + ((reg & PCI_HTCAP_ADDRMAP_NUMMAP_MASK) * 2);
usr/src/uts/common/os/sunpci.c
652
uint16_t reg;
usr/src/uts/common/os/sunpci.c
654
reg = pci_config_get16(confhdl, cap_ptr + PCI_CAP_ID_REGS_OFF);
usr/src/uts/common/os/sunpci.c
657
nwords = 1 + (reg & PCI_HTCAP_FUNCEXT_LEN_MASK);
usr/src/uts/common/pcmcia/cs/cs.c
6688
uint32_t reg = crt->iobase0_p;
usr/src/uts/common/pcmcia/cs/cs.c
6691
csx_Put8(cis_handle, reg, base & 0x0ff);
usr/src/uts/common/pcmcia/cs/cs.c
6692
reg = reg + 2;
usr/src/uts/common/pcmcia/nexus/pcmcia.c
1852
csregister_t *reg;
usr/src/uts/common/pcmcia/nexus/pcmcia.c
1873
reg = va_arg(arglist, csregister_t *);
usr/src/uts/common/pcmcia/nexus/pcmcia.c
1875
if (reg->cs_magic != PCCS_MAGIC ||
usr/src/uts/common/pcmcia/nexus/pcmcia.c
1876
reg->cs_version != PCCS_VERSION) {
usr/src/uts/common/pcmcia/nexus/pcmcia.c
1879
reg->cs_magic, reg->cs_version,
usr/src/uts/common/pcmcia/nexus/pcmcia.c
1880
(void *)reg->cs_card_services,
usr/src/uts/common/pcmcia/nexus/pcmcia.c
1881
(void *)reg->cs_event);
usr/src/uts/common/pcmcia/nexus/pcmcia.c
1888
reg->cs_event = pcmcia_cis_parser;
usr/src/uts/common/pcmcia/nexus/pcmcia.c
1891
pcmcia_cis_parser = reg->cs_event;
usr/src/uts/common/pcmcia/nexus/pcmcia.c
3011
client_reg_t reg;
usr/src/uts/common/pcmcia/nexus/pcmcia.c
3034
reg.dip = NULL;
usr/src/uts/common/pcmcia/nexus/pcmcia.c
3035
reg.Attributes = INFO_SOCKET_SERVICES;
usr/src/uts/common/pcmcia/nexus/pcmcia.c
3036
reg.EventMask = 0;
usr/src/uts/common/pcmcia/nexus/pcmcia.c
3037
reg.event_handler = NULL;
usr/src/uts/common/pcmcia/nexus/pcmcia.c
3038
reg.Version = CS_VERSION;
usr/src/uts/common/pcmcia/nexus/pcmcia.c
3044
®) != CS_SUCCESS) {
usr/src/uts/common/pcmcia/nexus/pcmcia.c
4350
struct regspec *reg;
usr/src/uts/common/pcmcia/nexus/pcmcia.c
4394
reg = kmem_zalloc(sizeof (pci_regspec_t), KM_SLEEP);
usr/src/uts/common/pcmcia/nexus/pcmcia.c
4395
reg = pcmcia_cons_regspec(pdip, type, (uchar_t *)reg, ra);
usr/src/uts/common/pcmcia/nexus/pcmcia.c
4422
mr.map_obj.rp = reg;
usr/src/uts/common/pcmcia/nexus/pcmcia.c
4440
kmem_free(reg, sizeof (pci_regspec_t));
usr/src/uts/common/pcmcia/nexus/pcmcia.c
4464
struct pcm_regs *reg, *assign;
usr/src/uts/common/pcmcia/nexus/pcmcia.c
4468
reg = &ppd->ppd_reg[rnum];
usr/src/uts/common/pcmcia/nexus/pcmcia.c
4472
assign->phys_hi = reg->phys_hi;
usr/src/uts/common/pcmcia/nexus/pcmcia.c
935
pcmcia_find_rnum(dev_info_t *dip, struct regspec *reg)
usr/src/uts/common/pcmcia/nexus/pcmcia.c
946
if (bcmp(reg, regp, sizeof (struct regspec)) == 0)
usr/src/uts/common/pcmcia/nexus/pcmcia.c
951
if (bcmp(reg, regp, sizeof (struct regspec)) == 0)
usr/src/uts/common/pcmcia/sys/cis_handlers.h
165
#define MAKE_CONFIG_REG_ADDR(base, reg) (base + (reg * 2))
usr/src/uts/common/sys/1394/s1394.h
1118
int s1394_cmp_read(s1394_target_t *target, t1394_cmp_reg_t reg, uint32_t *valp);
usr/src/uts/common/sys/1394/s1394.h
1120
int s1394_cmp_cas(s1394_target_t *target, t1394_cmp_reg_t reg, uint32_t arg_val,
usr/src/uts/common/sys/1394/t1394.h
565
int t1394_cmp_read(t1394_handle_t t1394_hdl, t1394_cmp_reg_t reg,
usr/src/uts/common/sys/1394/t1394.h
568
int t1394_cmp_cas(t1394_handle_t t1394_hdl, t1394_cmp_reg_t reg,
usr/src/uts/common/sys/crypto/dca.h
706
#define PUTMCR32(work, reg, val) \
usr/src/uts/common/sys/crypto/dca.h
708
(uint32_t *)(work->dw_mcr_kaddr + reg), val)
usr/src/uts/common/sys/crypto/dca.h
710
#define PUTMCR16(work, reg, val) \
usr/src/uts/common/sys/crypto/dca.h
712
(uint16_t *)(work->dw_mcr_kaddr + reg), val)
usr/src/uts/common/sys/crypto/dca.h
714
#define GETMCR32(work, reg) \
usr/src/uts/common/sys/crypto/dca.h
715
ddi_get32(work->dw_mcr_acch, (uint32_t *)(work->dw_mcr_kaddr + reg))
usr/src/uts/common/sys/crypto/dca.h
717
#define GETMCR16(work, reg) \
usr/src/uts/common/sys/crypto/dca.h
718
ddi_get16(work->dw_mcr_acch, (uint16_t *)(work->dw_mcr_kaddr + reg))
usr/src/uts/common/sys/crypto/dca.h
720
#define PUTDESC32(req, dc_desc_kaddr, reg, val) \
usr/src/uts/common/sys/crypto/dca.h
722
(uint32_t *)(dc_desc_kaddr + reg), val)
usr/src/uts/common/sys/crypto/dca.h
724
#define PUTDESC16(req, dc_desc_kaddr, reg, val) \
usr/src/uts/common/sys/crypto/dca.h
726
(uint16_t *)(dc_desc_kaddr + reg), val)
usr/src/uts/common/sys/crypto/dca.h
730
#define PUTCTX32(req, reg, val) \
usr/src/uts/common/sys/crypto/dca.h
732
(uint32_t *)(req->dr_ctx_kaddr + reg), val)
usr/src/uts/common/sys/crypto/dca.h
734
#define PUTCTX16(req, reg, val) \
usr/src/uts/common/sys/crypto/dca.h
736
(uint16_t *)(req->dr_ctx_kaddr + reg), val)
usr/src/uts/common/sys/crypto/dca.h
745
#define GETCSR(dca, reg) \
usr/src/uts/common/sys/crypto/dca.h
746
ddi_get32(dca->dca_regs_handle, (uint_t *)(dca->dca_regs + reg))
usr/src/uts/common/sys/crypto/dca.h
748
#define PUTCSR(dca, reg, val) \
usr/src/uts/common/sys/crypto/dca.h
749
ddi_put32(dca->dca_regs_handle, (uint_t *)(dca->dca_regs + reg), val)
usr/src/uts/common/sys/crypto/dca.h
751
#define SETBIT(dca, reg, val) \
usr/src/uts/common/sys/crypto/dca.h
752
PUTCSR(dca, reg, GETCSR(dca, reg) | val)
usr/src/uts/common/sys/crypto/dca.h
754
#define CLRBIT(dca, reg, val) \
usr/src/uts/common/sys/crypto/dca.h
755
PUTCSR(dca, reg, GETCSR(dca, reg) & ~val)
usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h
780
#define UNM_CAM_RAM(reg) (UNM_CAM_RAM_BASE + (reg))
usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h
820
#define UNM_PCIE_REG(reg) (UNM_CRB_PCIE + (reg))
usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h
845
#define UNM_PCIX_PH_REG(reg) (UNM_CRB_PCIE + (reg))
usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h
895
#define UNM_PCIX_PS_REG(reg) (UNM_CRB_PCIX_MD + (reg))
usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h
896
#define UNM_PCIX_PS2_REG(reg) (UNM_CRB_PCIE2 + (reg))
usr/src/uts/common/sys/nxge/nxge_espc_hw.h
53
#define ESPC_REG_ADDR(reg) (FZC_PROM + (reg))
usr/src/uts/common/sys/nxge/nxge_ipp_hw.h
80
#define IPP_REG_ADDR(port_num, reg)\
usr/src/uts/common/sys/nxge/nxge_ipp_hw.h
81
((port_num == 0) ? FZC_IPP + reg : \
usr/src/uts/common/sys/nxge/nxge_ipp_hw.h
82
FZC_IPP + reg + (((port_num % 2) * IPP_PORT_OFFSET) + \
usr/src/uts/common/sys/nxge/nxge_mac_hw.h
224
#define XMAC_REG_ADDR(port_num, reg)\
usr/src/uts/common/sys/nxge/nxge_mac_hw.h
225
(FZC_MAC + (XMAC_ADDR_OFFSET(port_num)) + (reg))
usr/src/uts/common/sys/nxge/nxge_mac_hw.h
238
#define BMAC_REG_ADDR(port_num, reg)\
usr/src/uts/common/sys/nxge/nxge_mac_hw.h
239
(FZC_MAC + (BMAC_ADDR_OFFSET(port_num)) + (reg))
usr/src/uts/common/sys/nxge/nxge_mac_hw.h
256
#define PCS_REG_ADDR(port_num, reg)\
usr/src/uts/common/sys/nxge/nxge_mac_hw.h
257
(FZC_MAC + (PCS_ADDR_OFFSET((port_num)) + (reg)))
usr/src/uts/common/sys/nxge/nxge_mac_hw.h
269
#define XPCS_ADDR(port_num, reg)\
usr/src/uts/common/sys/nxge/nxge_mac_hw.h
270
(FZC_MAC + (XPCS_ADDR_OFFSET((port_num)) + (reg)))
usr/src/uts/common/sys/nxge/nxge_mac_hw.h
277
#define ESR_ADDR(reg)\
usr/src/uts/common/sys/nxge/nxge_mac_hw.h
278
(FZC_MAC + (ESR_ADDR_OFFSET) + (reg))
usr/src/uts/common/sys/nxge/nxge_mac_hw.h
282
#define MIF_ADDR(reg)\
usr/src/uts/common/sys/nxge/nxge_mac_hw.h
283
(FZC_MAC + (MIF_ADDR_OFFSET) + (reg))
usr/src/uts/common/sys/nxge/nxge_phy_hw.h
1007
uint16_t reg;
usr/src/uts/common/sys/pci_impl.h
77
#define PCI_CADDR1(bus, device, function, reg) \
usr/src/uts/common/sys/pci_impl.h
79
| (((function) & 0x7) << 8) | ((reg) & 0xfc))
usr/src/uts/common/sys/pcie.h
1026
reg :6,
usr/src/uts/common/sys/pcie.h
342
#define PCIE_SLOTCAP_PHY_SLOT_NUM(reg) \
usr/src/uts/common/sys/pcie.h
343
(((reg) >> PCIE_SLOTCAP_PHY_SLOT_NUM_SHIFT) & \
usr/src/uts/common/sys/pcie.h
373
#define pcie_slotctl_pwr_indicator_get(reg) \
usr/src/uts/common/sys/pcie.h
374
(((reg) & PCIE_SLOTCTL_PWR_INDICATOR_MASK) >> 8)
usr/src/uts/common/sys/pcie.h
950
reg :6,
usr/src/uts/common/sys/scsi/adapters/mpt_sas/mptsas_var.h
1185
#define ClrSetBits32(hdl, reg, clr, set) \
usr/src/uts/common/sys/scsi/adapters/mpt_sas/mptsas_var.h
1186
ddi_put32(hdl, (reg), \
usr/src/uts/common/sys/scsi/adapters/mpt_sas/mptsas_var.h
1187
((mptsas_hirrd(mpt, (reg)) & ~(clr)) | (set)))
usr/src/uts/common/sys/scsi/adapters/mpt_sas/mptsas_var.h
1189
#define ClrSetBits(reg, clr, set) \
usr/src/uts/common/sys/scsi/adapters/mpt_sas/mptsas_var.h
1190
ddi_put8(mpt->m_datap, (uint8_t *)(reg), \
usr/src/uts/common/sys/scsi/adapters/mpt_sas/mptsas_var.h
1191
((ddi_get8(mpt->m_datap, (uint8_t *)(reg)) & ~(clr)) | (set)))
usr/src/uts/common/sys/vgasubr.h
49
extern int vga_get_reg(vgaregmap_t reg, int i);
usr/src/uts/common/sys/vgasubr.h
50
extern void vga_set_reg(vgaregmap_t reg, int i, int v);
usr/src/uts/common/sys/vgasubr.h
51
extern int vga_get_crtc(vgaregmap_t reg, int i);
usr/src/uts/common/sys/vgasubr.h
52
extern void vga_set_crtc(vgaregmap_t reg, int i, int v);
usr/src/uts/common/sys/vgasubr.h
53
extern int vga_get_seq(vgaregmap_t reg, int i);
usr/src/uts/common/sys/vgasubr.h
54
extern void vga_set_seq(vgaregmap_t reg, int i, int v);
usr/src/uts/common/sys/vgasubr.h
55
extern int vga_get_grc(vgaregmap_t reg, int i);
usr/src/uts/common/sys/vgasubr.h
56
extern void vga_set_grc(vgaregmap_t reg, int i, int v);
usr/src/uts/common/sys/vgasubr.h
57
extern int vga_get_atr(vgaregmap_t reg, int i);
usr/src/uts/common/sys/vgasubr.h
58
extern void vga_set_atr(vgaregmap_t reg, int i, int v);
usr/src/uts/common/sys/vgasubr.h
59
extern void vga_put_cmap(vgaregmap_t reg,
usr/src/uts/common/sys/vgasubr.h
61
extern void vga_get_cmap(vgaregmap_t reg,
usr/src/uts/common/sys/vgasubr.h
63
extern void vga_get_hardware_settings(vgaregmap_t reg,
usr/src/uts/common/sys/vgasubr.h
65
extern void vga_set_indexed(vgaregmap_t reg, int indexreg,
usr/src/uts/common/sys/vgasubr.h
67
extern int vga_get_indexed(vgaregmap_t reg, int indexreg,
usr/src/uts/common/sys/vgasubr.h
83
extern void vga_dump_regs(vgaregmap_t reg,
usr/src/uts/common/syscall/lseek.c
100
if (reg && off > (max - curoff)) {
usr/src/uts/common/syscall/lseek.c
105
if (reg && noff > max) {
usr/src/uts/common/syscall/lseek.c
116
if (reg && (off > (max - (offset_t)vattr.va_size))) {
usr/src/uts/common/syscall/lseek.c
121
if (reg && noff > max) {
usr/src/uts/common/syscall/lseek.c
149
if (reg && (noff > max))
usr/src/uts/common/syscall/lseek.c
180
if (reg && (noff > max))
usr/src/uts/common/syscall/lseek.c
192
ASSERT((reg && noff <= max) || !reg);
usr/src/uts/common/syscall/lseek.c
83
int reg;
usr/src/uts/common/syscall/lseek.c
86
reg = (vp->v_type == VREG);
usr/src/uts/common/syscall/lseek.c
93
if (reg && noff > max) {
usr/src/uts/common/xen/os/hypercall.c
234
HYPERVISOR_set_segment_base(int reg, ulong_t value)
usr/src/uts/common/xen/os/hypercall.c
236
return (__hypercall2(__HYPERVISOR_set_segment_base, (long)reg, value));
usr/src/uts/common/xen/public/arch-x86/xen-mca.h
154
uint64_t reg; /* MSR */
usr/src/uts/common/xen/public/physdev.h
118
uint32_t reg;
usr/src/uts/common/xen/public/platform.h
237
struct xen_power_register reg; /* GAS for Cx trigger register */
usr/src/uts/common/xen/public/platform.h
63
uint32_t reg;
usr/src/uts/common/xen/public/platform.h
79
uint32_t reg;
usr/src/uts/common/xen/public/platform.h
88
uint32_t reg;
usr/src/uts/i86pc/cpu/amd_opteron/ao_cpu.c
62
ao_pcicfg_write(uint_t procnodeid, uint_t func, uint_t reg, uint32_t val)
usr/src/uts/i86pc/cpu/amd_opteron/ao_cpu.c
66
ASSERT((reg & 3) == 0 && reg < 256);
usr/src/uts/i86pc/cpu/amd_opteron/ao_cpu.c
68
cmi_pci_putl(0, procnodeid + 24, func, reg, 0, val);
usr/src/uts/i86pc/cpu/amd_opteron/ao_cpu.c
72
ao_pcicfg_read(uint_t procnodeid, uint_t func, uint_t reg)
usr/src/uts/i86pc/cpu/amd_opteron/ao_cpu.c
76
ASSERT((reg & 3) == 0 && reg < 256);
usr/src/uts/i86pc/cpu/amd_opteron/ao_cpu.c
78
return (cmi_pci_getl(0, procnodeid + 24, func, reg, 0, 0));
usr/src/uts/i86pc/cpu/authenticamd/authamd_main.c
228
authamd_pcicfg_write(uint_t procnodeid, uint_t func, uint_t reg, uint32_t val)
usr/src/uts/i86pc/cpu/authenticamd/authamd_main.c
232
ASSERT((reg & 3) == 0 && reg < 4096);
usr/src/uts/i86pc/cpu/authenticamd/authamd_main.c
234
cmi_pci_putl(0, procnodeid + 24, func, reg, 0, val);
usr/src/uts/i86pc/cpu/authenticamd/authamd_main.c
238
authamd_pcicfg_read(uint_t procnodeid, uint_t func, uint_t reg)
usr/src/uts/i86pc/cpu/authenticamd/authamd_main.c
242
ASSERT((reg & 3) == 0 && reg < 4096);
usr/src/uts/i86pc/cpu/authenticamd/authamd_main.c
244
return (cmi_pci_getl(0, procnodeid + 24, func, reg, 0, 0));
usr/src/uts/i86pc/cpu/genuineintel/gintel_main.c
61
#define MC_COR_ECC_CNT(chipid, reg) (*pci_getl_func)(SOCKET_BUS(chipid), \
usr/src/uts/i86pc/cpu/genuineintel/gintel_main.c
63
0x80 + (reg) * 4)
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
473
acpidev_regspec_t reg;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
475
reg.phys_hi = high;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
476
reg.phys_mid = addrp->Address.Minimum >> 32;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
477
reg.phys_low = addrp->Address.Minimum & 0xFFFFFFFF;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
478
reg.size_hi = addrp->Address.AddressLength >> 32;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
479
reg.size_low = addrp->Address.AddressLength &
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
481
rc = acpidev_resource_insert_reg(rhdl, ®);
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
544
acpidev_regspec_t reg;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
546
reg.phys_hi = high;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
547
reg.phys_mid = addrp->Address.Minimum >> 32;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
548
reg.phys_low = addrp->Address.Minimum & 0xFFFFFFFF;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
549
reg.size_hi = addrp->Address.AddressLength >> 32;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
550
reg.size_low = addrp->Address.AddressLength &
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
552
rc = acpidev_resource_insert_reg(rhdl, ®);
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
825
acpidev_regspec_t reg;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
827
reg.phys_hi = ACPIDEV_REG_TYPE_IO;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
828
reg.phys_hi |= ACPIDEV_REG_IO_RANGE_FULL;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
831
reg.phys_hi |= ACPIDEV_REG_IO_DECODE16;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
833
reg.phys_low = rscp->Data.Io.Minimum;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
834
reg.size_low = rscp->Data.Io.AddressLength;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
836
reg.phys_hi |= ACPIDEV_REG_IO_DECODE16;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
837
reg.phys_low = rscp->Data.FixedIo.Address;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
838
reg.size_low = rscp->Data.FixedIo.AddressLength;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
840
reg.phys_mid = 0;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
841
reg.size_hi = 0;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
842
if ((uint64_t)reg.phys_low + reg.size_low > UINT16_MAX) {
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
846
} else if (reg.size_low != 0) {
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
847
rc = acpidev_resource_insert_reg(rhdl, ®);
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
859
acpidev_regspec_t reg;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
861
reg.phys_hi = ACPIDEV_REG_TYPE_MEMORY;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
862
reg.phys_hi |= ACPIDEV_REG_MEM_COHERENT_CA;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
866
reg.phys_hi |= ACPIDEV_REG_MEM_WRITABLE;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
868
reg.phys_low = rscp->Data.Memory32.Minimum;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
869
reg.size_low = rscp->Data.Memory32.AddressLength;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
873
reg.phys_hi |= ACPIDEV_REG_MEM_WRITABLE;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
875
reg.phys_low = rscp->Data.FixedMemory32.Address;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
876
reg.size_low = rscp->Data.FixedMemory32.AddressLength;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
878
reg.phys_mid = 0;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
879
reg.size_hi = 0;
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
880
if ((uint64_t)reg.phys_low + reg.size_low > UINT32_MAX) {
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
885
} else if (reg.size_low != 0) {
usr/src/uts/i86pc/io/acpi/acpidev/acpidev_resource.c
886
rc = acpidev_resource_insert_reg(rhdl, ®);
usr/src/uts/i86pc/io/gfx_private/gfxp_vgatext.c
1232
pci_regspec_t *reg;
usr/src/uts/i86pc/io/gfx_private/gfxp_vgatext.c
1235
"reg", (caddr_t)®, &length) != DDI_PROP_SUCCESS) {
usr/src/uts/i86pc/io/gfx_private/gfxp_vgatext.c
1240
if ((reg[index].pci_phys_hi & himask) != hival)
usr/src/uts/i86pc/io/gfx_private/gfxp_vgatext.c
1242
if (reg[index].pci_size_hi != 0)
usr/src/uts/i86pc/io/gfx_private/gfxp_vgatext.c
1244
if (reg[index].pci_phys_mid != 0)
usr/src/uts/i86pc/io/gfx_private/gfxp_vgatext.c
1246
if (reg[index].pci_phys_low > addr)
usr/src/uts/i86pc/io/gfx_private/gfxp_vgatext.c
1248
if (reg[index].pci_phys_low + reg[index].pci_size_low <= addr)
usr/src/uts/i86pc/io/gfx_private/gfxp_vgatext.c
1251
*offset = addr - reg[index].pci_phys_low;
usr/src/uts/i86pc/io/gfx_private/gfxp_vgatext.c
1252
kmem_free(reg, (size_t)length);
usr/src/uts/i86pc/io/gfx_private/gfxp_vgatext.c
1255
kmem_free(reg, (size_t)length);
usr/src/uts/i86pc/io/gfx_private/gfxp_vgatext.c
1291
struct regspec *reg;
usr/src/uts/i86pc/io/gfx_private/gfxp_vgatext.c
1294
"reg", (caddr_t)®, &length) != DDI_PROP_SUCCESS) {
usr/src/uts/i86pc/io/gfx_private/gfxp_vgatext.c
1299
if (reg[index].regspec_bustype != hival)
usr/src/uts/i86pc/io/gfx_private/gfxp_vgatext.c
1301
if (reg[index].regspec_addr > addr)
usr/src/uts/i86pc/io/gfx_private/gfxp_vgatext.c
1303
if (reg[index].regspec_addr + reg[index].regspec_size <= addr)
usr/src/uts/i86pc/io/gfx_private/gfxp_vgatext.c
1306
*offset = addr - reg[index].regspec_addr;
usr/src/uts/i86pc/io/gfx_private/gfxp_vgatext.c
1307
kmem_free(reg, (size_t)length);
usr/src/uts/i86pc/io/gfx_private/gfxp_vgatext.c
1310
kmem_free(reg, (size_t)length);
usr/src/uts/i86pc/io/immu_dmar.c
657
struct regspec reg;
usr/src/uts/i86pc/io/immu_dmar.c
665
reg.regspec_bustype = 0;
usr/src/uts/i86pc/io/immu_dmar.c
666
reg.regspec_addr = drhd->dr_regs;
usr/src/uts/i86pc/io/immu_dmar.c
667
reg.regspec_size = IMMU_REGSZ;
usr/src/uts/i86pc/io/immu_dmar.c
683
dip, "reg", (int *)®,
usr/src/uts/i86pc/io/immu_regs.c
824
immu_regs_get64(immu_t *immu, uint_t reg)
usr/src/uts/i86pc/io/immu_regs.c
826
return (get_reg64(immu, reg));
usr/src/uts/i86pc/io/immu_regs.c
830
immu_regs_get32(immu_t *immu, uint_t reg)
usr/src/uts/i86pc/io/immu_regs.c
832
return (get_reg32(immu, reg));
usr/src/uts/i86pc/io/immu_regs.c
836
immu_regs_put64(immu_t *immu, uint_t reg, uint64_t val)
usr/src/uts/i86pc/io/immu_regs.c
838
put_reg64(immu, reg, val);
usr/src/uts/i86pc/io/immu_regs.c
842
immu_regs_put32(immu_t *immu, uint_t reg, uint32_t val)
usr/src/uts/i86pc/io/immu_regs.c
844
put_reg32(immu, reg, val);
usr/src/uts/i86pc/io/ioat/ioat_chan.c
185
uint16_t reg;
usr/src/uts/i86pc/io/ioat/ioat_chan.c
187
reg = ddi_get16(state->is_reg_handle,
usr/src/uts/i86pc/io/ioat/ioat_chan.c
189
ASSERT(reg & 0x2);
usr/src/uts/i86pc/io/pci/pci.c
336
struct regspec64 reg;
usr/src/uts/i86pc/io/pci/pci.c
427
reg.regspec_bustype = 1;
usr/src/uts/i86pc/io/pci/pci.c
432
reg.regspec_bustype = 0;
usr/src/uts/i86pc/io/pci/pci.c
439
reg.regspec_addr = (uint64_t)pci_rp->pci_phys_mid << 32 |
usr/src/uts/i86pc/io/pci/pci.c
441
reg.regspec_size = (uint64_t)pci_rp->pci_size_hi << 32 |
usr/src/uts/i86pc/io/pci/pci.c
448
if (reg.regspec_addr + offset < MAX(reg.regspec_addr, offset))
usr/src/uts/i86pc/io/pci/pci.c
450
reg.regspec_addr += offset;
usr/src/uts/i86pc/io/pci/pci.c
452
reg.regspec_size = len;
usr/src/uts/i86pc/io/pci/pci.c
454
mp->map_obj.rp = (struct regspec *)®
usr/src/uts/i86pc/io/pci/pci.c
503
reg.regspec_bustype = 1;
usr/src/uts/i86pc/io/pci/pci.c
507
reg.regspec_bustype = 0;
usr/src/uts/i86pc/io/pci/pci.c
513
reg.regspec_addr = (uint64_t)pci_rp->pci_phys_mid << 32 |
usr/src/uts/i86pc/io/pci/pci.c
515
reg.regspec_size = pci_rlength;
usr/src/uts/i86pc/io/pci/pci.c
521
if (reg.regspec_addr + offset < MAX(reg.regspec_addr, offset))
usr/src/uts/i86pc/io/pci/pci.c
523
reg.regspec_addr += offset;
usr/src/uts/i86pc/io/pci/pci.c
525
reg.regspec_size = len;
usr/src/uts/i86pc/io/pci/pci.c
527
mp->map_obj.rp = (struct regspec *)®
usr/src/uts/i86pc/io/pci/pci_common.c
1532
int reg;
usr/src/uts/i86pc/io/pci/pci_common.c
1536
reg = (int)(uintptr_t)addr;
usr/src/uts/i86pc/io/pci/pci_common.c
1541
reg);
usr/src/uts/i86pc/io/pci/pci_common.c
1568
int reg;
usr/src/uts/i86pc/io/pci/pci_common.c
1572
reg = (int)(uintptr_t)addr;
usr/src/uts/i86pc/io/pci/pci_common.c
1577
reg);
usr/src/uts/i86pc/io/pci/pci_common.c
1604
int reg;
usr/src/uts/i86pc/io/pci/pci_common.c
1608
reg = (int)(uintptr_t)addr;
usr/src/uts/i86pc/io/pci/pci_common.c
1613
cfp->c_funcnum, reg);
usr/src/uts/i86pc/io/pci/pci_common.c
1640
int reg;
usr/src/uts/i86pc/io/pci/pci_common.c
1644
reg = (int)(uintptr_t)addr;
usr/src/uts/i86pc/io/pci/pci_common.c
1649
cfp->c_funcnum, reg, value);
usr/src/uts/i86pc/io/pci/pci_common.c
1673
int reg;
usr/src/uts/i86pc/io/pci/pci_common.c
1677
reg = (int)(uintptr_t)addr;
usr/src/uts/i86pc/io/pci/pci_common.c
1682
cfp->c_funcnum, reg, value);
usr/src/uts/i86pc/io/pci/pci_common.c
1706
int reg;
usr/src/uts/i86pc/io/pci/pci_common.c
1710
reg = (int)(uintptr_t)addr;
usr/src/uts/i86pc/io/pci/pci_common.c
1715
cfp->c_funcnum, reg, value);
usr/src/uts/i86pc/io/pciex/npe.c
513
struct regspec64 reg;
usr/src/uts/i86pc/io/pciex/npe.c
585
reg.regspec_bustype = 1;
usr/src/uts/i86pc/io/pciex/npe.c
612
reg.regspec_bustype = 0;
usr/src/uts/i86pc/io/pciex/npe.c
619
reg.regspec_addr = (uint64_t)pci_rp->pci_phys_mid << 32 |
usr/src/uts/i86pc/io/pciex/npe.c
621
reg.regspec_size = (uint64_t)pci_rp->pci_size_hi << 32 |
usr/src/uts/i86pc/io/pciex/npe.c
628
if (reg.regspec_addr + offset < MAX(reg.regspec_addr, offset))
usr/src/uts/i86pc/io/pciex/npe.c
630
reg.regspec_addr += offset;
usr/src/uts/i86pc/io/pciex/npe.c
632
reg.regspec_size = len;
usr/src/uts/i86pc/io/pciex/npe.c
634
mp->map_obj.rp = (struct regspec *)®
usr/src/uts/i86pc/io/pciex/npe.c
749
reg.regspec_bustype = 1;
usr/src/uts/i86pc/io/pciex/npe.c
754
reg.regspec_bustype = 0;
usr/src/uts/i86pc/io/pciex/npe.c
760
reg.regspec_addr = (uint64_t)pci_rp->pci_phys_mid << 32 |
usr/src/uts/i86pc/io/pciex/npe.c
762
reg.regspec_size = pci_rlength;
usr/src/uts/i86pc/io/pciex/npe.c
768
if (reg.regspec_addr + offset < MAX(reg.regspec_addr, offset))
usr/src/uts/i86pc/io/pciex/npe.c
770
reg.regspec_addr += offset;
usr/src/uts/i86pc/io/pciex/npe.c
772
reg.regspec_size = len;
usr/src/uts/i86pc/io/pciex/npe.c
775
mp->map_obj.rp = (struct regspec *)®
usr/src/uts/i86pc/io/pciex/npe_misc.c
232
uint16_t reg;
usr/src/uts/i86pc/io/pciex/npe_misc.c
238
reg = pci_config_get16(cfg_hdl, ptr + PCI_CAP_ID_REGS_OFF);
usr/src/uts/i86pc/io/pciex/npe_misc.c
239
reg |= PCI_HTCAP_MSIMAP_ENABLE;
usr/src/uts/i86pc/io/pciex/npe_misc.c
241
pci_config_put16(cfg_hdl, ptr + PCI_CAP_ID_REGS_OFF, reg);
usr/src/uts/i86pc/io/pcplusmp/apic_common.c
1622
ioapic_read(int ioapic_ix, uint32_t reg)
usr/src/uts/i86pc/io/pcplusmp/apic_common.c
1627
ioapic[APIC_IO_REG] = reg;
usr/src/uts/i86pc/io/pcplusmp/apic_common.c
1632
ioapic_write(int ioapic_ix, uint32_t reg, uint32_t value)
usr/src/uts/i86pc/io/pcplusmp/apic_common.c
1637
ioapic[APIC_IO_REG] = reg;
usr/src/uts/i86pc/io/pcplusmp/apic_regops.c
45
static uint64_t local_apic_read(uint32_t reg);
usr/src/uts/i86pc/io/pcplusmp/apic_regops.c
46
static void local_apic_write(uint32_t reg, uint64_t value);
usr/src/uts/i86pc/io/pcplusmp/apic_regops.c
91
local_apic_read(uint32_t reg)
usr/src/uts/i86pc/io/pcplusmp/apic_regops.c
93
return ((uint32_t)apicadr[reg]);
usr/src/uts/i86pc/io/pcplusmp/apic_regops.c
97
local_apic_write(uint32_t reg, uint64_t value)
usr/src/uts/i86pc/io/pcplusmp/apic_regops.c
99
apicadr[reg] = (uint32_t)value;
usr/src/uts/i86pc/io/todpc_subr.c
350
unsigned char reg;
usr/src/uts/i86pc/io/todpc_subr.c
371
reg = inb(RTC_DATA);
usr/src/uts/i86pc/io/todpc_subr.c
372
if ((reg & RTC_VRT) != 0)
usr/src/uts/i86pc/io/todpc_subr.c
382
reg = inb(RTC_DATA);
usr/src/uts/i86pc/io/todpc_subr.c
383
if (reg & RTC_UIP) {
usr/src/uts/i86pc/io/todpc_subr.c
405
reg = inb(RTC_DATA);
usr/src/uts/i86pc/io/todpc_subr.c
406
if (reg != ((struct rtc_t *)buf)->rtc_sec ||
usr/src/uts/i86pc/io/todpc_subr.c
423
unsigned char reg;
usr/src/uts/i86pc/io/todpc_subr.c
435
reg = inb(RTC_DATA);
usr/src/uts/i86pc/io/todpc_subr.c
437
outb(RTC_DATA, reg | RTC_SET); /* allow time set now */
usr/src/uts/i86pc/io/todpc_subr.c
458
reg = inb(RTC_DATA);
usr/src/uts/i86pc/io/todpc_subr.c
460
outb(RTC_DATA, reg & ~RTC_SET); /* allow time update */
usr/src/uts/i86pc/os/cmi_hw.c
1110
mci->mcinj_msr[0].reg = msr;
usr/src/uts/i86pc/os/cmi_hw.c
1895
cmi_pci_get_cmn(int bus, int dev, int func, int reg, int asz,
usr/src/uts/i86pc/os/cmi_hw.c
1901
pcii_lookup(bus, dev, func, reg, asz, &val)) {
usr/src/uts/i86pc/os/cmi_hw.c
1915
val = pci_config_get8(hdl, (off_t)reg);
usr/src/uts/i86pc/os/cmi_hw.c
1918
reg);
usr/src/uts/i86pc/os/cmi_hw.c
1922
val = pci_config_get16(hdl, (off_t)reg);
usr/src/uts/i86pc/os/cmi_hw.c
1925
reg);
usr/src/uts/i86pc/os/cmi_hw.c
1929
val = pci_config_get32(hdl, (off_t)reg);
usr/src/uts/i86pc/os/cmi_hw.c
1932
reg);
usr/src/uts/i86pc/os/cmi_hw.c
1941
cmi_pci_getb(int bus, int dev, int func, int reg, int *interpose,
usr/src/uts/i86pc/os/cmi_hw.c
1944
return ((uint8_t)cmi_pci_get_cmn(bus, dev, func, reg, 1, interpose,
usr/src/uts/i86pc/os/cmi_hw.c
1949
cmi_pci_getw(int bus, int dev, int func, int reg, int *interpose,
usr/src/uts/i86pc/os/cmi_hw.c
1952
return ((uint16_t)cmi_pci_get_cmn(bus, dev, func, reg, 2, interpose,
usr/src/uts/i86pc/os/cmi_hw.c
1957
cmi_pci_getl(int bus, int dev, int func, int reg, int *interpose,
usr/src/uts/i86pc/os/cmi_hw.c
1960
return (cmi_pci_get_cmn(bus, dev, func, reg, 4, interpose, hdl));
usr/src/uts/i86pc/os/cmi_hw.c
1964
cmi_pci_interposeb(int bus, int dev, int func, int reg, uint8_t val)
usr/src/uts/i86pc/os/cmi_hw.c
1966
pcii_addent(bus, dev, func, reg, val, 1);
usr/src/uts/i86pc/os/cmi_hw.c
1970
cmi_pci_interposew(int bus, int dev, int func, int reg, uint16_t val)
usr/src/uts/i86pc/os/cmi_hw.c
1972
pcii_addent(bus, dev, func, reg, val, 2);
usr/src/uts/i86pc/os/cmi_hw.c
1976
cmi_pci_interposel(int bus, int dev, int func, int reg, uint32_t val)
usr/src/uts/i86pc/os/cmi_hw.c
1978
pcii_addent(bus, dev, func, reg, val, 4);
usr/src/uts/i86pc/os/cmi_hw.c
1982
cmi_pci_put_cmn(int bus, int dev, int func, int reg, int asz,
usr/src/uts/i86pc/os/cmi_hw.c
1988
pcii_rment(bus, dev, func, reg, asz);
usr/src/uts/i86pc/os/cmi_hw.c
1996
pci_config_put8(hdl, (off_t)reg, (uint8_t)val);
usr/src/uts/i86pc/os/cmi_hw.c
1998
pci_cfgacc_put8(NULL, PCI_GETBDF(bus, dev, func), reg,
usr/src/uts/i86pc/os/cmi_hw.c
2004
pci_config_put16(hdl, (off_t)reg, (uint16_t)val);
usr/src/uts/i86pc/os/cmi_hw.c
2006
pci_cfgacc_put16(NULL, PCI_GETBDF(bus, dev, func), reg,
usr/src/uts/i86pc/os/cmi_hw.c
2012
pci_config_put32(hdl, (off_t)reg, val);
usr/src/uts/i86pc/os/cmi_hw.c
2014
pci_cfgacc_put32(NULL, PCI_GETBDF(bus, dev, func), reg,
usr/src/uts/i86pc/os/cmi_hw.c
2024
cmi_pci_putb(int bus, int dev, int func, int reg, ddi_acc_handle_t hdl,
usr/src/uts/i86pc/os/cmi_hw.c
2027
cmi_pci_put_cmn(bus, dev, func, reg, 1, hdl, val);
usr/src/uts/i86pc/os/cmi_hw.c
2031
cmi_pci_putw(int bus, int dev, int func, int reg, ddi_acc_handle_t hdl,
usr/src/uts/i86pc/os/cmi_hw.c
2034
cmi_pci_put_cmn(bus, dev, func, reg, 2, hdl, val);
usr/src/uts/i86pc/os/cmi_hw.c
2038
cmi_pci_putl(int bus, int dev, int func, int reg, ddi_acc_handle_t hdl,
usr/src/uts/i86pc/os/cmi_hw.c
2041
cmi_pci_put_cmn(bus, dev, func, reg, 4, hdl, val);
usr/src/uts/i86pc/os/cmi_hw.c
477
pcii_addent(int bus, int dev, int func, int reg, uint32_t val, int asz)
usr/src/uts/i86pc/os/cmi_hw.c
479
int idx = CMI_PCII_HASHIDX(bus, dev, func, reg);
usr/src/uts/i86pc/os/cmi_hw.c
488
if (CMI_PCII_MATCH(hep, bus, dev, func, reg, asz))
usr/src/uts/i86pc/os/cmi_hw.c
499
hep->pcii_reg = reg;
usr/src/uts/i86pc/os/cmi_hw.c
520
pcii_lookup(int bus, int dev, int func, int reg, int asz, uint32_t *valp)
usr/src/uts/i86pc/os/cmi_hw.c
522
int idx = CMI_PCII_HASHIDX(bus, dev, func, reg);
usr/src/uts/i86pc/os/cmi_hw.c
530
if (CMI_PCII_MATCH(hep, bus, dev, func, reg, asz)) {
usr/src/uts/i86pc/os/cmi_hw.c
542
pcii_rment(int bus, int dev, int func, int reg, int asz)
usr/src/uts/i86pc/os/cmi_hw.c
544
int idx = CMI_PCII_HASHIDX(bus, dev, func, reg);
usr/src/uts/i86pc/os/cmi_hw.c
551
if (CMI_PCII_MATCH(hep, bus, dev, func, reg, asz)) {
usr/src/uts/i86pc/os/cpupm/cpu_acpi.c
748
AML_RESOURCE_GENERIC_REGISTER *reg;
usr/src/uts/i86pc/os/cpupm/cpu_acpi.c
752
reg = (AML_RESOURCE_GENERIC_REGISTER *)
usr/src/uts/i86pc/os/cpupm/cpu_acpi.c
754
cstate->cs_addrspace_id = reg->AddressSpaceId;
usr/src/uts/i86pc/os/cpupm/cpu_acpi.c
755
cstate->cs_address = reg->Address;
usr/src/uts/i86pc/os/cpupm/cpupm_throttle.c
123
uint64_t reg;
usr/src/uts/i86pc/os/cpupm/cpupm_throttle.c
130
reg = rdmsr(IA32_CLOCK_MODULATION_MSR);
usr/src/uts/i86pc/os/cpupm/cpupm_throttle.c
131
*stat = reg & 0x1E;
usr/src/uts/i86pc/os/cpupm/cpupm_throttle.c
80
uint64_t reg;
usr/src/uts/i86pc/os/cpupm/cpupm_throttle.c
95
reg = rdmsr(IA32_CLOCK_MODULATION_MSR);
usr/src/uts/i86pc/os/cpupm/cpupm_throttle.c
96
reg &= ~((uint64_t)0x1E);
usr/src/uts/i86pc/os/cpupm/cpupm_throttle.c
97
reg |= ctrl;
usr/src/uts/i86pc/os/cpupm/cpupm_throttle.c
98
wrmsr(IA32_CLOCK_MODULATION_MSR, reg);
usr/src/uts/i86pc/os/cpupm/pwrnow.c
92
uint64_t reg;
usr/src/uts/i86pc/os/cpupm/pwrnow.c
98
reg = ctrl;
usr/src/uts/i86pc/os/cpupm/pwrnow.c
99
wrmsr(PWRNOW_PERF_CTL_MSR, reg);
usr/src/uts/i86pc/os/cpupm/speedstep.c
107
reg = rdmsr(IA32_PERF_CTL_MSR);
usr/src/uts/i86pc/os/cpupm/speedstep.c
108
reg &= ~((uint64_t)0xFFFF);
usr/src/uts/i86pc/os/cpupm/speedstep.c
109
reg |= ctrl;
usr/src/uts/i86pc/os/cpupm/speedstep.c
110
wrmsr(IA32_PERF_CTL_MSR, reg);
usr/src/uts/i86pc/os/cpupm/speedstep.c
97
uint64_t reg;
usr/src/uts/i86pc/os/lgrpplat.c
3332
#define OPT_DRAMADDR_HI(reg) \
usr/src/uts/i86pc/os/lgrpplat.c
3333
(((u_longlong_t)reg & OPT_DRAMADDR_HI_MASK_ADDR) << \
usr/src/uts/i86pc/os/lgrpplat.c
3336
#define OPT_DRAMADDR_LO(reg) \
usr/src/uts/i86pc/os/lgrpplat.c
3337
(((u_longlong_t)reg & OPT_DRAMADDR_LO_MASK_ADDR) << \
usr/src/uts/i86pc/os/lgrpplat.c
3380
#define OPT_NODE_CNT(reg) \
usr/src/uts/i86pc/os/lgrpplat.c
3381
((reg & OPT_NODE_MASK_CNT) >> OPT_NODE_RSHIFT_CNT)
usr/src/uts/i86pc/os/lgrpplat.c
3394
#define OPT_PCI_ECS_ADDR(bus, device, function, reg) \
usr/src/uts/i86pc/os/lgrpplat.c
3396
(((function) & 0x7) << 8) | ((reg) & 0xfc) | \
usr/src/uts/i86pc/os/lgrpplat.c
3397
((((reg) >> 8) & 0xf) << 24))
usr/src/uts/i86pc/os/mach_kdi.c
111
panic("invalid debug register dr%d", reg);
usr/src/uts/i86pc/os/mach_kdi.c
67
kdi_dreg_get(int reg)
usr/src/uts/i86pc/os/mach_kdi.c
69
switch (reg) {
usr/src/uts/i86pc/os/mach_kdi.c
83
panic("invalid debug register dr%d", reg);
usr/src/uts/i86pc/os/mach_kdi.c
89
kdi_dreg_set(int reg, ulong_t value)
usr/src/uts/i86pc/os/mach_kdi.c
91
switch (reg) {
usr/src/uts/i86pc/os/pci_cfgspace.c
83
uint8_t (*pci_getb_func)(int bus, int dev, int func, int reg);
usr/src/uts/i86pc/os/pci_cfgspace.c
84
uint16_t (*pci_getw_func)(int bus, int dev, int func, int reg);
usr/src/uts/i86pc/os/pci_cfgspace.c
85
uint32_t (*pci_getl_func)(int bus, int dev, int func, int reg);
usr/src/uts/i86pc/os/pci_cfgspace.c
86
void (*pci_putb_func)(int bus, int dev, int func, int reg, uint8_t val);
usr/src/uts/i86pc/os/pci_cfgspace.c
87
void (*pci_putw_func)(int bus, int dev, int func, int reg, uint16_t val);
usr/src/uts/i86pc/os/pci_cfgspace.c
88
void (*pci_putl_func)(int bus, int dev, int func, int reg, uint32_t val);
usr/src/uts/i86pc/os/pci_mech1.c
100
if (reg > pci_iocfg_max_offset) {
usr/src/uts/i86pc/os/pci_mech1.c
105
outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg));
usr/src/uts/i86pc/os/pci_mech1.c
112
pci_mech1_putb(int bus, int device, int function, int reg, uint8_t val)
usr/src/uts/i86pc/os/pci_mech1.c
119
if (reg > pci_iocfg_max_offset) {
usr/src/uts/i86pc/os/pci_mech1.c
124
outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg));
usr/src/uts/i86pc/os/pci_mech1.c
125
outb(PCI_CONFDATA | (reg & 0x3), val);
usr/src/uts/i86pc/os/pci_mech1.c
130
pci_mech1_putw(int bus, int device, int function, int reg, uint16_t val)
usr/src/uts/i86pc/os/pci_mech1.c
137
if (reg > pci_iocfg_max_offset) {
usr/src/uts/i86pc/os/pci_mech1.c
142
outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg));
usr/src/uts/i86pc/os/pci_mech1.c
143
outw(PCI_CONFDATA | (reg & 0x2), val);
usr/src/uts/i86pc/os/pci_mech1.c
148
pci_mech1_putl(int bus, int device, int function, int reg, uint32_t val)
usr/src/uts/i86pc/os/pci_mech1.c
155
if (reg > pci_iocfg_max_offset) {
usr/src/uts/i86pc/os/pci_mech1.c
160
outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg));
usr/src/uts/i86pc/os/pci_mech1.c
50
pci_mech1_getb(int bus, int device, int function, int reg)
usr/src/uts/i86pc/os/pci_mech1.c
58
if (reg > pci_iocfg_max_offset) {
usr/src/uts/i86pc/os/pci_mech1.c
63
outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg));
usr/src/uts/i86pc/os/pci_mech1.c
64
val = inb(PCI_CONFDATA | (reg & 0x3));
usr/src/uts/i86pc/os/pci_mech1.c
70
pci_mech1_getw(int bus, int device, int function, int reg)
usr/src/uts/i86pc/os/pci_mech1.c
79
if (reg > pci_iocfg_max_offset) {
usr/src/uts/i86pc/os/pci_mech1.c
84
outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg));
usr/src/uts/i86pc/os/pci_mech1.c
85
val = inw(PCI_CONFDATA | (reg & 0x2));
usr/src/uts/i86pc/os/pci_mech1.c
91
pci_mech1_getl(int bus, int device, int function, int reg)
usr/src/uts/i86pc/os/pci_mech1_amd.c
104
if (reg > pci_iocfg_max_offset) {
usr/src/uts/i86pc/os/pci_mech1_amd.c
109
outl(PCI_CONFADD, PCI_CADDR1_ECS(bus, device, function, reg));
usr/src/uts/i86pc/os/pci_mech1_amd.c
110
val = inb(PCI_CONFDATA | (reg & 0x3));
usr/src/uts/i86pc/os/pci_mech1_amd.c
116
pci_mech1_amd_getw(int bus, int device, int function, int reg)
usr/src/uts/i86pc/os/pci_mech1_amd.c
125
if (reg > pci_iocfg_max_offset) {
usr/src/uts/i86pc/os/pci_mech1_amd.c
130
outl(PCI_CONFADD, PCI_CADDR1_ECS(bus, device, function, reg));
usr/src/uts/i86pc/os/pci_mech1_amd.c
131
val = inw(PCI_CONFDATA | (reg & 0x2));
usr/src/uts/i86pc/os/pci_mech1_amd.c
137
pci_mech1_amd_getl(int bus, int device, int function, int reg)
usr/src/uts/i86pc/os/pci_mech1_amd.c
146
if (reg > pci_iocfg_max_offset) {
usr/src/uts/i86pc/os/pci_mech1_amd.c
151
outl(PCI_CONFADD, PCI_CADDR1_ECS(bus, device, function, reg));
usr/src/uts/i86pc/os/pci_mech1_amd.c
158
pci_mech1_amd_putb(int bus, int device, int function, int reg, uint8_t val)
usr/src/uts/i86pc/os/pci_mech1_amd.c
166
outl(PCI_CONFADD, PCI_CADDR1_ECS(bus, device, function, reg));
usr/src/uts/i86pc/os/pci_mech1_amd.c
167
outb(PCI_CONFDATA | (reg & 0x3), val);
usr/src/uts/i86pc/os/pci_mech1_amd.c
172
pci_mech1_amd_putw(int bus, int device, int function, int reg, uint16_t val)
usr/src/uts/i86pc/os/pci_mech1_amd.c
180
outl(PCI_CONFADD, PCI_CADDR1_ECS(bus, device, function, reg));
usr/src/uts/i86pc/os/pci_mech1_amd.c
181
outw(PCI_CONFDATA | (reg & 0x2), val);
usr/src/uts/i86pc/os/pci_mech1_amd.c
186
pci_mech1_amd_putl(int bus, int device, int function, int reg, uint32_t val)
usr/src/uts/i86pc/os/pci_mech1_amd.c
194
outl(PCI_CONFADD, PCI_CADDR1_ECS(bus, device, function, reg));
usr/src/uts/i86pc/os/pci_mech1_amd.c
95
pci_mech1_amd_getb(int bus, int device, int function, int reg)
usr/src/uts/i86pc/os/pci_mech2.c
101
val = inw(PCI_CADDR2(device, reg));
usr/src/uts/i86pc/os/pci_mech2.c
108
pci_mech2_getl(int bus, int device, int function, int reg)
usr/src/uts/i86pc/os/pci_mech2.c
113
if (device >= PCI_MAX_DEVS_2 || reg > pci_iocfg_max_offset)
usr/src/uts/i86pc/os/pci_mech2.c
117
val = inl(PCI_CADDR2(device, reg));
usr/src/uts/i86pc/os/pci_mech2.c
124
pci_mech2_putb(int bus, int device, int function, int reg, uint8_t val)
usr/src/uts/i86pc/os/pci_mech2.c
128
if (device >= PCI_MAX_DEVS_2 || reg > pci_iocfg_max_offset)
usr/src/uts/i86pc/os/pci_mech2.c
132
outb(PCI_CADDR2(device, reg), val);
usr/src/uts/i86pc/os/pci_mech2.c
137
pci_mech2_putw(int bus, int device, int function, int reg, uint16_t val)
usr/src/uts/i86pc/os/pci_mech2.c
141
if (device >= PCI_MAX_DEVS_2 || reg > pci_iocfg_max_offset)
usr/src/uts/i86pc/os/pci_mech2.c
145
outw(PCI_CADDR2(device, reg), val);
usr/src/uts/i86pc/os/pci_mech2.c
150
pci_mech2_putl(int bus, int device, int function, int reg, uint32_t val)
usr/src/uts/i86pc/os/pci_mech2.c
154
if (device >= PCI_MAX_DEVS_2 || reg > pci_iocfg_max_offset)
usr/src/uts/i86pc/os/pci_mech2.c
158
outl(PCI_CADDR2(device, reg), val);
usr/src/uts/i86pc/os/pci_mech2.c
76
pci_mech2_getb(int bus, int device, int function, int reg)
usr/src/uts/i86pc/os/pci_mech2.c
81
if (device >= PCI_MAX_DEVS_2 || reg > pci_iocfg_max_offset)
usr/src/uts/i86pc/os/pci_mech2.c
85
val = inb(PCI_CADDR2(device, reg));
usr/src/uts/i86pc/os/pci_mech2.c
92
pci_mech2_getw(int bus, int device, int function, int reg)
usr/src/uts/i86pc/os/pci_mech2.c
97
if (device >= PCI_MAX_DEVS_2 || reg > pci_iocfg_max_offset)
usr/src/uts/i86pc/os/pci_neptune.c
138
pci_neptune_getb(int bus, int device, int function, int reg)
usr/src/uts/i86pc/os/pci_neptune.c
144
val = pci_mech1_getb(bus, device, function, reg);
usr/src/uts/i86pc/os/pci_neptune.c
151
pci_neptune_getw(int bus, int device, int function, int reg)
usr/src/uts/i86pc/os/pci_neptune.c
157
val = pci_mech1_getw(bus, device, function, reg);
usr/src/uts/i86pc/os/pci_neptune.c
164
pci_neptune_getl(int bus, int device, int function, int reg)
usr/src/uts/i86pc/os/pci_neptune.c
170
val = pci_mech1_getl(bus, device, function, reg);
usr/src/uts/i86pc/os/pci_neptune.c
177
pci_neptune_putb(int bus, int device, int function, int reg, uint8_t val)
usr/src/uts/i86pc/os/pci_neptune.c
181
pci_mech1_putb(bus, device, function, reg, val);
usr/src/uts/i86pc/os/pci_neptune.c
187
pci_neptune_putw(int bus, int device, int function, int reg, uint16_t val)
usr/src/uts/i86pc/os/pci_neptune.c
191
pci_mech1_putw(bus, device, function, reg, val);
usr/src/uts/i86pc/os/pci_neptune.c
197
pci_neptune_putl(int bus, int device, int function, int reg, uint32_t val)
usr/src/uts/i86pc/os/pci_neptune.c
201
pci_mech1_putl(bus, device, function, reg, val);
usr/src/uts/i86pc/os/pci_orion.c
179
pci_orion_getb(int bus, int device, int function, int reg)
usr/src/uts/i86pc/os/pci_orion.c
185
val = pci_mech1_getb(bus, device, function, reg);
usr/src/uts/i86pc/os/pci_orion.c
192
pci_orion_getw(int bus, int device, int function, int reg)
usr/src/uts/i86pc/os/pci_orion.c
198
val = pci_mech1_getw(bus, device, function, reg);
usr/src/uts/i86pc/os/pci_orion.c
205
pci_orion_getl(int bus, int device, int function, int reg)
usr/src/uts/i86pc/os/pci_orion.c
211
val = pci_mech1_getl(bus, device, function, reg);
usr/src/uts/i86pc/os/pci_orion.c
218
pci_orion_putb(int bus, int device, int function, int reg, uint8_t val)
usr/src/uts/i86pc/os/pci_orion.c
222
pci_mech1_putb(bus, device, function, reg, val);
usr/src/uts/i86pc/os/pci_orion.c
228
pci_orion_putw(int bus, int device, int function, int reg, uint16_t val)
usr/src/uts/i86pc/os/pci_orion.c
232
pci_mech1_putw(bus, device, function, reg, val);
usr/src/uts/i86pc/os/pci_orion.c
238
pci_orion_putl(int bus, int device, int function, int reg, uint32_t val)
usr/src/uts/i86pc/os/pci_orion.c
242
pci_mech1_putl(bus, device, function, reg, val);
usr/src/uts/i86pc/sys/apic.h
188
#define X2APIC_WRITE(reg, v) \
usr/src/uts/i86pc/sys/apic.h
189
wrmsr((REG_X2APIC_BASE_MSR + (reg >> 2)), v)
usr/src/uts/i86pc/sys/apic.h
191
#define LOCAL_APIC_WRITE_REG(reg, v) \
usr/src/uts/i86pc/sys/apic.h
192
apicadr[reg] = v
usr/src/uts/i86pc/sys/apic.h
621
extern uint32_t ioapic_read(int ioapic_ix, uint32_t reg);
usr/src/uts/i86pc/sys/apic.h
622
extern void ioapic_write(int ioapic_ix, uint32_t reg, uint32_t value);
usr/src/uts/i86pc/sys/asm_misc.h
43
#define LOADCPU(reg) \
usr/src/uts/i86pc/sys/asm_misc.h
44
movq %gs:CPU_SELF, reg;
usr/src/uts/i86pc/sys/asm_misc.h
46
#define LOADCPU(reg) \
usr/src/uts/i86pc/sys/asm_misc.h
47
movl %gs:CPU_SELF, reg;
usr/src/uts/i86pc/sys/immu.h
915
uint64_t immu_regs_get64(immu_t *immu, uint_t reg);
usr/src/uts/i86pc/sys/immu.h
916
void immu_regs_put64(immu_t *immu, uint_t reg, uint64_t val);
usr/src/uts/i86pc/sys/immu.h
917
uint32_t immu_regs_get32(immu_t *immu, uint_t reg);
usr/src/uts/i86pc/sys/immu.h
918
void immu_regs_put32(immu_t *immu, uint_t reg, uint32_t val);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
44
extern uint8_t pci_mech1_getb(int bus, int dev, int func, int reg);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
45
extern uint16_t pci_mech1_getw(int bus, int dev, int func, int reg);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
46
extern uint32_t pci_mech1_getl(int bus, int dev, int func, int reg);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
47
extern void pci_mech1_putb(int bus, int dev, int func, int reg, uint8_t val);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
48
extern void pci_mech1_putw(int bus, int dev, int func, int reg, uint16_t val);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
49
extern void pci_mech1_putl(int bus, int dev, int func, int reg, uint32_t val);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
55
extern uint8_t pci_mech1_amd_getb(int bus, int dev, int func, int reg);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
56
extern uint16_t pci_mech1_amd_getw(int bus, int dev, int func, int reg);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
57
extern uint32_t pci_mech1_amd_getl(int bus, int dev, int func, int reg);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
58
extern void pci_mech1_amd_putb(int bus, int dev, int func, int reg,
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
60
extern void pci_mech1_amd_putw(int bus, int dev, int func, int reg,
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
62
extern void pci_mech1_amd_putl(int bus, int dev, int func, int reg,
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
68
extern uint8_t pci_mech2_getb(int bus, int dev, int func, int reg);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
69
extern uint16_t pci_mech2_getw(int bus, int dev, int func, int reg);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
70
extern uint32_t pci_mech2_getl(int bus, int dev, int func, int reg);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
71
extern void pci_mech2_putb(int bus, int dev, int func, int reg, uint8_t val);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
72
extern void pci_mech2_putw(int bus, int dev, int func, int reg, uint16_t val);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
73
extern void pci_mech2_putl(int bus, int dev, int func, int reg, uint32_t val);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
81
extern uint8_t pci_neptune_getb(int bus, int dev, int func, int reg);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
82
extern uint16_t pci_neptune_getw(int bus, int dev, int func, int reg);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
83
extern uint32_t pci_neptune_getl(int bus, int dev, int func, int reg);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
84
extern void pci_neptune_putb(int bus, int dev, int func, int reg, uint8_t val);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
85
extern void pci_neptune_putw(int bus, int dev, int func, int reg, uint16_t val);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
86
extern void pci_neptune_putl(int bus, int dev, int func, int reg, uint32_t val);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
94
extern uint8_t pci_orion_getb(int bus, int dev, int func, int reg);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
95
extern uint16_t pci_orion_getw(int bus, int dev, int func, int reg);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
96
extern uint32_t pci_orion_getl(int bus, int dev, int func, int reg);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
97
extern void pci_orion_putb(int bus, int dev, int func, int reg, uint8_t val);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
98
extern void pci_orion_putw(int bus, int dev, int func, int reg, uint16_t val);
usr/src/uts/i86pc/sys/pci_cfgspace_impl.h
99
extern void pci_orion_putl(int bus, int dev, int func, int reg, uint32_t val);
usr/src/uts/i86xpv/io/psm/xpv_psm.c
1514
ioapic_read(int apic_ix, uint32_t reg)
usr/src/uts/i86xpv/io/psm/xpv_psm.c
1519
apic.reg = reg;
usr/src/uts/i86xpv/io/psm/xpv_psm.c
1521
panic("read ioapic %d reg %d failed", apic_ix, reg);
usr/src/uts/i86xpv/io/psm/xpv_psm.c
1526
ioapic_write(int apic_ix, uint32_t reg, uint32_t value)
usr/src/uts/i86xpv/io/psm/xpv_psm.c
1531
apic.reg = reg;
usr/src/uts/i86xpv/io/psm/xpv_psm.c
1534
panic("write ioapic %d reg %d failed", apic_ix, reg);
usr/src/uts/i86xpv/io/psm/xpv_psm.c
1546
apic.reg = APIC_IO_EOI;
usr/src/uts/i86xpv/os/mach_kdi.c
87
kdi_dreg_get(int reg)
usr/src/uts/i86xpv/os/mach_kdi.c
89
return (__hypercall1(__HYPERVISOR_get_debugreg, (long)reg));
usr/src/uts/i86xpv/os/mach_kdi.c
93
kdi_dreg_set(int reg, ulong_t value)
usr/src/uts/i86xpv/os/mach_kdi.c
95
(void) __hypercall2(__HYPERVISOR_set_debugreg, (long)reg, value);
usr/src/uts/i86xpv/os/xen_machdep.c
1038
xen_set_segment_base(int reg, ulong_t value)
usr/src/uts/i86xpv/os/xen_machdep.c
1042
if ((err = HYPERVISOR_set_segment_base(reg, value)) != 0) {
usr/src/uts/i86xpv/os/xen_machdep.c
1048
reg, value, -(int)err);
usr/src/uts/intel/asm/atomic.h
111
#define __ATOMIC_OPXX(fxn, type1, type2, op, reg) \
usr/src/uts/intel/asm/atomic.h
118
: "i" reg (delta) \
usr/src/uts/intel/asm/atomic.h
168
#define __ATOMIC_OPXX(fxn, type, op, reg) \
usr/src/uts/intel/asm/atomic.h
176
: reg (new), "1" (cmp) \
usr/src/uts/intel/asm/atomic.h
212
#define __ATOMIC_OPXX(fxn, type, op, reg) \
usr/src/uts/intel/asm/atomic.h
218
: "+m" (*target), "+" reg (val)); \
usr/src/uts/intel/brand/common/brand_asm.h
153
#define GET_V(sp, pcnt, var, reg) \
usr/src/uts/intel/brand/common/brand_asm.h
154
mov V_OFFSET(pcnt, var)(sp), reg
usr/src/uts/intel/brand/common/brand_asm.h
156
#define SET_V(sp, pcnt, var, reg) \
usr/src/uts/intel/brand/common/brand_asm.h
157
mov reg, V_OFFSET(pcnt, var)(sp)
usr/src/uts/intel/brand/common/brand_asm.h
159
#define GET_PROCP(sp, pcnt, reg) \
usr/src/uts/intel/brand/common/brand_asm.h
160
GET_V(sp, pcnt, V_LWP, reg); /* get lwp pointer */ \
usr/src/uts/intel/brand/common/brand_asm.h
161
mov LWP_PROCP(reg), reg /* get proc pointer */
usr/src/uts/intel/brand/common/brand_asm.h
163
#define GET_P_BRAND_DATA(sp, pcnt, reg) \
usr/src/uts/intel/brand/common/brand_asm.h
164
GET_PROCP(sp, pcnt, reg); \
usr/src/uts/intel/brand/common/brand_asm.h
165
mov P_BRAND_DATA(reg), reg /* get p_brand_data */
usr/src/uts/intel/brand/common/brand_asm.h
194
#define CHECK_FOR_NATIVE(reg) \
usr/src/uts/intel/brand/common/brand_asm.h
195
cmp $1024, reg; \
usr/src/uts/intel/brand/common/brand_asm.h
197
sub $1024, reg; \
usr/src/uts/intel/dtrace/dtrace_isa.c
558
dtrace_getreg(struct regs *rp, uint_t reg)
usr/src/uts/intel/dtrace/dtrace_isa.c
560
if (reg <= SS) {
usr/src/uts/intel/dtrace/dtrace_isa.c
561
if (reg >= sizeof (dtrace_regmap) / sizeof (int)) {
usr/src/uts/intel/dtrace/dtrace_isa.c
566
reg = dtrace_regmap[reg];
usr/src/uts/intel/dtrace/dtrace_isa.c
568
reg -= SS + 1;
usr/src/uts/intel/dtrace/dtrace_isa.c
571
switch (reg) {
usr/src/uts/intel/dtrace/dtrace_isa.c
632
dtrace_setreg(struct regs *rp, uint_t reg, ulong_t val)
usr/src/uts/intel/dtrace/dtrace_isa.c
634
if (reg <= SS) {
usr/src/uts/intel/dtrace/dtrace_isa.c
635
ASSERT(reg < (sizeof (dtrace_regmap) / sizeof (int)));
usr/src/uts/intel/dtrace/dtrace_isa.c
637
reg = dtrace_regmap[reg];
usr/src/uts/intel/dtrace/dtrace_isa.c
639
reg -= SS + 1;
usr/src/uts/intel/dtrace/dtrace_isa.c
642
switch (reg) {
usr/src/uts/intel/dtrace/fasttrap_isa.c
1434
greg_t *reg;
usr/src/uts/intel/dtrace/fasttrap_isa.c
1461
reg = &rp->r_rax;
usr/src/uts/intel/dtrace/fasttrap_isa.c
1465
reg = &rp->r_rcx;
usr/src/uts/intel/dtrace/fasttrap_isa.c
1469
reg = &rp->r_r8;
usr/src/uts/intel/dtrace/fasttrap_isa.c
1473
reg = &rp->r_r9;
usr/src/uts/intel/dtrace/fasttrap_isa.c
1479
*(uint64_t *)&scratch[i] = *reg;
usr/src/uts/intel/dtrace/fasttrap_isa.c
1480
curthread->t_dtrace_regv = *reg;
usr/src/uts/intel/dtrace/fasttrap_isa.c
1481
*reg = pc + tp->ftt_size;
usr/src/uts/intel/dtrace/fasttrap_isa.c
1634
fasttrap_getreg(struct regs *rp, uint_t reg)
usr/src/uts/intel/dtrace/fasttrap_isa.c
1636
switch (reg) {
usr/src/uts/intel/dtrace/fasttrap_isa.c
353
uint_t reg = FASTTRAP_MODRM_REG(instr[start + 1]);
usr/src/uts/intel/dtrace/fasttrap_isa.c
356
if (reg == 2 || reg == 4) {
usr/src/uts/intel/dtrace/fasttrap_isa.c
359
if (reg == 2)
usr/src/uts/intel/dtrace/fasttrap_isa.c
547
uint_t reg = FASTTRAP_MODRM_REG(instr[rmindex]);
usr/src/uts/intel/dtrace/fasttrap_isa.c
562
if (reg != 0) {
usr/src/uts/intel/dtrace/fasttrap_isa.c
576
FASTTRAP_MODRM(2, reg, rm);
usr/src/uts/intel/dtrace/fasttrap_isa.c
71
#define FASTTRAP_MODRM(mod, reg, rm) (((mod) << 6) | ((reg) << 3) | (rm))
usr/src/uts/intel/io/amdzen/amdzen.c
1412
smn_reg_t reg;
usr/src/uts/intel/io/amdzen/amdzen.c
1415
reg = L3SOC_THREAD_EN(ccdno);
usr/src/uts/intel/io/amdzen/amdzen.c
1417
reg = SMUPWR_THREAD_EN(ccdno);
usr/src/uts/intel/io/amdzen/amdzen.c
1420
return (amdzen_smn_read(azn, df, reg));
usr/src/uts/intel/io/amdzen/amdzen.c
1426
smn_reg_t reg;
usr/src/uts/intel/io/amdzen/amdzen.c
1429
reg = L3SOC_CORE_EN(ccdno);
usr/src/uts/intel/io/amdzen/amdzen.c
1431
reg = SMUPWR_CORE_EN(ccdno);
usr/src/uts/intel/io/amdzen/amdzen.c
1434
return (amdzen_smn_read(azn, df, reg));
usr/src/uts/intel/io/amdzen/amdzen.c
1444
smn_reg_t reg = L3SOC_THREAD_CFG(ccdno);
usr/src/uts/intel/io/amdzen/amdzen.c
1445
uint32_t val = amdzen_smn_read(azn, df, reg);
usr/src/uts/intel/io/amdzen/amdzen.c
1450
smn_reg_t reg = SMUPWR_THREAD_CFG(ccdno);
usr/src/uts/intel/io/amdzen/amdzen.c
1451
uint32_t val = amdzen_smn_read(azn, df, reg);
usr/src/uts/intel/io/amdzen/amdzen.c
2227
int *regs, reg;
usr/src/uts/intel/io/amdzen/amdzen.c
2277
reg = *regs;
usr/src/uts/intel/io/amdzen/amdzen.c
2287
if (!valid && PCI_REG_BUS_G(reg) == AMDZEN_DF_BUSNO &&
usr/src/uts/intel/io/amdzen/amdzen.c
2288
PCI_REG_DEV_G(reg) >= AMDZEN_DF_FIRST_DEVICE) {
usr/src/uts/intel/io/amdzen/amdzen.c
2309
stub->azns_bus = PCI_REG_BUS_G(reg);
usr/src/uts/intel/io/amdzen/amdzen.c
2310
stub->azns_dev = PCI_REG_DEV_G(reg);
usr/src/uts/intel/io/amdzen/amdzen.c
2311
stub->azns_func = PCI_REG_FUNC_G(reg);
usr/src/uts/intel/io/amdzen/amdzen.c
241
amdzen_stub_get8(amdzen_stub_t *stub, off_t reg)
usr/src/uts/intel/io/amdzen/amdzen.c
243
return (pci_config_get8(stub->azns_cfgspace, reg));
usr/src/uts/intel/io/amdzen/amdzen.c
247
amdzen_stub_get16(amdzen_stub_t *stub, off_t reg)
usr/src/uts/intel/io/amdzen/amdzen.c
249
return (pci_config_get16(stub->azns_cfgspace, reg));
usr/src/uts/intel/io/amdzen/amdzen.c
253
amdzen_stub_get32(amdzen_stub_t *stub, off_t reg)
usr/src/uts/intel/io/amdzen/amdzen.c
255
return (pci_config_get32(stub->azns_cfgspace, reg));
usr/src/uts/intel/io/amdzen/amdzen.c
259
amdzen_stub_get64(amdzen_stub_t *stub, off_t reg)
usr/src/uts/intel/io/amdzen/amdzen.c
261
return (pci_config_get64(stub->azns_cfgspace, reg));
usr/src/uts/intel/io/amdzen/amdzen.c
265
amdzen_stub_put8(amdzen_stub_t *stub, off_t reg, uint8_t val)
usr/src/uts/intel/io/amdzen/amdzen.c
267
pci_config_put8(stub->azns_cfgspace, reg, val);
usr/src/uts/intel/io/amdzen/amdzen.c
271
amdzen_stub_put16(amdzen_stub_t *stub, off_t reg, uint16_t val)
usr/src/uts/intel/io/amdzen/amdzen.c
273
pci_config_put16(stub->azns_cfgspace, reg, val);
usr/src/uts/intel/io/amdzen/amdzen.c
277
amdzen_stub_put32(amdzen_stub_t *stub, off_t reg, uint32_t val)
usr/src/uts/intel/io/amdzen/amdzen.c
279
pci_config_put32(stub->azns_cfgspace, reg, val);
usr/src/uts/intel/io/amdzen/amdzen.c
358
amdzen_smn_read(amdzen_t *azn, amdzen_df_t *df, const smn_reg_t reg)
usr/src/uts/intel/io/amdzen/amdzen.c
360
const uint32_t base_addr = SMN_REG_ADDR_BASE(reg);
usr/src/uts/intel/io/amdzen/amdzen.c
361
const uint32_t addr_off = SMN_REG_ADDR_OFF(reg);
usr/src/uts/intel/io/amdzen/amdzen.c
363
VERIFY(SMN_REG_IS_NATURALLY_ALIGNED(reg));
usr/src/uts/intel/io/amdzen/amdzen.c
367
switch (SMN_REG_SIZE(reg)) {
usr/src/uts/intel/io/amdzen/amdzen.c
378
SMN_REG_SIZE(reg));
usr/src/uts/intel/io/amdzen/amdzen.c
383
amdzen_smn_write(amdzen_t *azn, amdzen_df_t *df, const smn_reg_t reg,
usr/src/uts/intel/io/amdzen/amdzen.c
386
const uint32_t base_addr = SMN_REG_ADDR_BASE(reg);
usr/src/uts/intel/io/amdzen/amdzen.c
387
const uint32_t addr_off = SMN_REG_ADDR_OFF(reg);
usr/src/uts/intel/io/amdzen/amdzen.c
389
VERIFY(SMN_REG_IS_NATURALLY_ALIGNED(reg));
usr/src/uts/intel/io/amdzen/amdzen.c
390
VERIFY(SMN_REG_VALUE_FITS(reg, val));
usr/src/uts/intel/io/amdzen/amdzen.c
394
switch (SMN_REG_SIZE(reg)) {
usr/src/uts/intel/io/amdzen/amdzen.c
408
SMN_REG_SIZE(reg));
usr/src/uts/intel/io/amdzen/amdzen.c
469
amdzen_c_smn_read(uint_t dfno, const smn_reg_t reg, uint32_t *valp)
usr/src/uts/intel/io/amdzen/amdzen.c
474
if (!SMN_REG_SIZE_IS_VALID(reg))
usr/src/uts/intel/io/amdzen/amdzen.c
476
if (!SMN_REG_IS_NATURALLY_ALIGNED(reg))
usr/src/uts/intel/io/amdzen/amdzen.c
491
*valp = amdzen_smn_read(azn, df, reg);
usr/src/uts/intel/io/amdzen/amdzen.c
497
amdzen_c_smn_write(uint_t dfno, const smn_reg_t reg, const uint32_t val)
usr/src/uts/intel/io/amdzen/amdzen.c
502
if (!SMN_REG_SIZE_IS_VALID(reg))
usr/src/uts/intel/io/amdzen/amdzen.c
504
if (!SMN_REG_IS_NATURALLY_ALIGNED(reg))
usr/src/uts/intel/io/amdzen/amdzen.c
506
if (!SMN_REG_VALUE_FITS(reg, val))
usr/src/uts/intel/io/amdzen/amdzen.c
521
amdzen_smn_write(azn, df, reg, val);
usr/src/uts/intel/io/amdzen/smntemp.c
208
uint32_t reg;
usr/src/uts/intel/io/amdzen/smntemp.c
214
®)) != 0) {
usr/src/uts/intel/io/amdzen/smntemp.c
219
stt->stt_raw = reg;
usr/src/uts/intel/io/amdzen/smntemp.c
221
raw = THM_CURTEMP_GET_TEMP(reg);
usr/src/uts/intel/io/amdzen/smntemp.c
223
raw = THM_DIE_GET_TEMP(reg);
usr/src/uts/intel/io/amdzen/usmn.c
102
const smn_reg_t reg = SMN_MAKE_REG_SIZED(usr.usr_addr, usr.usr_size);
usr/src/uts/intel/io/amdzen/usmn.c
111
ret = amdzen_c_smn_read(dfno, reg, &usr.usr_data);
usr/src/uts/intel/io/amdzen/usmn.c
122
ret = amdzen_c_smn_write(dfno, reg, usr.usr_data);
usr/src/uts/intel/io/amdzen/zen_umc.c
2264
uint_t reg = ent / ZEN_UMC_REMAP_PER_REG_4D2;
usr/src/uts/intel/io/amdzen/zen_umc.c
2267
DF_CS_REMAP_GET_CSX_V4B(rm[reg], idx);
usr/src/uts/intel/io/amdzen/zen_umc.c
2336
uint_t reg = ent / ZEN_UMC_REMAP_PER_REG;
usr/src/uts/intel/io/amdzen/zen_umc.c
2338
remap->csr_remaps[ent] = DF_CS_REMAP_GET_CSX(rm[reg],
usr/src/uts/intel/io/amdzen/zen_umc.c
2529
smn_reg_t reg;
usr/src/uts/intel/io/amdzen/zen_umc.c
2537
reg = UMC_DIMMCFG_DDR4(id, dimmno);
usr/src/uts/intel/io/amdzen/zen_umc.c
2539
reg = UMC_DIMMCFG_DDR5(id, dimmno);
usr/src/uts/intel/io/amdzen/zen_umc.c
2541
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
2543
"configuration register %x: %d", SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
2609
smn_reg_t reg;
usr/src/uts/intel/io/amdzen/zen_umc.c
2625
reg = UMC_BASE(id, reginst);
usr/src/uts/intel/io/amdzen/zen_umc.c
2626
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
2628
"register %x: %d", SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
2636
reg = UMC_BASE_SEC(id, reginst);
usr/src/uts/intel/io/amdzen/zen_umc.c
2637
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
2639
"secondary base register %x: %d", SMN_REG_ADDR(reg),
usr/src/uts/intel/io/amdzen/zen_umc.c
2654
reg = UMC_MASK_DDR4(id, dimmno);
usr/src/uts/intel/io/amdzen/zen_umc.c
2655
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
2657
"%x: %d", SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
2670
reg = UMC_MASK_SEC_DDR4(id, dimmno);
usr/src/uts/intel/io/amdzen/zen_umc.c
2671
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
2673
"register %x: %d", SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
2681
reg = UMC_ADDRCFG_DDR4(id, dimmno);
usr/src/uts/intel/io/amdzen/zen_umc.c
2682
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
2684
"register %x: %d", SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
2717
reg = UMC_ADDRSEL_DDR4(id, dimmno);
usr/src/uts/intel/io/amdzen/zen_umc.c
2718
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
2720
"select register %x: %d", SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
2742
reg = UMC_COLSEL_LO_DDR4(id, dimmno);
usr/src/uts/intel/io/amdzen/zen_umc.c
2743
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
2745
"select low register %x: %d", SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
2753
reg = UMC_COLSEL_HI_DDR4(id, dimmno);
usr/src/uts/intel/io/amdzen/zen_umc.c
2754
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
2756
"select high register %x: %d", SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
2772
reg = UMC_RMSEL_DDR4(id, dimmno);
usr/src/uts/intel/io/amdzen/zen_umc.c
2773
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
2775
"select register %x: %d", SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
2788
reg = UMC_RMSEL_SEC_DDR4(id, dimmno);
usr/src/uts/intel/io/amdzen/zen_umc.c
2789
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
2791
"address select register %x: %d", SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
2820
smn_reg_t reg;
usr/src/uts/intel/io/amdzen/zen_umc.c
2828
reg = UMC_BASE(id, regno);
usr/src/uts/intel/io/amdzen/zen_umc.c
2829
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
2831
"register %x: %d", SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
2840
reg = UMC_BASE_EXT_DDR5(id, regno);
usr/src/uts/intel/io/amdzen/zen_umc.c
2841
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) !=
usr/src/uts/intel/io/amdzen/zen_umc.c
2844
"extended base register %x: %d", SMN_REG_ADDR(reg),
usr/src/uts/intel/io/amdzen/zen_umc.c
2854
reg = UMC_BASE_SEC(id, regno);
usr/src/uts/intel/io/amdzen/zen_umc.c
2855
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
2857
"register %x: %d", SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
2866
reg = UMC_BASE_EXT_SEC_DDR5(id, regno);
usr/src/uts/intel/io/amdzen/zen_umc.c
2867
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) !=
usr/src/uts/intel/io/amdzen/zen_umc.c
2871
SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
2884
reg = UMC_MASK_DDR5(id, regno);
usr/src/uts/intel/io/amdzen/zen_umc.c
2885
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
2887
"register %x: %d", SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
2896
reg = UMC_MASK_EXT_DDR5(id, regno);
usr/src/uts/intel/io/amdzen/zen_umc.c
2897
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) !=
usr/src/uts/intel/io/amdzen/zen_umc.c
2900
"extended mask register %x: %d", SMN_REG_ADDR(reg),
usr/src/uts/intel/io/amdzen/zen_umc.c
2911
reg = UMC_MASK_SEC_DDR5(id, regno);
usr/src/uts/intel/io/amdzen/zen_umc.c
2912
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
2914
"register %x: %d", SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
2923
reg = UMC_MASK_EXT_SEC_DDR5(id, regno);
usr/src/uts/intel/io/amdzen/zen_umc.c
2924
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) !=
usr/src/uts/intel/io/amdzen/zen_umc.c
2927
"extended mask register %x: %d", SMN_REG_ADDR(reg),
usr/src/uts/intel/io/amdzen/zen_umc.c
2937
reg = UMC_ADDRCFG_DDR5(id, regno);
usr/src/uts/intel/io/amdzen/zen_umc.c
2938
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
2940
"register %x: %d", SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
2958
reg = UMC_ADDRSEL_DDR5(id, regno);
usr/src/uts/intel/io/amdzen/zen_umc.c
2959
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
2961
"register %x: %d", SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
2978
reg = UMC_COLSEL_LO_DDR5(id, regno);
usr/src/uts/intel/io/amdzen/zen_umc.c
2979
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
2981
"select low register %x: %d", SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
2989
reg = UMC_COLSEL_HI_DDR5(id, regno);
usr/src/uts/intel/io/amdzen/zen_umc.c
2990
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
2992
"select high register %x: %d", SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
3006
reg = UMC_RMSEL_DDR5(id, regno);
usr/src/uts/intel/io/amdzen/zen_umc.c
3007
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
3009
"select register %x: %d", SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
3114
const uint32_t reg = chan->chan_dramcfg_raw[mstate];
usr/src/uts/intel/io/amdzen/zen_umc.c
3115
const uint32_t wck = UMC_DRAMCFG_HYB_GET_WCLKRATIO(reg);
usr/src/uts/intel/io/amdzen/zen_umc.c
3116
const uint32_t clock = UMC_DRAMCFG_HYB_GET_MEMCLK(reg);
usr/src/uts/intel/io/amdzen/zen_umc.c
3211
smn_reg_t reg;
usr/src/uts/intel/io/amdzen/zen_umc.c
3224
reg = UMC_BANK_HASH_DDR4(id, i);
usr/src/uts/intel/io/amdzen/zen_umc.c
3226
reg = UMC_BANK_HASH_DDR5(id, i);
usr/src/uts/intel/io/amdzen/zen_umc.c
3229
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg,
usr/src/uts/intel/io/amdzen/zen_umc.c
3233
SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
3249
reg = UMC_RANK_HASH_DDR4(id, i);
usr/src/uts/intel/io/amdzen/zen_umc.c
3251
reg = UMC_RANK_HASH_DDR5(id, i);
usr/src/uts/intel/io/amdzen/zen_umc.c
3254
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg,
usr/src/uts/intel/io/amdzen/zen_umc.c
3258
SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
3271
reg = UMC_RANK_HASH_EXT_DDR5(id, i);
usr/src/uts/intel/io/amdzen/zen_umc.c
3272
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg,
usr/src/uts/intel/io/amdzen/zen_umc.c
3276
SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
3290
reg = UMC_PC_HASH_DDR4(id);
usr/src/uts/intel/io/amdzen/zen_umc.c
3292
reg = UMC_PC_HASH_DDR5(id);
usr/src/uts/intel/io/amdzen/zen_umc.c
3295
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
3297
"register %x: %d", SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
3306
reg = UMC_PC_HASH2_DDR4(id);
usr/src/uts/intel/io/amdzen/zen_umc.c
3308
reg = UMC_PC_HASH2_DDR5(id);
usr/src/uts/intel/io/amdzen/zen_umc.c
3311
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
3313
"2 register %x: %d", SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
3326
reg = UMC_CS_HASH_DDR4(id, i);
usr/src/uts/intel/io/amdzen/zen_umc.c
3328
reg = UMC_CS_HASH_DDR5(id, i);
usr/src/uts/intel/io/amdzen/zen_umc.c
3331
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg,
usr/src/uts/intel/io/amdzen/zen_umc.c
3334
"cs hash register %x", SMN_REG_ADDR(reg));
usr/src/uts/intel/io/amdzen/zen_umc.c
3347
reg = UMC_CS_HASH_EXT_DDR5(id, i);
usr/src/uts/intel/io/amdzen/zen_umc.c
3348
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg,
usr/src/uts/intel/io/amdzen/zen_umc.c
3352
SMN_REG_ADDR(reg));
usr/src/uts/intel/io/amdzen/zen_umc.c
3372
smn_reg_t reg;
usr/src/uts/intel/io/amdzen/zen_umc.c
3393
reg = UMC_UMCCFG(id);
usr/src/uts/intel/io/amdzen/zen_umc.c
3394
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
3396
"configuration register %x: %d", SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
3410
reg = UMC_DRAMCFG(id, 0);
usr/src/uts/intel/io/amdzen/zen_umc.c
3424
reg = UMC_DRAMCFG(id, i);
usr/src/uts/intel/io/amdzen/zen_umc.c
3425
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
3428
SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
3440
reg = UMC_DATACTL(id);
usr/src/uts/intel/io/amdzen/zen_umc.c
3441
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
3443
"register %x: %d", SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
3461
reg = UMC_ECCCTL(id);
usr/src/uts/intel/io/amdzen/zen_umc.c
3462
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
3464
"register %x: %d", SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
3473
reg = UMC_UMCCAP(id);
usr/src/uts/intel/io/amdzen/zen_umc.c
3474
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
3476
"register %x: %d", SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amdzen/zen_umc.c
3481
reg = UMC_UMCCAP_HI(id);
usr/src/uts/intel/io/amdzen/zen_umc.c
3482
if ((ret = amdzen_c_smn_read(df->zud_dfno, reg, &val)) != 0) {
usr/src/uts/intel/io/amdzen/zen_umc.c
3484
"register %x: %d", SMN_REG_ADDR(reg), ret);
usr/src/uts/intel/io/amr/amrreg.h
701
#define AMR_SBYTE_SET(sc, reg, val) pci_config_put8(sc->regsmap_handle, \
usr/src/uts/intel/io/amr/amrreg.h
702
reg, val)
usr/src/uts/intel/io/dnet/dnet.h
128
#define REG32(reg, off) ((uint32_t *)((uintptr_t)(reg) + off))
usr/src/uts/intel/io/dnet/dnet.h
129
#define REG16(reg, off) ((uint16_t *)((uintptr_t)(reg) + off))
usr/src/uts/intel/io/dnet/dnet.h
130
#define REG8(reg, off) ((uint8_t *)((uintptr_t)(reg) + off))
usr/src/uts/intel/io/dnet/dnet_mii.c
357
int reg;
usr/src/uts/intel/io/dnet/dnet_mii.c
377
regprop[i].reg, regprop[i].value);
usr/src/uts/intel/io/dnet/dnet_mii.c
381
regprop[i].reg, regprop[i].value);
usr/src/uts/intel/io/dnet/dnet_mii.c
780
ushort_t reg;
usr/src/uts/intel/io/dnet/dnet_mii.c
800
reg = mac->mii_read(dip, phy, 0x1b);
usr/src/uts/intel/io/dnet/dnet_mii.c
802
BIT(9, reg) ? "serial":"nibble");
usr/src/uts/intel/io/dnet/dnet_mii.c
805
BIT(reg, 5) ? "" : "no ",
usr/src/uts/intel/io/dnet/dnet_mii.c
806
BIT(reg, 4) ? "" : "no ",
usr/src/uts/intel/io/dnet/dnet_mii.c
807
BIT(reg, 3) ? "UTP" : "STP",
usr/src/uts/intel/io/dnet/dnet_mii.c
808
BIT(reg, 2) ? "low" : "normal",
usr/src/uts/intel/io/dnet/dnet_mii.c
809
BIT(reg, 0) ? "enabled" : "disabled");
usr/src/uts/intel/io/dnet/dnet_mii.c
891
ushort_t reg;
usr/src/uts/intel/io/dnet/dnet_mii.c
902
reg = mac->mii_read(mac->mii_dip, phy, 23) | (1<<10) | (1<<5);
usr/src/uts/intel/io/dnet/dnet_mii.c
903
mac->mii_write(mac->mii_dip, phy, 23, reg);
usr/src/uts/intel/io/dnet/dnet_mii.h
59
typedef ushort_t (*mii_readfunc_t)(dev_info_t *, int phy, int reg);
usr/src/uts/intel/io/dnet/dnet_mii.h
60
typedef void (*mii_writefunc_t)(dev_info_t *, int phy, int reg, int value);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1759
pci_regspec_t *reg;
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1908
(caddr_t)®, &length) != DDI_PROP_SUCCESS) {
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1918
if ((reg[i].pci_size_low != 0) || (reg[i].pci_size_hi != 0)) {
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1920
offset = PCI_REG_REG_G(reg[i].pci_phys_hi);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1922
switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) {
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1925
if (reg[i].pci_phys_hi & PCI_REG_PF_M) {
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1928
reg[i].pci_size_low, &mem_answer);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1931
reg[i].pci_size_low, &mem_answer);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1940
reg[i].pci_phys_hi |= PCI_REG_REL_M;
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1941
reg[i].pci_phys_low = PCICFG_LOADDR(mem_answer);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1942
reg[i].pci_phys_mid = PCICFG_HIADDR(mem_answer);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1946
if (reg[i].pci_phys_hi & PCI_REG_PF_M) {
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1949
reg[i].pci_size_low, &mem_answer);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1953
reg[i].pci_size_low, &mem_answer);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1962
reg[i].pci_phys_hi |= PCI_REG_REL_M;
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1963
reg[i].pci_phys_low = (uint32_t)mem_answer;
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1969
(void) pcicfg_get_io(entry, reg[i].pci_size_low,
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1976
reg[i].pci_phys_hi |= PCI_REG_REL_M;
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1977
reg[i].pci_phys_low = io_answer;
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1982
kmem_free(reg, length);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1992
if (pcicfg_update_assigned_prop(dip, ®[i])
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1994
kmem_free(reg, length);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2006
kmem_free((caddr_t)reg, length);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2014
pci_regspec_t *reg;
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2034
(caddr_t)®, &length) != DDI_PROP_SUCCESS) {
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2041
kmem_free(reg, length);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2077
if ((reg[i].pci_size_low != 0)|| (reg[i].pci_size_hi != 0)) {
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2079
offset = PCI_REG_REG_G(reg[i].pci_phys_hi);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2080
request.ra_len = reg[i].pci_size_low;
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2082
switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) {
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2084
if (reg[i].pci_phys_hi & PCI_REG_PF_M) {
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2094
kmem_free(reg, length);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2108
reg[i].pci_phys_hi |= PCI_REG_REL_M;
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2109
reg[i].pci_phys_low = PCICFG_LOADDR(answer);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2110
reg[i].pci_phys_mid = PCICFG_HIADDR(answer);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2115
reg[i].pci_phys_hi ^=
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2122
if (reg[i].pci_phys_hi & PCI_REG_PF_M)
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2131
kmem_free(reg, length);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2143
reg[i].pci_phys_hi |= PCI_REG_REL_M;
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2144
reg[i].pci_phys_low = PCICFG_LOADDR(answer);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2145
reg[i].pci_phys_mid = 0;
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2170
reg[i].pci_phys_hi |= PCI_REG_REL_M;
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2171
reg[i].pci_phys_low = PCICFG_LOADDR(answer);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2177
kmem_free(reg, length);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2187
if (pcicfg_update_assigned_prop(dip, ®[i])
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2189
kmem_free(reg, length);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2197
kmem_free(reg, length);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
3046
pci_regspec_t *reg;
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
3054
dip, DDI_PROP_DONTPASS, "reg", (caddr_t)®, &rlen);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
3077
hiword = PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi),
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
3078
PCI_REG_DEV_G(reg->pci_phys_hi),
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
3079
PCI_REG_FUNC_G(reg->pci_phys_hi), reg_offset);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
3107
bcopy(reg, newreg, rlen);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
3118
kmem_free((caddr_t)reg, rlen);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
3128
pci_regspec_t *reg;
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
3134
dip, DDI_PROP_DONTPASS, "reg", (caddr_t)®, &rlen);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
3156
hiword = PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi),
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
3157
PCI_REG_DEV_G(reg->pci_phys_hi),
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
3158
PCI_REG_FUNC_G(reg->pci_phys_hi), reg_offset);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
3194
kmem_free((caddr_t)reg, rlen);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
4742
pci_regspec_t *reg;
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
4750
(caddr_t)®, &rlen);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
4773
kmem_free((caddr_t)reg, rlen);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
4797
kmem_free((caddr_t)reg, rlen);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
4813
int reg[10] = { PCI_ADDR_CONFIG, 0, 0, 0, 0};
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
4815
reg[0] = PCICFG_MAKE_REG_HIGH(bus, device, func, 0);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
4817
return (ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", reg, 5));
usr/src/uts/intel/io/intel_nb5000/nb5000.h
1185
#define MIR_RD(reg) nb_pci_getw(0, 16, 1, 0x80 + ((reg)*4), 0)
usr/src/uts/intel/io/intel_nb5000/nb5000.h
1187
#define DMIR_RD(branch, reg) \
usr/src/uts/intel/io/intel_nb5000/nb5000.h
1189
nb_pci_getl(0, ((branch) == 0) ? 21 : 22, 0, 0x15c + ((reg)*4), 0) : \
usr/src/uts/intel/io/intel_nb5000/nb5000.h
1190
((branch) == 0) ? nb_pci_getl(0, 21, 0, 0x90 + ((reg)*4), 0) : \
usr/src/uts/intel/io/intel_nb5000/nb5000.h
1192
nb_pci_getl(0, 22, 0, 0x90 + ((reg)*4), 0) : 0
usr/src/uts/intel/io/intel_nb5000/nb5000.h
670
#define FERR_FBD_CHANNEL(reg) ((reg)>>28 & 3)
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
105
reg.pci_phys_hi += 1 << PCI_REG_DEV_SHIFT;
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
149
nb_pci_getb(int bus, int dev, int func, int reg, int *interpose)
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
154
return (cmi_pci_getb(bus, dev, func, reg, interpose, hdl));
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
158
nb_pci_getw(int bus, int dev, int func, int reg, int *interpose)
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
163
return (cmi_pci_getw(bus, dev, func, reg, interpose, hdl));
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
167
nb_pci_getl(int bus, int dev, int func, int reg, int *interpose)
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
172
return (cmi_pci_getl(bus, dev, func, reg, interpose, hdl));
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
176
nb_pci_putb(int bus, int dev, int func, int reg, uint8_t val)
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
181
cmi_pci_putb(bus, dev, func, reg, hdl, val);
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
185
nb_pci_putw(int bus, int dev, int func, int reg, uint16_t val)
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
190
cmi_pci_putw(bus, dev, func, reg, hdl, val);
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
194
nb_pci_putl(int bus, int dev, int func, int reg, uint32_t val)
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
199
cmi_pci_putl(bus, dev, func, reg, hdl, val);
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
49
pci_regspec_t reg;
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
52
reg.pci_phys_hi = 16 << PCI_REG_DEV_SHIFT; /* Bus=0, Dev=16, Func=0 */
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
53
reg.pci_phys_mid = 0;
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
54
reg.pci_phys_low = 0;
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
55
reg.pci_size_hi = 0;
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
56
reg.pci_size_low = PCIE_CONF_HDR_SIZE; /* overriden in pciex */
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
60
(int *)®, sizeof (reg)/sizeof (int)) != DDI_PROP_SUCCESS)
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
67
reg.pci_phys_hi += 1 << PCI_REG_FUNC_SHIFT;
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
69
reg.pci_phys_hi = 17 << PCI_REG_DEV_SHIFT; /* Bus=0, Dev=17, Func=0 */
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
72
(int *)®, sizeof (reg)/sizeof (int)) != DDI_PROP_SUCCESS)
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
79
reg.pci_phys_hi += 1 << PCI_REG_FUNC_SHIFT;
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
81
reg.pci_phys_hi = 21 << PCI_REG_DEV_SHIFT; /* Bus=0, Dev=21, Func=0 */
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
83
(int *)®, sizeof (reg)/sizeof (int)) != DDI_PROP_SUCCESS)
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
88
reg.pci_phys_hi = 22 << PCI_REG_DEV_SHIFT; /* Bus=0, Dev=22, Func=0 */
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
90
(int *)®, sizeof (reg)/sizeof (int)) != DDI_PROP_SUCCESS)
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
95
reg.pci_phys_hi = 0; /* Bus=0, Dev=0, Func=0 */
usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c
98
(int *)®, sizeof (reg)/sizeof (int)) != DDI_PROP_SUCCESS)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
102
#define MC_CONTROL_CHANNEL_ACTIVE(reg, channel) \
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
103
((reg) & (1 << (8 + (channel))) != 0)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
104
#define MC_CONTROL_ECCEN(reg) (((reg) >> 1) & 1)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
105
#define MC_CONTROL_CLOSED_PAGE(reg) ((reg) & 1)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
106
#define MC_CONTROL_DIVBY3(reg) ((reg >> 6) &1)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
113
#define CHANNEL_DISABLED(reg, channel) ((reg) & (1 << (channel)))
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
126
#define RANKOFFSET(reg) (((reg) >> 10) & 7)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
127
#define DIMMPRESENT(reg) (((reg) & (1 << 9)) != 0)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
128
#define NUMBANK(reg) (((reg) & (3 << 7)) == 0 ? 4 : (((reg) >> 7) & 3) * 8)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
129
#define NUMRANK(reg) (((reg) & (3 << 5)) == 0 ? 1 : (((reg) >> 5) & 3) * 2)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
130
#define NUMROW(reg) ((((reg) >> 2) & 7) + 12)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
131
#define NUMCOL(reg) (((reg) & 3) + 10)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
133
#define DIMMSIZE(reg) ((1ULL << (NUMCOL(reg) + NUMROW(reg))) * NUMRANK(reg) \
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
134
* NUMBANK(reg) * DIMMWIDTH)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
139
#define DIVBY3(reg) (((reg) >> 27) & 1) /* 3 or 6 way interleave */
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
140
#define REMOVE_6(reg) (((reg) >> 24) & 1)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
141
#define REMOVE_7(reg) (((reg) >> 25) & 1)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
142
#define REMOVE_8(reg) (((reg) >> 26) & 1)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
143
#define CH_ADDRESS_OFFSET(reg) \
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
144
(int64_t)((uint64_t)(reg) & 0x00ffffff)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
145
#define CH_ADDRESS_SOFFSET(reg) \
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
146
((int64_t)(((uint64_t)(reg) & 0x00ffffff) << 40) >>40)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
158
#define RIR_LIMIT(reg) ((((uint64_t)(reg) & 0x000003ff) + 1) << 28)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
162
#define RIR_OFFSET(reg) (int64_t)((uint64_t)(reg >> 4)& 0x3ff)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
163
#define RIR_SOFFSET(reg) ((int64_t)(((uint64_t)(reg) & 0x3ff0) << 50) \
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
165
#define RIR_DIMM_RANK(reg) ((reg) & 0xf)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
166
#define RIR_RANK(reg) ((reg) & 0x3)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
167
#define RIR_DIMM(reg) ((reg)>>2 & 0x03)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
182
#define RAS_LOCKSTEP_ENABLE(reg) (((reg) & 2) != 0)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
183
#define RAS_MIRROR_MEM_ENABLE(reg) (((reg) & 1) != 0)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
187
#define REDUNDANCY_LOSS(reg) (((reg) & 1) != 0)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
191
#define SPAREING_IN_PROGRESS(reg) (((reg) & 2) != 0)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
192
#define SPAREING_COMPLETE(reg) (((reg) & 1) != 0)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
197
#define SSR_MODE(reg) ((reg) & 3)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
209
#define MAX_DIMM_CLK_RATIO(reg) (((reg) >> 24) & 0x1f)
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
311
#define CHANNEL_MAP(reg, channel, write) (((reg) >> ((channel) * 6 + \
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
62
#define MC_SCRUB_CONTROL_WR(cpu, reg) nhm_pci_putl(SOCKET_BUS(cpu), 3, 2, \
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
63
0x4c, reg);
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
65
#define MC_SSR_CONTROL_WR(cpu, reg) nhm_pci_putl(SOCKET_BUS(cpu), 3, 2, 0x48, \
usr/src/uts/intel/io/intel_nhm/intel_nhm.h
66
reg);
usr/src/uts/intel/io/intel_nhm/nhm_pci_cfg.c
110
nhm_pci_getb(int bus, int dev, int func, int reg, int *interpose)
usr/src/uts/intel/io/intel_nhm/nhm_pci_cfg.c
115
return (cmi_pci_getb(bus, dev, func, reg, interpose, hdl));
usr/src/uts/intel/io/intel_nhm/nhm_pci_cfg.c
119
nhm_pci_getw(int bus, int dev, int func, int reg, int *interpose)
usr/src/uts/intel/io/intel_nhm/nhm_pci_cfg.c
124
return (cmi_pci_getw(bus, dev, func, reg, interpose, hdl));
usr/src/uts/intel/io/intel_nhm/nhm_pci_cfg.c
128
nhm_pci_getl(int bus, int dev, int func, int reg, int *interpose)
usr/src/uts/intel/io/intel_nhm/nhm_pci_cfg.c
133
return (cmi_pci_getl(bus, dev, func, reg, interpose, hdl));
usr/src/uts/intel/io/intel_nhm/nhm_pci_cfg.c
137
nhm_pci_putb(int bus, int dev, int func, int reg, uint8_t val)
usr/src/uts/intel/io/intel_nhm/nhm_pci_cfg.c
142
cmi_pci_putb(bus, dev, func, reg, hdl, val);
usr/src/uts/intel/io/intel_nhm/nhm_pci_cfg.c
146
nhm_pci_putw(int bus, int dev, int func, int reg, uint16_t val)
usr/src/uts/intel/io/intel_nhm/nhm_pci_cfg.c
151
cmi_pci_putw(bus, dev, func, reg, hdl, val);
usr/src/uts/intel/io/intel_nhm/nhm_pci_cfg.c
155
nhm_pci_putl(int bus, int dev, int func, int reg, uint32_t val)
usr/src/uts/intel/io/intel_nhm/nhm_pci_cfg.c
160
cmi_pci_putl(bus, dev, func, reg, hdl, val);
usr/src/uts/intel/io/intel_nhm/nhm_pci_cfg.c
49
pci_regspec_t reg;
usr/src/uts/intel/io/intel_nhm/nhm_pci_cfg.c
52
reg.pci_phys_mid = 0;
usr/src/uts/intel/io/intel_nhm/nhm_pci_cfg.c
53
reg.pci_phys_low = 0;
usr/src/uts/intel/io/intel_nhm/nhm_pci_cfg.c
54
reg.pci_size_hi = 0;
usr/src/uts/intel/io/intel_nhm/nhm_pci_cfg.c
55
reg.pci_size_low = PCIE_CONF_HDR_SIZE; /* overriden in pciex */
usr/src/uts/intel/io/intel_nhm/nhm_pci_cfg.c
59
reg.pci_phys_hi = PCI_REG_MAKE_BDFR(
usr/src/uts/intel/io/intel_nhm/nhm_pci_cfg.c
63
(int *)®, sizeof (reg)/sizeof (int)) !=
usr/src/uts/intel/io/pci/pci_boot.c
1181
uint16_t reg = pci_getw(bus, dev, func,
usr/src/uts/intel/io/pci/pci_boot.c
1183
if ((reg & PCIE_LINKCTL_LINK_DISABLE) != 0) {
usr/src/uts/intel/io/pci/pci_pci.c
853
uint16_t reg;
usr/src/uts/intel/io/pci/pci_pci.c
859
reg = pci_config_get16(cfg_hdl, ptr + PCI_CAP_ID_REGS_OFF);
usr/src/uts/intel/io/pci/pci_pci.c
862
reg |= PCI_HTCAP_MSIMAP_ENABLE;
usr/src/uts/intel/io/pci/pci_pci.c
866
reg &= ~(uint16_t)PCI_HTCAP_MSIMAP_ENABLE;
usr/src/uts/intel/io/pci/pci_pci.c
869
pci_config_put16(cfg_hdl, ptr + PCI_CAP_ID_REGS_OFF, reg);
usr/src/uts/intel/io/pciex/pcieb_x86.c
467
x86_error_reg_t *reg;
usr/src/uts/intel/io/pciex/pcieb_x86.c
494
reg = tbl->error_regs;
usr/src/uts/intel/io/pciex/pcieb_x86.c
495
for (j = 0; j < tbl->error_regs_len; j++, reg++) {
usr/src/uts/intel/io/pciex/pcieb_x86.c
498
switch (reg->size) {
usr/src/uts/intel/io/pciex/pcieb_x86.c
501
reg->offset);
usr/src/uts/intel/io/pciex/pcieb_x86.c
503
((data & reg->mask) | reg->value2) :
usr/src/uts/intel/io/pciex/pcieb_x86.c
504
((data & reg->mask) | reg->value1));
usr/src/uts/intel/io/pciex/pcieb_x86.c
505
pci_config_put32(cfg_hdl, reg->offset, value);
usr/src/uts/intel/io/pciex/pcieb_x86.c
507
reg->offset);
usr/src/uts/intel/io/pciex/pcieb_x86.c
511
reg->offset);
usr/src/uts/intel/io/pciex/pcieb_x86.c
513
((data & reg->mask) | reg->value2) :
usr/src/uts/intel/io/pciex/pcieb_x86.c
514
((data & reg->mask) | reg->value1));
usr/src/uts/intel/io/pciex/pcieb_x86.c
515
pci_config_put16(cfg_hdl, reg->offset,
usr/src/uts/intel/io/pciex/pcieb_x86.c
518
reg->offset);
usr/src/uts/intel/io/pciex/pcieb_x86.c
522
reg->offset);
usr/src/uts/intel/io/pciex/pcieb_x86.c
524
((data & reg->mask) | reg->value2) :
usr/src/uts/intel/io/pciex/pcieb_x86.c
525
((data & reg->mask) | reg->value1));
usr/src/uts/intel/io/pciex/pcieb_x86.c
526
pci_config_put8(cfg_hdl, reg->offset,
usr/src/uts/intel/io/pciex/pcieb_x86.c
529
reg->offset);
usr/src/uts/intel/io/pciex/pcieb_x86.c
535
"0x%x\n", bdf, mcheck, reg->size, reg->offset,
usr/src/uts/intel/io/pciex/pcieb_x86.c
536
reg->mask, (mcheck ? reg->value2 : reg->value1),
usr/src/uts/intel/io/scsi/adapters/arcmsr/arcmsr.c
3284
ddi_acc_handle_t reg;
usr/src/uts/intel/io/scsi/adapters/arcmsr/arcmsr.c
3293
reg = acb->reg_mu_acc_handle0;
usr/src/uts/intel/io/scsi/adapters/arcmsr/arcmsr.c
3304
reg = acb->reg_mu_acc_handle1;
usr/src/uts/intel/io/scsi/adapters/arcmsr/arcmsr.c
3314
reg = acb->reg_mu_acc_handle0;
usr/src/uts/intel/io/scsi/adapters/arcmsr/arcmsr.c
3321
temp = CHIP_REG_READ8(reg, devicemap);
usr/src/uts/intel/io/vmm/amd/svm.c
2068
swctx_regptr(struct svm_regctx *regctx, int reg)
usr/src/uts/intel/io/vmm/amd/svm.c
2070
switch (reg) {
usr/src/uts/intel/io/vmm/amd/svm.c
2288
svm_setdesc(void *arg, int vcpu, int reg, const struct seg_desc *desc)
usr/src/uts/intel/io/vmm/amd/svm.c
2297
switch (reg) {
usr/src/uts/intel/io/vmm/amd/svm.c
2307
seg = vmcb_segptr(vmcb, reg);
usr/src/uts/intel/io/vmm/amd/svm.c
2326
if (reg == VM_REG_GUEST_SS) {
usr/src/uts/intel/io/vmm/amd/svm.c
2334
seg = vmcb_segptr(vmcb, reg);
usr/src/uts/intel/io/vmm/amd/svm.c
2349
svm_getdesc(void *arg, int vcpu, int reg, struct seg_desc *desc)
usr/src/uts/intel/io/vmm/amd/svm.c
2358
switch (reg) {
usr/src/uts/intel/io/vmm/amd/svm.c
2365
seg = vmcb_segptr(vmcb, reg);
usr/src/uts/intel/io/vmm/amd/svm.c
2387
if (reg == VM_REG_GUEST_SS) {
usr/src/uts/intel/io/vmm/amd/svm.c
2398
seg = vmcb_segptr(vmcb, reg);
usr/src/uts/intel/io/vmm/amd/svm.c
2404
seg = vmcb_segptr(vmcb, reg);
usr/src/uts/intel/io/vmm/amd/svm.c
822
svm_handle_cr0_read(struct svm_softc *svm_sc, int vcpu, enum vm_reg_name reg)
usr/src/uts/intel/io/vmm/amd/svm.c
828
err = svm_setreg(svm_sc, vcpu, reg, val);
usr/src/uts/intel/io/vmm/amd/svm.c
833
svm_handle_cr0_write(struct svm_softc *svm_sc, int vcpu, enum vm_reg_name reg)
usr/src/uts/intel/io/vmm/amd/svm.c
841
err = svm_getreg(svm_sc, vcpu, reg, &val);
usr/src/uts/intel/io/vmm/intel/vmx.c
3035
vmxctx_regptr(struct vmxctx *vmxctx, int reg)
usr/src/uts/intel/io/vmm/intel/vmx.c
3037
switch (reg) {
usr/src/uts/intel/io/vmm/intel/vmx.c
305
static int vmx_getdesc(void *arg, int vcpu, int reg, struct seg_desc *desc);
usr/src/uts/intel/io/vmm/intel/vmx.c
306
static int vmx_getreg(void *arg, int vcpu, int reg, uint64_t *retval);
usr/src/uts/intel/io/vmm/intel/vmx.c
3087
vmx_getreg(void *arg, int vcpu, int reg, uint64_t *retval)
usr/src/uts/intel/io/vmm/intel/vmx.c
3093
if ((regp = vmxctx_regptr(&vmx->ctx[vcpu], reg)) != NULL) {
usr/src/uts/intel/io/vmm/intel/vmx.c
3101
if (reg == VM_REG_GUEST_INTR_SHADOW) {
usr/src/uts/intel/io/vmm/intel/vmx.c
3107
encoding = vmcs_field_encoding(reg);
usr/src/uts/intel/io/vmm/intel/vmx.c
3135
vmx_setreg(void *arg, int vcpu, int reg, uint64_t val)
usr/src/uts/intel/io/vmm/intel/vmx.c
3141
if ((regp = vmxctx_regptr(&vmx->ctx[vcpu], reg)) != NULL) {
usr/src/uts/intel/io/vmm/intel/vmx.c
3149
if (reg == VM_REG_GUEST_INTR_SHADOW) {
usr/src/uts/intel/io/vmm/intel/vmx.c
3168
encoding = vmcs_field_encoding(reg);
usr/src/uts/intel/io/vmm/intel/vmx.c
3389
uint32_t baseval, reg, flag;
usr/src/uts/intel/io/vmm/intel/vmx.c
3402
reg = VMCS_PRI_PROC_BASED_CTLS;
usr/src/uts/intel/io/vmm/intel/vmx.c
3410
reg = VMCS_PRI_PROC_BASED_CTLS;
usr/src/uts/intel/io/vmm/intel/vmx.c
3419
reg = VMCS_PRI_PROC_BASED_CTLS;
usr/src/uts/intel/io/vmm/intel/vmx.c
3428
reg = VMCS_SEC_PROC_BASED_CTLS;
usr/src/uts/intel/io/vmm/intel/vmx.c
3439
reg = VMCS_EXCEPTION_BITMAP;
usr/src/uts/intel/io/vmm/intel/vmx.c
3457
vmcs_write(reg, baseval);
usr/src/uts/intel/io/vmm/intel/vmx.h
100
uint32_t reg[PAGE_SIZE / 4];
usr/src/uts/intel/io/vmm/intel/vtd.c
361
struct regspec reg;
usr/src/uts/intel/io/vmm/intel/vtd.c
379
reg.regspec_bustype = 0;
usr/src/uts/intel/io/vmm/intel/vtd.c
380
reg.regspec_addr = drhd->Address;
usr/src/uts/intel/io/vmm/intel/vtd.c
381
reg.regspec_size = PAGE_SIZE;
usr/src/uts/intel/io/vmm/intel/vtd.c
397
dip, "reg", (int *)®,
usr/src/uts/intel/io/vmm/io/ppt.c
418
pci_regspec_t *reg = ®s[i];
usr/src/uts/intel/io/vmm/io/ppt.c
422
DTRACE_PROBE1(ppt__crawl__reg, pci_regspec_t *, reg);
usr/src/uts/intel/io/vmm/io/ppt.c
423
bar = PCI_REG_REG_G(reg->pci_phys_hi);
usr/src/uts/intel/io/vmm/io/ppt.c
443
pbar->type = reg->pci_phys_hi & PCI_ADDR_MASK;
usr/src/uts/intel/io/vmm/io/ppt.c
444
pbar->base = ((uint64_t)reg->pci_phys_mid << 32) |
usr/src/uts/intel/io/vmm/io/ppt.c
445
(uint64_t)reg->pci_phys_low;
usr/src/uts/intel/io/vmm/io/ppt.c
446
pbar->size = ((uint64_t)reg->pci_size_hi << 32) |
usr/src/uts/intel/io/vmm/io/ppt.c
447
(uint64_t)reg->pci_size_low;
usr/src/uts/intel/io/vmm/io/vioapic.c
110
low = vioapic->rtbl[pin].reg;
usr/src/uts/intel/io/vmm/io/vioapic.c
111
high = vioapic->rtbl[pin].reg >> 32;
usr/src/uts/intel/io/vmm/io/vioapic.c
126
vioapic->rtbl[pin].reg |= IOART_REM_IRR;
usr/src/uts/intel/io/vmm/io/vioapic.c
271
return (vioapic->rtbl[pin].reg >> rshift);
usr/src/uts/intel/io/vmm/io/vioapic.c
307
vioapic->rtbl[pin].reg &= ~mask64 | RTBL_RO_BITS;
usr/src/uts/intel/io/vmm/io/vioapic.c
308
vioapic->rtbl[pin].reg |= data64 & ~RTBL_RO_BITS;
usr/src/uts/intel/io/vmm/io/vioapic.c
316
if ((vioapic->rtbl[pin].reg & IOART_TRGRMOD) == IOART_TRGREDG &&
usr/src/uts/intel/io/vmm/io/vioapic.c
317
(vioapic->rtbl[pin].reg & IOART_REM_IRR) != 0)
usr/src/uts/intel/io/vmm/io/vioapic.c
318
vioapic->rtbl[pin].reg &= ~IOART_REM_IRR;
usr/src/uts/intel/io/vmm/io/vioapic.c
325
if ((vioapic->rtbl[pin].reg & IOART_TRGRMOD) == IOART_TRGRLVL &&
usr/src/uts/intel/io/vmm/io/vioapic.c
411
if ((vioapic->rtbl[pin].reg & IOART_REM_IRR) == 0)
usr/src/uts/intel/io/vmm/io/vioapic.c
413
if ((vioapic->rtbl[pin].reg & IOART_INTVEC) != vector)
usr/src/uts/intel/io/vmm/io/vioapic.c
415
vioapic->rtbl[pin].reg &= ~IOART_REM_IRR;
usr/src/uts/intel/io/vmm/io/vioapic.c
437
vioapic->rtbl[i].reg = 0x0001000000010000UL;
usr/src/uts/intel/io/vmm/io/vioapic.c
470
out->vi_pin_reg[i] = vioapic->rtbl[i].reg;
usr/src/uts/intel/io/vmm/io/vioapic.c
492
vioapic->rtbl[i].reg = src->vi_pin_reg[i] & ~RTBL_RO_BITS;
usr/src/uts/intel/io/vmm/io/vioapic.c
83
uint64_t reg;
usr/src/uts/intel/io/vmm/io/vlapic.c
1235
uint32_t *reg;
usr/src/uts/intel/io/vmm/io/vlapic.c
1270
reg = &lapic->isr0;
usr/src/uts/intel/io/vmm/io/vlapic.c
1271
data = *(reg + i);
usr/src/uts/intel/io/vmm/io/vlapic.c
1275
reg = &lapic->tmr0;
usr/src/uts/intel/io/vmm/io/vlapic.c
1276
data = *(reg + i);
usr/src/uts/intel/io/vmm/io/vlapic.c
1280
reg = &lapic->irr0;
usr/src/uts/intel/io/vmm/io/vlapic.c
1281
data = atomic_load_acq_int(reg + i);
usr/src/uts/intel/io/vmm/io/vlapic.c
1296
reg = vlapic_get_lvtptr(vlapic, offset);
usr/src/uts/intel/io/vmm/io/vlapic.c
1297
ASSERT3U(data, ==, *reg);
usr/src/uts/intel/io/vmm/io/vlapic.c
1638
const uint16_t reg = vlapic_msr_to_regoff(msr);
usr/src/uts/intel/io/vmm/io/vlapic.c
1639
switch (reg) {
usr/src/uts/intel/io/vmm/io/vlapic.c
1659
if (!vlapic_read(vlapic, reg, (uint32_t *)&out)) {
usr/src/uts/intel/io/vmm/io/vlapic.c
1680
const uint16_t reg = vlapic_msr_to_regoff(msr);
usr/src/uts/intel/io/vmm/io/vlapic.c
1681
switch (reg) {
usr/src/uts/intel/io/vmm/io/vlapic.c
1704
if (!vlapic_write(vlapic, reg, val)) {
usr/src/uts/intel/io/vmm/io/vlapic.c
485
uint32_t mode, reg, vec;
usr/src/uts/intel/io/vmm/io/vlapic.c
488
reg = atomic_load_acq_32(&vlapic->lvt_last[lvt]);
usr/src/uts/intel/io/vmm/io/vlapic.c
490
if (reg & APIC_LVT_M)
usr/src/uts/intel/io/vmm/io/vlapic.c
492
vec = reg & APIC_LVT_VECTOR;
usr/src/uts/intel/io/vmm/io/vlapic.c
493
mode = reg & APIC_LVT_DM;
usr/src/uts/intel/io/vmm/io/vlapic.c
527
uint32_t reg = *isrp;
usr/src/uts/intel/io/vmm/io/vlapic.c
529
if (reg != 0) {
usr/src/uts/intel/io/vmm/io/vlapic.c
530
uint_t vec = (i * 32) + bsrl(reg);
usr/src/uts/intel/io/vmm/sys/vmm_kernel.h
184
int vm_get_register(struct vm *vm, int vcpu, int reg, uint64_t *retval);
usr/src/uts/intel/io/vmm/sys/vmm_kernel.h
185
int vm_set_register(struct vm *vm, int vcpu, int reg, uint64_t val);
usr/src/uts/intel/io/vmm/sys/vmm_kernel.h
186
int vm_get_seg_desc(struct vm *vm, int vcpu, int reg,
usr/src/uts/intel/io/vmm/sys/vmm_kernel.h
188
int vm_set_seg_desc(struct vm *vm, int vcpu, int reg,
usr/src/uts/intel/io/vmm/vmm.c
1201
vm_get_register(struct vm *vm, int vcpuid, int reg, uint64_t *retval)
usr/src/uts/intel/io/vmm/vmm.c
1206
if (reg >= VM_REG_LAST)
usr/src/uts/intel/io/vmm/vmm.c
1210
switch (reg) {
usr/src/uts/intel/io/vmm/vmm.c
1215
return (VMGETREG(vm->cookie, vcpuid, reg, retval));
usr/src/uts/intel/io/vmm/vmm.c
1220
vm_set_register(struct vm *vm, int vcpuid, int reg, uint64_t val)
usr/src/uts/intel/io/vmm/vmm.c
1225
if (reg >= VM_REG_LAST)
usr/src/uts/intel/io/vmm/vmm.c
1230
switch (reg) {
usr/src/uts/intel/io/vmm/vmm.c
1232
error = VMSETREG(vm->cookie, vcpuid, reg, val);
usr/src/uts/intel/io/vmm/vmm.c
1244
return (VMSETREG(vm->cookie, vcpuid, reg, val));
usr/src/uts/intel/io/vmm/vmm.c
1249
is_descriptor_table(int reg)
usr/src/uts/intel/io/vmm/vmm.c
1251
switch (reg) {
usr/src/uts/intel/io/vmm/vmm.c
1261
is_segment_register(int reg)
usr/src/uts/intel/io/vmm/vmm.c
1263
switch (reg) {
usr/src/uts/intel/io/vmm/vmm.c
1279
vm_get_seg_desc(struct vm *vm, int vcpu, int reg, struct seg_desc *desc)
usr/src/uts/intel/io/vmm/vmm.c
1285
if (!is_segment_register(reg) && !is_descriptor_table(reg))
usr/src/uts/intel/io/vmm/vmm.c
1288
return (VMGETDESC(vm->cookie, vcpu, reg, desc));
usr/src/uts/intel/io/vmm/vmm.c
1292
vm_set_seg_desc(struct vm *vm, int vcpu, int reg, const struct seg_desc *desc)
usr/src/uts/intel/io/vmm/vmm.c
1297
if (!is_segment_register(reg) && !is_descriptor_table(reg))
usr/src/uts/intel/io/vmm/vmm.c
1300
return (VMSETDESC(vm->cookie, vcpu, reg, desc));
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1010
enum vm_reg_name reg;
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1033
reg = gpr_map[vie->reg];
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1039
error = vie_update_register(vm, vcpuid, reg, val, size);
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1053
reg = gpr_map[vie->reg];
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1058
error = vie_update_register(vm, vcpuid, reg, val, size);
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1076
reg = gpr_map[vie->reg];
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1082
error = vie_update_register(vm, vcpuid, reg, val, size);
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
119
reg:4,
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1395
enum vm_reg_name reg;
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1413
reg = gpr_map[vie->reg];
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1414
error = vm_get_register(vm, vcpuid, reg, &val1);
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1425
error = vie_update_register(vm, vcpuid, reg, result, size);
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1482
enum vm_reg_name reg;
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1500
reg = gpr_map[vie->reg];
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1501
error = vm_get_register(vm, vcpuid, reg, &val1);
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1512
error = vie_update_register(vm, vcpuid, reg, result, size);
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1570
enum vm_reg_name reg;
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1592
reg = gpr_map[vie->reg];
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1593
error = vm_get_register(vm, vcpuid, reg, ®op);
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1675
if ((vie->reg & 7) != 0)
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1697
if ((vie->reg & 7) != 0)
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1785
error = vie_update_register(vm, vcpuid, gpr_map[vie->reg], dst, size);
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1806
enum vm_reg_name reg;
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1822
reg = gpr_map[vie->reg];
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1823
error = vm_get_register(vm, vcpuid, reg, &val1);
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1834
error = vie_update_register(vm, vcpuid, reg, nval, size);
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1861
enum vm_reg_name reg;
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1877
reg = gpr_map[vie->reg];
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1878
error = vm_get_register(vm, vcpuid, reg, &val1);
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1889
error = vie_update_register(vm, vcpuid, reg, nval, size);
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1917
enum vm_reg_name reg;
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1938
reg = gpr_map[vie->reg];
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1939
error = vm_get_register(vm, vcpuid, reg, &val1);
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1951
error = vie_update_register(vm, vcpuid, reg, nval, size);
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
1954
const char *, vie_regnum_name(vie->reg, size),
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
2090
if ((vie->reg & 7) != 6)
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
2108
if ((vie->reg & 7) != 0)
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
2120
switch (vie->reg & 7) {
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
2150
if ((vie->reg & 7) != 4)
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
2186
switch (vie->reg & 7) {
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
3593
vie->reg = (x >> 3) & 0x7;
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
3621
vie->reg |= (vie->rex_r << 3);
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
513
vie_calc_bytereg(struct vie *vie, enum vm_reg_name *reg, int *lhbr)
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
516
*reg = gpr_map[vie->reg];
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
531
if (vie->reg & 0x4) {
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
533
*reg = gpr_map[vie->reg & 0x3];
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
543
enum vm_reg_name reg;
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
545
vie_calc_bytereg(vie, ®, &lhbr);
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
546
error = vm_get_register(vm, vcpuid, reg, &val);
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
564
enum vm_reg_name reg;
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
566
vie_calc_bytereg(vie, ®, &lhbr);
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
567
error = vm_get_register(vm, vcpuid, reg, &origval);
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
580
error = vm_set_register(vm, vcpuid, reg, val);
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
586
vie_update_register(struct vm *vm, int vcpuid, enum vm_reg_name reg,
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
595
error = vm_get_register(vm, vcpuid, reg, &origval);
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
610
error = vm_set_register(vm, vcpuid, reg, val);
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
790
enum vm_reg_name cr = cr_map[vie->reg];
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
894
enum vm_reg_name reg;
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
922
reg = gpr_map[vie->reg];
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
923
error = vm_get_register(vm, vcpuid, reg, &val);
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
949
reg = gpr_map[vie->reg];
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
950
error = vie_update_register(vm, vcpuid, reg, val, size);
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
962
reg = VM_REG_GUEST_RAX;
usr/src/uts/intel/io/vmm/vmm_instruction_emul.c
963
error = vie_update_register(vm, vcpuid, reg, val, size);
usr/src/uts/intel/io/vmm/vmm_sol_dev.c
3357
hma_reg_t *reg = NULL;
usr/src/uts/intel/io/vmm/vmm_sol_dev.c
3377
if ((reg = hma_register(vmmdev_hvm_name)) == NULL) {
usr/src/uts/intel/io/vmm/vmm_sol_dev.c
3383
hma_unregister(reg);
usr/src/uts/intel/io/vmm/vmm_sol_dev.c
3384
reg = NULL;
usr/src/uts/intel/io/vmm/vmm_sol_dev.c
3408
if (reg != NULL) {
usr/src/uts/intel/io/vmm/vmm_sol_dev.c
3409
hma_unregister(reg);
usr/src/uts/intel/io/vmxnet3s/vmxnet3_defs.h
70
#define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF))
usr/src/uts/intel/os/cpuid.c
3514
uint64_t reg;
usr/src/uts/intel/os/cpuid.c
3516
reg = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
usr/src/uts/intel/os/cpuid.c
3517
if (reg & IA32_ARCH_CAP_RDCL_NO) {
usr/src/uts/intel/os/cpuid.c
3521
if (reg & IA32_ARCH_CAP_IBRS_ALL) {
usr/src/uts/intel/os/cpuid.c
3525
if (reg & IA32_ARCH_CAP_RSBA) {
usr/src/uts/intel/os/cpuid.c
3529
if (reg & IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY) {
usr/src/uts/intel/os/cpuid.c
3533
if (reg & IA32_ARCH_CAP_SSB_NO) {
usr/src/uts/intel/os/cpuid.c
3537
if (reg & IA32_ARCH_CAP_MDS_NO) {
usr/src/uts/intel/os/cpuid.c
3541
if (reg & IA32_ARCH_CAP_TSX_CTRL) {
usr/src/uts/intel/os/cpuid.c
3545
if (reg & IA32_ARCH_CAP_TAA_NO) {
usr/src/uts/intel/os/cpuid.c
3549
if (reg & IA32_ARCH_CAP_RFDS_NO) {
usr/src/uts/intel/os/cpuid.c
3553
if (reg & IA32_ARCH_CAP_RFDS_CLEAR) {
usr/src/uts/intel/os/cpuid.c
3557
if (reg & IA32_ARCH_CAP_PBRSB_NO) {
usr/src/uts/intel/os/cpuid.c
3561
if (reg & IA32_ARCH_CAP_BHI_NO) {
usr/src/uts/intel/os/cpuid.c
7999
uint64_t reg;
usr/src/uts/intel/os/cpuid.c
8002
reg = rdmsr(MSR_AMD_INT_PENDING_CMP_HALT);
usr/src/uts/intel/os/cpuid.c
8004
if ((reg >> AMD_ACTONCMPHALT_SHIFT) &
usr/src/uts/intel/os/cpuid.c
8006
reg &= ~(AMD_ACTONCMPHALT_MASK <<
usr/src/uts/intel/os/cpuid.c
8008
wrmsr(MSR_AMD_INT_PENDING_CMP_HALT, reg);
usr/src/uts/intel/os/hma.c
174
struct hma_reg *reg;
usr/src/uts/intel/os/hma.c
195
reg = kmem_zalloc(sizeof (*reg), KM_SLEEP);
usr/src/uts/intel/os/hma.c
196
reg->hr_name = name;
usr/src/uts/intel/os/hma.c
197
list_insert_tail(&hma_registrations, reg);
usr/src/uts/intel/os/hma.c
199
return (reg);
usr/src/uts/intel/os/hma.c
205
struct hma_reg *reg = NULL;
usr/src/uts/intel/os/hma.c
212
reg = hma_register_backend(name);
usr/src/uts/intel/os/hma.c
216
return (reg);
usr/src/uts/intel/os/hma.c
222
struct hma_reg *reg = NULL;
usr/src/uts/intel/os/hma.c
229
reg = hma_register_backend(name);
usr/src/uts/intel/os/hma.c
230
if (reg != NULL)
usr/src/uts/intel/os/hma.c
236
return (reg);
usr/src/uts/intel/os/hma.c
240
hma_unregister(hma_reg_t *reg)
usr/src/uts/intel/os/hma.c
242
VERIFY(reg != NULL);
usr/src/uts/intel/os/hma.c
246
list_remove(&hma_registrations, reg);
usr/src/uts/intel/os/hma.c
250
kmem_free(reg, sizeof (*reg));
usr/src/uts/intel/sys/amdzen/ccd.h
108
const uint32_t reg = def.srd_reg + reginst32 * stride;
usr/src/uts/intel/sys/amdzen/ccd.h
109
ASSERT0(reg & APERTURE_MASK);
usr/src/uts/intel/sys/amdzen/ccd.h
111
return (SMN_MAKE_REG_SIZED(aperture + reg, size32));
usr/src/uts/intel/sys/amdzen/ccd.h
249
const uint32_t reg = def.srd_reg + reginst32 * stride;
usr/src/uts/intel/sys/amdzen/ccd.h
250
ASSERT0(reg & APERTURE_MASK);
usr/src/uts/intel/sys/amdzen/ccd.h
252
return (SMN_MAKE_REG_SIZED(aperture + reg, size32));
usr/src/uts/intel/sys/amdzen/ccd.h
367
const uint32_t reg = def.srd_reg + reginst32 * stride;
usr/src/uts/intel/sys/amdzen/ccd.h
368
ASSERT0(reg & APERTURE_MASK);
usr/src/uts/intel/sys/amdzen/ccd.h
370
return (SMN_MAKE_REG_SIZED(aperture + reg, size32));
usr/src/uts/intel/sys/amdzen/smn.h
381
SMN_REG_SIZE_IS_VALID(const smn_reg_t reg)
usr/src/uts/intel/sys/amdzen/smn.h
383
return (reg.sr_size == 1 || reg.sr_size == 2 || reg.sr_size == 4);
usr/src/uts/intel/sys/amdzen/smn.h
391
SMN_REG_IS_NATURALLY_ALIGNED(const smn_reg_t reg)
usr/src/uts/intel/sys/amdzen/smn.h
393
return (SMN_REG_IS_ALIGNED(reg, reg.sr_size));
usr/src/uts/intel/sys/amdzen/smn.h
406
SMN_REG_ADDR_BASE(const smn_reg_t reg)
usr/src/uts/intel/sys/amdzen/smn.h
408
return (reg.sr_addr & ~3);
usr/src/uts/intel/sys/amdzen/smn.h
417
SMN_REG_ADDR_OFF(const smn_reg_t reg)
usr/src/uts/intel/sys/amdzen/smn.h
419
return (reg.sr_addr & 3);
usr/src/uts/intel/sys/amdzen/smn.h
523
const uint32_t reg = def.srd_reg + reginst32 * stride; \
usr/src/uts/intel/sys/amdzen/smn.h
524
ASSERT0(reg & (_mask)); \
usr/src/uts/intel/sys/amdzen/smn.h
526
return (SMN_MAKE_REG_SIZED(aperture + reg, size32)); \
usr/src/uts/intel/sys/amdzen/umc.h
109
const uint32_t reg = def.srd_reg + reginst32 * stride;
usr/src/uts/intel/sys/amdzen/umc.h
110
ASSERT0(reg & APERTURE_MASK);
usr/src/uts/intel/sys/amdzen/umc.h
112
return (SMN_MAKE_REG(aperture + reg));
usr/src/uts/intel/sys/asm_linkage.h
319
#define INDIRECT_JMP_REG(reg) jmp __x86_indirect_thunk_##reg;
usr/src/uts/intel/sys/asm_linkage.h
322
#define INDIRECT_CALL_REG(reg) call __x86_indirect_thunk_##reg;
usr/src/uts/intel/sys/pci_cfgspace.h
43
extern uint8_t (*pci_getb_func)(int bus, int dev, int func, int reg);
usr/src/uts/intel/sys/pci_cfgspace.h
44
extern uint16_t (*pci_getw_func)(int bus, int dev, int func, int reg);
usr/src/uts/intel/sys/pci_cfgspace.h
45
extern uint32_t (*pci_getl_func)(int bus, int dev, int func, int reg);
usr/src/uts/intel/sys/pci_cfgspace.h
46
extern void (*pci_putb_func)(int bus, int dev, int func, int reg, uint8_t val);
usr/src/uts/intel/sys/pci_cfgspace.h
47
extern void (*pci_putw_func)(int bus, int dev, int func, int reg, uint16_t val);
usr/src/uts/intel/sys/pci_cfgspace.h
48
extern void (*pci_putl_func)(int bus, int dev, int func, int reg, uint32_t val);
usr/src/uts/intel/sys/traptrace.h
163
#define __GETCR2(_mov, reg) \
usr/src/uts/intel/sys/traptrace.h
164
_mov %gs:CPU_VCPU_INFO, reg; \
usr/src/uts/intel/sys/traptrace.h
165
_mov VCPU_INFO_ARCH_CR2(reg), reg
usr/src/uts/intel/sys/traptrace.h
167
#define __GETCR2(_mov, reg) \
usr/src/uts/intel/sys/traptrace.h
168
_mov %cr2, reg
usr/src/uts/intel/sys/traptrace.h
173
#define TRACE_REGS(ptr, reg, scr1, scr2) \
usr/src/uts/intel/sys/traptrace.h
176
9: movq (reg, scr1, 1), scr2; \
usr/src/uts/intel/sys/traptrace.h
188
#define TRACE_REGS(ptr, reg, scr1, scr2) \
usr/src/uts/intel/sys/traptrace.h
191
9: movl (reg, scr1, 1), scr2; \
usr/src/uts/intel/sys/traptrace.h
211
#define TRACE_STAMP(reg) \
usr/src/uts/intel/sys/traptrace.h
213
movl %eax, TTR_STAMP(reg); \
usr/src/uts/intel/sys/traptrace.h
214
movl %edx, TTR_STAMP+4(reg)
usr/src/uts/intel/sys/traptrace.h
245
#define TRACE_STAMP(reg) \
usr/src/uts/intel/sys/traptrace.h
251
9: movl %eax, TTR_STAMP(reg); \
usr/src/uts/intel/sys/traptrace.h
252
movl %edx, TTR_STAMP+4(reg)
usr/src/uts/intel/sys/traptrace.h
276
#define TRACE_REGS(ptr, reg, scr1, scr2)
usr/src/uts/intel/sys/traptrace.h
277
#define TRACE_STAMP(reg)
usr/src/uts/intel/sys/traptrace.h
278
#define TRACE_STACK(reg)
usr/src/uts/sfmmu/vm/hat_sfmmu.h
2000
#define MAKE_NOP_INSTR(reg) \
usr/src/uts/sfmmu/vm/hat_sfmmu.h
2001
sethi %hi(0x1000000), reg
usr/src/uts/sfmmu/vm/hat_sfmmu.h
2010
#define MAKE_JMP_INSTR(jump_reg_number, reg, tmp) \
usr/src/uts/sfmmu/vm/hat_sfmmu.h
2011
sethi %hi(0x81c00000), reg; \
usr/src/uts/sfmmu/vm/hat_sfmmu.h
2014
or reg, tmp, reg
usr/src/uts/sfmmu/vm/hat_sfmmu.h
2039
#define SFMMU_MMUID_GNUM_CNUM(entry, gnum, cnum, reg) \
usr/src/uts/sfmmu/vm/hat_sfmmu.h
2040
ldx [entry + SFMMU_CTXS], reg; /* reg = sfmmu (gnum | cnum) */ \
usr/src/uts/sfmmu/vm/hat_sfmmu.h
2041
srlx reg, SFMMU_MMU_GNUM_RSHIFT, gnum; /* gnum = sfmmu gnum */ \
usr/src/uts/sfmmu/vm/hat_sfmmu.h
2042
sllx reg, SFMMU_MMU_CNUM_LSHIFT, cnum; \
usr/src/uts/sparc/dtrace/dtrace_isa.c
747
dtrace_getreg(struct regs *rp, uint_t reg)
usr/src/uts/sparc/dtrace/dtrace_isa.c
753
if (reg == R_G0)
usr/src/uts/sparc/dtrace/dtrace_isa.c
756
if (reg <= R_G7)
usr/src/uts/sparc/dtrace/dtrace_isa.c
757
return ((&rp->r_g1)[reg - 1]);
usr/src/uts/sparc/dtrace/dtrace_isa.c
759
if (reg > R_I7) {
usr/src/uts/sparc/dtrace/dtrace_isa.c
760
switch (reg) {
usr/src/uts/sparc/dtrace/dtrace_isa.c
791
if (reg > R_O7)
usr/src/uts/sparc/dtrace/dtrace_isa.c
794
reg += R_I0 - R_O0;
usr/src/uts/sparc/dtrace/dtrace_isa.c
796
} else if (reg <= R_O7) {
usr/src/uts/sparc/dtrace/dtrace_isa.c
797
return ((&rp->r_g1)[reg - 1]);
usr/src/uts/sparc/dtrace/dtrace_isa.c
801
return (dtrace_getreg_win(reg, 1));
usr/src/uts/sparc/dtrace/dtrace_isa.c
814
return (rwin[i].rw_local[reg - 16]);
usr/src/uts/sparc/dtrace/dtrace_isa.c
819
value = dtrace_fulword(&fr->fr_local[reg - 16]);
usr/src/uts/sparc/dtrace/dtrace_isa.c
830
return (rwin[i].rw_local[reg - 16]);
usr/src/uts/sparc/dtrace/dtrace_isa.c
835
value = dtrace_fuword32(&fr->fr_local[reg - 16]);
usr/src/uts/sparc/dtrace/dtrace_isa.c
842
ASSERT(R_L0 <= reg && reg <= R_I7);
usr/src/uts/sparc/dtrace/dtrace_isa.c
849
return (dtrace_getreg_win(reg, 2));
usr/src/uts/sparc/dtrace/dtrace_isa.c
915
return (rwin[i].rw_local[reg - 16]);
usr/src/uts/sparc/dtrace/dtrace_isa.c
920
value = dtrace_fulword(&fr->fr_local[reg - 16]);
usr/src/uts/sparc/dtrace/dtrace_isa.c
931
return (rwin[i].rw_local[reg - 16]);
usr/src/uts/sparc/dtrace/dtrace_isa.c
936
value = dtrace_fuword32(&fr->fr_local[reg - 16]);
usr/src/uts/sparc/dtrace/dtrace_isa.c
945
dtrace_setreg(struct regs *rp, uint_t reg, ulong_t val)
usr/src/uts/sparc/dtrace/fasttrap_isa.c
1384
fasttrap_getreg(struct regs *rp, uint_t reg)
usr/src/uts/sparc/dtrace/fasttrap_isa.c
1396
if (reg == 0)
usr/src/uts/sparc/dtrace/fasttrap_isa.c
1399
if (reg < 16)
usr/src/uts/sparc/dtrace/fasttrap_isa.c
1400
return ((&rp->r_g1)[reg - 1]);
usr/src/uts/sparc/dtrace/fasttrap_isa.c
1408
value = dtrace_getreg_win(reg, 1);
usr/src/uts/sparc/dtrace/fasttrap_isa.c
1437
return (rwin[i].rw_local[reg - 16]);
usr/src/uts/sparc/dtrace/fasttrap_isa.c
1441
if (fasttrap_fulword(&fr->fr_local[reg - 16], &value) != 0)
usr/src/uts/sparc/dtrace/fasttrap_isa.c
1457
return (rwin[i].rw_local[reg - 16]);
usr/src/uts/sparc/dtrace/fasttrap_isa.c
1461
if (fasttrap_fuword32(&fr->fr_local[reg - 16], &v32[1]) != 0)
usr/src/uts/sparc/dtrace/fasttrap_isa.c
1484
fasttrap_putreg(struct regs *rp, uint_t reg, ulong_t value)
usr/src/uts/sparc/dtrace/fasttrap_isa.c
1490
if (reg == 0)
usr/src/uts/sparc/dtrace/fasttrap_isa.c
1493
if (reg < 16) {
usr/src/uts/sparc/dtrace/fasttrap_isa.c
1494
(&rp->r_g1)[reg - 1] = value;
usr/src/uts/sparc/dtrace/fasttrap_isa.c
1504
dtrace_putreg_win(reg, value);
usr/src/uts/sparc/dtrace/fasttrap_isa.c
1536
rwin[i].rw_local[reg - 16] = value;
usr/src/uts/sparc/dtrace/fasttrap_isa.c
1542
if (fasttrap_sulword(&fr->fr_local[reg - 16], value) != 0) {
usr/src/uts/sparc/dtrace/fasttrap_isa.c
1547
rwin[mpcb->mpcb_wbcnt].rw_local[reg - 16] = value;
usr/src/uts/sparc/dtrace/fasttrap_isa.c
1567
rwin[i].rw_local[reg - 16] = v32;
usr/src/uts/sparc/dtrace/fasttrap_isa.c
1573
if (fasttrap_suword32(&fr->fr_local[reg - 16], v32) != 0) {
usr/src/uts/sparc/dtrace/fasttrap_isa.c
1578
rwin[mpcb->mpcb_wbcnt].rw_local[reg - 16] = v32;
usr/src/uts/sparc/dtrace/fasttrap_isa.c
820
uint_t reg = RS1(tp->ftt_instr);
usr/src/uts/sparc/dtrace/fasttrap_isa.c
829
ASSERT(p->p_model == DATAMODEL_LP64 || reg < 16);
usr/src/uts/sparc/dtrace/fasttrap_isa.c
831
value = (int64_t)fasttrap_getreg(rp, reg);
usr/src/uts/sparc/dtrace/fbt.c
239
#define FBT_SETHI(val, reg) \
usr/src/uts/sparc/dtrace/fbt.c
240
(FBT_OP_SETHI | (reg << FBT_FMT2_RD_SHIFT) | \
usr/src/uts/sparc/dtrace/sdt.c
92
#define SDT_SETHI(val, reg) \
usr/src/uts/sparc/dtrace/sdt.c
93
(SDT_OP_SETHI | (reg << SDT_FMT2_RD_SHIFT) | \
usr/src/uts/sparc/io/pciex/pcieb_sparc.c
279
uint16_t reg = 0;
usr/src/uts/sparc/io/pciex/pcieb_sparc.c
310
reg |= pci_config_get16(config_handle, PCI_CONF_VENID);
usr/src/uts/sparc/os/cpr_sparc.c
472
int reg[512];
usr/src/uts/sparc/os/cpr_sparc.c
482
2 * sizeof (int) || prop_len >= sizeof (reg))
usr/src/uts/sparc/os/cpr_sparc.c
485
if (prom_getprop(node, OBP_REG, (caddr_t)reg) < 0)
usr/src/uts/sparc/os/cpr_sparc.c
488
(void) sprintf(buf, "@%x,%x", reg[0], reg[1]);
usr/src/uts/sparc/v9/os/simulator.c
1190
getreg(struct regs *rp, uint_t reg, uint64_t *val, caddr_t *badaddr)
usr/src/uts/sparc/v9/os/simulator.c
1197
if (reg == 0) {
usr/src/uts/sparc/v9/os/simulator.c
1199
} else if (reg < 16) {
usr/src/uts/sparc/v9/os/simulator.c
1200
*val = rgs[reg];
usr/src/uts/sparc/v9/os/simulator.c
1203
uint64_t *addr = (uint64_t *)&rw[reg - 16];
usr/src/uts/sparc/v9/os/simulator.c
1218
uint32_t *addr = (uint32_t *)&rw[reg - 16];
usr/src/uts/sparc/v9/os/simulator.c
1243
putreg(uint64_t *data, struct regs *rp, uint_t reg, caddr_t *badaddr)
usr/src/uts/sparc/v9/os/simulator.c
1250
if (reg == 0) {
usr/src/uts/sparc/v9/os/simulator.c
1252
} else if (reg < 16) {
usr/src/uts/sparc/v9/os/simulator.c
1253
rgs[reg] = *data;
usr/src/uts/sparc/v9/os/simulator.c
1256
uint64_t *addr = (uint64_t *)&rw[reg - 16];
usr/src/uts/sparc/v9/os/simulator.c
1280
uint32_t *addr = (uint32_t *)&rw[reg - 16];
usr/src/uts/sun/io/audio/drv/audiocs/audio_4231.c
1766
uint8_t reg;
usr/src/uts/sun/io/audio/drv/audiocs/audio_4231.c
1774
reg = FSDF_REG;
usr/src/uts/sun/io/audio/drv/audiocs/audio_4231.c
1778
reg = CDF_REG;
usr/src/uts/sun/io/audio/drv/audiocs/audio_4231.c
1784
SELIDX(state, reg | IAR_MCE);
usr/src/uts/sun/io/audio/drv/audiocs/audio_4231.c
2151
audiocs_sel_index(CS_state_t *state, uint8_t reg, int n)
usr/src/uts/sun/io/audio/drv/audiocs/audio_4231.c
2153
audiocs_sel_index(CS_state_t *state, uint8_t reg)
usr/src/uts/sun/io/audio/drv/audiocs/audio_4231.c
2162
ddi_put8(handle, addr, reg);
usr/src/uts/sun/io/audio/drv/audiocs/audio_4231.c
2164
if (T == reg) {
usr/src/uts/sun/io/audio/drv/audiocs/audio_4231.c
2177
T, reg);
usr/src/uts/sun/io/audio/drv/audiocs/audio_4231_apcdma.c
271
uint32_t reg;
usr/src/uts/sun/io/audio/drv/audiocs/audio_4231_apcdma.c
292
reg = ddi_get32(handle, &APC_DMACSR);
usr/src/uts/sun/io/audio/drv/audiocs/audio_4231_apcdma.c
293
for (int x = 0; (!(reg & drainbit)) && (x < CS4231_TIMEOUT); x++) {
usr/src/uts/sun/io/audio/drv/audiocs/audio_4231_apcdma.c
295
reg = ddi_get32(handle, &APC_DMACSR);
usr/src/uts/sun/io/audio/drv/audiocs/audio_4231_eb2dma.c
205
uint_t reg;
usr/src/uts/sun/io/audio/drv/audiocs/audio_4231_eb2dma.c
211
reg = ddi_get32(phandle, &EB2_PLAY_CSR);
usr/src/uts/sun/io/audio/drv/audiocs/audio_4231_eb2dma.c
212
for (x = 0; (reg & EB2_FIFO_DRAIN) && x < CS4231_TIMEOUT; x++) {
usr/src/uts/sun/io/audio/drv/audiocs/audio_4231_eb2dma.c
214
reg = ddi_get32(phandle, &EB2_PLAY_CSR);
usr/src/uts/sun/io/audio/drv/audiocs/audio_4231_eb2dma.c
222
reg = ddi_get32(rhandle, &EB2_REC_CSR);
usr/src/uts/sun/io/audio/drv/audiocs/audio_4231_eb2dma.c
223
for (x = 0; (reg & EB2_FIFO_DRAIN) && x < CS4231_TIMEOUT; x++) {
usr/src/uts/sun/io/audio/drv/audiocs/audio_4231_eb2dma.c
225
reg = ddi_get32(rhandle, &EB2_REC_CSR);
usr/src/uts/sun/io/eri/eri_common.h
344
#define GET_PCSREG(reg) \
usr/src/uts/sun/io/eri/eri_common.h
345
ddi_get32(erip->pcsregh, (uint32_t *)&erip->pcsregp->reg)
usr/src/uts/sun/io/eri/eri_common.h
346
#define PUT_PCSREG(reg, value) \
usr/src/uts/sun/io/eri/eri_common.h
347
ddi_put32(erip->pcsregh, (uint32_t *)&erip->pcsregp->reg, value)
usr/src/uts/sun/io/eri/eri_common.h
348
#define GET_MIFREG(reg) \
usr/src/uts/sun/io/eri/eri_common.h
349
ddi_get32(erip->mifregh, (uint32_t *)&erip->mifregp->reg)
usr/src/uts/sun/io/eri/eri_common.h
350
#define PUT_MIFREG(reg, value) \
usr/src/uts/sun/io/eri/eri_common.h
351
ddi_put32(erip->mifregh, (uint32_t *)&erip->mifregp->reg, value)
usr/src/uts/sun/io/eri/eri_common.h
352
#define GET_ETXREG(reg) \
usr/src/uts/sun/io/eri/eri_common.h
353
ddi_get32(erip->etxregh, (uint32_t *)&erip->etxregp->reg)
usr/src/uts/sun/io/eri/eri_common.h
354
#define PUT_ETXREG(reg, value) \
usr/src/uts/sun/io/eri/eri_common.h
355
ddi_put32(erip->etxregh, (uint32_t *)&erip->etxregp->reg, value)
usr/src/uts/sun/io/eri/eri_common.h
356
#define GET_ERXREG(reg) \
usr/src/uts/sun/io/eri/eri_common.h
357
ddi_get32(erip->erxregh, (uint32_t *)&erip->erxregp->reg)
usr/src/uts/sun/io/eri/eri_common.h
358
#define PUT_ERXREG(reg, value) \
usr/src/uts/sun/io/eri/eri_common.h
359
ddi_put32(erip->erxregh, (uint32_t *)&erip->erxregp->reg, value)
usr/src/uts/sun/io/eri/eri_common.h
360
#define GET_MACREG(reg) \
usr/src/uts/sun/io/eri/eri_common.h
361
ddi_get32(erip->bmacregh, (uint32_t *)&erip->bmacregp->reg)
usr/src/uts/sun/io/eri/eri_common.h
362
#define PUT_MACREG(reg, value) \
usr/src/uts/sun/io/eri/eri_common.h
364
(uint32_t *)&erip->bmacregp->reg, value)
usr/src/uts/sun/io/eri/eri_common.h
365
#define GET_GLOBREG(reg) \
usr/src/uts/sun/io/eri/eri_common.h
366
ddi_get32(erip->globregh, (uint32_t *)&erip->globregp->reg)
usr/src/uts/sun/io/eri/eri_common.h
367
#define PUT_GLOBREG(reg, value) \
usr/src/uts/sun/io/eri/eri_common.h
369
(uint32_t *)&erip->globregp->reg, value)
usr/src/uts/sun/io/eri/eri_common.h
371
#define GET_SWRSTREG(reg) \
usr/src/uts/sun/io/eri/eri_common.h
374
#define PUT_SWRSTREG(reg, value) \
usr/src/uts/sun/io/sbusmem.c
332
caddr_t reg;
usr/src/uts/sun/io/sbusmem.c
359
if (ddi_map_regs(dip, 0, ®, uio->uio_offset,
usr/src/uts/sun/io/sbusmem.c
364
if (ddi_peekpokeio(dip, uio, rw, reg, (int)c,
usr/src/uts/sun/io/sbusmem.c
368
ddi_unmap_regs(dip, 0, ®, uio->uio_offset, (off_t)msize);
usr/src/uts/sun/sys/socalreg.h
127
} reg;
usr/src/uts/sun/sys/socalreg.h
183
} reg;
usr/src/uts/sun/sys/socalreg.h
208
} reg;
usr/src/uts/sun/sys/socalreg.h
59
} reg;
usr/src/uts/sun/sys/socalreg.h
99
} reg;
usr/src/uts/sun/sys/zsdev.h
102
zs->zs_wreg[reg] = val; \
usr/src/uts/sun/sys/zsdev.h
104
#define SCC_WRITEB(reg, val) { \
usr/src/uts/sun/sys/zsdev.h
106
((uintptr_t)zs->zs_addr & ~ZSOFF))->zscc_control = reg; \
usr/src/uts/sun/sys/zsdev.h
111
zs->zs_wreg[reg] = val; \
usr/src/uts/sun/sys/zsdev.h
113
#define SCC_WRITE(reg, val) { \
usr/src/uts/sun/sys/zsdev.h
114
zs->zs_addr->zscc_control = reg; \
usr/src/uts/sun/sys/zsdev.h
118
zs->zs_wreg[reg] = val; \
usr/src/uts/sun/sys/zsdev.h
121
#define SCC_READA(reg, var) { \
usr/src/uts/sun/sys/zsdev.h
123
((uintptr_t)zs->zs_addr | ZSOFF))->zscc_control = reg; \
usr/src/uts/sun/sys/zsdev.h
129
#define SCC_READB(reg, var) { \
usr/src/uts/sun/sys/zsdev.h
131
((uintptr_t)zs->zs_addr & ~ZSOFF))->zscc_control = reg; \
usr/src/uts/sun/sys/zsdev.h
137
#define SCC_READ(reg, var) { \
usr/src/uts/sun/sys/zsdev.h
140
tmp->zscc_control = reg; \
usr/src/uts/sun/sys/zsdev.h
146
#define SCC_BIS(reg, val) { \
usr/src/uts/sun/sys/zsdev.h
147
zs->zs_addr->zscc_control = reg; \
usr/src/uts/sun/sys/zsdev.h
149
zs->zs_addr->zscc_control = zs->zs_wreg[reg] |= val; \
usr/src/uts/sun/sys/zsdev.h
153
#define SCC_BIC(reg, val) { \
usr/src/uts/sun/sys/zsdev.h
154
zs->zs_addr->zscc_control = reg; \
usr/src/uts/sun/sys/zsdev.h
156
zs->zs_addr->zscc_control = zs->zs_wreg[reg] &= ~val; \
usr/src/uts/sun/sys/zsdev.h
95
#define SCC_WRITEA(reg, val) { \
usr/src/uts/sun/sys/zsdev.h
97
((uintptr_t)zs->zs_addr | ZSOFF))->zscc_control = reg; \
usr/src/uts/sun4/io/efcode/fcpci.c
1000
reg = (p.pci_phys_hi & PCI_REG_REG_M) |
usr/src/uts/sun4/io/efcode/fcpci.c
1018
if ((reg & (len - 1)) != 0)
usr/src/uts/sun4/io/efcode/fcpci.c
1060
v = virt + reg;
usr/src/uts/sun4/io/efcode/fcpci.c
830
int error, reg, flags = 0;
usr/src/uts/sun4/io/efcode/fcpci.c
869
reg = (p.pci_phys_hi & PCI_REG_REG_M) |
usr/src/uts/sun4/io/efcode/fcpci.c
887
if ((reg & (len - 1)) != 0)
usr/src/uts/sun4/io/efcode/fcpci.c
929
v = virt + reg;
usr/src/uts/sun4/io/efcode/fcpci.c
965
int error, reg, flags = 0;
usr/src/uts/sun4/io/pcicfg.c
1867
pci_regspec_t *reg;
usr/src/uts/sun4/io/pcicfg.c
1969
DDI_PROP_DONTPASS, "reg", (caddr_t)®,
usr/src/uts/sun4/io/pcicfg.c
1979
if ((reg[i].pci_size_low != 0)||
usr/src/uts/sun4/io/pcicfg.c
1980
(reg[i].pci_size_hi != 0)) {
usr/src/uts/sun4/io/pcicfg.c
1982
offset = PCI_REG_REG_G(reg[i].pci_phys_hi);
usr/src/uts/sun4/io/pcicfg.c
1984
switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) {
usr/src/uts/sun4/io/pcicfg.c
1988
reg[i].pci_size_low, &mem_answer);
usr/src/uts/sun4/io/pcicfg.c
1997
reg[i].pci_phys_low = PCICFG_HIADDR(mem_answer);
usr/src/uts/sun4/io/pcicfg.c
1998
reg[i].pci_phys_mid =
usr/src/uts/sun4/io/pcicfg.c
2007
reg[i].pci_size_low, &mem_answer);
usr/src/uts/sun4/io/pcicfg.c
2015
reg[i].pci_phys_low = (uint32_t)mem_answer;
usr/src/uts/sun4/io/pcicfg.c
2022
reg[i].pci_size_low, &io_answer);
usr/src/uts/sun4/io/pcicfg.c
2029
reg[i].pci_phys_low = io_answer;
usr/src/uts/sun4/io/pcicfg.c
2034
kmem_free(reg, length);
usr/src/uts/sun4/io/pcicfg.c
2045
®[i]) != PCICFG_SUCCESS) {
usr/src/uts/sun4/io/pcicfg.c
2046
kmem_free(reg, length);
usr/src/uts/sun4/io/pcicfg.c
2061
kmem_free((caddr_t)reg, length);
usr/src/uts/sun4/io/pcicfg.c
2070
pci_regspec_t *reg;
usr/src/uts/sun4/io/pcicfg.c
2085
DDI_PROP_DONTPASS, "reg", (caddr_t)®,
usr/src/uts/sun4/io/pcicfg.c
2096
kmem_free((caddr_t)reg, length);
usr/src/uts/sun4/io/pcicfg.c
2124
if ((reg[i].pci_size_low != 0)||
usr/src/uts/sun4/io/pcicfg.c
2125
(reg[i].pci_size_hi != 0)) {
usr/src/uts/sun4/io/pcicfg.c
2127
offset = PCI_REG_REG_G(reg[i].pci_phys_hi);
usr/src/uts/sun4/io/pcicfg.c
2128
request.ra_len = reg[i].pci_size_low;
usr/src/uts/sun4/io/pcicfg.c
2130
switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) {
usr/src/uts/sun4/io/pcicfg.c
2139
kmem_free(reg, length);
usr/src/uts/sun4/io/pcicfg.c
2155
reg[i].pci_phys_low = PCICFG_LOADDR(answer);
usr/src/uts/sun4/io/pcicfg.c
2156
reg[i].pci_phys_mid = PCICFG_HIADDR(answer);
usr/src/uts/sun4/io/pcicfg.c
2160
reg[i].pci_phys_hi ^=
usr/src/uts/sun4/io/pcicfg.c
2172
kmem_free(reg, length);
usr/src/uts/sun4/io/pcicfg.c
2184
reg[i].pci_phys_low = PCICFG_LOADDR(answer);
usr/src/uts/sun4/io/pcicfg.c
2195
kmem_free(reg, length);
usr/src/uts/sun4/io/pcicfg.c
2206
reg[i].pci_phys_low = PCICFG_LOADDR(answer);
usr/src/uts/sun4/io/pcicfg.c
2211
kmem_free(reg, length);
usr/src/uts/sun4/io/pcicfg.c
2222
®[i]) != PCICFG_SUCCESS) {
usr/src/uts/sun4/io/pcicfg.c
2223
kmem_free(reg, length);
usr/src/uts/sun4/io/pcicfg.c
2231
kmem_free(reg, length);
usr/src/uts/sun4/io/pcicfg.c
3175
pci_regspec_t *reg;
usr/src/uts/sun4/io/pcicfg.c
3183
dip, DDI_PROP_DONTPASS, "reg", (caddr_t)®, &rlen);
usr/src/uts/sun4/io/pcicfg.c
3206
hiword = PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi),
usr/src/uts/sun4/io/pcicfg.c
3207
PCI_REG_DEV_G(reg->pci_phys_hi),
usr/src/uts/sun4/io/pcicfg.c
3208
PCI_REG_FUNC_G(reg->pci_phys_hi), reg_offset);
usr/src/uts/sun4/io/pcicfg.c
3234
bcopy(reg, newreg, rlen);
usr/src/uts/sun4/io/pcicfg.c
3245
kmem_free((caddr_t)reg, rlen);
usr/src/uts/sun4/io/pcicfg.c
3302
pci_regspec_t *reg;
usr/src/uts/sun4/io/pcicfg.c
3308
"reg", (caddr_t)®, &rlen);
usr/src/uts/sun4/io/pcicfg.c
3330
hiword = PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi),
usr/src/uts/sun4/io/pcicfg.c
3331
PCI_REG_DEV_G(reg->pci_phys_hi),
usr/src/uts/sun4/io/pcicfg.c
3332
PCI_REG_FUNC_G(reg->pci_phys_hi), reg_offset);
usr/src/uts/sun4/io/pcicfg.c
3369
kmem_free((caddr_t)reg, rlen);
usr/src/uts/sun4/io/pcicfg.c
5387
pci_regspec_t reg;
usr/src/uts/sun4/io/pcicfg.c
5435
reg.pci_phys_mid = reg.pci_size_hi = 0;
usr/src/uts/sun4/io/pcicfg.c
5437
reg.pci_phys_hi = (PCI_REG_REL_M | PCI_ADDR_IO);
usr/src/uts/sun4/io/pcicfg.c
5438
reg.pci_phys_low = io_assigned;
usr/src/uts/sun4/io/pcicfg.c
5439
reg.pci_size_low = io_size;
usr/src/uts/sun4/io/pcicfg.c
5440
if (pcicfg_update_available_prop(new_child, ®)) {
usr/src/uts/sun4/io/pcicfg.c
5447
reg.pci_phys_hi = (PCI_REG_REL_M | PCI_ADDR_MEM32);
usr/src/uts/sun4/io/pcicfg.c
5448
reg.pci_phys_low = mem_assigned;
usr/src/uts/sun4/io/pcicfg.c
5449
reg.pci_size_low = mem_size;
usr/src/uts/sun4/io/pcicfg.c
5450
if (pcicfg_update_available_prop(new_child, ®)) {
usr/src/uts/sun4/io/pcicfg.c
5618
pci_regspec_t *reg;
usr/src/uts/sun4/io/pcicfg.c
5635
dip, DDI_PROP_DONTPASS, "reg", (caddr_t)®, &rlen);
usr/src/uts/sun4/io/pcicfg.c
5663
if (pcicfg_map_phys(dip, reg, &virt, &attr, handle)
usr/src/uts/sun4/io/pcicfg.c
5670
kmem_free((caddr_t)reg, rlen);
usr/src/uts/sun4/io/pcicfg.c
5730
pcicfg_unmap_phys(handle, reg);
usr/src/uts/sun4/io/pcicfg.c
5733
kmem_free((caddr_t)reg, rlen);
usr/src/uts/sun4/io/pcicfg.c
5749
int reg[10] = { PCI_ADDR_CONFIG, 0, 0, 0, 0};
usr/src/uts/sun4/io/pcicfg.c
5751
reg[0] = PCICFG_MAKE_REG_HIGH(bus, device, func, 0);
usr/src/uts/sun4/io/pcicfg.c
5754
"reg", reg, 5));
usr/src/uts/sun4/io/pcicfg.c
5760
pci_regspec_t *reg;
usr/src/uts/sun4/io/pcicfg.c
5766
DDI_PROP_DONTPASS, "assigned-addresses", (caddr_t)®,
usr/src/uts/sun4/io/pcicfg.c
5775
reg[i].pci_size_low, reg[i].pci_phys_low,
usr/src/uts/sun4/io/pcicfg.c
5776
reg[i].pci_phys_mid, reg[i].pci_phys_hi);
usr/src/uts/sun4/io/pcicfg.c
5781
kmem_free((caddr_t)reg, length);
usr/src/uts/sun4/io/pcicfg.c
6201
pci_regspec_t *assigned, *reg;
usr/src/uts/sun4/io/pcicfg.c
6208
DDI_PROP_DONTPASS, "reg", (caddr_t)®,
usr/src/uts/sun4/io/pcicfg.c
6236
alloc_size = reg[i].pci_size_low;
usr/src/uts/sun4/io/pcicfg.c
6238
if (assigned[j].pci_phys_hi == reg[i].pci_phys_hi) {
usr/src/uts/sun4/io/pcicfg.c
6244
reg[i].pci_phys_hi);
usr/src/uts/sun4/io/pcicfg.c
6246
if (reg[i].pci_size_low >
usr/src/uts/sun4/io/pcicfg.c
6256
reg[i].pci_size_low);
usr/src/uts/sun4/io/pcicfg.c
6269
reg[i].pci_size_low);
usr/src/uts/sun4/io/pcicfg.c
6280
PCI_REG_BDFR_G(reg[i].pci_phys_hi)) {
usr/src/uts/sun4/io/pcicfg.c
6285
reg[i].pci_phys_hi);
usr/src/uts/sun4/io/pcicfg.c
6291
PCI_REG_ADDR_G(reg[i].pci_phys_hi)) {
usr/src/uts/sun4/io/pcicfg.c
6295
" on %s\n", reg[i].pci_phys_hi,
usr/src/uts/sun4/io/pcicfg.c
6309
alloc_size = MAX(reg[i].pci_size_low,
usr/src/uts/sun4/io/pcicfg.c
6324
reg[i].pci_phys_hi);
usr/src/uts/sun4/io/pcicfg.c
6326
reg[i].pci_size_low = alloc_size;
usr/src/uts/sun4/io/pcicfg.c
6327
if (pcicfg_alloc_resource(dip, reg[i])) {
usr/src/uts/sun4/io/pcicfg.c
6335
kmem_free((caddr_t)reg, reg_len);
usr/src/uts/sun4/io/pcicfg.c
6346
kmem_free((caddr_t)reg, reg_len);
usr/src/uts/sun4/sys/ebus.h
120
pci_regspec_t *reg;
usr/src/uts/sun4u/cpu/spitfire.c
2829
volatile uint64_t reg;
usr/src/uts/sun4u/cpu/spitfire.c
2840
reg = lddphysio(HB_ESTAR_MODE);
usr/src/uts/sun4u/cpu/spitfire.c
2841
cur_mask = reg & HB_ECLK_MASK;
usr/src/uts/sun4u/cpu/us3_cheetah.c
562
uint64_t reg;
usr/src/uts/sun4u/cpu/us3_cheetah.c
568
reg = get_safari_config();
usr/src/uts/sun4u/cpu/us3_cheetah.c
569
reg &= ~SAFARI_CONFIG_ECLK_MASK;
usr/src/uts/sun4u/cpu/us3_cheetah.c
570
reg |= bceclk->mask;
usr/src/uts/sun4u/cpu/us3_cheetah.c
571
set_safari_config(reg);
usr/src/uts/sun4u/cpu/us3_cheetahplus.c
766
uint64_t reg;
usr/src/uts/sun4u/cpu/us3_cheetahplus.c
772
reg = get_safari_config();
usr/src/uts/sun4u/cpu/us3_cheetahplus.c
773
reg &= ~SAFARI_CONFIG_ECLK_MASK;
usr/src/uts/sun4u/cpu/us3_cheetahplus.c
774
reg |= bceclk->mask;
usr/src/uts/sun4u/cpu/us3_cheetahplus.c
775
set_safari_config(reg);
usr/src/uts/sun4u/cpu/us3_jalapeno.c
703
uint64_t reg;
usr/src/uts/sun4u/cpu/us3_jalapeno.c
764
reg = get_jbus_config();
usr/src/uts/sun4u/cpu/us3_jalapeno.c
765
oldreg = reg;
usr/src/uts/sun4u/cpu/us3_jalapeno.c
766
reg &= ~JBUS_CONFIG_ECLK_MASK;
usr/src/uts/sun4u/cpu/us3_jalapeno.c
767
reg |= bceclk->mask;
usr/src/uts/sun4u/cpu/us3_jalapeno.c
768
set_jbus_config(reg);
usr/src/uts/sun4u/daktari/io/hpc3130_dak.c
1150
hpc3130_rw(i2c_client_hdl_t handle, uint8_t reg,
usr/src/uts/sun4u/daktari/io/hpc3130_dak.c
1171
"no transfer structure 0x%x", reg));
usr/src/uts/sun4u/daktari/io/hpc3130_dak.c
1174
i2c_tran_pointer->i2c_wbuf[0] = reg;
usr/src/uts/sun4u/daktari/io/hpc3130_dak.c
1185
"no I2C data transfered 0x%x", reg));
usr/src/uts/sun4u/daktari/io/hpc3130_dak.c
1225
while (tp->reg != HPC3130_NO_REGISTER) {
usr/src/uts/sun4u/daktari/io/hpc3130_dak.c
1226
if (hpc3130_write(handle, tp->reg, slot,
usr/src/uts/sun4u/daktari/io/hpc3130_dak.c
334
hpc3130_get(intptr_t arg, int reg, hpc3130_unit_t *unitp, int mode)
usr/src/uts/sun4u/daktari/io/hpc3130_dak.c
353
i2c_tran_pointer->i2c_wbuf[0] = (uchar_t)reg;
usr/src/uts/sun4u/daktari/io/hpc3130_dak.c
377
hpc3130_set(intptr_t arg, int reg, hpc3130_unit_t *unitp, int mode)
usr/src/uts/sun4u/daktari/io/hpc3130_dak.c
405
i2c_tran_pointer->i2c_wbuf[0] = (uchar_t)reg;
usr/src/uts/sun4u/daktari/io/hpc3130_dak.c
72
uint8_t reg;
usr/src/uts/sun4u/excalibur/io/xcalppm.c
392
uint8_t reg;
usr/src/uts/sun4u/excalibur/io/xcalppm.c
399
reg = XCPPM_GET8(unitp->hndls.gpio_data_ports,
usr/src/uts/sun4u/excalibur/io/xcalppm.c
402
reg &= ~LED;
usr/src/uts/sun4u/excalibur/io/xcalppm.c
404
reg |= LED;
usr/src/uts/sun4u/excalibur/io/xcalppm.c
406
unitp->regs.gpio_port1_data, reg);
usr/src/uts/sun4u/grover/io/grfans.c
447
uint8_t reg;
usr/src/uts/sun4u/grover/io/grfans.c
451
reg = ddi_get8(unitp->cpufan_rhandle,
usr/src/uts/sun4u/grover/io/grfans.c
453
reg = (reg & ~CPU_FAN_MASK) | reg_value;
usr/src/uts/sun4u/grover/io/grfans.c
455
unitp->cpufan_reg, reg);
usr/src/uts/sun4u/io/gptwo_cpu.c
259
gptwo_regspec_t reg;
usr/src/uts/sun4u/io/gptwo_cpu.c
283
reg.gptwo_phys_hi = 0x400 | (portid >> 9);
usr/src/uts/sun4u/io/gptwo_cpu.c
284
reg.gptwo_phys_low = (portid << 23);
usr/src/uts/sun4u/io/gptwo_cpu.c
285
reg.gptwo_size_hi = 0;
usr/src/uts/sun4u/io/gptwo_cpu.c
286
reg.gptwo_size_low = 0x10000;
usr/src/uts/sun4u/io/gptwo_cpu.c
289
new_child, "reg", (int *)®,
usr/src/uts/sun4u/io/gptwo_cpu.c
465
gptwo_regspec_t reg;
usr/src/uts/sun4u/io/gptwo_cpu.c
510
reg.gptwo_phys_hi = 0x400 | (portid >> 9);
usr/src/uts/sun4u/io/gptwo_cpu.c
511
reg.gptwo_phys_low = (portid << 23);
usr/src/uts/sun4u/io/gptwo_cpu.c
512
reg.gptwo_size_hi = 0;
usr/src/uts/sun4u/io/gptwo_cpu.c
513
reg.gptwo_size_low = 0x10000;
usr/src/uts/sun4u/io/gptwo_cpu.c
516
new_child, "reg", (int *)®,
usr/src/uts/sun4u/io/gptwo_cpu.c
903
gptwo_regspec_t reg;
usr/src/uts/sun4u/io/gptwo_cpu.c
947
reg.gptwo_phys_hi = 0x400 | (portid >> 9);
usr/src/uts/sun4u/io/gptwo_cpu.c
948
reg.gptwo_phys_low = (portid << 23) | 0x400000;
usr/src/uts/sun4u/io/gptwo_cpu.c
949
reg.gptwo_size_hi = 0;
usr/src/uts/sun4u/io/gptwo_cpu.c
950
reg.gptwo_size_low = 0x48;
usr/src/uts/sun4u/io/gptwo_cpu.c
953
new_child, "reg", (int *)®,
usr/src/uts/sun4u/io/i2c/clients/adm1026.c
382
adm1026_get8(adm1026_unit_t *unitp, uint8_t reg, uint8_t *val)
usr/src/uts/sun4u/io/i2c/clients/adm1026.c
393
i2c_tran_pointer->i2c_wbuf[0] = (uchar_t)reg;
usr/src/uts/sun4u/io/i2c/clients/adm1026.c
397
"adm1026_get8: I2C_WR_RD reg=0x%x failed", reg));
usr/src/uts/sun4u/io/i2c/clients/adm1026.c
401
reg, *val));
usr/src/uts/sun4u/io/i2c/clients/adm1026.c
409
adm1026_put8(adm1026_unit_t *unitp, uint8_t reg, uint8_t val)
usr/src/uts/sun4u/io/i2c/clients/adm1026.c
414
D1CMN_ERR((CE_WARN, "adm1026_put8: reg=%02x, val=%02x\n", reg, val));
usr/src/uts/sun4u/io/i2c/clients/adm1026.c
422
i2c_tran_pointer->i2c_wbuf[0] = reg;
usr/src/uts/sun4u/io/i2c/clients/adm1026.c
440
adm1026_send8(adm1026_unit_t *unitp, uint8_t reg, uint8_t reg_val,
usr/src/uts/sun4u/io/i2c/clients/adm1026.c
446
if ((err = adm1026_get8(unitp, reg, &val)) != I2C_SUCCESS)
usr/src/uts/sun4u/io/i2c/clients/adm1026.c
451
return (adm1026_put8(unitp, reg, val));
usr/src/uts/sun4u/io/i2c/clients/adm1026.c
81
static int adm1026_get8(adm1026_unit_t *unitp, uint8_t reg, uint8_t *val);
usr/src/uts/sun4u/io/i2c/clients/adm1026.c
82
static int adm1026_put8(adm1026_unit_t *unitp, uint8_t reg, uint8_t val);
usr/src/uts/sun4u/io/i2c/clients/adm1031.c
639
temperatures[fcn_inst].reg;
usr/src/uts/sun4u/io/i2c/clients/adm1031.c
660
fans[fcn_inst].reg;
usr/src/uts/sun4u/io/i2c/clients/lm75.c
220
lm75_get16(intptr_t arg, int reg, struct lm75_unit *unitp, int mode)
usr/src/uts/sun4u/io/i2c/clients/lm75.c
236
i2c_tran_pointer->i2c_wbuf[0] = (uchar_t)reg;
usr/src/uts/sun4u/io/i2c/clients/lm75.c
273
lm75_set16(intptr_t arg, int reg, struct lm75_unit *unitp, int mode)
usr/src/uts/sun4u/io/i2c/clients/lm75.c
305
i2c_tran_pointer->i2c_wbuf[0] = (uchar_t)reg;
usr/src/uts/sun4u/io/i2c/clients/max1617.c
559
get_temp_limit(struct max1617_unit *unitp, uchar_t reg, caddr_t arg, int mode)
usr/src/uts/sun4u/io/i2c/clients/max1617.c
568
i2ctp->i2c_wbuf[0] = reg;
usr/src/uts/sun4u/io/i2c/clients/max1617.c
597
uchar_t reg;
usr/src/uts/sun4u/io/i2c/clients/max1617.c
632
reg = MAX1617_LOCAL_TEMP_REG;
usr/src/uts/sun4u/io/i2c/clients/max1617.c
635
reg = MAX1617_REMOTE_TEMP_REG;
usr/src/uts/sun4u/io/i2c/clients/max1617.c
646
i2ctp->i2c_wbuf[0] = reg;
usr/src/uts/sun4u/io/i2c/clients/pca9556.c
185
uint8_t reg, reg_num = 0;
usr/src/uts/sun4u/io/i2c/clients/pca9556.c
219
reg = PCA9555_OUTPUT_REG;
usr/src/uts/sun4u/io/i2c/clients/pca9556.c
221
reg = PCA9556_OUTPUT_REG;
usr/src/uts/sun4u/io/i2c/clients/pca9556.c
224
pcap->pca9556_transfer->i2c_wbuf[0] = reg + i;
usr/src/uts/sun4u/io/i2c/clients/pca9556.c
235
reg = reg + reg_offset;
usr/src/uts/sun4u/io/i2c/clients/pca9556.c
422
uint8_t reg, reg_num = 0;
usr/src/uts/sun4u/io/i2c/clients/pca9556.c
476
reg = PCA9555_OUTPUT_REG;
usr/src/uts/sun4u/io/i2c/clients/pca9556.c
478
reg = PCA9556_OUTPUT_REG;
usr/src/uts/sun4u/io/i2c/clients/pca9556.c
487
pcap->pca9556_transfer->i2c_wbuf[0] = reg + i;
usr/src/uts/sun4u/io/i2c/clients/pca9556.c
500
reg = reg + reg_offset;
usr/src/uts/sun4u/io/i2c/clients/pcf8591.c
235
uchar_t control, reg;
usr/src/uts/sun4u/io/i2c/clients/pcf8591.c
269
reg = (uchar_t)port;
usr/src/uts/sun4u/io/i2c/clients/pcf8591.c
270
if ((reg == 0x02) && (ipmode == PCF8591_2DIFF)) {
usr/src/uts/sun4u/io/i2c/clients/pcf8591.c
279
if ((reg == 0x03) && (ipmode != PCF8591_4SINGLE)) {
usr/src/uts/sun4u/io/i2c/clients/pcf8591.c
289
(autoincr << PCF8591_AUTOINCR_SHIFT) | reg);
usr/src/uts/sun4u/io/i2c/clients/pcf8591.c
318
reg = (uchar_t)port;
usr/src/uts/sun4u/io/i2c/clients/pcf8591.c
348
(autoincr << PCF8591_AUTOINCR_SHIFT) | reg);
usr/src/uts/sun4u/io/i2c/clients/pic16f819.c
146
pic16f819_get(struct pic16f819_unit *unitp, int reg, uchar_t *byte, int flags)
usr/src/uts/sun4u/io/i2c/clients/pic16f819.c
158
i2c_tran_pointer->i2c_wbuf[0] = (uchar_t)reg;
usr/src/uts/sun4u/io/i2c/clients/pic16f819.c
162
unitp->pic16f819_name, reg));
usr/src/uts/sun4u/io/i2c/clients/pic16f819.c
172
pic16f819_set(struct pic16f819_unit *unitp, int reg, uchar_t byte)
usr/src/uts/sun4u/io/i2c/clients/pic16f819.c
186
i2c_tran_pointer->i2c_wbuf[0] = (uchar_t)reg;
usr/src/uts/sun4u/io/i2c/clients/pic16f819.c
189
unitp->pic16f819_name, reg, byte));
usr/src/uts/sun4u/io/i2c/clients/ssc050.c
254
ssc050_get(struct ssc050_unit *unitp, int reg, uchar_t *byte, int flags)
usr/src/uts/sun4u/io/i2c/clients/ssc050.c
266
i2c_tran_pointer->i2c_wbuf[0] = (uchar_t)reg;
usr/src/uts/sun4u/io/i2c/clients/ssc050.c
270
unitp->name, reg));
usr/src/uts/sun4u/io/i2c/clients/ssc050.c
280
ssc050_set(struct ssc050_unit *unitp, int reg, uchar_t byte)
usr/src/uts/sun4u/io/i2c/clients/ssc050.c
294
i2c_tran_pointer->i2c_wbuf[0] = (uchar_t)reg;
usr/src/uts/sun4u/io/i2c/clients/ssc050.c
296
D1CMN_ERR((CE_NOTE, "%s: set reg %x to %x", unitp->name, reg, byte));
usr/src/uts/sun4u/io/i2c/clients/ssc050.c
320
uchar_t reg, val8;
usr/src/uts/sun4u/io/i2c/clients/ssc050.c
352
reg = SSC050_DATADIRECTION_REG(port);
usr/src/uts/sun4u/io/i2c/clients/ssc050.c
354
err = ssc050_get(unitp, reg, &val8, I2C_SLEEP);
usr/src/uts/sun4u/io/i2c/clients/ssc050.c
363
err = ssc050_set(unitp, reg,
usr/src/uts/sun4u/io/i2c/clients/ssc050.c
390
reg = SSC050_DATADIRECTION_REG(port);
usr/src/uts/sun4u/io/i2c/clients/ssc050.c
392
err = ssc050_get(unitp, reg, &val8, I2C_SLEEP);
usr/src/uts/sun4u/io/i2c/clients/ssc050.c
406
err = ssc050_set(unitp, reg, val8);
usr/src/uts/sun4u/io/i2c/clients/ssc050.c
485
reg = (uchar_t)SSC050_BIT_REG(port, ioctl_bit.bit_num);
usr/src/uts/sun4u/io/i2c/clients/ssc050.c
486
D3CMN_ERR((CE_NOTE, "%s: reg = %x", unitp->name, reg));
usr/src/uts/sun4u/io/i2c/clients/ssc050.c
489
err = ssc050_get(unitp, reg, &val8, I2C_SLEEP);
usr/src/uts/sun4u/io/i2c/clients/ssc050.c
499
err = ssc050_set(unitp, reg,
usr/src/uts/sun4u/io/i2c/clients/ssc050.c
508
err = ssc050_get(unitp, reg, &val8, I2C_SLEEP);
usr/src/uts/sun4u/io/i2c/clients/ssc050.c
533
reg = (uchar_t)SSC050_BIT_REG(port, ioctl_bit.bit_num);
usr/src/uts/sun4u/io/i2c/clients/ssc050.c
534
D3CMN_ERR((CE_NOTE, "%s: reg = %x", unitp->name, reg));
usr/src/uts/sun4u/io/i2c/clients/ssc050.c
537
err = ssc050_set(unitp, reg, val8);
usr/src/uts/sun4u/io/i2c/clients/ssc050.c
691
int reg = (uchar_t)SSC050_BIT_REG(port, bit);
usr/src/uts/sun4u/io/i2c/clients/ssc050.c
701
return (ssc050_get(unitp, reg, rval, flags));
usr/src/uts/sun4u/io/i2c/clients/ssc100.c
257
ssc100_get_reg(struct ssc100_unit *unitp, uchar_t *byte, uchar_t reg)
usr/src/uts/sun4u/io/i2c/clients/ssc100.c
261
err = ssc100_common(unitp, byte, reg, I2C_WR_RD);
usr/src/uts/sun4u/io/i2c/nexus/smbus.c
71
static void smbus_put(smbus_t *smbus, uint8_t reg, uint8_t data, uint8_t flags);
usr/src/uts/sun4u/io/i2c/nexus/smbus.c
72
static uint8_t smbus_get(smbus_t *smbus, uint8_t reg);
usr/src/uts/sun4u/io/i2c/nexus/smbus.c
734
smbus_put(smbus_t *smbus, uint8_t reg, uint8_t data, uint8_t flags)
usr/src/uts/sun4u/io/i2c/nexus/smbus.c
741
ddi_put8(hp, ®_addr[reg], data);
usr/src/uts/sun4u/io/i2c/nexus/smbus.c
744
®_addr[reg], data));
usr/src/uts/sun4u/io/i2c/nexus/smbus.c
756
smbus_get(smbus_t *smbus, uint8_t reg)
usr/src/uts/sun4u/io/i2c/nexus/smbus.c
763
data = ddi_get8(hp, ®addr[reg]);
usr/src/uts/sun4u/io/iocache.c
186
uint64_t reg;
usr/src/uts/sun4u/io/iocache.c
195
reg = *reg_addr;
usr/src/uts/sun4u/io/iocache.c
199
hi = (uint_t)(reg >> 32);
usr/src/uts/sun4u/io/iocache.c
200
lo = (uint_t)(reg & 0xffffffff);
usr/src/uts/sun4u/io/iocache.c
208
if (reg & STR_PG_VALID) {
usr/src/uts/sun4u/io/iocache.c
209
ioaddr = (uint_t)reg << STR_PG_SHIFT;
usr/src/uts/sun4u/io/mc-us3.c
151
static int mlayout_add(int mc_id, int bank_no, uint64_t reg, void *dimminfop);
usr/src/uts/sun4u/io/mc-us3.c
1577
mlayout_add(int mc_id, int bank_no, uint64_t reg, void *dimminfop)
usr/src/uts/sun4u/io/mc-us3.c
1603
mcreg.madreg = reg;
usr/src/uts/sun4u/io/mc-us3.c
1606
"%d, reg 0x%lx\n", mc_id, bank_no, reg));
usr/src/uts/sun4u/io/pci/db21554.c
1010
DDI_PROP_DONTPASS, "reg", (caddr_t)®,
usr/src/uts/sun4u/io/pci/db21554.c
1020
offset = PCI_REG_REG_G(reg[i].pci_phys_hi);
usr/src/uts/sun4u/io/pci/db21554.c
1022
(reg[i].pci_size_low > DB_CSR_SIZE))
usr/src/uts/sun4u/io/pci/db21554.c
1047
kmem_free(reg, length);
usr/src/uts/sun4u/io/pci/db21554.c
940
pci_regspec_t *reg;
usr/src/uts/sun4u/io/pci/pci_cb.c
101
reg = ib_get_map_reg(mondo, cpu_id);
usr/src/uts/sun4u/io/pci/pci_cb.c
102
stdphysio(pa, reg);
usr/src/uts/sun4u/io/pci/pci_cb.c
113
DEBUG2(DBG_CB|DBG_CONT, NULL, "\tPA=%016llx data=%016llx\n", pa, reg);
usr/src/uts/sun4u/io/pci/pci_cb.c
93
uint64_t reg, pa;
usr/src/uts/sun4u/io/pci/pcipsy.c
409
ib_map_reg_get_cpu(volatile uint64_t reg)
usr/src/uts/sun4u/io/pci/pcipsy.c
411
return ((reg & COMMON_INTR_MAP_REG_TID) >>
usr/src/uts/sun4u/io/pci/pcisch.c
569
ib_map_reg_get_cpu(volatile uint64_t reg)
usr/src/uts/sun4u/io/pci/pcisch.c
571
return (((reg & COMMON_INTR_MAP_REG_TID) >>
usr/src/uts/sun4u/io/pci/pcisch.c
573
((reg & SCHIZO_INTR_MAP_REG_NID) >>
usr/src/uts/sun4u/io/px/px_csr.h
109
#define BIT_TST(reg, bitno) (reg & (1ull << bitno))
usr/src/uts/sun4u/io/px/px_hlib.c
2703
pec_config_state_regs[i].reg);
usr/src/uts/sun4u/io/px/px_hlib.c
2777
CSR_XS((caddr_t)dev_hdl, pec_config_state_regs[i].reg,
usr/src/uts/sun4u/io/px/px_hlib.c
2990
volatile uint64_t reg;
usr/src/uts/sun4u/io/px/px_hlib.c
2992
reg = CSR_XR(csr_base, TLU_PME_TURN_OFF_GENERATE);
usr/src/uts/sun4u/io/px/px_hlib.c
2994
if (reg & (1ull << TLU_PME_TURN_OFF_GENERATE_PTO)) {
usr/src/uts/sun4u/io/px/px_hlib.c
2996
"tlu_pme_turn_off_generate = %x\n", reg);
usr/src/uts/sun4u/io/px/px_hlib.c
3001
reg |= (1ull << TLU_PME_TURN_OFF_GENERATE_PTO);
usr/src/uts/sun4u/io/px/px_hlib.c
3002
CSR_XS(csr_base, TLU_PME_TURN_OFF_GENERATE, reg);
usr/src/uts/sun4u/io/px/px_hlib.c
3035
volatile uint64_t reg;
usr/src/uts/sun4u/io/px/px_hlib.c
3037
reg = CSR_XR(csr_base, TLU_CONTROL);
usr/src/uts/sun4u/io/px/px_hlib.c
3038
if (!(reg & (1ull << TLU_REMAIN_DETECT_QUIET))) {
usr/src/uts/sun4u/io/px/px_hlib.c
3050
reg = CSR_XR(csr_base, TLU_CONTROL);
usr/src/uts/sun4u/io/px/px_hlib.c
3051
reg &= ~(1ull << TLU_REMAIN_DETECT_QUIET);
usr/src/uts/sun4u/io/px/px_hlib.c
3052
CSR_XS(csr_base, TLU_CONTROL, reg);
usr/src/uts/sun4u/io/px/px_hlib.c
3070
volatile uint64_t reg;
usr/src/uts/sun4u/io/px/px_hlib.c
3077
reg = CSR_XR(csr_base, ILU_ERROR_LOG_ENABLE);
usr/src/uts/sun4u/io/px/px_hlib.c
3078
if (!(reg & (1ull << ILU_ERROR_LOG_ENABLE_SPARE3))) {
usr/src/uts/sun4u/io/px/px_hlib.c
3091
reg = CSR_XR(csr_base, TLU_SLOT_STATUS);
usr/src/uts/sun4u/io/px/px_hlib.c
3092
if (!(reg & (1ull << TLU_SLOT_STATUS_PSD)) ||
usr/src/uts/sun4u/io/px/px_hlib.c
3093
(reg & (1ull << TLU_SLOT_STATUS_MRLS))) {
usr/src/uts/sun4u/io/px/px_hlib.c
3095
reg);
usr/src/uts/sun4u/io/px/px_hlib.c
3162
reg = CSR_XR(csr_base, DLU_LINK_LAYER_STATUS);
usr/src/uts/sun4u/io/px/px_hlib.c
3164
if ((((reg >> DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS) &
usr/src/uts/sun4u/io/px/px_hlib.c
3167
(reg & (1ull << DLU_LINK_LAYER_STATUS_DLUP_STS)) &&
usr/src/uts/sun4u/io/px/px_hlib.c
3168
((reg &
usr/src/uts/sun4u/io/px/px_hlib.c
3195
reg = CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE);
usr/src/uts/sun4u/io/px/px_hlib.c
3197
reg |= 1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_P;
usr/src/uts/sun4u/io/px/px_hlib.c
3199
reg |= 1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_P;
usr/src/uts/sun4u/io/px/px_hlib.c
3201
reg |= 1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_S;
usr/src/uts/sun4u/io/px/px_hlib.c
3203
reg |= 1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_S;
usr/src/uts/sun4u/io/px/px_hlib.c
3204
CSR_XS(csr_base, TLU_OTHER_EVENT_LOG_ENABLE, reg);
usr/src/uts/sun4u/io/px/px_hlib.c
3210
reg = CSR_XR(csr_base, TLU_SLOT_CAPABILITIES);
usr/src/uts/sun4u/io/px/px_hlib.c
3211
reg &= ~(TLU_SLOT_CAPABILITIES_SPLS_MASK <<
usr/src/uts/sun4u/io/px/px_hlib.c
3213
reg &= ~(TLU_SLOT_CAPABILITIES_SPLV_MASK <<
usr/src/uts/sun4u/io/px/px_hlib.c
3215
reg |= (0x19 << TLU_SLOT_CAPABILITIES_SPLV);
usr/src/uts/sun4u/io/px/px_hlib.c
3216
CSR_XS(csr_base, TLU_SLOT_CAPABILITIES, reg);
usr/src/uts/sun4u/io/px/px_hlib.c
3219
reg = CSR_XR(csr_base, TLU_SLOT_CONTROL);
usr/src/uts/sun4u/io/px/px_hlib.c
3220
reg &= ~PCIE_SLOTCTL_PWR_INDICATOR_MASK;
usr/src/uts/sun4u/io/px/px_hlib.c
3221
reg = pcie_slotctl_pwr_indicator_set(reg,
usr/src/uts/sun4u/io/px/px_hlib.c
3223
CSR_XS(csr_base, TLU_SLOT_CONTROL, reg);
usr/src/uts/sun4u/io/px/px_hlib.c
3250
reg = CSR_XR(csr_base, TLU_SLOT_CONTROL);
usr/src/uts/sun4u/io/px/px_hlib.c
3251
reg &= ~PCIE_SLOTCTL_PWR_INDICATOR_MASK;
usr/src/uts/sun4u/io/px/px_hlib.c
3252
reg = pcie_slotctl_pwr_indicator_set(reg,
usr/src/uts/sun4u/io/px/px_hlib.c
3254
CSR_XS(csr_base, TLU_SLOT_CONTROL, reg);
usr/src/uts/sun4u/io/px/px_hlib.c
3267
volatile uint64_t reg;
usr/src/uts/sun4u/io/px/px_hlib.c
3284
reg = CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE);
usr/src/uts/sun4u/io/px/px_hlib.c
3285
reg &= ~((1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_P) |
usr/src/uts/sun4u/io/px/px_hlib.c
3289
CSR_XS(csr_base, TLU_OTHER_EVENT_LOG_ENABLE, reg);
usr/src/uts/sun4u/io/px/px_hlib.c
3324
reg = CSR_XR(csr_base, TLU_SLOT_CONTROL);
usr/src/uts/sun4u/io/px/px_hlib.c
3325
reg &= ~PCIE_SLOTCTL_PWR_INDICATOR_MASK;
usr/src/uts/sun4u/io/px/px_hlib.c
3326
reg = pcie_slotctl_pwr_indicator_set(reg,
usr/src/uts/sun4u/io/px/px_hlib.c
3328
CSR_XS(csr_base, TLU_SLOT_CONTROL, reg);
usr/src/uts/sun4u/io/px/px_hlib.c
3331
reg = CSR_XR(csr_base, TLU_SLOT_CONTROL);
usr/src/uts/sun4u/io/px/px_hlib.c
3332
reg &= ~PCIE_SLOTCTL_ATTN_INDICATOR_MASK;
usr/src/uts/sun4u/io/px/px_hlib.c
3333
reg = pcie_slotctl_attn_indicator_set(reg,
usr/src/uts/sun4u/io/px/px_hlib.c
3335
CSR_XS(csr_base, TLU_SLOT_CONTROL, reg);
usr/src/uts/sun4u/io/px/px_hlib.c
3359
reg = CSR_XR(csr_base, TLU_SLOT_CONTROL);
usr/src/uts/sun4u/io/px/px_hlib.c
3360
reg &= ~PCIE_SLOTCTL_ATTN_INDICATOR_MASK;
usr/src/uts/sun4u/io/px/px_hlib.c
3361
reg = pcie_slotctl_attn_indicator_set(reg,
usr/src/uts/sun4u/io/px/px_hlib.c
3363
CSR_XS(csr_base, TLU_SLOT_CONTROL, reg);
usr/src/uts/sun4u/io/px/px_hlib.c
3458
volatile uint64_t reg;
usr/src/uts/sun4u/io/px/px_hlib.c
3474
reg = CSR_XR((caddr_t)pxu_p->px_address[PX_REG_CSR],
usr/src/uts/sun4u/io/px/px_hlib.c
3476
reg &= ~((1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_P) |
usr/src/uts/sun4u/io/px/px_hlib.c
3481
TLU_OTHER_EVENT_LOG_ENABLE, reg);
usr/src/uts/sun4u/io/px/px_hlib.c
52
uint64_t reg;
usr/src/uts/sun4u/io/rmc_comm.c
176
sio_put_reg(struct rmc_comm_state *rcs, uint_t reg, uint8_t val)
usr/src/uts/sun4u/io/rmc_comm.c
178
DPRINTF(rcs, DSER, (CE_CONT, "REG[%d]<-$%02x", reg, val));
usr/src/uts/sun4u/io/rmc_comm.c
208
rcs->sd_state.sio_regs + reg, val);
usr/src/uts/sun4u/io/rmc_comm.c
218
sio_get_reg(struct rmc_comm_state *rcs, uint_t reg)
usr/src/uts/sun4u/io/rmc_comm.c
224
rcs->sd_state.sio_regs + reg);
usr/src/uts/sun4u/io/rmc_comm.c
227
DPRINTF(rcs, DSER, (CE_CONT, "$%02x<-REG[%d]", val, reg));
usr/src/uts/sun4u/lw2plus/io/lombus.c
419
sio_put_reg(struct lombus_state *ssp, uint_t reg, uint8_t val)
usr/src/uts/sun4u/lw2plus/io/lombus.c
421
lombus_trace(ssp, 'P', "sio_put_reg", "REG[%d] <- $%02x", reg, val);
usr/src/uts/sun4u/lw2plus/io/lombus.c
450
ddi_put8(ssp->sio_handle, ssp->sio_regs + reg, val);
usr/src/uts/sun4u/lw2plus/io/lombus.c
458
sio_get_reg(struct lombus_state *ssp, uint_t reg)
usr/src/uts/sun4u/lw2plus/io/lombus.c
463
val = ddi_get8(ssp->sio_handle, ssp->sio_regs + reg);
usr/src/uts/sun4u/lw2plus/io/lombus.c
467
lombus_trace(ssp, 'G', "sio_get_reg", "$%02x <- REG[%d]", val, reg);
usr/src/uts/sun4u/opl/io/mc-opl.c
2729
uint32_t reg;
usr/src/uts/sun4u/opl/io/mc-opl.c
2748
reg = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bk));
usr/src/uts/sun4u/opl/io/mc-opl.c
2749
bankp->mcb_ptrl_cntl = (reg & MAC_CNTL_PTRL_PRESERVE_BITS);
usr/src/uts/sun4u/opl/io/pcicmu/pcicmu.c
1259
ib_map_reg_get_cpu(volatile uint64_t reg)
usr/src/uts/sun4u/opl/io/pcicmu/pcicmu.c
1261
return ((reg & PCMU_INTR_MAP_REG_TID) >>
usr/src/uts/sun4u/opl/io/pcicmu/pcmu_cb.c
102
uint64_t reg, pa;
usr/src/uts/sun4u/opl/io/pcicmu/pcmu_cb.c
114
reg = ib_get_map_reg(mondo, cpu_id);
usr/src/uts/sun4u/opl/io/pcicmu/pcmu_cb.c
115
stdphysio(pa, reg);
usr/src/uts/sun4u/opl/io/pcicmu/pcmu_cb.c
127
"\tPA=%016llx data=%016llx\n", pa, reg);
usr/src/uts/sun4u/serengeti/io/sbdp_mem.c
1510
mc_regspace reg;
usr/src/uts/sun4u/serengeti/io/sbdp_mem.c
1535
if (prom_getprop(nodeid, "reg", (caddr_t)®) < 0)
usr/src/uts/sun4u/serengeti/io/sbdp_mem.c
1538
mc_addr = ((uint64_t)reg.regspec_addr_hi) << 32;
usr/src/uts/sun4u/serengeti/io/sbdp_mem.c
1539
mc_addr |= (uint64_t)reg.regspec_addr_lo;
usr/src/uts/sun4u/serengeti/io/sbdp_mem.c
1577
mc_regspace reg;
usr/src/uts/sun4u/serengeti/io/sbdp_mem.c
1589
if (prom_getprop(nodeid, "reg", (caddr_t)®) < 0)
usr/src/uts/sun4u/serengeti/io/sbdp_mem.c
1592
mc_addr = ((uint64_t)reg.regspec_addr_hi) << 32;
usr/src/uts/sun4u/serengeti/io/sbdp_mem.c
1593
mc_addr |= (uint64_t)reg.regspec_addr_lo;
usr/src/uts/sun4u/serengeti/io/sbdp_mem.c
662
mc_regspace reg;
usr/src/uts/sun4u/serengeti/io/sbdp_mem.c
669
if (prom_getprop(nodeid, "reg", (caddr_t)®) < 0)
usr/src/uts/sun4u/serengeti/io/sbdp_mem.c
674
*pa = ((uint64_t)reg.regspec_addr_hi) << 32;
usr/src/uts/sun4u/serengeti/io/sbdp_mem.c
675
*pa |= (uint64_t)reg.regspec_addr_lo;
usr/src/uts/sun4u/serengeti/ml/sbdp.il.cpp
123
! We need to free up a temp reg for the L2 flush macro (register usage
usr/src/uts/sun4u/sunfire/io/jtag.c
168
#define jtag_data(reg, nbits) (*(reg) >> (32 - (nbits)))
usr/src/uts/sun4u/sunfire/io/jtag.c
174
#define TAP_WAIT(reg) timeout = JTAG_TIMEOUT; \
usr/src/uts/sun4u/sunfire/io/jtag.c
175
while ((*(reg) & JTAG_BUSY_BIT) != 0) \
usr/src/uts/sun4u/sunfire/io/jtag.c
179
#define TAP_SHIFT(reg, data, nbits) \
usr/src/uts/sun4u/sunfire/io/jtag.c
180
*(reg) = ((data<<16) | ((nbits-1)<<12) | JTAG_SHIFT); \
usr/src/uts/sun4u/sunfire/io/jtag.c
181
TAP_WAIT(reg)
usr/src/uts/sun4u/sunfire/io/jtag.c
185
#define TAP_ISSUE_CMD(reg, cmd, status) \
usr/src/uts/sun4u/sunfire/io/jtag.c
186
status = tap_issue_cmd(reg, cmd); \
usr/src/uts/sun4u/sunfire/io/jtag.c
190
#define TAP_SHIFT_CONSTANT(reg, val, nbits, status) \
usr/src/uts/sun4u/sunfire/io/jtag.c
191
status = tap_shift_constant(reg, val, nbits); \
usr/src/uts/sun4u/sunfire/io/jtag.c
195
#define TAP_SHIFT_SINGLE(reg, val, nbits, status) \
usr/src/uts/sun4u/sunfire/io/jtag.c
196
status = tap_shift_single(reg, val, nbits); \
usr/src/uts/sun4u/sunfire/io/jtag.c
200
#define TAP_SHIFT_MULTIPLE(reg, in, nbits, out, status) \
usr/src/uts/sun4u/sunfire/io/jtag.c
201
status = tap_shift_multiple(reg, in, nbits, out); \
usr/src/uts/sun4u/sunfire/io/sysctrl.c
3275
uchar_t reg;
usr/src/uts/sun4u/sunfire/io/sysctrl.c
3316
while (uart_table[i].reg != TABLE_END) {
usr/src/uts/sun4u/sunfire/io/sysctrl.c
3317
*(softsp->rcons_ctl) = uart_table[i].reg;
usr/src/uts/sun4u/sunfire/sys/sysctrl.h
172
#define ISPLUSSYS(reg) ((reg != 0) && \
usr/src/uts/sun4u/sunfire/sys/sysctrl.h
173
(SYS_TYPE2(*reg) == SYS_PLUS_SYSTEM))
usr/src/uts/sun4u/sys/cheetahasm.h
38
#define ASM_LD(reg, symbol) \
usr/src/uts/sun4u/sys/cheetahasm.h
39
sethi %hi(symbol), reg; \
usr/src/uts/sun4u/sys/cheetahasm.h
40
ld [reg + %lo(symbol)], reg; \
usr/src/uts/sun4u/sys/cheetahasm.h
42
#define ASM_LDX(reg, symbol) \
usr/src/uts/sun4u/sys/cheetahasm.h
43
sethi %hi(symbol), reg; \
usr/src/uts/sun4u/sys/cheetahasm.h
44
ldx [reg + %lo(symbol)], reg; \
usr/src/uts/sun4u/sys/cheetahasm.h
46
#define ASM_JMP(reg, symbol) \
usr/src/uts/sun4u/sys/cheetahasm.h
47
sethi %hi(symbol), reg; \
usr/src/uts/sun4u/sys/cheetahasm.h
48
jmp reg + %lo(symbol); \
usr/src/uts/sun4u/sys/i2c/clients/adm1031_impl.h
155
uchar_t reg;
usr/src/uts/sun4u/sys/machthread.h
114
#define CPU_ADDR(reg, scr) \
usr/src/uts/sun4u/sys/machthread.h
116
CPU_INDEX(scr, reg); \
usr/src/uts/sun4u/sys/machthread.h
118
set cpu, reg; \
usr/src/uts/sun4u/sys/machthread.h
119
ldn [reg + scr], reg
usr/src/uts/sun4u/sys/machthread.h
128
#define CPU_PADDR(reg, scr) \
usr/src/uts/sun4u/sys/machthread.h
130
CPU_INDEX(scr, reg); \
usr/src/uts/sun4u/sys/machthread.h
132
set cpu_pa, reg; \
usr/src/uts/sun4u/sys/machthread.h
133
ldx [reg + scr], reg
usr/src/uts/sun4u/sys/mc-us3i.h
76
void *reg;
usr/src/uts/sun4u/sys/opl_olympus_regs.h
242
#define ERRLOG_REG_EIDR(reg) ((reg >> ERRLOG_REG_EIDR_SHIFT) & \
usr/src/uts/sun4u/sys/opl_olympus_regs.h
244
#define ERRLOG_REG_LOGPA(reg) (reg & ERRLOG_REG_LOGPA_MASK)
usr/src/uts/sun4u/sys/opl_olympus_regs.h
245
#define ERRLOG_REG_NUMERR(reg) (reg & ERRLOG_REG_NUMERR_MASK)
usr/src/uts/sun4u/sys/opl_olympus_regs.h
297
} reg;
usr/src/uts/sun4u/sys/pci/db21554_config.h
183
#define DB_PCI_REG_ADDR(bus, device, function, reg) \
usr/src/uts/sun4u/sys/pci/db21554_config.h
185
| (((function) & 0x7) << 8) | ((reg) & 0xff)
usr/src/uts/sun4u/sys/pci/db21554_config.h
188
#define DB_PCI_REG_ADDR_TYPE0(bus, device, function, reg) \
usr/src/uts/sun4u/sys/pci/db21554_config.h
191
((reg) & 0xfc))
usr/src/uts/sun4u/sys/pci/db21554_config.h
194
#define DB_PCI_REG_ADDR_TYPE1(bus, device, function, reg) \
usr/src/uts/sun4u/sys/pci/db21554_config.h
196
| (((function) & 0x7) << 8) | ((reg) & 0xfc))
usr/src/uts/sun4u/sys/pci/pci_chip.h
57
extern uint32_t ib_map_reg_get_cpu(volatile uint64_t reg);
usr/src/uts/sun4u/sys/sbbcvar.h
100
pci_regspec_t *reg;
usr/src/uts/sun4u/sys/traptrace.h
157
#define GET_TRACE_TICK(reg, scr) \
usr/src/uts/sun4u/sys/traptrace.h
158
rdpr %tick, reg;
usr/src/uts/sun4u/sys/traptrace.h
160
#define GET_TRACE_TICK(reg, scr) \
usr/src/uts/sun4u/sys/traptrace.h
161
sethi %hi(traptrace_use_stick), reg; \
usr/src/uts/sun4u/sys/traptrace.h
162
lduw [reg + %lo(traptrace_use_stick)], reg; \
usr/src/uts/sun4u/sys/traptrace.h
164
brz,a reg, .+12; \
usr/src/uts/sun4u/sys/traptrace.h
165
rdpr %tick, reg; \
usr/src/uts/sun4u/sys/traptrace.h
166
rd %asr24, reg;
usr/src/uts/sun4v/io/n2rng/n2rng_entp_setup.c
140
uint64_t reg;
usr/src/uts/sun4v/io/n2rng/n2rng_entp_setup.c
175
reg = LOGIC_TEST_EXPECTED_M1;
usr/src/uts/sun4v/io/n2rng/n2rng_entp_setup.c
178
if (buffer[j] == reg) {
usr/src/uts/sun4v/io/n2rng/n2rng_entp_setup.c
188
lfsr64_adv_seq(RNG_POLY, reg, 1, ®);
usr/src/uts/sun4v/io/vnet.c
417
uint64_t reg;
usr/src/uts/sun4v/io/vnet.c
462
reg = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
usr/src/uts/sun4v/io/vnet.c
464
if (reg == -1) {
usr/src/uts/sun4v/io/vnet.c
467
vnetp->reg = reg;
usr/src/uts/sun4v/io/vnet.c
504
status = vgen_init(vnetp, reg, vnetp->dip,
usr/src/uts/sun4v/io/vnet_dds.c
780
vdds_reg_t reg;
usr/src/uts/sun4v/io/vnet_dds.c
814
reg.addr_hi = 0xc0000000 | NIUCFGHDL(cba->cookie);
usr/src/uts/sun4v/io/vnet_dds.c
815
reg.addr_lo = 0;
usr/src/uts/sun4v/io/vnet_dds.c
816
reg.size_hi = 0;
usr/src/uts/sun4v/io/vnet_dds.c
817
reg.size_lo = 0;
usr/src/uts/sun4v/io/vnet_dds.c
819
"reg", (int *)®, sizeof (reg)/sizeof (int)) != DDI_SUCCESS) {
usr/src/uts/sun4v/io/vnet_dds.c
882
vdds_reg_t reg;
usr/src/uts/sun4v/io/vnet_dds.c
941
reg.addr_hi = HVCOOKIE(cba->cookie);
usr/src/uts/sun4v/io/vnet_dds.c
942
reg.addr_lo = 0;
usr/src/uts/sun4v/io/vnet_dds.c
943
reg.size_hi = 0;
usr/src/uts/sun4v/io/vnet_dds.c
944
reg.size_lo = size;
usr/src/uts/sun4v/io/vnet_dds.c
947
(int *)®, sizeof (reg) / sizeof (int)) != DDI_SUCCESS) {
usr/src/uts/sun4v/os/error.c
882
switch (errh_fltp->errh_er.reg) {
usr/src/uts/sun4v/sys/error.h
137
uint16_t reg; /* Value of the ASR register number */
usr/src/uts/sun4v/sys/machthread.h
73
#define CPU_ADDR(reg, scr) \
usr/src/uts/sun4v/sys/machthread.h
75
CPU_INDEX(scr, reg); \
usr/src/uts/sun4v/sys/machthread.h
77
set cpu, reg; \
usr/src/uts/sun4v/sys/machthread.h
78
ldn [reg + scr], reg
usr/src/uts/sun4v/sys/machthread.h
87
#define CPU_PADDR(reg, scr) \
usr/src/uts/sun4v/sys/machthread.h
89
CPU_INDEX(scr, reg); \
usr/src/uts/sun4v/sys/machthread.h
91
set cpu_pa, reg; \
usr/src/uts/sun4v/sys/machthread.h
92
ldx [reg + scr], reg
usr/src/uts/sun4v/sys/traptrace.h
219
#define GET_TRACE_TICK(reg, scr) \
usr/src/uts/sun4v/sys/traptrace.h
220
RD_TICK_NO_SUSPEND_CHECK(reg, scr);
usr/src/uts/sun4v/sys/traptrace.h
222
#define GET_TRACE_TICK(reg, scr) \
usr/src/uts/sun4v/sys/traptrace.h
223
RD_TICKSTICK_FLAG(reg, scr, traptrace_use_stick);
usr/src/uts/sun4v/sys/vnet.h
273
uint64_t reg; /* reg prop value */
