sys/arm/allwinner/a10_codec.c

179

#define CODEC_ANALOG_WRITE(sc, reg, val) bus_write_4((sc)->res[1], (reg), (val))

sys/arm/allwinner/a10_codec.c

182

#define CODEC_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))

sys/arm/allwinner/a10_dmac.c

87

#define DMA_WRITE(sc, reg, val) bus_write_4((sc)->sc_res[0], (reg), (val))

sys/arm/allwinner/a31_dmac.c

161

#define DMA_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))

sys/arm/allwinner/a33_codec.c

155

#define CODEC_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))

sys/arm/allwinner/a64/sun50i_a64_acodec.c

134

#define A64CODEC_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val))

sys/arm/allwinner/aw_cir.c

50

#define WRITE(_sc, _r, _v) bus_write_4((_sc)->res[0], (_r), (_v))

sys/arm/allwinner/aw_gpio.c

431

bus_write_4((_sc)->sc_res[AW_GPIO_MEMRES], _off, _val)

sys/arm/allwinner/aw_i2s.c

238

#define I2S_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))

sys/arm/allwinner/aw_mmc.c

220

bus_write_4((_sc)->aw_res[AW_MMC_MEMRES], _reg, _value)

sys/arm/allwinner/aw_nmi.c

62

#define SC_NMI_WRITE(_sc, _reg, _val) bus_write_4(_sc->res[0], _reg, _val)

sys/arm/allwinner/aw_reset.c

67

#define RESET_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val))

sys/arm/allwinner/aw_rsb.c

153

#define RSB_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val))

sys/arm/allwinner/aw_rtc.c

93

#define RTC_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val))

sys/arm/allwinner/aw_sid.c

287

#define WR4(sc, reg, val) bus_write_4((sc)->res, (reg), (val))

sys/arm/allwinner/aw_thermal.c

375

#define WR4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))

sys/arm/allwinner/aw_timer.c

107

bus_write_4(sc->res[AW_TIMER_MEMRES], reg, val)

sys/arm/allwinner/aw_ts.c

45

#define WRITE(_sc, _r, _v) bus_write_4((_sc)->res[0], (_r), (_v))

sys/arm/allwinner/aw_usb3phy.c

107

#define WR4(res, o, v) bus_write_4(res, (o), (v))

sys/arm/allwinner/aw_usbphy.c

181

#define WR4(res, o, v) bus_write_4(res, (o), (v))

sys/arm/allwinner/aw_usbphy.c

316

bus_write_4(sc->phy_ctrl, PHY_CSR, val);

sys/arm/allwinner/aw_usbphy.c

470

bus_write_4(sc->phy_ctrl, PHY_CSR, val);

sys/arm/allwinner/aw_wdog.c

50

#define WRITE(_sc, _r, _v) bus_write_4((_sc)->res, (_r), (_v))

sys/arm/allwinner/if_awg.c

1405

bus_write_4(sc->res[_RES_SYSCON], 0, val);

sys/arm/allwinner/if_awg.c

72

#define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_EMAC], (reg), (val))

sys/arm/annapurna/alpine/alpine_ccu.c

106

bus_write_4(sc->res, AL_CCU_SNOOP_CONTROL_IOFAB_0_OFFSET, 1);

sys/arm/annapurna/alpine/alpine_ccu.c

107

bus_write_4(sc->res, AL_CCU_SNOOP_CONTROL_IOFAB_1_OFFSET, 1);

sys/arm/annapurna/alpine/alpine_ccu.c

110

bus_write_4(sc->res, AL_CCU_SPECULATION_CONTROL_OFFSET, 7);

sys/arm/annapurna/alpine/alpine_nb_service.c

108

bus_write_4(sc->res, AL_NB_ACF_MISC_OFFSET, val);

sys/arm/arm/gic.c

157

bus_write_4((_sc)->gic_res[GIC_RES_CPU], (_reg), (_val))

sys/arm/arm/gic.c

164

bus_write_4((_sc)->gic_res[GIC_RES_DIST], (_reg), (_val))

sys/arm/arm/mpcore_timer.c

115

#define tmr_prv_write_4(sc, reg, val) bus_write_4((sc)->prv_mem, reg, val)

sys/arm/arm/mpcore_timer.c

117

#define tmr_gbl_write_4(sc, reg, val) bus_write_4((sc)->gbl_mem, reg, val)

sys/arm/broadcom/bcm2835/bcm2835_dma.c

187

bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), 0);

sys/arm/broadcom/bcm2835/bcm2835_dma.c

199

bus_write_4(sc->sc_mem, BCM_DMA_CBNEXT(ch), 0);

sys/arm/broadcom/bcm2835/bcm2835_dma.c

202

bus_write_4(sc->sc_mem, BCM_DMA_CS(ch),

sys/arm/broadcom/bcm2835/bcm2835_dma.c

207

bus_write_4(sc->sc_mem, BCM_DMA_CBADDR(ch), 0);

sys/arm/broadcom/bcm2835/bcm2835_dma.c

208

bus_write_4(sc->sc_mem, BCM_DMA_CBNEXT(ch), 0);

sys/arm/broadcom/bcm2835/bcm2835_dma.c

311

bus_write_4(sc->sc_mem, BCM_DMA_CS(i), CS_RESET);

sys/arm/broadcom/bcm2835/bcm2835_dma.c

585

bus_write_4(sc->sc_mem, BCM_DMA_CBADDR(ch),

sys/arm/broadcom/bcm2835/bcm2835_dma.c

587

bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), CS_ACTIVE);

sys/arm/broadcom/bcm2835/bcm2835_dma.c

650

bus_write_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch),

sys/arm/broadcom/bcm2835/bcm2835_dma.c

657

bus_write_4(sc->sc_mem, BCM_DMA_CS(ch->ch),

sys/arm/broadcom/bcm2835/bcm2835_rng.c

191

bus_write_4(sc->sc_mem_res, off, val);

sys/arm/broadcom/bcm2835/bcm2838_pci.c

169

bus_write_4(sc->base.base.res, reg, htole32(val));

sys/arm/broadcom/bcm2835/bcm2838_pci.c

368

bus_write_4(sc->base.base.res, offset, htole32(val));

sys/arm/freescale/imx/imx6_anatop.c

158

bus_write_4(imx6_anatop_sc->res[MEMRES], offset, value);

sys/arm/freescale/imx/imx6_ccm.c

76

bus_write_4(sc->mem_res, off, val);

sys/arm/freescale/imx/imx6_ipu.c

85

bus_write_4((_sc)->sc_mem_res, (reg), (value))

sys/arm/freescale/imx/imx6_src.c

67

bus_write_4(sc->mem_res, off, val);

sys/arm/freescale/imx/imx6_usbphy.c

149

bus_write_4(sc->mem_res, CTRL_SET_REG, CTRL_SFTRST);

sys/arm/freescale/imx/imx6_usbphy.c

150

bus_write_4(sc->mem_res, CTRL_CLR_REG, CTRL_SFTRST | CTRL_CLKGATE);

sys/arm/freescale/imx/imx6_usbphy.c

153

bus_write_4(sc->mem_res, CTRL_SET_REG,

sys/arm/freescale/imx/imx6_usbphy.c

157

bus_write_4(sc->mem_res, PWD_REG, 0);

sys/arm/freescale/imx/imx_epit.c

143

bus_write_4(sc->memres, offset, value);

sys/arm/freescale/imx/imx_epit.c

150

bus_write_4(sc->memres, offset, value);

sys/arm/freescale/imx/imx_iomux.c

115

bus_write_4(sc->mem_res, off, val);

sys/arm/freescale/imx/imx_spi.c

163

bus_write_4(sc->memres, offset, value);

sys/arm/include/pl310.h

178

bus_write_4(sc->sc_mem_res, off, val);

sys/arm/mv/armada/thermal.c

294

bus_write_4(sc->ctrl_res, 0, tsen_ctrl);

sys/arm/mv/armada/wdt.c

197

bus_write_4(wdt_softc->wdt_res, CPU_TIMER_CONTROL, val);

sys/arm/mv/armada/wdt.c

204

bus_write_4(wdt_softc->wdt_res, CPU_TIMER0 + timer * 0x8, val);

sys/arm/mv/armada38x/armada38x_rtc.c

328

bus_write_4(sc->res[RTC_RES], off, val);

sys/arm/mv/armada38x/armada38x_rtc.c

343

bus_write_4(sc->res[RTC_SOC_RES], A38X_RTC_BRIDGE_TIMING_CTRL, val);

sys/arm/mv/armada38x/armada38x_rtc.c

355

bus_write_4(sc->res[RTC_SOC_RES], A8K_RTC_BRIDGE_TIMING_CTRL1, val);

sys/arm/mv/armada38x/armada38x_rtc.c

360

bus_write_4(sc->res[RTC_SOC_RES], A8K_RTC_BRIDGE_TIMING_CTRL1, val);

sys/arm/mv/clk/armada38x_coreclk.c

109

bus_write_4(sc->res, addr, val);

sys/arm/mv/clk/armada38x_gateclk.c

54

#define WR4(_sc, addr, val) bus_write_4(_sc->res, addr, val)

sys/arm/mv/mv_ap806_gicp.c

79

#define WR4(sc, reg, val) bus_write_4((sc)->res, (reg), (val))

sys/arm/mv/mv_ap806_sei.c

103

#define WR4(sc, reg, val) bus_write_4((sc)->mem_res, (reg), (val))

sys/arm/mv/mv_cp110_icu.c

100

#define WR4(sc, reg, val) bus_write_4((sc)->res, (reg), (val))

sys/arm/mv/rtc.c

190

bus_write_4(sc->res[0], off, val);

sys/arm/nvidia/drm2/tegra_dc.c

55

#define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, 4 * (_r), (_v))

sys/arm/nvidia/drm2/tegra_hdmi.c

58

#define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, 4 * (_r), (_v))

sys/arm/nvidia/tegra124/tegra124_car.c

477

bus_write_4(sc->mem_res, addr, val);

sys/arm/nvidia/tegra124/tegra124_car.c

492

bus_write_4(sc->mem_res, addr, reg);

sys/arm/nvidia/tegra124/tegra124_pmc.c

135

#define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

170

#define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))

sys/arm/nvidia/tegra_ahci.c

207

#define AHCI_WR4(_sc, _r, _v) bus_write_4((_sc)->ctlr.r_mem, (_r), (_v))

sys/arm/nvidia/tegra_ahci.c

209

#define SATA_WR4(_sc, _r, _v) bus_write_4((_sc)->sata_mem, (_r), (_v))

sys/arm/nvidia/tegra_ahci.c

580

bus_write_4(sc->aux_mem, SATA_AUX_MISC_CNTL_1, val);

sys/arm/nvidia/tegra_gpio.c

157

bus_write_4(sc->mem_res, reg + GPIO_REGNUM(pin->gp_pin), tmp);

sys/arm/nvidia/tegra_gpio.c

349

bus_write_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq), tmp);

sys/arm/nvidia/tegra_gpio.c

364

bus_write_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq), tmp);

sys/arm/nvidia/tegra_gpio.c

62

#define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))

sys/arm/nvidia/tegra_gpio.c

788

bus_write_4(sc->mem_res, GPIO_INT_ENB + GPIO_REGNUM(i), 0);

sys/arm/nvidia/tegra_gpio.c

789

bus_write_4(sc->mem_res, GPIO_INT_STA + GPIO_REGNUM(i), 0xFF);

sys/arm/nvidia/tegra_gpio.c

790

bus_write_4(sc->mem_res, GPIO_INT_CLR + GPIO_REGNUM(i), 0xFF);

sys/arm/nvidia/tegra_i2c.c

191

#define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))

sys/arm/nvidia/tegra_lic.c

65

#define WR4(_sc, _b, _r, _v) bus_write_4((_sc)->mem_res[_b], (_r), (_v))

sys/arm/nvidia/tegra_mc.c

97

#define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))

sys/arm/nvidia/tegra_pcie.c

232

#define PADS_WR4(_sc, _r, _v) bus_write_4((_sc)->pads_mem_res, (_r), (_v))

sys/arm/nvidia/tegra_pcie.c

234

#define AFI_WR4(_sc, _r, _v) bus_write_4((_sc)->afi_mem_res, (_r), (_v))

sys/arm/nvidia/tegra_pcie.c

522

bus_write_4(sc->afi_mem_res, AFI_INTR_CODE, 0);

sys/arm/nvidia/tegra_pinmux.c

542

bus_write_4(sc->mux_mem_res, mux->reg, reg);

sys/arm/nvidia/tegra_pinmux.c

595

bus_write_4(sc->pad_mem_res, grp->reg, reg);

sys/arm/nvidia/tegra_pinmux.c

618

bus_write_4(sc->mipi_mem_res, 0, reg); /* register 0x820 */

sys/arm/nvidia/tegra_rtc.c

75

#define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))

sys/arm/nvidia/tegra_sdhci.c

194

bus_write_4(sc->mem_res, off, val);

sys/arm/nvidia/tegra_soctherm.c

131

#define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))

sys/arm/nvidia/tegra_usbphy.c

310

bus_write_4(sc->mem_res, offs, val)

sys/arm/nvidia/tegra_usbphy.c

422

bus_write_4(sc->pads_res, UTMIP_BIAS_CFG0, val);

sys/arm/nvidia/tegra_usbphy.c

546

bus_write_4(sc->pads_res, UTMIP_BIAS_CFG0, val);

sys/arm/nvidia/tegra_xhci.c

211

#define IPFS_WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res_ipfs, (_r), (_v))

sys/arm/nvidia/tegra_xhci.c

213

#define FPCI_WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res_fpci, (_r), (_v))

sys/arm/ti/am335x/am335x_dmtimer.c

89

#define DMTIMER_WRITE4(sc, reg, val) bus_write_4((sc)->tmr_mem_res, (reg), (val))

sys/arm/ti/am335x/am335x_dmtpps.c

146

#define DMTIMER_WRITE4(sc, reg, val) bus_write_4((sc)->mem_res, (reg), (val))

sys/arm/ti/am335x/am335x_ecap.c

62

bus_write_4((_sc)->sc_mem_res, reg, value);

sys/arm/ti/am335x/am335x_lcd.c

184

bus_write_4((_sc)->sc_mem_res, reg, value);

sys/arm/ti/am335x/am335x_musb.c

99

bus_write_4((sc)->sc_mem_res[idx], (reg), (val)); \

sys/arm/ti/am335x/am335x_rtc.c

54

bus_write_4((_sc)->sc_mem_res, reg, value)

sys/arm/ti/cpsw/if_cpsw.c

369

bus_write_4((_sc)->mem_res, (_reg), (_val))

sys/arm/ti/ti_adcvar.h

34

bus_write_4((_sc)->sc_mem_res, reg, value)

sys/arm/ti/ti_edma3.c

124

#define ti_edma3_cc_wr_4(reg, val) bus_write_4(ti_edma3_sc->mem_res[0], reg, val)

sys/arm/ti/ti_gpio.c

174

bus_write_4(sc->sc_mem_res, off, val);

sys/arm/ti/ti_sdhci.c

143

bus_write_4(sc->mem_res, off + sc->mmchs_reg_off, val);

sys/arm/ti/ti_sdhci.c

157

bus_write_4(sc->mem_res, off + sc->sdhci_reg_off, val);

sys/arm/ti/ti_sdma.c

175

bus_write_4(sc->sc_mem_res, off, val);

sys/arm/xilinx/zy7_devcfg.c

97

#define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val)))

sys/arm/xilinx/zy7_gpio.c

181

#define WR4(sc, off, val) bus_write_4((sc)->mem_res, (off), (val))

sys/arm/xilinx/zy7_qspi.c

106

#define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val)))

sys/arm/xilinx/zy7_slcr.c

74

#define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val)))

sys/arm/xilinx/zy7_spi.c

93

#define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val)))

sys/arm64/apple/apple_aic.c

412

bus_write_4(sc->sc_mem, AIC_TARGET_CPU(irq),

sys/arm64/apple/apple_aic.c

444

bus_write_4(sc->sc_mem, AIC_MASK_CLEAR(irq), AIC_IRQ_MASK(irq));

sys/arm64/apple/apple_aic.c

469

bus_write_4(sc->sc_mem, AIC_MASK_SET(irq), AIC_IRQ_MASK(irq));

sys/arm64/apple/apple_aic.c

494

bus_write_4(sc->sc_mem, AIC_SW_CLEAR(irq), AIC_IRQ_MASK(irq));

sys/arm64/apple/apple_aic.c

495

bus_write_4(sc->sc_mem, AIC_MASK_CLEAR(irq), AIC_IRQ_MASK(irq));

sys/arm64/apple/apple_aic.c

515

bus_write_4(sc->sc_mem, AIC_SW_CLEAR(irq), AIC_IRQ_MASK(irq));

sys/arm64/apple/apple_aic.c

531

bus_write_4(sc->sc_mem, AIC_MASK_CLEAR(irq), AIC_IRQ_MASK(irq));

sys/arm64/apple/apple_aic.c

662

bus_write_4(sc->sc_mem, AIC_TARGET_CPU(irq),

sys/arm64/apple/apple_aic.c

668

bus_write_4(sc->sc_mem, AIC_TARGET_CPU(irq), targets);

sys/arm64/apple/apple_aic.c

747

bus_write_4(sc->sc_mem, AIC_IPI_MASK_SET, AIC_IPI_SELF | AIC_IPI_OTHER);

sys/arm64/apple/apple_pinctrl.c

66

bus_write_4((sc)->sc_res[APPLE_PINCTRL_MEMRES], reg, val)

sys/arm64/arm64/cmn600.c

53

#define WR4(sc, r, v) bus_write_4((sc)->sc_res[0], (r), (v))

sys/arm64/arm64/gic_v3.c

252

bus_write_4(rdist, offset, val);

sys/arm64/arm64/gicv3_its.c

342

bus_write_4((sc)->sc_its_res, (reg), (val))

sys/arm64/arm64/pl031_rtc.c

132

bus_write_4(sc->reg, RTCLR, ts->tv_sec);

sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c

161

bus_write_4(sc->reg_base, MDIO_PARAM_OFFSET, param);

sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c

202

bus_write_4(sc->reg_base, MDIO_CTRL_OFFSET, 0);

sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c

214

bus_write_4(sc->reg_base, MDIO_PARAM_OFFSET, param);

sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c

216

bus_write_4(sc->reg_base, MDIO_ADDR_OFFSET, reg);

sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c

218

bus_write_4(sc->reg_base, MDIO_CTRL_OFFSET, op);

sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c

239

bus_write_4(sc->reg_base, MDIO_SCAN_CTRL_OFFSET, val);

sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c

249

bus_write_4(sc->reg_base, MDIO_RATE_ADJ_EXT_OFFSET, val);

sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c

250

bus_write_4(sc->reg_base, MDIO_RATE_ADJ_INT_OFFSET, val);

sys/arm64/broadcom/genet/if_genet.c

81

#define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_MAC], (reg), (val))

sys/arm64/coresight/coresight_cpu_debug.c

83

bus_write_4(sc->res, CORESIGHT_LAR, CORESIGHT_UNLOCK);

sys/arm64/coresight/coresight_cpu_debug.c

86

bus_write_4(sc->res, EDOSLAR, 0);

sys/arm64/coresight/coresight_cpu_debug.c

95

bus_write_4(sc->res, EDPRCR, reg);

sys/arm64/coresight/coresight_etm4x.c

100

bus_write_4(sc->res, TRCTRACEIDR, event->etm.trace_id);

sys/arm64/coresight/coresight_etm4x.c

106

bus_write_4(sc->res, TRCTSCTLR, 0);

sys/arm64/coresight/coresight_etm4x.c

124

bus_write_4(sc->res, TRCVICTLR, reg);

sys/arm64/coresight/coresight_etm4x.c

138

bus_write_4(sc->res, TRCACATR(i), reg);

sys/arm64/coresight/coresight_etm4x.c

143

bus_write_4(sc->res, TRCVIIECTLR, reg);

sys/arm64/coresight/coresight_etm4x.c

147

bus_write_4(sc->res, TRCVDARCCTLR, 0);

sys/arm64/coresight/coresight_etm4x.c

150

bus_write_4(sc->res, TRCSSCSR(0), 0);

sys/arm64/coresight/coresight_etm4x.c

154

bus_write_4(sc->res, TRCVIIECTLR, 0);

sys/arm64/coresight/coresight_etm4x.c

158

bus_write_4(sc->res, TRCVISSCTLR, 0);

sys/arm64/coresight/coresight_etm4x.c

161

bus_write_4(sc->res, TRCVDCTLR, 0);

sys/arm64/coresight/coresight_etm4x.c

164

bus_write_4(sc->res, TRCVDSACCTLR, 0);

sys/arm64/coresight/coresight_etm4x.c

178

bus_write_4(sc->res, CORESIGHT_LAR, CORESIGHT_UNLOCK);

sys/arm64/coresight/coresight_etm4x.c

181

bus_write_4(sc->res, TRCOSLAR, 0);

sys/arm64/coresight/coresight_etm4x.c

203

bus_write_4(sc->res, TRCPRGCTLR, TRCPRGCTLR_EN);

sys/arm64/coresight/coresight_etm4x.c

226

bus_write_4(sc->res, TRCPRGCTLR, 0);

sys/arm64/coresight/coresight_etm4x.c

87

bus_write_4(sc->res, TRCCONFIGR, reg);

sys/arm64/coresight/coresight_etm4x.c

90

bus_write_4(sc->res, TRCEVENTCTL0R, 0);

sys/arm64/coresight/coresight_etm4x.c

91

bus_write_4(sc->res, TRCEVENTCTL1R, 0);

sys/arm64/coresight/coresight_etm4x.c

94

bus_write_4(sc->res, TRCSTALLCTLR, 0);

sys/arm64/coresight/coresight_etm4x.c

97

bus_write_4(sc->res, TRCSYNCPR, TRCSYNCPR_4K);

sys/arm64/coresight/coresight_funnel.c

108

bus_write_4(sc->res, FUNNEL_FUNCTL, reg);

sys/arm64/coresight/coresight_funnel.c

69

bus_write_4(sc->res, CORESIGHT_LAR, CORESIGHT_UNLOCK);

sys/arm64/coresight/coresight_funnel.c

90

bus_write_4(sc->res, FUNNEL_FUNCTL, reg);

sys/arm64/coresight/coresight_replicator.c

58

bus_write_4(sc->res, CORESIGHT_LAR, CORESIGHT_UNLOCK);

sys/arm64/coresight/coresight_replicator.c

73

bus_write_4(sc->res, REPLICATOR_IDFILTER0, 0x00);

sys/arm64/coresight/coresight_replicator.c

74

bus_write_4(sc->res, REPLICATOR_IDFILTER1, 0xff);

sys/arm64/coresight/coresight_replicator.c

76

bus_write_4(sc->res, REPLICATOR_IDFILTER0, 0xff);

sys/arm64/coresight/coresight_replicator.c

77

bus_write_4(sc->res, REPLICATOR_IDFILTER1, 0x00);

sys/arm64/coresight/coresight_replicator.c

91

bus_write_4(sc->res, REPLICATOR_IDFILTER0, 0xff);

sys/arm64/coresight/coresight_replicator.c

92

bus_write_4(sc->res, REPLICATOR_IDFILTER1, 0xff);

sys/arm64/coresight/coresight_tmc.c

115

bus_write_4(sc->res, TMC_MODE, MODE_HW_FIFO);

sys/arm64/coresight/coresight_tmc.c

116

bus_write_4(sc->res, TMC_FFCR, FFCR_EN_FMT | FFCR_EN_TI);

sys/arm64/coresight/coresight_tmc.c

149

bus_write_4(sc->res, TMC_MODE, MODE_CIRCULAR_BUFFER);

sys/arm64/coresight/coresight_tmc.c

160

bus_write_4(sc->res, TMC_AXICTL, reg);

sys/arm64/coresight/coresight_tmc.c

164

bus_write_4(sc->res, TMC_FFCR, reg);

sys/arm64/coresight/coresight_tmc.c

166

bus_write_4(sc->res, TMC_TRG, 8);

sys/arm64/coresight/coresight_tmc.c

168

bus_write_4(sc->res, TMC_DBALO, event->etr.low);

sys/arm64/coresight/coresight_tmc.c

169

bus_write_4(sc->res, TMC_DBAHI, event->etr.high);

sys/arm64/coresight/coresight_tmc.c

170

bus_write_4(sc->res, TMC_RSZ, event->etr.bufsize / 4);

sys/arm64/coresight/coresight_tmc.c

172

bus_write_4(sc->res, TMC_RRP, event->etr.low);

sys/arm64/coresight/coresight_tmc.c

173

bus_write_4(sc->res, TMC_RWP, event->etr.low);

sys/arm64/coresight/coresight_tmc.c

177

bus_write_4(sc->res, TMC_STS, reg);

sys/arm64/coresight/coresight_tmc.c

193

bus_write_4(sc->res, CORESIGHT_LAR, CORESIGHT_UNLOCK);

sys/arm64/coresight/coresight_tmc.c

196

bus_write_4(sc->res, TMC_LAR, CORESIGHT_UNLOCK);

sys/arm64/coresight/coresight_tmc.c

70

bus_write_4(sc->res, TMC_CTL, CTL_TRACECAPTEN);

sys/arm64/coresight/coresight_tmc.c

94

bus_write_4(sc->res, TMC_CTL, reg);

sys/arm64/freescale/imx/imx_ccm.c

71

bus_write_4(sc->mem_res, off, val);

sys/arm64/iommu/smmu.c

1121

bus_write_4(sc->res[0], SMMU_GERROR_IRQ_CFG1, 0);

sys/arm64/iommu/smmu.c

1122

bus_write_4(sc->res[0], SMMU_GERROR_IRQ_CFG2, 0);

sys/arm64/iommu/smmu.c

1125

bus_write_4(sc->res[0], SMMU_EVENTQ_IRQ_CFG1, 0);

sys/arm64/iommu/smmu.c

1126

bus_write_4(sc->res[0], SMMU_EVENTQ_IRQ_CFG2, 0);

sys/arm64/iommu/smmu.c

1130

bus_write_4(sc->res[0], SMMU_PRIQ_IRQ_CFG1, 0);

sys/arm64/iommu/smmu.c

1131

bus_write_4(sc->res[0], SMMU_PRIQ_IRQ_CFG2, 0);

sys/arm64/iommu/smmu.c

1239

bus_write_4(sc->res[0], SMMU_CR1, reg);

sys/arm64/iommu/smmu.c

1242

bus_write_4(sc->res[0], SMMU_CR2, reg);

sys/arm64/iommu/smmu.c

1247

bus_write_4(sc->res[0], SMMU_STRTAB_BASE_CFG, strtab->base_cfg);

sys/arm64/iommu/smmu.c

1251

bus_write_4(sc->res[0], SMMU_CMDQ_PROD, sc->cmdq.lc.prod);

sys/arm64/iommu/smmu.c

1252

bus_write_4(sc->res[0], SMMU_CMDQ_CONS, sc->cmdq.lc.cons);

sys/arm64/iommu/smmu.c

1274

bus_write_4(sc->res[0], SMMU_EVENTQ_PROD, sc->evtq.lc.prod);

sys/arm64/iommu/smmu.c

1275

bus_write_4(sc->res[0], SMMU_EVENTQ_CONS, sc->evtq.lc.cons);

sys/arm64/iommu/smmu.c

1287

bus_write_4(sc->res[0], SMMU_PRIQ_PROD, sc->priq.lc.prod);

sys/arm64/iommu/smmu.c

1288

bus_write_4(sc->res[0], SMMU_PRIQ_CONS, sc->priq.lc.cons);

sys/arm64/iommu/smmu.c

296

bus_write_4(sc->res[0], reg, val);

sys/arm64/iommu/smmu.c

427

bus_write_4(sc->res[0], evtq->cons_off, evtq->lc.cons);

sys/arm64/iommu/smmu.c

553

bus_write_4(sc->res[0], cmdq->prod_off, cmdq->lc.prod);

sys/arm64/nvidia/tegra210/tegra210_car.c

475

bus_write_4(sc->mem_res, addr, val);

sys/arm64/nvidia/tegra210/tegra210_car.c

490

bus_write_4(sc->mem_res, addr, reg);

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

513

bus_write_4(sc->mux_mem_res, mux->reg, reg);

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

566

bus_write_4(sc->pad_mem_res, grp->reg, reg);

sys/arm64/nvidia/tegra210/tegra210_pmc.c

199

bus_write_4(sc->mem_res, r, v);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

324

#define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))

sys/arm64/qoriq/clk/qoriq_clkgen.c

135

bus_write_4(sc->res, addr, htole32(reg));

sys/arm64/qoriq/clk/qoriq_clkgen.c

137

bus_write_4(sc->res, addr, htobe32(reg));

sys/arm64/qoriq/clk/qoriq_clkgen.c

97

bus_write_4(sc->res, addr, htole32(val));

sys/arm64/qoriq/clk/qoriq_clkgen.c

99

bus_write_4(sc->res, addr, htobe32(val));

sys/arm64/qoriq/qoriq_gpio_pic.c

68

#define WR4(sc, off, data) bus_write_4((sc)->base.sc_mem, (off), (data))

sys/arm64/qoriq/qoriq_therm.c

200

bus_write_4(sc->mem_res, addr, val);

sys/arm64/qualcomm/qcom_gcc.c

76

bus_write_4(sc->res, GCC_QDSS_BCR, GCC_QDSS_BCR_BLK_ARES);

sys/arm64/qualcomm/qcom_gcc.c

79

bus_write_4(sc->res, GCC_QDSS_CFG_AHB_CBCR, AHB_CBCR_CLK_ENABLE);

sys/arm64/qualcomm/qcom_gcc.c

82

bus_write_4(sc->res, GCC_QDSS_DAP_CBCR, DAP_CBCR_CLK_ENABLE);

sys/arm64/qualcomm/qcom_gcc.c

85

bus_write_4(sc->res, GCC_QDSS_ETR_USB_CBCR, ETR_USB_CBCR_CLK_ENABLE);

sys/arm64/qualcomm/qcom_gcc.c

88

bus_write_4(sc->res, GCC_QDSS_BCR, 0);

sys/arm64/rockchip/rk3328_codec.c

160

#define RKCODEC_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val))

sys/arm64/rockchip/rk3568_combphy.c

179

bus_write_4(sc->mem, PHYREG7,

sys/arm64/rockchip/rk3568_combphy.c

183

bus_write_4(sc->mem, PHYREG15,

sys/arm64/rockchip/rk3568_combphy.c

207

bus_write_4(sc->mem, PHYREG32,

sys/arm64/rockchip/rk3568_combphy.c

226

bus_write_4(sc->mem, PHYREG32,

sys/arm64/rockchip/rk3568_combphy.c

231

bus_write_4(sc->mem, PHYREG15,

sys/arm64/rockchip/rk3568_combphy.c

235

bus_write_4(sc->mem, PHYREG33,

sys/arm64/rockchip/rk3568_combphy.c

240

bus_write_4(sc->mem, PHYREG12, PHYREG12_PLL_LPF_ADJ_VALUE);

sys/arm64/rockchip/rk3568_combphy.c

243

bus_write_4(sc->mem, PHYREG6,

sys/arm64/rockchip/rk3568_combphy.c

248

bus_write_4(sc->mem, PHYREG18, PHYREG18_PLL_LOOP);

sys/arm64/rockchip/rk3568_combphy.c

251

bus_write_4(sc->mem, PHYREG11, PHYREG11_SU_TRIM_0_7);

sys/arm64/rockchip/rk3568_combphy.c

278

bus_write_4(sc->mem, PHYREG15,

sys/arm64/rockchip/rk3568_combphy.c

283

bus_write_4(sc->mem, PHYREG16, PHYREG16_SSC_CNT_VALUE);

sys/arm64/rockchip/rk3568_combphy.c

298

bus_write_4(sc->mem, PHYREG33,

sys/arm64/rockchip/rk3568_combphy.c

303

bus_write_4(sc->mem, PHYREG12,

sys/arm64/rockchip/rk3568_combphy.c

307

bus_write_4(sc->mem, PHYREG6,

sys/arm64/rockchip/rk3568_combphy.c

312

bus_write_4(sc->mem, PHYREG18, PHYREG18_PLL_LOOP);

sys/arm64/rockchip/rk3568_combphy.c

315

bus_write_4(sc->mem, PHYREG11, PHYREG11_SU_TRIM_0_7);

sys/arm64/rockchip/rk3568_combphy.c

319

bus_write_4(sc->mem, PHYREG32,

sys/arm64/rockchip/rk3568_combphy.c

335

bus_write_4(sc->mem, PHYREG8,

sys/arm64/rockchip/rk3568_pcie.c

203

bus_write_4(sc->apb_res, PCIE_CLIENT_HOT_RESET_CTRL,

sys/arm64/rockchip/rk3568_pcie.c

205

bus_write_4(sc->apb_res, PCIE_CLIENT_GENERAL_CON,

sys/arm64/rockchip/rk3568_pcie.c

213

bus_write_4(sc->apb_res, PCIE_CLIENT_GENERAL_CON,

sys/arm64/rockchip/rk3568_pcie.c

245

bus_write_4(sc->apb_res, PCIE_CLIENT_INTR_MASK_MSG_RX, 0x7fff0000);

sys/arm64/rockchip/rk3568_pcie.c

248

bus_write_4(sc->apb_res, PCIE_CLIENT_INTR_MASK_LEGACY, 0x00ff0000);

sys/arm64/rockchip/rk3568_pcie.c

251

bus_write_4(sc->apb_res, PCIE_CLIENT_INTR_MASK_ERR, 0x0fff0000);

sys/arm64/rockchip/rk_i2s.c

164

#define RK_I2S_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))

sys/arm64/rockchip/rk_otp.c

104

bus_write_4(sc->mem, OTPC_SBPI_CTRL,

sys/arm64/rockchip/rk_otp.c

106

bus_write_4(sc->mem, OTPC_SBPI_CMD_VALID_PRE,

sys/arm64/rockchip/rk_otp.c

108

bus_write_4(sc->mem, OTPC_SBPI_CMD0_OFFSET,

sys/arm64/rockchip/rk_otp.c

111

bus_write_4(sc->mem, OTPC_SBPI_CMD1_OFFSET, SBPI_ECC_ENABLE);

sys/arm64/rockchip/rk_otp.c

113

bus_write_4(sc->mem, OTPC_SBPI_CMD1_OFFSET, SBPI_ECC_DISABLE);

sys/arm64/rockchip/rk_otp.c

114

bus_write_4(sc->mem, OTPC_SBPI_CTRL, SBPI_ENABLE_MASK | SBPI_ENABLE);

sys/arm64/rockchip/rk_otp.c

134

bus_write_4(sc->mem, OTPC_USER_CTRL, OTPC_USER | OTPC_USER_MASK);

sys/arm64/rockchip/rk_otp.c

137

bus_write_4(sc->mem, OTPC_USER_ADDR,

sys/arm64/rockchip/rk_otp.c

139

bus_write_4(sc->mem, OTPC_USER_ENABLE,

sys/arm64/rockchip/rk_otp.c

148

bus_write_4(sc->mem, OTPC_USER_CTRL, OTPC_USER_MASK);

sys/arm64/rockchip/rk_otp.c

96

bus_write_4(sc->mem, OTPC_SBPI_INT_STATUS, status);

sys/arm64/rockchip/rk_pcie.c

179

#define APB_WR4(_sc, _r, _v) bus_write_4((_sc)->apb_mem_res, (_r), (_v))

sys/arm64/rockchip/rk_pcie.c

286

bus_write_4(sc->apb_mem_res, base + reg, val);

sys/arm64/rockchip/rk_pcie.c

292

bus_write_4(sc->apb_mem_res, base + (reg & ~3), val2);

sys/arm64/rockchip/rk_pcie.c

298

bus_write_4(sc->apb_mem_res, base + (reg & ~3), val2);

sys/arm64/rockchip/rk_tsadc.c

100

#define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))

sys/arm64/rockchip/rk_typec_phy.c

135

#define RK_TYPEC_PHY_WRITE(sc, reg, val) bus_write_4(sc->res, (reg), (val))

sys/arm64/rockchip/rk_usbphy.c

67

#define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))

sys/dev/acpica/acpi_apei.c

141

bus_write_4(res, offset, val);

sys/dev/acpica/acpi_apei.c

142

bus_write_4(res, offset + 4, val >> 32);

sys/dev/acpica/acpi_hpet.c

191

bus_write_4(sc->mem_res, HPET_CONFIG, val);

sys/dev/acpica/acpi_hpet.c

201

bus_write_4(sc->mem_res, HPET_CONFIG, val);

sys/dev/acpica/acpi_hpet.c

225

bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num);

sys/dev/acpica/acpi_hpet.c

232

bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),

sys/dev/acpica/acpi_hpet.c

234

bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),

sys/dev/acpica/acpi_hpet.c

236

bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),

sys/dev/acpica/acpi_hpet.c

240

bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),

sys/dev/acpica/acpi_hpet.c

242

bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),

sys/dev/acpica/acpi_hpet.c

263

bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps);

sys/dev/acpica/acpi_hpet.c

294

bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),

sys/dev/acpica/acpi_hpet.c

305

bus_write_4(sc->mem_res,

sys/dev/acpica/acpi_hpet.c

324

bus_write_4(sc->mem_res, HPET_ISR, val);

sys/dev/acpica/acpi_hpet.c

732

bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff);

sys/dev/acpica/acpi_hpet.c

771

bus_write_4(sc->mem_res,

sys/dev/acpica/acpi_hpet.c

773

bus_write_4(sc->mem_res,

sys/dev/acpica/acpi_hpet.c

784

bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps);

sys/dev/acpica/acpi_hpet.c

897

bus_write_4(sc->mem_res,

sys/dev/acpica/acpi_hpet.c

899

bus_write_4(sc->mem_res,

sys/dev/acpica/acpi_hpet.c

911

bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),

sys/dev/acpica/acpi_hpet.c

913

bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),

sys/dev/acpica/acpi_hpet.c

916

bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),

sys/dev/acpica/acpi_hpet.c

920

bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),

sys/dev/acpica/acpi_hpet.c

923

bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num);

sys/dev/acpica/acpi_hpet.c

924

bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps);

sys/dev/acpica/acpi_hpet.c

978

bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr);

sys/dev/acpica/acpi_hpet.c

979

bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data);

sys/dev/adlink/adlink.c

139

bus_write_4(sc->res[0], 0x38, u | 0x003f4000);

sys/dev/adlink/adlink.c

157

bus_write_4(sc->res[0], 0x24, pg->phys);

sys/dev/adlink/adlink.c

158

bus_write_4(sc->res[0], 0x28, sc->p0->chunksize);

sys/dev/adlink/adlink.c

279

bus_write_4(sc->res[0], 0x38, 0x00004000);

sys/dev/adlink/adlink.c

282

bus_write_4(sc->res[1], 0x00, 1);

sys/dev/adlink/adlink.c

285

bus_write_4(sc->res[1], 0x04, sc->p0->divisor);

sys/dev/adlink/adlink.c

288

bus_write_4(sc->res[1], 0x08, 0);

sys/dev/adlink/adlink.c

291

bus_write_4(sc->res[1], 0x0c, 0);

sys/dev/adlink/adlink.c

294

bus_write_4(sc->res[1], 0x10, 0);

sys/dev/adlink/adlink.c

297

bus_write_4(sc->res[1], 0x18, 3);

sys/dev/adlink/adlink.c

300

bus_write_4(sc->res[1], 0x20, 2);

sys/dev/adlink/adlink.c

308

bus_write_4(sc->res[0], 0x24, pg->phys);

sys/dev/adlink/adlink.c

309

bus_write_4(sc->res[0], 0x28, sc->p0->chunksize);

sys/dev/adlink/adlink.c

311

bus_write_4(sc->res[0], 0x3c, u | 0x00000600);

sys/dev/adlink/adlink.c

314

bus_write_4(sc->res[1], 0x1c, 1);

sys/dev/ae/if_ae.c

195

bus_write_4((sc)->mem[0], (reg), (val))

sys/dev/age/if_agevar.h

237

bus_write_4((_sc)->age_res[0], (reg), (val))

sys/dev/agp/agp_i810.c

1137

bus_write_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2, pgetbl_ctl2);

sys/dev/agp/agp_i810.c

1143

bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgetbl_ctl);

sys/dev/agp/agp_i810.c

1200

bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,

sys/dev/agp/agp_i810.c

1216

bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);

sys/dev/agp/agp_i810.c

1329

bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 0);

sys/dev/agp/agp_i810.c

1342

bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);

sys/dev/agp/agp_i810.c

1377

bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,

sys/dev/agp/agp_i810.c

1490

bus_write_4(sc->sc_res[0], AGP_I810_GTT + index * 4, pte);

sys/dev/agp/agp_i810.c

1525

bus_write_4(sc->sc_res[1], index * 4, pte);

sys/dev/agp/agp_i810.c

1548

bus_write_4(sc->sc_res[0], index * 4 + (512 * 1024), pte);

sys/dev/agp/agp_i810.c

1571

bus_write_4(sc->sc_res[0], index * 4 + (2 * 1024 * 1024), pte);

sys/dev/agp/agp_i810.c

1853

bus_write_4(sc->sc_res[0],

sys/dev/agp/agp_i810.c

2009

bus_write_4(sc->sc_res[0], AGP_I830_HIC, hic | (1U << 31));

sys/dev/ahci/ahci.h

572

bus_write_4((res), (offset), (value))

sys/dev/alc/if_alcvar.h

260

bus_write_4((_sc)->alc_res[0], (reg), (val))

sys/dev/ale/if_alevar.h

229

bus_write_4((_sc)->ale_res[0], (reg), (val))

sys/dev/amdgpio/amdgpio.c

76

bus_write_4(sc->sc_res[0], off, val);

sys/dev/amdsbwd/amdsbwd.c

155

bus_write_4(sc->res_ctrl, 0, val);

sys/dev/amdsbwd/amdsbwd.c

167

bus_write_4(sc->res_count, 0, val);

sys/dev/ata/ata-all.h

526

bus_write_4((res), (offset), (value))

sys/dev/axgbe/xgbe-common.h

1513

bus_write_4((_pdata)->xgmac_res, _reg, (_val))

sys/dev/axgbe/xgbe-common.h

1538

bus_write_4((_pdata)->xgmac_res, \

sys/dev/axgbe/xgbe-common.h

1589

bus_write_4((_pdata)->xpcs_res, (_off), _val)

sys/dev/axgbe/xgbe-common.h

1698

bus_write_4((_pdata)->xgmac_res, _reg + XGBE_MAC_PROP_OFFSET, \

sys/dev/axgbe/xgbe-common.h

1732

bus_write_4((_pdata)->xgmac_res, _reg + XGBE_I2C_CTRL_OFFSET, \

sys/dev/bfe/if_bfereg.h

446

#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->bfe_res, reg, val)

sys/dev/bge/if_bgereg.h

2250

bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val)

sys/dev/bge/if_bgereg.h

2804

bus_write_4(sc->bge_res, reg, val)

sys/dev/bge/if_bgereg.h

2816

bus_write_4(sc->bge_res2, reg, val)

sys/dev/bhnd/bhnd.h

1669

bus_write_4((r)->res, (o), (v)) : \

sys/dev/bhnd/bhndb/bhndb_pci.c

1606

return (bus_write_4(r, res_offset, value));

sys/dev/bhnd/bhndb/bhndb_pci.c

727

bus_write_4(r, r_offset, value);

sys/dev/bhnd/cores/chipc/chipc_spi.h

83

#define SPI_WRITE(sc, reg, val) bus_write_4(sc->sc_res, (reg), (val));

sys/dev/bwn/if_bwnvar.h

81

(bus_write_4((mac)->mac_sc->sc_mem_res, (o), (v)))

sys/dev/cadence/if_cgem.c

221

#define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val)))

sys/dev/cesa/cesa.h

94

bus_write_4((sc)->sc_res[RES_CESA_REGS], (reg), (val))

sys/dev/cesa/cesa.h

99

bus_write_4((sc)->sc_res[RES_TDMA_REGS], (reg), (val))

sys/dev/clk/allwinner/aw_ccung.c

74

#define CCU_WRITE4(sc, reg, val) bus_write_4((sc)->res, (reg), (val))

sys/dev/clk/rockchip/rk_cru.c

68

#define CCU_WRITE4(sc, reg, val) bus_write_4((sc)->res, (reg), (val))

sys/dev/clk/starfive/jh7110_clk.c

48

bus_write_4(_sc->mem_res, _off, _val)

sys/dev/cxgbe/adapter.h

1285

bus_write_4(sc->regs_res, reg, val);

sys/dev/cxgbe/adapter.h

1310

bus_write_4(sc->regs_res, reg, val);

sys/dev/cxgbe/adapter.h

1311

bus_write_4(sc->regs_res, reg + 4, val>> 32);

sys/dev/cxgbe/t4_main.c

2664

bus_write_4(sc->regs_res, A_PL_RST,

sys/dev/dpaa/if_dtsec.c

335

bus_write_4(sc->sc_mem, DTSEC_REG_MAXFRM, mtu);

sys/dev/dpaa/if_dtsec.c

359

bus_write_4(sc->sc_mem, DTSEC_REG_GADDR(i), 0xFFFFFFFF);

sys/dev/dpaa2/dpaa2_mc.c

74

#define mcreg_write_4(_sc, _r, _v) bus_write_4(&(_sc)->map[1], (_r), (_v))

sys/dev/dpaa2/dpaa2_swp.c

1023

bus_write_4(map, offset + 4, p32[1]);

sys/dev/dpaa2/dpaa2_swp.c

1106

bus_write_4(map, offset + 4, cmd_pdat32[1]);

sys/dev/dpaa2/dpaa2_swp.c

352

bus_write_4(swp->cinh_map, o, v);

sys/dev/dpaa2/dpaa2_swp.c

876

bus_write_4(map,

sys/dev/dpaa2/dpaa2_swp.c

971

bus_write_4(map, offset + 4, cmd_pdat32[1]);

sys/dev/dpaa2/memac_mdio_common.c

168

bus_write_4(sc->mem_res, reg, v);

sys/dev/dwc/if_dwcvar.h

121

bus_write_4((_sc)->res[0], _reg, _val)

sys/dev/dwwdt/dwwdt.c

63

bus_write_4((sc)->sc_mem_res, (reg), (val))

sys/dev/enetc/enetc.h

106

bus_write_4((sc)->regs, reg, value)

sys/dev/enetc/enetc.h

113

bus_write_4((sc)->regs, ENETC_PORT_BASE + (reg), value)

sys/dev/enetc/enetc_mdio.c

44

bus_write_4((regs), (base) + (off), (value))

sys/dev/eqos/if_eqos.c

98

#define WR4(sc, o, v) bus_write_4(sc->res[EQOS_RES_MEM], (o), (v))

sys/dev/eqos/if_eqos_fdt.c

84

#define WR4(sc, o, v) bus_write_4(sc->res[EQOS_RES_MEM], (o), (v))

sys/dev/eqos/if_eqos_starfive.c

42

#define WR4(sc, o, v) bus_write_4(sc->base.res[EQOS_RES_MEM], (o), (v))

sys/dev/et/if_etvar.h

69

bus_write_4((sc)->sc_mem_res, (reg), (val))

sys/dev/etherswitch/ar40xx/ar40xx_var.h

38

bus_write_4(sc->sc_ess_mem_res, (reg), (val)); \

sys/dev/etherswitch/felix/felix_var.h

49

#define FELIX_WR4(sc, reg, value) bus_write_4((sc)->regs, reg, value)

sys/dev/etherswitch/mtkswitch/mtkswitchvar.h

131

bus_write_4((_sc)->sc_res, (_reg), (_val))

sys/dev/fdt/simple_mfd.c

102

bus_write_4(sc->mem_res, offset, val);

sys/dev/fdt/simple_mfd.c

118

bus_write_4(sc->mem_res, offset, val);

sys/dev/ffec/if_ffec.c

235

bus_write_4(sc->mem_res, off, val);

sys/dev/flash/cqspi.c

83

#define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val)

sys/dev/flash/cqspi.c

88

#define WRITE_DATA_4(_sc, _reg, _val) bus_write_4((_sc)->res[1], _reg, _val)

sys/dev/flash/flexspi/flex_spi.c

143

bus_write_4(sc->mem_res, offset, (value));

sys/dev/fxp/if_fxpvar.h

249

#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->fxp_res[0], reg, val)

sys/dev/glxiic/glxiic.c

1012

bus_write_4(sc->gpio_res, GLXIIC_GPIOL_IN_AUX1_SEL,

sys/dev/glxiic/glxiic.c

1014

bus_write_4(sc->gpio_res, GLXIIC_GPIOL_OUT_AUX1_SEL,

sys/dev/glxiic/glxiic.c

1022

bus_write_4(sc->gpio_res, GLXIIC_GPIOL_OUT_AUX1_SEL,

sys/dev/glxiic/glxiic.c

1024

bus_write_4(sc->gpio_res, GLXIIC_GPIOL_IN_AUX1_SEL,

sys/dev/glxsb/glxsb.c

297

bus_write_4(sc->sc_sr, SB_AES_INT, SB_AI_CLEAR_INTR);

sys/dev/glxsb/glxsb.c

568

bus_write_4(sc->sc_sr, SB_SOURCE_A, psrc);

sys/dev/glxsb/glxsb.c

571

bus_write_4(sc->sc_sr, SB_DEST_A, pdst);

sys/dev/glxsb/glxsb.c

574

bus_write_4(sc->sc_sr, SB_LENGTH_A, len);

sys/dev/glxsb/glxsb.c

586

bus_write_4(sc->sc_sr, SB_CTL_A,

sys/dev/goldfish/goldfish_rtc.c

159

bus_write_4(sc->res, GOLDFISH_RTC_TIME_HIGH, nsec >> 32);

sys/dev/goldfish/goldfish_rtc.c

160

bus_write_4(sc->res, GOLDFISH_RTC_TIME_LOW, nsec);

sys/dev/gpio/bytgpio.c

304

bus_write_4(sc->sc_mem_res, off, val);

sys/dev/gpio/chvgpio.c

126

bus_write_4(sc->sc_mem_res, chvgpio_pad_cfg0_offset(pin), val);

sys/dev/gpio/chvgpio.c

441

bus_write_4(sc->sc_mem_res, CHVGPIO_INTERRUPT_MASK, 0);

sys/dev/gpio/chvgpio.c

442

bus_write_4(sc->sc_mem_res, CHVGPIO_INTERRUPT_STATUS, 0xffff);

sys/dev/gpio/chvgpio.c

469

bus_write_4(sc->sc_mem_res, CHVGPIO_INTERRUPT_STATUS, 1 << line);

sys/dev/gpio/dwgpio/dwgpio_bus.c

128

bus_write_4(sc->res[0], offset, val);

sys/dev/gpio/qoriq_gpio.c

116

bus_write_4(sc->sc_mem, GPIO_GPDIR, reg);

sys/dev/gpio/qoriq_gpio.c

121

bus_write_4(sc->sc_mem, GPIO_GPDIR, reg);

sys/dev/gpio/qoriq_gpio.c

127

bus_write_4(sc->sc_mem, GPIO_GPODR, reg);

sys/dev/gpio/qoriq_gpio.c

188

bus_write_4(sc->sc_mem, GPIO_GPDAT, outvals);

sys/dev/gpio/qoriq_gpio.c

223

bus_write_4(sc->sc_mem, GPIO_GPDAT, val);

sys/dev/gpio/qoriq_gpio.c

263

bus_write_4(sc->sc_mem, GPIO_GPDAT,

sys/dev/gpio/qoriq_gpio.c

313

bus_write_4(sc->sc_mem, GPIO_GPDIR, reg);

sys/dev/gpio/qoriq_gpio.c

316

bus_write_4(sc->sc_mem, GPIO_GPODR, reg);

sys/dev/gpio/qoriq_gpio.c

378

bus_write_4(sc->sc_mem, GPIO_GPIBE, 0xffffffff);

sys/dev/gve/gve_utils.c

43

bus_write_4(priv->reg_bar, offset, htobe32(val));

sys/dev/gve/gve_utils.c

49

bus_write_4(priv->db_bar, offset, htobe32(val));

sys/dev/gve/gve_utils.c

55

bus_write_4(priv->db_bar, offset, val);

sys/dev/hwpmc/pmu_dmc620.c

70

#define WR4(sc, r, v) bus_write_4((sc)->sc_res[0], (r), (v))

sys/dev/ichiic/ig4_iic.c

162

bus_write_4(sc->regs_res, reg, value);

sys/dev/ichwd/i6300esbwd.c

137

bus_write_4(sc->res, WDT_PRELOAD_1_REG, timeout);

sys/dev/ichwd/i6300esbwd.c

140

bus_write_4(sc->res, WDT_PRELOAD_2_REG, timeout);

sys/dev/ichwd/ichwd.c

325

bus_write_4((sc)->tco_res, (off), (val))

sys/dev/ichwd/ichwd.c

327

bus_write_4((sc)->smi_res, (off), (val))

sys/dev/ichwd/ichwd.c

329

bus_write_4((sc)->gcs_res, (off), (val))

sys/dev/ichwd/ichwd.c

332

bus_write_4((sc)->gcs_res, (off), (val))

sys/dev/ichwd/ichwd.c

334

bus_write_4((sc)->gc_res, (off), (val))

sys/dev/ida/idavar.h

48

bus_write_4((ida)->regs, port, val)

sys/dev/iicbus/controller/qcom/geni_iic.c

126

#define WR(sc, reg, val) bus_write_4((sc)->regs_res, reg, val)

sys/dev/iicbus/controller/rockchip/rk_i2c.c

163

#define RK_I2C_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))

sys/dev/iicbus/controller/twsi/twsi.c

112

bus_write_4(sc->res[0], off, val);

sys/dev/intel/spi.c

73

bus_write_4((_sc)->sc_mem_res, (_off), (_val))

sys/dev/ips/ips.h

65

#define ips_write_4(sc,offset,value) bus_write_4(sc->iores, offset, value)

sys/dev/ismt/ismt.c

186

bus_write_4(sc->mmio_res, ISMT_MSTR_MSTS, val);

sys/dev/ismt/ismt.c

264

bus_write_4(sc->mmio_res, ISMT_MSTR_MCTRL, val);

sys/dev/ismt/ismt.c

269

bus_write_4(sc->mmio_res, ISMT_MSTR_MCTRL, val);

sys/dev/ismt/ismt.c

640

bus_write_4(sc->mmio_res, ISMT_MSTR_MDBA,

sys/dev/ismt/ismt.c

642

bus_write_4(sc->mmio_res, ISMT_MSTR_MDBA + 4,

sys/dev/ismt/ismt.c

646

bus_write_4(sc->mmio_res, ISMT_MSTR_MCTRL, ISMT_MCTRL_MEIE);

sys/dev/ismt/ismt.c

649

bus_write_4(sc->mmio_res, ISMT_MSTR_MSTS, 0);

sys/dev/ismt/ismt.c

655

bus_write_4(sc->mmio_res, ISMT_MSTR_MDS, val);

sys/dev/isp/isp_pci.c

717

#define BXW4(isp, off, v) bus_write_4((isp)->isp_regs, (off), (v))

sys/dev/isp/isp_pci.c

719

#define B2W4(isp, off, v) bus_write_4((isp)->isp_regs2, (off), (v))

sys/dev/jme/if_jmevar.h

230

bus_write_4((_sc)->jme_res[0], (reg), (val))

sys/dev/mailbox/arm/arm_doorbell.c

110

bus_write_4(sc->res[0], MHU_CHAN_RX_HP + MHU_INTR_CLEAR,

sys/dev/mailbox/arm/arm_doorbell.c

287

bus_write_4(sc->res[0], offset + MHU_INTR_SET, (1 << db->db));

sys/dev/mailbox/arm/arm_doorbell.c

315

bus_write_4(sc->res[0], offset + MHU_INTR_CLEAR,

sys/dev/mailbox/arm/arm_doorbell.c

88

bus_write_4(sc->res[0], MHU_CHAN_RX_LP + MHU_INTR_CLEAR,

sys/dev/mgb/if_mgb.h

234

bus_write_4((sc)->regs, reg, val)

sys/dev/mge/if_mgevar.h

120

#define MGE_WRITE(sc,reg,val) bus_write_4((sc)->res[0], (reg), (val))

sys/dev/mlx/mlxreg.h

122

#define MLX_V4_PUT_IDBR(sc, val) bus_write_4(sc->mlx_mem, MLX_V4_IDBR, val)

sys/dev/mlx/mlxreg.h

124

#define MLX_V4_PUT_ODBR(sc, val) bus_write_4(sc->mlx_mem, MLX_V4_ODBR, val)

sys/dev/mlx/mlxreg.h

125

#define MLX_V4_PUT_IER(sc, val) bus_write_4(sc->mlx_mem, MLX_V4_IER, val)

sys/dev/mmc/host/dwmmc.c

91

bus_write_4((_sc)->res[0], _reg, _val)

sys/dev/mmc/host/dwmmc_samsung.c

46

bus_write_4((_sc)->res[0], _reg, _val)

sys/dev/msk/if_mskreg.h

2125

bus_write_4((sc)->msk_res[0], (reg), (val))

sys/dev/msk/if_mskreg.h

2139

bus_write_4((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val))

sys/dev/mvs/mvs.h

652

bus_write_4((res), (offset), (value));

sys/dev/neta/if_mvnetavar.h

63

bus_write_4((sc)->res[0], (reg), (val))

sys/dev/netmap/if_ptnet.c

1089

bus_write_4(sc->iomem, PTNET_IO_PTCTL, cmd);

sys/dev/netmap/if_ptnet.c

1150

bus_write_4(sc->iomem, PTNET_IO_VNET_HDR_LEN, wanted_hdr_len);

sys/dev/netmap/if_ptnet.c

264

bus_write_4(pq->sc->iomem, pq->kick, 0);

sys/dev/netmap/if_ptnet.c

311

bus_write_4(sc->iomem, PTNET_IO_PTFEAT, ptfeatures); /* wanted */

sys/dev/netmap/if_ptnet.c

346

bus_write_4(sc->iomem, PTNET_IO_CSB_GH_BAH,

sys/dev/netmap/if_ptnet.c

348

bus_write_4(sc->iomem, PTNET_IO_CSB_GH_BAL,

sys/dev/netmap/if_ptnet.c

351

bus_write_4(sc->iomem, PTNET_IO_CSB_HG_BAH,

sys/dev/netmap/if_ptnet.c

353

bus_write_4(sc->iomem, PTNET_IO_CSB_HG_BAL,

sys/dev/netmap/if_ptnet.c

495

bus_write_4(sc->iomem, PTNET_IO_CSB_GH_BAH, 0);

sys/dev/netmap/if_ptnet.c

496

bus_write_4(sc->iomem, PTNET_IO_CSB_GH_BAL, 0);

sys/dev/netmap/if_ptnet.c

497

bus_write_4(sc->iomem, PTNET_IO_CSB_HG_BAH, 0);

sys/dev/netmap/if_ptnet.c

498

bus_write_4(sc->iomem, PTNET_IO_CSB_HG_BAL, 0);

sys/dev/nfe/if_nfereg.h

292

bus_write_4((sc)->nfe_res[0], (reg), (val))

sys/dev/nge/if_ngereg.h

674

bus_write_4((sc)->nge_res, reg, val)

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

123

bus_write_4((sc)->conf_res, PLX_NTX_OUR_BASE(sc) + (reg), (val))

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

129

bus_write_4((sc)->conf_res, PLX_NTX_PEER_BASE(sc) + (reg), (val))

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

136

bus_write_4((sc)->mw_info[(sc)->b2b_mw].mw_res, \

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

443

bus_write_4(sc->conf_res, sc->spad_off2, 0x12345678);

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

456

bus_write_4(sc->conf_res, sc->spad_off2, 0x12345678);

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

573

bus_write_4(sc->conf_res, reg, val);

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

590

bus_write_4(sc->conf_res, reg, val);

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

783

bus_write_4(sc->conf_res, val, eaddr);

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

784

bus_write_4(sc->conf_res, val + 0x400, eaddr >> 32);

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

785

bus_write_4(sc->conf_res, val + 0x800,

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

889

bus_write_4(sc->conf_res, off, val);

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

899

bus_write_4(sc->conf_res, off, val);

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

952

bus_write_4(sc->mw_info[sc->b2b_mw].mw_res, off, val);

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

954

bus_write_4(sc->conf_res, off, val);

sys/dev/nvme/nvme_private.h

332

bus_write_4((sc)->resource, nvme_mmio_offsetof(reg), val)

sys/dev/nvme/nvme_private.h

336

bus_write_4((sc)->resource, nvme_mmio_offsetof(reg), \

sys/dev/nvme/nvme_private.h

338

bus_write_4((sc)->resource, nvme_mmio_offsetof(reg) + 4, \

sys/dev/nvme/nvme_qpair.c

1071

bus_write_4(ctrlr->resource, qpair->sq_tdbl_off, qpair->sq_tail);

sys/dev/nvme/nvme_qpair.c

479

bus_write_4(qpair->ctrlr->resource, qpair->cq_hdbl_off,

sys/dev/p2sb/p2sb.c

99

bus_write_4(sc->res, P2SB_PORT_ADDRESS(port) + reg, val);

sys/dev/pci/pci.c

1703

bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);

sys/dev/pci/pci.c

1704

bus_write_4(msix->msix_table_res, offset + 4, address >> 32);

sys/dev/pci/pci.c

1705

bus_write_4(msix->msix_table_res, offset + 8, data);

sys/dev/pci/pci.c

1752

bus_write_4(msix->msix_table_res, offset, val);

sys/dev/pci/pci.c

1771

bus_write_4(msix->msix_table_res, offset, val);

sys/dev/pci/pci.c

3654

bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR);

sys/dev/pci/pci.c

3663

bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET);

sys/dev/pci/pci.c

3666

bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);

sys/dev/pci/pci.c

3747

bus_write_4(res, offs + EHCI_USBINTR, 0);

sys/dev/pci/pci.c

3808

bus_write_4(res, offs + XHCI_USBCMD, 0);

sys/dev/pci/pci_dw.c

121

bus_write_4(sc->dbi_res, reg, val);

sys/dev/pci/pci_dw.c

603

bus_write_4(res, reg, val);

sys/dev/pci/pci_dw.c

72

bus_write_4((sc)->iatu_ur_res, (sc)->iatu_ur_offset + (reg), (val))

sys/dev/pci/pci_host_generic.c

356

bus_write_4(sc->res, offset, htole32(val));

sys/dev/pci/pci_user.c

1092

bus_write_4(res, offset, pbi->pbi_value);

sys/dev/proto/proto_core.c

430

bus_write_4(r->r_d.res, ofs, buf.x4[0]);

sys/dev/pwm/controller/allwinner/aw_pwm.c

110

#define AW_PWM_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val))

sys/dev/pwm/controller/rockchip/rk_pwm.c

124

#define RK_PWM_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val))

sys/dev/qat/include/common/adf_accel_devices.h

478

bus_write_4(csr_base, csr_offset, val)

sys/dev/qat/include/common/adf_accel_devices.h

488

bus_write_4(csr_base, offset, (uint32_t)value);

sys/dev/qat/include/common/adf_accel_devices.h

489

bus_write_4(csr_base, offset + 4, (uint32_t)(value >> 32));

sys/dev/qcom_ess_edma/qcom_ess_edma_var.h

47

bus_write_4(sc->sc_mem_res, (reg), (val)); \

sys/dev/qcom_gcc/qcom_gcc_clock.c

63

bus_write_4(sc->reg, addr, val);

sys/dev/qcom_gcc/qcom_gcc_clock.c

78

bus_write_4(sc->reg, addr, reg);

sys/dev/qcom_gcc/qcom_gcc_ipq4018_reset.c

149

bus_write_4(sc->reg, gcc_ipq4019_reset_list[id].reg, reg);

sys/dev/qcom_mdio/qcom_mdio_ipq4018_var.h

40

bus_write_4(sc->sc_mem_res, (reg), (val)); \

sys/dev/qcom_qup/qcom_spi_var.h

117

#define QCOM_SPI_WRITE_4(sc, reg, val) bus_write_4((sc)->sc_mem_res, \

sys/dev/qcom_rnd/qcom_rnd.c

152

bus_write_4(sc->reg, QCOM_RND_PRNG_LFSR_CFG, reg);

sys/dev/qcom_rnd/qcom_rnd.c

157

bus_write_4(sc->reg, QCOM_RND_PRNG_CONFIG, reg);

sys/dev/qcom_tcsr/qcom_tcsr_var.h

32

#define QCOM_TCSR_WRITE_4(sc, reg, val) bus_write_4((sc)->sc_mem_res, \

sys/dev/qcom_tlmm/qcom_tlmm_var.h

41

bus_write_4(sc->gpio_mem_res, (reg), (val)); \

sys/dev/qlnx/qlnxe/qlnx_os.c

2999

bus_write_4(ha->pci_dbells, offset, value);

sys/dev/qlnx/qlnxe/qlnx_os.c

5161

bus_write_4(((qlnx_host_t *)p_hwfn->p_dev)->pci_reg, \

sys/dev/qlnx/qlnxe/qlnx_os.c

5189

bus_write_4(((qlnx_host_t *)cdev)->pci_dbells, offset, value);

sys/dev/qlnx/qlnxe/qlnx_os.c

5199

bus_write_4(((qlnx_host_t *)p_hwfn->p_dev)->pci_dbells, \

sys/dev/qlnx/qlnxe/qlnx_os.c

5229

bus_write_4(((qlnx_host_t *)cdev)->pci_reg, offset, value);

sys/dev/qlnx/qlnxr/qlnxr_verbs.c

3264

bus_write_4(ha->pci_dbells, reg_addr, qp->rq.db_data.raw);

sys/dev/qlnx/qlnxr/qlnxr_verbs.c

3270

bus_write_4(ha->pci_dbells, reg_addr,\

sys/dev/qlnx/qlnxr/qlnxr_verbs.c

4589

bus_write_4(ha->pci_dbells, reg_addr, qp->sq.db_data.raw);

sys/dev/qlnx/qlnxr/qlnxr_verbs.c

4721

bus_write_4(ha->pci_dbells, reg_addr, qp->rq.db_data.raw);

sys/dev/qlnx/qlnxr/qlnxr_verbs.c

4727

bus_write_4(ha->pci_dbells, reg_addr, \

sys/dev/qlxgb/qla_reg.h

233

bus_write_4((ha->pci_reg), reg, val);\

sys/dev/qlxgb/qla_reg.h

240

bus_write_4((ha->pci_reg), reg, val);\

sys/dev/qlxgb/qla_reg.h

245

bus_write_4((ha->pci_reg), off, val);\

sys/dev/qlxgbe/ql_hw.h

1716

bus_write_4((ha->pci_reg), prod_reg, val);

sys/dev/qlxgbe/ql_hw.h

1722

bus_write_4((ha->pci_reg), (ha->hw.sds[i].sds_consumer), val);

sys/dev/qlxgbe/ql_hw.h

1725

bus_write_4((ha->pci_reg), (ha->hw.intr_src[i]), 0);

sys/dev/qlxgbe/ql_hw.h

207

bus_write_4((ha->pci_reg), reg, val);\

sys/dev/qlxge/qls_hw.h

901

#define WRITE_REG32_ONLY(ha, reg, val) bus_write_4((ha->pci_reg), reg, val)

sys/dev/qlxge/qls_hw.h

903

#define WRITE_REG32(ha, reg, val) bus_write_4((ha->pci_reg), reg, val)

sys/dev/qlxge/qls_hw.h

919

#define Q81_WR_WQ_PROD_IDX(wq_idx, idx) bus_write_4((ha->pci_reg1),\

sys/dev/qlxge/qls_hw.h

925

#define Q81_SET_WQ_VALID(wq_idx) bus_write_4((ha->pci_reg1),\

sys/dev/qlxge/qls_hw.h

929

#define Q81_SET_WQ_INVALID(wq_idx) bus_write_4((ha->pci_reg1),\

sys/dev/qlxge/qls_hw.h

933

#define Q81_WR_CQ_CONS_IDX(cq_idx, idx) bus_write_4((ha->pci_reg1),\

sys/dev/qlxge/qls_hw.h

939

#define Q81_SET_CQ_VALID(cq_idx) bus_write_4((ha->pci_reg1),\

sys/dev/qlxge/qls_hw.h

943

#define Q81_SET_CQ_INVALID(cq_idx) bus_write_4((ha->pci_reg1),\

sys/dev/qlxge/qls_hw.h

947

#define Q81_WR_LBQ_PROD_IDX(cq_idx, idx) bus_write_4((ha->pci_reg1),\

sys/dev/qlxge/qls_hw.h

953

#define Q81_WR_SBQ_PROD_IDX(cq_idx, idx) bus_write_4((ha->pci_reg1),\

sys/dev/safexcel/safexcel_var.h

422

#define SAFEXCEL_WRITE(sc, off, val) bus_write_4((sc)->sc_res, (off), (val))

sys/dev/sdhci/fsl_sdhci.c

200

bus_write_4(sc->mem_res, off, val);

sys/dev/sdhci/sdhci_acpi.c

171

bus_write_4(sc->mem_res, off, val);

sys/dev/sdhci/sdhci_fdt.c

305

bus_write_4(sc->mem_res[slot->num], off, val);

sys/dev/sdhci/sdhci_fdt_cvitek.c

120

bus_write_4(res, CVI_CV181X_SDHCI_EMMC_CTRL, reg);

sys/dev/sdhci/sdhci_fdt_cvitek.c

121

bus_write_4(res, CVI_CV181X_SDHCI_PHY_TX_RX_DLY,

sys/dev/sdhci/sdhci_fdt_cvitek.c

123

bus_write_4(res, CVI_CV181X_SDHCI_PHY_CONFIG,

sys/dev/sdhci/sdhci_fdt_rockchip.c

177

bus_write_4(sc->mem_res[slot->num],

sys/dev/sdhci/sdhci_fdt_rockchip.c

179

bus_write_4(sc->mem_res[slot->num],

sys/dev/sdhci/sdhci_fdt_rockchip.c

181

bus_write_4(sc->mem_res[slot->num],

sys/dev/sdhci/sdhci_fdt_rockchip.c

183

bus_write_4(sc->mem_res[slot->num],

sys/dev/sdhci/sdhci_fdt_rockchip.c

188

bus_write_4(sc->mem_res[slot->num],

sys/dev/sdhci/sdhci_fdt_rockchip.c

191

bus_write_4(sc->mem_res[slot->num],

sys/dev/sdhci/sdhci_fdt_rockchip.c

193

bus_write_4(sc->mem_res[slot->num],

sys/dev/sdhci/sdhci_fdt_rockchip.c

204

bus_write_4(sc->mem_res[slot->num], RK3568_EMMC_ATCTRL,

sys/dev/sdhci/sdhci_fdt_rockchip.c

206

bus_write_4(sc->mem_res[slot->num],

sys/dev/sdhci/sdhci_fdt_rockchip.c

209

bus_write_4(sc->mem_res[slot->num],

sys/dev/sdhci/sdhci_fdt_rockchip.c

212

bus_write_4(sc->mem_res[slot->num],

sys/dev/sdhci/sdhci_fsl_fdt.c

268

bus_write_4(sc->mem_res, off, htobe32(val));

sys/dev/sdhci/sdhci_fsl_fdt.c

282

bus_write_4(sc->mem_res, off, val);

sys/dev/sdhci/sdhci_fsl_fdt.c

558

bus_write_4(sc->mem_res, off, val);

sys/dev/sdhci/sdhci_pci.c

233

bus_write_4(sc->mem_res[slot->num], off, val);

sys/dev/sdhci/sdhci_xenon.c

116

bus_write_4(sc->mem_res, off, val);

sys/dev/sdhci/sdhci_xenon.c

213

bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg);

sys/dev/sdhci/sdhci_xenon.c

217

bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg);

sys/dev/sdhci/sdhci_xenon.c

249

bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL, reg);

sys/dev/sdhci/sdhci_xenon.c

255

bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1, reg);

sys/dev/sdhci/sdhci_xenon.c

263

bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg);

sys/dev/sdhci/sdhci_xenon.c

273

bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL2, reg);

sys/dev/sdhci/sdhci_xenon.c

278

bus_write_4(sc->mem_res, SDHCI_CLOCK_CONTROL, reg);

sys/dev/sdhci/sdhci_xenon.c

297

bus_write_4(sc->mem_res, XENON_EMMC_PHY_FUNC_CONTROL, reg);

sys/dev/sdhci/sdhci_xenon.c

302

bus_write_4(sc->mem_res, SDHCI_CLOCK_CONTROL, reg);

sys/dev/sdhci/sdhci_xenon.c

305

bus_write_4(sc->mem_res, XENON_EMMC_PHY_LOGIC_TIMING_ADJUST,

sys/dev/sdhci/sdhci_xenon.c

311

bus_write_4(sc->mem_res, XENON_SLOT_EMMC_CTRL, reg);

sys/dev/sdhci/sdhci_xenon.c

316

bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1, reg);

sys/dev/sdhci/sdhci_xenon.c

370

bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);

sys/dev/sdhci/sdhci_xenon.c

549

bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);

sys/dev/sdhci/sdhci_xenon.c

553

bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);

sys/dev/sdhci/sdhci_xenon.c

558

bus_write_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL, reg);

sys/dev/sdhci/sdhci_xenon.c

562

bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);

sys/dev/sdhci/sdhci_xenon.c

567

bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);

sys/dev/sdhci/sdhci_xenon.c

572

bus_write_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL, reg);

sys/dev/sge/if_sge.c

180

#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sge_res, reg, val)

sys/dev/siis/siis.h

448

bus_write_4((res), (offset), (value))

sys/dev/sis/if_sis.c

118

#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val)

sys/dev/sk/if_skreg.h

1275

bus_write_4((sc)->sk_res[0], (reg), (val))

sys/dev/sound/macio/davbus.c

217

bus_write_4(d->reg, DAVBUS_CODEC_CTRL, data);

sys/dev/sound/macio/davbus.c

387

bus_write_4(d->reg, DAVBUS_CODEC_CTRL, x);

sys/dev/sound/macio/davbus.c

557

bus_write_4(sc->reg, DAVBUS_SOUND_CTRL, DAVBUS_INPUT_SUBFRAME0 |

sys/dev/sound/macio/davbus.c

593

bus_write_4(d->reg, DAVBUS_SOUND_CTRL, reg);

sys/dev/sound/macio/i2s.c

535

bus_write_4(sc->reg, I2S_WORDSIZE, wordformat);

sys/dev/spibus/controller/allwinner/aw_spi.c

162

#define AW_SPI_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))

sys/dev/spibus/controller/rockchip/rk_spi.c

124

#define RK_SPI_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))

sys/dev/ste/if_stereg.h

482

bus_write_4((sc)->ste_res, reg, val)

sys/dev/stge/if_stgereg.h

90

bus_write_4((_sc)->sc_res[0], (reg), (val))

sys/dev/sym/sym_hipd.c

850

#define OUTL_OFF(o, v) bus_write_4(np->io_res, (o), (v))

sys/dev/sym/sym_hipd.c

860

#define OUTL_OFF(o, v) bus_write_4(np->mmio_res, (o), (v))

sys/dev/syscon/syscon_generic.c

108

bus_write_4(sc->mem_res, offset, val);

sys/dev/syscon/syscon_generic.c

124

bus_write_4(sc->mem_res, offset, val);

sys/dev/tpm/tpm_bus.c

76

bus_write_4(sc->mem_res, off, val);

sys/dev/usb/controller/ehci_imx.c

161

bus_write_4(sc->mmio, index * sizeof(uint32_t), reg | bits);

sys/dev/usb/controller/ehci_imx.c

173

bus_write_4(sc->mmio, index * sizeof(uint32_t), reg & ~bits);

sys/dev/vge/if_vgevar.h

217

bus_write_4(sc->vge_res, reg, val)

sys/dev/viawd/viawd.c

47

bus_write_4((sc)->wd_res, (off), (val))

sys/dev/virtio/mmio/virtio_mmio.c

109

bus_write_4((sc)->res[0], (o), (v))

sys/dev/virtio/pci/virtio_pci_legacy.c

131

bus_write_4((sc)->vtpci_res, (o), (htole32(v)))

sys/dev/virtio/pci/virtio_pci_legacy.c

140

bus_write_4((sc)->vtpci_res, (o), (v))

sys/dev/virtio/pci/virtio_pci_modern.c

1345

bus_write_4(&sc->vtpci_common_res_map.vtrm_map,

sys/dev/virtio/pci/virtio_pci_modern.c

1433

bus_write_4(&sc->vtpci_device_res_map.vtrm_map, off, val);

sys/dev/vmd/vmd.c

213

return (bus_write_4(sc->vmd_regs_res[0], offset, val));

sys/dev/vmware/pvscsi/pvscsi.c

263

bus_write_4(sc->mm_res, offset, val);

sys/dev/vr/if_vrreg.h

749

#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->vr_res, reg, val)

sys/dev/xdma/controller/pl330.c

78

bus_write_4(_sc->res[0], _reg, _val)

sys/dev/xilinx/if_xae.c

74

#define XAE_WR4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val)

sys/dev/xilinx/if_xae.c

79

#define AXIDMA_WR4(_sc, _reg, _val) bus_write_4((_sc)->dma_res, _reg, _val)

sys/dev/xilinx/xlnx_pcib.c

124

bus_write_4(sc->res, XLNX_PCIE_RPERRFRR, ~0U);

sys/dev/xilinx/xlnx_pcib.c

198

bus_write_4(sc->res, XLNX_PCIE_IDR, val);

sys/dev/xilinx/xlnx_pcib.c

225

bus_write_4(sc->res, msireg, (1 << i));

sys/dev/xilinx/xlnx_pcib.c

296

bus_write_4(sc->res[0], XLNX_PCIE_IMR, 0);

sys/dev/xilinx/xlnx_pcib.c

300

bus_write_4(sc->res[0], XLNX_PCIE_IDR, reg);

sys/dev/xilinx/xlnx_pcib.c

306

bus_write_4(sc->res[0], XLNX_PCIE_RPMSIBR1, (addr >> 32));

sys/dev/xilinx/xlnx_pcib.c

307

bus_write_4(sc->res[0], XLNX_PCIE_RPMSIBR2, (addr >> 0));

sys/dev/xilinx/xlnx_pcib.c

312

bus_write_4(sc->res[0], XLNX_PCIE_RPSCR, reg);

sys/dev/xilinx/xlnx_pcib.c

332

bus_write_4(sc->res[0], XLNX_PCIE_IMR, reg);

sys/dev/xilinx/xlnx_pcib.c

704

bus_write_4(sc->res, msireg, reg);

sys/powerpc/amigaone/cpld_a1222.c

324

bus_write_4(sc->sc_mem, CPLD_MEM_DATA, *word);

sys/powerpc/amigaone/cpld_x5000.c

262

bus_write_4(sc->sc_mem, CPLD_MEM_DATA, *word);

sys/powerpc/mpc85xx/fsl_diu.c

206

bus_write_4(sc->res[0], DIU_INT_STATUS, reg);

sys/powerpc/mpc85xx/fsl_diu.c

248

bus_write_4(sc->res[0], DIU_DIU_MODE, reg);

sys/powerpc/mpc85xx/fsl_diu.c

256

bus_write_4(sc->res[0], DIU_GAMMA, vtophys(sc->sc_gamma));

sys/powerpc/mpc85xx/fsl_diu.c

257

bus_write_4(sc->res[0], DIU_CURSOR, vtophys(sc->sc_cursor));

sys/powerpc/mpc85xx/fsl_diu.c

258

bus_write_4(sc->res[0], DIU_CURS_POS, 0);

sys/powerpc/mpc85xx/fsl_diu.c

262

bus_write_4(sc->res[0], DIU_DISP_SIZE, reg);

sys/powerpc/mpc85xx/fsl_diu.c

267

bus_write_4(sc->res[0], DIU_HSYN_PARA, reg);

sys/powerpc/mpc85xx/fsl_diu.c

272

bus_write_4(sc->res[0], DIU_VSYN_PARA, reg);

sys/powerpc/mpc85xx/fsl_diu.c

274

bus_write_4(sc->res[0], DIU_BGND, 0);

sys/powerpc/mpc85xx/fsl_diu.c

277

bus_write_4(sc->res[0], DIU_INT_MASK, 0x3f);

sys/powerpc/mpc85xx/fsl_diu.c

282

bus_write_4(sc->res[0], DIU_DESC_1, vtophys(sc->sc_planes[0]));

sys/powerpc/mpc85xx/fsl_diu.c

283

bus_write_4(sc->res[0], DIU_DESC_2, 0);

sys/powerpc/mpc85xx/fsl_diu.c

284

bus_write_4(sc->res[0], DIU_DESC_3, 0);

sys/powerpc/mpc85xx/fsl_diu.c

319

bus_write_4(sc->res[0], DIU_PLUT, 0x1f5f666);

sys/powerpc/mpc85xx/fsl_diu.c

325

bus_write_4(sc->res[0], DIU_DIU_MODE, reg);

sys/powerpc/mpc85xx/fsl_espi.c

105

#define FSL_ESPI_WRITE(sc,off,val) bus_write_4(sc->sc_mem_res, off, val)

sys/powerpc/mpc85xx/fsl_sata.c

309

bus_write_4((res), (offset), (value))

sys/powerpc/mpc85xx/mpc85xx_cache.c

123

bus_write_4(sc->sc_mem, L2_CTL, L2CTL_L2E | L2CTL_L2I);

sys/powerpc/mpc85xx/mpc85xx_gpio.c

132

bus_write_4(sc->out_res, 0, outvals);

sys/powerpc/mpc85xx/mpc85xx_gpio.c

167

bus_write_4(sc->out_res, 0, val);

sys/powerpc/mpc85xx/platform_mpc85xx.c

597

bus_write_4(sc->sc_mem, RCPM_CTBENR, 0);

sys/powerpc/mpc85xx/platform_mpc85xx.c

599

bus_write_4(sc->sc_mem, RCPM_CTBENR, (1 << maxcpu) - 1);

sys/powerpc/mpc85xx/platform_mpc85xx.c

664

bus_write_4(sc->sc_mem, GUTS_DEVDISR,

sys/powerpc/mpc85xx/platform_mpc85xx.c

667

bus_write_4(sc->sc_mem, GUTS_DEVDISR,

sys/powerpc/powermac/ata_kauai.c

221

bus_write_4(sc->sc_memr, DMA_IRQ_REG, 0x80000000);

sys/powerpc/powermac/ata_kauai.c

304

bus_write_4(sc->sc_memr, 0, 0x00000007);

sys/powerpc/powermac/ata_kauai.c

363

bus_write_4(sc->sc_memr, UDMA_CONFIG_REG, sc->udmaconf[request->unit]);

sys/powerpc/powermac/ata_kauai.c

364

bus_write_4(sc->sc_memr, PIO_CONFIG_REG,

sys/powerpc/powermac/ata_macio.c

337

bus_write_4(sc->sc_mem, ATA_MACIO_TIMINGREG,

sys/powerpc/powermac/atibl.c

178

bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, tmp);

sys/powerpc/powermac/atibl.c

180

bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, save);

sys/powerpc/powermac/atibl.c

195

bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA, val);

sys/powerpc/powermac/atibl.c

201

bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, tmp);

sys/powerpc/powermac/atibl.c

203

bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, save);

sys/powerpc/powermac/atibl.c

226

bus_write_4(sc->sc_memr, RADEON_DISP_PWR_MAN, disp_pwr_reg);

sys/powerpc/powermac/atibl.c

229

bus_write_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);

sys/powerpc/powermac/atibl.c

231

bus_write_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);

sys/powerpc/powermac/atibl.c

242

bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);

sys/powerpc/powermac/atibl.c

249

bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);

sys/powerpc/powermac/atibl.c

252

bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);

sys/powerpc/powermac/dbdma.c

381

bus_write_4(chan->sc_regs, chan->sc_off + offset, val);

sys/powerpc/powermac/kiic.c

251

bus_write_4(sc->sc_reg, sc->sc_regstep * reg, val);

sys/powerpc/powermac/macgpio.c

386

bus_write_4(sc->sc_gpios, GPIO_LEVELS_0, sc->sc_saved_gpio_levels[0]);

sys/powerpc/powermac/macgpio.c

387

bus_write_4(sc->sc_gpios, GPIO_LEVELS_1, sc->sc_saved_gpio_levels[1]);

sys/powerpc/powermac/macio.c

418

bus_write_4(sc->sc_memr, HEATHROW_FCR, fcr);

sys/powerpc/powermac/macio.c

421

bus_write_4(sc->sc_memr, HEATHROW_FCR, fcr);

sys/powerpc/powermac/macio.c

424

bus_write_4(sc->sc_memr, HEATHROW_FCR, fcr);

sys/powerpc/powermac/macio.c

427

bus_write_4(sc->sc_memr, HEATHROW_FCR, fcr);

sys/powerpc/powermac/macio.c

440

bus_write_4(sc->sc_memr, KEYLARGO_FCR1, fcr1);

sys/powerpc/powermac/macio.c

741

bus_write_4(sc->sc_memr, KEYLARGO_FCR2, x);

sys/powerpc/powermac/macio.c

751

bus_write_4(sc->sc_memr, KEYLARGO_FCR2, x);

sys/powerpc/powermac/macio.c

759

bus_write_4(sc->sc_memr, 0x1c000, 0);

sys/powerpc/powermac/macio.c

762

bus_write_4(sc->sc_memr, 0x1a3e0, 0x41);

sys/powerpc/powermac/macio.c

765

bus_write_4(sc->sc_memr, KEYLARGO_FCR2, x);

sys/powerpc/powermac/macio.c

769

bus_write_4(sc->sc_memr, KEYLARGO_FCR2, x);

sys/powerpc/powernv/xive.c

682

bus_write_4(sc->sc_mem, XIVE_TM_QW2_HV_POOL + TM_WORD0, 0xff);

sys/powerpc/powernv/xive.c

683

bus_write_4(sc->sc_mem, XIVE_TM_QW2_HV_POOL + TM_WORD2,

sys/powerpc/powerpc/openpic.c

437

bus_write_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i), sc->sc_saved_ipis[i]);

sys/powerpc/powerpc/openpic.c

441

bus_write_4(sc->sc_memr, OPENPIC_PCPU_TPR(i), sc->sc_saved_prios[i]);

sys/powerpc/powerpc/openpic.c

445

bus_write_4(sc->sc_memr, OPENPIC_TCNT(i), sc->sc_saved_timers[i].tcnt);

sys/powerpc/powerpc/openpic.c

446

bus_write_4(sc->sc_memr, OPENPIC_TBASE(i), sc->sc_saved_timers[i].tbase);

sys/powerpc/powerpc/openpic.c

447

bus_write_4(sc->sc_memr, OPENPIC_TVEC(i), sc->sc_saved_timers[i].tvec);

sys/powerpc/powerpc/openpic.c

448

bus_write_4(sc->sc_memr, OPENPIC_TDST(i), sc->sc_saved_timers[i].tdst);

sys/powerpc/powerpc/openpic.c

452

bus_write_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i), sc->sc_saved_vectors[i]);

sys/powerpc/pseries/xics.c

486

bus_write_4(xicp_mem_for_cpu(PCPU_GET(hwref)), 4, xirr);

sys/riscv/cvitek/cvitek_restart.c

119

bus_write_4(sc->reg, RTC_EN_SHDN_REQ, 0x1);

sys/riscv/cvitek/cvitek_restart.c

120

bus_write_4(sc->reg, RTC_EN_PWR_CYC_REQ, 0x1);

sys/riscv/cvitek/cvitek_restart.c

121

bus_write_4(sc->reg, RTC_EN_WARM_RST_REQ, 0x1);

sys/riscv/cvitek/cvitek_restart.c

138

bus_write_4(sc->reg, RTC_EN_SHDN_REQ, 0x0);

sys/riscv/cvitek/cvitek_restart.c

139

bus_write_4(sc->reg, RTC_EN_PWR_CYC_REQ, 0x0);

sys/riscv/cvitek/cvitek_restart.c

140

bus_write_4(sc->reg, RTC_EN_WARM_RST_REQ, 0x0);

sys/riscv/cvitek/cvitek_restart.c

84

bus_write_4(sc->reg, RTC_CTRL0_UNLOCK, RTC_CTRL0_UNLOCK_KEY);

sys/riscv/cvitek/cvitek_restart.c

85

bus_write_4(sc->reg, RTC_CTRL0, val);

sys/riscv/riscv/aplic.c

160

#define aplic_write(sc, reg, val) bus_write_4(sc->mem_res, (reg), (val))

sys/riscv/riscv/plic.c

115

bus_write_4(sc->mem_res, (reg), (val))

sys/riscv/sifive/fe310_aon.c

108

#define FEAON_WRITE_4(sc, reg, val) bus_write_4(sc->reg_res, reg, val)

sys/riscv/sifive/fu740_pci_dw.c

102

#define FUDW_MGMT_WRITE(_sc, _o, _v) bus_write_4((_sc)->mgmt_res, (_o), (_v))

sys/riscv/sifive/sifive_gpio.c

83

bus_write_4((_sc)->mem_res, (_off), (_val))

sys/riscv/starfive/jh7110_gpio.c

78

#define JH7110_GPIO_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val))

sys/riscv/starfive/jh7110_pcie.c

162

#define WR4(sc, reg, val) bus_write_4((sc)->reg_mem_res, (reg), (val))

sys/riscv/starfive/jh7110_pcie.c

217

bus_write_4(sc->cfg_mem_res, offset, htole32(val));

sys/riscv/starfive/jh7110_pcie.c

470

bus_write_4(sc->cfg_mem_res, sc->msi_mask_offset, reg);

sys/x86/iommu/amd_iommu.h

167

bus_write_4(unit->mmio_res, reg, val);

sys/x86/iommu/amd_iommu.h

178

bus_write_4(unit->mmio_res, reg, low);

sys/x86/iommu/amd_iommu.h

179

bus_write_4(unit->mmio_res, reg + 4, high);

sys/x86/iommu/intel_dmar.h

300

bus_write_4(unit->regs, reg, val);

sys/x86/iommu/intel_dmar.h

313

bus_write_4(unit->regs, reg, low);

sys/x86/iommu/intel_dmar.h

314

bus_write_4(unit->regs, reg + 4, high);

tools/bus_space/C/libbus.h

38

int bus_write_4(int rid, long ofs, uint32_t val);

tools/bus_space/Python/lang.c

426

{ "write_4", bus_write_4, METH_VARARGS, "Write a 4-byte data item." },