bin/cpdup/hclink.c
154
struct HCHead tmp;
bin/cpdup/hclink.c
165
r = read(hc->fdin, (char *)&tmp + n, sizeof(struct HCHead) - n);
bin/cpdup/hclink.c
171
if (tmp.magic == HCMAGIC) {
bin/cpdup/hclink.c
174
tmp.magic = hc_bswap32(tmp.magic);
bin/cpdup/hclink.c
175
if (tmp.magic != HCMAGIC)
bin/cpdup/hclink.c
176
fatal("magic mismatch with %s (%04x)", hc->host, tmp.id);
bin/cpdup/hclink.c
178
tmp.bytes = hc_bswap32(tmp.bytes);
bin/cpdup/hclink.c
179
tmp.cmd = hc_bswap16(tmp.cmd);
bin/cpdup/hclink.c
180
tmp.id = hc_bswap16(tmp.id);
bin/cpdup/hclink.c
181
tmp.error = hc_bswap32(tmp.error);
bin/cpdup/hclink.c
184
assert(tmp.bytes >= (int)sizeof(tmp) && tmp.bytes < HC_BUFSIZE);
bin/cpdup/hclink.c
187
bcopy(&tmp, trans->rbuf, n);
bin/cpdup/hclink.c
188
aligned_bytes = HCC_ALIGN(tmp.bytes);
bin/date/date.c
125
tval = strtoll(optarg, &tmp, 0);
bin/date/date.c
126
if (*tmp != 0)
bin/date/date.c
136
tmp = strdup(optarg);
bin/date/date.c
139
for (tzlen = 0; !isspace(tmp[tzlen]); ++tzlen)
bin/date/date.c
141
if (tmp[0] == '"' && tmp[tzlen - 1] == '"') {
bin/date/date.c
142
tmp[tzlen - 1] = 0;
bin/date/date.c
143
setenv("TZ", tmp + 1, 1);
bin/date/date.c
145
tmp[tzlen] = 0;
bin/date/date.c
146
setenv("TZ", tmp, 1);
bin/date/date.c
148
while (isspace(tmp[tzlen]))
bin/date/date.c
150
if (tmp[tzlen])
bin/date/date.c
80
char *tmp;
bin/date/vary.c
430
char *tmp;
bin/date/vary.c
491
val = strtoul(arg, &tmp, 10);
bin/date/vary.c
492
if (tmp != arg && isalpha(tmp[0])) {
bin/date/vary.c
493
if (strcmp(tmp, "S") == 0 || strncmp(tmp, "sec", 3) == 0) {
bin/date/vary.c
496
} else if (strcmp(tmp, "M") == 0 || strncmp(tmp, "min", 3) == 0) {
bin/date/vary.c
499
} else if (strcmp(tmp, "H") == 0 || strncmp(tmp, "hour", 4) == 0) {
bin/date/vary.c
502
} else if (strcmp(tmp, "d") == 0 || strncmp(tmp, "day", 3) == 0) {
bin/date/vary.c
506
} else if (strcmp(tmp, "w") == 0 || strncmp(tmp, "week", 4) == 0) {
bin/date/vary.c
510
} else if (strcmp(tmp, "m") == 0 || strncmp(tmp, "mon", 3) == 0) {
bin/date/vary.c
514
} else if (strcmp(tmp, "y") == 0 || strncmp(tmp, "year", 4) == 0) {
bin/date/vary.c
556
val = strtoul(arg, &tmp, 10);
bin/date/vary.c
557
if (tmp != arg && (isspace(*tmp) || *tmp == 0)) {
bin/date/vary.c
561
arg = tmp;
bin/date/vary.c
573
val = strtol(arg, &tmp, 10);
bin/date/vary.c
574
if (tmp != arg && (*tmp == 0 || isspace(*tmp))) {
bin/date/vary.c
577
arg = tmp;
bin/date/vary.c
584
val = strtol(arg, &tmp, 10);
bin/date/vary.c
585
if (dohms && tmp != arg && *tmp == ':') {
bin/date/vary.c
604
arg = tmp;
bin/date/vary.c
616
val = strtol(arg, &tmp, 10);
bin/date/vary.c
617
if (tmp != arg && *tmp == 0) {
bin/date/vary.c
620
arg = tmp;
bin/dd/args.c
102
struct arg *ap, tmp;
bin/dd/args.c
115
tmp.name = oper;
bin/dd/args.c
116
if (!(ap = (struct arg *)bsearch(&tmp, args,
bin/dd/args.c
119
errx(1, "unknown operand %s", tmp.name);
bin/dd/args.c
122
tmp.name);
bin/dd/args.c
330
struct conv *cp, tmp;
bin/dd/args.c
333
tmp.name = strsep(&arg, ",");
bin/dd/args.c
334
cp = bsearch(&tmp, clist, sizeof(clist) / sizeof(struct conv),
bin/dd/args.c
337
errx(1, "unknown conversion %s", tmp.name);
bin/dd/args.c
339
errx(1, "%s: illegal conversion combination", tmp.name);
bin/expr/expr.y
187
char *tmp;
bin/expr/expr.y
192
tmp = malloc ((size_t)25);
bin/expr/expr.y
193
if (tmp == NULL) {
bin/expr/expr.y
197
sprintf (tmp, "%lld", (long long)vp->u.i);
bin/expr/expr.y
199
vp->u.s = tmp;
bin/ls/print.c
461
char tmp = (char)c;
bin/ls/print.c
463
write(STDOUT_FILENO, &tmp, 1);
bin/pax/options.c
1021
FSUB tmp;
bin/pax/options.c
1186
tmp.name = optarg;
bin/pax/options.c
1187
if ((frmt = (FSUB *)bsearch((void *)&tmp, (void *)fsub,
bin/pax/options.c
187
FSUB tmp;
bin/pax/options.c
363
tmp.name = optarg;
bin/pax/options.c
364
if ((frmt = (FSUB *)bsearch((void *)&tmp, (void *)fsub,
bin/stty/cchar.c
101
tmp.name = name;
bin/stty/cchar.c
102
if (!(cp = (struct cchar *)bsearch(&tmp, cchars1,
bin/stty/cchar.c
104
c_cchar)) && !(cp = (struct cchar *)bsearch(&tmp, cchars2,
bin/stty/cchar.c
95
struct cchar *cp, tmp;
bin/stty/gfmt.c
101
tp->c_lflag = tmp;
bin/stty/gfmt.c
105
tp->c_oflag = tmp;
bin/stty/gfmt.c
109
sscanf(ep, "%ld", &tmp);
bin/stty/gfmt.c
110
tp->c_ospeed = tmp;
bin/stty/gfmt.c
116
sscanf(ep, "%ld", &tmp);
bin/stty/gfmt.c
117
tp->c_cc[cp->sub] = tmp;
bin/stty/gfmt.c
73
long tmp;
bin/stty/gfmt.c
84
sscanf(ep, "%lx", &tmp);
bin/stty/gfmt.c
88
tp->c_cflag = tmp;
bin/stty/gfmt.c
92
tp->c_iflag = tmp;
bin/stty/gfmt.c
96
sscanf(ep, "%ld", &tmp);
bin/stty/gfmt.c
97
tp->c_ispeed = tmp;
bin/stty/key.c
105
struct key *kp, tmp;
bin/stty/key.c
114
tmp.name = name;
bin/stty/key.c
115
if (!(kp = (struct key *)bsearch(&tmp, keys,
bin/stty/key.c
193
int tmp = 0;
bin/stty/key.c
194
ioctl(ip->fd, TIOCEXT, &tmp);
bin/stty/key.c
196
int tmp = 1;
bin/stty/key.c
197
ioctl(ip->fd, TIOCEXT, &tmp);
bin/stty/key.c
284
int tmp;
bin/stty/key.c
286
tmp = TTYDISC;
bin/stty/key.c
287
if (ioctl(ip->fd, TIOCSETD, &tmp) < 0)
bin/stty/print.c
112
tmp = tp->c_iflag;
bin/stty/print.c
129
tmp = tp->c_oflag;
bin/stty/print.c
139
tmp = tp->c_cflag;
bin/stty/print.c
142
switch(tmp&CSIZE) {
bin/stty/print.c
161
switch(tmp & (CCTS_OFLOW | CRTS_IFLOW)) {
bin/stty/print.c
50
long tmp;
bin/stty/print.c
85
#define on(f) ((tmp & (f)) != 0)
bin/stty/print.c
91
tmp = tp->c_lflag;
crypto/libressl/apps/nc/netcat.c
1539
char *tmp;
crypto/libressl/apps/nc/netcat.c
1542
if (asprintf(&tmp, "%d", hi) != -1)
crypto/libressl/apps/nc/netcat.c
1543
portlist[0] = tmp;
crypto/libressl/apps/openssl/apps.c
440
char *tmp, tpass[APP_PASS_LEN];
crypto/libressl/apps/openssl/apps.c
448
tmp = getenv(arg + 4);
crypto/libressl/apps/openssl/apps.c
449
if (!tmp) {
crypto/libressl/apps/openssl/apps.c
454
return strdup(tmp);
crypto/libressl/apps/openssl/apps.c
507
tmp = strchr(tpass, '\n');
crypto/libressl/apps/openssl/apps.c
508
if (tmp)
crypto/libressl/apps/openssl/apps.c
509
*tmp = 0;
crypto/libressl/apps/openssl/asn1pars.c
319
BIO *tmp;
crypto/libressl/apps/openssl/asn1pars.c
324
tmp = in;
crypto/libressl/apps/openssl/asn1pars.c
326
b64 = tmp;
crypto/libressl/apps/openssl/ca.c
2823
char *tmp = NULL;
crypto/libressl/apps/openssl/ca.c
2863
free(tmp);
crypto/libressl/apps/openssl/ca.c
2918
char *tmp = NULL;
crypto/libressl/apps/openssl/ca.c
2926
if ((tmp = strdup(str)) == NULL) {
crypto/libressl/apps/openssl/ca.c
2930
p = strchr(tmp, ',');
crypto/libressl/apps/openssl/ca.c
2931
rtime_str = tmp;
crypto/libressl/apps/openssl/ca.c
3010
free(tmp);
crypto/libressl/apps/openssl/cms.c
1796
BIO *tmp;
crypto/libressl/apps/openssl/cms.c
1800
tmp = BIO_new_file(signerfile, "w");
crypto/libressl/apps/openssl/cms.c
1801
if (tmp == NULL)
crypto/libressl/apps/openssl/cms.c
1804
PEM_write_bio_X509(tmp, sk_X509_value(signers, i));
crypto/libressl/apps/openssl/cms.c
1805
BIO_free(tmp);
crypto/libressl/apps/openssl/req.c
1135
char *tmp, *dn_sect, *attr_sect;
crypto/libressl/apps/openssl/req.c
1137
tmp = NCONF_get_string(req_conf, SECTION, PROMPT);
crypto/libressl/apps/openssl/req.c
1138
if (tmp == NULL)
crypto/libressl/apps/openssl/req.c
1140
if ((tmp != NULL) && !strcmp(tmp, "no"))
crypto/libressl/apps/openssl/req.c
1577
const char *tmp;
crypto/libressl/apps/openssl/req.c
1582
tmp = str + slen - elen;
crypto/libressl/apps/openssl/req.c
1583
return strcmp(tmp, end);
crypto/libressl/apps/openssl/smime.c
1095
BIO *tmp;
crypto/libressl/apps/openssl/smime.c
1099
tmp = BIO_new_file(signerfile, "w");
crypto/libressl/apps/openssl/smime.c
1100
if (tmp == NULL)
crypto/libressl/apps/openssl/smime.c
1103
PEM_write_bio_X509(tmp, sk_X509_value(signers, i));
crypto/libressl/apps/openssl/smime.c
1104
BIO_free(tmp);
crypto/libressl/crypto/aes/aes_ige.c
115
aes_block_t tmp, tmp2;
crypto/libressl/crypto/aes/aes_ige.c
123
load_block(tmp, in);
crypto/libressl/crypto/aes/aes_ige.c
125
tmp2.data[n] = tmp.data[n] ^ iv.data[n];
crypto/libressl/crypto/aes/aes_ige.c
132
iv2 = tmp;
crypto/libressl/crypto/aes/aes_ige.c
148
aes_block_t tmp;
crypto/libressl/crypto/aes/aes_ige.c
153
tmp.data[n] = inp->data[n] ^ iv2p->data[n];
crypto/libressl/crypto/aes/aes_ige.c
154
AES_decrypt((unsigned char *)tmp.data,
crypto/libressl/crypto/aes/aes_ige.c
167
aes_block_t tmp, tmp2;
crypto/libressl/crypto/aes/aes_ige.c
175
load_block(tmp, in);
crypto/libressl/crypto/aes/aes_ige.c
176
tmp2 = tmp;
crypto/libressl/crypto/aes/aes_ige.c
178
tmp.data[n] ^= iv2.data[n];
crypto/libressl/crypto/aes/aes_ige.c
179
AES_decrypt((unsigned char *)tmp.data,
crypto/libressl/crypto/aes/aes_ige.c
180
(unsigned char *)tmp.data, key);
crypto/libressl/crypto/aes/aes_ige.c
182
tmp.data[n] ^= iv.data[n];
crypto/libressl/crypto/aes/aes_ige.c
183
store_block(out, tmp);
crypto/libressl/crypto/aes/aes_ige.c
185
iv2 = tmp;
crypto/libressl/crypto/asn1/a_strnid.c
268
ASN1_STRING_TABLE *tmp, *rv;
crypto/libressl/crypto/asn1/a_strnid.c
276
tmp = ASN1_STRING_TABLE_get(nid);
crypto/libressl/crypto/asn1/a_strnid.c
277
if (tmp != NULL && (tmp->flags & STABLE_FLAGS_MALLOC) != 0)
crypto/libressl/crypto/asn1/a_strnid.c
278
return tmp;
crypto/libressl/crypto/asn1/a_strnid.c
288
if (tmp != NULL) {
crypto/libressl/crypto/asn1/a_strnid.c
289
rv->nid = tmp->nid;
crypto/libressl/crypto/asn1/a_strnid.c
290
rv->minsize = tmp->minsize;
crypto/libressl/crypto/asn1/a_strnid.c
291
rv->maxsize = tmp->maxsize;
crypto/libressl/crypto/asn1/a_strnid.c
292
rv->mask = tmp->mask;
crypto/libressl/crypto/asn1/a_strnid.c
293
rv->flags = tmp->flags | STABLE_FLAGS_MALLOC;
crypto/libressl/crypto/asn1/a_strnid.c
307
ASN1_STRING_TABLE *tmp;
crypto/libressl/crypto/asn1/a_strnid.c
309
if ((tmp = stable_get(nid)) == NULL) {
crypto/libressl/crypto/asn1/a_strnid.c
314
tmp->minsize = minsize;
crypto/libressl/crypto/asn1/a_strnid.c
316
tmp->maxsize = maxsize;
crypto/libressl/crypto/asn1/a_strnid.c
318
tmp->mask = mask;
crypto/libressl/crypto/asn1/a_strnid.c
320
tmp->flags = flags | STABLE_FLAGS_MALLOC;
crypto/libressl/crypto/asn1/a_strnid.c
328
STACK_OF(ASN1_STRING_TABLE) *tmp;
crypto/libressl/crypto/asn1/a_strnid.c
330
tmp = stable;
crypto/libressl/crypto/asn1/a_strnid.c
331
if (tmp == NULL)
crypto/libressl/crypto/asn1/a_strnid.c
334
sk_ASN1_STRING_TABLE_pop_free(tmp, st_free);
crypto/libressl/crypto/asn1/a_time_tm.c
326
struct tm tml, *tmp = tm ? tm : &tml;
crypto/libressl/crypto/asn1/a_time_tm.c
339
if (asn1_time_parse_cbs(&cbs, type == V_ASN1_GENERALIZEDTIME, tmp)) {
crypto/libressl/crypto/asn1/a_time_tm.c
356
char *tmp;
crypto/libressl/crypto/asn1/a_time_tm.c
366
if ((tmp = strdup(str)) == NULL)
crypto/libressl/crypto/asn1/a_time_tm.c
369
s->data = tmp;
crypto/libressl/crypto/asn1/a_time_tm.c
370
s->length = strlen(tmp);
crypto/libressl/crypto/asn1/ameth_lib.c
173
EVP_PKEY_ASN1_METHOD tmp;
crypto/libressl/crypto/asn1/ameth_lib.c
174
const EVP_PKEY_ASN1_METHOD *t = &tmp, **ret;
crypto/libressl/crypto/asn1/ameth_lib.c
175
tmp.pkey_id = type;
crypto/libressl/crypto/asn1/ameth_lib.c
178
idx = sk_EVP_PKEY_ASN1_METHOD_find(app_methods, &tmp);
crypto/libressl/crypto/bio/b_dump.c
111
snprintf(tmp, sizeof tmp, "%04x - ", i*dump_width);
crypto/libressl/crypto/bio/b_dump.c
112
strlcat(buf, tmp, sizeof buf);
crypto/libressl/crypto/bio/b_dump.c
118
snprintf(tmp, sizeof tmp, "%02x%c", ch,
crypto/libressl/crypto/bio/b_dump.c
120
strlcat(buf, tmp, sizeof buf);
crypto/libressl/crypto/bio/b_dump.c
128
snprintf(tmp, sizeof tmp, "%c",
crypto/libressl/crypto/bio/b_dump.c
130
strlcat(buf, tmp, sizeof buf);
crypto/libressl/crypto/bio/b_dump.c
84
char buf[288 + 1], tmp[20], str[128 + 1];
crypto/libressl/crypto/bn/bn_add.c
108
const BIGNUM *tmp;
crypto/libressl/crypto/bn/bn_add.c
110
tmp = a;
crypto/libressl/crypto/bn/bn_add.c
112
b = tmp;
crypto/libressl/crypto/bn/bn_bpsw.c
104
if (!BN_add(V, V, tmp))
crypto/libressl/crypto/bn/bn_bpsw.c
66
BIGNUM *tmp;
crypto/libressl/crypto/bn/bn_bpsw.c
71
if ((tmp = BN_CTX_get(ctx)) == NULL)
crypto/libressl/crypto/bn/bn_bpsw.c
75
if (!BN_sqr(tmp, U, ctx))
crypto/libressl/crypto/bn/bn_bpsw.c
77
if (!BN_mul(tmp, D, tmp, ctx))
crypto/libressl/crypto/bn/bn_bpsw.c
87
if (!BN_add(V, V, tmp))
crypto/libressl/crypto/bn/bn_bpsw.c
94
if (!BN_mul(tmp, D, U, ctx))
crypto/libressl/crypto/bn/bn_div.c
124
BIGNUM *tmp, wnum, *snum, *sdiv, *res;
crypto/libressl/crypto/bn/bn_div.c
164
tmp = BN_CTX_get(ctx);
crypto/libressl/crypto/bn/bn_div.c
171
if (tmp == NULL || snum == NULL || sdiv == NULL || res == NULL)
crypto/libressl/crypto/bn/bn_div.c
232
if (!bn_wexpand(tmp, (div_n + 1)))
crypto/libressl/crypto/bn/bn_div.c
338
l0 = bn_mul_words(tmp->d, sdiv->d, div_n, q);
crypto/libressl/crypto/bn/bn_div.c
339
tmp->d[div_n] = l0;
crypto/libressl/crypto/bn/bn_div.c
343
if (bn_sub_words(wnum.d, wnum.d, tmp->d, div_n + 1)) {
crypto/libressl/crypto/bn/bn_exp.c
659
BIGNUM tmp, am;
crypto/libressl/crypto/bn/bn_exp.c
716
tmp.d = (BN_ULONG *)(powerbuf + sizeof(m->d[0]) * top * numPowers);
crypto/libressl/crypto/bn/bn_exp.c
717
am.d = tmp.d + top;
crypto/libressl/crypto/bn/bn_exp.c
718
tmp.top = am.top = 0;
crypto/libressl/crypto/bn/bn_exp.c
719
tmp.dmax = am.dmax = top;
crypto/libressl/crypto/bn/bn_exp.c
720
tmp.neg = am.neg = 0;
crypto/libressl/crypto/bn/bn_exp.c
721
tmp.flags = am.flags = BN_FLG_STATIC_DATA;
crypto/libressl/crypto/bn/bn_exp.c
725
if (!BN_to_montgomery(&tmp, BN_value_one(), mont, ctx))
crypto/libressl/crypto/bn/bn_exp.c
728
tmp.d[0] = (0 - m - >d[0]) & BN_MASK2; /* 2^(top*BN_BITS2) - m */
crypto/libressl/crypto/bn/bn_exp.c
730
tmp.d[i] = (~m->d[i]) & BN_MASK2;
crypto/libressl/crypto/bn/bn_exp.c
731
tmp.top = top;
crypto/libressl/crypto/bn/bn_exp.c
765
for (i = tmp.top; i < top; i++)
crypto/libressl/crypto/bn/bn_exp.c
766
tmp.d[i] = 0;
crypto/libressl/crypto/bn/bn_exp.c
768
bn_scatter5(tmp.d, top, powerbuf, 0);
crypto/libressl/crypto/bn/bn_exp.c
770
bn_mul_mont(tmp.d, am.d, am.d, np, n0, top);
crypto/libressl/crypto/bn/bn_exp.c
771
bn_scatter5(tmp.d, top, powerbuf, 2);
crypto/libressl/crypto/bn/bn_exp.c
776
bn_mul_mont_gather5(tmp.d, am.d, powerbuf, np,
crypto/libressl/crypto/bn/bn_exp.c
778
bn_scatter5(tmp.d, top, powerbuf, i);
crypto/libressl/crypto/bn/bn_exp.c
783
bn_mul_mont(tmp.d, tmp.d, tmp.d, np, n0, top);
crypto/libressl/crypto/bn/bn_exp.c
784
bn_scatter5(tmp.d, top, powerbuf, i);
crypto/libressl/crypto/bn/bn_exp.c
788
bn_mul_mont_gather5(tmp.d, am.d, powerbuf, np,
crypto/libressl/crypto/bn/bn_exp.c
790
bn_scatter5(tmp.d, top, powerbuf, i);
crypto/libressl/crypto/bn/bn_exp.c
792
bn_mul_mont(tmp.d, tmp.d, tmp.d, np, n0, top);
crypto/libressl/crypto/bn/bn_exp.c
793
bn_scatter5(tmp.d, top, powerbuf, j);
crypto/libressl/crypto/bn/bn_exp.c
797
bn_mul_mont_gather5(tmp.d, am.d, powerbuf, np,
crypto/libressl/crypto/bn/bn_exp.c
799
bn_scatter5(tmp.d, top, powerbuf, i);
crypto/libressl/crypto/bn/bn_exp.c
800
bn_mul_mont(tmp.d, tmp.d, tmp.d, np, n0, top);
crypto/libressl/crypto/bn/bn_exp.c
801
bn_scatter5(tmp.d, top, powerbuf, 2*i);
crypto/libressl/crypto/bn/bn_exp.c
804
bn_mul_mont_gather5(tmp.d, am.d, powerbuf, np,
crypto/libressl/crypto/bn/bn_exp.c
806
bn_scatter5(tmp.d, top, powerbuf, i);
crypto/libressl/crypto/bn/bn_exp.c
812
bn_gather5(tmp.d, top, powerbuf, wvalue);
crypto/libressl/crypto/bn/bn_exp.c
821
bn_mul_mont(tmp.d, tmp.d, tmp.d, np, n0, top);
crypto/libressl/crypto/bn/bn_exp.c
822
bn_mul_mont(tmp.d, tmp.d, tmp.d, np, n0, top);
crypto/libressl/crypto/bn/bn_exp.c
823
bn_mul_mont(tmp.d, tmp.d, tmp.d, np, n0, top);
crypto/libressl/crypto/bn/bn_exp.c
824
bn_mul_mont(tmp.d, tmp.d, tmp.d, np, n0, top);
crypto/libressl/crypto/bn/bn_exp.c
825
bn_mul_mont(tmp.d, tmp.d, tmp.d, np, n0, top);
crypto/libressl/crypto/bn/bn_exp.c
826
bn_mul_mont_gather5(tmp.d, tmp.d, powerbuf, np, n0, top, wvalue);
crypto/libressl/crypto/bn/bn_exp.c
829
tmp.top = top;
crypto/libressl/crypto/bn/bn_exp.c
830
bn_correct_top(&tmp);
crypto/libressl/crypto/bn/bn_exp.c
834
if (!MOD_EXP_CTIME_COPY_TO_PREBUF(&tmp, top, powerbuf, 0,
crypto/libressl/crypto/bn/bn_exp.c
847
if (!BN_mod_mul_montgomery(&tmp, &am, &am, mont, ctx))
crypto/libressl/crypto/bn/bn_exp.c
849
if (!MOD_EXP_CTIME_COPY_TO_PREBUF(&tmp, top, powerbuf,
crypto/libressl/crypto/bn/bn_exp.c
854
if (!BN_mod_mul_montgomery(&tmp, &am, &tmp,
crypto/libressl/crypto/bn/bn_exp.c
857
if (!MOD_EXP_CTIME_COPY_TO_PREBUF(&tmp, top,
crypto/libressl/crypto/bn/bn_exp.c
866
if (!MOD_EXP_CTIME_COPY_FROM_PREBUF(&tmp, top, powerbuf,
crypto/libressl/crypto/bn/bn_exp.c
878
if (!BN_mod_mul_montgomery(&tmp, &tmp, &tmp,
crypto/libressl/crypto/bn/bn_exp.c
890
if (!BN_mod_mul_montgomery(&tmp, &tmp, &am, mont, ctx))
crypto/libressl/crypto/bn/bn_exp.c
896
if (!BN_from_montgomery(rr, &tmp, mont, ctx))
crypto/libressl/crypto/bn/bn_gcd.c
396
BIGNUM *tmp;
crypto/libressl/crypto/bn/bn_gcd.c
449
tmp = A; /* keep the BIGNUM object, the value does not matter */
crypto/libressl/crypto/bn/bn_gcd.c
477
if (!BN_add(tmp, X, Y))
crypto/libressl/crypto/bn/bn_gcd.c
481
if (!BN_lshift1(tmp, X))
crypto/libressl/crypto/bn/bn_gcd.c
484
if (!BN_lshift(tmp, X, 2))
crypto/libressl/crypto/bn/bn_gcd.c
487
if (!BN_copy(tmp, X))
crypto/libressl/crypto/bn/bn_gcd.c
489
if (!BN_mul_word(tmp, D->d[0]))
crypto/libressl/crypto/bn/bn_gcd.c
492
if (!BN_mul(tmp, D,X, ctx))
crypto/libressl/crypto/bn/bn_gcd.c
495
if (!BN_add(tmp, tmp, Y))
crypto/libressl/crypto/bn/bn_gcd.c
501
X = tmp;
crypto/libressl/crypto/bn/bn_gcd.c
633
BIGNUM *tmp;
crypto/libressl/crypto/bn/bn_gcd.c
658
tmp = A; /* keep the BIGNUM object, the value does not matter */
crypto/libressl/crypto/bn/bn_gcd.c
684
if (!BN_mul(tmp, D, X, ctx))
crypto/libressl/crypto/bn/bn_gcd.c
686
if (!BN_add(tmp, tmp, Y))
crypto/libressl/crypto/bn/bn_gcd.c
691
X = tmp;
crypto/libressl/crypto/bn/bn_gcd.c
800
BIGNUM *tmp;
crypto/libressl/crypto/bn/bn_gcd.c
825
tmp = A; /* keep the BIGNUM object, the value does not matter */
crypto/libressl/crypto/bn/bn_gcd.c
851
if (!BN_mul(tmp, D, X, ctx))
crypto/libressl/crypto/bn/bn_gcd.c
853
if (!BN_add(tmp, tmp, Y))
crypto/libressl/crypto/bn/bn_gcd.c
858
X = tmp;
crypto/libressl/crypto/bn/bn_gf2m.c
1136
BIGNUM *a, *z, *rho, *w, *w2, *tmp;
crypto/libressl/crypto/bn/bn_gf2m.c
1184
if ((tmp = BN_CTX_get(ctx)) == NULL)
crypto/libressl/crypto/bn/bn_gf2m.c
1199
if (!BN_GF2m_mod_mul_arr(tmp, w2, a, p, ctx))
crypto/libressl/crypto/bn/bn_gf2m.c
1201
if (!BN_GF2m_add(z, z, tmp))
crypto/libressl/crypto/bn/bn_gf2m.c
638
BIGNUM *b, *c = NULL, *u = NULL, *v = NULL, *tmp;
crypto/libressl/crypto/bn/bn_gf2m.c
684
tmp = u;
crypto/libressl/crypto/bn/bn_gf2m.c
686
v = tmp;
crypto/libressl/crypto/bn/bn_gf2m.c
687
tmp = b;
crypto/libressl/crypto/bn/bn_gf2m.c
689
c = tmp;
crypto/libressl/crypto/bn/bn_gf2m.c
762
tmp = u;
crypto/libressl/crypto/bn/bn_gf2m.c
764
v = tmp;
crypto/libressl/crypto/bn/bn_gf2m.c
765
tmp = b;
crypto/libressl/crypto/bn/bn_gf2m.c
767
c = tmp;
crypto/libressl/crypto/bn/bn_kron.c
186
tmp = a;
crypto/libressl/crypto/bn/bn_kron.c
188
b = tmp;
crypto/libressl/crypto/bn/bn_kron.c
70
BIGNUM *a, *b, *tmp;
crypto/libressl/crypto/bn/bn_lcl.h
366
BN_ULONG high,low,ret,tmp=(a); \
crypto/libressl/crypto/bn/bn_lcl.h
368
BN_UMULT_LOHI(low,high,w,tmp); \
crypto/libressl/crypto/bn/bn_lcl.h
387
BN_ULONG tmp=(a); \
crypto/libressl/crypto/bn/bn_lcl.h
388
BN_UMULT_LOHI(r0,r1,tmp,tmp); \
crypto/libressl/crypto/bn/bn_lcl.h
393
BN_ULONG high,low,ret,tmp=(a); \
crypto/libressl/crypto/bn/bn_lcl.h
395
high= BN_UMULT_HIGH(w,tmp); \
crypto/libressl/crypto/bn/bn_lcl.h
397
low = (w) * tmp; \
crypto/libressl/crypto/bn/bn_lcl.h
416
BN_ULONG tmp=(a); \
crypto/libressl/crypto/bn/bn_lcl.h
417
(r0) = tmp * tmp; \
crypto/libressl/crypto/bn/bn_lcl.h
418
(r1) = BN_UMULT_HIGH(tmp,tmp); \
crypto/libressl/crypto/bn/bn_lcl.h
502
void bn_sqr_normal(BN_ULONG *r, const BN_ULONG *a, int n, BN_ULONG *tmp);
crypto/libressl/crypto/bn/bn_mont.c
134
BIGNUM *tmp;
crypto/libressl/crypto/bn/bn_mont.c
152
if ((tmp = BN_CTX_get(ctx)) == NULL)
crypto/libressl/crypto/bn/bn_mont.c
155
bn_check_top(tmp);
crypto/libressl/crypto/bn/bn_mont.c
157
if (!BN_sqr(tmp, a, ctx))
crypto/libressl/crypto/bn/bn_mont.c
160
if (!BN_mul(tmp, a,b, ctx))
crypto/libressl/crypto/bn/bn_mont.c
165
if (!BN_from_montgomery_word(r, tmp, mont))
crypto/libressl/crypto/bn/bn_mont.c
168
if (!BN_from_montgomery(r, tmp, mont, ctx))
crypto/libressl/crypto/bn/bn_nist.c
1287
BN_ULONG tmp, val;
crypto/libressl/crypto/bn/bn_nist.c
1317
tmp = val >> BN_NIST_521_RSHIFT;
crypto/libressl/crypto/bn/bn_nist.c
1319
t_d[i] = (tmp | val << BN_NIST_521_LSHIFT) & BN_MASK2;
crypto/libressl/crypto/bn/bn_shift.c
183
BN_ULONG l, tmp;
crypto/libressl/crypto/bn/bn_shift.c
221
tmp = (l >> rb) & BN_MASK2;
crypto/libressl/crypto/bn/bn_shift.c
223
*(t++) = (tmp|(l << lb)) & BN_MASK2;
crypto/libressl/crypto/bn/bn_sqr.c
121
if (bn_wexpand(tmp, k * 2) == NULL)
crypto/libressl/crypto/bn/bn_sqr.c
123
bn_sqr_recursive(rr->d, a->d, al, tmp->d);
crypto/libressl/crypto/bn/bn_sqr.c
125
if (bn_wexpand(tmp, max) == NULL)
crypto/libressl/crypto/bn/bn_sqr.c
127
bn_sqr_normal(rr->d, a->d, al, tmp->d);
crypto/libressl/crypto/bn/bn_sqr.c
131
if (bn_wexpand(tmp, max) == NULL)
crypto/libressl/crypto/bn/bn_sqr.c
133
bn_sqr_normal(rr->d, a->d, al, tmp->d);
crypto/libressl/crypto/bn/bn_sqr.c
150
bn_check_top(tmp);
crypto/libressl/crypto/bn/bn_sqr.c
157
bn_sqr_normal(BN_ULONG *r, const BN_ULONG *a, int n, BN_ULONG *tmp)
crypto/libressl/crypto/bn/bn_sqr.c
187
bn_sqr_words(tmp, a, n);
crypto/libressl/crypto/bn/bn_sqr.c
189
bn_add_words(r, r, tmp, max);
crypto/libressl/crypto/bn/bn_sqr.c
71
BIGNUM *tmp, *rr;
crypto/libressl/crypto/bn/bn_sqr.c
87
tmp = BN_CTX_get(ctx);
crypto/libressl/crypto/bn/bn_sqr.c
88
if (rr == NULL || tmp == NULL)
crypto/libressl/crypto/bn/bn_word.c
80
BIGNUM *tmp = BN_dup(a);
crypto/libressl/crypto/bn/bn_word.c
81
if (tmp == NULL) {
crypto/libressl/crypto/bn/bn_word.c
84
ret = BN_div_word(tmp, w);
crypto/libressl/crypto/bn/bn_word.c
85
BN_free(tmp);
crypto/libressl/crypto/chacha/chacha-merged.c
130
u8 tmp[64];
crypto/libressl/crypto/chacha/chacha-merged.c
156
tmp[i] = m[i];
crypto/libressl/crypto/chacha/chacha-merged.c
157
m = tmp;
crypto/libressl/crypto/chacha/chacha-merged.c
159
c = tmp;
crypto/libressl/crypto/cms/cms_pwri.c
227
unsigned char *tmp;
crypto/libressl/crypto/cms/cms_pwri.c
238
if ((tmp = malloc(inlen)) == NULL) {
crypto/libressl/crypto/cms/cms_pwri.c
244
if (!EVP_DecryptUpdate(ctx, tmp + inlen - 2 * blocklen, &outl,
crypto/libressl/crypto/cms/cms_pwri.c
251
|| !EVP_DecryptUpdate(ctx, tmp, &outl, tmp + inlen - blocklen, blocklen)
crypto/libressl/crypto/cms/cms_pwri.c
253
|| !EVP_DecryptUpdate(ctx, tmp, &outl, in, inlen - blocklen)
crypto/libressl/crypto/cms/cms_pwri.c
258
|| !EVP_DecryptUpdate(ctx, tmp, &outl, tmp, inlen))
crypto/libressl/crypto/cms/cms_pwri.c
261
if (((tmp[1] ^ tmp[4]) & (tmp[2] ^ tmp[5]) & (tmp[3] ^ tmp[6])) != 0xff) {
crypto/libressl/crypto/cms/cms_pwri.c
265
if (inlen < (size_t)(tmp[0] - 4)) {
crypto/libressl/crypto/cms/cms_pwri.c
269
*outlen = (size_t)tmp[0];
crypto/libressl/crypto/cms/cms_pwri.c
270
memcpy(out, tmp + 4, *outlen);
crypto/libressl/crypto/cms/cms_pwri.c
274
freezero(tmp, inlen);
crypto/libressl/crypto/ct/ct_log.c
214
char *tmp;
crypto/libressl/crypto/ct/ct_log.c
221
tmp = strndup(log_name, log_name_len);
crypto/libressl/crypto/ct/ct_log.c
222
if (tmp == NULL)
crypto/libressl/crypto/ct/ct_log.c
225
ret = ctlog_new_from_conf(&ct_log, load_ctx->conf, tmp);
crypto/libressl/crypto/ct/ct_log.c
226
free(tmp);
crypto/libressl/crypto/des/des_locl.h
148
{ DES_LONG tmp; LOAD_DATA(R,S,u,t,E0,E1,tmp); }
crypto/libressl/crypto/des/des_locl.h
150
#define LOAD_DATA(R,S,u,t,E0,E1,tmp) \
crypto/libressl/crypto/des/des_locl.h
153
tmp=(u<<16); u^=R^s[S ]; u^=tmp; \
crypto/libressl/crypto/des/des_locl.h
154
tmp=(t<<16); t^=R^s[S+1]; t^=tmp
crypto/libressl/crypto/des/des_locl.h
157
#define LOAD_DATA(R,S,u,t,E0,E1,tmp) \
crypto/libressl/crypto/dh/dh_key.c
178
BIGNUM *tmp;
crypto/libressl/crypto/dh/dh_key.c
191
if ((tmp = BN_CTX_get(ctx)) == NULL)
crypto/libressl/crypto/dh/dh_key.c
214
if (!dh->meth->bn_mod_exp(dh, tmp, pub_key, dh->priv_key, dh->p, ctx,
crypto/libressl/crypto/dh/dh_key.c
220
ret = BN_bn2bin(tmp, key);
crypto/libressl/crypto/ec/ec2_oct.c
112
if ((tmp = BN_CTX_get(ctx)) == NULL)
crypto/libressl/crypto/ec/ec2_oct.c
131
if (!group->meth->field_sqr(group, tmp, x, ctx))
crypto/libressl/crypto/ec/ec2_oct.c
133
if (!group->meth->field_div(group, tmp, &group->b, tmp, ctx))
crypto/libressl/crypto/ec/ec2_oct.c
135
if (!BN_GF2m_add(tmp, &group->a, tmp))
crypto/libressl/crypto/ec/ec2_oct.c
137
if (!BN_GF2m_add(tmp, x, tmp))
crypto/libressl/crypto/ec/ec2_oct.c
139
if (!BN_GF2m_mod_solve_quad_arr(z, tmp, group->poly, ctx)) {
crypto/libressl/crypto/ec/ec2_oct.c
98
BIGNUM *tmp, *x, *y, *z;
crypto/libressl/crypto/ec/ec_asn1.c
1014
tmp = EC_GROUP_get_curve_name(group);
crypto/libressl/crypto/ec/ec_asn1.c
1015
if (tmp) {
crypto/libressl/crypto/ec/ec_asn1.c
1017
if ((ret->value.named_curve = OBJ_nid2obj(tmp)) == NULL)
crypto/libressl/crypto/ec/ec_asn1.c
1040
int ok = 0, tmp;
crypto/libressl/crypto/ec/ec_asn1.c
1069
tmp = OBJ_obj2nid(params->fieldID->fieldType);
crypto/libressl/crypto/ec/ec_asn1.c
1070
if (tmp == NID_X9_62_characteristic_two_field)
crypto/libressl/crypto/ec/ec_asn1.c
1092
tmp = OBJ_obj2nid(char_two->type);
crypto/libressl/crypto/ec/ec_asn1.c
1094
if (tmp == NID_X9_62_tpBasis) {
crypto/libressl/crypto/ec/ec_asn1.c
1114
} else if (tmp == NID_X9_62_ppBasis) {
crypto/libressl/crypto/ec/ec_asn1.c
1137
} else if (tmp == NID_X9_62_onBasis) {
crypto/libressl/crypto/ec/ec_asn1.c
1149
else if (tmp == NID_X9_62_prime_field) {
crypto/libressl/crypto/ec/ec_asn1.c
1253
int tmp = 0;
crypto/libressl/crypto/ec/ec_asn1.c
1260
tmp = OBJ_obj2nid(params->value.named_curve);
crypto/libressl/crypto/ec/ec_asn1.c
1261
if ((ret = EC_GROUP_new_by_curve_name(tmp)) == NULL) {
crypto/libressl/crypto/ec/ec_asn1.c
1315
ECPKPARAMETERS *tmp = ec_asn1_group2pkparameters(a, NULL);
crypto/libressl/crypto/ec/ec_asn1.c
1316
if (tmp == NULL) {
crypto/libressl/crypto/ec/ec_asn1.c
1320
if ((ret = i2d_ECPKPARAMETERS(tmp, out)) == 0) {
crypto/libressl/crypto/ec/ec_asn1.c
1322
ECPKPARAMETERS_free(tmp);
crypto/libressl/crypto/ec/ec_asn1.c
1325
ECPKPARAMETERS_free(tmp);
crypto/libressl/crypto/ec/ec_asn1.c
689
BIGNUM *tmp = NULL;
crypto/libressl/crypto/ec/ec_asn1.c
707
if ((tmp = BN_new()) == NULL) {
crypto/libressl/crypto/ec/ec_asn1.c
712
if (!EC_GROUP_get_curve(group, tmp, NULL, NULL, NULL)) {
crypto/libressl/crypto/ec/ec_asn1.c
717
field->p.prime = BN_to_ASN1_INTEGER(tmp, NULL);
crypto/libressl/crypto/ec/ec_asn1.c
797
BN_free(tmp);
crypto/libressl/crypto/ec/ec_asn1.c
902
BIGNUM *tmp = NULL;
crypto/libressl/crypto/ec/ec_asn1.c
907
if ((tmp = BN_new()) == NULL) {
crypto/libressl/crypto/ec/ec_asn1.c
961
if (!EC_GROUP_get_order(group, tmp, NULL)) {
crypto/libressl/crypto/ec/ec_asn1.c
965
ret->order = BN_to_ASN1_INTEGER(tmp, ret->order);
crypto/libressl/crypto/ec/ec_asn1.c
971
if (EC_GROUP_get_cofactor(group, tmp, NULL)) {
crypto/libressl/crypto/ec/ec_asn1.c
972
ret->cofactor = BN_to_ASN1_INTEGER(tmp, ret->cofactor);
crypto/libressl/crypto/ec/ec_asn1.c
986
BN_free(tmp);
crypto/libressl/crypto/ec/ec_asn1.c
994
int ok = 1, tmp;
crypto/libressl/crypto/ec/ec_mult.c
340
EC_POINT *tmp = NULL;
crypto/libressl/crypto/ec/ec_mult.c
601
if (!(tmp = EC_POINT_new(group)))
crypto/libressl/crypto/ec/ec_mult.c
618
if (!EC_POINT_dbl(group, tmp, val_sub[i][0], ctx))
crypto/libressl/crypto/ec/ec_mult.c
621
if (!EC_POINT_add(group, val_sub[i][j], val_sub[i][j - 1], tmp, ctx))
crypto/libressl/crypto/ec/ec_mult.c
683
EC_POINT_free(tmp);
crypto/libressl/crypto/ec/ecp_smpl.c
1011
if ((tmp = BN_CTX_get(ctx)) == NULL)
crypto/libressl/crypto/ec/ecp_smpl.c
1032
if (!field_sqr(group, tmp, &point->Z, ctx))
crypto/libressl/crypto/ec/ecp_smpl.c
1034
if (!field_sqr(group, Z4, tmp, ctx))
crypto/libressl/crypto/ec/ecp_smpl.c
1036
if (!field_mul(group, Z6, Z4, tmp, ctx))
crypto/libressl/crypto/ec/ecp_smpl.c
1041
if (!BN_mod_lshift1_quick(tmp, Z4, p))
crypto/libressl/crypto/ec/ecp_smpl.c
1043
if (!BN_mod_add_quick(tmp, tmp, Z4, p))
crypto/libressl/crypto/ec/ecp_smpl.c
1045
if (!BN_mod_sub_quick(rh, rh, tmp, p))
crypto/libressl/crypto/ec/ecp_smpl.c
1050
if (!field_mul(group, tmp, Z4, &group->a, ctx))
crypto/libressl/crypto/ec/ecp_smpl.c
1052
if (!BN_mod_add_quick(rh, rh, tmp, p))
crypto/libressl/crypto/ec/ecp_smpl.c
1059
if (!field_mul(group, tmp, &group->b, Z6, ctx))
crypto/libressl/crypto/ec/ecp_smpl.c
1061
if (!BN_mod_add_quick(rh, rh, tmp, p))
crypto/libressl/crypto/ec/ecp_smpl.c
1077
if (!field_sqr(group, tmp, &point->Y, ctx))
crypto/libressl/crypto/ec/ecp_smpl.c
1080
ret = (0 == BN_ucmp(tmp, rh));
crypto/libressl/crypto/ec/ecp_smpl.c
1427
BIGNUM *tmp = NULL;
crypto/libressl/crypto/ec/ecp_smpl.c
1433
if ((tmp = BN_CTX_get(ctx)) == NULL)
crypto/libressl/crypto/ec/ecp_smpl.c
1449
if (!group->meth->field_sqr(group, tmp, lambda, ctx))
crypto/libressl/crypto/ec/ecp_smpl.c
1453
if (!group->meth->field_mul(group, &p->X, tmp, &p->X, ctx))
crypto/libressl/crypto/ec/ecp_smpl.c
1457
if (!group->meth->field_mul(group, tmp, tmp, lambda, ctx))
crypto/libressl/crypto/ec/ecp_smpl.c
1461
if (!group->meth->field_mul(group, &p->Y, tmp, &p->Y, ctx))
crypto/libressl/crypto/ec/ecp_smpl.c
993
BIGNUM *rh, *tmp, *Z4, *Z6;
crypto/libressl/crypto/ecdh/ech_key.c
101
EC_POINT *tmp = NULL;
crypto/libressl/crypto/ecdh/ech_key.c
134
if ((tmp = EC_POINT_new(group)) == NULL) {
crypto/libressl/crypto/ecdh/ech_key.c
139
if (!EC_POINT_mul(group, tmp, NULL, pub_key, priv_key, ctx)) {
crypto/libressl/crypto/ecdh/ech_key.c
144
if (!EC_POINT_get_affine_coordinates(group, tmp, x, y, ctx)) {
crypto/libressl/crypto/ecdh/ech_key.c
188
EC_POINT_free(tmp);
crypto/libressl/crypto/err/err.c
1027
ERR_STATE tmp;
crypto/libressl/crypto/err/err.c
1030
CRYPTO_THREADID_cpy(&tmp.tid, id);
crypto/libressl/crypto/err/err.c
1032
CRYPTO_THREADID_current(&tmp.tid);
crypto/libressl/crypto/err/err.c
1036
ERRFN(thread_del_item)(&tmp);
crypto/libressl/crypto/err/err.c
1051
ERR_STATE *ret, tmp, *tmpp = NULL;
crypto/libressl/crypto/err/err.c
1057
CRYPTO_THREADID_cpy(&tmp.tid, &tid);
crypto/libressl/crypto/err/err.c
1058
ret = ERRFN(thread_get_item)(&tmp);
crypto/libressl/crypto/evp/bio_b64.c
201
i = BIO_read(b->next_bio, &(ctx->tmp[ctx->tmp_len]),
crypto/libressl/crypto/evp/bio_b64.c
230
q = p =(unsigned char *)ctx->tmp;
crypto/libressl/crypto/evp/bio_b64.c
253
&(ctx->tmp[0])) {
crypto/libressl/crypto/evp/bio_b64.c
255
&(ctx->tmp[0]));
crypto/libressl/crypto/evp/bio_b64.c
257
ctx->tmp[x] = p[x];
crypto/libressl/crypto/evp/bio_b64.c
270
if (p == (unsigned char *)&(ctx->tmp[0])) {
crypto/libressl/crypto/evp/bio_b64.c
281
ctx->tmp[ii] = p[ii];
crypto/libressl/crypto/evp/bio_b64.c
301
(unsigned char *)ctx->tmp, jj);
crypto/libressl/crypto/evp/bio_b64.c
303
if (ctx->tmp[jj-1] == '=') {
crypto/libressl/crypto/evp/bio_b64.c
305
if (ctx->tmp[jj-2] == '=')
crypto/libressl/crypto/evp/bio_b64.c
312
memmove(ctx->tmp, &ctx->tmp[jj], i - jj);
crypto/libressl/crypto/evp/bio_b64.c
323
(unsigned char *)ctx->tmp, i);
crypto/libressl/crypto/evp/bio_b64.c
405
memcpy(&(ctx->tmp[ctx->tmp_len]), in, n);
crypto/libressl/crypto/evp/bio_b64.c
412
(unsigned char *)ctx->tmp, ctx->tmp_len);
crypto/libressl/crypto/evp/bio_b64.c
421
memcpy(ctx->tmp, in, n);
crypto/libressl/crypto/evp/bio_b64.c
516
(unsigned char *)ctx->tmp,
crypto/libressl/crypto/evp/bio_b64.c
94
char tmp[B64_BLOCK_SIZE];
crypto/libressl/crypto/evp/e_idea.c
90
IDEA_KEY_SCHEDULE tmp;
crypto/libressl/crypto/evp/e_idea.c
92
idea_set_encrypt_key(key, &tmp);
crypto/libressl/crypto/evp/e_idea.c
93
idea_set_decrypt_key(&tmp, ctx->cipher_data);
crypto/libressl/crypto/evp/e_idea.c
94
explicit_bzero((unsigned char *)&tmp,
crypto/libressl/crypto/evp/encode.c
255
int seof = 0, eof = 0, rv = -1, ret = 0, i, v, tmp, n, decoded_len;
crypto/libressl/crypto/evp/encode.c
274
tmp = *(in++);
crypto/libressl/crypto/evp/encode.c
275
v = conv_ascii2bin(tmp);
crypto/libressl/crypto/evp/encode.c
281
if (tmp == '=') {
crypto/libressl/crypto/evp/encode.c
313
d[n++] = tmp;
crypto/libressl/crypto/evp/pmeth_lib.c
143
EVP_PKEY_METHOD tmp;
crypto/libressl/crypto/evp/pmeth_lib.c
144
const EVP_PKEY_METHOD *t = &tmp, **ret;
crypto/libressl/crypto/evp/pmeth_lib.c
146
tmp.pkey_id = type;
crypto/libressl/crypto/evp/pmeth_lib.c
149
idx = sk_EVP_PKEY_METHOD_find(app_pkey_methods, &tmp);
crypto/libressl/crypto/gost/gostr341001.c
153
BIGNUM *r = NULL, *s = NULL, *X = NULL, *tmp = NULL, *tmp2 = NULL, *k =
crypto/libressl/crypto/gost/gostr341001.c
219
if (tmp == NULL) {
crypto/libressl/crypto/gost/gostr341001.c
220
if ((tmp = BN_CTX_get(ctx)) == NULL)
crypto/libressl/crypto/gost/gostr341001.c
223
if (BN_mod_mul(tmp, priv_key, r, order, ctx) == 0)
crypto/libressl/crypto/gost/gostr341001.c
231
if (BN_mod_add(s, tmp, tmp2, order, ctx) == 0)
crypto/libressl/crypto/gost/gostr341001.c
256
BIGNUM *X = NULL, *tmp = NULL;
crypto/libressl/crypto/gost/gostr341001.c
272
if ((tmp = BN_CTX_get(ctx)) == NULL)
crypto/libressl/crypto/gost/gostr341001.c
298
if (BN_sub(tmp, order, sig->r) == 0)
crypto/libressl/crypto/gost/gostr341001.c
300
if (BN_mod_mul(z2, tmp, v, order, ctx) == 0)
crypto/libressl/crypto/gost/streebog.c
1190
STREEBOG_LONG64 tmp[8];
crypto/libressl/crypto/gost/streebog.c
1192
tmp[0] = a[0] ^ b[0];
crypto/libressl/crypto/gost/streebog.c
1193
tmp[1] = a[1] ^ b[1];
crypto/libressl/crypto/gost/streebog.c
1194
tmp[2] = a[2] ^ b[2];
crypto/libressl/crypto/gost/streebog.c
1195
tmp[3] = a[3] ^ b[3];
crypto/libressl/crypto/gost/streebog.c
1196
tmp[4] = a[4] ^ b[4];
crypto/libressl/crypto/gost/streebog.c
1197
tmp[5] = a[5] ^ b[5];
crypto/libressl/crypto/gost/streebog.c
1198
tmp[6] = a[6] ^ b[6];
crypto/libressl/crypto/gost/streebog.c
1199
tmp[7] = a[7] ^ b[7];
crypto/libressl/crypto/gost/streebog.c
1201
out[0] = multipermute(tmp, 0);
crypto/libressl/crypto/gost/streebog.c
1202
out[1] = multipermute(tmp, 1);
crypto/libressl/crypto/gost/streebog.c
1203
out[2] = multipermute(tmp, 2);
crypto/libressl/crypto/gost/streebog.c
1204
out[3] = multipermute(tmp, 3);
crypto/libressl/crypto/gost/streebog.c
1205
out[4] = multipermute(tmp, 4);
crypto/libressl/crypto/gost/streebog.c
1206
out[5] = multipermute(tmp, 5);
crypto/libressl/crypto/gost/streebog.c
1207
out[6] = multipermute(tmp, 6);
crypto/libressl/crypto/gost/streebog.c
1208
out[7] = multipermute(tmp, 7);
crypto/libressl/crypto/modes/cbc128.c
121
union { size_t t[16/sizeof(size_t)]; unsigned char c[16]; } tmp;
crypto/libressl/crypto/modes/cbc128.c
157
(*block)(in, tmp.c, key);
crypto/libressl/crypto/modes/cbc128.c
160
out[n] = tmp.c[n] ^ ivec[n];
crypto/libressl/crypto/modes/cbc128.c
172
(*block)(in, tmp.c, key);
crypto/libressl/crypto/modes/cbc128.c
175
out_t[n] = tmp.t[n] ^ ivec_t[n];
crypto/libressl/crypto/modes/cbc128.c
187
(*block)(in, tmp.c, key);
crypto/libressl/crypto/modes/cbc128.c
190
out[n] = tmp.c[n] ^ ivec[n];
crypto/libressl/crypto/objects/obj_xref.c
130
nid_triple tmp;
crypto/libressl/crypto/objects/obj_xref.c
132
tmp.sign_id = signid;
crypto/libressl/crypto/objects/obj_xref.c
135
int idx = sk_nid_triple_find(sig_app, &tmp);
crypto/libressl/crypto/objects/obj_xref.c
142
rv = OBJ_bsearch_sig(&tmp, sigoid_srt,
crypto/libressl/crypto/objects/obj_xref.c
158
nid_triple tmp;
crypto/libressl/crypto/objects/obj_xref.c
159
const nid_triple *t = &tmp;
crypto/libressl/crypto/objects/obj_xref.c
162
tmp.hash_id = dig_nid;
crypto/libressl/crypto/objects/obj_xref.c
163
tmp.pkey_id = pkey_nid;
crypto/libressl/crypto/objects/obj_xref.c
166
int idx = sk_nid_triple_find(sigx_app, &tmp);
crypto/libressl/crypto/ocsp/ocsp_lib.c
190
char *host, *path, *port, *tmp;
crypto/libressl/crypto/ocsp/ocsp_lib.c
209
if ((tmp = strchr(host, '/')) != NULL) {
crypto/libressl/crypto/ocsp/ocsp_lib.c
210
path = strdup(tmp);
crypto/libressl/crypto/ocsp/ocsp_lib.c
211
*tmp = '\0';
crypto/libressl/crypto/ocsp/ocsp_lib.c
215
if ((tmp = strchr(host, ':')) != NULL ) {
crypto/libressl/crypto/ocsp/ocsp_lib.c
216
port = strdup(tmp + 1);
crypto/libressl/crypto/ocsp/ocsp_lib.c
217
*tmp = '\0';
crypto/libressl/crypto/pem/pvkfmt.c
533
unsigned char *tmp = NULL;
crypto/libressl/crypto/pem/pvkfmt.c
536
outlen = do_i2b(&tmp, pk, ispub);
crypto/libressl/crypto/pem/pvkfmt.c
539
wrlen = BIO_write(out, tmp, outlen);
crypto/libressl/crypto/pem/pvkfmt.c
540
free(tmp);
crypto/libressl/crypto/pem/pvkfmt.c
919
unsigned char *tmp = NULL;
crypto/libressl/crypto/pem/pvkfmt.c
922
outlen = i2b_PVK(&tmp, pk, enclevel, cb, u);
crypto/libressl/crypto/pem/pvkfmt.c
925
wrlen = BIO_write(out, tmp, outlen);
crypto/libressl/crypto/pem/pvkfmt.c
926
free(tmp);
crypto/libressl/crypto/rc4/rc4_skey.c
101
tmp=d[(n)]; \
crypto/libressl/crypto/rc4/rc4_skey.c
102
id2 = (data[id1] + tmp + id2) & 0xff; \
crypto/libressl/crypto/rc4/rc4_skey.c
105
d[id2]=tmp; }
crypto/libressl/crypto/rc4/rc4_skey.c
90
RC4_INT tmp;
crypto/libressl/crypto/rsa/rsa_gen.c
181
tmp = rsa->p;
crypto/libressl/crypto/rsa/rsa_gen.c
183
rsa->q = tmp;
crypto/libressl/crypto/rsa/rsa_gen.c
95
BIGNUM *r0 = NULL, *r1 = NULL, *r2 = NULL, *r3 = NULL, *tmp;
crypto/libressl/crypto/x509/by_dir.c
280
X509_OBJECT stmp, *tmp;
crypto/libressl/crypto/x509/by_dir.c
363
tmp = sk_X509_OBJECT_value(xl->store_ctx->objs, j);
crypto/libressl/crypto/x509/by_dir.c
402
if (tmp != NULL) {
crypto/libressl/crypto/x509/by_dir.c
404
ret->type = tmp->type;
crypto/libressl/crypto/x509/by_dir.c
405
memcpy(&ret->data, &tmp->data, sizeof(ret->data));
crypto/libressl/crypto/x509/pcy_cache.c
247
X509_POLICY_DATA tmp;
crypto/libressl/crypto/x509/pcy_cache.c
249
tmp.valid_policy = (ASN1_OBJECT *)id;
crypto/libressl/crypto/x509/pcy_cache.c
250
idx = sk_X509_POLICY_DATA_find(cache->data, &tmp);
crypto/libressl/crypto/x509/x509_constraints.c
129
struct x509_constraints_name **tmp;
crypto/libressl/crypto/x509/x509_constraints.c
130
if ((tmp = recallocarray(names->names, names->names_len,
crypto/libressl/crypto/x509/x509_constraints.c
131
names->names_len + 32, sizeof(*tmp))) == NULL)
crypto/libressl/crypto/x509/x509_constraints.c
134
names->names = tmp;
crypto/libressl/crypto/x509/x509_cpols.c
734
char *tmp;
crypto/libressl/crypto/x509/x509_cpols.c
738
tmp = i2s_ASN1_INTEGER(NULL, num);
crypto/libressl/crypto/x509/x509_cpols.c
739
BIO_puts(out, tmp);
crypto/libressl/crypto/x509/x509_cpols.c
740
free(tmp);
crypto/libressl/crypto/x509/x509_ia5.c
205
char *tmp;
crypto/libressl/crypto/x509/x509_ia5.c
209
if (!(tmp = malloc(ia5->length + 1))) {
crypto/libressl/crypto/x509/x509_ia5.c
213
memcpy(tmp, ia5->data, ia5->length);
crypto/libressl/crypto/x509/x509_ia5.c
214
tmp[ia5->length] = 0;
crypto/libressl/crypto/x509/x509_ia5.c
215
return tmp;
crypto/libressl/crypto/x509/x509_lib.c
118
X509V3_EXT_METHOD tmp;
crypto/libressl/crypto/x509/x509_lib.c
119
const X509V3_EXT_METHOD *t = &tmp, * const *ret;
crypto/libressl/crypto/x509/x509_lib.c
124
tmp.ext_nid = nid;
crypto/libressl/crypto/x509/x509_lib.c
130
idx = sk_X509V3_EXT_METHOD_find(ext_list, &tmp);
crypto/libressl/crypto/x509/x509_lu.c
328
X509_OBJECT stmp, *tmp;
crypto/libressl/crypto/x509/x509_lu.c
337
tmp = X509_OBJECT_retrieve_by_subject(ctx->objs, type, name);
crypto/libressl/crypto/x509/x509_lu.c
340
if (tmp == NULL || type == X509_LU_CRL) {
crypto/libressl/crypto/x509/x509_lu.c
344
tmp = &stmp;
crypto/libressl/crypto/x509/x509_lu.c
348
if (tmp == NULL)
crypto/libressl/crypto/x509/x509_lu.c
352
if (!X509_OBJECT_up_ref_count(tmp))
crypto/libressl/crypto/x509/x509_lu.c
355
*ret = *tmp;
crypto/libressl/crypto/x509/x509_purp.c
196
X509_PURPOSE tmp;
crypto/libressl/crypto/x509/x509_purp.c
201
tmp.purpose = purpose;
crypto/libressl/crypto/x509/x509_purp.c
204
idx = sk_X509_PURPOSE_find(xptable, &tmp);
crypto/libressl/crypto/x509/x509_sxnet.c
210
char *tmp;
crypto/libressl/crypto/x509/x509_sxnet.c
218
tmp = i2s_ASN1_INTEGER(NULL, id->zone);
crypto/libressl/crypto/x509/x509_sxnet.c
219
BIO_printf(out, "\n%*sZone: %s, User: ", indent, "", tmp);
crypto/libressl/crypto/x509/x509_sxnet.c
220
free(tmp);
crypto/libressl/crypto/x509/x509_trs.c
165
X509_TRUST tmp;
crypto/libressl/crypto/x509/x509_trs.c
170
tmp.trust = id;
crypto/libressl/crypto/x509/x509_trs.c
173
idx = sk_X509_TRUST_find(trtable, &tmp);
crypto/libressl/crypto/x509/x509_utl.c
1212
unsigned char tmp[16];
crypto/libressl/crypto/x509/x509_utl.c
1274
memcpy(v6, v6stat.tmp, v6stat.zero_pos);
crypto/libressl/crypto/x509/x509_utl.c
1280
v6stat.tmp + v6stat.zero_pos,
crypto/libressl/crypto/x509/x509_utl.c
1283
memcpy(v6, v6stat.tmp, 16);
crypto/libressl/crypto/x509/x509_utl.c
1313
if (!ipv4_from_asc(s->tmp + s->total, elem))
crypto/libressl/crypto/x509/x509_utl.c
1317
if (!ipv6_hex(s->tmp + s->total, elem, len))
crypto/libressl/crypto/x509/x509_utl.c
441
char *tmp, *q;
crypto/libressl/crypto/x509/x509_utl.c
448
if (!(tmp = malloc(len * 3 + 1))) {
crypto/libressl/crypto/x509/x509_utl.c
452
q = tmp;
crypto/libressl/crypto/x509/x509_utl.c
459
return tmp;
crypto/libressl/crypto/x509/x509_vpm.c
376
char *tmp;
crypto/libressl/crypto/x509/x509_vpm.c
385
if ((tmp = strdup(src)) == NULL)
crypto/libressl/crypto/x509/x509_vpm.c
390
if ((tmp = malloc(srclen)) == NULL)
crypto/libressl/crypto/x509/x509_vpm.c
392
memcpy(tmp, src, srclen);
crypto/libressl/crypto/x509/x509_vpm.c
397
*pdest = tmp;
crypto/libressl/ssl/ssl_clnt.c
1917
unsigned char premaster_secret[32], shared_ukm[32], tmp[256];
crypto/libressl/ssl/ssl_clnt.c
1996
if (EVP_PKEY_encrypt(pkey_ctx, tmp, &msglen, premaster_secret,
crypto/libressl/ssl/ssl_clnt.c
2004
if (!CBB_add_bytes(&gostblob, tmp, msglen))
crypto/libressl/ssl/ssl_lib.c
910
SSL_CERT *tmp;
crypto/libressl/ssl/ssl_lib.c
924
tmp = t->cert;
crypto/libressl/ssl/ssl_lib.c
930
ssl_cert_free(tmp);
crypto/libressl/ssl/ssl_sess.c
320
unsigned int tmp;
crypto/libressl/ssl/ssl_sess.c
371
tmp = ss->session_id_length;
crypto/libressl/ssl/ssl_sess.c
372
if (!cb(s, ss->session_id, &tmp)) {
crypto/libressl/ssl/ssl_sess.c
383
if (tmp == 0 || tmp > ss->session_id_length) {
crypto/libressl/ssl/ssl_sess.c
389
ss->session_id_length = tmp;
crypto/libressl/tls/tls_conninfo.c
230
const char *tmp;
crypto/libressl/tls/tls_conninfo.c
242
if ((tmp = SSL_get_cipher(ctx->ssl_conn)) == NULL)
crypto/libressl/tls/tls_conninfo.c
244
if ((ctx->conninfo->cipher = strdup(tmp)) == NULL)
crypto/libressl/tls/tls_conninfo.c
254
if ((tmp = SSL_get_version(ctx->ssl_conn)) == NULL)
crypto/libressl/tls/tls_conninfo.c
256
if ((ctx->conninfo->version = strdup(tmp)) == NULL)
crypto/openssh/addr.c
460
struct xaddr tmp;
crypto/openssh/addr.c
477
if (addr_pton(addrbuf, &tmp) == -1)
crypto/openssh/addr.c
481
masklen = addr_unicast_masklen(tmp.af);
crypto/openssh/addr.c
482
if (masklen_valid(tmp.af, masklen) == -1)
crypto/openssh/addr.c
484
if (addr_host_is_all0s(&tmp, masklen) != 0)
crypto/openssh/addr.c
488
memcpy(n, &tmp, sizeof(*n));
crypto/openssh/auth-options.c
258
char *opt, *tmp, *cp, *host, **permits = *permitsp;
crypto/openssh/auth-options.c
274
if (asprintf(&tmp, "*:%s", opt) == -1) {
crypto/openssh/auth-options.c
280
opt = tmp;
crypto/openssh/auth-options.c
282
if ((tmp = strdup(opt)) == NULL) {
crypto/openssh/auth-options.c
287
cp = tmp;
crypto/openssh/auth-options.c
291
free(tmp);
crypto/openssh/auth-options.c
302
free(tmp);
crypto/openssh/auth-options.c
308
free(tmp);
crypto/openssh/auth-options.c
326
char **oarray, *opt, *cp, *tmp;
crypto/openssh/auth-options.c
412
if ((tmp = strchr(opt, '=')) == NULL) {
crypto/openssh/auth-options.c
421
l = (size_t)(tmp - opt);
crypto/openssh/auth-options.c
539
const char *tmp;
crypto/openssh/auth-options.c
551
tmp = primary->required_from_host_cert;
crypto/openssh/auth-options.c
552
if (tmp == NULL)
crypto/openssh/auth-options.c
553
tmp = additional->required_from_host_cert;
crypto/openssh/auth-options.c
554
if (tmp != NULL && (ret->required_from_host_cert = strdup(tmp)) == NULL)
crypto/openssh/auth-options.c
556
tmp = primary->required_from_host_keys;
crypto/openssh/auth-options.c
557
if (tmp == NULL)
crypto/openssh/auth-options.c
558
tmp = additional->required_from_host_keys;
crypto/openssh/auth-options.c
559
if (tmp != NULL && (ret->required_from_host_keys = strdup(tmp)) == NULL)
crypto/openssh/auth-options.c
738
u_int tmp;
crypto/openssh/auth-options.c
741
if ((r = sshbuf_get_u32(m, &tmp)) != 0 ||
crypto/openssh/auth-options.c
744
if (tmp > INT_MAX) {
crypto/openssh/auth-options.c
748
n = tmp;
crypto/openssh/auth-options.c
855
u_int tmp;
crypto/openssh/auth-options.c
884
(r = sshbuf_get_u32(m, &tmp)) != 0)
crypto/openssh/auth-options.c
886
opts->force_tun_device = f ? -1 : (int)tmp;
crypto/openssh/auth2-pubkey.c
353
char *tmp, *username = NULL, *command = NULL, **av = NULL;
crypto/openssh/auth2-pubkey.c
419
tmp = percent_expand(av[i],
crypto/openssh/auth2-pubkey.c
434
if (tmp == NULL)
crypto/openssh/auth2-pubkey.c
437
av[i] = tmp;
crypto/openssh/auth2-pubkey.c
627
char uidstr[32], *tmp, *command = NULL, **av = NULL;
crypto/openssh/auth2-pubkey.c
680
tmp = percent_expand(av[i],
crypto/openssh/auth2-pubkey.c
690
if (tmp == NULL)
crypto/openssh/auth2-pubkey.c
693
av[i] = tmp;
crypto/openssh/auth2.c
721
struct sshkey **tmp, *dup;
crypto/openssh/auth2.c
736
(tmp = recallocarray(authctxt->prev_keys, authctxt->nprev_keys,
crypto/openssh/auth2.c
739
authctxt->prev_keys = tmp;
crypto/openssh/bitmap.c
84
BITMAP_WTYPE *tmp;
crypto/openssh/bitmap.c
91
if ((tmp = recallocarray(b->d, b->len,
crypto/openssh/bitmap.c
94
b->d = tmp;
crypto/openssh/chacha.c
118
for (i = 0;i < bytes;++i) tmp[i] = m[i];
crypto/openssh/chacha.c
119
m = tmp;
crypto/openssh/chacha.c
121
c = tmp;
crypto/openssh/chacha.c
94
u8 tmp[64];
crypto/openssh/cipher.c
119
char *tmp, *ret = NULL;
crypto/openssh/cipher.c
131
if ((tmp = realloc(ret, rlen + nlen + 2)) == NULL) {
crypto/openssh/cipher.c
135
ret = tmp;
crypto/openssh/clientloop.c
2092
struct sshkey **tmp;
crypto/openssh/clientloop.c
2158
if ((tmp = recallocarray(ctx->old_keys, ctx->nold, ctx->nold + 1,
crypto/openssh/clientloop.c
2161
ctx->old_keys = tmp;
crypto/openssh/clientloop.c
2438
struct sshkey *key = NULL, **tmp;
crypto/openssh/clientloop.c
2491
if ((tmp = recallocarray(ctx->keys, ctx->nkeys, ctx->nkeys + 1,
crypto/openssh/clientloop.c
2495
ctx->keys = tmp;
crypto/openssh/clientloop.c
539
struct timespec tmp;
crypto/openssh/clientloop.c
565
tmp.tv_sec = interval_ns / (1000 * 1000 * 1000);
crypto/openssh/clientloop.c
566
tmp.tv_nsec = interval_ns % (1000 * 1000 * 1000);
crypto/openssh/clientloop.c
568
timespecadd(now, &tmp, next_interval);
crypto/openssh/clientloop.c
581
struct timespec now, tmp;
crypto/openssh/clientloop.c
652
ms_to_timespec(&tmp, SSH_KEYSTROKE_CHAFF_MIN_MS +
crypto/openssh/clientloop.c
654
timespecadd(&now, &tmp, &chaff_until);
crypto/openssh/dh.c
241
BIGNUM *tmp;
crypto/openssh/dh.c
255
if ((tmp = BN_new()) == NULL) {
crypto/openssh/dh.c
259
if (!BN_sub(tmp, dh_p, BN_value_one()) ||
crypto/openssh/dh.c
260
BN_cmp(dh_pub, tmp) != -1) { /* pub_exp > p-2 */
crypto/openssh/dh.c
261
BN_clear_free(tmp);
crypto/openssh/dh.c
265
BN_clear_free(tmp);
crypto/openssh/hostfile.c
235
struct hostkey_entry *tmp;
crypto/openssh/hostfile.c
248
if ((tmp = recallocarray(hostkeys->entries, hostkeys->num_entries,
crypto/openssh/hostfile.c
251
hostkeys->entries = tmp;
crypto/openssh/kex-names.c
102
ret = tmp;
crypto/openssh/kex-names.c
199
char *ret = NULL, *tmp = NULL, *cp, *p;
crypto/openssh/kex-names.c
209
if ((tmp = cp = strdup(b)) == NULL ||
crypto/openssh/kex-names.c
211
free(tmp);
crypto/openssh/kex-names.c
220
free(tmp);
crypto/openssh/kex-names.c
225
free(tmp);
crypto/openssh/kex-names.c
239
char *cp, *tmp, *patterns;
crypto/openssh/kex-names.c
256
if ((tmp = kex_names_cat(def, list + 1)) == NULL) {
crypto/openssh/kex-names.c
261
list = tmp;
crypto/openssh/kex-names.c
273
if ((tmp = kex_names_cat(list + 1, def)) == NULL) {
crypto/openssh/kex-names.c
278
list = tmp;
crypto/openssh/kex-names.c
305
if ((tmp = kex_names_cat(ret, matching)) == NULL) {
crypto/openssh/kex-names.c
310
ret = tmp;
crypto/openssh/kex-names.c
90
char *ret = NULL, *tmp;
crypto/openssh/kex-names.c
98
if ((tmp = realloc(ret, rlen + nlen + 2)) == NULL) {
crypto/openssh/kexgen.c
145
struct sshbuf *tmp = NULL, *server_host_key_blob = NULL;
crypto/openssh/kexgen.c
158
if ((tmp = sshbuf_fromb(server_host_key_blob)) == NULL) {
crypto/openssh/kexgen.c
162
if ((r = sshkey_fromb(tmp, &server_host_key)) != 0)
crypto/openssh/kexgen.c
248
sshbuf_free(tmp);
crypto/openssh/kexgexc.c
151
struct sshbuf *tmp = NULL, *server_host_key_blob = NULL;
crypto/openssh/kexgexc.c
165
if ((tmp = sshbuf_fromb(server_host_key_blob)) == NULL) {
crypto/openssh/kexgexc.c
169
if ((r = sshkey_fromb(tmp, &server_host_key)) != 0 ||
crypto/openssh/kexgexc.c
236
sshbuf_free(tmp);
crypto/openssh/log.c
166
char **tmp;
crypto/openssh/log.c
169
if ((tmp = recallocarray(log_verbose, nlog_verbose, nlog_verbose + 1,
crypto/openssh/log.c
171
log_verbose = tmp;
crypto/openssh/mac.c
86
char *ret = NULL, *tmp;
crypto/openssh/mac.c
94
if ((tmp = realloc(ret, rlen + nlen + 2)) == NULL) {
crypto/openssh/mac.c
98
ret = tmp;
crypto/openssh/match.c
326
char *cp, *tmp;
crypto/openssh/match.c
335
tmp = orig_prop;
crypto/openssh/match.c
337
while ((cp = strsep(&tmp, ",")) != NULL) {
crypto/openssh/misc.c
1015
char *uridup, *cp, *tmp, ch;
crypto/openssh/misc.c
1034
uridup = tmp = xstrdup(uri);
crypto/openssh/misc.c
1037
if ((cp = strchr(tmp, '@')) != NULL) {
crypto/openssh/misc.c
1042
if ((delim = strchr(tmp, ';')) != NULL) {
crypto/openssh/misc.c
1046
if (*tmp == '\0') {
crypto/openssh/misc.c
1050
if ((user = urldecode(tmp)) == NULL)
crypto/openssh/misc.c
1052
tmp = cp + 1;
crypto/openssh/misc.c
1056
if ((cp = hpdelim2(&tmp, &ch)) == NULL || *cp == '\0')
crypto/openssh/misc.c
1062
if (tmp != NULL && *tmp != '\0') {
crypto/openssh/misc.c
1065
if ((cp = strchr(tmp, '/')) != NULL)
crypto/openssh/misc.c
1067
if ((port = a2port(tmp)) <= 0)
crypto/openssh/misc.c
1069
tmp = cp ? cp + 1 : NULL;
crypto/openssh/misc.c
1071
if (tmp != NULL && *tmp != '\0') {
crypto/openssh/misc.c
1073
if ((path = urldecode(tmp)) == NULL)
crypto/openssh/misc.c
820
char *sdup, *tmp;
crypto/openssh/misc.c
833
if ((tmp = colon(sdup)) == NULL)
crypto/openssh/misc.c
837
*tmp++ = '\0';
crypto/openssh/misc.c
838
if (*tmp == '\0')
crypto/openssh/misc.c
839
tmp = ".";
crypto/openssh/misc.c
840
path = xstrdup(tmp);
crypto/openssh/misc.c
843
tmp = strrchr(sdup, '@');
crypto/openssh/misc.c
844
if (tmp != NULL) {
crypto/openssh/misc.c
845
*tmp++ = '\0';
crypto/openssh/misc.c
846
host = xstrdup(cleanhostname(tmp));
crypto/openssh/misc.c
887
char *sdup, *cp, *tmp;
crypto/openssh/misc.c
898
if ((sdup = tmp = strdup(s)) == NULL)
crypto/openssh/misc.c
901
if ((cp = strrchr(tmp, '@')) != NULL) {
crypto/openssh/misc.c
903
if (*tmp == '\0')
crypto/openssh/misc.c
905
if ((user = strdup(tmp)) == NULL)
crypto/openssh/misc.c
907
tmp = cp + 1;
crypto/openssh/misc.c
910
if ((cp = hpdelim(&tmp)) == NULL || *cp == '\0')
crypto/openssh/misc.c
914
if (tmp != NULL && *tmp != '\0') {
crypto/openssh/misc.c
915
if ((port = a2port(tmp)) <= 0)
crypto/openssh/moduli.c
454
char tmp[PATH_MAX];
crypto/openssh/moduli.c
457
r = snprintf(tmp, sizeof(tmp), "%s.XXXXXXXXXX", cpfile);
crypto/openssh/moduli.c
462
if ((r = mkstemp(tmp)) == -1) {
crypto/openssh/moduli.c
463
logit("mkstemp(%s): %s", tmp, strerror(errno));
crypto/openssh/moduli.c
468
unlink(tmp);
crypto/openssh/moduli.c
474
if (writeok && closeok && rename(tmp, cpfile) == 0) {
crypto/openssh/moduli.c
480
(void)unlink(tmp);
crypto/openssh/packet.c
1168
u_char tmp, padlen, pad = 0;
crypto/openssh/packet.c
1226
tmp = state->extra_pad;
crypto/openssh/packet.c
1230
if (state->extra_pad < tmp)
crypto/openssh/packet.c
1232
tmp = (len + padlen) % state->extra_pad;
crypto/openssh/packet.c
1234
if (tmp > state->extra_pad)
crypto/openssh/packet.c
1236
pad = state->extra_pad - tmp;
crypto/openssh/packet.c
1239
tmp = padlen;
crypto/openssh/packet.c
1242
if (padlen < tmp)
crypto/openssh/scp.c
1557
char *filename, *tmp = NULL;
crypto/openssh/scp.c
1618
tmp = xstrdup(g.gl_pathv[i]);
crypto/openssh/scp.c
1619
if ((filename = basename(tmp)) == NULL) {
crypto/openssh/scp.c
1620
error("basename %s: %s", tmp, strerror(errno));
crypto/openssh/scp.c
1642
free(tmp);
crypto/openssh/scp.c
1643
tmp = NULL;
crypto/openssh/scp.c
1648
free(tmp);
crypto/openssh/scp.c
1994
char *abs_src = NULL, *tmp = NULL;
crypto/openssh/scp.c
2039
tmp = xstrdup(g.gl_pathv[i]);
crypto/openssh/scp.c
2040
if ((filename = basename(tmp)) == NULL) {
crypto/openssh/scp.c
2041
error("basename %s: %s", tmp, strerror(errno));
crypto/openssh/scp.c
2063
free(tmp);
crypto/openssh/scp.c
2064
tmp = NULL;
crypto/openssh/scp.c
2071
free(tmp);
crypto/openssh/scp.c
769
char **tmp;
crypto/openssh/scp.c
771
if ((tmp = reallocarray(*ap, *np + 1, sizeof(*tmp))) == NULL)
crypto/openssh/scp.c
773
tmp[(*np)] = cp;
crypto/openssh/scp.c
775
*ap = tmp;
crypto/openssh/serverloop.c
489
char *tmp, *ifname = NULL;
crypto/openssh/serverloop.c
538
tmp = tun_fwd_ifnames;
crypto/openssh/serverloop.c
543
free(tmp);
crypto/openssh/session.c
1350
char uidstr[32], *chroot_path, *tmp;
crypto/openssh/session.c
1380
tmp = tilde_expand_filename(options.chroot_directory,
crypto/openssh/session.c
1384
chroot_path = percent_expand(tmp, "h", pw->pw_dir,
crypto/openssh/session.c
1387
free(tmp);
crypto/openssh/session.c
1732
Session *s, *tmp;
crypto/openssh/session.c
1739
tmp = xrecallocarray(sessions, sessions_nalloc,
crypto/openssh/session.c
1741
if (tmp == NULL) {
crypto/openssh/session.c
1746
sessions = tmp;
crypto/openssh/session.c
307
char *tmp, *cp, *host;
crypto/openssh/session.c
314
tmp = cp = xstrdup(auth_opts->permitopen[i]);
crypto/openssh/session.c
323
free(tmp);
crypto/openssh/session.c
329
tmp = cp = xstrdup(auth_opts->permitlisten[i]);
crypto/openssh/session.c
338
free(tmp);
crypto/openssh/sftp.c
1555
char *path1, *path2, *tmp;
crypto/openssh/sftp.c
1647
if ((tmp = sftp_realpath(conn, path1)) == NULL) {
crypto/openssh/sftp.c
1651
if (sftp_stat(conn, tmp, 0, &aa) != 0) {
crypto/openssh/sftp.c
1652
free(tmp);
crypto/openssh/sftp.c
1658
free(tmp);
crypto/openssh/sftp.c
1664
"a directory", tmp);
crypto/openssh/sftp.c
1665
free(tmp);
crypto/openssh/sftp.c
1670
*pwd = tmp;
crypto/openssh/sftp.c
1679
tmp = NULL;
crypto/openssh/sftp.c
1681
tmp = *pwd;
crypto/openssh/sftp.c
1684
err = do_globbed_ls(conn, path1, tmp, lflag);
crypto/openssh/sftp.c
1696
tmp = tilde_expand_filename(path1, getuid());
crypto/openssh/sftp.c
1698
path1 = tmp;
crypto/openssh/sftp.c
1836
char *tmp;
crypto/openssh/sftp.c
1855
tmp = llen > len ? list[y] + len : "";
crypto/openssh/sftp.c
1856
mprintf("%-*s", colspace, tmp);
crypto/openssh/sftp.c
1892
char *tmp = xstrdup(list[0]);
crypto/openssh/sftp.c
1894
tmp[matchlen] = '\0';
crypto/openssh/sftp.c
1895
return tmp;
crypto/openssh/sftp.c
1908
char *tmp, **list, argterm[3];
crypto/openssh/sftp.c
1941
tmp = complete_ambiguous(cmd, list, count);
crypto/openssh/sftp.c
1949
if (tmp != NULL) {
crypto/openssh/sftp.c
1950
tmplen = strlen(tmp);
crypto/openssh/sftp.c
1954
if (el_insertstr(el, tmp + cmdlen) == -1)
crypto/openssh/sftp.c
1968
free(tmp);
crypto/openssh/sftp.c
2005
char *tmp, *tmp2, ins[8];
crypto/openssh/sftp.c
2012
tmp = xstrdup("*");
crypto/openssh/sftp.c
2014
xasprintf(&tmp, "%s*", file);
crypto/openssh/sftp.c
2017
isabs = path_absolute(tmp);
crypto/openssh/sftp.c
2021
tmp = make_absolute_pwd_glob(tmp, remote_path);
crypto/openssh/sftp.c
2022
sftp_glob(conn, tmp, GLOB_DOOFFS|GLOB_MARK, NULL, &g);
crypto/openssh/sftp.c
2024
(void)glob(tmp, GLOB_DOOFFS|GLOB_MARK, NULL, &g);
crypto/openssh/sftp.c
2027
for (hadglob = tmplen = pwdlen = 0; tmp[tmplen] != 0; tmplen++) {
crypto/openssh/sftp.c
2029
if (tmp[tmplen] == '*' || tmp[tmplen] == '?') {
crypto/openssh/sftp.c
2030
if (tmp[tmplen] != '*' || tmp[tmplen + 1] != '\0')
crypto/openssh/sftp.c
2034
if (tmp[tmplen] == '\\' && tmp[tmplen + 1] != '\0')
crypto/openssh/sftp.c
2036
if (tmp[tmplen] == '/')
crypto/openssh/sftp.c
2039
free(tmp);
crypto/openssh/sftp.c
2040
tmp = NULL;
crypto/openssh/sftp.c
2053
tmp = path_strip(tmp2, isabs ? NULL : remote_path);
crypto/openssh/sftp.c
2056
if (tmp == NULL)
crypto/openssh/sftp.c
2059
tmplen = strlen(tmp);
crypto/openssh/sftp.c
2073
tmp2 = tmp + filelen - cesc;
crypto/openssh/sftp.c
2119
free(tmp);
crypto/openssh/sftp.c
2440
int r, in, out, ch, err, tmp, port = -1, noisy = 0;
crypto/openssh/sftp.c
2615
switch (parse_uri("sftp", *argv, &user, &host, &tmp, &file1)) {
crypto/openssh/sftp.c
2620
if (tmp != -1)
crypto/openssh/sftp.c
2621
port = tmp;
crypto/openssh/sftp.c
2662
if ((r = argv_split(sftp_direct, &tmp, &cpp, 1)) != 0)
crypto/openssh/sftp.c
2667
argv_free(cpp, tmp);
crypto/openssh/sftp.c
652
char *filename, *abs_src = NULL, *abs_dst = NULL, *tmp = NULL;
crypto/openssh/sftp.c
682
tmp = xstrdup(g.gl_pathv[i]);
crypto/openssh/sftp.c
683
if ((filename = basename(tmp)) == NULL) {
crypto/openssh/sftp.c
684
error("basename %s: %s", tmp, strerror(errno));
crypto/openssh/sftp.c
685
free(tmp);
crypto/openssh/sftp.c
701
free(tmp);
crypto/openssh/sftp.c
739
char *tmp = NULL, *filename = NULL;
crypto/openssh/sftp.c
777
tmp = xstrdup(g.gl_pathv[i]);
crypto/openssh/sftp.c
778
if ((filename = basename(tmp)) == NULL) {
crypto/openssh/sftp.c
779
error("basename %s: %s", tmp, strerror(errno));
crypto/openssh/sftp.c
780
free(tmp);
crypto/openssh/sftp.c
798
free(tmp);
crypto/openssh/sftp.c
862
char *tmp;
crypto/openssh/sftp.c
871
tmp = path_strip(path, strip_path);
crypto/openssh/sftp.c
872
m += strlen(tmp);
crypto/openssh/sftp.c
873
free(tmp);
crypto/openssh/sftp.c
893
char *tmp, *fname;
crypto/openssh/sftp.c
898
tmp = sftp_path_append(path, d[n]->filename);
crypto/openssh/sftp.c
899
fname = path_strip(tmp, strip_path);
crypto/openssh/sftp.c
900
free(tmp);
crypto/openssh/srclimit.c
219
struct penalty *penalty, *tmp;
crypto/openssh/srclimit.c
222
RB_FOREACH_SAFE(penalty, penalties_by_expiry, by_expiry, tmp) {
crypto/openssh/ssh-ecdsa-sk.c
250
char *tmp = NULL;
crypto/openssh/ssh-ecdsa-sk.c
313
fprintf(stderr, "%s: sig_r: %s\n", __func__, (tmp = BN_bn2hex(sig_r)));
crypto/openssh/ssh-ecdsa-sk.c
314
free(tmp);
crypto/openssh/ssh-ecdsa-sk.c
315
fprintf(stderr, "%s: sig_s: %s\n", __func__, (tmp = BN_bn2hex(sig_s)));
crypto/openssh/ssh-ecdsa-sk.c
316
free(tmp);
crypto/openssh/ssh-keygen.c
1313
char *cp, tmp[PATH_MAX], old[PATH_MAX];
crypto/openssh/ssh-keygen.c
1342
if (strlcpy(tmp, identity_file, sizeof(tmp)) >= sizeof(tmp) ||
crypto/openssh/ssh-keygen.c
1343
strlcat(tmp, ".XXXXXXXXXX", sizeof(tmp)) >= sizeof(tmp) ||
crypto/openssh/ssh-keygen.c
1348
if ((fd = mkstemp(tmp)) == -1)
crypto/openssh/ssh-keygen.c
1352
unlink(tmp);
crypto/openssh/ssh-keygen.c
1365
unlink(tmp);
crypto/openssh/ssh-keygen.c
1377
unlink(tmp);
crypto/openssh/ssh-keygen.c
1383
unlink(tmp);
crypto/openssh/ssh-keygen.c
1392
if (rename(tmp, identity_file) == -1) {
crypto/openssh/ssh-keygen.c
1393
error("rename\"%s\" to \"%s\": %s", tmp, identity_file,
crypto/openssh/ssh-keygen.c
1395
unlink(tmp);
crypto/openssh/ssh-keygen.c
1774
char valid[64], *otmp, *tmp, *cp, *out, *comment;
crypto/openssh/ssh-keygen.c
1783
tmp = tilde_expand_filename(ca_key_path, pw->pw_uid);
crypto/openssh/ssh-keygen.c
1786
if ((ca = load_pkcs11_key(tmp)) == NULL)
crypto/openssh/ssh-keygen.c
1794
if ((r = sshkey_load_public(tmp, &ca, NULL)) != 0)
crypto/openssh/ssh-keygen.c
1795
fatal_r(r, "Cannot load CA public key %s", tmp);
crypto/openssh/ssh-keygen.c
1808
fatal("CA key %s not found in agent", tmp);
crypto/openssh/ssh-keygen.c
1813
ca = load_identity(tmp, NULL);
crypto/openssh/ssh-keygen.c
1821
free(tmp);
crypto/openssh/ssh-keygen.c
1839
otmp = tmp = xstrdup(cert_principals);
crypto/openssh/ssh-keygen.c
1841
for (; (cp = strsep(&tmp, ",")) != NULL; n++) {
crypto/openssh/ssh-keygen.c
1851
tmp = tilde_expand_filename(argv[i], pw->pw_uid);
crypto/openssh/ssh-keygen.c
1852
if ((r = sshkey_load_public(tmp, &public, &comment)) != 0)
crypto/openssh/ssh-keygen.c
1853
fatal_r(r, "load pubkey \"%s\"", tmp);
crypto/openssh/ssh-keygen.c
1856
tmp, sshkey_type(public));
crypto/openssh/ssh-keygen.c
1860
fatal_r(r, "Could not upgrade key %s to certificate", tmp);
crypto/openssh/ssh-keygen.c
1879
fatal_r(r, "Couldn't certify %s via agent", tmp);
crypto/openssh/ssh-keygen.c
1891
fatal_r(r, "Couldn't certify key %s", tmp);
crypto/openssh/ssh-keygen.c
1894
if ((cp = strrchr(tmp, '.')) != NULL && strcmp(cp, ".pub") == 0)
crypto/openssh/ssh-keygen.c
1896
xasprintf(&out, "%s-cert.pub", tmp);
crypto/openssh/ssh-keygen.c
1897
free(tmp);
crypto/openssh/ssh-keygen.c
2248
char *tmp;
crypto/openssh/ssh-keygen.c
2263
tmp = xmalloc(tlen + 4 + 1);
crypto/openssh/ssh-keygen.c
2264
strlcpy(tmp, cp, tlen + 1);
crypto/openssh/ssh-keygen.c
2266
tmp[tlen++] = '=';
crypto/openssh/ssh-keygen.c
2267
tmp[tlen] = '\0';
crypto/openssh/ssh-keygen.c
2271
if ((r = sshbuf_b64tod(b, tmp)) != 0)
crypto/openssh/ssh-keygen.c
2273
free(tmp);
crypto/openssh/ssh-keygen.c
2443
char *tmp;
crypto/openssh/ssh-keygen.c
2459
tmp = tilde_expand_filename(ca_key_path, pw->pw_uid);
crypto/openssh/ssh-keygen.c
2460
if ((r = sshkey_load_public(tmp, &ca, NULL)) != 0)
crypto/openssh/ssh-keygen.c
2461
fatal_r(r, "Cannot load CA public key %s", tmp);
crypto/openssh/ssh-keygen.c
2462
free(tmp);
crypto/openssh/ssh-keygen.c
2898
char *principals = NULL, *cp, *tmp;
crypto/openssh/ssh-keygen.c
2926
tmp = principals;
crypto/openssh/ssh-keygen.c
2927
while ((cp = strsep(&tmp, ",")) != NULL && *cp != '\0')
crypto/openssh/ssh-sk-client.c
403
struct sshsk_resident_key *srk = NULL, **srks = NULL, **tmp;
crypto/openssh/ssh-sk-client.c
450
if ((tmp = recallocarray(srks, nsrks, nsrks + 1,
crypto/openssh/ssh-sk-client.c
458
srks = tmp;
crypto/openssh/sshbuf-misc.c
134
struct sshbuf *tmp;
crypto/openssh/sshbuf-misc.c
137
if ((tmp = sshbuf_new()) == NULL)
crypto/openssh/sshbuf-misc.c
139
if (sshbuf_dtob64(buf, tmp, wrap) != 0) {
crypto/openssh/sshbuf-misc.c
140
sshbuf_free(tmp);
crypto/openssh/sshbuf-misc.c
143
ret = sshbuf_dup_string(tmp);
crypto/openssh/sshbuf-misc.c
144
sshbuf_free(tmp);
crypto/openssh/sshconnect.c
105
free(tmp);
crypto/openssh/sshconnect.c
877
char *key_fp = NULL, *keytext = NULL, *tmp;
crypto/openssh/sshconnect.c
910
tmp = percent_dollar_expand(av[i],
crypto/openssh/sshconnect.c
918
if (tmp == NULL)
crypto/openssh/sshconnect.c
92
char *tmp, *ret, strport[NI_MAXSERV];
crypto/openssh/sshconnect.c
921
av[i] = tmp;
crypto/openssh/sshconnect.c
97
xasprintf(&tmp, "exec %s", proxy_command);
crypto/openssh/sshconnect.c
98
ret = percent_expand(tmp,
crypto/openssh/sshconnect2.c
1154
char *allowed, *oallowed, *cp, *tmp, *alg = NULL;
crypto/openssh/sshconnect2.c
1188
tmp = match_list(sshkey_sigalg_by_name(cp),
crypto/openssh/sshconnect2.c
1190
if (tmp != NULL)
crypto/openssh/sshconnect2.c
1192
free(tmp);
crypto/openssh/sshconnect2.c
1667
struct identity *id, *id2, *tmp;
crypto/openssh/sshconnect2.c
1766
TAILQ_FOREACH_SAFE(id, &files, next, tmp) {
crypto/openssh/sshd-session.c
246
struct sshkey *tmp;
crypto/openssh/sshd-session.c
253
sensitive_data.host_keys[i], &tmp)) != 0)
crypto/openssh/sshd-session.c
257
sensitive_data.host_keys[i] = tmp;
crypto/openssh/sshkey.c
1543
struct sshkey *kswap = NULL, tmp;
crypto/openssh/sshkey.c
1617
tmp = *kswap;
crypto/openssh/sshkey.c
1619
*k = tmp;
crypto/openssh/sshkey.c
1639
explicit_bzero(&tmp, sizeof(tmp));
crypto/openssh/sshkey.c
1679
struct sshkey *kswap = NULL, tmp;
crypto/openssh/sshkey.c
1745
tmp = *kswap;
crypto/openssh/sshkey.c
1747
*k = tmp;
crypto/openssh/sshkey.c
1755
explicit_bzero(&tmp, sizeof(tmp));
crypto/openssh/sshkey.c
2592
BIGNUM *order = NULL, *x = NULL, *y = NULL, *tmp = NULL;
crypto/openssh/sshkey.c
2618
(tmp = BN_new()) == NULL) {
crypto/openssh/sshkey.c
2647
if (!BN_sub(tmp, order, BN_value_one())) {
crypto/openssh/sshkey.c
2651
if (BN_cmp(x, tmp) >= 0 || BN_cmp(y, tmp) >= 0)
crypto/openssh/sshkey.c
2658
BN_clear_free(tmp);
crypto/openssh/sshkey.c
2666
BIGNUM *order = NULL, *tmp = NULL;
crypto/openssh/sshkey.c
2669
if ((order = BN_new()) == NULL || (tmp = BN_new()) == NULL) {
crypto/openssh/sshkey.c
2684
if (!BN_sub(tmp, order, BN_value_one())) {
crypto/openssh/sshkey.c
2688
if (BN_cmp(EC_KEY_get0_private_key(key), tmp) >= 0)
crypto/openssh/sshkey.c
2693
BN_clear_free(tmp);
crypto/openssh/sshkey.c
321
char *tmp, *ret = NULL;
crypto/openssh/sshkey.c
336
if ((tmp = realloc(ret, rlen + nlen + 2)) == NULL) {
crypto/openssh/sshkey.c
340
ret = tmp;
crypto/openssh/sshkey.c
783
struct sshbuf *tmp;
crypto/openssh/sshkey.c
786
if ((tmp = sshbuf_new()) == NULL)
crypto/openssh/sshkey.c
788
r = to_blob_buf(key, tmp, 0, opts);
crypto/openssh/sshkey.c
790
r = sshbuf_put_stringb(b, tmp);
crypto/openssh/sshkey.c
791
sshbuf_free(tmp);
crypto/openssh/sshsig.c
1077
char *found, *line = NULL, **principals = NULL, **tmp;
crypto/openssh/sshsig.c
1107
if ((tmp = recallocarray(principals, nprincipals,
crypto/openssh/sshsig.c
1113
principals = tmp;
crypto/openssh/sshsig.c
735
char *opts = NULL, *tmp, *cp, *principals = NULL;
crypto/openssh/sshsig.c
754
if ((tmp = strdelimw(&cp)) == NULL || cp == NULL) {
crypto/openssh/sshsig.c
759
if ((principals = strdup(tmp)) == NULL) {
crypto/openssh/xmss_fast.c
812
bds_state tmp;
crypto/openssh/xmss_fast.c
936
memcpy(&tmp, states+params->d + i, sizeof(bds_state));
crypto/openssh/xmss_fast.c
938
memcpy(states + i, &tmp, sizeof(bds_state));
games/battlestar/save.c
104
tmp = location == dayfile;
games/battlestar/save.c
105
fwrite(&tmp, sizeof tmp, 1, fp);
games/battlestar/save.c
39
int tmp;
games/battlestar/save.c
50
fread(&tmp, sizeof tmp, 1, fp);
games/battlestar/save.c
51
location = tmp ? dayfile : nightfile;
games/battlestar/save.c
91
int tmp;
games/bcd/bcd.c
259
char tmp[1024];
games/bcd/bcd.c
262
if (fgets(tmp, sizeof(tmp), stdin) == NULL)
games/bcd/bcd.c
265
if (fgets(tmp, sizeof(tmp), stdin) == NULL)
games/bcd/bcd.c
272
if (fgets(tmp, sizeof(tmp), stdin) == NULL)
games/boggle/boggle/bog.c
585
const char *tmp, **cubes;
games/boggle/boggle/bog.c
608
tmp = cubes[p];
games/boggle/boggle/bog.c
610
cubes[q] = tmp;
games/gomoku/main.c
368
char tmp[128];
games/gomoku/main.c
477
printcombo(cbp, tmp, sizeof(tmp));
games/gomoku/main.c
478
debuglog("%s", tmp);
games/gomoku/main.c
84
char *tmp;
games/gomoku/main.c
91
tmp = getlogin();
games/gomoku/main.c
92
if (tmp) {
games/gomoku/main.c
93
strlcpy(user, tmp, sizeof(user));
games/gomoku/pickmove.c
421
char tmp[128];
games/gomoku/pickmove.c
512
printcombo(ncbp, tmp, sizeof(tmp));
games/gomoku/pickmove.c
513
debuglog("%s", tmp);
games/gomoku/pickmove.c
656
char tmp[128];
games/gomoku/pickmove.c
769
printcombo(ncbp, tmp, sizeof(tmp));
games/gomoku/pickmove.c
770
debuglog("%s", tmp);
games/gomoku/pickmove.c
807
char tmp[128];
games/gomoku/pickmove.c
810
printcombo(ocbp, tmp, sizeof(tmp));
games/gomoku/pickmove.c
811
debuglog("E%c %s", "bw"[curcolor], tmp);
games/hack/hack.apply.c
156
int tmp = dist(mtmp->mx, mtmp->my);
games/hack/hack.apply.c
161
if (tmp < 9 && !mtmp->isshk && rn2(4)) {
games/hack/hack.apply.c
166
if (tmp < 3)
games/hack/hack.apply.c
170
tmp2 += rnd(1 + 50 / tmp);
games/hack/hack.do.c
330
int tmp;
games/hack/hack.do.c
408
tmp = -1 + u.ulevel + mon->data->ac + abon();
games/hack/hack.do.c
412
tmp -= 4;
games/hack/hack.do.c
414
tmp += uwep->spe;
games/hack/hack.do.c
417
tmp += 4;
games/hack/hack.do.c
418
tmp += obj->spe;
games/hack/hack.do.c
419
if (u.uswallow || tmp >= rnd(20)) {
games/hack/hack.do.c
436
tmp = -1 + u.ulevel + mon->data->ac + abon();
games/hack/hack.do.c
438
tmp += 2;
games/hack/hack.do.c
440
tmp -= 2;
games/hack/hack.do.c
441
if (u.uswallow || tmp >= rnd(20)) {
games/hack/hack.dog.c
301
int tmp = rooms[dogroom].fdoor;
games/hack/hack.dog.c
307
dist(doors[tmp].x, doors[tmp].y)) {
games/hack/hack.dog.c
308
gx = doors[tmp].x;
games/hack/hack.dog.c
309
gy = doors[tmp].y;
games/hack/hack.dog.c
311
tmp++;
games/hack/hack.eat.c
167
int tmp;
games/hack/hack.eat.c
196
tmp = 1;
games/hack/hack.eat.c
200
tmp = 3;
games/hack/hack.eat.c
204
tmp = 6;
games/hack/hack.eat.c
226
tmp = 10 + rn2(1 + 500 / ((int) (u.ulevel + u.ustr)));
games/hack/hack.eat.c
228
tin.reqtime = tmp;
games/hack/hack.end.c
208
long int tmp;
games/hack/hack.end.c
209
tmp = u.ugold - u.ugold0;
games/hack/hack.end.c
210
if (tmp < 0)
games/hack/hack.end.c
211
tmp = 0;
games/hack/hack.end.c
213
tmp -= tmp / 10;
games/hack/hack.end.c
214
u.urexp += tmp;
games/hack/hack.fight.c
215
int tmp;
games/hack/hack.fight.c
219
tmp = rnd(2); /* attack with bare hands */
games/hack/hack.fight.c
227
tmp = rnd(2);
games/hack/hack.fight.c
230
tmp = rnd(objects[obj->otyp].wldam);
games/hack/hack.fight.c
232
tmp += d(2, 6);
games/hack/hack.fight.c
234
tmp += rnd(4);
games/hack/hack.fight.c
236
tmp = rnd(objects[obj->otyp].wsdam);
games/hack/hack.fight.c
238
tmp += obj->spe;
games/hack/hack.fight.c
247
tmp++;
games/hack/hack.fight.c
253
tmp += rnd(10);
games/hack/hack.fight.c
257
tmp = rnd(25);
games/hack/hack.fight.c
270
tmp = 1;
games/hack/hack.fight.c
280
tmp = 1;
games/hack/hack.fight.c
285
tmp = obj->owt / 10;
games/hack/hack.fight.c
286
if (tmp < 1)
games/hack/hack.fight.c
287
tmp = 1;
games/hack/hack.fight.c
289
tmp = rnd(tmp);
games/hack/hack.fight.c
290
if (tmp > 6)
games/hack/hack.fight.c
291
tmp = 6;
games/hack/hack.fight.c
296
tmp += u.udaminc + dbon();
games/hack/hack.fight.c
298
if ((tmp -= u.uswldtim) <= 0) {
games/hack/hack.fight.c
303
if (tmp < 1)
games/hack/hack.fight.c
304
tmp = 1;
games/hack/hack.fight.c
305
mon->mhp -= tmp;
games/hack/hack.fight.c
312
mon->mfleetim += 10 * rnd(tmp);
games/hack/hack.fight.c
320
mon, exclam(tmp));
games/hack/hack.fight.c
324
pline("You hit %s%s", monnam(mon), exclam(tmp));
games/hack/hack.fight.c
343
schar tmp;
games/hack/hack.fight.c
384
tmp = u.uluck + u.ulevel + mdat->ac + abon();
games/hack/hack.fight.c
387
tmp += uwep->spe;
games/hack/hack.fight.c
389
tmp -= 1;
games/hack/hack.fight.c
391
tmp += 2;
games/hack/hack.fight.c
393
tmp += 3;
games/hack/hack.fight.c
396
tmp += 2;
games/hack/hack.fight.c
400
tmp += 2;
games/hack/hack.fight.c
403
tmp += 4;
games/hack/hack.fight.c
408
tmp += 2;
games/hack/hack.fight.c
410
tmp -= 3;
games/hack/hack.fight.c
413
tmp -= (inv_weight() + 40) / 20;
games/hack/hack.fight.c
415
if (tmp <= rnd(20) && !u.uswallow) {
games/hack/hack.fight.c
78
schar tmp;
games/hack/hack.fight.c
85
tmp = pd->ac + pa->mlevel;
games/hack/hack.fight.c
87
tmp += 4;
games/hack/hack.fight.c
91
didhit = (tmp > rnd(20));
games/hack/hack.lev.c
117
for (tmp = 1; tmp < 32; tmp++) {
games/hack/hack.lev.c
118
for (wtmp = wsegs[tmp]; wtmp; wtmp = wtmp2) {
games/hack/hack.lev.c
122
wsegs[tmp] = 0;
games/hack/hack.lev.c
211
int tmp;
games/hack/hack.lev.c
290
for (tmp = 1; tmp < 32; tmp++)
games/hack/hack.lev.c
291
if (wsegs[tmp]) {
games/hack/hack.lev.c
292
wheads[tmp] = wsegs[tmp] = wtmp = newseg();
games/hack/hack.lev.c
297
wheads[tmp]->nseg = wtmp = newseg();
games/hack/hack.lev.c
298
wheads[tmp] = wtmp;
games/hack/hack.lev.c
84
int tmp;
games/hack/hack.makemon.c
100
if (tmp < dlevel - 4)
games/hack/hack.makemon.c
101
tmp = rn2(ct * dlevel / 24 + 12);
games/hack/hack.makemon.c
102
if (tmp >= ct)
games/hack/hack.makemon.c
103
tmp = rn1(ct - ct / 2, ct / 2);
games/hack/hack.makemon.c
108
if (!tmp--)
games/hack/hack.makemon.c
81
int tmp, ct;
games/hack/hack.makemon.c
99
tmp = rn2(ct * dlevel / 24 + 7);
games/hack/hack.mhitu.c
122
tmp = hitu(mtmp, d(mdat->damn, mdat->damd));
games/hack/hack.mhitu.c
124
tmp = 0;
games/hack/hack.mhitu.c
126
tmp += hitu(mtmp, d(mdat->damn, mdat->damd));
games/hack/hack.mhitu.c
128
ctmp = tmp && !mtmp->mcan &&
games/hack/hack.mhitu.c
147
if (tmp)
games/hack/hack.mhitu.c
151
if (tmp)
games/hack/hack.mhitu.c
240
tmp = hitu(mtmp, rnd(3));
games/hack/hack.mhitu.c
241
tmp &= hitu(mtmp, rnd(3));
games/hack/hack.mhitu.c
242
if (tmp) {
games/hack/hack.mhitu.c
253
if (tmp)
games/hack/hack.mhitu.c
285
tmp = hitu(mtmp, rnd(6));
games/hack/hack.mhitu.c
286
if (hitu(mtmp, rnd(6)) && tmp && /* hits with both paws */
games/hack/hack.mhitu.c
307
if (tmp && uarmh && !uarmh->rustfree &&
games/hack/hack.mhitu.c
324
if (tmp && !rn2(8)) {
games/hack/hack.mhitu.c
350
if (tmp)
games/hack/hack.mhitu.c
361
if (tmp)
games/hack/hack.mhitu.c
401
int tmp, res;
games/hack/hack.mhitu.c
416
tmp = u.uac;
games/hack/hack.mhitu.c
418
if (tmp < 0) {
games/hack/hack.mhitu.c
419
dam += tmp; /* decrease damage */
games/hack/hack.mhitu.c
422
tmp = -rn2(-tmp);
games/hack/hack.mhitu.c
424
tmp += mtmp->data->mlevel;
games/hack/hack.mhitu.c
426
tmp += 4;
games/hack/hack.mhitu.c
428
tmp -= 2;
games/hack/hack.mhitu.c
430
tmp -= 2;
games/hack/hack.mhitu.c
431
if (tmp <= rnd(20)) {
games/hack/hack.mhitu.c
75
int tmp, ctmp;
games/hack/hack.mklev.c
432
int tmp;
games/hack/hack.mklev.c
442
tmp = doorindex;
games/hack/hack.mklev.c
444
for (tmp = doorindex; tmp > broom->fdoor; tmp--)
games/hack/hack.mklev.c
445
doors[tmp] = doors[tmp - 1];
games/hack/hack.mklev.c
447
doors[tmp].x = x;
games/hack/hack.mklev.c
448
doors[tmp].y = y;
games/hack/hack.mon.c
231
int tmp = 0, nearby, scared;
games/hack/hack.mon.c
296
tmp = m_move(mtmp, 0); /* 2: monster died moving */
games/hack/hack.mon.c
297
if (tmp == 2 || (tmp && mdat->mmove <= 12))
games/hack/hack.mon.c
298
return (tmp == 2);
games/hack/hack.mon.c
307
tmp = m_move(mtmp, 1);
games/hack/hack.mon.c
308
return (tmp == 2);
games/hack/hack.mon.c
788
int tmp, nk, x, y;
games/hack/hack.mon.c
808
tmp = mdat - mons; /* strchr in mons array (if not 'd', '@', ...) */
games/hack/hack.mon.c
809
if (tmp >= 0 && tmp < CMNUM + 2) {
games/hack/hack.mon.c
810
u.nr_killed[tmp]++;
games/hack/hack.mon.c
811
if ((nk = u.nr_killed[tmp]) > MAXMONNO &&
games/hack/hack.mon.c
826
tmp = 1 + mdat->mlevel * mdat->mlevel;
games/hack/hack.mon.c
828
tmp += 2 * (7 - mdat->ac);
games/hack/hack.mon.c
830
tmp += 2 * mdat->mlevel;
games/hack/hack.mon.c
832
tmp += (7 * mdat->mlevel);
games/hack/hack.mon.c
834
tmp += 50;
games/hack/hack.mon.c
836
tmp += 1000;
games/hack/hack.mon.c
851
if (u.uexp + 1 + (tmp + ((tmp2 <= 0) ? 0 : 4 << (tmp2 - 1))) / nk
games/hack/hack.mon.c
857
tmp = (tmp + ((tmp2 < 0) ? 0 : 4 << tmp2)) / nk;
games/hack/hack.mon.c
858
if (!tmp)
games/hack/hack.mon.c
859
tmp = 1;
games/hack/hack.mon.c
865
more_experienced(tmp, 0);
games/hack/hack.mon.c
869
tmp = rnd(10);
games/hack/hack.mon.c
870
if (tmp < 3)
games/hack/hack.mon.c
871
tmp = rnd(10);
games/hack/hack.mon.c
872
u.uhpmax += tmp;
games/hack/hack.mon.c
873
u.uhp += tmp;
games/hack/hack.mon.c
881
tmp = mdat->mlet;
games/hack/hack.mon.c
882
if (tmp == 'm') { /* he killed a minotaur, give him a wand of
games/hack/hack.mon.c
890
if (tmp == 'w') {
games/hack/hack.mon.c
895
if (!letter(tmp) || (!strchr("mw", tmp) && !rn2(3)))
games/hack/hack.mon.c
896
tmp = 0;
games/hack/hack.mon.c
902
struct obj *obj2 = mkobj_at(tmp, x, y);
games/hack/hack.o_init.c
128
tmp = objects[j].oc_descr;
games/hack/hack.o_init.c
130
objects[i].oc_descr = tmp;
games/hack/hack.o_init.c
89
const char *tmp;
games/hack/hack.pri.c
431
char tmp;
games/hack/hack.pri.c
435
tmp = ' ';
games/hack/hack.pri.c
437
tmp = POOL_SYM;
games/hack/hack.pri.c
439
tmp = otmp->olet;
games/hack/hack.pri.c
441
tmp = '$';
games/hack/hack.pri.c
443
tmp = '<';
games/hack/hack.pri.c
445
tmp = '>';
games/hack/hack.pri.c
447
tmp = '^';
games/hack/hack.pri.c
452
tmp = room->scrsym; /* %% wrong after killing
games/hack/hack.pri.c
456
tmp = '-';
games/hack/hack.pri.c
459
tmp = '|';
games/hack/hack.pri.c
463
tmp = '+';
games/hack/hack.pri.c
466
tmp = CORR_SYM;
games/hack/hack.pri.c
470
tmp = '.';
games/hack/hack.pri.c
472
tmp = ' ';
games/hack/hack.pri.c
480
tmp = ERRCHAR;
games/hack/hack.pri.c
482
return (tmp);
games/hack/hack.save.c
113
tmp = getuid();
games/hack/hack.save.c
114
bwrite(fd, &tmp, sizeof tmp);
games/hack/hack.save.c
126
for (tmp = 1; tmp <= maxdlevel; tmp++) {
games/hack/hack.save.c
128
if (tmp == dlevel || !level_exists[tmp])
games/hack/hack.save.c
130
glo(tmp);
games/hack/hack.save.c
140
getlev(ofd, hackpid, tmp);
games/hack/hack.save.c
142
bwrite(fd, &tmp, sizeof tmp); /* level number */
games/hack/hack.save.c
143
savelev(fd, tmp); /* actual level */
games/hack/hack.save.c
158
int tmp; /* not a ! */
games/hack/hack.save.c
170
mread(fd, &tmp, sizeof tmp);
games/hack/hack.save.c
171
if (tmp != (int) getuid()) { /* strange ... */
games/hack/hack.save.c
190
if (read(fd, &tmp, sizeof tmp) != sizeof tmp)
games/hack/hack.save.c
192
getlev(fd, 0, tmp);
games/hack/hack.save.c
193
glo(tmp);
games/hack/hack.save.c
196
savelev(nfd, tmp);
games/hack/hack.save.c
97
int tmp; /* not ! */
games/hack/hack.shk.c
421
pay(long tmp, struct monst *shkp)
games/hack/hack.shk.c
425
u.ugold -= tmp;
games/hack/hack.shk.c
426
shkp->mgold += tmp;
games/hack/hack.shk.c
429
robbed -= tmp;
games/hack/hack.shk.c
442
int pass, tmp;
games/hack/hack.shk.c
536
tmp = 0;
games/hack/hack.shk.c
537
while (tmp < ESHK(shopkeeper)->billct) {
games/hack/hack.shk.c
538
bp = &bill[tmp];
games/hack/hack.shk.c
540
tmp++;
games/hack/hack.shk.c
545
bill[tmp] = bill[--ESHK(shopkeeper)->billct];
games/hack/hack.shk.c
679
int tmp;
games/hack/hack.shk.c
697
tmp = bp->price;
games/hack/hack.shk.c
702
bp->price = tmp;
games/hack/hack.shk.c
711
int tmp;
games/hack/hack.shk.c
745
((tmp = shtypes[rooms[ESHK(shopkeeper)->shoproom].rtype - 8]) && tmp != obj->olet)
games/hack/hack.shk.c
840
int tmp, ac;
games/hack/hack.shk.c
844
tmp = 10 * rnd(500);
games/hack/hack.shk.c
847
tmp = 10 * rnd((obj->otyp == EXPENSIVE_CAMERA) ? 150 : 30);
games/hack/hack.shk.c
850
tmp = 10 * rnd(100);
games/hack/hack.shk.c
853
tmp = 10 * rnd(100);
games/hack/hack.shk.c
856
tmp = 10 * rnd(50);
games/hack/hack.shk.c
859
tmp = rnd(5);
games/hack/hack.shk.c
863
tmp = 10 * rnd(50);
games/hack/hack.shk.c
866
tmp = 10 * rnd(5 + (2000 / realhunger()));
games/hack/hack.shk.c
869
tmp = 10 * rnd(20);
games/hack/hack.shk.c
875
tmp = 100 + ac * ac * rnd(10 + ac);
games/hack/hack.shk.c
879
tmp = 5 * rnd(10);
games/hack/hack.shk.c
882
tmp = 10 * rnd(150);
games/hack/hack.shk.c
884
tmp = 10 * rnd(75);
games/hack/hack.shk.c
890
tmp = 10;
games/hack/hack.shk.c
893
tmp = 10000;
games/hack/hack.shk.c
895
return (tmp);
games/hack/hack.shk.c
901
int tmp = u.uhunger;
games/hack/hack.shk.c
905
tmp += objects[otmp->otyp].nutrition;
games/hack/hack.shk.c
908
return ((tmp <= 0) ? 1 : tmp);
games/hack/hack.steal.c
141
int tmp;
games/hack/hack.steal.c
152
tmp = 0;
games/hack/hack.steal.c
155
tmp += ((otmp->owornmask & (W_ARMOR | W_RING)) ? 5 : 1);
games/hack/hack.steal.c
156
tmp = rn2(tmp);
games/hack/hack.steal.c
159
if ((tmp -= ((otmp->owornmask & (W_ARMOR | W_RING)) ? 5 : 1))
games/hack/hack.steal.c
269
long tmp;
games/hack/hack.steal.c
271
tmp = (mtmp->mgold > 10000) ? 10000 : mtmp->mgold;
games/hack/hack.steal.c
272
mkgold((long) (tmp + d(dlevel, 30)), mtmp->mx, mtmp->my);
games/hack/hack.steal.c
84
long tmp;
games/hack/hack.steal.c
97
u.ugold -= (tmp = somegold());
games/hack/hack.steal.c
99
mtmp->mgold += tmp;
games/hack/hack.unix.c
442
int tmp = rooms[uroom].fdoor;
games/hack/hack.unix.c
446
if (dist(fx, fy) < dist(doors[tmp].x, doors[tmp].y)) {
games/hack/hack.unix.c
447
fx = doors[tmp].x;
games/hack/hack.unix.c
448
fy = doors[tmp].y;
games/hack/hack.unix.c
450
tmp++;
games/hack/hack.unix.c
455
tmp = fx;
games/hack/hack.unix.c
457
md->mx = tmp;
games/hack/hack.unix.c
458
tmp = fy;
games/hack/hack.unix.c
460
md->my = tmp;
games/hack/hack.vault.c
171
int tmp = inroom(u.ux, u.uy);
games/hack/hack.vault.c
173
if (tmp < 0 || rooms[tmp].rtype != VAULT) {
games/hack/hack.worm.c
108
int tmp = mtmp->wormno;
games/hack/hack.worm.c
114
(whd = wheads[tmp])->nseg = wtmp;
games/hack/hack.worm.c
115
wheads[tmp] = wtmp;
games/hack/hack.worm.c
122
if (wgrowtime[tmp] <= moves) {
games/hack/hack.worm.c
123
if (!wgrowtime[tmp])
games/hack/hack.worm.c
124
wgrowtime[tmp] = moves + rnd(5);
games/hack/hack.worm.c
126
wgrowtime[tmp] += 2 + rnd(15);
games/hack/hack.worm.c
131
whd = wsegs[tmp];
games/hack/hack.worm.c
132
wsegs[tmp] = whd->nseg;
games/hack/hack.worm.c
139
int tmp;
games/hack/hack.worm.c
141
tmp = mtmp->wormno;
games/hack/hack.worm.c
142
wtmp = wsegs[tmp];
games/hack/hack.worm.c
143
if (wtmp == wheads[tmp])
games/hack/hack.worm.c
147
wsegs[tmp] = wtmp->nseg;
games/hack/hack.worm.c
155
int tmp = mtmp->wormno;
games/hack/hack.worm.c
157
if (!tmp)
games/hack/hack.worm.c
160
for (wtmp = wsegs[tmp]; wtmp; wtmp = wtmp2) {
games/hack/hack.worm.c
164
wsegs[tmp] = 0;
games/hack/hack.worm.c
170
int tmp = mtmp->wormno;
games/hack/hack.worm.c
172
if (!tmp)
games/hack/hack.worm.c
174
for (wtmp = wsegs[tmp]; wtmp; wtmp = wtmp->nseg)
games/hack/hack.worm.c
179
wormsee(unsigned tmp)
games/hack/hack.worm.c
181
struct wseg *wtmp = wsegs[tmp];
games/hack/hack.worm.c
206
int tmp, tmp2;
games/hack/hack.worm.c
211
tmp = rnd(20);
games/hack/hack.worm.c
214
tmp += 5;
games/hack/hack.worm.c
215
if (tmp < 12)
games/hack/hack.worm.c
219
tmp = mtmp->wormno;
games/hack/hack.worm.c
220
wtmp = wsegs[tmp];
games/hack/hack.worm.c
222
wsegs[tmp] = wtmp->nseg;
games/hack/hack.worm.c
237
wsegs[tmp2] = wsegs[tmp];
games/hack/hack.worm.c
244
wsegs[tmp] = wtmp->nseg->nseg;
games/hack/hack.worm.c
79
int tmp;
games/hack/hack.worm.c
80
for (tmp = 1; tmp < 32; tmp++)
games/hack/hack.worm.c
81
if (!wsegs[tmp]) {
games/hack/hack.worm.c
82
mtmp->wormno = tmp;
games/hack/hack.worm.c
93
int tmp = mtmp->wormno;
games/hack/hack.worm.c
94
if (!tmp)
games/hack/hack.worm.c
96
wheads[tmp] = wsegs[tmp] = wtmp = newseg();
games/hack/hack.worm.c
97
wgrowtime[tmp] = 0;
games/hack/hack.zap.c
501
int tmp;
games/hack/hack.zap.c
505
tmp = zhit(u.ustuck, type);
games/hack/hack.zap.c
507
fltxt, monnam(u.ustuck), exclam(tmp));
games/hack/hack.zap.c
559
int tmp = zhit(mon, abstype);
games/hack/hack.zap.c
569
hit(fltxt, mon, exclam(tmp));
games/hack/hack.zap.c
647
int tmp = 0;
games/hack/hack.zap.c
651
tmp = d(2, 6);
games/hack/hack.zap.c
657
tmp = d(6, 6);
games/hack/hack.zap.c
659
tmp += 7;
games/hack/hack.zap.c
667
tmp = d(6, 6);
games/hack/hack.zap.c
669
tmp += 7;
games/hack/hack.zap.c
674
tmp = mon->mhp + 1;
games/hack/hack.zap.c
677
mon->mhp -= tmp;
games/hack/hack.zap.c
678
return (tmp);
games/hack/hack.zap.c
92
int tmp = d(2, 12);
games/hack/hack.zap.c
93
hit("wand", mtmp, exclam(tmp));
games/hack/hack.zap.c
94
mtmp->mhp -= tmp;
games/hack/rnd.c
91
int tmp = n;
games/hack/rnd.c
94
tmp += RND(x);
games/hack/rnd.c
95
return (tmp);
games/larn/create.c
108
int i, j, tmp;
games/larn/create.c
114
tmp = 0;
games/larn/create.c
116
tmp = OWALL;
games/larn/create.c
119
item[j][i] = tmp;
games/larn/create.c
129
for (tmp = 0; tmp < tmp2; tmp++) {
games/larn/diag.c
344
long tmp;
games/larn/diag.c
345
tmp = c[EXPERIENCE] - skill[24]; /* amount to go up */
games/larn/diag.c
347
raiseexperience((long)tmp);
games/larn/global.c
197
int tmp, x;
games/larn/global.c
202
tmp = WATERLORD;
games/larn/global.c
204
while (tmp == WATERLORD)
games/larn/global.c
205
tmp = rnd((x = monstlevel[lev - 1]) ? x : 1);
games/larn/global.c
207
while (tmp == WATERLORD)
games/larn/global.c
208
tmp = rnd((x = monstlevel[lev - 1] - monstlevel[lev - 4])
games/larn/global.c
211
while (tmp < MAXMONST && monster[tmp].genocided) /* genocided? */
games/larn/global.c
212
tmp++;
games/larn/global.c
213
return (tmp);
games/larn/global.c
526
int tmp;
games/larn/global.c
534
tmp = iven[c[SHIELD]];
games/larn/global.c
535
if (tmp != OSCROLL)
games/larn/global.c
536
if (tmp != OPOTION) {
games/larn/global.c
542
tmp = iven[c[WEAR]];
games/larn/global.c
543
if (tmp != OSCROLL)
games/larn/global.c
544
if (tmp != OPOTION) {
games/larn/global.c
556
int tmp;
games/larn/global.c
563
tmp = iven[c[WIELD]];
games/larn/global.c
564
if (tmp != OSCROLL)
games/larn/global.c
565
if (tmp != OPOTION) {
games/larn/global.c
567
if (tmp == OCLEVERRING)
games/larn/global.c
569
else if (tmp == OSTRRING)
games/larn/global.c
571
else if (tmp == ODEXRING)
games/larn/global.c
599
int tmp, tmp2;
games/larn/global.c
600
for (tmp = playerx - 1; tmp < playerx + 2; tmp++)
games/larn/global.c
602
if (mitem[tmp][tmp2]) /* if monster nearby */
games/larn/global.c
63
int i, tmp;
games/larn/global.c
67
tmp = (c[CONSTITUTION] - c[HARDGAME]) >> 1;
games/larn/global.c
69
raisemhp((int)(rnd(3) + rnd((tmp > 0) ? tmp : 1)));
games/larn/global.c
90
int i, tmp;
games/larn/global.c
98
tmp = (c[CONSTITUTION] - c[HARDGAME]) >> 1; /* lose hpoints */
games/larn/global.c
99
losemhp((int)rnd((tmp > 0) ? tmp : 1)); /* lose hpoints */
games/larn/monster.c
1101
int tmp, monst, damag = 0, flag;
games/larn/monster.c
1109
tmp = monster[monst].armorclass + c[LEVEL] + c[DEXTERITY] +
games/larn/monster.c
1113
if ((rnd(20) < tmp - c[HARDGAME]) || (rnd(71) < 5)) {
games/larn/monster.c
1207
int dam, tmp, mster, bias;
games/larn/monster.c
1243
tmp = 0;
games/larn/monster.c
1250
tmp = 1;
games/larn/monster.c
1256
tmp = 1;
games/larn/monster.c
1265
if (tmp == 0)
games/larn/monster.c
1358
int tmp = 32, j;
games/larn/monster.c
1362
tmp = 37;
games/larn/monster.c
1364
tmp = 35;
games/larn/monster.c
1365
j = nobjtab[tmp = rnd(tmp)]; /* the object type */
games/larn/monster.c
1366
switch (tmp) {
games/larn/monster.c
673
int tmp;
games/larn/monster.c
676
if ((tmp = spelweird[monst - 1][x]) == 0)
games/larn/monster.c
680
lprintf(spelmes[tmp], monster[monst].name);
games/larn/movem.c
131
int k, m, z, tmp, xtmp, ytmp, monst;
games/larn/movem.c
152
if ((tmp = item[xl][yl]) != OWALL)
games/larn/movem.c
155
if (tmp != OCLOSEDDOOR)
games/larn/movem.c
198
for (tmp = 1; tmp < distance; tmp++) /* only up to 20 squares away */
games/larn/movem.c
202
if (screen[m][k] == tmp)
games/larn/movem.c
206
screen[xtmp][ytmp] = tmp + 1;
games/larn/movem.c
211
out: if (tmp < distance) /* did find connectivity */
games/larn/movem.c
214
if (screen[xl = i + diroffx[z]][yl = j + diroffy[z]] == tmp)
games/larn/movem.c
240
tmp = k - i + 4 + 3 * (m - j);
games/larn/movem.c
246
w1[tmp] = (playerx - k) * (playerx - k) + (playery - m) * (playery - m);
games/larn/movem.c
247
w1x[tmp] = k;
games/larn/movem.c
248
w1y[tmp] = m;
games/larn/movem.c
252
tmp = 0;
games/larn/movem.c
254
if (w1[tmp] > w1[k])
games/larn/movem.c
255
tmp = k;
games/larn/movem.c
257
if (w1[tmp] < 10000)
games/larn/movem.c
258
if ((i != w1x[tmp]) || (j != w1y[tmp]))
games/larn/movem.c
259
mmove(i, j, w1x[tmp], w1y[tmp]);
games/larn/movem.c
272
int tmp, i, flag;
games/larn/movem.c
302
tmp = mitem[cc][dd] = mitem[aa][bb];
games/larn/movem.c
304
if (tmp >= DEMONLORD + 3) { /* demons dispel spheres */
games/larn/movem.c
306
lprintf("\nThe %s dispels the sphere!", monster[tmp].name);
games/larn/movem.c
309
i = tmp = mitem[cc][dd] = 0;
games/larn/movem.c
316
if (tmp == LEPRECHAUN)
games/larn/movem.c
329
if (tmp == TROLL) /* if a troll regenerate him */
games/larn/movem.c
331
if (monster[tmp].hitpoints > hitp[cc][dd])
games/larn/movem.c
374
lprintf(p, who, monster[tmp].name);
games/larn/object.c
1172
int i, tmp;
games/larn/object.c
1174
i = rund((tmp = splev[lev]) ? tmp : 1);
games/larn/object.c
1176
i = rnd((tmp = splev[lev] - 9) ? tmp : 1) + 9;
games/larn/object.c
510
int tmp, i;
games/larn/object.c
512
tmp = iarg[playerx][playery];
games/larn/object.c
525
if (tmp > 0)
games/larn/object.c
526
lprintf("+ %d", (long)tmp);
games/larn/object.c
527
else if (tmp < 0)
games/larn/object.c
528
lprintf(" %d", (long)tmp);
games/larn/object.c
537
if (take(obj, tmp) == 0)
games/larn/object.c
614
int tmp;
games/larn/object.c
620
tmp = 0;
games/larn/object.c
622
tmp = rnd(5) + level - 3;
games/larn/object.c
623
if (tmp >= MAXLEVEL)
games/larn/object.c
624
tmp = MAXLEVEL - 1;
games/larn/object.c
625
if (tmp < 1)
games/larn/object.c
626
tmp = 1;
games/larn/object.c
628
tmp = rnd(3) + level - 2;
games/larn/object.c
629
if (tmp >= MAXLEVEL + MAXVLEVEL)
games/larn/object.c
630
tmp = MAXLEVEL + MAXVLEVEL - 1;
games/larn/object.c
631
if (tmp < MAXLEVEL)
games/larn/object.c
632
tmp = MAXLEVEL;
games/larn/object.c
636
if (level != tmp)
games/larn/object.c
637
newcavelevel(tmp);
games/monop/execute.c
578
int tmp;
games/monop/execute.c
605
if (getnum(attribute, txt, 0, N_SQRS, &tmp) < 0) {
games/monop/execute.c
608
pp->loc = tmp;
games/monop/execute.c
610
if (getnum(attribute, txt, 0, 2, &tmp) < 0) {
games/monop/execute.c
613
pp->num_gojf = tmp;
games/monop/execute.c
615
if (getnum(attribute, txt, 0, 3, &tmp) < 0) {
games/monop/execute.c
618
pp->in_jail = tmp;
games/monop/execute.c
633
int tmp, j;
games/monop/execute.c
641
&tmp) < 0) {
games/monop/execute.c
650
if (getnum(attribute, txt, 0, 1, &tmp) < 0) {
games/monop/execute.c
653
dp->gojf_used = tmp;
games/monop/execute.c
658
tmp = strtol(s, &s, 10);
games/monop/execute.c
659
if (tmp < 0 || tmp >= dp->num_cards) {
games/monop/execute.c
663
dp->cards[j] = tmp;
games/monop/execute.c
680
int tmp;
games/monop/execute.c
683
if (getnum(attribute, txt, -1, num_play-1, &tmp) < 0) {
games/monop/execute.c
686
sp->owner = tmp;
games/monop/execute.c
687
if (tmp >= 0)
games/monop/execute.c
688
add_list(tmp, &play[tmp].own_list, restore_itemnum);
games/monop/execute.c
694
if (getnum(attribute, txt, 0, 1, &tmp) < 0) {
games/monop/execute.c
697
sp->desc->morg = tmp;
games/monop/execute.c
703
if (getnum(attribute, txt, 0, 5, &tmp) < 0) {
games/monop/execute.c
706
sp->desc->houses = tmp;
games/sail/sync.c
250
struct stat tmp;
games/sail/sync.c
257
if (stat(sync_file, &tmp) < 0) {
games/snake/snake/snake.c
819
struct point tmp;
games/snake/snake/snake.c
833
tmp.col = snake[5].col;
games/snake/snake/snake.c
834
tmp.line = snake[5].line;
games/snake/snake/snake.c
841
if (same(&snake[i], &you) || same(&tmp, &you)) {
games/tetris/tetris.c
136
const struct shape *tmp;
games/tetris/tetris.c
139
tmp = &shapes[arc4random_uniform(7)];
games/tetris/tetris.c
142
tmp = &shapes[classic? tmp->rotc : tmp->rot];
games/tetris/tetris.c
143
return (tmp);
lib/i18n_module/ISO2022/citrus_iso2022.c
1015
char tmp[MB_LEN_MAX];
lib/i18n_module/ISO2022/citrus_iso2022.c
1046
p = tmp;
lib/i18n_module/ISO2022/citrus_iso2022.c
1155
len = (size_t)(p - tmp);
lib/i18n_module/ISO2022/citrus_iso2022.c
1164
memcpy(string, tmp, len);
lib/i18n_module/mapper_serial/citrus_mapper_serial.c
226
_index_t tmp;
lib/i18n_module/mapper_serial/citrus_mapper_serial.c
231
ret = _mapper_convert(ml->ml_mapper, &tmp, src, NULL);
lib/i18n_module/mapper_serial/citrus_mapper_serial.c
233
*dst = tmp;
lib/libc/citrus/citrus_db_factory.c
141
char *tmp;
lib/libc/citrus/citrus_db_factory.c
143
tmp = strdup(key);
lib/libc/citrus/citrus_db_factory.c
144
if (tmp == NULL)
lib/libc/citrus/citrus_db_factory.c
146
_region_init(&r, tmp, strlen(key));
lib/libc/citrus/citrus_db_hash.c
47
uint32_t hash, tmp;
lib/libc/citrus/citrus_db_hash.c
56
tmp = hash & 0xF0000000;
lib/libc/citrus/citrus_db_hash.c
57
if (tmp != 0) {
lib/libc/citrus/citrus_db_hash.c
58
hash ^= tmp;
lib/libc/citrus/citrus_db_hash.c
59
hash ^= tmp >> 24;
lib/libc/citrus/citrus_esdb.c
133
ret = _db_lookup32_by_s(db, _CITRUS_ESDB_SYM_INVALID, &tmp, NULL);
lib/libc/citrus/citrus_esdb.c
136
esdb->db_invalid = tmp;
lib/libc/citrus/citrus_esdb.c
80
uint32_t csid, i, num_charsets, tmp, version;
lib/libc/citrus/citrus_module.c
181
int dewey[MAXDEWEY], tmp[MAXDEWEY];
lib/libc/citrus/citrus_module.c
212
if ((n = _getdewey(tmp, dp->d_name+len+4)) == 0)
lib/libc/citrus/citrus_module.c
223
if (tmp[0] == major)
lib/libc/citrus/citrus_module.c
226
if (tmp[0] == major) {
lib/libc/citrus/citrus_module.c
227
if (n == 1 || tmp[1] >= minor)
lib/libc/citrus/citrus_module.c
236
if (_cmpndewey(tmp, n, dewey, ndewey) <= 0)
lib/libc/citrus/citrus_module.c
244
bcopy(tmp, dewey, sizeof(dewey));
lib/libc/db/btree/bt_open.c
204
if ((t->bt_fd = tmp()) == -1)
lib/libc/db/btree/bt_open.c
69
static int tmp(void);
lib/libc/db/btree/bt_put.c
123
tmp = key->size;
lib/libc/db/btree/bt_put.c
125
&tmp, sizeof(uint32_t));
lib/libc/db/btree/bt_put.c
135
tmp = data->size;
lib/libc/db/btree/bt_put.c
137
&tmp, sizeof(uint32_t));
lib/libc/db/btree/bt_put.c
70
uint32_t nbytes, tmp;
lib/libc/gen/fts.c
109
FTSENT *parent, *tmp;
lib/libc/gen/fts.c
126
tmp = NULL;
lib/libc/gen/fts.c
172
tmp = root = p;
lib/libc/gen/fts.c
174
tmp->fts_link = p;
lib/libc/gen/fts.c
175
tmp = p;
lib/libc/gen/fts.c
293
FTSENT *p, *tmp;
lib/libc/gen/fts.c
389
next: tmp = p;
lib/libc/gen/fts.c
391
free(tmp);
lib/libc/gen/fts.c
433
p = tmp->fts_parent;
lib/libc/gen/fts.c
434
free(tmp);
lib/libc/gen/getcap.c
1044
char *cp, tmp;
lib/libc/gen/getcap.c
1050
tmp = *(cp + 1);
lib/libc/gen/getcap.c
1053
*(cp + 1) = tmp;
lib/libc/inet/inet_cidr_ntop.c
153
char tmp[sizeof "ffff:ffff:ffff:ffff:ffff:ffff:255.255.255.255/128"];
lib/libc/inet/inet_cidr_ntop.c
200
tp = tmp;
lib/libc/inet/inet_cidr_ntop.c
224
n = decoct(src+12, n, tp, sizeof tmp - (tp - tmp));
lib/libc/inet/inet_cidr_ntop.c
247
if ((size_t)(tp - tmp) > size) {
lib/libc/inet/inet_cidr_ntop.c
251
strcpy(dst, tmp);
lib/libc/inet/inet_cidr_pton.c
147
u_char tmp[NS_IN6ADDRSZ], *tp, *endp, *colonp;
lib/libc/inet/inet_cidr_pton.c
153
memset((tp = tmp), '\0', NS_IN6ADDRSZ);
lib/libc/inet/inet_cidr_pton.c
232
memcpy(dst, tmp, NS_IN6ADDRSZ);
lib/libc/inet/inet_cidr_pton.c
79
int n, ch, tmp, bits;
lib/libc/inet/inet_cidr_pton.c
84
tmp = 0;
lib/libc/inet/inet_cidr_pton.c
88
tmp *= 10;
lib/libc/inet/inet_cidr_pton.c
89
tmp += n;
lib/libc/inet/inet_cidr_pton.c
90
if (tmp > 255)
lib/libc/inet/inet_cidr_pton.c
95
*dst++ = (u_char) tmp;
lib/libc/inet/inet_net_pton.c
105
*dst++ = (u_char) tmp;
lib/libc/inet/inet_net_pton.c
258
u_char tmp[NS_IN6ADDRSZ], *tp, *endp, *colonp;
lib/libc/inet/inet_net_pton.c
268
memset((tp = tmp), '\0', NS_IN6ADDRSZ);
lib/libc/inet/inet_net_pton.c
337
endp = tmp + 2 * words;
lib/libc/inet/inet_net_pton.c
361
memcpy(dst, tmp, bytes);
lib/libc/inet/inet_net_pton.c
57
int n, ch, tmp = 0, dirty, bits;
lib/libc/inet/inet_net_pton.c
75
tmp = n;
lib/libc/inet/inet_net_pton.c
77
tmp = (tmp << 4) | n;
lib/libc/inet/inet_net_pton.c
81
*dst++ = (u_char) tmp;
lib/libc/inet/inet_net_pton.c
88
*dst++ = (u_char) (tmp << 4);
lib/libc/inet/inet_net_pton.c
93
tmp = 0;
lib/libc/inet/inet_net_pton.c
97
tmp *= 10;
lib/libc/inet/inet_net_pton.c
98
tmp += n;
lib/libc/inet/inet_net_pton.c
99
if (tmp > 255)
lib/libc/inet/inet_ntop.c
111
char tmp[sizeof "ffff:ffff:ffff:ffff:ffff:ffff:255.255.255.255"], *tp;
lib/libc/inet/inet_ntop.c
152
tp = tmp;
lib/libc/inet/inet_ntop.c
168
if (!inet_ntop4(src+12, tp, sizeof tmp - (tp - tmp))) {
lib/libc/inet/inet_ntop.c
186
if ((socklen_t)(tp - tmp) > size) {
lib/libc/inet/inet_ntop.c
190
strcpy(dst, tmp);
lib/libc/inet/inet_ntop.c
83
char tmp[sizeof "255.255.255.255"];
lib/libc/inet/inet_ntop.c
86
l = snprintf(tmp, sizeof(tmp), fmt, src[0], src[1], src[2], src[3]);
lib/libc/inet/inet_ntop.c
91
strlcpy(dst, tmp, size);
lib/libc/inet/inet_pton.c
111
memcpy(dst, tmp, NS_INADDRSZ);
lib/libc/inet/inet_pton.c
133
u_char tmp[NS_IN6ADDRSZ], *tp, *endp, *colonp;
lib/libc/inet/inet_pton.c
138
memset((tp = tmp), '\0', NS_IN6ADDRSZ);
lib/libc/inet/inet_pton.c
210
memcpy(dst, tmp, NS_IN6ADDRSZ);
lib/libc/inet/inet_pton.c
80
u_char tmp[NS_INADDRSZ], *tp;
lib/libc/inet/inet_pton.c
84
*(tp = tmp) = 0;
lib/libc/nameser/ns_name.c
580
u_char tmp[NS_MAXCDNAME];
lib/libc/nameser/ns_name.c
583
if ((n = ns_name_unpack(msg, eom, src, tmp, sizeof tmp)) == -1)
lib/libc/nameser/ns_name.c
585
if (ns_name_ntop(tmp, dst, dstsiz) == -1)
lib/libc/nameser/ns_name.c
609
u_char tmp[NS_MAXCDNAME];
lib/libc/nameser/ns_name.c
611
if (ns_name_pton(src, tmp, sizeof tmp) == -1)
lib/libc/nameser/ns_name.c
613
return (ns_name_pack(tmp, dst, dstsiz, dnptrs, lastdnptr));
lib/libc/nameser/ns_parse.c
138
int tmp;
lib/libc/nameser/ns_parse.c
141
tmp = section;
lib/libc/nameser/ns_parse.c
142
if (tmp < 0 || section >= ns_s_max)
lib/libc/nameser/ns_print.c
113
char tmp[100];
lib/libc/nameser/ns_print.c
146
len = SPRINTF((tmp, " %s %s", p_class(class), p_type(type)));
lib/libc/nameser/ns_print.c
147
T(addstr(tmp, len, &buf, &buflen));
lib/libc/nameser/ns_print.c
209
len = SPRINTF((tmp, "%lu", t));
lib/libc/nameser/ns_print.c
210
T(addstr(tmp, len, &buf, &buflen));
lib/libc/nameser/ns_print.c
265
len = SPRINTF((tmp, "%u ", t));
lib/libc/nameser/ns_print.c
266
T(addstr(tmp, len, &buf, &buflen));
lib/libc/nameser/ns_print.c
283
len = SPRINTF((tmp, "%u ", t));
lib/libc/nameser/ns_print.c
284
T(addstr(tmp, len, &buf, &buflen));
lib/libc/nameser/ns_print.c
421
len = SPRINTF((tmp, " %u ( ", *rdata));
lib/libc/nameser/ns_print.c
422
T(addstr(tmp, len, &buf, &buflen));
lib/libc/nameser/ns_print.c
438
len = SPRINTF((tmp, "%d ", n));
lib/libc/nameser/ns_print.c
439
T(addstr(tmp, len, &buf, &buflen));
lib/libc/nameser/ns_print.c
468
len = SPRINTF((tmp, "0x%04x %u %u",
lib/libc/nameser/ns_print.c
470
T(addstr(tmp, len, &buf, &buflen));
lib/libc/nameser/ns_print.c
490
n = SPRINTF((tmp, " ; key_tag= %u", key_id));
lib/libc/nameser/ns_print.c
491
T(addstr(tmp, n, &buf, &buflen));
lib/libc/nameser/ns_print.c
511
len = SPRINTF((tmp, "%s %d %d %lu ",
lib/libc/nameser/ns_print.c
513
T(addstr(tmp, len, &buf, &buflen));
lib/libc/nameser/ns_print.c
519
len = SPRINTF((tmp, "%s ", p_secstodate(t)));
lib/libc/nameser/ns_print.c
520
T(addstr(tmp, len, &buf, &buflen));
lib/libc/nameser/ns_print.c
524
len = SPRINTF((tmp, "%s ", p_secstodate(t)));
lib/libc/nameser/ns_print.c
525
T(addstr(tmp, len, &buf, &buflen));
lib/libc/nameser/ns_print.c
529
len = SPRINTF((tmp, "%u ", footprint));
lib/libc/nameser/ns_print.c
530
T(addstr(tmp, len, &buf, &buflen));
lib/libc/nameser/ns_print.c
566
len = SPRINTF((tmp, " %s", p_type(c)));
lib/libc/nameser/ns_print.c
567
T(addstr(tmp, len, &buf, &buflen));
lib/libc/nameser/ns_print.c
576
char base64_cert[8192], tmp[40];
lib/libc/nameser/ns_print.c
583
len = SPRINTF((tmp, "%d %d %d ", c_type, key_tag, alg));
lib/libc/nameser/ns_print.c
584
T(addstr(tmp, len, &buf, &buflen));
lib/libc/nameser/ns_print.c
626
len = SPRINTF((tmp, "%s ", p_secstodate(t)));
lib/libc/nameser/ns_print.c
627
T(addstr(tmp, len, &buf, &buflen));
lib/libc/nameser/ns_print.c
631
len = SPRINTF((tmp, "%s ", p_secstodate(t)));
lib/libc/nameser/ns_print.c
632
T(addstr(tmp, len, &buf, &buflen));
lib/libc/nameser/ns_print.c
639
len = SPRINTF((tmp, "%u %u %u ", mode, err, keysize));
lib/libc/nameser/ns_print.c
640
T(addstr(tmp, len, &buf, &buflen));
lib/libc/nameser/ns_print.c
668
len = SPRINTF((tmp, "%d ", *rdata));
lib/libc/nameser/ns_print.c
669
T(addstr(tmp, len, &buf, &buflen));
lib/libc/nameser/ns_print.c
696
len = SPRINTF((tmp, "%u bytes", class));
lib/libc/nameser/ns_print.c
697
T(addstr(tmp, len, &buf, &buflen));
lib/libc/nameser/ns_print.c
712
len = SPRINTF((tmp, "\\# %u%s\t; %s", (unsigned)(edata - rdata),
lib/libc/nameser/ns_print.c
714
T(addstr(tmp, len, &buf, &buflen));
lib/libc/nameser/ns_print.c
716
p = tmp;
lib/libc/nameser/ns_print.c
722
T(addstr(tmp, p - tmp, &buf, &buflen));
lib/libc/nameser/ns_print.c
725
T(addtab(p - tmp + 1, 48, spaced, &buf, &buflen));
lib/libc/nameser/ns_print.c
727
p = tmp;
lib/libc/nameser/ns_print.c
733
T(addstr(tmp, p - tmp, &buf, &buflen));
lib/libc/nameser/ns_ttl.c
100
tmp = 0;
lib/libc/nameser/ns_ttl.c
107
tmp *= 10;
lib/libc/nameser/ns_ttl.c
108
tmp += (ch - '0');
lib/libc/nameser/ns_ttl.c
117
case 'W': tmp *= 7;
lib/libc/nameser/ns_ttl.c
118
case 'D': tmp *= 24;
lib/libc/nameser/ns_ttl.c
119
case 'H': tmp *= 60;
lib/libc/nameser/ns_ttl.c
120
case 'M': tmp *= 60;
lib/libc/nameser/ns_ttl.c
124
ttl += tmp;
lib/libc/nameser/ns_ttl.c
125
tmp = 0;
lib/libc/nameser/ns_ttl.c
133
ttl += tmp;
lib/libc/nameser/ns_ttl.c
148
char tmp[50];
lib/libc/nameser/ns_ttl.c
151
len = SPRINTF((tmp, "%d%c", t, s));
lib/libc/nameser/ns_ttl.c
154
strcpy(*buf, tmp);
lib/libc/nameser/ns_ttl.c
96
u_long ttl, tmp;
lib/libc/net/map_v4v6.c
79
char tmp[NS_INADDRSZ];
lib/libc/net/map_v4v6.c
83
memcpy(tmp, src, NS_INADDRSZ);
lib/libc/net/map_v4v6.c
90
memcpy((void*)p, tmp, NS_INADDRSZ);
lib/libc/resolv/res_findzonecut.c
646
char *tmp;
lib/libc/resolv/res_findzonecut.c
652
DE_CONST(nsrr->name, tmp);
lib/libc/resolv/res_findzonecut.c
653
free(tmp);
lib/libc/resolv/res_query.c
216
char tmp[NS_MAXDNAME];
lib/libc/resolv/res_query.c
233
if (!dots && (cp = res_hostalias(statp, name, tmp, sizeof tmp))!= NULL)
lib/libc/resolv/res_send.c
634
void *tmp;
lib/libc/resolv/res_send.c
722
DE_CONST(buf, tmp);
lib/libc/resolv/res_send.c
723
iov[1] = evConsIovec(tmp, buflen);
lib/libc/rpc/getnetconfig.c
645
char *tmp;
lib/libc/rpc/getnetconfig.c
648
if ((tmp=malloc(MAXNETCONFIGLINE)) == NULL)
lib/libc/rpc/getnetconfig.c
651
free(tmp);
lib/libc/rpc/getnetconfig.c
664
p->nc_netid = (char *)strcpy(tmp,ncp->nc_netid);
lib/libc/rpc/getnetconfig.c
665
tmp = strchr(tmp, '\0') + 1;
lib/libc/rpc/getnetconfig.c
666
p->nc_protofmly = (char *)strcpy(tmp,ncp->nc_protofmly);
lib/libc/rpc/getnetconfig.c
667
tmp = strchr(tmp, '\0') + 1;
lib/libc/rpc/getnetconfig.c
668
p->nc_proto = (char *)strcpy(tmp,ncp->nc_proto);
lib/libc/rpc/getnetconfig.c
669
tmp = strchr(tmp, '\0') + 1;
lib/libc/rpc/getnetconfig.c
670
p->nc_device = (char *)strcpy(tmp,ncp->nc_device);
lib/libc/rpc/getnetconfig.c
678
tmp = strchr(tmp, '\0') + 1;
lib/libc/rpc/getnetconfig.c
679
p->nc_lookups[i] = (char *)strcpy(tmp,ncp->nc_lookups[i]);
lib/libc/stdio/fdopen.c
50
int flags, oflags, fdflags, tmp;
lib/libc/stdio/fdopen.c
58
tmp = fdflags & O_ACCMODE;
lib/libc/stdio/fdopen.c
59
if (tmp != O_RDWR && (tmp != (oflags & O_ACCMODE))) {
lib/libc/stdio/fdopen.c
68
((tmp = _fcntl(fd, F_GETFD, 0)) & FD_CLOEXEC) == 0)
lib/libc/stdio/fdopen.c
69
_fcntl(fd, F_SETFD, tmp | FD_CLOEXEC); /* silently ignore err */
lib/libc/stdlib/heapsort.c
141
char tmp, *tmp1, *tmp2;
lib/libc/stdlib/heapsort.c
162
CREATE(l, nmemb, i, j, t, p, size, cnt, tmp);
lib/libc/stdlib/heapsort.c
48
#define SWAP(a, b, count, size, tmp) { \
lib/libc/stdlib/heapsort.c
51
tmp = *a; \
lib/libc/stdlib/heapsort.c
53
*b++ = tmp; \
lib/libc/stdlib/heapsort.c
74
#define CREATE(initval, nmemb, par_i, child_i, par, child, size, count, tmp) { \
lib/libc/stdlib/heapsort.c
85
SWAP(par, child, count, size, tmp); \
lib/libc/stdlib/merge.c
234
tmp = *a; *a++ = *s; *s++ = tmp; \
lib/libc/stdlib/merge.c
243
tmp = *bot; *bot++ = *s; *s++ = tmp; \
lib/libc/stdlib/merge.c
259
int i, length, size2, tmp, sense;
lib/libc/stdlib/merge.c
331
u_char *ai, *s, *t, *u, tmp;
lib/libc/stdlib/nmalloc.c
533
struct magazine *tmp;
lib/libc/stdlib/nmalloc.c
534
tmp = mp->loaded;
lib/libc/stdlib/nmalloc.c
536
mp->prev = tmp;
lib/libc/stdtime/getdate.c
125
tmp = localtime(&now);
lib/libc/stdtime/getdate.c
126
tmnow = *tmp;
lib/libc/stdtime/getdate.c
70
struct tm *tmp, *rtmp = &rtm;
lib/libc/stdtime/localtime.c
1279
struct tm * const tmp)
lib/libc/stdtime/localtime.c
1307
result = localsub(&newt, offset, tmp);
lib/libc/stdtime/localtime.c
1308
if (result == tmp) {
lib/libc/stdtime/localtime.c
1311
newy = tmp->tm_year;
lib/libc/stdtime/localtime.c
1315
tmp->tm_year = newy;
lib/libc/stdtime/localtime.c
1316
if (tmp->tm_year != newy)
lib/libc/stdtime/localtime.c
1343
result = timesub(&t, ttisp->tt_gmtoff, sp, tmp);
lib/libc/stdtime/localtime.c
1344
tmp->tm_isdst = ttisp->tt_isdst;
lib/libc/stdtime/localtime.c
1345
tzname[tmp->tm_isdst] = &sp->chars[ttisp->tt_abbrind];
lib/libc/stdtime/localtime.c
1346
tmp->TM_ZONE = &sp->chars[ttisp->tt_abbrind];
lib/libc/stdtime/localtime.c
1392
localtime_r(const time_t * __restrict const timep, struct tm * __restrict tmp)
lib/libc/stdtime/localtime.c
1396
localsub(timep, 0L, tmp);
lib/libc/stdtime/localtime.c
1398
return tmp;
lib/libc/stdtime/localtime.c
1413
struct tm * const tmp)
lib/libc/stdtime/localtime.c
1418
result = timesub(timep, offset, gmtptr, tmp);
lib/libc/stdtime/localtime.c
1425
tmp->TM_ZONE = wildabbr;
lib/libc/stdtime/localtime.c
1427
tmp->TM_ZONE = gmtptr->chars;
lib/libc/stdtime/localtime.c
1470
gmtime_r(const time_t * __restrict timep, struct tm * __restrict tmp)
lib/libc/stdtime/localtime.c
1472
return gmtsub(timep, 0L, tmp);
lib/libc/stdtime/localtime.c
1495
const struct state * const sp, struct tm * const tmp)
lib/libc/stdtime/localtime.c
1586
tmp->tm_year = y;
lib/libc/stdtime/localtime.c
1587
if (increment_overflow(&tmp->tm_year, -TM_YEAR_BASE))
lib/libc/stdtime/localtime.c
1589
tmp->tm_yday = idays;
lib/libc/stdtime/localtime.c
1593
tmp->tm_wday = EPOCH_WDAY +
lib/libc/stdtime/localtime.c
1599
tmp->tm_wday %= DAYSPERWEEK;
lib/libc/stdtime/localtime.c
1600
if (tmp->tm_wday < 0)
lib/libc/stdtime/localtime.c
1601
tmp->tm_wday += DAYSPERWEEK;
lib/libc/stdtime/localtime.c
1602
tmp->tm_hour = (int) (rem / SECSPERHOUR);
lib/libc/stdtime/localtime.c
1604
tmp->tm_min = (int) (rem / SECSPERMIN);
lib/libc/stdtime/localtime.c
1609
tmp->tm_sec = (int) (rem % SECSPERMIN) + hit;
lib/libc/stdtime/localtime.c
1611
for (tmp->tm_mon = 0; idays >= ip[tmp->tm_mon]; ++(tmp->tm_mon))
lib/libc/stdtime/localtime.c
1612
idays -= ip[tmp->tm_mon];
lib/libc/stdtime/localtime.c
1613
tmp->tm_mday = (int) (idays + 1);
lib/libc/stdtime/localtime.c
1614
tmp->tm_isdst = 0;
lib/libc/stdtime/localtime.c
1615
tmp->TM_GMTOFF = offset;
lib/libc/stdtime/localtime.c
1616
return tmp;
lib/libc/stdtime/localtime.c
162
struct tm * tmp);
lib/libc/stdtime/localtime.c
1632
struct tm *tmp = localtime(timep);
lib/libc/stdtime/localtime.c
1634
return tmp ? asctime(tmp) : NULL;
lib/libc/stdtime/localtime.c
164
struct tm * tmp);
lib/libc/stdtime/localtime.c
1641
struct tm *tmp = localtime_r(timep, &mytm);
lib/libc/stdtime/localtime.c
1643
return tmp ? asctime_r(tmp, buf) : NULL;
lib/libc/stdtime/localtime.c
174
static time_t time1(struct tm * tmp,
lib/libc/stdtime/localtime.c
1748
time2sub(struct tm * const tmp,
lib/libc/stdtime/localtime.c
1765
yourtm = *tmp;
lib/libc/stdtime/localtime.c
178
static time_t time2(struct tm *tmp,
lib/libc/stdtime/localtime.c
182
static time_t time2sub(struct tm *tmp,
lib/libc/stdtime/localtime.c
187
const struct state * sp, struct tm * tmp);
lib/libc/stdtime/localtime.c
1908
if ((*funcp)(&t, offset, tmp))
lib/libc/stdtime/localtime.c
1914
time2(struct tm * const tmp,
lib/libc/stdtime/localtime.c
1925
t = time2sub(tmp, funcp, offset, okayp, FALSE);
lib/libc/stdtime/localtime.c
1926
return *okayp ? t : time2sub(tmp, funcp, offset, okayp, TRUE);
lib/libc/stdtime/localtime.c
1930
time1(struct tm * const tmp,
lib/libc/stdtime/localtime.c
1944
if (tmp == NULL) {
lib/libc/stdtime/localtime.c
1948
if (tmp->tm_isdst > 1)
lib/libc/stdtime/localtime.c
1949
tmp->tm_isdst = 1;
lib/libc/stdtime/localtime.c
1950
t = time2(tmp, funcp, offset, &okay);
lib/libc/stdtime/localtime.c
1957
if (tmp->tm_isdst < 0)
lib/libc/stdtime/localtime.c
1958
tmp->tm_isdst = 0; /* reset to std and try again */
lib/libc/stdtime/localtime.c
1978
if (sp->ttis[samei].tt_isdst != tmp->tm_isdst)
lib/libc/stdtime/localtime.c
1982
if (sp->ttis[otheri].tt_isdst == tmp->tm_isdst)
lib/libc/stdtime/localtime.c
1984
tmp->tm_sec += sp->ttis[otheri].tt_gmtoff -
lib/libc/stdtime/localtime.c
1986
tmp->tm_isdst = !tmp->tm_isdst;
lib/libc/stdtime/localtime.c
1987
t = time2(tmp, funcp, offset, &okay);
lib/libc/stdtime/localtime.c
1990
tmp->tm_sec -= sp->ttis[otheri].tt_gmtoff -
lib/libc/stdtime/localtime.c
1992
tmp->tm_isdst = !tmp->tm_isdst;
lib/libc/stdtime/localtime.c
1999
mktime(struct tm * const tmp)
lib/libc/stdtime/localtime.c
2004
mktime_return_value = time1(tmp, localsub, 0L);
lib/libc/stdtime/localtime.c
2010
timelocal(struct tm * const tmp)
lib/libc/stdtime/localtime.c
2012
if (tmp != NULL)
lib/libc/stdtime/localtime.c
2013
tmp->tm_isdst = -1; /* in case it wasn't initialized */
lib/libc/stdtime/localtime.c
2014
return mktime(tmp);
lib/libc/stdtime/localtime.c
2018
timegm(struct tm * const tmp)
lib/libc/stdtime/localtime.c
2020
if (tmp != NULL)
lib/libc/stdtime/localtime.c
2021
tmp->tm_isdst = 0;
lib/libc/stdtime/localtime.c
2022
return time1(tmp, gmtsub, 0L);
lib/libc/stdtime/localtime.c
2026
timeoff(struct tm * const tmp, const long offset)
lib/libc/stdtime/localtime.c
2028
if (tmp != NULL)
lib/libc/stdtime/localtime.c
2029
tmp->tm_isdst = 0;
lib/libc/stdtime/localtime.c
2030
return time1(tmp, gmtsub, offset);
lib/libc/string/strerror.c
65
char tmp[EBUFSIZE];
lib/libc/string/strerror.c
67
t = tmp + sizeof(tmp);
lib/libc/string/strsignal.c
125
t = tmp;
lib/libc/string/strsignal.c
138
if (t <= tmp)
lib/libc/string/strsignal.c
91
char tmp[20];
lib/libc/sysvipc/ipc.c
123
struct hashentry *tmp;
lib/libc/sysvipc/ipc.c
136
LIST_FOREACH(tmp, list, entry_link) {
lib/libc/sysvipc/ipc.c
137
data = (struct shm_data*)tmp->value;
lib/libc/sysvipc/ipc.c
163
struct hashentry *tmp;
lib/libc/sysvipc/ipc.c
176
LIST_FOREACH(tmp, list, entry_link) {
lib/libc/sysvipc/ipc.c
177
data = (struct shm_data*)tmp->value;
lib/libc/sysvipc/shm.c
401
struct hashentry *tmp, *ttmp;
lib/libc/sysvipc/shm.c
414
LIST_FOREACH_MUTABLE(tmp, list, entry_link, ttmp) {
lib/libc/sysvipc/shm.c
415
data = (struct shm_data*)tmp->value;
lib/libc/sysvipc/sysvipc_hash.c
102
struct hashentry *tmp;
lib/libc/sysvipc/sysvipc_hash.c
104
LIST_FOREACH(tmp, list, entry_link) {
lib/libc/sysvipc/sysvipc_hash.c
105
if (tmp->key == key) {
lib/libc/sysvipc/sysvipc_hash.c
106
return tmp->value;
lib/libc/sysvipc/sysvipc_hash.c
121
struct hashentry *tmp;
lib/libc/sysvipc/sysvipc_hash.c
123
LIST_FOREACH(tmp, list, entry_link) {
lib/libc/sysvipc/sysvipc_hash.c
124
if (tmp->key == key)
lib/libc/sysvipc/sysvipc_hash.c
131
LIST_REMOVE(tmp, entry_link);
lib/libc/sysvipc/sysvipc_hash.c
132
value = tmp->value;
lib/libc/sysvipc/sysvipc_hash.c
133
free(tmp);
lib/libc/sysvipc/sysvipc_hash.c
69
struct entries_list *tmp;
lib/libc/sysvipc/sysvipc_hash.c
72
for (tmp = &hashtable->entries[0]; tmp <= &hashtable->entries[hashmask]; tmp++) {
lib/libc/sysvipc/sysvipc_hash.c
73
if (!LIST_EMPTY(tmp))
lib/libcompat/4.3/rexec.c
138
char *hdir, buf[BUFSIZ], *tmp;
lib/libcompat/4.3/rexec.c
177
if ((tmp = strchr(host, '.')) != NULL &&
lib/libcompat/4.3/rexec.c
178
strcasecmp(tmp, mydomain) == 0 &&
lib/libcompat/4.3/rexec.c
179
strncasecmp(host, tokval, tmp - host) == 0 &&
lib/libcompat/4.3/rexec.c
180
tokval[tmp - host] == '\0')
lib/libcompat/4.3/rexec.c
190
char *tmp;
lib/libcompat/4.3/rexec.c
191
tmp = malloc(strlen(tokval) + 1);
lib/libcompat/4.3/rexec.c
192
strcpy(tmp, tokval);
lib/libcompat/4.3/rexec.c
193
*aname = tmp;
lib/libcompat/4.3/rexec.c
209
char *tmp;
lib/libcompat/4.3/rexec.c
210
tmp = malloc(strlen(tokval) + 1);
lib/libcompat/4.3/rexec.c
211
strcpy(tmp, tokval);
lib/libcompat/4.3/rexec.c
212
*apass = tmp;
lib/libcompat/4.3/rexec.c
239
tmp = macros[macnum].mac_name;
lib/libcompat/4.3/rexec.c
240
*tmp++ = c;
lib/libcompat/4.3/rexec.c
243
*tmp++ = c;
lib/libcompat/4.3/rexec.c
249
*tmp = '\0';
lib/libcompat/4.3/rexec.c
263
tmp = macros[macnum].mac_start;
lib/libcompat/4.3/rexec.c
264
while (tmp != macbuf + 4096) {
lib/libcompat/4.3/rexec.c
269
*tmp = c;
lib/libcompat/4.3/rexec.c
270
if (*tmp == '\n') {
lib/libcompat/4.3/rexec.c
271
if (*(tmp-1) == '\0') {
lib/libcompat/4.3/rexec.c
272
macros[macnum++].mac_end = tmp - 1;
lib/libcompat/4.3/rexec.c
275
*tmp = '\0';
lib/libcompat/4.3/rexec.c
277
tmp++;
lib/libcompat/4.3/rexec.c
279
if (tmp == macbuf + 4096) {
lib/libcrypt/crypt-sha256.c
345
char *tmp = (char *) alloca (key_len + __alignof__ (uint32_t));
lib/libcrypt/crypt-sha256.c
347
memcpy (tmp + __alignof__ (uint32_t)
lib/libcrypt/crypt-sha256.c
348
- (tmp - (char *) 0) % __alignof__ (uint32_t),
lib/libcrypt/crypt-sha256.c
354
char *tmp = (char *) alloca (salt_len + __alignof__ (uint32_t));
lib/libcrypt/crypt-sha256.c
356
memcpy (tmp + __alignof__ (uint32_t)
lib/libcrypt/crypt-sha256.c
357
- (tmp - (char *) 0) % __alignof__ (uint32_t),
lib/libcrypt/crypt-sha512.c
376
char *tmp = (char *) alloca (key_len + __alignof__ (uint64_t));
lib/libcrypt/crypt-sha512.c
378
memcpy (tmp + __alignof__ (uint64_t)
lib/libcrypt/crypt-sha512.c
379
- (tmp - (char *) 0) % __alignof__ (uint64_t),
lib/libcrypt/crypt-sha512.c
385
char *tmp = (char *) alloca (salt_len + __alignof__ (uint64_t));
lib/libcrypt/crypt-sha512.c
387
memcpy (tmp + __alignof__ (uint64_t)
lib/libcrypt/crypt-sha512.c
388
- (tmp - (char *) 0) % __alignof__ (uint64_t),
lib/libevtr/evtr.c
1596
void *tmp;
lib/libevtr/evtr.c
1600
if (!(tmp = realloc(q->buf, len)))
lib/libevtr/evtr.c
1602
q->buf = tmp;
lib/libevtr/evtr.c
360
struct event_filter_unresolved *u, *tmp;
lib/libevtr/evtr.c
362
TAILQ_FOREACH_MUTABLE(u, &q->unresolved_filtq, link, tmp) {
lib/libevtr/ktrfmt.tab.c
1672
evtr_var_t var, tmp;
lib/libevtr/ktrfmt.tab.c
1675
tmp = evtr_var_new(uniq_varname());
lib/libevtr/ktrfmt.tab.c
1676
tmp->val.type = EVTR_VAL_STR;
lib/libevtr/ktrfmt.tab.c
1677
tmp->val.str = (yyvsp[(3) - (3)].tok)->str;
lib/libevtr/ktrfmt.tab.c
1679
if (index_hash(ctx, (yyvsp[(1) - (3)].var)->name, &tmp->val, &var))
lib/libevtr/ktrfmt.y
285
evtr_var_t var, tmp;
lib/libevtr/ktrfmt.y
288
tmp = evtr_var_new(uniq_varname());
lib/libevtr/ktrfmt.y
289
tmp->val.type = EVTR_VAL_STR;
lib/libevtr/ktrfmt.y
290
tmp->val.str = $3->str;
lib/libevtr/ktrfmt.y
292
if (index_hash(ctx, $1->name, &tmp->val, &var))
lib/libfetch/common.c
1419
char *tmp;
lib/libfetch/common.c
1443
tmp = conn->buf;
lib/libfetch/common.c
1445
if ((tmp = realloc(tmp, tmpsize)) == NULL) {
lib/libfetch/common.c
1449
conn->buf = tmp;
lib/libfetch/common.c
1614
struct url_ent *tmp;
lib/libfetch/common.c
1622
tmp = reallocarray(*p, *size * 2 + 1, sizeof(**p));
lib/libfetch/common.c
1623
if (tmp == NULL) {
lib/libfetch/common.c
1629
*p = tmp;
lib/libfetch/common.c
1632
tmp = *p + *len;
lib/libfetch/common.c
1633
snprintf(tmp->name, PATH_MAX, "%s", name);
lib/libfetch/common.c
1634
memcpy(&tmp->stat, us, sizeof(*us));
lib/libfetch/common.c
1637
(++tmp)->name[0] = 0;
lib/libfetch/http.c
196
char *tmp;
lib/libfetch/http.c
201
if ((tmp = realloc(io->buf, len)) == NULL)
lib/libfetch/http.c
203
io->buf = tmp;
lib/libnvmm/libnvmm_x86.c
2846
uint64_t tmp;
lib/libnvmm/libnvmm_x86.c
2850
op1 = memop1 ? &tmp : (uint64_t *)mem->data;
lib/libnvmm/libnvmm_x86.c
2851
op2 = memop1 ? (uint64_t *)mem->data : &tmp;
lib/libnvmm/libnvmm_x86.c
2854
mem->data = (uint8_t *)&tmp;
lib/libnvmm/libnvmm_x86.c
2913
uint64_t tmp;
lib/libnvmm/libnvmm_x86.c
2917
op1 = memop1 ? &tmp : (uint64_t *)mem->data;
lib/libnvmm/libnvmm_x86.c
2918
op2 = memop1 ? (uint64_t *)mem->data : &tmp;
lib/libnvmm/libnvmm_x86.c
2921
mem->data = (uint8_t *)&tmp;
lib/libnvmm/libnvmm_x86.c
2937
uint64_t tmp;
lib/libnvmm/libnvmm_x86.c
2941
op1 = memop1 ? &tmp : (uint64_t *)mem->data;
lib/libnvmm/libnvmm_x86.c
2942
op2 = memop1 ? (uint64_t *)mem->data : &tmp;
lib/libnvmm/libnvmm_x86.c
2945
mem->data = (uint8_t *)&tmp;
lib/libpam/modules/pam_exec/pam_exec.c
114
char **envlist, **tmp, *envstr;
lib/libpam/modules/pam_exec/pam_exec.c
142
tmp = realloc(envlist, (envlen + nitems + 1 + nitems_rv + 1) *
lib/libpam/modules/pam_exec/pam_exec.c
144
if (tmp == NULL) {
lib/libpam/modules/pam_exec/pam_exec.c
148
envlist = tmp;
lib/libssh/openbsd-compat/sys-tree.h
100
#define SPLAY_LINKLEFT(head, tmp, field) do { \
lib/libssh/openbsd-compat/sys-tree.h
101
SPLAY_LEFT(tmp, field) = (head)->sph_root; \
lib/libssh/openbsd-compat/sys-tree.h
102
tmp = (head)->sph_root; \
lib/libssh/openbsd-compat/sys-tree.h
106
#define SPLAY_LINKRIGHT(head, tmp, field) do { \
lib/libssh/openbsd-compat/sys-tree.h
107
SPLAY_RIGHT(tmp, field) = (head)->sph_root; \
lib/libssh/openbsd-compat/sys-tree.h
108
tmp = (head)->sph_root; \
lib/libssh/openbsd-compat/sys-tree.h
342
#define RB_ROTATE_LEFT(head, elm, tmp, field) do { \
lib/libssh/openbsd-compat/sys-tree.h
343
(tmp) = RB_RIGHT(elm, field); \
lib/libssh/openbsd-compat/sys-tree.h
344
if ((RB_RIGHT(elm, field) = RB_LEFT(tmp, field))) { \
lib/libssh/openbsd-compat/sys-tree.h
345
RB_PARENT(RB_LEFT(tmp, field), field) = (elm); \
lib/libssh/openbsd-compat/sys-tree.h
348
if ((RB_PARENT(tmp, field) = RB_PARENT(elm, field))) { \
lib/libssh/openbsd-compat/sys-tree.h
350
RB_LEFT(RB_PARENT(elm, field), field) = (tmp); \
lib/libssh/openbsd-compat/sys-tree.h
352
RB_RIGHT(RB_PARENT(elm, field), field) = (tmp); \
lib/libssh/openbsd-compat/sys-tree.h
354
(head)->rbh_root = (tmp); \
lib/libssh/openbsd-compat/sys-tree.h
355
RB_LEFT(tmp, field) = (elm); \
lib/libssh/openbsd-compat/sys-tree.h
356
RB_PARENT(elm, field) = (tmp); \
lib/libssh/openbsd-compat/sys-tree.h
357
RB_AUGMENT(tmp); \
lib/libssh/openbsd-compat/sys-tree.h
358
if ((RB_PARENT(tmp, field))) \
lib/libssh/openbsd-compat/sys-tree.h
359
RB_AUGMENT(RB_PARENT(tmp, field)); \
lib/libssh/openbsd-compat/sys-tree.h
362
#define RB_ROTATE_RIGHT(head, elm, tmp, field) do { \
lib/libssh/openbsd-compat/sys-tree.h
363
(tmp) = RB_LEFT(elm, field); \
lib/libssh/openbsd-compat/sys-tree.h
364
if ((RB_LEFT(elm, field) = RB_RIGHT(tmp, field))) { \
lib/libssh/openbsd-compat/sys-tree.h
365
RB_PARENT(RB_RIGHT(tmp, field), field) = (elm); \
lib/libssh/openbsd-compat/sys-tree.h
368
if ((RB_PARENT(tmp, field) = RB_PARENT(elm, field))) { \
lib/libssh/openbsd-compat/sys-tree.h
370
RB_LEFT(RB_PARENT(elm, field), field) = (tmp); \
lib/libssh/openbsd-compat/sys-tree.h
372
RB_RIGHT(RB_PARENT(elm, field), field) = (tmp); \
lib/libssh/openbsd-compat/sys-tree.h
374
(head)->rbh_root = (tmp); \
lib/libssh/openbsd-compat/sys-tree.h
375
RB_RIGHT(tmp, field) = (elm); \
lib/libssh/openbsd-compat/sys-tree.h
376
RB_PARENT(elm, field) = (tmp); \
lib/libssh/openbsd-compat/sys-tree.h
377
RB_AUGMENT(tmp); \
lib/libssh/openbsd-compat/sys-tree.h
378
if ((RB_PARENT(tmp, field))) \
lib/libssh/openbsd-compat/sys-tree.h
379
RB_AUGMENT(RB_PARENT(tmp, field)); \
lib/libssh/openbsd-compat/sys-tree.h
410
struct type *parent, *gparent, *tmp; \
lib/libssh/openbsd-compat/sys-tree.h
415
tmp = RB_RIGHT(gparent, field); \
lib/libssh/openbsd-compat/sys-tree.h
416
if (tmp && RB_COLOR(tmp, field) == RB_RED) { \
lib/libssh/openbsd-compat/sys-tree.h
417
RB_COLOR(tmp, field) = RB_BLACK; \
lib/libssh/openbsd-compat/sys-tree.h
423
RB_ROTATE_LEFT(head, parent, tmp, field);\
lib/libssh/openbsd-compat/sys-tree.h
424
tmp = parent; \
lib/libssh/openbsd-compat/sys-tree.h
426
elm = tmp; \
lib/libssh/openbsd-compat/sys-tree.h
429
RB_ROTATE_RIGHT(head, gparent, tmp, field); \
lib/libssh/openbsd-compat/sys-tree.h
431
tmp = RB_LEFT(gparent, field); \
lib/libssh/openbsd-compat/sys-tree.h
432
if (tmp && RB_COLOR(tmp, field) == RB_RED) { \
lib/libssh/openbsd-compat/sys-tree.h
433
RB_COLOR(tmp, field) = RB_BLACK; \
lib/libssh/openbsd-compat/sys-tree.h
439
RB_ROTATE_RIGHT(head, parent, tmp, field);\
lib/libssh/openbsd-compat/sys-tree.h
440
tmp = parent; \
lib/libssh/openbsd-compat/sys-tree.h
442
elm = tmp; \
lib/libssh/openbsd-compat/sys-tree.h
445
RB_ROTATE_LEFT(head, gparent, tmp, field); \
lib/libssh/openbsd-compat/sys-tree.h
454
struct type *tmp; \
lib/libssh/openbsd-compat/sys-tree.h
458
tmp = RB_RIGHT(parent, field); \
lib/libssh/openbsd-compat/sys-tree.h
459
if (RB_COLOR(tmp, field) == RB_RED) { \
lib/libssh/openbsd-compat/sys-tree.h
460
RB_SET_BLACKRED(tmp, parent, field); \
lib/libssh/openbsd-compat/sys-tree.h
461
RB_ROTATE_LEFT(head, parent, tmp, field);\
lib/libssh/openbsd-compat/sys-tree.h
462
tmp = RB_RIGHT(parent, field); \
lib/libssh/openbsd-compat/sys-tree.h
464
if ((RB_LEFT(tmp, field) == NULL || \
lib/libssh/openbsd-compat/sys-tree.h
465
RB_COLOR(RB_LEFT(tmp, field), field) == RB_BLACK) &&\
lib/libssh/openbsd-compat/sys-tree.h
466
(RB_RIGHT(tmp, field) == NULL || \
lib/libssh/openbsd-compat/sys-tree.h
467
RB_COLOR(RB_RIGHT(tmp, field), field) == RB_BLACK)) {\
lib/libssh/openbsd-compat/sys-tree.h
468
RB_COLOR(tmp, field) = RB_RED; \
lib/libssh/openbsd-compat/sys-tree.h
472
if (RB_RIGHT(tmp, field) == NULL || \
lib/libssh/openbsd-compat/sys-tree.h
473
RB_COLOR(RB_RIGHT(tmp, field), field) == RB_BLACK) {\
lib/libssh/openbsd-compat/sys-tree.h
475
if ((oleft = RB_LEFT(tmp, field)))\
lib/libssh/openbsd-compat/sys-tree.h
477
RB_COLOR(tmp, field) = RB_RED; \
lib/libssh/openbsd-compat/sys-tree.h
478
RB_ROTATE_RIGHT(head, tmp, oleft, field);\
lib/libssh/openbsd-compat/sys-tree.h
479
tmp = RB_RIGHT(parent, field); \
lib/libssh/openbsd-compat/sys-tree.h
481
RB_COLOR(tmp, field) = RB_COLOR(parent, field);\
lib/libssh/openbsd-compat/sys-tree.h
483
if (RB_RIGHT(tmp, field)) \
lib/libssh/openbsd-compat/sys-tree.h
484
RB_COLOR(RB_RIGHT(tmp, field), field) = RB_BLACK;\
lib/libssh/openbsd-compat/sys-tree.h
485
RB_ROTATE_LEFT(head, parent, tmp, field);\
lib/libssh/openbsd-compat/sys-tree.h
490
tmp = RB_LEFT(parent, field); \
lib/libssh/openbsd-compat/sys-tree.h
491
if (RB_COLOR(tmp, field) == RB_RED) { \
lib/libssh/openbsd-compat/sys-tree.h
492
RB_SET_BLACKRED(tmp, parent, field); \
lib/libssh/openbsd-compat/sys-tree.h
493
RB_ROTATE_RIGHT(head, parent, tmp, field);\
lib/libssh/openbsd-compat/sys-tree.h
494
tmp = RB_LEFT(parent, field); \
lib/libssh/openbsd-compat/sys-tree.h
496
if ((RB_LEFT(tmp, field) == NULL || \
lib/libssh/openbsd-compat/sys-tree.h
497
RB_COLOR(RB_LEFT(tmp, field), field) == RB_BLACK) &&\
lib/libssh/openbsd-compat/sys-tree.h
498
(RB_RIGHT(tmp, field) == NULL || \
lib/libssh/openbsd-compat/sys-tree.h
499
RB_COLOR(RB_RIGHT(tmp, field), field) == RB_BLACK)) {\
lib/libssh/openbsd-compat/sys-tree.h
500
RB_COLOR(tmp, field) = RB_RED; \
lib/libssh/openbsd-compat/sys-tree.h
504
if (RB_LEFT(tmp, field) == NULL || \
lib/libssh/openbsd-compat/sys-tree.h
505
RB_COLOR(RB_LEFT(tmp, field), field) == RB_BLACK) {\
lib/libssh/openbsd-compat/sys-tree.h
507
if ((oright = RB_RIGHT(tmp, field)))\
lib/libssh/openbsd-compat/sys-tree.h
509
RB_COLOR(tmp, field) = RB_RED; \
lib/libssh/openbsd-compat/sys-tree.h
510
RB_ROTATE_LEFT(head, tmp, oright, field);\
lib/libssh/openbsd-compat/sys-tree.h
511
tmp = RB_LEFT(parent, field); \
lib/libssh/openbsd-compat/sys-tree.h
513
RB_COLOR(tmp, field) = RB_COLOR(parent, field);\
lib/libssh/openbsd-compat/sys-tree.h
515
if (RB_LEFT(tmp, field)) \
lib/libssh/openbsd-compat/sys-tree.h
516
RB_COLOR(RB_LEFT(tmp, field), field) = RB_BLACK;\
lib/libssh/openbsd-compat/sys-tree.h
517
RB_ROTATE_RIGHT(head, parent, tmp, field);\
lib/libssh/openbsd-compat/sys-tree.h
598
struct type *tmp; \
lib/libssh/openbsd-compat/sys-tree.h
601
tmp = RB_ROOT(head); \
lib/libssh/openbsd-compat/sys-tree.h
602
while (tmp) { \
lib/libssh/openbsd-compat/sys-tree.h
603
parent = tmp; \
lib/libssh/openbsd-compat/sys-tree.h
606
tmp = RB_LEFT(tmp, field); \
lib/libssh/openbsd-compat/sys-tree.h
608
tmp = RB_RIGHT(tmp, field); \
lib/libssh/openbsd-compat/sys-tree.h
610
return (tmp); \
lib/libssh/openbsd-compat/sys-tree.h
629
struct type *tmp = RB_ROOT(head); \
lib/libssh/openbsd-compat/sys-tree.h
631
while (tmp) { \
lib/libssh/openbsd-compat/sys-tree.h
632
comp = cmp(elm, tmp); \
lib/libssh/openbsd-compat/sys-tree.h
634
tmp = RB_LEFT(tmp, field); \
lib/libssh/openbsd-compat/sys-tree.h
636
tmp = RB_RIGHT(tmp, field); \
lib/libssh/openbsd-compat/sys-tree.h
638
return (tmp); \
lib/libssh/openbsd-compat/sys-tree.h
647
struct type *tmp = RB_ROOT(head); \
lib/libssh/openbsd-compat/sys-tree.h
650
while (tmp) { \
lib/libssh/openbsd-compat/sys-tree.h
651
comp = cmp(elm, tmp); \
lib/libssh/openbsd-compat/sys-tree.h
653
res = tmp; \
lib/libssh/openbsd-compat/sys-tree.h
654
tmp = RB_LEFT(tmp, field); \
lib/libssh/openbsd-compat/sys-tree.h
657
tmp = RB_RIGHT(tmp, field); \
lib/libssh/openbsd-compat/sys-tree.h
659
return (tmp); \
lib/libssh/openbsd-compat/sys-tree.h
711
struct type *tmp = RB_ROOT(head); \
lib/libssh/openbsd-compat/sys-tree.h
713
while (tmp) { \
lib/libssh/openbsd-compat/sys-tree.h
714
parent = tmp; \
lib/libssh/openbsd-compat/sys-tree.h
716
tmp = RB_LEFT(tmp, field); \
lib/libssh/openbsd-compat/sys-tree.h
718
tmp = RB_RIGHT(tmp, field); \
lib/libssh/openbsd-compat/sys-tree.h
88
#define SPLAY_ROTATE_RIGHT(head, tmp, field) do { \
lib/libssh/openbsd-compat/sys-tree.h
89
SPLAY_LEFT((head)->sph_root, field) = SPLAY_RIGHT(tmp, field); \
lib/libssh/openbsd-compat/sys-tree.h
90
SPLAY_RIGHT(tmp, field) = (head)->sph_root; \
lib/libssh/openbsd-compat/sys-tree.h
91
(head)->sph_root = tmp; \
lib/libssh/openbsd-compat/sys-tree.h
94
#define SPLAY_ROTATE_LEFT(head, tmp, field) do { \
lib/libssh/openbsd-compat/sys-tree.h
95
SPLAY_RIGHT((head)->sph_root, field) = SPLAY_LEFT(tmp, field); \
lib/libssh/openbsd-compat/sys-tree.h
96
SPLAY_LEFT(tmp, field) = (head)->sph_root; \
lib/libssh/openbsd-compat/sys-tree.h
97
(head)->sph_root = tmp; \
lib/libtcplay/tcplay.c
536
uint64_t tmp;
lib/libtcplay/tcplay.c
695
&tmp)) != 0) {
lib/libtcplay/tcplay.c
700
if (tmp >= (blocks*blksz) - MIN_VOL_BYTES) {
lib/libtcplay/tcplay.c
707
hidden_blocks = (size_t)tmp;
lib/libtelnet/pk.c
201
BIGNUM *pk, *sk, *tmp, *base, *root, *modulus;
lib/libtelnet/pk.c
205
tmp = itobn(0);
lib/libtelnet/pk.c
220
BN_zero(tmp);
lib/libtelnet/pk.c
221
BN_add_word(tmp, r);
lib/libtelnet/pk.c
223
BN_add(sk, tmp, sk);
lib/libtelnet/pk.c
225
BN_zero(tmp);
lib/libtelnet/pk.c
226
BN_div(tmp, sk, sk, modulus, ctx);
lib/libtelnet/pk.c
246
BN_free(tmp);
lib/libthread_db/libthread_xu.c
388
td_thr_events_e tmp;
lib/libthread_db/libthread_xu.c
413
tmp = 0;
lib/libthread_db/libthread_xu.c
414
ps_pwrite(ta->ph, pt + ta->thread_off_event_buf, &tmp, sizeof(tmp));
lib/libthread_db/libthread_xu.c
630
td_thr_events_e tmp;
lib/libthread_db/libthread_xu.c
652
tmp = 0;
lib/libthread_db/libthread_xu.c
653
ps_pwrite(ta->ph, pt + ta->thread_off_event_buf, &tmp, sizeof(tmp));
lib/libthread_db/thread_db.c
53
td_err_e ret, tmp;
lib/libthread_db/thread_db.c
59
tmp = ops[i]->to_init();
lib/libthread_db/thread_db.c
60
if (tmp != TD_OK)
lib/libthread_db/thread_db.c
61
ret = tmp;
lib/libthread_xu/thread/thr_fork.c
166
umtx_t tmp;
lib/libthread_xu/thread/thr_fork.c
183
tmp = inprogress;
lib/libthread_xu/thread/thr_fork.c
184
while (tmp) {
lib/libthread_xu/thread/thr_fork.c
187
_thr_umtx_wait(&inprogress, tmp, NULL, 0);
lib/libthread_xu/thread/thr_fork.c
190
tmp = inprogress;
lib/libthread_xu/thread/thr_join.c
133
tmp = pthread->ret;
lib/libthread_xu/thread/thr_join.c
141
*thread_return = tmp;
lib/libthread_xu/thread/thr_join.c
74
void *tmp;
lib/libthread_xu/thread/thr_kern.c
133
int tmp = errno;
lib/libthread_xu/thread/thr_kern.c
143
errno = tmp;
lib/libthread_xu/thread/thr_mutex.c
705
int tmp;
lib/libthread_xu/thread/thr_mutex.c
712
tmp = (*mutex)->m_prio;
lib/libthread_xu/thread/thr_mutex.c
715
*old_ceiling = tmp;
lib/libthread_xu/thread/thr_suspend_np.c
118
umtx_t tmp;
lib/libthread_xu/thread/thr_suspend_np.c
123
tmp = thread->cycle;
lib/libthread_xu/thread/thr_suspend_np.c
127
_thr_umtx_wait(&thread->cycle, tmp, NULL, 0);
lib/libusb/libusb20_ugen20.c
134
const char *tmp = id;
lib/libusb/libusb20_ugen20.c
142
pdev->bus_number = ugen20_path_convert_one(&tmp);
lib/libusb/libusb20_ugen20.c
143
pdev->device_address = ugen20_path_convert_one(&tmp);
lib/libutil/dehumanize_number.c
101
tmp = strtoll(str, &ep, 10);
lib/libutil/dehumanize_number.c
104
else if (errno == ERANGE && (tmp == LLONG_MAX || tmp == LLONG_MIN))
lib/libutil/dehumanize_number.c
107
tmp2 = tmp * multiplier;
lib/libutil/dehumanize_number.c
109
if (tmp != tmp2) {
lib/libutil/dehumanize_number.c
113
*size = tmp * multiplier;
lib/libutil/dehumanize_number.c
56
long long tmp, tmp2;
lib/libutil/property.c
247
properties tmp;
lib/libutil/property.c
250
tmp = list->next;
lib/libutil/property.c
256
list = tmp;
libexec/ftpd/ftpcmd.y
222
char *tmp = NULL;
libexec/ftpd/ftpcmd.y
237
tmp = strdup($4);
libexec/ftpd/ftpcmd.y
239
syslog(LOG_DEBUG, "%s", tmp);
libexec/ftpd/ftpcmd.y
240
if (!tmp) {
libexec/ftpd/ftpcmd.y
244
p = tmp;
libexec/ftpd/ftpcmd.y
254
if (tmp)
libexec/ftpd/ftpcmd.y
255
free(tmp);
libexec/ftpd/ftpcmd.y
303
free(tmp);
libexec/ftpd/ftpcmd.y
304
tmp = NULL;
libexec/ftpd/ftpd.c
2446
union sockunion tmp;
libexec/ftpd/ftpd.c
2448
tmp = *su;
libexec/ftpd/ftpd.c
2449
if (tmp.su_family == AF_INET6)
libexec/ftpd/ftpd.c
2450
tmp.su_sin6.sin6_scope_id = 0;
libexec/ftpd/ftpd.c
2451
if (!getnameinfo((struct sockaddr *)&tmp, tmp.su_len,
libexec/ftpd/ftpd.c
2457
af, hname, htons(tmp.su_port));
libexec/getty/chat.c
140
char *tmp = NULL;
libexec/getty/chat.c
143
if ((l=strlen(str)) > 0 && (tmp=malloc(l + 1)) != NULL &&
libexec/getty/chat.c
148
for (l = 0, p = strtok(strcpy(tmp, str), ws);
libexec/getty/chat.c
226
*chatstr = tmp;
libexec/getty/chat.c
229
free(tmp);
libexec/getty/chat.c
244
char * tmp = buf ? *buf : tmpbuf;
libexec/getty/chat.c
247
strcpy(tmp, "M-");
libexec/getty/chat.c
254
tmp[l++] = '^';
libexec/getty/chat.c
255
tmp[l++] = ch + '@';
libexec/getty/chat.c
257
tmp[l++] = '^';
libexec/getty/chat.c
258
tmp[l++] = '?';
libexec/getty/chat.c
260
tmp[l++] = ch;
libexec/getty/chat.c
261
tmp[l] = '\0';
libexec/getty/chat.c
264
*buf = tmp + l;
libexec/getty/chat.c
265
return tmp;
libexec/getty/chat.c
276
static unsigned char * tmp = NULL;
libexec/getty/chat.c
280
tmp = realloc(tmp, tmplen = l * 4 + 1);
libexec/getty/chat.c
282
if (tmp == NULL) {
libexec/getty/chat.c
287
char * p = tmp;
libexec/getty/chat.c
294
return tmp;
libexec/mknetid/hash.c
135
struct grouplist *tmp = NULL;
libexec/mknetid/hash.c
142
tmp = (struct grouplist *)malloc(sizeof(struct grouplist));
libexec/mknetid/hash.c
143
tmp->groupid = gid;
libexec/mknetid/hash.c
144
tmp->next = NULL;
libexec/mknetid/hash.c
150
tmp->next = cur->groups;
libexec/mknetid/hash.c
151
cur->groups = tmp;
libexec/mknetid/hash.c
161
new->groups = tmp;
libexec/rbootd/utils.c
100
tmp->tm_sec, rconn->tstamp.tv_usec);
libexec/rbootd/utils.c
78
struct tm *tmp;
libexec/rbootd/utils.c
98
tmp = localtime((time_t *)&rconn->tstamp.tv_sec);
libexec/rbootd/utils.c
99
fprintf(DbgFp, "%02d:%02d:%02d.%06ld ", tmp->tm_hour, tmp->tm_min,
libexec/revnetgroup/hash.c
176
struct grouplist *tmp;
libexec/revnetgroup/hash.c
182
tmp = (struct grouplist *)malloc(sizeof(struct grouplist));
libexec/revnetgroup/hash.c
183
tmp->groupname = strdup(data);
libexec/revnetgroup/hash.c
184
tmp->next = NULL;
libexec/revnetgroup/hash.c
189
tmp->next = cur->groups;
libexec/revnetgroup/hash.c
190
cur->groups = tmp;
libexec/revnetgroup/hash.c
200
new->groups = tmp;
libexec/revnetgroup/revnetgroup.c
160
struct grouplist *tmp;
libexec/revnetgroup/revnetgroup.c
162
tmp = mcur->groups;
libexec/revnetgroup/revnetgroup.c
163
while(tmp) {
libexec/revnetgroup/revnetgroup.c
164
printf ("%s", tmp->groupname);
libexec/revnetgroup/revnetgroup.c
165
tmp = tmp->next;
libexec/revnetgroup/revnetgroup.c
166
if (tmp)
libexec/rtld-elf/rtld_printf.c
130
int base, lflag, qflag, tmp, width, ladjust, sharpflag, neg, sign, dot;
libexec/rtld-elf/rtld_printf.c
210
for (tmp = 0; *p;) {
libexec/rtld-elf/rtld_printf.c
213
PCHAR(tmp ? ',' : '<');
libexec/rtld-elf/rtld_printf.c
216
tmp = 1;
libexec/rtld-elf/rtld_printf.c
221
if (tmp)
libexec/rtld-elf/rtld_printf.c
377
tmp = 0;
libexec/rtld-elf/rtld_printf.c
380
tmp++;
libexec/rtld-elf/rtld_printf.c
382
tmp += 2;
libexec/rtld-elf/rtld_printf.c
385
tmp++;
libexec/rtld-elf/rtld_printf.c
388
dwidth = width - tmp;
libexec/rtld-elf/rtld_printf.c
389
width -= tmp + imax(dwidth, n);
sbin/ccdconfig/ccdconfig.c
627
int i, tmp, val = ~CCDF_USERMASK;
sbin/ccdconfig/ccdconfig.c
643
tmp = 0;
sbin/ccdconfig/ccdconfig.c
652
tmp |= flagvaltab[i].fv_val;
sbin/ccdconfig/ccdconfig.c
657
val = tmp;
sbin/dhclient/convert.c
104
u_int16_t tmp = htons(val);
sbin/dhclient/convert.c
106
memcpy(obuf, &tmp, sizeof(tmp));
sbin/dhclient/convert.c
112
int16_t tmp = htons(val);
sbin/dhclient/convert.c
114
memcpy(obuf, &tmp, sizeof(tmp));
sbin/dhclient/convert.c
88
u_int32_t tmp = htonl(val);
sbin/dhclient/convert.c
90
memcpy(obuf, &tmp, sizeof(tmp));
sbin/dhclient/convert.c
96
int32_t tmp = htonl(val);
sbin/dhclient/convert.c
98
memcpy(obuf, &tmp, sizeof(tmp));
sbin/disklabel32/disklabel.c
1066
char *tmp; \
sbin/disklabel32/disklabel.c
1068
(n) = strtoul(cp, &tmp, 10); \
sbin/disklabel32/disklabel.c
1069
if (tmp) (w) = *tmp; \
sbin/disklabel64/disklabel64.c
1051
char *tmp;
sbin/disklabel64/disklabel64.c
1059
*vv = strtoull(*cp, &tmp, 0);
sbin/disklabel64/disklabel64.c
1064
if (tmp)
sbin/disklabel64/disklabel64.c
1065
return(*tmp);
sbin/fdisk/fdisk.c
51
#define Decimal(str, ans, tmp) \
sbin/fdisk/fdisk.c
52
if (decimal(str, &tmp, ans)) ans = tmp
sbin/fdisk/fdisk.c
558
int tmp, tsec, tcyl, thd;
sbin/fdisk/fdisk.c
579
Decimal("sysid (108=DragonFly)", partp->dp_typ, tmp);
sbin/fdisk/fdisk.c
580
Decimal("start", partp->dp_start, tmp);
sbin/fdisk/fdisk.c
581
Decimal("size", partp->dp_size, tmp);
sbin/fdisk/fdisk.c
591
Decimal("beginning cylinder", tcyl, tmp);
sbin/fdisk/fdisk.c
592
Decimal("beginning head", thd, tmp);
sbin/fdisk/fdisk.c
593
Decimal("beginning sector", tsec, tmp);
sbin/fdisk/fdisk.c
609
Decimal("ending cylinder", tcyl, tmp);
sbin/fdisk/fdisk.c
610
Decimal("ending head", thd, tmp);
sbin/fdisk/fdisk.c
611
Decimal("ending sector", tsec, tmp);
sbin/fdisk/fdisk.c
650
int active, i, new, tmp;
sbin/fdisk/fdisk.c
671
Decimal("active partition", new, tmp);
sbin/fdisk/fdisk.c
695
int tmp;
sbin/fdisk/fdisk.c
700
Decimal("BIOS's idea of #cylinders", dos_cyls, tmp);
sbin/fdisk/fdisk.c
701
Decimal("BIOS's idea of #heads", dos_heads, tmp);
sbin/fdisk/fdisk.c
702
Decimal("BIOS's idea of #sectors", dos_sectors, tmp);
sbin/fsck/dir.c
126
u_char tmp;
sbin/fsck/dir.c
128
tmp = tdp->d_namlen;
sbin/fsck/dir.c
130
tdp->d_type = tmp;
sbin/fsck/dir.c
138
u_char tmp;
sbin/fsck/dir.c
141
tmp = tdp->d_namlen;
sbin/fsck/dir.c
143
tdp->d_type = tmp;
sbin/fsck/dir.c
382
u_char tmp;
sbin/fsck/dir.c
384
tmp = dirp->d_namlen;
sbin/fsck/dir.c
386
dirp->d_type = tmp;
sbin/fsck/pass2.c
271
u_char tmp;
sbin/fsck/pass2.c
273
tmp = proto.d_type;
sbin/fsck/pass2.c
275
proto.d_namlen = tmp;
sbin/fsck/pass2.c
314
u_char tmp;
sbin/fsck/pass2.c
316
tmp = proto.d_type;
sbin/fsck/pass2.c
318
proto.d_namlen = tmp;
sbin/gpt/gpt.c
300
uuid_t tmp;
sbin/gpt/gpt.c
314
uuid_name_lookup(&tmp, s, &status);
sbin/gpt/gpt.c
316
*uuid = tmp;
sbin/hammer/cmd_config.c
108
char *runcmd, *editor, *tmp;
sbin/hammer/cmd_config.c
168
if ((tmp = getenv("EDITOR")) != NULL ||
sbin/hammer/cmd_config.c
169
(tmp = getenv("VISUAL")) != NULL) {
sbin/hammer/cmd_config.c
170
editor = strdup(tmp);
sbin/hammer/cmd_dedup.c
265
char *tmp;
sbin/hammer/cmd_dedup.c
289
asprintf(&tmp, "%s/%s/.dedup.cycle",
sbin/hammer/cmd_dedup.c
292
asprintf(&tmp, "%s/.dedup.cycle",
sbin/hammer/cmd_dedup.c
295
CyclePath = tmp;
sbin/hammer/cmd_dedup.c
393
free(tmp);
sbin/hammer2/cmd_debug.c
1149
tmp = bref->data_off & ~HAMMER2_OFF_MASK_RADIX;
sbin/hammer2/cmd_debug.c
1150
tmp &= HAMMER2_SEGMASK;
sbin/hammer2/cmd_debug.c
1151
tmp /= HAMMER2_PBUFSIZE;
sbin/hammer2/cmd_debug.c
1152
assert(tmp >= HAMMER2_ZONE_FREEMAP_00);
sbin/hammer2/cmd_debug.c
1153
assert(tmp < HAMMER2_ZONE_FREEMAP_END);
sbin/hammer2/cmd_debug.c
1154
tmp -= HAMMER2_ZONE_FREEMAP_00;
sbin/hammer2/cmd_debug.c
1155
tmp /= HAMMER2_ZONE_FREEMAP_INC;
sbin/hammer2/cmd_debug.c
1156
tabprintf(tab, "rotation=%d\n", (int)tmp);
sbin/hammer2/cmd_debug.c
1183
tmp = bref->data_off & ~HAMMER2_OFF_MASK_RADIX;
sbin/hammer2/cmd_debug.c
1184
tmp &= HAMMER2_SEGMASK;
sbin/hammer2/cmd_debug.c
1185
tmp /= HAMMER2_PBUFSIZE;
sbin/hammer2/cmd_debug.c
1186
assert(tmp >= HAMMER2_ZONE_FREEMAP_00);
sbin/hammer2/cmd_debug.c
1187
assert(tmp < HAMMER2_ZONE_FREEMAP_END);
sbin/hammer2/cmd_debug.c
1188
tmp -= HAMMER2_ZONE_FREEMAP_00;
sbin/hammer2/cmd_debug.c
1189
tmp /= HAMMER2_ZONE_FREEMAP_INC;
sbin/hammer2/cmd_debug.c
1190
tabprintf(tab, "rotation=%d\n", (int)tmp);
sbin/hammer2/cmd_debug.c
403
hammer2_off_t tmp = voldata->volu_loff[i];
sbin/hammer2/cmd_debug.c
404
if (tmp > volu_loff) {
sbin/hammer2/cmd_debug.c
405
ret = tmp;
sbin/hammer2/cmd_debug.c
765
hammer2_off_t tmp;
sbin/hammer2/zlib/hammer2_zlib_adler32.c
31
unsigned long tmp = a >> 16; \
sbin/hammer2/zlib/hammer2_zlib_adler32.c
33
a += (tmp << 4) - tmp; \
sbin/hammer2/zlib/hammer2_zlib_adler32.c
47
z_off64_t tmp = a >> 32; \
sbin/hammer2/zlib/hammer2_zlib_adler32.c
49
a += (tmp << 8) - (tmp << 5) + tmp; \
sbin/hammer2/zlib/hammer2_zlib_adler32.c
50
tmp = a >> 16; \
sbin/hammer2/zlib/hammer2_zlib_adler32.c
52
a += (tmp << 4) - tmp; \
sbin/hammer2/zlib/hammer2_zlib_adler32.c
53
tmp = a >> 16; \
sbin/hammer2/zlib/hammer2_zlib_adler32.c
55
a += (tmp << 4) - tmp; \
sbin/ifconfig/ifconfig.c
355
struct ifa_order_elt *cur, *tmp;
sbin/ifconfig/ifconfig.c
540
TAILQ_FOREACH_MUTABLE(cur, &q, link, tmp)
sbin/ifconfig/iflagg.c
95
char *str, *tmp, *tok;
sbin/ifconfig/iflagg.c
98
str = tmp = strdup(val);
sbin/ifconfig/iflagg.c
99
while ((tok = strsep(&tmp, ",")) != NULL) {
sbin/ipfw3/ipfw3.c
173
struct ipfw3_keyword *tmp;
sbin/ipfw3/ipfw3.c
175
tmp=keywords;
sbin/ipfw3/ipfw3.c
177
if (tmp->type == NONE) {
sbin/ipfw3/ipfw3.c
178
strcpy(tmp->word, word);
sbin/ipfw3/ipfw3.c
179
tmp->module = module;
sbin/ipfw3/ipfw3.c
180
tmp->opcode = opcode;
sbin/ipfw3/ipfw3.c
181
tmp->type = type;
sbin/ipfw3/ipfw3.c
184
if (strcmp(tmp->word, word) == 0)
sbin/ipfw3/ipfw3.c
187
tmp++;
sbin/ipfw3/ipfw3.c
195
struct ipfw3_mapping *tmp;
sbin/ipfw3/ipfw3.c
197
tmp = mappings;
sbin/ipfw3/ipfw3.c
199
if (tmp->type == NONE) {
sbin/ipfw3/ipfw3.c
200
tmp->module = module;
sbin/ipfw3/ipfw3.c
201
tmp->opcode = opcode;
sbin/ipfw3/ipfw3.c
202
tmp->parser = parser;
sbin/ipfw3/ipfw3.c
203
tmp->shower = shower;
sbin/ipfw3/ipfw3.c
204
tmp->type = IN_USE;
sbin/ipfw3/ipfw3.c
207
if (tmp->opcode == opcode && tmp->module == module) {
sbin/ipfw3/ipfw3.c
212
tmp++;
sbin/iscontrol/auth_subr.c
102
SHA1_Update(&ctx, tmp, len);
sbin/iscontrol/auth_subr.c
103
free(tmp);
sbin/iscontrol/auth_subr.c
105
if((len = str2bin(cp, &tmp)) == 0) {
sbin/iscontrol/auth_subr.c
109
SHA1_Update(&ctx, tmp, len);
sbin/iscontrol/auth_subr.c
110
free(tmp);
sbin/iscontrol/auth_subr.c
152
unsigned char tmp[1024];
sbin/iscontrol/auth_subr.c
154
if(len > sizeof(tmp))
sbin/iscontrol/auth_subr.c
158
read(fd, tmp, len);
sbin/iscontrol/auth_subr.c
160
return bin2str(encoding, tmp, len);
sbin/iscontrol/auth_subr.c
56
char *tmp;
sbin/iscontrol/auth_subr.c
65
if((len = str2bin(chapSecret, &tmp)) == 0) {
sbin/iscontrol/auth_subr.c
69
MD5_Update(&ctx, tmp, len);
sbin/iscontrol/auth_subr.c
70
free(tmp);
sbin/iscontrol/auth_subr.c
72
if((len = str2bin(cp, &tmp)) == 0) {
sbin/iscontrol/auth_subr.c
76
MD5_Update(&ctx, tmp, len);
sbin/iscontrol/auth_subr.c
77
free(tmp);
sbin/iscontrol/auth_subr.c
89
char *tmp;
sbin/iscontrol/auth_subr.c
98
if((len = str2bin(chapSecret, &tmp)) == 0) {
sbin/iscontrol/misc.c
101
len = dst - tmp;
sbin/iscontrol/misc.c
109
if((tmp = malloc(len)) == NULL) {
sbin/iscontrol/misc.c
113
dst = tmp;
sbin/iscontrol/misc.c
134
len = dst - tmp;
sbin/iscontrol/misc.c
141
if((tmp = malloc(len)) == NULL)
sbin/iscontrol/misc.c
143
dst = tmp;
sbin/iscontrol/misc.c
149
*rsp = tmp;
sbin/iscontrol/misc.c
81
char *src, *dst, *tmp;
sbin/iscontrol/misc.c
85
tmp = NULL;
sbin/iscontrol/misc.c
90
if((tmp = malloc((len+1)/2)) == NULL) {
sbin/iscontrol/misc.c
94
dst = tmp;
sbin/kldunload/kldunload.c
51
long tmp;
sbin/kldunload/kldunload.c
58
tmp = strtol(optarg, &ep, 10);
sbin/kldunload/kldunload.c
59
if (*ep != '\0' || tmp < INT_MIN || tmp > INT_MAX)
sbin/kldunload/kldunload.c
61
fileid = (int)tmp;
sbin/mountctl/mountctl.c
103
char *tmp;
sbin/mountctl/mountctl.c
209
tmp = strdup(mountpt);
sbin/mountctl/mountctl.c
210
*strchr(tmp, ':') = 0;
sbin/mountctl/mountctl.c
211
mountpt = tmp;
sbin/newfs/fscopy.c
113
tmp = path;
sbin/newfs/fscopy.c
114
asprintf(&path, "%s/%s", scan->fs_Name, tmp);
sbin/newfs/fscopy.c
115
free(tmp);
sbin/newfs/fscopy.c
120
tmp = path;
sbin/newfs/fscopy.c
121
asprintf(&path, "../%s", tmp);
sbin/newfs/fscopy.c
122
free(tmp);
sbin/newfs/fscopy.c
95
char *tmp;
sbin/swapon/swapon.c
411
char tmp[16];
sbin/swapon/swapon.c
413
humanize_number(tmp, 5, (int64_t)val, "", HN_AUTOSCALE,
sbin/swapon/swapon.c
415
snprintf(buf, bufsize, "%*s", hlen, tmp);
sbin/vinum/commands.c
1105
reparse(char *buf, char *tmp)
sbin/vinum/commands.c
1112
strcpy(tmp, buf);
sbin/vinum/commands.c
1113
ptr = strtok(tmp, ws);
sbin/vinum/commands.c
66
static void reparse(char *buf, char *tmp);
share/examples/libvgl/demo.c
40
VGLBitmap *tmp;
share/examples/libvgl/demo.c
58
tmp = VGLBitmapCreate(MEMBUF, 256, 256, NULL);
share/examples/libvgl/demo.c
59
VGLBitmapAllocateBits(tmp);
share/examples/libvgl/demo.c
60
VGLClear(tmp, 0);
share/examples/libvgl/demo.c
91
tmp->Bitmap[i+256*j] = i%16;
share/examples/libvgl/demo.c
92
VGLBitmapCopy(tmp, 0, 0, VGLDisplay, 0, 0, 128, 128);
share/examples/libvgl/demo.c
95
tmp->Bitmap[i+256*j] = j%16;
share/examples/libvgl/demo.c
96
VGLBitmapCopy(tmp, 0, 0, VGLDisplay, 3, 128, 128, 128);
share/examples/libvgl/demo.c
98
VGLBitmapCopy(VGLDisplay, 237, 311, tmp, 64, 64, 128, 128);
share/examples/libvgl/demo.c
99
VGLBitmapCopy(tmp, 32, 32, VGLDisplay, 400, 128, 128, 128);
stand/boot/common/interp_parse.c
157
tmp = *q;
stand/boot/common/interp_parse.c
165
*q = tmp; /* restore value */
stand/boot/common/interp_parse.c
84
char token, tmp, quote, *buf;
stand/boot/dloader/cmds.c
227
int tmp;
stand/boot/dloader/cmds.c
310
tmp = perform(argc, argv);
stand/boot/dloader/cmds.c
311
if (tmp != CMD_OK) {
stand/lib/printf.c
185
int base, lflag, qflag, tmp, width, ladjust, sharpflag, neg, sign, dot;
stand/lib/printf.c
388
tmp = 0;
stand/lib/printf.c
391
tmp++;
stand/lib/printf.c
393
tmp += 2;
stand/lib/printf.c
396
tmp++;
stand/lib/printf.c
399
dwidth = width - tmp;
stand/lib/printf.c
400
width -= tmp + imax(dwidth, n);
stand/lib/qdivrem.c
102
tmp.ul[H] = tmp.ul[L] = 1 / zero;
stand/lib/qdivrem.c
105
return (tmp.q);
stand/lib/qdivrem.c
129
tmp.uq = uq;
stand/lib/qdivrem.c
131
u[1] = HHALF(tmp.ul[H]);
stand/lib/qdivrem.c
132
u[2] = LHALF(tmp.ul[H]);
stand/lib/qdivrem.c
133
u[3] = HHALF(tmp.ul[L]);
stand/lib/qdivrem.c
134
u[4] = LHALF(tmp.ul[L]);
stand/lib/qdivrem.c
135
tmp.uq = vq;
stand/lib/qdivrem.c
136
v[1] = HHALF(tmp.ul[H]);
stand/lib/qdivrem.c
137
v[2] = LHALF(tmp.ul[H]);
stand/lib/qdivrem.c
138
v[3] = HHALF(tmp.ul[L]);
stand/lib/qdivrem.c
139
v[4] = LHALF(tmp.ul[L]);
stand/lib/qdivrem.c
163
tmp.ul[H] = COMBINE(q1, q2);
stand/lib/qdivrem.c
164
tmp.ul[L] = COMBINE(q3, q4);
stand/lib/qdivrem.c
165
return (tmp.q);
stand/lib/qdivrem.c
271
tmp.ul[H] = COMBINE(uspace[1], uspace[2]);
stand/lib/qdivrem.c
272
tmp.ul[L] = COMBINE(uspace[3], uspace[4]);
stand/lib/qdivrem.c
273
*arq = tmp.q;
stand/lib/qdivrem.c
276
tmp.ul[H] = COMBINE(qspace[1], qspace[2]);
stand/lib/qdivrem.c
277
tmp.ul[L] = COMBINE(qspace[3], qspace[4]);
stand/lib/qdivrem.c
278
return (tmp.q);
stand/lib/qdivrem.c
88
union uu tmp;
stand/lib/splitfs.c
246
void *tmp;
stand/lib/splitfs.c
248
tmp = malloc(SEEK_BUF);
stand/lib/splitfs.c
249
if (tmp == NULL)
stand/lib/splitfs.c
255
errno = splitfs_read(f, tmp, min(seek_by, SEEK_BUF), &resid);
stand/lib/splitfs.c
261
free(tmp);
sys/bus/cam/scsi/scsi_sa.c
525
int unit, mode, error, writing, tmp;
sys/bus/cam/scsi/scsi_sa.c
613
tmp = sarewind(periph);
sys/bus/cam/scsi/scsi_sa.c
614
if (tmp) {
sys/bus/cam/scsi/scsi_sa.c
616
error = tmp;
sys/bus/cam/scsi/scsi_sa.c
629
tmp = saspace(periph, -1, SS_FILEMARKS);
sys/bus/cam/scsi/scsi_sa.c
630
if (tmp) {
sys/bus/cam/scsi/scsi_ses.c
501
ses_encstat tmp;
sys/bus/cam/scsi/scsi_ses.c
586
tmp = ssc->ses_encstat & ~ENCI_SVALID;
sys/bus/cam/scsi/scsi_ses.c
588
error = copyout(&tmp, addr, sizeof (ses_encstat));
sys/bus/cam/scsi/scsi_ses.c
589
ssc->ses_encstat = tmp;
sys/bus/cam/scsi/scsi_ses.c
593
error = copyin(addr, &tmp, sizeof (ses_encstat));
sys/bus/cam/scsi/scsi_ses.c
597
error = (*ssc->ses_vec.set_encstat)(ssc, tmp, 1);
sys/bus/pccard/pccard.c
544
bus_size_t iosize, tmp;
sys/bus/pccard/pccard.c
559
tmp = pf->pf_mfc_iomax - pf->pf_mfc_iobase;
sys/bus/pccard/pccard.c
561
for (iosize = 1; iosize < tmp; iosize <<= 1)
sys/bus/pccard/pccard.c
580
struct pccard_function *tmp;
sys/bus/pccard/pccard.c
606
STAILQ_FOREACH(tmp, &pf->sc->card.pf_head, pf_list) {
sys/bus/pccard/pccard.c
607
if ((tmp->pf_flags & PFF_ENABLED) &&
sys/bus/pccard/pccard.c
608
(pf->ccr_base >= (tmp->ccr_base - tmp->pf_ccr_offset)) &&
sys/bus/pccard/pccard.c
610
(tmp->ccr_base - tmp->pf_ccr_offset +
sys/bus/pccard/pccard.c
611
tmp->pf_ccr_realsize))) {
sys/bus/pccard/pccard.c
612
pf->pf_ccrt = tmp->pf_ccrt;
sys/bus/pccard/pccard.c
613
pf->pf_ccrh = tmp->pf_ccrh;
sys/bus/pccard/pccard.c
614
pf->pf_ccr_realsize = tmp->pf_ccr_realsize;
sys/bus/pccard/pccard.c
623
pf->pf_ccr_window = tmp->pf_ccr_window;
sys/bus/pccard/pccard.c
627
if (tmp == NULL) {
sys/bus/pccard/pccard.c
668
STAILQ_FOREACH(tmp, &pf->sc->card.pf_head, pf_list) {
sys/bus/pccard/pccard.c
669
device_printf(tmp->sc->dev,
sys/bus/pccard/pccard.c
672
tmp->number, tmp->pf_ccr_window,
sys/bus/pccard/pccard.c
673
tmp->pf_ccr_offset,
sys/bus/pccard/pccard.c
674
pccard_ccr_read(tmp, 0x00),
sys/bus/pccard/pccard.c
675
pccard_ccr_read(tmp, 0x02),
sys/bus/pccard/pccard.c
676
pccard_ccr_read(tmp, 0x04),
sys/bus/pccard/pccard.c
677
pccard_ccr_read(tmp, 0x06),
sys/bus/pccard/pccard.c
678
pccard_ccr_read(tmp, 0x0A),
sys/bus/pccard/pccard.c
679
pccard_ccr_read(tmp, 0x0C),
sys/bus/pccard/pccard.c
680
pccard_ccr_read(tmp, 0x0E),
sys/bus/pccard/pccard.c
681
pccard_ccr_read(tmp, 0x10),
sys/bus/pccard/pccard.c
682
pccard_ccr_read(tmp, 0x12));
sys/bus/pccard/pccard.c
704
struct pccard_function *tmp;
sys/bus/pccard/pccard.c
734
STAILQ_FOREACH(tmp, &pf->sc->card.pf_head, pf_list) {
sys/bus/pccard/pccard.c
735
if ((tmp->pf_flags & PFF_ENABLED) &&
sys/bus/pccard/pccard.c
736
(pf->ccr_base >= (tmp->ccr_base - tmp->pf_ccr_offset)) &&
sys/bus/pccard/pccard.c
738
(tmp->ccr_base - tmp->pf_ccr_offset +
sys/bus/pccard/pccard.c
739
tmp->pf_ccr_realsize)))
sys/bus/pccard/pccard.c
744
if (tmp == NULL) {
sys/bus/u4b/net/if_axge.c
324
uint8_t link_status, tmp[5];
sys/bus/u4b/net/if_axge.c
372
memcpy(tmp, &axge_bulk_size[0], 5);
sys/bus/u4b/net/if_axge.c
374
memcpy(tmp, &axge_bulk_size[1], 5);
sys/bus/u4b/net/if_axge.c
376
memcpy(tmp, &axge_bulk_size[3], 5);
sys/bus/u4b/net/if_axge.c
381
memcpy(tmp, &axge_bulk_size[2], 5);
sys/bus/u4b/net/if_axge.c
383
memcpy(tmp, &axge_bulk_size[3], 5);
sys/bus/u4b/net/if_axge.c
386
memcpy(tmp, &axge_bulk_size[3], 5);
sys/bus/u4b/net/if_axge.c
390
axge_write_mem(sc, AXGE_ACCESS_MAC, 5, AXGE_RX_BULKIN_QCTRL, tmp, 5);
sys/bus/u4b/usb_device.c
2250
uint8_t no[128], tmp[16], index = 128;
sys/bus/u4b/usb_device.c
2267
ksnprintf(tmp, 16, "%d.", no[index]);
sys/bus/u4b/usb_device.c
2268
if (len <= strlen(phys) + strlen(tmp) + 1)
sys/bus/u4b/usb_device.c
2270
strcat(phys, tmp);
sys/bus/u4b/uvc/uvc_ctrls.c
1078
struct uvc_topo_node *topo_node = NULL, *tmp = NULL;
sys/bus/u4b/uvc/uvc_ctrls.c
1090
STAILQ_FOREACH_SAFE(topo_node, &ctrls->topo_nodes, link, tmp) {
sys/bus/u4b/uvc/uvc_ctrls.c
920
struct uvc_topo_node *topo_node, *tmp;
sys/bus/u4b/uvc/uvc_ctrls.c
935
STAILQ_FOREACH_SAFE(topo_node, &ctrls->topo_nodes, link, tmp) {
sys/bus/u4b/uvc/uvc_drv.c
2455
struct uvc_topo_node *topo_node, *tmp;
sys/bus/u4b/uvc/uvc_drv.c
2459
STAILQ_FOREACH_SAFE(topo_node, &c->topo_nodes, link, tmp) {
sys/bus/u4b/uvc/uvc_drv.c
315
struct uvc_data_request tmp;
sys/bus/u4b/uvc/uvc_drv.c
318
memset(&tmp, 0x0, sizeof(tmp));
sys/bus/u4b/uvc/uvc_drv.c
324
KKASSERT(size <= sizeof(tmp));
sys/bus/u4b/uvc/uvc_drv.c
329
&tmp, size, USB_DEFAULT_TIMEOUT);
sys/bus/u4b/uvc/uvc_drv.c
335
uvc_drv_fixup_req(video, &tmp);
sys/bus/u4b/uvc/uvc_drv.c
336
memcpy(req, &tmp, size);
sys/bus/u4b/uvc/uvc_drv.c
344
char tmp[128];
sys/bus/u4b/uvc/uvc_drv.c
349
memset(tmp, 0, sizeof(tmp));
sys/bus/u4b/uvc/uvc_drv.c
352
ret = copyin(q->data, tmp, q->size);
sys/bus/u4b/uvc/uvc_drv.c
356
tmp, q->size, USB_DEFAULT_TIMEOUT);
sys/bus/u4b/uvc/uvc_drv.c
362
ret = copyout(tmp, q->data, q->size);
sys/bus/u4b/wlan/if_mtw.c
1059
uint32_t blksz, sent, tmp, xferlen;
sys/bus/u4b/wlan/if_mtw.c
1096
mtw_read(sc, MTW_MCU_FW_IDX, &tmp);
sys/bus/u4b/wlan/if_mtw.c
1097
mtw_write(sc, MTW_MCU_FW_IDX, tmp++);
sys/bus/u4b/wlan/if_mtw.c
1116
uint32_t tmp, iofs, dofs;
sys/bus/u4b/wlan/if_mtw.c
1121
mtw_read_cfg(sc, MTW_MCU_DMA_ADDR, &tmp);
sys/bus/u4b/wlan/if_mtw.c
1122
if (tmp == MTW_MCU_READY)
sys/bus/u4b/wlan/if_mtw.c
1234
if ((error = mtw_read_cfg(sc, MTW_MCU_DMA_ADDR, &tmp)) != 0)
sys/bus/u4b/wlan/if_mtw.c
1236
if (tmp & MTW_MCU_READY)
sys/bus/u4b/wlan/if_mtw.c
1278
uint32_t tmp;
sys/bus/u4b/wlan/if_mtw.c
1281
error = mtw_read_region_1(sc, reg, (uint8_t *)&tmp, sizeof tmp);
sys/bus/u4b/wlan/if_mtw.c
1283
*val = le32toh(tmp);
sys/bus/u4b/wlan/if_mtw.c
1358
uint32_t tmp;
sys/bus/u4b/wlan/if_mtw.c
1362
if ((error = mtw_read(sc, MTW_EFUSE_CTRL, &tmp)) != 0)
sys/bus/u4b/wlan/if_mtw.c
1373
tmp &= ~(MTW_EFSROM_MODE_MASK | MTW_EFSROM_AIN_MASK);
sys/bus/u4b/wlan/if_mtw.c
1374
tmp |= (addr & ~0xf) << MTW_EFSROM_AIN_SHIFT | MTW_EFSROM_KICK;
sys/bus/u4b/wlan/if_mtw.c
1375
mtw_write(sc, MTW_EFUSE_CTRL, tmp);
sys/bus/u4b/wlan/if_mtw.c
1377
if ((error = mtw_read(sc, MTW_EFUSE_CTRL, &tmp)) != 0)
sys/bus/u4b/wlan/if_mtw.c
1379
if (!(tmp & MTW_EFSROM_KICK))
sys/bus/u4b/wlan/if_mtw.c
1386
if ((tmp & MTW_EFUSE_AOUT_MASK) == MTW_EFUSE_AOUT_MASK) {
sys/bus/u4b/wlan/if_mtw.c
1392
if ((error = mtw_read(sc, reg, &tmp)) != 0)
sys/bus/u4b/wlan/if_mtw.c
1395
*val = (addr & 2) ? tmp >> 16 : tmp & 0xffff;
sys/bus/u4b/wlan/if_mtw.c
1409
uint32_t tmp;
sys/bus/u4b/wlan/if_mtw.c
1413
if ((error = mtw_read(sc, MTW_BBP_CSR, &tmp)) != 0)
sys/bus/u4b/wlan/if_mtw.c
1415
if (!(tmp & MTW_BBP_CSR_KICK))
sys/bus/u4b/wlan/if_mtw.c
1421
tmp = MTW_BBP_CSR_READ | MTW_BBP_CSR_KICK | reg << 8;
sys/bus/u4b/wlan/if_mtw.c
1422
if ((error = mtw_write(sc, MTW_BBP_CSR, tmp)) != 0)
sys/bus/u4b/wlan/if_mtw.c
1426
if ((error = mtw_read(sc, MTW_BBP_CSR, &tmp)) != 0)
sys/bus/u4b/wlan/if_mtw.c
1428
if (!(tmp & MTW_BBP_CSR_KICK))
sys/bus/u4b/wlan/if_mtw.c
1434
*val = tmp & 0xff;
sys/bus/u4b/wlan/if_mtw.c
1441
uint32_t tmp;
sys/bus/u4b/wlan/if_mtw.c
1445
if ((error = mtw_read(sc, MTW_BBP_CSR, &tmp)) != 0)
sys/bus/u4b/wlan/if_mtw.c
1447
if (!(tmp & MTW_BBP_CSR_KICK))
sys/bus/u4b/wlan/if_mtw.c
1453
tmp = MTW_BBP_CSR_KICK | reg << 8 | val;
sys/bus/u4b/wlan/if_mtw.c
1454
return (mtw_write(sc, MTW_BBP_CSR, tmp));
sys/bus/u4b/wlan/if_mtw.c
1748
uint32_t tmp;
sys/bus/u4b/wlan/if_mtw.c
1750
mtw_read(sc, MTW_BCN_TIME_CFG, &tmp);
sys/bus/u4b/wlan/if_mtw.c
1751
tmp &= ~(MTW_BCN_TX_EN | MTW_TSF_TIMER_EN | MTW_TBTT_TIMER_EN);
sys/bus/u4b/wlan/if_mtw.c
1752
mtw_write(sc, MTW_BCN_TIME_CFG, tmp);
sys/bus/u4b/wlan/if_mtw.c
3597
uint32_t tmp;
sys/bus/u4b/wlan/if_mtw.c
3601
if ((error = mtw_read(sc, MTW_RF_CSR, &tmp)) != 0)
sys/bus/u4b/wlan/if_mtw.c
3603
if (!(tmp & MTW_RF_CSR_KICK))
sys/bus/u4b/wlan/if_mtw.c
3614
tmp = MTW_RF_CSR_WRITE | MTW_RF_CSR_KICK | (bank & 0xf) << shift |
sys/bus/u4b/wlan/if_mtw.c
3616
return (mtw_write(sc, MTW_RF_CSR, tmp));
sys/bus/u4b/wlan/if_mtw.c
3622
uint32_t tmp;
sys/bus/u4b/wlan/if_mtw.c
3626
mtw_read(sc, MTW_TX_BAND_CFG, &tmp);
sys/bus/u4b/wlan/if_mtw.c
3627
tmp &= ~(
sys/bus/u4b/wlan/if_mtw.c
3629
tmp |= (group == 0) ? MTW_TX_BAND_SEL_2G : MTW_TX_BAND_SEL_5G;
sys/bus/u4b/wlan/if_mtw.c
3630
mtw_write(sc, MTW_TX_BAND_CFG, tmp);
sys/bus/u4b/wlan/if_mtw.c
3659
uint32_t tmp;
sys/bus/u4b/wlan/if_mtw.c
3663
if ((error = mtw_read(sc, MTW_RF_CSR, &tmp)) != 0)
sys/bus/u4b/wlan/if_mtw.c
3665
if (!(tmp & MTW_RF_CSR_KICK))
sys/bus/u4b/wlan/if_mtw.c
3676
tmp = MTW_RF_CSR_KICK | (bank & 0xf) << shift | reg << 8;
sys/bus/u4b/wlan/if_mtw.c
3677
if ((error = mtw_write(sc, MTW_RF_CSR, tmp)) != 0)
sys/bus/u4b/wlan/if_mtw.c
3681
if ((error = mtw_read(sc, MTW_RF_CSR, &tmp)) != 0)
sys/bus/u4b/wlan/if_mtw.c
3683
if (!(tmp & MTW_RF_CSR_KICK))
sys/bus/u4b/wlan/if_mtw.c
3689
*val = tmp & 0xff;
sys/bus/u4b/wlan/if_mtw.c
3695
uint32_t tmp;
sys/bus/u4b/wlan/if_mtw.c
3711
mtw_read(sc, MTW_TX_ALC_CFG0, &tmp);
sys/bus/u4b/wlan/if_mtw.c
3712
tmp &= ~0x3f3f;
sys/bus/u4b/wlan/if_mtw.c
3713
tmp |= (txpow1 & 0x3f);
sys/bus/u4b/wlan/if_mtw.c
3714
mtw_write(sc, MTW_TX_ALC_CFG0, tmp);
sys/bus/u4b/wlan/if_mtw.c
3939
uint32_t tmp;
sys/bus/u4b/wlan/if_mtw.c
3941
tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL;
sys/bus/u4b/wlan/if_mtw.c
3943
tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ?
sys/bus/u4b/wlan/if_mtw.c
3948
mtw_write(sc, MTW_CCK_PROT_CFG, tmp);
sys/bus/u4b/wlan/if_mtw.c
3951
tmp |= RT2860_PROT_CTRL_RTS_CTS;
sys/bus/u4b/wlan/if_mtw.c
3953
tmp |= RT2860_PROT_CTRL_CTS;
sys/bus/u4b/wlan/if_mtw.c
3955
mtw_write(sc, MTW_OFDM_PROT_CFG, tmp);
sys/bus/u4b/wlan/if_mtw.c
3982
uint16_t tmp;
sys/bus/u4b/wlan/if_mtw.c
3991
&req, &tmp, 0, &actlen, 1000));
sys/bus/u4b/wlan/if_mtw.c
3999
uint32_t tmp;
sys/bus/u4b/wlan/if_mtw.c
4001
mtw_read(sc, MTW_RX_FILTR_CFG, &tmp);
sys/bus/u4b/wlan/if_mtw.c
4003
tmp |= MTW_DROP_UC_NOME;
sys/bus/u4b/wlan/if_mtw.c
4005
tmp &= ~MTW_DROP_UC_NOME;
sys/bus/u4b/wlan/if_mtw.c
4007
mtw_write(sc, MTW_RX_FILTR_CFG, tmp);
sys/bus/u4b/wlan/if_mtw.c
4031
uint32_t tmp;
sys/bus/u4b/wlan/if_mtw.c
4033
mtw_read(sc, MTW_BCN_TIME_CFG, &tmp);
sys/bus/u4b/wlan/if_mtw.c
4034
tmp &= ~0x1fffff;
sys/bus/u4b/wlan/if_mtw.c
4035
tmp |= vap->iv_bss->ni_intval * 16;
sys/bus/u4b/wlan/if_mtw.c
4036
tmp |= MTW_TSF_TIMER_EN | MTW_TBTT_TIMER_EN;
sys/bus/u4b/wlan/if_mtw.c
4039
tmp |= 1 << MTW_TSF_SYNC_MODE_SHIFT;
sys/bus/u4b/wlan/if_mtw.c
4040
error = mtw_write(sc, MTW_BCN_TIME_CFG, tmp);
sys/bus/u4b/wlan/if_mtw.c
4077
uint32_t tmp;
sys/bus/u4b/wlan/if_mtw.c
4079
mtw_read(sc, MTW_AUTO_RSP_CFG, &tmp);
sys/bus/u4b/wlan/if_mtw.c
4081
tmp |= MTW_CCK_SHORT_EN;
sys/bus/u4b/wlan/if_mtw.c
4083
tmp &= ~MTW_CCK_SHORT_EN;
sys/bus/u4b/wlan/if_mtw.c
4084
mtw_write(sc, MTW_AUTO_RSP_CFG, tmp);
sys/bus/u4b/wlan/if_mtw.c
4139
uint32_t tmp;
sys/bus/u4b/wlan/if_mtw.c
4140
mtw_read(sc, MTW_BKOFF_SLOT_CFG, &tmp);
sys/bus/u4b/wlan/if_mtw.c
4141
tmp &= ~0xff;
sys/bus/u4b/wlan/if_mtw.c
4142
tmp |= IEEE80211_GET_SLOTTIME(ic);
sys/bus/u4b/wlan/if_mtw.c
4143
mtw_write(sc, MTW_BKOFF_SLOT_CFG, tmp);
sys/bus/u4b/wlan/if_mtw.c
4241
uint32_t tmp;
sys/bus/u4b/wlan/if_mtw.c
4245
if ((error = mtw_read(sc, MTW_WPDMA_GLO_CFG, &tmp)) != 0) {
sys/bus/u4b/wlan/if_mtw.c
4248
if ((tmp & (MTW_TX_DMA_BUSY | MTW_RX_DMA_BUSY)) == 0)
sys/bus/u4b/wlan/if_mtw.c
4258
tmp |= MTW_RX_DMA_EN | MTW_TX_DMA_EN | MTW_TX_WB_DDONE;
sys/bus/u4b/wlan/if_mtw.c
4259
mtw_write(sc, MTW_WPDMA_GLO_CFG, tmp);
sys/bus/u4b/wlan/if_mtw.c
4262
tmp = MTW_USB_TX_EN | MTW_USB_RX_EN | MTW_USB_RX_AGG_EN |
sys/bus/u4b/wlan/if_mtw.c
4264
mtw_write(sc, MTW_USB_DMA_CFG, tmp);
sys/bus/u4b/wlan/if_mtw.c
4267
tmp = MTW_DROP_CRC_ERR | MTW_DROP_PHY_ERR;
sys/bus/u4b/wlan/if_mtw.c
4269
tmp |= MTW_DROP_UC_NOME | MTW_DROP_DUPL | MTW_DROP_CTS |
sys/bus/u4b/wlan/if_mtw.c
4273
tmp |= MTW_DROP_RTS | MTW_DROP_PSPOLL;
sys/bus/u4b/wlan/if_mtw.c
4275
mtw_write(sc, MTW_RX_FILTR_CFG, tmp);
sys/bus/u4b/wlan/if_mtw.c
4283
uint32_t tmp;
sys/bus/u4b/wlan/if_mtw.c
4287
mtw_read(sc, MTW_MAC_SYS_CTRL, &tmp);
sys/bus/u4b/wlan/if_mtw.c
4308
mtw_write(sc, MTW_MAC_SYS_CTRL, tmp);
sys/bus/u4b/wlan/if_mtw.c
4373
uint32_t tmp;
sys/bus/u4b/wlan/if_mtw.c
4418
mtw_read(sc, MTW_LDO_CFG0, &tmp);
sys/bus/u4b/wlan/if_mtw.c
4419
tmp &= ~(1 << 4);
sys/bus/u4b/wlan/if_mtw.c
4420
tmp |= (1 << 2);
sys/bus/u4b/wlan/if_mtw.c
4421
mtw_write(sc, MTW_LDO_CFG0, tmp);
sys/bus/u4b/wlan/if_mtw.c
4435
uint32_t tmp;
sys/bus/u4b/wlan/if_mtw.c
4438
mtw_read(sc, MTW_TX_RTS_CFG, &tmp);
sys/bus/u4b/wlan/if_mtw.c
4439
tmp &= ~0xffff00;
sys/bus/u4b/wlan/if_mtw.c
444
uint32_t tmp;
sys/bus/u4b/wlan/if_mtw.c
4440
tmp |= 0x1000 << MTW_RTS_THRES_SHIFT;
sys/bus/u4b/wlan/if_mtw.c
4441
mtw_write(sc, MTW_TX_RTS_CFG, tmp);
sys/bus/u4b/wlan/if_mtw.c
4461
uint32_t tmp;
sys/bus/u4b/wlan/if_mtw.c
4470
if ((error = mtw_read(sc, MTW_WPDMA_GLO_CFG, &tmp)) != 0)
sys/bus/u4b/wlan/if_mtw.c
4472
if ((tmp & (MTW_TX_DMA_BUSY | MTW_RX_DMA_BUSY)) == 0)
sys/bus/u4b/wlan/if_mtw.c
448
mtw_read(sc, MTW_WLAN_CTRL, &tmp);
sys/bus/u4b/wlan/if_mtw.c
4481
tmp &= 0xff0;
sys/bus/u4b/wlan/if_mtw.c
4482
tmp |= MTW_TX_WB_DDONE;
sys/bus/u4b/wlan/if_mtw.c
4483
mtw_write(sc, MTW_WPDMA_GLO_CFG, tmp);
sys/bus/u4b/wlan/if_mtw.c
4499
if ((error = mtw_read(sc, MTW_MAC_STATUS_REG, &tmp)) != 0)
sys/bus/u4b/wlan/if_mtw.c
450
tmp &= ~0xfffff000;
sys/bus/u4b/wlan/if_mtw.c
4501
if (!(tmp & (MTW_RX_STATUS_BUSY | MTW_TX_STATUS_BUSY)))
sys/bus/u4b/wlan/if_mtw.c
4517
mtw_read(sc, MTW_FCE_L2_STUFF, &tmp);
sys/bus/u4b/wlan/if_mtw.c
4518
tmp &= ~MTW_L2S_WR_MPDU_LEN_EN;
sys/bus/u4b/wlan/if_mtw.c
4519
mtw_write(sc, MTW_FCE_L2_STUFF, tmp);
sys/bus/u4b/wlan/if_mtw.c
452
tmp &= ~MTW_WLAN_CLK_EN;
sys/bus/u4b/wlan/if_mtw.c
453
tmp |= MTW_WLAN_EN;
sys/bus/u4b/wlan/if_mtw.c
4534
mtw_read(sc, MTW_US_CYC_CNT, &tmp);
sys/bus/u4b/wlan/if_mtw.c
4535
tmp = (tmp & ~0xff);
sys/bus/u4b/wlan/if_mtw.c
4537
tmp |= 0x1e;
sys/bus/u4b/wlan/if_mtw.c
4538
mtw_write(sc, MTW_US_CYC_CNT, tmp);
sys/bus/u4b/wlan/if_mtw.c
454
mtw_write(sc, MTW_WLAN_CTRL, tmp);
sys/bus/u4b/wlan/if_mtw.c
4562
mtw_read(sc, MTW_CMB_CTRL, &tmp);
sys/bus/u4b/wlan/if_mtw.c
4563
tmp &= ~(1 << 18 | 1 << 14);
sys/bus/u4b/wlan/if_mtw.c
4564
mtw_write(sc, MTW_CMB_CTRL, tmp);
sys/bus/u4b/wlan/if_mtw.c
457
tmp |= MTW_WLAN_CLK_EN;
sys/bus/u4b/wlan/if_mtw.c
4571
mtw_read(sc, MTW_USB_DMA_CFG, &tmp);
sys/bus/u4b/wlan/if_mtw.c
4572
tmp &= ~(MTW_USB_TX_CLEAR | MTW_USB_TXOP_HALT | MTW_USB_RX_WL_DROP);
sys/bus/u4b/wlan/if_mtw.c
4573
mtw_write(sc, MTW_USB_DMA_CFG, tmp);
sys/bus/u4b/wlan/if_mtw.c
459
tmp |= (MTW_WLAN_RESET | MTW_WLAN_RESET_RF);
sys/bus/u4b/wlan/if_mtw.c
461
mtw_write(sc, MTW_WLAN_CTRL, tmp);
sys/bus/u4b/wlan/if_mtw.c
4630
uint32_t tmp;
sys/bus/u4b/wlan/if_mtw.c
464
mtw_read(sc, MTW_OSC_CTRL, &tmp);
sys/bus/u4b/wlan/if_mtw.c
465
tmp |= MTW_OSC_EN;
sys/bus/u4b/wlan/if_mtw.c
4655
mtw_read(sc, MTW_WPDMA_GLO_CFG, &tmp);
sys/bus/u4b/wlan/if_mtw.c
4656
tmp &= ~(MTW_RX_DMA_EN | MTW_TX_DMA_EN);
sys/bus/u4b/wlan/if_mtw.c
4657
mtw_write(sc, MTW_WPDMA_GLO_CFG, tmp);
sys/bus/u4b/wlan/if_mtw.c
466
mtw_write(sc, MTW_OSC_CTRL, tmp);
sys/bus/u4b/wlan/if_mtw.c
4661
if (mtw_read(sc, MTW_WPDMA_GLO_CFG, &tmp) != 0)
sys/bus/u4b/wlan/if_mtw.c
4663
if ((tmp & (MTW_TX_DMA_BUSY | MTW_RX_DMA_BUSY)) == 0)
sys/bus/u4b/wlan/if_mtw.c
467
tmp |= MTW_OSC_CAL_REQ;
sys/bus/u4b/wlan/if_mtw.c
4672
mtw_read(sc, MTW_MAC_SYS_CTRL, &tmp);
sys/bus/u4b/wlan/if_mtw.c
4673
tmp &= ~(MTW_MAC_RX_EN | MTW_MAC_TX_EN);
sys/bus/u4b/wlan/if_mtw.c
4674
mtw_write(sc, MTW_MAC_SYS_CTRL, tmp);
sys/bus/u4b/wlan/if_mtw.c
4677
mtw_read(sc, MTW_TX_RTS_CFG, &tmp);
sys/bus/u4b/wlan/if_mtw.c
4678
tmp &= ~0xff;
sys/bus/u4b/wlan/if_mtw.c
4679
mtw_write(sc, MTW_TX_RTS_CFG, tmp);
sys/bus/u4b/wlan/if_mtw.c
468
mtw_write(sc, MTW_OSC_CTRL, tmp);
sys/bus/u4b/wlan/if_mtw.c
4682
mtw_read(sc, MTW_US_CYC_CNT, &tmp);
sys/bus/u4b/wlan/if_mtw.c
4683
tmp = (tmp & ~0xff);
sys/bus/u4b/wlan/if_mtw.c
4684
mtw_write(sc, MTW_US_CYC_CNT, tmp);
sys/bus/u4b/wlan/if_mtw.c
4687
mtw_read(sc, MTW_PBF_CFG, &tmp);
sys/bus/u4b/wlan/if_mtw.c
4688
tmp &= ~0x3;
sys/bus/u4b/wlan/if_mtw.c
4689
mtw_write(sc, MTW_PBF_CFG, tmp);
sys/bus/u4b/wlan/if_mtw.c
4693
if ((error = mtw_read(sc, MTW_TXRXQ_PCNT, &tmp)) != 0)
sys/bus/u4b/wlan/if_mtw.c
4695
if ((tmp & MTW_TX2Q_PCNT_MASK) == 0)
sys/bus/u4b/wlan/if_mtw.c
470
mtw_read(sc, MTW_WLAN_CTRL, &tmp);
sys/bus/u4b/wlan/if_mtw.c
4703
mtw_read(sc, MTW_SKEY_MODE_0_7, &tmp);
sys/bus/u4b/wlan/if_mtw.c
4704
tmp &= ~(0xf << qid * 4);
sys/bus/u4b/wlan/if_mtw.c
4705
mtw_write(sc, MTW_SKEY_MODE_0_7, tmp);
sys/bus/u4b/wlan/if_mtw.c
471
tmp &= ~(MTW_WLAN_CLK_EN | MTW_WLAN_EN);
sys/bus/u4b/wlan/if_mtw.c
472
mtw_write(sc, MTW_WLAN_CTRL, tmp);
sys/bus/u4b/wlan/if_mtw.c
474
mtw_read(sc, MTW_OSC_CTRL, &tmp);
sys/bus/u4b/wlan/if_mtw.c
475
tmp &= ~MTW_OSC_EN;
sys/bus/u4b/wlan/if_mtw.c
476
mtw_write(sc, MTW_OSC_CTRL, tmp);
sys/bus/u4b/wlan/if_mtw.c
485
uint32_t tmp;
sys/bus/u4b/wlan/if_mtw.c
494
error = usbd_do_request_flags(sc->sc_udev, &sc->sc_lock, &req, &tmp, 0,
sys/bus/u4b/wlan/if_mtw.c
498
*val = le32toh(tmp);
sys/bus/u4b/wlan/if_mtw.c
526
uint32_t tmp;
sys/bus/u4b/wlan/if_mtw.c
589
mtw_usb_dma_read(sc, &tmp);
sys/bus/u4b/wlan/if_mtw.c
590
mtw_usb_dma_write(sc, tmp | (MTW_USB_RX_EN | MTW_USB_TX_EN));
sys/bus/u4b/wlan/if_mtw.c
594
if ((error = mtw_read(sc, MTW_MAC_VER_ID, &tmp)) != 0)
sys/bus/u4b/wlan/if_mtw.c
596
if (tmp != 0 && tmp != 0xffffffff)
sys/bus/u4b/wlan/if_mtw.c
605
sc->mac_ver = tmp >> 16;
sys/bus/u4b/wlan/if_mtw.c
606
sc->mac_rev = tmp & 0xffff;
sys/bus/u4b/wlan/if_rum.c
1820
uint32_t tmp = htole32(val);
sys/bus/u4b/wlan/if_rum.c
1822
return (rum_write_multi(sc, reg, &tmp, sizeof tmp));
sys/bus/u4b/wlan/if_rum.c
1891
uint32_t tmp;
sys/bus/u4b/wlan/if_rum.c
1900
tmp = RT2573_BBP_BUSY | (reg & 0x7f) << 8 | val;
sys/bus/u4b/wlan/if_rum.c
1901
rum_write(sc, RT2573_PHY_CSR3, tmp);
sys/bus/u4b/wlan/if_rum.c
1935
uint32_t tmp;
sys/bus/u4b/wlan/if_rum.c
1949
tmp = RT2573_RF_BUSY | RT2573_RF_20BIT | (val & 0xfffff) << 2 |
sys/bus/u4b/wlan/if_rum.c
1951
rum_write(sc, RT2573_PHY_CSR4, tmp);
sys/bus/u4b/wlan/if_rum.c
1963
uint32_t tmp;
sys/bus/u4b/wlan/if_rum.c
1971
tmp = rum_read(sc, RT2573_TXRX_CSR0);
sys/bus/u4b/wlan/if_rum.c
1972
rum_write(sc, RT2573_TXRX_CSR0, tmp | RT2573_DISABLE_RX);
sys/bus/u4b/wlan/if_rum.c
1977
rum_write(sc, RT2573_TXRX_CSR0, tmp);
sys/bus/u4b/wlan/if_rum.c
2169
uint32_t tmp;
sys/bus/u4b/wlan/if_rum.c
2181
tmp = rum_read(sc, RT2573_TXRX_CSR9) & 0xff000000;
sys/bus/u4b/wlan/if_rum.c
2185
tmp |= bintval * 16;
sys/bus/u4b/wlan/if_rum.c
2186
tmp |= RT2573_TSF_TIMER_EN | RT2573_TBTT_TIMER_EN;
sys/bus/u4b/wlan/if_rum.c
2194
tmp |= RT2573_TSF_SYNC_MODE(RT2573_TSF_SYNC_MODE_STA);
sys/bus/u4b/wlan/if_rum.c
2201
tmp |= RT2573_TSF_SYNC_MODE(RT2573_TSF_SYNC_MODE_IBSS);
sys/bus/u4b/wlan/if_rum.c
2202
tmp |= RT2573_BCN_TX_EN;
sys/bus/u4b/wlan/if_rum.c
2206
tmp |= RT2573_TSF_SYNC_MODE(RT2573_TSF_SYNC_MODE_HOSTAP);
sys/bus/u4b/wlan/if_rum.c
2207
tmp |= RT2573_BCN_TX_EN;
sys/bus/u4b/wlan/if_rum.c
2216
if (rum_write(sc, RT2573_TXRX_CSR9, tmp) != 0)
sys/bus/u4b/wlan/if_rum.c
2526
uint32_t tmp;
sys/bus/u4b/wlan/if_rum.c
2580
tmp = rum_read(sc, RT2573_TXRX_CSR0) & 0xffff;
sys/bus/u4b/wlan/if_rum.c
2582
tmp |= RT2573_DROP_PHY_ERROR | RT2573_DROP_CRC_ERROR;
sys/bus/u4b/wlan/if_rum.c
2584
tmp |= RT2573_DROP_CTL | RT2573_DROP_VER_ERROR |
sys/bus/u4b/wlan/if_rum.c
2587
tmp |= RT2573_DROP_TODS;
sys/bus/u4b/wlan/if_rum.c
2589
tmp |= RT2573_DROP_NOT_TO_ME;
sys/bus/u4b/wlan/if_rum.c
2591
rum_write(sc, RT2573_TXRX_CSR0, tmp);
sys/bus/u4b/wlan/if_rum.c
474
uint32_t tmp;
sys/bus/u4b/wlan/if_rum.c
499
if ((tmp = rum_read(sc, RT2573_MAC_CSR0)) != 0)
sys/bus/u4b/wlan/if_rum.c
514
tmp, rum_get_rf(sc->rf_rev));
sys/bus/u4b/wlan/if_run.c
1118
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
1189
if ((error = run_read(sc, RT2860_SYS_CTRL, &tmp)) != 0)
sys/bus/u4b/wlan/if_run.c
1191
if (tmp & RT2860_MCU_READY)
sys/bus/u4b/wlan/if_run.c
1247
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
1250
error = run_read_region_1(sc, reg, (uint8_t *)&tmp, sizeof tmp);
sys/bus/u4b/wlan/if_run.c
1252
*val = le32toh(tmp);
sys/bus/u4b/wlan/if_run.c
1355
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
1359
if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0)
sys/bus/u4b/wlan/if_run.c
1371
tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK);
sys/bus/u4b/wlan/if_run.c
1372
tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK;
sys/bus/u4b/wlan/if_run.c
1373
run_write(sc, RT3070_EFUSE_CTRL, tmp);
sys/bus/u4b/wlan/if_run.c
1375
if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0)
sys/bus/u4b/wlan/if_run.c
1377
if (!(tmp & RT3070_EFSROM_KICK))
sys/bus/u4b/wlan/if_run.c
1384
if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) {
sys/bus/u4b/wlan/if_run.c
1390
if ((error = run_read(sc, reg, &tmp)) != 0)
sys/bus/u4b/wlan/if_run.c
1393
tmp >>= (8 * (addr & 0x3));
sys/bus/u4b/wlan/if_run.c
1394
*val = (addr & 1) ? tmp >> 16 : tmp & 0xffff;
sys/bus/u4b/wlan/if_run.c
1410
uint16_t tmp;
sys/bus/u4b/wlan/if_run.c
1418
USETW(req.wLength, sizeof(tmp));
sys/bus/u4b/wlan/if_run.c
1420
error = usbd_do_request(sc->sc_udev, &sc->sc_lock, &req, &tmp);
sys/bus/u4b/wlan/if_run.c
1422
*val = le16toh(tmp);
sys/bus/u4b/wlan/if_run.c
1438
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
1442
if ((error = run_read(sc, RT2860_RF_CSR_CFG0, &tmp)) != 0)
sys/bus/u4b/wlan/if_run.c
1444
if (!(tmp & RT2860_RF_REG_CTRL))
sys/bus/u4b/wlan/if_run.c
1456
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
1461
if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0)
sys/bus/u4b/wlan/if_run.c
1463
if (!(tmp & RT3070_RF_KICK))
sys/bus/u4b/wlan/if_run.c
1469
tmp = RT3070_RF_KICK | reg << 8;
sys/bus/u4b/wlan/if_run.c
1470
if ((error = run_write(sc, RT3070_RF_CSR_CFG, tmp)) != 0)
sys/bus/u4b/wlan/if_run.c
1474
if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0)
sys/bus/u4b/wlan/if_run.c
1476
if (!(tmp & RT3070_RF_KICK))
sys/bus/u4b/wlan/if_run.c
1482
*val = tmp & 0xff;
sys/bus/u4b/wlan/if_run.c
1489
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
1493
if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0)
sys/bus/u4b/wlan/if_run.c
1495
if (!(tmp & RT3070_RF_KICK))
sys/bus/u4b/wlan/if_run.c
1501
tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val;
sys/bus/u4b/wlan/if_run.c
1502
return (run_write(sc, RT3070_RF_CSR_CFG, tmp));
sys/bus/u4b/wlan/if_run.c
1508
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
1512
if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0)
sys/bus/u4b/wlan/if_run.c
1514
if (!(tmp & RT2860_BBP_CSR_KICK))
sys/bus/u4b/wlan/if_run.c
1520
tmp = RT2860_BBP_CSR_READ | RT2860_BBP_CSR_KICK | reg << 8;
sys/bus/u4b/wlan/if_run.c
1521
if ((error = run_write(sc, RT2860_BBP_CSR_CFG, tmp)) != 0)
sys/bus/u4b/wlan/if_run.c
1525
if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0)
sys/bus/u4b/wlan/if_run.c
1527
if (!(tmp & RT2860_BBP_CSR_KICK))
sys/bus/u4b/wlan/if_run.c
1533
*val = tmp & 0xff;
sys/bus/u4b/wlan/if_run.c
1540
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
1544
if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0)
sys/bus/u4b/wlan/if_run.c
1546
if (!(tmp & RT2860_BBP_CSR_KICK))
sys/bus/u4b/wlan/if_run.c
1552
tmp = RT2860_BBP_CSR_KICK | reg << 8 | val;
sys/bus/u4b/wlan/if_run.c
1553
return (run_write(sc, RT2860_BBP_CSR_CFG, tmp));
sys/bus/u4b/wlan/if_run.c
1562
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
1566
if ((error = run_read(sc, RT2860_H2M_MAILBOX, &tmp)) != 0)
sys/bus/u4b/wlan/if_run.c
1568
if (!(tmp & RT2860_H2M_BUSY))
sys/bus/u4b/wlan/if_run.c
1574
tmp = RT2860_H2M_BUSY | RT2860_TOKEN_NO_INTR << 16 | arg;
sys/bus/u4b/wlan/if_run.c
1575
if ((error = run_write(sc, RT2860_H2M_MAILBOX, tmp)) == 0)
sys/bus/u4b/wlan/if_run.c
1746
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
1753
run_read(sc, RT3070_EFUSE_CTRL, &tmp);
sys/bus/u4b/wlan/if_run.c
1754
DPRINTF("EFUSE_CTRL=0x%08x\n", tmp);
sys/bus/u4b/wlan/if_run.c
1755
if ((tmp & RT3070_SEL_EFUSE) || sc->mac_ver == 0x3593)
sys/bus/u4b/wlan/if_run.c
2057
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
2091
run_read(sc, RT2860_BCN_TIME_CFG, &tmp);
sys/bus/u4b/wlan/if_run.c
2093
tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN |
sys/bus/u4b/wlan/if_run.c
3904
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
3983
run_read(sc, RT2860_TX_BAND_CFG, &tmp);
sys/bus/u4b/wlan/if_run.c
3984
tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P);
sys/bus/u4b/wlan/if_run.c
3985
tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P;
sys/bus/u4b/wlan/if_run.c
3986
run_write(sc, RT2860_TX_BAND_CFG, tmp);
sys/bus/u4b/wlan/if_run.c
3989
tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN;
sys/bus/u4b/wlan/if_run.c
3991
tmp |= 1 << 29 | 1 << 28;
sys/bus/u4b/wlan/if_run.c
3993
tmp |= RT2860_LNA_PE1_EN;
sys/bus/u4b/wlan/if_run.c
3995
tmp |= RT2860_PA_PE_G0_EN;
sys/bus/u4b/wlan/if_run.c
3997
tmp |= RT2860_PA_PE_G1_EN;
sys/bus/u4b/wlan/if_run.c
4000
tmp |= 1 << 25;
sys/bus/u4b/wlan/if_run.c
4003
tmp |= RT2860_PA_PE_A0_EN;
sys/bus/u4b/wlan/if_run.c
4005
tmp |= RT2860_PA_PE_A1_EN;
sys/bus/u4b/wlan/if_run.c
4009
run_write(sc, RT2860_TX_PIN_CFG, tmp);
sys/bus/u4b/wlan/if_run.c
4012
run_write(sc, RT2860_TX_PIN_CFG, tmp);
sys/bus/u4b/wlan/if_run.c
4020
run_read(sc, RT2860_GPIO_CTRL, &tmp);
sys/bus/u4b/wlan/if_run.c
4021
tmp &= ~0x01010000;
sys/bus/u4b/wlan/if_run.c
4023
tmp |= 0x00010000;
sys/bus/u4b/wlan/if_run.c
4024
tmp = (tmp & ~0x00009090) | 0x00000090;
sys/bus/u4b/wlan/if_run.c
4025
run_write(sc, RT2860_GPIO_CTRL, tmp);
sys/bus/u4b/wlan/if_run.c
4185
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
4318
run_read(sc, RT2860_GPIO_CTRL, &tmp);
sys/bus/u4b/wlan/if_run.c
4319
tmp &= ~0x8080;
sys/bus/u4b/wlan/if_run.c
4321
tmp |= 0x80;
sys/bus/u4b/wlan/if_run.c
4322
run_write(sc, RT2860_GPIO_CTRL, tmp);
sys/bus/u4b/wlan/if_run.c
4605
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
4610
run_read(sc, RT5592_DEBUG_INDEX, &tmp);
sys/bus/u4b/wlan/if_run.c
4611
freqs = (tmp & RT5592_SEL_XTAL) ?
sys/bus/u4b/wlan/if_run.c
4621
run_read(sc, RT3070_LDO_CFG0, &tmp);
sys/bus/u4b/wlan/if_run.c
4622
tmp &= ~0x1c000000;
sys/bus/u4b/wlan/if_run.c
4624
tmp |= 0x14000000;
sys/bus/u4b/wlan/if_run.c
4625
run_write(sc, RT3070_LDO_CFG0, tmp);
sys/bus/u4b/wlan/if_run.c
4741
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
4750
run_read(sc, RT2860_GPIO_CTRL, &tmp);
sys/bus/u4b/wlan/if_run.c
4751
run_write(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08);
sys/bus/u4b/wlan/if_run.c
4759
run_read(sc, RT2860_GPIO_CTRL, &tmp);
sys/bus/u4b/wlan/if_run.c
4760
run_write(sc, RT2860_GPIO_CTRL, tmp & ~0x0808);
sys/bus/u4b/wlan/if_run.c
4826
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
4831
run_read(sc, RT2860_BCN_TIME_CFG, &tmp);
sys/bus/u4b/wlan/if_run.c
4833
tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN |
sys/bus/u4b/wlan/if_run.c
4972
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
4974
tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL;
sys/bus/u4b/wlan/if_run.c
4976
tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ?
sys/bus/u4b/wlan/if_run.c
4981
run_write(sc, RT2860_CCK_PROT_CFG, tmp);
sys/bus/u4b/wlan/if_run.c
4984
tmp |= RT2860_PROT_CTRL_RTS_CTS;
sys/bus/u4b/wlan/if_run.c
4986
tmp |= RT2860_PROT_CTRL_CTS;
sys/bus/u4b/wlan/if_run.c
4988
run_write(sc, RT2860_OFDM_PROT_CFG, tmp);
sys/bus/u4b/wlan/if_run.c
5013
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
5022
run_read(sc, RT2860_DEBUG, &tmp);
sys/bus/u4b/wlan/if_run.c
5023
DPRINTFN(3, "debug reg %08x\n", tmp);
sys/bus/u4b/wlan/if_run.c
5024
if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) {
sys/bus/u4b/wlan/if_run.c
5036
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
5038
run_read(sc, RT2860_RX_FILTR_CFG, &tmp);
sys/bus/u4b/wlan/if_run.c
5040
tmp |= RT2860_DROP_UC_NOME;
sys/bus/u4b/wlan/if_run.c
5042
tmp &= ~RT2860_DROP_UC_NOME;
sys/bus/u4b/wlan/if_run.c
5044
run_write(sc, RT2860_RX_FILTR_CFG, tmp);
sys/bus/u4b/wlan/if_run.c
5068
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
5073
run_read(sc, RT2860_BCN_TIME_CFG, &tmp);
sys/bus/u4b/wlan/if_run.c
5074
tmp &= ~0x1fffff;
sys/bus/u4b/wlan/if_run.c
5075
tmp |= vap->iv_bss->ni_intval * 16;
sys/bus/u4b/wlan/if_run.c
5076
tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN;
sys/bus/u4b/wlan/if_run.c
5083
tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT;
sys/bus/u4b/wlan/if_run.c
5085
tmp |= RT2860_BCN_TX_EN;
sys/bus/u4b/wlan/if_run.c
5090
tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT;
sys/bus/u4b/wlan/if_run.c
5093
tmp |= RT2860_BCN_TX_EN;
sys/bus/u4b/wlan/if_run.c
5095
tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT;
sys/bus/u4b/wlan/if_run.c
5101
run_write(sc, RT2860_BCN_TIME_CFG, tmp);
sys/bus/u4b/wlan/if_run.c
5107
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
5109
if (run_read(sc, RT2860_BCN_TIME_CFG, &tmp) == 0) {
sys/bus/u4b/wlan/if_run.c
5110
tmp &= ~(RT2860_BCN_TX_EN | RT2860_TBTT_TIMER_EN);
sys/bus/u4b/wlan/if_run.c
5111
tmp |= RT2860_TSF_TIMER_EN;
sys/bus/u4b/wlan/if_run.c
5112
run_write(sc, RT2860_BCN_TIME_CFG, tmp);
sys/bus/u4b/wlan/if_run.c
5151
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
5153
run_read(sc, RT2860_AUTO_RSP_CFG, &tmp);
sys/bus/u4b/wlan/if_run.c
5155
tmp |= RT2860_CCK_SHORT_EN;
sys/bus/u4b/wlan/if_run.c
5157
tmp &= ~RT2860_CCK_SHORT_EN;
sys/bus/u4b/wlan/if_run.c
5158
run_write(sc, RT2860_AUTO_RSP_CFG, tmp);
sys/bus/u4b/wlan/if_run.c
5221
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
5223
run_read(sc, RT2860_BKOFF_SLOT_CFG, &tmp);
sys/bus/u4b/wlan/if_run.c
5224
tmp &= ~0xff;
sys/bus/u4b/wlan/if_run.c
5225
tmp |= IEEE80211_GET_SLOTTIME(ic);
sys/bus/u4b/wlan/if_run.c
5226
run_write(sc, RT2860_BKOFF_SLOT_CFG, tmp);
sys/bus/u4b/wlan/if_run.c
5369
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
5398
run_read(sc, RT3070_LDO_CFG0, &tmp);
sys/bus/u4b/wlan/if_run.c
5399
tmp = (tmp & ~0x0f000000) | 0x0d000000;
sys/bus/u4b/wlan/if_run.c
5400
run_write(sc, RT3070_LDO_CFG0, tmp);
sys/bus/u4b/wlan/if_run.c
5407
run_read(sc, RT3070_LDO_CFG0, &tmp);
sys/bus/u4b/wlan/if_run.c
5408
tmp &= ~0x1f000000;
sys/bus/u4b/wlan/if_run.c
5410
tmp |= 0x0d000000; /* 1.3V */
sys/bus/u4b/wlan/if_run.c
5412
tmp |= 0x01000000; /* 1.2V */
sys/bus/u4b/wlan/if_run.c
5413
run_write(sc, RT3070_LDO_CFG0, tmp);
sys/bus/u4b/wlan/if_run.c
5416
run_read(sc, RT3070_GPIO_SWITCH, &tmp);
sys/bus/u4b/wlan/if_run.c
5417
run_write(sc, RT3070_GPIO_SWITCH, tmp & ~0x20);
sys/bus/u4b/wlan/if_run.c
5424
run_read(sc, RT3070_LDO_CFG0, &tmp);
sys/bus/u4b/wlan/if_run.c
5425
tmp = (tmp & ~0x1f000000) | 0x0d000000;
sys/bus/u4b/wlan/if_run.c
5426
run_write(sc, RT3070_LDO_CFG0, tmp);
sys/bus/u4b/wlan/if_run.c
5431
tmp = (tmp & ~0x1f000000) | 0x01000000;
sys/bus/u4b/wlan/if_run.c
5432
run_write(sc, RT3070_LDO_CFG0, tmp);
sys/bus/u4b/wlan/if_run.c
5467
run_read(sc, RT3070_OPT_14, &tmp);
sys/bus/u4b/wlan/if_run.c
5468
run_write(sc, RT3070_OPT_14, tmp | 1);
sys/bus/u4b/wlan/if_run.c
5513
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
5518
run_read(sc, RT3070_GPIO_SWITCH, &tmp);
sys/bus/u4b/wlan/if_run.c
5519
tmp &= ~(1 << 4 | 1 << 7);
sys/bus/u4b/wlan/if_run.c
5520
run_write(sc, RT3070_GPIO_SWITCH, tmp);
sys/bus/u4b/wlan/if_run.c
5541
run_read(sc, RT3070_LDO_CFG0, &tmp);
sys/bus/u4b/wlan/if_run.c
5542
tmp = (tmp & ~0x1f000000) | 0x0d000000;
sys/bus/u4b/wlan/if_run.c
5543
run_write(sc, RT3070_LDO_CFG0, tmp);
sys/bus/u4b/wlan/if_run.c
5545
tmp = (tmp & ~0x1f000000) | 0x01000000;
sys/bus/u4b/wlan/if_run.c
5546
run_write(sc, RT3070_LDO_CFG0, tmp);
sys/bus/u4b/wlan/if_run.c
5555
run_read(sc, RT3070_OPT_14, &tmp);
sys/bus/u4b/wlan/if_run.c
5556
run_write(sc, RT3070_OPT_14, tmp | 1);
sys/bus/u4b/wlan/if_run.c
5562
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
5619
run_read(sc, RT3070_OPT_14, &tmp);
sys/bus/u4b/wlan/if_run.c
5620
run_write(sc, RT3070_OPT_14, tmp | 1);
sys/bus/u4b/wlan/if_run.c
5888
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
5893
if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0)
sys/bus/u4b/wlan/if_run.c
5895
if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
sys/bus/u4b/wlan/if_run.c
5904
tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | RT2860_TX_WB_DDONE;
sys/bus/u4b/wlan/if_run.c
5905
run_write(sc, RT2860_WPDMA_GLO_CFG, tmp);
sys/bus/u4b/wlan/if_run.c
5908
tmp = RT2860_USB_TX_EN | RT2860_USB_RX_EN | RT2860_USB_RX_AGG_EN |
sys/bus/u4b/wlan/if_run.c
5910
run_write(sc, RT2860_USB_DMA_CFG, tmp);
sys/bus/u4b/wlan/if_run.c
5913
tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR;
sys/bus/u4b/wlan/if_run.c
5915
tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL |
sys/bus/u4b/wlan/if_run.c
5920
tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL;
sys/bus/u4b/wlan/if_run.c
5922
run_write(sc, RT2860_RX_FILTR_CFG, tmp);
sys/bus/u4b/wlan/if_run.c
5933
uint8_t rf, tmp;
sys/bus/u4b/wlan/if_run.c
5936
tmp = rf;
sys/bus/u4b/wlan/if_run.c
5940
if (tmp != rf)
sys/bus/u4b/wlan/if_run.c
5941
run_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf);
sys/bus/u4b/wlan/if_run.c
5949
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
5966
if (run_read(sc, RT2860_ASIC_VER_ID, &tmp) != 0)
sys/bus/u4b/wlan/if_run.c
5968
if (tmp != 0 && tmp != 0xffffffff)
sys/bus/u4b/wlan/if_run.c
5981
if (run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp) != 0)
sys/bus/u4b/wlan/if_run.c
5983
if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
sys/bus/u4b/wlan/if_run.c
5991
tmp &= 0xff0;
sys/bus/u4b/wlan/if_run.c
5992
tmp |= RT2860_TX_WB_DDONE;
sys/bus/u4b/wlan/if_run.c
5993
run_write(sc, RT2860_WPDMA_GLO_CFG, tmp);
sys/bus/u4b/wlan/if_run.c
5996
run_read(sc, RT2860_SYS_CTRL, &tmp);
sys/bus/u4b/wlan/if_run.c
5997
run_write(sc, RT2860_SYS_CTRL, tmp & ~RT2860_PME_OEN);
sys/bus/u4b/wlan/if_run.c
6047
if (run_read(sc, RT2860_MAC_STATUS_REG, &tmp) != 0)
sys/bus/u4b/wlan/if_run.c
6049
if (!(tmp & (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY)))
sys/bus/u4b/wlan/if_run.c
6067
run_read(sc, RT2860_BCN_TIME_CFG, &tmp);
sys/bus/u4b/wlan/if_run.c
6068
tmp &= ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN |
sys/bus/u4b/wlan/if_run.c
6070
run_write(sc, RT2860_BCN_TIME_CFG, tmp);
sys/bus/u4b/wlan/if_run.c
6085
run_read(sc, RT2860_US_CYC_CNT, &tmp);
sys/bus/u4b/wlan/if_run.c
6086
tmp = (tmp & ~0xff) | 0x1e;
sys/bus/u4b/wlan/if_run.c
6087
run_write(sc, RT2860_US_CYC_CNT, tmp);
sys/bus/u4b/wlan/if_run.c
6172
uint32_t tmp;
sys/bus/u4b/wlan/if_run.c
6201
if (run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp) != 0)
sys/bus/u4b/wlan/if_run.c
6203
tmp &= ~(RT2860_RX_DMA_EN | RT2860_TX_DMA_EN);
sys/bus/u4b/wlan/if_run.c
6204
run_write(sc, RT2860_WPDMA_GLO_CFG, tmp);
sys/bus/u4b/wlan/if_run.c
6207
if (run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp) != 0)
sys/bus/u4b/wlan/if_run.c
6209
if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
sys/bus/u4b/wlan/if_run.c
6219
run_read(sc, RT2860_MAC_SYS_CTRL, &tmp);
sys/bus/u4b/wlan/if_run.c
6220
tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
sys/bus/u4b/wlan/if_run.c
6221
run_write(sc, RT2860_MAC_SYS_CTRL, tmp);
sys/bus/u4b/wlan/if_run.c
6225
if (run_read(sc, RT2860_TXRXQ_PCNT, &tmp) != 0) {
sys/bus/u4b/wlan/if_run.c
6229
if ((tmp & RT2860_TX2Q_PCNT_MASK) == 0) {
sys/crypto/camellia/camellia.c
1276
uint32_t tmp[4];
sys/crypto/camellia/camellia.c
1278
tmp[0] = GETU32(plaintext);
sys/crypto/camellia/camellia.c
1279
tmp[1] = GETU32(plaintext + 4);
sys/crypto/camellia/camellia.c
1280
tmp[2] = GETU32(plaintext + 8);
sys/crypto/camellia/camellia.c
1281
tmp[3] = GETU32(plaintext + 12);
sys/crypto/camellia/camellia.c
1285
camellia_encrypt128(subkey, tmp);
sys/crypto/camellia/camellia.c
1290
camellia_encrypt256(subkey, tmp);
sys/crypto/camellia/camellia.c
1296
PUTU32(ciphertext, tmp[0]);
sys/crypto/camellia/camellia.c
1297
PUTU32(ciphertext+4, tmp[1]);
sys/crypto/camellia/camellia.c
1298
PUTU32(ciphertext+8, tmp[2]);
sys/crypto/camellia/camellia.c
1299
PUTU32(ciphertext+12, tmp[3]);
sys/crypto/camellia/camellia.c
1308
uint32_t tmp[4];
sys/crypto/camellia/camellia.c
1310
tmp[0] = GETU32(ciphertext);
sys/crypto/camellia/camellia.c
1311
tmp[1] = GETU32(ciphertext + 4);
sys/crypto/camellia/camellia.c
1312
tmp[2] = GETU32(ciphertext + 8);
sys/crypto/camellia/camellia.c
1313
tmp[3] = GETU32(ciphertext + 12);
sys/crypto/camellia/camellia.c
1317
camellia_decrypt128(subkey, tmp);
sys/crypto/camellia/camellia.c
1322
camellia_decrypt256(subkey, tmp);
sys/crypto/camellia/camellia.c
1328
PUTU32(plaintext, tmp[0]);
sys/crypto/camellia/camellia.c
1329
PUTU32(plaintext+4, tmp[1]);
sys/crypto/camellia/camellia.c
1330
PUTU32(plaintext+8, tmp[2]);
sys/crypto/camellia/camellia.c
1331
PUTU32(plaintext+12, tmp[3]);
sys/crypto/chacha20/chacha.c
116
u8 tmp[64];
sys/crypto/chacha20/chacha.c
141
for (i = 0;i < bytes;++i) tmp[i] = m[i];
sys/crypto/chacha20/chacha.c
142
m = tmp;
sys/crypto/chacha20/chacha.c
147
c = tmp;
sys/crypto/des/des_locl.h
127
#define LOAD_DATA(R,S,u,t,E0,E1,tmp) \
sys/crypto/sha1.c
139
tmp = S(5, a) + F0(b, c, d) + e + W(s) + K(t);
sys/crypto/sha1.c
140
e = d; d = c; c = S(30, b); b = a; a = tmp;
sys/crypto/sha1.c
145
tmp = S(5, a) + F1(b, c, d) + e + W(s) + K(t);
sys/crypto/sha1.c
146
e = d; d = c; c = S(30, b); b = a; a = tmp;
sys/crypto/sha1.c
151
tmp = S(5, a) + F2(b, c, d) + e + W(s) + K(t);
sys/crypto/sha1.c
152
e = d; d = c; c = S(30, b); b = a; a = tmp;
sys/crypto/sha1.c
157
tmp = S(5, a) + F3(b, c, d) + e + W(s) + K(t);
sys/crypto/sha1.c
158
e = d; d = c; c = S(30, b); b = a; a = tmp;
sys/crypto/sha1.c
93
u_int32_t tmp;
sys/crypto/sha2/sha2.c
148
sha2_word32 tmp = (w); \
sys/crypto/sha2/sha2.c
149
tmp = (tmp >> 16) | (tmp << 16); \
sys/crypto/sha2/sha2.c
150
(x) = ((tmp & 0xff00ff00UL) >> 8) | ((tmp & 0x00ff00ffUL) << 8); \
sys/crypto/sha2/sha2.c
153
sha2_word64 tmp = (w); \
sys/crypto/sha2/sha2.c
154
tmp = (tmp >> 32) | (tmp << 32); \
sys/crypto/sha2/sha2.c
155
tmp = ((tmp & 0xff00ff00ff00ff00ULL) >> 8) | \
sys/crypto/sha2/sha2.c
156
((tmp & 0x00ff00ff00ff00ffULL) << 8); \
sys/crypto/sha2/sha2.c
157
(x) = ((tmp & 0xffff0000ffff0000ULL) >> 16) | \
sys/crypto/sha2/sha2.c
158
((tmp & 0x0000ffff0000ffffULL) << 16); \
sys/ddb/db_sym.c
86
static char tmp[256];
sys/ddb/db_sym.c
89
ksnprintf(tmp, sizeof(tmp), "%s:%s", symtabname, symname);
sys/ddb/db_sym.c
90
return tmp;
sys/dev/acpica/acpi_dock/acpi_dock.c
453
ACPI_HANDLE h, tmp;
sys/dev/acpica/acpi_dock/acpi_dock.c
457
ACPI_FAILURE(AcpiGetHandle(h, "_DCK", &tmp)))
sys/dev/acpica/acpi_package.c
59
UINT64 tmp;
sys/dev/acpica/acpi_package.c
62
error = acpi_PkgInt(res, idx, &tmp);
sys/dev/acpica/acpi_package.c
64
*dst = (uint32_t)tmp;
sys/dev/acpica/acpi_pci_link.c
272
ACPI_RESOURCE *tmp;
sys/dev/acpica/acpi_pci_link.c
326
tmp = &link->l_prs_template;
sys/dev/acpica/acpi_pci_link.c
328
bcopy(res, tmp, ACPI_RS_SIZE(tmp->Data.ExtendedIrq));
sys/dev/acpica/acpi_pci_link.c
334
bzero(&tmp->Data.ExtendedIrq.ResourceSource,
sys/dev/acpica/acpi_pci_link.c
335
sizeof(tmp->Data.ExtendedIrq.ResourceSource));
sys/dev/acpica/acpi_pci_link.c
336
tmp->Length = ACPI_RS_SIZE(tmp->Data.ExtendedIrq);
sys/dev/acpica/acpi_pci_link.c
342
bcopy(res, tmp, ACPI_RS_SIZE(tmp->Data.Irq));
sys/dev/acpica/acpi_wmi/acpi_wmi.c
292
struct wmi_info *winfo, *tmp;
sys/dev/acpica/acpi_wmi/acpi_wmi.c
307
TAILQ_FOREACH_MUTABLE(winfo, &sc->wmi_info_list, wmi_list, tmp) {
sys/dev/apple/smc/smc_sysctl.c
645
char tmp[3] = { hexbuf[i*2], hexbuf[i*2+1], 0 };
sys/dev/apple/smc/smc_sysctl.c
647
if (ksscanf(tmp, "%02x", &val) == 1) {
sys/dev/disk/dm/delay/dm_target_delay.c
132
int tmp;
sys/dev/disk/dm/delay/dm_target_delay.c
141
tmp = atoi64(argv[2]);
sys/dev/disk/dm/delay/dm_target_delay.c
142
di->delay = tmp * hz / 1000;
sys/dev/disk/dm/dm_ioctl.c
642
uint64_t ret, tmp;
sys/dev/disk/dm/dm_ioctl.c
649
if (prop_array_get_uint64(array, i, &tmp) == true)
sys/dev/disk/dm/dm_ioctl.c
650
if (ret == tmp)
sys/dev/disk/iscsi/initiator/iscsivar.h
546
pduq_t *pq, *tmp;
sys/dev/disk/iscsi/initiator/iscsivar.h
551
TAILQ_FOREACH_MUTABLE(pq, &sp->hld, pq_link, tmp) {
sys/dev/disk/isp/isp.c
2891
fcportdb_t *lp, tmp;
sys/dev/disk/isp/isp.c
3018
MAKE_WWN_FROM_NODE_NAME(tmp.node_wwn, pdb.nodename);
sys/dev/disk/isp/isp.c
3019
MAKE_WWN_FROM_NODE_NAME(tmp.port_wwn, pdb.portname);
sys/dev/disk/isp/isp.c
3020
tmp.roles = (pdb.s3_role & SVC3_ROLE_MASK) >> SVC3_ROLE_SHIFT;
sys/dev/disk/isp/isp.c
3021
tmp.portid = pdb.portid;
sys/dev/disk/isp/isp.c
3022
tmp.handle = pdb.handle;
sys/dev/disk/isp/isp.c
3029
if (tmp.node_wwn == 0 || tmp.port_wwn == 0 || tmp.portid == 0) {
sys/dev/disk/isp/isp.c
3031
a = (tmp.node_wwn == 0);
sys/dev/disk/isp/isp.c
3032
b = (tmp.port_wwn == 0);
sys/dev/disk/isp/isp.c
3033
c = (tmp.portid == 0);
sys/dev/disk/isp/isp.c
3035
tmp.node_wwn =
sys/dev/disk/isp/isp.c
3037
tmp.port_wwn =
sys/dev/disk/isp/isp.c
3039
if (tmp.node_wwn && tmp.port_wwn) {
sys/dev/disk/isp/isp.c
3063
if (lp->node_wwn != tmp.node_wwn) {
sys/dev/disk/isp/isp.c
3066
if (lp->port_wwn != tmp.port_wwn) {
sys/dev/disk/isp/isp.c
3096
if (lp->portid == tmp.portid &&
sys/dev/disk/isp/isp.c
3097
lp->handle == tmp.handle &&
sys/dev/disk/isp/isp.c
3098
lp->roles == tmp.roles) {
sys/dev/disk/isp/isp.c
3099
lp->new_portid = tmp.portid;
sys/dev/disk/isp/isp.c
3100
lp->new_roles = tmp.roles;
sys/dev/disk/isp/isp.c
3104
"Valid", chan, tmp.portid, tmp.handle);
sys/dev/disk/isp/isp.c
3112
lp->handle = tmp.handle;
sys/dev/disk/isp/isp.c
3120
chan, tmp.portid, tmp.handle);
sys/dev/disk/isp/isp.c
3122
lp->new_portid = tmp.portid;
sys/dev/disk/isp/isp.c
3123
lp->new_roles = tmp.roles;
sys/dev/disk/isp/isp.c
3156
lp->new_portid = tmp.portid;
sys/dev/disk/isp/isp.c
3157
lp->new_roles = tmp.roles;
sys/dev/disk/isp/isp.c
3158
lp->handle = tmp.handle;
sys/dev/disk/isp/isp.c
3159
lp->port_wwn = tmp.port_wwn;
sys/dev/disk/isp/isp.c
3160
lp->node_wwn = tmp.node_wwn;
sys/dev/disk/isp/isp.c
3163
chan, tmp.portid, tmp.handle);
sys/dev/disk/isp/isp.c
586
uint16_t tmp = isp->isp_mdvec->dv_conf1;
sys/dev/disk/isp/isp.c
591
tmp &= BIU_BURST_ENABLE;
sys/dev/disk/isp/isp.c
593
ISP_SETBITS(isp, BIU_CONF1, tmp);
sys/dev/disk/isp/isp.c
594
if (tmp & BIU_BURST_ENABLE) {
sys/dev/disk/isp/isp.c
7819
uint32_t tmp;
sys/dev/disk/isp/isp.c
7820
ISP_IOXGET_32(isp, &dptr[lwrds], tmp);
sys/dev/disk/isp/isp.c
7821
csum += tmp;
sys/dev/disk/isp/isp.c
7909
uint32_t tmp = 0;
sys/dev/disk/isp/isp.c
7917
tmp = ISP_READ(isp, BIU2400_FLASH_ADDR);
sys/dev/disk/isp/isp.c
7918
if ((tmp & (1U << 31)) != 0) {
sys/dev/disk/isp/isp.c
7922
if (tmp & (1U << 31)) {
sys/dev/disk/isp/isp_freebsd.c
2580
isp_notify_t tmp, *nt = &tmp;
sys/dev/disk/isp/isp_library.c
608
uint32_t tmp;
sys/dev/disk/isp/isp_library.c
614
for (tmp = 0; isp->isp_xflist && tmp < isp->isp_maxcmds; tmp++) {
sys/dev/disk/isp/isp_library.c
617
hdp = &isp->isp_xflist[tmp];
sys/dev/disk/isp/isp_library.c
634
for (tmp = 0; isp->isp_tgtlist && tmp < isp->isp_maxcmds; tmp++) {
sys/dev/disk/isp/isp_library.c
636
hdp = &isp->isp_tgtlist[tmp];
sys/dev/disk/isp/isp_library.c
660
for (tmp = 0; tmp < isp->isp_nchan; tmp++) {
sys/dev/disk/isp/isp_library.c
669
notify.nt_channel = tmp;
sys/dev/disk/mpt/mpt_cam.c
1062
CONFIG_PAGE_SCSI_PORT_1 tmp;
sys/dev/disk/mpt/mpt_cam.c
1066
tmp = mpt->mpt_port_page1;
sys/dev/disk/mpt/mpt_cam.c
1067
tmp.Configuration = pp1val;
sys/dev/disk/mpt/mpt_cam.c
1068
host2mpt_config_page_scsi_port_1(&tmp);
sys/dev/disk/mpt/mpt_cam.c
1070
&tmp.Header, sizeof(tmp), FALSE, 5000);
sys/dev/disk/mpt/mpt_cam.c
1075
&tmp.Header, sizeof(tmp), FALSE, 5000);
sys/dev/disk/mpt/mpt_cam.c
1079
mpt2host_config_page_scsi_port_1(&tmp);
sys/dev/disk/mpt/mpt_cam.c
1080
if (tmp.Configuration != pp1val) {
sys/dev/disk/mpt/mpt_cam.c
1085
mpt->mpt_port_page1 = tmp;
sys/dev/disk/mpt/mpt_cam.c
2777
MSG_LINK_SERVICE_RSP_REQUEST tmp;
sys/dev/disk/mpt/mpt_cam.c
2783
rsp = &tmp;
sys/dev/disk/mpt/mpt_cam.c
3751
CONFIG_PAGE_SCSI_DEVICE_0 tmp;
sys/dev/disk/mpt/mpt_cam.c
3754
tmp = mpt->mpt_dev_page0[tgt];
sys/dev/disk/mpt/mpt_cam.c
3755
rv = mpt_read_cur_cfg_page(mpt, tgt, &tmp.Header,
sys/dev/disk/mpt/mpt_cam.c
3756
sizeof(tmp), FALSE, 5000);
sys/dev/disk/mpt/mpt_cam.c
3761
mpt2host_config_page_scsi_device_0(&tmp);
sys/dev/disk/mpt/mpt_cam.c
3765
tmp.NegotiatedParameters, tmp.Information);
sys/dev/disk/mpt/mpt_cam.c
3766
dval |= (tmp.NegotiatedParameters & MPI_SCSIDEVPAGE0_NP_WIDE) ?
sys/dev/disk/mpt/mpt_cam.c
3772
oval = tmp.NegotiatedParameters;
sys/dev/disk/mpt/mpt_cam.c
3775
pval = tmp.NegotiatedParameters;
sys/dev/disk/mpt/mpt_cam.c
3778
mpt->mpt_dev_page0[tgt] = tmp;
sys/dev/disk/mpt/mpt_cam.c
3860
CONFIG_PAGE_SCSI_DEVICE_1 tmp;
sys/dev/disk/mpt/mpt_cam.c
3866
tmp = mpt->mpt_dev_page1[tgt];
sys/dev/disk/mpt/mpt_cam.c
3867
host2mpt_config_page_scsi_device_1(&tmp);
sys/dev/disk/mpt/mpt_cam.c
3869
&tmp.Header, sizeof(tmp), FALSE, 5000);
sys/dev/disk/nata/ata-isa.c
58
u_long tmp;
sys/dev/disk/nata/ata-isa.c
72
if (bus_get_resource(dev, SYS_RES_IOPORT, ATA_CTLADDR_RID, &tmp, &tmp)) {
sys/dev/disk/nata/ata-queue.c
568
struct ata_request *request, *tmp;
sys/dev/disk/nata/ata-queue.c
585
TAILQ_FOREACH_MUTABLE(request, &ch->ata_queue, chain, tmp) {
sys/dev/disk/nata/ata-queue.c
599
TAILQ_FOREACH_MUTABLE(request, &fail_requests, chain, tmp) {
sys/dev/disk/nata/ata-queue.c
66
struct ata_request *request, *tmp;
sys/dev/disk/nata/ata-queue.c
69
TAILQ_FOREACH_MUTABLE(request, &ch->ata_queue, chain, tmp) {
sys/dev/disk/nata/ata-raid.c
2130
char *tmp;
sys/dev/disk/nata/ata-raid.c
2139
tmp = (char *)meta;
sys/dev/disk/nata/ata-raid.c
2140
bcopy(tmp, tmp+1024, 512);
sys/dev/disk/nata/ata-raid.c
2141
bcopy(tmp+512, tmp, 1024);
sys/dev/disk/nata/ata-raid.c
2142
bzero(tmp+1024, 512);
sys/dev/disk/nata/ata-raid.c
2320
char *tmp;
sys/dev/disk/nata/ata-raid.c
2415
tmp = (char *)meta;
sys/dev/disk/nata/ata-raid.c
2416
bcopy(tmp, tmp+1024, 512);
sys/dev/disk/nata/ata-raid.c
2417
bcopy(tmp+512, tmp, 1024);
sys/dev/disk/nata/ata-raid.c
2418
bzero(tmp+1024, 512);
sys/dev/disk/sym/sym_hipd.c
4450
u32 tmp;
sys/dev/disk/sym/sym_hipd.c
4457
tmp = scr_to_cpu(pm->sg.addr);
sys/dev/disk/sym/sym_hipd.c
4458
cp->phys.wresid.addr = cpu_to_scr(tmp);
sys/dev/disk/sym/sym_hipd.c
4459
pm->sg.addr = cpu_to_scr(tmp + 1);
sys/dev/disk/sym/sym_hipd.c
4460
tmp = scr_to_cpu(pm->sg.size);
sys/dev/disk/sym/sym_hipd.c
4461
cp->phys.wresid.size = cpu_to_scr((tmp&0xff000000) | 1);
sys/dev/disk/sym/sym_hipd.c
4462
pm->sg.size = cpu_to_scr(tmp - 1);
sys/dev/disk/sym/sym_hipd.c
4468
if ((tmp&0xffffff) == 1)
sys/dev/disk/sym/sym_hipd.c
5286
int tmp;
sys/dev/disk/sym/sym_hipd.c
5321
tmp = scr_to_cpu(cp->phys.head.goalp);
sys/dev/disk/sym/sym_hipd.c
5323
if (dp_scr != tmp)
sys/dev/disk/sym/sym_hipd.c
5324
dp_sg -= (tmp - 8 - (int)dp_scr) / (2*4);
sys/dev/disk/sym/sym_hipd.c
5343
tmp = scr_to_cpu(cp->phys.data[dp_sg].size);
sys/dev/disk/sym/sym_hipd.c
5344
n = dp_ofs + (tmp & 0xffffff);
sys/dev/disk/sym/sym_hipd.c
5354
tmp = scr_to_cpu(cp->phys.data[dp_sg].size);
sys/dev/disk/sym/sym_hipd.c
5355
dp_ofs -= (tmp & 0xffffff);
sys/dev/disk/sym/sym_hipd.c
5405
u32 tmp;
sys/dev/disk/sym/sym_hipd.c
5469
tmp = scr_to_cpu(cp->phys.data[dp_sg-1].addr);
sys/dev/disk/sym/sym_hipd.c
5470
tmp += scr_to_cpu(cp->phys.data[dp_sg-1].size) + dp_ofs;
sys/dev/disk/sym/sym_hipd.c
5471
pm->sg.addr = cpu_to_scr(tmp);
sys/dev/disk/sym/sym_hipd.c
5550
u_int tmp = scr_to_cpu(cp->phys.data[dp_sg].size);
sys/dev/disk/sym/sym_hipd.c
5551
resid += (tmp & 0xffffff);
sys/dev/disk/sym/sym_hipd.c
6029
int tmp;
sys/dev/disk/sym/sym_hipd.c
6203
tmp = (np->msgin[3]<<24) + (np->msgin[4]<<16) +
sys/dev/disk/sym/sym_hipd.c
6205
sym_modify_dp(np, tp, cp, tmp);
sys/dev/disk/sym/sym_hipd.c
7463
int tmp;
sys/dev/disk/sym/sym_hipd.c
7541
tmp = ((ccb_h->flags & CAM_TAG_ACTION_VALID) != 0);
sys/dev/disk/sym/sym_hipd.c
7542
cp = sym_get_ccb(np, ccb_h->target_id, ccb_h->target_lun, tmp);
sys/dev/drm/amd/amdgpu/amdgpu_acpi.c
772
struct drm_encoder *tmp;
sys/dev/drm/amd/amdgpu/amdgpu_acpi.c
775
list_for_each_entry(tmp, &adev->ddev->mode_config.encoder_list,
sys/dev/drm/amd/amdgpu/amdgpu_acpi.c
777
struct amdgpu_encoder *enc = to_amdgpu_encoder(tmp);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
852
unsigned int tmp;
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
861
tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
862
if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
863
(tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
sys/dev/drm/amd/amdgpu/amdgpu_atombios.c
1158
u32 tmp;
sys/dev/drm/amd/amdgpu/amdgpu_atombios.c
1162
tmp = eng_clock & SET_CLOCK_FREQ_MASK;
sys/dev/drm/amd/amdgpu/amdgpu_atombios.c
1163
tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
sys/dev/drm/amd/amdgpu/amdgpu_atombios.c
1165
args.ulTargetEngineClock = cpu_to_le32(tmp);
sys/dev/drm/amd/amdgpu/amdgpu_atombios.c
1729
u32 tmp = RREG32(adev->bios_scratch_reg_offset + 3);
sys/dev/drm/amd/amdgpu/amdgpu_atombios.c
1732
tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
sys/dev/drm/amd/amdgpu/amdgpu_atombios.c
1734
tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
sys/dev/drm/amd/amdgpu/amdgpu_atombios.c
1736
WREG32(adev->bios_scratch_reg_offset + 3, tmp);
sys/dev/drm/amd/amdgpu/amdgpu_atombios.c
1741
u32 tmp = RREG32(adev->bios_scratch_reg_offset + 7);
sys/dev/drm/amd/amdgpu/amdgpu_atombios.c
1743
if (tmp & ATOM_S7_ASIC_INIT_COMPLETE_MASK)
sys/dev/drm/amd/amdgpu/amdgpu_bios.c
50
uint16_t tmp, bios_header_start;
sys/dev/drm/amd/amdgpu/amdgpu_bios.c
68
tmp = bios_header_start + 4;
sys/dev/drm/amd/amdgpu/amdgpu_bios.c
69
if (size < tmp) {
sys/dev/drm/amd/amdgpu/amdgpu_bios.c
74
if (!memcmp(bios + tmp, "ATOM", 4) ||
sys/dev/drm/amd/amdgpu/amdgpu_bios.c
75
!memcmp(bios + tmp, "MOTA", 4)) {
sys/dev/drm/amd/amdgpu/amdgpu_device.c
467
u32 tmp, reg, and_mask, or_mask;
sys/dev/drm/amd/amdgpu/amdgpu_device.c
479
tmp = or_mask;
sys/dev/drm/amd/amdgpu/amdgpu_device.c
481
tmp = RREG32(reg);
sys/dev/drm/amd/amdgpu/amdgpu_device.c
482
tmp &= ~and_mask;
sys/dev/drm/amd/amdgpu/amdgpu_device.c
483
tmp |= or_mask;
sys/dev/drm/amd/amdgpu/amdgpu_device.c
485
WREG32(reg, tmp);
sys/dev/drm/amd/amdgpu/amdgpu_dpm.c
192
u32 tmp;
sys/dev/drm/amd/amdgpu/amdgpu_dpm.c
195
tmp = i_c >> p_b;
sys/dev/drm/amd/amdgpu/amdgpu_dpm.c
197
while (tmp) {
sys/dev/drm/amd/amdgpu/amdgpu_dpm.c
199
tmp >>= 1;
sys/dev/drm/amd/amdgpu/amdgpu_fb.c
268
unsigned long tmp = amdgpu_bo_gpu_offset(abo) - adev->gmc.vram_start;
sys/dev/drm/amd/amdgpu/amdgpu_fb.c
270
info->paddr = adev->gmc.aper_base + tmp;
sys/dev/drm/amd/amdgpu/amdgpu_fb.c
279
tmp = amdgpu_bo_gpu_offset(abo) - adev->gmc.vram_start;
sys/dev/drm/amd/amdgpu/amdgpu_fb.c
280
info->fix.smem_start = adev->gmc.aper_base + tmp;
sys/dev/drm/amd/amdgpu/amdgpu_ib.c
125
struct dma_fence *tmp = NULL;
sys/dev/drm/amd/amdgpu/amdgpu_ib.c
170
((tmp = amdgpu_sync_get_fence(&job->sched_sync, NULL)) ||
sys/dev/drm/amd/amdgpu/amdgpu_ib.c
176
if (tmp)
sys/dev/drm/amd/amdgpu/amdgpu_ib.c
177
trace_amdgpu_ib_pipe_sync(job, tmp);
sys/dev/drm/amd/amdgpu/amdgpu_ib.c
180
dma_fence_put(tmp);
sys/dev/drm/amd/amdgpu/amdgpu_ids.c
294
struct dma_fence *tmp;
sys/dev/drm/amd/amdgpu/amdgpu_ids.c
298
tmp = amdgpu_sync_peek_fence(&(*id)->active, ring);
sys/dev/drm/amd/amdgpu/amdgpu_ids.c
299
if (tmp) {
sys/dev/drm/amd/amdgpu/amdgpu_ids.c
301
r = amdgpu_sync_fence(adev, sync, tmp, false);
sys/dev/drm/amd/amdgpu/amdgpu_pll.c
227
unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
sys/dev/drm/amd/amdgpu/amdgpu_pll.c
228
fb_div *= tmp;
sys/dev/drm/amd/amdgpu/amdgpu_pll.c
229
ref_div *= tmp;
sys/dev/drm/amd/amdgpu/amdgpu_pll.c
47
unsigned tmp;
sys/dev/drm/amd/amdgpu/amdgpu_pll.c
50
tmp = gcd(*nom, *den);
sys/dev/drm/amd/amdgpu/amdgpu_pll.c
51
*nom /= tmp;
sys/dev/drm/amd/amdgpu/amdgpu_pll.c
52
*den /= tmp;
sys/dev/drm/amd/amdgpu/amdgpu_pll.c
56
tmp = DIV_ROUND_UP(nom_min, *nom);
sys/dev/drm/amd/amdgpu/amdgpu_pll.c
57
*nom *= tmp;
sys/dev/drm/amd/amdgpu/amdgpu_pll.c
58
*den *= tmp;
sys/dev/drm/amd/amdgpu/amdgpu_pll.c
63
tmp = DIV_ROUND_UP(den_min, *den);
sys/dev/drm/amd/amdgpu/amdgpu_pll.c
64
*nom *= tmp;
sys/dev/drm/amd/amdgpu/amdgpu_pll.c
65
*den *= tmp;
sys/dev/drm/amd/amdgpu/amdgpu_pm.c
674
char *tmp;
sys/dev/drm/amd/amdgpu/amdgpu_pm.c
684
tmp = buf_cpy;
sys/dev/drm/amd/amdgpu/amdgpu_pm.c
685
while (tmp[0]) {
sys/dev/drm/amd/amdgpu/amdgpu_pm.c
686
sub_str = strsep(&tmp, delimiter);
sys/dev/drm/amd/amdgpu/amdgpu_pm.c
929
char tmp[2];
sys/dev/drm/amd/amdgpu/amdgpu_pm.c
933
tmp[0] = *(buf);
sys/dev/drm/amd/amdgpu/amdgpu_pm.c
934
tmp[1] = '\0';
sys/dev/drm/amd/amdgpu/amdgpu_pm.c
935
ret = kstrtol(tmp, 0, &profile_mode);
sys/dev/drm/amd/amdgpu/amdgpu_sa.c
116
struct amdgpu_sa_bo *sa_bo, *tmp;
sys/dev/drm/amd/amdgpu/amdgpu_sa.c
122
list_for_each_entry_safe_from(sa_bo, tmp, &sa_manager->olist, olist) {
sys/dev/drm/amd/amdgpu/amdgpu_sa.c
211
unsigned i, soffset, best, tmp;
sys/dev/drm/amd/amdgpu/amdgpu_sa.c
247
tmp = sa_bo->soffset;
sys/dev/drm/amd/amdgpu/amdgpu_sa.c
248
if (tmp < soffset) {
sys/dev/drm/amd/amdgpu/amdgpu_sa.c
250
tmp += sa_manager->size;
sys/dev/drm/amd/amdgpu/amdgpu_sa.c
252
tmp -= soffset;
sys/dev/drm/amd/amdgpu/amdgpu_sa.c
253
if (tmp < best) {
sys/dev/drm/amd/amdgpu/amdgpu_sa.c
255
best = tmp;
sys/dev/drm/amd/amdgpu/amdgpu_sa.c
80
struct amdgpu_sa_bo *sa_bo, *tmp;
sys/dev/drm/amd/amdgpu/amdgpu_sa.c
94
list_for_each_entry_safe(sa_bo, tmp, &sa_manager->olist, olist) {
sys/dev/drm/amd/amdgpu/amdgpu_sync.c
263
struct hlist_node *tmp;
sys/dev/drm/amd/amdgpu/amdgpu_sync.c
266
hash_for_each_safe(sync->fences, i, tmp, e, node) {
sys/dev/drm/amd/amdgpu/amdgpu_sync.c
305
struct hlist_node *tmp;
sys/dev/drm/amd/amdgpu/amdgpu_sync.c
308
hash_for_each_safe(sync->fences, i, tmp, e, node) {
sys/dev/drm/amd/amdgpu/amdgpu_sync.c
337
struct hlist_node *tmp;
sys/dev/drm/amd/amdgpu/amdgpu_sync.c
341
hash_for_each_safe(source->fences, i, tmp, e, node) {
sys/dev/drm/amd/amdgpu/amdgpu_sync.c
363
struct hlist_node *tmp;
sys/dev/drm/amd/amdgpu/amdgpu_sync.c
366
hash_for_each_safe(sync->fences, i, tmp, e, node) {
sys/dev/drm/amd/amdgpu/amdgpu_sync.c
389
struct hlist_node *tmp;
sys/dev/drm/amd/amdgpu/amdgpu_sync.c
392
hash_for_each_safe(sync->fences, i, tmp, e, node) {
sys/dev/drm/amd/amdgpu/amdgpu_ttm.c
1116
struct ttm_mem_reg tmp;
sys/dev/drm/amd/amdgpu/amdgpu_ttm.c
1131
tmp = bo->mem;
sys/dev/drm/amd/amdgpu/amdgpu_ttm.c
1132
tmp.mm_node = NULL;
sys/dev/drm/amd/amdgpu/amdgpu_ttm.c
1142
r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
sys/dev/drm/amd/amdgpu/amdgpu_ttm.c
1147
flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
sys/dev/drm/amd/amdgpu/amdgpu_ttm.c
1150
gtt->offset = (u64)tmp.start << PAGE_SHIFT;
sys/dev/drm/amd/amdgpu/amdgpu_ttm.c
1153
ttm_bo_mem_put(bo, &tmp);
sys/dev/drm/amd/amdgpu/amdgpu_ttm.c
1158
bo->mem = tmp;
sys/dev/drm/amd/amdgpu/amdgpu_uvd.c
528
unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
sys/dev/drm/amd/amdgpu/amdgpu_uvd.c
592
tmp = max(width_in_mb, height_in_mb);
sys/dev/drm/amd/amdgpu/amdgpu_uvd.c
593
min_dpb_size += ALIGN(tmp * 7 * 16, 64);
sys/dev/drm/amd/amdgpu/amdgpu_vce.c
1014
tmp = destroyed;
sys/dev/drm/amd/amdgpu/amdgpu_vce.c
1018
tmp = allocated;
sys/dev/drm/amd/amdgpu/amdgpu_vce.c
1022
if (tmp & (1 << i))
sys/dev/drm/amd/amdgpu/amdgpu_vce.c
716
uint32_t tmp, handle = 0;
sys/dev/drm/amd/amdgpu/amdgpu_vce.c
717
uint32_t *size = &tmp;
sys/dev/drm/amd/amdgpu/amdgpu_vce.c
760
tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
sys/dev/drm/amd/amdgpu/amdgpu_vce.c
762
tmp, bs_idx);
sys/dev/drm/amd/amdgpu/amdgpu_vce.c
876
tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
sys/dev/drm/amd/amdgpu/amdgpu_vce.c
878
tmp, bs_idx);
sys/dev/drm/amd/amdgpu/amdgpu_vce.c
925
tmp = destroyed;
sys/dev/drm/amd/amdgpu/amdgpu_vce.c
928
tmp = allocated;
sys/dev/drm/amd/amdgpu/amdgpu_vce.c
932
if (tmp & (1 << i))
sys/dev/drm/amd/amdgpu/amdgpu_vce.c
951
uint32_t tmp, handle = 0;
sys/dev/drm/amd/amdgpu/amdgpu_vcn.c
432
uint32_t tmp = 0;
sys/dev/drm/amd/amdgpu/amdgpu_vcn.c
448
tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9));
sys/dev/drm/amd/amdgpu/amdgpu_vcn.c
449
if (tmp == 0xDEADBEEF)
sys/dev/drm/amd/amdgpu/amdgpu_vcn.c
459
ring->idx, tmp);
sys/dev/drm/amd/amdgpu/amdgpu_vcn.c
786
uint32_t tmp = 0;
sys/dev/drm/amd/amdgpu/amdgpu_vcn.c
805
tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9));
sys/dev/drm/amd/amdgpu/amdgpu_vcn.c
806
if (tmp == 0xDEADBEEF)
sys/dev/drm/amd/amdgpu/amdgpu_vcn.c
816
ring->idx, tmp);
sys/dev/drm/amd/amdgpu/amdgpu_vcn.c
865
uint32_t tmp = 0;
sys/dev/drm/amd/amdgpu/amdgpu_vcn.c
888
tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9));
sys/dev/drm/amd/amdgpu/amdgpu_vcn.c
889
if (tmp == 0xDEADBEEF)
sys/dev/drm/amd/amdgpu/amdgpu_vcn.c
897
DRM_ERROR("ib test failed (0x%08X)\n", tmp);
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2370
struct amdgpu_bo_va *bo_va, *tmp;
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2375
list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2498
struct amdgpu_bo_va_mapping *mapping, *tmp;
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2517
tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2518
if (tmp) {
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2522
tmp->start, tmp->last + 1);
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2675
struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2697
tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2698
while (tmp) {
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2700
if (tmp->start < saddr) {
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2701
before->start = tmp->start;
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2703
before->offset = tmp->offset;
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2704
before->flags = tmp->flags;
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2705
before->bo_va = tmp->bo_va;
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2706
list_add(&before->list, &tmp->bo_va->invalids);
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2710
if (tmp->last > eaddr) {
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2712
after->last = tmp->last;
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2713
after->offset = tmp->offset;
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2714
after->offset += after->start - tmp->start;
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2715
after->flags = tmp->flags;
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2716
after->bo_va = tmp->bo_va;
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2717
list_add(&after->list, &tmp->bo_va->invalids);
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2720
list_del(&tmp->list);
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2721
list_add(&tmp->list, &removed);
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2723
tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2727
list_for_each_entry_safe(tmp, next, &removed, list) {
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2728
amdgpu_vm_it_remove(tmp, &vm->va);
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2729
list_del(&tmp->list);
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2731
if (tmp->start < saddr)
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2732
tmp->start = saddr;
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2733
if (tmp->last > eaddr)
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2734
tmp->last = eaddr;
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2736
tmp->bo_va = NULL;
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2737
list_add(&tmp->list, &vm->freed);
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2738
trace_amdgpu_vm_bo_unmap(NULL, tmp);
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2941
uint64_t tmp;
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2979
tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2981
tmp >>= amdgpu_vm_block_size - 9;
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2982
tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
2983
adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
3006
adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
3284
struct amdgpu_bo_va_mapping *mapping, *tmp;
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
3317
rbtree_postorder_for_each_entry_safe(mapping, tmp,
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
3335
list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
750
struct amdgpu_vm_bo_base *bo_base, *tmp;
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
755
list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
sys/dev/drm/amd/amdgpu/amdgpu_xgmi.c
45
struct amdgpu_hive_info *tmp;
sys/dev/drm/amd/amdgpu/amdgpu_xgmi.c
50
tmp = &xgmi_hives[i];
sys/dev/drm/amd/amdgpu/amdgpu_xgmi.c
51
if (tmp->hive_id == adev->gmc.xgmi.hive_id)
sys/dev/drm/amd/amdgpu/amdgpu_xgmi.c
52
return tmp;
sys/dev/drm/amd/amdgpu/amdgpu_xgmi.c
58
tmp = &xgmi_hives[hive_count++];
sys/dev/drm/amd/amdgpu/amdgpu_xgmi.c
59
tmp->hive_id = adev->gmc.xgmi.hive_id;
sys/dev/drm/amd/amdgpu/amdgpu_xgmi.c
60
INIT_LIST_HEAD(&tmp->device_list);
sys/dev/drm/amd/amdgpu/amdgpu_xgmi.c
61
return tmp;
sys/dev/drm/amd/amdgpu/atombios_dp.c
367
u8 tmp;
sys/dev/drm/amd/amdgpu/atombios_dp.c
377
DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
sys/dev/drm/amd/amdgpu/atombios_dp.c
378
if (tmp & 1)
sys/dev/drm/amd/amdgpu/atombios_dp.c
389
DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
sys/dev/drm/amd/amdgpu/atombios_dp.c
390
if (tmp & 1)
sys/dev/drm/amd/amdgpu/atombios_dp.c
533
u8 tmp;
sys/dev/drm/amd/amdgpu/atombios_dp.c
550
tmp = dp_info->dp_lane_count;
sys/dev/drm/amd/amdgpu/atombios_dp.c
552
tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
sys/dev/drm/amd/amdgpu/atombios_dp.c
553
drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
sys/dev/drm/amd/amdgpu/atombios_dp.c
556
tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
sys/dev/drm/amd/amdgpu/atombios_dp.c
557
drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
sys/dev/drm/amd/amdgpu/atombios_dp.c
720
u8 tmp;
sys/dev/drm/amd/amdgpu/atombios_dp.c
735
if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
sys/dev/drm/amd/amdgpu/atombios_dp.c
737
if (tmp & DP_TPS3_SUPPORTED)
sys/dev/drm/amd/amdgpu/ci_dpm.c
1011
u32 tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1022
tmp = RREG32_SMC(ixCG_THERMAL_INT);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1023
tmp &= ~(CG_THERMAL_INT__DIG_THERM_INTH_MASK | CG_THERMAL_INT__DIG_THERM_INTL_MASK);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1024
tmp |= ((high_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTH__SHIFT) |
sys/dev/drm/amd/amdgpu/ci_dpm.c
1026
WREG32_SMC(ixCG_THERMAL_INT, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1030
tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1031
tmp &= DIG_THERM_DPM_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1032
tmp |= DIG_THERM_DPM(high_temp / 1000);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1033
WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1073
u32 tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1076
tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK)
sys/dev/drm/amd/amdgpu/ci_dpm.c
1078
pi->fan_ctrl_default_mode = tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1079
tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK)
sys/dev/drm/amd/amdgpu/ci_dpm.c
1081
pi->t_min = tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1085
tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1086
tmp |= 0 << CG_FDO_CTRL2__TMIN__SHIFT;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1087
WREG32_SMC(ixCG_FDO_CTRL2, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1089
tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1090
tmp |= mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1091
WREG32_SMC(ixCG_FDO_CTRL2, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1101
u32 reference_clock, tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1155
tmp = (RREG32_SMC(ixCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK)
sys/dev/drm/amd/amdgpu/ci_dpm.c
1157
fan_table.TempSrc = (uint8_t)tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1247
u32 tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1272
tmp = RREG32_SMC(ixCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1273
tmp |= duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1274
WREG32_SMC(ixCG_FDO_CTRL0, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1339
u32 tach_period, tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1356
tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1357
tmp |= tach_period << CG_TACH_CTRL__TARGET_PERIOD__SHIFT;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1358
WREG32_SMC(CG_TACH_CTRL, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1369
u32 tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1372
tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1373
tmp |= pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1374
WREG32_SMC(ixCG_FDO_CTRL2, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1376
tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1377
tmp |= pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1378
WREG32_SMC(ixCG_FDO_CTRL2, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1393
u32 tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1396
tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1397
tmp |= (adev->pm.fan_pulses_per_revolution - 1)
sys/dev/drm/amd/amdgpu/ci_dpm.c
1399
WREG32_SMC(ixCG_TACH_CTRL, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1402
tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1403
tmp |= 0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1404
WREG32_SMC(ixCG_FDO_CTRL2, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1460
u16 tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1462
tmp = 45;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1463
table->FpsHighT = cpu_to_be16(tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1465
tmp = 30;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1466
table->FpsLowT = cpu_to_be16(tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1537
u32 tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1562
tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1563
tmp &= DPM_EVENT_SRC_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1564
tmp |= DPM_EVENT_SRC(dpm_event_src);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1565
WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1568
tmp = RREG32_SMC(ixGENERAL_PWRMGT);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1570
tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1572
tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1573
WREG32_SMC(ixGENERAL_PWRMGT, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1575
tmp = RREG32_SMC(ixGENERAL_PWRMGT);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1576
tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1577
WREG32_SMC(ixGENERAL_PWRMGT, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1684
u32 tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1686
tmp = RREG32_SMC(ixGENERAL_PWRMGT);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1687
tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1688
WREG32_SMC(ixGENERAL_PWRMGT, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1690
tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1691
tmp |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1692
WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1745
u32 tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1747
tmp = RREG32_SMC(ixGENERAL_PWRMGT);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1748
tmp &= ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1749
WREG32_SMC(ixGENERAL_PWRMGT, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1751
tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1752
tmp &= ~SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1753
WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1774
u32 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1777
tmp &= ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1779
tmp |= SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1780
WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1951
u32 tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1957
&tmp, pi->sram_end);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1961
pi->dpm_table_start = tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1966
&tmp, pi->sram_end);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1970
pi->soft_regs_start = tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1975
&tmp, pi->sram_end);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1979
pi->mc_reg_table_start = tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1984
&tmp, pi->sram_end);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1988
pi->fan_table_start = tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
1993
&tmp, pi->sram_end);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1997
pi->arb_table_start = tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
2039
u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2042
tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
2044
tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
2045
WREG32_SMC(ixGENERAL_PWRMGT, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2050
u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2052
tmp |= GENERAL_PWRMGT__STATIC_PM_EN_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
2054
WREG32_SMC(ixGENERAL_PWRMGT, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2119
u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2126
tmp &= ~CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
2128
tmp |= (AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2130
tmp |= (AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2131
WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2140
tmp = pre_vbi_time_in_us * (ref_clock / 100);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2142
WREG32_SMC(ixCG_DISPLAY_GAP_CNTL2, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2154
u32 tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
2158
tmp = RREG32_SMC(ixGENERAL_PWRMGT);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2159
tmp |= GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
2160
WREG32_SMC(ixGENERAL_PWRMGT, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2163
tmp = RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2164
tmp &= ~CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
2165
WREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2167
tmp = RREG32_SMC(ixGENERAL_PWRMGT);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2168
tmp &= ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
2169
WREG32_SMC(ixGENERAL_PWRMGT, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2182
u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2184
tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK |
sys/dev/drm/amd/amdgpu/ci_dpm.c
2186
tmp |= ((AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT) |
sys/dev/drm/amd/amdgpu/ci_dpm.c
2189
WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2194
u32 tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
2196
tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2197
tmp &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2198
WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2212
u32 tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
2214
tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2215
tmp |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2216
WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2555
u32 tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
2559
&tmp, pi->sram_end);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2563
tmp &= 0x00FFFFFF;
sys/dev/drm/amd/amdgpu/ci_dpm.c
2564
tmp |= MC_CG_ARB_FREQ_F1 << 24;
sys/dev/drm/amd/amdgpu/ci_dpm.c
2567
tmp, pi->sram_end);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2594
u32 tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
2601
tmp = sclk >> i;
sys/dev/drm/amd/amdgpu/ci_dpm.c
2602
if (tmp >= min || i == 0)
sys/dev/drm/amd/amdgpu/ci_dpm.c
2622
u32 tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
2624
tmp = (RREG32_SMC(ixSMC_SCRATCH9) & 0x0000ff00) >> 8;
sys/dev/drm/amd/amdgpu/ci_dpm.c
2626
if (tmp == MC_CG_ARB_FREQ_F0)
sys/dev/drm/amd/amdgpu/ci_dpm.c
2629
return ci_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2638
u32 tmp, tmp2;
sys/dev/drm/amd/amdgpu/ci_dpm.c
2640
tmp = RREG32(mmMC_SEQ_MISC0);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2641
patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
sys/dev/drm/amd/amdgpu/ci_dpm.c
2969
u32 tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
2977
tmp = (freq_nom / reference_clock);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2978
tmp = tmp * tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
2982
u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
sys/dev/drm/amd/amdgpu/ci_dpm.c
4224
u32 tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
4236
tmp = RREG32_SMC(ixDPM_TABLE_475);
sys/dev/drm/amd/amdgpu/ci_dpm.c
4237
tmp &= ~DPM_TABLE_475__UvdBootLevel_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
4238
tmp |= (pi->smc_state_table.UvdBootLevel << DPM_TABLE_475__UvdBootLevel__SHIFT);
sys/dev/drm/amd/amdgpu/ci_dpm.c
4239
WREG32_SMC(ixDPM_TABLE_475, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
4271
u32 tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
4276
tmp = RREG32_SMC(ixDPM_TABLE_475);
sys/dev/drm/amd/amdgpu/ci_dpm.c
4277
tmp &= ~DPM_TABLE_475__VceBootLevel_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
4278
tmp |= (pi->smc_state_table.VceBootLevel << DPM_TABLE_475__VceBootLevel__SHIFT);
sys/dev/drm/amd/amdgpu/ci_dpm.c
4279
WREG32_SMC(ixDPM_TABLE_475, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
4300
u32 tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
4305
tmp = RREG32_SMC(ixDPM_TABLE_475);
sys/dev/drm/amd/amdgpu/ci_dpm.c
4306
tmp &= ~AcpBootLevel_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
4307
tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
sys/dev/drm/amd/amdgpu/ci_dpm.c
4308
WREG32_SMC(ixDPM_TABLE_475, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
4358
u32 tmp, levels, i;
sys/dev/drm/amd/amdgpu/ci_dpm.c
4365
tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
sys/dev/drm/amd/amdgpu/ci_dpm.c
4366
while (tmp >>= 1)
sys/dev/drm/amd/amdgpu/ci_dpm.c
4373
tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
sys/dev/drm/amd/amdgpu/ci_dpm.c
4376
if (tmp == levels)
sys/dev/drm/amd/amdgpu/ci_dpm.c
4385
tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
sys/dev/drm/amd/amdgpu/ci_dpm.c
4386
while (tmp >>= 1)
sys/dev/drm/amd/amdgpu/ci_dpm.c
4393
tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
sys/dev/drm/amd/amdgpu/ci_dpm.c
4396
if (tmp == levels)
sys/dev/drm/amd/amdgpu/ci_dpm.c
4405
tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
sys/dev/drm/amd/amdgpu/ci_dpm.c
4406
while (tmp >>= 1)
sys/dev/drm/amd/amdgpu/ci_dpm.c
4413
tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
sys/dev/drm/amd/amdgpu/ci_dpm.c
4416
if (tmp == levels)
sys/dev/drm/amd/amdgpu/ci_dpm.c
4431
tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
sys/dev/drm/amd/amdgpu/ci_dpm.c
4434
if (tmp == levels)
sys/dev/drm/amd/amdgpu/ci_dpm.c
4447
tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
sys/dev/drm/amd/amdgpu/ci_dpm.c
4450
if (tmp == levels)
sys/dev/drm/amd/amdgpu/ci_dpm.c
4463
tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
sys/dev/drm/amd/amdgpu/ci_dpm.c
4466
if (tmp == levels)
sys/dev/drm/amd/amdgpu/ci_dpm.c
4687
u32 tmp;
sys/dev/drm/amd/amdgpu/ci_dpm.c
4690
tmp = RREG32(mmMC_SEQ_MISC0);
sys/dev/drm/amd/amdgpu/ci_dpm.c
4691
patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
sys/dev/drm/amd/amdgpu/ci_dpm.c
4764
tmp = RREG32(mmMC_SEQ_IO_DEBUG_DATA);
sys/dev/drm/amd/amdgpu/ci_dpm.c
4765
tmp = (tmp & 0xFFF8FFFF) | (1 << 16);
sys/dev/drm/amd/amdgpu/ci_dpm.c
4767
WREG32(mmMC_SEQ_IO_DEBUG_DATA, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
4940
u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
sys/dev/drm/amd/amdgpu/ci_dpm.c
4942
tmp |= GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
4943
WREG32_SMC(ixGENERAL_PWRMGT, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
5990
u32 tmp = RREG32_SMC(ixCNB_PWRMGT_CNTL);
sys/dev/drm/amd/amdgpu/ci_dpm.c
5994
tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
5995
tmp |= 1 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT;
sys/dev/drm/amd/amdgpu/ci_dpm.c
5998
tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
5999
tmp |= 2 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT;
sys/dev/drm/amd/amdgpu/ci_dpm.c
6002
tmp |= CNB_PWRMGT_CNTL__GNB_SLOW_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
6005
tmp |= CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
6008
tmp |= CNB_PWRMGT_CNTL__DPM_ENABLED_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
6014
WREG32_SMC(ixCNB_PWRMGT_CNTL, tmp);
sys/dev/drm/amd/amdgpu/ci_dpm.c
6635
uint32_t tmp = mask & pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
sys/dev/drm/amd/amdgpu/ci_dpm.c
6638
if (fls(tmp) != ffs(tmp))
sys/dev/drm/amd/amdgpu/ci_dpm.c
6643
fls(tmp) - 1);
sys/dev/drm/amd/amdgpu/ci_smc.c
119
u32 tmp = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
sys/dev/drm/amd/amdgpu/ci_smc.c
121
tmp &= ~SMC_SYSCON_RESET_CNTL__rst_reg_MASK;
sys/dev/drm/amd/amdgpu/ci_smc.c
122
WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, tmp);
sys/dev/drm/amd/amdgpu/ci_smc.c
127
u32 tmp = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
sys/dev/drm/amd/amdgpu/ci_smc.c
129
tmp |= SMC_SYSCON_RESET_CNTL__rst_reg_MASK;
sys/dev/drm/amd/amdgpu/ci_smc.c
130
WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, tmp);
sys/dev/drm/amd/amdgpu/ci_smc.c
142
u32 tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
sys/dev/drm/amd/amdgpu/ci_smc.c
144
tmp |= SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK;
sys/dev/drm/amd/amdgpu/ci_smc.c
146
WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, tmp);
sys/dev/drm/amd/amdgpu/ci_smc.c
151
u32 tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
sys/dev/drm/amd/amdgpu/ci_smc.c
153
tmp &= ~SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK;
sys/dev/drm/amd/amdgpu/ci_smc.c
155
WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, tmp);
sys/dev/drm/amd/amdgpu/ci_smc.c
171
u32 tmp;
sys/dev/drm/amd/amdgpu/ci_smc.c
180
tmp = RREG32(mmSMC_RESP_0);
sys/dev/drm/amd/amdgpu/ci_smc.c
181
if (tmp != 0)
sys/dev/drm/amd/amdgpu/ci_smc.c
185
tmp = RREG32(mmSMC_RESP_0);
sys/dev/drm/amd/amdgpu/ci_smc.c
187
return (PPSMC_Result)tmp;
sys/dev/drm/amd/amdgpu/ci_smc.c
192
u32 tmp;
sys/dev/drm/amd/amdgpu/ci_smc.c
199
tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
sys/dev/drm/amd/amdgpu/ci_smc.c
200
if ((tmp & SMC_SYSCON_CLOCK_CNTL_0__cken_MASK) == 0)
sys/dev/drm/amd/amdgpu/cik.c
1303
uint32_t tmp;
sys/dev/drm/amd/amdgpu/cik.c
1311
tmp = RREG32_SMC(cntl_reg);
sys/dev/drm/amd/amdgpu/cik.c
1312
tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
sys/dev/drm/amd/amdgpu/cik.c
1314
tmp |= dividers.post_divider;
sys/dev/drm/amd/amdgpu/cik.c
1315
WREG32_SMC(cntl_reg, tmp);
sys/dev/drm/amd/amdgpu/cik.c
1344
u32 tmp;
sys/dev/drm/amd/amdgpu/cik.c
1360
tmp = RREG32_SMC(ixCG_ECLK_CNTL);
sys/dev/drm/amd/amdgpu/cik.c
1361
tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK |
sys/dev/drm/amd/amdgpu/cik.c
1363
tmp |= dividers.post_divider;
sys/dev/drm/amd/amdgpu/cik.c
1364
WREG32_SMC(ixCG_ECLK_CNTL, tmp);
sys/dev/drm/amd/amdgpu/cik.c
1430
u32 max_lw, current_lw, tmp;
sys/dev/drm/amd/amdgpu/cik.c
1441
tmp = RREG32_PCIE(ixPCIE_LC_STATUS1);
sys/dev/drm/amd/amdgpu/cik.c
1442
max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >>
sys/dev/drm/amd/amdgpu/cik.c
1444
current_lw = (tmp & PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK)
sys/dev/drm/amd/amdgpu/cik.c
1448
tmp = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL);
sys/dev/drm/amd/amdgpu/cik.c
1449
if (tmp & PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK) {
sys/dev/drm/amd/amdgpu/cik.c
1450
tmp &= ~(PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK |
sys/dev/drm/amd/amdgpu/cik.c
1452
tmp |= (max_lw <<
sys/dev/drm/amd/amdgpu/cik.c
1454
tmp |= PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK |
sys/dev/drm/amd/amdgpu/cik.c
1457
WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, tmp);
sys/dev/drm/amd/amdgpu/cik.c
1473
tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
sys/dev/drm/amd/amdgpu/cik.c
1474
tmp |= PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;
sys/dev/drm/amd/amdgpu/cik.c
1475
WREG32_PCIE(ixPCIE_LC_CNTL4, tmp);
sys/dev/drm/amd/amdgpu/cik.c
1477
tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
sys/dev/drm/amd/amdgpu/cik.c
1478
tmp |= PCIE_LC_CNTL4__LC_REDO_EQ_MASK;
sys/dev/drm/amd/amdgpu/cik.c
1479
WREG32_PCIE(ixPCIE_LC_CNTL4, tmp);
sys/dev/drm/amd/amdgpu/cik.c
1505
tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
sys/dev/drm/amd/amdgpu/cik.c
1506
tmp &= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;
sys/dev/drm/amd/amdgpu/cik.c
1507
WREG32_PCIE(ixPCIE_LC_CNTL4, tmp);
sys/dev/drm/amd/amdgpu/cik.c
880
uint32_t tmp;
sys/dev/drm/amd/amdgpu/cik.c
882
tmp = RREG32(mmCONFIG_CNTL);
sys/dev/drm/amd/amdgpu/cik.c
884
tmp |= CONFIG_CNTL__VGA_DIS_MASK;
sys/dev/drm/amd/amdgpu/cik.c
886
tmp &= ~CONFIG_CNTL__VGA_DIS_MASK;
sys/dev/drm/amd/amdgpu/cik.c
887
WREG32(mmCONFIG_CNTL, tmp);
sys/dev/drm/amd/amdgpu/cik_ih.c
188
u32 wptr, tmp;
sys/dev/drm/amd/amdgpu/cik_ih.c
201
tmp = RREG32(mmIH_RB_CNTL);
sys/dev/drm/amd/amdgpu/cik_ih.c
202
tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
sys/dev/drm/amd/amdgpu/cik_ih.c
203
WREG32(mmIH_RB_CNTL, tmp);
sys/dev/drm/amd/amdgpu/cik_ih.c
379
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/cik_ih.c
381
if (tmp & SRBM_STATUS__IH_BUSY_MASK)
sys/dev/drm/amd/amdgpu/cik_ih.c
390
u32 tmp;
sys/dev/drm/amd/amdgpu/cik_ih.c
395
tmp = RREG32(mmSRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK;
sys/dev/drm/amd/amdgpu/cik_ih.c
396
if (!tmp)
sys/dev/drm/amd/amdgpu/cik_ih.c
408
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/cik_ih.c
410
if (tmp & SRBM_STATUS__IH_BUSY_MASK)
sys/dev/drm/amd/amdgpu/cik_ih.c
414
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/cik_ih.c
415
tmp |= srbm_soft_reset;
sys/dev/drm/amd/amdgpu/cik_ih.c
416
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/amd/amdgpu/cik_ih.c
417
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/cik_ih.c
418
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/cik_ih.c
422
tmp &= ~srbm_soft_reset;
sys/dev/drm/amd/amdgpu/cik_ih.c
423
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/cik_ih.c
424
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/cik_sdma.c
1059
u32 tmp = RREG32(mmSRBM_STATUS2);
sys/dev/drm/amd/amdgpu/cik_sdma.c
1061
if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
sys/dev/drm/amd/amdgpu/cik_sdma.c
1071
u32 tmp;
sys/dev/drm/amd/amdgpu/cik_sdma.c
1075
tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
sys/dev/drm/amd/amdgpu/cik_sdma.c
1078
if (!tmp)
sys/dev/drm/amd/amdgpu/cik_sdma.c
1089
u32 tmp = RREG32(mmSRBM_STATUS2);
sys/dev/drm/amd/amdgpu/cik_sdma.c
1091
if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
sys/dev/drm/amd/amdgpu/cik_sdma.c
1093
tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/drm/amd/amdgpu/cik_sdma.c
1094
tmp |= SDMA0_F32_CNTL__HALT_MASK;
sys/dev/drm/amd/amdgpu/cik_sdma.c
1095
WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
sys/dev/drm/amd/amdgpu/cik_sdma.c
1098
if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
sys/dev/drm/amd/amdgpu/cik_sdma.c
1100
tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/drm/amd/amdgpu/cik_sdma.c
1101
tmp |= SDMA0_F32_CNTL__HALT_MASK;
sys/dev/drm/amd/amdgpu/cik_sdma.c
1102
WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
sys/dev/drm/amd/amdgpu/cik_sdma.c
1107
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/cik_sdma.c
1108
tmp |= srbm_soft_reset;
sys/dev/drm/amd/amdgpu/cik_sdma.c
1109
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/amd/amdgpu/cik_sdma.c
1110
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/cik_sdma.c
1111
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/cik_sdma.c
1115
tmp &= ~srbm_soft_reset;
sys/dev/drm/amd/amdgpu/cik_sdma.c
1116
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/cik_sdma.c
1117
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/cik_sdma.c
617
u32 tmp;
sys/dev/drm/amd/amdgpu/cik_sdma.c
627
tmp = 0xCAFEDEAD;
sys/dev/drm/amd/amdgpu/cik_sdma.c
628
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/drm/amd/amdgpu/cik_sdma.c
644
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/drm/amd/amdgpu/cik_sdma.c
645
if (tmp == 0xDEADBEEF)
sys/dev/drm/amd/amdgpu/cik_sdma.c
654
ring->idx, tmp);
sys/dev/drm/amd/amdgpu/cik_sdma.c
676
u32 tmp = 0;
sys/dev/drm/amd/amdgpu/cik_sdma.c
687
tmp = 0xCAFEDEAD;
sys/dev/drm/amd/amdgpu/cik_sdma.c
688
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/drm/amd/amdgpu/cik_sdma.c
716
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/drm/amd/amdgpu/cik_sdma.c
717
if (tmp == 0xDEADBEEF) {
sys/dev/drm/amd/amdgpu/cik_sdma.c
721
DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
sys/dev/drm/amd/amdgpu/cz_ih.c
190
u32 wptr, tmp;
sys/dev/drm/amd/amdgpu/cz_ih.c
203
tmp = RREG32(mmIH_RB_CNTL);
sys/dev/drm/amd/amdgpu/cz_ih.c
204
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
sys/dev/drm/amd/amdgpu/cz_ih.c
205
WREG32(mmIH_RB_CNTL, tmp);
sys/dev/drm/amd/amdgpu/cz_ih.c
358
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/cz_ih.c
360
if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
sys/dev/drm/amd/amdgpu/cz_ih.c
369
u32 tmp;
sys/dev/drm/amd/amdgpu/cz_ih.c
374
tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/cz_ih.c
375
if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
sys/dev/drm/amd/amdgpu/cz_ih.c
386
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/cz_ih.c
388
if (tmp & SRBM_STATUS__IH_BUSY_MASK)
sys/dev/drm/amd/amdgpu/cz_ih.c
393
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/cz_ih.c
394
tmp |= srbm_soft_reset;
sys/dev/drm/amd/amdgpu/cz_ih.c
395
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/amd/amdgpu/cz_ih.c
396
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/cz_ih.c
397
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/cz_ih.c
401
tmp &= ~srbm_soft_reset;
sys/dev/drm/amd/amdgpu/cz_ih.c
402
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/cz_ih.c
403
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1022
u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1113
tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1114
WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1115
tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1116
tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1117
tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1118
WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1120
tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1121
WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1122
tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1123
tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1124
tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1125
WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1168
u32 offset, tmp;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1172
tmp = RREG32_AUDIO_ENDPT(offset,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1174
if (((tmp &
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1202
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1207
tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1208
tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1209
WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1220
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1241
tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1243
tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1246
tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1248
tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1252
ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1262
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1288
tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1290
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1293
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1296
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1299
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1302
ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1355
u32 tmp = 0;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1365
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1367
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1369
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1381
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1383
WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1465
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1467
tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1468
tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1469
WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1470
tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1471
tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1472
WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1474
tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1475
tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1476
WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1477
tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1478
tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1479
WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1481
tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1482
tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1483
WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1484
tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1485
tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1486
WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1522
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1532
tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1533
tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1535
WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1554
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1576
tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1577
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1578
WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1582
tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1589
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1590
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1595
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1596
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1601
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1602
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1607
WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1609
tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1610
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1611
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1612
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1613
WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1615
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1617
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1619
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1620
WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1622
tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1624
tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1625
WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1627
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1629
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1630
WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1634
tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1636
tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1638
tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1639
WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1641
tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1643
tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1644
WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1646
tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1649
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1652
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1654
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1655
WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1659
tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1660
tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1661
WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1663
tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1664
tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1665
WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1667
tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1668
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1669
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1670
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1671
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1672
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1673
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1674
WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1699
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1701
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1703
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1704
WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1706
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1707
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1708
WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1710
tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1712
tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1713
WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1836
u32 tmp, viewport_w, viewport_h;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1996
tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1997
tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1999
WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2017
tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2019
tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2021
tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2022
WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2075
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2077
tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2079
tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2081
tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2082
WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2092
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2096
tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2097
tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2098
tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2099
WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2101
tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2102
tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2103
WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2105
tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2106
tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2107
WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2109
tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2110
tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2111
tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2112
WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2138
tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2139
tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2140
tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2141
tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2142
WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2144
tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2145
tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2146
tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2147
WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2149
tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2150
tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2151
tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2152
WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2154
tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2155
tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2156
tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2157
WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2164
tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2165
tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2166
WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2279
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2281
tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2282
tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2283
WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2290
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2297
tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2298
tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2299
tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2300
WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
236
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
239
tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
240
tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
242
WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2920
u32 srbm_soft_reset = 0, tmp;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2927
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2928
tmp |= srbm_soft_reset;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2929
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2930
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2931
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2935
tmp &= ~srbm_soft_reset;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2936
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2937
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
300
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3008
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3017
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3018
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3019
WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3022
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3023
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3024
WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
306
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
308
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
310
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
311
WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3160
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3167
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3168
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3169
WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3175
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3182
tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3183
tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3184
WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3190
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3197
tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3198
tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3199
WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
326
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
341
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
342
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
343
WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
347
tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
348
tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
349
WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
351
tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
352
tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
355
tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
358
WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
378
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
386
tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
387
tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
388
WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
404
u32 i, j, tmp;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
407
tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
408
if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
sys/dev/drm/amd/amdgpu/dce_v10_0.c
417
tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
418
if (tmp != crtc_status[i])
sys/dev/drm/amd/amdgpu/dce_v10_0.c
433
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
436
tmp = RREG32(mmVGA_HDP_CONTROL);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
438
tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
440
tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
441
WREG32(mmVGA_HDP_CONTROL, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
444
tmp = RREG32(mmVGA_RENDER_CONTROL);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
446
tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
448
tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
449
WREG32(mmVGA_RENDER_CONTROL, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
471
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
482
tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
483
tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
484
WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
499
u32 tmp = 0;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
524
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
525
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
526
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
527
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
529
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
530
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
536
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
537
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
538
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
539
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
540
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
542
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
543
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
549
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
550
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
551
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
552
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
553
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
555
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
556
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
564
WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
585
u32 tmp, buffer_alloc, i, mem_cfg;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
615
tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
616
tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
617
WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
619
tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
620
tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
621
WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
624
tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
625
if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
sys/dev/drm/amd/amdgpu/dce_v10_0.c
657
u32 tmp = RREG32(mmMC_SHARED_CHMAP);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
659
switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
sys/dev/drm/amd/amdgpu/dce_v10_0.c
889
u32 tmp, dmif_size = 12288;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
908
tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
909
tmp = min(dfixed_trunc(a), tmp);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
911
lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1048
u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1139
tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1140
WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1141
tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1142
tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1143
tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1144
WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1146
tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1147
WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1148
tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1149
tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1150
tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1151
WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1194
u32 offset, tmp;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1198
tmp = RREG32_AUDIO_ENDPT(offset,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1200
if (((tmp &
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1228
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1233
tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1234
tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1235
WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1246
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1267
tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1269
tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1272
tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1274
tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1278
ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1288
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1314
tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1316
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1319
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1322
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1325
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1328
ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1381
u32 tmp = 0;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1391
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1393
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1395
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1407
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1409
WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1507
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1509
tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1510
tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1511
WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1512
tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1513
tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1514
WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1516
tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1517
tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1518
WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1519
tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1520
tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1521
WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1523
tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1524
tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1525
WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1526
tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1527
tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1528
WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1564
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1574
tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1575
tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1577
WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1596
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1618
tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1619
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1620
WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1624
tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1631
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1632
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1637
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1638
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1643
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1644
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1649
WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1651
tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1652
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1653
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1654
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1655
WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1657
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1659
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1661
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1662
WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1664
tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1666
tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1667
WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1669
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1671
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1672
WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1676
tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1678
tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1680
tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1681
WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1683
tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1685
tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1686
WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1688
tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1691
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1694
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1696
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1697
WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1701
tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1702
tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1703
WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1705
tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1706
tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1707
WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1709
tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1710
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1711
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1712
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1713
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1714
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1715
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1716
WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1741
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1743
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1745
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1746
WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1748
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1749
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1750
WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1752
tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1754
tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1755
WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1878
u32 tmp, viewport_w, viewport_h;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2038
tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2039
tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2041
WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2059
tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2061
tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2063
tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2064
WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2117
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2119
tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2121
tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2123
tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2124
WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2134
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2138
tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2139
tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2140
WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2142
tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2143
tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2144
WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2146
tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2147
tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2148
WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2174
tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2175
tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2176
tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2177
tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2178
WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2180
tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2181
tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2182
WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2184
tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2185
tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2186
WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2188
tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2189
tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2190
WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2197
tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2198
tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2199
WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2358
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2360
tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2361
tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2362
WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2369
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2376
tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2377
tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2378
tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2379
WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
254
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
257
tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
258
tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
260
WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3046
u32 srbm_soft_reset = 0, tmp;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3053
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3054
tmp |= srbm_soft_reset;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3055
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3056
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3057
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3061
tmp &= ~srbm_soft_reset;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3062
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3063
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3134
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3143
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3144
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3145
WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3148
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3149
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3150
WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
318
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
324
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
326
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
328
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3286
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
329
WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3293
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3294
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3295
WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3301
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3308
tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3309
tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3310
WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3316
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3323
tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3324
tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3325
WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
344
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
359
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
360
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
361
WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
365
tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
366
tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
367
WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
369
tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
370
tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
373
tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
376
WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
395
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
403
tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
404
tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
405
WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
420
u32 i, j, tmp;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
423
tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
424
if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
sys/dev/drm/amd/amdgpu/dce_v11_0.c
433
tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
434
if (tmp != crtc_status[i])
sys/dev/drm/amd/amdgpu/dce_v11_0.c
449
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
452
tmp = RREG32(mmVGA_HDP_CONTROL);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
454
tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
456
tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
457
WREG32(mmVGA_HDP_CONTROL, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
460
tmp = RREG32(mmVGA_RENDER_CONTROL);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
462
tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
464
tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
465
WREG32(mmVGA_RENDER_CONTROL, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
497
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
508
tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
509
tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
510
WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
525
u32 tmp = 0;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
550
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
551
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
552
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
553
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
555
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
556
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
562
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
563
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
564
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
565
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
566
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
568
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
569
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
575
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
576
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
577
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
578
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
579
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
581
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
582
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
590
WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
611
u32 tmp, buffer_alloc, i, mem_cfg;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
641
tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
642
tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
643
WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
645
tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
646
tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
647
WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
650
tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
651
if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
sys/dev/drm/amd/amdgpu/dce_v11_0.c
683
u32 tmp = RREG32(mmMC_SHARED_CHMAP);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
685
switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
sys/dev/drm/amd/amdgpu/dce_v11_0.c
915
u32 tmp, dmif_size = 12288;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
934
tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
935
tmp = min(dfixed_trunc(a), tmp);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
937
lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1048
tmp = wm_mask;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1049
tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1050
tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1051
WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1056
tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1057
tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1058
tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1059
WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1105
u32 offset, tmp;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1109
tmp = RREG32_AUDIO_ENDPT(offset,
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1111
if (((tmp &
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1158
u32 tmp = 0, offset;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1179
tmp =
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1185
tmp =
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1192
tmp =
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1198
tmp =
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1205
WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1215
u32 offset, tmp;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1243
tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1244
tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK |
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1247
tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1249
tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1251
tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1252
WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
245
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
251
tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
253
tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
255
tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
256
WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
271
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
279
tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
280
tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2808
u32 srbm_soft_reset = 0, tmp;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
281
WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2815
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2816
tmp |= srbm_soft_reset;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2817
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2818
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2819
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2823
tmp &= ~srbm_soft_reset;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2824
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2825
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
290
tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
291
tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
292
WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
313
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
3130
uint32_t disp_int, mask, tmp;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
3143
tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
3144
tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
3145
WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
321
tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
322
tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
338
u32 i, j, tmp;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
350
tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
351
if (tmp != crtc_status[i])
sys/dev/drm/amd/amdgpu/dce_v8_0.c
366
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
369
tmp = RREG32(mmVGA_HDP_CONTROL);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
371
tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
373
tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
374
WREG32(mmVGA_HDP_CONTROL, tmp);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
377
tmp = RREG32(mmVGA_RENDER_CONTROL);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
379
tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
381
tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
382
WREG32(mmVGA_RENDER_CONTROL, tmp);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
411
u32 tmp;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
422
tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
423
tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
424
WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
439
u32 tmp = 0;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
464
tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
sys/dev/drm/amd/amdgpu/dce_v8_0.c
469
tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
sys/dev/drm/amd/amdgpu/dce_v8_0.c
475
tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
sys/dev/drm/amd/amdgpu/dce_v8_0.c
481
tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
sys/dev/drm/amd/amdgpu/dce_v8_0.c
487
tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
sys/dev/drm/amd/amdgpu/dce_v8_0.c
493
tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
sys/dev/drm/amd/amdgpu/dce_v8_0.c
501
WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
522
u32 tmp, buffer_alloc, i;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
534
tmp = 1;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
537
tmp = 2;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
540
tmp = 0;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
544
tmp = 0;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
548
tmp = 1;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
553
(tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) |
sys/dev/drm/amd/amdgpu/dce_v8_0.c
566
switch (tmp) {
sys/dev/drm/amd/amdgpu/dce_v8_0.c
592
u32 tmp = RREG32(mmMC_SHARED_CHMAP);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
594
switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
sys/dev/drm/amd/amdgpu/dce_v8_0.c
824
u32 tmp, dmif_size = 12288;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
843
tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
844
tmp = min(dfixed_trunc(a), tmp);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
846
lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
957
u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
sys/dev/drm/amd/amdgpu/df_v1_7.c
100
tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
sys/dev/drm/amd/amdgpu/df_v1_7.c
101
if (tmp & DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY)
sys/dev/drm/amd/amdgpu/df_v1_7.c
39
u32 tmp;
sys/dev/drm/amd/amdgpu/df_v1_7.c
42
tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);
sys/dev/drm/amd/amdgpu/df_v1_7.c
43
tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
sys/dev/drm/amd/amdgpu/df_v1_7.c
44
WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);
sys/dev/drm/amd/amdgpu/df_v1_7.c
52
u32 tmp;
sys/dev/drm/amd/amdgpu/df_v1_7.c
54
tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
sys/dev/drm/amd/amdgpu/df_v1_7.c
55
tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
sys/dev/drm/amd/amdgpu/df_v1_7.c
56
tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
sys/dev/drm/amd/amdgpu/df_v1_7.c
58
return tmp;
sys/dev/drm/amd/amdgpu/df_v1_7.c
73
u32 tmp;
sys/dev/drm/amd/amdgpu/df_v1_7.c
79
tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
sys/dev/drm/amd/amdgpu/df_v1_7.c
80
tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
sys/dev/drm/amd/amdgpu/df_v1_7.c
81
tmp |= DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY;
sys/dev/drm/amd/amdgpu/df_v1_7.c
82
WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
sys/dev/drm/amd/amdgpu/df_v1_7.c
84
tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
sys/dev/drm/amd/amdgpu/df_v1_7.c
85
tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
sys/dev/drm/amd/amdgpu/df_v1_7.c
86
tmp |= DF_V1_7_MGCG_DISABLE;
sys/dev/drm/amd/amdgpu/df_v1_7.c
87
WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
sys/dev/drm/amd/amdgpu/df_v1_7.c
97
u32 tmp;
sys/dev/drm/amd/amdgpu/df_v3_6.c
100
u32 tmp;
sys/dev/drm/amd/amdgpu/df_v3_6.c
103
tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
sys/dev/drm/amd/amdgpu/df_v3_6.c
104
if (tmp & DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY)
sys/dev/drm/amd/amdgpu/df_v3_6.c
40
u32 tmp;
sys/dev/drm/amd/amdgpu/df_v3_6.c
43
tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);
sys/dev/drm/amd/amdgpu/df_v3_6.c
44
tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
sys/dev/drm/amd/amdgpu/df_v3_6.c
45
WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);
sys/dev/drm/amd/amdgpu/df_v3_6.c
53
u32 tmp;
sys/dev/drm/amd/amdgpu/df_v3_6.c
55
tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0);
sys/dev/drm/amd/amdgpu/df_v3_6.c
56
tmp &= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;
sys/dev/drm/amd/amdgpu/df_v3_6.c
57
tmp >>= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
sys/dev/drm/amd/amdgpu/df_v3_6.c
59
return tmp;
sys/dev/drm/amd/amdgpu/df_v3_6.c
76
u32 tmp;
sys/dev/drm/amd/amdgpu/df_v3_6.c
82
tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
sys/dev/drm/amd/amdgpu/df_v3_6.c
83
tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
sys/dev/drm/amd/amdgpu/df_v3_6.c
84
tmp |= DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY;
sys/dev/drm/amd/amdgpu/df_v3_6.c
85
WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
sys/dev/drm/amd/amdgpu/df_v3_6.c
87
tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
sys/dev/drm/amd/amdgpu/df_v3_6.c
88
tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
sys/dev/drm/amd/amdgpu/df_v3_6.c
89
tmp |= DF_V3_6_MGCG_DISABLE;
sys/dev/drm/amd/amdgpu/df_v3_6.c
90
WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1899
u32 tmp;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1966
tmp = RREG32(mmSPI_CONFIG_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1967
tmp |= 0x03000000;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1968
WREG32(mmSPI_CONFIG_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1974
tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1975
tmp |= 0x00000400;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1976
WREG32(mmDB_DEBUG2, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1978
tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1979
tmp |= 0x00020200;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1980
WREG32(mmDB_DEBUG3, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1982
tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1983
tmp |= 0x00018208;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1984
WREG32(mmCB_HW_CONTROL, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2015
tmp = RREG32(mmSPI_ARB_PRIORITY);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2016
tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2017
tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2018
tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2019
tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2020
WREG32(mmSPI_ARB_PRIORITY, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2062
uint32_t tmp = 0;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2084
tmp = RREG32(scratch);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2085
if (tmp == 0xDEADBEEF)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2093
ring->idx, scratch, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2315
uint32_t tmp = 0;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2348
tmp = RREG32(scratch);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2349
if (tmp == 0xDEADBEEF) {
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2354
scratch, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2567
u32 tmp;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2588
tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2590
tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2592
WREG32(mmCP_RB0_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2595
WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2608
WREG32(mmCP_RB0_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2846
u32 tmp;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2863
tmp = RREG32(mmCP_HPD_EOP_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2864
tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2865
tmp |= order_base_2(GFX7_MEC_HPD_SIZE / 8);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2866
WREG32(mmCP_HPD_EOP_CONTROL, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3019
uint32_t tmp;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3027
tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3028
tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3029
WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3084
u32 tmp;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3088
tmp = RREG32(mmCP_CPF_DEBUG);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3089
tmp |= (1 << 23);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3090
WREG32(mmCP_CPF_DEBUG, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3142
u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3145
tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3148
tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3150
WREG32(mmCP_INT_CNTL_RING0, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3377
u32 tmp;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3379
tmp = RREG32(mmRLC_LB_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3381
tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3383
tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3384
WREG32(mmRLC_LB_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3419
u32 tmp;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3421
tmp = RREG32(mmRLC_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3422
if (tmp != rlc)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3452
u32 tmp, i, mask;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3454
tmp = 0x1 | (1 << 1);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3455
WREG32(mmRLC_GPR_REG2, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3474
u32 tmp;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3476
tmp = 0x1 | (0 << 1);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3477
WREG32(mmRLC_GPR_REG2, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3514
u32 tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3516
tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3517
WREG32(mmGRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3519
tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3520
WREG32(mmGRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3538
u32 tmp;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3552
tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3553
WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3593
u32 data, orig, tmp, tmp2;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3600
tmp = gfx_v7_0_halt_rlc(adev);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3612
gfx_v7_0_update_rlc(adev, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3636
u32 data, orig, tmp = 0;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3654
tmp = gfx_v7_0_halt_rlc(adev);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3665
gfx_v7_0_update_rlc(adev, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3705
tmp = gfx_v7_0_halt_rlc(adev);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3715
gfx_v7_0_update_rlc(adev, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3917
u32 tmp;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3921
tmp = RREG32(mmRLC_MAX_PG_CU);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3922
tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3923
tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3924
WREG32(mmRLC_MAX_PG_CU, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4332
u32 tmp;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4415
tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4416
dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4417
dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4419
tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4420
dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4421
dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4440
tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4441
adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4682
u32 tmp;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4687
tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4689
if (!tmp)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4699
u32 tmp;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4703
tmp = RREG32(mmGRBM_STATUS);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4704
if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4713
if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4719
tmp = RREG32(mmGRBM_STATUS2);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4720
if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4724
tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4725
if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4743
tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4744
tmp |= grbm_soft_reset;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4745
dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4746
WREG32(mmGRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4747
tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4751
tmp &= ~grbm_soft_reset;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4752
WREG32(mmGRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4753
tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4757
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4758
tmp |= srbm_soft_reset;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4759
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4760
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4761
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4765
tmp &= ~srbm_soft_reset;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4766
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4767
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1115
tmp = (unsigned int *)((uintptr_t)rlc_hdr +
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1118
adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1122
tmp = (unsigned int *)((uintptr_t)rlc_hdr +
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1125
adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1623
u32 tmp;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1635
tmp = RREG32(mmGB_EDC_MODE);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1760
tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1761
tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1762
WREG32(mmGB_EDC_MODE, tmp);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1764
tmp = RREG32(mmCC_GC_EDC_CONFIG);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1765
tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1766
WREG32(mmCC_GC_EDC_CONFIG, tmp);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1785
u32 tmp;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1931
tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1932
dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1933
dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1935
tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1936
dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1937
dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1956
tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1957
adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3832
u32 tmp, sh_static_mem_cfg;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3860
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3861
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3862
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3864
WREG32(mmSH_MEM_CONFIG, tmp);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3867
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3868
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3869
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3871
WREG32(mmSH_MEM_CONFIG, tmp);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3872
tmp = adev->gmc.shared_aperture_start >> 48;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3873
WREG32(mmSH_MEM_BASES, tmp);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3901
tmp = RREG32(mmSPI_ARB_PRIORITY);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3902
tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3903
tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3904
tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3905
tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3906
WREG32(mmSPI_ARB_PRIORITY, tmp);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3953
u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3955
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3956
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3957
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3958
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3960
WREG32(mmCP_INT_CNTL_RING0, tmp);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4189
u32 tmp = RREG32(mmCP_ME_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4192
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4193
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4194
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4196
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4197
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4198
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4202
WREG32(mmCP_ME_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4300
u32 tmp;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4305
tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4308
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4310
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4312
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4315
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4318
WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4323
tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4326
WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4335
u32 tmp;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4349
tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4350
tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4351
tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4352
tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4354
tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4356
WREG32(mmCP_RB0_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4359
WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4372
WREG32(mmCP_RB0_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4408
uint32_t tmp;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4412
tmp = RREG32(mmRLC_CP_SCHEDULERS);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4413
tmp &= 0xffffff00;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4414
tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4415
WREG32(mmRLC_CP_SCHEDULERS, tmp);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4416
tmp |= 0x80;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4417
WREG32(mmRLC_CP_SCHEDULERS, tmp);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4510
uint32_t tmp;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4528
tmp = RREG32(mmCP_HQD_EOP_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4529
tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4532
mqd->cp_hqd_eop_control = tmp;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4535
tmp = REG_SET_FIELD(RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL),
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4540
mqd->cp_hqd_pq_doorbell_control = tmp;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4547
tmp = RREG32(mmCP_MQD_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4548
tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4549
mqd->cp_mqd_control = tmp;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4557
tmp = RREG32(mmCP_HQD_PQ_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4558
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4560
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4563
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4565
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4566
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4567
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4568
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4569
mqd->cp_hqd_pq_control = tmp;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4582
tmp = 0;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4585
tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4586
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4589
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4591
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4593
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4597
mqd->cp_hqd_pq_doorbell_control = tmp;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4607
tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4608
tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4609
mqd->cp_hqd_persistent_state = tmp;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4612
tmp = RREG32(mmCP_HQD_IB_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4613
tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4614
tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MTYPE, 3);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4615
mqd->cp_hqd_ib_control = tmp;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4617
tmp = RREG32(mmCP_HQD_IQ_TIMER);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4618
tmp = REG_SET_FIELD(tmp, CP_HQD_IQ_TIMER, MTYPE, 3);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4619
mqd->cp_hqd_iq_timer = tmp;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4621
tmp = RREG32(mmCP_HQD_CTX_SAVE_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4622
tmp = REG_SET_FIELD(tmp, CP_HQD_CTX_SAVE_CONTROL, MTYPE, 3);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4623
mqd->cp_hqd_ctx_save_control = tmp;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5005
u32 tmp;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5008
tmp = RREG32(mmGRBM_STATUS);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5009
if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5025
tmp = RREG32(mmGRBM_STATUS2);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5026
if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5030
if (REG_GET_FIELD(tmp, GRBM_STATUS2, CPF_BUSY) ||
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5031
REG_GET_FIELD(tmp, GRBM_STATUS2, CPC_BUSY) ||
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5032
REG_GET_FIELD(tmp, GRBM_STATUS2, CPG_BUSY)) {
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5044
tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5045
if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5048
if (REG_GET_FIELD(tmp, SRBM_STATUS, SEM_BUSY))
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5109
u32 tmp;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5119
tmp = RREG32(mmGMCON_DEBUG);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5120
tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5121
tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5122
WREG32(mmGMCON_DEBUG, tmp);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5127
tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5128
tmp |= grbm_soft_reset;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5129
dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5130
WREG32(mmGRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5131
tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5135
tmp &= ~grbm_soft_reset;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5136
WREG32(mmGRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5137
tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5141
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5142
tmp |= srbm_soft_reset;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5143
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5144
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5145
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5149
tmp &= ~srbm_soft_reset;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5150
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5151
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5155
tmp = RREG32(mmGMCON_DEBUG);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5156
tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5157
tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5158
WREG32(mmGMCON_DEBUG, tmp);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6263
int pipe_num, tmp, reg;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6273
tmp = RREG32(reg);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6274
tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6275
WREG32(reg, tmp);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
837
uint32_t tmp = 0;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
860
tmp = RREG32(scratch);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
861
if (tmp == 0xDEADBEEF)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
870
ring->idx, scratch, tmp);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
885
uint32_t tmp;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
923
tmp = adev->wb.wb[index];
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
924
if (tmp == 0xDEADBEEF) {
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
970
unsigned int *tmp = NULL, i;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1963
u32 tmp;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1981
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1983
WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1986
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1988
WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1989
tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1991
tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1993
WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2063
u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2065
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2066
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2067
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2068
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2070
WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2131
u32 tmp = 0;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2152
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2153
tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2154
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2535
u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2537
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2538
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2539
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2544
WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2610
int r, i, tmp;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2657
tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2659
amdgpu_ring_write(ring, tmp);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2670
u32 tmp;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2683
tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2684
tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2686
tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2688
WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2705
WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2711
tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2713
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2715
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2718
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2720
WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2722
tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2724
WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2758
u32 tmp;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2771
tmp = 0;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2772
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2773
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2774
WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2798
uint32_t tmp;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2802
tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2803
tmp &= 0xffffff00;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2804
tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2805
WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2806
tmp |= 0x80;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2807
WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2885
uint32_t tmp;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2907
tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2908
tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2911
mqd->cp_hqd_eop_control = tmp;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2914
tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2917
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2919
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2921
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2923
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2926
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2930
mqd->cp_hqd_pq_doorbell_control = tmp;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2944
tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2945
tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2946
mqd->cp_mqd_control = tmp;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2954
tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2955
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2957
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2960
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2962
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2963
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2964
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2965
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2966
mqd->cp_hqd_pq_control = tmp;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2979
tmp = 0;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2982
tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2983
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2986
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2988
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2990
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2994
mqd->cp_hqd_pq_doorbell_control = tmp;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3003
tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3004
tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3005
mqd->cp_hqd_persistent_state = tmp;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3008
tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3009
tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3010
mqd->cp_hqd_ib_control = tmp;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3482
u32 tmp;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3486
tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3487
if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3499
if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3505
tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3506
if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3522
tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3523
tmp |= grbm_soft_reset;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3524
dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3525
WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3526
tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3530
tmp &= ~grbm_soft_reset;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3531
WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3532
tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
394
uint32_t tmp = 0;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
417
tmp = RREG32(scratch);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
418
if (tmp == 0xDEADBEEF)
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
4203
int pipe_num, tmp, reg;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
4213
tmp = RREG32(reg);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
4214
tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
4215
WREG32(reg, tmp);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
427
ring->idx, scratch, tmp);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
442
uint32_t tmp;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
480
tmp = adev->wb.wb[index];
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
481
if (tmp == 0xDEADBEEF) {
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
601
unsigned int *tmp = NULL;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
703
tmp = (unsigned int *)((uintptr_t)rlc_hdr +
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
706
adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
710
tmp = (unsigned int *)((uintptr_t)rlc_hdr +
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
713
adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
111
uint32_t tmp;
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
114
tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
116
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
117
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
118
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
120
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
122
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
123
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
125
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
127
WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
132
uint32_t tmp;
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
135
tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
136
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
137
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
139
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
141
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
142
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
143
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
144
WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
146
tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
147
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
148
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
149
WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
151
tmp = mmVM_L2_CNTL3_DEFAULT;
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
153
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
154
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
157
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
158
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
161
WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
163
tmp = mmVM_L2_CNTL4_DEFAULT;
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
164
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
165
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
166
WREG32_SOC15(GC, 0, mmVM_L2_CNTL4, tmp);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
171
uint32_t tmp;
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
173
tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
174
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
175
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
176
WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
199
uint32_t tmp;
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
210
tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
211
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
212
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
214
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
216
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
219
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
221
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
223
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
225
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
227
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
229
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
233
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
235
WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
287
u32 tmp;
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
295
tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
296
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
297
tmp = REG_SET_FIELD(tmp,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
301
WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
317
u32 tmp;
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
318
tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
319
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
321
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
323
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
325
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
327
tmp = REG_SET_FIELD(tmp,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
331
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
333
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
335
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
337
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
339
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
341
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
344
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
346
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
349
WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1074
u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1076
tmp <<= 22;
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1077
adev->vm_manager.vram_base_offset = tmp;
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
108
u32 tmp;
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
111
tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
112
tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
113
WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
115
tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
116
tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1168
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
117
WREG32(mmBIF_FB_EN, tmp);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1170
if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1180
u32 tmp;
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1185
tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1190
if (!tmp)
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1202
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1204
if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1208
if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1222
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1223
tmp |= srbm_soft_reset;
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1224
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1225
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1226
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1230
tmp &= ~srbm_soft_reset;
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1231
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1232
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1249
u32 tmp;
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1260
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1261
tmp &= ~bits;
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1262
WREG32(mmVM_CONTEXT0_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1264
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1265
tmp &= ~bits;
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1266
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1270
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1271
tmp |= bits;
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1272
WREG32(mmVM_CONTEXT0_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1274
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1275
tmp |= bits;
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1276
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
259
u32 tmp;
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
277
tmp = RREG32(mmVGA_HDP_CONTROL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
278
tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
279
WREG32(mmVGA_HDP_CONTROL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
282
tmp = RREG32(mmVGA_RENDER_CONTROL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
283
tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
284
WREG32(mmVGA_RENDER_CONTROL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
302
tmp = RREG32(mmHDP_MISC_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
303
tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
304
WREG32(mmHDP_MISC_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
306
tmp = RREG32(mmHDP_HOST_PATH_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
307
WREG32(mmHDP_HOST_PATH_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
325
u32 tmp;
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
329
tmp = RREG32(mmMC_ARB_RAMCFG);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
330
if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
335
tmp = RREG32(mmMC_SHARED_CHMAP);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
336
switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
517
u32 tmp;
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
519
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
520
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
522
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
524
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
526
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
528
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
530
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
532
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
543
uint32_t tmp;
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
550
tmp = RREG32(mmVM_PRT_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
551
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
553
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
555
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
557
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
559
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
561
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
563
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
565
WREG32(mmVM_PRT_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
607
u32 tmp, field;
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
620
tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
621
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
622
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
623
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
624
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
625
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
626
WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
628
tmp = RREG32(mmVM_L2_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
629
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
630
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
631
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
632
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
633
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
634
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
635
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
636
WREG32(mmVM_L2_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
637
tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
638
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
639
WREG32(mmVM_L2_CNTL2, tmp);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
642
tmp = RREG32(mmVM_L2_CNTL3);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
643
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
644
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
645
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
646
WREG32(mmVM_L2_CNTL3, tmp);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
654
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
655
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
656
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
657
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
658
WREG32(mmVM_CONTEXT0_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
684
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
685
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
686
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
687
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
689
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
696
tmp = RREG32(mmCHUB_CONTROL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
697
tmp &= ~BYPASS_VM;
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
698
WREG32(mmCHUB_CONTROL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
735
u32 tmp;
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
741
tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
742
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
743
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
744
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
745
WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
747
tmp = RREG32(mmVM_L2_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
748
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
749
WREG32(mmVM_L2_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
989
u32 tmp = RREG32(mmMC_SEQ_MISC0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
990
tmp &= MC_SEQ_MISC0__MT__MASK;
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
991
adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1109
u32 tmp;
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1113
tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1115
tmp = RREG32(mmMC_SEQ_MISC0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1116
tmp &= MC_SEQ_MISC0__MT__MASK;
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1117
adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1200
u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1202
tmp <<= 22;
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1203
adev->vm_manager.vram_base_offset = tmp;
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1302
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1304
if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1314
u32 tmp;
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1319
tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1325
if (!tmp)
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1337
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1339
if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1343
if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1383
u32 tmp;
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1385
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1386
tmp |= srbm_soft_reset;
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1387
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1388
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1389
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1393
tmp &= ~srbm_soft_reset;
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1394
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1395
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1420
u32 tmp;
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1432
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1433
tmp &= ~bits;
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1434
WREG32(mmVM_CONTEXT0_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1436
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1437
tmp &= ~bits;
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1438
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1442
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1443
tmp |= bits;
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1444
WREG32(mmVM_CONTEXT0_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1446
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1447
tmp |= bits;
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1448
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
196
u32 tmp;
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
199
tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
200
tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
201
WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
203
tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
204
tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
205
WREG32(mmBIF_FB_EN, tmp);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
450
u32 tmp;
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
468
tmp = RREG32(mmVGA_HDP_CONTROL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
469
tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
470
WREG32(mmVGA_HDP_CONTROL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
473
tmp = RREG32(mmVGA_RENDER_CONTROL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
474
tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
475
WREG32(mmVGA_RENDER_CONTROL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
486
tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16;
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
487
tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
488
WREG32(mmMC_VM_FB_LOCATION, tmp);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
504
tmp = RREG32(mmHDP_MISC_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
505
tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
506
WREG32(mmHDP_MISC_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
508
tmp = RREG32(mmHDP_HOST_PATH_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
509
WREG32(mmHDP_HOST_PATH_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
527
u32 tmp;
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
531
tmp = RREG32(mmMC_ARB_RAMCFG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
532
if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
537
tmp = RREG32(mmMC_SHARED_CHMAP);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
538
switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
742
u32 tmp;
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
744
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
745
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
747
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
749
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
751
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
753
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
755
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
757
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
759
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
770
u32 tmp;
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
777
tmp = RREG32(mmVM_PRT_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
778
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
780
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
782
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
784
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
786
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
788
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
790
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
792
WREG32(mmVM_PRT_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
834
u32 tmp, field;
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
847
tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
848
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
849
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
850
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
851
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
852
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
853
WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
855
tmp = RREG32(mmVM_L2_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
856
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
857
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
858
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
859
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
860
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
861
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
862
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
863
WREG32(mmVM_L2_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
864
tmp = RREG32(mmVM_L2_CNTL2);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
865
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
866
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
867
WREG32(mmVM_L2_CNTL2, tmp);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
870
tmp = RREG32(mmVM_L2_CNTL3);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
871
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
872
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
873
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
874
WREG32(mmVM_L2_CNTL3, tmp);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
876
tmp = RREG32(mmVM_L2_CNTL4);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
877
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
878
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
879
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
880
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
881
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
882
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
883
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
884
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
885
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
886
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
887
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
888
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
889
WREG32(mmVM_L2_CNTL4, tmp);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
897
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
898
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
899
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
900
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
901
WREG32(mmVM_CONTEXT0_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
927
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
928
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
929
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
930
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
931
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
932
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
933
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
934
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
935
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
936
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
937
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
939
WREG32(mmVM_CONTEXT1_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
979
u32 tmp;
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
985
tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
986
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
987
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
988
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
989
WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
991
tmp = RREG32(mmVM_L2_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
992
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
993
WREG32(mmVM_L2_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
1091
u32 tmp;
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
1123
tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
1124
WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
208
u32 tmp, reg, bits, i, j;
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
224
tmp = RREG32(reg);
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
225
tmp &= ~bits;
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
226
WREG32(reg, tmp);
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
235
tmp = RREG32(reg);
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
236
tmp |= bits;
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
237
WREG32(reg, tmp);
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
384
u32 tmp = gmc_v9_0_get_invalidate_req(vmid);
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
390
hub->vm_inv_eng0_ack + eng, tmp, 1 << vmid);
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
397
WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
401
tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
402
tmp &= 1 << vmid;
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
403
if (tmp)
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
414
tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
415
tmp &= 1 << vmid;
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
416
if (tmp)
sys/dev/drm/amd/amdgpu/iceland_ih.c
190
u32 wptr, tmp;
sys/dev/drm/amd/amdgpu/iceland_ih.c
203
tmp = RREG32(mmIH_RB_CNTL);
sys/dev/drm/amd/amdgpu/iceland_ih.c
204
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
sys/dev/drm/amd/amdgpu/iceland_ih.c
205
WREG32(mmIH_RB_CNTL, tmp);
sys/dev/drm/amd/amdgpu/iceland_ih.c
358
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/iceland_ih.c
360
if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
sys/dev/drm/amd/amdgpu/iceland_ih.c
369
u32 tmp;
sys/dev/drm/amd/amdgpu/iceland_ih.c
374
tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/iceland_ih.c
375
if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
sys/dev/drm/amd/amdgpu/iceland_ih.c
386
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/iceland_ih.c
388
if (tmp & SRBM_STATUS__IH_BUSY_MASK)
sys/dev/drm/amd/amdgpu/iceland_ih.c
393
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/iceland_ih.c
394
tmp |= srbm_soft_reset;
sys/dev/drm/amd/amdgpu/iceland_ih.c
395
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/amd/amdgpu/iceland_ih.c
396
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/iceland_ih.c
397
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/iceland_ih.c
401
tmp &= ~srbm_soft_reset;
sys/dev/drm/amd/amdgpu/iceland_ih.c
402
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/iceland_ih.c
403
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/kv_dpm.c
1436
u16 tmp;
sys/dev/drm/amd/amdgpu/kv_dpm.c
1438
tmp = 45;
sys/dev/drm/amd/amdgpu/kv_dpm.c
1439
pi->fps_high_t = cpu_to_be16(tmp);
sys/dev/drm/amd/amdgpu/kv_dpm.c
1446
tmp = 30;
sys/dev/drm/amd/amdgpu/kv_dpm.c
1447
pi->fps_low_t = cpu_to_be16(tmp);
sys/dev/drm/amd/amdgpu/kv_dpm.c
2526
u32 tmp;
sys/dev/drm/amd/amdgpu/kv_dpm.c
2537
tmp = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
sys/dev/drm/amd/amdgpu/kv_dpm.c
2538
tmp &= ~(CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK |
sys/dev/drm/amd/amdgpu/kv_dpm.c
2540
tmp |= ((49 + (high_temp / 1000)) << CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT) |
sys/dev/drm/amd/amdgpu/kv_dpm.c
2542
WREG32_SMC(ixCG_THERMAL_INT_CTRL, tmp);
sys/dev/drm/amd/amdgpu/kv_dpm.c
2874
u32 sclk, tmp;
sys/dev/drm/amd/amdgpu/kv_dpm.c
2881
tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) &
sys/dev/drm/amd/amdgpu/kv_dpm.c
2884
vddc = kv_convert_8bit_index_to_voltage(adev, (u16)tmp);
sys/dev/drm/amd/amdgpu/kv_dpm.c
586
u32 tmp;
sys/dev/drm/amd/amdgpu/kv_dpm.c
591
&tmp, pi->sram_end);
sys/dev/drm/amd/amdgpu/kv_dpm.c
594
pi->dpm_table_start = tmp;
sys/dev/drm/amd/amdgpu/kv_dpm.c
598
&tmp, pi->sram_end);
sys/dev/drm/amd/amdgpu/kv_dpm.c
601
pi->soft_regs_start = tmp;
sys/dev/drm/amd/amdgpu/kv_dpm.c
728
u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
sys/dev/drm/amd/amdgpu/kv_dpm.c
730
tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
sys/dev/drm/amd/amdgpu/kv_dpm.c
731
WREG32_SMC(ixGENERAL_PWRMGT, tmp);
sys/dev/drm/amd/amdgpu/kv_smc.c
36
u32 tmp = 0;
sys/dev/drm/amd/amdgpu/kv_smc.c
45
tmp = RREG32(mmSMC_RESP_0) & SMC_RESP_0__SMC_RESP_MASK;
sys/dev/drm/amd/amdgpu/kv_smc.c
47
if (tmp != 1) {
sys/dev/drm/amd/amdgpu/kv_smc.c
48
if (tmp == 0xFF)
sys/dev/drm/amd/amdgpu/kv_smc.c
50
else if (tmp == 0xFE)
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
123
tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
124
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
126
WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
131
uint32_t tmp;
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
134
tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
136
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
137
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
138
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
140
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
142
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
143
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
145
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
147
WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
152
uint32_t tmp;
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
155
tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
156
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
157
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
159
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
161
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
162
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
163
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
164
WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
166
tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
167
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
168
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
169
WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
172
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
173
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
176
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
177
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
181
tmp = mmVM_L2_CNTL4_DEFAULT;
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
182
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
183
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
184
WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
189
uint32_t tmp;
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
191
tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
192
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
193
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
194
WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL, tmp);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
218
uint32_t tmp;
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
229
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
230
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
231
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
233
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
235
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
238
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
240
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
242
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
244
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
246
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
248
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
252
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
254
WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i, tmp);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
319
u32 tmp;
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
327
tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
328
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
329
tmp = REG_SET_FIELD(tmp,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
333
WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
336
tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
337
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
338
WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
350
u32 tmp;
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
351
tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
352
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
354
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
356
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
358
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
360
tmp = REG_SET_FIELD(tmp,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
364
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
366
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
368
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
370
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
372
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
374
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
377
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
379
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
383
WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
84
uint32_t tmp;
sys/dev/drm/amd/amdgpu/mxgpu_ai.c
226
u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));
sys/dev/drm/amd/amdgpu/mxgpu_ai.c
228
tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_MAILBOX_INT_CNTL, ACK_INT_EN,
sys/dev/drm/amd/amdgpu/mxgpu_ai.c
230
WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);
sys/dev/drm/amd/amdgpu/mxgpu_ai.c
278
u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));
sys/dev/drm/amd/amdgpu/mxgpu_ai.c
280
tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_MAILBOX_INT_CNTL, VALID_INT_EN,
sys/dev/drm/amd/amdgpu/mxgpu_ai.c
282
WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);
sys/dev/drm/amd/amdgpu/mxgpu_vi.c
503
u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);
sys/dev/drm/amd/amdgpu/mxgpu_vi.c
505
tmp = REG_SET_FIELD(tmp, MAILBOX_INT_CNTL, ACK_INT_EN,
sys/dev/drm/amd/amdgpu/mxgpu_vi.c
507
WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
sys/dev/drm/amd/amdgpu/mxgpu_vi.c
533
u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);
sys/dev/drm/amd/amdgpu/mxgpu_vi.c
535
tmp = REG_SET_FIELD(tmp, MAILBOX_INT_CNTL, VALID_INT_EN,
sys/dev/drm/amd/amdgpu/mxgpu_vi.c
537
WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
100
u32 tmp = 0;
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
103
tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
104
REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
105
REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
113
WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp);
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
38
u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
40
tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
41
tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
43
return tmp;
sys/dev/drm/amd/amdgpu/nbio_v7_0.c
39
u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
sys/dev/drm/amd/amdgpu/nbio_v7_0.c
41
tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
sys/dev/drm/amd/amdgpu/nbio_v7_0.c
42
tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
sys/dev/drm/amd/amdgpu/nbio_v7_0.c
44
return tmp;
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
100
REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
108
WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp);
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
37
u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
39
tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
40
tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
42
return tmp;
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
95
u32 tmp = 0;
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
98
tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
99
REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
1000
tmp |= srbm_soft_reset;
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
1001
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
1002
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
1003
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
1007
tmp &= ~srbm_soft_reset;
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
1008
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
1009
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
549
u32 tmp;
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
559
tmp = 0xCAFEDEAD;
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
560
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
578
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
579
if (tmp == 0xDEADBEEF)
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
588
ring->idx, tmp);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
610
u32 tmp = 0;
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
621
tmp = 0xCAFEDEAD;
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
622
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
654
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
655
if (tmp == 0xDEADBEEF) {
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
659
DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
951
u32 tmp = RREG32(mmSRBM_STATUS2);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
953
if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
963
u32 tmp;
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
967
tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
970
if (!tmp)
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
981
u32 tmp = RREG32(mmSRBM_STATUS2);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
983
if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
985
tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
986
tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
987
WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
990
if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
992
tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
993
tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
994
WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
999
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1237
u32 tmp = RREG32(mmSRBM_STATUS2);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1239
if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1249
u32 tmp;
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1253
tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1256
if (!tmp)
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1267
u32 tmp = RREG32(mmSRBM_STATUS2);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1269
if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) ||
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1270
(tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) {
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1326
u32 tmp;
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1334
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1335
tmp |= srbm_soft_reset;
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1336
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1337
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1338
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1342
tmp &= ~srbm_soft_reset;
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1343
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1344
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
821
u32 tmp;
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
831
tmp = 0xCAFEDEAD;
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
832
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
850
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
851
if (tmp == 0xDEADBEEF)
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
860
ring->idx, tmp);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
882
u32 tmp = 0;
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
893
tmp = 0xCAFEDEAD;
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
894
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
926
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
927
if (tmp == 0xDEADBEEF) {
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
931
DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1003
tmp = 0xCAFEDEAD;
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1004
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1022
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1023
if (tmp == 0xDEADBEEF)
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1032
ring->idx, tmp);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1055
u32 tmp = 0;
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1065
tmp = 0xCAFEDEAD;
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1066
adev->wb.wb[index] = cpu_to_le32(tmp);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1098
tmp = le32_to_cpu(adev->wb.wb[index]);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1099
if (tmp == 0xDEADBEEF) {
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1103
DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1417
u32 tmp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1419
if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
993
u32 tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
1866
s64 tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
1878
tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
sys/dev/drm/amd/amdgpu/si_dpm.c
1879
kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
sys/dev/drm/amd/amdgpu/si_dpm.c
1880
kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
sys/dev/drm/amd/amdgpu/si_dpm.c
2954
u32 tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
2989
tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
sys/dev/drm/amd/amdgpu/si_dpm.c
2991
spll_table->freq[i] = cpu_to_be32(tmp);
sys/dev/drm/amd/amdgpu/si_dpm.c
2993
tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
sys/dev/drm/amd/amdgpu/si_dpm.c
2995
spll_table->ss[i] = cpu_to_be32(tmp);
sys/dev/drm/amd/amdgpu/si_dpm.c
3342
u32 tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
3345
tmp = i_c >> p_b;
sys/dev/drm/amd/amdgpu/si_dpm.c
3347
while (tmp) {
sys/dev/drm/amd/amdgpu/si_dpm.c
3349
tmp >>= 1;
sys/dev/drm/amd/amdgpu/si_dpm.c
3665
u32 tmp, width, row, column, bank, density;
sys/dev/drm/amd/amdgpu/si_dpm.c
3668
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/drm/amd/amdgpu/si_dpm.c
3669
is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
sys/dev/drm/amd/amdgpu/si_dpm.c
3670
is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
sys/dev/drm/amd/amdgpu/si_dpm.c
3671
& (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
sys/dev/drm/amd/amdgpu/si_dpm.c
3676
tmp = RREG32(MC_ARB_RAMCFG);
sys/dev/drm/amd/amdgpu/si_dpm.c
3677
row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
sys/dev/drm/amd/amdgpu/si_dpm.c
3678
column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
sys/dev/drm/amd/amdgpu/si_dpm.c
3679
bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
sys/dev/drm/amd/amdgpu/si_dpm.c
3939
u32 tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
3945
&tmp, si_pi->sram_end);
sys/dev/drm/amd/amdgpu/si_dpm.c
3949
si_pi->state_table_start = tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
3954
&tmp, si_pi->sram_end);
sys/dev/drm/amd/amdgpu/si_dpm.c
3958
si_pi->soft_regs_start = tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
3963
&tmp, si_pi->sram_end);
sys/dev/drm/amd/amdgpu/si_dpm.c
3967
si_pi->mc_reg_table_start = tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
3972
&tmp, si_pi->sram_end);
sys/dev/drm/amd/amdgpu/si_dpm.c
3976
si_pi->fan_table_start = tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
3981
&tmp, si_pi->sram_end);
sys/dev/drm/amd/amdgpu/si_dpm.c
3985
si_pi->arb_table_start = tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
3990
&tmp, si_pi->sram_end);
sys/dev/drm/amd/amdgpu/si_dpm.c
3994
si_pi->cac_table_start = tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
3999
&tmp, si_pi->sram_end);
sys/dev/drm/amd/amdgpu/si_dpm.c
4003
si_pi->dte_table_start = tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
4008
&tmp, si_pi->sram_end);
sys/dev/drm/amd/amdgpu/si_dpm.c
4012
si_pi->spll_table_start = tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
4017
&tmp, si_pi->sram_end);
sys/dev/drm/amd/amdgpu/si_dpm.c
4021
si_pi->papm_cfg_table_start = tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
4131
u32 tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
4135
tmp = 0x10;
sys/dev/drm/amd/amdgpu/si_dpm.c
4137
tmp = 0x1;
sys/dev/drm/amd/amdgpu/si_dpm.c
4140
WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
sys/dev/drm/amd/amdgpu/si_dpm.c
4148
u32 tmp, pipe;
sys/dev/drm/amd/amdgpu/si_dpm.c
4151
tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
sys/dev/drm/amd/amdgpu/si_dpm.c
4153
tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
sys/dev/drm/amd/amdgpu/si_dpm.c
4155
tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/drm/amd/amdgpu/si_dpm.c
4158
tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
sys/dev/drm/amd/amdgpu/si_dpm.c
4160
tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/drm/amd/amdgpu/si_dpm.c
4162
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/drm/amd/amdgpu/si_dpm.c
4164
tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
sys/dev/drm/amd/amdgpu/si_dpm.c
4165
pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
sys/dev/drm/amd/amdgpu/si_dpm.c
4179
tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
sys/dev/drm/amd/amdgpu/si_dpm.c
4180
tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
sys/dev/drm/amd/amdgpu/si_dpm.c
4181
WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
sys/dev/drm/amd/amdgpu/si_dpm.c
4265
u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
sys/dev/drm/amd/amdgpu/si_dpm.c
4267
tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
sys/dev/drm/amd/amdgpu/si_dpm.c
4268
tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
sys/dev/drm/amd/amdgpu/si_dpm.c
4271
tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
sys/dev/drm/amd/amdgpu/si_dpm.c
4272
tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
sys/dev/drm/amd/amdgpu/si_dpm.c
4274
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/drm/amd/amdgpu/si_dpm.c
4692
u32 tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
4696
&tmp, si_pi->sram_end);
sys/dev/drm/amd/amdgpu/si_dpm.c
4700
tmp &= 0x00FFFFFF;
sys/dev/drm/amd/amdgpu/si_dpm.c
4701
tmp |= MC_CG_ARB_FREQ_F1 << 24;
sys/dev/drm/amd/amdgpu/si_dpm.c
4704
tmp, si_pi->sram_end);
sys/dev/drm/amd/amdgpu/si_dpm.c
4721
u32 tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
4725
&tmp, si_pi->sram_end);
sys/dev/drm/amd/amdgpu/si_dpm.c
4729
tmp = (tmp >> 24) & 0xff;
sys/dev/drm/amd/amdgpu/si_dpm.c
4731
if (tmp == MC_CG_ARB_FREQ_F0)
sys/dev/drm/amd/amdgpu/si_dpm.c
4734
return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
sys/dev/drm/amd/amdgpu/si_dpm.c
4743
u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
sys/dev/drm/amd/amdgpu/si_dpm.c
4745
if (tmp >= 4)
sys/dev/drm/amd/amdgpu/si_dpm.c
4748
dram_rows = 1 << (tmp + 10);
sys/dev/drm/amd/amdgpu/si_dpm.c
5256
u64 tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
5269
tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
sys/dev/drm/amd/amdgpu/si_dpm.c
5270
do_div(tmp, reference_clock);
sys/dev/drm/amd/amdgpu/si_dpm.c
5271
fbdiv = (u32) tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
5378
u32 tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
5386
tmp = freq_nom / reference_clock;
sys/dev/drm/amd/amdgpu/si_dpm.c
5387
tmp = tmp * tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
5391
u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
sys/dev/drm/amd/amdgpu/si_dpm.c
6443
u32 tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
6446
tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
sys/dev/drm/amd/amdgpu/si_dpm.c
6447
si_pi->fan_ctrl_default_mode = tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
6448
tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
sys/dev/drm/amd/amdgpu/si_dpm.c
6449
si_pi->t_min = tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
6453
tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
sys/dev/drm/amd/amdgpu/si_dpm.c
6454
tmp |= TMIN(0);
sys/dev/drm/amd/amdgpu/si_dpm.c
6455
WREG32(CG_FDO_CTRL2, tmp);
sys/dev/drm/amd/amdgpu/si_dpm.c
6457
tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
sys/dev/drm/amd/amdgpu/si_dpm.c
6458
tmp |= FDO_PWM_MODE(mode);
sys/dev/drm/amd/amdgpu/si_dpm.c
6459
WREG32(CG_FDO_CTRL2, tmp);
sys/dev/drm/amd/amdgpu/si_dpm.c
6469
u32 reference_clock, tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
6514
tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
sys/dev/drm/amd/amdgpu/si_dpm.c
6515
fan_table.temp_src = (uint8_t)tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
6591
u32 tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
6613
tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
sys/dev/drm/amd/amdgpu/si_dpm.c
6614
tmp |= FDO_STATIC_DUTY(duty);
sys/dev/drm/amd/amdgpu/si_dpm.c
6615
WREG32(CG_FDO_CTRL0, tmp);
sys/dev/drm/amd/amdgpu/si_dpm.c
6642
u32 tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
6647
tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
sys/dev/drm/amd/amdgpu/si_dpm.c
6648
return (tmp >> FDO_PWM_MODE_SHIFT);
sys/dev/drm/amd/amdgpu/si_dpm.c
6676
u32 tach_period, tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
6693
tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
sys/dev/drm/amd/amdgpu/si_dpm.c
6694
tmp |= TARGET_PERIOD(tach_period);
sys/dev/drm/amd/amdgpu/si_dpm.c
6695
WREG32(CG_TACH_CTRL, tmp);
sys/dev/drm/amd/amdgpu/si_dpm.c
6706
u32 tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
6709
tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
sys/dev/drm/amd/amdgpu/si_dpm.c
6710
tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
sys/dev/drm/amd/amdgpu/si_dpm.c
6711
WREG32(CG_FDO_CTRL2, tmp);
sys/dev/drm/amd/amdgpu/si_dpm.c
6713
tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
sys/dev/drm/amd/amdgpu/si_dpm.c
6714
tmp |= TMIN(si_pi->t_min);
sys/dev/drm/amd/amdgpu/si_dpm.c
6715
WREG32(CG_FDO_CTRL2, tmp);
sys/dev/drm/amd/amdgpu/si_dpm.c
6730
u32 tmp;
sys/dev/drm/amd/amdgpu/si_dpm.c
6733
tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
sys/dev/drm/amd/amdgpu/si_dpm.c
6734
tmp |= EDGE_PER_REV(adev->pm.fan_pulses_per_revolution -1);
sys/dev/drm/amd/amdgpu/si_dpm.c
6735
WREG32(CG_TACH_CTRL, tmp);
sys/dev/drm/amd/amdgpu/si_dpm.c
6738
tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
sys/dev/drm/amd/amdgpu/si_dpm.c
6739
tmp |= TACH_PWM_RESP_RATE(0x28);
sys/dev/drm/amd/amdgpu/si_dpm.c
6740
WREG32(CG_FDO_CTRL2, tmp);
sys/dev/drm/amd/amdgpu/soc15.c
369
u32 tmp, reg;
sys/dev/drm/amd/amdgpu/soc15.c
377
tmp = entry->or_mask;
sys/dev/drm/amd/amdgpu/soc15.c
379
tmp = RREG32(reg);
sys/dev/drm/amd/amdgpu/soc15.c
380
tmp &= ~(entry->and_mask);
sys/dev/drm/amd/amdgpu/soc15.c
381
tmp |= entry->or_mask;
sys/dev/drm/amd/amdgpu/soc15.c
383
WREG32(reg, tmp);
sys/dev/drm/amd/amdgpu/tonga_ih.c
198
u32 wptr, tmp;
sys/dev/drm/amd/amdgpu/tonga_ih.c
214
tmp = RREG32(mmIH_RB_CNTL);
sys/dev/drm/amd/amdgpu/tonga_ih.c
215
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
sys/dev/drm/amd/amdgpu/tonga_ih.c
216
WREG32(mmIH_RB_CNTL, tmp);
sys/dev/drm/amd/amdgpu/tonga_ih.c
381
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/tonga_ih.c
383
if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
sys/dev/drm/amd/amdgpu/tonga_ih.c
392
u32 tmp;
sys/dev/drm/amd/amdgpu/tonga_ih.c
397
tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/tonga_ih.c
398
if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
sys/dev/drm/amd/amdgpu/tonga_ih.c
409
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/tonga_ih.c
411
if (tmp & SRBM_STATUS__IH_BUSY_MASK)
sys/dev/drm/amd/amdgpu/tonga_ih.c
454
u32 tmp;
sys/dev/drm/amd/amdgpu/tonga_ih.c
456
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/tonga_ih.c
457
tmp |= srbm_soft_reset;
sys/dev/drm/amd/amdgpu/tonga_ih.c
458
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/amd/amdgpu/tonga_ih.c
459
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/tonga_ih.c
460
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/tonga_ih.c
464
tmp &= ~srbm_soft_reset;
sys/dev/drm/amd/amdgpu/tonga_ih.c
465
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/tonga_ih.c
466
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
159
uint32_t tmp;
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
178
tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
179
amdgpu_ring_write(ring, tmp);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
182
tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
183
amdgpu_ring_write(ring, tmp);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
186
tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
187
amdgpu_ring_write(ring, tmp);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
262
u32 tmp;
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
293
tmp = RREG32(mmUVD_MPC_CNTL);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
294
WREG32(mmUVD_MPC_CNTL, tmp | 0x10);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
305
tmp = RREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
306
WREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL, tmp & (~0x10));
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
481
uint32_t tmp = 0;
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
496
tmp = RREG32(mmUVD_CONTEXT_ID);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
497
if (tmp == 0xDEADBEEF)
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
507
ring->idx, tmp);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
614
u32 tmp, tmp2;
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
618
tmp = RREG32(mmUVD_CGC_CTRL);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
619
tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
620
tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
625
tmp &= ~0x7ffff800;
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
630
tmp |= 0x7ffff800;
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
634
WREG32(mmUVD_CGC_CTRL, tmp);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
154
uint32_t tmp;
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
174
tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
175
amdgpu_ring_write(ring, tmp);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
178
tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
179
amdgpu_ring_write(ring, tmp);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
182
tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
183
amdgpu_ring_write(ring, tmp);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
297
uint32_t rb_bufsz, tmp;
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
395
tmp = 0;
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
396
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
397
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
398
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
399
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
400
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
401
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
403
WREG32(mmUVD_RBC_RB_CNTL, tmp);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
497
uint32_t tmp = 0;
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
512
tmp = RREG32(mmUVD_CONTEXT_ID);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
513
if (tmp == 0xDEADBEEF)
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
523
ring->idx, tmp);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1145
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1147
if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1148
REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1182
u32 tmp;
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1184
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1185
tmp |= srbm_soft_reset;
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1186
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1187
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1188
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1192
tmp &= ~srbm_soft_reset;
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1193
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1194
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
472
uint32_t tmp;
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
492
tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
493
amdgpu_ring_write(ring, tmp);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
496
tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
497
amdgpu_ring_write(ring, tmp);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
500
tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
501
amdgpu_ring_write(ring, tmp);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
710
uint32_t rb_bufsz, tmp;
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
820
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
821
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
822
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
823
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
824
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
825
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
826
WREG32(mmUVD_RBC_RB_CNTL, tmp);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
966
uint32_t tmp = 0;
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
981
tmp = RREG32(mmUVD_CONTEXT_ID);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
982
if (tmp == 0xDEADBEEF)
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
992
ring->idx, tmp);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1067
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1068
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1069
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1070
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1071
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1072
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1073
WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1232
uint32_t tmp = 0;
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1248
tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1249
if (tmp == 0xDEADBEEF)
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1259
ring->me, ring->idx, tmp);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1464
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1466
if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1467
REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1503
u32 tmp;
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1505
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1506
tmp |= srbm_soft_reset;
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1507
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1508
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1509
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1513
tmp &= ~srbm_soft_reset;
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1514
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1515
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1686
u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1689
tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1692
tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1695
WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
527
uint32_t tmp;
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
556
tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
558
amdgpu_ring_write(ring, tmp);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
561
tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
563
amdgpu_ring_write(ring, tmp);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
566
tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
568
amdgpu_ring_write(ring, tmp);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
776
uint32_t offset, size, tmp;
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
900
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
901
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
902
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
938
uint32_t rb_bufsz, tmp;
sys/dev/drm/amd/amdgpu/vce_v2_0.c
149
u32 tmp;
sys/dev/drm/amd/amdgpu/vce_v2_0.c
151
tmp = RREG32(mmVCE_CLOCK_GATING_A);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
152
tmp &= ~0xfff;
sys/dev/drm/amd/amdgpu/vce_v2_0.c
153
tmp |= ((0 << 0) | (4 << 4));
sys/dev/drm/amd/amdgpu/vce_v2_0.c
154
tmp |= 0x40000;
sys/dev/drm/amd/amdgpu/vce_v2_0.c
155
WREG32(mmVCE_CLOCK_GATING_A, tmp);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
157
tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
158
tmp &= ~0xfff;
sys/dev/drm/amd/amdgpu/vce_v2_0.c
159
tmp |= ((0 << 0) | (4 << 4));
sys/dev/drm/amd/amdgpu/vce_v2_0.c
160
WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
162
tmp = RREG32(mmVCE_CLOCK_GATING_B);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
163
tmp |= 0x10;
sys/dev/drm/amd/amdgpu/vce_v2_0.c
164
tmp &= ~0x100000;
sys/dev/drm/amd/amdgpu/vce_v2_0.c
165
WREG32(mmVCE_CLOCK_GATING_B, tmp);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
312
u32 tmp;
sys/dev/drm/amd/amdgpu/vce_v2_0.c
315
tmp = RREG32(mmVCE_CLOCK_GATING_B);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
316
tmp |= 0xe70000;
sys/dev/drm/amd/amdgpu/vce_v2_0.c
317
WREG32(mmVCE_CLOCK_GATING_B, tmp);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
319
tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
320
tmp |= 0xff000000;
sys/dev/drm/amd/amdgpu/vce_v2_0.c
321
WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
323
tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
324
tmp &= ~0x3fc;
sys/dev/drm/amd/amdgpu/vce_v2_0.c
325
WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
329
tmp = RREG32(mmVCE_CLOCK_GATING_B);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
330
tmp |= 0xe7;
sys/dev/drm/amd/amdgpu/vce_v2_0.c
331
tmp &= ~0xe70000;
sys/dev/drm/amd/amdgpu/vce_v2_0.c
332
WREG32(mmVCE_CLOCK_GATING_B, tmp);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
334
tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
335
tmp |= 0x1fe000;
sys/dev/drm/amd/amdgpu/vce_v2_0.c
336
tmp &= ~0xff000000;
sys/dev/drm/amd/amdgpu/vce_v2_0.c
337
WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
339
tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
340
tmp |= 0x3fc;
sys/dev/drm/amd/amdgpu/vce_v2_0.c
341
WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
347
u32 orig, tmp;
sys/dev/drm/amd/amdgpu/vce_v2_0.c
352
tmp = RREG32(mmVCE_CLOCK_GATING_B);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
353
tmp &= ~0x00060006;
sys/dev/drm/amd/amdgpu/vce_v2_0.c
357
tmp |= 0xe10000;
sys/dev/drm/amd/amdgpu/vce_v2_0.c
358
WREG32(mmVCE_CLOCK_GATING_B, tmp);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
360
tmp |= 0xe1;
sys/dev/drm/amd/amdgpu/vce_v2_0.c
361
tmp &= ~0xe10000;
sys/dev/drm/amd/amdgpu/vce_v2_0.c
362
WREG32(mmVCE_CLOCK_GATING_B, tmp);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
365
orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
366
tmp &= ~0x1fe000;
sys/dev/drm/amd/amdgpu/vce_v2_0.c
367
tmp &= ~0xff000000;
sys/dev/drm/amd/amdgpu/vce_v2_0.c
368
if (tmp != orig)
sys/dev/drm/amd/amdgpu/vce_v2_0.c
369
WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
371
orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
372
tmp &= ~0x3fc;
sys/dev/drm/amd/amdgpu/vce_v2_0.c
373
if (tmp != orig)
sys/dev/drm/amd/amdgpu/vce_v2_0.c
374
WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
367
u32 tmp;
sys/dev/drm/amd/amdgpu/vce_v3_0.c
374
tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) &
sys/dev/drm/amd/amdgpu/vce_v3_0.c
378
tmp = (RREG32_SMC(ixCC_HARVEST_FUSES) &
sys/dev/drm/amd/amdgpu/vce_v3_0.c
382
switch (tmp) {
sys/dev/drm/amd/amdgpu/vce_v3_0.c
661
u32 tmp;
sys/dev/drm/amd/amdgpu/vce_v3_0.c
663
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
664
tmp |= srbm_soft_reset;
sys/dev/drm/amd/amdgpu/vce_v3_0.c
665
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
666
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
667
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
671
tmp &= ~srbm_soft_reset;
sys/dev/drm/amd/amdgpu/vce_v3_0.c
672
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
673
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
746
u32 tmp;
sys/dev/drm/amd/amdgpu/vce_v4_0.c
748
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
749
tmp |= srbm_soft_reset;
sys/dev/drm/amd/amdgpu/vce_v4_0.c
750
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
751
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
752
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
756
tmp &= ~srbm_soft_reset;
sys/dev/drm/amd/amdgpu/vce_v4_0.c
757
WREG32(mmSRBM_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
758
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
794
u32 tmp, data;
sys/dev/drm/amd/amdgpu/vce_v4_0.c
796
tmp = data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_ARB_CTRL));
sys/dev/drm/amd/amdgpu/vce_v4_0.c
802
if (tmp != data)
sys/dev/drm/amd/amdgpu/vce_v4_0.c
875
u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
878
tmp |= GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
sys/dev/drm/amd/amdgpu/vce_v4_0.c
880
tmp &= ~GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
sys/dev/drm/amd/amdgpu/vce_v4_0.c
882
WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1055
tmp = adev->gfx.config.gb_addr_config;
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1057
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1058
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1066
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1067
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1068
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1069
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1070
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1071
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1129
int ret_code, tmp;
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1133
tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1137
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1144
tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1146
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1178
int tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1180
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
773
uint32_t rb_bufsz, tmp;
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
782
tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
783
WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
793
tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
794
WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
806
tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
807
tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
808
tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
809
WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
845
tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
846
tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
847
tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
848
WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
888
tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY;
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
889
WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
893
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
894
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
895
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
896
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
897
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
898
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
962
uint32_t rb_bufsz, tmp;
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
971
tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
972
tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
973
tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
974
WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
980
tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
981
tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
982
tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
983
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0);
sys/dev/drm/amd/amdgpu/vega10_ih.c
152
tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL);
sys/dev/drm/amd/amdgpu/vega10_ih.c
153
tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
sys/dev/drm/amd/amdgpu/vega10_ih.c
155
WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp);
sys/dev/drm/amd/amdgpu/vega10_ih.c
157
tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL);
sys/dev/drm/amd/amdgpu/vega10_ih.c
158
tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);
sys/dev/drm/amd/amdgpu/vega10_ih.c
159
WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp);
sys/dev/drm/amd/amdgpu/vega10_ih.c
196
u32 wptr, tmp;
sys/dev/drm/amd/amdgpu/vega10_ih.c
210
tmp = (wptr + 32) & adev->irq.ih.ptr_mask;
sys/dev/drm/amd/amdgpu/vega10_ih.c
212
wptr, adev->irq.ih.rptr, tmp);
sys/dev/drm/amd/amdgpu/vega10_ih.c
213
adev->irq.ih.rptr = tmp;
sys/dev/drm/amd/amdgpu/vega10_ih.c
215
tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
sys/dev/drm/amd/amdgpu/vega10_ih.c
216
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
sys/dev/drm/amd/amdgpu/vega10_ih.c
217
WREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), tmp);
sys/dev/drm/amd/amdgpu/vega10_ih.c
92
u32 tmp;
sys/dev/drm/amd/amdgpu/vi.c
329
u32 tmp;
sys/dev/drm/amd/amdgpu/vi.c
334
tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
sys/dev/drm/amd/amdgpu/vi.c
335
if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
sys/dev/drm/amd/amdgpu/vi.c
338
tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);
sys/dev/drm/amd/amdgpu/vi.c
339
if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
sys/dev/drm/amd/amdgpu/vi.c
723
uint32_t tmp;
sys/dev/drm/amd/amdgpu/vi.c
731
tmp = RREG32_SMC(cntl_reg);
sys/dev/drm/amd/amdgpu/vi.c
734
tmp &= ~CG_DCLK_CNTL__DCLK_DIVIDER_MASK;
sys/dev/drm/amd/amdgpu/vi.c
736
tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
sys/dev/drm/amd/amdgpu/vi.c
738
tmp |= dividers.post_divider;
sys/dev/drm/amd/amdgpu/vi.c
739
WREG32_SMC(cntl_reg, tmp);
sys/dev/drm/amd/amdgpu/vi.c
742
tmp = RREG32_SMC(status_reg);
sys/dev/drm/amd/amdgpu/vi.c
744
if (tmp & 0x10000)
sys/dev/drm/amd/amdgpu/vi.c
747
if (tmp & CG_DCLK_STATUS__DCLK_STATUS_MASK)
sys/dev/drm/amd/amdgpu/vi.c
793
u32 tmp;
sys/dev/drm/amd/amdgpu/vi.c
826
tmp = RREG32_SMC(reg_ctrl);
sys/dev/drm/amd/amdgpu/vi.c
827
tmp &= ~reg_mask;
sys/dev/drm/amd/amdgpu/vi.c
828
tmp |= dividers.post_divider;
sys/dev/drm/amd/amdgpu/vi.c
829
WREG32_SMC(reg_ctrl, tmp);
sys/dev/drm/amd/amdgpu/vi.c
875
u32 tmp;
sys/dev/drm/amd/amdgpu/vi.c
881
tmp = RREG32(mmBIF_DOORBELL_APER_EN);
sys/dev/drm/amd/amdgpu/vi.c
883
tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
sys/dev/drm/amd/amdgpu/vi.c
885
tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
sys/dev/drm/amd/amdgpu/vi.c
887
WREG32(mmBIF_DOORBELL_APER_EN, tmp);
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
111
struct list_head *entry, *tmp;
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
131
list_for_each_safe(entry, tmp, hnd_list) {
sys/dev/drm/amd/display/dc/basics/fixpt31_32.c
135
unsigned long long tmp;
sys/dev/drm/amd/display/dc/basics/fixpt31_32.c
143
tmp = arg1_int * arg2_fra;
sys/dev/drm/amd/display/dc/basics/fixpt31_32.c
145
ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
sys/dev/drm/amd/display/dc/basics/fixpt31_32.c
147
res.value += tmp;
sys/dev/drm/amd/display/dc/basics/fixpt31_32.c
149
tmp = arg2_int * arg1_fra;
sys/dev/drm/amd/display/dc/basics/fixpt31_32.c
151
ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
sys/dev/drm/amd/display/dc/basics/fixpt31_32.c
153
res.value += tmp;
sys/dev/drm/amd/display/dc/basics/fixpt31_32.c
155
tmp = arg1_fra * arg2_fra;
sys/dev/drm/amd/display/dc/basics/fixpt31_32.c
157
tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) +
sys/dev/drm/amd/display/dc/basics/fixpt31_32.c
158
(tmp >= (unsigned long long)dc_fixpt_half.value);
sys/dev/drm/amd/display/dc/basics/fixpt31_32.c
160
ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
sys/dev/drm/amd/display/dc/basics/fixpt31_32.c
162
res.value += tmp;
sys/dev/drm/amd/display/dc/basics/fixpt31_32.c
180
unsigned long long tmp;
sys/dev/drm/amd/display/dc/basics/fixpt31_32.c
188
tmp = arg_int * arg_fra;
sys/dev/drm/amd/display/dc/basics/fixpt31_32.c
190
ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
sys/dev/drm/amd/display/dc/basics/fixpt31_32.c
192
res.value += tmp;
sys/dev/drm/amd/display/dc/basics/fixpt31_32.c
194
ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
sys/dev/drm/amd/display/dc/basics/fixpt31_32.c
196
res.value += tmp;
sys/dev/drm/amd/display/dc/basics/fixpt31_32.c
198
tmp = arg_fra * arg_fra;
sys/dev/drm/amd/display/dc/basics/fixpt31_32.c
200
tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) +
sys/dev/drm/amd/display/dc/basics/fixpt31_32.c
201
(tmp >= (unsigned long long)dc_fixpt_half.value);
sys/dev/drm/amd/display/dc/basics/fixpt31_32.c
203
ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
sys/dev/drm/amd/display/dc/basics/fixpt31_32.c
205
res.value += tmp;
sys/dev/drm/amd/display/dc/calcs/bw_fixed.c
159
uint64_t tmp;
sys/dev/drm/amd/display/dc/calcs/bw_fixed.c
167
tmp = arg1_int * arg2_fra;
sys/dev/drm/amd/display/dc/calcs/bw_fixed.c
169
ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value));
sys/dev/drm/amd/display/dc/calcs/bw_fixed.c
171
res.value += tmp;
sys/dev/drm/amd/display/dc/calcs/bw_fixed.c
173
tmp = arg2_int * arg1_fra;
sys/dev/drm/amd/display/dc/calcs/bw_fixed.c
175
ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value));
sys/dev/drm/amd/display/dc/calcs/bw_fixed.c
177
res.value += tmp;
sys/dev/drm/amd/display/dc/calcs/bw_fixed.c
179
tmp = arg1_fra * arg2_fra;
sys/dev/drm/amd/display/dc/calcs/bw_fixed.c
181
tmp = (tmp >> BW_FIXED_BITS_PER_FRACTIONAL_PART) +
sys/dev/drm/amd/display/dc/calcs/bw_fixed.c
182
(tmp >= (uint64_t)(bw_frc_to_fixed(1, 2).value));
sys/dev/drm/amd/display/dc/calcs/bw_fixed.c
184
ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value));
sys/dev/drm/amd/display/dc/calcs/bw_fixed.c
186
res.value += tmp;
sys/dev/drm/amd/display/dc/core/dc_link_dp.c
1669
uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
sys/dev/drm/amd/display/dc/core/dc_link_dp.c
1674
tmp,
sys/dev/drm/amd/display/dc/core/dc_link_dp.c
1675
sizeof(tmp));
sys/dev/drm/amd/display/dc/core/dc_link_dp.c
1680
irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
sys/dev/drm/amd/display/dc/core/dc_link_dp.c
1681
irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
sys/dev/drm/amd/display/dc/core/dc_link_dp.c
1682
irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
sys/dev/drm/amd/display/dc/core/dc_link_dp.c
1683
irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
sys/dev/drm/amd/display/dc/core/dc_link_dp.c
1684
irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
sys/dev/drm/amd/display/dc/core/dc_link_dp.c
1685
irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c
612
uint32_t tmp = 0;
sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c
656
tmp = timing->h_total -
sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c
661
tmp,
sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c
665
tmp = tmp + timing->h_addressable +
sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c
670
tmp,
sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c
679
tmp = timing->v_total - (v_sync_start + timing->v_border_top);
sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c
683
tmp,
sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c
687
tmp = tmp + timing->v_addressable + timing->v_border_top +
sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c
692
tmp,
sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
257
uint32_t tmp = 0;
sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
280
tmp = timing->h_total -
sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
285
tmp,
sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
289
tmp = tmp + timing->h_addressable +
sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
294
tmp,
sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
303
tmp = timing->v_total - (v_sync_start + timing->v_border_top);
sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
307
tmp,
sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
311
tmp = tmp + timing->v_addressable + timing->v_border_top +
sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
316
tmp,
sys/dev/drm/amd/powerplay/hwmgr/ppevvmath.h
514
int i, scaledDecimal = 0, tmp = A.partial.decimal;
sys/dev/drm/amd/powerplay/hwmgr/ppevvmath.h
517
dec[i] = tmp / (1 << SHIFT_AMOUNT);
sys/dev/drm/amd/powerplay/hwmgr/ppevvmath.h
518
tmp = tmp - ((1 << SHIFT_AMOUNT)*dec[i]);
sys/dev/drm/amd/powerplay/hwmgr/ppevvmath.h
519
tmp *= 10;
sys/dev/drm/amd/powerplay/hwmgr/processpptables.c
683
unsigned long tmp;
sys/dev/drm/amd/powerplay/hwmgr/processpptables.c
693
tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
sys/dev/drm/amd/powerplay/hwmgr/processpptables.c
696
ps->validation.singleDisplayOnly = (0 != tmp);
sys/dev/drm/amd/powerplay/hwmgr/processpptables.c
698
tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
sys/dev/drm/amd/powerplay/hwmgr/processpptables.c
701
ps->validation.disallowOnDC = (0 != tmp);
sys/dev/drm/amd/powerplay/hwmgr/processpptables.c
728
tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
sys/dev/drm/amd/powerplay/hwmgr/processpptables.c
731
ps->display.enableVariBright = (0 != tmp);
sys/dev/drm/amd/powerplay/hwmgr/processpptables.c
733
tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
sys/dev/drm/amd/powerplay/hwmgr/processpptables.c
736
ps->memory.dllOff = (0 != tmp);
sys/dev/drm/amd/powerplay/hwmgr/processpptables.c
747
tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
sys/dev/drm/amd/powerplay/hwmgr/processpptables.c
750
ps->software.disableLoadBalancing = tmp;
sys/dev/drm/amd/powerplay/hwmgr/processpptables.c
752
tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
sys/dev/drm/amd/powerplay/hwmgr/processpptables.c
755
ps->software.enableSleepForTimestamps = (0 != tmp);
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2400
int tmp;
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2402
tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk);
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2403
if (tmp)
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2406
tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_mclk);
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2407
if (tmp)
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2410
tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2411
if (tmp)
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2414
tmp = smu7_patch_vddci(hwmgr, hwmgr->dyn_state.vddci_dependency_on_mclk);
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2415
if (tmp)
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2418
tmp = smu7_patch_vce_vddc(hwmgr, hwmgr->dyn_state.vce_clock_voltage_dependency_table);
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2419
if (tmp)
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2422
tmp = smu7_patch_uvd_vddc(hwmgr, hwmgr->dyn_state.uvd_clock_voltage_dependency_table);
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2423
if (tmp)
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2426
tmp = smu7_patch_samu_vddc(hwmgr, hwmgr->dyn_state.samu_clock_voltage_dependency_table);
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2427
if (tmp)
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2430
tmp = smu7_patch_acp_vddc(hwmgr, hwmgr->dyn_state.acp_clock_voltage_dependency_table);
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2431
if (tmp)
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2434
tmp = smu7_patch_vddc_shed_limit(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table);
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2435
if (tmp)
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2438
tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_ac);
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2439
if (tmp)
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2442
tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_dc);
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2443
if (tmp)
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2446
tmp = smu7_patch_cac_vddc(hwmgr, hwmgr->dyn_state.cac_leakage_table);
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2447
if (tmp)
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
254
uint32_t tmp;
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2602
uint32_t level, tmp;
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2607
tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2608
while (tmp >>= 1)
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2620
tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2621
while (tmp >>= 1)
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2634
tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2635
while (tmp >>= 1)
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
323
tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDC);
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
325
(data->vddc_voltage_table.count <= tmp),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
327
phm_trim_voltage_table_to_fit_state_table(tmp,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
330
tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
332
(data->vddgfx_voltage_table.count <= tmp),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
334
phm_trim_voltage_table_to_fit_state_table(tmp,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
337
tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDCI);
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
339
(data->vddci_voltage_table.count <= tmp),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
341
phm_trim_voltage_table_to_fit_state_table(tmp,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
344
tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_MVDD);
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
346
(data->mvdd_voltage_table.count <= tmp),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3478
u32 tmp = 0;
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
348
phm_trim_voltage_table_to_fit_state_table(tmp,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3484
tmp = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3485
*query = tmp;
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3487
if (tmp != 0)
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3497
tmp = cgs_read_ind_register(hwmgr->device,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3500
if (tmp != 0)
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3503
*query = tmp;
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4209
uint32_t tmp;
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4223
tmp = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4225
if (tmp & (1 << 23)) {
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4384
uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4387
if (fls(tmp) != ffs(tmp))
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4392
fls(tmp) - 1);
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4946
uint32_t tmp, level;
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4951
tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4952
while (tmp >>= 1)
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4965
struct profile_mode_setting tmp;
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4977
tmp.bupdate_sclk = input[0];
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4978
tmp.sclk_up_hyst = input[1];
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4979
tmp.sclk_down_hyst = input[2];
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4980
tmp.sclk_activity = input[3];
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4981
tmp.bupdate_mclk = input[4];
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4982
tmp.mclk_up_hyst = input[5];
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4983
tmp.mclk_down_hyst = input[6];
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4984
tmp.mclk_activity = input[7];
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4985
if (!smum_update_dpm_settings(hwmgr, &tmp)) {
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4986
memcpy(&data->current_profile_setting, &tmp, sizeof(struct profile_mode_setting));
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4998
memcpy(&tmp, &smu7_profiling[mode], sizeof(struct profile_mode_setting));
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4999
if (!smum_update_dpm_settings(hwmgr, &tmp)) {
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
5000
if (tmp.bupdate_sclk) {
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
5001
data->current_profile_setting.bupdate_sclk = tmp.bupdate_sclk;
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
5002
data->current_profile_setting.sclk_up_hyst = tmp.sclk_up_hyst;
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
5003
data->current_profile_setting.sclk_down_hyst = tmp.sclk_down_hyst;
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
5004
data->current_profile_setting.sclk_activity = tmp.sclk_activity;
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
5006
if (tmp.bupdate_mclk) {
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
5007
data->current_profile_setting.bupdate_mclk = tmp.bupdate_mclk;
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
5008
data->current_profile_setting.mclk_up_hyst = tmp.mclk_up_hyst;
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
5009
data->current_profile_setting.mclk_down_hyst = tmp.mclk_down_hyst;
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
5010
data->current_profile_setting.mclk_activity = tmp.mclk_activity;
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
511
uint32_t tmp;
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
513
tmp = (cgs_read_ind_register(hwmgr->device,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
517
if (tmp == MC_CG_ARB_FREQ_F0)
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
521
tmp, MC_CG_ARB_FREQ_F0);
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
533
uint32_t tmp;
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
551
tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_LINK);
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
553
tmp,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
561
max_entry = (tmp < pcie_table->count) ? tmp : pcie_table->count;
sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
1695
uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent;
sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
1713
tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) &
sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
1715
vddnb = smu8_convert_8Bit_index_to_voltage(hwmgr, tmp) / 4;
sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
1719
tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) &
sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
1721
vddgfx = smu8_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp) / 4;
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
935
uint32_t tmp;
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
942
tmp = table.mask_low;
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
944
if (tmp & 1) {
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
949
tmp >>= 1;
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
1071
uint32_t tmp;
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
1081
tmp = (freq_nom / reference_clock);
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
1082
tmp = tmp * tmp;
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
1088
ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2368
uint32_t tmp = 0;
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2378
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2381
ci_data->dpm_table_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2388
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2391
data->soft_regs_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2392
ci_data->soft_regs_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2400
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2403
ci_data->mc_reg_table_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2408
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2411
ci_data->fan_table_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2418
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2421
ci_data->arb_table_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2428
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2431
hwmgr->microcode_version_info.SMC = tmp;
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2774
uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2792
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2793
tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2794
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2806
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2807
tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpH, sizeof(uint8_t));
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2808
tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownH, sizeof(uint8_t));
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2809
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2827
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2828
tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2829
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2841
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2842
tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpH, sizeof(uint8_t));
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2843
tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownH, sizeof(uint8_t));
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2844
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
561
uint16_t tmp;
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
566
tmp = hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity;
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
568
tmp = hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
570
smu_data->power_tune_table.FuzzyFan_PwmSetDelta = CONVERT_FROM_HOST_TO_SMC_US(tmp);
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1870
uint32_t tmp;
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1882
smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1887
tmp &= 0x00FFFFFF;
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1888
tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1891
smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1905
u32 tmp = param_led_dpm.mask_low;
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1908
if (tmp & 1) {
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1913
tmp >>= 1;
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2449
uint32_t tmp;
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2456
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2459
smu_data->smu7_data.dpm_table_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2466
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2469
data->soft_regs_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2470
smu_data->smu7_data.soft_regs_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2478
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2481
smu_data->smu7_data.mc_reg_table_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2486
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2489
smu_data->smu7_data.fan_table_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2496
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2499
smu_data->smu7_data.arb_table_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2506
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2509
hwmgr->microcode_version_info.SMC = tmp;
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2564
uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2582
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2583
tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2584
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2596
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2597
tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2598
tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2599
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2617
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2618
tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2619
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2631
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2632
tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2633
tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2634
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
422
uint32_t tmp;
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
423
tmp = raw_setting * 4096 / 100;
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
424
return (uint16_t)tmp;
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
1114
uint32_t tmp;
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
1124
tmp = (freq_nom / reference_clock);
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
1125
tmp = tmp * tmp;
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
1138
ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2281
uint32_t tmp;
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2288
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2291
smu7_data->dpm_table_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2299
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2302
data->soft_regs_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2303
smu7_data->soft_regs_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2312
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2315
smu7_data->mc_reg_table_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2321
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2324
smu7_data->fan_table_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2332
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2335
smu7_data->arb_table_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2344
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2347
hwmgr->microcode_version_info.SMC = tmp;
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2355
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2358
smu7_data->ulv_setting_starts = tmp;
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1649
uint32_t tmp, i;
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1695
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1698
tmp,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1705
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1707
tmp,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1724
uint32_t tmp;
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1736
smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1741
tmp &= 0x00FFFFFF;
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1742
tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1745
smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2326
uint32_t tmp;
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2333
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2336
smu_data->smu7_data.dpm_table_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2343
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2346
data->soft_regs_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2347
smu_data->smu7_data.soft_regs_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2355
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2358
smu_data->smu7_data.mc_reg_table_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2363
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2366
smu_data->smu7_data.fan_table_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2373
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2376
smu_data->smu7_data.arb_table_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2383
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2386
hwmgr->microcode_version_info.SMC = tmp;
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2417
uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2435
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2436
tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2437
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2449
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2450
tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2451
tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2452
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2470
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2471
tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2472
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2484
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2485
tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2486
tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2487
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
418
uint32_t tmp;
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
419
tmp = raw_setting * 4096 / 100;
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
420
return (uint16_t)tmp;
sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c
180
uint32_t tmp;
sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c
196
tmp = cgs_read_register(hwmgr->device,
sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c
198
tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c
199
tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c
200
cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, tmp);
sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c
202
tmp = cgs_read_register(hwmgr->device,
sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c
205
tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c
206
tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ATC, 0);
sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c
207
tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c
208
tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1);
sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c
209
cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_CNTL, tmp);
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
1800
uint32_t tmp;
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
1813
smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
1818
tmp &= 0x00FFFFFF;
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
1819
tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
1822
smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2758
uint32_t tmp;
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2765
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2768
smu_data->smu7_data.dpm_table_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2775
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2778
data->soft_regs_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2779
smu_data->smu7_data.soft_regs_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2788
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2791
smu_data->smu7_data.mc_reg_table_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2796
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2799
smu_data->smu7_data.fan_table_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2806
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2809
smu_data->smu7_data.arb_table_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2816
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2819
hwmgr->microcode_version_info.SMC = tmp;
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
3162
uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
3180
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
3181
tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
3182
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
3194
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
3195
tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
3196
tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
3197
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
3215
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
3216
tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
3217
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
3229
tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
3230
tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
3231
tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
3232
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
865
uint32_t tmp;
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
875
tmp = (freq_nom / reference_clock);
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
876
tmp = tmp * tmp;
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
889
ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1438
uint32_t tmp;
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1439
tmp = raw_setting * 4096 / 100;
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1440
return (uint16_t)tmp;
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1579
uint32_t tmp, i;
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1647
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1649
tmp,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1657
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1659
tmp,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
230
uint32_t tmp;
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
237
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
240
smu_data->smu7_data.dpm_table_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
247
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
250
data->soft_regs_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
251
smu_data->smu7_data.soft_regs_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
259
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
262
smu_data->smu7_data.mc_reg_table_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
267
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
270
smu_data->smu7_data.fan_table_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
277
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
280
smu_data->smu7_data.arb_table_start = tmp;
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
287
&tmp, SMC_RAM_END);
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
290
hwmgr->microcode_version_info.SMC = tmp;
sys/dev/drm/drm_context.c
131
struct drm_ctx_list *pos, *tmp;
sys/dev/drm/drm_context.c
139
list_for_each_entry_safe(pos, tmp, &dev->ctxlist, head) {
sys/dev/drm/drm_crtc.c
151
struct drm_crtc *tmp;
sys/dev/drm/drm_crtc.c
153
drm_for_each_crtc(tmp, dev) {
sys/dev/drm/drm_crtc.c
464
struct drm_crtc *tmp;
sys/dev/drm/drm_crtc.c
474
drm_for_each_crtc(tmp, crtc->dev) {
sys/dev/drm/drm_crtc.c
475
struct drm_plane *plane = tmp->primary;
sys/dev/drm/drm_crtc.c
490
drm_for_each_crtc(tmp, crtc->dev) {
sys/dev/drm/drm_crtc.c
491
struct drm_plane *plane = tmp->primary;
sys/dev/drm/drm_dp_dual_mode_helper.c
363
uint8_t tmp;
sys/dev/drm/drm_dp_dual_mode_helper.c
375
&tmp, sizeof(tmp));
sys/dev/drm/drm_dp_dual_mode_helper.c
383
if (tmp == tmds_oen)
sys/dev/drm/drm_dp_mst_topology.c
871
struct drm_dp_mst_port *port, *tmp;
sys/dev/drm/drm_dp_mst_topology.c
888
list_for_each_entry_safe(port, tmp, &mstb->ports, next) {
sys/dev/drm/drm_edid.c
3152
struct drm_display_mode *mode, *tmp;
sys/dev/drm/drm_edid.c
3211
list_for_each_entry_safe(mode, tmp, &list, head) {
sys/dev/drm/drm_memory.c
88
struct resource *tmp;
sys/dev/drm/drm_memory.c
91
for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling) {
sys/dev/drm/drm_memory.c
92
max_iomem = max(max_iomem, tmp->end);
sys/dev/drm/drm_modes.c
162
u64 tmp;
sys/dev/drm/drm_modes.c
320
tmp = drm_mode->htotal; /* perform intermediate calcs in u64 */
sys/dev/drm/drm_modes.c
321
tmp *= HV_FACTOR * 1000;
sys/dev/drm/drm_modes.c
322
do_div(tmp, hperiod);
sys/dev/drm/drm_modes.c
323
tmp -= drm_mode->clock % CVT_CLOCK_STEP;
sys/dev/drm/drm_modes.c
324
drm_mode->clock = tmp;
sys/dev/drm/drm_modeset_helper.c
49
struct drm_connector *connector, *tmp;
sys/dev/drm/drm_modeset_helper.c
55
list_for_each_entry_safe(connector, tmp,
sys/dev/drm/drm_pci.c
433
struct drm_device *dev, *tmp;
sys/dev/drm/drm_pci.c
439
list_for_each_entry_safe(dev, tmp, &driver->legacy_dev_list,
sys/dev/drm/drm_plane.c
65
struct drm_plane *tmp;
sys/dev/drm/drm_plane.c
67
drm_for_each_plane(tmp, dev) {
sys/dev/drm/drm_rect.c
353
struct drm_rect tmp;
sys/dev/drm/drm_rect.c
356
tmp = *r;
sys/dev/drm/drm_rect.c
359
r->x1 = width - tmp.x2;
sys/dev/drm/drm_rect.c
360
r->x2 = width - tmp.x1;
sys/dev/drm/drm_rect.c
364
r->y1 = height - tmp.y2;
sys/dev/drm/drm_rect.c
365
r->y2 = height - tmp.y1;
sys/dev/drm/drm_rect.c
373
tmp = *r;
sys/dev/drm/drm_rect.c
374
r->x1 = tmp.y1;
sys/dev/drm/drm_rect.c
375
r->x2 = tmp.y2;
sys/dev/drm/drm_rect.c
376
r->y1 = width - tmp.x2;
sys/dev/drm/drm_rect.c
377
r->y2 = width - tmp.x1;
sys/dev/drm/drm_rect.c
380
tmp = *r;
sys/dev/drm/drm_rect.c
381
r->x1 = width - tmp.x2;
sys/dev/drm/drm_rect.c
382
r->x2 = width - tmp.x1;
sys/dev/drm/drm_rect.c
383
r->y1 = height - tmp.y2;
sys/dev/drm/drm_rect.c
384
r->y2 = height - tmp.y1;
sys/dev/drm/drm_rect.c
387
tmp = *r;
sys/dev/drm/drm_rect.c
388
r->x1 = height - tmp.y2;
sys/dev/drm/drm_rect.c
389
r->x2 = height - tmp.y1;
sys/dev/drm/drm_rect.c
390
r->y1 = tmp.x1;
sys/dev/drm/drm_rect.c
391
r->y2 = tmp.x2;
sys/dev/drm/drm_rect.c
427
struct drm_rect tmp;
sys/dev/drm/drm_rect.c
433
tmp = *r;
sys/dev/drm/drm_rect.c
434
r->x1 = width - tmp.y2;
sys/dev/drm/drm_rect.c
435
r->x2 = width - tmp.y1;
sys/dev/drm/drm_rect.c
436
r->y1 = tmp.x1;
sys/dev/drm/drm_rect.c
437
r->y2 = tmp.x2;
sys/dev/drm/drm_rect.c
440
tmp = *r;
sys/dev/drm/drm_rect.c
441
r->x1 = width - tmp.x2;
sys/dev/drm/drm_rect.c
442
r->x2 = width - tmp.x1;
sys/dev/drm/drm_rect.c
443
r->y1 = height - tmp.y2;
sys/dev/drm/drm_rect.c
444
r->y2 = height - tmp.y1;
sys/dev/drm/drm_rect.c
447
tmp = *r;
sys/dev/drm/drm_rect.c
448
r->x1 = tmp.y1;
sys/dev/drm/drm_rect.c
449
r->x2 = tmp.y2;
sys/dev/drm/drm_rect.c
450
r->y1 = height - tmp.x2;
sys/dev/drm/drm_rect.c
451
r->y2 = height - tmp.x1;
sys/dev/drm/drm_rect.c
458
tmp = *r;
sys/dev/drm/drm_rect.c
461
r->x1 = width - tmp.x2;
sys/dev/drm/drm_rect.c
462
r->x2 = width - tmp.x1;
sys/dev/drm/drm_rect.c
466
r->y1 = height - tmp.y2;
sys/dev/drm/drm_rect.c
467
r->y2 = height - tmp.y1;
sys/dev/drm/drm_rect.c
55
u64 tmp = mul_u32_u32(src, dst - clip);
sys/dev/drm/drm_rect.c
62
return DIV_ROUND_UP_ULL(tmp, dst);
sys/dev/drm/drm_rect.c
64
return DIV_ROUND_DOWN_ULL(tmp, dst);
sys/dev/drm/drm_syncobj.c
175
struct drm_syncobj_cb *cur, *tmp;
sys/dev/drm/drm_syncobj.c
187
list_for_each_entry_safe(cur, tmp, &syncobj->cb_list, node) {
sys/dev/drm/i915/i915_cmd_parser.c
844
struct hlist_node *tmp;
sys/dev/drm/i915/i915_cmd_parser.c
848
hash_for_each_safe(engine->cmd_hash, i, tmp, desc_node, node) {
sys/dev/drm/i915/i915_drv.c
1322
u32 tmp;
sys/dev/drm/i915/i915_drv.c
1329
tmp = val & BXT_DRAM_RANK_MASK;
sys/dev/drm/i915/i915_drv.c
1331
if (tmp == BXT_DRAM_RANK_SINGLE)
sys/dev/drm/i915/i915_drv.c
1333
else if (tmp == BXT_DRAM_RANK_DUAL)
sys/dev/drm/i915/i915_drv.c
1338
tmp = val & BXT_DRAM_SIZE_MASK;
sys/dev/drm/i915/i915_drv.c
1339
if (tmp == BXT_DRAM_SIZE_4GB)
sys/dev/drm/i915/i915_drv.c
1341
else if (tmp == BXT_DRAM_SIZE_6GB)
sys/dev/drm/i915/i915_drv.c
1343
else if (tmp == BXT_DRAM_SIZE_8GB)
sys/dev/drm/i915/i915_drv.c
1345
else if (tmp == BXT_DRAM_SIZE_12GB)
sys/dev/drm/i915/i915_drv.c
1347
else if (tmp == BXT_DRAM_SIZE_16GB)
sys/dev/drm/i915/i915_drv.c
1352
tmp = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
sys/dev/drm/i915/i915_drv.c
1353
width = (1 << tmp) * 8;
sys/dev/drm/i915/i915_gpu_error.c
148
va_list tmp;
sys/dev/drm/i915/i915_gpu_error.c
150
va_copy(tmp, args);
sys/dev/drm/i915/i915_gpu_error.c
151
len = vsnprintf(NULL, 0, f, tmp);
sys/dev/drm/i915/i915_gpu_error.c
152
va_end(tmp);
sys/dev/drm/i915/i915_gpu_error.c
210
void *tmp;
sys/dev/drm/i915/i915_gpu_error.c
228
c->tmp = NULL;
sys/dev/drm/i915/i915_gpu_error.c
230
c->tmp = (void *)__get_free_page(GFP_ATOMIC | __GFP_NOWARN);
sys/dev/drm/i915/i915_gpu_error.c
256
if (c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
sys/dev/drm/i915/i915_gpu_error.c
257
zstream->next_in = c->tmp;
sys/dev/drm/i915/i915_gpu_error.c
316
if (c->tmp)
sys/dev/drm/i915/i915_gpu_error.c
317
free_page((unsigned long)c->tmp);
sys/dev/drm/i915/i915_irq.c
2049
u32 tmp = I915_READ(PORT_HOTPLUG_STAT) & hotplug_status_mask;
sys/dev/drm/i915/i915_irq.c
2051
if (tmp == 0)
sys/dev/drm/i915/i915_irq.c
2054
hotplug_status |= tmp;
sys/dev/drm/i915/i915_irq.c
3274
unsigned int tmp;
sys/dev/drm/i915/i915_irq.c
3310
for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
sys/dev/drm/i915/i915_irq.c
3338
for_each_engine(engine, dev_priv, tmp) {
sys/dev/drm/i915/i915_irq.c
3348
for_each_engine(engine, dev_priv, tmp) {
sys/dev/drm/i915/i915_perf.c
2765
u64 tmp = NSEC_PER_SEC;
sys/dev/drm/i915/i915_perf.c
2766
do_div(tmp, oa_period);
sys/dev/drm/i915/i915_perf.c
2767
oa_freq_hz = tmp;
sys/dev/drm/i915/i915_perf.c
3160
struct i915_oa_config *oa_config, *tmp;
sys/dev/drm/i915/i915_perf.c
3257
idr_for_each_entry(&dev_priv->perf.metrics_idr, tmp, id) {
sys/dev/drm/i915/i915_perf.c
3258
if (!strcmp(tmp->uuid, oa_config->uuid)) {
sys/dev/drm/i915/i915_request.c
1436
struct intel_ring *ring, *tmp;
sys/dev/drm/i915/i915_request.c
1443
list_for_each_entry_safe(ring, tmp, &i915->gt.active_rings, active_link)
sys/dev/drm/i915/i915_request.c
160
struct i915_dependency *dep, *tmp;
sys/dev/drm/i915/i915_request.c
170
list_for_each_entry_safe(dep, tmp, &node->signalers_list, signal_link) {
sys/dev/drm/i915/i915_request.c
180
list_for_each_entry_safe(dep, tmp, &node->waiters_list, wait_link) {
sys/dev/drm/i915/i915_request.c
395
struct i915_request *tmp;
sys/dev/drm/i915/i915_request.c
401
tmp = list_first_entry(&engine->timeline.requests,
sys/dev/drm/i915/i915_request.c
402
typeof(*tmp), link);
sys/dev/drm/i915/i915_request.c
404
GEM_BUG_ON(tmp->engine != engine);
sys/dev/drm/i915/i915_request.c
405
__retire_engine_request(engine, tmp);
sys/dev/drm/i915/i915_request.c
406
} while (tmp != rq);
sys/dev/drm/i915/i915_request.c
474
struct i915_request *tmp;
sys/dev/drm/i915/i915_request.c
489
tmp = list_first_entry(&ring->request_list,
sys/dev/drm/i915/i915_request.c
490
typeof(*tmp), ring_link);
sys/dev/drm/i915/i915_request.c
492
i915_request_retire(tmp);
sys/dev/drm/i915/i915_request.c
493
} while (tmp != rq);
sys/dev/drm/i915/icl_dsi.c
102
tmp = I915_READ(ICL_PORT_CL_DW10(port));
sys/dev/drm/i915/icl_dsi.c
103
tmp &= ~PWR_DOWN_LN_MASK;
sys/dev/drm/i915/icl_dsi.c
104
I915_WRITE(ICL_PORT_CL_DW10(port), tmp | lane_mask);
sys/dev/drm/i915/icl_dsi.c
62
u32 tmp;
sys/dev/drm/i915/icl_dsi.c
65
tmp = I915_READ(ICL_DSI_IO_MODECTL(port));
sys/dev/drm/i915/icl_dsi.c
66
tmp |= COMBO_PHY_MODE_DSI;
sys/dev/drm/i915/icl_dsi.c
67
I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp);
sys/dev/drm/i915/icl_dsi.c
82
u32 tmp;
sys/dev/drm/i915/intel_audio.c
234
u32 tmp;
sys/dev/drm/i915/intel_audio.c
237
tmp = I915_READ(reg_eldv);
sys/dev/drm/i915/intel_audio.c
238
tmp &= bits_eldv;
sys/dev/drm/i915/intel_audio.c
240
if (!tmp)
sys/dev/drm/i915/intel_audio.c
243
tmp = I915_READ(reg_elda);
sys/dev/drm/i915/intel_audio.c
244
tmp &= ~bits_elda;
sys/dev/drm/i915/intel_audio.c
245
I915_WRITE(reg_elda, tmp);
sys/dev/drm/i915/intel_audio.c
259
u32 eldv, tmp;
sys/dev/drm/i915/intel_audio.c
263
tmp = I915_READ(G4X_AUD_VID_DID);
sys/dev/drm/i915/intel_audio.c
264
if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
sys/dev/drm/i915/intel_audio.c
270
tmp = I915_READ(G4X_AUD_CNTL_ST);
sys/dev/drm/i915/intel_audio.c
271
tmp &= ~eldv;
sys/dev/drm/i915/intel_audio.c
272
I915_WRITE(G4X_AUD_CNTL_ST, tmp);
sys/dev/drm/i915/intel_audio.c
283
u32 tmp;
sys/dev/drm/i915/intel_audio.c
288
tmp = I915_READ(G4X_AUD_VID_DID);
sys/dev/drm/i915/intel_audio.c
289
if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
sys/dev/drm/i915/intel_audio.c
300
tmp = I915_READ(G4X_AUD_CNTL_ST);
sys/dev/drm/i915/intel_audio.c
301
tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
sys/dev/drm/i915/intel_audio.c
302
len = (tmp >> 9) & 0x1f; /* ELD buffer size */
sys/dev/drm/i915/intel_audio.c
303
I915_WRITE(G4X_AUD_CNTL_ST, tmp);
sys/dev/drm/i915/intel_audio.c
310
tmp = I915_READ(G4X_AUD_CNTL_ST);
sys/dev/drm/i915/intel_audio.c
311
tmp |= eldv;
sys/dev/drm/i915/intel_audio.c
312
I915_WRITE(G4X_AUD_CNTL_ST, tmp);
sys/dev/drm/i915/intel_audio.c
326
u32 tmp;
sys/dev/drm/i915/intel_audio.c
335
tmp = I915_READ(HSW_AUD_CFG(pipe));
sys/dev/drm/i915/intel_audio.c
336
tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
sys/dev/drm/i915/intel_audio.c
337
tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
sys/dev/drm/i915/intel_audio.c
338
tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
sys/dev/drm/i915/intel_audio.c
339
tmp |= AUD_CONFIG_N_VALUE_INDEX;
sys/dev/drm/i915/intel_audio.c
342
tmp &= ~AUD_CONFIG_N_MASK;
sys/dev/drm/i915/intel_audio.c
343
tmp |= AUD_CONFIG_N(nm->n);
sys/dev/drm/i915/intel_audio.c
344
tmp |= AUD_CONFIG_N_PROG_ENABLE;
sys/dev/drm/i915/intel_audio.c
347
I915_WRITE(HSW_AUD_CFG(pipe), tmp);
sys/dev/drm/i915/intel_audio.c
349
tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe));
sys/dev/drm/i915/intel_audio.c
350
tmp &= ~AUD_CONFIG_M_MASK;
sys/dev/drm/i915/intel_audio.c
351
tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
sys/dev/drm/i915/intel_audio.c
352
tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
sys/dev/drm/i915/intel_audio.c
355
tmp |= nm->m;
sys/dev/drm/i915/intel_audio.c
356
tmp |= AUD_M_CTS_M_VALUE_INDEX;
sys/dev/drm/i915/intel_audio.c
357
tmp |= AUD_M_CTS_M_PROG_ENABLE;
sys/dev/drm/i915/intel_audio.c
360
I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp);
sys/dev/drm/i915/intel_audio.c
373
u32 tmp;
sys/dev/drm/i915/intel_audio.c
377
tmp = I915_READ(HSW_AUD_CFG(pipe));
sys/dev/drm/i915/intel_audio.c
378
tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
sys/dev/drm/i915/intel_audio.c
379
tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
sys/dev/drm/i915/intel_audio.c
380
tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
sys/dev/drm/i915/intel_audio.c
381
tmp |= audio_config_hdmi_pixel_clock(crtc_state);
sys/dev/drm/i915/intel_audio.c
387
tmp &= ~AUD_CONFIG_N_MASK;
sys/dev/drm/i915/intel_audio.c
388
tmp |= AUD_CONFIG_N(n);
sys/dev/drm/i915/intel_audio.c
389
tmp |= AUD_CONFIG_N_PROG_ENABLE;
sys/dev/drm/i915/intel_audio.c
394
I915_WRITE(HSW_AUD_CFG(pipe), tmp);
sys/dev/drm/i915/intel_audio.c
400
tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe));
sys/dev/drm/i915/intel_audio.c
401
tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
sys/dev/drm/i915/intel_audio.c
402
tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
sys/dev/drm/i915/intel_audio.c
403
I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp);
sys/dev/drm/i915/intel_audio.c
423
u32 tmp;
sys/dev/drm/i915/intel_audio.c
430
tmp = I915_READ(HSW_AUD_CFG(pipe));
sys/dev/drm/i915/intel_audio.c
431
tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
sys/dev/drm/i915/intel_audio.c
432
tmp |= AUD_CONFIG_N_PROG_ENABLE;
sys/dev/drm/i915/intel_audio.c
433
tmp &= ~AUD_CONFIG_UPPER_N_MASK;
sys/dev/drm/i915/intel_audio.c
434
tmp &= ~AUD_CONFIG_LOWER_N_MASK;
sys/dev/drm/i915/intel_audio.c
436
tmp |= AUD_CONFIG_N_VALUE_INDEX;
sys/dev/drm/i915/intel_audio.c
437
I915_WRITE(HSW_AUD_CFG(pipe), tmp);
sys/dev/drm/i915/intel_audio.c
440
tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
sys/dev/drm/i915/intel_audio.c
441
tmp &= ~AUDIO_ELD_VALID(pipe);
sys/dev/drm/i915/intel_audio.c
442
tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);
sys/dev/drm/i915/intel_audio.c
443
I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
sys/dev/drm/i915/intel_audio.c
457
u32 tmp;
sys/dev/drm/i915/intel_audio.c
466
tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
sys/dev/drm/i915/intel_audio.c
467
tmp |= AUDIO_OUTPUT_ENABLE(pipe);
sys/dev/drm/i915/intel_audio.c
468
tmp &= ~AUDIO_ELD_VALID(pipe);
sys/dev/drm/i915/intel_audio.c
469
I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
sys/dev/drm/i915/intel_audio.c
479
tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
sys/dev/drm/i915/intel_audio.c
480
tmp &= ~IBX_ELD_ADDRESS_MASK;
sys/dev/drm/i915/intel_audio.c
481
I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
sys/dev/drm/i915/intel_audio.c
489
tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
sys/dev/drm/i915/intel_audio.c
490
tmp |= AUDIO_ELD_VALID(pipe);
sys/dev/drm/i915/intel_audio.c
491
I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
sys/dev/drm/i915/intel_audio.c
507
u32 tmp, eldv;
sys/dev/drm/i915/intel_audio.c
528
tmp = I915_READ(aud_config);
sys/dev/drm/i915/intel_audio.c
529
tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
sys/dev/drm/i915/intel_audio.c
530
tmp |= AUD_CONFIG_N_PROG_ENABLE;
sys/dev/drm/i915/intel_audio.c
531
tmp &= ~AUD_CONFIG_UPPER_N_MASK;
sys/dev/drm/i915/intel_audio.c
532
tmp &= ~AUD_CONFIG_LOWER_N_MASK;
sys/dev/drm/i915/intel_audio.c
534
tmp |= AUD_CONFIG_N_VALUE_INDEX;
sys/dev/drm/i915/intel_audio.c
535
I915_WRITE(aud_config, tmp);
sys/dev/drm/i915/intel_audio.c
540
tmp = I915_READ(aud_cntrl_st2);
sys/dev/drm/i915/intel_audio.c
541
tmp &= ~eldv;
sys/dev/drm/i915/intel_audio.c
542
I915_WRITE(aud_cntrl_st2, tmp);
sys/dev/drm/i915/intel_audio.c
555
u32 tmp, eldv;
sys/dev/drm/i915/intel_audio.c
593
tmp = I915_READ(aud_cntrl_st2);
sys/dev/drm/i915/intel_audio.c
594
tmp &= ~eldv;
sys/dev/drm/i915/intel_audio.c
595
I915_WRITE(aud_cntrl_st2, tmp);
sys/dev/drm/i915/intel_audio.c
598
tmp = I915_READ(aud_cntl_st);
sys/dev/drm/i915/intel_audio.c
599
tmp &= ~IBX_ELD_ADDRESS_MASK;
sys/dev/drm/i915/intel_audio.c
600
I915_WRITE(aud_cntl_st, tmp);
sys/dev/drm/i915/intel_audio.c
608
tmp = I915_READ(aud_cntrl_st2);
sys/dev/drm/i915/intel_audio.c
609
tmp |= eldv;
sys/dev/drm/i915/intel_audio.c
610
I915_WRITE(aud_cntrl_st2, tmp);
sys/dev/drm/i915/intel_audio.c
613
tmp = I915_READ(aud_config);
sys/dev/drm/i915/intel_audio.c
614
tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
sys/dev/drm/i915/intel_audio.c
615
tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
sys/dev/drm/i915/intel_audio.c
616
tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
sys/dev/drm/i915/intel_audio.c
618
tmp |= AUD_CONFIG_N_VALUE_INDEX;
sys/dev/drm/i915/intel_audio.c
620
tmp |= audio_config_hdmi_pixel_clock(crtc_state);
sys/dev/drm/i915/intel_audio.c
621
I915_WRITE(aud_config, tmp);
sys/dev/drm/i915/intel_audio.c
760
u32 tmp;
sys/dev/drm/i915/intel_audio.c
771
tmp = I915_READ(HSW_AUD_CHICKENBIT);
sys/dev/drm/i915/intel_audio.c
772
tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
sys/dev/drm/i915/intel_audio.c
773
I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
sys/dev/drm/i915/intel_audio.c
777
tmp = I915_READ(HSW_AUD_CHICKENBIT);
sys/dev/drm/i915/intel_audio.c
778
tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
sys/dev/drm/i915/intel_audio.c
779
I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
sys/dev/drm/i915/intel_cdclk.c
221
uint8_t tmp = 0;
sys/dev/drm/i915/intel_cdclk.c
237
tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
sys/dev/drm/i915/intel_cdclk.c
239
vco = vco_table[tmp & 0x7];
sys/dev/drm/i915/intel_cdclk.c
241
DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
sys/dev/drm/i915/intel_cdclk.c
258
uint16_t tmp = 0;
sys/dev/drm/i915/intel_cdclk.c
262
pci_read_config_word(pdev, GCFGC, &tmp);
sys/dev/drm/i915/intel_cdclk.c
264
cdclk_sel = (tmp >> 4) & 0x7;
sys/dev/drm/i915/intel_cdclk.c
292
cdclk_state->vco, tmp);
sys/dev/drm/i915/intel_cdclk.c
338
uint16_t tmp = 0;
sys/dev/drm/i915/intel_cdclk.c
342
pci_read_config_word(pdev, GCFGC, &tmp);
sys/dev/drm/i915/intel_cdclk.c
344
cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
sys/dev/drm/i915/intel_cdclk.c
369
cdclk_state->vco, tmp);
sys/dev/drm/i915/intel_cdclk.c
378
uint16_t tmp = 0;
sys/dev/drm/i915/intel_cdclk.c
382
pci_read_config_word(pdev, GCFGC, &tmp);
sys/dev/drm/i915/intel_cdclk.c
384
cdclk_sel = (tmp >> 12) & 0x1;
sys/dev/drm/i915/intel_cdclk.c
397
cdclk_state->vco, tmp);
sys/dev/drm/i915/intel_crt.c
104
u32 tmp, flags = 0;
sys/dev/drm/i915/intel_crt.c
106
tmp = I915_READ(crt->adpa_reg);
sys/dev/drm/i915/intel_crt.c
108
if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
sys/dev/drm/i915/intel_crt.c
113
if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
sys/dev/drm/i915/intel_crt.c
778
struct intel_load_detect_pipe tmp;
sys/dev/drm/i915/intel_crt.c
829
ret = intel_get_load_detect_pipe(connector, NULL, &tmp, ctx);
sys/dev/drm/i915/intel_crt.c
840
intel_release_load_detect_pipe(connector, &tmp, ctx);
sys/dev/drm/i915/intel_ddi.c
1457
u64 tmp;
sys/dev/drm/i915/intel_ddi.c
1498
tmp = (u64)m1 * m2_int * refclk +
sys/dev/drm/i915/intel_ddi.c
1500
tmp = div_u64(tmp, 5 * div1 * div2);
sys/dev/drm/i915/intel_ddi.c
1502
return tmp;
sys/dev/drm/i915/intel_ddi.c
1919
uint32_t tmp;
sys/dev/drm/i915/intel_ddi.c
1930
tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
sys/dev/drm/i915/intel_ddi.c
1932
tmp |= TRANS_DDI_HDCP_SIGNALLING;
sys/dev/drm/i915/intel_ddi.c
1934
tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
sys/dev/drm/i915/intel_ddi.c
1935
I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
sys/dev/drm/i915/intel_ddi.c
1950
uint32_t tmp;
sys/dev/drm/i915/intel_ddi.c
1967
tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
sys/dev/drm/i915/intel_ddi.c
1969
switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
sys/dev/drm/i915/intel_ddi.c
2008
u32 tmp;
sys/dev/drm/i915/intel_ddi.c
2017
tmp = I915_READ(DDI_BUF_CTL(port));
sys/dev/drm/i915/intel_ddi.c
2019
if (!(tmp & DDI_BUF_CTL_ENABLE))
sys/dev/drm/i915/intel_ddi.c
2023
tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
sys/dev/drm/i915/intel_ddi.c
2025
switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
sys/dev/drm/i915/intel_ddi.c
2046
tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
sys/dev/drm/i915/intel_ddi.c
2048
if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
sys/dev/drm/i915/intel_ddi.c
2049
if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
sys/dev/drm/i915/intel_ddi.c
2064
tmp = I915_READ(BXT_PHY_CTL(port));
sys/dev/drm/i915/intel_ddi.c
2065
if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
sys/dev/drm/i915/intel_ddi.c
2069
"(PHY_CTL %08x)\n", port_name(port), tmp);
sys/dev/drm/i915/intel_ddi.c
2149
u32 tmp;
sys/dev/drm/i915/intel_ddi.c
2151
tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
sys/dev/drm/i915/intel_ddi.c
2152
tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
sys/dev/drm/i915/intel_ddi.c
2154
tmp |= iboost << BALANCE_LEG_SHIFT(port);
sys/dev/drm/i915/intel_ddi.c
2156
tmp |= BALANCE_LEG_DISABLE(port);
sys/dev/drm/i915/intel_ddi.c
2157
I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
sys/dev/drm/i915/intel_display.c
1432
u32 tmp;
sys/dev/drm/i915/intel_display.c
1437
tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
sys/dev/drm/i915/intel_display.c
1438
tmp |= DPIO_DCLKP_EN;
sys/dev/drm/i915/intel_display.c
1439
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
sys/dev/drm/i915/intel_display.c
7484
uint32_t tmp;
sys/dev/drm/i915/intel_display.c
7486
tmp = I915_READ(HTOTAL(cpu_transcoder));
sys/dev/drm/i915/intel_display.c
7487
pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
sys/dev/drm/i915/intel_display.c
7488
pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
sys/dev/drm/i915/intel_display.c
7489
tmp = I915_READ(HBLANK(cpu_transcoder));
sys/dev/drm/i915/intel_display.c
7490
pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
sys/dev/drm/i915/intel_display.c
7491
pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
sys/dev/drm/i915/intel_display.c
7492
tmp = I915_READ(HSYNC(cpu_transcoder));
sys/dev/drm/i915/intel_display.c
7493
pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
sys/dev/drm/i915/intel_display.c
7494
pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
sys/dev/drm/i915/intel_display.c
7496
tmp = I915_READ(VTOTAL(cpu_transcoder));
sys/dev/drm/i915/intel_display.c
7497
pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
sys/dev/drm/i915/intel_display.c
7498
pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
sys/dev/drm/i915/intel_display.c
7499
tmp = I915_READ(VBLANK(cpu_transcoder));
sys/dev/drm/i915/intel_display.c
7500
pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
sys/dev/drm/i915/intel_display.c
7501
pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
sys/dev/drm/i915/intel_display.c
7502
tmp = I915_READ(VSYNC(cpu_transcoder));
sys/dev/drm/i915/intel_display.c
7503
pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
sys/dev/drm/i915/intel_display.c
7504
pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
sys/dev/drm/i915/intel_display.c
7518
u32 tmp;
sys/dev/drm/i915/intel_display.c
7520
tmp = I915_READ(PIPESRC(crtc->pipe));
sys/dev/drm/i915/intel_display.c
7521
pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
sys/dev/drm/i915/intel_display.c
7522
pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
sys/dev/drm/i915/intel_display.c
7799
uint32_t tmp;
sys/dev/drm/i915/intel_display.c
7805
tmp = I915_READ(PFIT_CONTROL);
sys/dev/drm/i915/intel_display.c
7806
if (!(tmp & PFIT_ENABLE))
sys/dev/drm/i915/intel_display.c
7814
if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
sys/dev/drm/i915/intel_display.c
7818
pipe_config->gmch_pfit.control = tmp;
sys/dev/drm/i915/intel_display.c
7971
uint32_t tmp;
sys/dev/drm/i915/intel_display.c
7983
tmp = I915_READ(PIPECONF(crtc->pipe));
sys/dev/drm/i915/intel_display.c
7984
if (!(tmp & PIPECONF_ENABLE))
sys/dev/drm/i915/intel_display.c
7989
switch (tmp & PIPECONF_BPC_MASK) {
sys/dev/drm/i915/intel_display.c
8005
(tmp & PIPECONF_COLOR_RANGE_SELECT))
sys/dev/drm/i915/intel_display.c
8009
pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
sys/dev/drm/i915/intel_display.c
8019
tmp = dev_priv->chv_dpll_md[crtc->pipe];
sys/dev/drm/i915/intel_display.c
8021
tmp = I915_READ(DPLL_MD(crtc->pipe));
sys/dev/drm/i915/intel_display.c
8023
((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
sys/dev/drm/i915/intel_display.c
8025
pipe_config->dpll_hw_state.dpll_md = tmp;
sys/dev/drm/i915/intel_display.c
8028
tmp = I915_READ(DPLL(crtc->pipe));
sys/dev/drm/i915/intel_display.c
8030
((tmp & SDVO_MULTIPLIER_MASK)
sys/dev/drm/i915/intel_display.c
8249
uint32_t tmp;
sys/dev/drm/i915/intel_display.c
8251
tmp = I915_READ(SOUTH_CHICKEN2);
sys/dev/drm/i915/intel_display.c
8252
tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
sys/dev/drm/i915/intel_display.c
8253
I915_WRITE(SOUTH_CHICKEN2, tmp);
sys/dev/drm/i915/intel_display.c
8259
tmp = I915_READ(SOUTH_CHICKEN2);
sys/dev/drm/i915/intel_display.c
8260
tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
sys/dev/drm/i915/intel_display.c
8261
I915_WRITE(SOUTH_CHICKEN2, tmp);
sys/dev/drm/i915/intel_display.c
8271
uint32_t tmp;
sys/dev/drm/i915/intel_display.c
8273
tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8274
tmp &= ~(0xFF << 24);
sys/dev/drm/i915/intel_display.c
8275
tmp |= (0x12 << 24);
sys/dev/drm/i915/intel_display.c
8276
intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8278
tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8279
tmp |= (1 << 11);
sys/dev/drm/i915/intel_display.c
8280
intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8282
tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8283
tmp |= (1 << 11);
sys/dev/drm/i915/intel_display.c
8284
intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8286
tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8287
tmp |= (1 << 24) | (1 << 21) | (1 << 18);
sys/dev/drm/i915/intel_display.c
8288
intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8290
tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8291
tmp |= (1 << 24) | (1 << 21) | (1 << 18);
sys/dev/drm/i915/intel_display.c
8292
intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8294
tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8295
tmp &= ~(7 << 13);
sys/dev/drm/i915/intel_display.c
8296
tmp |= (5 << 13);
sys/dev/drm/i915/intel_display.c
8297
intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8299
tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8300
tmp &= ~(7 << 13);
sys/dev/drm/i915/intel_display.c
8301
tmp |= (5 << 13);
sys/dev/drm/i915/intel_display.c
8302
intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8304
tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8305
tmp &= ~0xFF;
sys/dev/drm/i915/intel_display.c
8306
tmp |= 0x1C;
sys/dev/drm/i915/intel_display.c
8307
intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8309
tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8310
tmp &= ~0xFF;
sys/dev/drm/i915/intel_display.c
8311
tmp |= 0x1C;
sys/dev/drm/i915/intel_display.c
8312
intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8314
tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8315
tmp &= ~(0xFF << 16);
sys/dev/drm/i915/intel_display.c
8316
tmp |= (0x1C << 16);
sys/dev/drm/i915/intel_display.c
8317
intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8319
tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8320
tmp &= ~(0xFF << 16);
sys/dev/drm/i915/intel_display.c
8321
tmp |= (0x1C << 16);
sys/dev/drm/i915/intel_display.c
8322
intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8324
tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8325
tmp |= (1 << 27);
sys/dev/drm/i915/intel_display.c
8326
intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8328
tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8329
tmp |= (1 << 27);
sys/dev/drm/i915/intel_display.c
8330
intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8332
tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8333
tmp &= ~(0xF << 28);
sys/dev/drm/i915/intel_display.c
8334
tmp |= (4 << 28);
sys/dev/drm/i915/intel_display.c
8335
intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8337
tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8338
tmp &= ~(0xF << 28);
sys/dev/drm/i915/intel_display.c
8339
tmp |= (4 << 28);
sys/dev/drm/i915/intel_display.c
8340
intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
sys/dev/drm/i915/intel_display.c
8352
uint32_t reg, tmp;
sys/dev/drm/i915/intel_display.c
8362
tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
sys/dev/drm/i915/intel_display.c
8363
tmp &= ~SBI_SSCCTL_DISABLE;
sys/dev/drm/i915/intel_display.c
8364
tmp |= SBI_SSCCTL_PATHALT;
sys/dev/drm/i915/intel_display.c
8365
intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
sys/dev/drm/i915/intel_display.c
8370
tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
sys/dev/drm/i915/intel_display.c
8371
tmp &= ~SBI_SSCCTL_PATHALT;
sys/dev/drm/i915/intel_display.c
8372
intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
sys/dev/drm/i915/intel_display.c
8381
tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
sys/dev/drm/i915/intel_display.c
8382
tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
sys/dev/drm/i915/intel_display.c
8383
intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
sys/dev/drm/i915/intel_display.c
8391
uint32_t reg, tmp;
sys/dev/drm/i915/intel_display.c
8396
tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
sys/dev/drm/i915/intel_display.c
8397
tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
sys/dev/drm/i915/intel_display.c
8398
intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
sys/dev/drm/i915/intel_display.c
8400
tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
sys/dev/drm/i915/intel_display.c
8401
if (!(tmp & SBI_SSCCTL_DISABLE)) {
sys/dev/drm/i915/intel_display.c
8402
if (!(tmp & SBI_SSCCTL_PATHALT)) {
sys/dev/drm/i915/intel_display.c
8403
tmp |= SBI_SSCCTL_PATHALT;
sys/dev/drm/i915/intel_display.c
8404
intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
sys/dev/drm/i915/intel_display.c
8407
tmp |= SBI_SSCCTL_DISABLE;
sys/dev/drm/i915/intel_display.c
8408
intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
sys/dev/drm/i915/intel_display.c
8448
uint32_t tmp;
sys/dev/drm/i915/intel_display.c
8460
tmp = 0xAAAAAAAB;
sys/dev/drm/i915/intel_display.c
8462
tmp = 0x00000000;
sys/dev/drm/i915/intel_display.c
8463
intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
sys/dev/drm/i915/intel_display.c
8465
tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
sys/dev/drm/i915/intel_display.c
8466
tmp &= 0xffff0000;
sys/dev/drm/i915/intel_display.c
8467
tmp |= sscdivintphase[idx];
sys/dev/drm/i915/intel_display.c
8468
intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
sys/dev/drm/i915/intel_display.c
9020
uint32_t tmp;
sys/dev/drm/i915/intel_display.c
9022
tmp = I915_READ(PF_CTL(crtc->pipe));
sys/dev/drm/i915/intel_display.c
9024
if (tmp & PF_ENABLE) {
sys/dev/drm/i915/intel_display.c
9033
WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
sys/dev/drm/i915/intel_display.c
9045
uint32_t tmp;
sys/dev/drm/i915/intel_display.c
9056
tmp = I915_READ(PIPECONF(crtc->pipe));
sys/dev/drm/i915/intel_display.c
9057
if (!(tmp & PIPECONF_ENABLE))
sys/dev/drm/i915/intel_display.c
9060
switch (tmp & PIPECONF_BPC_MASK) {
sys/dev/drm/i915/intel_display.c
9077
if (tmp & PIPECONF_COLOR_RANGE_SELECT)
sys/dev/drm/i915/intel_display.c
9086
tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
sys/dev/drm/i915/intel_display.c
9087
pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
sys/dev/drm/i915/intel_display.c
9099
tmp = I915_READ(PCH_DPLL_SEL);
sys/dev/drm/i915/intel_display.c
9100
if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
sys/dev/drm/i915/intel_display.c
9113
tmp = pipe_config->dpll_hw_state.dpll;
sys/dev/drm/i915/intel_display.c
9115
((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
sys/dev/drm/i915/intel_display.c
9513
u32 tmp;
sys/dev/drm/i915/intel_display.c
9525
tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
sys/dev/drm/i915/intel_display.c
9526
if (tmp & TRANS_DDI_FUNC_ENABLE) {
sys/dev/drm/i915/intel_display.c
9528
switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
sys/dev/drm/i915/intel_display.c
9553
tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
sys/dev/drm/i915/intel_display.c
9555
return tmp & PIPECONF_ENABLE;
sys/dev/drm/i915/intel_display.c
9567
u32 tmp;
sys/dev/drm/i915/intel_display.c
9591
tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
sys/dev/drm/i915/intel_display.c
9592
if (!(tmp & DPI_ENABLE))
sys/dev/drm/i915/intel_display.c
9595
tmp = I915_READ(MIPI_CTRL(port));
sys/dev/drm/i915/intel_display.c
9596
if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
sys/dev/drm/i915/intel_display.c
9612
uint32_t tmp;
sys/dev/drm/i915/intel_display.c
9614
tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
sys/dev/drm/i915/intel_display.c
9616
port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
sys/dev/drm/i915/intel_display.c
9644
tmp = I915_READ(FDI_RX_CTL(PIPE_A));
sys/dev/drm/i915/intel_display.c
9645
pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
sys/dev/drm/i915/intel_display.c
9691
u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
sys/dev/drm/i915/intel_display.c
9692
bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
sys/dev/drm/i915/intel_display.c
9695
bool blend_mode_420 = tmp &
sys/dev/drm/i915/intel_display.c
9698
pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE;
sys/dev/drm/i915/intel_display.c
9701
DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp);
sys/dev/drm/i915/intel_dp.c
2904
u32 tmp, flags = 0;
sys/dev/drm/i915/intel_dp.c
2913
tmp = I915_READ(intel_dp->output_reg);
sys/dev/drm/i915/intel_dp.c
2915
pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
sys/dev/drm/i915/intel_dp.c
2930
if (tmp & DP_SYNC_HS_HIGH)
sys/dev/drm/i915/intel_dp.c
2935
if (tmp & DP_SYNC_VS_HIGH)
sys/dev/drm/i915/intel_dp.c
2943
if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
sys/dev/drm/i915/intel_dp.c
2947
((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
sys/dev/drm/i915/intel_dpll_mgr.c
2721
uint64_t tmp;
sys/dev/drm/i915/intel_dpll_mgr.c
2744
tmp = (uint64_t)m2div_rem * (1 << 22);
sys/dev/drm/i915/intel_dpll_mgr.c
2745
do_div(tmp, refclk_khz * m1div);
sys/dev/drm/i915/intel_dpll_mgr.c
2746
m2div_frac = tmp;
sys/dev/drm/i915/intel_dpll_mgr.c
2803
tmp = (uint64_t)dco_khz * 47 * 32;
sys/dev/drm/i915/intel_dpll_mgr.c
2804
do_div(tmp, refclk_khz * m1div * 10000);
sys/dev/drm/i915/intel_dpll_mgr.c
2805
ssc_stepsize = tmp;
sys/dev/drm/i915/intel_dpll_mgr.c
2807
tmp = (uint64_t)dco_khz * 1000;
sys/dev/drm/i915/intel_dpll_mgr.c
2808
ssc_steplen = DIV_ROUND_UP_ULL(tmp, 32 * 2 * 32);
sys/dev/drm/i915/intel_dpll_mgr.c
332
struct intel_shared_dpll_state tmp;
sys/dev/drm/i915/intel_dpll_mgr.c
336
tmp = pll->state;
sys/dev/drm/i915/intel_dpll_mgr.c
338
shared_dpll[i] = tmp;
sys/dev/drm/i915/intel_dsi_vbt.c
209
u32 tmp;
sys/dev/drm/i915/intel_dsi_vbt.c
244
tmp = 0x4 | value;
sys/dev/drm/i915/intel_dsi_vbt.c
245
vlv_iosf_sb_write(dev_priv, port, padval, tmp);
sys/dev/drm/i915/intel_dvo.c
127
u32 tmp;
sys/dev/drm/i915/intel_dvo.c
129
tmp = I915_READ(intel_dvo->dev.dvo_reg);
sys/dev/drm/i915/intel_dvo.c
131
if (!(tmp & DVO_ENABLE))
sys/dev/drm/i915/intel_dvo.c
142
u32 tmp;
sys/dev/drm/i915/intel_dvo.c
144
tmp = I915_READ(intel_dvo->dev.dvo_reg);
sys/dev/drm/i915/intel_dvo.c
146
*pipe = (tmp & DVO_PIPE_SEL_MASK) >> DVO_PIPE_SEL_SHIFT;
sys/dev/drm/i915/intel_dvo.c
148
return tmp & DVO_ENABLE;
sys/dev/drm/i915/intel_dvo.c
156
u32 tmp, flags = 0;
sys/dev/drm/i915/intel_dvo.c
160
tmp = I915_READ(intel_dvo->dev.dvo_reg);
sys/dev/drm/i915/intel_dvo.c
161
if (tmp & DVO_HSYNC_ACTIVE_HIGH)
sys/dev/drm/i915/intel_dvo.c
165
if (tmp & DVO_VSYNC_ACTIVE_HIGH)
sys/dev/drm/i915/intel_guc_submission.c
351
unsigned int tmp;
sys/dev/drm/i915/intel_guc_submission.c
365
for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
sys/dev/drm/i915/intel_hangcheck.c
167
u32 tmp = current_instdone | *old_instdone;
sys/dev/drm/i915/intel_hangcheck.c
170
unchanged = tmp == *old_instdone;
sys/dev/drm/i915/intel_hangcheck.c
171
*old_instdone |= tmp;
sys/dev/drm/i915/intel_hangcheck.c
233
u32 tmp;
sys/dev/drm/i915/intel_hangcheck.c
247
tmp = I915_READ_CTL(engine);
sys/dev/drm/i915/intel_hangcheck.c
248
if (tmp & RING_WAIT) {
sys/dev/drm/i915/intel_hangcheck.c
251
I915_WRITE_CTL(engine, tmp);
sys/dev/drm/i915/intel_hangcheck.c
255
if (IS_GEN(dev_priv, 6, 7) && tmp & RING_WAIT_SEMAPHORE) {
sys/dev/drm/i915/intel_hangcheck.c
263
I915_WRITE_CTL(engine, tmp);
sys/dev/drm/i915/intel_hangcheck.c
383
unsigned int tmp;
sys/dev/drm/i915/intel_hangcheck.c
393
for_each_engine_masked(engine, i915, hung, tmp)
sys/dev/drm/i915/intel_hdmi.c
1200
u32 tmp, flags = 0;
sys/dev/drm/i915/intel_hdmi.c
1205
tmp = I915_READ(intel_hdmi->hdmi_reg);
sys/dev/drm/i915/intel_hdmi.c
1207
if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
sys/dev/drm/i915/intel_hdmi.c
1212
if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
sys/dev/drm/i915/intel_hdmi.c
1217
if (tmp & HDMI_MODE_SELECT_HDMI)
sys/dev/drm/i915/intel_hdmi.c
1223
if (tmp & SDVO_AUDIO_ENABLE)
sys/dev/drm/i915/intel_hdmi.c
1227
tmp & HDMI_COLOR_RANGE_16_235)
sys/dev/drm/i915/intel_hdmi.c
1232
if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
sys/dev/drm/i915/intel_lvds.c
126
u32 tmp, flags = 0;
sys/dev/drm/i915/intel_lvds.c
130
tmp = I915_READ(lvds_encoder->reg);
sys/dev/drm/i915/intel_lvds.c
131
if (tmp & LVDS_HSYNC_POLARITY)
sys/dev/drm/i915/intel_lvds.c
135
if (tmp & LVDS_VSYNC_POLARITY)
sys/dev/drm/i915/intel_lvds.c
144
tmp & LVDS_BORDER_ENABLE;
sys/dev/drm/i915/intel_lvds.c
148
tmp = I915_READ(PFIT_CONTROL);
sys/dev/drm/i915/intel_lvds.c
150
pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
sys/dev/drm/i915/intel_opregion.c
853
u32 tmp;
sys/dev/drm/i915/intel_opregion.c
860
if (swsci(dev_priv, SWSCI_GBDA_SUPPORTED_CALLS, 0, &tmp) == 0) {
sys/dev/drm/i915/intel_opregion.c
862
tmp <<= 1;
sys/dev/drm/i915/intel_opregion.c
863
opregion->swsci_gbda_sub_functions |= tmp;
sys/dev/drm/i915/intel_opregion.c
871
if (swsci(dev_priv, SWSCI_GBDA_REQUESTED_CALLBACKS, 0, &tmp) == 0) {
sys/dev/drm/i915/intel_opregion.c
873
opregion->swsci_sbcb_sub_functions |= tmp;
sys/dev/drm/i915/intel_opregion.c
882
if (swsci(dev_priv, SWSCI_SBCB_SUPPORTED_CALLBACKS, 0, &tmp) == 0) {
sys/dev/drm/i915/intel_opregion.c
884
u32 low = tmp & 0x7ff;
sys/dev/drm/i915/intel_opregion.c
885
u32 high = tmp & ~0xfff; /* bit 11 is reserved */
sys/dev/drm/i915/intel_opregion.c
886
tmp = (high << 4) | (low << 1) | 1;
sys/dev/drm/i915/intel_opregion.c
891
if ((req & tmp) != req)
sys/dev/drm/i915/intel_opregion.c
892
DRM_DEBUG_DRIVER("SWSCI BIOS requested (%08x) SBCB callbacks that are not supported (%08x)\n", req, tmp);
sys/dev/drm/i915/intel_opregion.c
896
opregion->swsci_sbcb_sub_functions |= tmp;
sys/dev/drm/i915/intel_overlay.c
1020
tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
sys/dev/drm/i915/intel_overlay.c
1022
if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
sys/dev/drm/i915/intel_overlay.c
1033
tmp = rec->stride_Y*rec->src_height;
sys/dev/drm/i915/intel_overlay.c
1034
if (rec->offset_Y + tmp > new_bo->base.size)
sys/dev/drm/i915/intel_overlay.c
1044
tmp = rec->stride_Y * rec->src_height;
sys/dev/drm/i915/intel_overlay.c
1045
if (rec->offset_Y + tmp > new_bo->base.size)
sys/dev/drm/i915/intel_overlay.c
1048
tmp = rec->stride_UV * (rec->src_height / uv_vscale);
sys/dev/drm/i915/intel_overlay.c
1049
if (rec->offset_U + tmp > new_bo->base.size ||
sys/dev/drm/i915/intel_overlay.c
1050
rec->offset_V + tmp > new_bo->base.size)
sys/dev/drm/i915/intel_overlay.c
307
u32 tmp, *cs;
sys/dev/drm/i915/intel_overlay.c
315
tmp = I915_READ(DOVSTA);
sys/dev/drm/i915/intel_overlay.c
316
if (tmp & (1 << 17))
sys/dev/drm/i915/intel_overlay.c
317
DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
sys/dev/drm/i915/intel_overlay.c
933
u32 tmp;
sys/dev/drm/i915/intel_overlay.c
936
tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16;
sys/dev/drm/i915/intel_overlay.c
937
if (tmp > 7)
sys/dev/drm/i915/intel_overlay.c
940
tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16;
sys/dev/drm/i915/intel_overlay.c
941
if (tmp > 7)
sys/dev/drm/i915/intel_overlay.c
955
u32 tmp;
sys/dev/drm/i915/intel_panel.c
543
u32 tmp;
sys/dev/drm/i915/intel_panel.c
545
tmp = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
sys/dev/drm/i915/intel_panel.c
546
I915_WRITE(BLC_PWM_CPU_CTL, tmp | level);
sys/dev/drm/i915/intel_panel.c
554
u32 tmp, mask;
sys/dev/drm/i915/intel_panel.c
573
tmp = I915_READ(BLC_PWM_CTL) & ~mask;
sys/dev/drm/i915/intel_panel.c
574
I915_WRITE(BLC_PWM_CTL, tmp | level);
sys/dev/drm/i915/intel_panel.c
582
u32 tmp;
sys/dev/drm/i915/intel_panel.c
584
tmp = I915_READ(VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK;
sys/dev/drm/i915/intel_panel.c
585
I915_WRITE(VLV_BLC_PWM_CTL(pipe), tmp | level);
sys/dev/drm/i915/intel_panel.c
660
u32 tmp;
sys/dev/drm/i915/intel_panel.c
672
tmp = I915_READ(BLC_PWM_CPU_CTL2);
sys/dev/drm/i915/intel_panel.c
673
if (tmp & BLM_PWM_ENABLE) {
sys/dev/drm/i915/intel_panel.c
675
I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE);
sys/dev/drm/i915/intel_panel.c
678
tmp = I915_READ(BLC_PWM_PCH_CTL1);
sys/dev/drm/i915/intel_panel.c
679
I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE);
sys/dev/drm/i915/intel_panel.c
686
u32 tmp;
sys/dev/drm/i915/intel_panel.c
690
tmp = I915_READ(BLC_PWM_CPU_CTL2);
sys/dev/drm/i915/intel_panel.c
691
I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE);
sys/dev/drm/i915/intel_panel.c
693
tmp = I915_READ(BLC_PWM_PCH_CTL1);
sys/dev/drm/i915/intel_panel.c
694
I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE);
sys/dev/drm/i915/intel_panel.c
705
u32 tmp;
sys/dev/drm/i915/intel_panel.c
709
tmp = I915_READ(BLC_PWM_CTL2);
sys/dev/drm/i915/intel_panel.c
710
I915_WRITE(BLC_PWM_CTL2, tmp & ~BLM_PWM_ENABLE);
sys/dev/drm/i915/intel_panel.c
718
u32 tmp;
sys/dev/drm/i915/intel_panel.c
722
tmp = I915_READ(VLV_BLC_PWM_CTL2(pipe));
sys/dev/drm/i915/intel_panel.c
723
I915_WRITE(VLV_BLC_PWM_CTL2(pipe), tmp & ~BLM_PWM_ENABLE);
sys/dev/drm/i915/intel_panel.c
731
u32 tmp, val;
sys/dev/drm/i915/intel_panel.c
735
tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
sys/dev/drm/i915/intel_panel.c
737
tmp & ~BXT_BLC_PWM_ENABLE);
sys/dev/drm/i915/intel_panel.c
751
u32 tmp;
sys/dev/drm/i915/intel_panel.c
755
tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
sys/dev/drm/i915/intel_panel.c
757
tmp & ~BXT_BLC_PWM_ENABLE);
sys/dev/drm/i915/intel_pm.c
143
u32 tmp;
sys/dev/drm/i915/intel_pm.c
145
tmp = I915_READ(CLKCFG);
sys/dev/drm/i915/intel_pm.c
147
switch (tmp & CLKCFG_FSB_MASK) {
sys/dev/drm/i915/intel_pm.c
162
switch (tmp & CLKCFG_MEM_MASK) {
sys/dev/drm/i915/intel_pm.c
175
tmp = I915_READ(CSHRDDR3CTL);
sys/dev/drm/i915/intel_pm.c
176
dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
sys/dev/drm/i915/intel_pm.c
5640
u32 tmp = hw->wm_pipe[pipe];
sys/dev/drm/i915/intel_pm.c
5649
active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
sys/dev/drm/i915/intel_pm.c
5650
active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
sys/dev/drm/i915/intel_pm.c
5651
active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
sys/dev/drm/i915/intel_pm.c
5676
uint32_t tmp;
sys/dev/drm/i915/intel_pm.c
5678
tmp = I915_READ(DSPFW1);
sys/dev/drm/i915/intel_pm.c
5679
wm->sr.plane = _FW_WM(tmp, SR);
sys/dev/drm/i915/intel_pm.c
5680
wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
sys/dev/drm/i915/intel_pm.c
5681
wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
sys/dev/drm/i915/intel_pm.c
5682
wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
sys/dev/drm/i915/intel_pm.c
5684
tmp = I915_READ(DSPFW2);
sys/dev/drm/i915/intel_pm.c
5685
wm->fbc_en = tmp & DSPFW_FBC_SR_EN;
sys/dev/drm/i915/intel_pm.c
5686
wm->sr.fbc = _FW_WM(tmp, FBC_SR);
sys/dev/drm/i915/intel_pm.c
5687
wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
sys/dev/drm/i915/intel_pm.c
5688
wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB);
sys/dev/drm/i915/intel_pm.c
5689
wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
sys/dev/drm/i915/intel_pm.c
5690
wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
sys/dev/drm/i915/intel_pm.c
5692
tmp = I915_READ(DSPFW3);
sys/dev/drm/i915/intel_pm.c
5693
wm->hpll_en = tmp & DSPFW_HPLL_SR_EN;
sys/dev/drm/i915/intel_pm.c
5694
wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
sys/dev/drm/i915/intel_pm.c
5695
wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR);
sys/dev/drm/i915/intel_pm.c
5696
wm->hpll.plane = _FW_WM(tmp, HPLL_SR);
sys/dev/drm/i915/intel_pm.c
5703
uint32_t tmp;
sys/dev/drm/i915/intel_pm.c
5706
tmp = I915_READ(VLV_DDL(pipe));
sys/dev/drm/i915/intel_pm.c
5709
(tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
sys/dev/drm/i915/intel_pm.c
5711
(tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
sys/dev/drm/i915/intel_pm.c
5713
(tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
sys/dev/drm/i915/intel_pm.c
5715
(tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
sys/dev/drm/i915/intel_pm.c
5718
tmp = I915_READ(DSPFW1);
sys/dev/drm/i915/intel_pm.c
5719
wm->sr.plane = _FW_WM(tmp, SR);
sys/dev/drm/i915/intel_pm.c
5720
wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
sys/dev/drm/i915/intel_pm.c
5721
wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
sys/dev/drm/i915/intel_pm.c
5722
wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
sys/dev/drm/i915/intel_pm.c
5724
tmp = I915_READ(DSPFW2);
sys/dev/drm/i915/intel_pm.c
5725
wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
sys/dev/drm/i915/intel_pm.c
5726
wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
sys/dev/drm/i915/intel_pm.c
5727
wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
sys/dev/drm/i915/intel_pm.c
5729
tmp = I915_READ(DSPFW3);
sys/dev/drm/i915/intel_pm.c
5730
wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
sys/dev/drm/i915/intel_pm.c
5733
tmp = I915_READ(DSPFW7_CHV);
sys/dev/drm/i915/intel_pm.c
5734
wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
sys/dev/drm/i915/intel_pm.c
5735
wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
sys/dev/drm/i915/intel_pm.c
5737
tmp = I915_READ(DSPFW8_CHV);
sys/dev/drm/i915/intel_pm.c
5738
wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
sys/dev/drm/i915/intel_pm.c
5739
wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
sys/dev/drm/i915/intel_pm.c
5741
tmp = I915_READ(DSPFW9_CHV);
sys/dev/drm/i915/intel_pm.c
5742
wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
sys/dev/drm/i915/intel_pm.c
5743
wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
sys/dev/drm/i915/intel_pm.c
5745
tmp = I915_READ(DSPHOWM);
sys/dev/drm/i915/intel_pm.c
5746
wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
sys/dev/drm/i915/intel_pm.c
5747
wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
sys/dev/drm/i915/intel_pm.c
5748
wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
sys/dev/drm/i915/intel_pm.c
5749
wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;
sys/dev/drm/i915/intel_pm.c
5750
wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
sys/dev/drm/i915/intel_pm.c
5751
wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
sys/dev/drm/i915/intel_pm.c
5752
wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
sys/dev/drm/i915/intel_pm.c
5753
wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
sys/dev/drm/i915/intel_pm.c
5754
wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
sys/dev/drm/i915/intel_pm.c
5755
wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
sys/dev/drm/i915/intel_pm.c
5757
tmp = I915_READ(DSPFW7);
sys/dev/drm/i915/intel_pm.c
5758
wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
sys/dev/drm/i915/intel_pm.c
5759
wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
sys/dev/drm/i915/intel_pm.c
5761
tmp = I915_READ(DSPHOWM);
sys/dev/drm/i915/intel_pm.c
5762
wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
sys/dev/drm/i915/intel_pm.c
5763
wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
sys/dev/drm/i915/intel_pm.c
5764
wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
sys/dev/drm/i915/intel_pm.c
5765
wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
sys/dev/drm/i915/intel_pm.c
5766
wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
sys/dev/drm/i915/intel_pm.c
5767
wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
sys/dev/drm/i915/intel_pm.c
5768
wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
sys/dev/drm/i915/intel_pm.c
8609
uint32_t tmp;
sys/dev/drm/i915/intel_pm.c
8611
tmp = I915_READ(MCH_SSKPD);
sys/dev/drm/i915/intel_pm.c
8612
if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
sys/dev/drm/i915/intel_pm.c
8614
tmp);
sys/dev/drm/i915/intel_pm.c
9734
u32 lower, upper, tmp;
sys/dev/drm/i915/intel_pm.c
9757
tmp = upper;
sys/dev/drm/i915/intel_pm.c
9766
} while (upper != tmp && --loop);
sys/dev/drm/i915/intel_runtime_pm.c
1218
uint32_t tmp;
sys/dev/drm/i915/intel_runtime_pm.c
1246
tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
sys/dev/drm/i915/intel_runtime_pm.c
1247
tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
sys/dev/drm/i915/intel_runtime_pm.c
1249
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
sys/dev/drm/i915/intel_runtime_pm.c
1252
tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
sys/dev/drm/i915/intel_runtime_pm.c
1253
tmp |= DPIO_DYNPWRDOWNEN_CH1;
sys/dev/drm/i915/intel_runtime_pm.c
1254
vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
sys/dev/drm/i915/intel_runtime_pm.c
1261
tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
sys/dev/drm/i915/intel_runtime_pm.c
1262
tmp |= DPIO_CL2_LDOFUSE_PWRENB;
sys/dev/drm/i915/intel_runtime_pm.c
1263
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
sys/dev/drm/i915/intel_runtime_pm.c
789
u32 tmp = I915_READ(DBUF_CTL);
sys/dev/drm/i915/intel_runtime_pm.c
791
WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
sys/dev/drm/i915/intel_runtime_pm.c
793
"Unexpected DBuf power power state (0x%08x)\n", tmp);
sys/dev/drm/i915/intel_sdvo.c
2744
struct drm_connector *connector, *tmp;
sys/dev/drm/i915/intel_sdvo.c
2746
list_for_each_entry_safe(connector, tmp,
sys/dev/drm/i915/intel_sdvo.c
950
uint8_t hbuf_size, tmp[8];
sys/dev/drm/i915/intel_sdvo.c
969
memset(tmp, 0, 8);
sys/dev/drm/i915/intel_sdvo.c
971
memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
sys/dev/drm/i915/intel_sdvo.c
975
tmp, 8))
sys/dev/drm/i915/intel_sideband.c
247
u32 tmp;
sys/dev/drm/i915/intel_sideband.c
262
tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
sys/dev/drm/i915/intel_sideband.c
264
tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
sys/dev/drm/i915/intel_sideband.c
265
I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
sys/dev/drm/i915/intel_tv.c
1269
struct intel_load_detect_pipe tmp;
sys/dev/drm/i915/intel_tv.c
1272
ret = intel_get_load_detect_pipe(connector, &mode, &tmp, ctx);
sys/dev/drm/i915/intel_tv.c
1278
intel_release_load_detect_pipe(connector, &tmp, ctx);
sys/dev/drm/i915/intel_tv.c
1332
u64 tmp;
sys/dev/drm/i915/intel_tv.c
1366
tmp = mul_u32_u32(tv_mode->refresh, mode_ptr->vtotal);
sys/dev/drm/i915/intel_tv.c
1367
tmp *= mode_ptr->htotal;
sys/dev/drm/i915/intel_tv.c
1368
tmp = div_u64(tmp, 1000000);
sys/dev/drm/i915/intel_tv.c
1369
mode_ptr->clock = (int) tmp;
sys/dev/drm/i915/intel_tv.c
802
u32 tmp = I915_READ(TV_CTL);
sys/dev/drm/i915/intel_tv.c
804
*pipe = (tmp & TV_ENC_PIPE_SEL_MASK) >> TV_ENC_PIPE_SEL_SHIFT;
sys/dev/drm/i915/intel_tv.c
806
return tmp & TV_ENC_ENABLE;
sys/dev/drm/i915/intel_uncore.c
1168
unsigned int tmp;
sys/dev/drm/i915/intel_uncore.c
1172
for_each_fw_domain_masked(domain, fw_domains, dev_priv, tmp)
sys/dev/drm/i915/intel_uncore.c
1924
unsigned int tmp;
sys/dev/drm/i915/intel_uncore.c
1927
for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
sys/dev/drm/i915/intel_uncore.c
1968
unsigned int tmp;
sys/dev/drm/i915/intel_uncore.c
1971
for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
sys/dev/drm/i915/intel_uncore.c
2132
unsigned int tmp;
sys/dev/drm/i915/intel_uncore.c
2135
for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
sys/dev/drm/i915/intel_uncore.c
2158
for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
sys/dev/drm/i915/intel_uncore.c
221
unsigned int tmp;
sys/dev/drm/i915/intel_uncore.c
225
for_each_fw_domain_masked(d, fw_domains, i915, tmp) {
sys/dev/drm/i915/intel_uncore.c
230
for_each_fw_domain_masked(d, fw_domains, i915, tmp)
sys/dev/drm/i915/intel_uncore.c
241
unsigned int tmp;
sys/dev/drm/i915/intel_uncore.c
245
for_each_fw_domain_masked(d, fw_domains, i915, tmp) {
sys/dev/drm/i915/intel_uncore.c
250
for_each_fw_domain_masked(d, fw_domains, i915, tmp)
sys/dev/drm/i915/intel_uncore.c
260
unsigned int tmp;
sys/dev/drm/i915/intel_uncore.c
264
for_each_fw_domain_masked(d, fw_domains, i915, tmp)
sys/dev/drm/i915/intel_uncore.c
275
unsigned int tmp;
sys/dev/drm/i915/intel_uncore.c
282
for_each_fw_domain_masked(d, fw_domains, i915, tmp)
sys/dev/drm/i915/intel_uncore.c
387
unsigned int tmp;
sys/dev/drm/i915/intel_uncore.c
391
for_each_fw_domain(domain, dev_priv, tmp) {
sys/dev/drm/i915/intel_uncore.c
401
for_each_fw_domain(domain, dev_priv, tmp) {
sys/dev/drm/i915/intel_uncore.c
605
unsigned int tmp;
sys/dev/drm/i915/intel_uncore.c
609
for_each_fw_domain_masked(domain, fw_domains, dev_priv, tmp) {
sys/dev/drm/i915/intel_uncore.c
722
unsigned int tmp;
sys/dev/drm/i915/intel_uncore.c
726
for_each_fw_domain_masked(domain, fw_domains, dev_priv, tmp) {
sys/dev/drm/i915/vlv_dsi.c
1057
u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port));
sys/dev/drm/i915/vlv_dsi.c
1058
enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
sys/dev/drm/i915/vlv_dsi.c
1068
u32 tmp = I915_READ(MIPI_CTRL(port));
sys/dev/drm/i915/vlv_dsi.c
1069
tmp &= BXT_PIPE_SELECT_MASK;
sys/dev/drm/i915/vlv_dsi.c
1070
tmp >>= BXT_PIPE_SELECT_SHIFT;
sys/dev/drm/i915/vlv_dsi.c
1072
if (WARN_ON(tmp > PIPE_C))
sys/dev/drm/i915/vlv_dsi.c
1075
*pipe = tmp;
sys/dev/drm/i915/vlv_dsi.c
1411
u32 val, tmp;
sys/dev/drm/i915/vlv_dsi.c
1430
tmp = I915_READ(MIPI_CTRL(PORT_A));
sys/dev/drm/i915/vlv_dsi.c
1431
tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
sys/dev/drm/i915/vlv_dsi.c
1432
I915_WRITE(MIPI_CTRL(PORT_A), tmp |
sys/dev/drm/i915/vlv_dsi.c
1436
tmp = I915_READ(MIPI_CTRL(port));
sys/dev/drm/i915/vlv_dsi.c
1437
tmp &= ~READ_REQUEST_PRIORITY_MASK;
sys/dev/drm/i915/vlv_dsi.c
1438
I915_WRITE(MIPI_CTRL(port), tmp |
sys/dev/drm/i915/vlv_dsi.c
1443
tmp = I915_READ(MIPI_CTRL(port));
sys/dev/drm/i915/vlv_dsi.c
1444
tmp &= ~BXT_PIPE_SELECT_MASK;
sys/dev/drm/i915/vlv_dsi.c
1446
tmp |= BXT_PIPE_SELECT(pipe);
sys/dev/drm/i915/vlv_dsi.c
1447
I915_WRITE(MIPI_CTRL(port), tmp);
sys/dev/drm/i915/vlv_dsi.c
1472
tmp = 0;
sys/dev/drm/i915/vlv_dsi.c
1474
tmp |= EOT_DISABLE;
sys/dev/drm/i915/vlv_dsi.c
1476
tmp |= CLOCKSTOP;
sys/dev/drm/i915/vlv_dsi.c
1479
tmp |= BXT_DPHY_DEFEATURE_EN;
sys/dev/drm/i915/vlv_dsi.c
1481
tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
sys/dev/drm/i915/vlv_dsi.c
1542
I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
sys/dev/drm/i915/vlv_dsi.c
365
u32 tmp;
sys/dev/drm/i915/vlv_dsi.c
373
tmp = I915_READ(MIPI_CTRL(port));
sys/dev/drm/i915/vlv_dsi.c
374
I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
sys/dev/drm/i915/vlv_dsi.c
378
tmp = I915_READ(MIPI_CTRL(PORT_A));
sys/dev/drm/i915/vlv_dsi.c
379
tmp &= ~GLK_MIPIIO_RESET_RELEASED;
sys/dev/drm/i915/vlv_dsi.c
380
I915_WRITE(MIPI_CTRL(PORT_A), tmp);
sys/dev/drm/i915/vlv_dsi.c
384
tmp = I915_READ(MIPI_CTRL(port));
sys/dev/drm/i915/vlv_dsi.c
386
tmp &= ~GLK_LP_WAKE;
sys/dev/drm/i915/vlv_dsi.c
388
tmp |= GLK_LP_WAKE;
sys/dev/drm/i915/vlv_dsi.c
389
I915_WRITE(MIPI_CTRL(port), tmp);
sys/dev/drm/i915/vlv_dsi.c
598
u32 tmp;
sys/dev/drm/i915/vlv_dsi.c
601
tmp = I915_READ(MIPI_CTRL(PORT_A));
sys/dev/drm/i915/vlv_dsi.c
602
tmp &= ~GLK_MIPIIO_RESET_RELEASED;
sys/dev/drm/i915/vlv_dsi.c
603
I915_WRITE(MIPI_CTRL(PORT_A), tmp);
sys/dev/drm/i915/vlv_dsi.c
615
tmp = I915_READ(MIPI_CTRL(port));
sys/dev/drm/i915/vlv_dsi.c
616
tmp &= ~GLK_MIPIIO_ENABLE;
sys/dev/drm/i915/vlv_dsi.c
617
I915_WRITE(MIPI_CTRL(port), tmp);
sys/dev/drm/i915/vlv_dsi_pll.c
181
u32 tmp;
sys/dev/drm/i915/vlv_dsi_pll.c
187
tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
sys/dev/drm/i915/vlv_dsi_pll.c
188
tmp &= ~DSI_PLL_VCO_EN;
sys/dev/drm/i915/vlv_dsi_pll.c
189
tmp |= DSI_PLL_LDO_GATE;
sys/dev/drm/i915/vlv_dsi_pll.c
190
vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
sys/dev/drm/i915/vlv_dsi_pll.c
425
u32 tmp;
sys/dev/drm/i915/vlv_dsi_pll.c
435
tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
sys/dev/drm/i915/vlv_dsi_pll.c
436
tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
sys/dev/drm/i915/vlv_dsi_pll.c
437
tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
sys/dev/drm/i915/vlv_dsi_pll.c
438
tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
sys/dev/drm/i915/vlv_dsi_pll.c
439
tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
sys/dev/drm/i915/vlv_dsi_pll.c
466
tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
sys/dev/drm/i915/vlv_dsi_pll.c
467
tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);
sys/dev/drm/i915/vlv_dsi_pll.c
468
tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower);
sys/dev/drm/i915/vlv_dsi_pll.c
469
tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper);
sys/dev/drm/i915/vlv_dsi_pll.c
471
I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
sys/dev/drm/i915/vlv_dsi_pll.c
564
u32 tmp;
sys/dev/drm/i915/vlv_dsi_pll.c
570
tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
sys/dev/drm/i915/vlv_dsi_pll.c
571
tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
sys/dev/drm/i915/vlv_dsi_pll.c
572
tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
sys/dev/drm/i915/vlv_dsi_pll.c
573
tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
sys/dev/drm/i915/vlv_dsi_pll.c
574
tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
sys/dev/drm/i915/vlv_dsi_pll.c
575
I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
sys/dev/drm/i915/vlv_dsi_pll.c
577
tmp = I915_READ(MIPIO_TXESC_CLK_DIV1);
sys/dev/drm/i915/vlv_dsi_pll.c
578
tmp &= ~GLK_TX_ESC_CLK_DIV1_MASK;
sys/dev/drm/i915/vlv_dsi_pll.c
579
I915_WRITE(MIPIO_TXESC_CLK_DIV1, tmp);
sys/dev/drm/i915/vlv_dsi_pll.c
581
tmp = I915_READ(MIPIO_TXESC_CLK_DIV2);
sys/dev/drm/i915/vlv_dsi_pll.c
582
tmp &= ~GLK_TX_ESC_CLK_DIV2_MASK;
sys/dev/drm/i915/vlv_dsi_pll.c
583
I915_WRITE(MIPIO_TXESC_CLK_DIV2, tmp);
sys/dev/drm/include/drm/drm_fixed.h
64
u64 tmp = ((u64)A.full << 13);
sys/dev/drm/include/drm/drm_fixed.h
66
do_div(tmp, B.full);
sys/dev/drm/include/drm/drm_fixed.h
67
tmp += 1;
sys/dev/drm/include/drm/drm_fixed.h
68
tmp /= 2;
sys/dev/drm/include/drm/drm_fixed.h
69
return lower_32_bits(tmp);
sys/dev/drm/include/drm/ttm/ttm_bo_driver.h
910
pgprot_t ttm_io_prot(uint32_t caching_flags, pgprot_t tmp);
sys/dev/drm/linux_fence.c
227
struct dma_fence_cb *cur, *tmp;
sys/dev/drm/linux_fence.c
241
list_for_each_entry_safe(cur, tmp, &cb_list, node) {
sys/dev/drm/radeon/atombios_crtc.c
1155
u32 tmp, viewport_w, viewport_h;
sys/dev/drm/radeon/atombios_crtc.c
1310
tmp = rdev->config.cayman.tile_config;
sys/dev/drm/radeon/atombios_crtc.c
1312
tmp = rdev->config.evergreen.tile_config;
sys/dev/drm/radeon/atombios_crtc.c
1314
switch ((tmp & 0xf0) >> 4) {
sys/dev/drm/radeon/atombios_dp.c
418
u8 tmp;
sys/dev/drm/radeon/atombios_dp.c
431
DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
sys/dev/drm/radeon/atombios_dp.c
432
if (tmp & 1)
sys/dev/drm/radeon/atombios_dp.c
443
DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
sys/dev/drm/radeon/atombios_dp.c
444
if (tmp & 1)
sys/dev/drm/radeon/atombios_dp.c
606
u8 tmp;
sys/dev/drm/radeon/atombios_dp.c
623
tmp = dp_info->dp_lane_count;
sys/dev/drm/radeon/atombios_dp.c
625
tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
sys/dev/drm/radeon/atombios_dp.c
626
drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
sys/dev/drm/radeon/atombios_dp.c
629
tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
sys/dev/drm/radeon/atombios_dp.c
630
drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
sys/dev/drm/radeon/atombios_dp.c
797
u8 tmp, frev, crev;
sys/dev/drm/radeon/atombios_dp.c
834
if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
sys/dev/drm/radeon/atombios_dp.c
836
if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
sys/dev/drm/radeon/btc_dpm.c
1334
u32 tmp, bif;
sys/dev/drm/radeon/btc_dpm.c
1336
tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
sys/dev/drm/radeon/btc_dpm.c
1338
if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
sys/dev/drm/radeon/btc_dpm.c
1339
(tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
sys/dev/drm/radeon/btc_dpm.c
1345
tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
sys/dev/drm/radeon/btc_dpm.c
1346
tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
sys/dev/drm/radeon/btc_dpm.c
1347
tmp |= LC_GEN2_EN_STRAP;
sys/dev/drm/radeon/btc_dpm.c
1349
tmp |= LC_CLR_FAILED_SPD_CHANGE_CNT;
sys/dev/drm/radeon/btc_dpm.c
1350
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/drm/radeon/btc_dpm.c
1352
tmp &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
sys/dev/drm/radeon/btc_dpm.c
1353
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/drm/radeon/btc_dpm.c
1357
if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
sys/dev/drm/radeon/btc_dpm.c
1358
(tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
sys/dev/drm/radeon/btc_dpm.c
1364
tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
sys/dev/drm/radeon/btc_dpm.c
1365
tmp &= ~LC_GEN2_EN_STRAP;
sys/dev/drm/radeon/btc_dpm.c
1367
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/drm/radeon/btc_dpm.c
1441
u32 tmp;
sys/dev/drm/radeon/btc_dpm.c
1444
tmp = RREG32(sequence[i]);
sys/dev/drm/radeon/btc_dpm.c
1445
tmp &= ~sequence[i+2];
sys/dev/drm/radeon/btc_dpm.c
1446
tmp |= sequence[i+1] & sequence[i+2];
sys/dev/drm/radeon/btc_dpm.c
1447
WREG32(sequence[i], tmp);
sys/dev/drm/radeon/btc_dpm.c
1918
u32 tmp;
sys/dev/drm/radeon/btc_dpm.c
1923
tmp = RREG32(MC_PMG_CMD_EMRS);
sys/dev/drm/radeon/btc_dpm.c
1928
((tmp & 0xffff0000)) |
sys/dev/drm/radeon/btc_dpm.c
1936
tmp = RREG32(MC_PMG_CMD_MRS);
sys/dev/drm/radeon/btc_dpm.c
1941
(tmp & 0xffff0000) |
sys/dev/drm/radeon/btc_dpm.c
1952
tmp = RREG32(MC_PMG_CMD_MRS1);
sys/dev/drm/radeon/btc_dpm.c
1957
(tmp & 0xffff0000) |
sys/dev/drm/radeon/btc_dpm.c
2066
u32 tmp;
sys/dev/drm/radeon/btc_dpm.c
2070
tmp = RREG32(MC_PMG_AUTO_CFG);
sys/dev/drm/radeon/btc_dpm.c
2071
if ((0x200 & tmp) == 0) {
sys/dev/drm/radeon/btc_dpm.c
2072
tmp = (tmp & 0xfffffc0b) | 0x204;
sys/dev/drm/radeon/btc_dpm.c
2073
WREG32(MC_PMG_AUTO_CFG, tmp);
sys/dev/drm/radeon/ci_dpm.c
1051
tmp = (RREG32_SMC(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
sys/dev/drm/radeon/ci_dpm.c
1052
fan_table.TempSrc = (uint8_t)tmp;
sys/dev/drm/radeon/ci_dpm.c
1137
u32 tmp;
sys/dev/drm/radeon/ci_dpm.c
1160
tmp = RREG32_SMC(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
sys/dev/drm/radeon/ci_dpm.c
1161
tmp |= FDO_STATIC_DUTY(duty);
sys/dev/drm/radeon/ci_dpm.c
1162
WREG32_SMC(CG_FDO_CTRL0, tmp);
sys/dev/drm/radeon/ci_dpm.c
1186
u32 tmp;
sys/dev/drm/radeon/ci_dpm.c
1191
tmp = RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
sys/dev/drm/radeon/ci_dpm.c
1192
return (tmp >> FDO_PWM_MODE_SHIFT);
sys/dev/drm/radeon/ci_dpm.c
1220
u32 tach_period, tmp;
sys/dev/drm/radeon/ci_dpm.c
1237
tmp = RREG32_SMC(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
sys/dev/drm/radeon/ci_dpm.c
1238
tmp |= TARGET_PERIOD(tach_period);
sys/dev/drm/radeon/ci_dpm.c
1239
WREG32_SMC(CG_TACH_CTRL, tmp);
sys/dev/drm/radeon/ci_dpm.c
1250
u32 tmp;
sys/dev/drm/radeon/ci_dpm.c
1253
tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
sys/dev/drm/radeon/ci_dpm.c
1254
tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode);
sys/dev/drm/radeon/ci_dpm.c
1255
WREG32_SMC(CG_FDO_CTRL2, tmp);
sys/dev/drm/radeon/ci_dpm.c
1257
tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
sys/dev/drm/radeon/ci_dpm.c
1258
tmp |= TMIN(pi->t_min);
sys/dev/drm/radeon/ci_dpm.c
1259
WREG32_SMC(CG_FDO_CTRL2, tmp);
sys/dev/drm/radeon/ci_dpm.c
1274
u32 tmp;
sys/dev/drm/radeon/ci_dpm.c
1277
tmp = RREG32_SMC(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
sys/dev/drm/radeon/ci_dpm.c
1278
tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
sys/dev/drm/radeon/ci_dpm.c
1279
WREG32_SMC(CG_TACH_CTRL, tmp);
sys/dev/drm/radeon/ci_dpm.c
1282
tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
sys/dev/drm/radeon/ci_dpm.c
1283
tmp |= TACH_PWM_RESP_RATE(0x28);
sys/dev/drm/radeon/ci_dpm.c
1284
WREG32_SMC(CG_FDO_CTRL2, tmp);
sys/dev/drm/radeon/ci_dpm.c
1342
u16 tmp;
sys/dev/drm/radeon/ci_dpm.c
1344
tmp = 45;
sys/dev/drm/radeon/ci_dpm.c
1345
table->FpsHighT = cpu_to_be16(tmp);
sys/dev/drm/radeon/ci_dpm.c
1347
tmp = 30;
sys/dev/drm/radeon/ci_dpm.c
1348
table->FpsLowT = cpu_to_be16(tmp);
sys/dev/drm/radeon/ci_dpm.c
1419
u32 tmp;
sys/dev/drm/radeon/ci_dpm.c
1444
tmp = RREG32_SMC(CG_THERMAL_CTRL);
sys/dev/drm/radeon/ci_dpm.c
1445
tmp &= DPM_EVENT_SRC_MASK;
sys/dev/drm/radeon/ci_dpm.c
1446
tmp |= DPM_EVENT_SRC(dpm_event_src);
sys/dev/drm/radeon/ci_dpm.c
1447
WREG32_SMC(CG_THERMAL_CTRL, tmp);
sys/dev/drm/radeon/ci_dpm.c
1450
tmp = RREG32_SMC(GENERAL_PWRMGT);
sys/dev/drm/radeon/ci_dpm.c
1452
tmp &= ~THERMAL_PROTECTION_DIS;
sys/dev/drm/radeon/ci_dpm.c
1454
tmp |= THERMAL_PROTECTION_DIS;
sys/dev/drm/radeon/ci_dpm.c
1455
WREG32_SMC(GENERAL_PWRMGT, tmp);
sys/dev/drm/radeon/ci_dpm.c
1457
tmp = RREG32_SMC(GENERAL_PWRMGT);
sys/dev/drm/radeon/ci_dpm.c
1458
tmp |= THERMAL_PROTECTION_DIS;
sys/dev/drm/radeon/ci_dpm.c
1459
WREG32_SMC(GENERAL_PWRMGT, tmp);
sys/dev/drm/radeon/ci_dpm.c
1565
u32 tmp;
sys/dev/drm/radeon/ci_dpm.c
1567
tmp = RREG32_SMC(GENERAL_PWRMGT);
sys/dev/drm/radeon/ci_dpm.c
1568
tmp |= GLOBAL_PWRMGT_EN;
sys/dev/drm/radeon/ci_dpm.c
1569
WREG32_SMC(GENERAL_PWRMGT, tmp);
sys/dev/drm/radeon/ci_dpm.c
1571
tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
sys/dev/drm/radeon/ci_dpm.c
1572
tmp |= DYNAMIC_PM_EN;
sys/dev/drm/radeon/ci_dpm.c
1573
WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
sys/dev/drm/radeon/ci_dpm.c
1626
u32 tmp;
sys/dev/drm/radeon/ci_dpm.c
1628
tmp = RREG32_SMC(GENERAL_PWRMGT);
sys/dev/drm/radeon/ci_dpm.c
1629
tmp &= ~GLOBAL_PWRMGT_EN;
sys/dev/drm/radeon/ci_dpm.c
1630
WREG32_SMC(GENERAL_PWRMGT, tmp);
sys/dev/drm/radeon/ci_dpm.c
1632
tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
sys/dev/drm/radeon/ci_dpm.c
1633
tmp &= ~DYNAMIC_PM_EN;
sys/dev/drm/radeon/ci_dpm.c
1634
WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
sys/dev/drm/radeon/ci_dpm.c
1655
u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
sys/dev/drm/radeon/ci_dpm.c
1658
tmp &= ~SCLK_PWRMGT_OFF;
sys/dev/drm/radeon/ci_dpm.c
1660
tmp |= SCLK_PWRMGT_OFF;
sys/dev/drm/radeon/ci_dpm.c
1661
WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
sys/dev/drm/radeon/ci_dpm.c
1693
u32 tmp;
sys/dev/drm/radeon/ci_dpm.c
1702
tmp = RREG32(SMC_RESP_0);
sys/dev/drm/radeon/ci_dpm.c
1703
if (tmp != 0)
sys/dev/drm/radeon/ci_dpm.c
1707
tmp = RREG32(SMC_RESP_0);
sys/dev/drm/radeon/ci_dpm.c
1709
return (PPSMC_Result)tmp;
sys/dev/drm/radeon/ci_dpm.c
1853
u32 tmp;
sys/dev/drm/radeon/ci_dpm.c
1859
&tmp, pi->sram_end);
sys/dev/drm/radeon/ci_dpm.c
1863
pi->dpm_table_start = tmp;
sys/dev/drm/radeon/ci_dpm.c
1868
&tmp, pi->sram_end);
sys/dev/drm/radeon/ci_dpm.c
1872
pi->soft_regs_start = tmp;
sys/dev/drm/radeon/ci_dpm.c
1877
&tmp, pi->sram_end);
sys/dev/drm/radeon/ci_dpm.c
1881
pi->mc_reg_table_start = tmp;
sys/dev/drm/radeon/ci_dpm.c
1886
&tmp, pi->sram_end);
sys/dev/drm/radeon/ci_dpm.c
1890
pi->fan_table_start = tmp;
sys/dev/drm/radeon/ci_dpm.c
1895
&tmp, pi->sram_end);
sys/dev/drm/radeon/ci_dpm.c
1899
pi->arb_table_start = tmp;
sys/dev/drm/radeon/ci_dpm.c
1941
u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
sys/dev/drm/radeon/ci_dpm.c
1944
tmp &= ~THERMAL_PROTECTION_DIS;
sys/dev/drm/radeon/ci_dpm.c
1946
tmp |= THERMAL_PROTECTION_DIS;
sys/dev/drm/radeon/ci_dpm.c
1947
WREG32_SMC(GENERAL_PWRMGT, tmp);
sys/dev/drm/radeon/ci_dpm.c
1952
u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
sys/dev/drm/radeon/ci_dpm.c
1954
tmp |= STATIC_PM_EN;
sys/dev/drm/radeon/ci_dpm.c
1956
WREG32_SMC(GENERAL_PWRMGT, tmp);
sys/dev/drm/radeon/ci_dpm.c
2021
u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
sys/dev/drm/radeon/ci_dpm.c
2028
tmp &= ~DISP_GAP_MASK;
sys/dev/drm/radeon/ci_dpm.c
2030
tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
sys/dev/drm/radeon/ci_dpm.c
2032
tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/drm/radeon/ci_dpm.c
2033
WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/drm/radeon/ci_dpm.c
2042
tmp = pre_vbi_time_in_us * (ref_clock / 100);
sys/dev/drm/radeon/ci_dpm.c
2044
WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp);
sys/dev/drm/radeon/ci_dpm.c
2056
u32 tmp;
sys/dev/drm/radeon/ci_dpm.c
2060
tmp = RREG32_SMC(GENERAL_PWRMGT);
sys/dev/drm/radeon/ci_dpm.c
2061
tmp |= DYN_SPREAD_SPECTRUM_EN;
sys/dev/drm/radeon/ci_dpm.c
2062
WREG32_SMC(GENERAL_PWRMGT, tmp);
sys/dev/drm/radeon/ci_dpm.c
2065
tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
sys/dev/drm/radeon/ci_dpm.c
2066
tmp &= ~SSEN;
sys/dev/drm/radeon/ci_dpm.c
2067
WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp);
sys/dev/drm/radeon/ci_dpm.c
2069
tmp = RREG32_SMC(GENERAL_PWRMGT);
sys/dev/drm/radeon/ci_dpm.c
2070
tmp &= ~DYN_SPREAD_SPECTRUM_EN;
sys/dev/drm/radeon/ci_dpm.c
2071
WREG32_SMC(GENERAL_PWRMGT, tmp);
sys/dev/drm/radeon/ci_dpm.c
2082
u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
sys/dev/drm/radeon/ci_dpm.c
2084
tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK);
sys/dev/drm/radeon/ci_dpm.c
2085
tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
sys/dev/drm/radeon/ci_dpm.c
2088
WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/drm/radeon/ci_dpm.c
2093
u32 tmp;
sys/dev/drm/radeon/ci_dpm.c
2095
tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
sys/dev/drm/radeon/ci_dpm.c
2096
tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
sys/dev/drm/radeon/ci_dpm.c
2097
WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
sys/dev/drm/radeon/ci_dpm.c
2111
u32 tmp;
sys/dev/drm/radeon/ci_dpm.c
2113
tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
sys/dev/drm/radeon/ci_dpm.c
2114
tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
sys/dev/drm/radeon/ci_dpm.c
2115
WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
sys/dev/drm/radeon/ci_dpm.c
2450
u32 tmp;
sys/dev/drm/radeon/ci_dpm.c
2454
&tmp, pi->sram_end);
sys/dev/drm/radeon/ci_dpm.c
2458
tmp &= 0x00FFFFFF;
sys/dev/drm/radeon/ci_dpm.c
2459
tmp |= MC_CG_ARB_FREQ_F1 << 24;
sys/dev/drm/radeon/ci_dpm.c
2462
tmp, pi->sram_end);
sys/dev/drm/radeon/ci_dpm.c
2490
u32 tmp;
sys/dev/drm/radeon/ci_dpm.c
2498
tmp = sclk / (1 << i);
sys/dev/drm/radeon/ci_dpm.c
2499
if (tmp >= min || i == 0)
sys/dev/drm/radeon/ci_dpm.c
2519
u32 tmp;
sys/dev/drm/radeon/ci_dpm.c
2521
tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8;
sys/dev/drm/radeon/ci_dpm.c
2523
if (tmp == MC_CG_ARB_FREQ_F0)
sys/dev/drm/radeon/ci_dpm.c
2526
return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
sys/dev/drm/radeon/ci_dpm.c
2535
u32 tmp, tmp2;
sys/dev/drm/radeon/ci_dpm.c
2537
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/drm/radeon/ci_dpm.c
2538
patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
sys/dev/drm/radeon/ci_dpm.c
2864
u32 tmp;
sys/dev/drm/radeon/ci_dpm.c
2872
tmp = (freq_nom / reference_clock);
sys/dev/drm/radeon/ci_dpm.c
2873
tmp = tmp * tmp;
sys/dev/drm/radeon/ci_dpm.c
2877
u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
sys/dev/drm/radeon/ci_dpm.c
4114
u32 tmp;
sys/dev/drm/radeon/ci_dpm.c
4124
tmp = RREG32_SMC(DPM_TABLE_475);
sys/dev/drm/radeon/ci_dpm.c
4125
tmp &= ~UvdBootLevel_MASK;
sys/dev/drm/radeon/ci_dpm.c
4126
tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel);
sys/dev/drm/radeon/ci_dpm.c
4127
WREG32_SMC(DPM_TABLE_475, tmp);
sys/dev/drm/radeon/ci_dpm.c
4154
u32 tmp;
sys/dev/drm/radeon/ci_dpm.c
4162
tmp = RREG32_SMC(DPM_TABLE_475);
sys/dev/drm/radeon/ci_dpm.c
4163
tmp &= ~VceBootLevel_MASK;
sys/dev/drm/radeon/ci_dpm.c
4164
tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel);
sys/dev/drm/radeon/ci_dpm.c
4165
WREG32_SMC(DPM_TABLE_475, tmp);
sys/dev/drm/radeon/ci_dpm.c
4187
u32 tmp;
sys/dev/drm/radeon/ci_dpm.c
4192
tmp = RREG32_SMC(DPM_TABLE_475);
sys/dev/drm/radeon/ci_dpm.c
4193
tmp &= ~AcpBootLevel_MASK;
sys/dev/drm/radeon/ci_dpm.c
4194
tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
sys/dev/drm/radeon/ci_dpm.c
4195
WREG32_SMC(DPM_TABLE_475, tmp);
sys/dev/drm/radeon/ci_dpm.c
4244
u32 tmp, levels, i;
sys/dev/drm/radeon/ci_dpm.c
4251
tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
sys/dev/drm/radeon/ci_dpm.c
4252
while (tmp >>= 1)
sys/dev/drm/radeon/ci_dpm.c
4259
tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
sys/dev/drm/radeon/ci_dpm.c
4261
if (tmp == levels)
sys/dev/drm/radeon/ci_dpm.c
4270
tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
sys/dev/drm/radeon/ci_dpm.c
4271
while (tmp >>= 1)
sys/dev/drm/radeon/ci_dpm.c
4278
tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
sys/dev/drm/radeon/ci_dpm.c
4280
if (tmp == levels)
sys/dev/drm/radeon/ci_dpm.c
4289
tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
sys/dev/drm/radeon/ci_dpm.c
4290
while (tmp >>= 1)
sys/dev/drm/radeon/ci_dpm.c
4297
tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
sys/dev/drm/radeon/ci_dpm.c
4299
if (tmp == levels)
sys/dev/drm/radeon/ci_dpm.c
4314
tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
sys/dev/drm/radeon/ci_dpm.c
4316
if (tmp == levels)
sys/dev/drm/radeon/ci_dpm.c
4329
tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
sys/dev/drm/radeon/ci_dpm.c
4331
if (tmp == levels)
sys/dev/drm/radeon/ci_dpm.c
4344
tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
sys/dev/drm/radeon/ci_dpm.c
4346
if (tmp == levels)
sys/dev/drm/radeon/ci_dpm.c
4572
u32 tmp;
sys/dev/drm/radeon/ci_dpm.c
4575
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/drm/radeon/ci_dpm.c
4576
patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
sys/dev/drm/radeon/ci_dpm.c
4649
tmp = RREG32(MC_SEQ_IO_DEBUG_DATA);
sys/dev/drm/radeon/ci_dpm.c
4650
tmp = (tmp & 0xFFF8FFFF) | (1 << 16);
sys/dev/drm/radeon/ci_dpm.c
4652
WREG32(MC_SEQ_IO_DEBUG_DATA, tmp);
sys/dev/drm/radeon/ci_dpm.c
4825
u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
sys/dev/drm/radeon/ci_dpm.c
4827
tmp |= VOLT_PWRMGT_EN;
sys/dev/drm/radeon/ci_dpm.c
4828
WREG32_SMC(GENERAL_PWRMGT, tmp);
sys/dev/drm/radeon/ci_dpm.c
5128
u32 tmp;
sys/dev/drm/radeon/ci_dpm.c
5130
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/drm/radeon/ci_dpm.c
5132
if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
sys/dev/drm/radeon/ci_dpm.c
5891
u32 tmp = RREG32_SMC(CNB_PWRMGT_CNTL);
sys/dev/drm/radeon/ci_dpm.c
5895
tmp &= ~GNB_SLOW_MODE_MASK;
sys/dev/drm/radeon/ci_dpm.c
5896
tmp |= GNB_SLOW_MODE(1);
sys/dev/drm/radeon/ci_dpm.c
5899
tmp &= ~GNB_SLOW_MODE_MASK;
sys/dev/drm/radeon/ci_dpm.c
5900
tmp |= GNB_SLOW_MODE(2);
sys/dev/drm/radeon/ci_dpm.c
5903
tmp |= GNB_SLOW;
sys/dev/drm/radeon/ci_dpm.c
5906
tmp |= FORCE_NB_PS1;
sys/dev/drm/radeon/ci_dpm.c
5909
tmp |= DPM_ENABLED;
sys/dev/drm/radeon/ci_dpm.c
5915
WREG32_SMC(CNB_PWRMGT_CNTL, tmp);
sys/dev/drm/radeon/ci_dpm.c
909
u32 tmp;
sys/dev/drm/radeon/ci_dpm.c
920
tmp = RREG32_SMC(CG_THERMAL_INT);
sys/dev/drm/radeon/ci_dpm.c
921
tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK);
sys/dev/drm/radeon/ci_dpm.c
922
tmp |= CI_DIG_THERM_INTH(high_temp / 1000) |
sys/dev/drm/radeon/ci_dpm.c
924
WREG32_SMC(CG_THERMAL_INT, tmp);
sys/dev/drm/radeon/ci_dpm.c
928
tmp = RREG32_SMC(CG_THERMAL_CTRL);
sys/dev/drm/radeon/ci_dpm.c
929
tmp &= DIG_THERM_DPM_MASK;
sys/dev/drm/radeon/ci_dpm.c
930
tmp |= DIG_THERM_DPM(high_temp / 1000);
sys/dev/drm/radeon/ci_dpm.c
931
WREG32_SMC(CG_THERMAL_CTRL, tmp);
sys/dev/drm/radeon/ci_dpm.c
972
u32 tmp;
sys/dev/drm/radeon/ci_dpm.c
975
tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
sys/dev/drm/radeon/ci_dpm.c
976
pi->fan_ctrl_default_mode = tmp;
sys/dev/drm/radeon/ci_dpm.c
977
tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
sys/dev/drm/radeon/ci_dpm.c
978
pi->t_min = tmp;
sys/dev/drm/radeon/ci_dpm.c
982
tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
sys/dev/drm/radeon/ci_dpm.c
983
tmp |= TMIN(0);
sys/dev/drm/radeon/ci_dpm.c
984
WREG32_SMC(CG_FDO_CTRL2, tmp);
sys/dev/drm/radeon/ci_dpm.c
986
tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
sys/dev/drm/radeon/ci_dpm.c
987
tmp |= FDO_PWM_MODE(mode);
sys/dev/drm/radeon/ci_dpm.c
988
WREG32_SMC(CG_FDO_CTRL2, tmp);
sys/dev/drm/radeon/ci_dpm.c
998
u32 reference_clock, tmp;
sys/dev/drm/radeon/ci_smc.c
116
u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
sys/dev/drm/radeon/ci_smc.c
118
tmp &= ~RST_REG;
sys/dev/drm/radeon/ci_smc.c
119
WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
sys/dev/drm/radeon/ci_smc.c
124
u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
sys/dev/drm/radeon/ci_smc.c
126
tmp |= RST_REG;
sys/dev/drm/radeon/ci_smc.c
127
WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
sys/dev/drm/radeon/ci_smc.c
139
u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
sys/dev/drm/radeon/ci_smc.c
141
tmp |= CK_DISABLE;
sys/dev/drm/radeon/ci_smc.c
143
WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
sys/dev/drm/radeon/ci_smc.c
148
u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
sys/dev/drm/radeon/ci_smc.c
150
tmp &= ~CK_DISABLE;
sys/dev/drm/radeon/ci_smc.c
152
WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
sys/dev/drm/radeon/ci_smc.c
169
u32 tmp;
sys/dev/drm/radeon/ci_smc.c
176
tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
sys/dev/drm/radeon/ci_smc.c
177
if ((tmp & CKEN) == 0)
sys/dev/drm/radeon/cik.c
1859
u32 running, tmp;
sys/dev/drm/radeon/cik.c
1915
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/drm/radeon/cik.c
1916
if ((rdev->pdev->device == 0x6649) && ((tmp & 0xff00) == 0x5600)) {
sys/dev/drm/radeon/cik.c
3199
u32 tmp;
sys/dev/drm/radeon/cik.c
3295
tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
sys/dev/drm/radeon/cik.c
3296
rdev->config.cik.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
sys/dev/drm/radeon/cik.c
3380
tmp = RREG32(SPI_CONFIG_CNTL);
sys/dev/drm/radeon/cik.c
3381
tmp |= 0x03000000;
sys/dev/drm/radeon/cik.c
3382
WREG32(SPI_CONFIG_CNTL, tmp);
sys/dev/drm/radeon/cik.c
3388
tmp = RREG32(DB_DEBUG2) & ~0xf00fffff;
sys/dev/drm/radeon/cik.c
3389
tmp |= 0x00000400;
sys/dev/drm/radeon/cik.c
3390
WREG32(DB_DEBUG2, tmp);
sys/dev/drm/radeon/cik.c
3392
tmp = RREG32(DB_DEBUG3) & ~0x0002021c;
sys/dev/drm/radeon/cik.c
3393
tmp |= 0x00020200;
sys/dev/drm/radeon/cik.c
3394
WREG32(DB_DEBUG3, tmp);
sys/dev/drm/radeon/cik.c
3396
tmp = RREG32(CB_HW_CONTROL) & ~0x00010000;
sys/dev/drm/radeon/cik.c
3397
tmp |= 0x00018208;
sys/dev/drm/radeon/cik.c
3398
WREG32(CB_HW_CONTROL, tmp);
sys/dev/drm/radeon/cik.c
3422
tmp = RREG32(HDP_MISC_CNTL);
sys/dev/drm/radeon/cik.c
3423
tmp |= HDP_FLUSH_INVALIDATE_CACHE;
sys/dev/drm/radeon/cik.c
3424
WREG32(HDP_MISC_CNTL, tmp);
sys/dev/drm/radeon/cik.c
3474
uint32_t tmp = 0;
sys/dev/drm/radeon/cik.c
3496
tmp = RREG32(scratch);
sys/dev/drm/radeon/cik.c
3497
if (tmp == 0xDEADBEEF)
sys/dev/drm/radeon/cik.c
3505
ring->idx, scratch, tmp);
sys/dev/drm/radeon/cik.c
3799
uint32_t tmp = 0;
sys/dev/drm/radeon/cik.c
3841
tmp = RREG32(scratch);
sys/dev/drm/radeon/cik.c
3842
if (tmp == 0xDEADBEEF)
sys/dev/drm/radeon/cik.c
3850
scratch, tmp);
sys/dev/drm/radeon/cik.c
4075
u32 tmp;
sys/dev/drm/radeon/cik.c
4096
tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
sys/dev/drm/radeon/cik.c
4098
tmp |= BUF_SWAP_32BIT;
sys/dev/drm/radeon/cik.c
4100
WREG32(CP_RB0_CNTL, tmp);
sys/dev/drm/radeon/cik.c
4103
WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
sys/dev/drm/radeon/cik.c
4115
tmp |= RB_NO_UPDATE;
sys/dev/drm/radeon/cik.c
4118
WREG32(CP_RB0_CNTL, tmp);
sys/dev/drm/radeon/cik.c
4213
u32 j, tmp;
sys/dev/drm/radeon/cik.c
4217
tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
sys/dev/drm/radeon/cik.c
4218
tmp &= ~WPTR_POLL_EN;
sys/dev/drm/radeon/cik.c
4219
WREG32(CP_PQ_WPTR_POLL_CNTL, tmp);
sys/dev/drm/radeon/cik.c
4537
u32 tmp;
sys/dev/drm/radeon/cik.c
4551
tmp = RREG32(CP_CPF_DEBUG);
sys/dev/drm/radeon/cik.c
4552
tmp |= (1 << 23);
sys/dev/drm/radeon/cik.c
4553
WREG32(CP_CPF_DEBUG, tmp);
sys/dev/drm/radeon/cik.c
4573
tmp = RREG32(CP_HPD_EOP_CONTROL);
sys/dev/drm/radeon/cik.c
4574
tmp &= ~EOP_SIZE_MASK;
sys/dev/drm/radeon/cik.c
4575
tmp |= order_base_2(MEC_HPD_SIZE / 8);
sys/dev/drm/radeon/cik.c
4576
WREG32(CP_HPD_EOP_CONTROL, tmp);
sys/dev/drm/radeon/cik.c
4636
tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
sys/dev/drm/radeon/cik.c
4637
tmp &= ~WPTR_POLL_EN;
sys/dev/drm/radeon/cik.c
4638
WREG32(CP_PQ_WPTR_POLL_CNTL, tmp);
sys/dev/drm/radeon/cik.c
4871
u32 tmp;
sys/dev/drm/radeon/cik.c
4874
tmp = RREG32(GRBM_STATUS);
sys/dev/drm/radeon/cik.c
4875
if (tmp & (PA_BUSY | SC_BUSY |
sys/dev/drm/radeon/cik.c
4883
if (tmp & (CP_BUSY | CP_COHERENCY_BUSY))
sys/dev/drm/radeon/cik.c
4887
tmp = RREG32(GRBM_STATUS2);
sys/dev/drm/radeon/cik.c
4888
if (tmp & RLC_BUSY)
sys/dev/drm/radeon/cik.c
4892
tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);
sys/dev/drm/radeon/cik.c
4893
if (!(tmp & SDMA_IDLE))
sys/dev/drm/radeon/cik.c
4897
tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
sys/dev/drm/radeon/cik.c
4898
if (!(tmp & SDMA_IDLE))
sys/dev/drm/radeon/cik.c
4902
tmp = RREG32(SRBM_STATUS2);
sys/dev/drm/radeon/cik.c
4903
if (tmp & SDMA_BUSY)
sys/dev/drm/radeon/cik.c
4906
if (tmp & SDMA1_BUSY)
sys/dev/drm/radeon/cik.c
4910
tmp = RREG32(SRBM_STATUS);
sys/dev/drm/radeon/cik.c
4912
if (tmp & IH_BUSY)
sys/dev/drm/radeon/cik.c
4915
if (tmp & SEM_BUSY)
sys/dev/drm/radeon/cik.c
4918
if (tmp & GRBM_RQ_PENDING)
sys/dev/drm/radeon/cik.c
4921
if (tmp & VMC_BUSY)
sys/dev/drm/radeon/cik.c
4924
if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
sys/dev/drm/radeon/cik.c
4952
u32 tmp;
sys/dev/drm/radeon/cik.c
4980
tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/drm/radeon/cik.c
4981
tmp |= SDMA_HALT;
sys/dev/drm/radeon/cik.c
4982
WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
sys/dev/drm/radeon/cik.c
4986
tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/drm/radeon/cik.c
4987
tmp |= SDMA_HALT;
sys/dev/drm/radeon/cik.c
4988
WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);
sys/dev/drm/radeon/cik.c
5035
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/cik.c
5036
tmp |= grbm_soft_reset;
sys/dev/drm/radeon/cik.c
5037
dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/radeon/cik.c
5038
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/drm/radeon/cik.c
5039
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/cik.c
5043
tmp &= ~grbm_soft_reset;
sys/dev/drm/radeon/cik.c
5044
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/drm/radeon/cik.c
5045
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/cik.c
5049
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/cik.c
5050
tmp |= srbm_soft_reset;
sys/dev/drm/radeon/cik.c
5051
dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/radeon/cik.c
5052
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/drm/radeon/cik.c
5053
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/cik.c
5057
tmp &= ~srbm_soft_reset;
sys/dev/drm/radeon/cik.c
5058
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/drm/radeon/cik.c
5059
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/cik.c
5166
u32 tmp, i;
sys/dev/drm/radeon/cik.c
5183
tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/drm/radeon/cik.c
5184
tmp |= SDMA_HALT;
sys/dev/drm/radeon/cik.c
5185
WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
sys/dev/drm/radeon/cik.c
5187
tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/drm/radeon/cik.c
5188
tmp |= SDMA_HALT;
sys/dev/drm/radeon/cik.c
5189
WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);
sys/dev/drm/radeon/cik.c
5300
u32 tmp;
sys/dev/drm/radeon/cik.c
5326
tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
sys/dev/drm/radeon/cik.c
5327
tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
sys/dev/drm/radeon/cik.c
5328
WREG32(MC_VM_FB_LOCATION, tmp);
sys/dev/drm/radeon/cik.c
5356
u32 tmp;
sys/dev/drm/radeon/cik.c
5361
tmp = RREG32(MC_ARB_RAMCFG);
sys/dev/drm/radeon/cik.c
5362
if (tmp & CHANSIZE_MASK) {
sys/dev/drm/radeon/cik.c
5367
tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/drm/radeon/cik.c
5368
switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
sys/dev/drm/radeon/cik.c
5522
u32 tmp = RREG32(CHUB_CONTROL);
sys/dev/drm/radeon/cik.c
5523
tmp &= ~BYPASS_VM;
sys/dev/drm/radeon/cik.c
5524
WREG32(CHUB_CONTROL, tmp);
sys/dev/drm/radeon/cik.c
5647
u64 tmp = RREG32(MC_VM_FB_OFFSET);
sys/dev/drm/radeon/cik.c
5648
tmp <<= 22;
sys/dev/drm/radeon/cik.c
5649
rdev->vm_manager.vram_base_offset = tmp;
sys/dev/drm/radeon/cik.c
5787
u32 tmp = RREG32(CP_INT_CNTL_RING0);
sys/dev/drm/radeon/cik.c
5790
tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
sys/dev/drm/radeon/cik.c
5792
tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
sys/dev/drm/radeon/cik.c
5793
WREG32(CP_INT_CNTL_RING0, tmp);
sys/dev/drm/radeon/cik.c
5798
u32 tmp;
sys/dev/drm/radeon/cik.c
5800
tmp = RREG32(RLC_LB_CNTL);
sys/dev/drm/radeon/cik.c
5802
tmp |= LOAD_BALANCE_ENABLE;
sys/dev/drm/radeon/cik.c
5804
tmp &= ~LOAD_BALANCE_ENABLE;
sys/dev/drm/radeon/cik.c
5805
WREG32(RLC_LB_CNTL, tmp);
sys/dev/drm/radeon/cik.c
5835
u32 tmp;
sys/dev/drm/radeon/cik.c
5837
tmp = RREG32(RLC_CNTL);
sys/dev/drm/radeon/cik.c
5838
if (tmp != rlc)
sys/dev/drm/radeon/cik.c
5868
u32 tmp, i, mask;
sys/dev/drm/radeon/cik.c
5870
tmp = REQ | MESSAGE(MSG_ENTER_RLC_SAFE_MODE);
sys/dev/drm/radeon/cik.c
5871
WREG32(RLC_GPR_REG2, tmp);
sys/dev/drm/radeon/cik.c
5889
u32 tmp;
sys/dev/drm/radeon/cik.c
5891
tmp = REQ | MESSAGE(MSG_EXIT_RLC_SAFE_MODE);
sys/dev/drm/radeon/cik.c
5892
WREG32(RLC_GPR_REG2, tmp);
sys/dev/drm/radeon/cik.c
5938
u32 i, size, tmp;
sys/dev/drm/radeon/cik.c
5946
tmp = RREG32(RLC_CGCG_CGLS_CTRL) & 0xfffffffc;
sys/dev/drm/radeon/cik.c
5947
WREG32(RLC_CGCG_CGLS_CTRL, tmp);
sys/dev/drm/radeon/cik.c
6019
u32 data, orig, tmp, tmp2;
sys/dev/drm/radeon/cik.c
6026
tmp = cik_halt_rlc(rdev);
sys/dev/drm/radeon/cik.c
6034
cik_update_rlc(rdev, tmp);
sys/dev/drm/radeon/cik.c
6055
u32 data, orig, tmp = 0;
sys/dev/drm/radeon/cik.c
6073
tmp = cik_halt_rlc(rdev);
sys/dev/drm/radeon/cik.c
6081
cik_update_rlc(rdev, tmp);
sys/dev/drm/radeon/cik.c
6121
tmp = cik_halt_rlc(rdev);
sys/dev/drm/radeon/cik.c
6129
cik_update_rlc(rdev, tmp);
sys/dev/drm/radeon/cik.c
6553
u32 mask = 0, tmp, tmp1;
sys/dev/drm/radeon/cik.c
6557
tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
sys/dev/drm/radeon/cik.c
6561
tmp &= 0xffff0000;
sys/dev/drm/radeon/cik.c
6563
tmp |= tmp1;
sys/dev/drm/radeon/cik.c
6564
tmp >>= 16;
sys/dev/drm/radeon/cik.c
6571
return (~tmp) & mask;
sys/dev/drm/radeon/cik.c
6578
u32 tmp = 0;
sys/dev/drm/radeon/cik.c
6595
tmp |= (cu_bitmap << (i * 16 + j * 8));
sys/dev/drm/radeon/cik.c
6599
WREG32(RLC_PG_AO_CU_MASK, tmp);
sys/dev/drm/radeon/cik.c
6601
tmp = RREG32(RLC_MAX_PG_CU);
sys/dev/drm/radeon/cik.c
6602
tmp &= ~MAX_PU_CU_MASK;
sys/dev/drm/radeon/cik.c
6603
tmp |= MAX_PU_CU(active_cu_number);
sys/dev/drm/radeon/cik.c
6604
WREG32(RLC_MAX_PG_CU, tmp);
sys/dev/drm/radeon/cik.c
6883
u32 tmp;
sys/dev/drm/radeon/cik.c
6886
tmp = RREG32(CP_INT_CNTL_RING0) &
sys/dev/drm/radeon/cik.c
6888
WREG32(CP_INT_CNTL_RING0, tmp);
sys/dev/drm/radeon/cik.c
6890
tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
sys/dev/drm/radeon/cik.c
6891
WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp);
sys/dev/drm/radeon/cik.c
6892
tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
sys/dev/drm/radeon/cik.c
6893
WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp);
sys/dev/drm/radeon/cik.c
6936
tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/cik.c
6937
WREG32(DC_HPD1_INT_CONTROL, tmp);
sys/dev/drm/radeon/cik.c
6938
tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/cik.c
6939
WREG32(DC_HPD2_INT_CONTROL, tmp);
sys/dev/drm/radeon/cik.c
6940
tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/cik.c
6941
WREG32(DC_HPD3_INT_CONTROL, tmp);
sys/dev/drm/radeon/cik.c
6942
tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/cik.c
6943
WREG32(DC_HPD4_INT_CONTROL, tmp);
sys/dev/drm/radeon/cik.c
6944
tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/cik.c
6945
WREG32(DC_HPD5_INT_CONTROL, tmp);
sys/dev/drm/radeon/cik.c
6946
tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/cik.c
6947
WREG32(DC_HPD6_INT_CONTROL, tmp);
sys/dev/drm/radeon/cik.c
7314
u32 tmp;
sys/dev/drm/radeon/cik.c
7391
tmp = RREG32(DC_HPD1_INT_CONTROL);
sys/dev/drm/radeon/cik.c
7392
tmp |= DC_HPDx_INT_ACK;
sys/dev/drm/radeon/cik.c
7393
WREG32(DC_HPD1_INT_CONTROL, tmp);
sys/dev/drm/radeon/cik.c
7396
tmp = RREG32(DC_HPD2_INT_CONTROL);
sys/dev/drm/radeon/cik.c
7397
tmp |= DC_HPDx_INT_ACK;
sys/dev/drm/radeon/cik.c
7398
WREG32(DC_HPD2_INT_CONTROL, tmp);
sys/dev/drm/radeon/cik.c
7401
tmp = RREG32(DC_HPD3_INT_CONTROL);
sys/dev/drm/radeon/cik.c
7402
tmp |= DC_HPDx_INT_ACK;
sys/dev/drm/radeon/cik.c
7403
WREG32(DC_HPD3_INT_CONTROL, tmp);
sys/dev/drm/radeon/cik.c
7406
tmp = RREG32(DC_HPD4_INT_CONTROL);
sys/dev/drm/radeon/cik.c
7407
tmp |= DC_HPDx_INT_ACK;
sys/dev/drm/radeon/cik.c
7408
WREG32(DC_HPD4_INT_CONTROL, tmp);
sys/dev/drm/radeon/cik.c
7411
tmp = RREG32(DC_HPD5_INT_CONTROL);
sys/dev/drm/radeon/cik.c
7412
tmp |= DC_HPDx_INT_ACK;
sys/dev/drm/radeon/cik.c
7413
WREG32(DC_HPD5_INT_CONTROL, tmp);
sys/dev/drm/radeon/cik.c
7416
tmp = RREG32(DC_HPD6_INT_CONTROL);
sys/dev/drm/radeon/cik.c
7417
tmp |= DC_HPDx_INT_ACK;
sys/dev/drm/radeon/cik.c
7418
WREG32(DC_HPD6_INT_CONTROL, tmp);
sys/dev/drm/radeon/cik.c
7421
tmp = RREG32(DC_HPD1_INT_CONTROL);
sys/dev/drm/radeon/cik.c
7422
tmp |= DC_HPDx_RX_INT_ACK;
sys/dev/drm/radeon/cik.c
7423
WREG32(DC_HPD1_INT_CONTROL, tmp);
sys/dev/drm/radeon/cik.c
7426
tmp = RREG32(DC_HPD2_INT_CONTROL);
sys/dev/drm/radeon/cik.c
7427
tmp |= DC_HPDx_RX_INT_ACK;
sys/dev/drm/radeon/cik.c
7428
WREG32(DC_HPD2_INT_CONTROL, tmp);
sys/dev/drm/radeon/cik.c
7431
tmp = RREG32(DC_HPD3_INT_CONTROL);
sys/dev/drm/radeon/cik.c
7432
tmp |= DC_HPDx_RX_INT_ACK;
sys/dev/drm/radeon/cik.c
7433
WREG32(DC_HPD3_INT_CONTROL, tmp);
sys/dev/drm/radeon/cik.c
7436
tmp = RREG32(DC_HPD4_INT_CONTROL);
sys/dev/drm/radeon/cik.c
7437
tmp |= DC_HPDx_RX_INT_ACK;
sys/dev/drm/radeon/cik.c
7438
WREG32(DC_HPD4_INT_CONTROL, tmp);
sys/dev/drm/radeon/cik.c
7441
tmp = RREG32(DC_HPD5_INT_CONTROL);
sys/dev/drm/radeon/cik.c
7442
tmp |= DC_HPDx_RX_INT_ACK;
sys/dev/drm/radeon/cik.c
7443
WREG32(DC_HPD5_INT_CONTROL, tmp);
sys/dev/drm/radeon/cik.c
7446
tmp = RREG32(DC_HPD6_INT_CONTROL);
sys/dev/drm/radeon/cik.c
7447
tmp |= DC_HPDx_RX_INT_ACK;
sys/dev/drm/radeon/cik.c
7448
WREG32(DC_HPD6_INT_CONTROL, tmp);
sys/dev/drm/radeon/cik.c
7510
u32 wptr, tmp;
sys/dev/drm/radeon/cik.c
7526
tmp = RREG32(IH_RB_CNTL);
sys/dev/drm/radeon/cik.c
7527
tmp |= IH_WPTR_OVERFLOW_CLEAR;
sys/dev/drm/radeon/cik.c
7528
WREG32(IH_RB_CNTL, tmp);
sys/dev/drm/radeon/cik.c
8765
u32 tmp = 0;
sys/dev/drm/radeon/cik.c
8790
tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
sys/dev/drm/radeon/cik.c
8793
tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(0));
sys/dev/drm/radeon/cik.c
8798
tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
sys/dev/drm/radeon/cik.c
8802
tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(1));
sys/dev/drm/radeon/cik.c
8807
tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
sys/dev/drm/radeon/cik.c
8811
tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(2));
sys/dev/drm/radeon/cik.c
8818
WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/drm/radeon/cik.c
8838
u32 tmp, buffer_alloc, i;
sys/dev/drm/radeon/cik.c
8850
tmp = 1;
sys/dev/drm/radeon/cik.c
8853
tmp = 2;
sys/dev/drm/radeon/cik.c
8856
tmp = 0;
sys/dev/drm/radeon/cik.c
8860
tmp = 0;
sys/dev/drm/radeon/cik.c
8864
tmp = 1;
sys/dev/drm/radeon/cik.c
8869
LB_MEMORY_CONFIG(tmp) | LB_MEMORY_SIZE(0x6B0));
sys/dev/drm/radeon/cik.c
8881
switch (tmp) {
sys/dev/drm/radeon/cik.c
8907
u32 tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/drm/radeon/cik.c
8909
switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
sys/dev/drm/radeon/cik.c
9139
u32 tmp, dmif_size = 12288;
sys/dev/drm/radeon/cik.c
9158
tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
sys/dev/drm/radeon/cik.c
9159
tmp = min(dfixed_trunc(a), tmp);
sys/dev/drm/radeon/cik.c
9161
lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
sys/dev/drm/radeon/cik.c
9272
u32 tmp, wm_mask;
sys/dev/drm/radeon/cik.c
9367
tmp = wm_mask;
sys/dev/drm/radeon/cik.c
9368
tmp &= ~LATENCY_WATERMARK_MASK(3);
sys/dev/drm/radeon/cik.c
9369
tmp |= LATENCY_WATERMARK_MASK(1);
sys/dev/drm/radeon/cik.c
9370
WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/drm/radeon/cik.c
9375
tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
sys/dev/drm/radeon/cik.c
9376
tmp &= ~LATENCY_WATERMARK_MASK(3);
sys/dev/drm/radeon/cik.c
9377
tmp |= LATENCY_WATERMARK_MASK(2);
sys/dev/drm/radeon/cik.c
9378
WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/drm/radeon/cik.c
9446
uint32_t tmp;
sys/dev/drm/radeon/cik.c
9453
tmp = RREG32_SMC(cntl_reg);
sys/dev/drm/radeon/cik.c
9454
tmp &= ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK);
sys/dev/drm/radeon/cik.c
9455
tmp |= dividers.post_divider;
sys/dev/drm/radeon/cik.c
9456
WREG32_SMC(cntl_reg, tmp);
sys/dev/drm/radeon/cik.c
9485
u32 tmp;
sys/dev/drm/radeon/cik.c
9500
tmp = RREG32_SMC(CG_ECLK_CNTL);
sys/dev/drm/radeon/cik.c
9501
tmp &= ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK);
sys/dev/drm/radeon/cik.c
9502
tmp |= dividers.post_divider;
sys/dev/drm/radeon/cik.c
9503
WREG32_SMC(CG_ECLK_CNTL, tmp);
sys/dev/drm/radeon/cik.c
9577
u32 max_lw, current_lw, tmp;
sys/dev/drm/radeon/cik.c
9588
tmp = RREG32_PCIE_PORT(PCIE_LC_STATUS1);
sys/dev/drm/radeon/cik.c
9589
max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
sys/dev/drm/radeon/cik.c
9590
current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
sys/dev/drm/radeon/cik.c
9593
tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
sys/dev/drm/radeon/cik.c
9594
if (tmp & LC_RENEGOTIATION_SUPPORT) {
sys/dev/drm/radeon/cik.c
9595
tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
sys/dev/drm/radeon/cik.c
9596
tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
sys/dev/drm/radeon/cik.c
9597
tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
sys/dev/drm/radeon/cik.c
9598
WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
sys/dev/drm/radeon/cik.c
9614
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
sys/dev/drm/radeon/cik.c
9615
tmp |= LC_SET_QUIESCE;
sys/dev/drm/radeon/cik.c
9616
WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
sys/dev/drm/radeon/cik.c
9618
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
sys/dev/drm/radeon/cik.c
9619
tmp |= LC_REDO_EQ;
sys/dev/drm/radeon/cik.c
9620
WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
sys/dev/drm/radeon/cik.c
9646
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
sys/dev/drm/radeon/cik.c
9647
tmp &= ~LC_SET_QUIESCE;
sys/dev/drm/radeon/cik.c
9648
WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
sys/dev/drm/radeon/cik_sdma.c
649
u32 tmp;
sys/dev/drm/radeon/cik_sdma.c
659
tmp = 0xCAFEDEAD;
sys/dev/drm/radeon/cik_sdma.c
660
rdev->wb.wb[index/4] = cpu_to_le32(tmp);
sys/dev/drm/radeon/cik_sdma.c
675
tmp = le32_to_cpu(rdev->wb.wb[index/4]);
sys/dev/drm/radeon/cik_sdma.c
676
if (tmp == 0xDEADBEEF)
sys/dev/drm/radeon/cik_sdma.c
685
ring->idx, tmp);
sys/dev/drm/radeon/cik_sdma.c
706
u32 tmp = 0;
sys/dev/drm/radeon/cik_sdma.c
716
tmp = 0xCAFEDEAD;
sys/dev/drm/radeon/cik_sdma.c
717
rdev->wb.wb[index/4] = cpu_to_le32(tmp);
sys/dev/drm/radeon/cik_sdma.c
749
tmp = le32_to_cpu(rdev->wb.wb[index/4]);
sys/dev/drm/radeon/cik_sdma.c
750
if (tmp == 0xDEADBEEF)
sys/dev/drm/radeon/cik_sdma.c
757
DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
sys/dev/drm/radeon/cypress_dpm.c
1580
u32 tmp = RREG32(GENERAL_PWRMGT);
sys/dev/drm/radeon/cypress_dpm.c
1582
if (!(tmp & BACKBIAS_PAD_EN)) {
sys/dev/drm/radeon/cypress_dpm.c
1589
if (tmp & BACKBIAS_VALUE)
sys/dev/drm/radeon/cypress_dpm.c
1699
u32 tmp;
sys/dev/drm/radeon/cypress_dpm.c
1705
&tmp, pi->sram_end);
sys/dev/drm/radeon/cypress_dpm.c
1709
pi->state_table_start = (u16)tmp;
sys/dev/drm/radeon/cypress_dpm.c
1714
&tmp, pi->sram_end);
sys/dev/drm/radeon/cypress_dpm.c
1718
pi->soft_regs_start = (u16)tmp;
sys/dev/drm/radeon/cypress_dpm.c
1723
&tmp, pi->sram_end);
sys/dev/drm/radeon/cypress_dpm.c
1727
eg_pi->mc_reg_table_start = (u16)tmp;
sys/dev/drm/radeon/cypress_dpm.c
1734
u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
sys/dev/drm/radeon/cypress_dpm.c
1736
tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
sys/dev/drm/radeon/cypress_dpm.c
1737
tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
sys/dev/drm/radeon/cypress_dpm.c
1740
tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
sys/dev/drm/radeon/cypress_dpm.c
1741
tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
sys/dev/drm/radeon/cypress_dpm.c
1743
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/drm/radeon/cypress_dpm.c
1748
u32 tmp, pipe;
sys/dev/drm/radeon/cypress_dpm.c
1751
tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
sys/dev/drm/radeon/cypress_dpm.c
1753
tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
sys/dev/drm/radeon/cypress_dpm.c
1755
tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/drm/radeon/cypress_dpm.c
1758
tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
sys/dev/drm/radeon/cypress_dpm.c
1760
tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/drm/radeon/cypress_dpm.c
1762
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/drm/radeon/cypress_dpm.c
1764
tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
sys/dev/drm/radeon/cypress_dpm.c
1765
pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
sys/dev/drm/radeon/cypress_dpm.c
1779
tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
sys/dev/drm/radeon/cypress_dpm.c
1780
tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
sys/dev/drm/radeon/cypress_dpm.c
1781
WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
sys/dev/drm/radeon/cypress_dpm.c
306
u32 tmp;
sys/dev/drm/radeon/cypress_dpm.c
309
tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
sys/dev/drm/radeon/cypress_dpm.c
310
if ((perf_req == PCIE_PERF_REQ_PECI_GEN1) && (tmp & LC_CURRENT_DATA_RATE))
sys/dev/drm/radeon/cypress_dpm.c
331
u32 tmp;
sys/dev/drm/radeon/cypress_dpm.c
337
tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
sys/dev/drm/radeon/cypress_dpm.c
339
if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
sys/dev/drm/radeon/cypress_dpm.c
340
(tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
sys/dev/drm/radeon/cypress_dpm.c
53
u32 tmp, bif;
sys/dev/drm/radeon/cypress_dpm.c
55
tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
sys/dev/drm/radeon/cypress_dpm.c
57
if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
sys/dev/drm/radeon/cypress_dpm.c
58
(tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
sys/dev/drm/radeon/cypress_dpm.c
64
tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
sys/dev/drm/radeon/cypress_dpm.c
65
tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
sys/dev/drm/radeon/cypress_dpm.c
66
tmp |= LC_GEN2_EN_STRAP;
sys/dev/drm/radeon/cypress_dpm.c
68
tmp |= LC_CLR_FAILED_SPD_CHANGE_CNT;
sys/dev/drm/radeon/cypress_dpm.c
69
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/drm/radeon/cypress_dpm.c
71
tmp &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
sys/dev/drm/radeon/cypress_dpm.c
72
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/drm/radeon/cypress_dpm.c
77
tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
sys/dev/drm/radeon/cypress_dpm.c
78
tmp &= ~LC_GEN2_EN_STRAP;
sys/dev/drm/radeon/cypress_dpm.c
80
if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
sys/dev/drm/radeon/cypress_dpm.c
81
(tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
sys/dev/drm/radeon/cypress_dpm.c
82
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/drm/radeon/dce3_1_afmt.c
36
u32 tmp;
sys/dev/drm/radeon/dce3_1_afmt.c
39
tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
sys/dev/drm/radeon/dce3_1_afmt.c
40
tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
sys/dev/drm/radeon/dce3_1_afmt.c
42
tmp |= HDMI_CONNECTION;
sys/dev/drm/radeon/dce3_1_afmt.c
44
tmp |= SPEAKER_ALLOCATION(sadb[0]);
sys/dev/drm/radeon/dce3_1_afmt.c
46
tmp |= SPEAKER_ALLOCATION(5); /* stereo */
sys/dev/drm/radeon/dce3_1_afmt.c
47
WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
sys/dev/drm/radeon/dce3_1_afmt.c
56
u32 tmp;
sys/dev/drm/radeon/dce3_1_afmt.c
59
tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
sys/dev/drm/radeon/dce3_1_afmt.c
60
tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
sys/dev/drm/radeon/dce3_1_afmt.c
62
tmp |= DP_CONNECTION;
sys/dev/drm/radeon/dce3_1_afmt.c
64
tmp |= SPEAKER_ALLOCATION(sadb[0]);
sys/dev/drm/radeon/dce3_1_afmt.c
66
tmp |= SPEAKER_ALLOCATION(5); /* stereo */
sys/dev/drm/radeon/dce3_1_afmt.c
67
WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
sys/dev/drm/radeon/dce6_afmt.c
139
u32 tmp = 0;
sys/dev/drm/radeon/dce6_afmt.c
146
tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
sys/dev/drm/radeon/dce6_afmt.c
149
tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0);
sys/dev/drm/radeon/dce6_afmt.c
152
tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
sys/dev/drm/radeon/dce6_afmt.c
155
tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0);
sys/dev/drm/radeon/dce6_afmt.c
158
AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
sys/dev/drm/radeon/dce6_afmt.c
169
u32 tmp;
sys/dev/drm/radeon/dce6_afmt.c
175
tmp = RREG32_ENDPOINT(dig->pin->offset,
sys/dev/drm/radeon/dce6_afmt.c
177
tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
sys/dev/drm/radeon/dce6_afmt.c
179
tmp |= HDMI_CONNECTION;
sys/dev/drm/radeon/dce6_afmt.c
181
tmp |= SPEAKER_ALLOCATION(sadb[0]);
sys/dev/drm/radeon/dce6_afmt.c
183
tmp |= SPEAKER_ALLOCATION(5); /* stereo */
sys/dev/drm/radeon/dce6_afmt.c
185
AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
sys/dev/drm/radeon/dce6_afmt.c
196
u32 tmp;
sys/dev/drm/radeon/dce6_afmt.c
202
tmp = RREG32_ENDPOINT(dig->pin->offset,
sys/dev/drm/radeon/dce6_afmt.c
204
tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
sys/dev/drm/radeon/dce6_afmt.c
206
tmp |= DP_CONNECTION;
sys/dev/drm/radeon/dce6_afmt.c
208
tmp |= SPEAKER_ALLOCATION(sadb[0]);
sys/dev/drm/radeon/dce6_afmt.c
210
tmp |= SPEAKER_ALLOCATION(5); /* stereo */
sys/dev/drm/radeon/dce6_afmt.c
212
AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
sys/dev/drm/radeon/dce6_afmt.c
73
u32 offset, tmp;
sys/dev/drm/radeon/dce6_afmt.c
77
tmp = RREG32_ENDPOINT(offset,
sys/dev/drm/radeon/dce6_afmt.c
79
if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1)
sys/dev/drm/radeon/evergreen.c
1285
u32 tmp = 0;
sys/dev/drm/radeon/evergreen.c
1310
tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
sys/dev/drm/radeon/evergreen.c
1313
tmp |= FMT_TRUNCATE_EN;
sys/dev/drm/radeon/evergreen.c
1318
tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
sys/dev/drm/radeon/evergreen.c
1322
tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH);
sys/dev/drm/radeon/evergreen.c
1330
WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/drm/radeon/evergreen.c
1658
u32 tmp;
sys/dev/drm/radeon/evergreen.c
1664
tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
sys/dev/drm/radeon/evergreen.c
1665
tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
sys/dev/drm/radeon/evergreen.c
1666
WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/drm/radeon/evergreen.c
1683
u32 tmp;
sys/dev/drm/radeon/evergreen.c
1689
tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
sys/dev/drm/radeon/evergreen.c
1690
tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
sys/dev/drm/radeon/evergreen.c
1691
WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/drm/radeon/evergreen.c
1748
u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
sys/dev/drm/radeon/evergreen.c
1768
WREG32(DC_HPDx_CONTROL(hpd), tmp);
sys/dev/drm/radeon/evergreen.c
1810
u32 tmp, buffer_alloc, i;
sys/dev/drm/radeon/evergreen.c
1835
tmp = 0; /* 1/2 */
sys/dev/drm/radeon/evergreen.c
1838
tmp = 2; /* whole */
sys/dev/drm/radeon/evergreen.c
1842
tmp = 0;
sys/dev/drm/radeon/evergreen.c
1848
tmp += 4;
sys/dev/drm/radeon/evergreen.c
1849
WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
sys/dev/drm/radeon/evergreen.c
1863
switch (tmp) {
sys/dev/drm/radeon/evergreen.c
1898
u32 tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/drm/radeon/evergreen.c
1900
switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
sys/dev/drm/radeon/evergreen.c
2148
u32 tmp, arb_control3;
sys/dev/drm/radeon/evergreen.c
2267
tmp = arb_control3;
sys/dev/drm/radeon/evergreen.c
2268
tmp &= ~LATENCY_WATERMARK_MASK(3);
sys/dev/drm/radeon/evergreen.c
2269
tmp |= LATENCY_WATERMARK_MASK(1);
sys/dev/drm/radeon/evergreen.c
2270
WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
sys/dev/drm/radeon/evergreen.c
2275
tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
sys/dev/drm/radeon/evergreen.c
2276
tmp &= ~LATENCY_WATERMARK_MASK(3);
sys/dev/drm/radeon/evergreen.c
2277
tmp |= LATENCY_WATERMARK_MASK(2);
sys/dev/drm/radeon/evergreen.c
2278
WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
sys/dev/drm/radeon/evergreen.c
2341
u32 tmp;
sys/dev/drm/radeon/evergreen.c
2345
tmp = RREG32(SRBM_STATUS) & 0x1F00;
sys/dev/drm/radeon/evergreen.c
2346
if (!tmp)
sys/dev/drm/radeon/evergreen.c
2359
u32 tmp;
sys/dev/drm/radeon/evergreen.c
2366
tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
sys/dev/drm/radeon/evergreen.c
2367
tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
sys/dev/drm/radeon/evergreen.c
2368
if (tmp == 2) {
sys/dev/drm/radeon/evergreen.c
2372
if (tmp) {
sys/dev/drm/radeon/evergreen.c
2381
u32 tmp;
sys/dev/drm/radeon/evergreen.c
2398
tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
sys/dev/drm/radeon/evergreen.c
2403
WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
2404
WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
2405
WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
2407
WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
2408
WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
2409
WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
2414
WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
2416
WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
2417
WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
2418
WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
2419
WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
2439
u32 tmp;
sys/dev/drm/radeon/evergreen.c
2451
tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
sys/dev/drm/radeon/evergreen.c
2452
WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
2453
WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
2454
WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
2455
WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
2456
WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
2457
WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
2458
WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
2472
u32 tmp;
sys/dev/drm/radeon/evergreen.c
2481
tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
sys/dev/drm/radeon/evergreen.c
2485
WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
2486
WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
2487
WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
2488
WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
2489
WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
2490
WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
2491
WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
2648
u32 crtc_enabled, tmp, frame_count, blackout;
sys/dev/drm/radeon/evergreen.c
2665
tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
2666
if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
sys/dev/drm/radeon/evergreen.c
2669
tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
sys/dev/drm/radeon/evergreen.c
2670
WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
sys/dev/drm/radeon/evergreen.c
2674
tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
2675
if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
sys/dev/drm/radeon/evergreen.c
2678
tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
sys/dev/drm/radeon/evergreen.c
2679
WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/drm/radeon/evergreen.c
2703
tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
2704
tmp &= ~EVERGREEN_CRTC_MASTER_EN;
sys/dev/drm/radeon/evergreen.c
2705
WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/drm/radeon/evergreen.c
2730
tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
2731
if (!(tmp & EVERGREEN_GRPH_UPDATE_LOCK)) {
sys/dev/drm/radeon/evergreen.c
2732
tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
sys/dev/drm/radeon/evergreen.c
2733
WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
sys/dev/drm/radeon/evergreen.c
2735
tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
2736
if (!(tmp & 1)) {
sys/dev/drm/radeon/evergreen.c
2737
tmp |= 1;
sys/dev/drm/radeon/evergreen.c
2738
WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
sys/dev/drm/radeon/evergreen.c
2746
u32 tmp, frame_count;
sys/dev/drm/radeon/evergreen.c
2769
tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
2770
if ((tmp & 0x7) != 0) {
sys/dev/drm/radeon/evergreen.c
2771
tmp &= ~0x7;
sys/dev/drm/radeon/evergreen.c
2772
WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
sys/dev/drm/radeon/evergreen.c
2774
tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
2775
if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) {
sys/dev/drm/radeon/evergreen.c
2776
tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
sys/dev/drm/radeon/evergreen.c
2777
WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
sys/dev/drm/radeon/evergreen.c
2779
tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
2780
if (tmp & 1) {
sys/dev/drm/radeon/evergreen.c
2781
tmp &= ~1;
sys/dev/drm/radeon/evergreen.c
2782
WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
sys/dev/drm/radeon/evergreen.c
2785
tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
2786
if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0)
sys/dev/drm/radeon/evergreen.c
2794
tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
sys/dev/drm/radeon/evergreen.c
2795
tmp &= ~BLACKOUT_MODE_MASK;
sys/dev/drm/radeon/evergreen.c
2796
WREG32(MC_SHARED_BLACKOUT_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
2803
tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
2804
tmp &= ~EVERGREEN_CRTC_BLANK_DATA_EN;
sys/dev/drm/radeon/evergreen.c
2806
WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
sys/dev/drm/radeon/evergreen.c
2809
tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
2810
tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
sys/dev/drm/radeon/evergreen.c
2812
WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/drm/radeon/evergreen.c
2835
u32 tmp;
sys/dev/drm/radeon/evergreen.c
2880
tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
sys/dev/drm/radeon/evergreen.c
2881
tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
sys/dev/drm/radeon/evergreen.c
2882
tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
sys/dev/drm/radeon/evergreen.c
2883
WREG32(MC_FUS_VM_FB_OFFSET, tmp);
sys/dev/drm/radeon/evergreen.c
2885
tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
sys/dev/drm/radeon/evergreen.c
2886
tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
sys/dev/drm/radeon/evergreen.c
2887
WREG32(MC_VM_FB_LOCATION, tmp);
sys/dev/drm/radeon/evergreen.c
3048
u32 tmp;
sys/dev/drm/radeon/evergreen.c
3066
tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
sys/dev/drm/radeon/evergreen.c
3068
tmp |= BUF_SWAP_32BIT;
sys/dev/drm/radeon/evergreen.c
3070
WREG32(CP_RB_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
3078
WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
sys/dev/drm/radeon/evergreen.c
3092
tmp |= RB_NO_UPDATE;
sys/dev/drm/radeon/evergreen.c
3097
WREG32(CP_RB_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
3132
u32 hdp_host_path_cntl, tmp;
sys/dev/drm/radeon/evergreen.c
3440
tmp = (((efuse_straps_4 & 0xf) << 4) |
sys/dev/drm/radeon/evergreen.c
3443
tmp = 0;
sys/dev/drm/radeon/evergreen.c
3450
tmp <<= 4;
sys/dev/drm/radeon/evergreen.c
3451
tmp |= rb_disable_bitmap;
sys/dev/drm/radeon/evergreen.c
3455
disabled_rb_mask = tmp;
sys/dev/drm/radeon/evergreen.c
3456
tmp = 0;
sys/dev/drm/radeon/evergreen.c
3458
tmp |= (1 << i);
sys/dev/drm/radeon/evergreen.c
3460
if ((disabled_rb_mask & tmp) == tmp) {
sys/dev/drm/radeon/evergreen.c
3472
tmp <<= 16;
sys/dev/drm/radeon/evergreen.c
3473
tmp |= simd_disable_bitmap;
sys/dev/drm/radeon/evergreen.c
3475
rdev->config.evergreen.active_simds = hweight32(~tmp);
sys/dev/drm/radeon/evergreen.c
3492
tmp = 0x11111111;
sys/dev/drm/radeon/evergreen.c
3495
tmp = 0x00000000;
sys/dev/drm/radeon/evergreen.c
3498
tmp = gb_addr_config & NUM_PIPES_MASK;
sys/dev/drm/radeon/evergreen.c
3499
tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
sys/dev/drm/radeon/evergreen.c
3502
rdev->config.evergreen.backend_map = tmp;
sys/dev/drm/radeon/evergreen.c
3503
WREG32(GB_BACKEND_MAP, tmp);
sys/dev/drm/radeon/evergreen.c
3679
tmp = RREG32(HDP_MISC_CNTL);
sys/dev/drm/radeon/evergreen.c
3680
tmp |= HDP_FLUSH_INVALIDATE_CACHE;
sys/dev/drm/radeon/evergreen.c
3681
WREG32(HDP_MISC_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
3694
u32 tmp;
sys/dev/drm/radeon/evergreen.c
3702
tmp = RREG32(FUS_MC_ARB_RAMCFG);
sys/dev/drm/radeon/evergreen.c
3704
tmp = RREG32(MC_ARB_RAMCFG);
sys/dev/drm/radeon/evergreen.c
3705
if (tmp & CHANSIZE_OVERRIDE) {
sys/dev/drm/radeon/evergreen.c
3707
} else if (tmp & CHANSIZE_MASK) {
sys/dev/drm/radeon/evergreen.c
3712
tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/drm/radeon/evergreen.c
3713
switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
sys/dev/drm/radeon/evergreen.c
3783
u32 i, j, tmp;
sys/dev/drm/radeon/evergreen.c
3795
tmp = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
3796
if (tmp != crtc_status[i])
sys/dev/drm/radeon/evergreen.c
3811
u32 tmp;
sys/dev/drm/radeon/evergreen.c
3814
tmp = RREG32(GRBM_STATUS);
sys/dev/drm/radeon/evergreen.c
3815
if (tmp & (PA_BUSY | SC_BUSY |
sys/dev/drm/radeon/evergreen.c
3822
if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
sys/dev/drm/radeon/evergreen.c
3826
if (tmp & GRBM_EE_BUSY)
sys/dev/drm/radeon/evergreen.c
3830
tmp = RREG32(DMA_STATUS_REG);
sys/dev/drm/radeon/evergreen.c
3831
if (!(tmp & DMA_IDLE))
sys/dev/drm/radeon/evergreen.c
3835
tmp = RREG32(SRBM_STATUS2);
sys/dev/drm/radeon/evergreen.c
3836
if (tmp & DMA_BUSY)
sys/dev/drm/radeon/evergreen.c
3840
tmp = RREG32(SRBM_STATUS);
sys/dev/drm/radeon/evergreen.c
3841
if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
sys/dev/drm/radeon/evergreen.c
3844
if (tmp & IH_BUSY)
sys/dev/drm/radeon/evergreen.c
3847
if (tmp & SEM_BUSY)
sys/dev/drm/radeon/evergreen.c
3850
if (tmp & GRBM_RQ_PENDING)
sys/dev/drm/radeon/evergreen.c
3853
if (tmp & VMC_BUSY)
sys/dev/drm/radeon/evergreen.c
3856
if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
sys/dev/drm/radeon/evergreen.c
3864
tmp = RREG32(VM_L2_STATUS);
sys/dev/drm/radeon/evergreen.c
3865
if (tmp & L2_BUSY)
sys/dev/drm/radeon/evergreen.c
3881
u32 tmp;
sys/dev/drm/radeon/evergreen.c
3895
tmp = RREG32(DMA_RB_CNTL);
sys/dev/drm/radeon/evergreen.c
3896
tmp &= ~DMA_RB_ENABLE;
sys/dev/drm/radeon/evergreen.c
3897
WREG32(DMA_RB_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
3955
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/evergreen.c
3956
tmp |= grbm_soft_reset;
sys/dev/drm/radeon/evergreen.c
3957
dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/radeon/evergreen.c
3958
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/drm/radeon/evergreen.c
3959
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/evergreen.c
3963
tmp &= ~grbm_soft_reset;
sys/dev/drm/radeon/evergreen.c
3964
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/drm/radeon/evergreen.c
3965
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/evergreen.c
3969
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/evergreen.c
3970
tmp |= srbm_soft_reset;
sys/dev/drm/radeon/evergreen.c
3971
dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/radeon/evergreen.c
3972
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/drm/radeon/evergreen.c
3973
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/evergreen.c
3977
tmp &= ~srbm_soft_reset;
sys/dev/drm/radeon/evergreen.c
3978
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/drm/radeon/evergreen.c
3979
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/evergreen.c
3994
u32 tmp, i;
sys/dev/drm/radeon/evergreen.c
4004
tmp = RREG32(DMA_RB_CNTL);
sys/dev/drm/radeon/evergreen.c
4005
tmp &= ~DMA_RB_ENABLE;
sys/dev/drm/radeon/evergreen.c
4006
WREG32(DMA_RB_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
4380
u32 tmp = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;
sys/dev/drm/radeon/evergreen.c
4381
tmp |= 0xffffffff << rdev->config.cayman.max_simds_per_se;
sys/dev/drm/radeon/evergreen.c
4382
tmp = hweight32(~tmp);
sys/dev/drm/radeon/evergreen.c
4383
if (tmp == rdev->config.cayman.max_simds_per_se) {
sys/dev/drm/radeon/evergreen.c
4443
u32 tmp;
sys/dev/drm/radeon/evergreen.c
4450
tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
sys/dev/drm/radeon/evergreen.c
4451
WREG32(CAYMAN_DMA1_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
4454
tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
sys/dev/drm/radeon/evergreen.c
4455
WREG32(DMA_CNTL, tmp);
sys/dev/drm/radeon/evergreen.c
4660
u32 wptr, tmp;
sys/dev/drm/radeon/evergreen.c
4676
tmp = RREG32(IH_RB_CNTL);
sys/dev/drm/radeon/evergreen.c
4677
tmp |= IH_WPTR_OVERFLOW_CLEAR;
sys/dev/drm/radeon/evergreen.c
4678
WREG32(IH_RB_CNTL, tmp);
sys/dev/drm/radeon/evergreen_cs.c
1096
u32 tmp, *ib;
sys/dev/drm/radeon/evergreen_cs.c
1277
tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
sys/dev/drm/radeon/evergreen_cs.c
1278
track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
sys/dev/drm/radeon/evergreen_cs.c
1280
track->vgt_strmout_bo[tmp] = reloc->robj;
sys/dev/drm/radeon/evergreen_cs.c
1287
tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
sys/dev/drm/radeon/evergreen_cs.c
1289
track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
sys/dev/drm/radeon/evergreen_cs.c
1315
tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;
sys/dev/drm/radeon/evergreen_cs.c
1316
track->nsamples = 1 << tmp;
sys/dev/drm/radeon/evergreen_cs.c
1324
tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK;
sys/dev/drm/radeon/evergreen_cs.c
1325
track->nsamples = 1 << tmp;
sys/dev/drm/radeon/evergreen_cs.c
1335
tmp = (reg - CB_COLOR0_VIEW) / 0x3c;
sys/dev/drm/radeon/evergreen_cs.c
1336
track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
sys/dev/drm/radeon/evergreen_cs.c
1343
tmp = ((reg - CB_COLOR8_VIEW) / 0x1c) + 8;
sys/dev/drm/radeon/evergreen_cs.c
1344
track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
sys/dev/drm/radeon/evergreen_cs.c
1355
tmp = (reg - CB_COLOR0_INFO) / 0x3c;
sys/dev/drm/radeon/evergreen_cs.c
1356
track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
sys/dev/drm/radeon/evergreen_cs.c
1365
track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
sys/dev/drm/radeon/evergreen_cs.c
1373
tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8;
sys/dev/drm/radeon/evergreen_cs.c
1374
track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
sys/dev/drm/radeon/evergreen_cs.c
1383
track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
sys/dev/drm/radeon/evergreen_cs.c
1395
tmp = (reg - CB_COLOR0_PITCH) / 0x3c;
sys/dev/drm/radeon/evergreen_cs.c
1396
track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
sys/dev/drm/radeon/evergreen_cs.c
1403
tmp = ((reg - CB_COLOR8_PITCH) / 0x1c) + 8;
sys/dev/drm/radeon/evergreen_cs.c
1404
track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
sys/dev/drm/radeon/evergreen_cs.c
1415
tmp = (reg - CB_COLOR0_SLICE) / 0x3c;
sys/dev/drm/radeon/evergreen_cs.c
1416
track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
sys/dev/drm/radeon/evergreen_cs.c
1417
track->cb_color_slice_idx[tmp] = idx;
sys/dev/drm/radeon/evergreen_cs.c
1424
tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8;
sys/dev/drm/radeon/evergreen_cs.c
1425
track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
sys/dev/drm/radeon/evergreen_cs.c
1426
track->cb_color_slice_idx[tmp] = idx;
sys/dev/drm/radeon/evergreen_cs.c
1457
tmp = ((reg - CB_COLOR0_ATTRIB) / 0x3c);
sys/dev/drm/radeon/evergreen_cs.c
1458
track->cb_color_attrib[tmp] = ib[idx];
sys/dev/drm/radeon/evergreen_cs.c
1485
tmp = ((reg - CB_COLOR8_ATTRIB) / 0x1c) + 8;
sys/dev/drm/radeon/evergreen_cs.c
1486
track->cb_color_attrib[tmp] = ib[idx];
sys/dev/drm/radeon/evergreen_cs.c
1497
tmp = (reg - CB_COLOR0_FMASK) / 0x3c;
sys/dev/drm/radeon/evergreen_cs.c
1504
track->cb_color_fmask_bo[tmp] = reloc->robj;
sys/dev/drm/radeon/evergreen_cs.c
1514
tmp = (reg - CB_COLOR0_CMASK) / 0x3c;
sys/dev/drm/radeon/evergreen_cs.c
1521
track->cb_color_cmask_bo[tmp] = reloc->robj;
sys/dev/drm/radeon/evergreen_cs.c
1531
tmp = (reg - CB_COLOR0_FMASK_SLICE) / 0x3c;
sys/dev/drm/radeon/evergreen_cs.c
1532
track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx);
sys/dev/drm/radeon/evergreen_cs.c
1542
tmp = (reg - CB_COLOR0_CMASK_SLICE) / 0x3c;
sys/dev/drm/radeon/evergreen_cs.c
1543
track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx);
sys/dev/drm/radeon/evergreen_cs.c
1559
tmp = (reg - CB_COLOR0_BASE) / 0x3c;
sys/dev/drm/radeon/evergreen_cs.c
1560
track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
sys/dev/drm/radeon/evergreen_cs.c
1562
track->cb_color_bo[tmp] = reloc->robj;
sys/dev/drm/radeon/evergreen_cs.c
1575
tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8;
sys/dev/drm/radeon/evergreen_cs.c
1576
track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
sys/dev/drm/radeon/evergreen_cs.c
1578
track->cb_color_bo[tmp] = reloc->robj;
sys/dev/drm/radeon/evergreen_cs.c
1791
int tmp;
sys/dev/drm/radeon/evergreen_cs.c
1799
tmp = radeon_get_ib_value(p, idx + 1);
sys/dev/drm/radeon/evergreen_cs.c
1800
pred_op = (tmp >> 16) & 0x7;
sys/dev/drm/radeon/evergreen_cs.c
1819
((u64)(tmp & 0xff) << 32);
sys/dev/drm/radeon/evergreen_cs.c
1822
ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
sys/dev/drm/radeon/evergreen_cs.c
2113
u64 offset, tmp;
sys/dev/drm/radeon/evergreen_cs.c
2153
tmp = radeon_get_ib_value(p, idx) +
sys/dev/drm/radeon/evergreen_cs.c
2156
offset = reloc->gpu_offset + tmp;
sys/dev/drm/radeon/evergreen_cs.c
2158
if ((tmp + size) > radeon_bo_size(reloc->robj)) {
sys/dev/drm/radeon/evergreen_cs.c
2160
tmp + size, radeon_bo_size(reloc->robj));
sys/dev/drm/radeon/evergreen_cs.c
2191
tmp = radeon_get_ib_value(p, idx+2) +
sys/dev/drm/radeon/evergreen_cs.c
2194
offset = reloc->gpu_offset + tmp;
sys/dev/drm/radeon/evergreen_cs.c
2196
if ((tmp + size) > radeon_bo_size(reloc->robj)) {
sys/dev/drm/radeon/evergreen_cs.c
2198
tmp + size, radeon_bo_size(reloc->robj));
sys/dev/drm/radeon/evergreen_cs.c
2674
u32 tmp;
sys/dev/drm/radeon/evergreen_cs.c
2684
tmp = p->rdev->config.cayman.tile_config;
sys/dev/drm/radeon/evergreen_cs.c
2687
tmp = p->rdev->config.evergreen.tile_config;
sys/dev/drm/radeon/evergreen_cs.c
2692
switch (tmp & 0xf) {
sys/dev/drm/radeon/evergreen_cs.c
2708
switch ((tmp & 0xf0) >> 4) {
sys/dev/drm/radeon/evergreen_cs.c
2721
switch ((tmp & 0xf00) >> 8) {
sys/dev/drm/radeon/evergreen_cs.c
2731
switch ((tmp & 0xf000) >> 12) {
sys/dev/drm/radeon/evergreen_cs.c
450
unsigned long tmp, nby, bsize, size, min = 0;
sys/dev/drm/radeon/evergreen_cs.c
457
tmp = track->cb_color_bo_offset[id] << 8;
sys/dev/drm/radeon/evergreen_cs.c
460
if ((tmp + size * mslice) <= bsize) {
sys/dev/drm/radeon/evergreen_cs.c
469
tmp += surf.layer_size * mslice;
sys/dev/drm/radeon/evergreen_cs.c
470
if (tmp <= bsize) {
sys/dev/drm/radeon/evergreen_cs.c
933
unsigned tmp, i;
sys/dev/drm/radeon/evergreen_cs.c
971
tmp = track->cb_target_mask;
sys/dev/drm/radeon/evergreen_cs.c
976
(tmp >> (i * 4)) & 0xF) {
sys/dev/drm/radeon/evergreen_hdmi.c
108
u32 tmp = 0;
sys/dev/drm/radeon/evergreen_hdmi.c
112
tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
sys/dev/drm/radeon/evergreen_hdmi.c
115
tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
sys/dev/drm/radeon/evergreen_hdmi.c
118
tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
sys/dev/drm/radeon/evergreen_hdmi.c
121
tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
sys/dev/drm/radeon/evergreen_hdmi.c
123
WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
sys/dev/drm/radeon/evergreen_hdmi.c
132
u32 tmp;
sys/dev/drm/radeon/evergreen_hdmi.c
135
tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
sys/dev/drm/radeon/evergreen_hdmi.c
136
tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
sys/dev/drm/radeon/evergreen_hdmi.c
138
tmp |= HDMI_CONNECTION;
sys/dev/drm/radeon/evergreen_hdmi.c
140
tmp |= SPEAKER_ALLOCATION(sadb[0]);
sys/dev/drm/radeon/evergreen_hdmi.c
142
tmp |= SPEAKER_ALLOCATION(5); /* stereo */
sys/dev/drm/radeon/evergreen_hdmi.c
143
WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
sys/dev/drm/radeon/evergreen_hdmi.c
152
u32 tmp;
sys/dev/drm/radeon/evergreen_hdmi.c
155
tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
sys/dev/drm/radeon/evergreen_hdmi.c
156
tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
sys/dev/drm/radeon/evergreen_hdmi.c
158
tmp |= DP_CONNECTION;
sys/dev/drm/radeon/evergreen_hdmi.c
160
tmp |= SPEAKER_ALLOCATION(sadb[0]);
sys/dev/drm/radeon/evergreen_hdmi.c
162
tmp |= SPEAKER_ALLOCATION(5); /* stereo */
sys/dev/drm/radeon/evergreen_hdmi.c
163
WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
sys/dev/drm/radeon/evergreen_hdmi.c
44
u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
sys/dev/drm/radeon/evergreen_hdmi.c
50
tmp |= AUDIO_ENABLED;
sys/dev/drm/radeon/evergreen_hdmi.c
52
tmp |= PIN0_AUDIO_ENABLED;
sys/dev/drm/radeon/evergreen_hdmi.c
54
tmp |= PIN1_AUDIO_ENABLED;
sys/dev/drm/radeon/evergreen_hdmi.c
56
tmp |= PIN2_AUDIO_ENABLED;
sys/dev/drm/radeon/evergreen_hdmi.c
58
tmp |= PIN3_AUDIO_ENABLED;
sys/dev/drm/radeon/evergreen_hdmi.c
60
tmp &= ~(AUDIO_ENABLED |
sys/dev/drm/radeon/evergreen_hdmi.c
67
WREG32(AZ_HOT_PLUG_CONTROL, tmp);
sys/dev/drm/radeon/kv_dpm.c
1362
u16 tmp;
sys/dev/drm/radeon/kv_dpm.c
1364
tmp = 45;
sys/dev/drm/radeon/kv_dpm.c
1365
pi->fps_high_t = cpu_to_be16(tmp);
sys/dev/drm/radeon/kv_dpm.c
1372
tmp = 30;
sys/dev/drm/radeon/kv_dpm.c
1373
pi->fps_low_t = cpu_to_be16(tmp);
sys/dev/drm/radeon/kv_dpm.c
2453
u32 tmp;
sys/dev/drm/radeon/kv_dpm.c
2464
tmp = RREG32_SMC(CG_THERMAL_INT_CTRL);
sys/dev/drm/radeon/kv_dpm.c
2465
tmp &= ~(DIG_THERM_INTH_MASK | DIG_THERM_INTL_MASK);
sys/dev/drm/radeon/kv_dpm.c
2466
tmp |= (DIG_THERM_INTH(49 + (high_temp / 1000)) |
sys/dev/drm/radeon/kv_dpm.c
2468
WREG32_SMC(CG_THERMAL_INT_CTRL, tmp);
sys/dev/drm/radeon/kv_dpm.c
2803
u32 sclk, tmp;
sys/dev/drm/radeon/kv_dpm.c
2810
tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
sys/dev/drm/radeon/kv_dpm.c
2812
vddc = kv_convert_8bit_index_to_voltage(rdev, (u16)tmp);
sys/dev/drm/radeon/kv_dpm.c
454
u32 tmp;
sys/dev/drm/radeon/kv_dpm.c
459
&tmp, pi->sram_end);
sys/dev/drm/radeon/kv_dpm.c
462
pi->dpm_table_start = tmp;
sys/dev/drm/radeon/kv_dpm.c
466
&tmp, pi->sram_end);
sys/dev/drm/radeon/kv_dpm.c
469
pi->soft_regs_start = tmp;
sys/dev/drm/radeon/kv_dpm.c
642
u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
sys/dev/drm/radeon/kv_dpm.c
644
tmp |= GLOBAL_PWRMGT_EN;
sys/dev/drm/radeon/kv_dpm.c
645
WREG32_SMC(GENERAL_PWRMGT, tmp);
sys/dev/drm/radeon/kv_smc.c
33
u32 tmp = 0;
sys/dev/drm/radeon/kv_smc.c
42
tmp = RREG32(SMC_RESP_0) & SMC_RESP_MASK;
sys/dev/drm/radeon/kv_smc.c
44
if (tmp != 1) {
sys/dev/drm/radeon/kv_smc.c
45
if (tmp == 0xFF)
sys/dev/drm/radeon/kv_smc.c
47
else if (tmp == 0xFE)
sys/dev/drm/radeon/ni.c
1032
tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
sys/dev/drm/radeon/ni.c
1033
rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
sys/dev/drm/radeon/ni.c
1041
tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
sys/dev/drm/radeon/ni.c
1042
rdev->config.cayman.num_tile_pipes = (1 << tmp);
sys/dev/drm/radeon/ni.c
1043
tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
sys/dev/drm/radeon/ni.c
1044
rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
sys/dev/drm/radeon/ni.c
1045
tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
sys/dev/drm/radeon/ni.c
1046
rdev->config.cayman.num_shader_engines = tmp + 1;
sys/dev/drm/radeon/ni.c
1047
tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
sys/dev/drm/radeon/ni.c
1048
rdev->config.cayman.num_gpus = tmp + 1;
sys/dev/drm/radeon/ni.c
1049
tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
sys/dev/drm/radeon/ni.c
1050
rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
sys/dev/drm/radeon/ni.c
1051
tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
sys/dev/drm/radeon/ni.c
1052
rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
sys/dev/drm/radeon/ni.c
1101
tmp = 0;
sys/dev/drm/radeon/ni.c
1108
tmp <<= 4;
sys/dev/drm/radeon/ni.c
1109
tmp |= rb_disable_bitmap;
sys/dev/drm/radeon/ni.c
1112
disabled_rb_mask = tmp;
sys/dev/drm/radeon/ni.c
1113
tmp = 0;
sys/dev/drm/radeon/ni.c
1115
tmp |= (1 << i);
sys/dev/drm/radeon/ni.c
1117
if ((disabled_rb_mask & tmp) == tmp) {
sys/dev/drm/radeon/ni.c
1129
tmp <<= 16;
sys/dev/drm/radeon/ni.c
1130
tmp |= simd_disable_bitmap;
sys/dev/drm/radeon/ni.c
1132
rdev->config.cayman.active_simds = hweight32(~tmp);
sys/dev/drm/radeon/ni.c
1152
tmp = 0x00000000;
sys/dev/drm/radeon/ni.c
1155
tmp = 0x11111111;
sys/dev/drm/radeon/ni.c
1158
tmp = gb_addr_config & NUM_PIPES_MASK;
sys/dev/drm/radeon/ni.c
1159
tmp = r6xx_remap_render_backend(rdev, tmp,
sys/dev/drm/radeon/ni.c
1164
rdev->config.cayman.backend_map = tmp;
sys/dev/drm/radeon/ni.c
1165
WREG32(GB_BACKEND_MAP, tmp);
sys/dev/drm/radeon/ni.c
1250
tmp = RREG32(HDP_MISC_CNTL);
sys/dev/drm/radeon/ni.c
1251
tmp |= HDP_FLUSH_INVALIDATE_CACHE;
sys/dev/drm/radeon/ni.c
1252
WREG32(HDP_MISC_CNTL, tmp);
sys/dev/drm/radeon/ni.c
1263
tmp = RREG32_CG(CG_CGTT_LOCAL_0);
sys/dev/drm/radeon/ni.c
1264
tmp &= ~0x00380000;
sys/dev/drm/radeon/ni.c
1265
WREG32_CG(CG_CGTT_LOCAL_0, tmp);
sys/dev/drm/radeon/ni.c
1266
tmp = RREG32_CG(CG_CGTT_LOCAL_1);
sys/dev/drm/radeon/ni.c
1267
tmp &= ~0x0e000000;
sys/dev/drm/radeon/ni.c
1268
WREG32_CG(CG_CGTT_LOCAL_1, tmp);
sys/dev/drm/radeon/ni.c
1759
u32 tmp;
sys/dev/drm/radeon/ni.c
1762
tmp = RREG32(GRBM_STATUS);
sys/dev/drm/radeon/ni.c
1763
if (tmp & (PA_BUSY | SC_BUSY |
sys/dev/drm/radeon/ni.c
1771
if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
sys/dev/drm/radeon/ni.c
1775
if (tmp & GRBM_EE_BUSY)
sys/dev/drm/radeon/ni.c
1779
tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
sys/dev/drm/radeon/ni.c
1780
if (!(tmp & DMA_IDLE))
sys/dev/drm/radeon/ni.c
1784
tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
sys/dev/drm/radeon/ni.c
1785
if (!(tmp & DMA_IDLE))
sys/dev/drm/radeon/ni.c
1789
tmp = RREG32(SRBM_STATUS2);
sys/dev/drm/radeon/ni.c
1790
if (tmp & DMA_BUSY)
sys/dev/drm/radeon/ni.c
1793
if (tmp & DMA1_BUSY)
sys/dev/drm/radeon/ni.c
1797
tmp = RREG32(SRBM_STATUS);
sys/dev/drm/radeon/ni.c
1798
if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
sys/dev/drm/radeon/ni.c
1801
if (tmp & IH_BUSY)
sys/dev/drm/radeon/ni.c
1804
if (tmp & SEM_BUSY)
sys/dev/drm/radeon/ni.c
1807
if (tmp & GRBM_RQ_PENDING)
sys/dev/drm/radeon/ni.c
1810
if (tmp & VMC_BUSY)
sys/dev/drm/radeon/ni.c
1813
if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
sys/dev/drm/radeon/ni.c
1821
tmp = RREG32(VM_L2_STATUS);
sys/dev/drm/radeon/ni.c
1822
if (tmp & L2_BUSY)
sys/dev/drm/radeon/ni.c
1838
u32 tmp;
sys/dev/drm/radeon/ni.c
1860
tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
sys/dev/drm/radeon/ni.c
1861
tmp &= ~DMA_RB_ENABLE;
sys/dev/drm/radeon/ni.c
1862
WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
sys/dev/drm/radeon/ni.c
1867
tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
sys/dev/drm/radeon/ni.c
1868
tmp &= ~DMA_RB_ENABLE;
sys/dev/drm/radeon/ni.c
1869
WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
sys/dev/drm/radeon/ni.c
1930
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/ni.c
1931
tmp |= grbm_soft_reset;
sys/dev/drm/radeon/ni.c
1932
dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/radeon/ni.c
1933
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/drm/radeon/ni.c
1934
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/ni.c
1938
tmp &= ~grbm_soft_reset;
sys/dev/drm/radeon/ni.c
1939
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/drm/radeon/ni.c
1940
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/ni.c
1944
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/ni.c
1945
tmp |= srbm_soft_reset;
sys/dev/drm/radeon/ni.c
1946
dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/radeon/ni.c
1947
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/drm/radeon/ni.c
1948
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/ni.c
1952
tmp &= ~srbm_soft_reset;
sys/dev/drm/radeon/ni.c
1953
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/drm/radeon/ni.c
1954
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/ni.c
2523
u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
sys/dev/drm/radeon/ni.c
2524
tmp <<= 22;
sys/dev/drm/radeon/ni.c
2525
rdev->vm_manager.vram_base_offset = tmp;
sys/dev/drm/radeon/ni.c
910
u32 tmp;
sys/dev/drm/radeon/ni_dpm.c
1082
u32 tmp;
sys/dev/drm/radeon/ni_dpm.c
1086
tmp = RREG32(LB_SYNC_RESET_SEL) & LB_SYNC_RESET_SEL_MASK;
sys/dev/drm/radeon/ni_dpm.c
1087
if (tmp != 1)
sys/dev/drm/radeon/ni_dpm.c
1102
u32 tmp;
sys/dev/drm/radeon/ni_dpm.c
1108
&tmp, pi->sram_end);
sys/dev/drm/radeon/ni_dpm.c
1113
pi->state_table_start = (u16)tmp;
sys/dev/drm/radeon/ni_dpm.c
1118
&tmp, pi->sram_end);
sys/dev/drm/radeon/ni_dpm.c
1123
pi->soft_regs_start = (u16)tmp;
sys/dev/drm/radeon/ni_dpm.c
1128
&tmp, pi->sram_end);
sys/dev/drm/radeon/ni_dpm.c
1133
eg_pi->mc_reg_table_start = (u16)tmp;
sys/dev/drm/radeon/ni_dpm.c
1138
&tmp, pi->sram_end);
sys/dev/drm/radeon/ni_dpm.c
1143
ni_pi->fan_table_start = (u16)tmp;
sys/dev/drm/radeon/ni_dpm.c
1148
&tmp, pi->sram_end);
sys/dev/drm/radeon/ni_dpm.c
1153
ni_pi->arb_table_start = (u16)tmp;
sys/dev/drm/radeon/ni_dpm.c
1158
&tmp, pi->sram_end);
sys/dev/drm/radeon/ni_dpm.c
1163
ni_pi->cac_table_start = (u16)tmp;
sys/dev/drm/radeon/ni_dpm.c
1168
&tmp, pi->sram_end);
sys/dev/drm/radeon/ni_dpm.c
1173
ni_pi->spll_table_start = (u16)tmp;
sys/dev/drm/radeon/ni_dpm.c
1367
u32 tmp = RREG32(CG_CAC_CTRL) & TID_CNT_MASK;
sys/dev/drm/radeon/ni_dpm.c
1372
return tmp * xclk_period;
sys/dev/drm/radeon/ni_dpm.c
1395
u64 tmp, n, d;
sys/dev/drm/radeon/ni_dpm.c
1422
tmp = div64_u64(n, d);
sys/dev/drm/radeon/ni_dpm.c
1424
if (tmp >> 32)
sys/dev/drm/radeon/ni_dpm.c
1426
power_boost_limit = (u32)tmp;
sys/dev/drm/radeon/ni_dpm.c
1573
u32 tmp;
sys/dev/drm/radeon/ni_dpm.c
1577
&tmp, pi->sram_end);
sys/dev/drm/radeon/ni_dpm.c
1581
tmp &= 0x00FFFFFF;
sys/dev/drm/radeon/ni_dpm.c
1582
tmp |= ((u32)MC_CG_ARB_FREQ_F1) << 24;
sys/dev/drm/radeon/ni_dpm.c
1585
tmp, pi->sram_end);
sys/dev/drm/radeon/ni_dpm.c
1597
u32 tmp;
sys/dev/drm/radeon/ni_dpm.c
1601
&tmp, pi->sram_end);
sys/dev/drm/radeon/ni_dpm.c
1605
tmp = (tmp >> 24) & 0xff;
sys/dev/drm/radeon/ni_dpm.c
1607
if (tmp == MC_CG_ARB_FREQ_F0)
sys/dev/drm/radeon/ni_dpm.c
1610
return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
sys/dev/drm/radeon/ni_dpm.c
2009
u64 tmp;
sys/dev/drm/radeon/ni_dpm.c
2023
tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834;
sys/dev/drm/radeon/ni_dpm.c
2024
do_div(tmp, reference_clock);
sys/dev/drm/radeon/ni_dpm.c
2025
fbdiv = (u32) tmp;
sys/dev/drm/radeon/ni_dpm.c
2100
u32 tmp;
sys/dev/drm/radeon/ni_dpm.c
2138
tmp = ((fb_div << SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
sys/dev/drm/radeon/ni_dpm.c
2140
spll_table->freq[i] = cpu_to_be32(tmp);
sys/dev/drm/radeon/ni_dpm.c
2142
tmp = ((clk_v << SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
sys/dev/drm/radeon/ni_dpm.c
2144
spll_table->ss[i] = cpu_to_be32(tmp);
sys/dev/drm/radeon/ni_dpm.c
2321
u32 tmp = RREG32(DC_STUTTER_CNTL);
sys/dev/drm/radeon/ni_dpm.c
2334
(tmp & DC_STUTTER_ENABLE_A) &&
sys/dev/drm/radeon/ni_dpm.c
2335
(tmp & DC_STUTTER_ENABLE_B))
sys/dev/drm/radeon/ni_dpm.c
3442
u32 tmp;
sys/dev/drm/radeon/ni_dpm.c
3444
tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
sys/dev/drm/radeon/ni_dpm.c
3446
if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
sys/dev/drm/radeon/ni_dpm.c
3447
(tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
sys/dev/drm/radeon/ni_dpm.c
3462
u32 tmp, bif;
sys/dev/drm/radeon/ni_dpm.c
3464
tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
sys/dev/drm/radeon/ni_dpm.c
3466
if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
sys/dev/drm/radeon/ni_dpm.c
3467
(tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
sys/dev/drm/radeon/ni_dpm.c
3474
tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
sys/dev/drm/radeon/ni_dpm.c
3475
tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
sys/dev/drm/radeon/ni_dpm.c
3476
tmp |= LC_GEN2_EN_STRAP;
sys/dev/drm/radeon/ni_dpm.c
3478
tmp |= LC_CLR_FAILED_SPD_CHANGE_CNT;
sys/dev/drm/radeon/ni_dpm.c
3479
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/drm/radeon/ni_dpm.c
3481
tmp &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
sys/dev/drm/radeon/ni_dpm.c
3482
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/drm/radeon/ni_dpm.c
3489
tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
sys/dev/drm/radeon/ni_dpm.c
3490
tmp &= ~LC_GEN2_EN_STRAP;
sys/dev/drm/radeon/ni_dpm.c
3492
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/drm/radeon/r100.c
1130
uint32_t tmp;
sys/dev/drm/radeon/r100.c
1179
tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
sys/dev/drm/radeon/r100.c
1183
tmp |= RADEON_BUF_SWAP_32BIT;
sys/dev/drm/radeon/r100.c
1185
WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
sys/dev/drm/radeon/r100.c
1191
WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
sys/dev/drm/radeon/r100.c
1204
tmp |= RADEON_RB_NO_UPDATE;
sys/dev/drm/radeon/r100.c
1208
WREG32(RADEON_CP_RB_CNTL, tmp);
sys/dev/drm/radeon/r100.c
1276
u32 tmp;
sys/dev/drm/radeon/r100.c
1289
tmp = value & 0x003fffff;
sys/dev/drm/radeon/r100.c
1290
tmp += (((u32)reloc->gpu_offset) >> 10);
sys/dev/drm/radeon/r100.c
1304
tmp |= tile_flags;
sys/dev/drm/radeon/r100.c
1305
p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
sys/dev/drm/radeon/r100.c
1307
p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
sys/dev/drm/radeon/r100.c
1568
uint32_t tmp;
sys/dev/drm/radeon/r100.c
159
u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
sys/dev/drm/radeon/r100.c
164
WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
sys/dev/drm/radeon/r100.c
1640
tmp = idx_value & ~(0x7 << 2);
sys/dev/drm/radeon/r100.c
1641
tmp |= tile_flags;
sys/dev/drm/radeon/r100.c
1642
ib[idx] = tmp + ((u32)reloc->gpu_offset);
sys/dev/drm/radeon/r100.c
1721
tmp = idx_value & ~(0x7 << 16);
sys/dev/drm/radeon/r100.c
1722
tmp |= tile_flags;
sys/dev/drm/radeon/r100.c
1723
ib[idx] = tmp;
sys/dev/drm/radeon/r100.c
175
tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
sys/dev/drm/radeon/r100.c
176
WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
sys/dev/drm/radeon/r100.c
1823
tmp = (idx_value >> 23) & 0x7;
sys/dev/drm/radeon/r100.c
1824
if (tmp == 2 || tmp == 6)
sys/dev/drm/radeon/r100.c
1826
tmp = (idx_value >> 27) & 0x7;
sys/dev/drm/radeon/r100.c
1827
if (tmp == 2 || tmp == 6)
sys/dev/drm/radeon/r100.c
1887
tmp = idx_value;
sys/dev/drm/radeon/r100.c
1890
track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
sys/dev/drm/radeon/r100.c
1891
track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
sys/dev/drm/radeon/r100.c
2482
uint32_t tmp;
sys/dev/drm/radeon/r100.c
2485
tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
sys/dev/drm/radeon/r100.c
2486
if (tmp >= n) {
sys/dev/drm/radeon/r100.c
2497
uint32_t tmp;
sys/dev/drm/radeon/r100.c
2503
tmp = RREG32(RADEON_RBBM_STATUS);
sys/dev/drm/radeon/r100.c
2504
if (!(tmp & RADEON_RBBM_ACTIVE)) {
sys/dev/drm/radeon/r100.c
2515
uint32_t tmp;
sys/dev/drm/radeon/r100.c
2519
tmp = RREG32(RADEON_MC_STATUS);
sys/dev/drm/radeon/r100.c
2520
if (tmp & RADEON_MC_IDLE) {
sys/dev/drm/radeon/r100.c
2543
uint32_t tmp;
sys/dev/drm/radeon/r100.c
2545
tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
sys/dev/drm/radeon/r100.c
2546
WREG32(RADEON_BUS_CNTL, tmp);
sys/dev/drm/radeon/r100.c
2551
u32 tmp;
sys/dev/drm/radeon/r100.c
2554
tmp = RREG32(R_000030_BUS_CNTL);
sys/dev/drm/radeon/r100.c
2555
WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
sys/dev/drm/radeon/r100.c
2557
WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
sys/dev/drm/radeon/r100.c
2559
WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
sys/dev/drm/radeon/r100.c
2560
tmp = RREG32(RADEON_BUS_CNTL);
sys/dev/drm/radeon/r100.c
2569
u32 status, tmp;
sys/dev/drm/radeon/r100.c
2581
tmp = RREG32(RADEON_CP_RB_CNTL);
sys/dev/drm/radeon/r100.c
2582
WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
sys/dev/drm/radeon/r100.c
2585
WREG32(RADEON_CP_RB_CNTL, tmp);
sys/dev/drm/radeon/r100.c
2626
u32 tmp;
sys/dev/drm/radeon/r100.c
2700
tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
sys/dev/drm/radeon/r100.c
2701
tmp &= ~RADEON_PM_MODE_SEL;
sys/dev/drm/radeon/r100.c
2702
WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
sys/dev/drm/radeon/r100.c
2711
uint32_t tmp;
sys/dev/drm/radeon/r100.c
2721
tmp = RREG32(RADEON_MEM_CNTL);
sys/dev/drm/radeon/r100.c
2722
if (tmp & RV100_HALF_MODE) {
sys/dev/drm/radeon/r100.c
2732
tmp = RREG32(RADEON_MEM_CNTL);
sys/dev/drm/radeon/r100.c
2733
if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
sys/dev/drm/radeon/r100.c
2880
uint32_t save, tmp;
sys/dev/drm/radeon/r100.c
2883
tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
sys/dev/drm/radeon/r100.c
2884
WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
sys/dev/drm/radeon/r100.c
2885
tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
sys/dev/drm/radeon/r100.c
2987
uint32_t csq_stat, csq2_stat, tmp;
sys/dev/drm/radeon/r100.c
3014
tmp = RREG32(RADEON_CP_CSQ_DATA);
sys/dev/drm/radeon/r100.c
3015
seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
sys/dev/drm/radeon/r100.c
3020
tmp = RREG32(RADEON_CP_CSQ_DATA);
sys/dev/drm/radeon/r100.c
3021
seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
sys/dev/drm/radeon/r100.c
3026
tmp = RREG32(RADEON_CP_CSQ_DATA);
sys/dev/drm/radeon/r100.c
3027
seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
sys/dev/drm/radeon/r100.c
3037
uint32_t tmp;
sys/dev/drm/radeon/r100.c
3039
tmp = RREG32(RADEON_CONFIG_MEMSIZE);
sys/dev/drm/radeon/r100.c
3040
seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
sys/dev/drm/radeon/r100.c
3041
tmp = RREG32(RADEON_MC_FB_LOCATION);
sys/dev/drm/radeon/r100.c
3042
seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
sys/dev/drm/radeon/r100.c
3043
tmp = RREG32(RADEON_BUS_CNTL);
sys/dev/drm/radeon/r100.c
3044
seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
sys/dev/drm/radeon/r100.c
3045
tmp = RREG32(RADEON_MC_AGP_LOCATION);
sys/dev/drm/radeon/r100.c
3046
seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
sys/dev/drm/radeon/r100.c
3047
tmp = RREG32(RADEON_AGP_BASE);
sys/dev/drm/radeon/r100.c
3048
seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
sys/dev/drm/radeon/r100.c
3049
tmp = RREG32(RADEON_HOST_PATH_CNTL);
sys/dev/drm/radeon/r100.c
3050
seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
sys/dev/drm/radeon/r100.c
3051
tmp = RREG32(0x01D0);
sys/dev/drm/radeon/r100.c
3052
seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
sys/dev/drm/radeon/r100.c
3053
tmp = RREG32(RADEON_AIC_LO_ADDR);
sys/dev/drm/radeon/r100.c
3054
seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
sys/dev/drm/radeon/r100.c
3055
tmp = RREG32(RADEON_AIC_HI_ADDR);
sys/dev/drm/radeon/r100.c
3056
seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
sys/dev/drm/radeon/r100.c
3057
tmp = RREG32(0x01E4);
sys/dev/drm/radeon/r100.c
3058
seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
sys/dev/drm/radeon/r100.c
350
u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
sys/dev/drm/radeon/r100.c
354
tmp = RREG32(voltage->gpio.reg);
sys/dev/drm/radeon/r100.c
356
tmp |= voltage->gpio.mask;
sys/dev/drm/radeon/r100.c
358
tmp &= ~(voltage->gpio.mask);
sys/dev/drm/radeon/r100.c
359
WREG32(voltage->gpio.reg, tmp);
sys/dev/drm/radeon/r100.c
363
tmp = RREG32(voltage->gpio.reg);
sys/dev/drm/radeon/r100.c
365
tmp &= ~voltage->gpio.mask;
sys/dev/drm/radeon/r100.c
3664
uint32_t tmp = 0;
sys/dev/drm/radeon/r100.c
367
tmp |= voltage->gpio.mask;
sys/dev/drm/radeon/r100.c
368
WREG32(voltage->gpio.reg, tmp);
sys/dev/drm/radeon/r100.c
3684
tmp = RREG32(scratch);
sys/dev/drm/radeon/r100.c
3685
if (tmp == 0xDEADBEEF) {
sys/dev/drm/radeon/r100.c
3694
scratch, tmp);
sys/dev/drm/radeon/r100.c
3720
uint32_t tmp = 0;
sys/dev/drm/radeon/r100.c
3761
tmp = RREG32(scratch);
sys/dev/drm/radeon/r100.c
3762
if (tmp == 0xDEADBEEF) {
sys/dev/drm/radeon/r100.c
3771
scratch, tmp);
sys/dev/drm/radeon/r100.c
3841
u32 tmp;
sys/dev/drm/radeon/r100.c
3843
tmp = RREG8(R_0003C2_GENMO_WT);
sys/dev/drm/radeon/r100.c
3844
WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
sys/dev/drm/radeon/r100.c
3888
u32 tmp;
sys/dev/drm/radeon/r100.c
3893
tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
sys/dev/drm/radeon/r100.c
3894
tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
sys/dev/drm/radeon/r100.c
3896
tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
sys/dev/drm/radeon/r100.c
3897
WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
sys/dev/drm/radeon/r100.c
4024
u32 tmp;
sys/dev/drm/radeon/r100.c
4026
tmp = RREG32(RADEON_CP_CSQ_CNTL);
sys/dev/drm/radeon/r100.c
4027
if (tmp) {
sys/dev/drm/radeon/r100.c
4030
tmp = RREG32(RADEON_CP_RB_CNTL);
sys/dev/drm/radeon/r100.c
4031
if (tmp) {
sys/dev/drm/radeon/r100.c
4034
tmp = RREG32(RADEON_SCRATCH_UMSK);
sys/dev/drm/radeon/r100.c
4035
if (tmp) {
sys/dev/drm/radeon/r100.c
448
u32 tmp;
sys/dev/drm/radeon/r100.c
455
tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
sys/dev/drm/radeon/r100.c
456
tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
sys/dev/drm/radeon/r100.c
457
WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
sys/dev/drm/radeon/r100.c
459
tmp = RREG32(RADEON_CRTC_GEN_CNTL);
sys/dev/drm/radeon/r100.c
460
tmp |= RADEON_CRTC_DISP_REQ_EN_B;
sys/dev/drm/radeon/r100.c
461
WREG32(RADEON_CRTC_GEN_CNTL, tmp);
sys/dev/drm/radeon/r100.c
479
u32 tmp;
sys/dev/drm/radeon/r100.c
486
tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
sys/dev/drm/radeon/r100.c
487
tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
sys/dev/drm/radeon/r100.c
488
WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
sys/dev/drm/radeon/r100.c
490
tmp = RREG32(RADEON_CRTC_GEN_CNTL);
sys/dev/drm/radeon/r100.c
491
tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
sys/dev/drm/radeon/r100.c
492
WREG32(RADEON_CRTC_GEN_CNTL, tmp);
sys/dev/drm/radeon/r100.c
554
u32 tmp;
sys/dev/drm/radeon/r100.c
559
tmp = RREG32(RADEON_FP_GEN_CNTL);
sys/dev/drm/radeon/r100.c
561
tmp &= ~RADEON_FP_DETECT_INT_POL;
sys/dev/drm/radeon/r100.c
563
tmp |= RADEON_FP_DETECT_INT_POL;
sys/dev/drm/radeon/r100.c
564
WREG32(RADEON_FP_GEN_CNTL, tmp);
sys/dev/drm/radeon/r100.c
567
tmp = RREG32(RADEON_FP2_GEN_CNTL);
sys/dev/drm/radeon/r100.c
569
tmp &= ~RADEON_FP2_DETECT_INT_POL;
sys/dev/drm/radeon/r100.c
571
tmp |= RADEON_FP2_DETECT_INT_POL;
sys/dev/drm/radeon/r100.c
572
WREG32(RADEON_FP2_GEN_CNTL, tmp);
sys/dev/drm/radeon/r100.c
656
uint32_t tmp;
sys/dev/drm/radeon/r100.c
659
tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
sys/dev/drm/radeon/r100.c
660
WREG32(RADEON_AIC_CNTL, tmp);
sys/dev/drm/radeon/r100.c
666
tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
sys/dev/drm/radeon/r100.c
667
WREG32(RADEON_AIC_CNTL, tmp);
sys/dev/drm/radeon/r100.c
678
uint32_t tmp;
sys/dev/drm/radeon/r100.c
681
tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
sys/dev/drm/radeon/r100.c
682
WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
sys/dev/drm/radeon/r100.c
708
uint32_t tmp = 0;
sys/dev/drm/radeon/r100.c
716
tmp |= RADEON_SW_INT_ENABLE;
sys/dev/drm/radeon/r100.c
720
tmp |= RADEON_CRTC_VBLANK_MASK;
sys/dev/drm/radeon/r100.c
724
tmp |= RADEON_CRTC2_VBLANK_MASK;
sys/dev/drm/radeon/r100.c
727
tmp |= RADEON_FP_DETECT_MASK;
sys/dev/drm/radeon/r100.c
730
tmp |= RADEON_FP2_DETECT_MASK;
sys/dev/drm/radeon/r100.c
732
WREG32(RADEON_GEN_INT_CNTL, tmp);
sys/dev/drm/radeon/r100.c
742
u32 tmp;
sys/dev/drm/radeon/r100.c
747
tmp = RREG32(R_000044_GEN_INT_STATUS);
sys/dev/drm/radeon/r100.c
748
WREG32(R_000044_GEN_INT_STATUS, tmp);
sys/dev/drm/radeon/r100.c
964
u32 tmp;
sys/dev/drm/radeon/r100.c
967
tmp = RREG32(R_000E40_RBBM_STATUS);
sys/dev/drm/radeon/r100.c
968
if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
sys/dev/drm/radeon/r200.c
152
uint32_t tmp;
sys/dev/drm/radeon/r200.c
226
tmp = idx_value & ~(0x7 << 2);
sys/dev/drm/radeon/r200.c
227
tmp |= tile_flags;
sys/dev/drm/radeon/r200.c
228
ib[idx] = tmp + ((u32)reloc->gpu_offset);
sys/dev/drm/radeon/r200.c
298
tmp = idx_value & ~(0x7 << 16);
sys/dev/drm/radeon/r200.c
299
tmp |= tile_flags;
sys/dev/drm/radeon/r200.c
300
ib[idx] = tmp;
sys/dev/drm/radeon/r200.c
421
tmp = (idx_value >> 23) & 0x7;
sys/dev/drm/radeon/r200.c
422
if (tmp == 2 || tmp == 6)
sys/dev/drm/radeon/r200.c
424
tmp = (idx_value >> 27) & 0x7;
sys/dev/drm/radeon/r200.c
425
if (tmp == 2 || tmp == 6)
sys/dev/drm/radeon/r200.c
445
tmp = (idx_value >> 16) & 0x3;
sys/dev/drm/radeon/r200.c
447
switch (tmp) {
sys/dev/drm/radeon/r200.c
531
tmp = idx_value;
sys/dev/drm/radeon/r200.c
534
track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
sys/dev/drm/radeon/r200.c
535
track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
sys/dev/drm/radeon/r300.c
1000
if (tmp == 2 || tmp == 4 || tmp == 6) {
sys/dev/drm/radeon/r300.c
1023
tmp = idx_value & 0x3FFF;
sys/dev/drm/radeon/r300.c
1024
track->textures[i].pitch = tmp + 1;
sys/dev/drm/radeon/r300.c
1026
tmp = ((idx_value >> 15) & 1) << 11;
sys/dev/drm/radeon/r300.c
1027
track->textures[i].width_11 = tmp;
sys/dev/drm/radeon/r300.c
1028
tmp = ((idx_value >> 16) & 1) << 11;
sys/dev/drm/radeon/r300.c
1029
track->textures[i].height_11 = tmp;
sys/dev/drm/radeon/r300.c
1061
tmp = idx_value & 0x7FF;
sys/dev/drm/radeon/r300.c
1062
track->textures[i].width = tmp + 1;
sys/dev/drm/radeon/r300.c
1063
tmp = (idx_value >> 11) & 0x7FF;
sys/dev/drm/radeon/r300.c
1064
track->textures[i].height = tmp + 1;
sys/dev/drm/radeon/r300.c
1065
tmp = (idx_value >> 26) & 0xF;
sys/dev/drm/radeon/r300.c
1066
track->textures[i].num_levels = tmp;
sys/dev/drm/radeon/r300.c
1067
tmp = idx_value & (1 << 31);
sys/dev/drm/radeon/r300.c
1068
track->textures[i].use_pitch = !!tmp;
sys/dev/drm/radeon/r300.c
1069
tmp = (idx_value >> 22) & 0xF;
sys/dev/drm/radeon/r300.c
1070
track->textures[i].txdepth = tmp;
sys/dev/drm/radeon/r300.c
1356
u32 tmp;
sys/dev/drm/radeon/r300.c
1361
tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
sys/dev/drm/radeon/r300.c
1362
tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
sys/dev/drm/radeon/r300.c
1364
tmp |= S_00000D_FORCE_VAP(1);
sys/dev/drm/radeon/r300.c
1365
WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
sys/dev/drm/radeon/r300.c
146
uint32_t tmp;
sys/dev/drm/radeon/r300.c
157
tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
sys/dev/drm/radeon/r300.c
158
WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
sys/dev/drm/radeon/r300.c
160
tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
sys/dev/drm/radeon/r300.c
161
WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
sys/dev/drm/radeon/r300.c
171
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
sys/dev/drm/radeon/r300.c
172
tmp |= RADEON_PCIE_TX_GART_EN;
sys/dev/drm/radeon/r300.c
173
tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
sys/dev/drm/radeon/r300.c
174
WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
sys/dev/drm/radeon/r300.c
185
u32 tmp;
sys/dev/drm/radeon/r300.c
191
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
sys/dev/drm/radeon/r300.c
192
tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
sys/dev/drm/radeon/r300.c
193
WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
sys/dev/drm/radeon/r300.c
341
uint32_t tmp;
sys/dev/drm/radeon/r300.c
345
tmp = RREG32(RADEON_MC_STATUS);
sys/dev/drm/radeon/r300.c
346
if (tmp & R300_MC_IDLE) {
sys/dev/drm/radeon/r300.c
356
uint32_t gb_tile_config, tmp;
sys/dev/drm/radeon/r300.c
389
tmp = RREG32(R300_DST_PIPE_CONFIG);
sys/dev/drm/radeon/r300.c
390
WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
sys/dev/drm/radeon/r300.c
409
u32 status, tmp;
sys/dev/drm/radeon/r300.c
421
tmp = RREG32(RADEON_CP_RB_CNTL);
sys/dev/drm/radeon/r300.c
422
WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
sys/dev/drm/radeon/r300.c
425
WREG32(RADEON_CP_RB_CNTL, tmp);
sys/dev/drm/radeon/r300.c
469
u32 tmp;
sys/dev/drm/radeon/r300.c
473
tmp = RREG32(RADEON_MEM_CNTL);
sys/dev/drm/radeon/r300.c
474
tmp &= R300_MEM_NUM_CHANNELS_MASK;
sys/dev/drm/radeon/r300.c
475
switch (tmp) {
sys/dev/drm/radeon/r300.c
588
uint32_t tmp;
sys/dev/drm/radeon/r300.c
590
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
sys/dev/drm/radeon/r300.c
591
seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
sys/dev/drm/radeon/r300.c
592
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
sys/dev/drm/radeon/r300.c
593
seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
sys/dev/drm/radeon/r300.c
594
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
sys/dev/drm/radeon/r300.c
595
seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
sys/dev/drm/radeon/r300.c
596
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
sys/dev/drm/radeon/r300.c
597
seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
sys/dev/drm/radeon/r300.c
598
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
sys/dev/drm/radeon/r300.c
599
seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
sys/dev/drm/radeon/r300.c
600
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
sys/dev/drm/radeon/r300.c
601
seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
sys/dev/drm/radeon/r300.c
602
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
sys/dev/drm/radeon/r300.c
603
seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
sys/dev/drm/radeon/r300.c
628
uint32_t tmp, tile_flags = 0;
sys/dev/drm/radeon/r300.c
720
tmp = idx_value + ((u32)reloc->gpu_offset);
sys/dev/drm/radeon/r300.c
721
tmp |= tile_flags;
sys/dev/drm/radeon/r300.c
722
ib[idx] = tmp;
sys/dev/drm/radeon/r300.c
789
tmp = idx_value & ~(0x7 << 16);
sys/dev/drm/radeon/r300.c
790
tmp |= tile_flags;
sys/dev/drm/radeon/r300.c
791
ib[idx] = tmp;
sys/dev/drm/radeon/r300.c
80
uint32_t tmp;
sys/dev/drm/radeon/r300.c
85
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
sys/dev/drm/radeon/r300.c
86
WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
sys/dev/drm/radeon/r300.c
874
tmp = idx_value & ~(0x7 << 16);
sys/dev/drm/radeon/r300.c
875
tmp |= tile_flags;
sys/dev/drm/radeon/r300.c
876
ib[idx] = tmp;
sys/dev/drm/radeon/r300.c
88
WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
sys/dev/drm/radeon/r300.c
909
tmp = (idx_value >> 25) & 0x3;
sys/dev/drm/radeon/r300.c
910
track->textures[i].tex_coord_type = tmp;
sys/dev/drm/radeon/r300.c
995
tmp = idx_value & 0x7;
sys/dev/drm/radeon/r300.c
996
if (tmp == 2 || tmp == 4 || tmp == 6) {
sys/dev/drm/radeon/r300.c
999
tmp = (idx_value >> 3) & 0x7;
sys/dev/drm/radeon/r420.c
107
tmp = 0;
sys/dev/drm/radeon/r420.c
113
tmp = (0 << 1);
sys/dev/drm/radeon/r420.c
116
tmp = (3 << 1);
sys/dev/drm/radeon/r420.c
119
tmp = (6 << 1);
sys/dev/drm/radeon/r420.c
122
tmp = (7 << 1);
sys/dev/drm/radeon/r420.c
127
tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
sys/dev/drm/radeon/r420.c
128
WREG32(R300_GB_TILE_CONFIG, tmp);
sys/dev/drm/radeon/r420.c
133
tmp = RREG32(R300_DST_PIPE_CONFIG);
sys/dev/drm/radeon/r420.c
134
WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
sys/dev/drm/radeon/r420.c
146
tmp = RREG32(RV530_GB_PIPE_SELECT2);
sys/dev/drm/radeon/r420.c
147
if ((tmp & 3) == 3)
sys/dev/drm/radeon/r420.c
481
uint32_t tmp;
sys/dev/drm/radeon/r420.c
483
tmp = RREG32(R400_GB_PIPE_SELECT);
sys/dev/drm/radeon/r420.c
484
seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
sys/dev/drm/radeon/r420.c
485
tmp = RREG32(R300_GB_TILE_CONFIG);
sys/dev/drm/radeon/r420.c
486
seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
sys/dev/drm/radeon/r420.c
487
tmp = RREG32(R300_DST_PIPE_CONFIG);
sys/dev/drm/radeon/r420.c
488
seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
sys/dev/drm/radeon/r420.c
86
unsigned tmp;
sys/dev/drm/radeon/r520.c
100
switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
sys/dev/drm/radeon/r520.c
117
if (tmp & R520_MC_CHANNEL_SIZE)
sys/dev/drm/radeon/r520.c
39
uint32_t tmp;
sys/dev/drm/radeon/r520.c
43
tmp = RREG32_MC(R520_MC_STATUS);
sys/dev/drm/radeon/r520.c
44
if (tmp & R520_MC_STATUS_IDLE) {
sys/dev/drm/radeon/r520.c
54
unsigned pipe_select_current, gb_pipe_select, tmp;
sys/dev/drm/radeon/r520.c
83
tmp = RREG32(R300_DST_PIPE_CONFIG);
sys/dev/drm/radeon/r520.c
84
pipe_select_current = (tmp >> 2) & 3;
sys/dev/drm/radeon/r520.c
85
tmp = (1 << pipe_select_current) |
sys/dev/drm/radeon/r520.c
87
WREG32_PLL(0x000D, tmp);
sys/dev/drm/radeon/r520.c
95
uint32_t tmp;
sys/dev/drm/radeon/r520.c
99
tmp = RREG32_MC(R520_MC_CNTL0);
sys/dev/drm/radeon/r600.c
1067
u32 tmp;
sys/dev/drm/radeon/r600.c
1073
u32 tmp;
sys/dev/drm/radeon/r600.c
1081
tmp = readl((void __iomem *)ptr);
sys/dev/drm/radeon/r600.c
1090
tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
sys/dev/drm/radeon/r600.c
1091
tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
sys/dev/drm/radeon/r600.c
1092
if (tmp == 2) {
sys/dev/drm/radeon/r600.c
1096
if (tmp) {
sys/dev/drm/radeon/r600.c
1121
u32 tmp;
sys/dev/drm/radeon/r600.c
1139
tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
sys/dev/drm/radeon/r600.c
1143
WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1144
WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1145
WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
sys/dev/drm/radeon/r600.c
1146
WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1147
WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1148
WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1149
WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1150
WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1151
WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1152
WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1153
WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1154
WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1155
WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1156
WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1157
WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
sys/dev/drm/radeon/r600.c
1158
WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
sys/dev/drm/radeon/r600.c
1179
u32 tmp;
sys/dev/drm/radeon/r600.c
1191
tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
sys/dev/drm/radeon/r600.c
1193
WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1194
WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1195
WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1196
WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1197
WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1198
WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1199
WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1200
WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1201
WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1202
WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1203
WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1204
WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1205
WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1206
WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1207
WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1208
WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1221
u32 tmp;
sys/dev/drm/radeon/r600.c
1231
tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
sys/dev/drm/radeon/r600.c
1235
WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1236
WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1237
WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
sys/dev/drm/radeon/r600.c
1238
WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1239
WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1240
WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1241
WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1242
WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1243
WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1244
WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1245
WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1246
WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1247
WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
sys/dev/drm/radeon/r600.c
1248
WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
sys/dev/drm/radeon/r600.c
1256
u32 tmp;
sys/dev/drm/radeon/r600.c
1260
tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
sys/dev/drm/radeon/r600.c
1261
if (!tmp)
sys/dev/drm/radeon/r600.c
1296
u32 tmp;
sys/dev/drm/radeon/r600.c
1335
tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
sys/dev/drm/radeon/r600.c
1336
tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
sys/dev/drm/radeon/r600.c
1337
WREG32(MC_VM_FB_LOCATION, tmp);
sys/dev/drm/radeon/r600.c
1426
u32 tmp;
sys/dev/drm/radeon/r600.c
1433
tmp = RREG32(RAMCFG);
sys/dev/drm/radeon/r600.c
1434
if (tmp & CHANSIZE_OVERRIDE) {
sys/dev/drm/radeon/r600.c
1436
} else if (tmp & CHANSIZE_MASK) {
sys/dev/drm/radeon/r600.c
1441
tmp = RREG32(CHMAP);
sys/dev/drm/radeon/r600.c
1442
switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
sys/dev/drm/radeon/r600.c
1547
u32 tmp = RREG32(R600_BIOS_3_SCRATCH);
sys/dev/drm/radeon/r600.c
1550
tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
sys/dev/drm/radeon/r600.c
1552
tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
sys/dev/drm/radeon/r600.c
1554
WREG32(R600_BIOS_3_SCRATCH, tmp);
sys/dev/drm/radeon/r600.c
1581
u32 i, j, tmp;
sys/dev/drm/radeon/r600.c
1593
tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/drm/radeon/r600.c
1594
if (tmp != crtc_status[i])
sys/dev/drm/radeon/r600.c
1609
u32 tmp;
sys/dev/drm/radeon/r600.c
1612
tmp = RREG32(R_008010_GRBM_STATUS);
sys/dev/drm/radeon/r600.c
1614
if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
sys/dev/drm/radeon/r600.c
1615
G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
sys/dev/drm/radeon/r600.c
1616
G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
sys/dev/drm/radeon/r600.c
1617
G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
sys/dev/drm/radeon/r600.c
1618
G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
sys/dev/drm/radeon/r600.c
1621
if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
sys/dev/drm/radeon/r600.c
1622
G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
sys/dev/drm/radeon/r600.c
1623
G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
sys/dev/drm/radeon/r600.c
1624
G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
sys/dev/drm/radeon/r600.c
1625
G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
sys/dev/drm/radeon/r600.c
1629
if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) |
sys/dev/drm/radeon/r600.c
1630
G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp))
sys/dev/drm/radeon/r600.c
1633
if (G_008010_GRBM_EE_BUSY(tmp))
sys/dev/drm/radeon/r600.c
1637
tmp = RREG32(DMA_STATUS_REG);
sys/dev/drm/radeon/r600.c
1638
if (!(tmp & DMA_IDLE))
sys/dev/drm/radeon/r600.c
1642
tmp = RREG32(R_000E50_SRBM_STATUS);
sys/dev/drm/radeon/r600.c
1643
if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp))
sys/dev/drm/radeon/r600.c
1646
if (G_000E50_IH_BUSY(tmp))
sys/dev/drm/radeon/r600.c
1649
if (G_000E50_SEM_BUSY(tmp))
sys/dev/drm/radeon/r600.c
1652
if (G_000E50_GRBM_RQ_PENDING(tmp))
sys/dev/drm/radeon/r600.c
1655
if (G_000E50_VMC_BUSY(tmp))
sys/dev/drm/radeon/r600.c
1658
if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) |
sys/dev/drm/radeon/r600.c
1659
G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) |
sys/dev/drm/radeon/r600.c
1660
G_000E50_MCDW_BUSY(tmp))
sys/dev/drm/radeon/r600.c
1679
u32 tmp;
sys/dev/drm/radeon/r600.c
1699
tmp = RREG32(DMA_RB_CNTL);
sys/dev/drm/radeon/r600.c
1700
tmp &= ~DMA_RB_ENABLE;
sys/dev/drm/radeon/r600.c
1701
WREG32(DMA_RB_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1775
tmp = RREG32(R_008020_GRBM_SOFT_RESET);
sys/dev/drm/radeon/r600.c
1776
tmp |= grbm_soft_reset;
sys/dev/drm/radeon/r600.c
1777
dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/radeon/r600.c
1778
WREG32(R_008020_GRBM_SOFT_RESET, tmp);
sys/dev/drm/radeon/r600.c
1779
tmp = RREG32(R_008020_GRBM_SOFT_RESET);
sys/dev/drm/radeon/r600.c
1783
tmp &= ~grbm_soft_reset;
sys/dev/drm/radeon/r600.c
1784
WREG32(R_008020_GRBM_SOFT_RESET, tmp);
sys/dev/drm/radeon/r600.c
1785
tmp = RREG32(R_008020_GRBM_SOFT_RESET);
sys/dev/drm/radeon/r600.c
1789
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/r600.c
1790
tmp |= srbm_soft_reset;
sys/dev/drm/radeon/r600.c
1791
dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/radeon/r600.c
1792
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/drm/radeon/r600.c
1793
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/r600.c
1797
tmp &= ~srbm_soft_reset;
sys/dev/drm/radeon/r600.c
1798
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/drm/radeon/r600.c
1799
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/r600.c
1814
u32 tmp, i;
sys/dev/drm/radeon/r600.c
1830
tmp = RREG32(DMA_RB_CNTL);
sys/dev/drm/radeon/r600.c
1831
tmp &= ~DMA_RB_ENABLE;
sys/dev/drm/radeon/r600.c
1832
WREG32(DMA_RB_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1848
tmp = RREG32(BUS_CNTL);
sys/dev/drm/radeon/r600.c
1849
tmp |= VGA_COHE_SPEC_TIMER_DIS;
sys/dev/drm/radeon/r600.c
1850
WREG32(BUS_CNTL, tmp);
sys/dev/drm/radeon/r600.c
1852
tmp = RREG32(BIF_SCRATCH0);
sys/dev/drm/radeon/r600.c
1859
tmp = SOFT_RESET_BIF;
sys/dev/drm/radeon/r600.c
1860
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/drm/radeon/r600.c
1932
u32 pipe_rb_ratio, pipe_rb_remain, tmp;
sys/dev/drm/radeon/r600.c
1937
tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
sys/dev/drm/radeon/r600.c
1939
if ((tmp & 0xff) != 0xff)
sys/dev/drm/radeon/r600.c
1940
disabled_rb_mask = tmp;
sys/dev/drm/radeon/r600.c
1985
u32 tmp;
sys/dev/drm/radeon/r600.c
2100
tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
sys/dev/drm/radeon/r600.c
2101
if (tmp > 3) {
sys/dev/drm/radeon/r600.c
2105
tiling_config |= ROW_TILING(tmp);
sys/dev/drm/radeon/r600.c
2106
tiling_config |= SAMPLE_SPLIT(tmp);
sys/dev/drm/radeon/r600.c
2111
tmp = rdev->config.r600.max_simds -
sys/dev/drm/radeon/r600.c
2113
rdev->config.r600.active_simds = tmp;
sys/dev/drm/radeon/r600.c
2116
tmp = 0;
sys/dev/drm/radeon/r600.c
2118
tmp |= (1 << i);
sys/dev/drm/radeon/r600.c
2120
if ((disabled_rb_mask & tmp) == tmp) {
sys/dev/drm/radeon/r600.c
2124
tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
sys/dev/drm/radeon/r600.c
2125
tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
sys/dev/drm/radeon/r600.c
2127
tiling_config |= tmp << 16;
sys/dev/drm/radeon/r600.c
2128
rdev->config.r600.backend_map = tmp;
sys/dev/drm/radeon/r600.c
2136
tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
sys/dev/drm/radeon/r600.c
2137
WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
sys/dev/drm/radeon/r600.c
2138
WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
sys/dev/drm/radeon/r600.c
2150
tmp = RREG32(SX_DEBUG_1);
sys/dev/drm/radeon/r600.c
2151
tmp |= SMX_EVENT_RELEASE;
sys/dev/drm/radeon/r600.c
2153
tmp |= ENABLE_NEW_SMX_ADDRESS;
sys/dev/drm/radeon/r600.c
2154
WREG32(SX_DEBUG_1, tmp);
sys/dev/drm/radeon/r600.c
2175
tmp = RREG32(SQ_MS_FIFO_SIZES);
sys/dev/drm/radeon/r600.c
2180
tmp = (CACHE_FIFO_SIZE(0xa) |
sys/dev/drm/radeon/r600.c
2186
tmp &= ~DONE_FIFO_HIWATER(0xff);
sys/dev/drm/radeon/r600.c
2187
tmp |= DONE_FIFO_HIWATER(0x4);
sys/dev/drm/radeon/r600.c
2189
WREG32(SQ_MS_FIFO_SIZES, tmp);
sys/dev/drm/radeon/r600.c
2304
tmp = rdev->config.r600.max_pipes * 16;
sys/dev/drm/radeon/r600.c
2310
tmp += 32;
sys/dev/drm/radeon/r600.c
2313
tmp += 128;
sys/dev/drm/radeon/r600.c
2318
if (tmp > 256) {
sys/dev/drm/radeon/r600.c
2319
tmp = 256;
sys/dev/drm/radeon/r600.c
2322
WREG32(VGT_GS_PER_ES, tmp);
sys/dev/drm/radeon/r600.c
2353
tmp = TC_L2_SIZE(8);
sys/dev/drm/radeon/r600.c
2357
tmp = TC_L2_SIZE(4);
sys/dev/drm/radeon/r600.c
2360
tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
sys/dev/drm/radeon/r600.c
2363
tmp = TC_L2_SIZE(0);
sys/dev/drm/radeon/r600.c
2366
WREG32(TC_CNTL, tmp);
sys/dev/drm/radeon/r600.c
2368
tmp = RREG32(HDP_HOST_PATH_CNTL);
sys/dev/drm/radeon/r600.c
2369
WREG32(HDP_HOST_PATH_CNTL, tmp);
sys/dev/drm/radeon/r600.c
2371
tmp = RREG32(ARB_POP);
sys/dev/drm/radeon/r600.c
2372
tmp |= ENABLE_TC128;
sys/dev/drm/radeon/r600.c
2373
WREG32(ARB_POP, tmp);
sys/dev/drm/radeon/r600.c
2728
u32 tmp;
sys/dev/drm/radeon/r600.c
2740
tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
sys/dev/drm/radeon/r600.c
2742
tmp |= BUF_SWAP_32BIT;
sys/dev/drm/radeon/r600.c
2744
WREG32(CP_RB_CNTL, tmp);
sys/dev/drm/radeon/r600.c
2751
WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
sys/dev/drm/radeon/r600.c
2765
tmp |= RB_NO_UPDATE;
sys/dev/drm/radeon/r600.c
2770
WREG32(CP_RB_CNTL, tmp);
sys/dev/drm/radeon/r600.c
2835
uint32_t tmp = 0;
sys/dev/drm/radeon/r600.c
2856
tmp = RREG32(scratch);
sys/dev/drm/radeon/r600.c
2857
if (tmp == 0xDEADBEEF)
sys/dev/drm/radeon/r600.c
2865
ring->idx, scratch, tmp);
sys/dev/drm/radeon/r600.c
294
u32 tmp = 0;
sys/dev/drm/radeon/r600.c
2982
u32 size_in_bytes, cur_size_in_bytes, tmp;
sys/dev/drm/radeon/r600.c
3008
tmp = upper_32_bits(src_offset) & 0xff;
sys/dev/drm/radeon/r600.c
3010
tmp |= PACKET3_CP_DMA_CP_SYNC;
sys/dev/drm/radeon/r600.c
3013
radeon_ring_write(ring, tmp);
sys/dev/drm/radeon/r600.c
319
tmp |= FMT_SPATIAL_DITHER_EN;
sys/dev/drm/radeon/r600.c
321
tmp |= FMT_TRUNCATE_EN;
sys/dev/drm/radeon/r600.c
326
tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH);
sys/dev/drm/radeon/r600.c
328
tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH);
sys/dev/drm/radeon/r600.c
336
WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/drm/radeon/r600.c
3414
uint32_t tmp = 0;
sys/dev/drm/radeon/r600.c
3450
tmp = RREG32(scratch);
sys/dev/drm/radeon/r600.c
3451
if (tmp == 0xDEADBEEF)
sys/dev/drm/radeon/r600.c
3459
scratch, tmp);
sys/dev/drm/radeon/r600.c
3634
u32 tmp;
sys/dev/drm/radeon/r600.c
3637
tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
sys/dev/drm/radeon/r600.c
3638
WREG32(DMA_CNTL, tmp);
sys/dev/drm/radeon/r600.c
3646
tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
3647
WREG32(DC_HPD1_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
3648
tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
3649
WREG32(DC_HPD2_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
3650
tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
3651
WREG32(DC_HPD3_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
3652
tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
3653
WREG32(DC_HPD4_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
3655
tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
3656
WREG32(DC_HPD5_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
3657
tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
3658
WREG32(DC_HPD6_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
3659
tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/drm/radeon/r600.c
3660
WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
sys/dev/drm/radeon/r600.c
3661
tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/drm/radeon/r600.c
3662
WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
sys/dev/drm/radeon/r600.c
3664
tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/drm/radeon/r600.c
3665
WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
3666
tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/drm/radeon/r600.c
3667
WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
3672
tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
3673
WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
3674
tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
3675
WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
3676
tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
3677
WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
3678
tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/drm/radeon/r600.c
3679
WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
3680
tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/drm/radeon/r600.c
3681
WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
3928
u32 tmp;
sys/dev/drm/radeon/r600.c
3965
tmp = RREG32(DC_HPD1_INT_CONTROL);
sys/dev/drm/radeon/r600.c
3966
tmp |= DC_HPDx_INT_ACK;
sys/dev/drm/radeon/r600.c
3967
WREG32(DC_HPD1_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
3969
tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
sys/dev/drm/radeon/r600.c
3970
tmp |= DC_HPDx_INT_ACK;
sys/dev/drm/radeon/r600.c
3971
WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
3976
tmp = RREG32(DC_HPD2_INT_CONTROL);
sys/dev/drm/radeon/r600.c
3977
tmp |= DC_HPDx_INT_ACK;
sys/dev/drm/radeon/r600.c
3978
WREG32(DC_HPD2_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
3980
tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
sys/dev/drm/radeon/r600.c
3981
tmp |= DC_HPDx_INT_ACK;
sys/dev/drm/radeon/r600.c
3982
WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
3987
tmp = RREG32(DC_HPD3_INT_CONTROL);
sys/dev/drm/radeon/r600.c
3988
tmp |= DC_HPDx_INT_ACK;
sys/dev/drm/radeon/r600.c
3989
WREG32(DC_HPD3_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
3991
tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
sys/dev/drm/radeon/r600.c
3992
tmp |= DC_HPDx_INT_ACK;
sys/dev/drm/radeon/r600.c
3993
WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
3997
tmp = RREG32(DC_HPD4_INT_CONTROL);
sys/dev/drm/radeon/r600.c
3998
tmp |= DC_HPDx_INT_ACK;
sys/dev/drm/radeon/r600.c
3999
WREG32(DC_HPD4_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
4003
tmp = RREG32(DC_HPD5_INT_CONTROL);
sys/dev/drm/radeon/r600.c
4004
tmp |= DC_HPDx_INT_ACK;
sys/dev/drm/radeon/r600.c
4005
WREG32(DC_HPD5_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
4008
tmp = RREG32(DC_HPD6_INT_CONTROL);
sys/dev/drm/radeon/r600.c
4009
tmp |= DC_HPDx_INT_ACK;
sys/dev/drm/radeon/r600.c
4010
WREG32(DC_HPD6_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
4013
tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
sys/dev/drm/radeon/r600.c
4014
tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
sys/dev/drm/radeon/r600.c
4015
WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
sys/dev/drm/radeon/r600.c
4018
tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
sys/dev/drm/radeon/r600.c
4019
tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
sys/dev/drm/radeon/r600.c
4020
WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
sys/dev/drm/radeon/r600.c
4024
tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
sys/dev/drm/radeon/r600.c
4025
tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
sys/dev/drm/radeon/r600.c
4026
WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
4030
tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
sys/dev/drm/radeon/r600.c
4031
tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
sys/dev/drm/radeon/r600.c
4032
WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
4034
tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
sys/dev/drm/radeon/r600.c
4035
tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
sys/dev/drm/radeon/r600.c
4036
WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
4053
u32 wptr, tmp;
sys/dev/drm/radeon/r600.c
4069
tmp = RREG32(IH_RB_CNTL);
sys/dev/drm/radeon/r600.c
4070
tmp |= IH_WPTR_OVERFLOW_CLEAR;
sys/dev/drm/radeon/r600.c
4071
WREG32(IH_RB_CNTL, tmp);
sys/dev/drm/radeon/r600.c
4404
u32 tmp;
sys/dev/drm/radeon/r600.c
4407
tmp = readl((void __iomem *)ptr);
sys/dev/drm/radeon/r600.c
4504
u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
sys/dev/drm/radeon/r600.c
4580
tmp = RREG32(0x541c);
sys/dev/drm/radeon/r600.c
4581
WREG32(0x541c, tmp | 0x8);
sys/dev/drm/radeon/r600.c
852
u32 tmp;
sys/dev/drm/radeon/r600.c
858
tmp = RREG32(DC_HPD1_INT_CONTROL);
sys/dev/drm/radeon/r600.c
860
tmp &= ~DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
862
tmp |= DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
863
WREG32(DC_HPD1_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
866
tmp = RREG32(DC_HPD2_INT_CONTROL);
sys/dev/drm/radeon/r600.c
868
tmp &= ~DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
870
tmp |= DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
871
WREG32(DC_HPD2_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
874
tmp = RREG32(DC_HPD3_INT_CONTROL);
sys/dev/drm/radeon/r600.c
876
tmp &= ~DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
878
tmp |= DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
879
WREG32(DC_HPD3_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
882
tmp = RREG32(DC_HPD4_INT_CONTROL);
sys/dev/drm/radeon/r600.c
884
tmp &= ~DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
886
tmp |= DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
887
WREG32(DC_HPD4_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
890
tmp = RREG32(DC_HPD5_INT_CONTROL);
sys/dev/drm/radeon/r600.c
892
tmp &= ~DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
894
tmp |= DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
895
WREG32(DC_HPD5_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
899
tmp = RREG32(DC_HPD6_INT_CONTROL);
sys/dev/drm/radeon/r600.c
901
tmp &= ~DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
903
tmp |= DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
904
WREG32(DC_HPD6_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
912
tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
sys/dev/drm/radeon/r600.c
914
tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
916
tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
917
WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
920
tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
sys/dev/drm/radeon/r600.c
922
tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
924
tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
925
WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
928
tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
sys/dev/drm/radeon/r600.c
930
tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
932
tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
933
WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
959
u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
sys/dev/drm/radeon/r600.c
961
tmp |= DC_HPDx_EN;
sys/dev/drm/radeon/r600.c
965
WREG32(DC_HPD1_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
968
WREG32(DC_HPD2_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
971
WREG32(DC_HPD3_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
974
WREG32(DC_HPD4_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
978
WREG32(DC_HPD5_CONTROL, tmp);
sys/dev/drm/radeon/r600.c
981
WREG32(DC_HPD6_CONTROL, tmp);
sys/dev/drm/radeon/r600_cs.c
1083
tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
sys/dev/drm/radeon/r600_cs.c
1084
track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
sys/dev/drm/radeon/r600_cs.c
1086
track->vgt_strmout_bo[tmp] = reloc->robj;
sys/dev/drm/radeon/r600_cs.c
1087
track->vgt_strmout_bo_mc[tmp] = reloc->gpu_offset;
sys/dev/drm/radeon/r600_cs.c
1094
tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
sys/dev/drm/radeon/r600_cs.c
1096
track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
sys/dev/drm/radeon/r600_cs.c
1116
tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
sys/dev/drm/radeon/r600_cs.c
1117
track->log_nsamples = tmp;
sys/dev/drm/radeon/r600_cs.c
1118
track->nsamples = 1 << tmp;
sys/dev/drm/radeon/r600_cs.c
1122
tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx));
sys/dev/drm/radeon/r600_cs.c
1123
track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX;
sys/dev/drm/radeon/r600_cs.c
1141
tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
sys/dev/drm/radeon/r600_cs.c
1142
track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
sys/dev/drm/radeon/r600_cs.c
1145
track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
sys/dev/drm/radeon/r600_cs.c
1148
track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
sys/dev/drm/radeon/r600_cs.c
1151
tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
sys/dev/drm/radeon/r600_cs.c
1152
track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
sys/dev/drm/radeon/r600_cs.c
1164
tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4;
sys/dev/drm/radeon/r600_cs.c
1165
track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
sys/dev/drm/radeon/r600_cs.c
1176
tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
sys/dev/drm/radeon/r600_cs.c
1177
track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
sys/dev/drm/radeon/r600_cs.c
1178
track->cb_color_size_idx[tmp] = idx;
sys/dev/drm/radeon/r600_cs.c
1198
tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
sys/dev/drm/radeon/r600_cs.c
1200
if (!track->cb_color_base_last[tmp]) {
sys/dev/drm/radeon/r600_cs.c
1204
track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
sys/dev/drm/radeon/r600_cs.c
1205
track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp];
sys/dev/drm/radeon/r600_cs.c
1206
ib[idx] = track->cb_color_base_last[tmp];
sys/dev/drm/radeon/r600_cs.c
1213
track->cb_color_frag_bo[tmp] = reloc->robj;
sys/dev/drm/radeon/r600_cs.c
1214
track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8;
sys/dev/drm/radeon/r600_cs.c
1217
if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
sys/dev/drm/radeon/r600_cs.c
1229
tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
sys/dev/drm/radeon/r600_cs.c
1231
if (!track->cb_color_base_last[tmp]) {
sys/dev/drm/radeon/r600_cs.c
1235
track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
sys/dev/drm/radeon/r600_cs.c
1236
track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp];
sys/dev/drm/radeon/r600_cs.c
1237
ib[idx] = track->cb_color_base_last[tmp];
sys/dev/drm/radeon/r600_cs.c
1244
track->cb_color_tile_bo[tmp] = reloc->robj;
sys/dev/drm/radeon/r600_cs.c
1245
track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8;
sys/dev/drm/radeon/r600_cs.c
1248
if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
sys/dev/drm/radeon/r600_cs.c
1260
tmp = (reg - R_028100_CB_COLOR0_MASK) / 4;
sys/dev/drm/radeon/r600_cs.c
1261
track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx);
sys/dev/drm/radeon/r600_cs.c
1262
if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
sys/dev/drm/radeon/r600_cs.c
1280
tmp = (reg - CB_COLOR0_BASE) / 4;
sys/dev/drm/radeon/r600_cs.c
1281
track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
sys/dev/drm/radeon/r600_cs.c
1283
track->cb_color_base_last[tmp] = ib[idx];
sys/dev/drm/radeon/r600_cs.c
1284
track->cb_color_bo[tmp] = reloc->robj;
sys/dev/drm/radeon/r600_cs.c
1285
track->cb_color_bo_mc[tmp] = reloc->gpu_offset;
sys/dev/drm/radeon/r600_cs.c
1647
int tmp;
sys/dev/drm/radeon/r600_cs.c
1655
tmp = radeon_get_ib_value(p, idx + 1);
sys/dev/drm/radeon/r600_cs.c
1656
pred_op = (tmp >> 16) & 0x7;
sys/dev/drm/radeon/r600_cs.c
1675
((u64)(tmp & 0xff) << 32);
sys/dev/drm/radeon/r600_cs.c
1678
ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
sys/dev/drm/radeon/r600_cs.c
1780
u64 offset, tmp;
sys/dev/drm/radeon/r600_cs.c
1803
tmp = radeon_get_ib_value(p, idx) +
sys/dev/drm/radeon/r600_cs.c
1806
offset = reloc->gpu_offset + tmp;
sys/dev/drm/radeon/r600_cs.c
1808
if ((tmp + size) > radeon_bo_size(reloc->robj)) {
sys/dev/drm/radeon/r600_cs.c
1810
tmp + size, radeon_bo_size(reloc->robj));
sys/dev/drm/radeon/r600_cs.c
1833
tmp = radeon_get_ib_value(p, idx+2) +
sys/dev/drm/radeon/r600_cs.c
1836
offset = reloc->gpu_offset + tmp;
sys/dev/drm/radeon/r600_cs.c
1838
if ((tmp + size) > radeon_bo_size(reloc->robj)) {
sys/dev/drm/radeon/r600_cs.c
1840
tmp + size, radeon_bo_size(reloc->robj));
sys/dev/drm/radeon/r600_cs.c
353
u32 slice_tile_max, size, tmp;
sys/dev/drm/radeon/r600_cs.c
430
tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) *
sys/dev/drm/radeon/r600_cs.c
436
tmp += track->cb_color_view[i] & 0xFF;
sys/dev/drm/radeon/r600_cs.c
440
tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp;
sys/dev/drm/radeon/r600_cs.c
443
if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
sys/dev/drm/radeon/r600_cs.c
454
track->cb_color_bo_offset[i], tmp,
sys/dev/drm/radeon/r600_cs.c
463
tmp = (height * pitch) >> 6;
sys/dev/drm/radeon/r600_cs.c
464
if (tmp < slice_tile_max)
sys/dev/drm/radeon/r600_cs.c
465
slice_tile_max = tmp;
sys/dev/drm/radeon/r600_cs.c
466
tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
sys/dev/drm/radeon/r600_cs.c
468
ib[track->cb_color_size_idx[i]] = tmp;
sys/dev/drm/radeon/r600_cs.c
520
u32 nviews, bpe, ntiles, size, slice_tile_max, tmp;
sys/dev/drm/radeon/r600_cs.c
557
tmp = radeon_bo_size(track->db_bo) - track->db_offset;
sys/dev/drm/radeon/r600_cs.c
558
tmp = (tmp / bpe) >> 6;
sys/dev/drm/radeon/r600_cs.c
559
if (!tmp) {
sys/dev/drm/radeon/r600_cs.c
565
ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
sys/dev/drm/radeon/r600_cs.c
622
tmp = ntiles * bpe * 64 * nviews * track->nsamples;
sys/dev/drm/radeon/r600_cs.c
623
if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
sys/dev/drm/radeon/r600_cs.c
626
track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
sys/dev/drm/radeon/r600_cs.c
709
u32 tmp;
sys/dev/drm/radeon/r600_cs.c
745
tmp = track->cb_target_mask;
sys/dev/drm/radeon/r600_cs.c
749
tmp |= 0xff;
sys/dev/drm/radeon/r600_cs.c
756
(tmp >> (i * 4)) & 0xF) {
sys/dev/drm/radeon/r600_cs.c
973
u32 m, i, tmp, *ib;
sys/dev/drm/radeon/r600_dma.c
234
u32 tmp;
sys/dev/drm/radeon/r600_dma.c
244
tmp = 0xCAFEDEAD;
sys/dev/drm/radeon/r600_dma.c
245
rdev->wb.wb[index/4] = cpu_to_le32(tmp);
sys/dev/drm/radeon/r600_dma.c
259
tmp = le32_to_cpu(rdev->wb.wb[index/4]);
sys/dev/drm/radeon/r600_dma.c
260
if (tmp == 0xDEADBEEF)
sys/dev/drm/radeon/r600_dma.c
269
ring->idx, tmp);
sys/dev/drm/radeon/r600_dma.c
341
u32 tmp = 0;
sys/dev/drm/radeon/r600_dma.c
380
tmp = le32_to_cpu(rdev->wb.wb[index/4]);
sys/dev/drm/radeon/r600_dma.c
381
if (tmp == 0xDEADBEEF)
sys/dev/drm/radeon/r600_dma.c
388
DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
sys/dev/drm/radeon/r600_dpm.c
208
u32 tmp;
sys/dev/drm/radeon/r600_dpm.c
211
tmp = i_c >> p_b;
sys/dev/drm/radeon/r600_dpm.c
213
while (tmp) {
sys/dev/drm/radeon/r600_dpm.c
215
tmp >>= 1;
sys/dev/drm/radeon/r600_dpm.c
533
u32 tmp, mask;
sys/dev/drm/radeon/r600_dpm.c
539
tmp = RREG32(VID_UPPER_GPIO_CNTL);
sys/dev/drm/radeon/r600_dpm.c
540
tmp = (tmp & ~mask) | ((pins >> (32 - (3 * ix))) & mask);
sys/dev/drm/radeon/r600_dpm.c
541
WREG32(VID_UPPER_GPIO_CNTL, tmp);
sys/dev/drm/radeon/r600_dpm.c
607
u32 tmp = 0;
sys/dev/drm/radeon/r600_dpm.c
610
tmp = CTXSW_FREQ_DISPLAY_WATERMARK;
sys/dev/drm/radeon/r600_dpm.c
611
WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), tmp, ~CTXSW_FREQ_DISPLAY_WATERMARK);
sys/dev/drm/radeon/r600_dpm.c
618
u32 tmp = 0;
sys/dev/drm/radeon/r600_dpm.c
621
tmp = CTXSW_FREQ_GEN2PCIE_VOLT;
sys/dev/drm/radeon/r600_dpm.c
622
WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), tmp, ~CTXSW_FREQ_GEN2PCIE_VOLT);
sys/dev/drm/radeon/r600_dpm.c
627
u32 tmp;
sys/dev/drm/radeon/r600_dpm.c
629
tmp = RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK;
sys/dev/drm/radeon/r600_dpm.c
630
tmp >>= CURRENT_PROFILE_INDEX_SHIFT;
sys/dev/drm/radeon/r600_dpm.c
631
return tmp;
sys/dev/drm/radeon/r600_dpm.c
636
u32 tmp;
sys/dev/drm/radeon/r600_dpm.c
638
tmp = RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_PROFILE_INDEX_MASK;
sys/dev/drm/radeon/r600_dpm.c
639
tmp >>= TARGET_PROFILE_INDEX_SHIFT;
sys/dev/drm/radeon/r600_dpm.c
640
return tmp;
sys/dev/drm/radeon/r600_hdmi.c
145
u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
sys/dev/drm/radeon/r600_hdmi.c
151
tmp |= AUDIO_ENABLED;
sys/dev/drm/radeon/r600_hdmi.c
153
tmp |= PIN0_AUDIO_ENABLED;
sys/dev/drm/radeon/r600_hdmi.c
155
tmp |= PIN1_AUDIO_ENABLED;
sys/dev/drm/radeon/r600_hdmi.c
157
tmp |= PIN2_AUDIO_ENABLED;
sys/dev/drm/radeon/r600_hdmi.c
159
tmp |= PIN3_AUDIO_ENABLED;
sys/dev/drm/radeon/r600_hdmi.c
161
tmp &= ~(AUDIO_ENABLED |
sys/dev/drm/radeon/r600_hdmi.c
168
WREG32(AZ_HOT_PLUG_CONTROL, tmp);
sys/dev/drm/radeon/radeon_acpi.c
720
struct drm_encoder *tmp;
sys/dev/drm/radeon/radeon_acpi.c
724
list_for_each_entry(tmp, &rdev->ddev->mode_config.encoder_list,
sys/dev/drm/radeon/radeon_acpi.c
726
struct radeon_encoder *enc = to_radeon_encoder(tmp);
sys/dev/drm/radeon/radeon_atombios.c
3053
u32 tmp;
sys/dev/drm/radeon/radeon_atombios.c
3057
tmp = eng_clock & SET_CLOCK_FREQ_MASK;
sys/dev/drm/radeon/radeon_atombios.c
3058
tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
sys/dev/drm/radeon/radeon_atombios.c
3060
args.ulTargetEngineClock = cpu_to_le32(tmp);
sys/dev/drm/radeon/radeon_atombios.c
3083
u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
sys/dev/drm/radeon/radeon_atombios.c
3085
args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */
sys/dev/drm/radeon/radeon_bios.c
734
uint16_t tmp;
sys/dev/drm/radeon/radeon_bios.c
757
tmp = RBIOS16(0x18);
sys/dev/drm/radeon/radeon_bios.c
758
if (RBIOS8(tmp + 0x14) != 0x0) {
sys/dev/drm/radeon/radeon_bios.c
767
tmp = rdev->bios_header_start + 4;
sys/dev/drm/radeon/radeon_bios.c
768
if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
sys/dev/drm/radeon/radeon_bios.c
769
!memcmp(rdev->bios + tmp, "MOTA", 4)) {
sys/dev/drm/radeon/radeon_clocks.c
196
u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV);
sys/dev/drm/radeon/radeon_clocks.c
199
(tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT;
sys/dev/drm/radeon/radeon_clocks.c
201
p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK;
sys/dev/drm/radeon/radeon_clocks.c
389
uint32_t tmp;
sys/dev/drm/radeon/radeon_clocks.c
396
tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
397
tmp &= ~RADEON_DONT_USE_XTALIN;
sys/dev/drm/radeon/radeon_clocks.c
398
WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
400
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
401
tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
sys/dev/drm/radeon/radeon_clocks.c
402
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
406
tmp = RREG32_PLL(RADEON_SPLL_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
407
tmp |= RADEON_SPLL_SLEEP;
sys/dev/drm/radeon/radeon_clocks.c
408
WREG32_PLL(RADEON_SPLL_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
412
tmp = RREG32_PLL(RADEON_SPLL_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
413
tmp |= RADEON_SPLL_RESET;
sys/dev/drm/radeon/radeon_clocks.c
414
WREG32_PLL(RADEON_SPLL_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
418
tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
sys/dev/drm/radeon/radeon_clocks.c
419
tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT);
sys/dev/drm/radeon/radeon_clocks.c
420
tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT;
sys/dev/drm/radeon/radeon_clocks.c
421
WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp);
sys/dev/drm/radeon/radeon_clocks.c
424
tmp = RREG32_PLL(RADEON_SPLL_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
425
tmp &= ~RADEON_SPLL_PVG_MASK;
sys/dev/drm/radeon/radeon_clocks.c
427
tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT);
sys/dev/drm/radeon/radeon_clocks.c
429
tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT);
sys/dev/drm/radeon/radeon_clocks.c
430
WREG32_PLL(RADEON_SPLL_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
432
tmp = RREG32_PLL(RADEON_SPLL_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
433
tmp &= ~RADEON_SPLL_SLEEP;
sys/dev/drm/radeon/radeon_clocks.c
434
WREG32_PLL(RADEON_SPLL_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
438
tmp = RREG32_PLL(RADEON_SPLL_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
439
tmp &= ~RADEON_SPLL_RESET;
sys/dev/drm/radeon/radeon_clocks.c
440
WREG32_PLL(RADEON_SPLL_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
444
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
445
tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
sys/dev/drm/radeon/radeon_clocks.c
449
tmp |= 1;
sys/dev/drm/radeon/radeon_clocks.c
452
tmp |= 2;
sys/dev/drm/radeon/radeon_clocks.c
455
tmp |= 3;
sys/dev/drm/radeon/radeon_clocks.c
458
tmp |= 4;
sys/dev/drm/radeon/radeon_clocks.c
461
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
465
tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
466
tmp |= RADEON_DONT_USE_XTALIN;
sys/dev/drm/radeon/radeon_clocks.c
467
WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
474
uint32_t tmp;
sys/dev/drm/radeon/radeon_clocks.c
478
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
482
tmp &=
sys/dev/drm/radeon/radeon_clocks.c
486
tmp &=
sys/dev/drm/radeon/radeon_clocks.c
492
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
496
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
497
tmp &=
sys/dev/drm/radeon/radeon_clocks.c
511
tmp |= RADEON_DYN_STOP_LAT_MASK;
sys/dev/drm/radeon/radeon_clocks.c
512
tmp |=
sys/dev/drm/radeon/radeon_clocks.c
515
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
517
tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
518
tmp &= ~RADEON_SCLK_MORE_FORCEON;
sys/dev/drm/radeon/radeon_clocks.c
519
tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
sys/dev/drm/radeon/radeon_clocks.c
520
WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
522
tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
523
tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
sys/dev/drm/radeon/radeon_clocks.c
525
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
527
tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
528
tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
sys/dev/drm/radeon/radeon_clocks.c
541
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
543
tmp = RREG32_PLL(R300_SCLK_CNTL2);
sys/dev/drm/radeon/radeon_clocks.c
544
tmp &= ~(R300_SCLK_FORCE_TCL |
sys/dev/drm/radeon/radeon_clocks.c
547
tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT |
sys/dev/drm/radeon/radeon_clocks.c
550
WREG32_PLL(R300_SCLK_CNTL2, tmp);
sys/dev/drm/radeon/radeon_clocks.c
552
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
553
tmp &=
sys/dev/drm/radeon/radeon_clocks.c
567
tmp |= RADEON_DYN_STOP_LAT_MASK;
sys/dev/drm/radeon/radeon_clocks.c
568
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
570
tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
571
tmp &= ~RADEON_SCLK_MORE_FORCEON;
sys/dev/drm/radeon/radeon_clocks.c
572
tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
sys/dev/drm/radeon/radeon_clocks.c
573
WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
575
tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
576
tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
sys/dev/drm/radeon/radeon_clocks.c
578
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
580
tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
581
tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
sys/dev/drm/radeon/radeon_clocks.c
594
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
596
tmp = RREG32_PLL(RADEON_MCLK_MISC);
sys/dev/drm/radeon/radeon_clocks.c
597
tmp |= (RADEON_MC_MCLK_DYN_ENABLE |
sys/dev/drm/radeon/radeon_clocks.c
599
WREG32_PLL(RADEON_MCLK_MISC, tmp);
sys/dev/drm/radeon/radeon_clocks.c
601
tmp = RREG32_PLL(RADEON_MCLK_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
602
tmp |= (RADEON_FORCEON_MCLKA |
sys/dev/drm/radeon/radeon_clocks.c
605
tmp &= ~(RADEON_FORCEON_YCLKA |
sys/dev/drm/radeon/radeon_clocks.c
613
if ((tmp & R300_DISABLE_MC_MCLKA) &&
sys/dev/drm/radeon/radeon_clocks.c
614
(tmp & R300_DISABLE_MC_MCLKB)) {
sys/dev/drm/radeon/radeon_clocks.c
616
tmp = RREG32_PLL(RADEON_MCLK_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
620
tmp &=
sys/dev/drm/radeon/radeon_clocks.c
623
tmp &=
sys/dev/drm/radeon/radeon_clocks.c
626
tmp &= ~(R300_DISABLE_MC_MCLKA |
sys/dev/drm/radeon/radeon_clocks.c
631
WREG32_PLL(RADEON_MCLK_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
633
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
634
tmp &= ~(R300_SCLK_FORCE_VAP);
sys/dev/drm/radeon/radeon_clocks.c
635
tmp |= RADEON_SCLK_FORCE_CP;
sys/dev/drm/radeon/radeon_clocks.c
636
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
639
tmp = RREG32_PLL(R300_SCLK_CNTL2);
sys/dev/drm/radeon/radeon_clocks.c
640
tmp &= ~(R300_SCLK_FORCE_TCL |
sys/dev/drm/radeon/radeon_clocks.c
643
WREG32_PLL(R300_SCLK_CNTL2, tmp);
sys/dev/drm/radeon/radeon_clocks.c
646
tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
648
tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK |
sys/dev/drm/radeon/radeon_clocks.c
652
tmp |= (RADEON_ENGIN_DYNCLK_MODE |
sys/dev/drm/radeon/radeon_clocks.c
654
WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
657
tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
658
tmp |= RADEON_SCLK_DYN_START_CNTL;
sys/dev/drm/radeon/radeon_clocks.c
659
WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
665
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
667
tmp &= ~RADEON_SCLK_FORCEON_MASK;
sys/dev/drm/radeon/radeon_clocks.c
679
tmp |= RADEON_SCLK_FORCE_CP;
sys/dev/drm/radeon/radeon_clocks.c
680
tmp |= RADEON_SCLK_FORCE_VIP;
sys/dev/drm/radeon/radeon_clocks.c
683
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
688
tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
689
tmp &= ~RADEON_SCLK_MORE_FORCEON;
sys/dev/drm/radeon/radeon_clocks.c
697
tmp |= RADEON_SCLK_MORE_FORCEON;
sys/dev/drm/radeon/radeon_clocks.c
699
WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
709
tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
710
tmp |= RADEON_TCL_BYPASS_DISABLE;
sys/dev/drm/radeon/radeon_clocks.c
711
WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
716
tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
717
tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
sys/dev/drm/radeon/radeon_clocks.c
725
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
728
tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
729
tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
sys/dev/drm/radeon/radeon_clocks.c
732
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
738
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
739
tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP |
sys/dev/drm/radeon/radeon_clocks.c
746
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
749
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
750
tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
sys/dev/drm/radeon/radeon_clocks.c
758
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
760
tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
761
tmp |= RADEON_SCLK_MORE_FORCEON;
sys/dev/drm/radeon/radeon_clocks.c
762
WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
764
tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
765
tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
sys/dev/drm/radeon/radeon_clocks.c
768
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
770
tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
771
tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
sys/dev/drm/radeon/radeon_clocks.c
785
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
788
tmp = RREG32_PLL(R300_SCLK_CNTL2);
sys/dev/drm/radeon/radeon_clocks.c
789
tmp |= (R300_SCLK_FORCE_TCL |
sys/dev/drm/radeon/radeon_clocks.c
791
WREG32_PLL(R300_SCLK_CNTL2, tmp);
sys/dev/drm/radeon/radeon_clocks.c
793
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
794
tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
sys/dev/drm/radeon/radeon_clocks.c
802
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
804
tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
805
tmp |= RADEON_SCLK_MORE_FORCEON;
sys/dev/drm/radeon/radeon_clocks.c
806
WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
808
tmp = RREG32_PLL(RADEON_MCLK_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
809
tmp |= (RADEON_FORCEON_MCLKA |
sys/dev/drm/radeon/radeon_clocks.c
813
WREG32_PLL(RADEON_MCLK_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
815
tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
816
tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
sys/dev/drm/radeon/radeon_clocks.c
819
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
821
tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
822
tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
sys/dev/drm/radeon/radeon_clocks.c
836
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
838
tmp = RREG32_PLL(RADEON_SCLK_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
839
tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2);
sys/dev/drm/radeon/radeon_clocks.c
840
tmp |= RADEON_SCLK_FORCE_SE;
sys/dev/drm/radeon/radeon_clocks.c
843
tmp |= (RADEON_SCLK_FORCE_RB |
sys/dev/drm/radeon/radeon_clocks.c
856
tmp |= (RADEON_SCLK_FORCE_HDP |
sys/dev/drm/radeon/radeon_clocks.c
863
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
869
tmp = RREG32_PLL(R300_SCLK_CNTL2);
sys/dev/drm/radeon/radeon_clocks.c
870
tmp |= (R300_SCLK_FORCE_TCL |
sys/dev/drm/radeon/radeon_clocks.c
873
WREG32_PLL(R300_SCLK_CNTL2, tmp);
sys/dev/drm/radeon/radeon_clocks.c
878
tmp = RREG32_PLL(RADEON_MCLK_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
879
tmp &= ~(RADEON_FORCEON_MCLKA |
sys/dev/drm/radeon/radeon_clocks.c
881
WREG32_PLL(RADEON_MCLK_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
888
tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
889
tmp |= RADEON_SCLK_MORE_FORCEON;
sys/dev/drm/radeon/radeon_clocks.c
890
WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
894
tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
895
tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
sys/dev/drm/radeon/radeon_clocks.c
903
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
sys/dev/drm/radeon/radeon_clocks.c
906
tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
907
tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
sys/dev/drm/radeon/radeon_clocks.c
909
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
sys/dev/drm/radeon/radeon_combios.c
1173
int tmp, i;
sys/dev/drm/radeon/radeon_combios.c
1247
tmp = RBIOS16(lcd_info + 64 + i * 2);
sys/dev/drm/radeon/radeon_combios.c
1248
if (tmp == 0)
sys/dev/drm/radeon/radeon_combios.c
1251
if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
sys/dev/drm/radeon/radeon_combios.c
1252
(RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
sys/dev/drm/radeon/radeon_combios.c
1253
u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
sys/dev/drm/radeon/radeon_combios.c
1259
(RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
sys/dev/drm/radeon/radeon_combios.c
1263
(RBIOS8(tmp + 23) * 8);
sys/dev/drm/radeon/radeon_combios.c
1266
(RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
sys/dev/drm/radeon/radeon_combios.c
1268
((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
sys/dev/drm/radeon/radeon_combios.c
1270
((RBIOS16(tmp + 28) & 0xf800) >> 11);
sys/dev/drm/radeon/radeon_combios.c
1272
lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
sys/dev/drm/radeon/radeon_combios.c
2303
uint16_t tmp, connector_object_id;
sys/dev/drm/radeon/radeon_combios.c
2318
tmp = RBIOS16(entry);
sys/dev/drm/radeon/radeon_combios.c
2320
connector = (tmp >> 12) & 0xf;
sys/dev/drm/radeon/radeon_combios.c
2322
ddc_type = (tmp >> 8) & 0xf;
sys/dev/drm/radeon/radeon_combios.c
2332
if ((tmp >> 4) & 0x1)
sys/dev/drm/radeon/radeon_combios.c
2348
if ((tmp >> 4) & 0x1)
sys/dev/drm/radeon/radeon_combios.c
2364
if (tmp & 0x1) {
sys/dev/drm/radeon/radeon_combios.c
2392
if (tmp & 0x1) {
sys/dev/drm/radeon/radeon_combios.c
2415
tmp &= ~(1 << 4);
sys/dev/drm/radeon/radeon_combios.c
2417
if ((tmp >> 4) & 0x1) {
sys/dev/drm/radeon/radeon_combios.c
2446
if ((tmp >> 4) & 0x1) {
sys/dev/drm/radeon/radeon_combios.c
2634
u8 rev, blocks, tmp;
sys/dev/drm/radeon/radeon_combios.c
2751
tmp = RBIOS8(offset + 0x5 + 0xd);
sys/dev/drm/radeon/radeon_combios.c
2752
rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
sys/dev/drm/radeon/radeon_combios.c
2759
tmp = RBIOS8(voltage_table_offset + 0x2);
sys/dev/drm/radeon/radeon_combios.c
2760
rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
sys/dev/drm/radeon/radeon_combios.c
3014
uint32_t tmp;
sys/dev/drm/radeon/radeon_combios.c
3033
tmp = RREG32(addr);
sys/dev/drm/radeon/radeon_combios.c
3034
tmp &= and_mask;
sys/dev/drm/radeon/radeon_combios.c
3035
tmp |= or_mask;
sys/dev/drm/radeon/radeon_combios.c
3036
WREG32(addr, tmp);
sys/dev/drm/radeon/radeon_combios.c
3043
tmp = RREG32(addr);
sys/dev/drm/radeon/radeon_combios.c
3044
tmp &= and_mask;
sys/dev/drm/radeon/radeon_combios.c
3045
tmp |= or_mask;
sys/dev/drm/radeon/radeon_combios.c
3046
WREG32(addr, tmp);
sys/dev/drm/radeon/radeon_combios.c
3092
uint32_t val, shift, tmp;
sys/dev/drm/radeon/radeon_combios.c
3110
tmp = RREG32_PLL(addr);
sys/dev/drm/radeon/radeon_combios.c
3111
tmp &= and_mask;
sys/dev/drm/radeon/radeon_combios.c
3112
tmp |= or_mask;
sys/dev/drm/radeon/radeon_combios.c
3113
WREG32_PLL(addr, tmp);
sys/dev/drm/radeon/radeon_combios.c
3117
tmp = 1000;
sys/dev/drm/radeon/radeon_combios.c
3126
while (tmp--) {
sys/dev/drm/radeon/radeon_combios.c
3135
while (tmp--) {
sys/dev/drm/radeon/radeon_combios.c
3143
tmp =
sys/dev/drm/radeon/radeon_combios.c
3145
if (tmp & RADEON_CG_NO1_DEBUG_0) {
sys/dev/drm/radeon/radeon_combios.c
3158
tmp &
sys/dev/drm/radeon/radeon_combios.c
3178
uint32_t tmp;
sys/dev/drm/radeon/radeon_combios.c
3194
tmp = 20000;
sys/dev/drm/radeon/radeon_combios.c
3195
while (tmp--) {
sys/dev/drm/radeon/radeon_combios.c
3205
tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
sys/dev/drm/radeon/radeon_combios.c
3206
tmp &= RADEON_SDRAM_MODE_MASK;
sys/dev/drm/radeon/radeon_combios.c
3207
tmp |= or_mask;
sys/dev/drm/radeon/radeon_combios.c
3208
WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
sys/dev/drm/radeon/radeon_combios.c
3211
tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
sys/dev/drm/radeon/radeon_combios.c
3212
tmp &= RADEON_B3MEM_RESET_MASK;
sys/dev/drm/radeon/radeon_combios.c
3213
tmp |= or_mask;
sys/dev/drm/radeon/radeon_combios.c
3214
WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
sys/dev/drm/radeon/radeon_device.c
198
u32 tmp, reg, and_mask, or_mask;
sys/dev/drm/radeon/radeon_device.c
210
tmp = or_mask;
sys/dev/drm/radeon/radeon_device.c
212
tmp = RREG32(reg);
sys/dev/drm/radeon/radeon_device.c
213
tmp &= ~and_mask;
sys/dev/drm/radeon/radeon_device.c
214
tmp |= or_mask;
sys/dev/drm/radeon/radeon_device.c
216
WREG32(reg, tmp);
sys/dev/drm/radeon/radeon_display.c
1067
unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
sys/dev/drm/radeon/radeon_display.c
1068
fb_div *= tmp;
sys/dev/drm/radeon/radeon_display.c
1069
ref_div *= tmp;
sys/dev/drm/radeon/radeon_display.c
1199
uint64_t tmp;
sys/dev/drm/radeon/radeon_display.c
1203
tmp = (uint64_t)pll->reference_freq * feedback_div;
sys/dev/drm/radeon/radeon_display.c
1204
vco = radeon_div(tmp, ref_div);
sys/dev/drm/radeon/radeon_display.c
1216
tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
sys/dev/drm/radeon/radeon_display.c
1217
tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
sys/dev/drm/radeon/radeon_display.c
1218
current_freq = radeon_div(tmp, ref_div * post_div);
sys/dev/drm/radeon/radeon_display.c
884
unsigned tmp;
sys/dev/drm/radeon/radeon_display.c
887
tmp = gcd(*nom, *den);
sys/dev/drm/radeon/radeon_display.c
888
*nom /= tmp;
sys/dev/drm/radeon/radeon_display.c
889
*den /= tmp;
sys/dev/drm/radeon/radeon_display.c
893
tmp = DIV_ROUND_UP(nom_min, *nom);
sys/dev/drm/radeon/radeon_display.c
894
*nom *= tmp;
sys/dev/drm/radeon/radeon_display.c
895
*den *= tmp;
sys/dev/drm/radeon/radeon_display.c
900
tmp = DIV_ROUND_UP(den_min, *den);
sys/dev/drm/radeon/radeon_display.c
901
*nom *= tmp;
sys/dev/drm/radeon/radeon_display.c
902
*den *= tmp;
sys/dev/drm/radeon/radeon_dp_auxch.c
100
tmp |= (1 << 16);
sys/dev/drm/radeon/radeon_dp_auxch.c
101
WREG32(chan->rec.mask_clk_reg, tmp);
sys/dev/drm/radeon/radeon_dp_auxch.c
104
tmp = RREG32(AUX_CONTROL + aux_offset[instance]);
sys/dev/drm/radeon/radeon_dp_auxch.c
106
tmp &= AUX_HPD_SEL(0x7);
sys/dev/drm/radeon/radeon_dp_auxch.c
107
tmp |= AUX_HPD_SEL(chan->rec.hpd);
sys/dev/drm/radeon/radeon_dp_auxch.c
108
tmp |= AUX_EN | AUX_LS_READ_EN;
sys/dev/drm/radeon/radeon_dp_auxch.c
110
WREG32(AUX_CONTROL + aux_offset[instance], tmp);
sys/dev/drm/radeon/radeon_dp_auxch.c
153
tmp = RREG32(AUX_SW_STATUS + aux_offset[instance]);
sys/dev/drm/radeon/radeon_dp_auxch.c
154
if (tmp & AUX_SW_DONE) {
sys/dev/drm/radeon/radeon_dp_auxch.c
161
DRM_ERROR("auxch hw never signalled completion, error %08x\n", tmp);
sys/dev/drm/radeon/radeon_dp_auxch.c
166
if (tmp & AUX_SW_RX_TIMEOUT) {
sys/dev/drm/radeon/radeon_dp_auxch.c
170
if (tmp & AUX_RX_ERROR_FLAGS) {
sys/dev/drm/radeon/radeon_dp_auxch.c
172
tmp);
sys/dev/drm/radeon/radeon_dp_auxch.c
177
bytes = AUX_SW_REPLY_GET_BYTE_COUNT(tmp);
sys/dev/drm/radeon/radeon_dp_auxch.c
182
tmp = RREG32(AUX_SW_DATA + aux_offset[instance]);
sys/dev/drm/radeon/radeon_dp_auxch.c
183
ack = (tmp >> 8) & 0xff;
sys/dev/drm/radeon/radeon_dp_auxch.c
186
tmp = RREG32(AUX_SW_DATA + aux_offset[instance]);
sys/dev/drm/radeon/radeon_dp_auxch.c
188
buf[i] = (tmp >> 8) & 0xff;
sys/dev/drm/radeon/radeon_dp_auxch.c
62
uint32_t tmp, ack = 0;
sys/dev/drm/radeon/radeon_dp_auxch.c
99
tmp = RREG32(chan->rec.mask_clk_reg);
sys/dev/drm/radeon/radeon_fb.c
284
unsigned long tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start;
sys/dev/drm/radeon/radeon_fb.c
286
info->paddr = rdev->mc.aper_base + tmp;
sys/dev/drm/radeon/radeon_fb.c
294
tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start;
sys/dev/drm/radeon/radeon_fb.c
295
info->fix.smem_start = rdev->mc.aper_base + tmp;
sys/dev/drm/radeon/radeon_fence.c
714
struct radeon_fence *tmp = *fence;
sys/dev/drm/radeon/radeon_fence.c
717
if (tmp) {
sys/dev/drm/radeon/radeon_fence.c
718
dma_fence_put(&tmp->base);
sys/dev/drm/radeon/radeon_i2c.c
336
u32 tmp, reg;
sys/dev/drm/radeon/radeon_i2c.c
351
tmp = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/drm/radeon/radeon_i2c.c
352
WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
sys/dev/drm/radeon/radeon_i2c.c
479
tmp = RREG32(i2c_cntl_0);
sys/dev/drm/radeon/radeon_i2c.c
480
if (tmp & RADEON_I2C_GO)
sys/dev/drm/radeon/radeon_i2c.c
482
tmp = RREG32(i2c_cntl_0);
sys/dev/drm/radeon/radeon_i2c.c
483
if (tmp & RADEON_I2C_DONE)
sys/dev/drm/radeon/radeon_i2c.c
486
DRM_DEBUG("i2c write error 0x%08x\n", tmp);
sys/dev/drm/radeon/radeon_i2c.c
487
WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
sys/dev/drm/radeon/radeon_i2c.c
511
tmp = RREG32(i2c_cntl_0);
sys/dev/drm/radeon/radeon_i2c.c
512
if (tmp & RADEON_I2C_GO)
sys/dev/drm/radeon/radeon_i2c.c
514
tmp = RREG32(i2c_cntl_0);
sys/dev/drm/radeon/radeon_i2c.c
515
if (tmp & RADEON_I2C_DONE)
sys/dev/drm/radeon/radeon_i2c.c
518
DRM_DEBUG("i2c read error 0x%08x\n", tmp);
sys/dev/drm/radeon/radeon_i2c.c
519
WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
sys/dev/drm/radeon/radeon_i2c.c
539
tmp = RREG32(i2c_cntl_0);
sys/dev/drm/radeon/radeon_i2c.c
540
if (tmp & RADEON_I2C_GO)
sys/dev/drm/radeon/radeon_i2c.c
542
tmp = RREG32(i2c_cntl_0);
sys/dev/drm/radeon/radeon_i2c.c
543
if (tmp & RADEON_I2C_DONE)
sys/dev/drm/radeon/radeon_i2c.c
546
DRM_DEBUG("i2c write error 0x%08x\n", tmp);
sys/dev/drm/radeon/radeon_i2c.c
547
WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
sys/dev/drm/radeon/radeon_i2c.c
565
tmp = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/drm/radeon/radeon_i2c.c
566
tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
sys/dev/drm/radeon/radeon_i2c.c
567
WREG32(RADEON_BIOS_6_SCRATCH, tmp);
sys/dev/drm/radeon/radeon_i2c.c
588
u32 tmp, reg;
sys/dev/drm/radeon/radeon_i2c.c
598
tmp = RREG32(rec->mask_clk_reg);
sys/dev/drm/radeon/radeon_i2c.c
599
tmp &= ~rec->mask_clk_mask;
sys/dev/drm/radeon/radeon_i2c.c
600
WREG32(rec->mask_clk_reg, tmp);
sys/dev/drm/radeon/radeon_i2c.c
601
tmp = RREG32(rec->mask_clk_reg);
sys/dev/drm/radeon/radeon_i2c.c
603
tmp = RREG32(rec->mask_data_reg);
sys/dev/drm/radeon/radeon_i2c.c
604
tmp &= ~rec->mask_data_mask;
sys/dev/drm/radeon/radeon_i2c.c
605
WREG32(rec->mask_data_reg, tmp);
sys/dev/drm/radeon/radeon_i2c.c
606
tmp = RREG32(rec->mask_data_reg);
sys/dev/drm/radeon/radeon_i2c.c
609
tmp = RREG32(rec->a_clk_reg);
sys/dev/drm/radeon/radeon_i2c.c
610
tmp &= ~rec->a_clk_mask;
sys/dev/drm/radeon/radeon_i2c.c
611
WREG32(rec->a_clk_reg, tmp);
sys/dev/drm/radeon/radeon_i2c.c
612
tmp = RREG32(rec->a_clk_reg);
sys/dev/drm/radeon/radeon_i2c.c
614
tmp = RREG32(rec->a_data_reg);
sys/dev/drm/radeon/radeon_i2c.c
615
tmp &= ~rec->a_data_mask;
sys/dev/drm/radeon/radeon_i2c.c
616
WREG32(rec->a_data_reg, tmp);
sys/dev/drm/radeon/radeon_i2c.c
617
tmp = RREG32(rec->a_data_reg);
sys/dev/drm/radeon/radeon_i2c.c
620
tmp = RREG32(rec->en_clk_reg);
sys/dev/drm/radeon/radeon_i2c.c
621
tmp &= ~rec->en_clk_mask;
sys/dev/drm/radeon/radeon_i2c.c
622
WREG32(rec->en_clk_reg, tmp);
sys/dev/drm/radeon/radeon_i2c.c
623
tmp = RREG32(rec->en_clk_reg);
sys/dev/drm/radeon/radeon_i2c.c
625
tmp = RREG32(rec->en_data_reg);
sys/dev/drm/radeon/radeon_i2c.c
626
tmp &= ~rec->en_data_mask;
sys/dev/drm/radeon/radeon_i2c.c
627
WREG32(rec->en_data_reg, tmp);
sys/dev/drm/radeon/radeon_i2c.c
628
tmp = RREG32(rec->en_data_reg);
sys/dev/drm/radeon/radeon_i2c.c
631
tmp = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/drm/radeon/radeon_i2c.c
632
WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
sys/dev/drm/radeon/radeon_i2c.c
687
tmp = RREG32(AVIVO_DC_I2C_STATUS1);
sys/dev/drm/radeon/radeon_i2c.c
688
if (tmp & AVIVO_DC_I2C_GO)
sys/dev/drm/radeon/radeon_i2c.c
690
tmp = RREG32(AVIVO_DC_I2C_STATUS1);
sys/dev/drm/radeon/radeon_i2c.c
691
if (tmp & AVIVO_DC_I2C_DONE)
sys/dev/drm/radeon/radeon_i2c.c
694
DRM_DEBUG("i2c write error 0x%08x\n", tmp);
sys/dev/drm/radeon/radeon_i2c.c
729
tmp = RREG32(AVIVO_DC_I2C_STATUS1);
sys/dev/drm/radeon/radeon_i2c.c
730
if (tmp & AVIVO_DC_I2C_GO)
sys/dev/drm/radeon/radeon_i2c.c
732
tmp = RREG32(AVIVO_DC_I2C_STATUS1);
sys/dev/drm/radeon/radeon_i2c.c
733
if (tmp & AVIVO_DC_I2C_DONE)
sys/dev/drm/radeon/radeon_i2c.c
736
DRM_DEBUG("i2c read error 0x%08x\n", tmp);
sys/dev/drm/radeon/radeon_i2c.c
772
tmp = RREG32(AVIVO_DC_I2C_STATUS1);
sys/dev/drm/radeon/radeon_i2c.c
773
if (tmp & AVIVO_DC_I2C_GO)
sys/dev/drm/radeon/radeon_i2c.c
775
tmp = RREG32(AVIVO_DC_I2C_STATUS1);
sys/dev/drm/radeon/radeon_i2c.c
776
if (tmp & AVIVO_DC_I2C_DONE)
sys/dev/drm/radeon/radeon_i2c.c
779
DRM_DEBUG("i2c write error 0x%08x\n", tmp);
sys/dev/drm/radeon/radeon_i2c.c
802
tmp = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/drm/radeon/radeon_i2c.c
803
tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
sys/dev/drm/radeon/radeon_i2c.c
804
WREG32(RADEON_BIOS_6_SCRATCH, tmp);
sys/dev/drm/radeon/radeon_irq_kms.c
574
u32 tmp = RREG32(reg);
sys/dev/drm/radeon/radeon_irq_kms.c
577
if (!!(tmp & mask) == enable)
sys/dev/drm/radeon/radeon_irq_kms.c
582
WREG32(reg, tmp |= mask);
sys/dev/drm/radeon/radeon_irq_kms.c
585
WREG32(reg, tmp & ~mask);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1311
uint32_t disp_output_cntl, gpiopad_a, tmp;
sys/dev/drm/radeon/radeon_legacy_encoders.c
1329
tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
sys/dev/drm/radeon/radeon_legacy_encoders.c
1330
tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
sys/dev/drm/radeon/radeon_legacy_encoders.c
1331
WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1358
tmp = RREG32(RADEON_TV_DAC_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1359
if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
sys/dev/drm/radeon/radeon_legacy_encoders.c
1362
} else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
sys/dev/drm/radeon/radeon_legacy_encoders.c
1382
uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
sys/dev/drm/radeon/radeon_legacy_encoders.c
1394
tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
sys/dev/drm/radeon/radeon_legacy_encoders.c
1395
WREG32(RADEON_DAC_CNTL2, tmp);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1397
tmp = tv_master_cntl | RADEON_TV_ON;
sys/dev/drm/radeon/radeon_legacy_encoders.c
1398
tmp &= ~(RADEON_TV_ASYNC_RST |
sys/dev/drm/radeon/radeon_legacy_encoders.c
1403
tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
sys/dev/drm/radeon/radeon_legacy_encoders.c
1404
WREG32(RADEON_TV_MASTER_CNTL, tmp);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1406
tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
sys/dev/drm/radeon/radeon_legacy_encoders.c
1411
tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1413
tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1414
WREG32(RADEON_TV_DAC_CNTL, tmp);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1416
tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
sys/dev/drm/radeon/radeon_legacy_encoders.c
1421
WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1424
tmp = RREG32(RADEON_TV_DAC_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1425
if (tmp & RADEON_TV_DAC_GDACDET) {
sys/dev/drm/radeon/radeon_legacy_encoders.c
1428
} else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
sys/dev/drm/radeon/radeon_legacy_encoders.c
1448
uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp;
sys/dev/drm/radeon/radeon_legacy_encoders.c
1469
tmp = RREG32(RADEON_GPIO_MONID);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1470
tmp &= ~RADEON_GPIO_A_0;
sys/dev/drm/radeon/radeon_legacy_encoders.c
1471
WREG32(RADEON_GPIO_MONID, tmp);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1498
tmp = RREG32(RADEON_GPIO_MONID);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1499
if (tmp & RADEON_GPIO_Y_0)
sys/dev/drm/radeon/radeon_legacy_encoders.c
1537
uint32_t gpiopad_a = 0, pixclks_cntl, tmp;
sys/dev/drm/radeon/radeon_legacy_encoders.c
1600
tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
sys/dev/drm/radeon/radeon_legacy_encoders.c
1602
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1605
tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
sys/dev/drm/radeon/radeon_legacy_encoders.c
1606
WREG32(RADEON_CRTC_EXT_CNTL, tmp);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1608
tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
sys/dev/drm/radeon/radeon_legacy_encoders.c
1609
tmp |= RADEON_CRTC2_CRT2_ON |
sys/dev/drm/radeon/radeon_legacy_encoders.c
1611
WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1615
tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
sys/dev/drm/radeon/radeon_legacy_encoders.c
1616
tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
sys/dev/drm/radeon/radeon_legacy_encoders.c
1617
WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1619
tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
sys/dev/drm/radeon/radeon_legacy_encoders.c
1620
WREG32(RADEON_DISP_HW_DEBUG, tmp);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1624
tmp = RADEON_TV_DAC_NBLANK |
sys/dev/drm/radeon/radeon_legacy_encoders.c
1629
WREG32(RADEON_TV_DAC_CNTL, tmp);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1631
tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
sys/dev/drm/radeon/radeon_legacy_encoders.c
1635
tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
sys/dev/drm/radeon/radeon_legacy_encoders.c
1637
tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
sys/dev/drm/radeon/radeon_legacy_encoders.c
1640
tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1642
tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1644
WREG32(RADEON_DAC_EXT_CNTL, tmp);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1646
tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
sys/dev/drm/radeon/radeon_legacy_encoders.c
1647
WREG32(RADEON_DAC_CNTL2, tmp);
sys/dev/drm/radeon/radeon_legacy_encoders.c
646
uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
sys/dev/drm/radeon/radeon_legacy_encoders.c
665
tmp = vclk_ecp_cntl &
sys/dev/drm/radeon/radeon_legacy_encoders.c
667
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
sys/dev/drm/radeon/radeon_legacy_encoders.c
669
tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
sys/dev/drm/radeon/radeon_legacy_encoders.c
670
WREG32(RADEON_CRTC_EXT_CNTL, tmp);
sys/dev/drm/radeon/radeon_legacy_encoders.c
672
tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
sys/dev/drm/radeon/radeon_legacy_encoders.c
676
tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
sys/dev/drm/radeon/radeon_legacy_encoders.c
678
tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
sys/dev/drm/radeon/radeon_legacy_encoders.c
681
tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
sys/dev/drm/radeon/radeon_legacy_encoders.c
683
tmp |= (0x1ac << RADEON_DAC_FORCE_DATA_SHIFT);
sys/dev/drm/radeon/radeon_legacy_encoders.c
685
tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
sys/dev/drm/radeon/radeon_legacy_encoders.c
687
WREG32(RADEON_DAC_EXT_CNTL, tmp);
sys/dev/drm/radeon/radeon_legacy_encoders.c
689
tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
sys/dev/drm/radeon/radeon_legacy_encoders.c
690
tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
sys/dev/drm/radeon/radeon_legacy_encoders.c
691
WREG32(RADEON_DAC_CNTL, tmp);
sys/dev/drm/radeon/radeon_legacy_encoders.c
693
tmp = dac_macro_cntl;
sys/dev/drm/radeon/radeon_legacy_encoders.c
694
tmp &= ~(RADEON_DAC_PDWN_R |
sys/dev/drm/radeon/radeon_legacy_encoders.c
698
WREG32(RADEON_DAC_MACRO_CNTL, tmp);
sys/dev/drm/radeon/radeon_legacy_encoders.c
788
uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
sys/dev/drm/radeon/radeon_legacy_encoders.c
793
tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
794
tmp &= 0xfffff;
sys/dev/drm/radeon/radeon_legacy_encoders.c
797
tmp ^= (1 << 22);
sys/dev/drm/radeon/radeon_legacy_encoders.c
808
tmp = tmds->tmds_pll[i].value ;
sys/dev/drm/radeon/radeon_legacy_encoders.c
815
if (tmp & 0xfff00000)
sys/dev/drm/radeon/radeon_legacy_encoders.c
816
tmds_pll_cntl = tmp;
sys/dev/drm/radeon/radeon_legacy_encoders.c
819
tmds_pll_cntl |= tmp;
sys/dev/drm/radeon/radeon_legacy_encoders.c
822
tmds_pll_cntl = tmp;
sys/dev/drm/radeon/radeon_legacy_tv.c
303
uint32_t tmp;
sys/dev/drm/radeon/radeon_legacy_tv.c
312
tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL);
sys/dev/drm/radeon/radeon_legacy_tv.c
313
if ((tmp & RADEON_HOST_FIFO_WT_ACK) == 0)
sys/dev/drm/radeon/radeon_legacy_tv.c
325
uint32_t tmp;
sys/dev/drm/radeon/radeon_legacy_tv.c
332
tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL);
sys/dev/drm/radeon/radeon_legacy_tv.c
333
if ((tmp & RADEON_HOST_FIFO_RD_ACK) == 0)
sys/dev/drm/radeon/radeon_legacy_tv.c
390
uint32_t tmp;
sys/dev/drm/radeon/radeon_legacy_tv.c
398
tmp = ((uint32_t)tv_dac->tv.h_code_timing[i] << 14) | ((uint32_t)tv_dac->tv.h_code_timing[i+1]);
sys/dev/drm/radeon/radeon_legacy_tv.c
399
radeon_legacy_tv_write_fifo(radeon_encoder, h_table, tmp);
sys/dev/drm/radeon/radeon_legacy_tv.c
404
tmp = ((uint32_t)tv_dac->tv.v_code_timing[i+1] << 14) | ((uint32_t)tv_dac->tv.v_code_timing[i]);
sys/dev/drm/radeon/radeon_legacy_tv.c
405
radeon_legacy_tv_write_fifo(radeon_encoder, v_table, tmp);
sys/dev/drm/radeon/radeon_legacy_tv.c
543
uint32_t vert_space, flicker_removal, tmp;
sys/dev/drm/radeon/radeon_legacy_tv.c
620
tmp = RREG32(RADEON_TV_VSCALER_CNTL1);
sys/dev/drm/radeon/radeon_legacy_tv.c
621
tmp &= 0xe3ff0000;
sys/dev/drm/radeon/radeon_legacy_tv.c
622
tmp |= (vert_space * (1 << FRAC_BITS) / 10000);
sys/dev/drm/radeon/radeon_legacy_tv.c
623
tv_vscaler_cntl1 = tmp;
sys/dev/drm/radeon/radeon_legacy_tv.c
634
tmp = const_ptr->ver_total * 2 * 1000;
sys/dev/drm/radeon/radeon_legacy_tv.c
639
tmp /= NTSC_TV_LINES_PER_FRAME;
sys/dev/drm/radeon/radeon_legacy_tv.c
641
tmp /= PAL_TV_LINES_PER_FRAME;
sys/dev/drm/radeon/radeon_legacy_tv.c
643
flicker_removal = (tmp + 500) / 1000;
sys/dev/drm/radeon/radeon_legacy_tv.c
669
tmp = (tv_vscaler_cntl1 >> RADEON_UV_INC_SHIFT) & RADEON_UV_INC_MASK;
sys/dev/drm/radeon/radeon_legacy_tv.c
670
tmp = ((16384 * 256 * 10) / tmp + 5) / 10;
sys/dev/drm/radeon/radeon_legacy_tv.c
671
tmp = (tmp << RADEON_UV_OUTPUT_POST_SCALE_SHIFT) | 0x000b0000;
sys/dev/drm/radeon/radeon_legacy_tv.c
672
tv_dac->tv.timing_cntl = tmp;
sys/dev/drm/radeon/radeon_legacy_tv.c
761
tmp = RREG32(RADEON_TV_DAC_CNTL);
sys/dev/drm/radeon/radeon_legacy_tv.c
762
tmp &= ~RADEON_TV_DAC_NBLANK;
sys/dev/drm/radeon/radeon_legacy_tv.c
763
tmp |= RADEON_TV_DAC_BGSLEEP |
sys/dev/drm/radeon/radeon_legacy_tv.c
767
WREG32(RADEON_TV_DAC_CNTL, tmp);
sys/dev/drm/radeon/radeon_legacy_tv.c
843
uint32_t tmp;
sys/dev/drm/radeon/radeon_legacy_tv.c
852
tmp = *h_sync_strt_wid;
sys/dev/drm/radeon/radeon_legacy_tv.c
853
tmp &= ~(RADEON_CRTC_H_SYNC_STRT_PIX | RADEON_CRTC_H_SYNC_STRT_CHAR);
sys/dev/drm/radeon/radeon_legacy_tv.c
854
tmp |= (((const_ptr->hor_syncstart / 8) - 1) << RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT) |
sys/dev/drm/radeon/radeon_legacy_tv.c
856
*h_sync_strt_wid = tmp;
sys/dev/drm/radeon/radeon_legacy_tv.c
861
tmp = *v_sync_strt_wid;
sys/dev/drm/radeon/radeon_legacy_tv.c
862
tmp &= ~RADEON_CRTC_V_SYNC_STRT;
sys/dev/drm/radeon/radeon_legacy_tv.c
863
tmp |= ((const_ptr->ver_syncstart - 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT);
sys/dev/drm/radeon/radeon_legacy_tv.c
864
*v_sync_strt_wid = tmp;
sys/dev/drm/radeon/radeon_sa.c
156
struct radeon_sa_bo *sa_bo, *tmp;
sys/dev/drm/radeon/radeon_sa.c
162
list_for_each_entry_safe_from(sa_bo, tmp, &sa_manager->olist, olist) {
sys/dev/drm/radeon/radeon_sa.c
252
unsigned i, soffset, best, tmp;
sys/dev/drm/radeon/radeon_sa.c
287
tmp = sa_bo->soffset;
sys/dev/drm/radeon/radeon_sa.c
288
if (tmp < soffset) {
sys/dev/drm/radeon/radeon_sa.c
290
tmp += sa_manager->size;
sys/dev/drm/radeon/radeon_sa.c
292
tmp -= soffset;
sys/dev/drm/radeon/radeon_sa.c
293
if (tmp < best) {
sys/dev/drm/radeon/radeon_sa.c
295
best = tmp;
sys/dev/drm/radeon/radeon_sa.c
80
struct radeon_sa_bo *sa_bo, *tmp;
sys/dev/drm/radeon/radeon_sa.c
89
list_for_each_entry_safe(sa_bo, tmp, &sa_manager->olist, olist) {
sys/dev/drm/radeon/radeon_uvd.c
365
unsigned image_size, tmp, min_dpb_size;
sys/dev/drm/radeon/radeon_uvd.c
399
tmp = max(width_in_mb, height_in_mb);
sys/dev/drm/radeon/radeon_uvd.c
400
min_dpb_size += ALIGN(tmp * 7 * 16, 64);
sys/dev/drm/radeon/radeon_vce.c
561
uint32_t tmp, handle = 0;
sys/dev/drm/radeon/radeon_vce.c
562
uint32_t *size = &tmp;
sys/dev/drm/radeon/radeon_vce.c
639
tmp = radeon_get_ib_value(p, p->idx + 4);
sys/dev/drm/radeon/radeon_vce.c
641
tmp);
sys/dev/drm/radeon/radeon_vm.c
1233
struct radeon_bo_va *bo_va, *tmp;
sys/dev/drm/radeon/radeon_vm.c
1240
rbtree_postorder_for_each_entry_safe(bo_va, tmp, &vm->va, it.rb) {
sys/dev/drm/radeon/radeon_vm.c
1262
list_for_each_entry_safe(bo_va, tmp, &vm->freed, vm_status) {
sys/dev/drm/radeon/radeon_vm.c
484
struct radeon_bo_va *tmp;
sys/dev/drm/radeon/radeon_vm.c
485
tmp = container_of(it, struct radeon_bo_va, it);
sys/dev/drm/radeon/radeon_vm.c
489
soffset, tmp->bo, tmp->it.start, tmp->it.last);
sys/dev/drm/radeon/radeon_vm.c
498
struct radeon_bo_va *tmp;
sys/dev/drm/radeon/radeon_vm.c
499
tmp = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL);
sys/dev/drm/radeon/radeon_vm.c
500
if (!tmp) {
sys/dev/drm/radeon/radeon_vm.c
505
tmp->it.start = bo_va->it.start;
sys/dev/drm/radeon/radeon_vm.c
506
tmp->it.last = bo_va->it.last;
sys/dev/drm/radeon/radeon_vm.c
507
tmp->vm = vm;
sys/dev/drm/radeon/radeon_vm.c
508
tmp->bo = radeon_bo_ref(bo_va->bo);
sys/dev/drm/radeon/radeon_vm.c
515
list_add(&tmp->vm_status, &vm->freed);
sys/dev/drm/radeon/rs400.c
108
uint32_t tmp;
sys/dev/drm/radeon/rs400.c
110
tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
sys/dev/drm/radeon/rs400.c
111
tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
sys/dev/drm/radeon/rs400.c
112
WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
sys/dev/drm/radeon/rs400.c
147
tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
sys/dev/drm/radeon/rs400.c
148
tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
sys/dev/drm/radeon/rs400.c
150
WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
sys/dev/drm/radeon/rs400.c
151
tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
sys/dev/drm/radeon/rs400.c
152
WREG32(RADEON_BUS_CNTL, tmp);
sys/dev/drm/radeon/rs400.c
154
WREG32(RADEON_MC_AGP_LOCATION, tmp);
sys/dev/drm/radeon/rs400.c
155
tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
sys/dev/drm/radeon/rs400.c
156
WREG32(RADEON_BUS_CNTL, tmp);
sys/dev/drm/radeon/rs400.c
159
tmp = (u32)rdev->gart.table_addr & 0xfffff000;
sys/dev/drm/radeon/rs400.c
160
tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
sys/dev/drm/radeon/rs400.c
162
WREG32_MC(RS480_GART_BASE, tmp);
sys/dev/drm/radeon/rs400.c
174
tmp = RREG32_MC(RS480_MC_MISC_CNTL);
sys/dev/drm/radeon/rs400.c
175
tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN;
sys/dev/drm/radeon/rs400.c
176
WREG32_MC(RS480_MC_MISC_CNTL, tmp);
sys/dev/drm/radeon/rs400.c
178
tmp = RREG32_MC(RS480_MC_MISC_CNTL);
sys/dev/drm/radeon/rs400.c
179
tmp |= RS480_GART_INDEX_REG_EN;
sys/dev/drm/radeon/rs400.c
180
WREG32_MC(RS480_MC_MISC_CNTL, tmp);
sys/dev/drm/radeon/rs400.c
194
uint32_t tmp;
sys/dev/drm/radeon/rs400.c
196
tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
sys/dev/drm/radeon/rs400.c
197
tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
sys/dev/drm/radeon/rs400.c
198
WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
sys/dev/drm/radeon/rs400.c
238
uint32_t tmp;
sys/dev/drm/radeon/rs400.c
242
tmp = RREG32(RADEON_MC_STATUS);
sys/dev/drm/radeon/rs400.c
243
if (tmp & RADEON_MC_IDLE) {
sys/dev/drm/radeon/rs400.c
305
uint32_t tmp;
sys/dev/drm/radeon/rs400.c
307
tmp = RREG32(RADEON_HOST_PATH_CNTL);
sys/dev/drm/radeon/rs400.c
308
seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
309
tmp = RREG32(RADEON_BUS_CNTL);
sys/dev/drm/radeon/rs400.c
310
seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
311
tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
sys/dev/drm/radeon/rs400.c
312
seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
314
tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
sys/dev/drm/radeon/rs400.c
315
seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
316
tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
sys/dev/drm/radeon/rs400.c
317
seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
318
tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
sys/dev/drm/radeon/rs400.c
319
seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
320
tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION);
sys/dev/drm/radeon/rs400.c
321
seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
322
tmp = RREG32(RS690_HDP_FB_LOCATION);
sys/dev/drm/radeon/rs400.c
323
seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
325
tmp = RREG32(RADEON_AGP_BASE);
sys/dev/drm/radeon/rs400.c
326
seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
327
tmp = RREG32(RS480_AGP_BASE_2);
sys/dev/drm/radeon/rs400.c
328
seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
329
tmp = RREG32(RADEON_MC_AGP_LOCATION);
sys/dev/drm/radeon/rs400.c
330
seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
332
tmp = RREG32_MC(RS480_GART_BASE);
sys/dev/drm/radeon/rs400.c
333
seq_printf(m, "GART_BASE 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
334
tmp = RREG32_MC(RS480_GART_FEATURE_ID);
sys/dev/drm/radeon/rs400.c
335
seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
336
tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
sys/dev/drm/radeon/rs400.c
337
seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
338
tmp = RREG32_MC(RS480_MC_MISC_CNTL);
sys/dev/drm/radeon/rs400.c
339
seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
340
tmp = RREG32_MC(0x5F);
sys/dev/drm/radeon/rs400.c
341
seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
342
tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
sys/dev/drm/radeon/rs400.c
343
seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
344
tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
sys/dev/drm/radeon/rs400.c
345
seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
346
tmp = RREG32_MC(0x3B);
sys/dev/drm/radeon/rs400.c
347
seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
348
tmp = RREG32_MC(0x3C);
sys/dev/drm/radeon/rs400.c
349
seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
350
tmp = RREG32_MC(0x30);
sys/dev/drm/radeon/rs400.c
351
seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
352
tmp = RREG32_MC(0x31);
sys/dev/drm/radeon/rs400.c
353
seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
354
tmp = RREG32_MC(0x32);
sys/dev/drm/radeon/rs400.c
355
seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
356
tmp = RREG32_MC(0x33);
sys/dev/drm/radeon/rs400.c
357
seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
358
tmp = RREG32_MC(0x34);
sys/dev/drm/radeon/rs400.c
359
seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
360
tmp = RREG32_MC(0x35);
sys/dev/drm/radeon/rs400.c
361
seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
362
tmp = RREG32_MC(0x36);
sys/dev/drm/radeon/rs400.c
363
seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
364
tmp = RREG32_MC(0x37);
sys/dev/drm/radeon/rs400.c
365
seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
sys/dev/drm/radeon/rs400.c
60
uint32_t tmp;
sys/dev/drm/radeon/rs400.c
65
tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
sys/dev/drm/radeon/rs400.c
66
if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
sys/dev/drm/radeon/rs600.c
115
u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
sys/dev/drm/radeon/rs600.c
119
tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
sys/dev/drm/radeon/rs600.c
120
WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
sys/dev/drm/radeon/rs600.c
139
tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
sys/dev/drm/radeon/rs600.c
140
WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
sys/dev/drm/radeon/rs600.c
159
u32 tmp = 0;
sys/dev/drm/radeon/rs600.c
179
tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
sys/dev/drm/radeon/rs600.c
181
tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN;
sys/dev/drm/radeon/rs600.c
186
tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN |
sys/dev/drm/radeon/rs600.c
189
tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN |
sys/dev/drm/radeon/rs600.c
200
WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp);
sys/dev/drm/radeon/rs600.c
203
WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp);
sys/dev/drm/radeon/rs600.c
206
WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp);
sys/dev/drm/radeon/rs600.c
209
WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp);
sys/dev/drm/radeon/rs600.c
221
u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
sys/dev/drm/radeon/rs600.c
226
tmp = RREG32(voltage->gpio.reg);
sys/dev/drm/radeon/rs600.c
228
tmp |= voltage->gpio.mask;
sys/dev/drm/radeon/rs600.c
230
tmp &= ~(voltage->gpio.mask);
sys/dev/drm/radeon/rs600.c
231
WREG32(voltage->gpio.reg, tmp);
sys/dev/drm/radeon/rs600.c
235
tmp = RREG32(voltage->gpio.reg);
sys/dev/drm/radeon/rs600.c
237
tmp &= ~voltage->gpio.mask;
sys/dev/drm/radeon/rs600.c
239
tmp |= voltage->gpio.mask;
sys/dev/drm/radeon/rs600.c
240
WREG32(voltage->gpio.reg, tmp);
sys/dev/drm/radeon/rs600.c
315
u32 tmp;
sys/dev/drm/radeon/rs600.c
321
tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
sys/dev/drm/radeon/rs600.c
322
tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
sys/dev/drm/radeon/rs600.c
323
WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/drm/radeon/rs600.c
333
u32 tmp;
sys/dev/drm/radeon/rs600.c
339
tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
sys/dev/drm/radeon/rs600.c
340
tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
sys/dev/drm/radeon/rs600.c
341
WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
sys/dev/drm/radeon/rs600.c
349
u32 tmp;
sys/dev/drm/radeon/rs600.c
354
tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
sys/dev/drm/radeon/rs600.c
355
if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
sys/dev/drm/radeon/rs600.c
359
tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
sys/dev/drm/radeon/rs600.c
360
if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
sys/dev/drm/radeon/rs600.c
372
u32 tmp;
sys/dev/drm/radeon/rs600.c
377
tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
sys/dev/drm/radeon/rs600.c
379
tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
sys/dev/drm/radeon/rs600.c
381
tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
sys/dev/drm/radeon/rs600.c
382
WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
sys/dev/drm/radeon/rs600.c
385
tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
sys/dev/drm/radeon/rs600.c
387
tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
sys/dev/drm/radeon/rs600.c
389
tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
sys/dev/drm/radeon/rs600.c
390
WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
sys/dev/drm/radeon/rs600.c
453
u32 status, tmp;
sys/dev/drm/radeon/rs600.c
466
tmp = RREG32(RADEON_CP_RB_CNTL);
sys/dev/drm/radeon/rs600.c
467
WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
sys/dev/drm/radeon/rs600.c
470
WREG32(RADEON_CP_RB_CNTL, tmp);
sys/dev/drm/radeon/rs600.c
517
uint32_t tmp;
sys/dev/drm/radeon/rs600.c
519
tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
sys/dev/drm/radeon/rs600.c
520
tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
sys/dev/drm/radeon/rs600.c
521
WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
sys/dev/drm/radeon/rs600.c
523
tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
sys/dev/drm/radeon/rs600.c
524
tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
sys/dev/drm/radeon/rs600.c
525
WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
sys/dev/drm/radeon/rs600.c
527
tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
sys/dev/drm/radeon/rs600.c
528
tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
sys/dev/drm/radeon/rs600.c
529
WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
sys/dev/drm/radeon/rs600.c
530
tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
sys/dev/drm/radeon/rs600.c
552
u32 tmp;
sys/dev/drm/radeon/rs600.c
563
tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
sys/dev/drm/radeon/rs600.c
564
WREG32(RADEON_BUS_CNTL, tmp);
sys/dev/drm/radeon/rs600.c
602
tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
sys/dev/drm/radeon/rs600.c
603
WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
sys/dev/drm/radeon/rs600.c
604
tmp = RREG32_MC(R_000009_MC_CNTL1);
sys/dev/drm/radeon/rs600.c
605
WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
sys/dev/drm/radeon/rs600.c
616
u32 tmp;
sys/dev/drm/radeon/rs600.c
620
tmp = RREG32_MC(R_000009_MC_CNTL1);
sys/dev/drm/radeon/rs600.c
621
WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
sys/dev/drm/radeon/rs600.c
656
uint32_t tmp = 0;
sys/dev/drm/radeon/rs600.c
675
tmp |= S_000040_SW_INT_EN(1);
sys/dev/drm/radeon/rs600.c
694
WREG32(R_000040_GEN_INT_CNTL, tmp);
sys/dev/drm/radeon/rs600.c
711
u32 tmp;
sys/dev/drm/radeon/rs600.c
724
tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
sys/dev/drm/radeon/rs600.c
725
tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
sys/dev/drm/radeon/rs600.c
726
WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
sys/dev/drm/radeon/rs600.c
729
tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
sys/dev/drm/radeon/rs600.c
730
tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
sys/dev/drm/radeon/rs600.c
731
WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
sys/dev/drm/radeon/rs600.c
741
tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
sys/dev/drm/radeon/rs600.c
742
tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);
sys/dev/drm/radeon/rs600.c
743
WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);
sys/dev/drm/radeon/rs690.c
102
rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
sys/dev/drm/radeon/rs690.c
104
rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
sys/dev/drm/radeon/rs690.c
126
tmp.full = dfixed_const(4);
sys/dev/drm/radeon/rs690.c
127
rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
sys/dev/drm/radeon/rs690.c
131
tmp.full = dfixed_const(5);
sys/dev/drm/radeon/rs690.c
134
rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
sys/dev/drm/radeon/rs690.c
135
if (tmp.full < rdev->pm.max_bandwidth.full) {
sys/dev/drm/radeon/rs690.c
137
rdev->pm.max_bandwidth.full = tmp.full;
sys/dev/drm/radeon/rs690.c
142
tmp.full = dfixed_const(14);
sys/dev/drm/radeon/rs690.c
143
rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
sys/dev/drm/radeon/rs690.c
144
tmp.full = dfixed_const(10);
sys/dev/drm/radeon/rs690.c
145
rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
sys/dev/drm/radeon/rs690.c
207
u32 tmp;
sys/dev/drm/radeon/rs690.c
226
tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
sys/dev/drm/radeon/rs690.c
227
tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
sys/dev/drm/radeon/rs690.c
232
tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
sys/dev/drm/radeon/rs690.c
234
tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
sys/dev/drm/radeon/rs690.c
237
tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
sys/dev/drm/radeon/rs690.c
239
tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
sys/dev/drm/radeon/rs690.c
241
tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
sys/dev/drm/radeon/rs690.c
243
tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
sys/dev/drm/radeon/rs690.c
245
tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
sys/dev/drm/radeon/rs690.c
247
WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
sys/dev/drm/radeon/rs690.c
38
uint32_t tmp;
sys/dev/drm/radeon/rs690.c
42
tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
sys/dev/drm/radeon/rs690.c
43
if (G_000090_MC_SYSTEM_IDLE(tmp))
sys/dev/drm/radeon/rs690.c
589
u32 tmp;
sys/dev/drm/radeon/rs690.c
609
tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
sys/dev/drm/radeon/rs690.c
610
tmp &= C_000104_MC_DISP0R_INIT_LAT;
sys/dev/drm/radeon/rs690.c
611
tmp &= C_000104_MC_DISP1R_INIT_LAT;
sys/dev/drm/radeon/rs690.c
613
tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
sys/dev/drm/radeon/rs690.c
615
tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
sys/dev/drm/radeon/rs690.c
616
WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
sys/dev/drm/radeon/rs690.c
631
tmp = (wm0_high.lb_request_fifo_depth - 1);
sys/dev/drm/radeon/rs690.c
632
tmp |= (wm1_high.lb_request_fifo_depth - 1) << 16;
sys/dev/drm/radeon/rs690.c
633
WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
sys/dev/drm/radeon/rs690.c
70
fixed20_12 tmp;
sys/dev/drm/radeon/rs690.c
79
tmp.full = dfixed_const(100);
sys/dev/drm/radeon/rs690.c
81
rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
sys/dev/drm/radeon/rs690.c
86
rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
sys/dev/drm/radeon/rs690.c
93
tmp.full = dfixed_const(100);
sys/dev/drm/radeon/rs690.c
95
rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
sys/dev/drm/radeon/rv515.c
1235
u32 tmp;
sys/dev/drm/radeon/rv515.c
1251
tmp = wm0_high.lb_request_fifo_depth;
sys/dev/drm/radeon/rv515.c
1252
tmp |= wm1_high.lb_request_fifo_depth << 16;
sys/dev/drm/radeon/rv515.c
1253
WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
sys/dev/drm/radeon/rv515.c
1272
uint32_t tmp;
sys/dev/drm/radeon/rv515.c
1292
tmp = RREG32_MC(MC_MISC_LAT_TIMER);
sys/dev/drm/radeon/rv515.c
1293
tmp &= ~MC_DISP1R_INIT_LAT_MASK;
sys/dev/drm/radeon/rv515.c
1294
tmp &= ~MC_DISP0R_INIT_LAT_MASK;
sys/dev/drm/radeon/rv515.c
1296
tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
sys/dev/drm/radeon/rv515.c
1298
tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
sys/dev/drm/radeon/rv515.c
1299
WREG32_MC(MC_MISC_LAT_TIMER, tmp);
sys/dev/drm/radeon/rv515.c
132
uint32_t tmp;
sys/dev/drm/radeon/rv515.c
136
tmp = RREG32_MC(MC_STATUS);
sys/dev/drm/radeon/rv515.c
137
if (tmp & MC_STATUS_IDLE) {
sys/dev/drm/radeon/rv515.c
153
unsigned pipe_select_current, gb_pipe_select, tmp;
sys/dev/drm/radeon/rv515.c
161
tmp = RREG32(R300_DST_PIPE_CONFIG);
sys/dev/drm/radeon/rv515.c
162
pipe_select_current = (tmp >> 2) & 3;
sys/dev/drm/radeon/rv515.c
163
tmp = (1 << pipe_select_current) |
sys/dev/drm/radeon/rv515.c
165
WREG32_PLL(0x000D, tmp);
sys/dev/drm/radeon/rv515.c
176
uint32_t tmp;
sys/dev/drm/radeon/rv515.c
180
tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
sys/dev/drm/radeon/rv515.c
181
switch (tmp) {
sys/dev/drm/radeon/rv515.c
237
uint32_t tmp;
sys/dev/drm/radeon/rv515.c
239
tmp = RREG32(GB_PIPE_SELECT);
sys/dev/drm/radeon/rv515.c
240
seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
sys/dev/drm/radeon/rv515.c
241
tmp = RREG32(SU_REG_DEST);
sys/dev/drm/radeon/rv515.c
242
seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
sys/dev/drm/radeon/rv515.c
243
tmp = RREG32(GB_TILE_CONFIG);
sys/dev/drm/radeon/rv515.c
244
seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
sys/dev/drm/radeon/rv515.c
245
tmp = RREG32(DST_PIPE_CONFIG);
sys/dev/drm/radeon/rv515.c
246
seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
sys/dev/drm/radeon/rv515.c
255
uint32_t tmp;
sys/dev/drm/radeon/rv515.c
257
tmp = RREG32(0x2140);
sys/dev/drm/radeon/rv515.c
258
seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
sys/dev/drm/radeon/rv515.c
260
tmp = RREG32(0x425C);
sys/dev/drm/radeon/rv515.c
261
seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
sys/dev/drm/radeon/rv515.c
294
u32 crtc_enabled, tmp, frame_count, blackout;
sys/dev/drm/radeon/rv515.c
307
tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
sys/dev/drm/radeon/rv515.c
308
if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {
sys/dev/drm/radeon/rv515.c
311
tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
sys/dev/drm/radeon/rv515.c
312
WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/drm/radeon/rv515.c
325
tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
sys/dev/drm/radeon/rv515.c
326
tmp &= ~AVIVO_CRTC_EN;
sys/dev/drm/radeon/rv515.c
327
WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/drm/radeon/rv515.c
360
tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
sys/dev/drm/radeon/rv515.c
361
if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) {
sys/dev/drm/radeon/rv515.c
362
tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
sys/dev/drm/radeon/rv515.c
363
WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
sys/dev/drm/radeon/rv515.c
365
tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
sys/dev/drm/radeon/rv515.c
366
if (!(tmp & 1)) {
sys/dev/drm/radeon/rv515.c
367
tmp |= 1;
sys/dev/drm/radeon/rv515.c
368
WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
sys/dev/drm/radeon/rv515.c
376
u32 tmp, frame_count;
sys/dev/drm/radeon/rv515.c
404
tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
sys/dev/drm/radeon/rv515.c
405
if ((tmp & 0x7) != 3) {
sys/dev/drm/radeon/rv515.c
406
tmp &= ~0x7;
sys/dev/drm/radeon/rv515.c
407
tmp |= 0x3;
sys/dev/drm/radeon/rv515.c
408
WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
sys/dev/drm/radeon/rv515.c
410
tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
sys/dev/drm/radeon/rv515.c
411
if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) {
sys/dev/drm/radeon/rv515.c
412
tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
sys/dev/drm/radeon/rv515.c
413
WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
sys/dev/drm/radeon/rv515.c
415
tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
sys/dev/drm/radeon/rv515.c
416
if (tmp & 1) {
sys/dev/drm/radeon/rv515.c
417
tmp &= ~1;
sys/dev/drm/radeon/rv515.c
418
WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
sys/dev/drm/radeon/rv515.c
421
tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
sys/dev/drm/radeon/rv515.c
422
if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0)
sys/dev/drm/radeon/rv515.c
432
tmp = RREG32(R700_MC_CITF_CNTL);
sys/dev/drm/radeon/rv515.c
434
tmp = RREG32(R600_CITF_CNTL);
sys/dev/drm/radeon/rv515.c
435
tmp &= ~R600_BLACKOUT_MASK;
sys/dev/drm/radeon/rv515.c
437
WREG32(R700_MC_CITF_CNTL, tmp);
sys/dev/drm/radeon/rv515.c
439
WREG32(R600_CITF_CNTL, tmp);
sys/dev/drm/radeon/rv515.c
446
tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
sys/dev/drm/radeon/rv515.c
447
tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
sys/dev/drm/radeon/rv515.c
448
WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
sys/dev/drm/radeon/rv6xx_dpm.c
103
u32 tmp;
sys/dev/drm/radeon/rv6xx_dpm.c
105
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL) & ~LC_L0S_INACTIVITY_MASK;
sys/dev/drm/radeon/rv6xx_dpm.c
106
tmp |= LC_L0S_INACTIVITY(3);
sys/dev/drm/radeon/rv6xx_dpm.c
107
WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
sys/dev/drm/radeon/rv6xx_dpm.c
112
u32 tmp;
sys/dev/drm/radeon/rv6xx_dpm.c
114
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL);
sys/dev/drm/radeon/rv6xx_dpm.c
115
tmp &= ~LC_L1_INACTIVITY_MASK;
sys/dev/drm/radeon/rv6xx_dpm.c
116
tmp |= LC_L1_INACTIVITY(4);
sys/dev/drm/radeon/rv6xx_dpm.c
117
tmp &= ~LC_PMI_TO_L1_DIS;
sys/dev/drm/radeon/rv6xx_dpm.c
118
tmp &= ~LC_ASPM_TO_L1_DIS;
sys/dev/drm/radeon/rv6xx_dpm.c
1183
u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
sys/dev/drm/radeon/rv6xx_dpm.c
1185
tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
sys/dev/drm/radeon/rv6xx_dpm.c
1187
tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
sys/dev/drm/radeon/rv6xx_dpm.c
1188
tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/drm/radeon/rv6xx_dpm.c
119
WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
sys/dev/drm/radeon/rv6xx_dpm.c
1190
tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/drm/radeon/rv6xx_dpm.c
1191
tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
sys/dev/drm/radeon/rv6xx_dpm.c
1193
tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/drm/radeon/rv6xx_dpm.c
1194
tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/drm/radeon/rv6xx_dpm.c
1196
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/drm/radeon/rv6xx_dpm.c
124
u32 tmp;
sys/dev/drm/radeon/rv6xx_dpm.c
126
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL) & ~LC_L1_INACTIVITY_MASK;
sys/dev/drm/radeon/rv6xx_dpm.c
127
tmp |= LC_L1_INACTIVITY(8);
sys/dev/drm/radeon/rv6xx_dpm.c
128
WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
sys/dev/drm/radeon/rv6xx_dpm.c
131
tmp = RREG32_PCIE(PCIE_P_CNTL);
sys/dev/drm/radeon/rv6xx_dpm.c
132
tmp |= P_PLL_PWRDN_IN_L1L23;
sys/dev/drm/radeon/rv6xx_dpm.c
133
tmp &= ~P_PLL_BUF_PDNB;
sys/dev/drm/radeon/rv6xx_dpm.c
134
tmp &= ~P_PLL_PDNB;
sys/dev/drm/radeon/rv6xx_dpm.c
135
tmp |= P_ALLOW_PRX_FRONTEND_SHUTOFF;
sys/dev/drm/radeon/rv6xx_dpm.c
136
WREG32_PCIE(PCIE_P_CNTL, tmp);
sys/dev/drm/radeon/rv6xx_dpm.c
413
u32 tmp = 1 << (2 * unit);
sys/dev/drm/radeon/rv6xx_dpm.c
415
return tmp;
sys/dev/drm/radeon/rv6xx_dpm.c
53
u32 tmp;
sys/dev/drm/radeon/rv6xx_dpm.c
56
tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
sys/dev/drm/radeon/rv6xx_dpm.c
57
tmp &= LC_GEN2_EN;
sys/dev/drm/radeon/rv6xx_dpm.c
58
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/drm/radeon/rv6xx_dpm.c
60
tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
sys/dev/drm/radeon/rv6xx_dpm.c
61
tmp |= LC_INITIATE_LINK_SPEED_CHANGE;
sys/dev/drm/radeon/rv6xx_dpm.c
62
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/drm/radeon/rv6xx_dpm.c
70
tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
sys/dev/drm/radeon/rv6xx_dpm.c
71
tmp &= ~LC_INITIATE_LINK_SPEED_CHANGE;
sys/dev/drm/radeon/rv6xx_dpm.c
72
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/drm/radeon/rv6xx_dpm.c
77
u32 tmp;
sys/dev/drm/radeon/rv6xx_dpm.c
786
u32 tmp;
sys/dev/drm/radeon/rv6xx_dpm.c
788
tmp = (RREG32(RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
sys/dev/drm/radeon/rv6xx_dpm.c
789
dram_rows = 1 << (tmp + 10);
sys/dev/drm/radeon/rv6xx_dpm.c
79
tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
sys/dev/drm/radeon/rv6xx_dpm.c
81
if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
sys/dev/drm/radeon/rv6xx_dpm.c
82
(tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
sys/dev/drm/radeon/rv6xx_dpm.c
83
tmp |= LC_GEN2_EN;
sys/dev/drm/radeon/rv6xx_dpm.c
84
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/drm/radeon/rv6xx_dpm.c
91
u32 tmp;
sys/dev/drm/radeon/rv6xx_dpm.c
93
tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
sys/dev/drm/radeon/rv6xx_dpm.c
95
tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
sys/dev/drm/radeon/rv6xx_dpm.c
97
tmp |= LC_HW_VOLTAGE_IF_CONTROL(0);
sys/dev/drm/radeon/rv6xx_dpm.c
98
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/drm/radeon/rv6xx_dpm.c
984
u32 tmp = (DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM) |
sys/dev/drm/radeon/rv6xx_dpm.c
990
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/drm/radeon/rv730_dpm.c
51
u64 tmp;
sys/dev/drm/radeon/rv730_dpm.c
70
tmp = (u64) engine_clock * reference_divider * post_divider * 16384;
sys/dev/drm/radeon/rv730_dpm.c
71
do_div(tmp, reference_clock);
sys/dev/drm/radeon/rv730_dpm.c
72
fbdiv = (u32) tmp;
sys/dev/drm/radeon/rv740_dpm.c
131
u64 tmp;
sys/dev/drm/radeon/rv740_dpm.c
144
tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
sys/dev/drm/radeon/rv740_dpm.c
145
do_div(tmp, reference_clock);
sys/dev/drm/radeon/rv740_dpm.c
146
fbdiv = (u32) tmp;
sys/dev/drm/radeon/rv770.c
1004
u32 tmp;
sys/dev/drm/radeon/rv770.c
1018
tmp = RREG32(HDP_DEBUG1);
sys/dev/drm/radeon/rv770.c
1048
tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
sys/dev/drm/radeon/rv770.c
1049
tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
sys/dev/drm/radeon/rv770.c
1050
WREG32(MC_VM_FB_LOCATION, tmp);
sys/dev/drm/radeon/rv770.c
1133
u32 tmp, i;
sys/dev/drm/radeon/rv770.c
1138
tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
sys/dev/drm/radeon/rv770.c
1139
tmp &= SCLK_MUX_SEL_MASK;
sys/dev/drm/radeon/rv770.c
1140
tmp |= SCLK_MUX_SEL(1) | SCLK_MUX_UPDATE;
sys/dev/drm/radeon/rv770.c
1141
WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
sys/dev/drm/radeon/rv770.c
1149
tmp &= ~SCLK_MUX_UPDATE;
sys/dev/drm/radeon/rv770.c
1150
WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
sys/dev/drm/radeon/rv770.c
1152
tmp = RREG32(MPLL_CNTL_MODE);
sys/dev/drm/radeon/rv770.c
1154
tmp &= ~RV730_MPLL_MCLK_SEL;
sys/dev/drm/radeon/rv770.c
1156
tmp &= ~MPLL_MCLK_SEL;
sys/dev/drm/radeon/rv770.c
1157
WREG32(MPLL_CNTL_MODE, tmp);
sys/dev/drm/radeon/rv770.c
1181
u32 db_debug4, tmp;
sys/dev/drm/radeon/rv770.c
1300
for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) {
sys/dev/drm/radeon/rv770.c
1301
if (!(inactive_pipes & tmp)) {
sys/dev/drm/radeon/rv770.c
1304
tmp <<= 1;
sys/dev/drm/radeon/rv770.c
1313
tmp = rdev->config.rv770.max_simds -
sys/dev/drm/radeon/rv770.c
1315
rdev->config.rv770.active_simds = tmp;
sys/dev/drm/radeon/rv770.c
1335
tmp = 0;
sys/dev/drm/radeon/rv770.c
1337
tmp |= (1 << i);
sys/dev/drm/radeon/rv770.c
1339
if ((disabled_rb_mask & tmp) == tmp) {
sys/dev/drm/radeon/rv770.c
1343
tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
sys/dev/drm/radeon/rv770.c
1344
tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends,
sys/dev/drm/radeon/rv770.c
1346
gb_tiling_config |= tmp << 16;
sys/dev/drm/radeon/rv770.c
1347
rdev->config.rv770.backend_map = tmp;
sys/dev/drm/radeon/rv770.c
1640
u32 tmp;
sys/dev/drm/radeon/rv770.c
1645
tmp = RREG32(MC_ARB_RAMCFG);
sys/dev/drm/radeon/rv770.c
1646
if (tmp & CHANSIZE_OVERRIDE) {
sys/dev/drm/radeon/rv770.c
1648
} else if (tmp & CHANSIZE_MASK) {
sys/dev/drm/radeon/rv770.c
1653
tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/drm/radeon/rv770.c
1654
switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
sys/dev/drm/radeon/rv770.c
2021
u32 link_width_cntl, lanes, speed_cntl, tmp;
sys/dev/drm/radeon/rv770.c
2064
tmp = RREG32(0x541c);
sys/dev/drm/radeon/rv770.c
2065
WREG32(0x541c, tmp | 0x8);
sys/dev/drm/radeon/rv770.c
790
u32 tmp = RREG32(CG_CLKPIN_CNTL);
sys/dev/drm/radeon/rv770.c
792
if (tmp & MUX_TCLK_TO_XCLK)
sys/dev/drm/radeon/rv770.c
795
if (tmp & XTALIN_DIVIDE)
sys/dev/drm/radeon/rv770.c
804
u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
sys/dev/drm/radeon/rv770.c
808
tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
sys/dev/drm/radeon/rv770.c
809
WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
sys/dev/drm/radeon/rv770.c
835
tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
sys/dev/drm/radeon/rv770.c
836
WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
sys/dev/drm/radeon/rv770.c
892
u32 tmp;
sys/dev/drm/radeon/rv770.c
909
tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
sys/dev/drm/radeon/rv770.c
913
WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
sys/dev/drm/radeon/rv770.c
914
WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
sys/dev/drm/radeon/rv770.c
915
WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
sys/dev/drm/radeon/rv770.c
917
WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
sys/dev/drm/radeon/rv770.c
918
WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
sys/dev/drm/radeon/rv770.c
919
WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
sys/dev/drm/radeon/rv770.c
920
WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
sys/dev/drm/radeon/rv770.c
921
WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
sys/dev/drm/radeon/rv770.c
942
u32 tmp;
sys/dev/drm/radeon/rv770.c
955
tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
sys/dev/drm/radeon/rv770.c
956
WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
sys/dev/drm/radeon/rv770.c
957
WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
sys/dev/drm/radeon/rv770.c
958
WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
sys/dev/drm/radeon/rv770.c
959
WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
sys/dev/drm/radeon/rv770.c
960
WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
sys/dev/drm/radeon/rv770.c
961
WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
sys/dev/drm/radeon/rv770.c
962
WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
sys/dev/drm/radeon/rv770.c
976
u32 tmp;
sys/dev/drm/radeon/rv770.c
986
tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
sys/dev/drm/radeon/rv770.c
990
WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
sys/dev/drm/radeon/rv770.c
991
WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
sys/dev/drm/radeon/rv770.c
992
WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
sys/dev/drm/radeon/rv770.c
993
WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
sys/dev/drm/radeon/rv770.c
994
WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
sys/dev/drm/radeon/rv770.c
995
WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
sys/dev/drm/radeon/rv770.c
996
WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
sys/dev/drm/radeon/rv770_dpm.c
100
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL) & ~LC_L0S_INACTIVITY_MASK;
sys/dev/drm/radeon/rv770_dpm.c
101
tmp |= LC_L0S_INACTIVITY(3);
sys/dev/drm/radeon/rv770_dpm.c
102
WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
sys/dev/drm/radeon/rv770_dpm.c
107
u32 tmp;
sys/dev/drm/radeon/rv770_dpm.c
109
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL);
sys/dev/drm/radeon/rv770_dpm.c
110
tmp &= ~LC_L1_INACTIVITY_MASK;
sys/dev/drm/radeon/rv770_dpm.c
111
tmp |= LC_L1_INACTIVITY(4);
sys/dev/drm/radeon/rv770_dpm.c
112
tmp &= ~LC_PMI_TO_L1_DIS;
sys/dev/drm/radeon/rv770_dpm.c
113
tmp &= ~LC_ASPM_TO_L1_DIS;
sys/dev/drm/radeon/rv770_dpm.c
114
WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
sys/dev/drm/radeon/rv770_dpm.c
119
u32 tmp;
sys/dev/drm/radeon/rv770_dpm.c
121
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL) & ~LC_L1_INACTIVITY_MASK;
sys/dev/drm/radeon/rv770_dpm.c
122
tmp |= LC_L1_INACTIVITY(8);
sys/dev/drm/radeon/rv770_dpm.c
123
WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
sys/dev/drm/radeon/rv770_dpm.c
126
tmp = RREG32_PCIE(PCIE_P_CNTL);
sys/dev/drm/radeon/rv770_dpm.c
127
tmp |= P_PLL_PWRDN_IN_L1L23;
sys/dev/drm/radeon/rv770_dpm.c
128
tmp &= ~P_PLL_BUF_PDNB;
sys/dev/drm/radeon/rv770_dpm.c
129
tmp &= ~P_PLL_PDNB;
sys/dev/drm/radeon/rv770_dpm.c
130
tmp |= P_ALLOW_PRX_FRONTEND_SHUTOFF;
sys/dev/drm/radeon/rv770_dpm.c
131
WREG32_PCIE(PCIE_P_CNTL, tmp);
sys/dev/drm/radeon/rv770_dpm.c
1348
u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
sys/dev/drm/radeon/rv770_dpm.c
1350
tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
sys/dev/drm/radeon/rv770_dpm.c
1352
tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
sys/dev/drm/radeon/rv770_dpm.c
1353
tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/drm/radeon/rv770_dpm.c
1355
tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/drm/radeon/rv770_dpm.c
1356
tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
sys/dev/drm/radeon/rv770_dpm.c
1358
tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/drm/radeon/rv770_dpm.c
1359
tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/drm/radeon/rv770_dpm.c
1361
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/drm/radeon/rv770_dpm.c
1597
u32 tmp;
sys/dev/drm/radeon/rv770_dpm.c
1599
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/drm/radeon/rv770_dpm.c
1601
if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
sys/dev/drm/radeon/rv770_dpm.c
1612
u32 tmp;
sys/dev/drm/radeon/rv770_dpm.c
1614
tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
sys/dev/drm/radeon/rv770_dpm.c
1616
if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
sys/dev/drm/radeon/rv770_dpm.c
1617
(tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
sys/dev/drm/radeon/rv770_dpm.c
1623
if (tmp & LC_CURRENT_DATA_RATE)
sys/dev/drm/radeon/rv770_dpm.c
504
u64 tmp;
sys/dev/drm/radeon/rv770_dpm.c
522
tmp = (u64) engine_clock * reference_divider * post_divider * 16384;
sys/dev/drm/radeon/rv770_dpm.c
523
do_div(tmp, reference_clock);
sys/dev/drm/radeon/rv770_dpm.c
524
fbdiv = (u32) tmp;
sys/dev/drm/radeon/rv770_dpm.c
732
u32 tmp;
sys/dev/drm/radeon/rv770_dpm.c
734
tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
sys/dev/drm/radeon/rv770_dpm.c
735
dram_rows = 1 << (tmp + 10);
sys/dev/drm/radeon/rv770_dpm.c
736
tmp = RREG32(MC_SEQ_MISC0) & 3;
sys/dev/drm/radeon/rv770_dpm.c
737
dram_refresh_rate = 1 << (tmp + 3);
sys/dev/drm/radeon/rv770_dpm.c
77
u32 tmp;
sys/dev/drm/radeon/rv770_dpm.c
79
tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
sys/dev/drm/radeon/rv770_dpm.c
81
tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
sys/dev/drm/radeon/rv770_dpm.c
82
tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
sys/dev/drm/radeon/rv770_dpm.c
83
tmp |= LC_GEN2_EN_STRAP;
sys/dev/drm/radeon/rv770_dpm.c
86
tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
sys/dev/drm/radeon/rv770_dpm.c
87
tmp &= ~LC_GEN2_EN_STRAP;
sys/dev/drm/radeon/rv770_dpm.c
884
u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
sys/dev/drm/radeon/rv770_dpm.c
886
tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
sys/dev/drm/radeon/rv770_dpm.c
887
tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) |
sys/dev/drm/radeon/rv770_dpm.c
889
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/drm/radeon/rv770_dpm.c
90
if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
sys/dev/drm/radeon/rv770_dpm.c
91
(tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
sys/dev/drm/radeon/rv770_dpm.c
92
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
sys/dev/drm/radeon/rv770_dpm.c
98
u32 tmp;
sys/dev/drm/radeon/rv770_smc.c
366
u32 tmp, i;
sys/dev/drm/radeon/rv770_smc.c
372
tmp = FIRST_SMC_INT_VECT_REG - smc_first_vector;
sys/dev/drm/radeon/rv770_smc.c
374
if (tmp > byte_count)
sys/dev/drm/radeon/rv770_smc.c
377
byte_count -= tmp;
sys/dev/drm/radeon/rv770_smc.c
378
src += tmp;
sys/dev/drm/radeon/rv770_smc.c
384
tmp = (src[i] << 24) | (src[i + 1] << 16) | (src[i + 2] << 8) | src[i + 3];
sys/dev/drm/radeon/rv770_smc.c
386
WREG32(SMC_ISR_FFD8_FFDB + i, tmp);
sys/dev/drm/radeon/rv770_smc.c
414
u32 tmp;
sys/dev/drm/radeon/rv770_smc.c
416
tmp = RREG32(SMC_IO);
sys/dev/drm/radeon/rv770_smc.c
418
if ((tmp & SMC_RST_N) && (tmp & SMC_CLK_EN))
sys/dev/drm/radeon/rv770_smc.c
426
u32 tmp;
sys/dev/drm/radeon/rv770_smc.c
436
tmp = RREG32(SMC_MSG) & HOST_SMC_RESP_MASK;
sys/dev/drm/radeon/rv770_smc.c
437
tmp >>= HOST_SMC_RESP_SHIFT;
sys/dev/drm/radeon/rv770_smc.c
438
if (tmp != 0)
sys/dev/drm/radeon/rv770_smc.c
443
tmp = RREG32(SMC_MSG) & HOST_SMC_RESP_MASK;
sys/dev/drm/radeon/rv770_smc.c
444
tmp >>= HOST_SMC_RESP_SHIFT;
sys/dev/drm/radeon/rv770_smc.c
446
result = (PPSMC_Result)tmp;
sys/dev/drm/radeon/si.c
1332
u32 tmp;
sys/dev/drm/radeon/si.c
1334
tmp = RREG32(CG_CLKPIN_CNTL_2);
sys/dev/drm/radeon/si.c
1335
if (tmp & MUX_TCLK_TO_XCLK)
sys/dev/drm/radeon/si.c
1338
tmp = RREG32(CG_CLKPIN_CNTL);
sys/dev/drm/radeon/si.c
1339
if (tmp & XTALIN_DIVIDE)
sys/dev/drm/radeon/si.c
1962
u32 tmp, buffer_alloc, i;
sys/dev/drm/radeon/si.c
1979
tmp = 0; /* 1/2 */
sys/dev/drm/radeon/si.c
1982
tmp = 2; /* whole */
sys/dev/drm/radeon/si.c
1986
tmp = 0;
sys/dev/drm/radeon/si.c
1991
DC_LB_MEMORY_CONFIG(tmp));
sys/dev/drm/radeon/si.c
2003
switch (tmp) {
sys/dev/drm/radeon/si.c
2018
u32 tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/drm/radeon/si.c
2020
switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
sys/dev/drm/radeon/si.c
2202
u32 tmp, dmif_size = 12288;
sys/dev/drm/radeon/si.c
2221
tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
sys/dev/drm/radeon/si.c
2222
tmp = min(dfixed_trunc(a), tmp);
sys/dev/drm/radeon/si.c
2224
lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
sys/dev/drm/radeon/si.c
2297
u32 tmp, arb_control3;
sys/dev/drm/radeon/si.c
2422
tmp = arb_control3;
sys/dev/drm/radeon/si.c
2423
tmp &= ~LATENCY_WATERMARK_MASK(3);
sys/dev/drm/radeon/si.c
2424
tmp |= LATENCY_WATERMARK_MASK(1);
sys/dev/drm/radeon/si.c
2425
WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
sys/dev/drm/radeon/si.c
2430
tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
sys/dev/drm/radeon/si.c
2431
tmp &= ~LATENCY_WATERMARK_MASK(3);
sys/dev/drm/radeon/si.c
2432
tmp |= LATENCY_WATERMARK_MASK(2);
sys/dev/drm/radeon/si.c
2433
WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
sys/dev/drm/radeon/si.c
3085
u32 tmp;
sys/dev/drm/radeon/si.c
3199
tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
sys/dev/drm/radeon/si.c
3200
rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
sys/dev/drm/radeon/si.c
3333
tmp = RREG32(HDP_MISC_CNTL);
sys/dev/drm/radeon/si.c
3334
tmp |= HDP_FLUSH_INVALIDATE_CACHE;
sys/dev/drm/radeon/si.c
3335
WREG32(HDP_MISC_CNTL, tmp);
sys/dev/drm/radeon/si.c
3637
u32 tmp;
sys/dev/drm/radeon/si.c
3656
tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
sys/dev/drm/radeon/si.c
3658
tmp |= BUF_SWAP_32BIT;
sys/dev/drm/radeon/si.c
3660
WREG32(CP_RB0_CNTL, tmp);
sys/dev/drm/radeon/si.c
3663
WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
sys/dev/drm/radeon/si.c
3674
tmp |= RB_NO_UPDATE;
sys/dev/drm/radeon/si.c
3679
WREG32(CP_RB0_CNTL, tmp);
sys/dev/drm/radeon/si.c
3687
tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
sys/dev/drm/radeon/si.c
3689
tmp |= BUF_SWAP_32BIT;
sys/dev/drm/radeon/si.c
3691
WREG32(CP_RB1_CNTL, tmp);
sys/dev/drm/radeon/si.c
3694
WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
sys/dev/drm/radeon/si.c
3703
WREG32(CP_RB1_CNTL, tmp);
sys/dev/drm/radeon/si.c
3711
tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
sys/dev/drm/radeon/si.c
3713
tmp |= BUF_SWAP_32BIT;
sys/dev/drm/radeon/si.c
3715
WREG32(CP_RB2_CNTL, tmp);
sys/dev/drm/radeon/si.c
3718
WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
sys/dev/drm/radeon/si.c
3727
WREG32(CP_RB2_CNTL, tmp);
sys/dev/drm/radeon/si.c
3763
u32 tmp;
sys/dev/drm/radeon/si.c
3766
tmp = RREG32(GRBM_STATUS);
sys/dev/drm/radeon/si.c
3767
if (tmp & (PA_BUSY | SC_BUSY |
sys/dev/drm/radeon/si.c
3775
if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
sys/dev/drm/radeon/si.c
3779
if (tmp & GRBM_EE_BUSY)
sys/dev/drm/radeon/si.c
3783
tmp = RREG32(GRBM_STATUS2);
sys/dev/drm/radeon/si.c
3784
if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
sys/dev/drm/radeon/si.c
3788
tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
sys/dev/drm/radeon/si.c
3789
if (!(tmp & DMA_IDLE))
sys/dev/drm/radeon/si.c
3793
tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
sys/dev/drm/radeon/si.c
3794
if (!(tmp & DMA_IDLE))
sys/dev/drm/radeon/si.c
3798
tmp = RREG32(SRBM_STATUS2);
sys/dev/drm/radeon/si.c
3799
if (tmp & DMA_BUSY)
sys/dev/drm/radeon/si.c
3802
if (tmp & DMA1_BUSY)
sys/dev/drm/radeon/si.c
3806
tmp = RREG32(SRBM_STATUS);
sys/dev/drm/radeon/si.c
3808
if (tmp & IH_BUSY)
sys/dev/drm/radeon/si.c
3811
if (tmp & SEM_BUSY)
sys/dev/drm/radeon/si.c
3814
if (tmp & GRBM_RQ_PENDING)
sys/dev/drm/radeon/si.c
3817
if (tmp & VMC_BUSY)
sys/dev/drm/radeon/si.c
3820
if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
sys/dev/drm/radeon/si.c
3828
tmp = RREG32(VM_L2_STATUS);
sys/dev/drm/radeon/si.c
3829
if (tmp & L2_BUSY)
sys/dev/drm/radeon/si.c
3845
u32 tmp;
sys/dev/drm/radeon/si.c
3870
tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
sys/dev/drm/radeon/si.c
3871
tmp &= ~DMA_RB_ENABLE;
sys/dev/drm/radeon/si.c
3872
WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
sys/dev/drm/radeon/si.c
3876
tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
sys/dev/drm/radeon/si.c
3877
tmp &= ~DMA_RB_ENABLE;
sys/dev/drm/radeon/si.c
3878
WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
sys/dev/drm/radeon/si.c
3937
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/si.c
3938
tmp |= grbm_soft_reset;
sys/dev/drm/radeon/si.c
3939
dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/radeon/si.c
3940
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/drm/radeon/si.c
3941
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/si.c
3945
tmp &= ~grbm_soft_reset;
sys/dev/drm/radeon/si.c
3946
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/drm/radeon/si.c
3947
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/si.c
3951
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/si.c
3952
tmp |= srbm_soft_reset;
sys/dev/drm/radeon/si.c
3953
dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
sys/dev/drm/radeon/si.c
3954
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/drm/radeon/si.c
3955
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/si.c
3959
tmp &= ~srbm_soft_reset;
sys/dev/drm/radeon/si.c
3960
WREG32(SRBM_SOFT_RESET, tmp);
sys/dev/drm/radeon/si.c
3961
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/si.c
3975
u32 tmp, i;
sys/dev/drm/radeon/si.c
3977
tmp = RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/drm/radeon/si.c
3978
tmp |= SPLL_BYPASS_EN;
sys/dev/drm/radeon/si.c
3979
WREG32(CG_SPLL_FUNC_CNTL, tmp);
sys/dev/drm/radeon/si.c
3981
tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
sys/dev/drm/radeon/si.c
3982
tmp |= SPLL_CTLREQ_CHG;
sys/dev/drm/radeon/si.c
3983
WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
sys/dev/drm/radeon/si.c
3991
tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
sys/dev/drm/radeon/si.c
3992
tmp &= ~(SPLL_CTLREQ_CHG | SCLK_MUX_UPDATE);
sys/dev/drm/radeon/si.c
3993
WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
sys/dev/drm/radeon/si.c
3995
tmp = RREG32(MPLL_CNTL_MODE);
sys/dev/drm/radeon/si.c
3996
tmp &= ~MPLL_MCLK_SEL;
sys/dev/drm/radeon/si.c
3997
WREG32(MPLL_CNTL_MODE, tmp);
sys/dev/drm/radeon/si.c
4002
u32 tmp;
sys/dev/drm/radeon/si.c
4004
tmp = RREG32(SPLL_CNTL_MODE);
sys/dev/drm/radeon/si.c
4005
tmp |= SPLL_SW_DIR_CONTROL;
sys/dev/drm/radeon/si.c
4006
WREG32(SPLL_CNTL_MODE, tmp);
sys/dev/drm/radeon/si.c
4008
tmp = RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/drm/radeon/si.c
4009
tmp |= SPLL_RESET;
sys/dev/drm/radeon/si.c
4010
WREG32(CG_SPLL_FUNC_CNTL, tmp);
sys/dev/drm/radeon/si.c
4012
tmp = RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/drm/radeon/si.c
4013
tmp |= SPLL_SLEEP;
sys/dev/drm/radeon/si.c
4014
WREG32(CG_SPLL_FUNC_CNTL, tmp);
sys/dev/drm/radeon/si.c
4016
tmp = RREG32(SPLL_CNTL_MODE);
sys/dev/drm/radeon/si.c
4017
tmp &= ~SPLL_SW_DIR_CONTROL;
sys/dev/drm/radeon/si.c
4018
WREG32(SPLL_CNTL_MODE, tmp);
sys/dev/drm/radeon/si.c
4024
u32 tmp, i;
sys/dev/drm/radeon/si.c
4037
tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
sys/dev/drm/radeon/si.c
4038
tmp &= ~DMA_RB_ENABLE;
sys/dev/drm/radeon/si.c
4039
WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
sys/dev/drm/radeon/si.c
4041
tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
sys/dev/drm/radeon/si.c
4042
tmp &= ~DMA_RB_ENABLE;
sys/dev/drm/radeon/si.c
4043
WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
sys/dev/drm/radeon/si.c
4130
u32 tmp;
sys/dev/drm/radeon/si.c
4157
tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
sys/dev/drm/radeon/si.c
4158
tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
sys/dev/drm/radeon/si.c
4159
WREG32(MC_VM_FB_LOCATION, tmp);
sys/dev/drm/radeon/si.c
4194
u32 tmp;
sys/dev/drm/radeon/si.c
4199
tmp = RREG32(MC_ARB_RAMCFG);
sys/dev/drm/radeon/si.c
4200
if (tmp & CHANSIZE_OVERRIDE) {
sys/dev/drm/radeon/si.c
4202
} else if (tmp & CHANSIZE_MASK) {
sys/dev/drm/radeon/si.c
4207
tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/drm/radeon/si.c
4208
switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
sys/dev/drm/radeon/si.c
4243
tmp = RREG32(CONFIG_MEMSIZE);
sys/dev/drm/radeon/si.c
4245
if (tmp & 0xffff0000) {
sys/dev/drm/radeon/si.c
4246
DRM_INFO("Probable bad vram size: 0x%08x\n", tmp);
sys/dev/drm/radeon/si.c
4247
if (tmp & 0xffff)
sys/dev/drm/radeon/si.c
4248
tmp &= 0xffff;
sys/dev/drm/radeon/si.c
4250
rdev->mc.mc_vram_size = tmp * 1024ULL * 1024ULL;
sys/dev/drm/radeon/si.c
5134
u32 tmp = RREG32(CP_INT_CNTL_RING0);
sys/dev/drm/radeon/si.c
5139
tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
sys/dev/drm/radeon/si.c
5141
tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
sys/dev/drm/radeon/si.c
5142
WREG32(CP_INT_CNTL_RING0, tmp);
sys/dev/drm/radeon/si.c
5146
tmp = RREG32(DB_DEPTH_INFO);
sys/dev/drm/radeon/si.c
5160
u32 tmp, tmp2;
sys/dev/drm/radeon/si.c
5162
tmp = RREG32(UVD_CGC_CTRL);
sys/dev/drm/radeon/si.c
5163
tmp &= ~(CLK_OD_MASK | CG_DT_MASK);
sys/dev/drm/radeon/si.c
5164
tmp |= DCM | CG_DT(1) | CLK_OD(4);
sys/dev/drm/radeon/si.c
5167
tmp &= ~0x7ffff800;
sys/dev/drm/radeon/si.c
5170
tmp |= 0x7ffff800;
sys/dev/drm/radeon/si.c
5174
WREG32(UVD_CGC_CTRL, tmp);
sys/dev/drm/radeon/si.c
5185
u32 tmp = RREG32(UVD_CGC_CTRL);
sys/dev/drm/radeon/si.c
5186
tmp &= ~DCM;
sys/dev/drm/radeon/si.c
5187
WREG32(UVD_CGC_CTRL, tmp);
sys/dev/drm/radeon/si.c
5209
u32 tmp;
sys/dev/drm/radeon/si.c
5211
tmp = RREG32(RLC_CNTL);
sys/dev/drm/radeon/si.c
5212
if (tmp != rlc)
sys/dev/drm/radeon/si.c
5231
u32 tmp;
sys/dev/drm/radeon/si.c
5236
for (tmp = 0; tmp < 5; tmp++)
sys/dev/drm/radeon/si.c
5243
u32 tmp;
sys/dev/drm/radeon/si.c
5246
tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10);
sys/dev/drm/radeon/si.c
5247
WREG32(RLC_TTOP_D, tmp);
sys/dev/drm/radeon/si.c
5249
tmp = RREG32(RLC_PG_CNTL);
sys/dev/drm/radeon/si.c
5250
tmp |= GFX_PG_ENABLE;
sys/dev/drm/radeon/si.c
5251
WREG32(RLC_PG_CNTL, tmp);
sys/dev/drm/radeon/si.c
5253
tmp = RREG32(RLC_AUTO_PG_CTRL);
sys/dev/drm/radeon/si.c
5254
tmp |= AUTO_PG_EN;
sys/dev/drm/radeon/si.c
5255
WREG32(RLC_AUTO_PG_CTRL, tmp);
sys/dev/drm/radeon/si.c
5257
tmp = RREG32(RLC_AUTO_PG_CTRL);
sys/dev/drm/radeon/si.c
5258
tmp &= ~AUTO_PG_EN;
sys/dev/drm/radeon/si.c
5259
WREG32(RLC_AUTO_PG_CTRL, tmp);
sys/dev/drm/radeon/si.c
5261
tmp = RREG32(DB_RENDER_CONTROL);
sys/dev/drm/radeon/si.c
5267
u32 tmp;
sys/dev/drm/radeon/si.c
5271
tmp = RREG32(RLC_PG_CNTL);
sys/dev/drm/radeon/si.c
5272
tmp |= GFX_PG_SRC;
sys/dev/drm/radeon/si.c
5273
WREG32(RLC_PG_CNTL, tmp);
sys/dev/drm/radeon/si.c
5277
tmp = RREG32(RLC_AUTO_PG_CTRL);
sys/dev/drm/radeon/si.c
5279
tmp &= ~GRBM_REG_SGIT_MASK;
sys/dev/drm/radeon/si.c
5280
tmp |= GRBM_REG_SGIT(0x700);
sys/dev/drm/radeon/si.c
5281
tmp &= ~PG_AFTER_GRBM_REG_ST_MASK;
sys/dev/drm/radeon/si.c
5282
WREG32(RLC_AUTO_PG_CTRL, tmp);
sys/dev/drm/radeon/si.c
5287
u32 mask = 0, tmp, tmp1;
sys/dev/drm/radeon/si.c
5291
tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
sys/dev/drm/radeon/si.c
5295
tmp &= 0xffff0000;
sys/dev/drm/radeon/si.c
5297
tmp |= tmp1;
sys/dev/drm/radeon/si.c
5298
tmp >>= 16;
sys/dev/drm/radeon/si.c
5305
return (~tmp) & mask;
sys/dev/drm/radeon/si.c
5312
u32 tmp = 0;
sys/dev/drm/radeon/si.c
5329
tmp |= (cu_bitmap << (i * 16 + j * 8));
sys/dev/drm/radeon/si.c
5333
WREG32(RLC_PG_AO_CU_MASK, tmp);
sys/dev/drm/radeon/si.c
5335
tmp = RREG32(RLC_MAX_PG_CU);
sys/dev/drm/radeon/si.c
5336
tmp &= ~MAX_PU_CU_MASK;
sys/dev/drm/radeon/si.c
5337
tmp |= MAX_PU_CU(active_cu_number);
sys/dev/drm/radeon/si.c
5338
WREG32(RLC_MAX_PG_CU, tmp);
sys/dev/drm/radeon/si.c
5344
u32 data, orig, tmp;
sys/dev/drm/radeon/si.c
5353
tmp = si_halt_rlc(rdev);
sys/dev/drm/radeon/si.c
5361
si_update_rlc(rdev, tmp);
sys/dev/drm/radeon/si.c
5384
u32 data, orig, tmp = 0;
sys/dev/drm/radeon/si.c
5404
tmp = si_halt_rlc(rdev);
sys/dev/drm/radeon/si.c
5410
si_update_rlc(rdev, tmp);
sys/dev/drm/radeon/si.c
5427
tmp = si_halt_rlc(rdev);
sys/dev/drm/radeon/si.c
5433
si_update_rlc(rdev, tmp);
sys/dev/drm/radeon/si.c
5440
u32 orig, data, tmp;
sys/dev/drm/radeon/si.c
5443
tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
sys/dev/drm/radeon/si.c
5444
tmp |= 0x3fff;
sys/dev/drm/radeon/si.c
5445
WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, tmp);
sys/dev/drm/radeon/si.c
5455
tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
sys/dev/drm/radeon/si.c
5456
tmp &= ~0x3fff;
sys/dev/drm/radeon/si.c
5457
WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, tmp);
sys/dev/drm/radeon/si.c
5795
u32 tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/si.c
5797
tmp |= SOFT_RESET_RLC;
sys/dev/drm/radeon/si.c
5798
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/drm/radeon/si.c
5800
tmp &= ~SOFT_RESET_RLC;
sys/dev/drm/radeon/si.c
5801
WREG32(GRBM_SOFT_RESET, tmp);
sys/dev/drm/radeon/si.c
5825
u32 tmp;
sys/dev/drm/radeon/si.c
5828
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/drm/radeon/si.c
5829
if ((tmp & 0xF0000000) == 0xB0000000)
sys/dev/drm/radeon/si.c
5836
u32 tmp;
sys/dev/drm/radeon/si.c
5838
tmp = RREG32(RLC_LB_CNTL);
sys/dev/drm/radeon/si.c
5840
tmp |= LOAD_BALANCE_ENABLE;
sys/dev/drm/radeon/si.c
5842
tmp &= ~LOAD_BALANCE_ENABLE;
sys/dev/drm/radeon/si.c
5843
WREG32(RLC_LB_CNTL, tmp);
sys/dev/drm/radeon/si.c
5937
u32 tmp;
sys/dev/drm/radeon/si.c
5939
tmp = RREG32(CP_INT_CNTL_RING0) &
sys/dev/drm/radeon/si.c
5941
WREG32(CP_INT_CNTL_RING0, tmp);
sys/dev/drm/radeon/si.c
5944
tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
sys/dev/drm/radeon/si.c
5945
WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp);
sys/dev/drm/radeon/si.c
5946
tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
sys/dev/drm/radeon/si.c
5947
WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
sys/dev/drm/radeon/si.c
6198
u32 wptr, tmp;
sys/dev/drm/radeon/si.c
6214
tmp = RREG32(IH_RB_CNTL);
sys/dev/drm/radeon/si.c
6215
tmp |= IH_WPTR_OVERFLOW_CLEAR;
sys/dev/drm/radeon/si.c
6216
WREG32(IH_RB_CNTL, tmp);
sys/dev/drm/radeon/si.c
7142
u32 max_lw, current_lw, tmp;
sys/dev/drm/radeon/si.c
7153
tmp = RREG32_PCIE(PCIE_LC_STATUS1);
sys/dev/drm/radeon/si.c
7154
max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
sys/dev/drm/radeon/si.c
7155
current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
sys/dev/drm/radeon/si.c
7158
tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
sys/dev/drm/radeon/si.c
7159
if (tmp & LC_RENEGOTIATION_SUPPORT) {
sys/dev/drm/radeon/si.c
7160
tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
sys/dev/drm/radeon/si.c
7161
tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
sys/dev/drm/radeon/si.c
7162
tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
sys/dev/drm/radeon/si.c
7163
WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
sys/dev/drm/radeon/si.c
7179
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
sys/dev/drm/radeon/si.c
7180
tmp |= LC_SET_QUIESCE;
sys/dev/drm/radeon/si.c
7181
WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
sys/dev/drm/radeon/si.c
7183
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
sys/dev/drm/radeon/si.c
7184
tmp |= LC_REDO_EQ;
sys/dev/drm/radeon/si.c
7185
WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
sys/dev/drm/radeon/si.c
7211
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
sys/dev/drm/radeon/si.c
7212
tmp &= ~LC_SET_QUIESCE;
sys/dev/drm/radeon/si.c
7213
WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
sys/dev/drm/radeon/si_dpm.c
1776
s64 tmp;
sys/dev/drm/radeon/si_dpm.c
1788
tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
sys/dev/drm/radeon/si_dpm.c
1789
kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
sys/dev/drm/radeon/si_dpm.c
1790
kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
sys/dev/drm/radeon/si_dpm.c
2856
u32 tmp;
sys/dev/drm/radeon/si_dpm.c
2892
tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
sys/dev/drm/radeon/si_dpm.c
2894
spll_table->freq[i] = cpu_to_be32(tmp);
sys/dev/drm/radeon/si_dpm.c
2896
tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
sys/dev/drm/radeon/si_dpm.c
2898
spll_table->ss[i] = cpu_to_be32(tmp);
sys/dev/drm/radeon/si_dpm.c
3210
u32 tmp, width, row, column, bank, density;
sys/dev/drm/radeon/si_dpm.c
3213
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/drm/radeon/si_dpm.c
3214
is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
sys/dev/drm/radeon/si_dpm.c
3215
is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
sys/dev/drm/radeon/si_dpm.c
3216
& (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
sys/dev/drm/radeon/si_dpm.c
3221
tmp = RREG32(MC_ARB_RAMCFG);
sys/dev/drm/radeon/si_dpm.c
3222
row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
sys/dev/drm/radeon/si_dpm.c
3223
column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
sys/dev/drm/radeon/si_dpm.c
3224
bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
sys/dev/drm/radeon/si_dpm.c
3483
u32 tmp;
sys/dev/drm/radeon/si_dpm.c
3489
&tmp, si_pi->sram_end);
sys/dev/drm/radeon/si_dpm.c
3493
si_pi->state_table_start = tmp;
sys/dev/drm/radeon/si_dpm.c
3498
&tmp, si_pi->sram_end);
sys/dev/drm/radeon/si_dpm.c
3502
si_pi->soft_regs_start = tmp;
sys/dev/drm/radeon/si_dpm.c
3507
&tmp, si_pi->sram_end);
sys/dev/drm/radeon/si_dpm.c
3511
si_pi->mc_reg_table_start = tmp;
sys/dev/drm/radeon/si_dpm.c
3516
&tmp, si_pi->sram_end);
sys/dev/drm/radeon/si_dpm.c
3520
si_pi->fan_table_start = tmp;
sys/dev/drm/radeon/si_dpm.c
3525
&tmp, si_pi->sram_end);
sys/dev/drm/radeon/si_dpm.c
3529
si_pi->arb_table_start = tmp;
sys/dev/drm/radeon/si_dpm.c
3534
&tmp, si_pi->sram_end);
sys/dev/drm/radeon/si_dpm.c
3538
si_pi->cac_table_start = tmp;
sys/dev/drm/radeon/si_dpm.c
3543
&tmp, si_pi->sram_end);
sys/dev/drm/radeon/si_dpm.c
3547
si_pi->dte_table_start = tmp;
sys/dev/drm/radeon/si_dpm.c
3552
&tmp, si_pi->sram_end);
sys/dev/drm/radeon/si_dpm.c
3556
si_pi->spll_table_start = tmp;
sys/dev/drm/radeon/si_dpm.c
3561
&tmp, si_pi->sram_end);
sys/dev/drm/radeon/si_dpm.c
3565
si_pi->papm_cfg_table_start = tmp;
sys/dev/drm/radeon/si_dpm.c
3675
u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
sys/dev/drm/radeon/si_dpm.c
3678
WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
sys/dev/drm/radeon/si_dpm.c
3686
u32 tmp, pipe;
sys/dev/drm/radeon/si_dpm.c
3689
tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
sys/dev/drm/radeon/si_dpm.c
3691
tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
sys/dev/drm/radeon/si_dpm.c
3693
tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/drm/radeon/si_dpm.c
3696
tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
sys/dev/drm/radeon/si_dpm.c
3698
tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
sys/dev/drm/radeon/si_dpm.c
3700
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/drm/radeon/si_dpm.c
3702
tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
sys/dev/drm/radeon/si_dpm.c
3703
pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
sys/dev/drm/radeon/si_dpm.c
3717
tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
sys/dev/drm/radeon/si_dpm.c
3718
tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
sys/dev/drm/radeon/si_dpm.c
3719
WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
sys/dev/drm/radeon/si_dpm.c
3803
u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
sys/dev/drm/radeon/si_dpm.c
3805
tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
sys/dev/drm/radeon/si_dpm.c
3806
tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
sys/dev/drm/radeon/si_dpm.c
3809
tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
sys/dev/drm/radeon/si_dpm.c
3810
tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
sys/dev/drm/radeon/si_dpm.c
3812
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
sys/dev/drm/radeon/si_dpm.c
4233
u32 tmp;
sys/dev/drm/radeon/si_dpm.c
4236
ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
sys/dev/drm/radeon/si_dpm.c
4240
tmp &= 0x00FFFFFF;
sys/dev/drm/radeon/si_dpm.c
4241
tmp |= MC_CG_ARB_FREQ_F1 << 24;
sys/dev/drm/radeon/si_dpm.c
4243
return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end);
sys/dev/drm/radeon/si_dpm.c
4260
u32 tmp;
sys/dev/drm/radeon/si_dpm.c
4264
&tmp, si_pi->sram_end);
sys/dev/drm/radeon/si_dpm.c
4268
tmp = (tmp >> 24) & 0xff;
sys/dev/drm/radeon/si_dpm.c
4270
if (tmp == MC_CG_ARB_FREQ_F0)
sys/dev/drm/radeon/si_dpm.c
4273
return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
sys/dev/drm/radeon/si_dpm.c
4282
u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
sys/dev/drm/radeon/si_dpm.c
4284
if (tmp >= 4)
sys/dev/drm/radeon/si_dpm.c
4287
dram_rows = 1 << (tmp + 10);
sys/dev/drm/radeon/si_dpm.c
4797
u64 tmp;
sys/dev/drm/radeon/si_dpm.c
4810
tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
sys/dev/drm/radeon/si_dpm.c
4811
do_div(tmp, reference_clock);
sys/dev/drm/radeon/si_dpm.c
4812
fbdiv = (u32) tmp;
sys/dev/drm/radeon/si_dpm.c
4919
u32 tmp;
sys/dev/drm/radeon/si_dpm.c
4927
tmp = freq_nom / reference_clock;
sys/dev/drm/radeon/si_dpm.c
4928
tmp = tmp * tmp;
sys/dev/drm/radeon/si_dpm.c
4932
u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
sys/dev/drm/radeon/si_dpm.c
6011
u32 tmp;
sys/dev/drm/radeon/si_dpm.c
6014
tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
sys/dev/drm/radeon/si_dpm.c
6015
si_pi->fan_ctrl_default_mode = tmp;
sys/dev/drm/radeon/si_dpm.c
6016
tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
sys/dev/drm/radeon/si_dpm.c
6017
si_pi->t_min = tmp;
sys/dev/drm/radeon/si_dpm.c
6021
tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
sys/dev/drm/radeon/si_dpm.c
6022
tmp |= TMIN(0);
sys/dev/drm/radeon/si_dpm.c
6023
WREG32(CG_FDO_CTRL2, tmp);
sys/dev/drm/radeon/si_dpm.c
6025
tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
sys/dev/drm/radeon/si_dpm.c
6026
tmp |= FDO_PWM_MODE(mode);
sys/dev/drm/radeon/si_dpm.c
6027
WREG32(CG_FDO_CTRL2, tmp);
sys/dev/drm/radeon/si_dpm.c
6037
u32 reference_clock, tmp;
sys/dev/drm/radeon/si_dpm.c
6090
tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
sys/dev/drm/radeon/si_dpm.c
6091
fan_table.temp_src = (uint8_t)tmp;
sys/dev/drm/radeon/si_dpm.c
6165
u32 tmp;
sys/dev/drm/radeon/si_dpm.c
6187
tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
sys/dev/drm/radeon/si_dpm.c
6188
tmp |= FDO_STATIC_DUTY(duty);
sys/dev/drm/radeon/si_dpm.c
6189
WREG32(CG_FDO_CTRL0, tmp);
sys/dev/drm/radeon/si_dpm.c
6213
u32 tmp;
sys/dev/drm/radeon/si_dpm.c
6218
tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
sys/dev/drm/radeon/si_dpm.c
6219
return (tmp >> FDO_PWM_MODE_SHIFT);
sys/dev/drm/radeon/si_dpm.c
6247
u32 tach_period, tmp;
sys/dev/drm/radeon/si_dpm.c
6264
tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
sys/dev/drm/radeon/si_dpm.c
6265
tmp |= TARGET_PERIOD(tach_period);
sys/dev/drm/radeon/si_dpm.c
6266
WREG32(CG_TACH_CTRL, tmp);
sys/dev/drm/radeon/si_dpm.c
6277
u32 tmp;
sys/dev/drm/radeon/si_dpm.c
6280
tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
sys/dev/drm/radeon/si_dpm.c
6281
tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
sys/dev/drm/radeon/si_dpm.c
6282
WREG32(CG_FDO_CTRL2, tmp);
sys/dev/drm/radeon/si_dpm.c
6284
tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
sys/dev/drm/radeon/si_dpm.c
6285
tmp |= TMIN(si_pi->t_min);
sys/dev/drm/radeon/si_dpm.c
6286
WREG32(CG_FDO_CTRL2, tmp);
sys/dev/drm/radeon/si_dpm.c
6301
u32 tmp;
sys/dev/drm/radeon/si_dpm.c
6304
tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
sys/dev/drm/radeon/si_dpm.c
6305
tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
sys/dev/drm/radeon/si_dpm.c
6306
WREG32(CG_TACH_CTRL, tmp);
sys/dev/drm/radeon/si_dpm.c
6309
tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
sys/dev/drm/radeon/si_dpm.c
6310
tmp |= TACH_PWM_RESP_RATE(0x28);
sys/dev/drm/radeon/si_dpm.c
6311
WREG32(CG_FDO_CTRL2, tmp);
sys/dev/drm/radeon/si_smc.c
115
u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
sys/dev/drm/radeon/si_smc.c
117
tmp &= ~RST_REG;
sys/dev/drm/radeon/si_smc.c
119
WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
sys/dev/drm/radeon/si_smc.c
124
u32 tmp;
sys/dev/drm/radeon/si_smc.c
131
tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
sys/dev/drm/radeon/si_smc.c
132
tmp |= RST_REG;
sys/dev/drm/radeon/si_smc.c
133
WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
sys/dev/drm/radeon/si_smc.c
145
u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
sys/dev/drm/radeon/si_smc.c
147
tmp |= CK_DISABLE;
sys/dev/drm/radeon/si_smc.c
149
WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
sys/dev/drm/radeon/si_smc.c
154
u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
sys/dev/drm/radeon/si_smc.c
156
tmp &= ~CK_DISABLE;
sys/dev/drm/radeon/si_smc.c
158
WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
sys/dev/drm/radeon/si_smc.c
174
u32 tmp;
sys/dev/drm/radeon/si_smc.c
183
tmp = RREG32(SMC_RESP_0);
sys/dev/drm/radeon/si_smc.c
184
if (tmp != 0)
sys/dev/drm/radeon/si_smc.c
188
tmp = RREG32(SMC_RESP_0);
sys/dev/drm/radeon/si_smc.c
190
return (PPSMC_Result)tmp;
sys/dev/drm/radeon/si_smc.c
195
u32 tmp;
sys/dev/drm/radeon/si_smc.c
202
tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
sys/dev/drm/radeon/si_smc.c
203
if ((tmp & CKEN) == 0)
sys/dev/drm/radeon/trinity_dpm.c
944
u32 tmp = RREG32(CG_MISC_REG);
sys/dev/drm/radeon/trinity_dpm.c
945
tmp &= 0xfffffffd;
sys/dev/drm/radeon/trinity_dpm.c
946
WREG32(CG_MISC_REG, tmp);
sys/dev/drm/radeon/uvd_v1_0.c
160
uint32_t tmp;
sys/dev/drm/radeon/uvd_v1_0.c
186
tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
sys/dev/drm/radeon/uvd_v1_0.c
187
radeon_ring_write(ring, tmp);
sys/dev/drm/radeon/uvd_v1_0.c
190
tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
sys/dev/drm/radeon/uvd_v1_0.c
191
radeon_ring_write(ring, tmp);
sys/dev/drm/radeon/uvd_v1_0.c
194
tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
sys/dev/drm/radeon/uvd_v1_0.c
195
radeon_ring_write(ring, tmp);
sys/dev/drm/radeon/uvd_v1_0.c
423
uint32_t tmp = 0;
sys/dev/drm/radeon/uvd_v1_0.c
438
tmp = RREG32(UVD_CONTEXT_ID);
sys/dev/drm/radeon/uvd_v1_0.c
439
if (tmp == 0xDEADBEEF)
sys/dev/drm/radeon/uvd_v1_0.c
449
ring->idx, tmp);
sys/dev/drm/radeon/vce_v1_0.c
105
u32 tmp;
sys/dev/drm/radeon/vce_v1_0.c
108
tmp = RREG32(VCE_CLOCK_GATING_A);
sys/dev/drm/radeon/vce_v1_0.c
109
tmp |= CGC_DYN_CLOCK_MODE;
sys/dev/drm/radeon/vce_v1_0.c
110
WREG32(VCE_CLOCK_GATING_A, tmp);
sys/dev/drm/radeon/vce_v1_0.c
112
tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/drm/radeon/vce_v1_0.c
113
tmp &= ~0x1ff000;
sys/dev/drm/radeon/vce_v1_0.c
114
tmp |= 0xff800000;
sys/dev/drm/radeon/vce_v1_0.c
115
WREG32(VCE_UENC_CLOCK_GATING, tmp);
sys/dev/drm/radeon/vce_v1_0.c
117
tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
sys/dev/drm/radeon/vce_v1_0.c
118
tmp &= ~0x3ff;
sys/dev/drm/radeon/vce_v1_0.c
119
WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
sys/dev/drm/radeon/vce_v1_0.c
121
tmp = RREG32(VCE_CLOCK_GATING_A);
sys/dev/drm/radeon/vce_v1_0.c
122
tmp &= ~CGC_DYN_CLOCK_MODE;
sys/dev/drm/radeon/vce_v1_0.c
123
WREG32(VCE_CLOCK_GATING_A, tmp);
sys/dev/drm/radeon/vce_v1_0.c
125
tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/drm/radeon/vce_v1_0.c
126
tmp |= 0x1ff000;
sys/dev/drm/radeon/vce_v1_0.c
127
tmp &= ~0xff800000;
sys/dev/drm/radeon/vce_v1_0.c
128
WREG32(VCE_UENC_CLOCK_GATING, tmp);
sys/dev/drm/radeon/vce_v1_0.c
130
tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
sys/dev/drm/radeon/vce_v1_0.c
131
tmp |= 0x3ff;
sys/dev/drm/radeon/vce_v1_0.c
132
WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
sys/dev/drm/radeon/vce_v1_0.c
138
u32 tmp;
sys/dev/drm/radeon/vce_v1_0.c
140
tmp = RREG32(VCE_CLOCK_GATING_A);
sys/dev/drm/radeon/vce_v1_0.c
141
tmp |= CGC_DYN_CLOCK_MODE;
sys/dev/drm/radeon/vce_v1_0.c
142
WREG32(VCE_CLOCK_GATING_A, tmp);
sys/dev/drm/radeon/vce_v1_0.c
144
tmp = RREG32(VCE_CLOCK_GATING_B);
sys/dev/drm/radeon/vce_v1_0.c
145
tmp |= 0x1e;
sys/dev/drm/radeon/vce_v1_0.c
146
tmp &= ~0xe100e1;
sys/dev/drm/radeon/vce_v1_0.c
147
WREG32(VCE_CLOCK_GATING_B, tmp);
sys/dev/drm/radeon/vce_v1_0.c
149
tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/drm/radeon/vce_v1_0.c
150
tmp &= ~0xff9ff000;
sys/dev/drm/radeon/vce_v1_0.c
151
WREG32(VCE_UENC_CLOCK_GATING, tmp);
sys/dev/drm/radeon/vce_v1_0.c
153
tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
sys/dev/drm/radeon/vce_v1_0.c
154
tmp &= ~0x3ff;
sys/dev/drm/radeon/vce_v1_0.c
155
WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
sys/dev/drm/radeon/vce_v2_0.c
132
u32 tmp;
sys/dev/drm/radeon/vce_v2_0.c
134
tmp = RREG32(VCE_CLOCK_GATING_A);
sys/dev/drm/radeon/vce_v2_0.c
135
tmp &= ~(CGC_CLK_GATE_DLY_TIMER_MASK | CGC_CLK_GATER_OFF_DLY_TIMER_MASK);
sys/dev/drm/radeon/vce_v2_0.c
136
tmp |= (CGC_CLK_GATE_DLY_TIMER(0) | CGC_CLK_GATER_OFF_DLY_TIMER(4));
sys/dev/drm/radeon/vce_v2_0.c
137
tmp |= CGC_UENC_WAIT_AWAKE;
sys/dev/drm/radeon/vce_v2_0.c
138
WREG32(VCE_CLOCK_GATING_A, tmp);
sys/dev/drm/radeon/vce_v2_0.c
140
tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/drm/radeon/vce_v2_0.c
141
tmp &= ~(CLOCK_ON_DELAY_MASK | CLOCK_OFF_DELAY_MASK);
sys/dev/drm/radeon/vce_v2_0.c
142
tmp |= (CLOCK_ON_DELAY(0) | CLOCK_OFF_DELAY(4));
sys/dev/drm/radeon/vce_v2_0.c
143
WREG32(VCE_UENC_CLOCK_GATING, tmp);
sys/dev/drm/radeon/vce_v2_0.c
145
tmp = RREG32(VCE_CLOCK_GATING_B);
sys/dev/drm/radeon/vce_v2_0.c
146
tmp |= 0x10;
sys/dev/drm/radeon/vce_v2_0.c
147
tmp &= ~0x100000;
sys/dev/drm/radeon/vce_v2_0.c
148
WREG32(VCE_CLOCK_GATING_B, tmp);
sys/dev/drm/radeon/vce_v2_0.c
40
u32 tmp;
sys/dev/drm/radeon/vce_v2_0.c
43
tmp = RREG32(VCE_CLOCK_GATING_B);
sys/dev/drm/radeon/vce_v2_0.c
44
tmp |= 0xe70000;
sys/dev/drm/radeon/vce_v2_0.c
45
WREG32(VCE_CLOCK_GATING_B, tmp);
sys/dev/drm/radeon/vce_v2_0.c
47
tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/drm/radeon/vce_v2_0.c
48
tmp |= 0xff000000;
sys/dev/drm/radeon/vce_v2_0.c
49
WREG32(VCE_UENC_CLOCK_GATING, tmp);
sys/dev/drm/radeon/vce_v2_0.c
51
tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
sys/dev/drm/radeon/vce_v2_0.c
52
tmp &= ~0x3fc;
sys/dev/drm/radeon/vce_v2_0.c
53
WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
sys/dev/drm/radeon/vce_v2_0.c
57
tmp = RREG32(VCE_CLOCK_GATING_B);
sys/dev/drm/radeon/vce_v2_0.c
58
tmp |= 0xe7;
sys/dev/drm/radeon/vce_v2_0.c
59
tmp &= ~0xe70000;
sys/dev/drm/radeon/vce_v2_0.c
60
WREG32(VCE_CLOCK_GATING_B, tmp);
sys/dev/drm/radeon/vce_v2_0.c
62
tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/drm/radeon/vce_v2_0.c
63
tmp |= 0x1fe000;
sys/dev/drm/radeon/vce_v2_0.c
64
tmp &= ~0xff000000;
sys/dev/drm/radeon/vce_v2_0.c
65
WREG32(VCE_UENC_CLOCK_GATING, tmp);
sys/dev/drm/radeon/vce_v2_0.c
67
tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
sys/dev/drm/radeon/vce_v2_0.c
68
tmp |= 0x3fc;
sys/dev/drm/radeon/vce_v2_0.c
69
WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
sys/dev/drm/radeon/vce_v2_0.c
75
u32 orig, tmp;
sys/dev/drm/radeon/vce_v2_0.c
77
tmp = RREG32(VCE_CLOCK_GATING_B);
sys/dev/drm/radeon/vce_v2_0.c
78
tmp &= ~0x00060006;
sys/dev/drm/radeon/vce_v2_0.c
80
tmp |= 0xe10000;
sys/dev/drm/radeon/vce_v2_0.c
82
tmp |= 0xe1;
sys/dev/drm/radeon/vce_v2_0.c
83
tmp &= ~0xe10000;
sys/dev/drm/radeon/vce_v2_0.c
85
WREG32(VCE_CLOCK_GATING_B, tmp);
sys/dev/drm/radeon/vce_v2_0.c
87
orig = tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/drm/radeon/vce_v2_0.c
88
tmp &= ~0x1fe000;
sys/dev/drm/radeon/vce_v2_0.c
89
tmp &= ~0xff000000;
sys/dev/drm/radeon/vce_v2_0.c
90
if (tmp != orig)
sys/dev/drm/radeon/vce_v2_0.c
91
WREG32(VCE_UENC_CLOCK_GATING, tmp);
sys/dev/drm/radeon/vce_v2_0.c
93
orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
sys/dev/drm/radeon/vce_v2_0.c
94
tmp &= ~0x3fc;
sys/dev/drm/radeon/vce_v2_0.c
95
if (tmp != orig)
sys/dev/drm/radeon/vce_v2_0.c
96
WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
sys/dev/drm/scheduler/sched_main.c
301
struct drm_sched_entity *entity, *tmp;
sys/dev/drm/scheduler/sched_main.c
326
list_for_each_entry_safe(entity, tmp, &rq->entities, list) {
sys/dev/drm/scheduler/sched_main.c
350
struct drm_sched_job *s_job, *tmp;
sys/dev/drm/scheduler/sched_main.c
355
list_for_each_entry_safe(s_job, tmp, &sched->ring_mirror_list, node) {
sys/dev/drm/ttm/ttm_bo_util.c
509
pgprot_t ttm_io_prot(uint32_t caching_flags, pgprot_t tmp)
sys/dev/drm/ttm/ttm_bo_util.c
513
return tmp;
sys/dev/drm/ttm/ttm_bo_util.c
517
tmp = pgprot_writecombine(tmp);
sys/dev/drm/ttm/ttm_bo_util.c
519
tmp = pgprot_noncached(tmp);
sys/dev/drm/ttm/ttm_bo_util.c
524
tmp = pgprot_writecombine(tmp);
sys/dev/drm/ttm/ttm_bo_util.c
526
tmp = pgprot_noncached(tmp);
sys/dev/drm/ttm/ttm_bo_util.c
529
tmp = pgprot_noncached(tmp);
sys/dev/drm/ttm/ttm_bo_util.c
531
return tmp;
sys/dev/drm/ttm/ttm_page_alloc_dma.c
369
struct dma_page *d_page, *tmp;
sys/dev/drm/ttm/ttm_page_alloc_dma.c
372
list_for_each_entry_safe(d_page, tmp, d_pages, page_list)
sys/dev/drm/ttm/ttm_page_alloc_dma.c
384
list_for_each_entry_safe(d_page, tmp, d_pages, page_list) {
sys/dev/drm/ttm/ttm_page_alloc_dma.c
405
struct dma_page *dma_p, *tmp;
sys/dev/drm/ttm/ttm_page_alloc_dma.c
431
list_for_each_entry_safe_reverse(dma_p, tmp, &pool->free_list,
sys/dev/drm/ttm/ttm_page_alloc_dma.c
635
struct dma_pool *pool, *tmp;
sys/dev/drm/ttm/ttm_page_alloc_dma.c
651
list_for_each_entry_safe(pool, tmp, &dev->dma_pools, pools)
sys/dev/drm/ttm/ttm_page_alloc_dma.c
667
struct dma_page *d_page, *tmp;
sys/dev/drm/ttm/ttm_page_alloc_dma.c
675
list_for_each_entry_safe(d_page, tmp, d_pages, page_list) {
sys/dev/misc/cpuctl/cpuctl.c
261
uint32_t tmp[4];
sys/dev/misc/cpuctl/cpuctl.c
300
do_cpuid(0, tmp);
sys/dev/misc/cpuctl/cpuctl.c
320
uint32_t tmp[4];
sys/dev/misc/cpuctl/cpuctl.c
359
do_cpuid(0, tmp);
sys/dev/misc/cpuctl/cpuctl.c
374
uint32_t tmp[4];
sys/dev/misc/cpuctl/cpuctl.c
406
do_cpuid(1, tmp);
sys/dev/misc/evdev/evdev.c
368
struct evdev_client *client, *tmp;
sys/dev/misc/evdev/evdev.c
378
LIST_FOREACH_MUTABLE(client, &evdev->ev_clients, ec_link, tmp) {
sys/dev/misc/musycc/musycc.c
1298
sc->ram->tmp[ch] = vtophys(&sc->mdt[ch][0]);
sys/dev/misc/musycc/musycc.c
1338
sc->ram->tmp[ch] = 0;
sys/dev/misc/musycc/musycc.c
90
u_int32_t tmp[32]; /* Transmit Message Pointer [5-30] */
sys/dev/misc/syscons/dragon/dragon_saver.c
119
int tmp;
sys/dev/misc/syscons/dragon/dragon_saver.c
125
for (tmp = 0; tmp < 3*CURVE; ++tmp) {
sys/dev/misc/syscons/dragon/dragon_saver.c
126
dragon_pal[3+tmp] = (u_char)krandom();
sys/dev/misc/syscons/dragon/dragon_saver.c
168
tmp = dx; dx = dy; dy = -tmp; /* turn right */
sys/dev/misc/syscons/dragon/dragon_saver.c
172
tmp = dx; dx = -dy; dy = tmp; /* turn left */
sys/dev/netif/ath/ath_hal/ar5212/ar5212_attach.c
217
struct ar5212AniParams tmp;
sys/dev/netif/ath/ath_hal/ar5212/ar5212_attach.c
218
OS_MEMCPY(&tmp, &aniparams, sizeof(struct ar5212AniParams));
sys/dev/netif/ath/ath_hal/ar5212/ar5212_attach.c
219
tmp.maxSpurImmunityLevel = 7; /* Venice and earlier */
sys/dev/netif/ath/ath_hal/ar5212/ar5212_attach.c
220
ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE);
sys/dev/netif/ath/ath_hal/ar5416/ar5416_attach.c
653
int tmp, new;
sys/dev/netif/ath/ath_hal/ar5416/ar5416_attach.c
686
tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0));
sys/dev/netif/ath/ath_hal/ar5416/ar5416_attach.c
687
new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
sys/dev/netif/ath/ath_hal/ar5416/ar5416_gpio.c
38
uint32_t gpio_shift, tmp;
sys/dev/netif/ath/ath_hal/ar5416/ar5416_gpio.c
72
tmp = OS_REG_READ(ah, addr);
sys/dev/netif/ath/ath_hal/ar5416/ar5416_gpio.c
73
tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
sys/dev/netif/ath/ath_hal/ar5416/ar5416_gpio.c
74
tmp &= ~(0x1f << gpio_shift);
sys/dev/netif/ath/ath_hal/ar5416/ar5416_gpio.c
75
tmp |= type << gpio_shift;
sys/dev/netif/ath/ath_hal/ar5416/ar5416_gpio.c
76
OS_REG_WRITE(ah, addr, tmp);
sys/dev/netif/ath/ath_hal/ar9002/ar9280_attach.c
589
int tmp, newVal;
sys/dev/netif/ath/ath_hal/ar9002/ar9280_attach.c
658
tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0));
sys/dev/netif/ath/ath_hal/ar9002/ar9280_attach.c
660
newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
sys/dev/netif/bwn/bwn/if_bwn.c
1444
uint32_t tmp;
sys/dev/netif/bwn/bwn/if_bwn.c
1447
tmp = BWN_READ_2(mac, BWN_PHYVER);
sys/dev/netif/bwn/bwn/if_bwn.c
1450
phy->analog = (tmp & BWN_PHYVER_ANALOG) >> 12;
sys/dev/netif/bwn/bwn/if_bwn.c
1451
phy->type = (tmp & BWN_PHYVER_TYPE) >> 8;
sys/dev/netif/bwn/bwn/if_bwn.c
1452
phy->rev = (tmp & BWN_PHYVER_VERSION);
sys/dev/netif/bwn/bwn/if_bwn.c
1464
tmp = 0x3205017f;
sys/dev/netif/bwn/bwn/if_bwn.c
1466
tmp = 0x4205017f;
sys/dev/netif/bwn/bwn/if_bwn.c
1468
tmp = 0x5205017f;
sys/dev/netif/bwn/bwn/if_bwn.c
1471
tmp = BWN_READ_2(mac, BWN_RFDATALO);
sys/dev/netif/bwn/bwn/if_bwn.c
1473
tmp |= (uint32_t)BWN_READ_2(mac, BWN_RFDATAHI) << 16;
sys/dev/netif/bwn/bwn/if_bwn.c
1475
phy->rf_rev = (tmp & 0xf0000000) >> 28;
sys/dev/netif/bwn/bwn/if_bwn.c
1476
phy->rf_ver = (tmp & 0x0ffff000) >> 12;
sys/dev/netif/bwn/bwn/if_bwn.c
1477
phy->rf_manuf = (tmp & 0x00000fff);
sys/dev/netif/bwn/bwn/if_bwn.c
2226
uint32_t tmp;
sys/dev/netif/bwn/bwn/if_bwn.c
2235
tmp = BWN_READ_4(mac, BWN_XMITSTAT_0);
sys/dev/netif/bwn/bwn/if_bwn.c
2236
if (!(tmp & 0x00000001))
sys/dev/netif/bwn/bwn/if_bwn.c
2238
tmp = BWN_READ_4(mac, BWN_XMITSTAT_1);
sys/dev/netif/bwn/bwn/if_bwn.c
2640
uint32_t tmp;
sys/dev/netif/bwn/bwn/if_bwn.c
2643
tmp = BWN_READ_4(mac, SIBA_TGSHIGH);
sys/dev/netif/bwn/bwn/if_bwn.c
2644
if (tmp & SIBA_TGSHIGH_DMA64)
sys/dev/netif/bwn/bwn/if_bwn.c
2648
tmp = BWN_READ_4(mac, base + BWN_DMA32_TXCTL);
sys/dev/netif/bwn/bwn/if_bwn.c
2649
if (tmp & BWN_DMA32_TXADDREXT_MASK)
sys/dev/netif/bwn/bwn/if_bwn.c
3641
uint16_t tmp;
sys/dev/netif/bwn/bwn/if_bwn.c
3646
tmp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL);
sys/dev/netif/bwn/bwn/if_bwn.c
3647
tmp = (tmp & ~BWN_TX_PHY_ANT) | ant;
sys/dev/netif/bwn/bwn/if_bwn.c
3648
bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL, tmp);
sys/dev/netif/bwn/bwn/if_bwn.c
3650
tmp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL);
sys/dev/netif/bwn/bwn/if_bwn.c
3651
tmp = (tmp & ~BWN_TX_PHY_ANT) | ant;
sys/dev/netif/bwn/bwn/if_bwn.c
3652
bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL, tmp);
sys/dev/netif/bwn/bwn/if_bwn.c
3695
uint32_t tmp;
sys/dev/netif/bwn/bwn/if_bwn.c
3698
tmp = BWN_READ_4(mac, SIBA_TGSHIGH);
sys/dev/netif/bwn/bwn/if_bwn.c
3699
if (tmp & SIBA_TGSHIGH_DMA64)
sys/dev/netif/bwn/bwn/if_bwn.c
3703
tmp = BWN_READ_4(mac, base + BWN_DMA32_TXCTL);
sys/dev/netif/bwn/bwn/if_bwn.c
3704
if (tmp & BWN_DMA32_TXADDREXT_MASK)
sys/dev/netif/bwn/bwn/if_bwn.c
3825
uint32_t tmp;
sys/dev/netif/bwn/bwn/if_bwn.c
3837
tmp = BWN_READ_4(mac, BWN_INTR_REASON);
sys/dev/netif/bwn/bwn/if_bwn.c
3838
if (tmp & BWN_INTR_MAC_SUSPENDED)
sys/dev/netif/bwn/bwn/if_bwn.c
3843
tmp = BWN_READ_4(mac, BWN_INTR_REASON);
sys/dev/netif/bwn/bwn/if_bwn.c
3844
if (tmp & BWN_INTR_MAC_SUSPENDED)
sys/dev/netif/bwn/bwn/if_bwn.c
4490
int slot, tmp;
sys/dev/netif/bwn/bwn/if_bwn.c
4512
tmp = bwn_shm_read_2(mac, BWN_SHARED,
sys/dev/netif/bwn/bwn/if_bwn.c
4514
tmp |= 0x100;
sys/dev/netif/bwn/bwn/if_bwn.c
4516
tmp);
sys/dev/netif/bwn/bwn/if_bwn.c
4528
uint32_t tmp;
sys/dev/netif/bwn/bwn/if_bwn.c
4538
tmp = (uint32_t) (mac_bssid[i + 0]);
sys/dev/netif/bwn/bwn/if_bwn.c
4539
tmp |= (uint32_t) (mac_bssid[i + 1]) << 8;
sys/dev/netif/bwn/bwn/if_bwn.c
4540
tmp |= (uint32_t) (mac_bssid[i + 2]) << 16;
sys/dev/netif/bwn/bwn/if_bwn.c
4541
tmp |= (uint32_t) (mac_bssid[i + 3]) << 24;
sys/dev/netif/bwn/bwn/if_bwn.c
4542
bwn_ram_write(mac, 0x20 + i, tmp);
sys/dev/netif/bwn/bwn/if_bwn.c
5170
uint32_t tmp;
sys/dev/netif/bwn/bwn/if_bwn.c
5173
tmp = BWN_READ_4(mac, BWN_PS_STATUS);
sys/dev/netif/bwn/bwn/if_bwn.c
5174
if (!(tmp & 0x00000008))
sys/dev/netif/bwn/bwn/if_bwn.c
5184
uint16_t tmp;
sys/dev/netif/bwn/bwn/if_bwn.c
5217
tmp = (bwn_shm_read_2(mac, BWN_SHARED, 0x40c) / 128) & 0x1f;
sys/dev/netif/bwn/bwn/if_bwn.c
5218
if (tmp >= 8)
sys/dev/netif/bwn/bwn/if_bwn.c
5222
average -= (tmp == 8) ? 72 : 48;
sys/dev/netif/bwn/bwn/if_bwn.c
5292
uint16_t tmp;
sys/dev/netif/bwn/bwn/if_bwn.c
5311
tmp = (stat0 & 0x0000ffff);
sys/dev/netif/bwn/bwn/if_bwn.c
5312
stat.framecnt = ((tmp & 0xf000) >> 12);
sys/dev/netif/bwn/bwn/if_bwn.c
5313
stat.rtscnt = ((tmp & 0x0f00) >> 8);
sys/dev/netif/bwn/bwn/if_bwn.c
5314
stat.sreason = ((tmp & 0x001c) >> 2);
sys/dev/netif/bwn/bwn/if_bwn.c
5315
stat.pm = (tmp & 0x0080) ? 1 : 0;
sys/dev/netif/bwn/bwn/if_bwn.c
5316
stat.im = (tmp & 0x0040) ? 1 : 0;
sys/dev/netif/bwn/bwn/if_bwn.c
5317
stat.ampdu = (tmp & 0x0020) ? 1 : 0;
sys/dev/netif/bwn/bwn/if_bwn.c
5318
stat.ack = (tmp & 0x0002) ? 1 : 0;
sys/dev/netif/bwn/bwn/if_bwn.c
5451
int32_t tmp;
sys/dev/netif/bwn/bwn/if_bwn.c
5487
tmp = len;
sys/dev/netif/bwn/bwn/if_bwn.c
5495
tmp -= dr->dr_rx_bufsize;
sys/dev/netif/bwn/bwn/if_bwn.c
5496
if (tmp <= 0)
sys/dev/netif/bwn/bwn/if_bwn.c
5795
int tmp;
sys/dev/netif/bwn/bwn/if_bwn.c
5800
tmp = in_rssi;
sys/dev/netif/bwn/bwn/if_bwn.c
5801
if (tmp > 127)
sys/dev/netif/bwn/bwn/if_bwn.c
5802
tmp -= 256;
sys/dev/netif/bwn/bwn/if_bwn.c
5803
tmp = tmp * 73 / 64;
sys/dev/netif/bwn/bwn/if_bwn.c
5805
tmp += 25;
sys/dev/netif/bwn/bwn/if_bwn.c
5807
tmp -= 3;
sys/dev/netif/bwn/bwn/if_bwn.c
5813
tmp = gphy->pg_nrssi_lt[in_rssi];
sys/dev/netif/bwn/bwn/if_bwn.c
5814
tmp = (31 - tmp) * -131 / 128 - 57;
sys/dev/netif/bwn/bwn/if_bwn.c
5816
tmp = in_rssi;
sys/dev/netif/bwn/bwn/if_bwn.c
5817
tmp = (31 - tmp) * -149 / 128 - 68;
sys/dev/netif/bwn/bwn/if_bwn.c
5820
tmp += 25;
sys/dev/netif/bwn/bwn/if_bwn.c
5825
tmp = in_rssi - 256;
sys/dev/netif/bwn/bwn/if_bwn.c
5827
tmp = in_rssi;
sys/dev/netif/bwn/bwn/if_bwn.c
5830
tmp = in_rssi;
sys/dev/netif/bwn/bwn/if_bwn.c
5831
tmp = (tmp - 11) * 103 / 64;
sys/dev/netif/bwn/bwn/if_bwn.c
5833
tmp -= 109;
sys/dev/netif/bwn/bwn/if_bwn.c
5835
tmp -= 83;
sys/dev/netif/bwn/bwn/if_bwn.c
5838
return (tmp);
sys/dev/netif/bwn/bwn/if_bwn_phy_common.c
173
uint32_t tmp;
sys/dev/netif/bwn/bwn/if_bwn_phy_common.c
179
tmp = siba_read_4(sc->sc_dev, SIBA_TGSLOW);
sys/dev/netif/bwn/bwn/if_bwn_phy_common.c
181
tmp |= SIBA_TGSLOW_FGC;
sys/dev/netif/bwn/bwn/if_bwn_phy_common.c
183
tmp &= ~SIBA_TGSLOW_FGC;
sys/dev/netif/bwn/bwn/if_bwn_phy_common.c
184
siba_write_4(sc->sc_dev, SIBA_TGSLOW, tmp);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2053
int tmp;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2060
tmp = lb_gain;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2062
tmp = (10 - lb_gain);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2063
if (tmp < 0)
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2064
tmp += 6;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2066
tmp += 3;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2068
tmp /= 4;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2069
if (tmp >= cmp_val)
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2072
rf_pctl_reg = tmp;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2125
uint64_t tmp;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2129
tmp = bwn_shm_read_2(mac, BWN_SHARED, 0x310 + i);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2130
power_vector |= (tmp << (i * 8));
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2145
uint16_t tmp;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2193
tmp = BWN_RF_READ(mac, 0x7a);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2195
tmp &= ~0x0008;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2197
tmp |= 0x0008;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2198
BWN_RF_WRITE(mac, 0x7a, tmp);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2209
uint16_t tmp;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2280
tmp =
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2282
BWN_PHY_WRITE(mac, tmp, 0x007f);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2284
tmp = sav->phy_syncctl;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2285
BWN_PHY_WRITE(mac, BWN_PHY_SYNCCTL, tmp & 0xff7f);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2286
tmp = sav->rf1;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2287
BWN_RF_WRITE(mac, 0x007a, tmp & 0xfff0);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2323
uint16_t tmp;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2327
tmp = (pg->pg_pga_gain << 8);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2328
BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, tmp | 0xa0);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2330
BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, tmp | 0xa2);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2332
BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, tmp | 0xa3);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2334
tmp = (pg->pg_pga_gain | 0xefa0);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2335
BWN_PHY_WRITE(mac, BWN_PHY_PGACTL, tmp);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2355
tmp = sav->rf2;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2356
BWN_RF_SETMASK(mac, 0x52, 0xff0f, tmp);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2375
tmp = (sav->phy_lomask & 0xbfff);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2376
BWN_PHY_WRITE(mac, BWN_PHY_LO_MASK, tmp);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2757
uint16_t delta, tmp;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2844
tmp = BWN_RF_READ(mac, 0x0052) & 0xff0f;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2845
BWN_RF_WRITE(mac, 0x0052, tmp | 0x0060);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2846
tmp = BWN_RF_READ(mac, 0x0043) & 0xfff0;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
2847
BWN_RF_WRITE(mac, 0x0043, tmp | 0x0009);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
3074
uint16_t tmp;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
3092
tmp = ((uint16_t) third << 14) | ((uint16_t) third << 6);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
3093
BWN_PHY_SETMASK(mac, 0x04a0, 0xbfbf, tmp);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
3094
BWN_PHY_SETMASK(mac, 0x04a1, 0xbfbf, tmp);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
3095
BWN_PHY_SETMASK(mac, 0x04a2, 0xbfbf, tmp);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
3104
uint16_t i, tmp;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
3117
tmp = (i & 0xfffc);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
3118
tmp |= (i & 0x0001) << 1;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
3119
tmp |= (i & 0x0002) >> 1;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
3121
bwn_ofdmtab_write_2(mac, table, i, tmp);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
3230
uint16_t nr_written = 0, tmp, value;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
3257
tmp = lo->bbatt.array[bb].att;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
3258
tmp <<= 8;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
3260
tmp |= 0x50;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
3262
tmp |= 0x40;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
3263
tmp |= lo->rfatt.array[rf].att;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
3264
BWN_PHY_WRITE(mac, 0x3c0 + nr_written, tmp);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
3511
uint32_t tmp;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
3513
tmp = bwn_shm_read_4(mac, BWN_SHARED, shm_offset);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
3514
a = tmp & 0xff;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
3515
b = (tmp >> 8) & 0xff;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
3516
c = (tmp >> 16) & 0xff;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
3517
d = (tmp >> 24) & 0xff;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
481
struct bwn_lo_calib *cal, *tmp;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
485
TAILQ_FOREACH_SAFE(cal, &lo->calib_list, list, tmp) {
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
593
uint16_t tmp;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
607
tmp = BWN_PHY_READ(mac, BWN_PHY_ANTDWELL);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
609
tmp &= ~BWN_PHY_ANTDWELL_AUTODIV1;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
611
tmp |= BWN_PHY_ANTDWELL_AUTODIV1;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
612
BWN_PHY_WRITE(mac, BWN_PHY_ANTDWELL, tmp);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
614
tmp = BWN_PHY_READ(mac, BWN_PHY_ANTWRSETT);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
616
tmp |= BWN_PHY_ANTWRSETT_ARXDIV;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
618
tmp &= ~BWN_PHY_ANTWRSETT_ARXDIV;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
619
BWN_PHY_WRITE(mac, BWN_PHY_ANTWRSETT, tmp);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
775
struct bwn_lo_calib *cal, *tmp;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
794
TAILQ_FOREACH_SAFE(cal, &lo->calib_list, list, tmp) {
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
858
uint16_t i, tmp;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
881
tmp = BWN_PHY_READ(mac, BWN_PHY_VERSION_OFDM);
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
882
tmp &= BWN_PHYVER_VERSION;
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
883
if (tmp == 3 || tmp == 5) {
sys/dev/netif/bwn/bwn/if_bwn_phy_g.c
887
if (tmp == 5) {
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1001
uint16_t tmp = (channel == 14);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1004
BWN_PHY_SETMASK(mac, BWN_PHY_LP_PHY_CTL, 0xfcff, tmp << 9);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1019
uint16_t iso, tmp[3];
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1032
tmp[0] = ((iso - 26) / 12) << 12;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1033
tmp[1] = tmp[0] + 0x1000;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1034
tmp[2] = tmp[0] + 0x2000;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1036
bwn_tab_write_multi(mac, BWN_TAB_2(13, 0), 3, tmp);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1037
bwn_tab_write_multi(mac, BWN_TAB_2(12, 0), 3, tmp);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1458
uint16_t tmp, tmp2;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1493
tmp = plp->plp_rssivf | plp->plp_rssivc << 4 | 0xa000;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1494
BWN_PHY_WRITE(mac, BWN_PHY_AFE_RSSI_CTL_0, tmp);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1553
tmp = BWN_PHY_READ(mac, BWN_PHY_CLIPCTRTHRESH);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1554
tmp2 = (tmp & 0x03e0) >> 5;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1557
tmp = BWN_PHY_READ(mac, BWN_PHY_GAINDIRECTMISMATCH);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1558
tmp2 = (tmp & 0x1f00) >> 8;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1561
tmp = BWN_PHY_READ(mac, BWN_PHY_VERYLOWGAINDB);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1562
tmp2 = tmp & 0x00ff;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1563
tmp2 |= tmp << 8;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1705
uint8_t tmp;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1707
tmp = BWN_RF_READ(mac, BWN_B2063_RX_BB_SP8) & 0xff;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1721
BWN_RF_WRITE(mac, BWN_B2063_RX_BB_SP8, tmp);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1723
tmp = BWN_RF_READ(mac, BWN_B2063_TX_BB_SP3) & 0xff;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1741
BWN_RF_WRITE(mac, BWN_B2063_TX_BB_SP3, tmp);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1758
uint32_t npwr, ipwr, sqpwr, tmp;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1820
tmp = 0;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1834
if ((i == 128) || (sum < tmp)) {
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
1836
tmp = sum;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
2150
uint16_t tmp;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
2154
tmp = BWN_PHY_READ(mac,
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
2156
tg.tg_gm = tmp & 0x0007;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
2157
tg.tg_pga = (tmp & 0x0078) >> 3;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
2158
tg.tg_pad = (tmp & 0x780) >> 7;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
2162
tmp = BWN_PHY_READ(mac, BWN_PHY_TX_GAIN_CTL_OVERRIDE_VAL);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
2164
tg.tg_gm = tmp & 0xff;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
2165
tg.tg_pga = (tmp >> 8) & 0xff;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
2222
uint16_t ext_lna, high_gain, lna, low_gain, trsw, tmp;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
2249
tmp = (gain >> 2) & 0x3;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
2251
0xe7ff, tmp<<11);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
2253
tmp << 3);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
2327
int tmp[2], ret;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
2345
CALC_COEFF(tmp[0], bwn_nbits(ie.ie_iqprod), ie.ie_iqprod, ie.ie_ipwr);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
2346
CALC_COEFF2(tmp[1], bwn_nbits(ie.ie_qpwr), ie.ie_qpwr, ie.ie_ipwr);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
2348
tmp[1] = -bwn_sqrt(mac, tmp[1] - (tmp[0] * tmp[0]));
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
2349
v0 = tmp[0] >> 3;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
2350
v1 = tmp[1] >> 4;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
3452
uint32_t tmp;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
3471
tmp = (ie.ie_ipwr + ie.ie_qpwr) / 1000;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
3472
if ((tmp > 4000) && (tmp < 10000)) {
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
3624
uint32_t tmp;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
3627
for (tmp = abs(val); tmp != 0; tmp >>= 1)
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
3659
uint32_t tmp;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
3663
tmp = (te.te_pad << 16) | (te.te_pga << 8) | te.te_gm;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
3665
tmp |= ((IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) ?
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
3668
tmp |= ((IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) ?
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
3671
bwn_tab_write(mac, BWN_TAB_4(7, 0xc0 + offset), tmp);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
437
uint16_t tmp;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
456
tmp = BWN_RF_READ(mac, st->st_rfaddr);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
457
tmp >>= st->st_rfshift;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
458
tmp <<= st->st_physhift;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
461
~(st->st_mask << st->st_physhift), tmp);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
797
tmp[6];
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
851
tmp[0] = ((val[2] * 62500) / freqref) << 4;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
852
tmp[1] = ((val[2] * 62500) % freqref) << 4;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
853
while (tmp[1] >= freqref) {
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
854
tmp[0]++;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
855
tmp[1] -= freqref;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
857
BWN_RF_SETMASK(mac, BWN_B2063_JTAG_SG1, 0xffe0, tmp[0] >> 4);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
858
BWN_RF_SETMASK(mac, BWN_B2063_JTAG_SG2, 0xfe0f, tmp[0] << 4);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
859
BWN_RF_SETMASK(mac, BWN_B2063_JTAG_SG2, 0xfff0, tmp[0] >> 16);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
860
BWN_RF_WRITE(mac, BWN_B2063_JTAG_SG3, (tmp[1] >> 8) & 0xff);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
861
BWN_RF_WRITE(mac, BWN_B2063_JTAG_SG4, tmp[1] & 0xff);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
868
tmp[2] = ((41 * (val[2] - 3000)) /1200) + 27;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
869
tmp[3] = bwn_phy_lp_roundup(132000 * tmp[0], 8451, 16);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
871
if (howmany(tmp[3], tmp[2]) > 60) {
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
873
tmp[4] = ((tmp[3] + tmp[2]) / (tmp[2] << 1)) - 8;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
876
tmp[4] = ((tmp[3] + (tmp[2] >> 1)) / tmp[2]) - 8;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
878
BWN_RF_SETMASK(mac, BWN_B2063_JTAG_CP2, 0xffc0, tmp[4]);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
881
tmp[5] = bwn_phy_lp_roundup(100 * val[0], val[2], 16) * (tmp[4] * 8) *
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
883
if (tmp[5] > 150)
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
884
tmp[5] = 0;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
886
BWN_RF_SETMASK(mac, BWN_B2063_JTAG_CP3, 0xffe0, tmp[5]);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
928
uint32_t tmp[9];
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
955
tmp[0] = freqxtal / 1000;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
956
tmp[1] = plp->plp_div * 1000;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
957
tmp[2] = tmp[1] * ieee80211_ieee2mhz(chan, 0);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
959
tmp[2] *= 2;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
960
tmp[3] = 48 * tmp[0];
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
961
tmp[5] = tmp[2] / tmp[3];
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
962
tmp[6] = tmp[2] % tmp[3];
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
963
BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL26, tmp[5]);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
964
tmp[4] = tmp[6] * 0x100;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
965
tmp[5] = tmp[4] / tmp[3];
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
966
tmp[6] = tmp[4] % tmp[3];
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
967
BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL27, tmp[5]);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
968
tmp[4] = tmp[6] * 0x100;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
969
tmp[5] = tmp[4] / tmp[3];
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
970
tmp[6] = tmp[4] % tmp[3];
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
971
BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL28, tmp[5]);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
972
tmp[4] = tmp[6] * 0x100;
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
973
tmp[5] = tmp[4] / tmp[3];
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
974
tmp[6] = tmp[4] % tmp[3];
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
976
tmp[5] + ((2 * tmp[6]) / tmp[3]));
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
977
tmp[7] = BWN_RF_READ(mac, BWN_B2062_S_RFPLLCTL19);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
978
tmp[8] = ((2 * tmp[2] * (tmp[7] + 1)) + (3 * tmp[0])) / (6 * tmp[0]);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
979
BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL23, (tmp[8] >> 8) + 16);
sys/dev/netif/bwn/bwn/if_bwn_phy_lp.c
980
BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL24, tmp[8] & 0xff);
sys/dev/netif/bwn/bwn/if_bwn_util.c
153
unsigned int tmp;
sys/dev/netif/bwn/bwn/if_bwn_util.c
155
for (tmp = 0; x >= (2 * tmp) + 1; x -= (2 * tmp++) + 1)
sys/dev/netif/bwn/bwn/if_bwn_util.c
157
return (tmp);
sys/dev/netif/bwn/bwn/if_bwnvar.h
141
#define BWN_BITREV4(tmp) (BWN_BITREV8(tmp) >> 4)
sys/dev/netif/bwn/siba/siba_core.c
1212
uint32_t pmu, tmp, pll;
sys/dev/netif/bwn/siba/siba_core.c
1251
tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS);
sys/dev/netif/bwn/siba/siba_core.c
1252
if (!(tmp & SIBA_CC_CLKCTLSTATUS_HT))
sys/dev/netif/bwn/siba/siba_core.c
1256
tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS);
sys/dev/netif/bwn/siba/siba_core.c
1257
if (tmp & SIBA_CC_CLKCTLSTATUS_HT)
sys/dev/netif/bwn/siba/siba_core.c
2061
uint32_t tmp;
sys/dev/netif/bwn/siba/siba_core.c
2069
tmp = siba_read_4_sub(psd, SIBA_IMCFGLO);
sys/dev/netif/bwn/siba/siba_core.c
2070
tmp &= ~SIBA_IMCFGLO_SERTO;
sys/dev/netif/bwn/siba/siba_core.c
2071
tmp = (tmp | 2) & ~SIBA_IMCFGLO_REQTO;
sys/dev/netif/bwn/siba/siba_core.c
2072
tmp |= 3 << 4 /* SIBA_IMCFGLO_REQTO_SHIFT */;
sys/dev/netif/bwn/siba/siba_core.c
2073
siba_write_4_sub(psd, SIBA_IMCFGLO, tmp);
sys/dev/netif/bwn/siba/siba_core.c
2087
tmp = siba_pcicore_read_4(spc, SIBA_PCICORE_SBTOPCI2);
sys/dev/netif/bwn/siba/siba_core.c
2088
tmp |= SIBA_PCICORE_SBTOPCI_MRM;
sys/dev/netif/bwn/siba/siba_core.c
2089
siba_pcicore_write_4(spc, SIBA_PCICORE_SBTOPCI2, tmp);
sys/dev/netif/bwn/siba/siba_core.c
2114
uint32_t tmp;
sys/dev/netif/bwn/siba/siba_core.c
2125
tmp = pci_read_config(siba->siba_dev, SIBA_IRQMASK, 4);
sys/dev/netif/bwn/siba/siba_core.c
2126
tmp |= (1 << sd->sd_coreidx) << 8;
sys/dev/netif/bwn/siba/siba_core.c
2127
pci_write_config(siba->siba_dev, SIBA_IRQMASK, tmp, 4);
sys/dev/netif/bwn/siba/siba_core.c
2129
tmp = siba_read_4_sub(sd, SIBA_TPS);
sys/dev/netif/bwn/siba/siba_core.c
2130
tmp &= SIBA_TPS_BPFLAG;
sys/dev/netif/bwn/siba/siba_core.c
2132
siba_read_4_sub(psd, SIBA_INTR_MASK) | (1 << tmp));
sys/dev/netif/bwn/siba/siba_core.c
2809
uint32_t tmp;
sys/dev/netif/bwn/siba/siba_core.c
2817
tmp = siba_read_4_sub(sd, SIBA_IMCFGLO) &
sys/dev/netif/bwn/siba/siba_core.c
2822
tmp |= 0x32;
sys/dev/netif/bwn/siba/siba_core.c
2825
tmp |= 0x53;
sys/dev/netif/bwn/siba/siba_core.c
2828
siba_write_4_sub(sd, SIBA_IMCFGLO, tmp);
sys/dev/netif/bwn/siba/siba_core.c
287
uint32_t idhi, tmp;
sys/dev/netif/bwn/siba/siba_core.c
302
tmp = siba_scan_read_4(siba, 0, SIBA_CC_CHIPID);
sys/dev/netif/bwn/siba/siba_core.c
303
siba->siba_chipid = SIBA_CC_ID(tmp);
sys/dev/netif/bwn/siba/siba_core.c
304
siba->siba_chiprev = SIBA_CC_REV(tmp);
sys/dev/netif/bwn/siba/siba_core.c
305
siba->siba_chippkg = SIBA_CC_PKG(tmp);
sys/dev/netif/bwn/siba/siba_core.c
307
siba->siba_ndevs = SIBA_CC_NCORES(tmp);
sys/dev/netif/bwn/siba/siba_core.c
784
uint32_t tmp;
sys/dev/netif/bwn/siba/siba_core.c
799
tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) &
sys/dev/netif/bwn/siba/siba_core.c
802
if ((tmp & SIBA_CC_CLKSLOW_SRC) != SIBA_CC_CLKSLOW_SRC_CRYSTAL)
sys/dev/netif/bwn/siba/siba_core.c
803
tmp |= SIBA_CC_CLKSLOW_ENXTAL;
sys/dev/netif/bwn/siba/siba_core.c
804
SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW, tmp);
sys/dev/netif/bwn/siba/siba_core.c
805
if (tmp & SIBA_CC_CLKSLOW_ENXTAL)
sys/dev/netif/dc/if_dc.c
1837
int tmp = 0;
sys/dev/netif/dc/if_dc.c
2118
tmp = sc->dc_pmode;
sys/dev/netif/dc/if_dc.c
2140
sc->dc_pmode = tmp;
sys/dev/netif/de/if_de.c
3358
u_int32_t tmp = csr & sc->tulip_intrmask
sys/dev/netif/de/if_de.c
3370
sc->tulip_statusbits |= tmp;
sys/dev/netif/de/if_de.c
3372
tulip_print_abnormal_interrupt(sc, tmp);
sys/dev/netif/em/if_em.c
1487
int tmp;
sys/dev/netif/em/if_em.c
1489
tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
sys/dev/netif/em/if_em.c
1490
tmp |= E1000_CTRL_EXT_PBA_CLR;
sys/dev/netif/em/if_em.c
1491
E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
sys/dev/netif/emx/if_emx.c
1431
int tmp;
sys/dev/netif/emx/if_emx.c
1433
tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
sys/dev/netif/emx/if_emx.c
1434
tmp |= E1000_CTRL_EXT_PBA_CLR;
sys/dev/netif/emx/if_emx.c
1435
E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
sys/dev/netif/fxp/if_fxp.c
1204
u_int8_t tmp;
sys/dev/netif/fxp/if_fxp.c
1208
tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
sys/dev/netif/fxp/if_fxp.c
1209
if (tmp == 0xff || tmp == 0)
sys/dev/netif/fxp/if_fxp.c
1211
tmp &= ~statack;
sys/dev/netif/fxp/if_fxp.c
1213
if (tmp != 0)
sys/dev/netif/fxp/if_fxp.c
1214
CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
sys/dev/netif/fxp/if_fxp.c
1215
statack |= tmp;
sys/dev/netif/ig_hal/e1000_manage.c
228
u8 *tmp;
sys/dev/netif/ig_hal/e1000_manage.c
240
tmp = (u8 *)&data;
sys/dev/netif/ig_hal/e1000_manage.c
247
*(tmp + j) = *bufptr++;
sys/dev/netif/ig_hal/e1000_manage.c
248
*sum += *(tmp + j);
sys/dev/netif/ig_hal/e1000_manage.c
266
*(tmp + j) = *bufptr++;
sys/dev/netif/ig_hal/e1000_manage.c
267
*sum += *(tmp + j);
sys/dev/netif/ig_hal/e1000_manage.c
276
*(tmp + j) = *bufptr++;
sys/dev/netif/ig_hal/e1000_manage.c
278
*(tmp + j) = 0;
sys/dev/netif/ig_hal/e1000_manage.c
280
*sum += *(tmp + j);
sys/dev/netif/igb/if_igb.c
4008
uint32_t tmp;
sys/dev/netif/igb/if_igb.c
4012
tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
sys/dev/netif/igb/if_igb.c
4013
tmp |= E1000_CTRL_EXT_IRCA;
sys/dev/netif/igb/if_igb.c
4014
E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
sys/dev/netif/iwi/if_iwi.c
1179
uint32_t tmp;
sys/dev/netif/iwi/if_iwi.c
1214
tmp = MEM_READ_4(sc, IWI_MEM_EEPROM_CTL);
sys/dev/netif/iwi/if_iwi.c
1215
val |= ((tmp & IWI_EEPROM_Q) >> IWI_EEPROM_SHIFT_Q) << n;
sys/dev/netif/iwi/if_iwi.c
2146
uint32_t tmp;
sys/dev/netif/iwi/if_iwi.c
2161
tmp = CSR_READ_4(sc, IWI_CSR_RST);
sys/dev/netif/iwi/if_iwi.c
2162
CSR_WRITE_4(sc, IWI_CSR_RST, tmp | IWI_RST_PRINCETON_RESET);
sys/dev/netif/iwi/if_iwi.c
2170
uint32_t tmp;
sys/dev/netif/iwi/if_iwi.c
2175
tmp = CSR_READ_4(sc, IWI_CSR_CTL);
sys/dev/netif/iwi/if_iwi.c
2176
CSR_WRITE_4(sc, IWI_CSR_CTL, tmp | IWI_CTL_INIT);
sys/dev/netif/iwi/if_iwi.c
2192
tmp = CSR_READ_4(sc, IWI_CSR_RST);
sys/dev/netif/iwi/if_iwi.c
2193
CSR_WRITE_4(sc, IWI_CSR_RST, tmp | IWI_RST_SOFT_RESET);
sys/dev/netif/iwi/if_iwi.c
2197
tmp = CSR_READ_4(sc, IWI_CSR_CTL);
sys/dev/netif/iwi/if_iwi.c
2198
CSR_WRITE_4(sc, IWI_CSR_CTL, tmp | IWI_CTL_INIT);
sys/dev/netif/iwi/if_iwi.c
2406
uint32_t tmp;
sys/dev/netif/iwi/if_iwi.c
2430
tmp = CSR_READ_4(sc, IWI_CSR_RST);
sys/dev/netif/iwi/if_iwi.c
2431
tmp &= ~IWI_RST_PRINCETON_RESET;
sys/dev/netif/iwi/if_iwi.c
2432
CSR_WRITE_4(sc, IWI_CSR_RST, tmp);
sys/dev/netif/iwi/if_iwi.c
2482
uint32_t sentinel, ctl, src, dst, sum, len, mlen, tmp;
sys/dev/netif/iwi/if_iwi.c
2533
tmp = CSR_READ_4(sc, IWI_CSR_RST);
sys/dev/netif/iwi/if_iwi.c
2534
tmp &= ~(IWI_RST_MASTER_DISABLED | IWI_RST_STOP_MASTER);
sys/dev/netif/iwi/if_iwi.c
2535
CSR_WRITE_4(sc, IWI_CSR_RST, tmp);
sys/dev/netif/iwi/if_iwi.c
2564
tmp = CSR_READ_4(sc, IWI_CSR_CTL);
sys/dev/netif/iwi/if_iwi.c
2565
CSR_WRITE_4(sc, IWI_CSR_CTL, tmp | IWI_CTL_ALLOW_STANDBY);
sys/dev/netif/iwm/if_iwm.c
5759
int tmp;
sys/dev/netif/iwm/if_iwm.c
5761
tmp = htole32(ict[sc->ict_cur]);
sys/dev/netif/iwm/if_iwm.c
5762
if (!tmp)
sys/dev/netif/iwm/if_iwm.c
5769
while (tmp) {
sys/dev/netif/iwm/if_iwm.c
5770
r1 |= tmp;
sys/dev/netif/iwm/if_iwm.c
5773
tmp = htole32(ict[sc->ict_cur]);
sys/dev/netif/iwm/if_iwm.c
6317
struct wmeParams tmp[WME_NUM_AC];
sys/dev/netif/iwm/if_iwm.c
6328
tmp[aci] = chp.cap_wmeParams[aci];
sys/dev/netif/iwm/if_iwm.c
6333
tmp[aci] = ic->ic_wme.wme_chanParams.cap_wmeParams[aci];
sys/dev/netif/iwm/if_iwm.c
6339
const struct wmeParams *ac = &tmp[aci];
sys/dev/netif/iwn/if_iwn.c
1617
uint32_t tmp;
sys/dev/netif/iwn/if_iwn.c
1619
tmp = iwn_mem_read(sc, addr & ~3);
sys/dev/netif/iwn/if_iwn.c
1621
tmp = (tmp & 0x0000ffff) | data << 16;
sys/dev/netif/iwn/if_iwn.c
1623
tmp = (tmp & 0xffff0000) | data;
sys/dev/netif/iwn/if_iwn.c
1624
iwn_mem_write(sc, addr & ~3, tmp);
sys/dev/netif/iwn/if_iwn.c
1737
uint32_t val, tmp;
sys/dev/netif/iwn/if_iwn.c
1758
tmp = IWN_READ(sc, IWN_OTP_GP);
sys/dev/netif/iwn/if_iwn.c
1759
if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) {
sys/dev/netif/iwn/if_iwn.c
1764
if (tmp & IWN_OTP_GP_ECC_CORR_STTS) {
sys/dev/netif/iwn/if_iwn.c
4088
uint32_t tmp = IWN_READ(sc, IWN_GP_CNTRL);
sys/dev/netif/iwn/if_iwn.c
4093
(tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled");
sys/dev/netif/iwn/if_iwn.c
4094
if (tmp & IWN_GP_CNTRL_RFKILL)
sys/dev/netif/iwn/if_iwn.c
4166
uint32_t r1, r2, tmp;
sys/dev/netif/iwn/if_iwn.c
4175
tmp = 0;
sys/dev/netif/iwn/if_iwn.c
4177
tmp |= sc->ict[sc->ict_cur];
sys/dev/netif/iwn/if_iwn.c
4181
tmp = le32toh(tmp);
sys/dev/netif/iwn/if_iwn.c
4182
if (tmp == 0xffffffff) /* Shouldn't happen. */
sys/dev/netif/iwn/if_iwn.c
4183
tmp = 0;
sys/dev/netif/iwn/if_iwn.c
4184
else if (tmp & 0xc0000) /* Workaround a HW bug. */
sys/dev/netif/iwn/if_iwn.c
4185
tmp |= 0x8000;
sys/dev/netif/iwn/if_iwn.c
4186
r1 = (tmp & 0xff00) << 16 | (tmp & 0xff);
sys/dev/netif/iwn/if_iwn.c
8245
uint32_t len, tmp;
sys/dev/netif/iwn/if_iwn.c
8316
tmp = le32toh(*ptr);
sys/dev/netif/iwn/if_iwn.c
8317
if (tmp < 253) {
sys/dev/netif/iwn/if_iwn.c
8318
sc->reset_noise_gain = tmp;
sys/dev/netif/iwn/if_iwn.c
8319
sc->noise_gain = tmp + 1;
sys/dev/netif/iwn/if_iwn.c
8564
uint32_t tmp;
sys/dev/netif/iwn/if_iwn.c
8588
tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR);
sys/dev/netif/iwn/if_iwn.c
8589
tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK;
sys/dev/netif/iwn/if_iwn.c
8590
tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32;
sys/dev/netif/iwn/if_iwn.c
8591
iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp);
sys/dev/netif/ix/if_ix.c
5148
uint32_t rxpb, frame, size, tmp;
sys/dev/netif/ix/if_ix.c
5158
tmp = IXGBE_DV_X540(frame, frame);
sys/dev/netif/ix/if_ix.c
5161
tmp = IXGBE_DV(frame, frame);
sys/dev/netif/ix/if_ix.c
5164
size = IXGBE_BT2KB(tmp);
sys/dev/netif/ix/if_ix.c
5174
tmp = IXGBE_LOW_DV_X540(frame);
sys/dev/netif/ix/if_ix.c
5177
tmp = IXGBE_LOW_DV(frame);
sys/dev/netif/ix/if_ix.c
5180
hw->fc.low_water[0] = IXGBE_BT2KB(tmp);
sys/dev/netif/nfe/if_nfe.c
1441
uint32_t tmp;
sys/dev/netif/nfe/if_nfe.c
1530
tmp = NFE_READ(sc, NFE_PWR_STATE);
sys/dev/netif/nfe/if_nfe.c
1531
NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP);
sys/dev/netif/nfe/if_nfe.c
1533
tmp = NFE_READ(sc, NFE_PWR_STATE);
sys/dev/netif/nfe/if_nfe.c
1534
NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID);
sys/dev/netif/ral/rt2560.c
2063
uint32_t tmp;
sys/dev/netif/ral/rt2560.c
2076
tmp = RT2560_BBP_WRITE | RT2560_BBP_BUSY | reg << 8 | val;
sys/dev/netif/ral/rt2560.c
2077
RAL_WRITE(sc, RT2560_BBPCSR, tmp);
sys/dev/netif/ral/rt2560.c
2115
uint32_t tmp;
sys/dev/netif/ral/rt2560.c
2128
tmp = RT2560_RF_BUSY | RT2560_RF_20BIT | (val & 0xfffff) << 2 |
sys/dev/netif/ral/rt2560.c
2130
RAL_WRITE(sc, RT2560_RFCSR, tmp);
sys/dev/netif/ral/rt2560.c
2142
uint8_t power, tmp;
sys/dev/netif/ral/rt2560.c
2224
tmp = rt2560_bbp_read(sc, 70);
sys/dev/netif/ral/rt2560.c
2226
tmp &= ~RT2560_JAPAN_FILTER;
sys/dev/netif/ral/rt2560.c
2228
tmp |= RT2560_JAPAN_FILTER;
sys/dev/netif/ral/rt2560.c
2230
rt2560_bbp_write(sc, 70, tmp);
sys/dev/netif/ral/rt2560.c
2255
uint32_t tmp;
sys/dev/netif/ral/rt2560.c
2258
tmp = sc->rf_regs[RAL_RF1] & ~RAL_RF1_AUTOTUNE;
sys/dev/netif/ral/rt2560.c
2259
rt2560_rf_write(sc, RAL_RF1, tmp);
sys/dev/netif/ral/rt2560.c
2262
tmp = sc->rf_regs[RAL_RF3] & ~RAL_RF3_AUTOTUNE;
sys/dev/netif/ral/rt2560.c
2263
rt2560_rf_write(sc, RAL_RF3, tmp);
sys/dev/netif/ral/rt2560.c
2279
uint32_t tmp;
sys/dev/netif/ral/rt2560.c
2284
tmp = 16 * vap->iv_bss->ni_intval;
sys/dev/netif/ral/rt2560.c
2285
RAL_WRITE(sc, RT2560_CSR12, tmp);
sys/dev/netif/ral/rt2560.c
2291
tmp = logcwmin << 16 | preload;
sys/dev/netif/ral/rt2560.c
2292
RAL_WRITE(sc, RT2560_BCNOCSR, tmp);
sys/dev/netif/ral/rt2560.c
2295
tmp = RT2560_ENABLE_TSF | RT2560_ENABLE_TBCN;
sys/dev/netif/ral/rt2560.c
2297
tmp |= RT2560_ENABLE_TSF_SYNC(1);
sys/dev/netif/ral/rt2560.c
2299
tmp |= RT2560_ENABLE_TSF_SYNC(2) |
sys/dev/netif/ral/rt2560.c
2301
RAL_WRITE(sc, RT2560_CSR14, tmp);
sys/dev/netif/ral/rt2560.c
2348
uint32_t tmp;
sys/dev/netif/ral/rt2560.c
2378
tmp = RAL_READ(sc, RT2560_CSR11);
sys/dev/netif/ral/rt2560.c
2379
tmp = (tmp & ~0x1f00) | slottime << 8;
sys/dev/netif/ral/rt2560.c
2380
RAL_WRITE(sc, RT2560_CSR11, tmp);
sys/dev/netif/ral/rt2560.c
2382
tmp = tx_pifs << 16 | tx_sifs;
sys/dev/netif/ral/rt2560.c
2383
RAL_WRITE(sc, RT2560_CSR18, tmp);
sys/dev/netif/ral/rt2560.c
2385
tmp = eifs << 16 | tx_difs;
sys/dev/netif/ral/rt2560.c
2386
RAL_WRITE(sc, RT2560_CSR19, tmp);
sys/dev/netif/ral/rt2560.c
2418
uint32_t tmp;
sys/dev/netif/ral/rt2560.c
2421
tmp = led1 << 16 | led2 << 17 | 70 << 8 | 30;
sys/dev/netif/ral/rt2560.c
2422
RAL_WRITE(sc, RT2560_LEDCSR, tmp);
sys/dev/netif/ral/rt2560.c
2428
uint32_t tmp;
sys/dev/netif/ral/rt2560.c
2430
tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24;
sys/dev/netif/ral/rt2560.c
2431
RAL_WRITE(sc, RT2560_CSR5, tmp);
sys/dev/netif/ral/rt2560.c
2433
tmp = bssid[4] | bssid[5] << 8;
sys/dev/netif/ral/rt2560.c
2434
RAL_WRITE(sc, RT2560_CSR6, tmp);
sys/dev/netif/ral/rt2560.c
2446
uint32_t tmp;
sys/dev/netif/ral/rt2560.c
2448
tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24;
sys/dev/netif/ral/rt2560.c
2449
RAL_WRITE(sc, RT2560_CSR3, tmp);
sys/dev/netif/ral/rt2560.c
2451
tmp = addr[4] | addr[5] << 8;
sys/dev/netif/ral/rt2560.c
2452
RAL_WRITE(sc, RT2560_CSR4, tmp);
sys/dev/netif/ral/rt2560.c
2464
uint32_t tmp;
sys/dev/netif/ral/rt2560.c
2466
tmp = RAL_READ(sc, RT2560_CSR3);
sys/dev/netif/ral/rt2560.c
2467
addr[0] = tmp & 0xff;
sys/dev/netif/ral/rt2560.c
2468
addr[1] = (tmp >> 8) & 0xff;
sys/dev/netif/ral/rt2560.c
2469
addr[2] = (tmp >> 16) & 0xff;
sys/dev/netif/ral/rt2560.c
2470
addr[3] = (tmp >> 24);
sys/dev/netif/ral/rt2560.c
2472
tmp = RAL_READ(sc, RT2560_CSR4);
sys/dev/netif/ral/rt2560.c
2473
addr[4] = tmp & 0xff;
sys/dev/netif/ral/rt2560.c
2474
addr[5] = (tmp >> 8) & 0xff;
sys/dev/netif/ral/rt2560.c
2481
uint32_t tmp;
sys/dev/netif/ral/rt2560.c
2483
tmp = RAL_READ(sc, RT2560_RXCSR0);
sys/dev/netif/ral/rt2560.c
2485
tmp &= ~RT2560_DROP_NOT_TO_ME;
sys/dev/netif/ral/rt2560.c
2487
tmp |= RT2560_DROP_NOT_TO_ME;
sys/dev/netif/ral/rt2560.c
2489
RAL_WRITE(sc, RT2560_RXCSR0, tmp);
sys/dev/netif/ral/rt2560.c
2612
uint32_t tmp;
sys/dev/netif/ral/rt2560.c
2631
tmp = RAL_READ(sc, RT2560_BBPCSR1) & ~0x00070007;
sys/dev/netif/ral/rt2560.c
2632
tmp |= (tx & 0x7) << 16 | (tx & 0x7);
sys/dev/netif/ral/rt2560.c
2633
RAL_WRITE(sc, RT2560_BBPCSR1, tmp);
sys/dev/netif/ral/rt2560.c
2661
uint32_t tmp;
sys/dev/netif/ral/rt2560.c
2669
tmp = RT2560_PRIO_RING_COUNT << 24 |
sys/dev/netif/ral/rt2560.c
2675
RAL_WRITE(sc, RT2560_TXCSR2, tmp);
sys/dev/netif/ral/rt2560.c
2682
tmp = RT2560_RX_RING_COUNT << 8 | RT2560_RX_DESC_SIZE;
sys/dev/netif/ral/rt2560.c
2684
RAL_WRITE(sc, RT2560_RXCSR1, tmp);
sys/dev/netif/ral/rt2560.c
2715
tmp = RT2560_DROP_PHY_ERROR | RT2560_DROP_CRC_ERROR;
sys/dev/netif/ral/rt2560.c
2717
tmp |= RT2560_DROP_CTL | RT2560_DROP_VERSION_ERROR;
sys/dev/netif/ral/rt2560.c
2720
tmp |= RT2560_DROP_TODS;
sys/dev/netif/ral/rt2560.c
2722
tmp |= RT2560_DROP_NOT_TO_ME;
sys/dev/netif/ral/rt2560.c
2724
RAL_WRITE(sc, RT2560_RXCSR0, tmp);
sys/dev/netif/ral/rt2560.c
844
uint32_t tmp;
sys/dev/netif/ral/rt2560.c
880
tmp = RAL_READ(sc, RT2560_CSR21);
sys/dev/netif/ral/rt2560.c
881
val |= ((tmp & RT2560_Q) >> RT2560_SHIFT_Q) << n;
sys/dev/netif/ral/rt2661.c
1790
uint32_t tmp;
sys/dev/netif/ral/rt2661.c
1803
tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val;
sys/dev/netif/ral/rt2661.c
1804
RAL_WRITE(sc, RT2661_PHY_CSR3, tmp);
sys/dev/netif/ral/rt2661.c
1842
uint32_t tmp;
sys/dev/netif/ral/rt2661.c
1855
tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 |
sys/dev/netif/ral/rt2661.c
1857
RAL_WRITE(sc, RT2661_PHY_CSR4, tmp);
sys/dev/netif/ral/rt2661.c
1883
uint32_t tmp;
sys/dev/netif/ral/rt2661.c
1891
tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
sys/dev/netif/ral/rt2661.c
1892
RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
sys/dev/netif/ral/rt2661.c
1898
RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
sys/dev/netif/ral/rt2661.c
1909
uint32_t tmp;
sys/dev/netif/ral/rt2661.c
1911
tmp = RAL_READ(sc, RT2661_TXRX_CSR4);
sys/dev/netif/ral/rt2661.c
1913
tmp &= ~RT2661_MRR_CCK_FALLBACK;
sys/dev/netif/ral/rt2661.c
1915
tmp |= RT2661_MRR_CCK_FALLBACK;
sys/dev/netif/ral/rt2661.c
1916
tmp |= RT2661_MRR_ENABLED;
sys/dev/netif/ral/rt2661.c
1918
RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp);
sys/dev/netif/ral/rt2661.c
1925
uint32_t tmp;
sys/dev/netif/ral/rt2661.c
1927
tmp = RAL_READ(sc, RT2661_TXRX_CSR4);
sys/dev/netif/ral/rt2661.c
1929
tmp &= ~RT2661_SHORT_PREAMBLE;
sys/dev/netif/ral/rt2661.c
1931
tmp |= RT2661_SHORT_PREAMBLE;
sys/dev/netif/ral/rt2661.c
1933
RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp);
sys/dev/netif/ral/rt2661.c
1968
uint32_t tmp;
sys/dev/netif/ral/rt2661.c
1997
tmp = RAL_READ(sc, RT2661_PHY_CSR0);
sys/dev/netif/ral/rt2661.c
1998
tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ);
sys/dev/netif/ral/rt2661.c
2000
tmp |= RT2661_PA_PE_2GHZ;
sys/dev/netif/ral/rt2661.c
2002
tmp |= RT2661_PA_PE_5GHZ;
sys/dev/netif/ral/rt2661.c
2003
RAL_WRITE(sc, RT2661_PHY_CSR0, tmp);
sys/dev/netif/ral/rt2661.c
2082
uint32_t tmp;
sys/dev/netif/ral/rt2661.c
2084
tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24;
sys/dev/netif/ral/rt2661.c
2085
RAL_WRITE(sc, RT2661_MAC_CSR4, tmp);
sys/dev/netif/ral/rt2661.c
2087
tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16;
sys/dev/netif/ral/rt2661.c
2088
RAL_WRITE(sc, RT2661_MAC_CSR5, tmp);
sys/dev/netif/ral/rt2661.c
2094
uint32_t tmp;
sys/dev/netif/ral/rt2661.c
2096
tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24;
sys/dev/netif/ral/rt2661.c
2097
RAL_WRITE(sc, RT2661_MAC_CSR2, tmp);
sys/dev/netif/ral/rt2661.c
2099
tmp = addr[4] | addr[5] << 8;
sys/dev/netif/ral/rt2661.c
2100
RAL_WRITE(sc, RT2661_MAC_CSR3, tmp);
sys/dev/netif/ral/rt2661.c
2107
uint32_t tmp;
sys/dev/netif/ral/rt2661.c
2109
tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
sys/dev/netif/ral/rt2661.c
2111
tmp &= ~RT2661_DROP_NOT_TO_ME;
sys/dev/netif/ral/rt2661.c
2113
tmp |= RT2661_DROP_NOT_TO_ME;
sys/dev/netif/ral/rt2661.c
2115
RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
sys/dev/netif/ral/rt2661.c
2172
uint32_t tmp;
sys/dev/netif/ral/rt2661.c
2176
tmp = RAL_READ(sc, RT2661_MAC_CSR9);
sys/dev/netif/ral/rt2661.c
2177
tmp = (tmp & ~0xff) | slottime;
sys/dev/netif/ral/rt2661.c
2178
RAL_WRITE(sc, RT2661_MAC_CSR9, tmp);
sys/dev/netif/ral/rt2661.c
2324
uint32_t tmp, sta[3];
sys/dev/netif/ral/rt2661.c
2415
tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff;
sys/dev/netif/ral/rt2661.c
2417
tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR;
sys/dev/netif/ral/rt2661.c
2419
tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR |
sys/dev/netif/ral/rt2661.c
2423
tmp |= RT2661_DROP_TODS;
sys/dev/netif/ral/rt2661.c
2425
tmp |= RT2661_DROP_NOT_TO_ME;
sys/dev/netif/ral/rt2661.c
2428
RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
sys/dev/netif/ral/rt2661.c
2469
uint32_t tmp;
sys/dev/netif/ral/rt2661.c
2489
tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
sys/dev/netif/ral/rt2661.c
2490
RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
sys/dev/netif/ral/rt2661.c
2659
uint32_t tmp;
sys/dev/netif/ral/rt2661.c
2662
tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
sys/dev/netif/ral/rt2661.c
2663
RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
sys/dev/netif/ral/rt2661.c
2685
RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
sys/dev/netif/ral/rt2661.c
2748
uint32_t tmp;
sys/dev/netif/ral/rt2661.c
2758
tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000;
sys/dev/netif/ral/rt2661.c
2761
tmp |= vap->iv_bss->ni_intval * 16;
sys/dev/netif/ral/rt2661.c
2763
tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT;
sys/dev/netif/ral/rt2661.c
2765
tmp |= RT2661_TSF_MODE(1);
sys/dev/netif/ral/rt2661.c
2767
tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON;
sys/dev/netif/ral/rt2661.c
2769
RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp);
sys/dev/netif/ral/rt2661.c
2831
uint32_t tmp;
sys/dev/netif/ral/rt2661.c
2834
tmp = RAL_READ(sc, RT2661_TXRX_CSR9);
sys/dev/netif/ral/rt2661.c
2835
RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0xffffff);
sys/dev/netif/ral/rt2661.c
795
uint32_t tmp;
sys/dev/netif/ral/rt2661.c
798
tmp = RAL_READ(sc, RT2661_TXRX_CSR9);
sys/dev/netif/ral/rt2661.c
799
RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff);
sys/dev/netif/ral/rt2661.c
836
uint32_t tmp;
sys/dev/netif/ral/rt2661.c
872
tmp = RAL_READ(sc, RT2661_E2PROM_CSR);
sys/dev/netif/ral/rt2661.c
873
val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n;
sys/dev/netif/ral/rt2860.c
1007
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
1019
tmp = RAL_READ(sc, RT3070_EFUSE_CTRL);
sys/dev/netif/ral/rt2860.c
1020
tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK);
sys/dev/netif/ral/rt2860.c
1021
tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK;
sys/dev/netif/ral/rt2860.c
1022
RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp);
sys/dev/netif/ral/rt2860.c
1024
tmp = RAL_READ(sc, RT3070_EFUSE_CTRL);
sys/dev/netif/ral/rt2860.c
1025
if (!(tmp & RT3070_EFSROM_KICK))
sys/dev/netif/ral/rt2860.c
1032
if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK)
sys/dev/netif/ral/rt2860.c
1037
tmp = RAL_READ(sc, reg);
sys/dev/netif/ral/rt2860.c
1039
return (addr & 2) ? tmp >> 16 : tmp & 0xffff;
sys/dev/netif/ral/rt2860.c
1049
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
1085
tmp = RAL_READ(sc, RT2860_PCI_EECTRL);
sys/dev/netif/ral/rt2860.c
1086
val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n;
sys/dev/netif/ral/rt2860.c
1110
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
1117
tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
sys/dev/netif/ral/rt2860.c
1118
tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN);
sys/dev/netif/ral/rt2860.c
1119
RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
sys/dev/netif/ral/rt2860.c
2187
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
2201
tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT |
sys/dev/netif/ral/rt2860.c
2203
RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp);
sys/dev/netif/ral/rt2860.c
2209
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
2221
tmp = RT3070_RF_KICK | reg << 8;
sys/dev/netif/ral/rt2860.c
2222
RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp);
sys/dev/netif/ral/rt2860.c
2225
tmp = RAL_READ(sc, RT3070_RF_CSR_CFG);
sys/dev/netif/ral/rt2860.c
2226
if (!(tmp & RT3070_RF_KICK))
sys/dev/netif/ral/rt2860.c
2234
return tmp & 0xff;
sys/dev/netif/ral/rt2860.c
2240
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
2253
tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val;
sys/dev/netif/ral/rt2860.c
2254
RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp);
sys/dev/netif/ral/rt2860.c
2264
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
2284
tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID);
sys/dev/netif/ral/rt2860.c
2286
for (slot = 0; slot < 4; slot++, tmp >>= 8)
sys/dev/netif/ral/rt2860.c
2287
if ((tmp & 0xff) == cid)
sys/dev/netif/ral/rt2860.c
2300
tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS);
sys/dev/netif/ral/rt2860.c
2301
tmp = (tmp >> (slot * 8)) & 0xff;
sys/dev/netif/ral/rt2860.c
2303
cmd, slot, tmp));
sys/dev/netif/ral/rt2860.c
2307
return (tmp == 1) ? 0 : EIO;
sys/dev/netif/ral/rt2860.c
2338
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
2340
tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG);
sys/dev/netif/ral/rt2860.c
2341
tmp &= ~RT2860_CCK_SHORT_EN;
sys/dev/netif/ral/rt2860.c
2343
tmp |= RT2860_CCK_SHORT_EN;
sys/dev/netif/ral/rt2860.c
2344
RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp);
sys/dev/netif/ral/rt2860.c
237
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
2373
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
2375
tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG);
sys/dev/netif/ral/rt2860.c
2377
tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN |
sys/dev/netif/ral/rt2860.c
2407
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
2433
tmp = RAL_READ(sc, RT2860_TX_BAND_CFG);
sys/dev/netif/ral/rt2860.c
2434
tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P);
sys/dev/netif/ral/rt2860.c
2435
tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P;
sys/dev/netif/ral/rt2860.c
2436
RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp);
sys/dev/netif/ral/rt2860.c
2439
tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN;
sys/dev/netif/ral/rt2860.c
2441
tmp |= RT2860_LNA_PE1_EN;
sys/dev/netif/ral/rt2860.c
2443
tmp |= RT3593_LNA_PE2_EN;
sys/dev/netif/ral/rt2860.c
2445
tmp |= RT2860_PA_PE_G0_EN;
sys/dev/netif/ral/rt2860.c
2447
tmp |= RT2860_PA_PE_G1_EN;
sys/dev/netif/ral/rt2860.c
2449
tmp |= RT3593_PA_PE_G2_EN;
sys/dev/netif/ral/rt2860.c
2451
tmp |= RT2860_PA_PE_A0_EN;
sys/dev/netif/ral/rt2860.c
2453
tmp |= RT2860_PA_PE_A1_EN;
sys/dev/netif/ral/rt2860.c
2455
tmp |= RT3593_PA_PE_A2_EN;
sys/dev/netif/ral/rt2860.c
2457
RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp);
sys/dev/netif/ral/rt2860.c
2460
tmp = RAL_READ(sc, RT2860_GPIO_CTRL);
sys/dev/netif/ral/rt2860.c
2462
tmp &= ~0x01010000;
sys/dev/netif/ral/rt2860.c
2464
tmp |= 0x00010000;
sys/dev/netif/ral/rt2860.c
2466
tmp &= ~0x00008080;
sys/dev/netif/ral/rt2860.c
2468
tmp |= 0x00000080;
sys/dev/netif/ral/rt2860.c
2470
tmp = (tmp & ~0x00001000) | 0x00000010;
sys/dev/netif/ral/rt2860.c
2471
RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp);
sys/dev/netif/ral/rt2860.c
256
tmp = RAL_READ(sc, RT2860_ASIC_VER_ID);
sys/dev/netif/ral/rt2860.c
257
if (tmp != 0 && tmp != 0xffffffff)
sys/dev/netif/ral/rt2860.c
2611
uint8_t h20mhz, rf, tmp;
sys/dev/netif/ral/rt2860.c
2658
tmp = rf;
sys/dev/netif/ral/rt2860.c
2661
if (tmp != rf)
sys/dev/netif/ral/rt2860.c
2662
rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0);
sys/dev/netif/ral/rt2860.c
267
sc->mac_ver = tmp >> 16;
sys/dev/netif/ral/rt2860.c
268
sc->mac_rev = tmp & 0xffff;
sys/dev/netif/ral/rt2860.c
2712
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
2722
tmp = RAL_READ(sc, RT3070_LDO_CFG0);
sys/dev/netif/ral/rt2860.c
2723
tmp &= ~0x1f000000;
sys/dev/netif/ral/rt2860.c
2725
tmp |= 0x0d000000; /* 1.35V */
sys/dev/netif/ral/rt2860.c
2727
tmp |= 0x01000000; /* 1.2V */
sys/dev/netif/ral/rt2860.c
2728
RAL_WRITE(sc, RT3070_LDO_CFG0, tmp);
sys/dev/netif/ral/rt2860.c
2731
tmp = RAL_READ(sc, RT3070_GPIO_SWITCH);
sys/dev/netif/ral/rt2860.c
2732
RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20);
sys/dev/netif/ral/rt2860.c
2768
tmp = RAL_READ(sc, RT3070_OPT_14);
sys/dev/netif/ral/rt2860.c
2769
RAL_WRITE(sc, RT3070_OPT_14, tmp | 1);
sys/dev/netif/ral/rt2860.c
2889
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
2946
tmp = RAL_READ(sc, RT3070_LDO_CFG0);
sys/dev/netif/ral/rt2860.c
2947
tmp = (tmp & ~0x1f000000) | 0x0d000000;
sys/dev/netif/ral/rt2860.c
2948
RAL_WRITE(sc, RT3070_LDO_CFG0, tmp);
sys/dev/netif/ral/rt2860.c
2955
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
2982
tmp = RAL_READ(sc, RT3070_LDO_CFG0);
sys/dev/netif/ral/rt2860.c
2983
tmp = (tmp & ~0x1f000000) | 0x0d000000;
sys/dev/netif/ral/rt2860.c
2984
RAL_WRITE(sc, RT3070_LDO_CFG0, tmp);
sys/dev/netif/ral/rt2860.c
3099
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
3102
tmp = RAL_READ(sc, RT2860_INT_TIMER_EN);
sys/dev/netif/ral/rt2860.c
3103
RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN);
sys/dev/netif/ral/rt2860.c
3108
tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG);
sys/dev/netif/ral/rt2860.c
3110
tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT;
sys/dev/netif/ral/rt2860.c
3111
RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp);
sys/dev/netif/ral/rt2860.c
3114
tmp = RAL_READ(sc, RT2860_INT_TIMER_EN);
sys/dev/netif/ral/rt2860.c
3115
RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN);
sys/dev/netif/ral/rt2860.c
3140
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
3142
tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG);
sys/dev/netif/ral/rt2860.c
3143
tmp &= ~0xff;
sys/dev/netif/ral/rt2860.c
3144
tmp |= IEEE80211_GET_SLOTTIME(ic);
sys/dev/netif/ral/rt2860.c
3145
RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp);
sys/dev/netif/ral/rt2860.c
3152
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
3154
tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL;
sys/dev/netif/ral/rt2860.c
3156
tmp |= IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ?
sys/dev/netif/ral/rt2860.c
3161
RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp);
sys/dev/netif/ral/rt2860.c
3165
tmp |= RT2860_PROT_CTRL_RTS_CTS;
sys/dev/netif/ral/rt2860.c
3167
tmp |= RT2860_PROT_CTRL_CTS;
sys/dev/netif/ral/rt2860.c
3169
RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp);
sys/dev/netif/ral/rt2860.c
3176
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
3178
tmp = RAL_READ(sc, RT2860_RX_FILTR_CFG);
sys/dev/netif/ral/rt2860.c
3179
tmp &= ~RT2860_DROP_NOT_MYBSS;
sys/dev/netif/ral/rt2860.c
3181
tmp |= RT2860_DROP_NOT_MYBSS;
sys/dev/netif/ral/rt2860.c
3182
RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp);
sys/dev/netif/ral/rt2860.c
3427
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
3434
tmp = RAL_READ(sc, RT3070_EFUSE_CTRL);
sys/dev/netif/ral/rt2860.c
3435
DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp));
sys/dev/netif/ral/rt2860.c
3436
if (tmp & RT3070_SEL_EFUSE)
sys/dev/netif/ral/rt2860.c
3814
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
3821
tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
sys/dev/netif/ral/rt2860.c
3822
if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
sys/dev/netif/ral/rt2860.c
3833
tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN |
sys/dev/netif/ral/rt2860.c
3835
RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
sys/dev/netif/ral/rt2860.c
3838
tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR;
sys/dev/netif/ral/rt2860.c
3840
tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL |
sys/dev/netif/ral/rt2860.c
3845
tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL;
sys/dev/netif/ral/rt2860.c
3847
RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp);
sys/dev/netif/ral/rt2860.c
3874
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
3894
tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
sys/dev/netif/ral/rt2860.c
3895
tmp &= 0xff0;
sys/dev/netif/ral/rt2860.c
3896
RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
sys/dev/netif/ral/rt2860.c
3919
tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
sys/dev/netif/ral/rt2860.c
3920
if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
sys/dev/netif/ral/rt2860.c
3929
tmp &= 0xff0;
sys/dev/netif/ral/rt2860.c
3930
RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
sys/dev/netif/ral/rt2860.c
3959
tmp = RAL_READ(sc, RT2860_US_CYC_CNT);
sys/dev/netif/ral/rt2860.c
3960
tmp = (tmp & ~0xff) | 0x7d;
sys/dev/netif/ral/rt2860.c
3961
RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp);
sys/dev/netif/ral/rt2860.c
4019
tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
sys/dev/netif/ral/rt2860.c
4020
if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
sys/dev/netif/ral/rt2860.c
4029
tmp &= 0xff0;
sys/dev/netif/ral/rt2860.c
4030
RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
sys/dev/netif/ral/rt2860.c
4100
tmp = RAL_READ(sc, RT2860_TX_RTS_CFG);
sys/dev/netif/ral/rt2860.c
4101
tmp &= ~0xffff00;
sys/dev/netif/ral/rt2860.c
4102
tmp |= IEEE80211_RTS_DEFAULT << 8;
sys/dev/netif/ral/rt2860.c
4103
RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp);
sys/dev/netif/ral/rt2860.c
4143
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
4160
tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL);
sys/dev/netif/ral/rt2860.c
4161
tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
sys/dev/netif/ral/rt2860.c
4162
RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp);
sys/dev/netif/ral/rt2860.c
4274
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
4281
tmp = RAL_READ(sc, RT2860_PCI_EECTRL);
sys/dev/netif/ral/rt2860.c
4282
RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp & ~RT2860_C);
sys/dev/netif/ral/rt2860.c
4283
tmp = RAL_READ(sc, RT2860_GPIO_CTRL);
sys/dev/netif/ral/rt2860.c
4284
RAL_WRITE(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08);
sys/dev/netif/ral/rt2860.c
4291
tmp = RAL_READ(sc, RT2860_PCI_EECTRL);
sys/dev/netif/ral/rt2860.c
4292
RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp | RT2860_C);
sys/dev/netif/ral/rt2860.c
4293
tmp = RAL_READ(sc, RT2860_GPIO_CTRL);
sys/dev/netif/ral/rt2860.c
4294
RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp & ~0x0808);
sys/dev/netif/ral/rt2860.c
4372
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
4374
tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG);
sys/dev/netif/ral/rt2860.c
4376
tmp &= ~0x1fffff;
sys/dev/netif/ral/rt2860.c
4377
tmp |= vap->iv_bss->ni_intval * 16;
sys/dev/netif/ral/rt2860.c
4378
tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN;
sys/dev/netif/ral/rt2860.c
4384
tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT;
sys/dev/netif/ral/rt2860.c
4388
tmp |= RT2860_BCN_TX_EN;
sys/dev/netif/ral/rt2860.c
4393
tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT;
sys/dev/netif/ral/rt2860.c
4395
tmp |= RT2860_BCN_TX_EN;
sys/dev/netif/ral/rt2860.c
4397
tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT;
sys/dev/netif/ral/rt2860.c
4400
RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp);
sys/dev/netif/ral/rt2860.c
865
uint32_t tmp = RAL_READ(sc, RT2860_DEBUG);
sys/dev/netif/ral/rt2860.c
866
if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) {
sys/dev/netif/ral/rt2860.c
920
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
923
tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4);
sys/dev/netif/ral/rt2860.c
924
tmp |= (1 << tid) << 16;
sys/dev/netif/ral/rt2860.c
925
RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp);
sys/dev/netif/ral/rt2860.c
935
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
938
tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4);
sys/dev/netif/ral/rt2860.c
939
tmp &= ~((1 << tid) << 16);
sys/dev/netif/ral/rt2860.c
940
RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp);
sys/dev/netif/ral/rt2860.c
950
uint32_t tmp;
sys/dev/netif/ral/rt2860.c
960
tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG);
sys/dev/netif/ral/rt2860.c
962
tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN |
sys/dev/netif/sis/if_sis.c
1044
uint16_t tmp[4];
sys/dev/netif/sis/if_sis.c
1046
sis_read_eeprom(sc, (caddr_t)&tmp,
sys/dev/netif/sis/if_sis.c
1050
tmp[3] = tmp[3] >> 1;
sys/dev/netif/sis/if_sis.c
1051
tmp[3] |= tmp[2] << 15;
sys/dev/netif/sis/if_sis.c
1052
tmp[2] = tmp[2] >> 1;
sys/dev/netif/sis/if_sis.c
1053
tmp[2] |= tmp[1] << 15;
sys/dev/netif/sis/if_sis.c
1054
tmp[1] = tmp[1] >> 1;
sys/dev/netif/sis/if_sis.c
1055
tmp[1] |= tmp[0] << 15;
sys/dev/netif/sis/if_sis.c
1058
tmp[3] = sis_reverse(tmp[3]);
sys/dev/netif/sis/if_sis.c
1059
tmp[2] = sis_reverse(tmp[2]);
sys/dev/netif/sis/if_sis.c
1060
tmp[1] = sis_reverse(tmp[1]);
sys/dev/netif/sis/if_sis.c
1062
bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN);
sys/dev/netif/ti/if_ti.c
1989
int tmp;
sys/dev/netif/ti/if_ti.c
2055
tmp = ifm->ifm_media;
sys/dev/netif/ti/if_ti.c
2058
ifm->ifm_media = tmp;
sys/dev/netif/tx/if_tx.c
194
int i, rid, tmp;
sys/dev/netif/tx/if_tx.c
259
tmp = epic_read_eeprom(sc, i);
sys/dev/netif/tx/if_tx.c
260
if (' ' == (u_int8_t)tmp) break;
sys/dev/netif/tx/if_tx.c
261
kprintf("%c", (u_int8_t)tmp);
sys/dev/netif/tx/if_tx.c
262
tmp >>= 8;
sys/dev/netif/tx/if_tx.c
263
if (' ' == (u_int8_t)tmp) break;
sys/dev/netif/tx/if_tx.c
264
kprintf("%c", (u_int8_t)tmp);
sys/dev/pccard/cardbus/cardbus.c
225
int tmp;
sys/dev/pccard/cardbus/cardbus.c
236
for (tmp = 0; tmp < numdevs; tmp++) {
sys/dev/pccard/cardbus/cardbus.c
237
struct cardbus_devinfo *dinfo = device_get_ivars(devlist[tmp]);
sys/dev/pccard/cardbus/cardbus.c
238
int status = device_get_state(devlist[tmp]);
sys/dev/pccard/cardbus/cardbus.c
240
if (dinfo->pci.cfg.dev != devlist[tmp])
sys/dev/pccard/cardbus/cardbus.c
243
device_detach(devlist[tmp]);
sys/dev/pccard/cardbus/cardbus.c
245
device_delete_child(cbdev, devlist[tmp]);
sys/dev/pccard/exca/exca.c
830
int tmp;
sys/dev/pccard/exca/exca.c
848
tmp = rman_get_start(sc->irq_res);
sys/dev/pccard/exca/exca.c
849
if (start > tmp || end < tmp || count != 1) {
sys/dev/pccard/pccbb/pccbb.c
1145
int tmp;
sys/dev/pccard/pccbb/pccbb.c
1151
tmp = rman_get_start(sc->irq_res);
sys/dev/pccard/pccbb/pccbb.c
1152
if (start > tmp || end < tmp || count != 1) {
sys/dev/pccard/pccbb/pccbb.c
1158
start = end = tmp;
sys/dev/pccard/pccbb/pccbb.c
1304
int tmp;
sys/dev/pccard/pccbb/pccbb.c
1327
tmp = rman_get_start(sc->irq_res);
sys/dev/pccard/pccbb/pccbb.c
1328
if (start > tmp || end < tmp || count != 1) {
sys/dev/pccard/pccbb/pccbb.c
1552
uint32_t tmp;
sys/dev/pccard/pccbb/pccbb.c
1570
tmp = cbb_get(sc, CBB_SOCKET_EVENT);
sys/dev/pccard/pccbb/pccbb.c
1571
cbb_set(sc, CBB_SOCKET_EVENT, tmp);
sys/dev/pccard/pccbb/pccbb.c
390
int tmp;
sys/dev/pccard/pccbb/pccbb.c
396
for (tmp = 0; tmp < numdevs; tmp++) {
sys/dev/pccard/pccbb/pccbb.c
397
dev = devlist[tmp];
sys/dev/powermng/intpm/intpm.c
425
int status, tmp;
sys/dev/powermng/intpm/intpm.c
434
tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
sys/dev/powermng/intpm/intpm.c
436
tmp & ~PIIX4_SMBHSTCNT_INTREN);
sys/dev/powermng/intpm/intpm.c
510
unsigned char tmp;
sys/dev/powermng/intpm/intpm.c
513
tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
sys/dev/powermng/intpm/intpm.c
514
tmp &= 0xe0;
sys/dev/powermng/intpm/intpm.c
515
tmp |= cmd;
sys/dev/powermng/intpm/intpm.c
516
tmp |= PIIX4_SMBHSTCNT_START;
sys/dev/powermng/intpm/intpm.c
520
tmp |= PIIX4_SMBHSTCNT_INTREN;
sys/dev/powermng/intpm/intpm.c
521
bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp);
sys/dev/powermng/intpm/intpm.c
560
int error, i, status, tmp;
sys/dev/powermng/intpm/intpm.c
582
tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
sys/dev/powermng/intpm/intpm.c
583
bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp & ~PIIX4_SMBHSTCNT_INTREN);
sys/dev/raid/ips/ips.c
473
u_int32_t tmp;
sys/dev/raid/ips/ips.c
476
tmp = ips_read_4(sc, MORPHEUS_REG_OISR);
sys/dev/raid/ips/ips.c
478
(ips_read_4(sc, MORPHEUS_REG_OMR1) != 0xdeadbeef) && !tmp) {
sys/dev/raid/ips/ips.c
489
tmp = ips_read_4(sc, MORPHEUS_REG_OISR);
sys/dev/raid/ips/ips.c
490
for (i = 0; i < 45 && !(tmp & MORPHEUS_BIT_POST1); i++) {
sys/dev/raid/ips/ips.c
493
tmp = ips_read_4(sc, MORPHEUS_REG_OISR);
sys/dev/raid/ips/ips.c
495
if (tmp & MORPHEUS_BIT_POST1)
sys/dev/raid/ips/ips.c
503
for (i = 0; i < 240 && !(tmp & MORPHEUS_BIT_POST2); i++) {
sys/dev/raid/ips/ips.c
506
tmp = ips_read_4(sc, MORPHEUS_REG_OISR);
sys/dev/raid/ips/ips.c
508
if (tmp & MORPHEUS_BIT_POST2)
sys/dev/raid/mfi/mfi.c
1299
struct mfi_system_pd *syspd, *tmp;
sys/dev/raid/mfi/mfi.c
1344
TAILQ_FOREACH_MUTABLE(syspd, &sc->mfi_syspd_tqh, pd_link, tmp) {
sys/dev/raid/mfi/mfi.c
1642
struct mfi_aen *mfi_aen_entry, *tmp;
sys/dev/raid/mfi/mfi.c
1668
aen_link, tmp) {
sys/dev/raid/mfi/mfi.c
2512
struct mfi_aen *mfi_aen_entry, *tmp;
sys/dev/raid/mfi/mfi.c
2519
TAILQ_FOREACH_MUTABLE(mfi_aen_entry, &sc->mfi_aen_pids, aen_link, tmp) {
sys/dev/raid/mfi/mfi_tbolt.c
1205
struct mfi_command *cm, *tmp;
sys/dev/raid/mfi/mfi_tbolt.c
1208
TAILQ_FOREACH_REVERSE_MUTABLE(cm, &sc->mfi_busy, BUSYQ, cm_link, tmp) {
sys/dev/raid/mrsas/mrsas.c
114
void mrsas_free_tmp_dcmd(struct mrsas_tmp_dcmd *tmp);
sys/dev/raid/mrsas/mrsas.c
3445
void mrsas_free_tmp_dcmd(struct mrsas_tmp_dcmd *tmp)
sys/dev/raid/mrsas/mrsas.c
3447
if (tmp->tmp_dcmd_phys_addr)
sys/dev/raid/mrsas/mrsas.c
3448
bus_dmamap_unload(tmp->tmp_dcmd_tag, tmp->tmp_dcmd_dmamap);
sys/dev/raid/mrsas/mrsas.c
3449
if (tmp->tmp_dcmd_mem != NULL)
sys/dev/raid/mrsas/mrsas.c
3450
bus_dmamem_free(tmp->tmp_dcmd_tag, tmp->tmp_dcmd_mem, tmp->tmp_dcmd_dmamap);
sys/dev/raid/mrsas/mrsas.c
3451
if (tmp->tmp_dcmd_tag != NULL)
sys/dev/raid/mrsas/mrsas.c
3452
bus_dma_tag_destroy(tmp->tmp_dcmd_tag);
sys/dev/raid/vinum/vinumio.c
700
char *tmp;
sys/dev/raid/vinum/vinumio.c
707
if ((tmp = rindex(devicename[driveno], '/')) == NULL)
sys/dev/raid/vinum/vinumio.c
708
tmp = devicename[driveno];
sys/dev/raid/vinum/vinumio.c
710
tmp++;
sys/dev/raid/vinum/vinumio.c
711
ksscanf(tmp, "%*[a-z]%*d%*[s]%d%c", &has_slice, &has_part);
sys/dev/sound/clone.c
447
struct snd_clone_entry *ce, *tmp;
sys/dev/sound/clone.c
454
tmp = TAILQ_NEXT(ce, link);
sys/dev/sound/clone.c
461
ce = tmp;
sys/dev/sound/midi/sequencer.c
1124
int midiunit, ret, tmp;
sys/dev/sound/midi/sequencer.c
1388
tmp = *(int *)arg;
sys/dev/sound/midi/sequencer.c
1389
if (tmp < 0)
sys/dev/sound/midi/sequencer.c
1390
tmp = 0;
sys/dev/sound/midi/sequencer.c
1392
scp->pre_event_timeout = (hz * tmp) / 10;
sys/dev/sound/pci/emu10k1.c
1348
u_int32_t blksz, start, idx, ofs, tmp, found;
sys/dev/sound/pci/emu10k1.c
1388
tmp = (uint32_t)(blk->buf_addr + ofs);
sys/dev/sound/pci/emu10k1.c
1390
printf("pte[%d] -> %x phys, %x virt\n", idx, tmp,
sys/dev/sound/pci/emu10k1.c
1393
mem->ptb_pages[idx] = (tmp << 1) | idx;
sys/dev/sound/pci/emu10k1.c
1403
u_int32_t idx, tmp;
sys/dev/sound/pci/emu10k1.c
1416
tmp = (u_int32_t)(sc->mem.silent_page_addr) << 1;
sys/dev/sound/pci/emu10k1.c
1419
mem->ptb_pages[idx] = tmp | idx;
sys/dev/sound/pci/emu10k1.c
1753
u_int32_t spcs, ch, tmp, i;
sys/dev/sound/pci/emu10k1.c
1875
u_int32_t tmp;
sys/dev/sound/pci/emu10k1.c
1878
tmp = emu_rdptr(sc, 0, EMU_A_SPDIF_SAMPLERATE) & 0xfffff1ff;
sys/dev/sound/pci/emu10k1.c
1879
emu_wrptr(sc, 0, EMU_A_SPDIF_SAMPLERATE, tmp | 0x400);
sys/dev/sound/pci/emu10k1.c
1904
tmp = (u_int32_t)(sc->mem.silent_page_addr) << 1;
sys/dev/sound/pci/emu10k1.c
1906
sc->mem.ptb_pages[i] = tmp | i;
sys/dev/sound/pci/emu10k1.c
1913
emu_wrptr(sc, ch, EMU_CHAN_MAPA, tmp | EMU_CHAN_MAP_PTI_MASK);
sys/dev/sound/pci/emu10k1.c
1914
emu_wrptr(sc, ch, EMU_CHAN_MAPB, tmp | EMU_CHAN_MAP_PTI_MASK);
sys/dev/sound/pci/emu10k1.c
1942
tmp = EMU_HCFG_AUTOMUTE | EMU_HCFG_JOYENABLE;
sys/dev/sound/pci/emu10k1.c
1944
tmp = EMU_HCFG_AUDIOENABLE | EMU_HCFG_AC3ENABLE_CDSPDIF |
sys/dev/sound/pci/emu10k1.c
1946
emu_wr(sc, EMU_HCFG, tmp, 4);
sys/dev/sound/pci/emu10k1.c
1967
tmp = EMU_HCFG_AUDIOENABLE | EMU_HCFG_LOCKTANKCACHE_MASK
sys/dev/sound/pci/emu10k1.c
1970
tmp |= EMU_HCFG_JOYENABLE;
sys/dev/sound/pci/emu10k1.c
1972
emu_wr(sc, EMU_HCFG, tmp, 4);
sys/dev/sound/pci/emu10k1.c
1976
tmp = emu_rd(sc, EMU_HCFG, 4);
sys/dev/sound/pci/emu10k1.c
1977
if (tmp & (EMU_HCFG_GPINPUT0 | EMU_HCFG_GPINPUT1)) {
sys/dev/sound/pci/emu10k1.c
1978
emu_wr(sc, EMU_HCFG, tmp | EMU_HCFG_GPOUT1, 4);
sys/dev/sound/pci/emu10k1.c
1980
if (tmp != (emu_rd(sc, EMU_HCFG, 4) & ~EMU_HCFG_GPOUT1)) {
sys/dev/sound/pci/emu10k1.c
1982
emu_wr(sc, EMU_HCFG, tmp, 4);
sys/dev/sound/pci/emu10k1.c
410
int i, tmp, rate;
sys/dev/sound/pci/emu10k1.c
416
tmp = (pch->spd * sndbuf_getalign(pch->buffer))
sys/dev/sound/pci/emu10k1.c
418
if (tmp > rate)
sys/dev/sound/pci/emu10k1.c
419
rate = tmp;
sys/dev/sound/pci/emu10k1.c
426
tmp = (rch->spd * sndbuf_getalign(rch->buffer))
sys/dev/sound/pci/emu10k1.c
428
if (tmp > rate)
sys/dev/sound/pci/emu10k1.c
429
rate = tmp;
sys/dev/sound/pci/emu10kx-pcm.c
532
int tmp;
sys/dev/sound/pci/emu10kx-pcm.c
557
tmp = emu_rd(sc->card, EMU_AC97DATA, 2);
sys/dev/sound/pci/emu10kx-pcm.c
560
emulated = tmp;
sys/dev/sound/pci/emu10kx.c
1092
uint32_t blksz, start, idx, ofs, tmp, found;
sys/dev/sound/pci/emu10kx.c
1143
tmp = (uint32_t) (blk->buf_addr + ofs);
sys/dev/sound/pci/emu10kx.c
1144
mem->ptb_pages[idx] = (tmp << 1) | idx;
sys/dev/sound/pci/emu10kx.c
1154
uint32_t idx, tmp;
sys/dev/sound/pci/emu10kx.c
1166
tmp = (uint32_t) (mem->silent_page_addr) << 1;
sys/dev/sound/pci/emu10kx.c
1169
mem->ptb_pages[idx] = tmp | idx;
sys/dev/sound/pci/emu10kx.c
2462
uint32_t tmp;
sys/dev/sound/pci/emu10kx.c
2518
tmp = emu_rd(sc, EMU_A_IOCFG, 2);
sys/dev/sound/pci/emu10kx.c
2519
tmp = a_iocfg;
sys/dev/sound/pci/emu10kx.c
2520
emu_wr(sc, EMU_A_IOCFG, tmp, 2);
sys/dev/sound/pci/emu10kx.c
2676
uint32_t ch, tmp;
sys/dev/sound/pci/emu10kx.c
2746
tmp = (uint32_t) (sc->mem.silent_page_addr) << 1;
sys/dev/sound/pci/emu10kx.c
2748
sc->mem.ptb_pages[i] = tmp | i;
sys/dev/sound/pci/emu10kx.c
2751
emu_wrptr(sc, ch, EMU_CHAN_MAPA, tmp | EMU_CHAN_MAP_PTI_MASK);
sys/dev/sound/pci/emu10kx.c
2752
emu_wrptr(sc, ch, EMU_CHAN_MAPB, tmp | EMU_CHAN_MAP_PTI_MASK);
sys/dev/sound/pci/emu10kx.c
2830
tmp = emu_rd(sc, EMU_A_IOCFG, 2);
sys/dev/sound/pci/emu10kx.c
2831
emu_wr(sc, EMU_A_IOCFG, tmp & ~0x8, 2);
sys/dev/sound/pci/emu10kx.c
2846
tmp = emu_rd(sc, EMU_HCFG, 4);
sys/dev/sound/pci/emu10kx.c
2847
device_printf(sc->dev, "Card Configuration ( 0x%08x )\n", tmp);
sys/dev/sound/pci/emu10kx.c
2849
(tmp & 0x80000000 ? "[Legacy MPIC] " : ""),
sys/dev/sound/pci/emu10kx.c
2850
(tmp & 0x40000000 ? "[0x40] " : ""),
sys/dev/sound/pci/emu10kx.c
2851
(tmp & 0x20000000 ? "[0x20] " : ""),
sys/dev/sound/pci/emu10kx.c
2852
(tmp & 0x10000000 ? "[0x10] " : ""),
sys/dev/sound/pci/emu10kx.c
2853
(tmp & 0x08000000 ? "[0x08] " : ""),
sys/dev/sound/pci/emu10kx.c
2854
(tmp & 0x04000000 ? "[0x04] " : ""),
sys/dev/sound/pci/emu10kx.c
2855
(tmp & 0x02000000 ? "[0x02] " : ""),
sys/dev/sound/pci/emu10kx.c
2856
(tmp & 0x01000000 ? "[0x01]" : " "));
sys/dev/sound/pci/emu10kx.c
2858
(tmp & 0x00800000 ? "[0x80] " : ""),
sys/dev/sound/pci/emu10kx.c
2859
(tmp & 0x00400000 ? "[0x40] " : ""),
sys/dev/sound/pci/emu10kx.c
2860
(tmp & 0x00200000 ? "[Legacy INT] " : ""),
sys/dev/sound/pci/emu10kx.c
2861
(tmp & 0x00100000 ? "[0x10] " : ""),
sys/dev/sound/pci/emu10kx.c
2862
(tmp & 0x00080000 ? "[0x08] " : ""),
sys/dev/sound/pci/emu10kx.c
2863
(tmp & 0x00040000 ? "[Codec4] " : ""),
sys/dev/sound/pci/emu10kx.c
2864
(tmp & 0x00020000 ? "[Codec2] " : ""),
sys/dev/sound/pci/emu10kx.c
2865
(tmp & 0x00010000 ? "[I2S Codec]" : " "));
sys/dev/sound/pci/emu10kx.c
2867
(tmp & 0x00008000 ? "[0x80] " : ""),
sys/dev/sound/pci/emu10kx.c
2868
(tmp & 0x00004000 ? "[GPINPUT0] " : ""),
sys/dev/sound/pci/emu10kx.c
2869
(tmp & 0x00002000 ? "[GPINPUT1] " : ""),
sys/dev/sound/pci/emu10kx.c
2870
(tmp & 0x00001000 ? "[GPOUT0] " : ""),
sys/dev/sound/pci/emu10kx.c
2871
(tmp & 0x00000800 ? "[GPOUT1] " : ""),
sys/dev/sound/pci/emu10kx.c
2872
(tmp & 0x00000400 ? "[GPOUT2] " : ""),
sys/dev/sound/pci/emu10kx.c
2873
(tmp & 0x00000200 ? "[Joystick] " : ""),
sys/dev/sound/pci/emu10kx.c
2874
(tmp & 0x00000100 ? "[0x01]" : " "));
sys/dev/sound/pci/emu10kx.c
2876
(tmp & 0x00000080 ? "[0x80] " : ""),
sys/dev/sound/pci/emu10kx.c
2877
(tmp & 0x00000040 ? "[0x40] " : ""),
sys/dev/sound/pci/emu10kx.c
2878
(tmp & 0x00000020 ? "[0x20] " : ""),
sys/dev/sound/pci/emu10kx.c
2879
(tmp & 0x00000010 ? "[AUTOMUTE] " : ""),
sys/dev/sound/pci/emu10kx.c
2880
(tmp & 0x00000008 ? "[LOCKSOUNDCACHE] " : ""),
sys/dev/sound/pci/emu10kx.c
2881
(tmp & 0x00000004 ? "[LOCKTANKCACHE] " : ""),
sys/dev/sound/pci/emu10kx.c
2882
(tmp & 0x00000002 ? "[MUTEBUTTONENABLE] " : ""),
sys/dev/sound/pci/emu10kx.c
2883
(tmp & 0x00000001 ? "[AUDIOENABLE]" : " "));
sys/dev/sound/pci/emu10kx.c
2886
tmp = emu_rd(sc, EMU_A_IOCFG, 2);
sys/dev/sound/pci/emu10kx.c
2887
device_printf(sc->dev, "Audigy Card Configuration ( 0x%04x )\n", tmp);
sys/dev/sound/pci/emu10kx.c
2890
(tmp & 0x8000 ? "[Rear Speakers] " : ""),
sys/dev/sound/pci/emu10kx.c
2891
(tmp & 0x4000 ? "[Front Speakers] " : ""),
sys/dev/sound/pci/emu10kx.c
2892
(tmp & 0x2000 ? "[0x20] " : ""),
sys/dev/sound/pci/emu10kx.c
2893
(tmp & 0x1000 ? "[0x10] " : ""),
sys/dev/sound/pci/emu10kx.c
2894
(tmp & 0x0800 ? "[0x08] " : ""),
sys/dev/sound/pci/emu10kx.c
2895
(tmp & 0x0400 ? "[0x04] " : ""),
sys/dev/sound/pci/emu10kx.c
2896
(tmp & 0x0200 ? "[0x02] " : ""),
sys/dev/sound/pci/emu10kx.c
2897
(tmp & 0x0100 ? "[AudigyDrive Phones]" : " "));
sys/dev/sound/pci/emu10kx.c
2900
(tmp & 0x0080 ? "[0x80] " : ""),
sys/dev/sound/pci/emu10kx.c
2901
(tmp & 0x0040 ? "[Mute AnalogOut] " : ""),
sys/dev/sound/pci/emu10kx.c
2902
(tmp & 0x0020 ? "[0x20] " : ""),
sys/dev/sound/pci/emu10kx.c
2903
(tmp & 0x0010 ? "[0x10] " : ""),
sys/dev/sound/pci/emu10kx.c
2904
(tmp & 0x0008 ? "[0x08] " : ""),
sys/dev/sound/pci/emu10kx.c
2905
(tmp & 0x0004 ? "[GPOUT0] " : ""),
sys/dev/sound/pci/emu10kx.c
2906
(tmp & 0x0002 ? "[GPOUT1] " : ""),
sys/dev/sound/pci/emu10kx.c
2907
(tmp & 0x0001 ? "[GPOUT2]" : " "));
sys/dev/sound/pci/envy24.c
525
u_int32_t tmp;
sys/dev/sound/pci/envy24.c
532
tmp = envy24_rdcs(sc, ENVY24_CCS_I2CSTAT, 1);
sys/dev/sound/pci/envy24.c
533
if ((tmp & ENVY24_CCS_I2CSTAT_BSY) == 0)
sys/dev/sound/pci/envy24ht.c
563
u_int32_t tmp;
sys/dev/sound/pci/envy24ht.c
570
tmp = envy24ht_rdcs(sc, ENVY24HT_CCS_I2CSTAT, 1);
sys/dev/sound/pci/envy24ht.c
571
if ((tmp & ENVY24HT_CCS_I2CSTAT_BSY) == 0)
sys/dev/sound/pci/t4dwave.c
742
int tmp;
sys/dev/sound/pci/t4dwave.c
754
tmp = (bufhalf & mask)? 1 : 0;
sys/dev/sound/pci/t4dwave.c
758
if (ch->bufhalf != tmp) {
sys/dev/sound/pci/t4dwave.c
760
ch->bufhalf = tmp;
sys/dev/sound/pcm/channel.c
1134
char tmp[AFMTSTR_LEN];
sys/dev/sound/pcm/channel.c
1140
bzero(tmp, sizeof(tmp));
sys/dev/sound/pcm/channel.c
1148
strlcpy(tmp, afmt_tab[i].name, sizeof(tmp));
sys/dev/sound/pcm/channel.c
1149
strlcat(tmp, ":", sizeof(tmp));
sys/dev/sound/pcm/channel.c
1154
if (strlen(tmp) == 0)
sys/dev/sound/pcm/channel.c
1161
strlcat(tmp, matrix_id_tab[i].name, sizeof(tmp));
sys/dev/sound/pcm/channel.c
1166
if (strlen(tmp) == 0)
sys/dev/sound/pcm/channel.c
1169
strlcpy(buf, tmp, len);
sys/dev/sound/pcm/channel.c
1593
u_int32_t ret, tmp;
sys/dev/sound/pcm/channel.c
1603
tmp = ret - (ret % round);
sys/dev/sound/pcm/channel.c
1604
while (tmp < 16 || tmp < round) {
sys/dev/sound/pcm/channel.c
1606
tmp = ret - (ret % round);
sys/dev/sound/pcm/dsp.c
1099
int *arg_i, ret, tmp;
sys/dev/sound/pcm/dsp.c
1433
tmp = 0;
sys/dev/sound/pcm/dsp.c
1438
tmp = wrch->speed;
sys/dev/sound/pcm/dsp.c
1444
if (tmp == 0)
sys/dev/sound/pcm/dsp.c
1445
tmp = rdch->speed;
sys/dev/sound/pcm/dsp.c
1449
*arg_i = tmp;
sys/dev/sound/pcm/dsp.c
1465
tmp = -1;
sys/dev/sound/pcm/dsp.c
1472
tmp = (AFMT_CHANNEL(wrch->format) > 1)? 1 : 0;
sys/dev/sound/pcm/dsp.c
1479
if (tmp == -1)
sys/dev/sound/pcm/dsp.c
1480
tmp = (AFMT_CHANNEL(rdch->format) > 1)? 1 : 0;
sys/dev/sound/pcm/dsp.c
1484
*arg_i = tmp;
sys/dev/sound/pcm/dsp.c
1498
tmp = 0;
sys/dev/sound/pcm/dsp.c
1513
tmp = AFMT_CHANNEL(wrch->format);
sys/dev/sound/pcm/dsp.c
1520
if (tmp == 0)
sys/dev/sound/pcm/dsp.c
1521
tmp = AFMT_CHANNEL(rdch->format);
sys/dev/sound/pcm/dsp.c
1525
*arg_i = tmp;
sys/dev/sound/pcm/dsp.c
1560
tmp = 0;
sys/dev/sound/pcm/dsp.c
1567
tmp = wrch->format;
sys/dev/sound/pcm/dsp.c
1575
if (tmp == 0)
sys/dev/sound/pcm/dsp.c
1576
tmp = rdch->format;
sys/dev/sound/pcm/dsp.c
1580
*arg_i = AFMT_ENCODING(tmp);
sys/dev/sound/pcm/dsp.c
1988
tmp = (sndbuf_getsize(b) + chn_getptr(chn) - sndbuf_gethwptr(b)) % sndbuf_getsize(b);
sys/dev/sound/pcm/dsp.c
1989
oc->samples = (sndbuf_gettotal(b) + tmp) / sndbuf_getalign(b);
sys/dev/sound/pcm/dsp.c
1990
oc->fifo_samples = (sndbuf_getready(b) - tmp) / sndbuf_getalign(b);
sys/dev/sound/pcm/dsp.c
281
struct dsp_cdevinfo *cdi, *tmp;
sys/dev/sound/pcm/dsp.c
315
TAILQ_FOREACH_MUTABLE(cdi, &d->dsp_cdevinfo_pool, link, tmp) {
sys/dev/sound/pcm/dsp.c
354
struct dsp_cdevinfo *cdi, *tmp;
sys/dev/sound/pcm/dsp.c
362
tmp = TAILQ_NEXT(cdi, link);
sys/dev/sound/pcm/dsp.c
364
cdi = tmp;
sys/dev/sound/pcm/feeder_matrix.c
774
struct pcmchan_matrix tmp;
sys/dev/sound/pcm/feeder_matrix.c
782
tmp = *m;
sys/dev/sound/pcm/feeder_matrix.c
783
tmp.channels = 0;
sys/dev/sound/pcm/feeder_matrix.c
784
tmp.ext = 0;
sys/dev/sound/pcm/feeder_matrix.c
785
tmp.mask = 0;
sys/dev/sound/pcm/feeder_matrix.c
786
memset(tmp.offset, -1, sizeof(tmp.offset));
sys/dev/sound/pcm/feeder_matrix.c
795
tmp.map[i] = m->map[i];
sys/dev/sound/pcm/feeder_matrix.c
807
if (chmask & tmp.mask)
sys/dev/sound/pcm/feeder_matrix.c
809
tmp.map[i] = m->map[m->offset[ch]];
sys/dev/sound/pcm/feeder_matrix.c
810
if (tmp.map[i].type != ch)
sys/dev/sound/pcm/feeder_matrix.c
812
tmp.offset[ch] = i;
sys/dev/sound/pcm/feeder_matrix.c
813
tmp.mask |= chmask;
sys/dev/sound/pcm/feeder_matrix.c
814
tmp.channels++;
sys/dev/sound/pcm/feeder_matrix.c
816
tmp.ext++;
sys/dev/sound/pcm/feeder_matrix.c
819
if (tmp.channels != m->channels || tmp.ext != m->ext ||
sys/dev/sound/pcm/feeder_matrix.c
820
tmp.mask != m->mask ||
sys/dev/sound/pcm/feeder_matrix.c
821
tmp.map[m->channels].type != SND_CHN_T_MAX)
sys/dev/sound/pcm/feeder_matrix.c
824
*m = tmp;
sys/dev/sound/pcm/feeder_mixer.c
288
uint8_t *tmp;
sys/dev/sound/pcm/feeder_mixer.c
309
tmp = sndbuf_getbuf(src);
sys/dev/sound/pcm/feeder_mixer.c
343
FEEDER_FEED(ch->feeder, ch, tmp, count,
sys/dev/sound/pcm/feeder_mixer.c
356
FEEDER_FEED(ch->feeder, ch, tmp, count,
sys/dev/sound/pcm/feeder_mixer.c
365
tmp, count, ch->bufsoft), sz);
sys/dev/sound/pcm/feeder_mixer.c
373
info->mix(tmp, b, cnt);
sys/dev/sound/pcm/sound.c
655
struct pcm_channel *tmp;
sys/dev/sound/pcm/sound.c
660
tmp = NULL;
sys/dev/sound/pcm/sound.c
662
CHN_FOREACH(tmp, d, channels.pcm) {
sys/dev/sound/pcm/sound.c
663
if (tmp == ch)
sys/dev/sound/pcm/sound.c
667
if (tmp != ch)
sys/kern/kern_acct.c
201
struct timeval tmp;
sys/kern/kern_acct.c
234
microtime(&tmp);
sys/kern/kern_acct.c
235
timevalsub(&tmp, &p->p_start);
sys/kern/kern_acct.c
236
acct.ac_etime = encode_comp_t(tmp.tv_sec, tmp.tv_usec);
sys/kern/kern_acct.c
240
tmp = ru.ru_utime;
sys/kern/kern_acct.c
241
timevaladd(&tmp, &ru.ru_stime);
sys/kern/kern_acct.c
242
t = tmp.tv_sec * hz + tmp.tv_usec / ustick;
sys/kern/kern_clock.c
142
struct kinfo_cputime tmp;
sys/kern/kern_clock.c
150
tmp = cputime_percpu[cpu];
sys/kern/kern_clock.c
152
tmp.cp_sample_pc =
sys/kern/kern_clock.c
154
tmp.cp_sample_sp =
sys/kern/kern_clock.c
157
if ((error = SYSCTL_OUT(req, &tmp, size)) != 0)
sys/kern/kern_descrip.c
709
int tmp, error, flg = F_POSIX;
sys/kern/kern_descrip.c
718
error = fgetfdflags(p->p_fd, fd, &tmp);
sys/kern/kern_descrip.c
720
dat->fc_fdflags = ((tmp & UF_EXCLOSE) ? FD_CLOEXEC : 0) |
sys/kern/kern_descrip.c
721
((tmp & UF_FOCLOSE) ? FD_CLOFORK : 0);
sys/kern/kern_descrip.c
797
tmp = nflags & FASYNC;
sys/kern/kern_descrip.c
798
error = fo_ioctl(fp, FIOASYNC, (caddr_t)&tmp,
sys/kern/kern_environment.c
363
char *tmp;
sys/kern/kern_environment.c
365
tmp = kgetenv(name);
sys/kern/kern_environment.c
366
if (tmp != NULL) {
sys/kern/kern_environment.c
367
strncpy(data, tmp, size);
sys/kern/kern_environment.c
369
kfreeenv(tmp);
sys/kern/kern_environment.c
381
quad_t tmp;
sys/kern/kern_environment.c
384
rval = kgetenv_quad(name, &tmp);
sys/kern/kern_environment.c
386
*data = (int) tmp;
sys/kern/kern_environment.c
396
quad_t tmp;
sys/kern/kern_environment.c
399
rval = kgetenv_quad(name, &tmp);
sys/kern/kern_environment.c
401
*data = (long)tmp;
sys/kern/kern_environment.c
411
quad_t tmp;
sys/kern/kern_environment.c
414
rval = kgetenv_quad(name, &tmp);
sys/kern/kern_environment.c
416
*data = (unsigned long) tmp;
sys/kern/kern_resource.c
923
struct uidinfo *uip, *tmp;
sys/kern/kern_resource.c
945
tmp = uilookup(uid);
sys/kern/kern_resource.c
946
if (tmp != NULL) {
sys/kern/kern_resource.c
947
uihold(tmp);
sys/kern/kern_resource.c
954
uip = tmp;
sys/kern/kern_sysctl.c
339
struct sysctl_oid *p, *tmp;
sys/kern/kern_sysctl.c
359
SYSCTL_CHILDREN(oidp), oid_link, tmp) {
sys/kern/kern_sysctl.c
414
struct sysctl_oid *p, *tmp;
sys/kern/kern_sysctl.c
419
SLIST_FOREACH_MUTABLE(p, SYSCTL_CHILDREN(parent), oid_link, tmp) {
sys/kern/subr_bus.c
1996
device_t tmp;
sys/kern/subr_bus.c
1999
for (tmp = dev->parent; tmp; tmp = tmp->parent)
sys/kern/subr_bus.c
2000
kprintf(".%s", device_get_nameunit(tmp));
sys/kern/subr_bus.c
2052
device_t tmp;
sys/kern/subr_bus.c
2055
for (tmp = dev->parent; tmp; tmp = tmp->parent)
sys/kern/subr_bus.c
2056
kprintf(".%s", device_get_nameunit(tmp));
sys/kern/subr_bus.c
636
char *tmp = NULL;
sys/kern/subr_bus.c
641
tmp = kmalloc(1024, M_BUS, M_NOWAIT);
sys/kern/subr_bus.c
642
if (tmp == NULL)
sys/kern/subr_bus.c
646
ksnprintf(tmp, 1024, "%s %s", device_get_nameunit(dev), pnp);
sys/kern/subr_bus.c
647
devaddq("+", tmp, dev);
sys/kern/subr_bus.c
651
if (tmp != NULL)
sys/kern/subr_bus.c
652
kfree(tmp, M_BUS);
sys/kern/subr_bus.c
664
char *tmp = NULL;
sys/kern/subr_bus.c
669
tmp = kmalloc(1024, M_BUS, M_NOWAIT);
sys/kern/subr_bus.c
670
if (tmp == NULL)
sys/kern/subr_bus.c
674
ksnprintf(tmp, 1024, "%s %s", device_get_nameunit(dev), pnp);
sys/kern/subr_bus.c
675
devaddq("-", tmp, dev);
sys/kern/subr_bus.c
679
if (tmp != NULL)
sys/kern/subr_bus.c
680
kfree(tmp, M_BUS);
sys/kern/subr_prf.c
559
int base, tmp, width, ladjust, sharpflag, spaceflag, neg, sign, dot;
sys/kern/subr_prf.c
717
for (tmp = 0; *p;) {
sys/kern/subr_prf.c
720
PCHAR(tmp ? ',' : '<');
sys/kern/subr_prf.c
723
tmp = 1;
sys/kern/subr_prf.c
729
if (tmp)
sys/kern/subr_prf.c
828
tmp = 0;
sys/kern/subr_prf.c
831
tmp++;
sys/kern/subr_prf.c
833
tmp += 2;
sys/kern/subr_prf.c
836
tmp++;
sys/kern/subr_prf.c
839
dwidth = width - tmp;
sys/kern/subr_prf.c
840
width -= tmp + imax(dwidth, n);
sys/kern/sys_generic.c
571
int tmp;
sys/kern/sys_generic.c
701
if ((tmp = *(int *)data))
sys/kern/sys_generic.c
709
if ((tmp = *(int *)data))
sys/kern/sys_generic.c
713
error = fo_ioctl(fp, FIOASYNC, (caddr_t)&tmp, cred, msg);
sys/kern/sys_process.c
142
int write, tmp;
sys/kern/sys_process.c
398
tmp = 0;
sys/kern/sys_process.c
400
iov.iov_base = write ? (caddr_t)&data : (caddr_t)&tmp;
sys/kern/sys_process.c
424
*res = tmp;
sys/kern/tty.c
2511
int tmp;
sys/kern/tty.c
2522
tmp = (averunnable.ldavg[0] * 100 + FSCALE / 2) >> FSHIFT;
sys/kern/tty.c
2523
ttyprintf(tp, "load: %d.%02d ", tmp / 100, tmp % 100);
sys/kern/uipc_syscalls.c
296
int error, tmp;
sys/kern/uipc_syscalls.c
382
tmp = fflag & FASYNC;
sys/kern/uipc_syscalls.c
383
fo_ioctl(nfp, FIOASYNC, (caddr_t)&tmp, td->td_ucred, NULL);
sys/kern/vfs_subr.c
2629
union _qcvt tmp; \
sys/kern/vfs_subr.c
2630
tmp.qcvt = (q); \
sys/kern/vfs_subr.c
2631
tmp.val[_QUAD_HIGHWORD] = (h); \
sys/kern/vfs_subr.c
2632
(q) = tmp.qcvt; \
sys/kern/vfs_subr.c
2635
union _qcvt tmp; \
sys/kern/vfs_subr.c
2636
tmp.qcvt = (q); \
sys/kern/vfs_subr.c
2637
tmp.val[_QUAD_LOWWORD] = (l); \
sys/kern/vfs_subr.c
2638
(q) = tmp.qcvt; \
sys/libkern/inet_ntop.c
142
tp = tmp;
sys/libkern/inet_ntop.c
158
if (!inet_ntop4(src+12, tp, sizeof tmp - (tp - tmp)))
sys/libkern/inet_ntop.c
174
if ((socklen_t)(tp - tmp) > size) {
sys/libkern/inet_ntop.c
177
strcpy(dst, tmp);
sys/libkern/inet_ntop.c
72
char tmp[sizeof "255.255.255.255"];
sys/libkern/inet_ntop.c
75
l = ksnprintf(tmp, sizeof(tmp), fmt, src[0], src[1], src[2], src[3]);
sys/libkern/inet_ntop.c
79
strlcpy(dst, tmp, size);
sys/libkern/inet_ntop.c
99
char tmp[sizeof "ffff:ffff:ffff:ffff:ffff:ffff:255.255.255.255"], *tp;
sys/libprop/prop_rb.c
113
struct rb_node *parent, *tmp, *self = RB_ITEMTONODE(rbto, object);
sys/libprop/prop_rb.c
119
tmp = rbt->rbt_root;
sys/libprop/prop_rb.c
133
while (!RB_SENTINEL_P(tmp)) {
sys/libprop/prop_rb.c
134
void *tobj = RB_NODETOITEM(rbto, tmp);
sys/libprop/prop_rb.c
143
parent = tmp;
sys/libprop/prop_rb.c
145
tmp = parent->rb_nodes[position];
sys/libprop/prop_rb.c
154
else if (tmp != rbt->rbt_root)
sys/libprop/prop_rb.c
292
struct rb_node tmp;
sys/libprop/prop_rb.c
293
tmp.rb_info = 0;
sys/libprop/prop_rb.c
294
RB_COPY_PROPERTIES(&tmp, old_child);
sys/libprop/prop_rb.c
296
RB_COPY_PROPERTIES(new_child, &tmp);
sys/net/dummynet/ip_dummynet.c
298
struct dn_heap_entry tmp;
sys/net/dummynet/ip_dummynet.c
304
HEAP_SWAP(h->p[son], h->p[father], tmp);
sys/net/dummynet3/ip_dummynet3.c
317
struct dn_heap_entry tmp;
sys/net/dummynet3/ip_dummynet3.c
323
HEAP_SWAP(h->p[son], h->p[father], tmp);
sys/net/ip_mroute/ip_mroute.c
2645
struct bw_meter *prev, *tmp;
sys/net/ip_mroute/ip_mroute.c
2657
for (prev = NULL, tmp = bw_meter_timers[time_hash];
sys/net/ip_mroute/ip_mroute.c
2658
tmp != NULL; prev = tmp, tmp = tmp->bm_time_next)
sys/net/ip_mroute/ip_mroute.c
2659
if (tmp == x)
sys/net/ip_mroute/ip_mroute.c
2662
if (tmp == NULL)
sys/net/ipfw3/ip_fw3.c
172
struct ipfw3_module *tmp;
sys/net/ipfw3/ip_fw3.c
175
tmp = fw3_modules;
sys/net/ipfw3/ip_fw3.c
177
if (tmp->type == 0) {
sys/net/ipfw3/ip_fw3.c
178
tmp->type = 1;
sys/net/ipfw3/ip_fw3.c
179
tmp->id = module_id;
sys/net/ipfw3/ip_fw3.c
180
strncpy(tmp->name, module_name, strlen(module_name));
sys/net/ipfw3/ip_fw3.c
183
tmp++;
sys/net/ipfw3/ip_fw3.c
191
struct ipfw3_module *tmp;
sys/net/ipfw3/ip_fw3.c
197
tmp = fw3_modules;
sys/net/ipfw3/ip_fw3.c
219
if (tmp->type == 1 && tmp->id == module_id) {
sys/net/ipfw3/ip_fw3.c
220
tmp->type = 0;
sys/net/ipfw3/ip_fw3.c
222
tmp->name);
sys/net/ipfw3/ip_fw3.c
225
tmp++;
sys/net/ipfw3_basic/ip_fw3_state.c
364
struct ipfw3_state *s, *tmp;
sys/net/ipfw3_basic/ip_fw3_state.c
366
RB_FOREACH_SAFE(s, fw3_state_tree, &state_ctx->rb_icmp_in, tmp) {
sys/net/ipfw3_basic/ip_fw3_state.c
372
RB_FOREACH_SAFE(s, fw3_state_tree, &state_ctx->rb_icmp_out, tmp) {
sys/net/ipfw3_basic/ip_fw3_state.c
378
RB_FOREACH_SAFE(s, fw3_state_tree, &state_ctx->rb_tcp_in, tmp) {
sys/net/ipfw3_basic/ip_fw3_state.c
384
RB_FOREACH_SAFE(s, fw3_state_tree, &state_ctx->rb_tcp_out, tmp) {
sys/net/ipfw3_basic/ip_fw3_state.c
390
RB_FOREACH_SAFE(s, fw3_state_tree, &state_ctx->rb_udp_in, tmp) {
sys/net/ipfw3_basic/ip_fw3_state.c
396
RB_FOREACH_SAFE(s, fw3_state_tree, &state_ctx->rb_udp_out, tmp) {
sys/net/ipfw3_basic/ip_fw3_state.c
543
struct ipfw3_state *s, *tmp;
sys/net/ipfw3_basic/ip_fw3_state.c
545
RB_FOREACH_SAFE(s, fw3_state_tree, &state_ctx->rb_icmp_in, tmp) {
sys/net/ipfw3_basic/ip_fw3_state.c
551
RB_FOREACH_SAFE(s, fw3_state_tree, &state_ctx->rb_icmp_out, tmp) {
sys/net/ipfw3_basic/ip_fw3_state.c
557
RB_FOREACH_SAFE(s, fw3_state_tree, &state_ctx->rb_tcp_in, tmp) {
sys/net/ipfw3_basic/ip_fw3_state.c
563
RB_FOREACH_SAFE(s, fw3_state_tree, &state_ctx->rb_tcp_out, tmp) {
sys/net/ipfw3_basic/ip_fw3_state.c
569
RB_FOREACH_SAFE(s, fw3_state_tree, &state_ctx->rb_udp_in, tmp) {
sys/net/ipfw3_basic/ip_fw3_state.c
575
RB_FOREACH_SAFE(s, fw3_state_tree, &state_ctx->rb_udp_out, tmp) {
sys/net/ipfw3_basic/ip_fw3_state.c
621
struct ipfw3_state_context *tmp;
sys/net/ipfw3_basic/ip_fw3_state.c
623
tmp = kmalloc(LEN_STATE_CTX, M_IPFW3_STATE, M_WAITOK | M_ZERO);
sys/net/ipfw3_basic/ip_fw3_state.c
624
RB_INIT(&tmp->rb_icmp_in);
sys/net/ipfw3_basic/ip_fw3_state.c
625
RB_INIT(&tmp->rb_icmp_out);
sys/net/ipfw3_basic/ip_fw3_state.c
626
RB_INIT(&tmp->rb_tcp_in);
sys/net/ipfw3_basic/ip_fw3_state.c
627
RB_INIT(&tmp->rb_tcp_out);
sys/net/ipfw3_basic/ip_fw3_state.c
628
RB_INIT(&tmp->rb_udp_in);
sys/net/ipfw3_basic/ip_fw3_state.c
629
RB_INIT(&tmp->rb_udp_out);
sys/net/ipfw3_basic/ip_fw3_state.c
630
fw3_state_ctx[mycpuid] = tmp;
sys/net/ipfw3_basic/ip_fw3_state.c
638
struct ipfw3_state *s, *tmp;
sys/net/ipfw3_basic/ip_fw3_state.c
640
RB_FOREACH_SAFE(s, fw3_state_tree, &state_ctx->rb_icmp_in, tmp) {
sys/net/ipfw3_basic/ip_fw3_state.c
646
RB_FOREACH_SAFE(s, fw3_state_tree, &state_ctx->rb_icmp_out, tmp) {
sys/net/ipfw3_basic/ip_fw3_state.c
652
RB_FOREACH_SAFE(s, fw3_state_tree, &state_ctx->rb_tcp_in, tmp) {
sys/net/ipfw3_basic/ip_fw3_state.c
658
RB_FOREACH_SAFE(s, fw3_state_tree, &state_ctx->rb_tcp_out, tmp) {
sys/net/ipfw3_basic/ip_fw3_state.c
664
RB_FOREACH_SAFE(s, fw3_state_tree, &state_ctx->rb_udp_in, tmp) {
sys/net/ipfw3_basic/ip_fw3_state.c
670
RB_FOREACH_SAFE(s, fw3_state_tree, &state_ctx->rb_udp_out, tmp) {
sys/net/ipfw3_nat/ip_fw3_nat.c
130
uint32_t tmp;
sys/net/ipfw3_nat/ip_fw3_nat.c
134
tmp = cksum + old_info - new_info;
sys/net/ipfw3_nat/ip_fw3_nat.c
135
tmp = (tmp >> 16) + (tmp & 65535);
sys/net/ipfw3_nat/ip_fw3_nat.c
136
tmp = tmp & 65535;
sys/net/ipfw3_nat/ip_fw3_nat.c
137
if (is_udp && !tmp)
sys/net/ipfw3_nat/ip_fw3_nat.c
139
return tmp;
sys/net/ipfw3_nat/ip_fw3_nat.c
791
struct nat_state *s, *tmp;
sys/net/ipfw3_nat/ip_fw3_nat.c
800
RB_FOREACH_SAFE(s, state_tree, &nat->rb_icmp_out, tmp) {
sys/net/ipfw3_nat/ip_fw3_nat.c
815
RB_FOREACH_SAFE(s, state_tree, &nat->rb_tcp_out, tmp) {
sys/net/ipfw3_nat/ip_fw3_nat.c
829
RB_FOREACH_SAFE(s, state_tree, &nat->rb_udp_out, tmp) {
sys/net/ipfw3_nat/ip_fw3_nat.c
910
struct ip_fw3_nat_context *tmp;
sys/net/ipfw3_nat/ip_fw3_nat.c
911
tmp = kmalloc(sizeof(struct ip_fw3_nat_context),
sys/net/ipfw3_nat/ip_fw3_nat.c
914
ip_fw3_nat_ctx[mycpuid] = tmp;
sys/net/ipfw3_nat/ip_fw3_nat.c
928
struct nat_state *s, *tmp;
sys/net/ipfw3_nat/ip_fw3_nat.c
942
RB_FOREACH_SAFE(s, state_tree, &nat->rb_icmp_out, tmp) {
sys/net/ipfw3_nat/ip_fw3_nat.c
961
RB_FOREACH_SAFE(s, state_tree, &nat->rb_tcp_out, tmp) {
sys/net/ipfw3_nat/ip_fw3_nat.c
979
RB_FOREACH_SAFE(s, state_tree, &nat->rb_udp_out, tmp) {
sys/net/netmap/netmap.c
802
struct netmap_slot *src, *dst, tmp;
sys/net/netmap/netmap.c
805
tmp = *src;
sys/net/netmap/netmap.c
809
dst->buf_idx = tmp.buf_idx;
sys/net/netmap/netmap.c
810
dst->len = tmp.len;
sys/net/netmap/netmap_vale.c
433
uint8_t tmp[NM_BDG_MAXPORTS];
sys/net/netmap/netmap_vale.c
449
memcpy(tmp, b->bdg_port_index, sizeof(tmp));
sys/net/netmap/netmap_vale.c
451
if (hw >= 0 && tmp[i] == hw) {
sys/net/netmap/netmap_vale.c
454
tmp[i] = tmp[lim]; /* swap with i */
sys/net/netmap/netmap_vale.c
455
tmp[lim] = hw; /* now this is inactive */
sys/net/netmap/netmap_vale.c
457
} else if (sw >= 0 && tmp[i] == sw) {
sys/net/netmap/netmap_vale.c
460
tmp[i] = tmp[lim];
sys/net/netmap/netmap_vale.c
461
tmp[lim] = sw;
sys/net/netmap/netmap_vale.c
476
memcpy(b->bdg_port_index, tmp, sizeof(tmp));
sys/net/pf/if_pflog.c
310
struct pflog_softc *pflogif, *tmp;
sys/net/pf/if_pflog.c
324
LIST_FOREACH_MUTABLE(pflogif, &pflogif_list, sc_list, tmp)
sys/net/pf/if_pfsync.c
1754
struct pfsync_softc *pfs_if, *tmp;
sys/net/pf/if_pfsync.c
1771
LIST_FOREACH_MUTABLE(pfs_if, &pfsync_list, sc_next, tmp) {
sys/net/pf/pf.c
3005
u_int16_t tmp;
sys/net/pf/pf.c
3008
tmp = low;
sys/net/pf/pf.c
3010
high = tmp;
sys/net/pf/pf.c
3015
for (tmp = cut; tmp <= high; ++(tmp)) {
sys/net/pf/pf.c
3016
key.port[1] = htons(tmp);
sys/net/pf/pf.c
3026
NULL && !in_baddynamic(tmp, proto)) {
sys/net/pf/pf.c
3029
*nport = htons(tmp);
sys/net/pf/pf.c
3033
for (tmp = cut - 1; tmp >= low; --(tmp)) {
sys/net/pf/pf.c
3034
key.port[1] = htons(tmp);
sys/net/pf/pf.c
3044
NULL && !in_baddynamic(tmp, proto)) {
sys/net/pf/pf.c
3047
*nport = htons(tmp);
sys/net/pf/pf_if.c
856
u_int32_t tmp;
sys/net/pf/pf_if.c
863
tmp = ntohl(m->addr32[j]);
sys/net/pf/pf_if.c
864
for (i = 31; tmp & (1 << i); --i)
sys/net/pf/pf_table.c
84
type tmp = a1; \
sys/net/pf/pf_table.c
86
a2 = tmp; \
sys/net/wg/wg_noise.c
1525
uint8_t tmp[NOISE_HASH_LEN];
sys/net/wg/wg_noise.c
1527
noise_kdf(ck, tmp, key, psk,
sys/net/wg/wg_noise.c
1530
noise_mix_hash(hash, tmp, NOISE_HASH_LEN);
sys/net/wg/wg_noise.c
1531
explicit_bzero(tmp, NOISE_HASH_LEN);
sys/netgraph/ng_device.c
227
struct ngd_connection *tmp = NULL;
sys/netgraph/ng_device.c
247
SLIST_FOREACH(tmp, &sc->head, links) {
sys/netgraph/ng_device.c
249
if(tmp->unit == n) {
sys/netgraph/ng_device.c
338
struct ngd_connection * tmp;
sys/netgraph/ng_device.c
345
SLIST_FOREACH(tmp, &sc->head, links) {
sys/netgraph/ng_device.c
346
if(tmp->active_hook == hook) {
sys/netgraph/ng_device.c
347
connection = tmp;
sys/netgraph/ng_device.c
390
struct ngd_connection * tmp;
sys/netgraph/ng_device.c
396
SLIST_FOREACH(tmp, &sc->head, links) {
sys/netgraph/ng_device.c
397
if(tmp->active_hook == hook) {
sys/netgraph/ng_device.c
398
connection = tmp;
sys/netgraph/ng_device.c
455
struct ngd_connection * tmp;
sys/netgraph/ng_device.c
464
SLIST_FOREACH(tmp, &sc->head, links) {
sys/netgraph/ng_device.c
465
if(tmp->ngddev == dev) {
sys/netgraph/ng_device.c
466
connection = tmp;
sys/netgraph/ng_device.c
512
struct ngd_connection * tmp;
sys/netgraph/ng_device.c
518
SLIST_FOREACH(tmp, &sc->head, links) {
sys/netgraph/ng_device.c
519
if(tmp->ngddev == dev) {
sys/netgraph/ng_device.c
520
connection = tmp;
sys/netgraph/ng_device.c
566
struct ngd_connection * tmp;
sys/netgraph/ng_device.c
572
SLIST_FOREACH(tmp, &sc->head, links) {
sys/netgraph/ng_device.c
573
if(tmp->ngddev == dev) {
sys/netgraph/ng_device.c
574
connection = tmp;
sys/netgraph/ng_device.c
612
struct ngd_connection * tmp;
sys/netgraph/ng_device.c
617
SLIST_FOREACH(tmp, &sc->head, links) {
sys/netgraph/ng_device.c
618
if(tmp->ngddev == dev) {
sys/netgraph/ng_device.c
619
connection = tmp;
sys/netgraph7/bpf/ng_bpf.c
269
hook_p tmp;
sys/netgraph7/bpf/ng_bpf.c
281
NG_NODE_FOREACH_HOOK(node, ng_bpf_addrefs, hook, tmp);
sys/netgraph7/bpf/ng_bpf.c
522
hook_p tmp;
sys/netgraph7/bpf/ng_bpf.c
527
NG_NODE_FOREACH_HOOK(node, ng_bpf_remrefs, hook, tmp);
sys/netgraph7/ng_device.c
376
struct ngd_connection * tmp;
sys/netinet/ip6.h
324
int tmp; \
sys/netinet/ip6.h
328
t = m_pulldown((m), (off), (len), &tmp); \
sys/netinet/ip6.h
330
if (t->m_len < tmp + (len)) \
sys/netinet/ip6.h
332
(val) = (typ)(mtod(t, caddr_t) + tmp); \
sys/netinet/ip_output.c
677
int length, tmp;
sys/netinet/ip_output.c
679
tmp = length = m->m_pkthdr.len;
sys/netinet/ip_output.c
690
m->m_pkthdr.len = tmp;
sys/netinet/tcp_subr.c
527
struct tcptemp *tmp;
sys/netinet/tcp_subr.c
529
if ((tmp = mpipe_alloc_nowait(&tcptemp_mpipe)) == NULL)
sys/netinet/tcp_subr.c
531
tcp_fillheaders(tp, &tmp->tt_ipgen, &tmp->tt_t, FALSE);
sys/netinet/tcp_subr.c
532
return (tmp);
sys/netinet/tcp_subr.c
536
tcp_freetemplate(struct tcptemp *tmp)
sys/netinet/tcp_subr.c
538
mpipe_free(&tcptemp_mpipe, tmp);
sys/netinet6/raw_ip6.c
660
struct sockaddr_in6 tmp;
sys/netinet6/raw_ip6.c
682
tmp = *addr;
sys/netinet6/raw_ip6.c
683
addr = &tmp;
sys/netinet6/raw_ip6.c
719
struct sockaddr_in6 tmp;
sys/netinet6/raw_ip6.c
731
bzero(&tmp, sizeof(tmp));
sys/netinet6/raw_ip6.c
732
tmp.sin6_family = AF_INET6;
sys/netinet6/raw_ip6.c
733
tmp.sin6_len = sizeof(struct sockaddr_in6);
sys/netinet6/raw_ip6.c
734
bcopy(&inp->in6p_faddr, &tmp.sin6_addr,
sys/netinet6/raw_ip6.c
736
dst = &tmp;
sys/netinet6/raw_ip6.c
743
tmp = *(struct sockaddr_in6 *)nam;
sys/netinet6/raw_ip6.c
744
dst = &tmp;
sys/netinet6/udp6_output.c
126
struct sockaddr_in6 tmp;
sys/netinet6/udp6_output.c
172
tmp = *sin6;
sys/netinet6/udp6_output.c
173
sin6 = &tmp;
sys/netproto/802_11/wlan/ieee80211_regdomain.c
174
uint8_t tmp = *_a; \
sys/netproto/802_11/wlan/ieee80211_regdomain.c
176
*s++ = tmp; \
sys/netproto/smb/smb_rq.c
451
u_int16_t tmp, bc, dcount;
sys/netproto/smb/smb_rq.c
482
if ((error = md_get_uint16le(mdp, &tmp)) != 0)
sys/netproto/smb/smb_rq.c
484
if (totpcount > tmp)
sys/netproto/smb/smb_rq.c
485
totpcount = tmp;
sys/netproto/smb/smb_rq.c
486
md_get_uint16le(mdp, &tmp);
sys/netproto/smb/smb_rq.c
487
if (totdcount > tmp)
sys/netproto/smb/smb_rq.c
488
totdcount = tmp;
sys/netproto/smb/smb_rq.c
489
if ((error = md_get_uint16le(mdp, &tmp)) != 0 || /* reserved */
sys/netproto/smb/smb_rq.c
511
tmp = wc;
sys/netproto/smb/smb_rq.c
512
while (tmp--)
sys/platform/pc64/x86_64/machdep.c
2384
uint64_t tmp;
sys/platform/pc64/x86_64/machdep.c
2449
tmp = *ptr;
sys/platform/pc64/x86_64/machdep.c
2483
*ptr = tmp;
sys/platform/pc64/x86_64/pmap_inval.c
236
cpumask_t tmp;
sys/platform/pc64/x86_64/pmap_inval.c
238
tmp = info->mask;
sys/platform/pc64/x86_64/pmap_inval.c
239
CPUMASK_ANDMASK(tmp, info->sigmask);
sys/platform/pc64/x86_64/pmap_inval.c
240
if (CPUMASK_CMPMASKNEQ(tmp, info->mask)) {
sys/platform/vkernel64/platform/init.c
1296
char *tmp;
sys/platform/vkernel64/platform/init.c
1312
tmp = netifExp[i];
sys/platform/vkernel64/platform/init.c
1313
strsep(&tmp, "=");
sys/platform/vkernel64/platform/init.c
1357
if (tmp != NULL) {
sys/platform/vkernel64/platform/init.c
1361
if ((kether_aton(tmp, info->enaddr)) == NULL) {
sys/platform/vkernel64/platform/init.c
169
char *tmp;
sys/platform/vkernel64/platform/init.c
289
if ((tmp = realloc(kern_envp, kenv_size2)) == NULL)
sys/platform/vkernel64/platform/init.c
291
kern_envp = tmp;
sys/sys/signal2.h
100
sigset_t tmp;
sys/sys/signal2.h
108
tmp = *mask; /* check maskable signals */
sys/sys/signal2.h
109
SIG_CANTMASK(tmp);
sys/sys/signal2.h
110
if (SIGISEMPTY(tmp)) /* no unmaskable signals */
sys/sys/tree.h
1002
struct type *tmp; \
sys/sys/tree.h
1005
tmp = RB_ROOT(head); \
sys/sys/tree.h
1006
while (tmp) { \
sys/sys/tree.h
1007
r = xcmp(value, tmp); \
sys/sys/tree.h
1009
return(tmp); \
sys/sys/tree.h
101
#define SPLAY_LINKLEFT(head, tmp, field) do { \
sys/sys/tree.h
1011
tmp = RB_RIGHT(tmp, field); \
sys/sys/tree.h
1013
tmp = RB_LEFT(tmp, field); \
sys/sys/tree.h
102
SPLAY_LEFT(tmp, field) = (head)->sph_root; \
sys/sys/tree.h
103
tmp = (head)->sph_root; \
sys/sys/tree.h
107
#define SPLAY_LINKRIGHT(head, tmp, field) do { \
sys/sys/tree.h
108
SPLAY_RIGHT(tmp, field) = (head)->sph_root; \
sys/sys/tree.h
109
tmp = (head)->sph_root; \
sys/sys/tree.h
364
#define RB_ROTATE_LEFT(head, elm, tmp, field) do { \
sys/sys/tree.h
365
(tmp) = RB_RIGHT(elm, field); \
sys/sys/tree.h
366
if ((RB_RIGHT(elm, field) = RB_LEFT(tmp, field)) != NULL) { \
sys/sys/tree.h
367
RB_PARENT(RB_LEFT(tmp, field), field) = (elm); \
sys/sys/tree.h
370
if ((RB_PARENT(tmp, field) = RB_PARENT(elm, field)) != NULL) { \
sys/sys/tree.h
372
RB_LEFT(RB_PARENT(elm, field), field) = (tmp); \
sys/sys/tree.h
374
RB_RIGHT(RB_PARENT(elm, field), field) = (tmp); \
sys/sys/tree.h
376
(head)->rbh_root = (tmp); \
sys/sys/tree.h
377
RB_LEFT(tmp, field) = (elm); \
sys/sys/tree.h
378
RB_PARENT(elm, field) = (tmp); \
sys/sys/tree.h
379
RB_AUGMENT(tmp); \
sys/sys/tree.h
380
if ((RB_PARENT(tmp, field))) \
sys/sys/tree.h
381
RB_AUGMENT(RB_PARENT(tmp, field)); \
sys/sys/tree.h
384
#define RB_ROTATE_RIGHT(head, elm, tmp, field) do { \
sys/sys/tree.h
385
(tmp) = RB_LEFT(elm, field); \
sys/sys/tree.h
386
if ((RB_LEFT(elm, field) = RB_RIGHT(tmp, field)) != NULL) { \
sys/sys/tree.h
387
RB_PARENT(RB_RIGHT(tmp, field), field) = (elm); \
sys/sys/tree.h
390
if ((RB_PARENT(tmp, field) = RB_PARENT(elm, field)) != NULL) { \
sys/sys/tree.h
392
RB_LEFT(RB_PARENT(elm, field), field) = (tmp); \
sys/sys/tree.h
394
RB_RIGHT(RB_PARENT(elm, field), field) = (tmp); \
sys/sys/tree.h
396
(head)->rbh_root = (tmp); \
sys/sys/tree.h
397
RB_RIGHT(tmp, field) = (elm); \
sys/sys/tree.h
398
RB_PARENT(elm, field) = (tmp); \
sys/sys/tree.h
399
RB_AUGMENT(tmp); \
sys/sys/tree.h
400
if ((RB_PARENT(tmp, field))) \
sys/sys/tree.h
401
RB_AUGMENT(RB_PARENT(tmp, field)); \
sys/sys/tree.h
464
struct type *parent, *gparent, *tmp; \
sys/sys/tree.h
469
tmp = RB_RIGHT(gparent, field); \
sys/sys/tree.h
470
if (tmp && RB_COLOR(tmp, field) == RB_RED) { \
sys/sys/tree.h
471
RB_COLOR(tmp, field) = RB_BLACK; \
sys/sys/tree.h
477
RB_ROTATE_LEFT(head, parent, tmp, field);\
sys/sys/tree.h
478
tmp = parent; \
sys/sys/tree.h
480
elm = tmp; \
sys/sys/tree.h
483
RB_ROTATE_RIGHT(head, gparent, tmp, field); \
sys/sys/tree.h
485
tmp = RB_LEFT(gparent, field); \
sys/sys/tree.h
486
if (tmp && RB_COLOR(tmp, field) == RB_RED) { \
sys/sys/tree.h
487
RB_COLOR(tmp, field) = RB_BLACK; \
sys/sys/tree.h
493
RB_ROTATE_RIGHT(head, parent, tmp, field);\
sys/sys/tree.h
494
tmp = parent; \
sys/sys/tree.h
496
elm = tmp; \
sys/sys/tree.h
499
RB_ROTATE_LEFT(head, gparent, tmp, field); \
sys/sys/tree.h
509
struct type *tmp; \
sys/sys/tree.h
513
tmp = RB_RIGHT(parent, field); \
sys/sys/tree.h
514
if (RB_COLOR(tmp, field) == RB_RED) { \
sys/sys/tree.h
515
RB_SET_BLACKRED(tmp, parent, field); \
sys/sys/tree.h
516
RB_ROTATE_LEFT(head, parent, tmp, field);\
sys/sys/tree.h
517
tmp = RB_RIGHT(parent, field); \
sys/sys/tree.h
519
if ((RB_LEFT(tmp, field) == NULL || \
sys/sys/tree.h
520
RB_COLOR(RB_LEFT(tmp, field), field) == RB_BLACK) &&\
sys/sys/tree.h
521
(RB_RIGHT(tmp, field) == NULL || \
sys/sys/tree.h
522
RB_COLOR(RB_RIGHT(tmp, field), field) == RB_BLACK)) {\
sys/sys/tree.h
523
RB_COLOR(tmp, field) = RB_RED; \
sys/sys/tree.h
527
if (RB_RIGHT(tmp, field) == NULL || \
sys/sys/tree.h
528
RB_COLOR(RB_RIGHT(tmp, field), field) == RB_BLACK) {\
sys/sys/tree.h
530
if ((oleft = RB_LEFT(tmp, field)) \
sys/sys/tree.h
533
RB_COLOR(tmp, field) = RB_RED; \
sys/sys/tree.h
534
RB_ROTATE_RIGHT(head, tmp, oleft, field);\
sys/sys/tree.h
535
tmp = RB_RIGHT(parent, field); \
sys/sys/tree.h
537
RB_COLOR(tmp, field) = RB_COLOR(parent, field);\
sys/sys/tree.h
539
if (RB_RIGHT(tmp, field)) \
sys/sys/tree.h
540
RB_COLOR(RB_RIGHT(tmp, field), field) = RB_BLACK;\
sys/sys/tree.h
541
RB_ROTATE_LEFT(head, parent, tmp, field);\
sys/sys/tree.h
546
tmp = RB_LEFT(parent, field); \
sys/sys/tree.h
547
if (RB_COLOR(tmp, field) == RB_RED) { \
sys/sys/tree.h
548
RB_SET_BLACKRED(tmp, parent, field); \
sys/sys/tree.h
549
RB_ROTATE_RIGHT(head, parent, tmp, field);\
sys/sys/tree.h
550
tmp = RB_LEFT(parent, field); \
sys/sys/tree.h
552
if ((RB_LEFT(tmp, field) == NULL || \
sys/sys/tree.h
553
RB_COLOR(RB_LEFT(tmp, field), field) == RB_BLACK) &&\
sys/sys/tree.h
554
(RB_RIGHT(tmp, field) == NULL || \
sys/sys/tree.h
555
RB_COLOR(RB_RIGHT(tmp, field), field) == RB_BLACK)) {\
sys/sys/tree.h
556
RB_COLOR(tmp, field) = RB_RED; \
sys/sys/tree.h
560
if (RB_LEFT(tmp, field) == NULL || \
sys/sys/tree.h
561
RB_COLOR(RB_LEFT(tmp, field), field) == RB_BLACK) {\
sys/sys/tree.h
563
if ((oright = RB_RIGHT(tmp, field)) \
sys/sys/tree.h
566
RB_COLOR(tmp, field) = RB_RED; \
sys/sys/tree.h
567
RB_ROTATE_LEFT(head, tmp, oright, field);\
sys/sys/tree.h
568
tmp = RB_LEFT(parent, field); \
sys/sys/tree.h
570
RB_COLOR(tmp, field) = RB_COLOR(parent, field);\
sys/sys/tree.h
572
if (RB_LEFT(tmp, field)) \
sys/sys/tree.h
573
RB_COLOR(RB_LEFT(tmp, field), field) = RB_BLACK;\
sys/sys/tree.h
574
RB_ROTATE_RIGHT(head, parent, tmp, field);\
sys/sys/tree.h
663
struct type *tmp; \
sys/sys/tree.h
666
tmp = RB_ROOT(head); \
sys/sys/tree.h
667
while (tmp) { \
sys/sys/tree.h
668
parent = tmp; \
sys/sys/tree.h
671
tmp = RB_LEFT(tmp, field); \
sys/sys/tree.h
673
tmp = RB_RIGHT(tmp, field); \
sys/sys/tree.h
675
return(tmp); \
sys/sys/tree.h
694
struct type *tmp = RB_ROOT(head); \
sys/sys/tree.h
696
while (tmp) { \
sys/sys/tree.h
697
comp = cmp(elm, tmp); \
sys/sys/tree.h
699
tmp = RB_LEFT(tmp, field); \
sys/sys/tree.h
701
tmp = RB_RIGHT(tmp, field); \
sys/sys/tree.h
703
return (tmp); \
sys/sys/tree.h
750
struct type *tmp; \
sys/sys/tree.h
760
tmp = RB_ROOT(head); \
sys/sys/tree.h
762
while (tmp) { \
sys/sys/tree.h
763
comp = scancmp(tmp, data); \
sys/sys/tree.h
765
tmp = RB_RIGHT(tmp, field); \
sys/sys/tree.h
767
tmp = RB_LEFT(tmp, field); \
sys/sys/tree.h
769
best = tmp; \
sys/sys/tree.h
770
if (RB_LEFT(tmp, field) == NULL) \
sys/sys/tree.h
772
tmp = RB_LEFT(tmp, field); \
sys/sys/tree.h
860
struct type *tmp = RB_ROOT(head); \
sys/sys/tree.h
862
while (tmp) { \
sys/sys/tree.h
863
parent = tmp; \
sys/sys/tree.h
865
tmp = RB_LEFT(tmp, field); \
sys/sys/tree.h
867
tmp = RB_RIGHT(tmp, field); \
sys/sys/tree.h
885
struct type *tmp; \
sys/sys/tree.h
887
tmp = RB_ROOT(head); \
sys/sys/tree.h
888
while (tmp) { \
sys/sys/tree.h
889
if (value > tmp->indexfield) \
sys/sys/tree.h
89
#define SPLAY_ROTATE_RIGHT(head, tmp, field) do { \
sys/sys/tree.h
890
tmp = RB_RIGHT(tmp, field); \
sys/sys/tree.h
891
else if (value < tmp->indexfield) \
sys/sys/tree.h
892
tmp = RB_LEFT(tmp, field); \
sys/sys/tree.h
894
return(tmp); \
sys/sys/tree.h
90
SPLAY_LEFT((head)->sph_root, field) = SPLAY_RIGHT(tmp, field); \
sys/sys/tree.h
902
struct type *tmp; \
sys/sys/tree.h
905
tmp = name##_RB_PREV(rel); \
sys/sys/tree.h
906
if (tmp && value != tmp->indexfield) \
sys/sys/tree.h
907
tmp = NULL; \
sys/sys/tree.h
908
return tmp; \
sys/sys/tree.h
91
SPLAY_RIGHT(tmp, field) = (head)->sph_root; \
sys/sys/tree.h
911
tmp = name##_RB_NEXT(rel); \
sys/sys/tree.h
912
if (tmp && value != tmp->indexfield) \
sys/sys/tree.h
913
tmp = NULL; \
sys/sys/tree.h
914
return tmp; \
sys/sys/tree.h
917
tmp = RB_ROOT(head); \
sys/sys/tree.h
918
while (tmp) { \
sys/sys/tree.h
919
if (value > tmp->indexfield) \
sys/sys/tree.h
92
(head)->sph_root = tmp; \
sys/sys/tree.h
920
tmp = RB_RIGHT(tmp, field); \
sys/sys/tree.h
921
else if (value < tmp->indexfield) \
sys/sys/tree.h
922
tmp = RB_LEFT(tmp, field); \
sys/sys/tree.h
924
return(tmp); \
sys/sys/tree.h
942
struct type *tmp; \
sys/sys/tree.h
944
tmp = RB_ROOT(head); \
sys/sys/tree.h
945
while (tmp) { \
sys/sys/tree.h
946
if (value >= tmp->begfield && value <= tmp->endfield) \
sys/sys/tree.h
947
return(tmp); \
sys/sys/tree.h
948
if (value > tmp->begfield) \
sys/sys/tree.h
949
tmp = RB_RIGHT(tmp, field); \
sys/sys/tree.h
95
#define SPLAY_ROTATE_LEFT(head, tmp, field) do { \
sys/sys/tree.h
951
tmp = RB_LEFT(tmp, field); \
sys/sys/tree.h
96
SPLAY_RIGHT((head)->sph_root, field) = SPLAY_LEFT(tmp, field); \
sys/sys/tree.h
97
SPLAY_LEFT(tmp, field) = (head)->sph_root; \
sys/sys/tree.h
971
struct type *tmp; \
sys/sys/tree.h
973
tmp = RB_ROOT(head); \
sys/sys/tree.h
974
while (tmp) { \
sys/sys/tree.h
975
if (value >= tmp->begfield && \
sys/sys/tree.h
976
value < tmp->begfield + tmp->sizefield) { \
sys/sys/tree.h
977
return(tmp); \
sys/sys/tree.h
979
if (value > tmp->begfield) \
sys/sys/tree.h
98
(head)->sph_root = tmp; \
sys/sys/tree.h
980
tmp = RB_RIGHT(tmp, field); \
sys/sys/tree.h
982
tmp = RB_LEFT(tmp, field); \
sys/vfs/autofs/autofs.c
176
char *path, *tmp;
sys/vfs/autofs/autofs.c
181
tmp = kmalloc(len, M_AUTOFS, M_WAITOK);
sys/vfs/autofs/autofs.c
182
ksnprintf(tmp, len, "%s/%s", anp->an_name, path);
sys/vfs/autofs/autofs.c
184
path = tmp;
sys/vfs/autofs/autofs.c
188
tmp = kmalloc(len, M_AUTOFS, M_WAITOK);
sys/vfs/autofs/autofs.c
189
ksnprintf(tmp, len, "%s/%s", amp->am_on, path);
sys/vfs/autofs/autofs.c
191
path = tmp;
sys/vfs/dirfs/dirfs_subr.c
168
char *tmp;
sys/vfs/dirfs/dirfs_subr.c
191
pathnp = dirfs_findfd(dmp, dnp, &tmp, &pathfree);
sys/vfs/dirfs/dirfs_subr.c
194
dnp->dn_fd = openat(pathnp->dn_fd, tmp,
sys/vfs/dirfs/dirfs_subr.c
202
error = dirfs_node_stat(pathnp->dn_fd, tmp, dnp);
sys/vfs/dirfs/dirfs_subr.c
216
dbg(9, "tmp=%s dnp=%p allocated\n", tmp, dnp);
sys/vfs/dirfs/dirfs_subr.c
562
char *tmp;
sys/vfs/dirfs/dirfs_subr.c
570
tmp = NULL;
sys/vfs/dirfs/dirfs_subr.c
592
tmp = relpath;
sys/vfs/dirfs/dirfs_subr.c
596
pathnp = dirfs_findfd(dmp, dnp, &tmp, &pathfree);
sys/vfs/dirfs/dirfs_subr.c
602
dnp->dn_fd = openat(parentfd, tmp, flags);
sys/vfs/dirfs/dirfs_subr.c
607
"flags=%08x w=%d x=%d\n", dnp, tmp, parentfd, flags, error,
sys/vfs/dirfs/dirfs_subr.c
648
char *tmp;
sys/vfs/dirfs/dirfs_subr.c
659
tmp = dirfs_node_absolute_path(dmp, dnp, &pathfree);
sys/vfs/dirfs/dirfs_subr.c
660
KKASSERT(tmp);
sys/vfs/dirfs/dirfs_subr.c
661
if((lutimes(tmp, NULL)) == -1)
sys/vfs/dirfs/dirfs_subr.c
664
dirfs_node_stat(DIRFS_NOFD, tmp, dnp);
sys/vfs/dirfs/dirfs_subr.c
680
char *tmp;
sys/vfs/dirfs/dirfs_subr.c
697
tmp = dirfs_node_absolute_path(dmp, dnp, &pathfree);
sys/vfs/dirfs/dirfs_subr.c
698
KKASSERT(tmp);
sys/vfs/dirfs/dirfs_subr.c
699
if((lchflags(tmp, flags)) == -1)
sys/vfs/dirfs/dirfs_subr.c
701
dirfs_node_stat(DIRFS_NOFD, tmp, dnp);
sys/vfs/dirfs/dirfs_subr.c
713
char *tmp;
sys/vfs/dirfs/dirfs_subr.c
717
tmp = dirfs_node_absolute_path(dmp, dnp, &pathfree);
sys/vfs/dirfs/dirfs_subr.c
718
KKASSERT(tmp);
sys/vfs/dirfs/dirfs_subr.c
719
if (lchmod(tmp, mode) < 0)
sys/vfs/dirfs/dirfs_subr.c
721
dirfs_node_stat(DIRFS_NOFD, tmp, dnp);
sys/vfs/dirfs/dirfs_subr.c
731
char *tmp;
sys/vfs/dirfs/dirfs_subr.c
735
tmp = dirfs_node_absolute_path(dmp, dnp, &pathfree);
sys/vfs/dirfs/dirfs_subr.c
736
KKASSERT(tmp);
sys/vfs/dirfs/dirfs_subr.c
737
if (lchown(tmp, uid, gid) < 0)
sys/vfs/dirfs/dirfs_subr.c
740
lchmod(tmp, mode);
sys/vfs/dirfs/dirfs_subr.c
741
dirfs_node_stat(DIRFS_NOFD, tmp, dnp);
sys/vfs/dirfs/dirfs_subr.c
754
char *tmp;
sys/vfs/dirfs/dirfs_subr.c
778
tmp = dirfs_node_absolute_path(dmp, dnp, &pathfree);
sys/vfs/dirfs/dirfs_subr.c
786
if (error == 0 && truncate(tmp, nsize) < 0)
sys/vfs/dirfs/dirfs_vnops.c
1032
char *tmp, *pathfree;
sys/vfs/dirfs/dirfs_vnops.c
1046
pathfree = tmp = path = NULL;
sys/vfs/dirfs/dirfs_vnops.c
1054
dnp1 = dirfs_findfd(dmp, pdnp, &tmp, &pathfree);
sys/vfs/dirfs/dirfs_vnops.c
1058
ksnprintf(path, MAXPATHLEN, "%s/%s", tmp, ncp->nc_name);
sys/vfs/dirfs/dirfs_vnops.c
1096
char *tmp;
sys/vfs/dirfs/dirfs_vnops.c
1102
tmp = NULL;
sys/vfs/dirfs/dirfs_vnops.c
1121
tmp = dirfs_node_absolute_path(dmp, dnp, &pathfree);
sys/vfs/dirfs/dirfs_vnops.c
1123
error = rmdir(tmp);
sys/vfs/dirfs/dirfs_vnops.c
1163
char *tmp, *pathfree;
sys/vfs/dirfs/dirfs_vnops.c
1177
pathfree = tmp = path = NULL;
sys/vfs/dirfs/dirfs_vnops.c
1184
tmp = dirfs_node_absolute_path(dmp, pdnp, &pathfree);
sys/vfs/dirfs/dirfs_vnops.c
1187
ksnprintf(path, MAXPATHLEN, "%s/%s", tmp, ncp->nc_name);
sys/vfs/dirfs/dirfs_vnops.c
1307
char *tmp, *pathfree, *buf;
sys/vfs/dirfs/dirfs_vnops.c
1318
tmp = pathfree = NULL;
sys/vfs/dirfs/dirfs_vnops.c
1326
pathnp = dirfs_findfd(dmp, dnp, &tmp, &pathfree);
sys/vfs/dirfs/dirfs_vnops.c
375
char *tmp;
sys/vfs/dirfs/dirfs_vnops.c
389
pathnp = dirfs_findfd(dmp, dnp, &tmp, &pathfree);
sys/vfs/dirfs/dirfs_vnops.c
393
error = dirfs_node_stat(pathnp->dn_fd, tmp, dnp);
sys/vfs/dirfs/dirfs_vnops.c
787
char *tmp;
sys/vfs/dirfs/dirfs_vnops.c
842
tmp = dirfs_node_absolute_path(dmp, dnp, &pathfree);
sys/vfs/dirfs/dirfs_vnops.c
843
dirfs_node_stat(DIRFS_NOFD, tmp, dnp);
sys/vfs/dirfs/dirfs_vnops.c
882
char *tmp;
sys/vfs/dirfs/dirfs_vnops.c
888
tmp = NULL;
sys/vfs/dirfs/dirfs_vnops.c
907
pathnp = dirfs_findfd(dmp, dnp, &tmp, &pathfree);
sys/vfs/dirfs/dirfs_vnops.c
909
error = unlinkat(pathnp->dn_fd, tmp, 0);
sys/vfs/ext2fs/ext2_alloc.c
692
int tmp;
sys/vfs/ext2fs/ext2_alloc.c
710
for (tmp = indx - 1; tmp >= 0; tmp--)
sys/vfs/ext2fs/ext2_alloc.c
711
if (bap[tmp])
sys/vfs/ext2fs/ext2_alloc.c
712
return (le32toh(bap[tmp]));
sys/vfs/ext2fs/ext2_alloc.c
874
uint64_t start, tmp;
sys/vfs/ext2fs/ext2_alloc.c
892
tmp = e2fs_gd_get_b_bitmap(&fs->e2fs_gd[cg]);
sys/vfs/ext2fs/ext2_alloc.c
894
ext2_block_in_group(fs, tmp, cg))
sys/vfs/ext2fs/ext2_alloc.c
895
setbit(bp->b_data, tmp - start);
sys/vfs/ext2fs/ext2_alloc.c
897
tmp = e2fs_gd_get_i_bitmap(&fs->e2fs_gd[cg]);
sys/vfs/ext2fs/ext2_alloc.c
899
ext2_block_in_group(fs, tmp, cg))
sys/vfs/ext2fs/ext2_alloc.c
900
setbit(bp->b_data, tmp - start);
sys/vfs/ext2fs/ext2_alloc.c
902
tmp = e2fs_gd_get_i_tables(&fs->e2fs_gd[cg]);
sys/vfs/ext2fs/ext2_alloc.c
904
while( tmp < e2fs_gd_get_i_tables(&fs->e2fs_gd[cg]) +
sys/vfs/ext2fs/ext2_alloc.c
907
ext2_block_in_group(fs, tmp, cg))
sys/vfs/ext2fs/ext2_alloc.c
908
setbit(bp->b_data, tmp - start);
sys/vfs/ext2fs/ext2_alloc.c
909
tmp++;
sys/vfs/ext2fs/ext2_htree.c
865
struct buf *tmp = info.h_levels[1].h_bp;
sys/vfs/ext2fs/ext2_htree.c
868
dst_bp = tmp;
sys/vfs/fuse/fuse_vnops.c
501
char *p, tmp[1024];
sys/vfs/fuse/fuse_vnops.c
518
strlcpy(tmp, p, sizeof(tmp));
sys/vfs/fuse/fuse_vnops.c
531
fuse_dbg("lookup \"%s\" ENOENT\n", tmp);
sys/vfs/fuse/fuse_vnops.c
534
fuse_dbg("lookup \"%s\" error=%d\n", tmp, error);
sys/vfs/hammer2/hammer2_vfsops.c
2037
struct statfs tmp;
sys/vfs/hammer2/hammer2_vfsops.c
2045
bzero(&tmp, sizeof(tmp));
sys/vfs/hammer2/hammer2_vfsops.c
2056
tmp.f_files = bref.embed.stats.inode_count;
sys/vfs/hammer2/hammer2_vfsops.c
2057
tmp.f_ffree = 0;
sys/vfs/hammer2/hammer2_vfsops.c
2058
tmp.f_blocks = hmp->voldata.allocator_size /
sys/vfs/hammer2/hammer2_vfsops.c
2060
tmp.f_bfree = hmp->voldata.allocator_free /
sys/vfs/hammer2/hammer2_vfsops.c
2062
tmp.f_bavail = tmp.f_bfree;
sys/vfs/hammer2/hammer2_vfsops.c
2069
tmp.f_blocks -= adj;
sys/vfs/hammer2/hammer2_vfsops.c
2070
tmp.f_bfree -= adj;
sys/vfs/hammer2/hammer2_vfsops.c
2071
tmp.f_bavail -= adj;
sys/vfs/hammer2/hammer2_vfsops.c
2074
mp->mnt_stat.f_blocks = tmp.f_blocks;
sys/vfs/hammer2/hammer2_vfsops.c
2075
mp->mnt_stat.f_bfree = tmp.f_bfree;
sys/vfs/hammer2/hammer2_vfsops.c
2076
mp->mnt_stat.f_bavail = tmp.f_bavail;
sys/vfs/hammer2/hammer2_vfsops.c
2077
mp->mnt_stat.f_files = tmp.f_files;
sys/vfs/hammer2/hammer2_vfsops.c
2078
mp->mnt_stat.f_ffree = tmp.f_ffree;
sys/vfs/hammer2/hammer2_vfsops.c
2092
struct statvfs tmp;
sys/vfs/hammer2/hammer2_vfsops.c
2099
bzero(&tmp, sizeof(tmp));
sys/vfs/hammer2/hammer2_vfsops.c
2110
tmp.f_files = bref.embed.stats.inode_count;
sys/vfs/hammer2/hammer2_vfsops.c
2111
tmp.f_ffree = 0;
sys/vfs/hammer2/hammer2_vfsops.c
2112
tmp.f_blocks = hmp->voldata.allocator_size /
sys/vfs/hammer2/hammer2_vfsops.c
2114
tmp.f_bfree = hmp->voldata.allocator_free /
sys/vfs/hammer2/hammer2_vfsops.c
2116
tmp.f_bavail = tmp.f_bfree;
sys/vfs/hammer2/hammer2_vfsops.c
2123
tmp.f_blocks -= adj;
sys/vfs/hammer2/hammer2_vfsops.c
2124
tmp.f_bfree -= adj;
sys/vfs/hammer2/hammer2_vfsops.c
2125
tmp.f_bavail -= adj;
sys/vfs/hammer2/hammer2_vfsops.c
2128
mp->mnt_vstat.f_blocks = tmp.f_blocks;
sys/vfs/hammer2/hammer2_vfsops.c
2129
mp->mnt_vstat.f_bfree = tmp.f_bfree;
sys/vfs/hammer2/hammer2_vfsops.c
2130
mp->mnt_vstat.f_bavail = tmp.f_bavail;
sys/vfs/hammer2/hammer2_vfsops.c
2131
mp->mnt_vstat.f_files = tmp.f_files;
sys/vfs/hammer2/hammer2_vfsops.c
2132
mp->mnt_vstat.f_ffree = tmp.f_ffree;
sys/vfs/hammer2/hammer2_xops.c
519
hammer2_chain_t *tmp;
sys/vfs/hammer2/hammer2_xops.c
764
tmp = hammer2_chain_lookup(&parent, &key_next,
sys/vfs/hammer2/hammer2_xops.c
769
while (tmp) {
sys/vfs/hammer2/hammer2_xops.c
771
if (hammer2_chain_dirent_test(tmp, xop->head.name2,
sys/vfs/hammer2/hammer2_xops.c
773
e2 = hammer2_chain_delete(parent, tmp,
sys/vfs/hammer2/hammer2_xops.c
778
tmp = hammer2_chain_next(&parent, tmp, &key_next,
sys/vfs/hammer2/hammer2_xops.c
791
tmp = hammer2_chain_lookup(&parent, &key_next,
sys/vfs/hammer2/hammer2_xops.c
794
KKASSERT(tmp == NULL);
sys/vfs/hammer2/zlib/hammer2_zlib_adler32.c
31
unsigned long tmp = a >> 16; \
sys/vfs/hammer2/zlib/hammer2_zlib_adler32.c
33
a += (tmp << 4) - tmp; \
sys/vfs/hammer2/zlib/hammer2_zlib_adler32.c
47
z_off64_t tmp = a >> 32; \
sys/vfs/hammer2/zlib/hammer2_zlib_adler32.c
49
a += (tmp << 8) - (tmp << 5) + tmp; \
sys/vfs/hammer2/zlib/hammer2_zlib_adler32.c
50
tmp = a >> 16; \
sys/vfs/hammer2/zlib/hammer2_zlib_adler32.c
52
a += (tmp << 4) - tmp; \
sys/vfs/hammer2/zlib/hammer2_zlib_adler32.c
53
tmp = a >> 16; \
sys/vfs/hammer2/zlib/hammer2_zlib_adler32.c
55
a += (tmp << 4) - tmp; \
sys/vfs/nfs/nfs_mountrpc.c
105
if ((tmp = substr(p, "rsize=")))
sys/vfs/nfs/nfs_mountrpc.c
106
args->rsize = getdec(&tmp);
sys/vfs/nfs/nfs_mountrpc.c
107
if ((tmp = substr(p, "wsize=")))
sys/vfs/nfs/nfs_mountrpc.c
108
args->wsize = getdec(&tmp);
sys/vfs/nfs/nfs_mountrpc.c
109
if ((tmp = substr(p, "intr")))
sys/vfs/nfs/nfs_mountrpc.c
111
if ((tmp = substr(p, "soft")))
sys/vfs/nfs/nfs_mountrpc.c
113
if ((tmp = substr(p, "noconn")))
sys/vfs/nfs/nfs_mountrpc.c
115
if ((tmp = substr(p, "udp")))
sys/vfs/nfs/nfs_mountrpc.c
96
char *tmp;
sys/vfs/ntfs/ntfs_subr.c
590
cn_t tmp;
sys/vfs/ntfs/ntfs_subr.c
615
tmp = ((u_int64_t) - 1) << (sz << 3);
sys/vfs/ntfs/ntfs_subr.c
617
tmp |= (u_int64_t) run[off++] << (i << 3);
sys/vfs/ntfs/ntfs_subr.c
619
tmp = 0;
sys/vfs/ntfs/ntfs_subr.c
621
tmp |= (u_int64_t) run[off++] << (i << 3);
sys/vfs/ntfs/ntfs_subr.c
623
if (tmp)
sys/vfs/ntfs/ntfs_subr.c
624
prev = cn[cnt] = prev + tmp;
sys/vfs/ntfs/ntfs_subr.c
626
cn[cnt] = tmp;
sys/vfs/ntfs/ntfs_vfsops.c
579
u_int8_t *tmp;
sys/vfs/ntfs/ntfs_vfsops.c
588
tmp = kmalloc(bmsize, M_TEMP, M_WAITOK);
sys/vfs/ntfs/ntfs_vfsops.c
591
0, bmsize, tmp, NULL);
sys/vfs/ntfs/ntfs_vfsops.c
597
if(~tmp[i] & (1 << j)) cfree++;
sys/vfs/ntfs/ntfs_vfsops.c
601
kfree(tmp, M_TEMP);
sys/vfs/ntfs/ntfs_vnops.c
282
size_t tmp;
sys/vfs/ntfs/ntfs_vnops.c
330
bp->b_data, &tmp, NULL);
sys/vfs/tmpfs/tmpfs.h
480
struct tmpfs_mount *tmp;
sys/vfs/tmpfs/tmpfs.h
483
tmp = (struct tmpfs_mount *)(mp)->mnt_data;
sys/vfs/tmpfs/tmpfs.h
484
return tmp;
sys/vfs/tmpfs/tmpfs_subr.c
1008
tmp->tm_pages_used + newpages - oldpages > tmp->tm_pages_max) {
sys/vfs/tmpfs/tmpfs_subr.c
1016
atomic_add_long(&tmp->tm_pages_used, (newpages - oldpages));
sys/vfs/tmpfs/tmpfs_subr.c
107
if (tmp->tm_nodes_inuse >= tmp->tm_nodes_max)
sys/vfs/tmpfs/tmpfs_subr.c
110
nnode = kmalloc_obj(sizeof(struct tmpfs_node), tmp->tm_node_zone,
sys/vfs/tmpfs/tmpfs_subr.c
126
nnode->tn_id = tmpfs_fetch_ino(tmp);
sys/vfs/tmpfs/tmpfs_subr.c
137
kfree_obj(nnode, tmp->tm_node_zone);
sys/vfs/tmpfs/tmpfs_subr.c
1418
tmpfs_fetch_ino(struct tmpfs_mount *tmp)
sys/vfs/tmpfs/tmpfs_subr.c
1422
ret = atomic_fetchadd_64(&tmp->tm_ino, 1);
sys/vfs/tmpfs/tmpfs_subr.c
157
nnode->tn_link = kmalloc(nnode->tn_size + 1, tmp->tm_name_zone,
sys/vfs/tmpfs/tmpfs_subr.c
161
kfree_obj(nnode, tmp->tm_node_zone);
sys/vfs/tmpfs/tmpfs_subr.c
181
TMPFS_LOCK(tmp);
sys/vfs/tmpfs/tmpfs_subr.c
182
LIST_INSERT_HEAD(&tmp->tm_nodes_used, nnode, tn_entries);
sys/vfs/tmpfs/tmpfs_subr.c
183
tmp->tm_nodes_inuse++;
sys/vfs/tmpfs/tmpfs_subr.c
184
TMPFS_UNLOCK(tmp);
sys/vfs/tmpfs/tmpfs_subr.c
213
tmpfs_free_node(struct tmpfs_mount *tmp, struct tmpfs_node *node)
sys/vfs/tmpfs/tmpfs_subr.c
221
TMPFS_LOCK(tmp);
sys/vfs/tmpfs/tmpfs_subr.c
223
tmp->tm_nodes_inuse--;
sys/vfs/tmpfs/tmpfs_subr.c
224
TMPFS_UNLOCK(tmp);
sys/vfs/tmpfs/tmpfs_subr.c
253
if (node == tmp->tm_root)
sys/vfs/tmpfs/tmpfs_subr.c
254
tmp->tm_root = NULL;
sys/vfs/tmpfs/tmpfs_subr.c
262
kfree(node->tn_link, tmp->tm_name_zone);
sys/vfs/tmpfs/tmpfs_subr.c
282
kfree_obj(node, tmp->tm_node_zone);
sys/vfs/tmpfs/tmpfs_subr.c
286
atomic_add_long(&tmp->tm_pages_used, -(long)pages);
sys/vfs/tmpfs/tmpfs_subr.c
301
tmpfs_alloc_dirent(struct tmpfs_mount *tmp, struct tmpfs_node *node,
sys/vfs/tmpfs/tmpfs_subr.c
307
tmp->tm_dirent_zone, M_WAITOK);
sys/vfs/tmpfs/tmpfs_subr.c
308
nde->td_name = kmalloc(len + 1, tmp->tm_name_zone, M_WAITOK | M_NULLOK);
sys/vfs/tmpfs/tmpfs_subr.c
310
kfree_obj(nde, tmp->tm_dirent_zone);
sys/vfs/tmpfs/tmpfs_subr.c
339
tmpfs_free_dirent(struct tmpfs_mount *tmp, struct tmpfs_dirent *de)
sys/vfs/tmpfs/tmpfs_subr.c
348
kfree(de->td_name, tmp->tm_name_zone);
sys/vfs/tmpfs/tmpfs_subr.c
352
kfree_obj(de, tmp->tm_dirent_zone);
sys/vfs/tmpfs/tmpfs_subr.c
528
struct tmpfs_mount *tmp;
sys/vfs/tmpfs/tmpfs_subr.c
532
tmp = VFS_TO_TMPFS(dvp->v_mount);
sys/vfs/tmpfs/tmpfs_subr.c
544
if (dnode != tmp->tm_root && dnode->tn_dir.tn_parent == NULL) {
sys/vfs/tmpfs/tmpfs_subr.c
558
error = tmpfs_alloc_node(tmp, vap->va_type, cred->cr_uid,
sys/vfs/tmpfs/tmpfs_subr.c
568
error = tmpfs_alloc_dirent(tmp, node, ncp->nc_name, ncp->nc_nlen, &de);
sys/vfs/tmpfs/tmpfs_subr.c
571
tmpfs_free_node(tmp, node);
sys/vfs/tmpfs/tmpfs_subr.c
580
tmpfs_free_dirent(tmp, de);
sys/vfs/tmpfs/tmpfs_subr.c
581
tmpfs_free_node(tmp, node);
sys/vfs/tmpfs/tmpfs_subr.c
743
tmpfs_dir_getdotdotdent(struct tmpfs_mount *tmp, struct tmpfs_node *node,
sys/vfs/tmpfs/tmpfs_subr.c
757
d_ino = tmp->tm_root->tn_id;
sys/vfs/tmpfs/tmpfs_subr.c
760
d_ino = tmp->tm_root->tn_id;
sys/vfs/tmpfs/tmpfs_subr.c
835
struct tmpfs_dirent *tmp;
sys/vfs/tmpfs/tmpfs_subr.c
838
tmp = RB_ROOT(&node->tn_dir.tn_cookietree);
sys/vfs/tmpfs/tmpfs_subr.c
839
while (tmp) {
sys/vfs/tmpfs/tmpfs_subr.c
840
if (cdent == tmp)
sys/vfs/tmpfs/tmpfs_subr.c
842
if (cdent > tmp) {
sys/vfs/tmpfs/tmpfs_subr.c
843
last = tmp;
sys/vfs/tmpfs/tmpfs_subr.c
844
tmp = RB_RIGHT(tmp, rb_cookienode);
sys/vfs/tmpfs/tmpfs_subr.c
846
tmp = RB_LEFT(tmp, rb_cookienode);
sys/vfs/tmpfs/tmpfs_subr.c
95
tmpfs_alloc_node(struct tmpfs_mount *tmp, enum vtype type,
sys/vfs/tmpfs/tmpfs_subr.c
983
struct tmpfs_mount *tmp;
sys/vfs/tmpfs/tmpfs_subr.c
994
tmp = VFS_TO_TMPFS(vp->v_mount);
sys/vfs/tmpfs/tmpfs_vfsops.c
189
tmp = kmalloc(sizeof(*tmp), M_TMPFSMNT, M_WAITOK | M_ZERO);
sys/vfs/tmpfs/tmpfs_vfsops.c
191
tmp->tm_mount = mp;
sys/vfs/tmpfs/tmpfs_vfsops.c
192
tmp->tm_nodes_max = nodes;
sys/vfs/tmpfs/tmpfs_vfsops.c
193
tmp->tm_nodes_inuse = 0;
sys/vfs/tmpfs/tmpfs_vfsops.c
194
tmp->tm_maxfilesize = maxfsize;
sys/vfs/tmpfs/tmpfs_vfsops.c
195
LIST_INIT(&tmp->tm_nodes_used);
sys/vfs/tmpfs/tmpfs_vfsops.c
197
tmp->tm_pages_max = pages;
sys/vfs/tmpfs/tmpfs_vfsops.c
198
tmp->tm_pages_used = 0;
sys/vfs/tmpfs/tmpfs_vfsops.c
200
kmalloc_create_obj(&tmp->tm_node_zone, "tmpfs node",
sys/vfs/tmpfs/tmpfs_vfsops.c
202
kmalloc_create_obj(&tmp->tm_dirent_zone, "tmpfs dirent",
sys/vfs/tmpfs/tmpfs_vfsops.c
204
kmalloc_create(&tmp->tm_name_zone, "tmpfs name zone");
sys/vfs/tmpfs/tmpfs_vfsops.c
206
kmalloc_obj_raise_limit(tmp->tm_node_zone,
sys/vfs/tmpfs/tmpfs_vfsops.c
207
sizeof(struct tmpfs_node) * tmp->tm_nodes_max);
sys/vfs/tmpfs/tmpfs_vfsops.c
209
tmp->tm_ino = TMPFS_ROOTINO;
sys/vfs/tmpfs/tmpfs_vfsops.c
212
error = tmpfs_alloc_node(tmp, VDIR, root_uid, root_gid,
sys/vfs/tmpfs/tmpfs_vfsops.c
223
kmalloc_destroy(&tmp->tm_name_zone);
sys/vfs/tmpfs/tmpfs_vfsops.c
224
kmalloc_destroy(&tmp->tm_dirent_zone_obj);
sys/vfs/tmpfs/tmpfs_vfsops.c
225
kmalloc_destroy(&tmp->tm_node_zone_obj);
sys/vfs/tmpfs/tmpfs_vfsops.c
226
kfree(tmp, M_TMPFSMNT);
sys/vfs/tmpfs/tmpfs_vfsops.c
233
tmp->tm_root = root;
sys/vfs/tmpfs/tmpfs_vfsops.c
240
mp->mnt_data = (qaddr_t)tmp;
sys/vfs/tmpfs/tmpfs_vfsops.c
267
struct tmpfs_mount *tmp;
sys/vfs/tmpfs/tmpfs_vfsops.c
272
tmp = VFS_TO_TMPFS(mp);
sys/vfs/tmpfs/tmpfs_vfsops.c
273
TMPFS_LOCK(tmp);
sys/vfs/tmpfs/tmpfs_vfsops.c
284
LIST_FOREACH(node, &tmp->tm_nodes_used, tn_entries) {
sys/vfs/tmpfs/tmpfs_vfsops.c
332
TMPFS_UNLOCK(tmp);
sys/vfs/tmpfs/tmpfs_vfsops.c
344
LIST_FOREACH(node, &tmp->tm_nodes_used, tn_entries) {
sys/vfs/tmpfs/tmpfs_vfsops.c
354
tmpfs_free_dirent(tmp, de);
sys/vfs/tmpfs/tmpfs_vfsops.c
367
KKASSERT(tmp->tm_root);
sys/vfs/tmpfs/tmpfs_vfsops.c
368
TMPFS_NODE_LOCK(tmp->tm_root);
sys/vfs/tmpfs/tmpfs_vfsops.c
369
atomic_add_int(&tmp->tm_root->tn_links, -1);
sys/vfs/tmpfs/tmpfs_vfsops.c
370
TMPFS_NODE_UNLOCK(tmp->tm_root);
sys/vfs/tmpfs/tmpfs_vfsops.c
376
while ((node = LIST_FIRST(&tmp->tm_nodes_used)) != NULL) {
sys/vfs/tmpfs/tmpfs_vfsops.c
383
tmpfs_free_node(tmp, node);
sys/vfs/tmpfs/tmpfs_vfsops.c
387
KKASSERT(tmp->tm_root == NULL);
sys/vfs/tmpfs/tmpfs_vfsops.c
389
kmalloc_destroy(&tmp->tm_name_zone);
sys/vfs/tmpfs/tmpfs_vfsops.c
390
kmalloc_destroy(&tmp->tm_dirent_zone_obj);
sys/vfs/tmpfs/tmpfs_vfsops.c
391
kmalloc_destroy(&tmp->tm_node_zone_obj);
sys/vfs/tmpfs/tmpfs_vfsops.c
393
tmp->tm_node_zone_obj = NULL;
sys/vfs/tmpfs/tmpfs_vfsops.c
394
tmp->tm_dirent_zone_obj = NULL;
sys/vfs/tmpfs/tmpfs_vfsops.c
396
KKASSERT(tmp->tm_pages_used == 0);
sys/vfs/tmpfs/tmpfs_vfsops.c
397
KKASSERT(tmp->tm_nodes_inuse == 0);
sys/vfs/tmpfs/tmpfs_vfsops.c
399
TMPFS_UNLOCK(tmp);
sys/vfs/tmpfs/tmpfs_vfsops.c
402
kfree(tmp, M_TMPFSMNT);
sys/vfs/tmpfs/tmpfs_vfsops.c
414
struct tmpfs_mount *tmp;
sys/vfs/tmpfs/tmpfs_vfsops.c
417
tmp = VFS_TO_TMPFS(mp);
sys/vfs/tmpfs/tmpfs_vfsops.c
418
if (tmp->tm_root == NULL) {
sys/vfs/tmpfs/tmpfs_vfsops.c
424
error = tmpfs_alloc_vp(mp, NULL, tmp->tm_root,
sys/vfs/tmpfs/tmpfs_vfsops.c
440
struct tmpfs_mount *tmp;
sys/vfs/tmpfs/tmpfs_vfsops.c
444
tmp = VFS_TO_TMPFS(mp);
sys/vfs/tmpfs/tmpfs_vfsops.c
453
TMPFS_LOCK(tmp);
sys/vfs/tmpfs/tmpfs_vfsops.c
454
LIST_FOREACH(node, &tmp->tm_nodes_used, tn_entries) {
sys/vfs/tmpfs/tmpfs_vfsops.c
465
TMPFS_UNLOCK(tmp);
sys/vfs/tmpfs/tmpfs_vfsops.c
477
struct tmpfs_mount *tmp;
sys/vfs/tmpfs/tmpfs_vfsops.c
479
tmp = VFS_TO_TMPFS(mp);
sys/vfs/tmpfs/tmpfs_vfsops.c
486
sbp->f_blocks = tmp->tm_pages_max;
sys/vfs/tmpfs/tmpfs_vfsops.c
487
sbp->f_bavail = tmp->tm_pages_max - tmp->tm_pages_used;
sys/vfs/tmpfs/tmpfs_vfsops.c
490
freenodes = tmp->tm_nodes_max - tmp->tm_nodes_inuse;
sys/vfs/tmpfs/tmpfs_vfsops.c
492
sbp->f_files = freenodes + tmp->tm_nodes_inuse;
sys/vfs/tmpfs/tmpfs_vfsops.c
494
sbp->f_owner = tmp->tm_root->tn_uid;
sys/vfs/tmpfs/tmpfs_vfsops.c
523
struct tmpfs_mount *tmp;
sys/vfs/tmpfs/tmpfs_vfsops.c
526
tmp = (struct tmpfs_mount *) mp->mnt_data;
sys/vfs/tmpfs/tmpfs_vfsops.c
527
nc = vfs_export_lookup(mp, &tmp->tm_export, nam);
sys/vfs/tmpfs/tmpfs_vfsops.c
99
struct tmpfs_mount *tmp;
sys/vfs/tmpfs/tmpfs_vnops.c
1094
struct tmpfs_mount *tmp;
sys/vfs/tmpfs/tmpfs_vnops.c
1119
tmp = VFS_TO_TMPFS(vp->v_mount);
sys/vfs/tmpfs/tmpfs_vnops.c
1148
tmpfs_free_dirent(tmp, de);
sys/vfs/tmpfs/tmpfs_vnops.c
1174
struct tmpfs_mount *tmp = VFS_TO_TMPFS(vp->v_mount);
sys/vfs/tmpfs/tmpfs_vnops.c
1202
if (dnode != tmp->tm_root && dnode->tn_dir.tn_parent == NULL) {
sys/vfs/tmpfs/tmpfs_vnops.c
1261
struct tmpfs_mount *tmp;
sys/vfs/tmpfs/tmpfs_vnops.c
1293
tmp = VFS_TO_TMPFS(tdvp->v_mount);
sys/vfs/tmpfs/tmpfs_vnops.c
1310
if (tdnode != tmp->tm_root && tdnode->tn_dir.tn_parent == NULL) {
sys/vfs/tmpfs/tmpfs_vnops.c
1368
newname = kmalloc(tncp->nc_nlen + 1, tmp->tm_name_zone,
sys/vfs/tmpfs/tmpfs_vnops.c
1453
kfree(newname, tmp->tm_name_zone);
sys/vfs/tmpfs/tmpfs_vnops.c
1505
struct tmpfs_mount *tmp;
sys/vfs/tmpfs/tmpfs_vnops.c
1531
tmp = VFS_TO_TMPFS(dvp->v_mount);
sys/vfs/tmpfs/tmpfs_vnops.c
1589
tmpfs_free_dirent(tmp, de);
sys/vfs/tmpfs/tmpfs_vnops.c
1649
struct tmpfs_mount *tmp;
sys/vfs/tmpfs/tmpfs_vnops.c
1660
tmp = VFS_TO_TMPFS(vp->v_mount);
sys/vfs/tmpfs/tmpfs_vnops.c
1675
error = tmpfs_dir_getdotdotdent(tmp, node, uio);
sys/vfs/tmpfs/tmpfs_vnops.c
1840
struct tmpfs_mount *tmp;
sys/vfs/tmpfs/tmpfs_vnops.c
1848
tmp = VFS_TO_TMPFS(vp->v_mount);
sys/vfs/tmpfs/tmpfs_vnops.c
1849
KKASSERT(mp == tmp->tm_mount);
sys/vfs/tmpfs/tmpfs_vnops.c
1865
tmpfs_free_node(tmp, node);
sys/vfs/tmpfs/tmpfs_vnops.c
1881
struct tmpfs_mount *tmp;
sys/vfs/tmpfs/tmpfs_vnops.c
1890
tmp = (struct tmpfs_mount *) mp->mnt_data;
sys/vfs/tmpfs/tmpfs_vnops.c
1895
rc = vfs_export(mp, &tmp->tm_export,
sys/vfs/tmpfs/tmpfs_vnops.c
1940
struct tmpfs_mount *tmp;
sys/vfs/tmpfs/tmpfs_vnops.c
1951
tmp = VFS_TO_TMPFS(vp->v_mount);
sys/vfs/tmpfs/tmpfs_vnops.c
1952
*retval = max(32, flsll(tmp->tm_pages_max * PAGE_SIZE) + 1);
sys/vfs/ufs/ffs_vfsops.c
1301
int32_t *lp, tmp; /* XXX */
sys/vfs/ufs/ffs_vfsops.c
1304
tmp = lp[4]; /* XXX */
sys/vfs/ufs/ffs_vfsops.c
1307
lp[0] = tmp; /* XXX */
sys/vfs/ufs/ufs_lookup.c
674
{ u_char tmp = newdirp->d_namlen;
sys/vfs/ufs/ufs_lookup.c
676
newdirp->d_type = tmp; }
sys/vm/vm_map.c
1206
vm_map_entry_t tmp;
sys/vm/vm_map.c
1218
tmp = RB_ROOT(&map->rb_root);
sys/vm/vm_map.c
1220
while (tmp) {
sys/vm/vm_map.c
1221
if (address >= tmp->ba.start) {
sys/vm/vm_map.c
1222
if (address < tmp->ba.end) {
sys/vm/vm_map.c
1223
*entry = tmp;
sys/vm/vm_map.c
1226
last = tmp;
sys/vm/vm_map.c
1227
tmp = RB_RIGHT(tmp, rb_entry);
sys/vm/vm_map.c
1229
tmp = RB_LEFT(tmp, rb_entry);
sys/vm/vm_map.c
1485
vm_map_entry_t tmp;
sys/vm/vm_map.c
1517
if (vm_map_lookup_entry(map, start, &tmp))
sys/vm/vm_map.c
1518
start = tmp->ba.end;
sys/vm/vm_map.c
1519
entry = tmp; /* may be NULL */
sys/vm/vm_pageout.c
2385
long tmp;
sys/vm/vm_pageout.c
2606
tmp = avail_shortage * 2;
sys/vm/vm_pageout.c
2607
if (tmp > vmstats.v_inactive_target / 10)
sys/vm/vm_pageout.c
2608
tmp = vmstats.v_inactive_target / 10;
sys/vm/vm_pageout.c
2609
inactive_shortage += tmp;
test/debug/bufqueues.c
204
struct buf b, *tmp;
test/debug/bufqueues.c
211
tmp = bqp->bufqueues[q].tqh_first;
test/debug/bufqueues.c
212
if (tmp != NULL)
test/debug/bufqueues.c
214
while (tmp != NULL) {
test/debug/bufqueues.c
216
printf("cpu=%d queue=%8s buf=%p", cpu, q2s(q), tmp);
test/debug/bufqueues.c
217
tmp = b.b_freelist.tqe_next;
test/debug/bufqueues.c
218
if (kkread(kd, (u_long)tmp, &b, sizeof(b), 0) == -1) {
test/debug/buserr.c
26
char tmp[100];
test/debug/buserr.c
41
memcpy(&tmp, mapping, 12);
test/interbench/interbench.c
1107
int tmp;
test/interbench/interbench.c
1109
if ((tmp = open(name, O_RDONLY)) == -1) {
test/interbench/interbench.c
688
int tmp;
test/interbench/interbench.c
690
if ((tmp = open(name, O_RDONLY)) == -1)
test/interbench/interbench.c
706
while ((rd = Read(tmp , buf, bsize)) > 0);
test/interbench/interbench.c
709
if (lseek(tmp, (off_t)0, SEEK_SET) == -1)
tools/tools/ath/athdecode/main.c
407
int tmp, n;
tools/tools/ath/athdecode/main.c
409
for (tmp = 0, p++; *p;) {
tools/tools/ath/athdecode/main.c
412
putc(tmp ? ',' : '<', fd);
tools/tools/ath/athdecode/main.c
415
tmp = 1;
tools/tools/ath/athdecode/main.c
420
if (tmp)
tools/tools/net80211/stumbler/stumbler.c
251
char tmp[3];
tools/tools/net80211/stumbler/stumbler.c
256
snprintf(tmp, sizeof(tmp), "%.2d", chaninfo.chan);
tools/tools/net80211/stumbler/stumbler.c
257
mvaddstr(y, x, tmp);
tools/tools/net80211/w00t/redir/buddy.c
57
char tmp[4];
tools/tools/net80211/w00t/redir/buddy.c
82
memcpy(tmp, &id, 2);
tools/tools/net80211/w00t/redir/buddy.c
84
memcpy(&tmp[2], &id, 2);
tools/tools/net80211/w00t/redir/buddy.c
86
iov[0].iov_base = tmp;
tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c
140
uint8_t tmp;
tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c
145
tmp = state->s[i];
tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c
147
state->s[j] = tmp;
tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c
155
uint8_t tmp;
tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c
159
tmp = state->s[state->i];
tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c
161
state->s[state->j] = tmp;
tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c
190
uint8_t tmp;
tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c
198
tmp = state[i];
tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c
200
state[j] = tmp;
tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c
203
tmp = jj - keystream[jj-1];
tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c
205
while(tmp != state[ii]) {
tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c
287
uint8_t tmp;
tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c
292
tmp = 3 + keybyte;
tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c
294
tmp += 3 + key[i] + i;
tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c
295
key[keybyte] = 256-tmp;
tools/tools/net80211/wesside/wesside/aircrack-ptw-lib.c
296
if(doRound(sortedtable, keybyte+1, fixat, fixvalue, searchborders, key, keylen, state, (256-tmp+sum)%256, strongbytes) == 1) {
tools/tools/net80211/wesside/wesside/wesside.c
2087
char tmp[16];
tools/tools/net80211/wesside/wesside/wesside.c
2096
sprintf(tmp, "%.2X", *key++);
tools/tools/net80211/wesside/wesside/wesside.c
2097
strcat(k, tmp);
tools/tools/net80211/wesside/wesside/wesside.c
222
unsigned char *tmp;
tools/tools/net80211/wesside/wesside/wesside.c
225
tmp = (unsigned char*) malloc(len + sizeof(struct ippseudo));
tools/tools/net80211/wesside/wesside/wesside.c
226
if(!tmp)
tools/tools/net80211/wesside/wesside/wesside.c
229
ph = (struct ippseudo*) tmp;
tools/tools/net80211/wesside/wesside/wesside.c
237
memcpy(tmp + sizeof(struct ippseudo), stuff, len);
tools/tools/net80211/wesside/wesside/wesside.c
239
return in_cksum((unsigned short*)tmp, len+sizeof(struct ippseudo));
tools/tools/netrate/accept_connect/kq_connect_client/kq_connect_client.c
121
tmp = &in[i];
tools/tools/netrate/accept_connect/kq_connect_client/kq_connect_client.c
122
tmp->sin_family = AF_INET;
tools/tools/netrate/accept_connect/kq_connect_client/kq_connect_client.c
123
tmp->sin_port = port;
tools/tools/netrate/accept_connect/kq_connect_client/kq_connect_client.c
226
const struct sockaddr_in *tmp;
tools/tools/netrate/accept_connect/kq_connect_client/kq_connect_client.c
229
tmp = &in[in_idx % in_cnt];
tools/tools/netrate/accept_connect/kq_connect_client/kq_connect_client.c
233
udp_send(tmp);
tools/tools/netrate/accept_connect/kq_connect_client/kq_connect_client.c
248
n = connect(s, (const struct sockaddr *)tmp,
tools/tools/netrate/accept_connect/kq_connect_client/kq_connect_client.c
249
sizeof(*tmp));
tools/tools/netrate/accept_connect/kq_connect_client/kq_connect_client.c
39
struct sockaddr_in *in, *tmp;
tools/tools/netrate/accept_connect/kq_connect_client/kq_connect_client.c
79
tmp = &in[in_cnt];
tools/tools/netrate/accept_connect/kq_connect_client/kq_connect_client.c
80
if (inet_pton(AF_INET, optarg, &tmp->sin_addr) <= 0) {
usr.bin/calendar/utils.h
114
int tmp = *a;
usr.bin/calendar/utils.h
116
*b = tmp;
usr.bin/compress/zopen.c
238
u_char tmp;
usr.bin/compress/zopen.c
255
tmp = (u_char)((maxbits) | block_compress);
usr.bin/compress/zopen.c
256
if (fwrite(&tmp, sizeof(char), sizeof(tmp), fp) != sizeof(tmp))
usr.bin/crunch/crunchgen/crunchgen.c
1343
strlst_t *tmp;
usr.bin/crunch/crunchgen/crunchgen.c
1346
tmp = head;
usr.bin/crunch/crunchgen/crunchgen.c
1348
free(tmp->str);
usr.bin/crunch/crunchgen/crunchgen.c
1349
free(tmp);
usr.bin/dsynth/build.c
3055
char *tmp;
usr.bin/dsynth/build.c
3063
asprintf(&tmp, "%s.new", dst);
usr.bin/dsynth/build.c
3068
fd2 = open(tmp, O_RDWR|O_CREAT|O_TRUNC|O_CLOEXEC, 0644);
usr.bin/dsynth/build.c
3083
remove(tmp);
usr.bin/dsynth/build.c
3085
if (rename(tmp, dst)) {
usr.bin/dsynth/build.c
3087
remove(tmp);
usr.bin/dsynth/build.c
3092
freestrp(&tmp);
usr.bin/dsynth/mount.c
330
char *tmp;
usr.bin/dsynth/mount.c
395
asprintf(&tmp, discretefmt, work->index);
usr.bin/dsynth/mount.c
396
spath = tmp;
usr.bin/dsynth/mount.c
406
tmp = NULL;
usr.bin/dsynth/mount.c
417
if (tmp)
usr.bin/dsynth/mount.c
418
free(tmp);
usr.bin/evtranalyze/evtranalyze.c
1294
const char *tmp = ev->stmt.val->ctor.name;
usr.bin/evtranalyze/evtranalyze.c
1298
ev->stmt.val->ctor.name = tmp;
usr.bin/evtranalyze/evtranalyze.c
1306
ev->stmt.val->ctor.name = tmp;
usr.bin/evtranalyze/evtranalyze.c
1318
ev->stmt.val->ctor.name = tmp;
usr.bin/evtranalyze/evtranalyze.c
1488
char *tmp;
usr.bin/evtranalyze/evtranalyze.c
1496
if ((tmp = strchr(optarg, ':'))) {
usr.bin/evtranalyze/evtranalyze.c
1497
*tmp++ = '\0';
usr.bin/evtranalyze/evtranalyze.c
1498
evtr_set_debug(tmp);
usr.bin/evtranalyze/evtranalyze.c
327
uintmax_t *tmp;
usr.bin/evtranalyze/evtranalyze.c
329
tmp = realloc(v->vals, 2 * v->allocated * sizeof(v->vals[0]));
usr.bin/evtranalyze/evtranalyze.c
330
if (!tmp)
usr.bin/evtranalyze/evtranalyze.c
332
v->vals = tmp;
usr.bin/evtranalyze/evtranalyze.c
637
struct evtr_thread *tmp;
usr.bin/evtranalyze/evtranalyze.c
640
tmp = ctx->top_threads[j];
usr.bin/evtranalyze/evtranalyze.c
642
if (tmp == ntd) {
usr.bin/evtranalyze/evtranalyze.c
650
td = tmp;
usr.bin/evtranalyze/plotter.c
107
struct ploticus_plot **tmp;
usr.bin/evtranalyze/plotter.c
112
if (!(tmp = realloc(ctx->plots, sizeof(struct ploticus_plot *) *
usr.bin/evtranalyze/plotter.c
115
ctx->plots = tmp;
usr.bin/find/option.c
169
OPTION tmp;
usr.bin/find/option.c
171
tmp.name = name;
usr.bin/find/option.c
172
return ((OPTION *)bsearch(&tmp, options,
usr.bin/finger/finger.c
235
PERSON *tmp;
usr.bin/finger/finger.c
242
memmove(&tmp, data.data, sizeof tmp);
usr.bin/finger/finger.c
243
enter_lastlog(tmp);
usr.bin/finger/finger.c
365
PERSON *tmp;
usr.bin/finger/finger.c
372
memmove(&tmp, data.data, sizeof tmp);
usr.bin/finger/finger.c
373
enter_lastlog(tmp);
usr.bin/finger/lprint.c
66
PERSON *tmp;
usr.bin/finger/lprint.c
75
memmove(&tmp, data.data, sizeof tmp);
usr.bin/finger/lprint.c
76
pn = tmp;
usr.bin/finger/sprint.c
56
PERSON *tmp;
usr.bin/finger/sprint.c
91
memmove(&tmp, data.data, sizeof tmp);
usr.bin/finger/sprint.c
92
pn = tmp;
usr.bin/fmt/fmt.c
256
wchar_t *tmp;
usr.bin/fmt/fmt.c
275
tmp = XMALLOC((len + 1) * sizeof(wchar_t));
usr.bin/fmt/fmt.c
276
mbsrtowcs(tmp, &src, len + 1, NULL);
usr.bin/fmt/fmt.c
277
sentence_enders = tmp;
usr.bin/gencat/gencat.c
334
char *tmp;
usr.bin/gencat/gencat.c
335
tmp = cptr + 1;
usr.bin/gencat/gencat.c
336
if (*tmp && (!isspace((unsigned char) *tmp) || *wskip(tmp))) {
usr.bin/join/join.c
266
LINE *lp, *lastlp, tmp;
usr.bin/join/join.c
306
tmp = F->set[F->setcnt];
usr.bin/join/join.c
308
F->set[F->pushback] = tmp;
usr.bin/locale/locale.c
215
int tmp;
usr.bin/locale/locale.c
261
tmp = 0;
usr.bin/locale/locale.c
263
while (tmp < argc)
usr.bin/locale/locale.c
264
if (strcasecmp(argv[tmp++], "list") == 0) {
usr.bin/lock/lock.c
100
if (*ep != '\0' || tmp > INT_MAX || tmp < INT_MIN)
usr.bin/lock/lock.c
102
sectimeout = (int)tmp;
usr.bin/lock/lock.c
84
long tmp;
usr.bin/lock/lock.c
99
tmp = strtol(optarg, &ep, 10);
usr.bin/m4/eval.c
901
const char *tmp;
usr.bin/m4/eval.c
936
tmp = from;
usr.bin/m4/eval.c
962
while (*tmp) {
usr.bin/m4/eval.c
963
mapvec[(unsigned char)(*tmp)] = (unsigned char)(*tmp);
usr.bin/m4/eval.c
964
tmp++;
usr.bin/mail/v7.local.c
53
char *tmp = getenv("MAIL");
usr.bin/mail/v7.local.c
55
if (tmp == NULL)
usr.bin/mail/v7.local.c
58
strlcpy(buf, tmp, buflen);
usr.bin/newkey/generic.c
100
BIGNUM *pk, *sk, *tmp, *base, *root, *modulus;
usr.bin/newkey/generic.c
104
tmp = itobn(0);
usr.bin/newkey/generic.c
119
BN_zero(tmp);
usr.bin/newkey/generic.c
120
BN_add_word(tmp, r);
usr.bin/newkey/generic.c
122
BN_add(sk, tmp, sk);
usr.bin/newkey/generic.c
124
BN_zero(tmp);
usr.bin/newkey/generic.c
125
BN_div(tmp, sk, sk, modulus, ctx);
usr.bin/newkey/generic.c
145
BN_free(tmp);
usr.bin/paste/paste.c
125
LIST *head, *tmp;
usr.bin/paste/paste.c
128
for (cnt = 0, head = tmp = NULL; (p = *argv); ++argv, ++cnt) {
usr.bin/paste/paste.c
139
head = tmp = lp;
usr.bin/paste/paste.c
141
tmp->next = lp;
usr.bin/paste/paste.c
142
tmp = lp;
usr.bin/patch/pch.c
1565
size_t min_components, min_baselen, min_len, tmp;
usr.bin/patch/pch.c
1582
if ((tmp = num_components(path)) > min_components)
usr.bin/patch/pch.c
1584
if (tmp < min_components) {
usr.bin/patch/pch.c
1585
min_components = tmp;
usr.bin/patch/pch.c
1588
if ((tmp = strlen(basename(path))) > min_baselen)
usr.bin/patch/pch.c
1590
if (tmp < min_baselen) {
usr.bin/patch/pch.c
1591
min_baselen = tmp;
usr.bin/patch/pch.c
1594
if ((tmp = strlen(path)) > min_len)
usr.bin/patch/pch.c
1596
min_len = tmp;
usr.bin/patch/pch.c
409
struct file_name tmp = names[OLD_FILE];
usr.bin/patch/pch.c
411
names[NEW_FILE] = tmp;
usr.bin/rpcgen/rpc_main.c
426
char *guard, *tmp, *stopat;
usr.bin/rpcgen/rpc_main.c
437
for (tmp = guard; *tmp != '\000'; ++tmp) {
usr.bin/rpcgen/rpc_main.c
438
if (islower(*tmp))
usr.bin/rpcgen/rpc_main.c
439
*tmp = toupper(*tmp);
usr.bin/rpcgen/rpc_main.c
440
else if (isupper(*tmp) || *tmp == '_')
usr.bin/rpcgen/rpc_main.c
442
else if (tmp == guard)
usr.bin/rpcgen/rpc_main.c
443
*tmp = '_';
usr.bin/rpcgen/rpc_main.c
444
else if (isdigit(*tmp))
usr.bin/rpcgen/rpc_main.c
446
else if (tmp == stopat) {
usr.bin/rpcgen/rpc_main.c
447
*tmp = '\0';
usr.bin/rpcgen/rpc_main.c
450
*tmp = '_';
usr.bin/rpcgen/rpc_main.c
458
for (tmp = guard; *tmp == '_'; ++tmp)
usr.bin/rpcgen/rpc_main.c
460
strcpy(guard, tmp);
usr.bin/rpcgen/rpc_parse.c
374
char tmp[100];
usr.bin/rpcgen/rpc_parse.c
378
sprintf(tmp,
usr.bin/rpcgen/rpc_parse.c
381
error(tmp);
usr.bin/rpcgen/rpc_parse.c
387
sprintf(tmp,
usr.bin/rpcgen/rpc_parse.c
390
error(tmp);
usr.bin/rpcgen/rpc_scan.c
313
char *tmp;
usr.bin/rpcgen/rpc_scan.c
324
tmp = xmalloc(size + 1);
usr.bin/rpcgen/rpc_scan.c
325
strncpy(tmp, *str, size);
usr.bin/rpcgen/rpc_scan.c
326
tmp[size] = 0;
usr.bin/rpcgen/rpc_scan.c
327
*val = tmp;
usr.bin/rpcgen/rpc_scan.c
335
char *tmp;
usr.bin/rpcgen/rpc_scan.c
348
tmp = xmalloc(size + 1);
usr.bin/rpcgen/rpc_scan.c
349
strncpy(tmp, *str, size);
usr.bin/rpcgen/rpc_scan.c
350
tmp[size] = 0;
usr.bin/rpcgen/rpc_scan.c
351
*val = tmp;
usr.bin/rpcgen/rpc_scan.c
359
char *tmp;
usr.bin/rpcgen/rpc_scan.c
374
tmp = xmalloc(size + 1);
usr.bin/rpcgen/rpc_scan.c
375
strncpy(tmp, *str, size);
usr.bin/rpcgen/rpc_scan.c
376
tmp[size] = 0;
usr.bin/rpcgen/rpc_scan.c
377
*val = tmp;
usr.bin/rpcgen/rpc_scan.c
413
char *str, *tmp;
usr.bin/rpcgen/rpc_scan.c
429
tmp = xmalloc(len + 1);
usr.bin/rpcgen/rpc_scan.c
430
strncpy(tmp, str, len);
usr.bin/rpcgen/rpc_scan.c
431
tmp[len] = 0;
usr.bin/rpcgen/rpc_scan.c
432
tokp->str = tmp;
usr.bin/sed/process.c
498
SPACE tmp;
usr.bin/sed/process.c
539
tmp = PS;
usr.bin/sed/process.c
541
psanl = tmp.append_newline;
usr.bin/sed/process.c
542
YS = tmp;
usr.bin/sort/bwstring.c
57
unsigned char *tmp;
usr.bin/sort/bwstring.c
67
tmp = (unsigned char *) nl_langinfo(item[i]);
usr.bin/sort/bwstring.c
69
printf("month[%d]=%s\n", i, tmp);
usr.bin/sort/bwstring.c
70
if (*tmp == '\0')
usr.bin/sort/bwstring.c
72
m = sort_strdup(tmp);
usr.bin/sort/bwstring.c
73
len = strlen(tmp);
usr.bin/sort/bwstring.c
87
tmp = (unsigned char *) nl_langinfo(item[i]);
usr.bin/sort/bwstring.c
89
printf("month[%d]=%s\n", i, tmp);
usr.bin/sort/bwstring.c
90
if (*tmp == '\0')
usr.bin/sort/bwstring.c
92
len = strlen(tmp);
usr.bin/sort/bwstring.c
94
if (mbstowcs(m, (char*)tmp, len) ==
usr.bin/sort/coll.c
513
const struct bwstring *tmp;
usr.bin/sort/coll.c
515
tmp = s1;
usr.bin/sort/coll.c
517
s2 = tmp;
usr.bin/sort/file.c
1063
struct bwstring *tmp;
usr.bin/sort/file.c
1065
tmp = file_reader_readline(fh->fr);
usr.bin/sort/file.c
1066
if (tmp == NULL) {
usr.bin/sort/file.c
1077
sort_list_item_set(fh->si, tmp);
usr.bin/sort/file.c
1170
if (fl->tmp) {
usr.bin/sort/file.c
1179
fl->tmp = false; /* already taken care of */
usr.bin/sort/file.c
1185
fl->tmp = new_fl.tmp;
usr.bin/sort/file.c
1352
struct sort_list *tmp;
usr.bin/sort/file.c
1354
tmp = sl[i1];
usr.bin/sort/file.c
1356
sl[i2] = tmp;
usr.bin/sort/file.c
213
file_list_init(struct file_list *fl, bool tmp)
usr.bin/sort/file.c
220
fl->tmp = tmp;
usr.bin/sort/file.c
271
if (fl->tmp)
usr.bin/sort/file.c
282
fl->tmp = false;
usr.bin/sort/file.c
949
struct file_header *tmp;
usr.bin/sort/file.c
951
tmp = fh[i1];
usr.bin/sort/file.c
953
fh[i2] = tmp;
usr.bin/sort/file.h
108
void file_list_init(struct file_list *fl, bool tmp);
usr.bin/sort/file.h
70
bool tmp;
usr.bin/sort/sort.c
1324
char* tmp = sort_malloc(strlen(outfile) +
usr.bin/sort/sort.c
1327
strcpy(tmp, outfile);
usr.bin/sort/sort.c
1328
strcpy(tmp + strlen(tmp), ".tmp");
usr.bin/sort/sort.c
1330
outfile = tmp;
usr.bin/stat/stat.c
1019
snprintf(tmp, sizeof(tmp), "%d", size);
usr.bin/stat/stat.c
1020
strcat(lfmt, tmp);
usr.bin/stat/stat.c
1037
snprintf(tmp, sizeof(tmp), "%dld", prec > 9 ? 9 : prec);
usr.bin/stat/stat.c
1038
strcat(lfmt, tmp);
usr.bin/stat/stat.c
1061
snprintf(tmp, sizeof(tmp), "%d", size);
usr.bin/stat/stat.c
1062
strcat(lfmt, tmp);
usr.bin/stat/stat.c
1065
snprintf(tmp, sizeof(tmp), ".%d", prec);
usr.bin/stat/stat.c
1066
strcat(lfmt, tmp);
usr.bin/stat/stat.c
624
char *stmp, lfmt[24], tmp[20];
usr.bin/stat/stat.c
994
snprintf(tmp, sizeof(tmp), "%d", size);
usr.bin/stat/stat.c
995
strcat(lfmt, tmp);
usr.bin/strfile/strfile.c
428
off_t tmp;
usr.bin/strfile/strfile.c
440
tmp = sp[0];
usr.bin/strfile/strfile.c
442
sp[i] = tmp;
usr.bin/systat/convtbl.c
74
uintmax_t tmp;
usr.bin/systat/convtbl.c
88
for (tmp = size, idx = disp_bits ? SC_BIT : SC_BYTE;
usr.bin/systat/convtbl.c
89
tmp >= 1000 / (disp_bits ? BIT : BYTE) &&
usr.bin/systat/convtbl.c
91
tmp /= 1000, idx++);
usr.bin/systat/devs.c
152
char tmp[64];
usr.bin/systat/devs.c
154
snprintf(tmp, sizeof(tmp), "md*");
usr.bin/systat/devs.c
155
dscmd("ignore", tmp, maxshowdevs, s1);
usr.bin/systat/devs.c
156
snprintf(tmp, sizeof(tmp), "pass*");
usr.bin/systat/devs.c
157
dscmd("ignore", tmp, maxshowdevs, s1);
usr.bin/systat/devs.c
158
snprintf(tmp, sizeof(tmp), "sg*");
usr.bin/systat/devs.c
159
dscmd("ignore", tmp, maxshowdevs, s1);
usr.bin/telnet/sys_bsd.c
920
int tmp;
usr.bin/telnet/sys_bsd.c
929
tmp = howmany(maxfd+1, NFDBITS) * sizeof(fd_mask);
usr.bin/telnet/sys_bsd.c
930
if (tmp > fdsn) {
usr.bin/telnet/sys_bsd.c
938
fdsn = tmp;
usr.bin/telnet/telnet.c
2243
unsigned char tmp[16];
usr.bin/telnet/telnet.c
2250
cp = tmp;
usr.bin/telnet/telnet.c
2258
if (NETROOM() >= cp - tmp) {
usr.bin/telnet/telnet.c
2259
ring_supply_data(&netoring, tmp, cp-tmp);
usr.bin/telnet/telnet.c
2260
printsub('>', tmp+2, cp - tmp - 2);
usr.bin/telnet/telnet.c
2344
unsigned char tmp[16];
usr.bin/telnet/telnet.c
2357
cp = tmp;
usr.bin/telnet/telnet.c
2366
if (NETROOM() >= cp - tmp) {
usr.bin/telnet/telnet.c
2367
ring_supply_data(&netoring, tmp, cp-tmp);
usr.bin/telnet/telnet.c
2368
printsub('>', tmp+2, cp - tmp - 2);
usr.bin/truss/setup.c
131
struct procfs_status tmp;
usr.bin/truss/setup.c
151
if (ioctl(fd, PIOCSTATUS, &tmp) == -1) {
usr.bin/truss/setup.c
154
evflags = tmp.events;
usr.bin/truss/syscalls.c
176
char *tmp = NULL;
usr.bin/truss/syscalls.c
179
asprintf(&tmp, "0x%x", (uint32_t)args[sc->offset]);
usr.bin/truss/syscalls.c
182
asprintf(&tmp, "0%o", (uint32_t)args[sc->offset]);
usr.bin/truss/syscalls.c
185
asprintf(&tmp, "%d", (int32_t)args[sc->offset]);
usr.bin/truss/syscalls.c
188
asprintf(&tmp, "0x%lx", args[sc->offset]);
usr.bin/truss/syscalls.c
191
asprintf(&tmp, "%ld", args[sc->offset]);
usr.bin/truss/syscalls.c
197
asprintf(&tmp, "\"%s\"", tmp2);
usr.bin/truss/syscalls.c
202
asprintf(&tmp, "0x%lx", args[sc->offset]);
usr.bin/truss/syscalls.c
208
tmp = strdup(temp);
usr.bin/truss/syscalls.c
210
asprintf(&tmp, "0x%lx", args[sc->offset]);
usr.bin/truss/syscalls.c
220
asprintf(&tmp, "sig%s", sys_signame[sig]);
usr.bin/truss/syscalls.c
221
for (i = 0; tmp[i] != '\0'; ++i)
usr.bin/truss/syscalls.c
222
tmp[i] = toupper(tmp[i]);
usr.bin/truss/syscalls.c
224
asprintf(&tmp, "%ld", sig);
usr.bin/truss/syscalls.c
261
asprintf(&tmp, "{ AF_INET %s:%d }", addr, htons(lsin->sin_port));
usr.bin/truss/syscalls.c
266
asprintf(&tmp, "{ AF_INET6 [%s]:%d }", addr, htons(lsin6->sin6_port));
usr.bin/truss/syscalls.c
270
asprintf(&tmp, "{ AF_UNIX \"%s\" }", sun->sun_path);
usr.bin/truss/syscalls.c
274
asprintf(&tmp, "{ sa_len = %d, sa_family = %d, sa_data = {%n%*s } }",
usr.bin/truss/syscalls.c
277
if (tmp != NULL) {
usr.bin/truss/syscalls.c
278
p = tmp + i;
usr.bin/truss/syscalls.c
286
return tmp;
usr.bin/unifdef/unifdef.h
44
mktempmode(char *tmp, int mode)
usr.bin/unifdef/unifdef.h
46
int fd = mkstemp(tmp);
usr.bin/usbhidaction/usbhidaction.c
283
char usbuf[SIZE], coll[SIZE], *tmp;
usr.bin/usbhidaction/usbhidaction.c
319
tmp = strchr(name, '#');
usr.bin/usbhidaction/usbhidaction.c
320
if (tmp != NULL) {
usr.bin/usbhidaction/usbhidaction.c
321
*tmp = 0;
usr.bin/usbhidaction/usbhidaction.c
322
inst = atoi(tmp + 1);
usr.bin/window/parser2.c
100
tmp = t.v_type == V_STR ? t.v_str : 0;
usr.bin/window/parser2.c
103
if (tmp)
usr.bin/window/parser2.c
104
str_free(tmp);
usr.bin/window/parser2.c
110
if (tmp) {
usr.bin/window/parser2.c
119
!str_match(tmp, ap->arg_name,
usr.bin/window/parser2.c
125
name, tmp);
usr.bin/window/parser2.c
131
str_free(tmp);
usr.bin/window/parser2.c
97
char *tmp;
usr.bin/window/parser4.c
208
int tmp = strcmp(l.v_str, r.v_str);
usr.bin/window/parser4.c
212
l.v_num = tmp;
usr.bin/window/parser5.c
100
else if (tmp)
usr.bin/window/parser5.c
96
int tmp = cx.x_type == X_BUF && cx.x_arg != 0 &&
usr.bin/window/parser5.c
99
v->v_num = tmp;
usr.bin/window/wwscroll.c
125
union ww_char *tmp;
usr.bin/window/wwscroll.c
131
tmp = *cpp;
usr.bin/window/wwscroll.c
134
*cpp = tmp;
usr.bin/window/wwscroll.c
138
tmp = *cqq;
usr.bin/window/wwscroll.c
141
*cqq = tmp;
usr.bin/window/wwscroll.c
144
tmp++->c_w = ' ';
usr.bin/window/wwscroll.c
157
union ww_char *tmp;
usr.bin/window/wwscroll.c
162
tmp = *cpp;
usr.bin/window/wwscroll.c
165
*cpp = tmp;
usr.bin/window/wwscroll.c
186
union ww_char *tmp;
usr.bin/window/wwscroll.c
191
tmp = *cqq;
usr.bin/window/wwscroll.c
194
*cqq = tmp;
usr.bin/window/wwwrite.c
109
int tmp = 8 - ((i - w->ww_w.l) & 7);
usr.bin/window/wwwrite.c
111
i += tmp;
usr.bin/window/wwwrite.c
112
bp += tmp;
usr.bin/xargs/xargs.c
482
char **tmp, **tmp2, **avj;
usr.bin/xargs/xargs.c
499
tmp = malloc((argc + 1) * sizeof(char *));
usr.bin/xargs/xargs.c
500
if (tmp == NULL) {
usr.bin/xargs/xargs.c
504
tmp2 = tmp;
usr.bin/xargs/xargs.c
510
if ((*tmp++ = strdup(*avj++)) == NULL) {
usr.bin/xargs/xargs.c
524
*tmp = *avj++;
usr.bin/xargs/xargs.c
525
if (repls && strstr(*tmp, replstr) != NULL) {
usr.bin/xargs/xargs.c
526
if (strnsubst(tmp++, replstr, inpline, (size_t)Sflag)) {
usr.bin/xargs/xargs.c
533
if ((*tmp = strdup(*tmp)) == NULL) {
usr.bin/xargs/xargs.c
537
tmp++;
usr.bin/xargs/xargs.c
544
*tmp = NULL;
usr.bin/xargs/xargs.c
550
for (; tmp2 != tmp; tmp--)
usr.bin/xargs/xargs.c
551
free(*tmp);
usr.bin/xstr/xstr.c
232
static char tmp[] = "b\bt\tr\rn\nf\f\\\\\"\"";
usr.bin/xstr/xstr.c
257
for (tp = tmp; (ch = *tp++); tp++)
usr.sbin/acpi/acpicall/acpicall.c
205
char tmp[3] = { 0 };
usr.sbin/acpi/acpicall/acpicall.c
217
tmp[0] = src[i * 2];
usr.sbin/acpi/acpicall/acpicall.c
218
tmp[1] = src[i * 2 + 1];
usr.sbin/acpi/acpicall/acpicall.c
219
dst->Buffer.Pointer[i] = strtol(tmp, NULL, 16);
usr.sbin/authpf/authpf.c
519
char tmp[MAXPATHLEN];
usr.sbin/authpf/authpf.c
521
n = snprintf(tmp, sizeof(tmp), "%s/%s", userdir, user);
usr.sbin/authpf/authpf.c
522
if (n < 0 || (u_int)n >= sizeof(tmp)) {
usr.sbin/authpf/authpf.c
527
if ((f = fopen(tmp, "r")) == NULL) {
usr.sbin/authpf/authpf.c
541
tmp, strerror(errno));
usr.sbin/authpf/authpf.c
550
luser, tmp);
usr.sbin/authpf/authpf.c
553
strlcpy(tmp, "\n\n-**- Sorry, you have been banned! -**-\n\n",
usr.sbin/authpf/authpf.c
554
sizeof(tmp));
usr.sbin/authpf/authpf.c
555
while (fputs(tmp, stdout) != EOF && !feof(f)) {
usr.sbin/authpf/authpf.c
556
if (fgets(tmp, sizeof(tmp), f) == NULL) {
usr.sbin/autofs/automountd.c
167
char *key, *options, *fstype, *nobrowse, *retrycnt, *tmp;
usr.sbin/autofs/automountd.c
273
tmp = concat(adr->adr_path, '/', key);
usr.sbin/autofs/automountd.c
274
node = node_find(root, tmp);
usr.sbin/autofs/common.c
117
char *component, *copy, *tofree, *partial, *tmp;
usr.sbin/autofs/common.c
132
tmp = concat(partial, '/', component);
usr.sbin/autofs/common.c
134
partial = tmp;
usr.sbin/autofs/common.c
246
struct node *child, *tmp;
usr.sbin/autofs/common.c
250
TAILQ_FOREACH_SAFE(child, &n->n_children, n_next, tmp)
usr.sbin/autofs/common.c
275
struct node *n, *n2, *tmp, *tmp2, *tmproot;
usr.sbin/autofs/common.c
278
TAILQ_FOREACH_SAFE(n, &root->n_children, n_next, tmp) {
usr.sbin/autofs/common.c
490
struct node *child, *tmp;
usr.sbin/autofs/common.c
492
TAILQ_FOREACH_SAFE(child, &n->n_children, n_next, tmp) {
usr.sbin/autofs/common.c
608
char *path, *options, *tmp;
usr.sbin/autofs/common.c
611
tmp = node_options(n);
usr.sbin/autofs/common.c
612
options = concat(cmdline_options, ',', tmp);
usr.sbin/autofs/common.c
613
free(tmp);
usr.sbin/autofs/common.c
665
char *tmp;
usr.sbin/autofs/common.c
671
tmp = node_path(node);
usr.sbin/autofs/common.c
672
tmplen = strlen(tmp);
usr.sbin/autofs/common.c
673
if (strncmp(tmp, path, tmplen) != 0) {
usr.sbin/autofs/common.c
674
free(tmp);
usr.sbin/autofs/common.c
682
free(tmp);
usr.sbin/autofs/common.c
685
free(tmp);
usr.sbin/bthcid/parser.y
357
char tmp[PATH_MAX], buf[BTHCID_BUFFER_SIZE];
usr.sbin/bthcid/parser.y
360
snprintf(tmp, sizeof(tmp), "%s.tmp", BTHCID_KEYSFILE);
usr.sbin/bthcid/parser.y
361
if ((f = open(tmp, O_RDWR|O_CREAT|O_TRUNC|O_EXCL, 0600)) < 0) {
usr.sbin/bthcid/parser.y
363
tmp, strerror(errno), errno);
usr.sbin/bthcid/parser.y
388
if (rename(tmp, BTHCID_KEYSFILE) < 0) {
usr.sbin/bthcid/parser.y
390
tmp, BTHCID_KEYSFILE, strerror(errno), errno);
usr.sbin/bthcid/parser.y
391
unlink(tmp);
usr.sbin/config/main.c
141
char tmp[strlen(p) + 8];
usr.sbin/config/main.c
145
snprintf(tmp, sizeof(tmp), "rm -rf %s", p);
usr.sbin/config/main.c
146
if (system(tmp)) {
usr.sbin/config/main.c
148
err(2, "%s", tmp);
usr.sbin/cron/crontab/crontab.c
491
FILE *tmp;
usr.sbin/cron/crontab/crontab.c
504
if (!(tmp = fopen(tn, "w+"))) {
usr.sbin/cron/crontab/crontab.c
513
fprintf(tmp, "# DO NOT EDIT THIS FILE - edit the master and reinstall.\n");
usr.sbin/cron/crontab/crontab.c
514
fprintf(tmp, "# (%s installed on %-24.24s)\n", Filename, ctime(&now));
usr.sbin/cron/crontab/crontab.c
521
putc(ch, tmp);
usr.sbin/cron/crontab/crontab.c
522
ftruncate(fileno(tmp), ftell(tmp));
usr.sbin/cron/crontab/crontab.c
523
fflush(tmp); rewind(tmp);
usr.sbin/cron/crontab/crontab.c
525
if (ferror(tmp)) {
usr.sbin/cron/crontab/crontab.c
527
fclose(tmp); unlink(tn);
usr.sbin/cron/crontab/crontab.c
541
switch (load_env(envstr, tmp)) {
usr.sbin/cron/crontab/crontab.c
546
e = load_entry(tmp, check_error, pw, envp);
usr.sbin/cron/crontab/crontab.c
557
fclose(tmp); unlink(tn);
usr.sbin/cron/crontab/crontab.c
562
if (fchown(fileno(tmp), ROOT_UID, -1) < OK)
usr.sbin/cron/crontab/crontab.c
568
fclose(tmp); unlink(tn);
usr.sbin/cron/crontab/crontab.c
573
if (fchmod(fileno(tmp), 0600) < OK)
usr.sbin/cron/crontab/crontab.c
579
fclose(tmp); unlink(tn);
usr.sbin/cron/crontab/crontab.c
583
if (fclose(tmp) == EOF) {
usr.sbin/cron/lib/compat.c
217
char *tmp;
usr.sbin/cron/lib/compat.c
222
if (!(tmp = malloc(strlen(name) + strlen(value) + 2))) {
usr.sbin/cron/lib/compat.c
227
sprintf(tmp, "%s=%s", name, value);
usr.sbin/cron/lib/compat.c
228
return putenv(tmp); /* intentionally orphan 'tmp' storage */
usr.sbin/ftp-proxy/ftp-proxy.c
370
struct session *s, *tmp;
usr.sbin/ftp-proxy/ftp-proxy.c
372
LIST_FOREACH_MUTABLE(s, &sessions, entry, tmp) {
usr.sbin/fwcontrol/fwcontrol.c
422
int fd, i, tmp, ch, len=1024;
usr.sbin/fwcontrol/fwcontrol.c
439
tmp = strtol(optarg, NULL, 0);
usr.sbin/fwcontrol/fwcontrol.c
440
send_phy_config(fd, -1, tmp);
usr.sbin/fwcontrol/fwcontrol.c
443
tmp = strtol(optarg, NULL, 0);
usr.sbin/fwcontrol/fwcontrol.c
444
send_link_on(fd, tmp);
usr.sbin/fwcontrol/fwcontrol.c
447
tmp = strtol(optarg, NULL, 0);
usr.sbin/fwcontrol/fwcontrol.c
448
reset_start(fd, tmp);
usr.sbin/fwcontrol/fwcontrol.c
451
tmp = strtol(optarg, NULL, 0);
usr.sbin/fwcontrol/fwcontrol.c
452
set_pri_req(fd, tmp);
usr.sbin/fwcontrol/fwcontrol.c
455
if(ioctl(fd, FW_IBUSRST, &tmp) < 0)
usr.sbin/fwcontrol/fwcontrol.c
462
tmp = strtol(optarg, NULL, 0);
usr.sbin/fwcontrol/fwcontrol.c
463
get_crom(fd, tmp, crom_buf, len);
usr.sbin/fwcontrol/fwcontrol.c
467
tmp = strtol(optarg, NULL, 0);
usr.sbin/fwcontrol/fwcontrol.c
468
get_crom(fd, tmp, crom_buf, len);
usr.sbin/inetd/inetd.c
262
int tmp;
usr.sbin/inetd/inetd.c
265
tmp = strtol(arg, &p, 0);
usr.sbin/inetd/inetd.c
266
if (tmp < 0 || *p) {
usr.sbin/inetd/inetd.c
270
*value = tmp;
usr.sbin/installer/dfuibe_installer/flow.c
1485
a->os_root, cmd_name(a, "MKDIR"), a->tmp);
usr.sbin/installer/dfuibe_installer/flow.c
1487
a->os_root, cmd_name(a, "CP"), a->os_root, a->tmp);
usr.sbin/installer/dfuibe_installer/flow.c
1493
a->tmp, a->os_root);
usr.sbin/installer/dfuibe_installer/fn_configure.c
1218
a->os_root, cmd_name(a, "RM"), a->tmp,
usr.sbin/installer/dfuibe_installer/fn_configure.c
1220
a->os_root, a->tmp);
usr.sbin/installer/dfuibe_installer/fn_configure.c
1266
a->tmp,
usr.sbin/installer/dfuibe_installer/fn_disk.c
721
a->tmp);
usr.sbin/installer/dfuibe_installer/fn_disk.c
728
a->tmp);
usr.sbin/installer/dfuibe_installer/fn_disk.c
733
a->tmp);
usr.sbin/installer/dfuibe_installer/fn_disk.c
737
a->os_root, cmd_name(a, "CAT"), a->tmp);
usr.sbin/installer/dfuibe_installer/fn_disk.c
744
a->os_root, cmd_name(a, "FDISK"), a->tmp,
usr.sbin/installer/dfuibe_installer/fn_disk.c
756
a->tmp,
usr.sbin/installer/dfuibe_installer/fn_install.c
754
a->tmp, a->os_root);
usr.sbin/installer/dfuibe_installer/fn_subpart_hammer.c
118
a->tmp,
usr.sbin/installer/dfuibe_installer/fn_subpart_hammer.c
128
a->tmp,
usr.sbin/installer/dfuibe_installer/fn_subpart_hammer.c
147
a->tmp,
usr.sbin/installer/dfuibe_installer/fn_subpart_hammer.c
149
a->tmp);
usr.sbin/installer/dfuibe_installer/fn_subpart_hammer.c
158
a->os_root, cmd_name(a, "ECHO"), num_partitions ,a->tmp);
usr.sbin/installer/dfuibe_installer/fn_subpart_hammer.c
162
a->tmp);
usr.sbin/installer/dfuibe_installer/fn_subpart_hammer.c
189
a->tmp);
usr.sbin/installer/dfuibe_installer/fn_subpart_hammer.c
197
a->tmp);
usr.sbin/installer/dfuibe_installer/fn_subpart_hammer.c
205
whichfs, a->tmp);
usr.sbin/installer/dfuibe_installer/fn_subpart_hammer.c
216
a->tmp);
usr.sbin/installer/dfuibe_installer/fn_subpart_ufs.c
103
a->tmp,
usr.sbin/installer/dfuibe_installer/fn_subpart_ufs.c
113
a->tmp,
usr.sbin/installer/dfuibe_installer/fn_subpart_ufs.c
129
a->tmp,
usr.sbin/installer/dfuibe_installer/fn_subpart_ufs.c
131
a->tmp);
usr.sbin/installer/dfuibe_installer/fn_subpart_ufs.c
140
a->os_root, cmd_name(a, "ECHO"), num_partitions ,a->tmp);
usr.sbin/installer/dfuibe_installer/fn_subpart_ufs.c
144
a->tmp);
usr.sbin/installer/dfuibe_installer/fn_subpart_ufs.c
169
a->tmp);
usr.sbin/installer/dfuibe_installer/fn_subpart_ufs.c
176
a->tmp);
usr.sbin/installer/dfuibe_installer/fn_subpart_ufs.c
187
a->tmp);
usr.sbin/installer/libinstaller/commands.c
231
aura_buffer_cat_file(error_log, "%sinstall.log", a->tmp);
usr.sbin/installer/libinstaller/commands.c
395
asprintf(&filename, "%sinstall.log", a->tmp);
usr.sbin/installer/libinstaller/confed.c
178
asprintf(&tmp_filename, "%sextract_vars", a->tmp);
usr.sbin/installer/libinstaller/confed.c
184
fprintf(script, "set | %susr/bin/sort >%senv.before\n", a->os_root, a->tmp);
usr.sbin/installer/libinstaller/confed.c
186
fprintf(script, "set | %susr/bin/sort >%senv.after\n", a->os_root, a->tmp);
usr.sbin/installer/libinstaller/confed.c
188
a->os_root, a->tmp, a->tmp);
usr.sbin/installer/libinstaller/confed.c
195
a->os_root, a->tmp, a->tmp);
usr.sbin/installer/libinstaller/confed.c
200
a->os_root, a->tmp, a->tmp);
usr.sbin/installer/libinstaller/confed.c
211
asprintf(&tmp_filename, "%sextract_vars", a->tmp);
usr.sbin/installer/libinstaller/confed.c
215
asprintf(&tmp_filename, "%sextracted_vars.txt", a->tmp);
usr.sbin/installer/libinstaller/functions.c
114
a->tmp = def_tmp_dir; /* XXX temporarily set to this */
usr.sbin/installer/libinstaller/functions.c
124
a->tmp = cmd_name(a, "INSTALLER_TEMP");
usr.sbin/installer/libinstaller/functions.c
347
asprintf(&filename, "%s%s", a->tmp, (char *)rk);
usr.sbin/installer/libinstaller/functions.c
77
a->tmp = NULL;
usr.sbin/installer/libinstaller/functions.h
65
const char *tmp; /* directory for temporary files */
usr.sbin/installer/libinstaller/survey.c
204
a->os_root, cmd_name(a, "ECHO"), a->tmp);
usr.sbin/installer/libinstaller/survey.c
225
a->os_root, cmd_name(a, "ECHO"), a->tmp);
usr.sbin/installer/libinstaller/survey.c
228
a->os_root, cmd_name(a, "ECHO"), disk, a->tmp);
usr.sbin/installer/libinstaller/survey.c
235
a->os_root, cmd_name(a, "ECHO"), a->tmp);
usr.sbin/installer/libinstaller/survey.c
241
a->tmp);
usr.sbin/installer/libinstaller/survey.c
244
a->os_root, cmd_name(a, "ECHO"), a->tmp);
usr.sbin/installer/libinstaller/survey.c
251
a->os_root, cmd_name(a, "ECHO"), a->tmp);
usr.sbin/installer/libinstaller/survey.c
261
a->tmp);
usr.sbin/installer/libinstaller/survey.c
263
a->os_root, cmd_name(a, "ECHO"), a->tmp);
usr.sbin/installer/libinstaller/survey.c
270
a->os_root, cmd_name(a, "ECHO"), a->tmp);
usr.sbin/installer/libinstaller/survey.c
275
a->tmp,
usr.sbin/installer/libinstaller/survey.c
277
a->tmp);
usr.sbin/installer/libinstaller/survey.c
279
a->os_root, cmd_name(a, "ECHO"), a->tmp);
usr.sbin/installer/libinstaller/survey.c
284
a->os_root, cmd_name(a, "ECHO"), a->tmp);
usr.sbin/installer/libinstaller/survey.c
297
asprintf(&filename, "%ssurvey.txt", a->tmp);
usr.sbin/kbdmap/kbdmap.c
241
char *tmp, *p, *q;
usr.sbin/kbdmap/kbdmap.c
249
tmp = strdup(fnt);
usr.sbin/kbdmap/kbdmap.c
252
p = strrchr(tmp, '-');
usr.sbin/kbdmap/kbdmap.c
276
free(tmp);
usr.sbin/kbdmap/kbdmap.c
301
char *vid_cmd, *tmp, *p, *q;
usr.sbin/kbdmap/kbdmap.c
307
tmp = strdup(km->keym);
usr.sbin/kbdmap/kbdmap.c
308
p = strrchr(tmp, '-');
usr.sbin/kbdmap/kbdmap.c
317
free(tmp);
usr.sbin/kbdmap/kbdmap.c
617
char *tmp = strdup(lng);
usr.sbin/kbdmap/kbdmap.c
618
char *delim = tmp;
usr.sbin/kbdmap/kbdmap.c
620
for (delim = tmp; ; ) {
usr.sbin/kbdmap/kbdmap.c
624
if (!sl_find(lang_list, tmp))
usr.sbin/kbdmap/kbdmap.c
625
sl_add(lang_list, tmp);
usr.sbin/kbdmap/kbdmap.c
628
tmp = delim;
usr.sbin/lpr/lpd/printjob.c
1832
char *s = strdup(pp->mode_set), *tmp;
usr.sbin/lpr/lpd/printjob.c
1834
while ((tmp = strsep(&s, ",")) != NULL) {
usr.sbin/lpr/lpd/printjob.c
1835
msearch(tmp, &ttybuf);
usr.sbin/makefs/cd9660.c
1032
char *tmp;
usr.sbin/makefs/cd9660.c
1046
tmp = emalloc(ISO_FILENAME_MAXLENGTH);
usr.sbin/makefs/cd9660.c
1093
memmove(&tmp[numbts],&tmp[dot],4);
usr.sbin/makefs/cd9660.c
1100
memcpy(tmp, (iter->o_name), numbts);
usr.sbin/makefs/cd9660.c
1107
snprintf(&tmp[numbts], ISO_FILENAME_MAXLENGTH - numbts,
usr.sbin/makefs/cd9660.c
1115
tmp[numbts] = (*naming);
usr.sbin/makefs/cd9660.c
1120
tmp[numbts] = ';';
usr.sbin/makefs/cd9660.c
1121
tmp[numbts+1] = '1';
usr.sbin/makefs/cd9660.c
1122
tmp[numbts+2] = '\0';
usr.sbin/makefs/cd9660.c
1128
memcpy((iter->isoDirRecord->name), tmp, numbts + 3);
usr.sbin/makefs/cd9660.c
1134
free(tmp);
usr.sbin/makefs/cd9660/cd9660_debug.c
145
volume_descriptor *tmp = diskStructure->firstVolumeDescriptor;
usr.sbin/makefs/cd9660/cd9660_debug.c
150
while (tmp != NULL) {
usr.sbin/makefs/cd9660/cd9660_debug.c
152
memcpy(temp, tmp->volumeDescriptorData + 1, 5);
usr.sbin/makefs/cd9660/cd9660_debug.c
155
tmp->sector, tmp->volumeDescriptorData[0], temp);
usr.sbin/makefs/cd9660/cd9660_debug.c
156
switch(tmp->volumeDescriptorData[0]) {
usr.sbin/makefs/cd9660/cd9660_debug.c
172
tmp = tmp->next;
usr.sbin/makefs/hammer2.c
1274
char *o, tmp[PATH_MAX];
usr.sbin/makefs/hammer2.c
1284
strlcpy(tmp, p, sizeof(tmp));
usr.sbin/makefs/hammer2.c
1285
if (strncmp(tmp, p, sizeof(tmp)))
usr.sbin/makefs/hammer2.c
1294
if (tmp[i] == c) {
usr.sbin/makefs/hammer2.c
1296
*p++ = tmp[i];
usr.sbin/makefs/hammer2.c
1299
*p++ = tmp[i];
usr.sbin/makefs/hammer2.c
1304
assert(strlen(p) <= strlen(tmp));
usr.sbin/makefs/hammer2.c
1538
char tmp[PATH_MAX];
usr.sbin/makefs/hammer2.c
1569
bzero(tmp, sizeof(tmp));
usr.sbin/makefs/hammer2.c
1570
error = hammer2_readlink(vp, tmp, sizeof(tmp));
usr.sbin/makefs/hammer2.c
1573
if (!is_supported_link(tmp))
usr.sbin/makefs/hammer2.c
1575
strlcat(tmp, "/", sizeof(tmp));
usr.sbin/makefs/hammer2.c
1576
strlcat(tmp, p, sizeof(tmp));
usr.sbin/makefs/hammer2.c
1577
error = trim_slash(tmp);
usr.sbin/makefs/hammer2.c
1580
p = name = tmp;
usr.sbin/makefs/hammer2.c
1659
char tmp[PATH_MAX];
usr.sbin/makefs/hammer2.c
1727
bzero(tmp, sizeof(tmp));
usr.sbin/makefs/hammer2.c
1728
error = hammer2_readlink(vp, tmp, sizeof(tmp));
usr.sbin/makefs/hammer2.c
1731
if (!is_supported_link(tmp))
usr.sbin/makefs/hammer2.c
1733
strlcat(tmp, "/", sizeof(tmp));
usr.sbin/makefs/hammer2.c
1734
strlcat(tmp, p, sizeof(tmp));
usr.sbin/makefs/hammer2.c
1735
error = trim_slash(tmp);
usr.sbin/makefs/hammer2.c
1738
p = name = tmp;
usr.sbin/makefs/hammer2.c
1777
char tmp[PATH_MAX];
usr.sbin/makefs/hammer2.c
1884
bzero(tmp, sizeof(tmp));
usr.sbin/makefs/hammer2.c
1885
error = hammer2_readlink(vp, tmp, sizeof(tmp));
usr.sbin/makefs/hammer2.c
1888
if (!is_supported_link(tmp))
usr.sbin/makefs/hammer2.c
1890
strlcat(tmp, "/", sizeof(tmp));
usr.sbin/makefs/hammer2.c
1891
strlcat(tmp, p, sizeof(tmp));
usr.sbin/makefs/hammer2.c
1892
error = trim_slash(tmp);
usr.sbin/makefs/hammer2.c
1895
p = name = tmp;
usr.sbin/makefs/hammer2.c
1953
char tmp[PATH_MAX];
usr.sbin/makefs/hammer2.c
1981
bzero(tmp, sizeof(tmp));
usr.sbin/makefs/hammer2.c
1982
error = hammer2_readlink(vp, tmp, sizeof(tmp));
usr.sbin/makefs/hammer2.c
1985
if (!is_supported_link(tmp))
usr.sbin/makefs/hammer2.c
1987
strlcat(tmp, "/", sizeof(tmp));
usr.sbin/makefs/hammer2.c
1988
strlcat(tmp, p, sizeof(tmp));
usr.sbin/makefs/hammer2.c
1989
error = trim_slash(tmp);
usr.sbin/makefs/hammer2.c
1992
p = name = tmp;
usr.sbin/makefs/hammer2.c
2158
char *buf, tmp[PATH_MAX];
usr.sbin/makefs/hammer2.c
2164
snprintf(tmp, sizeof(tmp), "%s/%s", dir, name);
usr.sbin/makefs/hammer2.c
2165
if (stat(tmp, &st) == -1 && mkdir(tmp, 0666) == -1)
usr.sbin/makefs/hammer2.c
2166
err(1, "failed to mkdir %s", tmp);
usr.sbin/makefs/hammer2.c
2184
error = hammer2_readx_handle(vp, tmp,
usr.sbin/makefs/hammer2.c
2195
hammer2_utimes(dvp, tmp);
usr.sbin/makefs/hammer2.c
2314
char tmp[PATH_MAX];
usr.sbin/makefs/hammer2.c
2347
bzero(tmp, sizeof(tmp));
usr.sbin/makefs/hammer2.c
2348
error = hammer2_readlink(vp, tmp, sizeof(tmp));
usr.sbin/makefs/hammer2.c
2351
if (!is_supported_link(tmp))
usr.sbin/makefs/hammer2.c
2353
strlcat(tmp, "/", sizeof(tmp));
usr.sbin/makefs/hammer2.c
2354
strlcat(tmp, p, sizeof(tmp));
usr.sbin/makefs/hammer2.c
2355
error = trim_slash(tmp);
usr.sbin/makefs/hammer2.c
2358
p = name = tmp;
usr.sbin/makefs/hammer2/hammer2_inode.c
1845
struct hammer2_inode *ip, *tmp;
usr.sbin/makefs/hammer2/hammer2_inode.c
1862
tmp = ip->next;
usr.sbin/makefs/hammer2/hammer2_inode.c
1874
ip = tmp;
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2003
struct statfs tmp;
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2011
bzero(&tmp, sizeof(tmp));
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2022
tmp.f_files = bref.embed.stats.inode_count;
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2023
tmp.f_ffree = 0;
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2024
tmp.f_blocks = hmp->voldata.allocator_size /
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2026
tmp.f_bfree = hmp->voldata.allocator_free /
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2028
tmp.f_bavail = tmp.f_bfree;
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2035
tmp.f_blocks -= adj;
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2036
tmp.f_bfree -= adj;
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2037
tmp.f_bavail -= adj;
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2040
mp->mnt_stat.f_blocks = tmp.f_blocks;
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2041
mp->mnt_stat.f_bfree = tmp.f_bfree;
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2042
mp->mnt_stat.f_bavail = tmp.f_bavail;
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2043
mp->mnt_stat.f_files = tmp.f_files;
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2044
mp->mnt_stat.f_ffree = tmp.f_ffree;
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2058
struct statvfs tmp;
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2065
bzero(&tmp, sizeof(tmp));
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2076
tmp.f_files = bref.embed.stats.inode_count;
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2077
tmp.f_ffree = 0;
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2078
tmp.f_blocks = hmp->voldata.allocator_size /
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2080
tmp.f_bfree = hmp->voldata.allocator_free /
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2082
tmp.f_bavail = tmp.f_bfree;
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2089
tmp.f_blocks -= adj;
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2090
tmp.f_bfree -= adj;
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2091
tmp.f_bavail -= adj;
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2094
mp->mnt_vstat.f_blocks = tmp.f_blocks;
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2095
mp->mnt_vstat.f_bfree = tmp.f_bfree;
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2096
mp->mnt_vstat.f_bavail = tmp.f_bavail;
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2097
mp->mnt_vstat.f_files = tmp.f_files;
usr.sbin/makefs/hammer2/hammer2_vfsops.c
2098
mp->mnt_vstat.f_ffree = tmp.f_ffree;
usr.sbin/makefs/hammer2/hammer2_xops.c
522
hammer2_chain_t *tmp;
usr.sbin/makefs/hammer2/hammer2_xops.c
767
tmp = hammer2_chain_lookup(&parent, &key_next,
usr.sbin/makefs/hammer2/hammer2_xops.c
772
while (tmp) {
usr.sbin/makefs/hammer2/hammer2_xops.c
774
if (hammer2_chain_dirent_test(tmp, xop->head.name2,
usr.sbin/makefs/hammer2/hammer2_xops.c
776
e2 = hammer2_chain_delete(parent, tmp,
usr.sbin/makefs/hammer2/hammer2_xops.c
781
tmp = hammer2_chain_next(&parent, tmp, &key_next,
usr.sbin/makefs/hammer2/hammer2_xops.c
794
tmp = hammer2_chain_lookup(&parent, &key_next,
usr.sbin/makefs/hammer2/hammer2_xops.c
797
KKASSERT(tmp == NULL);
usr.sbin/makefs/hammer2/zlib/hammer2_zlib_adler32.c
31
unsigned long tmp = a >> 16; \
usr.sbin/makefs/hammer2/zlib/hammer2_zlib_adler32.c
33
a += (tmp << 4) - tmp; \
usr.sbin/makefs/hammer2/zlib/hammer2_zlib_adler32.c
47
z_off64_t tmp = a >> 32; \
usr.sbin/makefs/hammer2/zlib/hammer2_zlib_adler32.c
49
a += (tmp << 8) - (tmp << 5) + tmp; \
usr.sbin/makefs/hammer2/zlib/hammer2_zlib_adler32.c
50
tmp = a >> 16; \
usr.sbin/makefs/hammer2/zlib/hammer2_zlib_adler32.c
52
a += (tmp << 4) - tmp; \
usr.sbin/makefs/hammer2/zlib/hammer2_zlib_adler32.c
53
tmp = a >> 16; \
usr.sbin/makefs/hammer2/zlib/hammer2_zlib_adler32.c
55
a += (tmp << 4) - tmp; \
usr.sbin/makefs/walk.c
645
uint64_t tmp;
usr.sbin/makefs/walk.c
680
tmp = entry->st.st_dev;
usr.sbin/makefs/walk.c
681
tmp <<= HTBITS>>1;
usr.sbin/makefs/walk.c
682
tmp |= entry->st.st_ino;
usr.sbin/makefs/walk.c
683
tmp *= HTCONST;
usr.sbin/makefs/walk.c
684
h = tmp >> (HTBITS - htshift);
usr.sbin/makefs/walk.c
685
h2 = 1 | ( tmp >> (HTBITS - (htshift<<1) - 1)); /* must be odd */
usr.sbin/mpsutil/mpsutil.c
215
int n, tmp, retval = 0;
usr.sbin/mpsutil/mpsutil.c
221
tmp = retval;
usr.sbin/mpsutil/mpsutil.c
225
PCHAR(retval != tmp ? ',' : '<');
usr.sbin/mpsutil/mpsutil.c
232
if (retval != tmp)
usr.sbin/mtree/misc.c
111
KEY *k, tmp;
usr.sbin/mtree/misc.c
119
tmp.name = name;
usr.sbin/mtree/misc.c
122
k = (KEY *)bsearch(&tmp, keylist, sizeof(keylist) / sizeof(KEY),
usr.sbin/mtree/misc.c
136
KEY *k, tmp;
usr.sbin/mtree/misc.c
138
tmp.name = name;
usr.sbin/mtree/misc.c
139
k = (KEY *)bsearch(&tmp, typelist, sizeof(typelist) / sizeof(KEY),
usr.sbin/newsyslog/newsyslog.c
1930
char *tmp;
usr.sbin/newsyslog/newsyslog.c
1979
asprintf(&tmp, "%s %d", swork->sw_fname, swork->sw_signum);
usr.sbin/newsyslog/newsyslog.c
1980
if (tmp == NULL) {
usr.sbin/newsyslog/newsyslog.c
1986
printf("Run command: %s\n", tmp);
usr.sbin/newsyslog/newsyslog.c
1987
kres = system(tmp);
usr.sbin/newsyslog/newsyslog.c
1990
tmp, kres);
usr.sbin/newsyslog/newsyslog.c
1992
free(tmp);
usr.sbin/newsyslog/newsyslog.c
2440
char tmp[MAXPATHLEN + sizeof(".0") + COMPRESS_SUFFIX_MAXLEN + 1];
usr.sbin/newsyslog/newsyslog.c
2448
strlcpy(tmp, archdirname, sizeof(tmp));
usr.sbin/newsyslog/newsyslog.c
2451
strlcpy(tmp, file, sizeof(tmp));
usr.sbin/newsyslog/newsyslog.c
2452
if ((p = strrchr(tmp, '/')) == NULL)
usr.sbin/newsyslog/newsyslog.c
2453
tmp[0] = '\0';
usr.sbin/newsyslog/newsyslog.c
2456
strlcat(tmp, archdirname, sizeof(tmp));
usr.sbin/newsyslog/newsyslog.c
2459
strlcat(tmp, "/", sizeof(tmp));
usr.sbin/newsyslog/newsyslog.c
2463
strlcat(tmp, file, sizeof(tmp));
usr.sbin/newsyslog/newsyslog.c
2465
strlcat(tmp, p + 1, sizeof(tmp));
usr.sbin/newsyslog/newsyslog.c
2467
strlcpy(tmp, file, sizeof(tmp));
usr.sbin/newsyslog/newsyslog.c
2471
mtime = mtime_old_timelog(tmp);
usr.sbin/newsyslog/newsyslog.c
2475
strlcat(tmp, ".0", sizeof(tmp));
usr.sbin/newsyslog/newsyslog.c
2476
logfile_suffix = get_logfile_suffix(tmp);
usr.sbin/newsyslog/newsyslog.c
2479
(void) strlcat(tmp, logfile_suffix, sizeof(tmp));
usr.sbin/newsyslog/newsyslog.c
2480
if (stat(tmp, &sb) < 0)
usr.sbin/newsyslog/ptimes.c
229
char *tmp;
usr.sbin/newsyslog/ptimes.c
248
l = strtol(s, &tmp, 10);
usr.sbin/newsyslog/ptimes.c
251
endval = tmp;
usr.sbin/newsyslog/ptimes.c
261
l = strtol(s, &tmp, 10);
usr.sbin/newsyslog/ptimes.c
264
endval = tmp;
usr.sbin/newsyslog/ptimes.c
296
l = strtol(s, &tmp, 10);
usr.sbin/newsyslog/ptimes.c
302
endval = tmp;
usr.sbin/pfctl/parse.y
4638
char *tmp;
usr.sbin/pfctl/parse.y
4641
if ((tmp = calloc(1, len)) == NULL)
usr.sbin/pfctl/parse.y
4646
if ((strlcat(tmp, p, len) >= len) ||
usr.sbin/pfctl/parse.y
4647
(strlcat(tmp, repl, len) >= len))
usr.sbin/pfctl/parse.y
4652
if (strlcat(tmp, p, len) >= len)
usr.sbin/pfctl/parse.y
4654
strlcpy(label, tmp, len); /* always fits */
usr.sbin/pfctl/parse.y
4655
free(tmp);
usr.sbin/pfctl/parse.y
4673
char tmp[64], tmp_not[66];
usr.sbin/pfctl/parse.y
4678
snprintf(tmp, sizeof(tmp), "(%s)", h->addr.v.ifname);
usr.sbin/pfctl/parse.y
4681
snprintf(tmp, sizeof(tmp), "<%s>", h->addr.v.tblname);
usr.sbin/pfctl/parse.y
4684
snprintf(tmp, sizeof(tmp), "no-route");
usr.sbin/pfctl/parse.y
4687
snprintf(tmp, sizeof(tmp), "urpf-failed");
usr.sbin/pfctl/parse.y
4692
snprintf(tmp, sizeof(tmp), "any");
usr.sbin/pfctl/parse.y
4699
snprintf(tmp, sizeof(tmp), "?");
usr.sbin/pfctl/parse.y
4704
snprintf(tmp, sizeof(tmp),
usr.sbin/pfctl/parse.y
4707
snprintf(tmp, sizeof(tmp),
usr.sbin/pfctl/parse.y
4713
snprintf(tmp, sizeof(tmp), "?");
usr.sbin/pfctl/parse.y
4718
snprintf(tmp_not, sizeof(tmp_not), "! %s", tmp);
usr.sbin/pfctl/parse.y
4721
expand_label_str(label, len, name, tmp);
usr.sbin/pfctl/pf_print_state.c
373
u_int32_t tmp;
usr.sbin/pfctl/pf_print_state.c
380
tmp = ntohl(m->addr32[j]);
usr.sbin/pfctl/pf_print_state.c
381
for (i = 31; tmp & (1 << i); --i)
usr.sbin/pfctl/pfctl_osfp.c
1012
char tmp[32];
usr.sbin/pfctl/pfctl_osfp.c
1025
snprintf(tmp, sizeof(tmp), "%d", fp->fp_wsize);
usr.sbin/pfctl/pfctl_osfp.c
1026
strlcat(buf, tmp, sizeof(buf));
usr.sbin/pfctl/pfctl_osfp.c
1030
snprintf(tmp, sizeof(tmp), "%d", fp->fp_ttl);
usr.sbin/pfctl/pfctl_osfp.c
1031
strlcat(buf, tmp, sizeof(buf));
usr.sbin/pfctl/pfctl_osfp.c
1045
snprintf(tmp, sizeof(tmp), "%d", fp->fp_psize);
usr.sbin/pfctl/pfctl_osfp.c
1046
strlcat(buf, tmp, sizeof(buf));
usr.sbin/pfctl/pfctl_osfp.c
1074
snprintf(tmp, sizeof(tmp), "%d", fp->fp_mss);
usr.sbin/pfctl/pfctl_osfp.c
1075
strlcat(buf, tmp, sizeof(buf));
usr.sbin/pfctl/pfctl_osfp.c
1085
snprintf(tmp, sizeof(tmp), "%d", fp->fp_wscale);
usr.sbin/pfctl/pfctl_osfp.c
1086
strlcat(buf, tmp, sizeof(buf));
usr.sbin/pfctl/pfctl_osfp.c
1103
snprintf(tmp, sizeof(tmp), "TcpOpts %d 0x%llx", fp->fp_optcnt,
usr.sbin/pfctl/pfctl_osfp.c
1105
strlcat(buf, tmp, sizeof(buf));
usr.sbin/pflogd/privsep_fdpass.c
101
msg.msg_control = tmp;
usr.sbin/pflogd/privsep_fdpass.c
102
msg.msg_controllen = sizeof(tmp);
usr.sbin/pflogd/privsep_fdpass.c
53
char tmp[CMSG_SPACE(sizeof(int))];
usr.sbin/pflogd/privsep_fdpass.c
62
msg.msg_control = (caddr_t)tmp;
usr.sbin/pflogd/privsep_fdpass.c
89
char tmp[CMSG_SPACE(sizeof(int))];
usr.sbin/ppp/ip.c
475
u_short *hptr, tmp;
usr.sbin/ppp/ip.c
516
memcpy(&tmp, end, sizeof tmp);
usr.sbin/ppp/ip.c
517
qtype = dns_Qtype2Txt(ntohs(tmp));
usr.sbin/ppp/ip.c
518
memcpy(&tmp, end + 2, sizeof tmp);
usr.sbin/ppp/ip.c
519
qclass = dns_Qclass2Txt(ntohs(tmp));
usr.sbin/ppp/route.c
100
log_Printf(LogDEBUG, " Addr %s\n", tmp);
usr.sbin/ppp/route.c
102
inet_ntop(pmask->sa_family, pmask->sa_data, tmp, sizeof tmp);
usr.sbin/ppp/route.c
103
log_Printf(LogDEBUG, " Mask %s\n", tmp);
usr.sbin/ppp/route.c
94
char tmp[50];
usr.sbin/ppp/route.c
99
inet_ntop(phost->sa_family, phost->sa_data, tmp, sizeof tmp);
usr.sbin/pw/fileupd.c
45
char *tmp = realloc(*buf, needed);
usr.sbin/pw/fileupd.c
46
if (tmp == NULL)
usr.sbin/pw/fileupd.c
48
*buf = tmp;
usr.sbin/pw/fileupd.c
58
char **tmp = realloc(*buf, needed * sizeof(char *));
usr.sbin/pw/fileupd.c
59
if (tmp == NULL)
usr.sbin/pw/fileupd.c
61
*buf = tmp;
usr.sbin/pw/psdate.c
228
char *q, tmp[64];
usr.sbin/pw/psdate.c
234
strlcpy(tmp, str, sizeof(tmp));
usr.sbin/pw/psdate.c
235
str = tmp;
usr.sbin/pw/psdate.c
241
while ((q = strrchr(tmp, ' ')) != NULL) {
usr.sbin/pw/psdate.c
259
if ((p = strchr(tmp, ':')) == NULL) {
usr.sbin/pw/psdate.c
265
parse_datesub(tmp, &T->tm_mday, &T->tm_mon, &T->tm_year);
usr.sbin/pw/psdate.c
279
} else if ((q = strrchr(tmp, ' ')) != NULL) { /* Time last */
usr.sbin/pw/psdate.c
280
int l = q - tmp;
usr.sbin/pw/psdate.c
283
strlcpy(datestr, tmp, l + 1);
usr.sbin/pw/pw.c
138
int tmp;
usr.sbin/pw/pw.c
155
else if (mode == -1 && (tmp = getindex(Modes, argv[1])) != -1)
usr.sbin/pw/pw.c
156
mode = tmp;
usr.sbin/pw/pw.c
157
else if (which == -1 && (tmp = getindex(Which, argv[1])) != -1)
usr.sbin/pw/pw.c
158
which = tmp;
usr.sbin/pw/pw.c
160
((tmp = getindex(Combo1, argv[1])) != -1 ||
usr.sbin/pw/pw.c
161
(tmp = getindex(Combo2, argv[1])) != -1)) {
usr.sbin/pw/pw.c
162
which = tmp / M_NUM;
usr.sbin/pw/pw.c
163
mode = tmp % M_NUM;
usr.sbin/pw/pw_user.c
1229
char tmp[MAXPATHLEN];
usr.sbin/pw/pw_user.c
1231
sprintf(tmp, "/usr/bin/atrm %s", e->d_name);
usr.sbin/pw/pw_user.c
1232
system(tmp);
usr.sbin/pw/pw_user.c
873
char tmp[32];
usr.sbin/pw/pw_user.c
888
sprintf(tmp, "%lu", (unsigned long) prefer);
usr.sbin/pw/pw_user.c
889
addarg(&grpargs, 'g', tmp);
usr.sbin/rpc.yppasswdd/yppasswdd_server.c
237
char *tmp = NULL;
usr.sbin/rpc.yppasswdd/yppasswdd_server.c
258
tmp = (char *)dirp->d_name;
usr.sbin/rpc.yppasswdd/yppasswdd_server.c
262
if (yp_get_record(tmp,"master.passwd.byname",
usr.sbin/rpc.yppasswdd/yppasswdd_server.c
271
snprintf(domain, YPMAXDOMAIN, "%s", tmp);
usr.sbin/rpcbind/rpcb_svc_4.c
435
rpcb_entry_list_ptr rbl, tmp;
usr.sbin/rpcbind/rpcb_svc_4.c
438
tmp = rbl;
usr.sbin/rpcbind/rpcb_svc_4.c
440
free((char *)tmp->rpcb_entry_map.r_maddr);
usr.sbin/rpcbind/rpcb_svc_4.c
441
free((char *)tmp);
usr.sbin/rpcbind/rpcb_svc_com.c
241
rpcblist_ptr rbl, prev, tmp;
usr.sbin/rpcbind/rpcb_svc_com.c
265
tmp = rbl;
usr.sbin/rpcbind/rpcb_svc_com.c
271
free(tmp->rpcb_map.r_addr);
usr.sbin/rpcbind/rpcb_svc_com.c
272
free(tmp->rpcb_map.r_netid);
usr.sbin/rpcbind/rpcb_svc_com.c
273
free(tmp->rpcb_map.r_owner);
usr.sbin/rpcbind/rpcb_svc_com.c
274
free(tmp);
usr.sbin/rwhod/rwhod.c
171
long tmp;
usr.sbin/rwhod/rwhod.c
187
tmp = strtol(*argv, &ep, 10);
usr.sbin/rwhod/rwhod.c
188
if (*ep != '\0' || tmp < INT_MIN || tmp > INT_MAX)
usr.sbin/rwhod/rwhod.c
190
multicast_scope = (int)tmp;
usr.sbin/spray/spray.c
220
long tmp;
usr.sbin/spray/spray.c
222
tmp = strtol(arg, &ep, 10);
usr.sbin/spray/spray.c
223
if (*ep != '\0' || tmp < INT_MIN || tmp > INT_MAX)
usr.sbin/spray/spray.c
226
return((int)tmp);
usr.sbin/uefisign/pe.c
315
uint16_t tmp;
usr.sbin/uefisign/pe.c
322
for (i = 0; i + sizeof(tmp) < x->x_len; i += 2) {
usr.sbin/uefisign/pe.c
328
tmp = 0;
usr.sbin/uefisign/pe.c
330
assert(i + sizeof(tmp) <= x->x_len);
usr.sbin/uefisign/pe.c
331
memcpy(&tmp, x->x_buf + i, sizeof(tmp));
usr.sbin/uefisign/pe.c
334
cksum += tmp;
usr.sbin/uefisign/uefisign.c
123
unsigned char *hex, *tmp, ch;
usr.sbin/uefisign/uefisign.c
132
tmp = hex;
usr.sbin/uefisign/uefisign.c
135
tmp += sprintf(tmp, "%02x", ch);
usr.sbin/uefisign/uefisign.c
158
unsigned char *buf, *tmp;
usr.sbin/uefisign/uefisign.c
208
tmp = buf = calloc(1, len);
usr.sbin/uefisign/uefisign.c
209
if (tmp == NULL)
usr.sbin/uefisign/uefisign.c
211
i2d_ASN1_TYPE(t, &tmp);
usr.sbin/uefisign/uefisign.c
216
tmp = NULL;
usr.sbin/vnconfig/vnconfig.c
272
const char *tmp;
usr.sbin/vnconfig/vnconfig.c
280
tmp = vname;
usr.sbin/vnconfig/vnconfig.c
281
while (*tmp != 0) {
usr.sbin/vnconfig/vnconfig.c
282
if(isdigit(*tmp)){
usr.sbin/vnconfig/vnconfig.c
283
i = atoi(tmp);
usr.sbin/vnconfig/vnconfig.c
287
tmp++;
usr.sbin/vnconfig/vnconfig.c
289
if (*tmp == '\0')
usr.sbin/yppush/yppush_main.c
488
struct hostlist *tmp;
usr.sbin/yppush/yppush_main.c
504
if ((tmp = (struct hostlist *)malloc(sizeof(struct hostlist))) == NULL) {
usr.sbin/yppush/yppush_main.c
508
tmp->name = strdup(optarg);
usr.sbin/yppush/yppush_main.c
509
tmp->next = yppush_hostlist;
usr.sbin/yppush/yppush_main.c
510
yppush_hostlist = tmp;
usr.sbin/yppush/yppush_main.c
596
tmp = yppush_hostlist;
usr.sbin/yppush/yppush_main.c
597
while (tmp) {
usr.sbin/yppush/yppush_main.c
598
yppush_foreach(YP_TRUE, NULL, 0, tmp->name,
usr.sbin/yppush/yppush_main.c
599
strlen(tmp->name), NULL);
usr.sbin/yppush/yppush_main.c
600
tmp = tmp->next;
usr.sbin/ypserv/yp_access.c
107
struct securenet *tmp;
usr.sbin/ypserv/yp_access.c
115
tmp = securenets->next;
usr.sbin/ypserv/yp_access.c
117
securenets = tmp;
usr.sbin/ypserv/yp_access.c
149
tmp = (struct securenet *)malloc(sizeof(struct securenet));
usr.sbin/ypserv/yp_access.c
151
if (!inet_aton((char *)&addr1, (struct in_addr *)&tmp->net)) {
usr.sbin/ypserv/yp_access.c
153
free(tmp);
usr.sbin/ypserv/yp_access.c
157
if (!inet_aton((char *)&addr2, (struct in_addr *)&tmp->mask)) {
usr.sbin/ypserv/yp_access.c
159
free(tmp);
usr.sbin/ypserv/yp_access.c
163
tmp->next = securenets;
usr.sbin/ypserv/yp_access.c
164
securenets = tmp;
usr.sbin/ypserv/yp_access.c
216
struct securenet *tmp;
usr.sbin/ypserv/yp_access.c
270
tmp = securenets;
usr.sbin/ypserv/yp_access.c
271
while (tmp) {
usr.sbin/ypserv/yp_access.c
272
if (((rqhost->sin_addr.s_addr & ~tmp->mask.s_addr)
usr.sbin/ypserv/yp_access.c
273
| tmp->net.s_addr) == rqhost->sin_addr.s_addr) {
usr.sbin/ypserv/yp_access.c
277
tmp = tmp->next;
usr.sbin/zic/zdump.c
133
static char *abbr(struct tm *tmp);
usr.sbin/zic/zdump.c
136
static void dumptime(const struct tm *tmp);
usr.sbin/zic/zdump.c
149
struct tm * tmp;
usr.sbin/zic/zdump.c
151
tmp = localtime(tp);
usr.sbin/zic/zdump.c
152
if (tp != NULL && tmp != NULL) {
usr.sbin/zic/zdump.c
156
tm = *tmp;
usr.sbin/zic/zdump.c
163
fprintf(stderr, " year=%d", tmp->tm_year);
usr.sbin/zic/zdump.c
164
fprintf(stderr, " mon=%d", tmp->tm_mon);
usr.sbin/zic/zdump.c
165
fprintf(stderr, " mday=%d", tmp->tm_mday);
usr.sbin/zic/zdump.c
166
fprintf(stderr, " hour=%d", tmp->tm_hour);
usr.sbin/zic/zdump.c
167
fprintf(stderr, " min=%d", tmp->tm_min);
usr.sbin/zic/zdump.c
168
fprintf(stderr, " sec=%d", tmp->tm_sec);
usr.sbin/zic/zdump.c
169
fprintf(stderr, " isdst=%d", tmp->tm_isdst);
usr.sbin/zic/zdump.c
175
return tmp;
usr.sbin/zic/zdump.c
220
struct tm *tmp;
usr.sbin/zic/zdump.c
339
tmp = my_localtime(&t);
usr.sbin/zic/zdump.c
340
if (tmp != NULL) {
usr.sbin/zic/zdump.c
341
tm = *tmp;
usr.sbin/zic/zdump.c
353
if ((tmp == NULL || newtmp == NULL) ? (tmp != newtmp) :
usr.sbin/zic/zdump.c
368
tmp = newtmp;
usr.sbin/zic/zdump.c
442
struct tm * tmp;
usr.sbin/zic/zdump.c
460
tmp = my_localtime(&t);
usr.sbin/zic/zdump.c
461
if (tmp != NULL)
usr.sbin/zic/zdump.c
462
tm = *tmp;
usr.sbin/zic/zdump.c
463
if ((lotmp == NULL || tmp == NULL) ? (lotmp == tmp) :
usr.sbin/zic/zdump.c
469
lotmp = tmp;
usr.sbin/zic/zdump.c
505
struct tm * tmp;
usr.sbin/zic/zdump.c
509
tmp = gmtime(&t);
usr.sbin/zic/zdump.c
510
if (tmp == NULL) {
usr.sbin/zic/zdump.c
513
dumptime(tmp);
usr.sbin/zic/zdump.c
518
tmp = my_localtime(&t);
usr.sbin/zic/zdump.c
519
dumptime(tmp);
usr.sbin/zic/zdump.c
520
if (tmp != NULL) {
usr.sbin/zic/zdump.c
521
if (*abbr(tmp) != '\0')
usr.sbin/zic/zdump.c
522
printf(" %s", abbr(tmp));
usr.sbin/zic/zdump.c
524
printf(" isdst=%d", tmp->tm_isdst);
usr.sbin/zic/zdump.c
525
printf(" gmtoff=%ld", tmp->TM_GMTOFF);
usr.sbin/zic/zdump.c
529
if (tmp != NULL && *abbr(tmp) != '\0')
usr.sbin/zic/zdump.c
530
abbrok(abbr(tmp), zone);
usr.sbin/zic/zdump.c
534
abbr(struct tm *tmp)
usr.sbin/zic/zdump.c
539
if (tmp->tm_isdst != 0 && tmp->tm_isdst != 1)
usr.sbin/zic/zdump.c
541
result = tzname[tmp->tm_isdst];
