Symbol: MIPS_PHYS_TO_KSEG1
sys/arch/algor/algor/algor_p4032_intr.c
68
#define REGVAL(x) *((volatile u_int32_t *)(MIPS_PHYS_TO_KSEG1((x))))
sys/arch/algor/algor/algor_p5064_intr.c
72
#define REGVAL(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x))))
sys/arch/algor/algor/led.c
58
#define LEDBASE MIPS_PHYS_TO_KSEG1(P4032_LED)
sys/arch/algor/algor/led.c
61
#define LEDBASE MIPS_PHYS_TO_KSEG1(P5064_LED1)
sys/arch/algor/algor/led.c
67
#define LEDBASE MIPS_PHYS_TO_KSEG1(P6032_HDSP2532_BASE + HD2532_CRAM)
sys/arch/algor/algor/machdep.c
217
vt->vt_addr = MIPS_PHYS_TO_KSEG1(P4032_V962PBC);
sys/arch/algor/algor/machdep.c
218
vt->vt_cfgbase = MIPS_PHYS_TO_KSEG1(P4032_PCICFG);
sys/arch/algor/algor/machdep.c
264
vt->vt_addr = MIPS_PHYS_TO_KSEG1(P5064_V360EPC);
sys/arch/algor/algor/machdep.c
265
vt->vt_cfgbase = MIPS_PHYS_TO_KSEG1(P5064_PCICFG);
sys/arch/arc/arc/bus_dma.c
678
*kvap = (void *)MIPS_PHYS_TO_KSEG1(segs[0]._ds_paddr);
sys/arch/arc/arc/bus_space_sparse.c
90
MIPS_PHYS_TO_KSEG1(start));
sys/arch/cobalt/cobalt/console.c
135
*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(CONSOLE_PROBE);
sys/arch/cobalt/cobalt/interrupt.c
437
(uint32_t *)MIPS_PHYS_TO_KSEG1(GT_BASE + GT_INTR_CAUSE);
sys/arch/cobalt/cobalt/machdep.c
379
*(volatile char *)MIPS_PHYS_TO_KSEG1(LED_ADDR) = LED_RESET;
sys/arch/cobalt/cobalt/machdep.c
514
pcicfg_addr = (uint32_t *)MIPS_PHYS_TO_KSEG1(GT_BASE + GT_PCICFG_ADDR);
sys/arch/cobalt/cobalt/machdep.c
515
pcicfg_data = (uint32_t *)MIPS_PHYS_TO_KSEG1(GT_BASE + GT_PCICFG_DATA);
sys/arch/cobalt/dev/lcdpanel.c
179
sc->sc_kp.sc_ioh = MIPS_PHYS_TO_KSEG1(LCDPANEL_BASE); /* XXX */
sys/arch/cobalt/dev/zs.c
168
zs_base = (void *)MIPS_PHYS_TO_KSEG1(maa->ma_addr);
sys/arch/cobalt/dev/zs.c
515
zs_cons = (uint8_t *)MIPS_PHYS_TO_KSEG1(ZS_BASE) + ZS_CHAN_A; /* XXX */
sys/arch/cobalt/stand/boot/boot.c
137
*(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(LED_ADDR) = LED_RESET;
sys/arch/cobalt/stand/boot/clock.c
71
mcclock_reg = (void *)MIPS_PHYS_TO_KSEG1(MCCLOCK_BASE + MCCLOCK_REG);
sys/arch/cobalt/stand/boot/clock.c
72
mcclock_data = (void *)MIPS_PHYS_TO_KSEG1(MCCLOCK_BASE + MCCLOCK_DATA);
sys/arch/cobalt/stand/boot/lcd.c
77
lcd_base = MIPS_PHYS_TO_KSEG1(LCD_BASE);
sys/arch/cobalt/stand/boot/ns16550.c
50
com_port = (void *)MIPS_PHYS_TO_KSEG1(COM_BASE + addr);
sys/arch/cobalt/stand/boot/pci.c
45
pcicfg_addr = (uint32_t *)MIPS_PHYS_TO_KSEG1(GT_BASE + GT_PCICFG_ADDR);
sys/arch/cobalt/stand/boot/pci.c
46
pcicfg_data = (uint32_t *)MIPS_PHYS_TO_KSEG1(GT_BASE + GT_PCICFG_DATA);
sys/arch/cobalt/stand/boot/pciide.c
57
cmdreg = MIPS_PHYS_TO_KSEG1(COBALT_IO_SPACE_BASE +
sys/arch/cobalt/stand/boot/pciide.c
59
ctlreg = MIPS_PHYS_TO_KSEG1(COBALT_IO_SPACE_BASE +
sys/arch/cobalt/stand/boot/tlp.c
191
l->csr = MIPS_PHYS_TO_KSEG1(pcicfgread(tag, 0x10) & ~3U);
sys/arch/cobalt/stand/boot/tlp.c
194
l->csr = MIPS_PHYS_TO_KSEG1(COBALT_TLP0_BASE);
sys/arch/cobalt/stand/boot/zs.c
131
zs = (void *)MIPS_PHYS_TO_KSEG1(ZS_BASE + addr);
sys/arch/emips/emips/bus_dma.c
698
*kvap = (void *)MIPS_PHYS_TO_KSEG1(segs[0].ds_addr);
sys/arch/emips/emips/bus_space.c
60
*bshp = MIPS_PHYS_TO_KSEG1(bpa);
sys/arch/emips/emips/machdep.c
610
cp = (char *)MIPS_PHYS_TO_KSEG1(mem << PGSHIFT);
sys/arch/evbmips/alchemy/dbau1500.c
48
(*((volatile uint16_t *)MIPS_PHYS_TO_KSEG1(x)))
sys/arch/evbmips/alchemy/dbau1500.c
50
(*((volatile uint16_t *)MIPS_PHYS_TO_KSEG1(x)) = (v))
sys/arch/evbmips/alchemy/dbau1500.c
90
whoami = *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(DBAU1500_WHOAMI));
sys/arch/evbmips/alchemy/dbau1550.c
61
(*((volatile uint16_t *)MIPS_PHYS_TO_KSEG1(x)))
sys/arch/evbmips/alchemy/dbau1550.c
63
(*((volatile uint16_t *)MIPS_PHYS_TO_KSEG1(x)) = (v))
sys/arch/evbmips/alchemy/dbau1550.c
65
(*((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(x)))
sys/arch/evbmips/alchemy/dbau1550.c
67
(*((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(x)) = (v))
sys/arch/evbmips/alchemy/mtx-1.c
49
(*((volatile uint16_t *)MIPS_PHYS_TO_KSEG1(x)))
sys/arch/evbmips/alchemy/mtx-1.c
51
(*((volatile uint16_t *)MIPS_PHYS_TO_KSEG1(x)) = (v))
sys/arch/evbmips/alchemy/omsal400.c
56
(*((volatile uint16_t *)MIPS_PHYS_TO_KSEG1(x)))
sys/arch/evbmips/alchemy/omsal400.c
58
(*((volatile uint16_t *)MIPS_PHYS_TO_KSEG1(x)) = (v))
sys/arch/evbmips/gdium/gdium_genfb.c
83
ri->ri_bits = (char *)MIPS_PHYS_TO_KSEG1(BONITO_PCILO_BASE + reg);
sys/arch/evbmips/gdium/machdep.c
260
mips3_sd(MIPS_PHYS_TO_KSEG1(BONITO_REGBASE + 0x158), 0xe);
sys/arch/evbmips/loongson/gdium_machdep.c
358
ri->ri_bits = (char *)MIPS_PHYS_TO_KSEG1(BONITO_PCILO_BASE + reg);
sys/arch/evbmips/malta/dev/gtreg.h
4
(MIPS_PHYS_TO_KSEG1(MALTA_CORECTRL_BASE + (x))))
sys/arch/evbmips/malta/leds.c
50
uint8_t *ledbar = (uint8_t *)MIPS_PHYS_TO_KSEG1(MALTA_LEDBAR);
sys/arch/evbmips/malta/leds.c
58
uint32_t *ledbar = (uint32_t *)MIPS_PHYS_TO_KSEG1(MALTA_ASCIIWORD);
sys/arch/evbmips/malta/leds.c
66
uint8_t *leds = (uint8_t *)MIPS_PHYS_TO_KSEG1(MALTA_ASCII_BASE);
sys/arch/evbmips/malta/leds.c
79
uint8_t *leds = (uint8_t *)MIPS_PHYS_TO_KSEG1(MALTA_ASCII_BASE);
sys/arch/evbmips/malta/machdep.c
125
#define REGVAL(x) *((volatile u_int32_t *)(MIPS_PHYS_TO_KSEG1((x))))
sys/arch/evbmips/malta/machdep.c
149
uint8_t * const brkres = (uint8_t *)MIPS_PHYS_TO_KSEG1(MALTA_BRKRES);
sys/arch/evbmips/malta/machdep.c
155
CTASSERT((intptr_t)MIPS_PHYS_TO_KSEG1(MALTA_BRKRES) < 0);
sys/arch/evbmips/mipssim/machdep.c
114
volatile uint8_t *data = (void *)MIPS_PHYS_TO_KSEG1(
sys/arch/evbmips/mipssim/machdep.c
243
memptr = (void *)MIPS_PHYS_TO_KSEG1(addr - sizeof(*memptr));
sys/arch/evbmips/rasoc/machdep.c
166
MIPS_PHYS_TO_KSEG1(RA_SYSCTL_BASE + RA_SYSCTL_CFG0);
sys/arch/evbmips/sbmips/cpu.c
107
plldiv = G_SYS_PLL_DIV(READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_CFG)));
sys/arch/evbmips/sbmips/cpu.c
81
part = G_SYS_PART(READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_REVISION)));
sys/arch/evbmips/sbmips/machdep.c
416
(void *)MIPS_PHYS_TO_KSEG1(SWARM_LEDS_PHYS);
sys/arch/evbmips/sbmips/rtc.c
420
#define READ_REG(rp) mips3_ld((register_t)(MIPS_PHYS_TO_KSEG1(rp)))
sys/arch/evbmips/sbmips/rtc.c
421
#define WRITE_REG(rp, val) mips3_sd((register_t)(MIPS_PHYS_TO_KSEG1(rp)), (val))
sys/arch/evbmips/sbmips/sb1250_icu.c
211
MIPS_PHYS_TO_KSEG1(A_IMR_MAPPER(cpu->sb1cpu_ci->ci_cpuid));
sys/arch/evbmips/sbmips/sb1250_icu.c
268
u_int sys_part = G_SYS_PART(READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_REVISION)));
sys/arch/evbmips/sbmips/sb1250_icu.c
275
vaddr_t imr = MIPS_PHYS_TO_KSEG1(A_IMR_CPU0_BASE + R_IMR_INTERRUPT_MASK);
sys/arch/evbmips/sbmips/sb1250_icu.c
280
WRITE_REG(MIPS_PHYS_TO_KSEG1(A_IMR_CPU0_BASE + R_IMR_INTERRUPT_MASK),
sys/arch/ews4800mips/ews4800mips/bus_dma.c
584
*kvap = (void *)MIPS_PHYS_TO_KSEG1(segs[0].ds_addr);
sys/arch/ews4800mips/ews4800mips/sbd.c
167
m = (uint32_t *)MIPS_PHYS_TO_KSEG1(start);
sys/arch/ews4800mips/ews4800mips/sbd.c
168
mend = (uint32_t *)MIPS_PHYS_TO_KSEG1(start + size);
sys/arch/ews4800mips/sbd/if_iee_sbdio.c
92
(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(sa->sa_addr1);
sys/arch/ews4800mips/sbd/kbms_sbdio.c
149
base = (uint8_t *)MIPS_PHYS_TO_KSEG1(sa->sa_addr1);
sys/arch/ews4800mips/sbd/zs_sbdio.c
121
zs_addr = (void *)MIPS_PHYS_TO_KSEG1(sa->sa_addr1);
sys/arch/hpcmips/dev/m38813c.c
143
scc->scc_csh = MIPS_PHYS_TO_KSEG1(addr);
sys/arch/hpcmips/dev/mq200.c
124
MIPS_PHYS_TO_KSEG1(mips_ptob(mips_btop(sc->sc_baseaddr)));
sys/arch/hpcmips/dev/tc5165buf.c
167
scc->scc_csh = MIPS_PHYS_TO_KSEG1(addr);
sys/arch/hpcmips/hpcmips/bus_dma.c
580
*kvap = (void *)MIPS_PHYS_TO_KSEG1(segs[0].ds_addr);
sys/arch/hpcmips/hpcmips/bus_space.c
257
return cacheable ? MIPS_PHYS_TO_KSEG0(bpa) : MIPS_PHYS_TO_KSEG1(bpa);
sys/arch/hpcmips/isa/isa_machdep.c
294
addr = MIPS_PHYS_TO_KSEG1(i + port);
sys/arch/hpcmips/isa/isa_machdep.c
335
addr = MIPS_PHYS_TO_KSEG1(port_addr);
sys/arch/hpcmips/stand/lcboot/extern.h
84
(__REG_1(MIPS_PHYS_TO_KSEG1((u_int32_t) (base) + (off))) \
sys/arch/hpcmips/stand/lcboot/extern.h
87
(__REG_2(MIPS_PHYS_TO_KSEG1((u_int32_t) (base) + (off))) \
sys/arch/hpcmips/stand/lcboot/extern.h
90
(__REG_4(MIPS_PHYS_TO_KSEG1((u_int32_t) (base) + (off))) \
sys/arch/hpcmips/stand/lcboot/extern.h
94
(__REG_1(MIPS_PHYS_TO_KSEG1((u_int32_t) (base) + (off))))
sys/arch/hpcmips/stand/lcboot/extern.h
96
(__REG_2(MIPS_PHYS_TO_KSEG1((u_int32_t) (base) + (off))))
sys/arch/hpcmips/stand/lcboot/extern.h
98
(__REG_4(MIPS_PHYS_TO_KSEG1((u_int32_t) (base) + (off))))
sys/arch/hpcmips/tx/tx39.c
188
startaddr = (char *)MIPS_PHYS_TO_KSEG1(start);
sys/arch/hpcmips/tx/tx39.c
189
endaddr = (char *)MIPS_PHYS_TO_KSEG1(end);
sys/arch/hpcmips/tx/tx3912video.c
242
vaddr_t fbvaddr = (vaddr_t)MIPS_PHYS_TO_KSEG1(chip->vc_fbpaddr);
sys/arch/hpcmips/tx/tx3912video.c
351
bootinfo->fb_addr = (void *)MIPS_PHYS_TO_KSEG1(chip->vc_fbpaddr);
sys/arch/hpcmips/tx/tx3912video.c
386
chip->vc_fbvaddr = MIPS_PHYS_TO_KSEG1(addr);
sys/arch/hpcmips/tx/tx3912video.c
431
vaddr = MIPS_PHYS_TO_KSEG1(fb_addr);
sys/arch/hpcmips/vr/bcu_vrip.c
343
revreg = (u_int16_t *)MIPS_PHYS_TO_KSEG1
sys/arch/hpcmips/vr/bcu_vrip.c
346
revreg = (u_int16_t *)MIPS_PHYS_TO_KSEG1
sys/arch/hpcmips/vr/bcu_vrip.c
381
revreg = (u_int16_t *)MIPS_PHYS_TO_KSEG1
sys/arch/hpcmips/vr/bcu_vrip.c
398
revreg = (u_int16_t *)MIPS_PHYS_TO_KSEG1
sys/arch/hpcmips/vr/bcu_vrip.c
418
clksp = *(u_int16_t *)MIPS_PHYS_TO_KSEG1
sys/arch/hpcmips/vr/bcu_vrip.c
422
clksp = *(u_int16_t *)MIPS_PHYS_TO_KSEG1
sys/arch/hpcmips/vr/vr.c
347
page = (char *)MIPS_PHYS_TO_KSEG1(addr);
sys/arch/hpcmips/vr/vrdsu.c
109
memset((void *)MIPS_PHYS_TO_KSEG1(0), 0, ptoa(physmem) - 0);
sys/arch/mips/adm5120/adm5120_intr.c
158
#define REG_READ(o) *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(ADM5120_BASE_ICU + (o)))
sys/arch/mips/adm5120/include/adm5120reg.h
124
#define _REG_READ(b, o) *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((b) + (o)))
sys/arch/mips/alchemy/au_icu.c
88
#define REGVAL(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x))))
sys/arch/mips/alchemy/dev/augpio.c
73
(*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(x))
sys/arch/mips/alchemy/dev/augpio.c
75
((*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(x)) = (v))
sys/arch/mips/alchemy/dev/aurtc.c
87
#define REGVAL(x) (*(volatile uint32_t *)(MIPS_PHYS_TO_KSEG1(PC_BASE + (x))))
sys/arch/mips/atheros/ar5312_board.c
124
MIPS_PHYS_TO_KSEG1(AR5312_FLASH_END-0x1000);
sys/arch/mips/atheros/ar5312_board.c
132
if (end == (uint8_t *) MIPS_PHYS_TO_KSEG1(AR5312_FLASH_END)) {
sys/arch/mips/atheros/ar5312_board.c
136
MIPS_PHYS_TO_KSEG1(AR5312_FLASH_END-0x1000 + 0xf8);
sys/arch/mips/atheros/ar5312_board.c
94
ptr = (const uint8_t *) MIPS_PHYS_TO_KSEG1(AR5312_FLASH_END - 0x1000);
sys/arch/mips/atheros/ar5315.c
83
#define REGVAL(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x))))
sys/arch/mips/atheros/ar5315_board.c
124
end = (const uint8_t *)MIPS_PHYS_TO_KSEG1(AR5315_RADIO_END);
sys/arch/mips/atheros/ar5315_board.c
93
ptr = (const uint8_t *) MIPS_PHYS_TO_KSEG1(AR5315_CONFIG_END
sys/arch/mips/atheros/ar_conf.c
183
MIPS_PHYS_TO_KSEG1(apsw->apsw_revision_id_addr);
sys/arch/mips/atheros/ar_console.c
108
(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(platformsw->apsw_uart0_base);
sys/arch/mips/atheros/ar_console.c
84
(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(platformsw->apsw_uart0_base);
sys/arch/mips/atheros/ar_console.c
96
(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(platformsw->apsw_uart0_base);
sys/arch/mips/atheros/ar_intr.c
58
#define REGVAL(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x))))
sys/arch/mips/atheros/dev/ehci_arbus.c
80
if (badaddr((void *)MIPS_PHYS_TO_KSEG1(aa->aa_addr), 4))
sys/arch/mips/atheros/include/ar5312reg.h
172
#define REGVAL(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x))))
sys/arch/mips/atheros/include/ar9344reg.h
346
#define REGVAL(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x))))
sys/arch/mips/bonito/bonitoreg.h
30
#define REGVAL(x) *((volatile u_int32_t *) MIPS_PHYS_TO_KSEG1(x))
sys/arch/mips/bonito/bonitoreg.h
31
#define REGVAL8(x) *((volatile u_int8_t *)MIPS_PHYS_TO_KSEG1(x))
sys/arch/mips/include/cpuregs.h
468
#define MIPS_RESET_EXC_VEC MIPS_PHYS_TO_KSEG1(0x1FC00000)
sys/arch/mips/ingenic/ingenic_com.c
100
com0addr = (uint32_t *)MIPS_PHYS_TO_KSEG1(JZ_UART0);
sys/arch/mips/ingenic/ingenic_com.c
51
volatile int32_t *com0addr = (int32_t *)MIPS_PHYS_TO_KSEG1(JZ_UART0);
sys/arch/mips/ingenic/ingenic_regs.h
121
*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(reg) = val;
sys/arch/mips/ingenic/ingenic_regs.h
129
return *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(reg);
sys/arch/mips/mips/bus_dma.c
1129
*kvap = (void *)MIPS_PHYS_TO_KSEG1(segs[0].ds_addr);
sys/arch/mips/mips/bus_dma.c
693
kva = (void *)MIPS_PHYS_TO_KSEG1(segs->ds_addr);
sys/arch/mips/mips/bus_space_alignstride_chipdep.c
386
*hp = (intptr_t)MIPS_PHYS_TO_KSEG1(addr);
sys/arch/mips/mips/bus_space_alignstride_chipdep.c
422
*hp = (intptr_t)MIPS_PHYS_TO_KSEG1(addr);
sys/arch/mips/mips/bus_space_alignstride_chipdep.c
624
*bshp = MIPS_PHYS_TO_KSEG1(mbst.mbst_sys_start +
sys/arch/mips/mips/cache_r5k.c
255
(void) *(volatile int *)MIPS_PHYS_TO_KSEG1(0);
sys/arch/mips/mips/cache_r5k.c
259
(void) *(volatile int *)MIPS_PHYS_TO_KSEG1(0);
sys/arch/mips/mips/cache_r5k.c
329
(void) *(volatile int *)MIPS_PHYS_TO_KSEG1(0);
sys/arch/mips/mips/cache_r5k.c
334
(void) *(volatile int *)MIPS_PHYS_TO_KSEG1(0);
sys/arch/mips/mips/cache_r5k.c
385
(void) *(volatile int *)MIPS_PHYS_TO_KSEG1(0);
sys/arch/mips/mips/cache_r5k.c
390
(void) *(volatile int *)MIPS_PHYS_TO_KSEG1(0);
sys/arch/mips/mips/pmap_machdep.c
146
CTASSERT((intptr_t)MIPS_PHYS_TO_KSEG1(0x1000) < 0);
sys/arch/mips/mips/pmap_machdep.c
156
CTASSERT(MIPS_KSEG1_P(MIPS_PHYS_TO_KSEG1(0)));
sys/arch/mips/ralink/ralink_reg.h
134
(volatile uint32_t *)MIPS_PHYS_TO_KSEG1((base) + (offset))
sys/arch/mips/rmi/rmixl_com.c
143
MIPS_PHYS_TO_KSEG1(RMIXL_IO_DEV_PBASE + RMIXL_IO_DEV_UART_1);
sys/arch/mips/rmi/rmixl_com.c
155
MIPS_PHYS_TO_KSEG1(io_pbase + RMIXL_IO_DEV_UART_1);
sys/arch/mips/rmi/rmixl_pcix.c
184
(volatile uint32_t *)MIPS_PHYS_TO_KSEG1( \
sys/arch/mips/rmi/rmixl_usbi.c
59
(volatile uint32_t *)MIPS_PHYS_TO_KSEG1( \
sys/arch/mips/rmi/rmixlreg.h
212
#define RMIXL_IO_DEV_VBASE MIPS_PHYS_TO_KSEG1(RMIXL_IO_DEV_PBASE)
sys/arch/mips/rmi/rmixlreg.h
47
(volatile uint32_t *)MIPS_PHYS_TO_KSEG1( \
sys/arch/mips/sibyte/dev/sbbuswatch.c
51
(void)READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_BUS_ERR_STATUS));
sys/arch/mips/sibyte/dev/sbbuswatch.c
52
WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_L2_ERRORS), 0);
sys/arch/mips/sibyte/dev/sbbuswatch.c
53
WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_MEM_IO_ERRORS), 0);
sys/arch/mips/sibyte/dev/sbbuswatch.c
76
MIPS_PHYS_TO_KSEG1(A_SCD_BUS_ERR_STATUS));
sys/arch/mips/sibyte/dev/sbbuswatch.c
82
MIPS_PHYS_TO_KSEG1(A_BUS_L2_ERRORS));
sys/arch/mips/sibyte/dev/sbbuswatch.c
84
WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_L2_ERRORS), 0);
sys/arch/mips/sibyte/dev/sbbuswatch.c
87
MIPS_PHYS_TO_KSEG1(A_BUS_MEM_IO_ERRORS));
sys/arch/mips/sibyte/dev/sbbuswatch.c
89
WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_MEM_IO_ERRORS), 0);
sys/arch/mips/sibyte/dev/sbgbus.c
137
rv = mips3_ld((volatile uint64_t *)MIPS_PHYS_TO_KSEG1(
sys/arch/mips/sibyte/dev/sbgbus.c
141
rv = mips3_ld((volatile uint64_t *)MIPS_PHYS_TO_KSEG1(
sys/arch/mips/sibyte/dev/sbjcn.c
1515
while ((ctrl_val = READ_REG(MIPS_PHYS_TO_KSEG1(sbjcn_cons_addr + JTAG_CONS_CONTROL))) == 0)
sys/arch/mips/sibyte/dev/sbjcn.c
1545
WRITE_REG(MIPS_PHYS_TO_KSEG1(sbjcn_cons_addr + JTAG_CONS_OUTPUT), outbuf);
sys/arch/mips/sibyte/dev/sbjcn.c
1561
inbuf = READ_REG(MIPS_PHYS_TO_KSEG1(sbjcn_cons_addr + JTAG_CONS_INPUT));
sys/arch/mips/sibyte/dev/sbjcn.c
284
ch->ch_base = (void *)MIPS_PHYS_TO_KSEG1(chan_addr);
sys/arch/mips/sibyte/dev/sbjcn.c
286
(void *)MIPS_PHYS_TO_KSEG1(sc->sc_addr + JTAG_CONS_INPUT);
sys/arch/mips/sibyte/dev/sbjcn.c
288
(void *)MIPS_PHYS_TO_KSEG1(sc->sc_addr + JTAG_CONS_OUTPUT);
sys/arch/mips/sibyte/dev/sbjcn.c
290
(void *)MIPS_PHYS_TO_KSEG1(sc->sc_addr + JTAG_CONS_CONTROL);
sys/arch/mips/sibyte/dev/sbmac.c
118
#define PKSEG1(x) ((sbmac_port_t) MIPS_PHYS_TO_KSEG1(x))
sys/arch/mips/sibyte/dev/sbobio.c
183
sysrev = mips3_ld((register_t)MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_REVISION));
sys/arch/mips/sibyte/dev/sbobio.c
208
sysrev = mips3_ld((register_t)MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_REVISION));
sys/arch/mips/sibyte/dev/sbscn.c
1684
u_long base = MIPS_PHYS_TO_KSEG1(addr + (chan * 0x100));
sys/arch/mips/sibyte/dev/sbscn.c
1701
u_long base = MIPS_PHYS_TO_KSEG1(addr + (chan * 0x100));
sys/arch/mips/sibyte/dev/sbscn.c
1725
u_long chanregbase = MIPS_PHYS_TO_KSEG1(addr + (chan * 0x100));
sys/arch/mips/sibyte/dev/sbscn.c
1726
u_long imaskreg = MIPS_PHYS_TO_KSEG1(addr + 0x230 + (chan * 0x20));
sys/arch/mips/sibyte/dev/sbscn.c
255
((~READ_REG(MIPS_PHYS_TO_KSEG1((ch)->ch_sc->sc_addr + 0x280))) & (ch)->ch_i_mask)
sys/arch/mips/sibyte/dev/sbscn.c
264
WRITE_REG(MIPS_PHYS_TO_KSEG1((ch)->ch_sc->sc_addr + 0x2c0), \
sys/arch/mips/sibyte/dev/sbscn.c
266
WRITE_REG(MIPS_PHYS_TO_KSEG1((ch)->ch_sc->sc_addr + 0x2b0), \
sys/arch/mips/sibyte/dev/sbscn.c
296
WRITE_REG(MIPS_PHYS_TO_KSEG1(sc->sc_addr + 0x270), 0);
sys/arch/mips/sibyte/dev/sbscn.c
298
WRITE_REG(MIPS_PHYS_TO_KSEG1(sc->sc_addr + 0x210), 0x0f); /* XXX */
sys/arch/mips/sibyte/dev/sbscn.c
312
ch->ch_base = (void *)MIPS_PHYS_TO_KSEG1(chan_addr);
sys/arch/mips/sibyte/dev/sbscn.c
314
(void *)MIPS_PHYS_TO_KSEG1(sc->sc_addr + 0x220 + (0x20 * chan));
sys/arch/mips/sibyte/dev/sbscn.c
316
(void *)MIPS_PHYS_TO_KSEG1(sc->sc_addr + 0x230 + (0x20 * chan));
sys/arch/mips/sibyte/dev/sbscn.c
319
(void *)MIPS_PHYS_TO_KSEG1(sc->sc_addr + 0x2d0 + (0x10 * chan));
sys/arch/mips/sibyte/dev/sbtimer.c
101
sc->sc_addr_cnt = (uint64_t *)MIPS_PHYS_TO_KSEG1(sa->sa_base +
sys/arch/mips/sibyte/dev/sbtimer.c
103
sc->sc_addr_cfg = (uint64_t *)MIPS_PHYS_TO_KSEG1(sa->sa_base +
sys/arch/mips/sibyte/dev/sbtimer.c
160
if (G_SYS_PLL_DIV(READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_CFG))) == 0) {
sys/arch/mips/sibyte/dev/sbtimer.c
99
sc->sc_addr_icnt = (uint64_t *)MIPS_PHYS_TO_KSEG1(sa->sa_base +
sys/arch/mips/sibyte/dev/sbwdog.c
103
sc->sc_addr = MIPS_PHYS_TO_KSEG1(sa->sa_base + sa->sa_locs.sa_offset);
sys/arch/mips/sibyte/pci/sbbrz.c
177
regval = mips3_ld((register_t)MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_CFG));
sys/arch/mips/sibyte/pci/sbbrz_pci.c
150
regval = mips3_ld((register_t)MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_CFG));
sys/arch/mipsco/isa/isa_machdep.c
85
vaddr_t vaddr = MIPS_PHYS_TO_KSEG1(paddr); /* XXX */
sys/arch/mipsco/mipsco/bus_dma.c
544
*kvap = (void *)MIPS_PHYS_TO_KSEG1(segs[0].ds_addr);
sys/arch/mipsco/mipsco/machdep.c
468
vp = (int *)MIPS_PHYS_TO_KSEG1(mem << PGSHIFT);
sys/arch/mipsco/mipsco/machdep.c
469
vp0 = (int *)MIPS_PHYS_TO_KSEG1(0); /* Start of physical memory */
sys/arch/mipsco/obio/if_le.c
194
sc->sc_mem = (void *)MIPS_PHYS_TO_KSEG1(kvaddr);
sys/arch/newsmips/apbus/xafb.c
162
dc->dc_fbbase = (void *)MIPS_PHYS_TO_KSEG1(dc->dc_fbpaddr);
sys/arch/newsmips/apbus/xafb.c
351
dc->dc_fbbase = (void *)MIPS_PHYS_TO_KSEG1(dc->dc_fbpaddr);
sys/arch/newsmips/newsmips/bus.c
743
*kvap = (void *)MIPS_PHYS_TO_KSEG1(segs[0].ds_addr);
sys/arch/newsmips/newsmips/bus.c
98
*bshp = MIPS_PHYS_TO_KSEG1(bpa);
sys/arch/newsmips/newsmips/machdep.c
242
*(int *)(MIPS_PHYS_TO_KSEG1(MACH_MAXMEMSIZE_ADDR)) = x_maxmem;
sys/arch/newsmips/newsmips/machdep.c
243
*(int *)(MIPS_PHYS_TO_KSEG1(MACH_BOOTDEV_ADDR)) = x_bootdev;
sys/arch/newsmips/newsmips/machdep.c
244
*(int *)(MIPS_PHYS_TO_KSEG1(MACH_BOOTSW_ADDR)) = x_boothowto;
sys/arch/playstation2/dev/emac3.c
75
#define EMAC3_BASE MIPS_PHYS_TO_KSEG1(0x14002000)
sys/arch/playstation2/dev/if_smapreg.h
51
#define SMAP_TXFIFO_CTRL_REG8 MIPS_PHYS_TO_KSEG1(0x14001000)
sys/arch/playstation2/dev/if_smapreg.h
52
#define SMAP_TXFIFO_PTR_REG16 MIPS_PHYS_TO_KSEG1(0x14001004)
sys/arch/playstation2/dev/if_smapreg.h
53
#define SMAP_TXFIFO_FRAME_REG8 MIPS_PHYS_TO_KSEG1(0x1400100c)
sys/arch/playstation2/dev/if_smapreg.h
54
#define SMAP_TXFIFO_FRAME_INC_REG8 MIPS_PHYS_TO_KSEG1(0x14001010)
sys/arch/playstation2/dev/if_smapreg.h
55
#define SMAP_TXFIFO_DATA_REG MIPS_PHYS_TO_KSEG1(0x14001100)
sys/arch/playstation2/dev/if_smapreg.h
56
#define SMAP_RXFIFO_CTRL_REG8 MIPS_PHYS_TO_KSEG1(0x14001030)
sys/arch/playstation2/dev/if_smapreg.h
57
#define SMAP_RXFIFO_PTR_REG16 MIPS_PHYS_TO_KSEG1(0x14001034)
sys/arch/playstation2/dev/if_smapreg.h
58
#define SMAP_RXFIFO_FRAME_REG8 MIPS_PHYS_TO_KSEG1(0x1400103c)
sys/arch/playstation2/dev/if_smapreg.h
59
#define SMAP_RXFIFO_FRAME_DEC_REG8 MIPS_PHYS_TO_KSEG1(0x14001040)
sys/arch/playstation2/dev/if_smapreg.h
60
#define SMAP_RXFIFO_DATA_REG MIPS_PHYS_TO_KSEG1(0x14001200)
sys/arch/playstation2/dev/if_smapreg.h
66
#define SMAP_DESC_MODE_REG8 MIPS_PHYS_TO_KSEG1(0x14000102)
sys/arch/playstation2/dev/if_smapreg.h
69
#define SMAP_TXDESC_BASE MIPS_PHYS_TO_KSEG1(0x14003000)
sys/arch/playstation2/dev/if_smapreg.h
70
#define SMAP_RXDESC_BASE MIPS_PHYS_TO_KSEG1(0x14003200)
sys/arch/playstation2/dev/ohci_sbus.c
66
#define SBUS_OHCI_REGBASE MIPS_PHYS_TO_KSEG1(0x1f801600)
sys/arch/playstation2/dev/sbusreg.h
32
#define SBUS_SMFLG_REG MIPS_PHYS_TO_KSEG1(0x1000f230)
sys/arch/playstation2/dev/sbusreg.h
36
#define SBUS_AIF_INTSR_REG16 MIPS_PHYS_TO_KSEG1(0x18000004)
sys/arch/playstation2/dev/sbusreg.h
37
#define SBUS_AIF_INTEN_REG16 MIPS_PHYS_TO_KSEG1(0x18000006)
sys/arch/playstation2/dev/sbusreg.h
39
#define SBUS_PCMCIA_EXC1_REG16 MIPS_PHYS_TO_KSEG1(0x1f801476)
sys/arch/playstation2/dev/sbusreg.h
40
#define SBUS_PCMCIA_CSC1_REG16 MIPS_PHYS_TO_KSEG1(0x1f801464)
sys/arch/playstation2/dev/sbusreg.h
41
#define SBUS_PCMCIA_IMR1_REG16 MIPS_PHYS_TO_KSEG1(0x1f801468)
sys/arch/playstation2/dev/sbusreg.h
42
#define SBUS_PCMCIA_TIMR_REG16 MIPS_PHYS_TO_KSEG1(0x1f80147e)
sys/arch/playstation2/dev/sbusreg.h
43
#define SBUS_PCMCIA3_TIMR_REG16 MIPS_PHYS_TO_KSEG1(0x1f801466)
sys/arch/playstation2/dev/spdreg.h
37
#define SPD_INTR_ENABLE_REG16 MIPS_PHYS_TO_KSEG1(0x1400002a)
sys/arch/playstation2/dev/spdreg.h
38
#define SPD_INTR_STATUS_REG16 MIPS_PHYS_TO_KSEG1(0x14000028)
sys/arch/playstation2/dev/spdreg.h
39
#define SPD_INTR_CLEAR_REG16 MIPS_PHYS_TO_KSEG1(0x14000128)
sys/arch/playstation2/dev/spdreg.h
48
#define SPD_IO_DIR_REG8 MIPS_PHYS_TO_KSEG1(0x1400002c)
sys/arch/playstation2/dev/spdreg.h
49
#define SPD_IO_DATA_REG8 MIPS_PHYS_TO_KSEG1(0x1400002e)
sys/arch/playstation2/dev/spdreg.h
59
#define SPD_XFR_CTRL_REG8 MIPS_PHYS_TO_KSEG1(0x14000032)
sys/arch/playstation2/dev/spdreg.h
60
#define SPD_HDD_IO_BASE MIPS_PHYS_TO_KSEG1(0x14000040)
sys/arch/playstation2/dev/spdreg.h
61
#define SPD_IF_CTRL_REG8 MIPS_PHYS_TO_KSEG1(0x14000064)
sys/arch/playstation2/ee/dmacreg.h
100
#define D0_MADR_REG MIPS_PHYS_TO_KSEG1(0x10008010)
sys/arch/playstation2/ee/dmacreg.h
101
#define D0_QWC_REG MIPS_PHYS_TO_KSEG1(0x10008020)
sys/arch/playstation2/ee/dmacreg.h
102
#define D0_TADR_REG MIPS_PHYS_TO_KSEG1(0x10008030)
sys/arch/playstation2/ee/dmacreg.h
103
#define D0_ASR0_REG MIPS_PHYS_TO_KSEG1(0x10008040)
sys/arch/playstation2/ee/dmacreg.h
104
#define D0_ASR1_REG MIPS_PHYS_TO_KSEG1(0x10008050)
sys/arch/playstation2/ee/dmacreg.h
106
#define D1_CHCR_REG MIPS_PHYS_TO_KSEG1(0x10009000)
sys/arch/playstation2/ee/dmacreg.h
107
#define D1_MADR_REG MIPS_PHYS_TO_KSEG1(0x10009010)
sys/arch/playstation2/ee/dmacreg.h
108
#define D1_QWC_REG MIPS_PHYS_TO_KSEG1(0x10009020)
sys/arch/playstation2/ee/dmacreg.h
109
#define D1_TADR_REG MIPS_PHYS_TO_KSEG1(0x10009030)
sys/arch/playstation2/ee/dmacreg.h
110
#define D1_ASR0_REG MIPS_PHYS_TO_KSEG1(0x10009040)
sys/arch/playstation2/ee/dmacreg.h
111
#define D1_ASR1_REG MIPS_PHYS_TO_KSEG1(0x10009050)
sys/arch/playstation2/ee/dmacreg.h
113
#define D2_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000a000)
sys/arch/playstation2/ee/dmacreg.h
114
#define D2_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000a010)
sys/arch/playstation2/ee/dmacreg.h
115
#define D2_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000a020)
sys/arch/playstation2/ee/dmacreg.h
116
#define D2_TADR_REG MIPS_PHYS_TO_KSEG1(0x1000a030)
sys/arch/playstation2/ee/dmacreg.h
117
#define D2_ASR0_REG MIPS_PHYS_TO_KSEG1(0x1000a040)
sys/arch/playstation2/ee/dmacreg.h
118
#define D2_ASR1_REG MIPS_PHYS_TO_KSEG1(0x1000a050)
sys/arch/playstation2/ee/dmacreg.h
120
#define D3_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000b000)
sys/arch/playstation2/ee/dmacreg.h
121
#define D3_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000b010)
sys/arch/playstation2/ee/dmacreg.h
122
#define D3_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000b020)
sys/arch/playstation2/ee/dmacreg.h
124
#define D4_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000b400)
sys/arch/playstation2/ee/dmacreg.h
125
#define D4_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000b410)
sys/arch/playstation2/ee/dmacreg.h
126
#define D4_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000b420)
sys/arch/playstation2/ee/dmacreg.h
127
#define D4_TADR_REG MIPS_PHYS_TO_KSEG1(0x1000b430)
sys/arch/playstation2/ee/dmacreg.h
129
#define D5_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000c000)
sys/arch/playstation2/ee/dmacreg.h
130
#define D5_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000c010)
sys/arch/playstation2/ee/dmacreg.h
131
#define D5_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000c020)
sys/arch/playstation2/ee/dmacreg.h
133
#define D6_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000c400)
sys/arch/playstation2/ee/dmacreg.h
134
#define D6_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000c410)
sys/arch/playstation2/ee/dmacreg.h
135
#define D6_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000c420)
sys/arch/playstation2/ee/dmacreg.h
136
#define D6_TADR_REG MIPS_PHYS_TO_KSEG1(0x1000c430)
sys/arch/playstation2/ee/dmacreg.h
138
#define D7_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000c800)
sys/arch/playstation2/ee/dmacreg.h
139
#define D7_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000c810)
sys/arch/playstation2/ee/dmacreg.h
140
#define D7_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000c820)
sys/arch/playstation2/ee/dmacreg.h
142
#define D8_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000d000)
sys/arch/playstation2/ee/dmacreg.h
143
#define D8_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000d010)
sys/arch/playstation2/ee/dmacreg.h
144
#define D8_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000d020)
sys/arch/playstation2/ee/dmacreg.h
145
#define D8_SADR_REG MIPS_PHYS_TO_KSEG1(0x1000d080)
sys/arch/playstation2/ee/dmacreg.h
147
#define D9_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000d400)
sys/arch/playstation2/ee/dmacreg.h
148
#define D9_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000d410)
sys/arch/playstation2/ee/dmacreg.h
149
#define D9_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000d420)
sys/arch/playstation2/ee/dmacreg.h
150
#define D9_TADR_REG MIPS_PHYS_TO_KSEG1(0x1000d430)
sys/arch/playstation2/ee/dmacreg.h
151
#define D9_SADR_REG MIPS_PHYS_TO_KSEG1(0x1000d480)
sys/arch/playstation2/ee/dmacreg.h
41
#define DMAC_REGBASE MIPS_PHYS_TO_KSEG1(0x10008000)
sys/arch/playstation2/ee/dmacreg.h
47
#define D_CTRL_REG MIPS_PHYS_TO_KSEG1(0x1000e000) /* DMA control */
sys/arch/playstation2/ee/dmacreg.h
48
#define D_STAT_REG MIPS_PHYS_TO_KSEG1(0x1000e010) /* interrupt status */
sys/arch/playstation2/ee/dmacreg.h
49
#define D_PCR_REG MIPS_PHYS_TO_KSEG1(0x1000e020) /* priority control */
sys/arch/playstation2/ee/dmacreg.h
50
#define D_SQWC_REG MIPS_PHYS_TO_KSEG1(0x1000e030) /* interleave size */
sys/arch/playstation2/ee/dmacreg.h
51
#define D_RBOR_REG MIPS_PHYS_TO_KSEG1(0x1000e040) /* ring buffer addr */
sys/arch/playstation2/ee/dmacreg.h
52
#define D_RBSR_REG MIPS_PHYS_TO_KSEG1(0x1000e050) /* ring buffer size */
sys/arch/playstation2/ee/dmacreg.h
53
#define D_STADR_REG MIPS_PHYS_TO_KSEG1(0x1000e060) /* stall address */
sys/arch/playstation2/ee/dmacreg.h
54
#define D_ENABLER_REG MIPS_PHYS_TO_KSEG1(0x1000f520) /* DMA enable (r) */
sys/arch/playstation2/ee/dmacreg.h
55
#define D_ENABLEW_REG MIPS_PHYS_TO_KSEG1(0x1000f590) /* DMA enable (w) */
sys/arch/playstation2/ee/dmacreg.h
80
#define D0_REGBASE MIPS_PHYS_TO_KSEG1(0x10008000)
sys/arch/playstation2/ee/dmacreg.h
81
#define D1_REGBASE MIPS_PHYS_TO_KSEG1(0x10009000)
sys/arch/playstation2/ee/dmacreg.h
82
#define D2_REGBASE MIPS_PHYS_TO_KSEG1(0x1000a000)
sys/arch/playstation2/ee/dmacreg.h
83
#define D3_REGBASE MIPS_PHYS_TO_KSEG1(0x1000b000)
sys/arch/playstation2/ee/dmacreg.h
84
#define D4_REGBASE MIPS_PHYS_TO_KSEG1(0x1000b400)
sys/arch/playstation2/ee/dmacreg.h
85
#define D5_REGBASE MIPS_PHYS_TO_KSEG1(0x1000c000)
sys/arch/playstation2/ee/dmacreg.h
86
#define D6_REGBASE MIPS_PHYS_TO_KSEG1(0x1000c400)
sys/arch/playstation2/ee/dmacreg.h
87
#define D7_REGBASE MIPS_PHYS_TO_KSEG1(0x1000c800)
sys/arch/playstation2/ee/dmacreg.h
88
#define D8_REGBASE MIPS_PHYS_TO_KSEG1(0x1000d000)
sys/arch/playstation2/ee/dmacreg.h
89
#define D9_REGBASE MIPS_PHYS_TO_KSEG1(0x1000d400)
sys/arch/playstation2/ee/dmacreg.h
99
#define D0_CHCR_REG MIPS_PHYS_TO_KSEG1(0x10008000)
sys/arch/playstation2/ee/gifreg.h
32
#define GIF_CTRL_REG MIPS_PHYS_TO_KSEG1(0x10003000)
sys/arch/playstation2/ee/gsfb.c
320
u_int32_t *buf = (void *)MIPS_PHYS_TO_KSEG1(paddr);
sys/arch/playstation2/ee/gsfb.c
393
u_int32_t *buf = (void *)MIPS_PHYS_TO_KSEG1(paddr);
sys/arch/playstation2/ee/gsfb.c
437
u_int32_t *buf = (void *)MIPS_PHYS_TO_KSEG1(paddr);
sys/arch/playstation2/ee/gsfb.c
455
u_int32_t *cmd = (void *)MIPS_PHYS_TO_KSEG1(paddr);
sys/arch/playstation2/ee/gsfb.c
487
u_int32_t *cmd = (void *)MIPS_PHYS_TO_KSEG1(paddr);
sys/arch/playstation2/ee/gsreg.h
32
#define GS_S_PMODE_REG MIPS_PHYS_TO_KSEG1(0x12000000)
sys/arch/playstation2/ee/gsreg.h
33
#define GS_S_SMODE1_REG MIPS_PHYS_TO_KSEG1(0x12000010)
sys/arch/playstation2/ee/gsreg.h
34
#define GS_S_SMODE2_REG MIPS_PHYS_TO_KSEG1(0x12000020)
sys/arch/playstation2/ee/gsreg.h
35
#define GS_S_SRFSH_REG MIPS_PHYS_TO_KSEG1(0x12000030)
sys/arch/playstation2/ee/gsreg.h
36
#define GS_S_SYNCH1_REG MIPS_PHYS_TO_KSEG1(0x12000040)
sys/arch/playstation2/ee/gsreg.h
37
#define GS_S_SYNCH2_REG MIPS_PHYS_TO_KSEG1(0x12000050)
sys/arch/playstation2/ee/gsreg.h
38
#define GS_S_SYNCV_REG MIPS_PHYS_TO_KSEG1(0x12000060)
sys/arch/playstation2/ee/gsreg.h
39
#define GS_S_DISPFB1_REG MIPS_PHYS_TO_KSEG1(0x12000070)
sys/arch/playstation2/ee/gsreg.h
40
#define GS_S_DISPLAY1_REG MIPS_PHYS_TO_KSEG1(0x12000080)
sys/arch/playstation2/ee/gsreg.h
41
#define GS_S_DISPFB2_REG MIPS_PHYS_TO_KSEG1(0x12000090)
sys/arch/playstation2/ee/gsreg.h
42
#define GS_S_DISPLAY2_REG MIPS_PHYS_TO_KSEG1(0x120000a0)
sys/arch/playstation2/ee/gsreg.h
43
#define GS_S_EXTBUF_REG MIPS_PHYS_TO_KSEG1(0x120000b0)
sys/arch/playstation2/ee/gsreg.h
44
#define GS_S_EXTDATA_REG MIPS_PHYS_TO_KSEG1(0x120000c0)
sys/arch/playstation2/ee/gsreg.h
45
#define GS_S_EXTWRITE_REG MIPS_PHYS_TO_KSEG1(0x120000d0)
sys/arch/playstation2/ee/gsreg.h
46
#define GS_S_BGCOLOR_REG MIPS_PHYS_TO_KSEG1(0x120000e0)
sys/arch/playstation2/ee/gsreg.h
47
#define GS_S_CSR_REG MIPS_PHYS_TO_KSEG1(0x12001000)
sys/arch/playstation2/ee/gsreg.h
48
#define GS_S_IMR_REG MIPS_PHYS_TO_KSEG1(0x12001010)
sys/arch/playstation2/ee/gsreg.h
49
#define GS_S_BUSDIR_REG MIPS_PHYS_TO_KSEG1(0x12001040)
sys/arch/playstation2/ee/gsreg.h
50
#define GS_S_SIGLBLID_REG MIPS_PHYS_TO_KSEG1(0x12001080)
sys/arch/playstation2/ee/intcreg.h
32
#define I_STAT_REG MIPS_PHYS_TO_KSEG1(0x1000f000)
sys/arch/playstation2/ee/intcreg.h
33
#define I_MASK_REG MIPS_PHYS_TO_KSEG1(0x1000f010)
sys/arch/playstation2/ee/timerreg.h
47
#define T_COUNT_REG(x) MIPS_PHYS_TO_KSEG1((TIMER_REGBASE + TIMER_OFS * (x)))
sys/arch/playstation2/ee/timerreg.h
48
#define T_MODE_REG(x) MIPS_PHYS_TO_KSEG1((TIMER_REGBASE + \
sys/arch/playstation2/ee/timerreg.h
50
#define T_COMP_REG(x) MIPS_PHYS_TO_KSEG1((TIMER_REGBASE + \
sys/arch/playstation2/ee/timerreg.h
58
#define T0_COUNT_REG MIPS_PHYS_TO_KSEG1(0x10000000)
sys/arch/playstation2/ee/timerreg.h
59
#define T0_MODE_REG MIPS_PHYS_TO_KSEG1(0x10000010)
sys/arch/playstation2/ee/timerreg.h
60
#define T0_COMP_REG MIPS_PHYS_TO_KSEG1(0x10000020)
sys/arch/playstation2/ee/timerreg.h
61
#define T0_HOLD_REG MIPS_PHYS_TO_KSEG1(0x10000030)
sys/arch/playstation2/ee/timerreg.h
62
#define T1_COUNT_REG MIPS_PHYS_TO_KSEG1(0x10000800)
sys/arch/playstation2/ee/timerreg.h
63
#define T1_MODE_REG MIPS_PHYS_TO_KSEG1(0x10000810)
sys/arch/playstation2/ee/timerreg.h
64
#define T1_COMP_REG MIPS_PHYS_TO_KSEG1(0x10000820)
sys/arch/playstation2/ee/timerreg.h
65
#define T1_HOLD_REG MIPS_PHYS_TO_KSEG1(0x10000830)
sys/arch/playstation2/ee/timerreg.h
66
#define T2_COUNT_REG MIPS_PHYS_TO_KSEG1(0x10001000)
sys/arch/playstation2/ee/timerreg.h
67
#define T2_MODE_REG MIPS_PHYS_TO_KSEG1(0x10001010)
sys/arch/playstation2/ee/timerreg.h
68
#define T2_COMP_REG MIPS_PHYS_TO_KSEG1(0x10001020)
sys/arch/playstation2/ee/timerreg.h
69
#define T3_COUNT_REG MIPS_PHYS_TO_KSEG1(0x10001800)
sys/arch/playstation2/ee/timerreg.h
70
#define T3_MODE_REG MIPS_PHYS_TO_KSEG1(0x10001810)
sys/arch/playstation2/ee/timerreg.h
71
#define T3_COMP_REG MIPS_PHYS_TO_KSEG1(0x10001820)
sys/arch/playstation2/include/bootinfo.h
43
(*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(BOOTINFO_BLOCK_BASE + (x)))
sys/arch/playstation2/playstation2/bus_dma.c
519
*kvap = (void *)MIPS_PHYS_TO_KSEG1(segs[0].ds_addr);
sys/arch/playstation2/playstation2/clock.c
82
(void *)MIPS_PHYS_TO_KSEG1(BOOTINFO_BLOCK_BASE + BOOTINFO_RTC);
sys/arch/playstation2/playstation2/machdep.c
130
memset((void *)MIPS_PHYS_TO_KSEG1(start), 0, size);
sys/arch/playstation2/playstation2/sifbios.c
52
#define SIFBIOS_SIGNATURE_PTR MIPS_PHYS_TO_KSEG1(0x00001004)
sys/arch/playstation2/playstation2/sifbios.h
39
#define SIFDMA_BASE MIPS_PHYS_TO_KSEG1(0x1c000000)
sys/arch/pmax/ibus/dz_ibus.c
172
sc->sc_ioh = (bus_space_handle_t)MIPS_PHYS_TO_KSEG1(iba->ia_addr);
sys/arch/pmax/ibus/dz_ibus.c
264
dzcn = (void *)MIPS_PHYS_TO_KSEG1(addr);
sys/arch/pmax/ibus/ibus_pmax.c
58
#define KV(x) MIPS_PHYS_TO_KSEG1(x)
sys/arch/pmax/ibus/if_le_ibus.c
82
sc->sc_mem = (void *)MIPS_PHYS_TO_KSEG1(KN01_SYS_LANCE_B_START);
sys/arch/pmax/ibus/if_le_ibus.c
83
cp = (uint8_t *)(MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK) + 1);
sys/arch/pmax/ibus/pm.c
207
mem = (void *)MIPS_PHYS_TO_KSEG1(KN01_PHYS_FBUF_START);
sys/arch/pmax/ibus/pm.c
268
kn01csr = *(volatile uint16_t *)MIPS_PHYS_TO_KSEG1(KN01_SYS_CSR);
sys/arch/pmax/ibus/pm.c
269
pcc = (void *)MIPS_PHYS_TO_KSEG1(KN01_SYS_PCC);
sys/arch/pmax/ibus/pm.c
270
vdac = (void *)MIPS_PHYS_TO_KSEG1(KN01_SYS_VDAC);
sys/arch/pmax/ibus/pm.c
280
ri->ri_bits = (void *)MIPS_PHYS_TO_KSEG1(KN01_PHYS_FBUF_START);
sys/arch/pmax/ibus/pm.c
327
*(uint8_t *)MIPS_PHYS_TO_KSEG1(KN01_PHYS_COLMASK_START) = 0xff;
sys/arch/pmax/ibus/pm.c
386
pcc = (void *)MIPS_PHYS_TO_KSEG1(KN01_SYS_PCC);
sys/arch/pmax/ibus/pm.c
397
pcc = (void *)MIPS_PHYS_TO_KSEG1(KN01_SYS_PCC);
sys/arch/pmax/ibus/pm.c
415
pcc = (void *)MIPS_PHYS_TO_KSEG1(KN01_SYS_PCC);
sys/arch/pmax/ibus/pm.c
416
vdac = (void *)MIPS_PHYS_TO_KSEG1(KN01_SYS_VDAC);
sys/arch/pmax/ibus/pm.c
589
vdac = (void *)MIPS_PHYS_TO_KSEG1(KN01_SYS_VDAC);
sys/arch/pmax/ibus/pm.c
590
pcc = (void *)MIPS_PHYS_TO_KSEG1(KN01_SYS_PCC);
sys/arch/pmax/ibus/sii_ds.c
67
#define SII_BUF_ADDR (MIPS_PHYS_TO_KSEG1(KN01_SYS_SII_B_START) \
sys/arch/pmax/ibus/sii_ds.c
94
sc->sc_regs = (SIIRegs *)MIPS_PHYS_TO_KSEG1(ia->ia_addr);
sys/arch/pmax/ibus/sii_ds.c
97
sc->sc_buf = (void*)(MIPS_PHYS_TO_KSEG1(KN01_SYS_SII_B_START));
sys/arch/pmax/include/tc_machdep.h
76
#define TC_PHYS_TO_UNCACHED(addr) MIPS_PHYS_TO_KSEG1(addr)
sys/arch/pmax/include/tc_machdep.h
85
#define KV(x) ((tc_addr_t)MIPS_PHYS_TO_KSEG1(x))
sys/arch/pmax/pmax/bus_dma.c
698
*kvap = (void *)MIPS_PHYS_TO_KSEG1(segs[0].ds_addr);
sys/arch/pmax/pmax/bus_space.c
55
*bshp = MIPS_PHYS_TO_KSEG1(bpa);
sys/arch/pmax/pmax/dec_3100.c
138
mc_cpuspeed(MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK), MIPS_INT_MASK_3);
sys/arch/pmax/pmax/dec_3100.c
205
"r"(MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK)));
sys/arch/pmax/pmax/dec_3100.c
241
csr = *(volatile uint16_t *)MIPS_PHYS_TO_KSEG1(KN01_SYS_CSR);
sys/arch/pmax/pmax/dec_3100.c
245
*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN01_SYS_ERRADR));
sys/arch/pmax/pmax/dec_3100.c
249
*(volatile uint16_t *)MIPS_PHYS_TO_KSEG1(KN01_SYS_CSR) = csr;
sys/arch/pmax/pmax/dec_3max.c
141
*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR) = 0;
sys/arch/pmax/pmax/dec_3max.c
147
mc_cpuspeed(MIPS_PHYS_TO_KSEG1(KN02_SYS_CLOCK), MIPS_INT_MASK_1);
sys/arch/pmax/pmax/dec_3max.c
153
csr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
sys/arch/pmax/pmax/dec_3max.c
155
*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) = csr;
sys/arch/pmax/pmax/dec_3max.c
172
*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR) = 0;
sys/arch/pmax/pmax/dec_3max.c
175
*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CHKSYN) = 0;
sys/arch/pmax/pmax/dec_3max.c
239
csr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) &
sys/arch/pmax/pmax/dec_3max.c
242
*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) = csr;
sys/arch/pmax/pmax/dec_3max.c
262
csr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
sys/arch/pmax/pmax/dec_3max.c
272
"r"(MIPS_PHYS_TO_KSEG1(KN02_SYS_CLOCK)));
sys/arch/pmax/pmax/dec_3max.c
283
csr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
sys/arch/pmax/pmax/dec_3max.c
321
erradr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR);
sys/arch/pmax/pmax/dec_3max.c
322
errsyn = MIPS_PHYS_TO_KSEG1(KN02_SYS_CHKSYN);
sys/arch/pmax/pmax/dec_3max.c
323
*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR) = 0;
sys/arch/pmax/pmax/dec_3max.c
325
csr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
sys/arch/pmax/pmax/dec_3maxplus.c
152
*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0;
sys/arch/pmax/pmax/dec_3maxplus.c
155
ioasic_base = MIPS_PHYS_TO_KSEG1(KN03_SYS_ASIC);
sys/arch/pmax/pmax/dec_3maxplus.c
179
prodtype = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN03_REG_INTR);
sys/arch/pmax/pmax/dec_3maxplus.c
201
*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0;
sys/arch/pmax/pmax/dec_3maxplus.c
405
erradr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR);
sys/arch/pmax/pmax/dec_3maxplus.c
406
errsyn = MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRSYN);
sys/arch/pmax/pmax/dec_3maxplus.c
407
*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0;
sys/arch/pmax/pmax/dec_3maxplus.c
409
csr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_CSR);
sys/arch/pmax/pmax/dec_3min.c
148
*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0;
sys/arch/pmax/pmax/dec_3min.c
151
ioasic_base = MIPS_PHYS_TO_KSEG1(KMIN_SYS_ASIC);
sys/arch/pmax/pmax/dec_3min.c
181
if ((KMIN_MSR_SIZE_16Mb & *(int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR))
sys/arch/pmax/pmax/dec_3min.c
184
physmem_boardmax = MIPS_PHYS_TO_KSEG1(physmem_boardmax);
sys/arch/pmax/pmax/dec_3min.c
200
*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0;
sys/arch/pmax/pmax/dec_3min.c
447
"i"(MIPS_PHYS_TO_KSEG1(KMIN_REG_IMSK)));
sys/arch/pmax/pmax/dec_5100.c
100
mc_cpuspeed(MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK), MIPS_INT_MASK_2);
sys/arch/pmax/pmax/dec_5100.c
114
icsr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN230_SYS_ICSR);
sys/arch/pmax/pmax/dec_5100.c
116
*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN230_SYS_ICSR) = icsr;
sys/arch/pmax/pmax/dec_5100.c
168
icsr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN230_SYS_ICSR);
sys/arch/pmax/pmax/dec_5100.c
175
"r"(MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK)));
sys/arch/pmax/pmax/dec_5100.c
214
icsr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN230_SYS_ICSR);
sys/arch/pmax/pmax/dec_5100.c
216
*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN230_SYS_ICSR) = icsr;
sys/arch/pmax/pmax/dec_maxine.c
147
*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(XINE_REG_TIMEOUT) = 0;
sys/arch/pmax/pmax/dec_maxine.c
150
ioasic_base = MIPS_PHYS_TO_KSEG1(XINE_SYS_ASIC);
sys/arch/pmax/pmax/dec_maxine.c
186
*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(XINE_REG_TIMEOUT) = 0;
sys/arch/pmax/pmax/dec_maxine.c
371
"i"(MIPS_PHYS_TO_KSEG1(XINE_REG_IMSK)));
sys/arch/pmax/pmax/dec_maxine.c
378
return *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(XINE_REG_FCTR);
sys/arch/pmax/pmax/machdep.c
478
cp = (char *)MIPS_PHYS_TO_KSEG1(mem << PGSHIFT);
sys/arch/pmax/pmax/memc_3min.c
70
siz = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR);
sys/arch/pmax/pmax/memc_3min.c
71
mer = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MER);
sys/arch/pmax/pmax/memc_3min.c
72
adr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_AER);
sys/arch/pmax/pmax/memc_3min.c
75
*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0;
sys/arch/pmax/tc/dt.c
245
MIPS_PHYS_TO_KSEG1(XINE_REG_INTR);
sys/arch/pmax/tc/dt.c
247
MIPS_PHYS_TO_KSEG1(XINE_PHYS_TC_3_START + 0x280000);
sys/arch/sbmips/sbmips/cpu.c
106
plldiv = G_SYS_PLL_DIV(READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_CFG)));
sys/arch/sbmips/sbmips/cpu.c
80
part = G_SYS_PART(READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_REVISION)));
sys/arch/sbmips/sbmips/machdep.c
401
(void *)MIPS_PHYS_TO_KSEG1(SWARM_LEDS_PHYS);
sys/arch/sbmips/sbmips/rtc.c
420
#define READ_REG(rp) mips3_ld((register_t)(MIPS_PHYS_TO_KSEG1(rp)))
sys/arch/sbmips/sbmips/rtc.c
421
#define WRITE_REG(rp, val) mips3_sd((register_t)(MIPS_PHYS_TO_KSEG1(rp)), (val))
sys/arch/sbmips/sbmips/sb1250_icu.c
211
MIPS_PHYS_TO_KSEG1(A_IMR_MAPPER(cpu->sb1cpu_ci->ci_cpuid));
sys/arch/sbmips/sbmips/sb1250_icu.c
268
u_int sys_part = G_SYS_PART(READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_REVISION)));
sys/arch/sbmips/sbmips/sb1250_icu.c
275
vaddr_t imr = MIPS_PHYS_TO_KSEG1(A_IMR_CPU0_BASE + R_IMR_INTERRUPT_MASK);
sys/arch/sbmips/sbmips/sb1250_icu.c
280
WRITE_REG(MIPS_PHYS_TO_KSEG1(A_IMR_CPU0_BASE + R_IMR_INTERRUPT_MASK),
sys/arch/sgimips/dev/scn.c
1869
(volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004);
sys/arch/sgimips/dev/scn.c
1896
(volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004);
sys/arch/sgimips/dev/scn.c
1914
(volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004);
sys/arch/sgimips/dev/scn.c
1940
(volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004);
sys/arch/sgimips/dev/scn.c
1942
(volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004);
sys/arch/sgimips/dev/scn.c
840
duart_base = (volatile u_char *)MIPS_PHYS_TO_KSEG1(ma->ma_addr);
sys/arch/sgimips/dev/zs.c
630
MIPS_PHYS_TO_KSEG1(0x1fb80d20);
sys/arch/sgimips/dev/zs.c
638
MIPS_PHYS_TO_KSEG1(0x1fb80d00);
sys/arch/sgimips/dev/zs.c
641
MIPS_PHYS_TO_KSEG1(0x1fb80d10);
sys/arch/sgimips/dev/zs.c
652
addr = (struct zsdevice *) MIPS_PHYS_TO_KSEG1(0x1fbd9830);
sys/arch/sgimips/gio/gio.c
211
if (platform.badaddr((void *)MIPS_PHYS_TO_KSEG1(ga.ga_addr),
sys/arch/sgimips/gio/gio.c
259
if (platform.badaddr((void *)MIPS_PHYS_TO_KSEG1(ga.ga_addr),
sys/arch/sgimips/gio/gio.c
334
ga->ga_ioh = MIPS_PHYS_TO_KSEG1(ga->ga_addr);
sys/arch/sgimips/gio/gio.c
377
if (platform.badaddr((void *)MIPS_PHYS_TO_KSEG1(ga.ga_addr),
sys/arch/sgimips/gio/newport.c
961
(void *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + NEWPORT_REX3_OFFSET + REX3_REG_XSTARTI),
sys/arch/sgimips/gio/newport.c
965
(void *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + NEWPORT_REX3_OFFSET + REX3_REG_XSTART),
sys/arch/sgimips/hpc/haltwo.c
278
rev = *(uint32_t *)MIPS_PHYS_TO_KSEG1(haa->ha_sh + haa->ha_devoff +
sys/arch/sgimips/hpc/haud.c
789
*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(haa->ha_sh + haa->ha_devoff +
sys/arch/sgimips/hpc/haud.c
794
MIPS_PHYS_TO_KSEG1(haa->ha_sh + haa->ha_dmaoff) = random_24b;
sys/arch/sgimips/hpc/haud.c
796
MIPS_PHYS_TO_KSEG1(haa->ha_sh + haa->ha_dmaoff) != random_24b) {
sys/arch/sgimips/hpc/hpc.c
391
if (!platform.badaddr((void*)MIPS_PHYS_TO_KSEG1(ga->ga_addr),
sys/arch/sgimips/hpc/hpc.c
442
*(uint32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr+HPC1_BIGENDIAN) = 0;
sys/arch/sgimips/hpc/hpc.c
471
(void *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_2), 4))
sys/arch/sgimips/hpc/hpc.c
518
MIPS_PHYS_TO_KSEG1(sc->sc_base), ha.hpc_eeprom,
sys/arch/sgimips/hpc/hpc.c
597
if (!platform.badaddr((void *)MIPS_PHYS_TO_KSEG1(ga->ga_addr +
sys/arch/sgimips/hpc/hpc.c
599
reg = *(uint32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr +
sys/arch/sgimips/hpc/hpc.c
630
if (platform.badaddr((void *)MIPS_PHYS_TO_KSEG1(ga->ga_addr +
sys/arch/sgimips/hpc/hpc.c
675
value = *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_0 +
sys/arch/sgimips/hpc/hpc.c
678
*(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_0 +
sys/arch/sgimips/hpc/if_sq.c
1322
uint8_t *physaddr = (uint8_t *)MIPS_PHYS_TO_KSEG1(addr);
sys/arch/sgimips/hpc/if_sq.c
157
reset = MIPS_PHYS_TO_KSEG1(ha->ha_sh +
sys/arch/sgimips/hpc/if_sq.c
159
txstat = MIPS_PHYS_TO_KSEG1(ha->ha_sh +
sys/arch/sgimips/hpc/wdsc.c
104
reset = MIPS_PHYS_TO_KSEG1(haa->ha_sh + haa->ha_dmaoff +
sys/arch/sgimips/hpc/wdsc.c
106
asr = MIPS_PHYS_TO_KSEG1(haa->ha_sh + haa->ha_devoff);
sys/arch/sgimips/ioc/if_le_oioc.c
206
sc->sc_mem = (void *)MIPS_PHYS_TO_KSEG1(
sys/arch/sgimips/ioc/oioc.c
106
if (platform.badaddr((void *)MIPS_PHYS_TO_KSEG1(ma->ma_addr +
sys/arch/sgimips/mace/mace.c
320
isa_irq = mips3_ld(MIPS_PHYS_TO_KSEG1(MACE_BASE
sys/arch/sgimips/sgimips/arcemu.c
160
if (memmem((void*)MIPS_PHYS_TO_KSEG1(0x1fc00000), len,
sys/arch/sgimips/sgimips/arcemu.c
522
memcfg = *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(0x1f800000) & 0x1f;
sys/arch/sgimips/sgimips/arcemu.c
534
tp1 = (volatile uint8_t *)MIPS_PHYS_TO_KSEG1((pages - 4096) << 12);
sys/arch/sgimips/sgimips/arcemu.c
629
MIPS_PHYS_TO_KSEG1(PIC_MEMCFG0_PHYSADDR) >> 16;
sys/arch/sgimips/sgimips/arcemu.c
634
MIPS_PHYS_TO_KSEG1(PIC_MEMCFG0_PHYSADDR) & 0xffff;
sys/arch/sgimips/sgimips/arcemu.c
639
MIPS_PHYS_TO_KSEG1(PIC_MEMCFG1_PHYSADDR) >> 16;
sys/arch/sgimips/sgimips/arcemu.c
644
MIPS_PHYS_TO_KSEG1(PIC_MEMCFG1_PHYSADDR) & 0xffff;
sys/arch/sgimips/sgimips/arcemu.h
106
*(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(0x1f8e0000) |= 0x10;
sys/arch/sgimips/sgimips/arcemu.h
108
*(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(0x1f8e0000) &= ~0x10;
sys/arch/sgimips/sgimips/arcemu.h
116
*(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(0x1f8e0000) |= 0x20;
sys/arch/sgimips/sgimips/arcemu.h
118
*(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(0x1f8e0000) &= ~0x20;
sys/arch/sgimips/sgimips/arcemu.h
126
*(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(0x1f8e0000) |= 0x40;
sys/arch/sgimips/sgimips/arcemu.h
128
*(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(0x1f8e0000) &= ~0x40;
sys/arch/sgimips/sgimips/arcemu.h
136
if (*(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(0x1f800001) & 0x01)
sys/arch/sgimips/sgimips/arcemu.h
145
*(volatile uint16_t *)MIPS_PHYS_TO_KSEG1(0x1f880002) |= 0x0100;
sys/arch/sgimips/sgimips/arcemu.h
147
*(volatile uint16_t *)MIPS_PHYS_TO_KSEG1(0x1f880002) &= ~0x0100;
sys/arch/sgimips/sgimips/arcemu.h
154
return (volatile uint8_t*)MIPS_PHYS_TO_KSEG1(
sys/arch/sgimips/sgimips/arcemu.h
67
(MIPS_PHYS_TO_KSEG1((_x)) >= 0xa0000000 && \
sys/arch/sgimips/sgimips/arcemu.h
68
MIPS_PHYS_TO_KSEG1((_x)) < 0xa0800000)
sys/arch/sgimips/sgimips/machdep.c
389
i = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9858);
sys/arch/sgimips/sgimips/machdep.c
557
i = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd0000);
sys/arch/sgimips/sgimips/machdep.c
579
i = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd0000);
sys/arch/sgimips/sgimips/mainbus.c
89
ma->ma_ioh = MIPS_PHYS_TO_KSEG1(ma->ma_addr);
sys/arch/sgimips/stand/common/iris_autoconf.c
40
wd33c93_init((void *)MIPS_PHYS_TO_KSEG1(SCSIA_ADDR),
sys/arch/sgimips/stand/common/iris_autoconf.c
41
(void *)MIPS_PHYS_TO_KSEG1(SCSID_ADDR));
sys/arch/sgimips/stand/common/iris_zs.c
159
addr = (struct zsdevice *)MIPS_PHYS_TO_KSEG1(ZS_ADDR);
sys/dev/tc/asc_tcds.c
437
addr = (uint32_t *)MIPS_PHYS_TO_KSEG1(pa);
sys/dev/tc/xcfb.c
282
ri->ri_bits = (void *)MIPS_PHYS_TO_KSEG1(XCFB_FB_BASE);
sys/dev/tc/xcfb.c
325
xcfb_consaddr = MIPS_PHYS_TO_KSEG1(XINE_PHYS_CFB_START);
sys/dev/tc/zs_ioasic.c
165
addr = (struct zsdevice *)MIPS_PHYS_TO_KSEG1(zsaddr);
sys/dev/tc/zs_ioasic.c
726
zs_addr = MIPS_PHYS_TO_KSEG1(ioasic_addr + zs_offset);