games/trek/phaser.c
108
struct banks bank[NBANKS];
games/trek/phaser.c
157
bank[i].units = 0;
games/trek/phaser.c
165
b = &bank[i];
games/trek/phaser.c
218
b = &bank[i];
games/trek/phaser.c
249
b = &bank[i];
games/trek/phaser.c
270
b = &bank[i];
games/trek/phaser.c
283
b = &bank[i];
games/trek/phaser.c
353
extra += bank[i].units;
sys/arch/aarch64/aarch64/pmap.c
512
uvm_physseg_t bank;
sys/arch/aarch64/aarch64/pmap.c
521
for (bank = uvm_physseg_get_first(); uvm_physseg_valid_p(bank);
sys/arch/aarch64/aarch64/pmap.c
522
bank = uvm_physseg_get_next(bank)) {
sys/arch/aarch64/aarch64/pmap.c
524
bank_npage = uvm_physseg_get_avail_end(bank) -
sys/arch/aarch64/aarch64/pmap.c
525
uvm_physseg_get_avail_start(bank);
sys/arch/aarch64/aarch64/pmap.c
530
if (!uvm_physseg_valid_p(bank)) {
sys/arch/aarch64/aarch64/pmap.c
535
pa = ptoa(uvm_physseg_get_avail_start(bank));
sys/arch/aarch64/aarch64/pmap_machdep.c
622
pmap_md_ok_to_steal_p(const uvm_physseg_t bank, size_t npgs)
sys/arch/alpha/alpha/machdep.c
676
uvm_physseg_t bank;
sys/arch/alpha/alpha/machdep.c
678
bank = uvm_physseg_get_last();
sys/arch/alpha/alpha/machdep.c
681
if (uvm_physseg_get_avail_end(bank) - uvm_physseg_get_avail_start(bank) < atop(sz))
sys/arch/alpha/alpha/machdep.c
682
sz = ptoa(uvm_physseg_get_avail_end(bank) - uvm_physseg_get_avail_start(bank));
sys/arch/alpha/alpha/machdep.c
684
end = uvm_physseg_get_end(bank);
sys/arch/alpha/alpha/pmap.c
1494
uvm_physseg_t bank;
sys/arch/alpha/alpha/pmap.c
1503
for (bank = uvm_physseg_get_first();
sys/arch/alpha/alpha/pmap.c
1504
uvm_physseg_valid_p(bank);
sys/arch/alpha/alpha/pmap.c
1505
bank = uvm_physseg_get_next(bank)) {
sys/arch/alpha/alpha/pmap.c
1511
"avail_end 0x%"PRIxPADDR"\n", bank, uvm_physseg_get_avail_start(bank),
sys/arch/alpha/alpha/pmap.c
1512
uvm_physseg_get_start(bank), uvm_physseg_get_avail_end(bank));
sys/arch/alpha/alpha/pmap.c
1515
if (uvm_physseg_get_avail_start(bank) != uvm_physseg_get_start(bank) ||
sys/arch/alpha/alpha/pmap.c
1516
uvm_physseg_get_avail_start(bank) >= uvm_physseg_get_avail_end(bank))
sys/arch/alpha/alpha/pmap.c
1521
uvm_physseg_get_avail_end(bank) - uvm_physseg_get_avail_start(bank));
sys/arch/alpha/alpha/pmap.c
1524
if (uvm_physseg_get_avail_end(bank) - uvm_physseg_get_avail_start(bank)
sys/arch/alpha/alpha/pmap.c
1531
pa = ptoa(uvm_physseg_get_start(bank));
sys/arch/alpha/alpha/pmap.c
1586
for (uvm_physseg_t bank = uvm_physseg_get_first();
sys/arch/alpha/alpha/pmap.c
1587
uvm_physseg_valid_p(bank);
sys/arch/alpha/alpha/pmap.c
1588
bank = uvm_physseg_get_next(bank)) {
sys/arch/alpha/alpha/pmap.c
1589
printf("bank %d\n", bank);
sys/arch/alpha/alpha/pmap.c
1590
printf("\tstart = 0x%lx\n", ptoa(uvm_physseg_get_start(bank)));
sys/arch/alpha/alpha/pmap.c
1591
printf("\tend = 0x%lx\n", ptoa(uvm_physseg_get_end(bank)));
sys/arch/alpha/alpha/pmap.c
1593
ptoa(uvm_physseg_get_avail_start(bank)));
sys/arch/alpha/alpha/pmap.c
1595
ptoa(uvm_physseg_get_avail_end(bank)));
sys/arch/amiga/dev/gtsc.c
149
rp->bank = 0;
sys/arch/amiga/dev/gtsc.c
289
sdp->bank =
sys/arch/amiga/dev/gtsc.c
383
sdp->bank =
sys/arch/amiga/dev/gtscreg.h
56
vu_short bank;
sys/arch/arm/amlogic/gxlphy.c
104
gxl_readreg(struct mii_softc *sc, u_int bank, u_int reg)
sys/arch/arm/amlogic/gxlphy.c
111
__SHIFTIN(bank, TSTCNTL_REG_BANK_SEL) |
sys/arch/arm/amlogic/gxlphy.c
120
gxl_writereg(struct mii_softc *sc, u_int bank, u_int reg, uint16_t val)
sys/arch/arm/amlogic/gxlphy.c
126
__SHIFTIN(bank, TSTCNTL_REG_BANK_SEL) |
sys/arch/arm/amlogic/meson_pinctrl.c
130
if (group->bank[n] == bankno)
sys/arch/arm/amlogic/meson_pinctrl.c
161
u_int n, bank;
sys/arch/arm/amlogic/meson_pinctrl.c
174
for (bank = 0; bank < target_group->nbank; bank++) {
sys/arch/arm/amlogic/meson_pinctrl.c
175
if (meson_pinctrl_group_in_bank(sc, group, target_group->bank[bank]))
sys/arch/arm/amlogic/meson_pinctrl.c
349
u_int n, bank;
sys/arch/arm/amlogic/meson_pinctrl.c
364
for (bank = 0; bank < group->nbank; bank++) {
sys/arch/arm/amlogic/meson_pinctrl.c
365
if (group->bank[bank] == pin_def->id)
sys/arch/arm/amlogic/meson_pinctrl.h
64
u_int bank[MESON_PINCTRL_MAXBANK];
sys/arch/arm/amlogic/mesong12a_pinctrl.c
339
.bank = { _group }, .nbank = 1, \
sys/arch/arm/amlogic/mesong12a_pinctrl.c
595
.bank = { _group }, .nbank = 1, \
sys/arch/arm/broadcom/bcm2835_gpio.c
267
int bank;
sys/arch/arm/broadcom/bcm2835_gpio.c
332
for (bank = 0; bank < BCMGPIO_NBANKS; bank++) {
sys/arch/arm/broadcom/bcm2835_gpio.c
335
if (!fdtbus_intr_str(phandle, bank, intrstr, sizeof(intrstr))) {
sys/arch/arm/broadcom/bcm2835_gpio.c
342
bank);
sys/arch/arm/broadcom/bcm2835_gpio.c
343
sc->sc_banks[bank].sc_bankno = bank;
sys/arch/arm/broadcom/bcm2835_gpio.c
344
sc->sc_banks[bank].sc_bcm = sc;
sys/arch/arm/broadcom/bcm2835_gpio.c
345
sc->sc_banks[bank].sc_ih = fdtbus_intr_establish_xname(phandle,
sys/arch/arm/broadcom/bcm2835_gpio.c
346
bank, IPL_VM, FDT_INTR_MPSAFE, bcmgpio_intr,
sys/arch/arm/broadcom/bcm2835_gpio.c
347
&sc->sc_banks[bank], xname);
sys/arch/arm/broadcom/bcm2835_gpio.c
348
if (sc->sc_banks[bank].sc_ih) {
sys/arch/arm/broadcom/bcm2835_gpio.c
351
bank * 32,
sys/arch/arm/broadcom/bcm2835_gpio.c
352
MIN((bank * 32) + 31, sc->sc_maxpins),
sys/arch/arm/broadcom/bcm2835_gpio.c
357
bank * 32,
sys/arch/arm/broadcom/bcm2835_gpio.c
358
MIN((bank * 32) + 31, sc->sc_maxpins));
sys/arch/arm/broadcom/bcm2835_gpio.c
452
int bank, int pin, int flags)
sys/arch/arm/broadcom/bcm2835_gpio.c
460
if (bank < 0 || bank >= BCMGPIO_NBANKS)
sys/arch/arm/broadcom/bcm2835_gpio.c
477
eint = &sc->sc_banks[bank].sc_eint[pin];
sys/arch/arm/broadcom/bcm2835_gpio.c
491
eint->eint_bank = bank;
sys/arch/arm/broadcom/bcm2835_gpio.c
495
BCM2835_GPIO_GPREN(bank));
sys/arch/arm/broadcom/bcm2835_gpio.c
497
BCM2835_GPIO_GPFEN(bank));
sys/arch/arm/broadcom/bcm2835_gpio.c
499
BCM2835_GPIO_GPHEN(bank));
sys/arch/arm/broadcom/bcm2835_gpio.c
501
BCM2835_GPIO_GPLEN(bank));
sys/arch/arm/broadcom/bcm2835_gpio.c
518
BCM2835_GPIO_GPREN(bank), enabled_ren);
sys/arch/arm/broadcom/bcm2835_gpio.c
520
BCM2835_GPIO_GPFEN(bank), enabled_fen);
sys/arch/arm/broadcom/bcm2835_gpio.c
522
BCM2835_GPIO_GPHEN(bank), enabled_hen);
sys/arch/arm/broadcom/bcm2835_gpio.c
524
BCM2835_GPIO_GPLEN(bank), enabled_len);
sys/arch/arm/broadcom/bcm2835_gpio.c
534
int bank = eint->eint_bank;
sys/arch/arm/broadcom/bcm2835_gpio.c
543
BCM2835_GPIO_GPREN(bank));
sys/arch/arm/broadcom/bcm2835_gpio.c
545
BCM2835_GPIO_GPFEN(bank));
sys/arch/arm/broadcom/bcm2835_gpio.c
547
BCM2835_GPIO_GPHEN(bank));
sys/arch/arm/broadcom/bcm2835_gpio.c
549
BCM2835_GPIO_GPLEN(bank));
sys/arch/arm/broadcom/bcm2835_gpio.c
557
BCM2835_GPIO_GPREN(bank), enabled_ren);
sys/arch/arm/broadcom/bcm2835_gpio.c
559
BCM2835_GPIO_GPFEN(bank), enabled_fen);
sys/arch/arm/broadcom/bcm2835_gpio.c
561
BCM2835_GPIO_GPHEN(bank), enabled_hen);
sys/arch/arm/broadcom/bcm2835_gpio.c
563
BCM2835_GPIO_GPLEN(bank), enabled_len);
sys/arch/arm/broadcom/bcm2835_gpio.c
587
const u_int bank = be32toh(specifier[0]) / 32;
sys/arch/arm/broadcom/bcm2835_gpio.c
613
return (bmcgpio_intr_enable(sc, func, arg, bank, pin, eint_flags));
sys/arch/arm/broadcom/bcm2835_gpio.c
631
int bank = pin / 32;
sys/arch/arm/broadcom/bcm2835_gpio.c
664
return (bmcgpio_intr_enable(sc, func, arg, bank, pin, eint_flags));
sys/arch/arm/broadcom/bcm2835_gpio.c
697
const u_int bank = be32toh(specifier[0]) / 32;
sys/arch/arm/broadcom/bcm2835_gpio.c
702
if (bank >= BCMGPIO_NBANKS)
sys/arch/arm/broadcom/bcm2835_gpio.c
727
snprintf(buf, buflen, "GPIO %u (%s)", (bank * 32) + pin, typestr);
sys/arch/arm/broadcom/bcm2835_intr.c
527
const u_int bank = be32toh(specifier[0]);
sys/arch/arm/broadcom/bcm2835_intr.c
528
switch (bank) {
sys/arch/arm/footbridge/isa/dsrtc.c
91
ds1687_bank_select(struct dsrtc_softc *sc, int bank)
sys/arch/arm/footbridge/isa/dsrtc.c
97
if (bank)
sys/arch/arm/nvidia/tegra_gpio.c
139
#define GPIO_WRITE(bank, reg, val) \
sys/arch/arm/nvidia/tegra_gpio.c
140
bus_space_write_4((bank)->bank_sc->sc_bst, \
sys/arch/arm/nvidia/tegra_gpio.c
141
(bank)->bank_sc->sc_bsh, \
sys/arch/arm/nvidia/tegra_gpio.c
142
(bank)->bank_pb->base + (reg), (val))
sys/arch/arm/nvidia/tegra_gpio.c
143
#define GPIO_READ(bank, reg) \
sys/arch/arm/nvidia/tegra_gpio.c
144
bus_space_read_4((bank)->bank_sc->sc_bst, \
sys/arch/arm/nvidia/tegra_gpio.c
145
(bank)->bank_sc->sc_bsh, \
sys/arch/arm/nvidia/tegra_gpio.c
146
(bank)->bank_pb->base + (reg))
sys/arch/arm/nvidia/tegra_gpio.c
202
struct tegra_gpio_bank *bank = &sc->sc_banks[bankno];
sys/arch/arm/nvidia/tegra_gpio.c
206
bank->bank_sc = sc;
sys/arch/arm/nvidia/tegra_gpio.c
207
bank->bank_pb = &tegra_gpio_pinbanks[bankno];
sys/arch/arm/nvidia/tegra_gpio.c
208
bank->bank_gc.gp_cookie = bank;
sys/arch/arm/nvidia/tegra_gpio.c
209
bank->bank_gc.gp_pin_read = tegra_gpio_pin_read;
sys/arch/arm/nvidia/tegra_gpio.c
210
bank->bank_gc.gp_pin_write = tegra_gpio_pin_write;
sys/arch/arm/nvidia/tegra_gpio.c
211
bank->bank_gc.gp_pin_ctl = tegra_gpio_pin_ctl;
sys/arch/arm/nvidia/tegra_gpio.c
213
const uint32_t cnf = GPIO_READ(bank, GPIO_CNF_REG);
sys/arch/arm/nvidia/tegra_gpio.c
215
for (pin = 0; pin < __arraycount(bank->bank_pins); pin++) {
sys/arch/arm/nvidia/tegra_gpio.c
216
bank->bank_pins[pin].pin_num = pin;
sys/arch/arm/nvidia/tegra_gpio.c
220
bank->bank_pins[pin].pin_caps =
sys/arch/arm/nvidia/tegra_gpio.c
223
bank->bank_pins[pin].pin_state =
sys/arch/arm/nvidia/tegra_gpio.c
224
tegra_gpio_pin_read(bank, pin);
sys/arch/arm/nvidia/tegra_gpio.c
228
gba.gba_gc = &bank->bank_gc;
sys/arch/arm/nvidia/tegra_gpio.c
229
gba.gba_pins = bank->bank_pins;
sys/arch/arm/nvidia/tegra_gpio.c
230
gba.gba_npins = __arraycount(bank->bank_pins);
sys/arch/arm/nvidia/tegra_gpio.c
232
bank->bank_dev =
sys/arch/arm/nvidia/tegra_gpio.c
240
struct tegra_gpio_bank *bank = gba->gba_gc->gp_cookie;
sys/arch/arm/nvidia/tegra_gpio.c
241
const char *bankname = bank->bank_pb->name;
sys/arch/arm/nvidia/tegra_gpio.c
254
struct tegra_gpio_bank *bank = priv;
sys/arch/arm/nvidia/tegra_gpio.c
256
const uint32_t v = GPIO_READ(bank, GPIO_IN_REG);
sys/arch/arm/nvidia/tegra_gpio.c
264
struct tegra_gpio_bank *bank = priv;
sys/arch/arm/nvidia/tegra_gpio.c
269
GPIO_WRITE(bank, GPIO_MSK_OUT_REG, v);
sys/arch/arm/nvidia/tegra_gpio.c
275
struct tegra_gpio_bank *bank = priv;
sys/arch/arm/nvidia/tegra_gpio.c
280
GPIO_WRITE(bank, GPIO_MSK_OE_REG, v);
sys/arch/arm/nvidia/tegra_gpio.c
284
GPIO_WRITE(bank, GPIO_MSK_OE_REG, v);
sys/arch/arm/nvidia/tegra_gpio.c
298
const u_int bank = be32toh(gpio[1]) >> 3;
sys/arch/arm/nvidia/tegra_gpio.c
302
if (bank >= __arraycount(tegra_gpio_pinbanks) || pin > 8)
sys/arch/arm/nvidia/tegra_gpio.c
306
gbank.bank_pb = &tegra_gpio_pinbanks[bank];
sys/arch/arm/nvidia/tegra_gpio.c
389
struct tegra_gpio_bank bank;
sys/arch/arm/nvidia/tegra_gpio.c
398
bank.bank_sc = device_private(dev);
sys/arch/arm/nvidia/tegra_gpio.c
399
bank.bank_pb = tegra_gpio_pin_lookup(pinname, &pin);
sys/arch/arm/nvidia/tegra_gpio.c
400
if (bank.bank_pb == NULL)
sys/arch/arm/nvidia/tegra_gpio.c
403
const uint32_t cnf = GPIO_READ(&bank, GPIO_CNF_REG);
sys/arch/arm/nvidia/tegra_gpio.c
405
GPIO_WRITE(&bank, GPIO_CNF_REG, cnf | __BIT(pin));
sys/arch/arm/nvidia/tegra_gpio.c
408
gpin->pin_bank = bank;
sys/arch/arm/rockchip/rk3288_iomux.c
126
rk3288_iomux_get_reg(struct rk3288_iomux_softc *sc, u_int bank, u_int idx,
sys/arch/arm/rockchip/rk3288_iomux.c
129
if (bank >= NBANKS || idx >= NPINSPERBANK) {
sys/arch/arm/rockchip/rk3288_iomux.c
133
if (bank == 0) {
sys/arch/arm/rockchip/rk3288_iomux.c
141
reg->pull_reg = 0x130 + (bank * 0x10) + (idx / 8) * 4;
sys/arch/arm/rockchip/rk3288_iomux.c
143
reg->drv_reg = 0x1b0 + (bank * 0x10) + (idx / 8) * 4;
sys/arch/arm/rockchip/rk3288_iomux.c
146
reg->flags = rk3288_iomux_flags[bank][idx / 8];
sys/arch/arm/rockchip/rk3288_iomux.c
147
reg->mux_reg = rk3288_iomux_offset[bank][idx / 8];
sys/arch/arm/rockchip/rk3288_iomux.c
294
const u_int bank = be32toh(pins[0]);
sys/arch/arm/rockchip/rk3288_iomux.c
300
if (rk3288_iomux_get_reg(sc, bank, idx, ®def)) {
sys/arch/arm/rockchip/rk3288_iomux.c
302
printf(" -> gpio%u P%c%u (%u)\n", bank, 'A' + (idx / 8), idx % 8, idx);
sys/arch/arm/rockchip/rk3288_iomux.c
307
bank, mux);
sys/arch/arm/rockchip/rk3328_iomux.c
145
rk3328_iomux_calc_iomux_reg(struct rk3328_iomux_softc *sc, u_int bank, u_int pin, bus_size_t *reg, uint32_t *mask)
sys/arch/arm/rockchip/rk3328_iomux.c
149
KASSERT(bank < sc->sc_conf->nbanks);
sys/arch/arm/rockchip/rk3328_iomux.c
151
*reg = banks[bank].iomux[pin / 8].base;
sys/arch/arm/rockchip/rk3328_iomux.c
152
if (banks[bank].iomux[pin / 8].type & RK3328_IOMUX_TYPE_3BIT) {
sys/arch/arm/rockchip/rk3328_iomux.c
164
rk3328_iomux_set_bias(struct rk3328_iomux_softc *sc, u_int bank, u_int idx, u_int bias)
sys/arch/arm/rockchip/rk3328_iomux.c
166
WR4(sc, GRF_GPIO_P_REG(bank, idx),
sys/arch/arm/rockchip/rk3328_iomux.c
172
rk3328_iomux_set_drive_strength(struct rk3328_iomux_softc *sc, u_int bank, u_int idx, u_int drv)
sys/arch/arm/rockchip/rk3328_iomux.c
174
WR4(sc, GRF_GPIO_E_REG(bank, idx),
sys/arch/arm/rockchip/rk3328_iomux.c
180
rk3328_iomux_set_mux(struct rk3328_iomux_softc *sc, u_int bank, u_int idx, u_int mux)
sys/arch/arm/rockchip/rk3328_iomux.c
185
rk3328_iomux_calc_iomux_reg(sc, bank, idx, ®, &mask);
sys/arch/arm/rockchip/rk3328_iomux.c
191
rk3328_iomux_config(struct rk3328_iomux_softc *sc, const int phandle, u_int bank, u_int idx, u_int mux)
sys/arch/arm/rockchip/rk3328_iomux.c
197
rk3328_iomux_set_bias(sc, bank, idx, GRF_GPIO_P_CTL_Z);
sys/arch/arm/rockchip/rk3328_iomux.c
200
rk3328_iomux_set_bias(sc, bank, idx, GRF_GPIO_P_CTL_PULLUP);
sys/arch/arm/rockchip/rk3328_iomux.c
203
rk3328_iomux_set_bias(sc, bank, idx, GRF_GPIO_P_CTL_PULLDOWN);
sys/arch/arm/rockchip/rk3328_iomux.c
212
rk3328_iomux_set_drive_strength(sc, bank, idx, GRF_GPIO_E_CTL_2MA);
sys/arch/arm/rockchip/rk3328_iomux.c
215
rk3328_iomux_set_drive_strength(sc, bank, idx, GRF_GPIO_E_CTL_4MA);
sys/arch/arm/rockchip/rk3328_iomux.c
218
rk3328_iomux_set_drive_strength(sc, bank, idx, GRF_GPIO_E_CTL_8MA);
sys/arch/arm/rockchip/rk3328_iomux.c
221
rk3328_iomux_set_drive_strength(sc, bank, idx, GRF_GPIO_E_CTL_12MA);
sys/arch/arm/rockchip/rk3328_iomux.c
233
rk3328_iomux_set_direction(sc, bank, idx, direction,
sys/arch/arm/rockchip/rk3328_iomux.c
238
rk3328_iomux_set_mux(sc, bank, idx, mux);
sys/arch/arm/rockchip/rk3328_iomux.c
256
const u_int bank = be32toh(pins[0]);
sys/arch/arm/rockchip/rk3328_iomux.c
262
rk3328_iomux_config(sc, cfg, bank, idx, mux);
sys/arch/arm/rockchip/rk3399_iomux.c
212
rk3399_iomux_set_bias(struct rk3399_iomux_softc *sc, u_int bank, u_int idx, int flags)
sys/arch/arm/rockchip/rk3399_iomux.c
218
KASSERT(bank < sc->sc_conf->nbanks);
sys/arch/arm/rockchip/rk3399_iomux.c
220
struct syscon * const syscon = sc->sc_syscon[banks[bank].regs];
sys/arch/arm/rockchip/rk3399_iomux.c
221
if (RK3399_IOMUX_BANK_IS_PMU(bank)) {
sys/arch/arm/rockchip/rk3399_iomux.c
222
reg = 0x00040 + (0x10 * bank);
sys/arch/arm/rockchip/rk3399_iomux.c
224
reg = 0x0e040 + (0x10 * (bank - 2));
sys/arch/arm/rockchip/rk3399_iomux.c
228
const int pull_type = banks[bank].iomux[idx / 8].pull_type;
sys/arch/arm/rockchip/rk3399_iomux.c
248
printf("%s: bank %d idx %d flags %#x: %08x -> ", __func__, bank, idx, flags, RD4(syscon, reg));
sys/arch/arm/rockchip/rk3399_iomux.c
266
rk3399_iomux_set_drive_strength(struct rk3399_iomux_softc *sc, u_int bank, u_int idx, u_int val)
sys/arch/arm/rockchip/rk3399_iomux.c
272
KASSERT(bank < sc->sc_conf->nbanks);
sys/arch/arm/rockchip/rk3399_iomux.c
277
const int drv = rk3399_iomux_map_drive_strength(sc, banks[bank].iomux[idx / 8].drv_type, val);
sys/arch/arm/rockchip/rk3399_iomux.c
281
struct syscon * const syscon = sc->sc_syscon[banks[bank].regs];
sys/arch/arm/rockchip/rk3399_iomux.c
282
switch (bank) {
sys/arch/arm/rockchip/rk3399_iomux.c
285
reg = 0x00040 + (0x10 * bank) + 0x4 * (idx / 4);
sys/arch/arm/rockchip/rk3399_iomux.c
340
printf("%s: bank %d idx %d val %d: %08x -> ", __func__, bank, idx, val, RD4(syscon, reg));
sys/arch/arm/rockchip/rk3399_iomux.c
356
rk3399_iomux_set_mux(struct rk3399_iomux_softc *sc, u_int bank, u_int idx, u_int mux)
sys/arch/arm/rockchip/rk3399_iomux.c
362
KASSERT(bank < sc->sc_conf->nbanks);
sys/arch/arm/rockchip/rk3399_iomux.c
364
struct syscon * const syscon = sc->sc_syscon[banks[bank].regs];
sys/arch/arm/rockchip/rk3399_iomux.c
365
if (RK3399_IOMUX_BANK_IS_PMU(bank)) {
sys/arch/arm/rockchip/rk3399_iomux.c
366
reg = 0x00000 + (0x10 * bank);
sys/arch/arm/rockchip/rk3399_iomux.c
368
reg = 0x0e000 + (0x10 * (bank - 2));
sys/arch/arm/rockchip/rk3399_iomux.c
374
printf("%s: bank %d idx %d mux %#x: %08x -> ", __func__, bank, idx, mux, RD4(syscon, reg));
sys/arch/arm/rockchip/rk3399_iomux.c
383
rk3399_iomux_config(struct rk3399_iomux_softc *sc, const int phandle, u_int bank, u_int idx, u_int mux)
sys/arch/arm/rockchip/rk3399_iomux.c
388
rk3399_iomux_set_bias(sc, bank, idx, bias);
sys/arch/arm/rockchip/rk3399_iomux.c
392
rk3399_iomux_set_drive_strength(sc, bank, idx, drv) != 0)
sys/arch/arm/rockchip/rk3399_iomux.c
400
rk3399_iomux_set_direction(sc, bank, idx, direction,
sys/arch/arm/rockchip/rk3399_iomux.c
405
rk3399_iomux_set_mux(sc, bank, idx, mux);
sys/arch/arm/rockchip/rk3399_iomux.c
424
const u_int bank = be32toh(pins[0]);
sys/arch/arm/rockchip/rk3399_iomux.c
429
struct syscon * const syscon = sc->sc_syscon[banks[bank].regs];
sys/arch/arm/rockchip/rk3399_iomux.c
431
rk3399_iomux_config(sc, cfg, bank, idx, mux);
sys/arch/arm/rockchip/rk3588_iomux.c
70
#define PIN(bank, idx) (((bank) * NPINPERBANK) + (idx))
sys/arch/arm/rockchip/rk3588_iomux.c
844
int bank = pin / 32;
sys/arch/arm/rockchip/rk3588_iomux.c
848
pin, bank, 'A' + group, idx);
sys/arch/arm/rockchip/rk3588_iomux.c
942
u_int bank, u_int idx, u_int mux)
sys/arch/arm/rockchip/rk3588_iomux.c
944
const int pin = PIN(bank, idx);
sys/arch/arm/rockchip/rk3588_iomux.c
981
const u_int bank = be32toh(pins[0]);
sys/arch/arm/rockchip/rk3588_iomux.c
988
rk3588_iomux_config(sc, cfg, bank, idx, mux);
sys/arch/arm/samsung/exynos_gpio.c
241
#define GPIO_WRITE(bank, reg, val) \
sys/arch/arm/samsung/exynos_gpio.c
242
bus_space_write_4((bank)->bank_sc->sc_bst, \
sys/arch/arm/samsung/exynos_gpio.c
243
(bank)->bank_sc->sc_bsh, \
sys/arch/arm/samsung/exynos_gpio.c
244
(bank)->bank_core_offset + (reg), (val))
sys/arch/arm/samsung/exynos_gpio.c
245
#define GPIO_READ(bank, reg) \
sys/arch/arm/samsung/exynos_gpio.c
246
bus_space_read_4((bank)->bank_sc->sc_bst, \
sys/arch/arm/samsung/exynos_gpio.c
247
(bank)->bank_sc->sc_bsh, \
sys/arch/arm/samsung/exynos_gpio.c
248
(bank)->bank_core_offset + (reg))
sys/arch/arm/samsung/exynos_gpio.c
254
struct exynos_gpio_bank *bank = gba->gba_gc->gp_cookie;
sys/arch/arm/samsung/exynos_gpio.c
255
const char *bankname = bank->bank_name;
sys/arch/arm/samsung/exynos_gpio.c
268
struct exynos_gpio_bank * const bank = cookie;
sys/arch/arm/samsung/exynos_gpio.c
271
KASSERT(pin < bank->bank_bits);
sys/arch/arm/samsung/exynos_gpio.c
272
val = bus_space_read_1(bank->bank_sc->sc_bst, bank->bank_sc->sc_bsh,
sys/arch/arm/samsung/exynos_gpio.c
281
struct exynos_gpio_bank * const bank = cookie;
sys/arch/arm/samsung/exynos_gpio.c
284
KASSERT(pin < bank->bank_bits);
sys/arch/arm/samsung/exynos_gpio.c
285
val = bus_space_read_1(bank->bank_sc->sc_bst, bank->bank_sc->sc_bsh,
sys/arch/arm/samsung/exynos_gpio.c
290
bus_space_write_1(bank->bank_sc->sc_bst, bank->bank_sc->sc_bsh,
sys/arch/arm/samsung/exynos_gpio.c
297
struct exynos_gpio_bank * const bank = cookie;
sys/arch/arm/samsung/exynos_gpio.c
320
exynos_gpio_pin_ctl_write(bank, &ncfg, pin);
sys/arch/arm/samsung/exynos_gpio.c
323
void exynos_gpio_pin_ctl_write(const struct exynos_gpio_bank *bank,
sys/arch/arm/samsung/exynos_gpio.c
330
val = GPIO_READ(bank, EXYNOS_GPIO_CON);
sys/arch/arm/samsung/exynos_gpio.c
333
GPIO_WRITE(bank, EXYNOS_GPIO_CON, val);
sys/arch/arm/samsung/exynos_gpio.c
337
val = GPIO_READ(bank, EXYNOS_GPIO_PUD);
sys/arch/arm/samsung/exynos_gpio.c
340
GPIO_WRITE(bank, EXYNOS_GPIO_PUD, val);
sys/arch/arm/samsung/exynos_gpio.c
344
val = GPIO_READ(bank, EXYNOS_GPIO_DRV);
sys/arch/arm/samsung/exynos_gpio.c
347
GPIO_WRITE(bank, EXYNOS_GPIO_DRV, val);
sys/arch/arm/samsung/exynos_gpio.c
351
val = GPIO_READ(bank, EXYNOS_GPIO_CONPWD);
sys/arch/arm/samsung/exynos_gpio.c
354
GPIO_WRITE(bank, EXYNOS_GPIO_CONPWD, val);
sys/arch/arm/samsung/exynos_gpio.c
358
val = GPIO_READ(bank, EXYNOS_GPIO_PUDPWD);
sys/arch/arm/samsung/exynos_gpio.c
361
GPIO_WRITE(bank, EXYNOS_GPIO_PUDPWD, val);
sys/arch/arm/samsung/exynos_gpio.c
375
struct exynos_gpio_bank *bank =
sys/arch/arm/samsung/exynos_gpio.c
377
if (bank == NULL) {
sys/arch/arm/samsung/exynos_gpio.c
386
sc->sc_bank = bank;
sys/arch/arm/samsung/exynos_gpio.c
388
gc_tag = &bank->bank_gc;
sys/arch/arm/samsung/exynos_gpio.c
389
gc_tag->gp_cookie = bank;
sys/arch/arm/samsung/exynos_gpio.c
394
gba.gba_gc = &bank->bank_gc;
sys/arch/arm/samsung/exynos_gpio.c
395
gba.gba_pins = bank->bank_pins;
sys/arch/arm/samsung/exynos_gpio.c
396
gba.gba_npins = bank->bank_bits;
sys/arch/arm/samsung/exynos_gpio.c
398
bank->bank_sc = sc;
sys/arch/arm/samsung/exynos_gpio.c
399
bank->bank_dev =
sys/arch/arm/samsung/exynos_gpio.c
403
bank->bank_cfg.cfg = GPIO_READ(bank, EXYNOS_GPIO_CON);
sys/arch/arm/samsung/exynos_gpio.c
404
bank->bank_cfg.pud = GPIO_READ(bank, EXYNOS_GPIO_PUD);
sys/arch/arm/samsung/exynos_gpio.c
405
bank->bank_cfg.drv = GPIO_READ(bank, EXYNOS_GPIO_DRV);
sys/arch/arm/samsung/exynos_gpio.c
406
bank->bank_cfg.conpwd = GPIO_READ(bank, EXYNOS_GPIO_CONPWD);
sys/arch/arm/samsung/exynos_gpio.c
407
bank->bank_cfg.pudpwd = GPIO_READ(bank, EXYNOS_GPIO_PUDPWD);
sys/arch/arm/samsung/exynos_gpio.c
409
fdtbus_register_gpio_controller(bank->bank_dev, node,
sys/arch/arm/samsung/exynos_gpio.c
423
struct exynos_gpio_bank *bank;
sys/arch/arm/samsung/exynos_gpio.c
426
bank = &epb->epb_banks[n];
sys/arch/arm/samsung/exynos_gpio.c
427
if (!strncmp(bank->bank_name, name,
sys/arch/arm/samsung/exynos_gpio.c
428
strlen(bank->bank_name))) {
sys/arch/arm/samsung/exynos_gpio.c
429
return bank;
sys/arch/arm/samsung/exynos_gpio.c
456
struct exynos_gpio_bank *bank = NULL;
sys/arch/arm/samsung/exynos_gpio.c
471
bank = &epb->epb_banks[n];
sys/arch/arm/samsung/exynos_gpio.c
475
KASSERTMSG(bank != NULL, "no such gpio bank child of %s @ %p: %s @ %p",
sys/arch/arm/samsung/exynos_gpio.c
479
gpin->pin_sc = bank->bank_sc;
sys/arch/arm/samsung/exynos_gpio.c
480
gpin->pin_bank = bank;
sys/arch/arm/samsung/exynos_gpio.c
485
exynos_gpio_pin_ctl(bank, gpin->pin_no, gpin->pin_flags);
sys/arch/arm/samsung/exynos_pinctrl.c
166
struct exynos_gpio_bank *bank;
sys/arch/arm/samsung/exynos_pinctrl.c
177
bank = exynos_gpio_bank_lookup(epb, pins);
sys/arch/arm/samsung/exynos_pinctrl.c
179
if (bank == NULL) {
sys/arch/arm/samsung/exynos_pinctrl.c
184
exynos_gpio_pin_ctl_write(bank, gc, pin);
sys/arch/arm/sunxi/sunxi_gpio.c
447
u_int bank;
sys/arch/arm/sunxi/sunxi_gpio.c
450
for (bank = 0; bank <= sc->sc_eint_bank_max; bank++) {
sys/arch/arm/sunxi/sunxi_gpio.c
451
status = GPIO_READ(sc, SUNXI_GPIO_INT_STATUS(bank));
sys/arch/arm/sunxi/sunxi_gpio.c
454
GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS(bank), status);
sys/arch/arm/sunxi/sunxi_gpio.c
458
eint = &sc->sc_eint[bank][bit - 1];
sys/arch/arm/sunxi/sunxi_gpio.c
66
#define SUNXI_GPIO_INT_CFG(bank, eint) (0x200 + (0x20 * (bank)) + (0x4 * ((eint) / 8)))
sys/arch/arm/sunxi/sunxi_gpio.c
73
#define SUNXI_GPIO_INT_CTL(bank) (0x210 + 0x20 * (bank))
sys/arch/arm/sunxi/sunxi_gpio.c
74
#define SUNXI_GPIO_INT_STATUS(bank) (0x214 + 0x20 * (bank))
sys/arch/arm/sunxi/sunxi_gpio.c
75
#define SUNXI_GPIO_INT_DEBOUNCE(bank) (0x218 + 0x20 * (bank))
sys/arch/arm/sunxi/sunxi_gpio.c
78
#define SUNXI_GPIO_GRP_CONFIG(bank) (0x300 + 0x4 * (bank))
sys/arch/arm/xscale/pxa2x0_gpio.c
414
int bank;
sys/arch/arm/xscale/pxa2x0_gpio.c
430
bank = GPIO_BANK(gpio_base);
sys/arch/arm/xscale/pxa2x0_gpio.c
437
if ((gedr & sc->sc_mask[bank]) == 0) {
sys/arch/arm/xscale/pxa2x0_gpio.c
440
bank, gedr, sc->sc_mask[bank]);
sys/arch/arm/xscale/pxa2x0_gpio.c
445
gedr &= sc->sc_mask[bank];
sys/arch/atari/atari/atari_init.c
236
int slot, bank, seg;
sys/arch/atari/atari/atari_init.c
245
for (bank = 0; bank < 2; bank++) {
sys/arch/atari/atari/atari_init.c
247
if (bank == 0 && slot == 0) {
sys/arch/atari/atari/atari_init.c
253
mb = milan_probe_bank_1(simm_base[bank][slot]);
sys/arch/atari/atari/atari_init.c
263
mb = milan_probe_bank(simm_base[bank][slot]);
sys/arch/atari/atari/atari_init.c
266
simm_base[bank][slot];
sys/arch/atari/atari/atari_init.c
268
simm_base[bank][slot] + MB(mb);
sys/arch/hpc/stand/hpcboot/memory.cpp
61
struct MemoryManager::bank *b = &_bank[_nbank++];
sys/arch/hpc/stand/hpcboot/memory.h
75
struct bank _bank[MAX_MEM_BANK];
sys/arch/hpcmips/tx/tx3912video.c
397
u_int32_t fb_addr, fb_size, vaddr, bank, base;
sys/arch/hpcmips/tx/tx3912video.c
412
bank = TX3912_VIDEOCTRL3_VIDBANK(fb_addr);
sys/arch/hpcmips/tx/tx3912video.c
414
reg = TX3912_VIDEOCTRL3_VIDBANK_SET(0, bank);
sys/arch/hpcmips/vr/vrgiu.c
476
int bank;
sys/arch/hpcmips/vr/vrgiu.c
483
bank = port < 32 ? 0 : 1;
sys/arch/hpcmips/vr/vrgiu.c
484
if (bank == 1)
sys/arch/hpcmips/vr/vrgiu.c
488
reg[bank] |= (1<<port);
sys/arch/hpcmips/vr/vrgiu.c
490
reg[bank] &= ~(1<<port);
sys/arch/m68k/m68k/pmap_motorola.c
1846
uvm_physseg_t bank;
sys/arch/m68k/m68k/pmap_motorola.c
1854
for (bank = uvm_physseg_get_first();
sys/arch/m68k/m68k/pmap_motorola.c
1855
uvm_physseg_valid_p(bank);
sys/arch/m68k/m68k/pmap_motorola.c
1856
bank = uvm_physseg_get_next(bank)) {
sys/arch/m68k/m68k/pmap_motorola.c
1857
pmap_collect1(pmap_kernel(), ptoa(uvm_physseg_get_start(bank)),
sys/arch/m68k/m68k/pmap_motorola.c
1858
ptoa(uvm_physseg_get_end(bank)));
sys/arch/m68k/m68k/pmap_motorola.c
312
uvm_physseg_t bank = 0; /* XXX gcc4 -Wuninitialized */
sys/arch/m68k/m68k/pmap_motorola.c
315
bank = uvm_physseg_find(atop((pa)), &pg);
sys/arch/m68k/m68k/pmap_motorola.c
316
return &uvm_physseg_get_pmseg(bank)->pvheader[pg];
sys/arch/m68k/m68k/pmap_motorola.c
484
uvm_physseg_t bank;
sys/arch/m68k/m68k/pmap_motorola.c
506
for (page_cnt = 0, bank = uvm_physseg_get_first();
sys/arch/m68k/m68k/pmap_motorola.c
507
uvm_physseg_valid_p(bank);
sys/arch/m68k/m68k/pmap_motorola.c
508
bank = uvm_physseg_get_next(bank))
sys/arch/m68k/m68k/pmap_motorola.c
509
page_cnt += uvm_physseg_get_end(bank) - uvm_physseg_get_start(bank);
sys/arch/m68k/m68k/pmap_motorola.c
535
for (bank = uvm_physseg_get_first();
sys/arch/m68k/m68k/pmap_motorola.c
536
uvm_physseg_valid_p(bank);
sys/arch/m68k/m68k/pmap_motorola.c
537
bank = uvm_physseg_get_next(bank)) {
sys/arch/m68k/m68k/pmap_motorola.c
538
npages = uvm_physseg_get_end(bank) - uvm_physseg_get_start(bank);
sys/arch/m68k/m68k/pmap_motorola.c
539
uvm_physseg_get_pmseg(bank)->pvheader = pvh;
sys/arch/macppc/dev/platinumfb.c
415
uint8_t bank[] = {0, 0, 0};
sys/arch/macppc/dev/platinumfb.c
440
bank[i] = fbuffer[offset] == test_val[i];
sys/arch/macppc/dev/platinumfb.c
441
total_vram += bank[i] * PLATINUM_FB_BANK_SIZE;
sys/arch/mips/cavium/octeon_intr.c
261
int bank;
sys/arch/mips/cavium/octeon_intr.c
285
for (bank = 0; bank < NBANKS; bank++) {
sys/arch/mips/cavium/octeon_intr.c
289
bank,
sys/arch/mips/cavium/octeon_intr.c
290
cpu->cpu_ip2_enable[bank],
sys/arch/mips/cavium/octeon_intr.c
291
cpu->cpu_ip3_enable[bank],
sys/arch/mips/cavium/octeon_intr.c
292
cpu->cpu_ip4_enable[bank]);
sys/arch/mips/cavium/octeon_intr.c
296
for (bank = 0; bank < NBANKS; bank++) {
sys/arch/mips/cavium/octeon_intr.c
297
mips3_sd(cpu->cpu_ip2_en[bank], cpu->cpu_ip2_enable[bank]);
sys/arch/mips/cavium/octeon_intr.c
298
mips3_sd(cpu->cpu_ip3_en[bank], cpu->cpu_ip3_enable[bank]);
sys/arch/mips/cavium/octeon_intr.c
299
mips3_sd(cpu->cpu_ip4_en[bank], cpu->cpu_ip4_enable[bank]);
sys/arch/mips/cavium/octeon_intr.c
370
const int bank = irq / 64;
sys/arch/mips/cavium/octeon_intr.c
376
cpu->cpu_ip2_enable[bank] |= irq_mask;
sys/arch/mips/cavium/octeon_intr.c
377
mips3_sd(cpu->cpu_ip2_en[bank], cpu->cpu_ip2_enable[bank]);
sys/arch/mips/cavium/octeon_intr.c
383
cpu->cpu_ip3_enable[bank] |= irq_mask;
sys/arch/mips/cavium/octeon_intr.c
384
mips3_sd(cpu->cpu_ip3_en[bank], cpu->cpu_ip3_enable[bank]);
sys/arch/mips/cavium/octeon_intr.c
390
cpu->cpu_ip3_enable[bank] |= irq_mask;
sys/arch/mips/cavium/octeon_intr.c
391
mips3_sd(cpu->cpu_ip3_en[bank], cpu->cpu_ip3_enable[bank]);
sys/arch/mips/cavium/octeon_intr.c
400
cpu->cpu_ip4_enable[bank] |= irq_mask;
sys/arch/mips/cavium/octeon_intr.c
401
mips3_sd(cpu->cpu_ip4_en[bank], cpu->cpu_ip4_enable[bank]);
sys/arch/mips/cavium/octeon_intr.c
407
cpu->cpu_ip4_enable[bank] |= irq_mask;
sys/arch/mips/cavium/octeon_intr.c
408
mips3_sd(cpu->cpu_ip4_en[bank], cpu->cpu_ip4_enable[bank]);
sys/arch/mips/cavium/octeon_intr.c
433
const int bank = irq / 64;
sys/arch/mips/cavium/octeon_intr.c
439
cpu->cpu_ip2_enable[bank] &= ~irq_mask;
sys/arch/mips/cavium/octeon_intr.c
440
mips3_sd(cpu->cpu_ip2_en[bank], cpu->cpu_ip2_enable[bank]);
sys/arch/mips/cavium/octeon_intr.c
448
cpu->cpu_ip3_enable[bank] &= ~irq_mask;
sys/arch/mips/cavium/octeon_intr.c
449
mips3_sd(cpu->cpu_ip3_en[bank], cpu->cpu_ip3_enable[bank]);
sys/arch/mips/cavium/octeon_intr.c
459
cpu->cpu_ip4_enable[bank] &= ~irq_mask;
sys/arch/mips/cavium/octeon_intr.c
460
mips3_sd(cpu->cpu_ip4_en[bank], cpu->cpu_ip4_enable[bank]);
sys/arch/mips/cavium/octeon_intr.c
482
int bank;
sys/arch/mips/cavium/octeon_intr.c
506
for (bank = 0; bank <= 1; bank++) {
sys/arch/mips/cavium/octeon_intr.c
507
while (hwpend[bank] != 0) {
sys/arch/mips/cavium/octeon_intr.c
508
const int bit = ffs64(hwpend[bank]) - 1;
sys/arch/mips/cavium/octeon_intr.c
509
const int irq = (bank * 64) + bit;
sys/arch/mips/cavium/octeon_intr.c
510
hwpend[bank] &= ~__BIT(bit);
sys/arch/mips/mips/mips_machdep.c
2094
uvm_physseg_t bank = uvm_physseg_get_last();
sys/arch/mips/mips/mips_machdep.c
2099
for (; uvm_physseg_valid_p(bank); bank = uvm_physseg_get_prev(bank)) {
sys/arch/mips/mips/mips_machdep.c
2100
if (uvm_physseg_get_avail_start(bank) + atop(sz) <= atop(MIPS_PHYS_MASK))
sys/arch/mips/mips/mips_machdep.c
2105
paddr_t start = uvm_physseg_get_start(bank);
sys/arch/mips/mips/mips_machdep.c
2106
paddr_t end = uvm_physseg_get_end(bank);
sys/arch/mips/mips/pmap_machdep.c
325
pmap_md_ok_to_steal_p(const uvm_physseg_t bank, size_t npgs)
sys/arch/mips/mips/pmap_machdep.c
328
if (uvm_physseg_get_avail_start(bank) + npgs >= atop(MIPS_PHYS_MASK + 1)) {
sys/arch/powerpc/ibm4xx/pmap.c
220
uvm_physseg_t bank;
sys/arch/powerpc/ibm4xx/pmap.c
223
bank = uvm_physseg_find(atop(pa), &pg);
sys/arch/powerpc/ibm4xx/pmap.c
224
if (bank == UVM_PHYSSEG_TYPE_INVALID)
sys/arch/powerpc/ibm4xx/pmap.c
226
return &uvm_physseg_get_pmseg(bank)->pvent[pg];
sys/arch/powerpc/ibm4xx/pmap.c
232
uvm_physseg_t bank;
sys/arch/powerpc/ibm4xx/pmap.c
235
bank = uvm_physseg_find(atop(pa), &pg);
sys/arch/powerpc/ibm4xx/pmap.c
236
if (bank == UVM_PHYSSEG_TYPE_INVALID)
sys/arch/powerpc/ibm4xx/pmap.c
238
return &uvm_physseg_get_pmseg(bank)->attrs[pg];
sys/arch/powerpc/ibm4xx/pmap.c
483
int bank, i, s;
sys/arch/powerpc/ibm4xx/pmap.c
500
for (bank = uvm_physseg_get_first(); uvm_physseg_valid_p(bank);
sys/arch/powerpc/ibm4xx/pmap.c
501
bank = uvm_physseg_get_next(bank)) {
sys/arch/powerpc/ibm4xx/pmap.c
502
sz = uvm_physseg_get_end(bank) - uvm_physseg_get_start(bank);
sys/arch/powerpc/ibm4xx/pmap.c
503
uvm_physseg_get_pmseg(bank)->pvent = pv;
sys/arch/powerpc/ibm4xx/pmap.c
504
uvm_physseg_get_pmseg(bank)->attrs = attr;
sys/arch/powerpc/include/booke/pmap.h
167
pmap_md_ok_to_steal_p(const uvm_physseg_t bank, size_t npgs)
sys/arch/powerpc/isa/isadma_machdep.c
166
int error, cookieflags, bank;
sys/arch/powerpc/isa/isadma_machdep.c
171
for (bank = uvm_physseg_get_first();
sys/arch/powerpc/isa/isadma_machdep.c
172
uvm_physseg_valid_p(bank);
sys/arch/powerpc/isa/isadma_machdep.c
173
bank = uvm_physseg_get_next(bank)) {
sys/arch/powerpc/isa/isadma_machdep.c
174
if (avail_end < uvm_physseg_get_avail_end(bank) << PGSHIFT)
sys/arch/powerpc/isa/isadma_machdep.c
175
avail_end = uvm_physseg_get_avail_end(bank) << PGSHIFT;
sys/arch/powerpc/isa/isadma_machdep.c
601
int bank;
sys/arch/powerpc/isa/isadma_machdep.c
603
for (bank = uvm_physseg_get_first();
sys/arch/powerpc/isa/isadma_machdep.c
604
uvm_physseg_valid_p(bank);
sys/arch/powerpc/isa/isadma_machdep.c
605
bank = uvm_physseg_get_next(bank)) {
sys/arch/powerpc/isa/isadma_machdep.c
606
if (avail_end < uvm_physseg_get_avail_end(bank) << PGSHIFT)
sys/arch/powerpc/isa/isadma_machdep.c
607
avail_end = uvm_physseg_get_avail_end(bank) << PGSHIFT;
sys/arch/powerpc/oea/pmap.c
2938
uvm_physseg_t bank;
sys/arch/powerpc/oea/pmap.c
2954
for (bank = uvm_physseg_get_first();
sys/arch/powerpc/oea/pmap.c
2955
uvm_physseg_valid_p(bank);
sys/arch/powerpc/oea/pmap.c
2956
bank = uvm_physseg_get_next(bank)) {
sys/arch/powerpc/oea/pmap.c
2958
freelist = uvm_physseg_get_free_list(bank);
sys/arch/powerpc/oea/pmap.c
2959
start = uvm_physseg_get_start(bank);
sys/arch/powerpc/oea/pmap.c
2960
end = uvm_physseg_get_end(bank);
sys/arch/powerpc/oea/pmap.c
2980
for (bank = uvm_physseg_get_first();
sys/arch/powerpc/oea/pmap.c
2981
uvm_physseg_valid_p(bank);
sys/arch/powerpc/oea/pmap.c
2982
bank = uvm_physseg_get_next(bank)) {
sys/arch/powerpc/oea/pmap.c
2983
cnt += uvm_physseg_get_avail_end(bank) - uvm_physseg_get_avail_start(bank);
sys/arch/powerpc/oea/pmap.c
3445
uvm_physseg_t bank;
sys/arch/powerpc/oea/pmap.c
3447
for (cnt = 0, bank = uvm_physseg_get_first();
sys/arch/powerpc/oea/pmap.c
3448
uvm_physseg_valid_p(bank);
sys/arch/powerpc/oea/pmap.c
3449
bank = uvm_physseg_get_next(bank)) {
sys/arch/powerpc/oea/pmap.c
3450
cnt += uvm_physseg_get_avail_end(bank) -
sys/arch/powerpc/oea/pmap.c
3451
uvm_physseg_get_avail_start(bank);
sys/arch/powerpc/oea/pmap.c
3453
bank,
sys/arch/powerpc/oea/pmap.c
3454
ptoa(uvm_physseg_get_avail_start(bank)),
sys/arch/powerpc/oea/pmap.c
3455
ptoa(uvm_physseg_get_avail_end(bank)),
sys/arch/powerpc/oea/pmap.c
3456
ptoa(uvm_physseg_get_avail_end(bank) - uvm_physseg_get_avail_start(bank)));
sys/arch/powerpc/oea/pmap.c
3477
uvm_physseg_t bank;
sys/arch/powerpc/oea/pmap.c
3482
for (bank = uvm_physseg_get_first();
sys/arch/powerpc/oea/pmap.c
3483
uvm_physseg_valid_p(bank);
sys/arch/powerpc/oea/pmap.c
3484
bank = uvm_physseg_get_next(bank)) {
sys/arch/powerpc/oea/pmap.c
3485
if (uvm_physseg_get_free_list(bank) !=
sys/arch/powerpc/oea/pmap.c
3488
for (pa = uimax(ptoa(uvm_physseg_get_avail_start(bank)),
sys/arch/powerpc/oea/pmap.c
3490
pa < ptoa(uvm_physseg_get_avail_end(bank));
sys/arch/powerpc/oea/pmap.c
3511
int bank;
sys/arch/powerpc/oea/pmap.c
3516
for (bank = 0; bank < vm_nphysseg; bank++) {
sys/arch/powerpc/oea/pmap.c
3517
pa_end = ptoa(VM_PHYSMEM_PTR(bank)->avail_end);
sys/arch/powerpc/oea/pmap.c
3518
pa = ptoa(VM_PHYSMEM_PTR(bank)->avail_start);
sys/arch/powerpc/powerpc/bus_dma.c
674
uvm_physseg_t bank;
sys/arch/powerpc/powerpc/bus_dma.c
676
for (bank = uvm_physseg_get_first();
sys/arch/powerpc/powerpc/bus_dma.c
677
uvm_physseg_valid_p(bank);
sys/arch/powerpc/powerpc/bus_dma.c
678
bank = uvm_physseg_get_next(bank)) {
sys/arch/powerpc/powerpc/bus_dma.c
679
if (start > ptoa(uvm_physseg_get_avail_start(bank)))
sys/arch/powerpc/powerpc/bus_dma.c
680
start = ptoa(uvm_physseg_get_avail_start(bank));
sys/arch/powerpc/powerpc/bus_dma.c
681
if (end < ptoa(uvm_physseg_get_avail_end(bank)))
sys/arch/powerpc/powerpc/bus_dma.c
682
end = ptoa(uvm_physseg_get_avail_end(bank));
sys/arch/riscv/riscv/pmap_machdep.c
182
pmap_md_ok_to_steal_p(const uvm_physseg_t bank, size_t npgs)
sys/arch/riscv/starfive/jh7100_pinctrl.c
393
const uint32_t bank = GPIORD4(sc, GPIO_DIN(pin_no));
sys/arch/riscv/starfive/jh7100_pinctrl.c
394
const uint32_t mask = pin_no % (sizeof(bank) * NBBY);
sys/arch/riscv/starfive/jh7100_pinctrl.c
396
int val = __SHIFTOUT(bank, mask);
sys/arch/riscv/starfive/jh7110_pinctrl.c
647
const uint32_t bank = RD4(sc, sc->sc_jpd->jpd_gpioin + offset);
sys/arch/riscv/starfive/jh7110_pinctrl.c
649
int val = __SHIFTOUT(bank, mask);
sys/arch/riscv/starfive/jh7110_pinctrl.c
676
uint32_t bank = RD4(sc, sc->sc_jpd->jpd_dout + offset);
sys/arch/riscv/starfive/jh7110_pinctrl.c
677
bank &= ~mask;
sys/arch/riscv/starfive/jh7110_pinctrl.c
678
bank |= __SHIFTIN(val != 0 ? GPOUT_HIGH : GPOUT_LOW, mask);
sys/arch/riscv/starfive/jh7110_pinctrl.c
679
WR4(sc, sc->sc_jpd->jpd_dout + offset, bank);
sys/arch/sgimips/sgimips/arcemu.c
621
for (int bank = 0; bank < 4; bank++) {
sys/arch/sgimips/sgimips/arcemu.c
626
switch (bank) {
sys/arch/sgimips/sgimips/arcemu.c
659
sgi_prom_printf("Bank %d: No RAM present\n", bank);
sys/arch/sgimips/sgimips/arcemu.c
663
bank, bp, pc);
sys/arch/sgimips/sgimips/arcemu.c
667
bank, bp, pc);
sys/arch/sh3/sh3/pmap.c
133
uvm_physseg_t bank;
sys/arch/sh3/sh3/pmap.c
140
for (bank = uvm_physseg_get_first();
sys/arch/sh3/sh3/pmap.c
141
uvm_physseg_valid_p(bank);
sys/arch/sh3/sh3/pmap.c
142
bank = uvm_physseg_get_next(bank)) {
sys/arch/sh3/sh3/pmap.c
143
if (npage <= uvm_physseg_get_avail_end(bank)
sys/arch/sh3/sh3/pmap.c
144
- uvm_physseg_get_avail_start(bank))
sys/arch/sh3/sh3/pmap.c
148
KDASSERT(uvm_physseg_valid_p(bank));
sys/arch/sh3/sh3/pmap.c
151
pa = ptoa(uvm_physseg_get_avail_start(bank));
sys/arch/sun3/sun3x/pmap.c
481
struct pmap_physmem_struct *bank;
sys/arch/sun3/sun3x/pmap.c
484
bank = &avail_mem[0];
sys/arch/sun3/sun3x/pmap.c
485
while (pa >= bank->pmem_seg->ps_end)
sys/arch/sun3/sun3x/pmap.c
486
bank = bank->pmem_next;
sys/arch/sun3/sun3x/pmap.c
488
pa -= bank->pmem_seg->ps_start;
sys/arch/sun3/sun3x/pmap.c
489
idx = bank->pmem_pvbase + m68k_btop(pa);
sys/arch/vax/vax/pmap.c
453
uvm_physseg_t bank;
sys/arch/vax/vax/pmap.c
469
bank = uvm_physseg_get_first();
sys/arch/vax/vax/pmap.c
471
v = (uvm_physseg_get_start(bank) << PGSHIFT) | KERNBASE;
sys/arch/vax/vax/pmap.c
472
uvm_physseg_unplug(uvm_physseg_get_start(bank), npgs);
sys/dev/acpi/apei_hest.c
705
ACPI_HEST_IA_ERROR_BANK *const bank = (void *)(imc + 1);
sys/dev/acpi/apei_hest.c
706
if (maxlen < imc->NumHardwareBanks*sizeof(*bank))
sys/dev/acpi/apei_hest.c
708
return (ACPI_HEST_HEADER *)(bank + imc->NumHardwareBanks);
sys/dev/acpi/apei_hest.c
720
ACPI_HEST_IA_ERROR_BANK *const bank = (void *)(imcc + 1);
sys/dev/acpi/apei_hest.c
721
if (maxlen < imcc->NumHardwareBanks*sizeof(*bank))
sys/dev/acpi/apei_hest.c
723
return (ACPI_HEST_HEADER *)(bank + imcc->NumHardwareBanks);
sys/dev/acpi/apei_hest.c
797
ACPI_HEST_IA_ERROR_BANK *const bank = (void *)(imdc + 1);
sys/dev/acpi/apei_hest.c
798
if (maxlen < imdc->NumHardwareBanks*sizeof(*bank))
sys/dev/acpi/apei_hest.c
800
return (ACPI_HEST_HEADER *)(bank + imdc->NumHardwareBanks);
sys/dev/i2c/mcp23xxxgpio_i2c.c
105
mcpgpio_i2c_read(struct mcpgpio_softc *sc, unsigned int bank,
sys/dev/i2c/mcp23xxxgpio_i2c.c
111
KASSERT((bank & ~1U) == 0);
sys/dev/i2c/mcp23xxxgpio_i2c.c
118
mcpgpio_i2c_write(struct mcpgpio_softc *sc, unsigned int bank,
sys/dev/i2c/mcp23xxxgpio_i2c.c
124
KASSERT((bank & ~1U) == 0);
sys/dev/i2c/w83795g.c
143
uint8_t bank, vend, chip, deva;
sys/dev/i2c/w83795g.c
149
iic_smbus_read_byte(ia->ia_tag, ia->ia_addr, W83795G_BANKSEL, &bank, 0);
sys/dev/i2c/w83795g.c
155
if ((bank & BANKSEL_HBACS && vend == VENDOR_NUVOTON_ID_HI) ||
sys/dev/i2c/w83795g.c
156
(~bank & BANKSEL_HBACS && vend == VENDOR_NUVOTON_ID_LO))
sys/dev/ic/advlib.c
752
AscSetBank(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bank)
sys/dev/ic/advlib.c
761
switch (bank) {
sys/dev/ic/interwave.c
298
u_long bank[4] = {0L, 0L, 0L, 0L};
sys/dev/ic/interwave.c
342
bank[i] += RAM_STEP;
sys/dev/ic/interwave.c
350
*lpbanks = bank[i];
sys/dev/ic/interwave.c
353
bank[i] = bank[i] >> 10;
sys/dev/ic/interwave.c
354
printf("%s bank[%d]: %ldK", i ? "," : "", i, bank[i]);
sys/dev/ic/interwavevar.h
35
u_char bank; /* lower 2 bits select one of 4 4M bank for voice data */
sys/dev/ic/mcp23xxxgpio.c
105
return banknames[bank & 1];
sys/dev/ic/mcp23xxxgpio.c
132
uint8_t bank, uint8_t reg, uint8_t *valp)
sys/dev/ic/mcp23xxxgpio.c
135
uint8_t regaddr = mcpgpio_regaddr(sc, bank, reg);
sys/dev/ic/mcp23xxxgpio.c
137
error = sc->sc_accessops->read(sc, bank, regaddr, valp);
sys/dev/ic/mcp23xxxgpio.c
141
mcpgpio_regname(reg), mcpgpio_bankname(sc, bank),
sys/dev/ic/mcp23xxxgpio.c
152
uint8_t bank, uint8_t reg, uint8_t val)
sys/dev/ic/mcp23xxxgpio.c
155
uint8_t regaddr = mcpgpio_regaddr(sc, bank, reg);
sys/dev/ic/mcp23xxxgpio.c
157
error = sc->sc_accessops->write(sc, bank, regaddr, val);
sys/dev/ic/mcp23xxxgpio.c
161
mcpgpio_regname(reg), mcpgpio_bankname(sc, bank),
sys/dev/ic/mcp23xxxgpio.c
182
const uint8_t bank = PIN_BANK(pin);
sys/dev/ic/mcp23xxxgpio.c
189
error = mcpgpio_read(sc, bank, REG_GPIO, &data);
sys/dev/ic/mcp23xxxgpio.c
209
const uint8_t bank = PIN_BANK(pin);
sys/dev/ic/mcp23xxxgpio.c
217
error = mcpgpio_read(sc, bank, REG_OLAT, &data);
sys/dev/ic/mcp23xxxgpio.c
224
(void) mcpgpio_write(sc, bank, REG_OLAT, data);
sys/dev/ic/mcp23xxxgpio.c
239
const uint8_t bank = PIN_BANK(pin);
sys/dev/ic/mcp23xxxgpio.c
248
if ((error = mcpgpio_read(sc, bank, REG_IODIR, &iodir)) != 0 ||
sys/dev/ic/mcp23xxxgpio.c
249
(error = mcpgpio_read(sc, bank, REG_IPOL, &ipol)) != 0 ||
sys/dev/ic/mcp23xxxgpio.c
250
(error = mcpgpio_read(sc, bank, REG_GPPU, &gppu)) != 0) {
sys/dev/ic/mcp23xxxgpio.c
275
(void) mcpgpio_write(sc, bank, REG_IODIR, iodir);
sys/dev/ic/mcp23xxxgpio.c
276
(void) mcpgpio_write(sc, bank, REG_IPOL, ipol);
sys/dev/ic/mcp23xxxgpio.c
277
(void) mcpgpio_write(sc, bank, REG_GPPU, gppu);
sys/dev/ic/mcp23xxxgpio.c
65
mcpgpio_regaddr(struct mcpgpio_softc *sc, uint8_t bank, uint8_t reg)
sys/dev/ic/mcp23xxxgpio.c
72
return REGADDR_BANK1(bank & 1, reg);
sys/dev/ic/mcp23xxxgpio.c
74
return REGADDR_BANK0(bank & 1, reg);
sys/dev/ic/mcp23xxxgpio.c
98
mcpgpio_bankname(struct mcpgpio_softc *sc, uint8_t bank)
sys/dev/ic/mcp23xxxgpioreg.h
104
#define REGADDR_BANK1(bank, reg) (((bank) << 4) | (reg))
sys/dev/ic/mcp23xxxgpioreg.h
107
#define REGADDR_BANK0(bank, reg) (((reg) << 1) | (bank))
sys/dev/ic/nslm7x.c
1006
.bank = 0,
sys/dev/ic/nslm7x.c
1014
.bank = 0,
sys/dev/ic/nslm7x.c
1022
.bank = 0,
sys/dev/ic/nslm7x.c
1030
.bank = 5,
sys/dev/ic/nslm7x.c
1038
.bank = 5,
sys/dev/ic/nslm7x.c
1048
.bank = 0,
sys/dev/ic/nslm7x.c
1056
.bank = 1,
sys/dev/ic/nslm7x.c
1064
.bank = 2,
sys/dev/ic/nslm7x.c
1074
.bank = 0,
sys/dev/ic/nslm7x.c
1082
.bank = 0,
sys/dev/ic/nslm7x.c
1090
.bank = 0,
sys/dev/ic/nslm7x.c
1105
.bank = 0,
sys/dev/ic/nslm7x.c
1113
.bank = 0,
sys/dev/ic/nslm7x.c
1121
.bank = 0,
sys/dev/ic/nslm7x.c
1129
.bank = 0,
sys/dev/ic/nslm7x.c
1137
.bank = 0,
sys/dev/ic/nslm7x.c
1145
.bank = 0,
sys/dev/ic/nslm7x.c
1155
.bank = 0,
sys/dev/ic/nslm7x.c
1163
.bank = 1,
sys/dev/ic/nslm7x.c
1173
.bank = 0,
sys/dev/ic/nslm7x.c
1181
.bank = 0,
sys/dev/ic/nslm7x.c
1189
.bank = 0,
sys/dev/ic/nslm7x.c
1204
.bank = 0,
sys/dev/ic/nslm7x.c
1212
.bank = 0,
sys/dev/ic/nslm7x.c
1220
.bank = 0,
sys/dev/ic/nslm7x.c
1228
.bank = 0,
sys/dev/ic/nslm7x.c
123
.bank = 0,
sys/dev/ic/nslm7x.c
1236
.bank = 0,
sys/dev/ic/nslm7x.c
1244
.bank = 0,
sys/dev/ic/nslm7x.c
1252
.bank = 0,
sys/dev/ic/nslm7x.c
1260
.bank = 0,
sys/dev/ic/nslm7x.c
1268
.bank = 0,
sys/dev/ic/nslm7x.c
1276
.bank = 0,
sys/dev/ic/nslm7x.c
1286
.bank = 0,
sys/dev/ic/nslm7x.c
1294
.bank = 0,
sys/dev/ic/nslm7x.c
1302
.bank = 0,
sys/dev/ic/nslm7x.c
131
.bank = 0,
sys/dev/ic/nslm7x.c
1312
.bank = 0,
sys/dev/ic/nslm7x.c
1320
.bank = 0,
sys/dev/ic/nslm7x.c
1328
.bank = 0,
sys/dev/ic/nslm7x.c
1336
.bank = 0,
sys/dev/ic/nslm7x.c
1344
.bank = 0,
sys/dev/ic/nslm7x.c
1359
.bank = 0,
sys/dev/ic/nslm7x.c
1367
.bank = 0,
sys/dev/ic/nslm7x.c
1375
.bank = 0,
sys/dev/ic/nslm7x.c
1383
.bank = 0,
sys/dev/ic/nslm7x.c
139
.bank = 0,
sys/dev/ic/nslm7x.c
1391
.bank = 0,
sys/dev/ic/nslm7x.c
1399
.bank = 0,
sys/dev/ic/nslm7x.c
1407
.bank = 0,
sys/dev/ic/nslm7x.c
1415
.bank = 0,
sys/dev/ic/nslm7x.c
1423
.bank = 0,
sys/dev/ic/nslm7x.c
1433
.bank = 0,
sys/dev/ic/nslm7x.c
1441
.bank = 0,
sys/dev/ic/nslm7x.c
1449
.bank = 0,
sys/dev/ic/nslm7x.c
1459
.bank = 0,
sys/dev/ic/nslm7x.c
1467
.bank = 0,
sys/dev/ic/nslm7x.c
147
.bank = 0,
sys/dev/ic/nslm7x.c
1475
.bank = 0,
sys/dev/ic/nslm7x.c
1483
.bank = 0,
sys/dev/ic/nslm7x.c
1491
.bank = 0,
sys/dev/ic/nslm7x.c
1499
.bank = 0,
sys/dev/ic/nslm7x.c
1507
.bank = 0,
sys/dev/ic/nslm7x.c
1522
.bank = 0,
sys/dev/ic/nslm7x.c
1530
.bank = 0,
sys/dev/ic/nslm7x.c
1538
.bank = 0,
sys/dev/ic/nslm7x.c
1546
.bank = 0,
sys/dev/ic/nslm7x.c
155
.bank = 0,
sys/dev/ic/nslm7x.c
1554
.bank = 0,
sys/dev/ic/nslm7x.c
1562
.bank = 0,
sys/dev/ic/nslm7x.c
1570
.bank = 0,
sys/dev/ic/nslm7x.c
1580
.bank = 0,
sys/dev/ic/nslm7x.c
1588
.bank = 1,
sys/dev/ic/nslm7x.c
1596
.bank = 2,
sys/dev/ic/nslm7x.c
1606
.bank = 0,
sys/dev/ic/nslm7x.c
1614
.bank = 0,
sys/dev/ic/nslm7x.c
1622
.bank = 0,
sys/dev/ic/nslm7x.c
163
.bank = 0,
sys/dev/ic/nslm7x.c
1637
.bank = 0,
sys/dev/ic/nslm7x.c
1645
.bank = 0,
sys/dev/ic/nslm7x.c
1653
.bank = 0,
sys/dev/ic/nslm7x.c
1661
.bank = 0,
sys/dev/ic/nslm7x.c
1669
.bank = 0,
sys/dev/ic/nslm7x.c
1677
.bank = 0,
sys/dev/ic/nslm7x.c
1685
.bank = 0,
sys/dev/ic/nslm7x.c
1693
.bank = 5,
sys/dev/ic/nslm7x.c
1701
.bank = 5,
sys/dev/ic/nslm7x.c
171
.bank = 0,
sys/dev/ic/nslm7x.c
1711
.bank = 0,
sys/dev/ic/nslm7x.c
1719
.bank = 1,
sys/dev/ic/nslm7x.c
1727
.bank = 2,
sys/dev/ic/nslm7x.c
1737
.bank = 6,
sys/dev/ic/nslm7x.c
1745
.bank = 6,
sys/dev/ic/nslm7x.c
1753
.bank = 6,
sys/dev/ic/nslm7x.c
1761
.bank = 6,
sys/dev/ic/nslm7x.c
1770
.bank = 6,
sys/dev/ic/nslm7x.c
1785
.bank = 0,
sys/dev/ic/nslm7x.c
1793
.bank = 0,
sys/dev/ic/nslm7x.c
1801
.bank = 0,
sys/dev/ic/nslm7x.c
1809
.bank = 0,
sys/dev/ic/nslm7x.c
181
.bank = 0,
sys/dev/ic/nslm7x.c
1817
.bank = 0,
sys/dev/ic/nslm7x.c
1825
.bank = 0,
sys/dev/ic/nslm7x.c
1833
.bank = 0,
sys/dev/ic/nslm7x.c
1841
.bank = 0,
sys/dev/ic/nslm7x.c
1849
.bank = 0,
sys/dev/ic/nslm7x.c
1859
.bank = 0,
sys/dev/ic/nslm7x.c
1867
.bank = 0,
sys/dev/ic/nslm7x.c
1875
.bank = 0,
sys/dev/ic/nslm7x.c
1885
.bank = 0,
sys/dev/ic/nslm7x.c
1893
.bank = 0,
sys/dev/ic/nslm7x.c
1901
.bank = 0,
sys/dev/ic/nslm7x.c
191
.bank = 0,
sys/dev/ic/nslm7x.c
1916
.bank = 4,
sys/dev/ic/nslm7x.c
1924
.bank = 4,
sys/dev/ic/nslm7x.c
1932
.bank = 4,
sys/dev/ic/nslm7x.c
1940
.bank = 4,
sys/dev/ic/nslm7x.c
1948
.bank = 4,
sys/dev/ic/nslm7x.c
1956
.bank = 4,
sys/dev/ic/nslm7x.c
1964
.bank = 4,
sys/dev/ic/nslm7x.c
1972
.bank = 4,
sys/dev/ic/nslm7x.c
1980
.bank = 4,
sys/dev/ic/nslm7x.c
1988
.bank = 4,
sys/dev/ic/nslm7x.c
199
.bank = 0,
sys/dev/ic/nslm7x.c
1996
.bank = 4,
sys/dev/ic/nslm7x.c
2004
.bank = 4,
sys/dev/ic/nslm7x.c
2012
.bank = 4,
sys/dev/ic/nslm7x.c
2020
.bank = 4,
sys/dev/ic/nslm7x.c
2028
.bank = 4,
sys/dev/ic/nslm7x.c
2038
.bank = 4,
sys/dev/ic/nslm7x.c
2046
.bank = 4,
sys/dev/ic/nslm7x.c
2054
.bank = 4,
sys/dev/ic/nslm7x.c
2062
.bank = 4,
sys/dev/ic/nslm7x.c
207
.bank = 0,
sys/dev/ic/nslm7x.c
2070
.bank = 4,
sys/dev/ic/nslm7x.c
2078
.bank = 4,
sys/dev/ic/nslm7x.c
2088
.bank = 4,
sys/dev/ic/nslm7x.c
2096
.bank = 4,
sys/dev/ic/nslm7x.c
2104
.bank = 4,
sys/dev/ic/nslm7x.c
2112
.bank = 4,
sys/dev/ic/nslm7x.c
2120
.bank = 4,
sys/dev/ic/nslm7x.c
2128
.bank = 4,
sys/dev/ic/nslm7x.c
2136
.bank = 4,
sys/dev/ic/nslm7x.c
2188
lm_generic_banksel(struct lm_softc *lmsc, uint8_t bank)
sys/dev/ic/nslm7x.c
2190
(*lmsc->lm_writereg)(lmsc, WB_BANKSEL, bank);
sys/dev/ic/nslm7x.c
222
.bank = 0,
sys/dev/ic/nslm7x.c
230
.bank = 0,
sys/dev/ic/nslm7x.c
238
.bank = 0,
sys/dev/ic/nslm7x.c
246
.bank = 0,
sys/dev/ic/nslm7x.c
254
.bank = 0,
sys/dev/ic/nslm7x.c
262
.bank = 0,
sys/dev/ic/nslm7x.c
270
.bank = 0,
sys/dev/ic/nslm7x.c
2767
uint8_t banksel, bank;
sys/dev/ic/nslm7x.c
2773
banksel = bank = sc->lm_readreg(sc, WB_BANKSEL);
sys/dev/ic/nslm7x.c
2775
if (bank != sc->lm_sensors[i].bank) {
sys/dev/ic/nslm7x.c
2776
bank = sc->lm_sensors[i].bank;
sys/dev/ic/nslm7x.c
2777
lm_generic_banksel(sc, bank);
sys/dev/ic/nslm7x.c
278
.bank = 5,
sys/dev/ic/nslm7x.c
286
.bank = 5,
sys/dev/ic/nslm7x.c
296
.bank = 0,
sys/dev/ic/nslm7x.c
304
.bank = 1,
sys/dev/ic/nslm7x.c
312
.bank = 2,
sys/dev/ic/nslm7x.c
322
.bank = 0,
sys/dev/ic/nslm7x.c
330
.bank = 0,
sys/dev/ic/nslm7x.c
338
.bank = 0,
sys/dev/ic/nslm7x.c
361
.bank = 0,
sys/dev/ic/nslm7x.c
369
.bank = 0,
sys/dev/ic/nslm7x.c
377
.bank = 0,
sys/dev/ic/nslm7x.c
385
.bank = 0,
sys/dev/ic/nslm7x.c
393
.bank = 0,
sys/dev/ic/nslm7x.c
401
.bank = 0,
sys/dev/ic/nslm7x.c
409
.bank = 0,
sys/dev/ic/nslm7x.c
417
.bank = 5,
sys/dev/ic/nslm7x.c
425
.bank = 5,
sys/dev/ic/nslm7x.c
433
.bank = 5,
sys/dev/ic/nslm7x.c
443
.bank = 0,
sys/dev/ic/nslm7x.c
451
.bank = 1,
sys/dev/ic/nslm7x.c
459
.bank = 2,
sys/dev/ic/nslm7x.c
469
.bank = 0,
sys/dev/ic/nslm7x.c
477
.bank = 0,
sys/dev/ic/nslm7x.c
485
.bank = 0,
sys/dev/ic/nslm7x.c
500
.bank = 0,
sys/dev/ic/nslm7x.c
508
.bank = 0,
sys/dev/ic/nslm7x.c
516
.bank = 0,
sys/dev/ic/nslm7x.c
524
.bank = 0,
sys/dev/ic/nslm7x.c
532
.bank = 0,
sys/dev/ic/nslm7x.c
540
.bank = 0,
sys/dev/ic/nslm7x.c
548
.bank = 0,
sys/dev/ic/nslm7x.c
556
.bank = 5,
sys/dev/ic/nslm7x.c
564
.bank = 5,
sys/dev/ic/nslm7x.c
574
.bank = 0,
sys/dev/ic/nslm7x.c
582
.bank = 1,
sys/dev/ic/nslm7x.c
590
.bank = 2,
sys/dev/ic/nslm7x.c
600
.bank = 0,
sys/dev/ic/nslm7x.c
608
.bank = 0,
sys/dev/ic/nslm7x.c
616
.bank = 0,
sys/dev/ic/nslm7x.c
631
.bank = 0,
sys/dev/ic/nslm7x.c
639
.bank = 0,
sys/dev/ic/nslm7x.c
647
.bank = 0,
sys/dev/ic/nslm7x.c
655
.bank = 0,
sys/dev/ic/nslm7x.c
663
.bank = 0,
sys/dev/ic/nslm7x.c
671
.bank = 5,
sys/dev/ic/nslm7x.c
679
.bank = 5,
sys/dev/ic/nslm7x.c
689
.bank = 0,
sys/dev/ic/nslm7x.c
697
.bank = 1,
sys/dev/ic/nslm7x.c
705
.bank = 2,
sys/dev/ic/nslm7x.c
715
.bank = 0,
sys/dev/ic/nslm7x.c
723
.bank = 0,
sys/dev/ic/nslm7x.c
731
.bank = 0,
sys/dev/ic/nslm7x.c
746
.bank = 0,
sys/dev/ic/nslm7x.c
754
.bank = 0,
sys/dev/ic/nslm7x.c
762
.bank = 0,
sys/dev/ic/nslm7x.c
770
.bank = 0,
sys/dev/ic/nslm7x.c
778
.bank = 0,
sys/dev/ic/nslm7x.c
786
.bank = 0,
sys/dev/ic/nslm7x.c
794
.bank = 5,
sys/dev/ic/nslm7x.c
802
.bank = 5,
sys/dev/ic/nslm7x.c
812
.bank = 0,
sys/dev/ic/nslm7x.c
820
.bank = 1,
sys/dev/ic/nslm7x.c
830
.bank = 0,
sys/dev/ic/nslm7x.c
838
.bank = 0,
sys/dev/ic/nslm7x.c
859
.bank = 0,
sys/dev/ic/nslm7x.c
867
.bank = 0,
sys/dev/ic/nslm7x.c
875
.bank = 0,
sys/dev/ic/nslm7x.c
883
.bank = 0,
sys/dev/ic/nslm7x.c
891
.bank = 0,
sys/dev/ic/nslm7x.c
899
.bank = 0,
sys/dev/ic/nslm7x.c
907
.bank = 0,
sys/dev/ic/nslm7x.c
917
.bank = 0,
sys/dev/ic/nslm7x.c
925
.bank = 1,
sys/dev/ic/nslm7x.c
933
.bank = 2,
sys/dev/ic/nslm7x.c
943
.bank = 0,
sys/dev/ic/nslm7x.c
951
.bank = 0,
sys/dev/ic/nslm7x.c
959
.bank = 0,
sys/dev/ic/nslm7x.c
974
.bank = 0,
sys/dev/ic/nslm7x.c
982
.bank = 0,
sys/dev/ic/nslm7x.c
990
.bank = 0,
sys/dev/ic/nslm7x.c
998
.bank = 0,
sys/dev/ic/nslm7xvar.h
181
uint8_t bank;
sys/dev/ic/ug.c
349
uint8_t bank, sens, rv;
sys/dev/ic/ug.c
351
bank = (sensor & 0xFF00) >> 8;
sys/dev/ic/ug.c
354
bus_space_write_1(sc->sc_iot, sc->sc_ioh, UG_DATA, bank);
sys/dev/ic/ug.c
638
ug2_read(struct ug_softc *sc, uint8_t bank, uint8_t offset, uint8_t count,
sys/dev/ic/ug.c
650
bus_space_write_1(iot, ioh, UG_CMD, bank);
sys/dev/mvme/memc.c
572
int syncode, bank, bitnum;
sys/dev/mvme/memc.c
577
bank = (syncode >> MEMECC_SYN_BANK_SHIFT) &MEMECC_SYN_BANK_MASK;
sys/dev/mvme/memc.c
586
addr |= (u_int32_t) (bank << 2);
sys/dev/mvme/memc.c
588
"DRAM Bank %c, Bit#%d", 'A' + bank, bitnum);
sys/dev/pci/if_wm.c
14506
wm_nvm_valid_bank_detect_ich8lan(struct wm_softc *sc, unsigned int *bank)
sys/dev/pci/if_wm.c
14523
*bank = 0;
sys/dev/pci/if_wm.c
14531
*bank = 0;
sys/dev/pci/if_wm.c
14540
*bank = 1;
sys/dev/pci/if_wm.c
14544
"%s: no valid NVM bank present (%u)\n", __func__, *bank);
sys/dev/pci/if_wm.c
14550
*bank = ((eecd & EECD_SEC1VAL) != 0) ? 1 : 0;
sys/dev/pci/if_wm.c
14556
*bank = 0;
sys/dev/pci/if_wm.c
14561
*bank = 0;
sys/dev/pci/if_wm.c
14569
*bank = 1;
sys/dev/pci/qat/qat.c
1006
qat_etr_setup_ring(struct qat_softc *sc, int bank, uint32_t ring,
sys/dev/pci/qat/qat.c
1018
KASSERT(bank < sc->sc_hw.qhw_num_banks);
sys/dev/pci/qat/qat.c
1021
qb = &sc->sc_etr_banks[bank];
sys/dev/pci/qat/qat.c
1032
qr->qr_bank = bank;
sys/dev/pci/qat/qat.c
1039
qr->qr_ev_rxintr_name, "bank%d ring%d rxintr", bank, ring);
sys/dev/pci/qat/qat.c
1041
qr->qr_ev_rxmsg_name, "bank%d ring%d rxmsg", bank, ring);
sys/dev/pci/qat/qat.c
1043
qr->qr_ev_txmsg_name, "bank%d ring%d txmsg", bank, ring);
sys/dev/pci/qat/qat.c
1045
qr->qr_ev_txfull_name, "bank%d ring%d txfull", bank, ring);
sys/dev/pci/qat/qat.c
1072
ring, bank, name, ring_size_bytes,
sys/dev/pci/qat/qat.c
1095
qat_etr_bank_ring_write_4(sc, bank, ring, ETR_RING_CONFIG, ring_config);
sys/dev/pci/qat/qat.c
1098
qat_etr_bank_ring_base_write_8(sc, bank, ring, ring_base);
sys/dev/pci/qat/qat.c
1116
bank, qb->qb_coalescing_time, intr_mask);
sys/dev/pci/qat/qat.c
1117
qat_etr_bank_write_4(sc, bank, ETR_INT_COL_EN,
sys/dev/pci/qat/qat.c
1119
qat_etr_bank_write_4(sc, bank, ETR_INT_COL_CTL,
sys/dev/pci/qat/qat.c
1731
int error, i, bank;
sys/dev/pci/qat/qat.c
1735
bank = qcb->qcb_bank;
sys/dev/pci/qat/qat.c
1738
snprintf(name, QAT_RING_NAME_SIZE, "bank%d sym_tx", bank);
sys/dev/pci/qat/qat.c
1746
snprintf(name, QAT_RING_NAME_SIZE, "bank%d sym_rx", bank);
sys/dev/pci/qat/qat.c
1806
int error, bank, i;
sys/dev/pci/qat/qat.c
1821
for (bank = 0; bank < num_banks; bank++) {
sys/dev/pci/qat/qat.c
1822
struct qat_crypto_bank *qcb = &qcy->qcy_banks[bank];
sys/dev/pci/qat/qat.c
1823
qcb->qcb_bank = bank;
sys/dev/pci/qat/qat.c
2130
qat_dump_ring(int bank, int ring)
sys/dev/pci/qat/qat.c
2133
struct qat_bank *qb = &sc->sc_etr_banks[bank];
sys/dev/pci/qat/qat.c
2139
printf("dumping bank %d ring %d\n", bank, ring);
sys/dev/pci/qat/qat.c
851
qat_etr_bank_init(struct qat_softc *sc, int bank)
sys/dev/pci/qat/qat.c
853
struct qat_bank *qb = &sc->sc_etr_banks[bank];
sys/dev/pci/qat/qat.c
856
KASSERT(bank < sc->sc_hw.qhw_num_banks);
sys/dev/pci/qat/qat.c
861
qb->qb_bank = bank;
sys/dev/pci/qat/qat.c
864
qb->qb_ev_rxintr_name, "bank%d rxintr", bank);
sys/dev/pci/qat/qat.c
870
qat_etr_bank_ring_write_4(sc, bank, i,
sys/dev/pci/qat/qat.c
872
qat_etr_bank_ring_base_write_8(sc, bank, i, 0);
sys/dev/pci/qat/qat.c
885
sc->sc_hw.qhw_init_etr_intr(sc, bank);
sys/dev/pci/qat/qat.c
888
qat_etr_bank_write_4(sc, bank, ETR_INT_REG,
sys/dev/pci/qat/qat.c
892
qat_etr_bank_write_4(sc, bank, ETR_INT_SRCSEL +
sys/dev/pci/qat/qat_c2xxx.c
148
qat_c2xxx_init_etr_intr(struct qat_softc *sc, int bank)
sys/dev/pci/qat/qat_c2xxx.c
156
qat_etr_bank_write_4(sc, bank, ETR_INT_SRCSEL,
sys/dev/pci/qat/qat_c2xxx.c
158
qat_etr_bank_write_4(sc, bank, ETR_INT_SRCSEL_2,
sys/dev/pci/qat/qatvar.h
1055
qat_etr_bank_write_4(struct qat_softc *sc, int bank,
sys/dev/pci/qat/qatvar.h
1059
qat_etr_write_4(sc, sc->sc_hw.qhw_etr_bundle_size * bank + offset,
sys/dev/pci/qat/qatvar.h
1064
qat_etr_bank_read_4(struct qat_softc *sc, int bank,
sys/dev/pci/qat/qatvar.h
1069
sc->sc_hw.qhw_etr_bundle_size * bank + offset);
sys/dev/pci/qat/qatvar.h
1090
qat_etr_bank_ring_write_4(struct qat_softc *sc, int bank, int ring,
sys/dev/pci/qat/qatvar.h
1094
qat_etr_bank_write_4(sc, bank, (ring << 2) + offset, value);
sys/dev/pci/qat/qatvar.h
1098
qat_etr_bank_ring_read_4(struct qat_softc *sc, int bank, int ring,
sys/dev/pci/qat/qatvar.h
1102
return qat_etr_bank_read_4(sc, bank, (ring << 2) * offset);
sys/dev/pci/qat/qatvar.h
1106
qat_etr_bank_ring_base_write_8(struct qat_softc *sc, int bank, int ring,
sys/dev/pci/qat/qatvar.h
1113
qat_etr_bank_ring_write_4(sc, bank, ring, ETR_RING_LBASE, lo);
sys/dev/pci/qat/qatvar.h
1114
qat_etr_bank_ring_write_4(sc, bank, ring, ETR_RING_UBASE, hi);
sys/dev/pci/yds.c
196
#define YDS_DUMP_PLAY_SLOT(n, sc, bank) \
sys/dev/pci/yds.c
197
if (ydsdebug > (n)) yds_dump_play_slot(sc, bank)
sys/dev/pci/yds.c
199
#define YDS_DUMP_PLAY_SLOT(n, sc, bank)
sys/dev/pci/yds.c
281
yds_dump_play_slot(struct yds_softc *sc, int bank)
sys/dev/pci/ydsreg.h
327
struct rec_slot_ctrl_bank bank[N_REC_SLOT_CTRL_BANK];
sys/dev/spi/mcp23xxxgpio_spi.c
138
mcpgpio_spi_read(struct mcpgpio_softc *sc, unsigned int bank,
sys/dev/spi/mcp23xxxgpio_spi.c
144
KASSERT(bank < (sc->sc_npins >> 3));
sys/dev/spi/mcp23xxxgpio_spi.c
146
buf[0] = OP_READ(ssc->sc_ha[bank]);
sys/dev/spi/mcp23xxxgpio_spi.c
153
mcpgpio_spi_write(struct mcpgpio_softc *sc, unsigned int bank,
sys/dev/spi/mcp23xxxgpio_spi.c
159
KASSERT(bank < (sc->sc_npins >> 3));
sys/dev/spi/mcp23xxxgpio_spi.c
161
buf[0] = OP_WRITE(ssc->sc_ha[bank]);
sys/dev/spi/mcp23xxxgpio_spi.c
241
int bank, nchips, error, ha;
sys/dev/spi/mcp23xxxgpio_spi.c
322
for (bank = 0; spi_present_mask != 0; spi_present_mask &= ~__BIT(ha)) {
sys/dev/spi/mcp23xxxgpio_spi.c
326
ha_first = bank * MCPGPIO_PINS_PER_BANK;
sys/dev/spi/mcp23xxxgpio_spi.c
327
ssc->sc_ha[bank++] = ha;
sys/dev/spi/mcp23xxxgpio_spi.c
329
ssc->sc_ha[bank++] = ha;
sys/dev/spi/mcp23xxxgpio_spi.c
331
ha_last = (bank * MCPGPIO_PINS_PER_BANK) - 1;
sys/dev/spi/mcp23xxxgpio_spi.c
335
KASSERT((bank * MCPGPIO_PINS_PER_BANK) == sc->sc_npins);
sys/uvm/pmap/pmap.c
583
for (uvm_physseg_t bank = uvm_physseg_get_first();
sys/uvm/pmap/pmap.c
584
uvm_physseg_valid_p(bank);
sys/uvm/pmap/pmap.c
585
bank = uvm_physseg_get_next(bank)) {
sys/uvm/pmap/pmap.c
591
__func__, bank,
sys/uvm/pmap/pmap.c
592
uvm_physseg_get_avail_start(bank), uvm_physseg_get_start(bank),
sys/uvm/pmap/pmap.c
593
uvm_physseg_get_avail_end(bank), uvm_physseg_get_end(bank));
sys/uvm/pmap/pmap.c
595
if (uvm_physseg_get_avail_start(bank) != uvm_physseg_get_start(bank)
sys/uvm/pmap/pmap.c
596
|| uvm_physseg_get_avail_start(bank) >= uvm_physseg_get_avail_end(bank)) {
sys/uvm/pmap/pmap.c
597
DPRINTF("%s: seg %"PRIxPHYSSEG": bad start\n", __func__, bank);
sys/uvm/pmap/pmap.c
601
if (uvm_physseg_get_avail_end(bank) - uvm_physseg_get_avail_start(bank) < npgs) {
sys/uvm/pmap/pmap.c
603
__func__, bank, npgs);
sys/uvm/pmap/pmap.c
607
if (!pmap_md_ok_to_steal_p(bank, npgs)) {
sys/uvm/pmap/pmap.c
617
|| VM_PHYSMEM_SPACE(bank) < VM_PHYSMEM_SPACE(maybe_bank)) {
sys/uvm/pmap/pmap.c
618
maybe_bank = bank;
sys/uvm/pmap/pmap.c
623
const uvm_physseg_t bank = maybe_bank;
sys/uvm/pmap/pmap.c
628
pa = ptoa(uvm_physseg_get_start(bank));
sys/uvm/pmap/pmap.c
632
__func__, bank, npgs, VM_PHYSMEM_SPACE(bank));
sys/uvm/uvm_page.c
336
uvm_physseg_t bank;
sys/uvm/uvm_page.c
377
for (bank = uvm_physseg_get_first();
sys/uvm/uvm_page.c
378
uvm_physseg_valid_p(bank) ;
sys/uvm/uvm_page.c
379
bank = uvm_physseg_get_next(bank)) {
sys/uvm/uvm_page.c
380
freepages += (uvm_physseg_get_end(bank) - uvm_physseg_get_start(bank));
sys/uvm/uvm_page.c
430
for (bank = uvm_physseg_get_first(),
sys/uvm/uvm_page.c
431
uvm_physseg_seg_chomp_slab(bank, pagearray, pagecount);
sys/uvm/uvm_page.c
432
uvm_physseg_valid_p(bank);
sys/uvm/uvm_page.c
433
bank = uvm_physseg_get_next(bank)) {
sys/uvm/uvm_page.c
435
n = uvm_physseg_get_end(bank) - uvm_physseg_get_start(bank);
sys/uvm/uvm_page.c
436
uvm_physseg_seg_alloc_from_slab(bank, n);
sys/uvm/uvm_page.c
437
uvm_physseg_init_seg(bank, pagearray);
sys/uvm/uvm_pglist.c
574
const uvm_physseg_t bank = uvm_physseg_find(candidate, &cidx);
sys/uvm/uvm_pglist.c
575
KDASSERTMSG(bank == psi,
sys/uvm/uvm_pglist.c
577
candidate, bank, psi);
tests/sys/uvm/t_uvm_physseg.c
436
uvm_physseg_t bank;
tests/sys/uvm/t_uvm_physseg.c
439
for (bank = uvm_physseg_get_first(),
tests/sys/uvm/t_uvm_physseg.c
440
uvm_physseg_seg_chomp_slab(bank, pagearray, pagecount);
tests/sys/uvm/t_uvm_physseg.c
441
uvm_physseg_valid_p(bank);
tests/sys/uvm/t_uvm_physseg.c
442
bank = uvm_physseg_get_next(bank)) {
tests/sys/uvm/t_uvm_physseg.c
444
n = uvm_physseg_get_end(bank) - uvm_physseg_get_start(bank);
tests/sys/uvm/t_uvm_physseg.c
445
uvm_physseg_seg_alloc_from_slab(bank, n);
tests/sys/uvm/t_uvm_physseg.c
446
uvm_physseg_init_seg(bank, pagearray);
tests/sys/uvm/t_uvm_physseg_load.c
257
uvm_physseg_t bank;
tests/sys/uvm/t_uvm_physseg_load.c
260
for (bank = uvm_physseg_get_first(),
tests/sys/uvm/t_uvm_physseg_load.c
261
uvm_physseg_seg_chomp_slab(bank, pagearray, pagecount);
tests/sys/uvm/t_uvm_physseg_load.c
262
uvm_physseg_valid_p(bank);
tests/sys/uvm/t_uvm_physseg_load.c
263
bank = uvm_physseg_get_next(bank)) {
tests/sys/uvm/t_uvm_physseg_load.c
265
n = uvm_physseg_get_end(bank) - uvm_physseg_get_start(bank);
tests/sys/uvm/t_uvm_physseg_load.c
266
uvm_physseg_seg_alloc_from_slab(bank, n);
tests/sys/uvm/t_uvm_physseg_load.c
267
uvm_physseg_init_seg(bank, pagearray);
usr.sbin/acpitools/acpidump/acpi.c
335
acpi_print_hest_errorbank(ACPI_HEST_IA_ERROR_BANK *bank)
usr.sbin/acpitools/acpidump/acpi.c
338
printf("\tBank Number=%d\n", bank->BankNumber);
usr.sbin/acpitools/acpidump/acpi.c
340
bank->ClearStatusOnInit ? "NO" : "YES");
usr.sbin/acpitools/acpidump/acpi.c
342
switch (bank->StatusFormat) {
usr.sbin/acpitools/acpidump/acpi.c
355
if (bank->ControlRegister)
usr.sbin/acpitools/acpidump/acpi.c
356
printf("\tControl Register=0x%x\n", bank->ControlRegister);
usr.sbin/acpitools/acpidump/acpi.c
357
printf("\tControl Init Data=0x%"PRIx64"\n", bank->ControlData);
usr.sbin/acpitools/acpidump/acpi.c
358
printf("\tStatus MSR=0x%x\n", bank->StatusRegister);
usr.sbin/acpitools/acpidump/acpi.c
359
printf("\tAddress MSR=0x%x\n", bank->AddressRegister);
usr.sbin/acpitools/acpidump/acpi.c
360
printf("\tMisc MSR=0x%x\n", bank->MiscRegister);
usr.sbin/acpitools/acpidump/acpi.c
598
ACPI_HEST_IA_ERROR_BANK *bank;
usr.sbin/acpitools/acpidump/acpi.c
619
bank = (ACPI_HEST_IA_ERROR_BANK *)((char *)data + pos);
usr.sbin/acpitools/acpidump/acpi.c
620
acpi_print_hest_errorbank(bank);
usr.sbin/acpitools/acpidump/acpi.c
629
ACPI_HEST_IA_ERROR_BANK *bank;
usr.sbin/acpitools/acpidump/acpi.c
648
bank = (ACPI_HEST_IA_ERROR_BANK *)((char *)data + pos);
usr.sbin/acpitools/acpidump/acpi.c
649
acpi_print_hest_errorbank(bank);
