arch/alpha/include/asm/io.h
264
extern void __raw_writel(u32 b, volatile void __iomem *addr);
arch/alpha/include/asm/io.h
272
#define __raw_writel __raw_writel
arch/alpha/include/asm/io.h
531
__raw_writel(b, addr);
arch/alpha/kernel/io.c
169
EXPORT_SYMBOL(__raw_writel);
arch/alpha/kernel/io.c
223
__raw_writel(b, addr);
arch/alpha/kernel/io.c
558
__raw_writel(*(const u32 *)from, to);
arch/alpha/kernel/io.c
610
__raw_writel(c, to);
arch/alpha/kernel/io.c
629
__raw_writel(c, to);
arch/arc/include/asm/io.h
144
#define __raw_writel __raw_writel
arch/arc/include/asm/io.h
227
#define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
arch/arc/include/asm/io.h
43
#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force u32)cpu_to_be32(v), p); })
arch/arm/boot/compressed/misc-ep93xx.h
38
__raw_writel(v | ETH_SELF_CTL_RESET, PHYS_ETH_SELF_CTL);
arch/arm/include/asm/hardware/iomd.h
23
#define iomd_writel(val,off) __raw_writel(val, IOMD_BASE + (off))
arch/arm/include/asm/io.h
238
#define outl(v,p) ({ __iowmb(); __raw_writel((__force __u32) \
arch/arm/include/asm/io.h
282
#define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
arch/arm/include/asm/io.h
394
#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
arch/arm/include/asm/io.h
92
#define __raw_writel __raw_writel
arch/arm/kernel/v7m.c
13
__raw_writel(V7M_SCB_AIRCR_VECTKEY | V7M_SCB_AIRCR_SYSRESETREQ,
arch/arm/mach-aspeed/platsmp.c
51
__raw_writel(0xBADABABA, base + BOOT_SIG);
arch/arm/mach-at91/pm.c
170
__raw_writel(value, soc_pm.data.ramc[id] + field)
arch/arm/mach-davinci/mux.c
80
__raw_writel(reg, pinmux_base + cfg->mux_reg);
arch/arm/mach-davinci/pm.c
52
__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
arch/arm/mach-davinci/pm.c
59
__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
arch/arm/mach-davinci/pm.c
66
__raw_writel(val, pm_config.deepsleep_reg);
arch/arm/mach-davinci/pm.c
76
__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
arch/arm/mach-davinci/pm.c
81
__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
arch/arm/mach-davinci/pm.c
89
__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
arch/arm/mach-davinci/pm.c
98
__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
arch/arm/mach-exynos/mcpm-exynos.c
226
__raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */
arch/arm/mach-exynos/mcpm-exynos.c
227
__raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */
arch/arm/mach-exynos/mcpm-exynos.c
228
__raw_writel(__pa_symbol(mcpm_entry_point), ns_sram_base_addr + 8);
arch/arm/mach-lpc32xx/common.c
47
__raw_writel(savedval2 + 1, iramptr2);
arch/arm/mach-lpc32xx/common.c
52
__raw_writel(savedval2, iramptr2);
arch/arm/mach-lpc32xx/common.c
73
__raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
arch/arm/mach-lpc32xx/pm.c
129
__raw_writel(__raw_readl(EMC_CTRL_REG) | EMC_SRMMC, EMC_CTRL_REG);
arch/arm/mach-lpc32xx/serial.c
110
__raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg);
arch/arm/mach-lpc32xx/serial.c
117
__raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
arch/arm/mach-lpc32xx/serial.c
118
__raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
arch/arm/mach-lpc32xx/serial.c
123
__raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
arch/arm/mach-lpc32xx/serial.c
127
__raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
arch/arm/mach-lpc32xx/serial.c
131
__raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
arch/arm/mach-lpc32xx/serial.c
132
__raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
arch/arm/mach-lpc32xx/serial.c
136
__raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
arch/arm/mach-lpc32xx/serial.c
142
__raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
arch/arm/mach-lpc32xx/serial.c
147
__raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
arch/arm/mach-mmp/platsmp.c
19
__raw_writel(__pa_symbol(secondary_startup), SW_BRANCH_VIRT_ADDR);
arch/arm/mach-mmp/time.c
103
__raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0));
arch/arm/mach-mmp/time.c
108
__raw_writel(0x03, mmp_timer_base + TMR_CER);
arch/arm/mach-mmp/time.c
121
__raw_writel(0x00, mmp_timer_base + TMR_IER(0));
arch/arm/mach-mmp/time.c
153
__raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */
arch/arm/mach-mmp/time.c
158
__raw_writel(ccr, mmp_timer_base + TMR_CCR);
arch/arm/mach-mmp/time.c
161
__raw_writel(0x2, mmp_timer_base + TMR_CMR);
arch/arm/mach-mmp/time.c
163
__raw_writel(0x1, mmp_timer_base + TMR_PLCR(0)); /* periodic */
arch/arm/mach-mmp/time.c
164
__raw_writel(0x7, mmp_timer_base + TMR_ICR(0)); /* clear status */
arch/arm/mach-mmp/time.c
165
__raw_writel(0x0, mmp_timer_base + TMR_IER(0));
arch/arm/mach-mmp/time.c
167
__raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */
arch/arm/mach-mmp/time.c
168
__raw_writel(0x7, mmp_timer_base + TMR_ICR(1)); /* clear status */
arch/arm/mach-mmp/time.c
169
__raw_writel(0x0, mmp_timer_base + TMR_IER(1));
arch/arm/mach-mmp/time.c
172
__raw_writel(0x2, mmp_timer_base + TMR_CER);
arch/arm/mach-mmp/time.c
50
__raw_writel(1, mmp_timer_base + TMR_CVWR(1));
arch/arm/mach-mmp/time.c
70
__raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
arch/arm/mach-mmp/time.c
75
__raw_writel(0x02, mmp_timer_base + TMR_CER);
arch/arm/mach-mmp/time.c
92
__raw_writel(0x02, mmp_timer_base + TMR_CER);
arch/arm/mach-mmp/time.c
97
__raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
arch/arm/mach-mmp/time.c
98
__raw_writel(0x01, mmp_timer_base + TMR_IER(0));
arch/arm/mach-mvebu/pmsu.c
150
__raw_writel((unsigned long)resume_addr_reg,
arch/arm/mach-mxs/mach-mxs.c
63
__raw_writel(mask, reg + MXS_SET_ADDR);
arch/arm/mach-mxs/mach-mxs.c
68
__raw_writel(mask, reg + MXS_CLR_ADDR);
arch/arm/mach-mxs/mach-mxs.c
73
__raw_writel(mask, reg + MXS_TOG_ADDR);
arch/arm/mach-omap1/clock.c
396
__raw_writel(val, clk->enable_reg);
arch/arm/mach-omap1/clock.c
555
__raw_writel(regval32, clk->enable_reg);
arch/arm/mach-omap1/clock.c
600
__raw_writel(regval32, clk->enable_reg);
arch/arm/mach-omap1/gpio16xx.c
243
__raw_writel(SYSCONFIG_WORD, base + OMAP1610_GPIO_SYSCONFIG);
arch/arm/mach-omap1/io.c
107
__raw_writel(v, OMAP1_IO_ADDRESS(pa));
arch/arm/mach-orion5x/pci.c
308
__raw_writel(val, PCI_CONF_DATA);
arch/arm/mach-pxa/generic.c
62
__raw_writel(mcmem, MCMEM(sock));
arch/arm/mach-pxa/generic.c
63
__raw_writel(mcatt, MCATT(sock));
arch/arm/mach-pxa/generic.c
64
__raw_writel(mcio, MCIO(sock));
arch/arm/mach-pxa/generic.c
72
__raw_writel(0, MECR);
arch/arm/mach-pxa/generic.c
79
__raw_writel(MECR_CIT, MECR);
arch/arm/mach-pxa/generic.c
83
__raw_writel(MECR_CIT | MECR_NOS, MECR);
arch/arm/mach-pxa/irq.c
129
__raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw));
arch/arm/mach-pxa/irq.c
159
__raw_writel(0, base + ICMR); /* disable all IRQs */
arch/arm/mach-pxa/irq.c
160
__raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */
arch/arm/mach-pxa/irq.c
163
__raw_writel(1, irq_base(0) + ICCR);
arch/arm/mach-pxa/irq.c
189
__raw_writel(0, base + ICMR);
arch/arm/mach-pxa/irq.c
207
__raw_writel(saved_icmr[i], base + ICMR);
arch/arm/mach-pxa/irq.c
208
__raw_writel(0, base + ICLR);
arch/arm/mach-pxa/irq.c
213
__raw_writel(saved_ipr[i], pxa_irq_base + IPR(i));
arch/arm/mach-pxa/irq.c
215
__raw_writel(1, pxa_irq_base + ICCR);
arch/arm/mach-pxa/irq.c
72
__raw_writel(icmr, base + ICMR);
arch/arm/mach-pxa/irq.c
82
__raw_writel(icmr, base + ICMR);
arch/arm/mach-pxa/pxa27x.c
113
__raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR);
arch/arm/mach-pxa/smemc.c
37
__raw_writel(msc[0], MSC0);
arch/arm/mach-pxa/smemc.c
38
__raw_writel(msc[1], MSC1);
arch/arm/mach-pxa/smemc.c
39
__raw_writel(sxcnfg, SXCNFG);
arch/arm/mach-pxa/smemc.c
40
__raw_writel(memclkcfg, MEMCLKCFG);
arch/arm/mach-pxa/smemc.c
41
__raw_writel(csadrcfg[0], CSADRCFG0);
arch/arm/mach-pxa/smemc.c
42
__raw_writel(csadrcfg[1], CSADRCFG1);
arch/arm/mach-pxa/smemc.c
43
__raw_writel(csadrcfg[2], CSADRCFG2);
arch/arm/mach-pxa/smemc.c
44
__raw_writel(csadrcfg[3], CSADRCFG3);
arch/arm/mach-pxa/smemc.c
46
__raw_writel(0x2, CSMSADRCFG);
arch/arm/mach-pxa/smemc.c
69
__raw_writel(0x2, CSMSADRCFG);
arch/arm/mach-pxa/spitz.c
1085
__raw_writel((msc0 & 0xffff) | 0x7ee00000, MSC0);
arch/arm/mach-rpc/include/mach/hardware.h
57
#define vidc_writel(val) __raw_writel(val, VIDC_BASE)
arch/arm/mach-s3c/cpuidle-s3c64xx.c
31
__raw_writel(tmp, S3C64XX_PWR_CFG);
arch/arm/mach-s3c/gpio-samsung.c
149
__raw_writel(con, reg);
arch/arm/mach-s3c/gpio-samsung.c
257
__raw_writel(con, base + 0x00);
arch/arm/mach-s3c/gpio-samsung.c
278
__raw_writel(dat, base + 0x04);
arch/arm/mach-s3c/gpio-samsung.c
284
__raw_writel(con, base + 0x00);
arch/arm/mach-s3c/gpio-samsung.c
285
__raw_writel(dat, base + 0x04);
arch/arm/mach-s3c/gpio-samsung.c
319
__raw_writel(con, base + GPIOCON_OFF);
arch/arm/mach-s3c/gpio-samsung.c
345
__raw_writel(dat, base + GPIODAT_OFF);
arch/arm/mach-s3c/gpio-samsung.c
346
__raw_writel(con, base + GPIOCON_OFF);
arch/arm/mach-s3c/gpio-samsung.c
347
__raw_writel(dat, base + GPIODAT_OFF);
arch/arm/mach-s3c/gpio-samsung.c
391
__raw_writel(con, regcon);
arch/arm/mach-s3c/gpio-samsung.c
424
__raw_writel(dat, base + GPIODAT_OFF);
arch/arm/mach-s3c/gpio-samsung.c
425
__raw_writel(con, regcon);
arch/arm/mach-s3c/gpio-samsung.c
426
__raw_writel(dat, base + GPIODAT_OFF);
arch/arm/mach-s3c/gpio-samsung.c
447
__raw_writel(dat, base + 0x04);
arch/arm/mach-s3c/gpio-samsung.c
50
__raw_writel(pup, reg);
arch/arm/mach-s3c/gpio-samsung.c
86
__raw_writel(con, reg);
arch/arm/mach-s3c/irq-pm-s3c64xx.c
92
__raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM);
arch/arm/mach-s3c/irq-pm-s3c64xx.c
95
__raw_writel(grp->con, S3C64XX_EINT12CON + (i * 4));
arch/arm/mach-s3c/irq-pm-s3c64xx.c
96
__raw_writel(grp->mask, S3C64XX_EINT12MASK + (i * 4));
arch/arm/mach-s3c/irq-pm-s3c64xx.c
97
__raw_writel(grp->fltcon, S3C64XX_EINT12FLTCON + (i * 4));
arch/arm/mach-s3c/pm-core-s3c64xx.h
30
__raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND);
arch/arm/mach-s3c/pm-core-s3c64xx.h
55
__raw_writel(0, S3C64XX_SLPEN);
arch/arm/mach-s3c/pm-core-s3c64xx.h
65
__raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN);
arch/arm/mach-s3c/pm-gpio.c
132
__raw_writel(chip->pm_save[2], base + OFFS_UP);
arch/arm/mach-s3c/pm-gpio.c
175
__raw_writel(gpcon, base + OFFS_CON);
arch/arm/mach-s3c/pm-gpio.c
179
__raw_writel(gps_gpdat, base + OFFS_DAT);
arch/arm/mach-s3c/pm-gpio.c
180
__raw_writel(gps_gpcon, base + OFFS_CON);
arch/arm/mach-s3c/pm-gpio.c
253
__raw_writel(gpcon, con);
arch/arm/mach-s3c/pm-gpio.c
276
__raw_writel(chip->pm_save[2], base + OFFS_DAT);
arch/arm/mach-s3c/pm-gpio.c
277
__raw_writel(chip->pm_save[1], base + OFFS_CON);
arch/arm/mach-s3c/pm-gpio.c
279
__raw_writel(chip->pm_save[0], base - 4);
arch/arm/mach-s3c/pm-gpio.c
281
__raw_writel(chip->pm_save[2], base + OFFS_DAT);
arch/arm/mach-s3c/pm-gpio.c
282
__raw_writel(chip->pm_save[3], base + OFFS_UP);
arch/arm/mach-s3c/pm-gpio.c
48
__raw_writel(gpcon, base + OFFS_CON);
arch/arm/mach-s3c/pm-gpio.c
52
__raw_writel(gps_gpdat, base + OFFS_DAT);
arch/arm/mach-s3c/pm-gpio.c
53
__raw_writel(gps_gpcon, base + OFFS_CON);
arch/arm/mach-s3c/pm-s3c64xx.c
203
__raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK);
arch/arm/mach-s3c/pm-s3c64xx.c
208
__raw_writel(0, S3C64XX_EINT_MASK);
arch/arm/mach-s3c/pm-s3c64xx.c
235
__raw_writel(tmp, S3C64XX_PWR_CFG);
arch/arm/mach-s3c/pm-s3c64xx.c
239
__raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT),
arch/arm/mach-s3c/pm-s3c64xx.c
280
__raw_writel(__pa_symbol(s3c_cpu_resume), S3C64XX_INFORM0);
arch/arm/mach-s3c/pm-s3c64xx.c
283
__raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
arch/arm/mach-s3c/pm-s3c64xx.c
50
__raw_writel(val, S3C64XX_NORMAL_CFG);
arch/arm/mach-s3c/pm-s3c64xx.c
65
__raw_writel(val, S3C64XX_NORMAL_CFG);
arch/arm/mach-s3c/s3c64xx.c
245
__raw_writel(mask, S3C64XX_EINT0MASK);
arch/arm/mach-s3c/s3c64xx.c
254
__raw_writel(mask, S3C64XX_EINT0MASK);
arch/arm/mach-s3c/s3c64xx.c
259
__raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
arch/arm/mach-s3c/s3c64xx.c
325
__raw_writel(ctrl, reg);
arch/arm/mach-s3c/wakeup-mask.c
41
__raw_writel(val, reg);
arch/arm/mach-s5pv210/pm.c
112
__raw_writel(s5pv210_irqwake_intmask, S5P_WAKEUP_MASK);
arch/arm/mach-s5pv210/pm.c
115
__raw_writel(__pa_symbol(s5pv210_cpu_resume), S5P_INFORM0);
arch/arm/mach-s5pv210/pm.c
119
__raw_writel(tmp, S5P_SLEEP_CFG);
arch/arm/mach-s5pv210/pm.c
125
__raw_writel(tmp, S5P_PWR_CFG);
arch/arm/mach-s5pv210/pm.c
130
__raw_writel(tmp, S5P_OTHERS);
arch/arm/mach-s5pv210/s5pv210.c
51
__raw_writel(0x1, S5P_SWRESET);
arch/arm/mach-spear/platsmp.c
122
__raw_writel(__pa_symbol(spear13xx_secondary_startup), SYS_LOCATION);
arch/arm/mach-sti/platsmp.c
40
__raw_writel(entry_pa, cpu_strt_ptr);
arch/arm/mm/cache-b15-rac.c
66
__raw_writel(0, b15_rac_base + RAC_CONFIG0_REG);
arch/arm/mm/cache-b15-rac.c
75
__raw_writel(FLUSH_RAC, b15_rac_base + rac_flush_offset);
arch/arm/mm/cache-b15-rac.c
97
__raw_writel(val, b15_rac_base + RAC_CONFIG0_REG);
arch/arm64/include/asm/io.h
181
__raw_writel(*from, to);
arch/arm64/include/asm/io.h
303
#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
arch/arm64/include/asm/io.h
39
#define __raw_writel __raw_writel
arch/hexagon/include/asm/io.h
115
#define __raw_writel __raw_writel
arch/m68k/coldfire/dma_timer.c
61
__raw_writel(0x00000000, DTRR0);
arch/m68k/coldfire/intc-2.c
198
__raw_writel(0x1, MCFICM_INTC0 + MCFINTC_IMRL);
arch/m68k/coldfire/intc-2.c
200
__raw_writel(0x1, MCFICM_INTC1 + MCFINTC_IMRL);
arch/m68k/coldfire/intc-2.c
65
__raw_writel(val | imrbit, imraddr);
arch/m68k/coldfire/intc-2.c
87
__raw_writel(val & ~imrbit, imraddr);
arch/m68k/coldfire/intc.c
73
__raw_writel(imr | (0x1 << index), MCFSIM_IMR);
arch/m68k/coldfire/intc.c
80
__raw_writel(imr & ~(0x1 << index), MCFSIM_IMR);
arch/m68k/coldfire/intc.c
88
__raw_writel(imr, MCFSIM_IMR);
arch/m68k/coldfire/m5441x.c
204
__raw_writel(__raw_readl(MCFSDHC_CLK) | (1 << clk->slot), MCFSDHC_CLK);
arch/m68k/coldfire/m5441x.c
209
__raw_writel(__raw_readl(MCFSDHC_CLK) & ~(1 << clk->slot), MCFSDHC_CLK);
arch/m68k/coldfire/m54xx.c
82
__raw_writel(0, MCF_GPT_GMS0);
arch/m68k/coldfire/m54xx.c
83
__raw_writel(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0);
arch/m68k/coldfire/m54xx.c
84
__raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
arch/m68k/coldfire/pci.c
103
__raw_writel(PCICAR_E | addr, PCICAR);
arch/m68k/coldfire/pci.c
115
__raw_writel(cpu_to_le32(value), addr);
arch/m68k/coldfire/pci.c
119
__raw_writel(0, PCICAR);
arch/m68k/coldfire/pci.c
178
__raw_writel(PCIGSCR_RESET, PCIGSCR);
arch/m68k/coldfire/pci.c
179
__raw_writel(0, PCITCR);
arch/m68k/coldfire/pci.c
185
__raw_writel(PACR_INTMPRI | PACR_INTMINTE | PACR_EXTMPRI(0x1f) |
arch/m68k/coldfire/pci.c
193
__raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
arch/m68k/coldfire/pci.c
195
__raw_writel(PCICR1_LT(32) | PCICR1_CL(8), PCICR1);
arch/m68k/coldfire/pci.c
196
__raw_writel(0, PCICR2);
arch/m68k/coldfire/pci.c
203
__raw_writel(WXBTAR(PCI_MEM_PA, PCI_MEM_BA, PCI_MEM_SIZE),
arch/m68k/coldfire/pci.c
205
__raw_writel(WXBTAR(PCI_IO_PA, PCI_IO_BA, PCI_IO_SIZE),
arch/m68k/coldfire/pci.c
207
__raw_writel(PCIIWCR_W0_MEM /*| PCIIWCR_W0_MRDL*/ | PCIIWCR_W0_E |
arch/m68k/coldfire/pci.c
214
__raw_writel(CONFIG_RAMBASE, PCIBAR1);
arch/m68k/coldfire/pci.c
215
__raw_writel(CONFIG_RAMBASE | PCITBATR1_E, PCITBATR1);
arch/m68k/coldfire/pci.c
227
__raw_writel(0, PCIGSCR);
arch/m68k/coldfire/pci.c
71
__raw_writel(PCICAR_E | addr, PCICAR);
arch/m68k/coldfire/pci.c
87
__raw_writel(0, PCICAR);
arch/m68k/coldfire/sltimers.c
132
__raw_writel(mcfslt_cycles_per_jiffy - 1, TA(MCFSLT_STCNT));
arch/m68k/coldfire/sltimers.c
133
__raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
arch/m68k/coldfire/sltimers.c
47
__raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, PA(MCFSLT_SSR));
arch/m68k/coldfire/sltimers.c
68
__raw_writel(MCF_BUSCLK / PROFILEHZ - 1, PA(MCFSLT_STCNT));
arch/m68k/coldfire/sltimers.c
69
__raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
arch/m68k/coldfire/sltimers.c
89
__raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, TA(MCFSLT_SSR));
arch/m68k/coldfire/timers.c
42
#define __raw_writetrr __raw_writel
arch/m68k/include/asm/io_no.h
106
#define writel __raw_writel
arch/m68k/include/asm/io_no.h
94
__raw_writel(value, addr);
arch/m68k/include/asm/io_no.h
96
__raw_writel(swab32(value), addr);
arch/m68k/include/asm/mcfgpio.h
117
#define mcfgpio_write(data, port) __raw_writel(data, port)
arch/microblaze/include/asm/io.h
38
#define out_be32(a, v) __raw_writel((v), (void __iomem __force *)(a))
arch/microblaze/include/asm/io.h
48
#define out_le32(a, v) __raw_writel(__cpu_to_le32(v), (a))
arch/mips/alchemy/board-xxs1500.c
68
__raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18));
arch/mips/alchemy/common/dbdma.c
1007
__raw_writel(alchemy_dbdma_pm_data[i][0] & ~1, addr + 0x00);
arch/mips/alchemy/common/dbdma.c
1016
__raw_writel(0, addr + 0x0c);
arch/mips/alchemy/common/dbdma.c
1028
__raw_writel(alchemy_dbdma_pm_data[0][0], addr + 0x00);
arch/mips/alchemy/common/dbdma.c
1029
__raw_writel(alchemy_dbdma_pm_data[0][1], addr + 0x04);
arch/mips/alchemy/common/dbdma.c
1030
__raw_writel(alchemy_dbdma_pm_data[0][2], addr + 0x08);
arch/mips/alchemy/common/dbdma.c
1031
__raw_writel(alchemy_dbdma_pm_data[0][3], addr + 0x0c);
arch/mips/alchemy/common/dbdma.c
1036
__raw_writel(alchemy_dbdma_pm_data[i][0], addr + 0x00);
arch/mips/alchemy/common/dbdma.c
1037
__raw_writel(alchemy_dbdma_pm_data[i][1], addr + 0x04);
arch/mips/alchemy/common/dbdma.c
1038
__raw_writel(alchemy_dbdma_pm_data[i][2], addr + 0x08);
arch/mips/alchemy/common/dbdma.c
1039
__raw_writel(alchemy_dbdma_pm_data[i][3], addr + 0x0c);
arch/mips/alchemy/common/dbdma.c
1040
__raw_writel(alchemy_dbdma_pm_data[i][4], addr + 0x10);
arch/mips/alchemy/common/dbdma.c
1041
__raw_writel(alchemy_dbdma_pm_data[i][5], addr + 0x14);
arch/mips/alchemy/common/irq.c
293
__raw_writel(1 << bit, base + IC_MASKSET);
arch/mips/alchemy/common/irq.c
294
__raw_writel(1 << bit, base + IC_WAKESET);
arch/mips/alchemy/common/irq.c
303
__raw_writel(1 << bit, base + IC_MASKSET);
arch/mips/alchemy/common/irq.c
304
__raw_writel(1 << bit, base + IC_WAKESET);
arch/mips/alchemy/common/irq.c
313
__raw_writel(1 << bit, base + IC_MASKCLR);
arch/mips/alchemy/common/irq.c
314
__raw_writel(1 << bit, base + IC_WAKECLR);
arch/mips/alchemy/common/irq.c
323
__raw_writel(1 << bit, base + IC_MASKCLR);
arch/mips/alchemy/common/irq.c
324
__raw_writel(1 << bit, base + IC_WAKECLR);
arch/mips/alchemy/common/irq.c
337
__raw_writel(1 << bit, base + IC_FALLINGCLR);
arch/mips/alchemy/common/irq.c
338
__raw_writel(1 << bit, base + IC_RISINGCLR);
arch/mips/alchemy/common/irq.c
351
__raw_writel(1 << bit, base + IC_FALLINGCLR);
arch/mips/alchemy/common/irq.c
352
__raw_writel(1 << bit, base + IC_RISINGCLR);
arch/mips/alchemy/common/irq.c
361
__raw_writel(1 << bit, base + IC_WAKECLR);
arch/mips/alchemy/common/irq.c
362
__raw_writel(1 << bit, base + IC_MASKCLR);
arch/mips/alchemy/common/irq.c
363
__raw_writel(1 << bit, base + IC_RISINGCLR);
arch/mips/alchemy/common/irq.c
364
__raw_writel(1 << bit, base + IC_FALLINGCLR);
arch/mips/alchemy/common/irq.c
373
__raw_writel(1 << bit, base + IC_WAKECLR);
arch/mips/alchemy/common/irq.c
374
__raw_writel(1 << bit, base + IC_MASKCLR);
arch/mips/alchemy/common/irq.c
375
__raw_writel(1 << bit, base + IC_RISINGCLR);
arch/mips/alchemy/common/irq.c
376
__raw_writel(1 << bit, base + IC_FALLINGCLR);
arch/mips/alchemy/common/irq.c
452
__raw_writel(1 << bit, base + IC_CFG2CLR);
arch/mips/alchemy/common/irq.c
453
__raw_writel(1 << bit, base + IC_CFG1CLR);
arch/mips/alchemy/common/irq.c
454
__raw_writel(1 << bit, base + IC_CFG0SET);
arch/mips/alchemy/common/irq.c
459
__raw_writel(1 << bit, base + IC_CFG2CLR);
arch/mips/alchemy/common/irq.c
460
__raw_writel(1 << bit, base + IC_CFG1SET);
arch/mips/alchemy/common/irq.c
461
__raw_writel(1 << bit, base + IC_CFG0CLR);
arch/mips/alchemy/common/irq.c
466
__raw_writel(1 << bit, base + IC_CFG2CLR);
arch/mips/alchemy/common/irq.c
467
__raw_writel(1 << bit, base + IC_CFG1SET);
arch/mips/alchemy/common/irq.c
468
__raw_writel(1 << bit, base + IC_CFG0SET);
arch/mips/alchemy/common/irq.c
473
__raw_writel(1 << bit, base + IC_CFG2SET);
arch/mips/alchemy/common/irq.c
474
__raw_writel(1 << bit, base + IC_CFG1CLR);
arch/mips/alchemy/common/irq.c
475
__raw_writel(1 << bit, base + IC_CFG0SET);
arch/mips/alchemy/common/irq.c
480
__raw_writel(1 << bit, base + IC_CFG2SET);
arch/mips/alchemy/common/irq.c
481
__raw_writel(1 << bit, base + IC_CFG1SET);
arch/mips/alchemy/common/irq.c
482
__raw_writel(1 << bit, base + IC_CFG0CLR);
arch/mips/alchemy/common/irq.c
487
__raw_writel(1 << bit, base + IC_CFG2CLR);
arch/mips/alchemy/common/irq.c
488
__raw_writel(1 << bit, base + IC_CFG1CLR);
arch/mips/alchemy/common/irq.c
489
__raw_writel(1 << bit, base + IC_CFG0CLR);
arch/mips/alchemy/common/irq.c
523
__raw_writel(l, r + AU1300_GPIC_PINCFG);
arch/mips/alchemy/common/irq.c
556
__raw_writel(bit, r + AU1300_GPIC_DEVSEL);
arch/mips/alchemy/common/irq.c
589
__raw_writel(r, AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL);
arch/mips/alchemy/common/irq.c
608
__raw_writel(bit, r + AU1300_GPIC_IDIS);
arch/mips/alchemy/common/irq.c
625
__raw_writel(bit, r + AU1300_GPIC_IEN);
arch/mips/alchemy/common/irq.c
637
__raw_writel(bit, r + AU1300_GPIC_IPEND); /* ack */
arch/mips/alchemy/common/irq.c
638
__raw_writel(bit, r + AU1300_GPIC_IDIS); /* mask */
arch/mips/alchemy/common/irq.c
652
__raw_writel(bit, r + AU1300_GPIC_IPEND); /* ack */
arch/mips/alchemy/common/irq.c
718
__raw_writel(0xffffffff, base + IC_CFG0CLR);
arch/mips/alchemy/common/irq.c
719
__raw_writel(0xffffffff, base + IC_CFG1CLR);
arch/mips/alchemy/common/irq.c
720
__raw_writel(0xffffffff, base + IC_CFG2CLR);
arch/mips/alchemy/common/irq.c
721
__raw_writel(0xffffffff, base + IC_MASKCLR);
arch/mips/alchemy/common/irq.c
722
__raw_writel(0xffffffff, base + IC_ASSIGNCLR);
arch/mips/alchemy/common/irq.c
723
__raw_writel(0xffffffff, base + IC_WAKECLR);
arch/mips/alchemy/common/irq.c
724
__raw_writel(0xffffffff, base + IC_SRCSET);
arch/mips/alchemy/common/irq.c
725
__raw_writel(0xffffffff, base + IC_FALLINGCLR);
arch/mips/alchemy/common/irq.c
726
__raw_writel(0xffffffff, base + IC_RISINGCLR);
arch/mips/alchemy/common/irq.c
727
__raw_writel(0x00000000, base + IC_TESTBIT);
arch/mips/alchemy/common/irq.c
749
__raw_writel(d[0], base + IC_CFG0SET);
arch/mips/alchemy/common/irq.c
750
__raw_writel(d[1], base + IC_CFG1SET);
arch/mips/alchemy/common/irq.c
751
__raw_writel(d[2], base + IC_CFG2SET);
arch/mips/alchemy/common/irq.c
752
__raw_writel(d[3], base + IC_SRCSET);
arch/mips/alchemy/common/irq.c
753
__raw_writel(d[4], base + IC_ASSIGNSET);
arch/mips/alchemy/common/irq.c
754
__raw_writel(d[5], base + IC_WAKESET);
arch/mips/alchemy/common/irq.c
757
__raw_writel(d[6], base + IC_MASKSET);
arch/mips/alchemy/common/irq.c
793
__raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0);
arch/mips/alchemy/common/irq.c
794
__raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4);
arch/mips/alchemy/common/irq.c
795
__raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8);
arch/mips/alchemy/common/irq.c
796
__raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc);
arch/mips/alchemy/common/irq.c
815
__raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0);
arch/mips/alchemy/common/irq.c
816
__raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4);
arch/mips/alchemy/common/irq.c
817
__raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8);
arch/mips/alchemy/common/irq.c
818
__raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc);
arch/mips/alchemy/common/irq.c
824
__raw_writel(alchemy_gpic_pmdata[i + 5], base + (i << 2));
arch/mips/alchemy/common/irq.c
829
__raw_writel(alchemy_gpic_pmdata[4], base + AU1300_GPIC_DMASEL);
arch/mips/alchemy/common/irq.c
833
__raw_writel(alchemy_gpic_pmdata[0], base + AU1300_GPIC_IEN + 0x0);
arch/mips/alchemy/common/irq.c
834
__raw_writel(alchemy_gpic_pmdata[1], base + AU1300_GPIC_IEN + 0x4);
arch/mips/alchemy/common/irq.c
835
__raw_writel(alchemy_gpic_pmdata[2], base + AU1300_GPIC_IEN + 0x8);
arch/mips/alchemy/common/irq.c
836
__raw_writel(alchemy_gpic_pmdata[3], base + AU1300_GPIC_IEN + 0xc);
arch/mips/alchemy/common/irq.c
919
__raw_writel(1 << bit, base + IC_ASSIGNSET);
arch/mips/alchemy/common/irq.c
942
__raw_writel(~0UL, bank_base + AU1300_GPIC_IDIS);
arch/mips/alchemy/common/irq.c
944
__raw_writel(~0UL, bank_base + AU1300_GPIC_IPEND);
arch/mips/alchemy/common/usb.c
112
__raw_writel(r, base + USB_DWC_CTRL2);
arch/mips/alchemy/common/usb.c
118
__raw_writel(r, base + USB_DWC_CTRL2);
arch/mips/alchemy/common/usb.c
128
__raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */
arch/mips/alchemy/common/usb.c
134
__raw_writel(r, base + USB_DWC_CTRL3);
arch/mips/alchemy/common/usb.c
141
__raw_writel(r, base + USB_INT_ENABLE);
arch/mips/alchemy/common/usb.c
145
__raw_writel(0, base + USB_DWC_CTRL7);
arch/mips/alchemy/common/usb.c
150
__raw_writel(r, base + USB_INT_ENABLE);
arch/mips/alchemy/common/usb.c
156
__raw_writel(r, base + USB_DWC_CTRL3);
arch/mips/alchemy/common/usb.c
170
__raw_writel(r, base + USB_DWC_CTRL3);
arch/mips/alchemy/common/usb.c
175
__raw_writel(r, base + USB_DWC_CTRL1);
arch/mips/alchemy/common/usb.c
182
__raw_writel(r, base + USB_INT_ENABLE);
arch/mips/alchemy/common/usb.c
187
__raw_writel(r, base + USB_INT_ENABLE);
arch/mips/alchemy/common/usb.c
192
__raw_writel(r, base + USB_DWC_CTRL1);
arch/mips/alchemy/common/usb.c
197
__raw_writel(r, base + USB_DWC_CTRL3);
arch/mips/alchemy/common/usb.c
211
__raw_writel(r, base + USB_DWC_CTRL1);
arch/mips/alchemy/common/usb.c
218
__raw_writel(r, base + USB_INT_ENABLE);
arch/mips/alchemy/common/usb.c
223
__raw_writel(r, base + USB_INT_ENABLE);
arch/mips/alchemy/common/usb.c
228
__raw_writel(r, base + USB_DWC_CTRL1);
arch/mips/alchemy/common/usb.c
241
__raw_writel(r, base + USB_DWC_CTRL3);
arch/mips/alchemy/common/usb.c
246
__raw_writel(r, base + USB_DWC_CTRL1);
arch/mips/alchemy/common/usb.c
253
__raw_writel(r, base + USB_DWC_CTRL1);
arch/mips/alchemy/common/usb.c
258
__raw_writel(r, base + USB_DWC_CTRL3);
arch/mips/alchemy/common/usb.c
303
__raw_writel(0, base + USB_INT_ENABLE); /* disable all USB irqs */
arch/mips/alchemy/common/usb.c
305
__raw_writel(0, base + USB_DWC_CTRL3); /* disable all clocks */
arch/mips/alchemy/common/usb.c
307
__raw_writel(~0, base + USB_MSR_ERR); /* clear all errors */
arch/mips/alchemy/common/usb.c
309
__raw_writel(~0, base + USB_INT_STATUS); /* clear int status */
arch/mips/alchemy/common/usb.c
312
__raw_writel(USB_SBUS_CTRL_SBCA, base + USB_SBUS_CTRL);
arch/mips/alchemy/common/usb.c
320
__raw_writel(r | USBCFG_OCE, base + AU1200_USBCFG);
arch/mips/alchemy/common/usb.c
324
__raw_writel(r & ~USBCFG_OCE, base + AU1200_USBCFG);
arch/mips/alchemy/common/usb.c
334
__raw_writel(r | USBCFG_ECE | USBCFG_PPE, base + AU1200_USBCFG);
arch/mips/alchemy/common/usb.c
340
__raw_writel(r & ~USBCFG_ECE, base + AU1200_USBCFG);
arch/mips/alchemy/common/usb.c
350
__raw_writel(r | USBCFG_UCE | USBCFG_PPE, base + AU1200_USBCFG);
arch/mips/alchemy/common/usb.c
355
__raw_writel(r & ~USBCFG_UCE, base + AU1200_USBCFG);
arch/mips/alchemy/common/usb.c
387
__raw_writel(USBCFG_INIT_AU1200, base + AU1200_USBCFG);
arch/mips/alchemy/common/usb.c
417
__raw_writel(r, base);
arch/mips/alchemy/common/usb.c
438
__raw_writel(r | USBHEN_CE, base + creg);
arch/mips/alchemy/common/usb.c
441
__raw_writel(r | USBHEN_CE | USBHEN_E, base + creg);
arch/mips/alchemy/common/usb.c
450
__raw_writel(r & ~(USBHEN_CE | USBHEN_E), base + creg);
arch/mips/alchemy/common/usb.c
519
__raw_writel(0, base + 0x04);
arch/mips/alchemy/common/usb.c
521
__raw_writel(0, base + creg);
arch/mips/alchemy/common/usb.c
524
__raw_writel(alchemy_usb_pmdata[0], base + creg);
arch/mips/alchemy/common/usb.c
543
__raw_writel(alchemy_usb_pmdata[0], base + 0x00);
arch/mips/alchemy/common/usb.c
544
__raw_writel(alchemy_usb_pmdata[1], base + 0x04);
arch/mips/alchemy/common/usb.c
558
__raw_writel(alchemy_usb_pmdata[0], base + USB_DWC_CTRL4);
arch/mips/alchemy/common/vss.c
27
__raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */
arch/mips/alchemy/common/vss.c
30
__raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */
arch/mips/alchemy/common/vss.c
34
__raw_writel(0x01, base + VSS_FTR);
arch/mips/alchemy/common/vss.c
36
__raw_writel(0x03, base + VSS_FTR);
arch/mips/alchemy/common/vss.c
38
__raw_writel(0x07, base + VSS_FTR);
arch/mips/alchemy/common/vss.c
40
__raw_writel(0x0f, base + VSS_FTR);
arch/mips/alchemy/common/vss.c
43
__raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */
arch/mips/alchemy/common/vss.c
46
__raw_writel(2, base + VSS_CLKRST); /* deassert reset */
arch/mips/alchemy/common/vss.c
49
__raw_writel(0x1f, base + VSS_FTR); /* enable isolation cells */
arch/mips/alchemy/common/vss.c
58
__raw_writel(0x0f, base + VSS_FTR); /* disable isolation cells */
arch/mips/alchemy/common/vss.c
60
__raw_writel(0, base + VSS_GATE); /* disable FSM */
arch/mips/alchemy/common/vss.c
62
__raw_writel(3, base + VSS_CLKRST); /* assert reset */
arch/mips/alchemy/common/vss.c
64
__raw_writel(1, base + VSS_CLKRST); /* disable clock */
arch/mips/alchemy/common/vss.c
66
__raw_writel(0, base + VSS_FTR); /* disable all footers */
arch/mips/alchemy/devboards/db1200.c
908
__raw_writel(PSC_SEL_CLK_SERCLK,
arch/mips/alchemy/devboards/db1300.c
816
__raw_writel(PSC_SEL_CLK_SERCLK,
arch/mips/alchemy/devboards/db1300.c
819
__raw_writel(PSC_SEL_CLK_SERCLK,
arch/mips/alchemy/devboards/db1300.c
829
__raw_writel(PSC_SEL_CLK_INTCLK,
arch/mips/alchemy/devboards/db1550.c
48
__raw_writel(PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE,
arch/mips/alchemy/devboards/db1550.c
50
__raw_writel(PSC_CTRL_DISABLE, base + PSC_CTRL_OFFSET);
arch/mips/alchemy/devboards/db1550.c
52
__raw_writel(PSC_AC97RST_RST, base + PSC_AC97RST_OFFSET);
arch/mips/alchemy/devboards/db1550.c
608
__raw_writel(PSC_SEL_CLK_SERCLK,
arch/mips/alchemy/devboards/db1550.c
611
__raw_writel(PSC_SEL_CLK_SERCLK,
arch/mips/alchemy/devboards/db1550.c
615
__raw_writel(PSC_SEL_CLK_INTCLK,
arch/mips/alchemy/devboards/db1550.c
618
__raw_writel(PSC_SEL_CLK_INTCLK,
arch/mips/ath25/ar2315.c
45
__raw_writel(val, ar2315_rst_base + reg);
arch/mips/ath25/ar5312.c
210
__raw_writel(ctl, flashctl_base + AR5312_FLASHCTL0);
arch/mips/ath25/ar5312.c
215
__raw_writel(ctl, flashctl_base + AR5312_FLASHCTL1);
arch/mips/ath25/ar5312.c
218
__raw_writel(ctl, flashctl_base + AR5312_FLASHCTL2);
arch/mips/ath25/ar5312.c
46
__raw_writel(val, ar5312_rst_base + reg);
arch/mips/ath25/early_printk.c
21
__raw_writel(ch, base + 4 * reg);
arch/mips/ath79/common.c
61
__raw_writel(0x1, flush_reg);
arch/mips/ath79/common.c
66
__raw_writel(0x1, flush_reg);
arch/mips/ath79/common.c
76
__raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0x0);
arch/mips/ath79/common.c
77
__raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 0x4);
arch/mips/ath79/common.c
78
__raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 0x8);
arch/mips/ath79/common.c
79
__raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 0xc);
arch/mips/ath79/common.c
80
__raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 0x10);
arch/mips/ath79/common.c
81
__raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 0x14);
arch/mips/ath79/common.c
82
__raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 0x18);
arch/mips/ath79/common.c
83
__raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 0x1c);
arch/mips/ath79/early_printk.c
38
__raw_writel((unsigned char)ch, base + UART_TX * 4);
arch/mips/ath79/early_printk.c
47
__raw_writel(AR933X_UART_DATA_TX_CSR | (unsigned char)ch,
arch/mips/ath79/early_printk.c
94
__raw_writel(t, gpio_base + AR71XX_GPIO_REG_FUNC);
arch/mips/bmips/dma.c
25
__raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
arch/mips/bmips/setup.c
55
__raw_writel(kbase | RELO_NORMAL_VEC,
arch/mips/include/asm/io.h
372
__raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
arch/mips/include/asm/io.h
500
#define __raw_writel __raw_writel
arch/mips/include/asm/mach-ath79/ath79.h
156
__raw_writel(val, ath79_pll_base + reg);
arch/mips/include/asm/mach-ath79/ath79.h
166
__raw_writel(val, ath79_reset_base + reg);
arch/mips/include/asm/mach-au1x00/au1000.h
615
__raw_writel(v, b + regofs);
arch/mips/include/asm/mach-au1x00/au1000.h
631
__raw_writel(v, b + regofs);
arch/mips/include/asm/mach-au1x00/au1000.h
733
__raw_writel(0, addr + 0x100);
arch/mips/include/asm/mach-au1x00/au1000.h
735
__raw_writel(1, addr + 0x100);
arch/mips/include/asm/mach-au1x00/au1000.h
738
__raw_writel(3, addr + 0x100);
arch/mips/include/asm/mach-au1x00/au1000.h
746
__raw_writel(0, addr + 0x100); /* UART_MOD_CNTRL */
arch/mips/include/asm/mach-au1x00/au1000.h
765
__raw_writel(c, base + 0x04); /* tx */
arch/mips/include/asm/mach-au1x00/au1000_dma.h
159
__raw_writel(DMA_BE0, chan->io + DMA_MODE_SET);
arch/mips/include/asm/mach-au1x00/au1000_dma.h
168
__raw_writel(DMA_BE1, chan->io + DMA_MODE_SET);
arch/mips/include/asm/mach-au1x00/au1000_dma.h
176
__raw_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
arch/mips/include/asm/mach-au1x00/au1000_dma.h
185
__raw_writel(DMA_GO, chan->io + DMA_MODE_SET);
arch/mips/include/asm/mach-au1x00/au1000_dma.h
197
__raw_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
arch/mips/include/asm/mach-au1x00/au1000_dma.h
217
__raw_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
arch/mips/include/asm/mach-au1x00/au1000_dma.h
241
__raw_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);
arch/mips/include/asm/mach-au1x00/au1000_dma.h
247
__raw_writel(~mode, chan->io + DMA_MODE_CLEAR);
arch/mips/include/asm/mach-au1x00/au1000_dma.h
248
__raw_writel(mode, chan->io + DMA_MODE_SET);
arch/mips/include/asm/mach-au1x00/au1000_dma.h
306
__raw_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR);
arch/mips/include/asm/mach-au1x00/au1000_dma.h
318
__raw_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
arch/mips/include/asm/mach-au1x00/au1000_dma.h
327
__raw_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
arch/mips/include/asm/mach-au1x00/au1000_dma.h
346
__raw_writel(a, chan->io + DMA_BUFFER0_START);
arch/mips/include/asm/mach-au1x00/au1000_dma.h
358
__raw_writel(a, chan->io + DMA_BUFFER1_START);
arch/mips/include/asm/mach-au1x00/au1000_dma.h
372
__raw_writel(count, chan->io + DMA_BUFFER0_COUNT);
arch/mips/include/asm/mach-au1x00/au1000_dma.h
385
__raw_writel(count, chan->io + DMA_BUFFER1_COUNT);
arch/mips/include/asm/mach-au1x00/au1000_dma.h
398
__raw_writel(count, chan->io + DMA_BUFFER0_COUNT);
arch/mips/include/asm/mach-au1x00/au1000_dma.h
399
__raw_writel(count, chan->io + DMA_BUFFER1_COUNT);
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
276
__raw_writel(0, base + 0x110); /* the write op is key */
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
294
__raw_writel(d, base + AU1000_GPIO2_DIR);
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
303
__raw_writel(mask, base + AU1000_GPIO2_OUTPUT);
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
367
__raw_writel(r, base + AU1000_GPIO2_INTENABLE);
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
444
__raw_writel(3, base + AU1000_GPIO2_ENABLE); /* reset, clock enabled */
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
446
__raw_writel(1, base + AU1000_GPIO2_ENABLE); /* clock enabled */
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
458
__raw_writel(2, base + AU1000_GPIO2_ENABLE); /* reset, clock disabled */
arch/mips/include/asm/mach-au1x00/gpio-au1300.h
49
__raw_writel(bit, roff + AU1300_GPIC_DEVCLR);
arch/mips/include/asm/mach-au1x00/gpio-au1300.h
64
__raw_writel(bit, roff + (v ? AU1300_GPIC_PINVAL
arch/mips/include/asm/mach-lantiq/lantiq.h
15
#define ltq_w32(val, reg) __raw_writel(val, reg)
arch/mips/include/asm/mach-ralink/ralink_regs.h
37
__raw_writel(val, rt_sysc_membase + reg);
arch/mips/include/asm/mach-ralink/ralink_regs.h
49
__raw_writel(val | set, rt_sysc_membase + reg);
arch/mips/include/asm/mach-ralink/ralink_regs.h
54
__raw_writel(val, rt_memc_membase + reg);
arch/mips/include/asm/mach-rc32434/dma_v.h
30
__raw_writel(0, &ch->dmac);
arch/mips/include/asm/mach-rc32434/dma_v.h
33
__raw_writel(0, &ch->dmas);
arch/mips/include/asm/mach-rc32434/dma_v.h
44
__raw_writel(0, &ch->dmandptr);
arch/mips/include/asm/mach-rc32434/dma_v.h
45
__raw_writel(dma_addr, &ch->dmadptr);
arch/mips/include/asm/mach-rc32434/dma_v.h
50
__raw_writel(dma_addr, &ch->dmandptr);
arch/mips/include/asm/mips-cps.h
52
__raw_writel(val, addr_##unit##_##name()); \
arch/mips/include/asm/mips-cps.h
61
__raw_writel((uint64_t)val >> 32, \
arch/mips/include/asm/mips-cps.h
63
__raw_writel(val, addr_##unit##_##name()); \
arch/mips/include/asm/mips-gic.h
131
__raw_writel(BIT(intr % 32), addr); \
arch/mips/include/asm/mips-gic.h
155
__raw_writel(_val, addr); \
arch/mips/include/asm/mips-gic.h
70
__raw_writel(val, addr_gic_##name(intr)); \
arch/mips/include/asm/pci/bridge.h
819
#define bridge_write(bc, reg, val) __raw_writel(val, &bc->base->reg)
arch/mips/include/asm/pci/bridge.h
821
__raw_writel(__raw_readl(&bc->base->reg) | (val), &bc->base->reg)
arch/mips/include/asm/pci/bridge.h
823
__raw_writel(__raw_readl(&bc->base->reg) & ~(val), &bc->base->reg)
arch/mips/kernel/cevt-txx9.c
100
__raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
arch/mips/kernel/cevt-txx9.c
111
__raw_writel(TXx9_TMITMR_TIIE, &tmrptr->itmr);
arch/mips/kernel/cevt-txx9.c
122
__raw_writel(0, &tmrptr->itmr);
arch/mips/kernel/cevt-txx9.c
133
__raw_writel(TIMER_CCD, &tmrptr->ccdr);
arch/mips/kernel/cevt-txx9.c
134
__raw_writel(0, &tmrptr->itmr);
arch/mips/kernel/cevt-txx9.c
147
__raw_writel(delta, &tmrptr->cpra);
arch/mips/kernel/cevt-txx9.c
148
__raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
arch/mips/kernel/cevt-txx9.c
172
__raw_writel(0, &tmrptr->tisr); /* ack interrupt */
arch/mips/kernel/cevt-txx9.c
185
__raw_writel(TIMER_CCD, &tmrptr->ccdr);
arch/mips/kernel/cevt-txx9.c
186
__raw_writel(0, &tmrptr->itmr);
arch/mips/kernel/cevt-txx9.c
211
__raw_writel(TXx9_TMTCR_CRE | TXx9_TMTCR_TCE, &tmrptr->tcr);
arch/mips/kernel/cevt-txx9.c
213
__raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr);
arch/mips/kernel/cevt-txx9.c
214
__raw_writel(0, &tmrptr->tisr);
arch/mips/kernel/cevt-txx9.c
215
__raw_writel(0xffffffff, &tmrptr->cpra);
arch/mips/kernel/cevt-txx9.c
216
__raw_writel(0, &tmrptr->itmr);
arch/mips/kernel/cevt-txx9.c
217
__raw_writel(0, &tmrptr->ccdr);
arch/mips/kernel/cevt-txx9.c
218
__raw_writel(0, &tmrptr->pgmr);
arch/mips/kernel/cevt-txx9.c
63
__raw_writel(TCR_BASE, &tmrptr->tcr);
arch/mips/kernel/cevt-txx9.c
64
__raw_writel(0, &tmrptr->tisr);
arch/mips/kernel/cevt-txx9.c
65
__raw_writel(TIMER_CCD, &tmrptr->ccdr);
arch/mips/kernel/cevt-txx9.c
66
__raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr);
arch/mips/kernel/cevt-txx9.c
67
__raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra);
arch/mips/kernel/cevt-txx9.c
68
__raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
arch/mips/kernel/cevt-txx9.c
83
__raw_writel(TCR_BASE, &tmrptr->tcr);
arch/mips/kernel/cevt-txx9.c
85
__raw_writel(0, &tmrptr->tisr);
arch/mips/kernel/cevt-txx9.c
96
__raw_writel(TXx9_TMITMR_TIIE | TXx9_TMITMR_TZCE, &tmrptr->itmr);
arch/mips/kernel/cevt-txx9.c
98
__raw_writel(((u64)(NSEC_PER_SEC / HZ) * evt->mult) >> evt->shift,
arch/mips/kernel/gpio_txx9.c
32
__raw_writel(val, &txx9_pioptr->dout);
arch/mips/kernel/gpio_txx9.c
51
__raw_writel(__raw_readl(&txx9_pioptr->dir) & ~(1 << offset),
arch/mips/kernel/gpio_txx9.c
64
__raw_writel(__raw_readl(&txx9_pioptr->dir) | (1 << offset),
arch/mips/kernel/irq_txx9.c
122
__raw_writel(cr, crp);
arch/mips/kernel/irq_txx9.c
149
__raw_writel(0, &txx9_ircptr->imr);
arch/mips/kernel/irq_txx9.c
151
__raw_writel(0, &txx9_ircptr->ilr[i]);
arch/mips/kernel/irq_txx9.c
154
__raw_writel(0, &txx9_ircptr->cr[i]);
arch/mips/kernel/irq_txx9.c
156
__raw_writel(TXx9_IRCER_ICE, &txx9_ircptr->cer);
arch/mips/kernel/irq_txx9.c
157
__raw_writel(irc_elevel, &txx9_ircptr->imr);
arch/mips/kernel/irq_txx9.c
72
__raw_writel((__raw_readl(ilrp) & ~(0xff << ofs))
arch/mips/kernel/irq_txx9.c
83
__raw_writel((__raw_readl(ilrp) & ~(0xff << ofs))
arch/mips/kernel/irq_txx9.c
96
__raw_writel(TXx9_IRSCR_EIClrE | irq_nr, &txx9_ircptr->scr);
arch/mips/kernel/smp-bmips.c
524
__raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
arch/mips/kernel/smp-bmips.c
528
__raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
arch/mips/kernel/smp-bmips.c
612
__raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
arch/mips/kernel/smp-bmips.c
616
__raw_writel(cfg | 0xf, cbr + BMIPS_RAC_CONFIG);
arch/mips/kernel/smp-bmips.c
620
__raw_writel(cfg | 0x0fff0000, cbr + BMIPS_RAC_ADDRESS_RANGE);
arch/mips/kernel/smp-bmips.c
632
__raw_writel(cfg | 0xf, cbr + rac_addr);
arch/mips/kernel/smp-bmips.c
637
__raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
arch/mips/kernel/smp-bmips.c
649
__raw_writel(cfg & ~0x07000000, cbr + BMIPS_L2_CONFIG);
arch/mips/mti-malta/malta-dtshim.c
249
__raw_writel(sc_cfg, biu_base + MSC01_SC_CFG_OFS);
arch/mips/n64/init.c
57
__raw_writel(value, REG_BASE + reg);
arch/mips/pci/ops-bcm63xx.c
137
__raw_writel(cpu_to_le32(data), pci_iospace_start);
arch/mips/pci/ops-tx4927.c
130
__raw_writel(val, &pcicptr->g2pcfgdata);
arch/mips/pci/ops-tx4927.c
243
__raw_writel(__raw_readl(&pcicptr->pciccfg)
arch/mips/pci/ops-tx4927.c
251
__raw_writel((channel->io_resource->end - channel->io_resource->start)
arch/mips/pci/ops-tx4927.c
265
__raw_writel(0, &pcicptr->g2pmmask[i]);
arch/mips/pci/ops-tx4927.c
270
__raw_writel((channel->mem_resource->end
arch/mips/pci/ops-tx4927.c
285
__raw_writel(0, &pcicptr->p2giopbase); /* 256B */
arch/mips/pci/ops-tx4927.c
288
__raw_writel(0, &pcicptr->p2gm0plbase);
arch/mips/pci/ops-tx4927.c
289
__raw_writel(0, &pcicptr->p2gm0pubase);
arch/mips/pci/ops-tx4927.c
298
__raw_writel(0xffffffff, &pcicptr->p2gm1plbase);
arch/mips/pci/ops-tx4927.c
299
__raw_writel(0xffffffff, &pcicptr->p2gm1pubase);
arch/mips/pci/ops-tx4927.c
302
__raw_writel(0xffffffff, &pcicptr->p2gm2pbase); /* 1MB */
arch/mips/pci/ops-tx4927.c
306
__raw_writel((tx4927_pci_opts.gbwc << 16)
arch/mips/pci/ops-tx4927.c
311
__raw_writel(__raw_readl(&pcicptr->pciccfg)
arch/mips/pci/ops-tx4927.c
316
__raw_writel(__raw_readl(&pcicptr->pciccfg)
arch/mips/pci/ops-tx4927.c
320
__raw_writel(__raw_readl(&pcicptr->pciccfg)
arch/mips/pci/ops-tx4927.c
325
__raw_writel(0, &pcicptr->pcicfg1);
arch/mips/pci/ops-tx4927.c
327
__raw_writel((__raw_readl(&pcicptr->g2ptocnt) & ~0xffff)
arch/mips/pci/ops-tx4927.c
333
__raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus);
arch/mips/pci/ops-tx4927.c
335
__raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicmask);
arch/mips/pci/ops-tx4927.c
337
__raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus);
arch/mips/pci/ops-tx4927.c
339
__raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pmask);
arch/mips/pci/ops-tx4927.c
341
__raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
arch/mips/pci/ops-tx4927.c
345
__raw_writel(TX4927_PCIC_PCISTATUS_ALL, &pcicptr->pcimask);
arch/mips/pci/ops-tx4927.c
349
__raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg);
arch/mips/pci/ops-tx4927.c
350
__raw_writel(0, &pcicptr->pbabm);
arch/mips/pci/ops-tx4927.c
352
__raw_writel(TX4927_PCIC_PBACFG_PBAEN, &pcicptr->pbacfg);
arch/mips/pci/ops-tx4927.c
355
__raw_writel(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
arch/mips/pci/ops-tx4927.c
485
__raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
arch/mips/pci/ops-tx4927.c
488
__raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus);
arch/mips/pci/ops-tx4927.c
489
__raw_writel(TX4927_PCIC_PBASTATUS_ALL, &pcicptr->pbastatus);
arch/mips/pci/ops-tx4927.c
490
__raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus);
arch/mips/pci/ops-tx4927.c
507
__raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg);
arch/mips/pci/ops-tx4927.c
513
__raw_writel(0x72543610, &pcicptr->pbareqport);
arch/mips/pci/ops-tx4927.c
514
__raw_writel(0, &pcicptr->pbabm);
arch/mips/pci/ops-tx4927.c
516
__raw_writel(TX4927_PCIC_PBACFG_FIXPA, &pcicptr->pbacfg);
arch/mips/pci/ops-tx4927.c
518
__raw_writel(TX4927_PCIC_PBACFG_FIXPA |
arch/mips/pci/ops-tx4927.c
64
__raw_writel(((bus->number & 0xff) << 0x10)
arch/mips/pci/ops-tx4927.c
69
__raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
arch/mips/pci/ops-tx4927.c
84
__raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
arch/mips/pci/pci-alchemy.c
116
__raw_writel(r, ctx->regs + PCI_REG_STATCMD);
arch/mips/pci/pci-alchemy.c
155
__raw_writel(*data, ctx->pci_cfg_vm->addr + offset);
arch/mips/pci/pci-alchemy.c
175
__raw_writel(status & 0xf000ffff, ctx->regs + PCI_REG_STATCMD);
arch/mips/pci/pci-alchemy.c
335
__raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM);
arch/mips/pci/pci-alchemy.c
336
__raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH);
arch/mips/pci/pci-alchemy.c
337
__raw_writel(ctx->pm[3], ctx->regs + PCI_REG_B2BBASE0_VID);
arch/mips/pci/pci-alchemy.c
338
__raw_writel(ctx->pm[4], ctx->regs + PCI_REG_B2BBASE1_SID);
arch/mips/pci/pci-alchemy.c
339
__raw_writel(ctx->pm[5], ctx->regs + PCI_REG_MWMASK_DEV);
arch/mips/pci/pci-alchemy.c
340
__raw_writel(ctx->pm[6], ctx->regs + PCI_REG_MWBASE_REV_CCL);
arch/mips/pci/pci-alchemy.c
341
__raw_writel(ctx->pm[7], ctx->regs + PCI_REG_ID);
arch/mips/pci/pci-alchemy.c
342
__raw_writel(ctx->pm[8], ctx->regs + PCI_REG_CLASSREV);
arch/mips/pci/pci-alchemy.c
343
__raw_writel(ctx->pm[9], ctx->regs + PCI_REG_PARAM);
arch/mips/pci/pci-alchemy.c
344
__raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR);
arch/mips/pci/pci-alchemy.c
345
__raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT);
arch/mips/pci/pci-alchemy.c
347
__raw_writel(ctx->pm[1], ctx->regs + PCI_REG_CONFIG);
arch/mips/pci/pci-alchemy.c
440
__raw_writel(val, ctx->regs + PCI_REG_CONFIG);
arch/mips/pci/pci-alchemy.c
480
__raw_writel(val, ctx->regs + PCI_REG_CONFIG);
arch/mips/pci/pci-ar2315.c
199
__raw_writel(val, apc->mmr_mem + reg);
arch/mips/pci/pci-ar2315.c
243
__raw_writel(value, apc->cfg_mem + addr);
arch/mips/pci/pci-ar71xx.c
124
__raw_writel(pci_err, base + AR71XX_PCI_REG_PCI_ERR);
arch/mips/pci/pci-ar71xx.c
138
__raw_writel(ahb_err, base + AR71XX_PCI_REG_AHB_ERR);
arch/mips/pci/pci-ar71xx.c
155
__raw_writel(ad_cbe, base + AR71XX_PCI_REG_CRP_AD_CBE);
arch/mips/pci/pci-ar71xx.c
156
__raw_writel(value, base + AR71XX_PCI_REG_CRP_WRDATA);
arch/mips/pci/pci-ar71xx.c
169
__raw_writel(addr, base + AR71XX_PCI_REG_CFG_AD);
arch/mips/pci/pci-ar71xx.c
170
__raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
arch/mips/pci/pci-ar71xx.c
216
__raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA);
arch/mips/pci/pci-ar71xx.c
264
__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
arch/mips/pci/pci-ar71xx.c
281
__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
arch/mips/pci/pci-ar71xx.c
299
__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
arch/mips/pci/pci-ar71xx.c
300
__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
arch/mips/pci/pci-ar724x.c
106
__raw_writel(data, base + (where & ~3));
arch/mips/pci/pci-ar724x.c
217
__raw_writel(data, base + (where & ~3));
arch/mips/pci/pci-ar724x.c
262
__raw_writel(t | AR724X_PCI_INT_DEV0,
arch/mips/pci/pci-ar724x.c
283
__raw_writel(t & ~AR724X_PCI_INT_DEV0,
arch/mips/pci/pci-ar724x.c
290
__raw_writel(t | AR724X_PCI_INT_DEV0,
arch/mips/pci/pci-ar724x.c
313
__raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
arch/mips/pci/pci-ar724x.c
314
__raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
arch/mips/pci/pci-ar724x.c
351
__raw_writel(app, apc->ctrl_base + AR724X_PCI_REG_APP);
arch/mips/pic32/common/reset.c
33
__raw_writel(1, reg);
arch/mips/pic32/pic32mzda/early_console.c
160
__raw_writel(c, uart_base + U_TXR(console_port));
arch/mips/pic32/pic32mzda/early_console.c
57
__raw_writel(0, uart_base + U_MODE(port));
arch/mips/pic32/pic32mzda/early_console.c
58
__raw_writel(((pbclk / baud) / 16) - 1, uart_base + U_BRG(port));
arch/mips/pic32/pic32mzda/early_console.c
59
__raw_writel(UART_ENABLE, uart_base + U_MODE(port));
arch/mips/pic32/pic32mzda/early_console.c
60
__raw_writel(UART_ENABLE_TX | UART_ENABLE_RX,
arch/mips/pic32/pic32mzda/early_pin.c
130
__raw_writel(pin, pps_base + input_pin_reg[i].reg);
arch/mips/pic32/pic32mzda/early_pin.c
260
__raw_writel(function,
arch/mips/ralink/early_printk.c
37
__raw_writel(val, uart_membase + reg);
arch/mips/ralink/irq.c
62
__raw_writel(val, rt_intc_membase + rt_intc_regs[reg]);
arch/mips/ralink/mt7621.c
70
__raw_writel(MT7621_MEM_TEST_PATTERN, dm);
arch/mips/ralink/mt7621.c
73
__raw_writel(~MT7621_MEM_TEST_PATTERN, dm);
arch/mips/ralink/timer.c
44
__raw_writel(val, rt->membase + reg);
arch/mips/rb532/setup.c
61
__raw_writel(val, (void *)&pci_reg->pcic);
arch/mips/sgi-ip22/ip22-nvram.c
36
__raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \
arch/mips/sgi-ip22/ip22-nvram.c
37
__raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
arch/mips/sgi-ip22/ip22-nvram.c
38
__raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \
arch/mips/sgi-ip22/ip22-nvram.c
40
__raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \
arch/mips/sgi-ip22/ip22-nvram.c
41
__raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
arch/mips/sgi-ip22/ip22-nvram.c
45
__raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
arch/mips/sgi-ip22/ip22-nvram.c
46
__raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \
arch/mips/sgi-ip22/ip22-nvram.c
47
__raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \
arch/mips/sgi-ip22/ip22-nvram.c
48
__raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
arch/mips/sgi-ip22/ip22-nvram.c
64
__raw_writel(__raw_readl(ctrl) | EEPROM_DATO, ctrl);
arch/mips/sgi-ip22/ip22-nvram.c
66
__raw_writel(__raw_readl(ctrl) & ~EEPROM_DATO, ctrl);
arch/mips/sgi-ip22/ip22-nvram.c
67
__raw_writel(__raw_readl(ctrl) & ~EEPROM_ECLK, ctrl);
arch/mips/sgi-ip22/ip22-nvram.c
69
__raw_writel(__raw_readl(ctrl) | EEPROM_ECLK, ctrl);
arch/mips/sgi-ip22/ip22-nvram.c
74
__raw_writel(__raw_readl(ctrl) & ~EEPROM_DATO, ctrl);
arch/mips/sgi-ip22/ip22-nvram.c
82
__raw_writel(__raw_readl(ctrl) & ~EEPROM_EPROT, ctrl);
arch/mips/sgi-ip22/ip22-nvram.c
88
__raw_writel(__raw_readl(ctrl) & ~EEPROM_ECLK, ctrl);
arch/mips/sgi-ip22/ip22-nvram.c
90
__raw_writel(__raw_readl(ctrl) | EEPROM_ECLK, ctrl);
arch/mips/txx9/generic/setup.c
335
__raw_writel(TXx9_TMWTMR_WDIS | TXx9_TMWTMR_TWC, &tmrptr->wtmr);
arch/mips/txx9/generic/setup.c
336
__raw_writel(0, &tmrptr->tcr);
arch/mips/txx9/generic/setup.c
338
__raw_writel(TXx9_TMWTMR_TWIE, &tmrptr->wtmr);
arch/mips/txx9/generic/setup.c
339
__raw_writel(1, &tmrptr->cpra); /* immediate */
arch/mips/txx9/generic/setup.c
340
__raw_writel(TXx9_TMTCR_TCE | TXx9_TMTCR_CCDE | TXx9_TMTCR_TMODE_WDOG,
arch/mips/txx9/generic/setup.c
415
__raw_writel(c, early_txx9_sio_port + TXX9_SITFIFO);
arch/mips/txx9/generic/setup_tx4927.c
216
__raw_writel(0, &tx4927_pioptr->maskcpu);
arch/mips/txx9/generic/setup_tx4927.c
217
__raw_writel(0, &tx4927_pioptr->maskext);
arch/mips/txx9/generic/setup_tx4938.c
242
__raw_writel(0, &tx4938_pioptr->maskcpu);
arch/mips/txx9/generic/setup_tx4938.c
243
__raw_writel(0, &tx4938_pioptr->maskext);
arch/parisc/lib/iomap.c
216
__raw_writel(datum, addr);
arch/parisc/lib/iomap.c
274
__raw_writel(*(u32 *)s, addr);
arch/powerpc/kvm/book3s_xive.c
702
__raw_writel(vcpu->arch.xive_cam_word, tima + TM_QW1_OS + TM_WORD2);
arch/riscv/include/asm/mmio.h
31
#define __raw_writel __raw_writel
arch/riscv/include/asm/mmio.h
94
#define writel_cpu(v, c) ((void)__raw_writel((__force u32)cpu_to_le32(v), (c)))
arch/sh/boards/board-magicpanelr2.c
67
__raw_writel(0x36db0400, CS2BCR);
arch/sh/boards/board-magicpanelr2.c
69
__raw_writel(0x000003c0, CS2WCR);
arch/sh/boards/board-magicpanelr2.c
73
__raw_writel(0x00000200, CS4BCR);
arch/sh/boards/board-magicpanelr2.c
75
__raw_writel(0x00100981, CS4WCR);
arch/sh/boards/board-magicpanelr2.c
79
__raw_writel(0x00000200, CS5ABCR);
arch/sh/boards/board-magicpanelr2.c
81
__raw_writel(0x00100981, CS5AWCR);
arch/sh/boards/board-magicpanelr2.c
85
__raw_writel(0x00000200, CS5BBCR);
arch/sh/boards/board-magicpanelr2.c
87
__raw_writel(0x00100981, CS5BWCR);
arch/sh/boards/board-magicpanelr2.c
91
__raw_writel(0x00000200, CS6ABCR);
arch/sh/boards/board-magicpanelr2.c
93
__raw_writel(0x001009C1, CS6AWCR);
arch/sh/boards/board-sh2007.c
132
__raw_writel(CS5BCR_D, CS5BCR);
arch/sh/boards/board-sh2007.c
133
__raw_writel(CS5WCR_D, CS5WCR);
arch/sh/boards/board-sh2007.c
134
__raw_writel(CS5PCR_D, CS5PCR);
arch/sh/boards/mach-dreamcast/rtc.c
68
__raw_writel((adj & 0xffff0000) >> 16, AICA_RTC_SECS_H);
arch/sh/boards/mach-dreamcast/rtc.c
69
__raw_writel((adj & 0xffff), AICA_RTC_SECS_L);
arch/sh/boards/mach-kfr2r09/setup.c
501
__raw_writel(0x36db0400, BSC_CS0BCR);
arch/sh/boards/mach-kfr2r09/setup.c
502
__raw_writel(0x00000500, BSC_CS0WCR);
arch/sh/boards/mach-kfr2r09/setup.c
505
__raw_writel(0x36db0400, BSC_CS4BCR);
arch/sh/boards/mach-kfr2r09/setup.c
506
__raw_writel(0x00000500, BSC_CS4WCR);
arch/sh/boards/mach-landisk/gio.c
87
__raw_writel(data, addr);
arch/sh/boards/mach-migor/setup.c
467
__raw_writel(0x00003400, BSC_CS4BCR);
arch/sh/boards/mach-migor/setup.c
468
__raw_writel(0x00110080, BSC_CS4WCR);
arch/sh/boards/mach-migor/setup.c
484
__raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
arch/sh/boards/mach-rsk/devices-rsk7203.c
131
__raw_writel(0x36db0400, 0xfffc0008); /* CS1BCR */
arch/sh/boards/mach-se/7780/irq.c
47
__raw_writel(0xAAAA0000, INTC_ICR1);
arch/sh/boards/mach-sh7763rdp/irq.c
28
__raw_writel(1 << 25, INTC_INT2MSKCR);
arch/sh/boards/mach-sh7763rdp/irq.c
31
__raw_writel((__raw_readl(INTC_INT2PRI7) & 0xFF00FFFF) | 0x000F0000,
arch/sh/boards/mach-sh7763rdp/irq.c
35
__raw_writel(1 << 17, INTC_INT2MSKCR1);
arch/sh/boards/mach-sh7763rdp/irq.c
38
__raw_writel(1 << 16, INTC_INT2MSKCR1);
arch/sh/boards/mach-sh7763rdp/irq.c
41
__raw_writel(1 << 8, INTC_INT2MSKCR);
arch/sh/boards/mach-sh7763rdp/setup.c
204
__raw_writel(__raw_readl(MSTPCR1) & ~0x8, MSTPCR1);
arch/sh/boards/mach-x3proto/setup.c
222
__raw_writel(__raw_readl(0xfe410000) | (1 << 21), 0xfe410000);
arch/sh/boot/romimage/mmcif-sh7724.c
42
__raw_writel(__raw_readl(MSTPCR2) & ~0x20000000, MSTPCR2);
arch/sh/boot/romimage/mmcif-sh7724.c
75
__raw_writel(__raw_readl(MSTPCR2) | 0x20000000, MSTPCR2);
arch/sh/drivers/dma/dma-pvr2.c
43
__raw_writel(0, PVR2_DMA_LMMODE0);
arch/sh/drivers/dma/dma-pvr2.c
60
__raw_writel(chan->dar, PVR2_DMA_ADDR);
arch/sh/drivers/dma/dma-pvr2.c
61
__raw_writel(chan->count, PVR2_DMA_COUNT);
arch/sh/drivers/dma/dma-pvr2.c
62
__raw_writel(chan->mode & DMA_MODE_MASK, PVR2_DMA_MODE);
arch/sh/drivers/dma/dma-sh.c
129
__raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR));
arch/sh/drivers/dma/dma-sh.c
163
__raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR));
arch/sh/drivers/dma/dma-sh.c
180
__raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR));
arch/sh/drivers/dma/dma-sh.c
200
__raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR));
arch/sh/drivers/dma/dma-sh.c
231
__raw_writel(chan->sar, (dma_base_addr(chan->chan) + SAR));
arch/sh/drivers/dma/dma-sh.c
234
__raw_writel(chan->dar, (dma_base_addr(chan->chan) + DAR));
arch/sh/drivers/dma/dma-sh.c
236
__raw_writel(chan->count >> calc_xmit_shift(chan),
arch/sh/drivers/dma/dmabrg.c
114
__raw_writel(dcr, DMABRGCR);
arch/sh/drivers/dma/dmabrg.c
122
__raw_writel(dcr, DMABRGCR);
arch/sh/drivers/dma/dmabrg.c
167
__raw_writel(0, DMABRGCR);
arch/sh/drivers/dma/dmabrg.c
168
__raw_writel(0, DMACHCR0);
arch/sh/drivers/dma/dmabrg.c
169
__raw_writel(0x94000000, DMARSRA); /* enable DMABRG in DMAC 0 */
arch/sh/drivers/dma/dmabrg.c
173
__raw_writel(or | DMAOR_BRG | DMAOR_DMEN, DMAOR);
arch/sh/drivers/dma/dmabrg.c
90
__raw_writel(dcr & ~0x00ff0003, DMABRGCR); /* ack all */
arch/sh/drivers/pci/pci-sh4.h
173
__raw_writel(val, chan->reg_base + reg);
arch/sh/drivers/pci/pci-sh7751.c
96
__raw_writel(reg, SH7751_BCR1);
arch/sh/drivers/pci/pci-sh7780.c
127
__raw_writel(cmd, hose->reg_base + SH4_PCIAINT);
arch/sh/drivers/pci/pci-sh7780.c
140
__raw_writel(cmd, hose->reg_base + SH4_PCIINT);
arch/sh/drivers/pci/pci-sh7780.c
154
__raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM);
arch/sh/drivers/pci/pci-sh7780.c
169
__raw_writel(0, hose->reg_base + SH4_PCIAINT);
arch/sh/drivers/pci/pci-sh7780.c
200
__raw_writel(SH4_PCIAINT_MBKN | SH4_PCIAINT_TBTO | SH4_PCIAINT_MBTO | \
arch/sh/drivers/pci/pci-sh7780.c
205
__raw_writel(SH4_PCIINTM_TTADIM | SH4_PCIINTM_TMTOIM | \
arch/sh/drivers/pci/pci-sh7780.c
231
__raw_writel(tmp, hose->reg_base + SH4_PCICR);
arch/sh/drivers/pci/pci-sh7780.c
241
__raw_writel(tmp, hose->reg_base + SH4_PCICR);
arch/sh/drivers/pci/pci-sh7780.c
258
__raw_writel(PCIECR_ENBL, PCIECR);
arch/sh/drivers/pci/pci-sh7780.c
261
__raw_writel(SH4_PCICR_PREFIX | SH4_PCICR_PRST | PCICR_ENDIANNESS,
arch/sh/drivers/pci/pci-sh7780.c
296
__raw_writel(SH4_PCICR_PREFIX | PCICR_ENDIANNESS,
arch/sh/drivers/pci/pci-sh7780.c
307
__raw_writel(memphys + SZ_512M, chan->reg_base + SH4_PCILAR1);
arch/sh/drivers/pci/pci-sh7780.c
308
__raw_writel((((memsize - SZ_512M) - SZ_1M) & 0x1ff00000) | 1,
arch/sh/drivers/pci/pci-sh7780.c
315
__raw_writel(0, chan->reg_base + SH4_PCILAR1);
arch/sh/drivers/pci/pci-sh7780.c
316
__raw_writel(0, chan->reg_base + SH4_PCILSR1);
arch/sh/drivers/pci/pci-sh7780.c
323
__raw_writel(memphys, chan->reg_base + SH4_PCILAR0);
arch/sh/drivers/pci/pci-sh7780.c
324
__raw_writel(((memsize - SZ_1M) & 0x1ff00000) | 1,
arch/sh/drivers/pci/pci-sh7780.c
337
__raw_writel(0, chan->reg_base + SH7780_PCICSCR0);
arch/sh/drivers/pci/pci-sh7780.c
338
__raw_writel(0, chan->reg_base + SH7780_PCICSAR0);
arch/sh/drivers/pci/pci-sh7780.c
339
__raw_writel(0, chan->reg_base + SH7780_PCICSCR1);
arch/sh/drivers/pci/pci-sh7780.c
340
__raw_writel(0, chan->reg_base + SH7780_PCICSAR1);
arch/sh/drivers/pci/pci-sh7780.c
367
__raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,
arch/sh/drivers/pci/pci-sh7780.c
369
__raw_writel(res->start, chan->reg_base + SH7780_PCIMBR(i - 1));
arch/sh/drivers/pci/pci-sh7780.c
375
__raw_writel(0, chan->reg_base + PCI_BASE_ADDRESS_0);
arch/sh/drivers/pci/pci-sh7780.c
376
__raw_writel(0, chan->reg_base + SH7780_PCIIOBR);
arch/sh/drivers/pci/pci-sh7780.c
377
__raw_writel(0, chan->reg_base + SH7780_PCIIOBMR);
arch/sh/drivers/pci/pci-sh7780.c
387
__raw_writel(SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO |
arch/sh/drivers/pci/pcie-sh7786.h
568
__raw_writel(val, chan->reg_base + reg);
arch/sh/include/asm/io.h
45
#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c))
arch/sh/include/asm/mmu_context.h
150
__raw_writel(MMU_CONTROL_INIT, MMUCR);
arch/sh/include/asm/mmu_context.h
165
__raw_writel(cr, MMUCR);
arch/sh/include/asm/mmu_context_32.h
44
__raw_writel((unsigned long)pgd, MMU_TTB);
arch/sh/include/asm/mmu_context_32.h
8
__raw_writel(asid, MMU_PTEAEX);
arch/sh/include/asm/watchdog.h
113
__raw_writel((WTCSR_HIGH << 24) | (__u32)val, WTCSR);
arch/sh/include/asm/watchdog.h
80
__raw_writel((WTCNT_HIGH << 24) | (__u32)val, WTCNT);
arch/sh/include/asm/watchdog.h
92
__raw_writel((WTBST_HIGH << 24) | (__u32)val, WTBST);
arch/sh/include/mach-common/mach/magicpanelr2.h
21
#define SETBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) | mask, reg)
arch/sh/include/mach-common/mach/magicpanelr2.h
24
#define CLRBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) & ~mask, reg)
arch/sh/kernel/cpu/init.c
156
__raw_writel(0, addr);
arch/sh/kernel/cpu/init.c
189
__raw_writel(flags, SH_CCR);
arch/sh/kernel/cpu/init.c
62
__raw_writel(__raw_readl(CPUOPM) & ~CPUOPM_RABD, CPUOPM);
arch/sh/kernel/cpu/init.c
91
__raw_writel(expmask, EXPMASK);
arch/sh/kernel/cpu/sh2/probe.c
49
if (j2_ccr_base) __raw_writel(0x80000303, j2_ccr_base + 4*cpu);
arch/sh/kernel/cpu/sh2/smp-j2.c
122
__raw_writel(val | (1U<<28), j2_ipi_trigger + cpu);
arch/sh/kernel/cpu/sh2/smp-j2.c
94
__raw_writel(entry_point, initpc);
arch/sh/kernel/cpu/sh2/smp-j2.c
95
__raw_writel(1, release);
arch/sh/kernel/cpu/sh3/probe.c
31
__raw_writel(data0&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr0);
arch/sh/kernel/cpu/sh3/probe.c
33
__raw_writel(data1&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr1);
arch/sh/kernel/cpu/sh3/probe.c
38
__raw_writel(data0, addr0);
arch/sh/kernel/cpu/sh3/probe.c
41
__raw_writel(data2, addr1);
arch/sh/kernel/cpu/sh3/probe.c
45
__raw_writel(data0&~SH_CACHE_VALID, addr0);
arch/sh/kernel/cpu/sh3/probe.c
46
__raw_writel(data2&~SH_CACHE_VALID, addr1);
arch/sh/kernel/cpu/sh3/probe.c
94
__raw_writel(CCR_CACHE_32KB, CCR3_REG);
arch/sh/kernel/cpu/sh3/probe.c
96
__raw_writel(CCR_CACHE_16KB, CCR3_REG);
arch/sh/kernel/cpu/sh4/sq.c
125
__raw_writel(((map->addr >> 26) << 2) & 0x1c, SQ_QACR0);
arch/sh/kernel/cpu/sh4/sq.c
126
__raw_writel(((map->addr >> 26) << 2) & 0x1c, SQ_QACR1);
arch/sh/kernel/cpu/sh4/sq.c
45
__raw_writel(0, P4SEG_STORE_QUE + 0); \
arch/sh/kernel/cpu/sh4/sq.c
46
__raw_writel(0, P4SEG_STORE_QUE + 8); \
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
133
__raw_writel(value, FRQCRA);
arch/sh/kernel/cpu/sh4a/intc-shx3.c
23
__raw_writel(irq2evt(irq), INTACKCLR);
arch/sh/kernel/cpu/sh4a/perf_event.c
238
__raw_writel(tmp, PPC_CCBR(idx));
arch/sh/kernel/cpu/sh4a/perf_event.c
248
__raw_writel(tmp, PPC_PMCAT);
arch/sh/kernel/cpu/sh4a/perf_event.c
252
__raw_writel(tmp, PPC_CCBR(idx));
arch/sh/kernel/cpu/sh4a/perf_event.c
254
__raw_writel(__raw_readl(PPC_CCBR(idx)) | CCBR_DUC, PPC_CCBR(idx));
arch/sh/kernel/cpu/sh4a/perf_event.c
262
__raw_writel(__raw_readl(PPC_CCBR(i)) & ~CCBR_DUC, PPC_CCBR(i));
arch/sh/kernel/cpu/sh4a/perf_event.c
270
__raw_writel(__raw_readl(PPC_CCBR(i)) | CCBR_DUC, PPC_CCBR(i));
arch/sh/kernel/cpu/sh4a/setup-sh7723.c
428
__raw_writel(L2_CACHE_ENABLE, RAMCR);
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1218
__raw_writel(sh7724_rstandby_state.mmselr, 0xff800020); /* MMSELR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1219
__raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004); /* CS0BCR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1220
__raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010); /* CS4BCR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1221
__raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014); /* CS5ABCR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1222
__raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018); /* CS5BBCR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1223
__raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c); /* CS6ABCR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1224
__raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020); /* CS6BBCR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1225
__raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030); /* CS4WCR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1226
__raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034); /* CS5AWCR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1227
__raw_writel(sh7724_rstandby_state.cs5bwcr, 0xfec10038); /* CS5BWCR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1228
__raw_writel(sh7724_rstandby_state.cs6awcr, 0xfec1003c); /* CS6AWCR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1229
__raw_writel(sh7724_rstandby_state.cs6bwcr, 0xfec10040); /* CS6BWCR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1263
__raw_writel(sh7724_rstandby_state.irdaclk, 0xa4150018); /* IRDACLKCR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1264
__raw_writel(sh7724_rstandby_state.spuclk, 0xa415003c); /* SPUCLKCR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
846
__raw_writel(L2_CACHE_ENABLE, RAMCR);
arch/sh/kernel/cpu/sh4a/setup-sh7734.c
586
__raw_writel(0xF0000000, INTC_INTMSK0);
arch/sh/kernel/cpu/sh4a/setup-sh7734.c
589
__raw_writel(0x80000000, INTC_INTMSK1);
arch/sh/kernel/cpu/sh4a/setup-sh7734.c
592
__raw_writel(__raw_readl(INTC_ICR0) & ~0x00800000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7734.c
595
__raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7734.c
605
__raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7734.c
610
__raw_writel(0x80000000, INTC_INTMSKCLR1);
arch/sh/kernel/cpu/sh4a/setup-sh7734.c
611
__raw_writel(0xf0000000, INTC_INTMSKCLR0);
arch/sh/kernel/cpu/sh4a/setup-sh7734.c
615
__raw_writel(0x80000000, INTC_INTMSKCLR0);
arch/sh/kernel/cpu/sh4a/setup-sh7757.c
1190
__raw_writel(0xff000000, INTC_INTMSK0);
arch/sh/kernel/cpu/sh4a/setup-sh7757.c
1193
__raw_writel(0xc0000000, INTC_INTMSK1);
arch/sh/kernel/cpu/sh4a/setup-sh7757.c
1194
__raw_writel(0xfffefffe, INTC_INTMSK2);
arch/sh/kernel/cpu/sh4a/setup-sh7757.c
1197
__raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7757.c
1200
__raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7757.c
1210
__raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7757.c
1215
__raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7757.c
1220
__raw_writel(0x40000000, INTC_INTMSKCLR1);
arch/sh/kernel/cpu/sh4a/setup-sh7757.c
1221
__raw_writel(0x0000fffe, INTC_INTMSKCLR2);
arch/sh/kernel/cpu/sh4a/setup-sh7757.c
1225
__raw_writel(0x80000000, INTC_INTMSKCLR1);
arch/sh/kernel/cpu/sh4a/setup-sh7757.c
1226
__raw_writel(0xfffe0000, INTC_INTMSKCLR2);
arch/sh/kernel/cpu/sh4a/setup-sh7757.c
1230
__raw_writel(0x40000000, INTC_INTMSKCLR1);
arch/sh/kernel/cpu/sh4a/setup-sh7757.c
1235
__raw_writel(0x80000000, INTC_INTMSKCLR1);
arch/sh/kernel/cpu/sh4a/setup-sh7763.c
415
__raw_writel(0xff000000, INTC_INTMSK0);
arch/sh/kernel/cpu/sh4a/setup-sh7763.c
418
__raw_writel(0xc0000000, INTC_INTMSK1);
arch/sh/kernel/cpu/sh4a/setup-sh7763.c
419
__raw_writel(0xfffefffe, INTC_INTMSK2);
arch/sh/kernel/cpu/sh4a/setup-sh7763.c
429
__raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7763.c
434
__raw_writel(0x40000000, INTC_INTMSKCLR1);
arch/sh/kernel/cpu/sh4a/setup-sh7763.c
435
__raw_writel(0x0000fffe, INTC_INTMSKCLR2);
arch/sh/kernel/cpu/sh4a/setup-sh7763.c
439
__raw_writel(0x80000000, INTC_INTMSKCLR1);
arch/sh/kernel/cpu/sh4a/setup-sh7763.c
440
__raw_writel(0xfffe0000, INTC_INTMSKCLR2);
arch/sh/kernel/cpu/sh4a/setup-sh7763.c
444
__raw_writel(0x40000000, INTC_INTMSKCLR1);
arch/sh/kernel/cpu/sh4a/setup-sh7763.c
449
__raw_writel(0x80000000, INTC_INTMSKCLR1);
arch/sh/kernel/cpu/sh4a/setup-sh7770.c
525
__raw_writel(0xff000000, INTC_INTMSK0);
arch/sh/kernel/cpu/sh4a/setup-sh7770.c
528
__raw_writel(0xc0000000, INTC_INTMSK1);
arch/sh/kernel/cpu/sh4a/setup-sh7770.c
529
__raw_writel(0xfffefffe, INTC_INTMSK2);
arch/sh/kernel/cpu/sh4a/setup-sh7770.c
532
__raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7770.c
535
__raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7770.c
545
__raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7770.c
550
__raw_writel(0x40000000, INTC_INTMSKCLR1);
arch/sh/kernel/cpu/sh4a/setup-sh7770.c
551
__raw_writel(0x0000fffe, INTC_INTMSKCLR2);
arch/sh/kernel/cpu/sh4a/setup-sh7770.c
555
__raw_writel(0x80000000, INTC_INTMSKCLR1);
arch/sh/kernel/cpu/sh4a/setup-sh7770.c
556
__raw_writel(0xfffe0000, INTC_INTMSKCLR2);
arch/sh/kernel/cpu/sh4a/setup-sh7770.c
560
__raw_writel(0x40000000, INTC_INTMSKCLR1);
arch/sh/kernel/cpu/sh4a/setup-sh7770.c
565
__raw_writel(0x80000000, INTC_INTMSKCLR1);
arch/sh/kernel/cpu/sh4a/setup-sh7780.c
459
__raw_writel(0xff000000, INTC_INTMSK0);
arch/sh/kernel/cpu/sh4a/setup-sh7780.c
462
__raw_writel(0xc0000000, INTC_INTMSK1);
arch/sh/kernel/cpu/sh4a/setup-sh7780.c
463
__raw_writel(0xfffefffe, INTC_INTMSK2);
arch/sh/kernel/cpu/sh4a/setup-sh7780.c
466
__raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7780.c
469
__raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7780.c
479
__raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7780.c
484
__raw_writel(0x40000000, INTC_INTMSKCLR1);
arch/sh/kernel/cpu/sh4a/setup-sh7780.c
485
__raw_writel(0x0000fffe, INTC_INTMSKCLR2);
arch/sh/kernel/cpu/sh4a/setup-sh7780.c
489
__raw_writel(0x80000000, INTC_INTMSKCLR1);
arch/sh/kernel/cpu/sh4a/setup-sh7780.c
490
__raw_writel(0xfffe0000, INTC_INTMSKCLR2);
arch/sh/kernel/cpu/sh4a/setup-sh7780.c
494
__raw_writel(0x40000000, INTC_INTMSKCLR1);
arch/sh/kernel/cpu/sh4a/setup-sh7780.c
499
__raw_writel(0x80000000, INTC_INTMSKCLR1);
arch/sh/kernel/cpu/sh4a/setup-sh7785.c
551
__raw_writel(0xff000000, INTC_INTMSK0);
arch/sh/kernel/cpu/sh4a/setup-sh7785.c
554
__raw_writel(0xc0000000, INTC_INTMSK1);
arch/sh/kernel/cpu/sh4a/setup-sh7785.c
555
__raw_writel(0xfffefffe, INTC_INTMSK2);
arch/sh/kernel/cpu/sh4a/setup-sh7785.c
558
__raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7785.c
561
__raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7785.c
571
__raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7785.c
576
__raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7785.c
581
__raw_writel(0x40000000, INTC_INTMSKCLR1);
arch/sh/kernel/cpu/sh4a/setup-sh7785.c
582
__raw_writel(0x0000fffe, INTC_INTMSKCLR2);
arch/sh/kernel/cpu/sh4a/setup-sh7785.c
586
__raw_writel(0x80000000, INTC_INTMSKCLR1);
arch/sh/kernel/cpu/sh4a/setup-sh7785.c
587
__raw_writel(0xfffe0000, INTC_INTMSKCLR2);
arch/sh/kernel/cpu/sh4a/setup-sh7785.c
591
__raw_writel(0x40000000, INTC_INTMSKCLR1);
arch/sh/kernel/cpu/sh4a/setup-sh7785.c
596
__raw_writel(0x80000000, INTC_INTMSKCLR1);
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
427
__raw_writel(USBINITVAL1, USBINITREG1);
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
428
__raw_writel(USBINITVAL2, USBINITREG2);
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
433
__raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
437
__raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
736
__raw_writel(0xff000000, INTC_INTMSK0);
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
739
__raw_writel(0xc0000000, INTC_INTMSK1);
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
740
__raw_writel(0xfffefffe, INTC_INTMSK2);
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
743
__raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
753
__raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
758
__raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
763
__raw_writel(0x40000000, INTC_INTMSKCLR1);
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
764
__raw_writel(0x0000fffe, INTC_INTMSKCLR2);
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
768
__raw_writel(0x80000000, INTC_INTMSKCLR1);
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
769
__raw_writel(0xfffe0000, INTC_INTMSKCLR2);
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
773
__raw_writel(0x40000000, INTC_INTMSKCLR1);
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
778
__raw_writel(0x80000000, INTC_INTMSKCLR1);
arch/sh/kernel/cpu/sh4a/smp-shx3.c
112
__raw_writel(1 << (message << 2), addr); /* C0INTICI..CnINTICI */
arch/sh/kernel/cpu/sh4a/smp-shx3.c
117
__raw_writel(STBCR_MSTP, STBCR_REG(cpu));
arch/sh/kernel/cpu/sh4a/smp-shx3.c
120
__raw_writel(STBCR_RESET, STBCR_REG(cpu));
arch/sh/kernel/cpu/sh4a/smp-shx3.c
36
__raw_writel(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */
arch/sh/kernel/cpu/sh4a/smp-shx3.c
51
__raw_writel(__raw_readl(STBCR_REG(cpu)) | STBCR_LTSLP, STBCR_REG(cpu));
arch/sh/kernel/cpu/sh4a/smp-shx3.c
87
__raw_writel(entry_point, RESET_REG(cpu));
arch/sh/kernel/cpu/sh4a/smp-shx3.c
89
__raw_writel(virt_to_phys(entry_point), RESET_REG(cpu));
arch/sh/kernel/cpu/sh4a/smp-shx3.c
92
__raw_writel(STBCR_MSTP, STBCR_REG(cpu));
arch/sh/kernel/cpu/sh4a/smp-shx3.c
98
__raw_writel(STBCR_RESET | STBCR_LTSLP, STBCR_REG(cpu));
arch/sh/kernel/cpu/sh4a/ubc.c
112
__raw_writel(0, UBC_CBCR);
arch/sh/kernel/cpu/sh4a/ubc.c
115
__raw_writel(0, UBC_CAMR(i));
arch/sh/kernel/cpu/sh4a/ubc.c
116
__raw_writel(0, UBC_CBR(i));
arch/sh/kernel/cpu/sh4a/ubc.c
118
__raw_writel(UBC_CRR_BIE | UBC_CRR_PCB, UBC_CRR(i));
arch/sh/kernel/cpu/sh4a/ubc.c
34
__raw_writel(UBC_CBR_CE | info->len | info->type, UBC_CBR(idx));
arch/sh/kernel/cpu/sh4a/ubc.c
35
__raw_writel(info->address, UBC_CAR(idx));
arch/sh/kernel/cpu/sh4a/ubc.c
40
__raw_writel(0, UBC_CBR(idx));
arch/sh/kernel/cpu/sh4a/ubc.c
41
__raw_writel(0, UBC_CAR(idx));
arch/sh/kernel/cpu/sh4a/ubc.c
50
__raw_writel(__raw_readl(UBC_CBR(i)) | UBC_CBR_CE,
arch/sh/kernel/cpu/sh4a/ubc.c
59
__raw_writel(__raw_readl(UBC_CBR(i)) & ~UBC_CBR_CE,
arch/sh/kernel/cpu/sh4a/ubc.c
82
__raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR);
arch/sh/kernel/dwarf.c
248
__raw_writel(decoded_addr, val);
arch/sh/kernel/ftrace.c
272
__raw_writel(new_addr, ip);
arch/sh/kernel/ftrace.c
363
__raw_writel(old, parent);
arch/sh/kernel/ftrace.c
50
__raw_writel(ip + MCOUNT_INSN_SIZE, ftrace_nop);
arch/sh/kernel/ftrace.c
57
__raw_writel(addr, ftrace_replaced_code);
arch/sh/kernel/io_trapped.c
211
__raw_writel(tmp, dst_addr);
arch/sh/mm/cache-j2.c
31
__raw_writel(CACHE_ENABLE | ICACHE_FLUSH, j2_ccr_base + cpu);
arch/sh/mm/cache-j2.c
38
__raw_writel(CACHE_ENABLE | DCACHE_FLUSH, j2_ccr_base + cpu);
arch/sh/mm/cache-j2.c
45
__raw_writel(CACHE_ENABLE | CACHE_FLUSH, j2_ccr_base + cpu);
arch/sh/mm/cache-sh2.c
33
__raw_writel(data, addr | (way << 12));
arch/sh/mm/cache-sh2.c
49
__raw_writel((v & CACHE_PHYSADDR_MASK),
arch/sh/mm/cache-sh2.c
67
__raw_writel(ccr, SH_CCR);
arch/sh/mm/cache-sh2.c
80
__raw_writel((v & CACHE_PHYSADDR_MASK),
arch/sh/mm/cache-sh2a.c
136
__raw_writel(__raw_readl(SH_CCR) | CCR_OCACHE_INVALIDATE,
arch/sh/mm/cache-sh2a.c
170
__raw_writel(__raw_readl(SH_CCR) | CCR_ICACHE_INVALIDATE,
arch/sh/mm/cache-sh2a.c
34
__raw_writel(data, CACHE_OC_ADDRESS_ARRAY | addr);
arch/sh/mm/cache-sh2a.c
43
__raw_writel((addr & CACHE_PHYSADDR_MASK), cache_addr | addr);
arch/sh/mm/cache-sh2a.c
73
__raw_writel(data & ~SH_CACHE_UPDATED, v);
arch/sh/mm/cache-sh3.c
55
__raw_writel(data, addr);
arch/sh/mm/cache-sh3.c
86
__raw_writel(data, addr);
arch/sh/mm/cache-sh4.c
148
__raw_writel(ccr, SH_CCR);
arch/sh/mm/cache-sh4.c
171
__raw_writel(0, addr); addr += entry_offset;
arch/sh/mm/cache-sh4.c
172
__raw_writel(0, addr); addr += entry_offset;
arch/sh/mm/cache-sh4.c
173
__raw_writel(0, addr); addr += entry_offset;
arch/sh/mm/cache-sh4.c
174
__raw_writel(0, addr); addr += entry_offset;
arch/sh/mm/cache-sh4.c
175
__raw_writel(0, addr); addr += entry_offset;
arch/sh/mm/cache-sh4.c
176
__raw_writel(0, addr); addr += entry_offset;
arch/sh/mm/cache-sh4.c
177
__raw_writel(0, addr); addr += entry_offset;
arch/sh/mm/cache-sh4.c
178
__raw_writel(0, addr); addr += entry_offset;
arch/sh/mm/cache-sh4.c
80
__raw_writel(0, icacheaddr + (j * PAGE_SIZE));
arch/sh/mm/cache-sh7705.c
120
__raw_writel(data, addr);
arch/sh/mm/cache-sh7705.c
53
__raw_writel(data & ~v, addr);
arch/sh/mm/pmb.c
302
__raw_writel(pmbe->vpn | PMB_V, addr);
arch/sh/mm/pmb.c
303
__raw_writel(pmbe->ppn | pmbe->flags | PMB_V, data);
arch/sh/mm/tlb-pteaex.c
101
__raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));
arch/sh/mm/tlb-pteaex.c
32
__raw_writel(vpn, MMU_PTEH);
arch/sh/mm/tlb-pteaex.c
35
__raw_writel(get_asid(), MMU_PTEAEX);
arch/sh/mm/tlb-pteaex.c
47
__raw_writel(pte.pte_high, MMU_PTEA);
arch/sh/mm/tlb-pteaex.c
56
__raw_writel(pteval, MMU_PTEL);
arch/sh/mm/tlb-pteaex.c
73
__raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT);
arch/sh/mm/tlb-pteaex.c
74
__raw_writel(asid, MMU_UTLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT);
arch/sh/mm/tlb-pteaex.c
75
__raw_writel(page, MMU_ITLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT);
arch/sh/mm/tlb-pteaex.c
76
__raw_writel(asid, MMU_ITLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT);
arch/sh/mm/tlb-pteaex.c
98
__raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
arch/sh/mm/tlb-sh3.c
41
__raw_writel(vpn, MMU_PTEH);
arch/sh/mm/tlb-sh3.c
48
__raw_writel(pteval, MMU_PTEL);
arch/sh/mm/tlb-sh3.c
75
__raw_writel(data, addr + (i << 8));
arch/sh/mm/tlb-sh3.c
92
__raw_writel(status, MMUCR);
arch/sh/mm/tlb-sh4.c
100
__raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
arch/sh/mm/tlb-sh4.c
103
__raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));
arch/sh/mm/tlb-sh4.c
30
__raw_writel(vpn, MMU_PTEH);
arch/sh/mm/tlb-sh4.c
42
__raw_writel(pte.pte_high, MMU_PTEA);
arch/sh/mm/tlb-sh4.c
48
__raw_writel(copy_ptea_attributes(pteval), MMU_PTEA);
arch/sh/mm/tlb-sh4.c
58
__raw_writel(pteval, MMU_PTEL);
arch/sh/mm/tlb-sh4.c
78
__raw_writel(data, addr);
arch/sh/mm/tlb-urb.c
43
__raw_writel(status, MMUCR);
arch/sh/mm/tlb-urb.c
55
__raw_writel(status, MMUCR);
arch/sh/mm/tlb-urb.c
89
__raw_writel(status, MMUCR);
arch/sh/mm/tlbflush_32.c
134
__raw_writel(__raw_readl(MMUCR) | MMUCR_TI, MMUCR);
arch/sparc/include/asm/io.h
19
#define writel_be(__w, __addr) __raw_writel(__w, __addr)
arch/sparc/include/asm/io_64.h
336
__raw_writel(l, addr);
arch/sparc/include/asm/io_64.h
448
#define iowrite32be __raw_writel
arch/sparc/include/asm/io_64.h
85
#define __raw_writel __raw_writel
arch/sparc/kernel/leon_pci_grpci1.c
50
#define REGSTORE(a, v) (__raw_writel(cpu_to_be32(v), &(a)))
arch/sparc/kernel/leon_pci_grpci2.c
95
#define REGSTORE(a, v) (__raw_writel(cpu_to_be32(v), &(a)))
arch/sparc/lib/PeeCeeI.c
46
__raw_writel(*(u32 *)src, addr);
arch/sparc/lib/PeeCeeI.c
55
__raw_writel(l, addr);
arch/sparc/lib/PeeCeeI.c
67
__raw_writel(l, addr);
arch/sparc/lib/PeeCeeI.c
79
__raw_writel(l, addr);
drivers/ata/ahci_brcm.c
113
__raw_writel(val, addr);
drivers/ata/pata_imx.c
177
__raw_writel(PATA_IMX_ATA_CTRL_FIFO_RST_B |
drivers/ata/pata_imx.c
181
__raw_writel(PATA_IMX_ATA_INTR_ATA_INTRQ2,
drivers/ata/pata_imx.c
201
__raw_writel(0, priv->host_regs + PATA_IMX_ATA_INT_EN);
drivers/ata/pata_imx.c
212
__raw_writel(0, priv->host_regs + PATA_IMX_ATA_INT_EN);
drivers/ata/pata_imx.c
228
__raw_writel(priv->ata_ctl, priv->host_regs + PATA_IMX_ATA_CONTROL);
drivers/ata/pata_imx.c
230
__raw_writel(PATA_IMX_ATA_INTR_ATA_INTRQ2,
drivers/ata/pata_imx.c
97
__raw_writel(val, priv->host_regs + PATA_IMX_ATA_CONTROL);
drivers/auxdisplay/img-ascii-lcd.c
64
__raw_writel(val, ctx->base);
drivers/auxdisplay/img-ascii-lcd.c
66
__raw_writel(val, ctx->base + 4);
drivers/bcma/host_soc.c
126
__raw_writel((__force u32)(*buf), addr);
drivers/cdrom/gdrom.c
390
__raw_writel(0x1fffff, GDROM_RESET_REG);
drivers/cdrom/gdrom.c
585
__raw_writel(page_to_phys(bio_page(req->bio)) + bio_offset(req->bio),
drivers/cdrom/gdrom.c
587
__raw_writel(block_cnt * GDROM_HARD_SECTOR, GDROM_DMA_LENGTH_REG);
drivers/cdrom/gdrom.c
588
__raw_writel(1, GDROM_DMA_DIRECTION_REG);
drivers/cdrom/gdrom.c
589
__raw_writel(1, GDROM_DMA_ENABLE_REG);
drivers/cdrom/gdrom.c
702
__raw_writel(0x8843407F, GDROM_DMA_ACCESS_CTRL_REG);
drivers/cdrom/gdrom.c
703
__raw_writel(9, GDROM_DMA_WAIT_REG); /* DMA word setting */
drivers/char/hw_random/bcm2835-rng.c
58
__raw_writel(val, priv->base + offset);
drivers/char/hw_random/mxc-rnga.c
107
__raw_writel(ctrl & ~RNGA_CONTROL_SLEEP, mxc_rng->mem + RNGA_CONTROL);
drivers/char/hw_random/mxc-rnga.c
118
__raw_writel(ctrl | RNGA_CONTROL_GO, mxc_rng->mem + RNGA_CONTROL);
drivers/char/hw_random/mxc-rnga.c
131
__raw_writel(ctrl & ~RNGA_CONTROL_GO, mxc_rng->mem + RNGA_CONTROL);
drivers/char/hw_random/mxc-rnga.c
93
__raw_writel(ctrl | RNGA_CONTROL_CLEAR_INT,
drivers/char/hw_random/omap-rng.c
169
__raw_writel(val, priv->base + priv->pdata->regs[reg]);
drivers/clk/bcm/clk-bcm63268-timer.c
96
__raw_writel(val, reset->regs);
drivers/clk/imx/clk-pllv2.c
172
__raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
drivers/clk/imx/clk-pllv2.c
174
__raw_writel(dp_op, pllbase + MXC_PLL_DP_OP);
drivers/clk/imx/clk-pllv2.c
175
__raw_writel(dp_mfd, pllbase + MXC_PLL_DP_MFD);
drivers/clk/imx/clk-pllv2.c
176
__raw_writel(dp_mfn, pllbase + MXC_PLL_DP_MFN);
drivers/clk/imx/clk-pllv2.c
211
__raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
drivers/clk/imx/clk-pllv2.c
238
__raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
drivers/clk/samsung/clk-exynos3250.c
791
__raw_writel(tmp, reg_base + PWR_CTRL1);
drivers/clk/samsung/clk-exynos3250.c
797
__raw_writel(0x0, reg_base + PWR_CTRL2);
drivers/clk/samsung/clk-exynos5250.c
845
__raw_writel(tmp, reg_base + PWR_CTRL1);
drivers/clk/samsung/clk-exynos5250.c
855
__raw_writel(tmp, reg_base + PWR_CTRL2);
drivers/clk/tegra/clk-dfll.c
339
__raw_writel(val, td->base + offs);
drivers/clk/tegra/clk-dfll.c
356
__raw_writel(val, td->i2c_base + offs);
drivers/clk/tegra/clk-dfll.c
691
__raw_writel(val, td->lut_base + i * 4);
drivers/clk/tegra/clk-dfll.c
729
__raw_writel(val, td->i2c_controller_base + DFLL_I2C_CLK_DIVISOR);
drivers/clk/ti/clk-dra7-atl.c
64
__raw_writel(val, cinfo->iobase + reg);
drivers/clocksource/mxs_timer.c
105
__raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0));
drivers/clocksource/mxs_timer.c
127
__raw_writel(0xffff, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
drivers/clocksource/mxs_timer.c
129
__raw_writel(0xffffffff,
drivers/clocksource/mxs_timer.c
234
__raw_writel((timrot_is_v1() ?
drivers/clocksource/mxs_timer.c
242
__raw_writel((timrot_is_v1() ?
drivers/clocksource/mxs_timer.c
250
__raw_writel(0xffff,
drivers/clocksource/mxs_timer.c
253
__raw_writel(0xffffffff,
drivers/clocksource/mxs_timer.c
70
__raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base +
drivers/clocksource/mxs_timer.c
76
__raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base +
drivers/clocksource/mxs_timer.c
82
__raw_writel(BM_TIMROT_TIMCTRLn_IRQ, mxs_timrot_base +
drivers/clocksource/mxs_timer.c
96
__raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0));
drivers/clocksource/timer-ixp4xx.c
105
__raw_writel((cycles & ~IXP4XX_OST_RELOAD_MASK) | val,
drivers/clocksource/timer-ixp4xx.c
118
__raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
drivers/clocksource/timer-ixp4xx.c
127
__raw_writel(IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT,
drivers/clocksource/timer-ixp4xx.c
140
__raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
drivers/clocksource/timer-ixp4xx.c
152
__raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
drivers/clocksource/timer-ixp4xx.c
187
__raw_writel(0, tmr->base + IXP4XX_OSRT1_OFFSET);
drivers/clocksource/timer-ixp4xx.c
190
__raw_writel(IXP4XX_OSST_TIMER_1_PEND,
drivers/clocksource/timer-ixp4xx.c
194
__raw_writel(0, tmr->base + IXP4XX_OSTS_OFFSET);
drivers/clocksource/timer-ixp4xx.c
88
__raw_writel(IXP4XX_OSST_TIMER_1_PEND,
drivers/crypto/inside-secure/eip93/eip93-main.c
67
__raw_writel(mask, eip93->base + EIP93_REG_MASK_DISABLE);
drivers/crypto/inside-secure/eip93/eip93-main.c
72
__raw_writel(mask, eip93->base + EIP93_REG_MASK_ENABLE);
drivers/crypto/inside-secure/eip93/eip93-main.c
77
__raw_writel(mask, eip93->base + EIP93_REG_INT_CLR);
drivers/crypto/intel/qat/qat_common/adf_accel_devices.h
360
__raw_writel(val, csr_base + csr_offset)
drivers/crypto/omap-aes.c
68
__raw_writel(value, dd->io_base + offset); \
drivers/crypto/omap-aes.c
74
__raw_writel(value, dd->io_base + offset);
drivers/crypto/omap-des.c
188
__raw_writel(value, dd->io_base + offset); \
drivers/crypto/omap-des.c
194
__raw_writel(value, dd->io_base + offset);
drivers/crypto/omap-sham.c
257
__raw_writel(value, dd->io_base + offset);
drivers/crypto/s5p-sss.c
145
#define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg))
drivers/crypto/s5p-sss.c
148
#define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \
drivers/crypto/s5p-sss.c
600
__raw_writel(value, dd->io_hash_base + offset);
drivers/dma/at_hdmac.c
301
__raw_writel((val), (atchan)->ch_regs + ATC_##name##_OFFSET)
drivers/dma/at_hdmac.c
364
__raw_writel((val), (atdma)->regs + AT_DMA_##name)
drivers/dma/imx-dma.c
238
__raw_writel(val, imxdma->base + offset);
drivers/dma/sh/shdmac.c
102
__raw_writel(data, addr);
drivers/dma/sh/shdmac.c
111
__raw_writel(data, sh_dc->base + shdev->chcr_offset);
drivers/dma/sh/shdmac.c
74
__raw_writel(val, shdev->chan_reg + chan_pdata->chclr_offset);
drivers/dma/sh/shdmac.c
79
__raw_writel(data, sh_dc->base + reg);
drivers/dma/ti/cppi41.c
280
__raw_writel(val, mem);
drivers/dma/ti/edma.c
307
__raw_writel(val, ecc->base + offset);
drivers/dma/txx9dmac.c
115
__raw_writel((val), &(__txx9dmac_regs(ddev)->name))
drivers/dma/txx9dmac.c
120
__raw_writel((val), &(__txx9dmac_regs32(ddev)->name))
drivers/dma/txx9dmac.c
42
__raw_writel((val), &(__dma_regs(dc)->name))
drivers/dma/txx9dmac.c
47
__raw_writel((val), &(__dma_regs32(dc)->name))
drivers/edac/cpc925_edac.c
390
__raw_writel(apimask, pdata->vbase + REG_APIMASK_OFFSET);
drivers/edac/cpc925_edac.c
397
__raw_writel(mccr, pdata->vbase + REG_MCCR_OFFSET);
drivers/edac/cpc925_edac.c
632
__raw_writel(apimask, dev_info->vbase + REG_APIMASK_OFFSET);
drivers/edac/cpc925_edac.c
685
__raw_writel(ht_errctrl, dev_info->vbase + REG_ERRCTRL_OFFSET);
drivers/edac/cpc925_edac.c
696
__raw_writel(ht_errctrl, dev_info->vbase + REG_ERRCTRL_OFFSET);
drivers/edac/cpc925_edac.c
727
__raw_writel(BRGCTRL_DETSERR,
drivers/edac/cpc925_edac.c
731
__raw_writel(HT_LINKCTRL_DETECTED,
drivers/edac/cpc925_edac.c
736
__raw_writel(BRGCTRL_SECBUSRESET,
drivers/edac/cpc925_edac.c
740
__raw_writel(ERRCTRL_RSP_ERR,
drivers/edac/cpc925_edac.c
744
__raw_writel(HT_LINKERR_DETECTED,
drivers/firmware/tegra/bpmp-tegra210.c
106
__raw_writel(SL_QUED(channel->index), priv->arb_sema + SET_OFFSET);
drivers/firmware/tegra/bpmp-tegra210.c
78
__raw_writel(CH_MASK(channel->index), priv->arb_sema + CLR_OFFSET);
drivers/firmware/tegra/bpmp-tegra210.c
87
__raw_writel(MA_ACKD(channel->index), priv->arb_sema + SET_OFFSET);
drivers/firmware/tegra/bpmp-tegra210.c
96
__raw_writel(MA_ACKD(channel->index) ^ MA_FREE(channel->index),
drivers/fpga/socfpga.c
154
__raw_writel(value, priv->fpga_base_addr + reg_offset);
drivers/gpio/gpio-ixp4xx.c
151
__raw_writel(val, g->base + int_reg);
drivers/gpio/gpio-ixp4xx.c
153
__raw_writel(BIT(line), g->base + IXP4XX_REG_GPIS);
drivers/gpio/gpio-ixp4xx.c
158
__raw_writel(val, g->base + int_reg);
drivers/gpio/gpio-ixp4xx.c
163
__raw_writel(val, g->base + IXP4XX_REG_GPOE);
drivers/gpio/gpio-ixp4xx.c
280
__raw_writel(val, g->base + IXP4XX_REG_GPCLK);
drivers/gpio/gpio-ixp4xx.c
75
__raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS);
drivers/gpio/gpio-loongson1.c
31
__raw_writel(__raw_readl(ls1x_gc->reg_base + GPIO_CFG) | BIT(offset),
drivers/gpio/gpio-loongson1.c
43
__raw_writel(__raw_readl(ls1x_gc->reg_base + GPIO_CFG) & ~BIT(offset),
drivers/gpio/gpio-lpc32xx.c
175
__raw_writel(val, group->reg_base + offset);
drivers/gpio/gpio-stp-xway.c
76
#define xway_stp_w32(m, val, reg) __raw_writel(val, m + reg)
drivers/gpio/gpio-xilinx.c
41
# define xgpio_writereg(offset, val) __raw_writel(val, offset)
drivers/gpu/drm/omapdrm/dss/dispc.c
358
__raw_writel(val, dispc->base + idx);
drivers/gpu/drm/omapdrm/dss/dsi.c
98
__raw_writel(val, base + idx.idx);
drivers/gpu/drm/omapdrm/dss/dss.c
98
__raw_writel(val, dss->base + idx.idx);
drivers/gpu/drm/omapdrm/dss/hdmi.h
269
__raw_writel(val, base_addr + idx);
drivers/gpu/drm/omapdrm/dss/venc.c
270
__raw_writel(val, venc->base + idx);
drivers/hwtracing/coresight/coresight-ctcu-core.c
24
#define ctcu_writel(drvdata, val, offset) __raw_writel((val), drvdata->base + offset)
drivers/i2c/busses/i2c-au1550.c
46
__raw_writel(v, a->psc_base + r);
drivers/i2c/busses/i2c-iop3xx.c
100
__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
drivers/i2c/busses/i2c-iop3xx.c
114
__raw_writel(sr, iop3xx_adap->ioaddr + SR_OFFSET);
drivers/i2c/busses/i2c-iop3xx.c
244
__raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET);
drivers/i2c/busses/i2c-iop3xx.c
249
__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
drivers/i2c/busses/i2c-iop3xx.c
263
__raw_writel(byte, iop3xx_adap->ioaddr + DBR_OFFSET);
drivers/i2c/busses/i2c-iop3xx.c
271
__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
drivers/i2c/busses/i2c-iop3xx.c
293
__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
drivers/i2c/busses/i2c-iop3xx.c
402
__raw_writel(cr, adapter_data->ioaddr + CR_OFFSET);
drivers/i2c/busses/i2c-iop3xx.c
59
__raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET);
drivers/i2c/busses/i2c-iop3xx.c
60
__raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET);
drivers/i2c/busses/i2c-iop3xx.c
61
__raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET);
drivers/i2c/busses/i2c-iop3xx.c
89
__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
drivers/i2c/busses/i2c-sh7760.c
104
__raw_writel(val, (unsigned long)cam->iobase + reg);
drivers/iio/adc/lpc32xx_adc.c
77
__raw_writel(LPC32XXAD_INTERNAL | (chan->address) |
drivers/iio/adc/lpc32xx_adc.c
81
__raw_writel(LPC32XXAD_PDN_CTRL | LPC32XXAD_STROBE,
drivers/iio/adc/spear_adc.c
102
__raw_writel(val, &st->adc_base_spear6xx->status);
drivers/iio/adc/spear_adc.c
115
__raw_writel(SPEAR_ADC_CLK_LOW(clk_low) | SPEAR_ADC_CLK_HIGH(clk_high),
drivers/iio/adc/spear_adc.c
122
__raw_writel(val, &st->adc_base_spear6xx->ch_ctrl[n]);
drivers/iio/adc/spear_adc.c
139
__raw_writel(SPEAR600_ADC_SCAN_RATE_LO(rate),
drivers/iio/adc/spear_adc.c
141
__raw_writel(SPEAR600_ADC_SCAN_RATE_HI(rate),
drivers/iio/adc/spear_adc.c
144
__raw_writel(rate, &st->adc_base_spear3xx->scan_rate);
drivers/iio/adc/spear_adc.c
253
__raw_writel(0, &st->adc_base_spear6xx->clk);
drivers/infiniband/hw/hns/hns_roce_common.h
40
__raw_writel((__force u32)cpu_to_le32(value), (addr))
drivers/infiniband/hw/mthca/mthca_cmd.c
209
__raw_writel((__force u32) cpu_to_be32(in_param >> 32), ptr + offs[0]);
drivers/infiniband/hw/mthca/mthca_cmd.c
211
__raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), ptr + offs[1]);
drivers/infiniband/hw/mthca/mthca_cmd.c
213
__raw_writel((__force u32) cpu_to_be32(in_modifier), ptr + offs[2]);
drivers/infiniband/hw/mthca/mthca_cmd.c
215
__raw_writel((__force u32) cpu_to_be32(out_param >> 32), ptr + offs[3]);
drivers/infiniband/hw/mthca/mthca_cmd.c
217
__raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), ptr + offs[4]);
drivers/infiniband/hw/mthca/mthca_cmd.c
219
__raw_writel((__force u32) cpu_to_be32(token << 16), ptr + offs[5]);
drivers/infiniband/hw/mthca/mthca_cmd.c
221
__raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
drivers/infiniband/hw/mthca/mthca_cmd.c
226
__raw_writel((__force u32) 0, ptr + offs[7]);
drivers/infiniband/hw/mthca/mthca_cmd.c
257
__raw_writel((__force u32) cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4);
drivers/infiniband/hw/mthca/mthca_cmd.c
258
__raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4);
drivers/infiniband/hw/mthca/mthca_cmd.c
259
__raw_writel((__force u32) cpu_to_be32(in_modifier), dev->hcr + 2 * 4);
drivers/infiniband/hw/mthca/mthca_cmd.c
260
__raw_writel((__force u32) cpu_to_be32(out_param >> 32), dev->hcr + 3 * 4);
drivers/infiniband/hw/mthca/mthca_cmd.c
261
__raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4);
drivers/infiniband/hw/mthca/mthca_cmd.c
262
__raw_writel((__force u32) cpu_to_be32(token << 16), dev->hcr + 5 * 4);
drivers/infiniband/hw/mthca/mthca_cmd.c
267
__raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
drivers/infiniband/hw/mthca/mthca_doorbell.h
84
__raw_writel(((__force u32 *) &val)[0], dest);
drivers/infiniband/hw/mthca/mthca_doorbell.h
85
__raw_writel(((__force u32 *) &val)[1], dest + 4);
drivers/infiniband/hw/mthca/mthca_doorbell.h
97
__raw_writel(hi, dest);
drivers/infiniband/hw/mthca/mthca_doorbell.h
98
__raw_writel(lo, dest + 4);
drivers/infiniband/hw/mthca/mthca_eq.c
193
__raw_writel((__force u32) cpu_to_be32(ci),
drivers/input/keyboard/ep93xx_keypad.c
138
__raw_writel(val, keypad->mmio_base + KEY_INIT);
drivers/input/keyboard/goldfish_events.c
125
__raw_writel(PAGE_NAME, addr + REG_SET_PAGE);
drivers/input/keyboard/goldfish_events.c
58
__raw_writel(PAGE_EVBITS | type, addr + REG_SET_PAGE);
drivers/input/keyboard/goldfish_events.c
81
__raw_writel(PAGE_ABSDATA, addr + REG_SET_PAGE);
drivers/input/keyboard/omap4-keypad.c
111
__raw_writel(value,
drivers/input/keyboard/omap4-keypad.c
98
__raw_writel(value,
drivers/input/keyboard/pxa27x_keypad.c
101
#define keypad_writel(off, v) __raw_writel((v), keypad->mmio_base + (off))
drivers/input/touchscreen/lpc32xx_ts.c
62
__raw_writel((val), (dev)->tsc_base + (reg))
drivers/iommu/omap-iommu.h
261
__raw_writel(val, obj->regbase + offs);
drivers/irqchip/irq-ath79-misc.c
127
__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
drivers/irqchip/irq-ath79-misc.c
128
__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
drivers/irqchip/irq-ath79-misc.c
69
__raw_writel(t | BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
drivers/irqchip/irq-ath79-misc.c
82
__raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
drivers/irqchip/irq-ath79-misc.c
95
__raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
drivers/irqchip/irq-bcm6345-l1.c
150
__raw_writel(intc->cpus[cpu_idx]->enable_cache[word],
drivers/irqchip/irq-bcm6345-l1.c
162
__raw_writel(intc->cpus[cpu_idx]->enable_cache[word],
drivers/irqchip/irq-bcm6345-l1.c
255
__raw_writel(0, cpu->map_base + reg_enable(intc, i));
drivers/irqchip/irq-ixp4xx.c
100
__raw_writel(val, ixi->irqbase + IXP4XX_ICMR2);
drivers/irqchip/irq-ixp4xx.c
104
__raw_writel(val, ixi->irqbase + IXP4XX_ICMR);
drivers/irqchip/irq-ixp4xx.c
215
__raw_writel(0x0, ixi->irqbase + IXP4XX_ICLR);
drivers/irqchip/irq-ixp4xx.c
218
__raw_writel(0x0, ixi->irqbase + IXP4XX_ICMR);
drivers/irqchip/irq-ixp4xx.c
222
__raw_writel(0x0, ixi->irqbase + IXP4XX_ICLR2);
drivers/irqchip/irq-ixp4xx.c
225
__raw_writel(0x0, ixi->irqbase + IXP4XX_ICMR2);
drivers/irqchip/irq-ixp4xx.c
80
__raw_writel(val, ixi->irqbase + IXP4XX_ICMR2);
drivers/irqchip/irq-ixp4xx.c
84
__raw_writel(val, ixi->irqbase + IXP4XX_ICMR);
drivers/irqchip/irq-jcore-aic.c
86
__raw_writel(0xffffffff, base + JCORE_AIC1_INTPRI_REG);
drivers/irqchip/irq-mxs.c
103
__raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE),
drivers/irqchip/irq-mxs.c
109
__raw_writel(ASM9260_BM_CLEAR_BIT(d->hwirq),
drivers/irqchip/irq-mxs.c
113
__raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE),
drivers/irqchip/irq-mxs.c
138
__raw_writel(irqnr, icoll_priv.vector);
drivers/irqchip/irq-mxs.c
85
__raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0,
drivers/irqchip/irq-mxs.c
91
__raw_writel(BM_ICOLL_INTR_ENABLE,
drivers/irqchip/irq-mxs.c
97
__raw_writel(BM_ICOLL_INTR_ENABLE,
drivers/mailbox/omap-mailbox.c
104
__raw_writel(val, mdev->mbox_base + ofs);
drivers/media/pci/cx18/cx18-io.h
32
__raw_writel(val, addr);
drivers/media/pci/ivtv/ivtv-firmware.c
63
__raw_writel(*src, dst);
drivers/media/platform/intel/pxa_camera.c
1112
__raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
drivers/media/platform/intel/pxa_camera.c
1120
__raw_writel(0x3ff, pcdev->base + CICR0);
drivers/media/platform/intel/pxa_camera.c
1133
__raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
drivers/media/platform/intel/pxa_camera.c
1162
__raw_writel(cifr, pcdev->base + CIFR);
drivers/media/platform/intel/pxa_camera.c
1184
__raw_writel(status, pcdev->base + CISR);
drivers/media/platform/intel/pxa_camera.c
1188
__raw_writel(cicr0, pcdev->base + CICR0);
drivers/media/platform/intel/pxa_camera.c
1241
__raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
drivers/media/platform/intel/pxa_camera.c
1277
__raw_writel(cicr1, pcdev->base + CICR1);
drivers/media/platform/intel/pxa_camera.c
1278
__raw_writel(cicr2, pcdev->base + CICR2);
drivers/media/platform/intel/pxa_camera.c
1279
__raw_writel(cicr3, pcdev->base + CICR3);
drivers/media/platform/intel/pxa_camera.c
1280
__raw_writel(cicr4, pcdev->base + CICR4);
drivers/media/platform/intel/pxa_camera.c
1286
__raw_writel(cicr0, pcdev->base + CICR0);
drivers/media/platform/intel/pxa_camera.c
1749
__raw_writel(reg->val, pcdev->base + reg->reg);
drivers/media/platform/intel/pxa_camera.c
2135
__raw_writel(0x3ff, pcdev->base + CICR0);
drivers/media/platform/intel/pxa_camera.c
2178
__raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
drivers/media/platform/intel/pxa_camera.c
2179
__raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
drivers/media/platform/intel/pxa_camera.c
2180
__raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
drivers/media/platform/intel/pxa_camera.c
2181
__raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
drivers/media/platform/intel/pxa_camera.c
2182
__raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
drivers/media/platform/intel/pxa_camera.c
921
__raw_writel(__raw_readl(pcdev->base + CISR), pcdev->base + CISR);
drivers/media/platform/intel/pxa_camera.c
925
__raw_writel(cicr0, pcdev->base + CICR0);
drivers/media/platform/intel/pxa_camera.c
935
__raw_writel(cicr0, pcdev->base + CICR0);
drivers/media/platform/renesas/sh_vou.c
102
__raw_writel(value, vou_dev->base + reg);
drivers/media/platform/renesas/sh_vou.c
103
__raw_writel(value, vou_dev->base + reg + 0x1000);
drivers/media/platform/renesas/sh_vou.c
109
__raw_writel(value, vou_dev->base + reg + 0x2000);
drivers/media/platform/renesas/sh_vou.c
123
__raw_writel(value, vou_dev->base + reg);
drivers/media/platform/renesas/sh_vou.c
96
__raw_writel(value, vou_dev->base + reg);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
39
__raw_writel(v, r); \
drivers/media/platform/ti/omap3isp/isp.h
301
__raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset);
drivers/media/rc/mtk-cir.c
177
__raw_writel(tmp, ir->base + reg);
drivers/media/rc/mtk-cir.c
182
__raw_writel(val, ir->base + reg);
drivers/memstick/host/jmb38x_ms.c
248
__raw_writel(*(unsigned int *)(buf + off),
drivers/memstick/host/r592.c
81
__raw_writel(cpu_to_be32(value), dev->mmio + address);
drivers/memstick/host/tifm_ms.c
155
__raw_writel(*(unsigned int *)(buf + off),
drivers/misc/genwqe/card_utils.c
108
__raw_writel((__force u32)cpu_to_be32(val), cd->mmio + byte_offs);
drivers/mmc/host/atmel-mci.c
172
__raw_writel((value), (port)->regs + reg)
drivers/mmc/host/au1xmmc.c
1086
__raw_writel(0, HOST_ENABLE(host));
drivers/mmc/host/au1xmmc.c
1087
__raw_writel(0, HOST_CONFIG(host));
drivers/mmc/host/au1xmmc.c
1088
__raw_writel(0, HOST_CONFIG2(host));
drivers/mmc/host/au1xmmc.c
1130
__raw_writel(0, HOST_ENABLE(host));
drivers/mmc/host/au1xmmc.c
1131
__raw_writel(0, HOST_CONFIG(host));
drivers/mmc/host/au1xmmc.c
1132
__raw_writel(0, HOST_CONFIG2(host));
drivers/mmc/host/au1xmmc.c
1157
__raw_writel(0, HOST_CONFIG2(host));
drivers/mmc/host/au1xmmc.c
1158
__raw_writel(0, HOST_CONFIG(host));
drivers/mmc/host/au1xmmc.c
1159
__raw_writel(0xffffffff, HOST_STATUS(host));
drivers/mmc/host/au1xmmc.c
1160
__raw_writel(0, HOST_ENABLE(host));
drivers/mmc/host/au1xmmc.c
169
__raw_writel(val, HOST_CONFIG(host));
drivers/mmc/host/au1xmmc.c
177
__raw_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
drivers/mmc/host/au1xmmc.c
184
__raw_writel(val, HOST_CONFIG2(host));
drivers/mmc/host/au1xmmc.c
192
__raw_writel(val, HOST_CONFIG(host));
drivers/mmc/host/au1xmmc.c
204
__raw_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host));
drivers/mmc/host/au1xmmc.c
208
__raw_writel(STOP_CMD, HOST_CMD(host));
drivers/mmc/host/au1xmmc.c
303
__raw_writel(cmd->arg, HOST_CMDARG(host));
drivers/mmc/host/au1xmmc.c
306
__raw_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
drivers/mmc/host/au1xmmc.c
348
__raw_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
drivers/mmc/host/au1xmmc.c
410
__raw_writel((unsigned long)val, HOST_TXPORT(host));
drivers/mmc/host/au1xmmc.c
598
__raw_writel(config, HOST_CONFIG(host));
drivers/mmc/host/au1xmmc.c
623
__raw_writel(data->blksz - 1, HOST_BLKSIZE(host));
drivers/mmc/host/au1xmmc.c
710
__raw_writel(SD_ENABLE_CE, HOST_ENABLE(host));
drivers/mmc/host/au1xmmc.c
714
__raw_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
drivers/mmc/host/au1xmmc.c
718
__raw_writel(~0, HOST_STATUS(host));
drivers/mmc/host/au1xmmc.c
721
__raw_writel(0, HOST_BLKSIZE(host));
drivers/mmc/host/au1xmmc.c
722
__raw_writel(0x001fffff, HOST_TIMEOUT(host));
drivers/mmc/host/au1xmmc.c
725
__raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
drivers/mmc/host/au1xmmc.c
728
__raw_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
drivers/mmc/host/au1xmmc.c
732
__raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
drivers/mmc/host/au1xmmc.c
736
__raw_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
drivers/mmc/host/au1xmmc.c
770
__raw_writel(config2, HOST_CONFIG2(host));
drivers/mmc/host/au1xmmc.c
829
__raw_writel(status, HOST_STATUS(host));
drivers/mmc/host/dw_mmc.h
474
#define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value)
drivers/mmc/host/omap_hsmmc.c
162
__raw_writel((val), (base) + OMAP_HSMMC_##reg)
drivers/mtd/nand/raw/brcmnand/brcmnand.c
871
__raw_writel(val, ctrl->nand_fc + word * 4);
drivers/mtd/nand/raw/brcmnand/brcmnand.h
71
__raw_writel(val, addr);
drivers/mtd/nand/raw/davinci_nand.c
148
__raw_writel(value, info->base + offset);
drivers/mtd/nand/raw/txx9ndfmc.c
117
__raw_writel(*buf++, ndfdtr);
drivers/mtd/nand/raw/txx9ndfmc.c
98
__raw_writel(val, ndregaddr(dev, reg));
drivers/mtd/nand/raw/vf610_nfc.c
274
__raw_writel(swab32(val), dst + i);
drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c
799
__raw_writel(data_last, can->reg_base +
drivers/net/can/kvaser_pciefd/kvaser_pciefd_core.c
803
__raw_writel(0, can->reg_base +
drivers/net/can/ti_hecc.c
209
__raw_writel(val, priv->hecc_ram + mbxno * 4);
drivers/net/can/ti_hecc.c
220
__raw_writel(val, priv->mbx + mbxno * 0x10 + reg);
drivers/net/can/ti_hecc.c
230
__raw_writel(val, priv->base + reg);
drivers/net/ethernet/aeroflex/greth.c
157
__raw_writel(cpu_to_be32(val), bd);
drivers/net/ethernet/aeroflex/greth.c
82
#define GRETH_REGSAVE(a, v) (__raw_writel(cpu_to_be32(v), &(a)))
drivers/net/ethernet/broadcom/genet/bcmgenet.c
74
__raw_writel(value, offset);
drivers/net/ethernet/broadcom/genet/bcmgenet.h
711
__raw_writel(val, priv->base + offset + off); \
drivers/net/ethernet/cadence/macb_main.c
202
__raw_writel(value, bp->regs + offset);
drivers/net/ethernet/cadence/macb_main.c
223
__raw_writel(value, addr + MACB_NCR);
drivers/net/ethernet/cadence/macb_main.c
227
__raw_writel(0, addr + MACB_NCR);
drivers/net/ethernet/calxeda/xgmac.c
1239
__raw_writel(DMA_INTR_DEFAULT_MASK, priv->base + XGMAC_DMA_INTR_ENA);
drivers/net/ethernet/calxeda/xgmac.c
1389
__raw_writel(intr_status, priv->base + XGMAC_DMA_STATUS);
drivers/net/ethernet/calxeda/xgmac.c
1421
__raw_writel(DMA_INTR_ABNORMAL, priv->base + XGMAC_DMA_INTR_ENA);
drivers/net/ethernet/cirrus/ep93xx_eth.c
181
#define wrl(ep, off, val) __raw_writel((val), (ep)->base_addr + (off))
drivers/net/ethernet/freescale/enetc/enetc4_pf.c
61
__raw_writel(upper, hw->port + ENETC4_PSIPMAR0(si));
drivers/net/ethernet/freescale/enetc/enetc4_pf.c
62
__raw_writel(lower, hw->port + ENETC4_PSIPMAR1(si));
drivers/net/ethernet/freescale/enetc/enetc4_pf.c
64
__raw_writel(upper, hw->port + ENETC4_PMAR0);
drivers/net/ethernet/freescale/enetc/enetc4_pf.c
65
__raw_writel(lower, hw->port + ENETC4_PMAR1);
drivers/net/ethernet/freescale/enetc/enetc_pf.c
30
__raw_writel(upper, hw->port + ENETC_PSIPMAR0(si));
drivers/net/ethernet/freescale/fs_enet/fs_enet.h
198
#define __cbd_out32(addr, x) __raw_writel(x, addr)
drivers/net/ethernet/freescale/fs_enet/mac-fec.c
44
#define __fs_out32(addr, x) __raw_writel(x, addr)
drivers/net/ethernet/freescale/fs_enet/mac-scc.c
40
#define __fs_out32(addr, x) __raw_writel(x, addr)
drivers/net/ethernet/huawei/hinic/hinic_hw_mbox.c
673
__raw_writel(*(data + i), mbox->data + i * sizeof(u32));
drivers/net/ethernet/huawei/hinic/hinic_hw_mbox.c
695
__raw_writel(*(data + i),
drivers/net/ethernet/huawei/hinic3/hinic3_mbox.c
561
__raw_writel(swab32((__force __u32)src32[i]), dst32 + i);
drivers/net/ethernet/lantiq_xrx200.c
100
__raw_writel(val, priv->pmac_reg + offset);
drivers/net/ethernet/mediatek/mtk_eth_soc.c
291
__raw_writel(val, eth->base + reg);
drivers/net/ethernet/mellanox/mlx4/catas.c
130
__raw_writel((__force u32)cpu_to_be32(comm_flags),
drivers/net/ethernet/mellanox/mlx4/cmd.c
2189
__raw_writel((__force u32) cpu_to_be32(reply),
drivers/net/ethernet/mellanox/mlx4/cmd.c
2217
__raw_writel((__force u32) cpu_to_be32(reply),
drivers/net/ethernet/mellanox/mlx4/cmd.c
2339
__raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
drivers/net/ethernet/mellanox/mlx4/cmd.c
2340
__raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
drivers/net/ethernet/mellanox/mlx4/cmd.c
2397
__raw_writel((__force u32) 0,
drivers/net/ethernet/mellanox/mlx4/cmd.c
2399
__raw_writel((__force u32) 0,
drivers/net/ethernet/mellanox/mlx4/cmd.c
2562
__raw_writel((__force u32)cpu_to_be32(slave_read),
drivers/net/ethernet/mellanox/mlx4/cmd.c
282
__raw_writel((__force u32) cpu_to_be32(val),
drivers/net/ethernet/mellanox/mlx4/cmd.c
482
__raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0);
drivers/net/ethernet/mellanox/mlx4/cmd.c
483
__raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1);
drivers/net/ethernet/mellanox/mlx4/cmd.c
484
__raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2);
drivers/net/ethernet/mellanox/mlx4/cmd.c
485
__raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3);
drivers/net/ethernet/mellanox/mlx4/cmd.c
486
__raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
drivers/net/ethernet/mellanox/mlx4/cmd.c
487
__raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5);
drivers/net/ethernet/mellanox/mlx4/cmd.c
492
__raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
drivers/net/ethernet/mellanox/mlx4/eq.c
99
__raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) |
drivers/net/ethernet/mellanox/mlx5/core/lib/eq.h
73
__raw_writel((__force u32)cpu_to_be32(val), addr);
drivers/net/ethernet/myricom/myri10ge/myri10ge.c
363
__raw_writel((__force __u32) val, (__force void __iomem *)p);
drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c
1029
__raw_writel(*rdptr32++, wrptr32++);
drivers/net/ethernet/sfc/falcon/io.h
126
__raw_writel((__force u32)value->u32[0], membase + addr);
drivers/net/ethernet/sfc/falcon/io.h
127
__raw_writel((__force u32)value->u32[1], membase + addr + 4);
drivers/net/ethernet/sfc/falcon/io.h
81
__raw_writel((__force u32)value, efx->membase + reg);
drivers/net/ethernet/sfc/io.h
74
__raw_writel((__force u32)value, efx->membase + reg);
drivers/net/ethernet/sfc/siena/io.h
143
__raw_writel((__force u32)value->u32[0], membase + addr);
drivers/net/ethernet/sfc/siena/io.h
144
__raw_writel((__force u32)value->u32[1], membase + addr + 4);
drivers/net/ethernet/sfc/siena/io.h
98
__raw_writel((__force u32)value, efx->membase + reg);
drivers/net/ethernet/xscale/ixp4xx_eth.c
1296
__raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);
drivers/net/ethernet/xscale/ixp4xx_eth.c
1297
__raw_writel(0x08, &port->regs->random_seed);
drivers/net/ethernet/xscale/ixp4xx_eth.c
1298
__raw_writel(0x12, &port->regs->partial_empty_threshold);
drivers/net/ethernet/xscale/ixp4xx_eth.c
1299
__raw_writel(0x30, &port->regs->partial_full_threshold);
drivers/net/ethernet/xscale/ixp4xx_eth.c
1300
__raw_writel(0x08, &port->regs->tx_start_bytes);
drivers/net/ethernet/xscale/ixp4xx_eth.c
1301
__raw_writel(0x15, &port->regs->tx_deferral);
drivers/net/ethernet/xscale/ixp4xx_eth.c
1302
__raw_writel(0x08, &port->regs->tx_2part_deferral[0]);
drivers/net/ethernet/xscale/ixp4xx_eth.c
1303
__raw_writel(0x07, &port->regs->tx_2part_deferral[1]);
drivers/net/ethernet/xscale/ixp4xx_eth.c
1304
__raw_writel(0x80, &port->regs->slot_time);
drivers/net/ethernet/xscale/ixp4xx_eth.c
1305
__raw_writel(0x01, &port->regs->int_clock_threshold);
drivers/net/ethernet/xscale/ixp4xx_eth.c
1316
__raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
drivers/net/ethernet/xscale/ixp4xx_eth.c
1317
__raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
drivers/net/ethernet/xscale/ixp4xx_eth.c
1318
__raw_writel(0, &port->regs->rx_control[1]);
drivers/net/ethernet/xscale/ixp4xx_eth.c
1319
__raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
drivers/net/ethernet/xscale/ixp4xx_eth.c
1559
__raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,
drivers/net/ethernet/xscale/ixp4xx_eth.c
1562
__raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
drivers/net/ethernet/xscale/ixp4xx_eth.c
348
__raw_writel(RX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event);
drivers/net/ethernet/xscale/ixp4xx_eth.c
394
__raw_writel(TX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event);
drivers/net/ethernet/xscale/ixp4xx_eth.c
425
__raw_writel(0, ®s->channel[ch].ch_control);
drivers/net/ethernet/xscale/ixp4xx_eth.c
429
__raw_writel(MASTER_MODE, ®s->channel[ch].ch_control);
drivers/net/ethernet/xscale/ixp4xx_eth.c
438
__raw_writel(TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED,
drivers/net/ethernet/xscale/ixp4xx_eth.c
487
__raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);
drivers/net/ethernet/xscale/ixp4xx_eth.c
488
__raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);
drivers/net/ethernet/xscale/ixp4xx_eth.c
490
__raw_writel(((phy_id << 5) | location) & 0xFF,
drivers/net/ethernet/xscale/ixp4xx_eth.c
492
__raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,
drivers/net/ethernet/xscale/ixp4xx_eth.c
566
__raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
drivers/net/ethernet/xscale/ixp4xx_eth.c
605
__raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
drivers/net/ethernet/xscale/ixp4xx_eth.c
608
__raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
drivers/net/ethernet/xscale/ixp4xx_eth.c
961
__raw_writel(allmulti[i], &port->regs->mcast_addr[i]);
drivers/net/ethernet/xscale/ixp4xx_eth.c
962
__raw_writel(allmulti[i], &port->regs->mcast_mask[i]);
drivers/net/ethernet/xscale/ixp4xx_eth.c
964
__raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
drivers/net/ethernet/xscale/ixp4xx_eth.c
970
__raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,
drivers/net/ethernet/xscale/ixp4xx_eth.c
986
__raw_writel(addr[i], &port->regs->mcast_addr[i]);
drivers/net/ethernet/xscale/ixp4xx_eth.c
987
__raw_writel(~diffs[i], &port->regs->mcast_mask[i]);
drivers/net/ethernet/xscale/ixp4xx_eth.c
990
__raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
drivers/net/ethernet/xscale/ptp_ixp46x.c
113
__raw_writel(ack, ®s->event);
drivers/net/ethernet/xscale/ptp_ixp46x.c
131
__raw_writel(addend, ®s->addend);
drivers/net/ethernet/xscale/ptp_ixp46x.c
283
__raw_writel(DEFAULT_ADDEND, &ixp_clock.regs->addend);
drivers/net/ethernet/xscale/ptp_ixp46x.c
284
__raw_writel(1, &ixp_clock.regs->trgt_lo);
drivers/net/ethernet/xscale/ptp_ixp46x.c
285
__raw_writel(0, &ixp_clock.regs->trgt_hi);
drivers/net/ethernet/xscale/ptp_ixp46x.c
286
__raw_writel(TTIPEND, &ixp_clock.regs->event);
drivers/net/ethernet/xscale/ptp_ixp46x.c
64
__raw_writel(lo, ®s->systime_lo);
drivers/net/ethernet/xscale/ptp_ixp46x.c
65
__raw_writel(hi, ®s->systime_hi);
drivers/net/mdio/mdio-bcm-unimac.c
62
__raw_writel(val, priv->base + offset);
drivers/net/mdio/mdio-mux-bcm6368.c
43
__raw_writel(0, md->base + MDIOC_REG);
drivers/net/mdio/mdio-mux-bcm6368.c
51
__raw_writel(reg, md->base + MDIOC_REG);
drivers/net/mdio/mdio-mux-bcm6368.c
64
__raw_writel(0, md->base + MDIOC_REG);
drivers/net/mdio/mdio-mux-bcm6368.c
73
__raw_writel(reg, md->base + MDIOC_REG);
drivers/net/wireless/ath/wil6210/fw.c
25
__raw_writel(val, d++);
drivers/net/wireless/ath/wil6210/main.c
165
__raw_writel(*s++, d++);
drivers/net/wireless/ath/wil6210/main.c
172
__raw_writel(tmp, d);
drivers/net/wireless/intersil/p54/p54pci.h
87
#define P54P_WRITE(r, val) __raw_writel((__force u32)(__le32)(val), &priv->map->r)
drivers/parisc/ccio-dma.c
1465
__raw_writel(((parent->start)>>16) | 0xffff0000,
drivers/parisc/ccio-dma.c
1467
__raw_writel(((parent->end)>>16) | 0xffff0000,
drivers/parisc/ccio-dma.c
1471
__raw_writel(((parent->start)>>16) | 0xffff0000,
drivers/parisc/ccio-dma.c
1473
__raw_writel(((parent->end)>>16) | 0xffff0000,
drivers/parisc/ccio-dma.c
90
#define WRITE_U32(value, addr) __raw_writel(value, addr)
drivers/parisc/dino.c
185
__raw_writel(v, base_addr + DINO_PCI_ADDR);
drivers/parisc/dino.c
220
__raw_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR);
drivers/parisc/dino.c
224
__raw_writel(v, base_addr + DINO_PCI_ADDR);
drivers/parisc/dino.c
260
__raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
drivers/parisc/dino.c
277
__raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
drivers/parisc/dino.c
305
__raw_writel(dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
drivers/parisc/dino.c
326
__raw_writel( dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
drivers/parisc/dino.c
363
__raw_writel(eim, dino_dev->hba.base_addr+DINO_IAR0);
drivers/parisc/dino.c
551
__raw_writel(1 << i, base_addr + DINO_IO_ADDR_EN);
drivers/parisc/dino.c
712
__raw_writel(0x00000005,
drivers/parisc/dino.c
717
__raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_GMASK);
drivers/parisc/dino.c
718
__raw_writel(0x00000001, dino_dev->hba.base_addr+DINO_IO_FBB_EN);
drivers/parisc/dino.c
719
__raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_ICR);
drivers/parisc/dino.c
729
__raw_writel( brdg_feat, dino_dev->hba.base_addr+DINO_BRDG_FEAT);
drivers/parisc/dino.c
736
__raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_IO_ADDR_EN);
drivers/parisc/dino.c
738
__raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_DAMODE);
drivers/parisc/dino.c
739
__raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIROR);
drivers/parisc/dino.c
740
__raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIWOR);
drivers/parisc/dino.c
742
__raw_writel(0x00000040, dino_dev->hba.base_addr+DINO_MLTIM);
drivers/parisc/dino.c
743
__raw_writel(0x00000080, dino_dev->hba.base_addr+DINO_IO_CONTROL);
drivers/parisc/dino.c
744
__raw_writel(0x0000008c, dino_dev->hba.base_addr+DINO_TLTIM);
drivers/parisc/dino.c
747
__raw_writel(0x0000007e, dino_dev->hba.base_addr+DINO_PAMR);
drivers/parisc/dino.c
748
__raw_writel(0x0000007f, dino_dev->hba.base_addr+DINO_PAPR);
drivers/parisc/dino.c
749
__raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_PAMR);
drivers/parisc/dino.c
756
__raw_writel(0x0000004f, dino_dev->hba.base_addr+DINO_PCICMD);
drivers/parisc/dino.c
881
__raw_writel(eim, dino_dev->hba.base_addr+DINO_IAR0);
drivers/parisc/iosapic.c
207
__raw_writel((__force u32)data, addr);
drivers/parisc/lba_pci.c
133
#define WRITE_U32(value, addr) __raw_writel(value, addr)
drivers/pci/controller/pci-ixp4xx.c
131
__raw_writel(val, p->base + reg);
drivers/phy/broadcom/phy-bcm63xx-usbh.c
238
__raw_writel(value, usbh->base + usbh->variant->regs[reg]);
drivers/phy/broadcom/phy-brcm-usb-init.h
101
__raw_writel(val, addr);
drivers/phy/ti/phy-omap-usb2.c
89
__raw_writel(data, addr + offset);
drivers/phy/ti/phy-ti-pipe3.c
297
__raw_writel(data, addr + offset);
drivers/pinctrl/samsung/pinctrl-exynos-arm.c
64
__raw_writel(tmp, clk_base + S5P_OTHERS);
drivers/pinctrl/samsung/pinctrl-exynos.c
576
__raw_writel(eint_wake_mask_values[0],
drivers/pmdomain/bcm/bcm63xx-power.c
67
__raw_writel(val, power->base);
drivers/ptp/ptp_ines.c
104
#define ines_write32(s, v, r) __raw_writel(v, (void __iomem *)&s->regs->r)
drivers/pwm/pwm-brcmstb.c
72
__raw_writel(value, p->base + offset);
drivers/reset/reset-bcm6345.c
44
__raw_writel(val, bcm6345_reset->base);
drivers/rtc/rtc-ds1286.c
32
__raw_writel(data, &priv->rtcregs[reg]);
drivers/rtc/rtc-lpc32xx.c
45
__raw_writel((val), (dev)->rtc_base + (reg))
drivers/rtc/rtc-ma35d1.c
67
__raw_writel(value, p->rtc_reg + offset);
drivers/rtc/rtc-msm6242.c
88
__raw_writel(val, &priv->regs[reg]);
drivers/rtc/rtc-pl030.c
114
__raw_writel(0, rtc->base + RTC_CR);
drivers/rtc/rtc-pl030.c
115
__raw_writel(0, rtc->base + RTC_EOI);
drivers/rtc/rtc-pxa.c
71
__raw_writel((value), (pxa_rtc)->base + (reg))
drivers/rtc/rtc-rp5c01.c
79
__raw_writel(val, &priv->regs[reg]);
drivers/scsi/lpfc/lpfc_sli.c
306
__raw_writel(*((uint32_t *)(tmp + i)),
drivers/scsi/mpt3sas/mpt3sas_base.c
4111
__raw_writel((u32)(b), addr);
drivers/scsi/mpt3sas/mpt3sas_base.c
4112
__raw_writel((u32)(b >> 32), (addr + 4));
drivers/scsi/ncr53c8xx.h
276
#define writel_b2l __raw_writel
drivers/scsi/ncr53c8xx.h
280
#define writel_raw __raw_writel
drivers/scsi/zalon.c
102
__raw_writel(IOIIDATA_MINT5EN | IOIIDATA_PACKEN | IOIIDATA_PREFETCHEN,
drivers/scsi/zalon.c
116
__raw_writel(gsc_irq.txn_addr | gsc_irq.txn_data, zalon + IO_MODULE_EIM);
drivers/scsi/zalon.c
99
__raw_writel(CMD_RESET, zalon + IO_MODULE_IO_COMMAND);
drivers/sh/clk/cpg.c
418
__raw_writel(0, clk->mapping->base);
drivers/sh/clk/cpg.c
429
__raw_writel((value << 16) | 0x3, clk->mapping->base);
drivers/sh/clk/cpg.c
440
__raw_writel(0, clk->mapping->base);
drivers/sh/clk/cpg.c
442
__raw_writel(idx << 16, clk->mapping->base);
drivers/sh/intc/access.c
118
__raw_writel(intc_set_field_from_handle(0, data, h), ptr);
drivers/sh/intc/access.c
159
__raw_writel(value, ptr);
drivers/sh/intc/chip.c
108
__raw_writel(0xffffffff ^ value, addr);
drivers/sh/intc/userimask.c
56
__raw_writel(0xa5 << 24 | level << 4, uimask);
drivers/sh/maple/maple.c
100
__raw_writel(1, MAPLE_TRIGTYPE);
drivers/sh/maple/maple.c
109
__raw_writel(MAPLE_2MBPS | MAPLE_TIMEOUT(0xFFFF), MAPLE_SPEED);
drivers/sh/maple/maple.c
110
__raw_writel(virt_to_phys(maple_sendbuf), MAPLE_DMAADDR);
drivers/sh/maple/maple.c
111
__raw_writel(1, MAPLE_ENABLE);
drivers/sh/maple/maple.c
279
__raw_writel(0, MAPLE_ENABLE);
drivers/sh/maple/maple.c
454
__raw_writel(0, MAPLE_ENABLE);
drivers/sh/maple/maple.c
640
__raw_writel(0, MAPLE_ENABLE);
drivers/sh/maple/maple.c
792
__raw_writel(0, MAPLE_ENABLE);
drivers/sh/maple/maple.c
98
__raw_writel(MAPLE_MAGIC, MAPLE_RESET);
drivers/soc/bcm/brcmstb/pm/pm-mips.c
140
__raw_writel(tmp, base + AON_CTRL_HOST_MISC_CMDS);
drivers/soc/bcm/brcmstb/pm/pm-mips.c
143
__raw_writel(0, base + AON_CTRL_PM_INITIATE);
drivers/soc/bcm/brcmstb/pm/pm-mips.c
145
__raw_writel(BSP_CLOCK_STOP | PM_INITIATE,
drivers/soc/bcm/brcmstb/pm/pm-mips.c
164
__raw_writel(0x10, base + AON_CTRL_PM_CPU_WAIT_COUNT);
drivers/soc/bcm/brcmstb/pm/pm-mips.c
168
__raw_writel(PM_COLD_CONFIG, base + AON_CTRL_PM_CTRL);
drivers/soc/bcm/brcmstb/pm/pm-mips.c
171
__raw_writel((PM_COLD_CONFIG | PM_PWR_DOWN), base +
drivers/soc/bcm/brcmstb/pm/pm-mips.c
196
__raw_writel(tmp, ctrl.aon_ctrl_base + AON_CTRL_RESET_CTRL);
drivers/soc/bcm/brcmstb/pm/pm-mips.c
206
__raw_writel(tmp, ctrl.memcs[i].ddr_phy_base +
drivers/soc/bcm/brcmstb/pm/pm-mips.c
209
__raw_writel(tmp, ctrl.memcs[i].ddr_phy_base +
drivers/soc/bcm/brcmstb/pm/pm-mips.c
237
__raw_writel(s3_context.memc0_rts[i], memc_arb_base);
drivers/soc/bcm/brcmstb/pm/pm-mips.c
81
__raw_writel(val, base + (idx << 2))
drivers/soc/ixp4xx/ixp4xx-npe.c
172
__raw_writel(data, &npe->regs->exec_data);
drivers/soc/ixp4xx/ixp4xx-npe.c
173
__raw_writel(addr, &npe->regs->exec_addr);
drivers/soc/ixp4xx/ixp4xx-npe.c
174
__raw_writel(cmd, &npe->regs->exec_status_cmd);
drivers/soc/ixp4xx/ixp4xx-npe.c
179
__raw_writel(addr, &npe->regs->exec_addr);
drivers/soc/ixp4xx/ixp4xx-npe.c
180
__raw_writel(cmd, &npe->regs->exec_status_cmd);
drivers/soc/ixp4xx/ixp4xx-npe.c
202
__raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
drivers/soc/ixp4xx/ixp4xx-npe.c
203
__raw_writel(CMD_NPE_START, &npe->regs->exec_status_cmd);
drivers/soc/ixp4xx/ixp4xx-npe.c
208
__raw_writel(CMD_NPE_STOP, &npe->regs->exec_status_cmd);
drivers/soc/ixp4xx/ixp4xx-npe.c
209
__raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); /*FIXME?*/
drivers/soc/ixp4xx/ixp4xx-npe.c
232
__raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
drivers/soc/ixp4xx/ixp4xx-npe.c
242
__raw_writel(CMD_NPE_STEP, &npe->regs->exec_status_cmd);
drivers/soc/ixp4xx/ixp4xx-npe.c
296
__raw_writel(ctl & 0x3F00FFFF, &npe->regs->messaging_control);
drivers/soc/ixp4xx/ixp4xx-npe.c
301
__raw_writel(0, &npe->regs->exec_count);
drivers/soc/ixp4xx/ixp4xx-npe.c
323
__raw_writel(RESET_MBOX_STAT, &npe->regs->mailbox_status);
drivers/soc/ixp4xx/ixp4xx-npe.c
365
__raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
drivers/soc/ixp4xx/ixp4xx-npe.c
367
__raw_writel(exec_count, &npe->regs->exec_count);
drivers/soc/ixp4xx/ixp4xx-npe.c
376
__raw_writel(CMD_CLR_PROFILE_CNT, &npe->regs->exec_status_cmd);
drivers/soc/ixp4xx/ixp4xx-npe.c
378
__raw_writel(0, &npe->regs->exec_count);
drivers/soc/ixp4xx/ixp4xx-npe.c
379
__raw_writel(0, &npe->regs->action_points[0]);
drivers/soc/ixp4xx/ixp4xx-npe.c
380
__raw_writel(0, &npe->regs->action_points[1]);
drivers/soc/ixp4xx/ixp4xx-npe.c
381
__raw_writel(0, &npe->regs->action_points[2]);
drivers/soc/ixp4xx/ixp4xx-npe.c
382
__raw_writel(0, &npe->regs->action_points[3]);
drivers/soc/ixp4xx/ixp4xx-npe.c
383
__raw_writel(0, &npe->regs->watch_count);
drivers/soc/ixp4xx/ixp4xx-npe.c
407
__raw_writel(ctl, &npe->regs->messaging_control);
drivers/soc/ixp4xx/ixp4xx-npe.c
425
__raw_writel(send[0], &npe->regs->in_out_fifo);
drivers/soc/ixp4xx/ixp4xx-npe.c
432
__raw_writel(send[1], &npe->regs->in_out_fifo);
drivers/soc/ixp4xx/ixp4xx-qmgr.c
129
__raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit),
drivers/soc/ixp4xx/ixp4xx-qmgr.c
147
__raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[0]);
drivers/soc/ixp4xx/ixp4xx-qmgr.c
172
__raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[1]);
drivers/soc/ixp4xx/ixp4xx-qmgr.c
193
__raw_writel(req_bitmap, &qmgr_regs->irqstat[half]); /* ACK */
drivers/soc/ixp4xx/ixp4xx-qmgr.c
212
__raw_writel(__raw_readl(&qmgr_regs->irqen[half]) | mask,
drivers/soc/ixp4xx/ixp4xx-qmgr.c
224
__raw_writel(__raw_readl(&qmgr_regs->irqen[half]) & ~mask,
drivers/soc/ixp4xx/ixp4xx-qmgr.c
226
__raw_writel(mask, &qmgr_regs->irqstat[half]); /* clear */
drivers/soc/ixp4xx/ixp4xx-qmgr.c
313
__raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]);
drivers/soc/ixp4xx/ixp4xx-qmgr.c
363
__raw_writel(0, &qmgr_regs->sram[queue]);
drivers/soc/ixp4xx/ixp4xx-qmgr.c
37
__raw_writel(val, &qmgr_regs->acc[queue][0]);
drivers/soc/ixp4xx/ixp4xx-qmgr.c
401
__raw_writel(0x33333333, &qmgr_regs->stat1[i]);
drivers/soc/ixp4xx/ixp4xx-qmgr.c
402
__raw_writel(0, &qmgr_regs->irqsrc[i]);
drivers/soc/ixp4xx/ixp4xx-qmgr.c
405
__raw_writel(0, &qmgr_regs->stat2[i]);
drivers/soc/ixp4xx/ixp4xx-qmgr.c
406
__raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[i]); /* clear */
drivers/soc/ixp4xx/ixp4xx-qmgr.c
407
__raw_writel(0, &qmgr_regs->irqen[i]);
drivers/soc/ixp4xx/ixp4xx-qmgr.c
410
__raw_writel(0xFFFFFFFF, &qmgr_regs->statne_h);
drivers/soc/ixp4xx/ixp4xx-qmgr.c
411
__raw_writel(0, &qmgr_regs->statf_h);
drivers/soc/ixp4xx/ixp4xx-qmgr.c
414
__raw_writel(0, &qmgr_regs->sram[i]);
drivers/soc/pxa/mfp.c
133
__raw_writel(val, mfpr_mmio_base + (off))
drivers/soc/ti/smartreflex.c
41
__raw_writel(value, (sr->base + offset));
drivers/soc/ti/smartreflex.c
70
__raw_writel(reg_val, (sr->base + offset));
drivers/spi/spi-bcm63xx-hsspi.c
177
__raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
drivers/spi/spi-bcm63xx-hsspi.c
418
__raw_writel(reg | 0xff,
drivers/spi/spi-bcm63xx-hsspi.c
433
__raw_writel(HSSPI_PINGx_CMD_DONE(0), bs->regs + HSSPI_INT_MASK_REG);
drivers/spi/spi-bcm63xx-hsspi.c
439
__raw_writel(reg, bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));
drivers/spi/spi-bcm63xx-hsspi.c
462
__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
drivers/spi/spi-bcm63xx-hsspi.c
473
__raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg,
drivers/spi/spi-bcm63xx-hsspi.c
481
__raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
drivers/spi/spi-bcm63xx-hsspi.c
489
__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
drivers/spi/spi-bcm63xx-hsspi.c
528
__raw_writel(reg | 0xff,
drivers/spi/spi-bcm63xx-hsspi.c
545
__raw_writel(HSSPI_PINGx_CMD_DONE(0),
drivers/spi/spi-bcm63xx-hsspi.c
551
__raw_writel(reg, bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));
drivers/spi/spi-bcm63xx-hsspi.c
579
__raw_writel(reg, bs->regs +
drivers/spi/spi-bcm63xx-hsspi.c
591
__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
drivers/spi/spi-bcm63xx-hsspi.c
734
__raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
drivers/spi/spi-bcm63xx-hsspi.c
735
__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
drivers/spi/spi-bcm63xx-hsspi.c
848
__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
drivers/spi/spi-bcm63xx-hsspi.c
851
__raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
drivers/spi/spi-bcm63xx-hsspi.c
856
__raw_writel(reg | GLOBAL_CTRL_CLK_GATE_SSOFF,
drivers/spi/spi-bcm63xx-hsspi.c
904
__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
drivers/spi/spi-bcmbca-hsspi.c
154
__raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
drivers/spi/spi-bcmbca-hsspi.c
188
__raw_writel(reg, bs->spim_ctrl);
drivers/spi/spi-bcmbca-hsspi.c
200
__raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg,
drivers/spi/spi-bcmbca-hsspi.c
208
__raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
drivers/spi/spi-bcmbca-hsspi.c
216
__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
drivers/spi/spi-bcmbca-hsspi.c
284
__raw_writel(reg | 0xff,
drivers/spi/spi-bcmbca-hsspi.c
301
__raw_writel(HSSPI_PINGx_CMD_DONE(0),
drivers/spi/spi-bcmbca-hsspi.c
313
__raw_writel(reg, bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));
drivers/spi/spi-bcmbca-hsspi.c
341
__raw_writel(reg, bs->regs +
drivers/spi/spi-bcmbca-hsspi.c
351
__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
drivers/spi/spi-bcmbca-hsspi.c
362
__raw_writel(reg, bs->spim_ctrl);
drivers/spi/spi-bcmbca-hsspi.c
424
__raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
drivers/spi/spi-bcmbca-hsspi.c
425
__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
drivers/spi/spi-bcmbca-hsspi.c
523
__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
drivers/spi/spi-bcmbca-hsspi.c
526
__raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
drivers/spi/spi-bcmbca-hsspi.c
531
__raw_writel(reg | GLOBAL_CTRL_CLK_GATE_SSOFF,
drivers/spi/spi-bcmbca-hsspi.c
575
__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
drivers/spi/spi-dw.h
212
__raw_writel(val, dws->regs + offset);
drivers/spi/spi-hisi-sfc-v3xx.c
257
__raw_writel(val, to);
drivers/spi/spi-hisi-sfc-v3xx.c
268
__raw_writel(val, to);
drivers/spi/spi-lantiq-ssc.c
197
__raw_writel(val, spi->regbase + reg);
drivers/spi/spi-lantiq-ssc.c
207
__raw_writel(val, spi->regbase + reg);
drivers/spi/spi-rb4xx.c
42
__raw_writel(value, rbspi->base + reg);
drivers/spi/spi-s3c64xx.c
447
__raw_writel(*buf++, addr);
drivers/spi/spi-s3c64xx.c
459
__raw_writel(*buf++, addr);
drivers/spi/spi-xtensa-xtfpga.c
34
__raw_writel(val, spi->regs + addr);
drivers/spmi/spmi-pmic-arb.c
306
__raw_writel(data, pmic_arb->wr_base + reg);
drivers/ssb/host_soc.c
150
__raw_writel((__force u32)(*buf), addr);
drivers/thermal/broadcom/brcmstb_thermal.c
188
__raw_writel(val, priv->tmon_base + trip->enable_offs);
drivers/thermal/broadcom/brcmstb_thermal.c
222
__raw_writel(orig, priv->tmon_base + trip->reg_offs);
drivers/tty/mips_ejtag_fdc.c
1238
__raw_writel(word.word,
drivers/tty/mips_ejtag_fdc.c
174
__raw_writel(data, priv->reg + offs);
drivers/tty/mips_ejtag_fdc.c
350
__raw_writel(word.word, regs + REG_FDTX(c->index));
drivers/tty/serial/8250/8250_rt288x.c
51
__raw_writel(value, p->membase + (offset << p->regshift));
drivers/tty/serial/8250/8250_rt288x.c
62
__raw_writel(value, up->port.membase + RT288X_DL);
drivers/tty/serial/apbuart.h
54
#define UART_PUT_CHAR(port, v) (__raw_writel(v, APBBASE_DATA_P(port)))
drivers/tty/serial/apbuart.h
56
#define UART_PUT_STATUS(port, v)(__raw_writel(v, APBBASE_STATUS_P(port)))
drivers/tty/serial/apbuart.h
58
#define UART_PUT_CTRL(port, v) (__raw_writel(v, APBBASE_CTRL_P(port)))
drivers/tty/serial/apbuart.h
60
#define UART_PUT_SCAL(port, v) (__raw_writel(v, APBBASE_SCALAR_P(port)))
drivers/tty/serial/atmel_serial.c
215
__raw_writel(value, port->membase + reg);
drivers/tty/serial/bcm63xx_uart.c
82
__raw_writel(value, port->membase + offset);
drivers/tty/serial/lantiq.c
127
__raw_writel((tmp & ~clear) | set, reg);
drivers/tty/serial/lantiq.c
167
__raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE);
drivers/tty/serial/lantiq.c
240
__raw_writel(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR);
drivers/tty/serial/lantiq.c
254
__raw_writel(ASC_IRNCR_EIR, port->membase + LTQ_ASC_IRNCR);
drivers/tty/serial/lantiq.c
270
__raw_writel(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR);
drivers/tty/serial/lantiq.c
341
__raw_writel(0, port->membase + LTQ_ASC_PISEL);
drivers/tty/serial/lantiq.c
342
__raw_writel(
drivers/tty/serial/lantiq.c
346
__raw_writel(
drivers/tty/serial/lantiq.c
363
__raw_writel(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX,
drivers/tty/serial/lantiq.c
377
__raw_writel(0, port->membase + LTQ_ASC_CON);
drivers/tty/serial/lantiq.c
471
__raw_writel(divisor, port->membase + LTQ_ASC_BG);
drivers/tty/serial/lantiq.c
477
__raw_writel(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE);
drivers/tty/serial/mux.c
63
#define UART_PUT_CHAR(p, c) __raw_writel((c), (p)->membase + IO_DATA_REG_OFFSET)
drivers/tty/serial/pic32_uart.c
81
__raw_writel(val, sport->port.membase + reg);
drivers/tty/serial/sa1100.c
53
#define UART_PUT_UTCR0(sport,v) __raw_writel((v),(sport)->port.membase + UTCR0)
drivers/tty/serial/sa1100.c
54
#define UART_PUT_UTCR1(sport,v) __raw_writel((v),(sport)->port.membase + UTCR1)
drivers/tty/serial/sa1100.c
55
#define UART_PUT_UTCR2(sport,v) __raw_writel((v),(sport)->port.membase + UTCR2)
drivers/tty/serial/sa1100.c
56
#define UART_PUT_UTCR3(sport,v) __raw_writel((v),(sport)->port.membase + UTCR3)
drivers/tty/serial/sa1100.c
57
#define UART_PUT_UTSR0(sport,v) __raw_writel((v),(sport)->port.membase + UTSR0)
drivers/tty/serial/sa1100.c
58
#define UART_PUT_UTSR1(sport,v) __raw_writel((v),(sport)->port.membase + UTSR1)
drivers/tty/serial/sa1100.c
59
#define UART_PUT_CHAR(sport,v) __raw_writel((v),(sport)->port.membase + UTDR)
drivers/tty/serial/serial_txx9.c
174
__raw_writel(value, up->membase + offset);
drivers/usb/gadget/udc/at91_udc.c
1022
__raw_writel(csr, creg);
drivers/usb/gadget/udc/at91_udc.c
1034
__raw_writel(csr, creg);
drivers/usb/gadget/udc/at91_udc.c
1076
__raw_writel(csr, creg);
drivers/usb/gadget/udc/at91_udc.c
1103
__raw_writel(csr | AT91_UDP_TXPKTRDY, creg);
drivers/usb/gadget/udc/at91_udc.c
1214
__raw_writel(tmp, ep->creg);
drivers/usb/gadget/udc/at91_udc.c
1237
__raw_writel(tmp, ep->creg);
drivers/usb/gadget/udc/at91_udc.c
1260
__raw_writel(csr, creg);
drivers/usb/gadget/udc/at91_udc.c
1270
__raw_writel(csr, creg);
drivers/usb/gadget/udc/at91_udc.c
1286
__raw_writel(csr, creg);
drivers/usb/gadget/udc/at91_udc.c
1322
__raw_writel(csr, creg);
drivers/usb/gadget/udc/at91_udc.c
1359
__raw_writel(csr, creg);
drivers/usb/gadget/udc/at91_udc.c
1381
__raw_writel(csr | AT91_UDP_FORCESTALL, creg);
drivers/usb/gadget/udc/at91_udc.c
1388
__raw_writel(csr, creg);
drivers/usb/gadget/udc/at91_udc.c
353
__raw_writel(csr, creg);
drivers/usb/gadget/udc/at91_udc.c
410
__raw_writel(csr, creg);
drivers/usb/gadget/udc/at91_udc.c
444
__raw_writel(csr, creg);
drivers/usb/gadget/udc/at91_udc.c
535
__raw_writel(tmp, ep->creg);
drivers/usb/gadget/udc/at91_udc.c
571
__raw_writel(0, ep->creg);
drivers/usb/gadget/udc/at91_udc.c
678
__raw_writel(tmp, ep->creg);
drivers/usb/gadget/udc/at91_udc.c
772
__raw_writel(csr, creg);
drivers/usb/gadget/udc/at91_udc.c
93
__raw_writel((val), (udc)->udp_baseaddr + (reg))
drivers/usb/gadget/udc/fsl_udc_core.c
245
__raw_writel(ctrl, &usb_sys_regs->control);
drivers/usb/gadget/udc/fsl_udc_core.c
261
__raw_writel(ctrl, &usb_sys_regs->control);
drivers/usb/gadget/udc/fsl_udc_core.c
329
__raw_writel(ctrl, &usb_sys_regs->control);
drivers/usb/gadget/udc/fsl_udc_core.c
339
__raw_writel(tmp, &usb_sys_regs->snoop1);
drivers/usb/gadget/udc/fsl_udc_core.c
341
__raw_writel(tmp, &usb_sys_regs->snoop2);
drivers/usb/gadget/udc/pxa27x_udc.h
183
__raw_writel((value), ep->dev->regs + ofs_##reg(ep))
drivers/usb/gadget/udc/pxa27x_udc.h
191
__raw_writel((value), (udc)->regs + (reg))
drivers/usb/host/ehci-omap.c
61
__raw_writel(val, base + reg);
drivers/usb/host/ehci.h
754
#define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
drivers/usb/host/ohci-nxp.c
128
__raw_writel(tmp, usb_otg_stat_control);
drivers/usb/host/ohci-nxp.c
144
__raw_writel(tmp, usb_otg_stat_control);
drivers/usb/host/ohci-pxa27x.c
164
__raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);
drivers/usb/host/ohci-pxa27x.c
165
__raw_writel(uhcrhdb, pxa_ohci->mmio_base + UHCRHDB);
drivers/usb/host/ohci-pxa27x.c
253
__raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
drivers/usb/host/ohci-pxa27x.c
254
__raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);
drivers/usb/host/ohci-pxa27x.c
261
__raw_writel(uhchr | UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);
drivers/usb/host/ohci-pxa27x.c
263
__raw_writel(uhchr & ~UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);
drivers/usb/host/ohci-pxa27x.c
281
__raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
drivers/usb/host/ohci-pxa27x.c
297
__raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
drivers/usb/host/ohci-pxa27x.c
298
__raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, pxa_ohci->mmio_base + UHCHIE);
drivers/usb/host/ohci-pxa27x.c
319
__raw_writel(uhccoms, pxa_ohci->mmio_base + UHCCOMS);
drivers/usb/isp1760/isp1760-hcd.c
432
__raw_writel(*src, dst);
drivers/usb/isp1760/isp1760-hcd.c
448
__raw_writel(*src, dst);
drivers/usb/musb/musb_core.c
431
__raw_writel(data, addr + offset);
drivers/usb/phy/phy-fsl-usb.c
930
__raw_writel(temp, &p_otg->dr_mem_map->control);
drivers/video/fbdev/atmel_lcdfb.c
70
#define lcdc_writel(sinfo, reg, val) __raw_writel((val), (sinfo)->mmio+(reg))
drivers/video/fbdev/ep93xx-fb.c
131
__raw_writel(val, fbi->mmio_base + off);
drivers/video/fbdev/grvga.c
149
__raw_writel(((info->var.yres - 1) << 16) | (info->var.xres - 1),
drivers/video/fbdev/grvga.c
152
__raw_writel((info->var.lower_margin << 16) | (info->var.right_margin),
drivers/video/fbdev/grvga.c
155
__raw_writel((info->var.vsync_len << 16) | (info->var.hsync_len),
drivers/video/fbdev/grvga.c
158
__raw_writel(((info->var.yres + info->var.lower_margin + info->var.upper_margin + info->var.vsync_len - 1) << 16) |
drivers/video/fbdev/grvga.c
180
__raw_writel((par->clk_sel << 6) | (func << 4) | 1,
drivers/video/fbdev/grvga.c
213
__raw_writel((regno << 24) | (red << 16) | (green << 8) | blue,
drivers/video/fbdev/grvga.c
247
__raw_writel(base_addr,
drivers/video/fbdev/grvga.c
482
__raw_writel(physical_start, &par->regs->fb_pos);
drivers/video/fbdev/grvga.c
483
__raw_writel(__raw_readl(&par->regs->status) | 1, /* Enable framebuffer */
drivers/video/fbdev/mb862xx/mb862xxfb.h
106
#define gdc_write __raw_writel
drivers/video/fbdev/nvidia/nv_local.h
66
#define NV_WR32(p,i,d) (__raw_writel((d), (void __iomem *)(p) + (i)))
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
253
__raw_writel(val, dispc.base + idx);
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
445
__raw_writel(val, base + idx.idx);
drivers/video/fbdev/omap2/omapfb/dss/dss.c
116
__raw_writel(val, dss.base + idx.idx);
drivers/video/fbdev/omap2/omapfb/dss/hdmi.h
250
__raw_writel(val, base_addr + idx);
drivers/video/fbdev/omap2/omapfb/dss/venc.c
262
__raw_writel(val, venc.base + idx);
drivers/video/fbdev/omap2/omapfb/omapfb-main.c
85
__raw_writel(color, p);
drivers/video/fbdev/omap2/omapfb/vrfb.c
74
__raw_writel(val, vrfb_base + SMS_ROT_CONTROL(ctx));
drivers/video/fbdev/omap2/omapfb/vrfb.c
79
__raw_writel(val, vrfb_base + SMS_ROT_SIZE(ctx));
drivers/video/fbdev/omap2/omapfb/vrfb.c
84
__raw_writel(val, vrfb_base + SMS_ROT_PHYSICAL_BA(ctx));
drivers/video/fbdev/pxa3xx-gcu.c
112
__raw_writel(val, priv->mmio_base + off);
drivers/video/fbdev/pxafb.c
105
__raw_writel(val, fbi->mmio_base + off);
drivers/video/fbdev/riva/riva_hw.h
82
#define NV_WR32(p,i,d) (__raw_writel((d), (void __iomem *)(p) + (i)))
drivers/video/fbdev/s3c-fb.c
47
__raw_writel(v, r); \
drivers/video/fbdev/tgafb.c
1020
__raw_writel(data, fb_base + pos);
drivers/video/fbdev/tgafb.c
1033
__raw_writel(fdata, fb_base + pos + j*Bpp);
drivers/video/fbdev/tgafb.c
1035
__raw_writel(ldata, fb_base + pos + j*Bpp);
drivers/video/fbdev/tgafb.c
1042
__raw_writel((is8bpp
drivers/video/fbdev/tgafb.c
1071
__raw_writel(TGA_MODE_SBM_8BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
drivers/video/fbdev/tgafb.c
1072
__raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
drivers/video/fbdev/tgafb.c
1084
__raw_writel(spos, tga_regs+TGA_COPY64_SRC);
drivers/video/fbdev/tgafb.c
1086
__raw_writel(dpos, tga_regs+TGA_COPY64_DST);
drivers/video/fbdev/tgafb.c
1094
__raw_writel(spos, tga_regs+TGA_COPY64_SRC);
drivers/video/fbdev/tgafb.c
1096
__raw_writel(dpos, tga_regs+TGA_COPY64_DST);
drivers/video/fbdev/tgafb.c
1104
__raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
drivers/video/fbdev/tgafb.c
1119
__raw_writel(TGA_MODE_SBM_24BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
drivers/video/fbdev/tgafb.c
1120
__raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
drivers/video/fbdev/tgafb.c
1132
__raw_writel(0xffff, src);
drivers/video/fbdev/tgafb.c
1134
__raw_writel(0xffff, dst);
drivers/video/fbdev/tgafb.c
1142
__raw_writel(0xffff, src);
drivers/video/fbdev/tgafb.c
1144
__raw_writel(0xffff, dst);
drivers/video/fbdev/tgafb.c
1152
__raw_writel(TGA_MODE_SBM_24BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
drivers/video/fbdev/tgafb.c
1213
__raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
drivers/video/fbdev/tgafb.c
1214
__raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
drivers/video/fbdev/tgafb.c
1229
__raw_writel(sfb - tga_fb, tga_regs+TGA_COPY64_SRC);
drivers/video/fbdev/tgafb.c
1231
__raw_writel(dfb - tga_fb, tga_regs+TGA_COPY64_DST);
drivers/video/fbdev/tgafb.c
1240
__raw_writel(0xffffffff, sfb);
drivers/video/fbdev/tgafb.c
1242
__raw_writel(0xffffffff, dfb);
drivers/video/fbdev/tgafb.c
1251
__raw_writel(mask_last, sfb);
drivers/video/fbdev/tgafb.c
1253
__raw_writel(mask_last, dfb);
drivers/video/fbdev/tgafb.c
1262
__raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
drivers/video/fbdev/tgafb.c
683
__raw_writel(fgcolor, regs_base + TGA_FOREGROUND_REG);
drivers/video/fbdev/tgafb.c
684
__raw_writel(bgcolor, regs_base + TGA_BACKGROUND_REG);
drivers/video/fbdev/tgafb.c
702
__raw_writel((is8bpp
drivers/video/fbdev/tgafb.c
716
__raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
drivers/video/fbdev/tgafb.c
729
__raw_writel(mask << shift, fb_base + pos);
drivers/video/fbdev/tgafb.c
735
__raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
drivers/video/fbdev/tgafb.c
758
__raw_writel(mask, fb_base + pos + j*bincr);
drivers/video/fbdev/tgafb.c
767
__raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
drivers/video/fbdev/tgafb.c
778
__raw_writel(mask, fb_base + pos);
drivers/video/fbdev/tgafb.c
783
__raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
drivers/video/fbdev/tgafb.c
797
__raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
drivers/video/fbdev/tgafb.c
807
__raw_writel(mask, fb_base + pos + j*bincr);
drivers/video/fbdev/tgafb.c
816
__raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
drivers/video/fbdev/tgafb.c
828
__raw_writel(mask, fb_base + pos);
drivers/video/fbdev/tgafb.c
834
__raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
drivers/video/fbdev/tgafb.c
838
__raw_writel((is8bpp
drivers/video/fbdev/tgafb.c
879
__raw_writel(color, fb_base + pos + j*4);
drivers/video/fbdev/tgafb.c
974
__raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
drivers/video/fbdev/tgafb.c
975
__raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
drivers/video/fbdev/tgafb.c
979
__raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
drivers/video/fbdev/tgafb.c
980
__raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
drivers/video/fbdev/tgafb.c
981
__raw_writel(color, regs_base + TGA_BLOCK_COLOR2_REG);
drivers/video/fbdev/tgafb.c
982
__raw_writel(color, regs_base + TGA_BLOCK_COLOR3_REG);
drivers/video/fbdev/tgafb.c
983
__raw_writel(color, regs_base + TGA_BLOCK_COLOR4_REG);
drivers/video/fbdev/tgafb.c
984
__raw_writel(color, regs_base + TGA_BLOCK_COLOR5_REG);
drivers/video/fbdev/tgafb.c
985
__raw_writel(color, regs_base + TGA_BLOCK_COLOR6_REG);
drivers/video/fbdev/tgafb.c
986
__raw_writel(color, regs_base + TGA_BLOCK_COLOR7_REG);
drivers/video/fbdev/tgafb.c
991
__raw_writel(0xffffffff, regs_base + TGA_DATA_REG);
drivers/video/fbdev/tgafb.c
994
__raw_writel((is8bpp
drivers/w1/masters/omap_hdq.c
69
__raw_writel(val, hdq_data->hdq_base + offset);
drivers/w1/masters/omap_hdq.c
77
__raw_writel(new_val, hdq_data->hdq_base + offset);
drivers/watchdog/bcm7038_wdt.c
44
__raw_writel(value, addr);
drivers/watchdog/ixp4xx_wdt.c
55
__raw_writel(IXP4XX_WDT_KEY, iwdt->base + IXP4XX_OSWK_OFFSET);
drivers/watchdog/ixp4xx_wdt.c
56
__raw_writel(0, iwdt->base + IXP4XX_OSWE_OFFSET);
drivers/watchdog/ixp4xx_wdt.c
57
__raw_writel(wdd->timeout * iwdt->rate,
drivers/watchdog/ixp4xx_wdt.c
59
__raw_writel(IXP4XX_WDT_COUNT_ENABLE | IXP4XX_WDT_RESET_ENABLE,
drivers/watchdog/ixp4xx_wdt.c
61
__raw_writel(0, iwdt->base + IXP4XX_OSWK_OFFSET);
drivers/watchdog/ixp4xx_wdt.c
70
__raw_writel(IXP4XX_WDT_KEY, iwdt->base + IXP4XX_OSWK_OFFSET);
drivers/watchdog/ixp4xx_wdt.c
71
__raw_writel(0, iwdt->base + IXP4XX_OSWE_OFFSET);
drivers/watchdog/ixp4xx_wdt.c
72
__raw_writel(0, iwdt->base + IXP4XX_OSWK_OFFSET);
drivers/watchdog/ixp4xx_wdt.c
92
__raw_writel(IXP4XX_WDT_KEY, iwdt->base + IXP4XX_OSWK_OFFSET);
drivers/watchdog/ixp4xx_wdt.c
93
__raw_writel(0, iwdt->base + IXP4XX_OSWT_OFFSET);
drivers/watchdog/ixp4xx_wdt.c
94
__raw_writel(IXP4XX_WDT_COUNT_ENABLE | IXP4XX_WDT_RESET_ENABLE,
drivers/watchdog/lantiq_wdt.c
75
__raw_writel(val, priv->membase + offset);
drivers/watchdog/m54xx_wdt.c
54
__raw_writel(gms0, MCF_GPT_GMS0);
drivers/watchdog/m54xx_wdt.c
55
__raw_writel(MCF_GPT_GCIR_PRE(heartbeat*(MCF_BUSCLK/0xffff)) |
drivers/watchdog/m54xx_wdt.c
58
__raw_writel(gms0, MCF_GPT_GMS0);
drivers/watchdog/m54xx_wdt.c
68
__raw_writel(gms0, MCF_GPT_GMS0);
drivers/watchdog/m54xx_wdt.c
77
__raw_writel(gms0, MCF_GPT_GMS0);
drivers/watchdog/txx9wdt.c
46
__raw_writel(TXx9_TMWTMR_TWIE | TXx9_TMWTMR_TWC, &txx9wdt_reg->wtmr);
drivers/watchdog/txx9wdt.c
54
__raw_writel(WD_TIMER_CLK * wdt_dev->timeout, &txx9wdt_reg->cpra);
drivers/watchdog/txx9wdt.c
55
__raw_writel(WD_TIMER_CCD, &txx9wdt_reg->ccdr);
drivers/watchdog/txx9wdt.c
56
__raw_writel(0, &txx9wdt_reg->tisr); /* clear pending interrupt */
drivers/watchdog/txx9wdt.c
57
__raw_writel(TXx9_TMTCR_TCE | TXx9_TMTCR_CCDE | TXx9_TMTCR_TMODE_WDOG,
drivers/watchdog/txx9wdt.c
59
__raw_writel(TXx9_TMWTMR_TWIE | TXx9_TMWTMR_TWC, &txx9wdt_reg->wtmr);
drivers/watchdog/txx9wdt.c
67
__raw_writel(TXx9_TMWTMR_WDIS, &txx9wdt_reg->wtmr);
drivers/watchdog/txx9wdt.c
68
__raw_writel(__raw_readl(&txx9wdt_reg->tcr) & ~TXx9_TMTCR_TCE,
include/asm-generic/io.h
165
#ifndef __raw_writel
include/asm-generic/io.h
166
#define __raw_writel __raw_writel
include/asm-generic/io.h
293
__raw_writel((u32 __force)__cpu_to_le32(value), addr);
include/asm-generic/io.h
411
__raw_writel((u32 __force)__cpu_to_le32(value), addr);
include/asm-generic/io.h
538
__raw_writel(*buf++, addr);
include/asm-generic/io.h
665
__raw_writel((u32 __force)cpu_to_le32(value), PCI_IOBASE + addr);
include/asm-generic/logic_io.h
59
#define __raw_writel __raw_writel
include/asm-generic/logic_io.h
60
void __raw_writel(u32 value, volatile void __iomem *addr);
include/asm-generic/video.h
97
__raw_writel(b, addr);
include/linux/atmel-ssc.h
333
#define ssc_writel(base, reg, value) __raw_writel((value), base + SSC_##reg)
include/linux/mlx4/doorbell.h
79
__raw_writel((__force u32) val[0], dest);
include/linux/mlx4/doorbell.h
80
__raw_writel((__force u32) val[1], dest + 4);
include/linux/mlx5/doorbell.h
55
__raw_writel((__force u32) val[0], dest);
include/linux/mlx5/doorbell.h
56
__raw_writel((__force u32) val[1], dest + 4);
include/linux/mtd/doc2000.h
87
__raw_writel(data, addr + reg);
include/linux/mtd/map.h
420
__raw_writel(datum.x[0], map->virt + ofs);
include/linux/platform_data/sh_mmcif.h
86
__raw_writel(val, addr + reg);
include/linux/pxa2xx_ssp.h
261
__raw_writel(val, dev->mmio_base + reg);
lib/iomap.c
354
__raw_writel(*src, addr);
lib/iomap_copy.c
27
__raw_writel(*src++, dst++);
lib/iomem_copy.c
118
__raw_writel(val, dst);
lib/iomem_copy.c
37
__raw_writel(qc, addr);
sound/atmel/ac97c.c
60
__raw_writel((val), (chip)->regs + AC97C_##reg)
sound/mips/hal2.c
99
__raw_writel(val, reg);
sound/parisc/harmony.c
103
__raw_writel(v, h->iobase + r);
sound/pci/mixart/mixart_hwdep.h
20
#define writel_be(data,addr) __raw_writel((__force u32)cpu_to_be32(data),addr)
sound/pci/mixart/mixart_hwdep.h
28
#define writel_le(data,addr) __raw_writel((__force u32)cpu_to_le32(data),addr)
sound/sh/aica.c
170
__raw_writel(0xea000002, SPU_MEMORY_BASE);
sound/soc/atmel/atmel-pcm.h
71
#define ssc_writex(base, reg, value) __raw_writel((value), (base) + (reg))
sound/soc/au1x/ac97c.c
79
__raw_writel(v, ctx->mmio + reg);
sound/soc/au1x/i2sc.c
77
__raw_writel(v, ctx->mmio + reg);
sound/soc/au1x/psc-ac97.c
118
__raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
sound/soc/au1x/psc-ac97.c
125
__raw_writel(PSC_AC97CDC_INDX(reg) | (val & 0xffff),
sound/soc/au1x/psc-ac97.c
136
__raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
sound/soc/au1x/psc-ac97.c
148
__raw_writel(PSC_AC97RST_SNC, AC97_RST(pscdata));
sound/soc/au1x/psc-ac97.c
151
__raw_writel(0, AC97_RST(pscdata));
sound/soc/au1x/psc-ac97.c
161
__raw_writel(0, AC97_CFG(au1xpsc_ac97_workdata));
sound/soc/au1x/psc-ac97.c
163
__raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(pscdata));
sound/soc/au1x/psc-ac97.c
167
__raw_writel(PSC_AC97RST_RST, AC97_RST(pscdata));
sound/soc/au1x/psc-ac97.c
170
__raw_writel(0, AC97_RST(pscdata));
sound/soc/au1x/psc-ac97.c
174
__raw_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata));
sound/soc/au1x/psc-ac97.c
188
__raw_writel(pscdata->cfg | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
sound/soc/au1x/psc-ac97.c
251
__raw_writel(r & ~PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
sound/soc/au1x/psc-ac97.c
263
__raw_writel(r, AC97_CFG(pscdata));
sound/soc/au1x/psc-ac97.c
267
__raw_writel(r | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
sound/soc/au1x/psc-ac97.c
299
__raw_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
sound/soc/au1x/psc-ac97.c
301
__raw_writel(AC97PCR_START(stype), AC97_PCR(pscdata));
sound/soc/au1x/psc-ac97.c
306
__raw_writel(AC97PCR_STOP(stype), AC97_PCR(pscdata));
sound/soc/au1x/psc-ac97.c
312
__raw_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
sound/soc/au1x/psc-ac97.c
397
__raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
sound/soc/au1x/psc-ac97.c
399
__raw_writel(0, PSC_SEL(wd));
sound/soc/au1x/psc-ac97.c
401
__raw_writel(PSC_SEL_PS_AC97MODE | sel, PSC_SEL(wd));
sound/soc/au1x/psc-ac97.c
431
__raw_writel(0, AC97_CFG(wd));
sound/soc/au1x/psc-ac97.c
433
__raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
sound/soc/au1x/psc-ac97.c
446
__raw_writel(0, AC97_CFG(wd));
sound/soc/au1x/psc-ac97.c
448
__raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
sound/soc/au1x/psc-ac97.c
459
__raw_writel(wd->pm[0] | PSC_SEL_PS_AC97MODE, PSC_SEL(wd));
sound/soc/au1x/psc-ac97.c
78
__raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
sound/soc/au1x/psc-ac97.c
85
__raw_writel(PSC_AC97CDC_RD | PSC_AC97CDC_INDX(reg),
sound/soc/au1x/psc-ac97.c
98
__raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
sound/soc/au1x/psc-i2s.c
149
__raw_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata));
sound/soc/au1x/psc-i2s.c
159
__raw_writel(0, I2S_CFG(pscdata));
sound/soc/au1x/psc-i2s.c
161
__raw_writel(pscdata->cfg | PSC_I2SCFG_DE_ENABLE, I2S_CFG(pscdata));
sound/soc/au1x/psc-i2s.c
173
__raw_writel(0, I2S_CFG(pscdata));
sound/soc/au1x/psc-i2s.c
174
__raw_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata));
sound/soc/au1x/psc-i2s.c
194
__raw_writel(I2SPCR_CLRFIFO(stype), I2S_PCR(pscdata));
sound/soc/au1x/psc-i2s.c
196
__raw_writel(I2SPCR_START(stype), I2S_PCR(pscdata));
sound/soc/au1x/psc-i2s.c
205
__raw_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata));
sound/soc/au1x/psc-i2s.c
217
__raw_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata));
sound/soc/au1x/psc-i2s.c
228
__raw_writel(0, I2S_CFG(pscdata));
sound/soc/au1x/psc-i2s.c
230
__raw_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata));
sound/soc/au1x/psc-i2s.c
322
__raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
sound/soc/au1x/psc-i2s.c
324
__raw_writel(PSC_SEL_PS_I2SMODE | sel, PSC_SEL(wd));
sound/soc/au1x/psc-i2s.c
325
__raw_writel(0, I2S_CFG(wd));
sound/soc/au1x/psc-i2s.c
351
__raw_writel(0, I2S_CFG(wd));
sound/soc/au1x/psc-i2s.c
353
__raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
sound/soc/au1x/psc-i2s.c
364
__raw_writel(0, I2S_CFG(wd));
sound/soc/au1x/psc-i2s.c
366
__raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
sound/soc/au1x/psc-i2s.c
377
__raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
sound/soc/au1x/psc-i2s.c
379
__raw_writel(0, PSC_SEL(wd));
sound/soc/au1x/psc-i2s.c
381
__raw_writel(wd->pm[0], PSC_SEL(wd));
sound/soc/cirrus/ep93xx-i2s.c
85
__raw_writel(val, info->regs + reg);
sound/soc/mxs/mxs-saif.c
138
__raw_writel(BM_SAIF_CTRL_RUN,
sound/soc/mxs/mxs-saif.c
230
__raw_writel(scr, master_saif->base + SAIF_CTRL);
sound/soc/mxs/mxs-saif.c
272
__raw_writel(scr, master_saif->base + SAIF_CTRL);
sound/soc/mxs/mxs-saif.c
297
__raw_writel(BM_SAIF_CTRL_CLKGATE,
sound/soc/mxs/mxs-saif.c
299
__raw_writel(BM_SAIF_CTRL_RUN,
sound/soc/mxs/mxs-saif.c
335
__raw_writel(BM_SAIF_CTRL_RUN,
sound/soc/mxs/mxs-saif.c
362
__raw_writel(BM_SAIF_CTRL_SFTRST,
sound/soc/mxs/mxs-saif.c
364
__raw_writel(BM_SAIF_CTRL_CLKGATE,
sound/soc/mxs/mxs-saif.c
424
__raw_writel(scr | scr0, saif->base + SAIF_CTRL);
sound/soc/mxs/mxs-saif.c
444
__raw_writel(BM_SAIF_CTRL_SFTRST,
sound/soc/mxs/mxs-saif.c
448
__raw_writel(BM_SAIF_CTRL_CLKGATE,
sound/soc/mxs/mxs-saif.c
557
__raw_writel(scr, saif->base + SAIF_CTRL);
sound/soc/mxs/mxs-saif.c
567
__raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN,
sound/soc/mxs/mxs-saif.c
57
__raw_writel(BM_SAIF_CTRL_CLKGATE,
sound/soc/mxs/mxs-saif.c
59
__raw_writel(BM_SAIF_CTRL_RUN,
sound/soc/mxs/mxs-saif.c
612
__raw_writel(BM_SAIF_CTRL_RUN,
sound/soc/mxs/mxs-saif.c
617
__raw_writel(BM_SAIF_CTRL_RUN,
sound/soc/mxs/mxs-saif.c
628
__raw_writel(0, saif->base + SAIF_DATA);
sound/soc/mxs/mxs-saif.c
629
__raw_writel(0, saif->base + SAIF_DATA);
sound/soc/mxs/mxs-saif.c
665
__raw_writel(BM_SAIF_CTRL_RUN,
sound/soc/mxs/mxs-saif.c
672
__raw_writel(BM_SAIF_CTRL_RUN,
sound/soc/mxs/mxs-saif.c
738
__raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ,
sound/soc/mxs/mxs-saif.c
744
__raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ,
sound/soc/mxs/mxs-saif.c
76
__raw_writel(BM_SAIF_CTRL_SFTRST,
sound/soc/mxs/mxs-saif.c
80
__raw_writel(BM_SAIF_CTRL_CLKGATE,
sound/soc/pxa/mmp-sspa.c
270
__raw_writel(sspa_ctrl, sspa->tx_base + SSPA_CTL);
sound/soc/pxa/mmp-sspa.c
271
__raw_writel(0x1, sspa->tx_base + SSPA_FIFO_UL);
sound/soc/pxa/mmp-sspa.c
273
__raw_writel(sspa_ctrl, sspa->rx_base + SSPA_CTL);
sound/soc/pxa/mmp-sspa.c
274
__raw_writel(0x0, sspa->rx_base + SSPA_FIFO_UL);
sound/soc/pxa/mmp-sspa.c
429
__raw_writel(sspa->sp, sspa->tx_base + SSPA_SP);
sound/soc/pxa/mmp-sspa.c
430
__raw_writel(sspa->sp, sspa->rx_base + SSPA_SP);
sound/soc/pxa/mmp-sspa.c
433
__raw_writel(sspa->sp, sspa->tx_base + SSPA_SP);
sound/soc/pxa/mmp-sspa.c
434
__raw_writel(sspa->sp, sspa->rx_base + SSPA_SP);
sound/soc/pxa/mmp-sspa.c
443
__raw_writel(sspa->sp & ~SSPA_SP_MSL, sspa->tx_base + SSPA_SP);
sound/soc/pxa/mmp-sspa.c
445
__raw_writel(sspa->ctrl, sspa->tx_base + SSPA_CTL);
sound/soc/pxa/mmp-sspa.c
446
__raw_writel(sspa->ctrl, sspa->rx_base + SSPA_CTL);
sound/soc/pxa/mmp-sspa.c
52
__raw_writel(sspa_sp, sspa->tx_base + SSPA_SP);
sound/soc/pxa/mmp-sspa.c
62
__raw_writel(sspa_sp, sspa->tx_base + SSPA_SP);
sound/soc/pxa/mmp-sspa.c
71
__raw_writel(sspa_sp, sspa->rx_base + SSPA_SP);
sound/soc/pxa/mmp-sspa.c
80
__raw_writel(sspa_sp, sspa->rx_base + SSPA_SP);
sound/soc/pxa/pxa-ssp.c
144
__raw_writel(sssr, ssp->mmio_base + SSSR);
sound/soc/pxa/pxa-ssp.c
145
__raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
sound/soc/pxa/pxa-ssp.c
146
__raw_writel(priv->cr1, ssp->mmio_base + SSCR1);
sound/soc/pxa/pxa-ssp.c
147
__raw_writel(priv->to, ssp->mmio_base + SSTO);
sound/soc/pxa/pxa-ssp.c
148
__raw_writel(priv->psp, ssp->mmio_base + SSPSP);
sound/soc/renesas/fsi.c
315
__raw_writel(data, reg);
sound/soc/renesas/siu.h
136
__raw_writel(val, addr);
sound/soc/ti/davinci-i2s.c
172
__raw_writel(val, dev->base + reg);
sound/soc/ti/davinci-mcasp.c
143
__raw_writel(__raw_readl(reg) | val, reg);
sound/soc/ti/davinci-mcasp.c
150
__raw_writel((__raw_readl(reg) & ~(val)), reg);
sound/soc/ti/davinci-mcasp.c
157
__raw_writel((__raw_readl(reg) & ~mask) | val, reg);
sound/soc/ti/davinci-mcasp.c
163
__raw_writel(val, mcasp->base + offset);
tools/include/asm-generic/io.h
128
#ifndef __raw_writel
tools/include/asm-generic/io.h
129
#define __raw_writel __raw_writel
tools/include/asm-generic/io.h
239
__raw_writel((u32 __force)__cpu_to_le32(value), addr);
tools/include/asm-generic/io.h
339
__raw_writel((u32 __force)__cpu_to_le32(value), addr);
tools/include/asm-generic/io.h
461
__raw_writel(*buf++, addr);
tools/testing/selftests/kvm/include/arm64/processor.h
241
#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
