Symbol: tegra_dc_writel
drivers/gpu/drm/tegra/dc.c
1026
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
drivers/gpu/drm/tegra/dc.c
1085
tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
drivers/gpu/drm/tegra/dc.c
1089
tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
drivers/gpu/drm/tegra/dc.c
124
tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
drivers/gpu/drm/tegra/dc.c
125
tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
drivers/gpu/drm/tegra/dc.c
1687
tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
drivers/gpu/drm/tegra/dc.c
1696
tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
drivers/gpu/drm/tegra/dc.c
1790
tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
drivers/gpu/drm/tegra/dc.c
1802
tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
drivers/gpu/drm/tegra/dc.c
1827
tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
drivers/gpu/drm/tegra/dc.c
1830
tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
drivers/gpu/drm/tegra/dc.c
1835
tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
drivers/gpu/drm/tegra/dc.c
1839
tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
drivers/gpu/drm/tegra/dc.c
1843
tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
drivers/gpu/drm/tegra/dc.c
1846
tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
drivers/gpu/drm/tegra/dc.c
1970
tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
drivers/gpu/drm/tegra/dc.c
2133
tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
drivers/gpu/drm/tegra/dc.c
2188
tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
drivers/gpu/drm/tegra/dc.c
2191
tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
drivers/gpu/drm/tegra/dc.c
2197
tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
drivers/gpu/drm/tegra/dc.c
2204
tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
drivers/gpu/drm/tegra/dc.c
2208
tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
drivers/gpu/drm/tegra/dc.c
2211
tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
drivers/gpu/drm/tegra/dc.c
2213
tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
drivers/gpu/drm/tegra/dc.c
2217
tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
drivers/gpu/drm/tegra/dc.c
2221
tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
drivers/gpu/drm/tegra/dc.c
2226
tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
drivers/gpu/drm/tegra/dc.c
2230
tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
drivers/gpu/drm/tegra/dc.c
2234
tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
drivers/gpu/drm/tegra/dc.c
2238
tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
drivers/gpu/drm/tegra/dc.c
2242
tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);
drivers/gpu/drm/tegra/dc.c
2244
tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
drivers/gpu/drm/tegra/dc.c
2249
tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
drivers/gpu/drm/tegra/dc.c
2259
tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
drivers/gpu/drm/tegra/dc.c
2265
tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
drivers/gpu/drm/tegra/dc.c
2271
tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
drivers/gpu/drm/tegra/dc.c
2277
tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
drivers/gpu/drm/tegra/dc.c
2283
tegra_dc_writel(dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);
drivers/gpu/drm/tegra/dc.c
2322
tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
drivers/gpu/drm/tegra/dc.c
2326
tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
drivers/gpu/drm/tegra/dc.c
2541
tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
drivers/gpu/drm/tegra/dc.c
55
tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
drivers/gpu/drm/tegra/dc.c
57
tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
drivers/gpu/drm/tegra/dc.c
94
tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
drivers/gpu/drm/tegra/dc.c
951
tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
drivers/gpu/drm/tegra/dc.c
955
tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
drivers/gpu/drm/tegra/dc.c
961
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
drivers/gpu/drm/tegra/dc.c
975
tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
drivers/gpu/drm/tegra/dc.c
987
tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR);
drivers/gpu/drm/tegra/dc.c
991
tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR);
drivers/gpu/drm/tegra/dc.c
999
tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
drivers/gpu/drm/tegra/dsi.c
864
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
drivers/gpu/drm/tegra/dsi.c
942
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
drivers/gpu/drm/tegra/hdmi.c
1182
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
drivers/gpu/drm/tegra/hdmi.c
1260
tegra_dc_writel(dc, VSYNC_H_POSITION(1),
drivers/gpu/drm/tegra/hdmi.c
1262
tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,
drivers/gpu/drm/tegra/hdmi.c
1268
tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
drivers/gpu/drm/tegra/hdmi.c
1272
tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
drivers/gpu/drm/tegra/hdmi.c
1275
tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
drivers/gpu/drm/tegra/hdmi.c
1419
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
drivers/gpu/drm/tegra/hub.c
111
tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
drivers/gpu/drm/tegra/hub.c
202
tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL);
drivers/gpu/drm/tegra/hub.c
222
tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL);
drivers/gpu/drm/tegra/hub.c
294
tegra_dc_writel(dc, value, offset);
drivers/gpu/drm/tegra/hub.c
898
tegra_dc_writel(dc, value, DC_CMD_IHUB_COMMON_MISC_CTL);
drivers/gpu/drm/tegra/hub.c
902
tegra_dc_writel(dc, value, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER);
drivers/gpu/drm/tegra/hub.c
904
tegra_dc_writel(dc, COMMON_UPDATE, DC_CMD_STATE_CONTROL);
drivers/gpu/drm/tegra/hub.c
906
tegra_dc_writel(dc, COMMON_ACTREQ, DC_CMD_STATE_CONTROL);
drivers/gpu/drm/tegra/rgb.c
110
tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
drivers/gpu/drm/tegra/rgb.c
125
tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
drivers/gpu/drm/tegra/rgb.c
130
tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
drivers/gpu/drm/tegra/rgb.c
88
tegra_dc_writel(dc, table[i].value, table[i].offset);
drivers/gpu/drm/tegra/sor.c
2232
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
drivers/gpu/drm/tegra/sor.c
2457
tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
drivers/gpu/drm/tegra/sor.c
2460
tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
drivers/gpu/drm/tegra/sor.c
2464
tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
drivers/gpu/drm/tegra/sor.c
2554
tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
drivers/gpu/drm/tegra/sor.c
2584
tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
drivers/gpu/drm/tegra/sor.c
2629
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
drivers/gpu/drm/tegra/sor.c
2635
tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
drivers/gpu/drm/tegra/sor.c
2685
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
drivers/gpu/drm/tegra/sor.c
2926
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);